--- gcc-6-6.3.0.orig/debian/FAQ.gcj
+++ gcc-6-6.3.0/debian/FAQ.gcj
@@ -0,0 +1,494 @@
+The GCJ FAQ
+===========
+
+      The latest version of this document is always available at
+      http://gcc.gnu.org/java/faq.html.
+
+        General Questions
+
+            What license is used for libgcj?
+            How can I report a bug in libgcj?
+            How can I contribute to libgcj
+            Is libgcj part of GCC?
+            Will gcj and libgcj work on my machine?
+            How can I debug my Java program?
+            Can I interface byte-compiled and native java code?
+
+
+        Java Feature Support
+
+            What Java API's are supported? How complete is
+              the support?
+            Does GCJ support using straight C native methods
+              ala JNI?
+            Why does GCJ use CNI?
+            What is the state of AWT support?
+            How about support for Swing ?
+            What support is there for RMI ?
+            Can I use any code from other OpenSource projects
+              to supplement libgcj's current features ?
+            What features of the Java language are/arn't supported
+
+
+        Build Issues
+
+            I need something more recent than the last release; how
+                  should I build it?
+            Linker bug on Solaris
+            Can I configure/build in the source tree?
+            My libgcj build fails with "invalid use of undefined type
+                  struct sigcontext_struct"
+
+
+        Gcj Compile/Link Questions
+
+            Why do I get undefined reference to `main' errors?
+            Can GCJ only handle source code?
+            "gcj -C" Doesn't seem to work like javac/jikes. Whats going on?
+            Where does GCJ look for files?
+            How does gcj resolve wether to compile .class or .java files?
+            I'm getting link errors!
+            I'm getting 'undefined symbol: __dso_handle'
+
+
+        Runtime Questions
+
+            My program is dumping core! What's going on?
+            When I run the debugger I get a SEGV in the GC! What's going on?
+            I have just compiled and benchmarked my Java application
+            and it seems to be running slower than than XXX JIT JVM. Is there
+            anything I can do to make it go faster?
+            Can I profile Garbage Collection?
+            How do I increase the runtime's initial and maximum heap sizes?
+            How can I profile my application?
+            My program seems to hang and doesn't produce any output
+
+
+        Programming Issues
+
+            Are there any examples of how to use CNI?
+            Is it possible to invoke GCJ compiled Java code from a
+            C++ application?
+
+General Questions
+=================
+
+      1.1 What license is used for libgcj?
+
+          libgcj is distributed under the GPL, with the 'libgcc exception'.
+          This means that linking with libgcj does not by itself cause
+          your program to fall under the GPL.  See LIBGCJ_LICENSE in
+          the source tree for more details.
+
+      1.2 How can I report a bug in libgcj?
+
+          libgcj has a corresponding Gnats bug database which you can
+          browse. You can also submit new bug reports from the Gnats
+          page.
+
+      1.3 How can I contribute to libgcj?
+
+          You can send simple bug fixes in as patches. Please follow
+          the GCC guidelines for submitting patches. For more complex
+          changes, you must sign copyright over to the Free Software
+          Foundation. See the contribution page for details.
+
+      1.4 Is libgcj part of GCC?
+
+          Yes, libgcj is now part of GCC. It can be downloaded,
+          configured and built as one single tree.
+
+      1.5 Will gcj and libgcj work on my machine?
+
+          Gcj and libgcj are known to work more or less with IA-32 and
+          Sparc Solaris, Tru64 Unix, as well as IA-32, IA-64, Alpha,
+          and PowerPC Linux. They might work on other
+          systems. Generally speaking, porting to a new system should
+          not be hard. This would be a good way to volunteer.
+
+      1.6 How can I debug my Java program?
+
+          gdb 5.0 includes support for debugging gcj-compiled Java
+          programs. For more information please read Java Debugging
+          with gdb.
+
+      1.7 Can I interface byte-compiled and native java code
+
+          libgcj has a bytecode interpreter that allows you to mix
+          .class files with compiled code. It works pretty
+          transparently: if a compiled version of a class is not found
+          in the application binary or linked shared libraries, the
+          class loader will search for a bytecode version in your
+          classpath, much like a VM would. Be sure to build libgcj
+          with the --enable-interpreter option to enable this
+          functionality.
+
+          The program "gij" provides a front end to the interpreter
+          that behaves much like a traditional virtual machine. You
+          can even use "gij" to run a shared library which is compiled
+          from java code and contains a main method:
+
+          $ gcj -shared -o lib-HelloWorld.so HelloWorld.java
+          $ gij HelloWorld
+
+          This works because gij uses Class.forName, which knows how
+          to load shared objects.
+
+Java Feature Support
+====================
+
+      2.1 What Java API's are supported? How complete is
+        the support?
+
+          Matt Welsh writes:
+
+            Just look in the 'libjava' directory of libgcj and see
+            what classes are there. Most GUI stuff isn't there yet,
+            that's true, but many of the other classes are easy to add
+            if they don't yet exist.
+
+            I think it's important to stress that there is a big
+            difference between Java and the many libraries which Java
+            supports. Unfortunately, Sun's promise of "write once, run
+            everywhere" assumes much more than a JVM: you also need
+            the full set of JDK libraries. Considering that new Java
+            APIs come out every week, it's going to be impossible to
+            track everything.
+
+            To make things worse, you can't simply run Sun's JDK
+            classes on any old JVM -- they assume that a bunch of
+            native methods are also defined. Since this native method
+            requirement isn't defined by the JDK specs, you're
+            effectively constrained to using Sun's JVMs if you want to
+            use Sun's JDK libraries. Oh yes -- you could also
+            reimplement all of those native methods yourself, and make
+            sure they behave exactly as Sun's do. Note that they're
+            undocumented!
+
+      2.2 Does GCJ support using straight C native methods
+         ala JNI?
+
+          Yes. libgcj now has experimental support for JNI, in
+          addition to its native Compiled Native Interface (CNI). gcjh
+          will generate JNI stubs and headers using the "-jni"
+          option. However, we do prefer CNI: it is more efficient,
+          easier to write, and (at least potentially) easier to debug.
+
+      2.3 Why does GCJ use CNI?
+
+          Per Bothner explains:
+
+            We use CNI because we think it is a better solution,
+            especially for a Java implementation that is based on the
+            idea that Java is just another programming language that
+            can be implemented using standard compilation
+            techniques. Given that, and the idea that languages
+            implemented using Gcc should be compatible where it makes
+            sense, it follows that the Java calling convention should
+            be as similar as practical to that used for other
+            languages, especially C++, since we can think of Java as a
+            subset of C++. CNI is just a set of helper functions and
+            conventions built on the idea that C++ and Java have the
+            *same* calling convention and object layout; they are
+            binary compatible. (This is a simplification, but close
+            enough.)
+
+      2.4 What is the state of AWT support?
+
+          Work is in progress to implement AWT and Java2D. We intend
+          to support both GTK and xlib peers written using CNI. Some
+          components are already working atop the xlib peers.
+
+      2.5 How about support for Swing?
+
+          Once AWT support is working then Swing support can be
+          considered. There is at least one free-software partial
+          implementations of Swing that may be usable.
+
+      2.6 What support is there for RMI?
+
+         RMI code exists on the CVS trunk (aka gcc 3.1), but it has
+         not been heavily tested.  This code was donated by
+         Transvirtual Technologies.
+
+      2.7 Can I use any code from other OpenSource
+          projects to supplement libgcj's current features?
+
+           Certainly. However, in many cases, if you wanted to
+           contribute the code back into the official libgcj
+           distribution, we would require that the original author(s)
+           assign copyright to the Free Software Foundation.  As of
+           March 6, 2000, libgcj has been relicenced, and copyright
+           has been assigned to the FSF. This allows us to share and
+           merge much of the libgcj codebase with the Classpath
+           project.  Our eventual goal is for Classpath to be an
+           upstream source provider for libgcj, however it will be
+           some time before this becomes reality: libgcj and Classpath
+           have different implementations of many core java
+           classes. In order to merge them, we need to select the best
+           (most efficient, cleanest) implementation of each
+           method/class/package, resolve any conflicts created by the
+           merge, and test the final result.  Needless to say, this is
+           a lot of work. If you can help out, please let us know!
+
+      2.8 What features of the Java language are/aren't supported.
+
+          GCJ supports all Java language constructs as per the Java
+          language Specification.  Recent GCJ snapshots have added
+          support for most JDK1.1 (and beyond) language features,
+          including inner classes.
+
+Build Issues
+============
+
+      3.1 I need something more recent than the last release.
+          How should I build it?
+
+          Please read here: http://gcc.gnu.org/java/build-snapshot.html
+
+      3.2 Linker bug on Solaris
+
+          There is a known problem with the native Solaris linker when
+          using gcc/gcj. A good indication you've run into this
+          problem is if you get an error that looks like the following
+          when building libgcj:
+
+ld: warning: option -o appears more than once, first setting taken
+ld: fatal: file libfoo.so: cannot open file: No such file or directory
+ld: fatal: File processing errors. No output written to .libs/libfoo.so
+collect2: ld returned 1 exit status
+
+          A known workaround for this and other reported link problems
+          on the various releases of Solaris is to build gcc/gcj with
+          the latest GNU binutils instead of the native Solaris
+          ld. The most straightforward way to do this is to build and
+          install binutils, and then reference it in the configure for
+          gcc via --with-ld=/path_to_binutils_install/bin/ld
+          (--with-as may also be similarly specified but is not
+          believed to be required).
+
+          Please note, gcc/gcj must be built using GNU ld prior to
+          doing a clean build of libgcj!
+
+      3.3 Can I configure/build in the source tree?
+
+          No.  You cannot configure/build in the source tree.  If you
+          try, you'll see something like:
+
+              $ ./configure [...]
+              Configuring for a i686-pc-linux-gnu host.
+              *** Cannot currently configure in source tree.
+
+          Instead, you must build in another directory.  E.g.:
+
+              $ mkdir build
+              $ cd build
+              $ ../configure [...]
+
+      3.4 My libgcj build fails with "invalid use of undefined type
+          struct sigcontext_struct"
+
+          If you're using Linux, this probably means you need to
+          upgrade to a newwer, glibc (libc6) based Linux
+          distribution. libgcj does not support the older linux libc5.
+          It might be possible to get a working libgcj by changing
+          occurances of "sigcontext_struct" to "sigcontext", however
+          this has not been tested.  Even if it works, it is likely
+          that there are other issues with older libc versions that
+          would prevent libgcj from working correctly (threads bugs,
+          for example).
+
+Gcj Compile/Link Questions
+==========================
+
+      4.1 Why do I get undefined reference to `main' errors?
+
+          When using gcj to link a Java program, you must use the --main=
+          option to indicate the class that has the desired main method.
+          This is because every Java class can have a main method, thus
+          you have to tell gcj which one to use.
+
+      4.2 Can GCJ only handle source code?
+
+          GCJ will compile both source (.java) and bytecode (.class)
+          files. However, in many cases the native code produced by
+          compiling from source is better optimized than that compiled
+          from .class files.
+
+          Per Bothner explains:
+
+            The reason is that when you compile to bytecode you lose a
+            lot of information about program structure etc. That
+            information helps in generating better code. We can in
+            theory recover the information we need by analysing the
+            structure of the bytecodes, but it is sometimes difficult
+            - or sometimes it just that no-one has gotten around to
+            it.  Specific examples include loop structure (gcc
+            generates better code with explicit loops rather than with
+            the equivalent spaghetti code), array initializers, and
+            the JDK 1.1 `CLASS.class' syntax, all of which are
+            represented using more low-level constructs in bytecode.
+
+      4.3 "gcj -C" Doesn't seem to work like javac/jikes.  Whats going on?
+
+          The behavior of "gcj -C" is not at all like javac or jikes,
+          which will compile (not just scan) all .java's which are out
+          of date with regard to their .class's.
+
+      4.4 Where does GCJ look for files?
+
+          GCJ looks for classes to compile based on the CLASSPATH
+          environment variable. libgcj.jar and other files are found
+          relative to the path of the compiler itself, so it is safe
+          to move the entire compiler tree to a different path, and
+          there is no need to include libgcj.jar in your CLASSPATH.
+
+      4.5 How does gcj resolve whether to compile .class or .java files?
+
+          GCJ compiles only the files presented to it on the command
+          line. However, it also needs to scan other files in order to
+          determine the layout of other classes and check for errors
+          in your code.  For these dependencies, GCJ will favour
+          .class files if they are available because it is faster to
+          parse a class file than source code.
+
+      4.6 I'm getting link errors
+
+          If you get errors at link time that refer to 'undefined
+          reference to `java::lang::Object type_info function', verify
+          that you have compiled any CNI C++ files with the -fno-rtti
+          option. This is only required for versions of GCJ earlier
+          than 3.0.
+
+      4.7 I'm getting 'undefined symbol: __dso_handle'
+
+          Some versions of the GNU linker have broken support for the
+          '.hidden' directive, which results in problems with shared
+          libraries built with recent versions of gcc.
+
+          There are three solutions:
+
+            - downgrade to binutils that don't support .hidden at all,
+            - upgrade to a recent binutils, or
+            - undef the HAVE_GAS_HIDDEN definition in gcc's auto-host.h
+              (and rebuild gcc).
+
+Runtime Questions
+=================
+
+      5.1 My program is dumping core! What's going on?
+
+          It could be any number of things. One common mistake is
+          having your CLASSPATH environment variable pointing at a
+          third party's java.lang and friends. Either unset CLASSPATH,
+          or make sure it does not refer to core libraries other than
+          those found in libgcj.jar.Note that newwer versions of GCJ
+          will reject the core class library if it wasn't generated by
+          GCJ itself.
+
+      5.2 When I run the debugger I get a SEGV in the GC! What's going on?
+
+          This is "normal"; the Garbage Collector (GC) uses it to
+          determine stack boundaries. It is ordinarily caught and
+          handled by the GC -- you can see this in the debugger by
+          using cont to continue to the "real" segv.
+
+      5.3 I have just compiled and benchmarked my Java application
+          and it seems to be running slower than than XXX JIT JVM. Is there
+          anything I can do to make it go faster?
+
+        A few things:
+
+          - If your programs allocate many small, short lived objects,
+            the heap could be filling and triggering GC too
+            regularly. Try increasing the initial and maximum heap sizes
+            as per 5.5 How do I increase the runtime's initial and
+            maximum heap size?
+          - RE - array accesses. We have sub-optimal runtime checking
+            code, and the compiler is still not so smart about
+            automatically removing array checks. If your code is ready,
+            and it doesn't rely on them, try compiling with
+            --no-bounds-check.
+          - Try static linking.  On many platforms, dynamic (PIC)
+            function calls are more expensive than static ones. In
+            particular, the interaction with boehm-gc seems to incur
+            extra overhead when shared libraries are used.
+          - If your Java application doesn't need threads, try
+            building libgcj using --enable-threads=none. Portions of the
+            libgcj runtime are still more efficient when
+            single-threaded.
+
+       5.4 Can I profile Garbage Collection?
+
+          It is possible to turn on verbose GC output by supressing
+          the -DSILENT flag during build. One way to do this is to
+          comment out the line with #define SILENT 1 from
+          boehm-gc/configure before configuring libgcj.  The GC will
+          print collection statistics to stdout. (Rebuilding boehm-gc
+          alone without this flag doesn't seem to work.)
+
+      5.5 How do I increase the runtime's initial and maximum heap sizes?
+
+          Some programs that allocate many small, short-lived objects
+          can cause the default-sized heap to fill quickly and GC
+          often. With the 2.95.1 release there is no means to adjust
+          the heap at runtime. Recent snapshots provide the -ms and
+          -mx arguments to gij to specify the initial and maximum heap
+          sizes, respectively.
+
+      5.6 How can I profile my application?
+
+          Currently, only single threaded Java code may be used by the
+          profiler (gprof). POSIX threads seem to be incompatible with
+          the gmon stuff.  A couple of other tools that have been
+          mentioned on the GCJ mailing list are sprof and cprof.  The
+          former is part of GNU libc.
+
+      5.7 My program seems to hang and doesn't produce any output
+
+          Some versions had a bug in the iconv support. You can work
+          around it by setting LANG=en_US.UTF-8 at runtime, or give
+          the following option during compile time
+          -Dfile.encoding=UTF-8.  This problem should no longer occur
+          as of November 1, 2000.
+
+Programming Issues
+==================
+
+      6.1 Are there any examples of how to use CNI?
+
+          Glenn Chambers has created a couple of trivial examples for
+          version 2.95 and version 3.0.  As a comparison, here is the
+          same example as a JNI application using Kaffe.  The same
+          code will work with GCJ, as shown here.
+
+          Note that for version 2.95, you must compile the C++ files
+          used for CNI with the -fno-rtti option.  This constraint
+          does not apply in version 3.0 and later.
+
+          The primary source of documentation for CNI is at
+          http://gcc.gnu.org/java/papers/cni/t1.html
+
+      6.2 Is it possible to invoke GCJ compiled Java code from a
+          C++ application?
+
+          Yes, GCJ 3.1 supports a CNI-based invocation interface as
+          well as the traditional JNI invocation API.  See the GCJ
+          Manual for more details on how to use the CNI interface.
+
+Please send FSF & GNU inquiries & questions tognu@gnu.org.There are
+also other waysto contact the FSF.
+
+These pages are maintained by The GCC team.
+
+Please send comments on these web pages and GCC to our publicmailing
+list at gcc@gnu.org orgcc@gcc.gnu.org, send other questions to
+gnu@gnu.org.
+
+Copyright (C) Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA  02111,  USA.
+
+Verbatim copying and distribution of this entire article is permitted
+in any medium, provided this notice is preserved.
+
+Last modified 2003-04-30
--- gcc-6-6.3.0.orig/debian/NEWS.gcc
+++ gcc-6-6.3.0/debian/NEWS.gcc
@@ -0,0 +1,707 @@
+This file contains information about GCC releases which has been generated
+automatically from the online release notes.  It covers releases of GCC
+(and the former EGCS project) since EGCS 1.0, on the line of development
+that led to GCC 3. For information on GCC 2.8.1 and older releases of GCC 2,
+see ONEWS.
+
+======================================================================
+http://gcc.gnu.org/gcc-6/index.html
+                              GCC 6 Release Series
+
+   April 27, 2015
+
+   The [1]GNU project and the GCC developers are pleased to announce the
+   release of GCC 6.1.
+
+   This release is a major release, containing new features (as well as
+   many other improvements) relative to GCC 5.x.
+
+Release History
+
+   GCC 6.1
+          April 27, 2015 ([2]changes, [3]documentation)
+
+References and Acknowledgements
+
+   GCC used to stand for the GNU C Compiler, but since the compiler
+   supports several other languages aside from C, it now stands for the
+   GNU Compiler Collection.
+
+   A list of [4]successful builds is updated as new information becomes
+   available.
+
+   The GCC developers would like to thank the numerous people that have
+   contributed new features, improvements, bug fixes, and other changes as
+   well as test results to GCC. This [5]amazing group of volunteers is
+   what makes GCC successful.
+
+   For additional information about GCC please refer to the [6]GCC project
+   web site or contact the [7]GCC development mailing list.
+
+   To obtain GCC please use [8]our mirror sites or [9]our SVN server.
+
+
+    For questions related to the use of GCC, please consult these web
+    pages and the [10]GCC manuals. If that fails, the
+    [11]gcc-help@gcc.gnu.org mailing list might help. Comments on these
+    web pages and the development of GCC are welcome on our developer
+    list at [12]gcc@gcc.gnu.org. All of [13]our lists have public
+    archives.
+
+   Copyright (C) [14]Free Software Foundation, Inc. Verbatim copying and
+   distribution of this entire article is permitted in any medium,
+   provided this notice is preserved.
+
+   These pages are [15]maintained by the GCC team. Last modified
+   2016-04-27[16].
+
+References
+
+   1. http://www.gnu.org/
+   2. http://gcc.gnu.org/gcc-6/changes.html
+   3. http://gcc.gnu.org/onlinedocs/6.1.0/
+   4. http://gcc.gnu.org/gcc-6/buildstat.html
+   5. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
+   6. http://gcc.gnu.org/index.html
+   7. mailto:gcc@gcc.gnu.org
+   8. http://gcc.gnu.org/mirrors.html
+   9. http://gcc.gnu.org/svn.html
+  10. https://gcc.gnu.org/onlinedocs/
+  11. mailto:gcc-help@gcc.gnu.org
+  12. mailto:gcc@gcc.gnu.org
+  13. https://gcc.gnu.org/lists.html
+  14. http://www.fsf.org/
+  15. https://gcc.gnu.org/about.html
+  16. http://validator.w3.org/check/referer
+======================================================================
+http://gcc.gnu.org/gcc-6/changes.html
+                              GCC 6 Release Series
+                        Changes, New Features, and Fixes
+
+   This page is a brief summary of some of the huge number of improvements
+   in GCC 6. For more information, see the [1]Porting to GCC 6 page and
+   the [2]full GCC documentation.
+
+Caveats
+
+     * The default mode for C++ is now -std=gnu++14 instead of
+       -std=gnu++98.
+     * Support for a number of older systems and recently unmaintained or
+       untested target ports of GCC has been declared obsolete in GCC 6.
+       Unless there is activity to revive them, the next release of GCC
+       will have their sources permanently removed.
+       The following ports for individual systems on particular
+       architectures have been obsoleted:
+          + SH5 / SH64 (sh64-*-*) as announced [3]here.
+
+General Optimizer Improvements
+
+     * UndefinedBehaviorSanitizer gained a new sanitization option,
+       -fsanitize=bounds-strict, which enables strict checking of array
+       bounds. In particular, it enables -fsanitize=bounds as well as
+       instrumentation of flexible array member-like arrays.
+     * Type-based alias analysis now disambiguates accesses to different
+       pointers. This improves precision of the alias oracle by about
+       20-30% on higher-level C++ programs. Programs doing invalid type
+       punning of pointer types may now need -fno-strict-aliasing to work
+       correctly.
+     * Alias analysis now correctly supports weakref and alias attributes.
+       This makes it possible to access both a variable and its alias in
+       one translation unit which is common with link-time optimization.
+     * Value range propagation now assumes that the this pointer of C++
+       member functions is non-null. This eliminates common null pointer
+       checks but also breaks some non-conforming code-bases (such as
+       Qt-5, Chromium, KDevelop). As a temporary work-around
+       -fno-delete-null-pointer-checks can be used. Wrong code can be
+       identified by using -fsanitize=undefined.
+     * Link-time optimization improvements:
+          + warning and error attributes are now correctly preserved by
+            declaration linking and thus -D_FORTIFY_SOURCE=2 is now
+            supported with -flto.
+          + Type merging was fixed to handle C and Fortran
+            interoperability rules as defined by the Fortran 2008 language
+            standard.
+            As an exception, CHARACTER(KIND=C_CHAR) is not inter-operable
+            with char in all cases because it is an array while char is
+            scalar. INTEGER(KIND=C_SIGNED_CHAR) should be used instead. In
+            general, this inter-operability cannot be implemented, for
+            example, on targets where function passing conventions of
+            arrays differs from scalars.
+          + More type information is now preserved at link time reducing
+            the loss of accuracy of the type based alias analysis compared
+            to builds without link-time optimization.
+          + Invalid type punning on global variables and declarations is
+            now reported with -Wodr-type-mismatch.
+          + The size of LTO object files was reduced by about 11%
+            (measured by compiling Firefox 46.0).
+          + Link-time parallelization (enabled using -flto=n) was
+            significantly improved by decreasing the size of streamed data
+            when partitioning programs. The size of streamed IL while
+            compiling Firefox 46.0 was reduced by 66%.
+          + The linker plugin was extended to pass information about type
+            of binary produced to GCC back end (that can be also manually
+            controlled by -flinker-output). This makes it possible to
+            properly configure the code generator and support incremental
+            linking. Incremental linking of LTO objects by gcc -r is now
+            supported on plugin-enabled setups.
+            There are two ways to perform incremental linking:
+              1. Linking by ld -r will result in an object file with all
+                 sections from individual object files mechanically
+                 merged. This delays the actual link time optimization to
+                 final linking step and thus permits whole program
+                 optimization. Linking final binary with such object files
+                 is however slower.
+              2. Linking by gcc -r will lead to link time optimization and
+                 produce final binary into the object file. Linking such
+                 object file is fast but avoids any benefits from whole
+                 program optimization.
+            GCC 7 will support incremental link-time optimization with gcc
+            -r.
+     * Inter-procedural optimization improvements:
+          + Basic jump threading is now performed before profile
+            construction and inline analysis, resulting in more realistic
+            size and time estimates that drive the heuristics of the of
+            inliner and function cloning passes.
+          + Function cloning now more aggressively eliminates unused
+            function parameters.
+
+New Languages and Language specific improvements
+
+   Compared to GCC 5, the GCC 6 release series includes a much improved
+   implementation of the [4]OpenACC 2.0a specification. Highlights are:
+     * In addition to single-threaded host-fallback execution, offloading
+       is supported for nvptx (Nvidia GPUs) on x86_64 and PowerPC 64-bit
+       little-endian GNU/Linux host systems. For nvptx offloading, with
+       the OpenACC parallel construct, the execution model allows for an
+       arbitrary number of gangs, up to 32 workers, and 32 vectors.
+     * Initial support for parallelized execution of OpenACC kernels
+       constructs:
+          + Parallelization of a kernels region is switched on by
+            -fopenacc combined with -O2 or higher.
+          + Code is offloaded onto multiple gangs, but executes with just
+            one worker, and a vector length of 1.
+          + Directives inside a kernels region are not supported.
+          + Loops with reductions can be parallelized.
+          + Only kernels regions with one loop nest are parallelized.
+          + Only the outer-most loop of a loop nest can be parallelized.
+          + Loop nests containing sibling loops are not parallelized.
+       Typically, using the OpenACC parallel construct gives much better
+       performance, compared to the initial support of the OpenACC kernels
+       construct.
+     * The device_type clause is not supported. The bind and nohost
+       clauses are not supported. The host_data directive is not supported
+       in Fortran.
+     * Nested parallelism (cf. CUDA dynamic parallelism) is not supported.
+     * Usage of OpenACC constructs inside multithreaded contexts (such as
+       created by OpenMP, or pthread programming) is not supported.
+     * If a call to the acc_on_device function has a compile-time constant
+       argument, the function call evaluates to a compile-time constant
+       value only for C and C++ but not for Fortran.
+
+   See the [5]OpenACC and [6]Offloading wiki pages for further
+   information.
+
+  C family
+
+     * Version 4.5 of the [7]OpenMP specification is now supported in the
+       C and C++ compilers.
+     * The C and C++ compilers now support attributes on enumerators. For
+       instance, it is now possible to mark enumerators as deprecated:
+
+enum {
+  newval,
+  oldval __attribute__ ((deprecated ("too old")))
+};
+
+     * Source locations for the C and C++ compilers are now tracked as
+       ranges, rather than just points, making it easier to identify the
+       subexpression of interest within a complicated expression. For
+       example:
+
+test.cc: In function 'int test(int, int, foo, int, int)':
+test.cc:5:16: error: no match for 'operator*' (operand types are 'int' and 'foo'
+)
+   return p + q * r * s + t;
+              ~~^~~
+
+       In addition, there is now initial support for precise diagnostic
+       locations within strings:
+
+format-strings.c:3:14: warning: field width specifier '*' expects a matching 'in
+t' argument [-Wformat=]
+   printf("%*d");
+            ^
+
+     * Diagnostics can now contain "fix-it hints", which are displayed in
+       context underneath the relevant source code. For example:
+
+fixits.c: In function 'bad_deref':
+fixits.c:11:13: error: 'ptr' is a pointer; did you mean to use '->'?
+   return ptr.x;
+             ^
+             ->
+
+     * The C and C++ compilers now offer suggestions for misspelled field
+       names:
+
+spellcheck-fields.cc:52:13: error: 'struct s' has no member named 'colour'; did
+you mean 'color'?
+   return ptr->colour;
+               ^~~~~~
+
+     * New command-line options have been added for the C and C++
+       compilers:
+          + -Wshift-negative-value warns about left shifting a negative
+            value.
+          + -Wshift-overflow warns about left shift overflows. This
+            warning is enabled by default. -Wshift-overflow=2 also warns
+            about left-shifting 1 into the sign bit.
+          + -Wtautological-compare warns if a self-comparison always
+            evaluates to true or false. This warning is enabled by -Wall.
+          + -Wnull-dereference warns if the compiler detects paths that
+            trigger erroneous or undefined behavior due to dereferencing a
+            null pointer. This option is only active when
+            -fdelete-null-pointer-checks is active, which is enabled by
+            optimizations in most targets. The precision of the warnings
+            depends on the optimization options used.
+          + -Wduplicated-cond warns about duplicated conditions in an
+            if-else-if chain.
+          + -Wmisleading-indentation warns about places where the
+            indentation of the code gives a misleading idea of the block
+            structure of the code to a human reader. For example, given
+            [8]CVE-2014-1266:
+
+sslKeyExchange.c: In function 'SSLVerifySignedServerKeyExchange':
+sslKeyExchange.c:629:3: warning: this 'if' clause does not guard... [-Wmisleadin
+g-indentation]
+    if ((err = SSLHashSHA1.update(&hashCtx, &signedParams)) != 0)
+    ^~
+sslKeyExchange.c:631:5: note: ...this statement, but the latter is misleadingly
+indented as if it is guarded by the 'if'
+        goto fail;
+        ^~~~
+
+            This warning is enabled by -Wall.
+     * The C and C++ compilers now emit saner error messages if
+       merge-conflict markers are present in a source file.
+
+test.c:3:1: error: version control conflict marker in file
+ <<<<<<< HEAD
+ ^~~~~~~
+
+  C
+
+     * It is possible to disable warnings when an initialized field of a
+       structure or a union with side effects is being overridden when
+       using designated initializers via a new warning option
+       -Woverride-init-side-effects.
+     * A new type attribute scalar_storage_order applying to structures
+       and unions has been introduced. It specifies the storage order (aka
+       endianness) in memory of scalar fields in structures or unions.
+
+  C++
+
+     * The default mode has been changed to -std=gnu++14.
+     * [9]C++ Concepts are now supported when compiling with -fconcepts.
+     * -flifetime-dse is more aggressive in dead-store elimination in
+       situations where a memory store to a location precedes a
+       constructor to the memory location.
+     * G++ now supports [10]C++17 fold expressions, u8 character literals,
+       extended static_assert, and nested namespace definitions.
+     * G++ now allows constant evaluation for all non-type template
+       arguments.
+     * G++ now supports C++ Transactional Memory when compiling with
+       -fgnu-tm.
+
+    Runtime Library (libstdc++)
+
+     * Extensions to the C++ Library to support mathematical special
+       functions (ISO/IEC 29124:2010), thanks to Edward Smith-Rowland.
+     * Experimental support for C++17, including the following new
+       features:
+          + std::uncaught_exceptions function (this is also available for
+            -std=gnu++NN modes);
+          + new member functions try_emplace and insert_or_assign for
+            unique_key maps;
+          + non-member functions std::size, std::empty, and std::data for
+            accessing containers and arrays;
+          + std::invoke;
+          + std::shared_mutex;
+          + std::void_t and std::bool_constant metaprogramming utilities.
+       Thanks to Ville Voutilainen for contributing many of the C++17
+       features.
+     * An experimental implementation of the File System TS.
+     * Experimental support for most features of the second version of the
+       Library Fundamentals TS. This includes polymorphic memory resources
+       and array support in shared_ptr, thanks to Fan You.
+     * Some assertions checked by Debug Mode can now also be enabled by
+       _GLIBCXX_ASSERTIONS. The subset of checks enabled by the new macro
+       have less run-time overhead than the full _GLIBCXX_DEBUG checks and
+       don't affect the library ABI, so can be enabled per-translation
+       unit.
+     * Timed mutex types are supported on more targets, including Darwin.
+     * Improved std::locale support for DragonFly and FreeBSD, thanks to
+       John Marino and Andreas Tobler.
+
+  Fortran
+
+     * The MATMUL intrinsic is now inlined for straightforward cases if
+       front-end optimization is active. The maximum size for inlining can
+       be set to n with the -finline-matmul-limit=n option and turned off
+       with -finline-matmul-llimit=0.
+     * The -Wconversion-extra option will warn about REAL constants which
+       have excess precision for their kind.
+     * The -Winteger-division option has been added, which warns about
+       divisions of integer constants which are truncated. This option is
+       included in -Wall by default.
+
+libgccjit
+
+     * The driver code is now run in-process within libgccjit, providing a
+       small speed-up of the compilation process.
+     * The API has gained entrypoints for
+          + [11]timing how long was spent in different parts of code,
+          + [12]creating switch statements,
+          + [13]allowing unreachable basic blocks in a function, and
+          + [14]adding arbitrary command-line options to a compilation.
+
+New Targets and Target Specific Improvements
+
+  AArch64
+
+     * The new command line options -march=native, -mcpu=native and
+       -mtune=native are now available on native AArch64 GNU/Linux
+       systems. Specifying these options will cause GCC to auto-detect the
+       host CPU and rewrite these options to the optimal setting for that
+       system. If GCC is unable to detect the host CPU these options have
+       no effect.
+     * -fpic is now supported by the AArch64 target when generating code
+       for the small code model (-mcmodel=small). The size of the global
+       offset table (GOT) is limited to 28KiB under the LP64 SysV ABI ,
+       and 15KiB under the ILP32 SysV ABI.
+     * The AArch64 port now supports target attributes and pragmas. Please
+       refer to the [15]documentation for details of available attributes
+       and pragmas as well as usage instructions.
+     * Link-time optimization across translation units with different
+       target-specific options is now supported.
+
+  ARM
+
+     * Support for revisions of the ARM architecture prior to ARMv4t has
+       been deprecated and will be removed in a future GCC release. The
+       -mcpu and -mtune values that are deprecated are: arm2, arm250,
+       arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di,
+       arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500,
+       arm7500fe, arm7m, arm7dm, arm7dmi, arm8, arm810, strongarm,
+       strongarm110, strongarm1100, strongarm1110, fa526, fa626. The value
+       arm7tdmi is still supported. The values of -march that are
+       deprecated are: armv2,armv2a,armv3,armv3m,armv4.
+     * The ARM port now supports target attributes and pragmas. Please
+       refer to the [16]documentation for details of available attributes
+       and pragmas as well as usage instructions.
+     * Support has been added for the following processors (GCC
+       identifiers in parentheses): ARM Cortex-A32 (cortex-a32), ARM
+       Cortex-A35 (cortex-a35). The GCC identifiers can be used as
+       arguments to the -mcpu or -mtune options, for example:
+       -mcpu=cortex-a32 or -mtune=cortex-a35.
+
+  Heterogeneous Systems Architecture
+
+     * GCC can now generate HSAIL (Heterogeneous System Architecture
+       Intermediate Language) for simple OpenMP device constructs if
+       configured with --enable-offload-targets=hsa. A new libgomp plugin
+       then runs the HSA GPU kernels implementing these constructs on HSA
+       capable GPUs via a standard HSA run time.
+       If the HSA compilation back end determines it cannot output HSAIL
+       for a particular input, it gives a warning by default. These
+       warnings can be suppressed with -Wno-hsa. To give a few examples,
+       the HSA back end does not implement compilation of code using
+       function pointers, automatic allocation of variable sized arrays,
+       functions with variadic arguments as well as a number of other less
+       common programming constructs.
+       When compilation for HSA is enabled, the compiler attempts to
+       compile composite OpenMP constructs
+
+#pragma omp target teams distribute parallel for
+
+       into parallel HSA GPU kernels.
+
+  IA-32/x86-64
+
+     * GCC now supports the Intel CPU named Skylake with AVX-512
+       extensions through -march=skylake-avx512. The switch enables the
+       following ISA extensions: AVX-512F, AVX512VL, AVX-512CD, AVX-512BW,
+       AVX-512DQ.
+     * Support for new AMD instructions monitorx and mwaitx has been
+       added. This includes new intrinsic and built-in support. It is
+       enabled through option -mmwaitx. The instructions monitorx and
+       mwaitx implement the same functionality as the old monitor and
+       mwait instructions. In addition mwaitx adds a configurable timer.
+       The timer value is received as third argument and stored in
+       register %ebx.
+     * x86-64 targets now allow stack realignment from a word-aligned
+       stack pointer using the command-line option -mstackrealign or
+       __attribute__ ((force_align_arg_pointer)). This allows functions
+       compiled with a vector-aligned stack to be invoked from objects
+       that keep only word-alignment.
+     * Support for address spaces __seg_fs, __seg_gs, and __seg_tls. These
+       can be used to access data via the %fs and %gs segments without
+       having to resort to inline assembly. Please refer to the
+       [17]documentation for usage instructions.
+     * Support for AMD Zen (family 17h) processors is now available
+       through the -march=znver1 and -mtune=znver1 options.
+
+  MeP
+
+     * Support for the MeP (mep-elf) architecture has been deprecated and
+       will be removed in a future GCC release.
+
+  MSP430
+
+     * The MSP430 compiler now has the ability to automatically distribute
+       code and data between low memory (addresses below 64K) and high
+       memory. This only applies to parts that actually have both memory
+       regions and only if the linker script for the part has been
+       specifically set up to support this feature.
+       A new attribute of either can be applied to both functions and
+       data, and this tells the compiler to place the object into low
+       memory if there is room and into high memory otherwise. Two other
+       new attributes - lower and upper - can be used to explicitly state
+       that an object should be placed in the specified memory region. If
+       there is not enough left in that region the compilation will fail.
+       Two new command-line options - -mcode-region=[lower|upper|either]
+       and -mdata-region=[lower|upper|either] - can be used to tell the
+       compiler what to do with objects that do not have one of these new
+       attributes.
+
+  PowerPC / PowerPC64 / RS6000
+
+     * PowerPC64 now supports IEEE 128-bit floating-point using the
+       __float128 data type. In GCC 6, this is NOT enabled by default, but
+       you can enable it with -mfloat128. The IEEE 128-bit floating-point
+       support requires the use of the VSX instruction set. IEEE 128-bit
+       floating-point values are passed and returned as a single vector
+       value. The software emulator for IEEE 128-bit floating-point
+       support is only built on PowerPC Linux systems where the default
+       cpu is at least power7. On future ISA 3.0 systems (power9 and
+       later), you will be able to use the -mfloat128-hardware option to
+       use the ISA 3.0 instructions that support IEEE 128-bit
+       floating-point. An additional type (__ibm128) has been added to
+       refer to the IBM extended double type that normally implements long
+       double. This will allow for a future transition to implementing
+       long double with IEEE 128-bit floating-point.
+     * Basic support has been added for POWER9 hardware that will use the
+       recently published OpenPOWER ISA 3.0 instructions. The following
+       new switches are available:
+          + -mcpu=power9: Implement all of the ISA 3.0 instructions
+            supported by the compiler.
+          + -mtune=power9: In the future, apply tuning for POWER9 systems.
+            Currently, POWER8 tunings are used.
+          + -mmodulo: Generate code using the ISA 3.0 integer instructions
+            (modulus, count trailing zeros, array index support, integer
+            multiply/add).
+          + -mpower9-fusion: Generate code to suitably fuse instruction
+            sequences for a POWER9 system.
+          + -mpower9-dform: Generate code to use the new D-form (register
+            +offset) memory instructions for the vector registers.
+          + -mpower9-vector: Generate code using the new ISA 3.0 vector
+            (VSX or Altivec) instructions.
+          + -mpower9-minmax: Reserved for future development.
+          + -mtoc-fusion: Keep TOC entries together to provide more fusion
+            opportunities.
+     * New constraints have been added to support IEEE 128-bit
+       floating-point and ISA 3.0 instructions:
+          + wb: Altivec register if -mpower9-dform is enabled.
+          + we: VSX register if -mpower9-vector is enabled for 64-bit code
+            generation.
+          + wo: VSX register if -mpower9-vector is enabled.
+          + wp: Reserved for future use if long double is implemented with
+            IEEE 128-bit floating-point instead of IBM extended double.
+          + wq: VSX register if -mfloat128 is enabled.
+          + wF: Memory operand suitable for POWER9 fusion load/store.
+          + wG: Memory operand suitable for TOC fusion memory references.
+          + wL: Integer constant identifying the element number mfvsrld
+            accesses within a vector.
+     * Support has been added for __builtin_cpu_is () and
+       __builtin_cpu_supports (), allowing for very fast access to
+       AT_PLATFORM, AT_HWCAP, and AT_HWCAP2 values. This requires use of
+       glibc 2.23 or later.
+     * All hardware transactional memory builtins now correctly behave as
+       memory barriers. Programmers can use #ifdef __TM_FENCE__ to
+       determine whether their "old" compiler treats the builtins as
+       barriers.
+     * Split-stack support has been added for gccgo on PowerPC64 for both
+       big- and little-endian (but NOT for 32-bit). The gold linker from
+       at least binutils 2.25.1 must be available in the PATH when
+       configuring and building gccgo to enable split stack. (The
+       requirement for binutils 2.25.1 applies to PowerPC64 only.) The
+       split-stack feature allows a small initial stack size to be
+       allocated for each goroutine, which increases as needed.
+     * GCC on PowerPC now supports the standard lround function.
+     * A new configuration option ---with-advance-toolchain=at was added
+       for PowerPC 64-bit GNU/Linux systems to use the header files,
+       library files, and the dynamic linker from a specific Advance
+       Toolchain release instead of the default versions that are provided
+       by the GNU/Linux distribution. In general, this option is intended
+       for the developers of GCC, and it is not intended for general use.
+     * The "q", "S", "T", and "t" asm-constraints have been removed.
+     * The "b", "B", "m", "M", and "W" format modifiers have been removed.
+
+  S/390, System z, IBM z Systems
+
+     * Support for the IBM z13 processor has been added. When using the
+       -march=z13 option, the compiler will generate code making use of
+       the new instructions and registers introduced with the vector
+       extension facility. The -mtune=z13 option enables z13 specific
+       instruction scheduling without making use of new instructions.
+       Compiling code with -march=z13 reduces the default alignment of
+       vector types bigger than 8 bytes to 8. This is an ABI change and
+       care must be taken when linking modules compiled with different
+       arch levels which interchange variables containing vector type
+       values. For newly compiled code the GNU linker will emit a warning.
+     * The -mzvector option enables a C/C++ language extension. This
+       extension provides a new keyword vector which can be used to define
+       vector type variables. (Note: This is not available when enforcing
+       strict standard compliance e.g. with -std=c99. Either enable GNU
+       extensions with e.g. -std=gnu99 or use __vector instead of vector.)
+       Additionally a set of overloaded builtins is provided which is
+       partially compatible to the PowerPC Altivec builtins. In order to
+       make use of these builtins the vecintrin.h header file needs to be
+       included.
+     * The new command line options -march=native, and -mtune=native are
+       now available on native IBM z Systems. Specifying these options
+       will cause GCC to auto-detect the host CPU and rewrite these
+       options to the optimal setting for that system. If GCC is unable to
+       detect the host CPU these options have no effect.
+     * The IBM z Systems port now supports target attributes and pragmas.
+       Please refer to the [18]documentation for details of available
+       attributes and pragmas as well as usage instructions.
+     * -fsplit-stack is now supported as part of the IBM z Systems port.
+       This feature requires a recent gold linker to be used.
+     * Support for the g5 and g6 -march=/-mtune= CPU level switches has
+       been deprecated and will be removed in a future GCC release. -m31
+       from now on defaults to -march=z900 if not specified otherwise.
+       -march=native on a g5/g6 machine will default to -march=z900.
+
+  SH
+
+     * Support for SH5 / SH64 has been declared obsolete and will be
+       removed in future releases.
+     * Support for the FDPIC ABI has been added. It can be enabled using
+       the new -mfdpic target option and --enable-fdpic configure option.
+
+  SPARC
+
+     * An ABI bug has been fixed in 64-bit mode. Unfortunately, this
+       change will break binary compatibility with earlier releases for
+       code it affects, but this should be pretty rare in practice. The
+       conditions are: a 16-byte structure containing a double or a 8-byte
+       vector in the second half is passed to a subprogram in slot #15,
+       for example as 16th parameter if the first 15 ones have at most 8
+       bytes. The double or vector was wrongly passed in floating-point
+       register %d32 in lieu of on the stack as per the SPARC calling
+       conventions.
+
+Operating Systems
+
+  Linux
+
+     * Support for the [19]musl C library was added for the AArch64, ARM,
+       MicroBlaze, MIPS, MIPS64, PowerPC, PowerPC64, SH, i386, x32 and
+       x86_64 targets. It can be selected using the new -mmusl option in
+       case musl is not the default libc. GCC defaults to musl libc if it
+       is built with a target triplet matching the *-linux-musl* pattern.
+
+  RTEMS
+
+     * The RTEMS thread model implementation changed. Mutexes now use
+       self-contained objects defined in Newlib <sys/lock.h> instead of
+       Classic API semaphores. The keys for thread specific data and the
+       once function are directly defined via <pthread.h>. Self-contained
+       condition variables are provided via Newlib <sys/lock.h>. The RTEMS
+       thread model also supports C++11 threads.
+     * OpenMP support now uses self-contained objects provided by Newlib
+       <sys/lock.h> and offers a significantly better performance compared
+       to the POSIX configuration of libgomp. It is possible to configure
+       thread pools for each scheduler instance via the environment
+       variable GOMP_RTEMS_THREAD_POOLS.
+
+  AIX
+
+     * DWARF debugging support for AIX 7.1 has been enabled as an optional
+       debugging format. A more recent Technology Level (TL) and GCC built
+       with that level are required for full exploitation of DWARF
+       debugging capabilities.
+
+  Solaris
+
+     * Solaris 12 is now fully supported. Minimal support had already been
+       present in GCC 5.3.
+     * Solaris 12 provides a full set of startup files (crt1.o, crti.o,
+       crtn.o), which GCC now prefers over its own ones.
+     * Position independent executables (PIE) are now supported on Solaris
+       12.
+     * Constructor priority is now supported on Solaris 12 with the system
+       linker.
+     * libvtv has been ported to Solaris 11 and up.
+
+  Windows
+
+     * The option -mstackrealign is now automatically activated in 32-bit
+       mode whenever the use of SSE instructions is requested.
+
+Other significant improvements
+
+     * The gcc and g++ driver programs will now provide suggestions for
+       misspelled command line options.
+
+$ gcc -static-libfortran test.f95
+gcc: error: unrecognized command line option '-static-libfortran'; did you mean
+'-static-libgfortran'?
+
+     * The --enable-default-pie configure option enables generation of PIE
+       by default.
+
+
+    For questions related to the use of GCC, please consult these web
+    pages and the [20]GCC manuals. If that fails, the
+    [21]gcc-help@gcc.gnu.org mailing list might help. Comments on these
+    web pages and the development of GCC are welcome on our developer
+    list at [22]gcc@gcc.gnu.org. All of [23]our lists have public
+    archives.
+
+   Copyright (C) [24]Free Software Foundation, Inc. Verbatim copying and
+   distribution of this entire article is permitted in any medium,
+   provided this notice is preserved.
+
+   These pages are [25]maintained by the GCC team. Last modified
+   2016-04-25[26].
+
+References
+
+   1. http://gcc.gnu.org/gcc-6/porting_to.html
+   2. http://gcc.gnu.org/onlinedocs/index.html#current
+   3. https://gcc.gnu.org/ml/gcc/2015-08/msg00101.html
+   4. http://www.openacc.org/
+   5. https://gcc.gnu.org/wiki/OpenACC
+   6. https://gcc.gnu.org/wiki/Offloading
+   7. http://openmp.org/wp/openmp-specifications/
+   8. https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2014-1266
+   9. http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4377.pdf
+  10. https://gcc.gnu.org/projects/cxx-status.html#cxx1z.html
+  11. https://gcc.gnu.org/onlinedocs/jit/topics/performance.html
+  12. https://gcc.gnu.org/onlinedocs/jit/topics/functions.html#gcc_jit_block_end_with_switch
+  13. https://gcc.gnu.org/onlinedocs/jit/topics/contexts.html#gcc_jit_context_set_bool_allow_unreachable_blocks
+  14. https://gcc.gnu.org/onlinedocs/jit/topics/contexts.html#gcc_jit_context_add_command_line_option
+  15. https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes
+  16. https://gcc.gnu.org/onlinedocs/gcc/ARM-Function-Attributes.html#ARM-Function-Attributes
+  17. https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html#Named-Address-Spaces
+  18. https://gcc.gnu.org/onlinedocs/gcc/S_002f390-Function-Attributes.html#S_002f390-Function-Attributes
+  19. http://www.musl-libc.org/
+  20. https://gcc.gnu.org/onlinedocs/
+  21. mailto:gcc-help@gcc.gnu.org
+  22. mailto:gcc@gcc.gnu.org
+  23. https://gcc.gnu.org/lists.html
+  24. http://www.fsf.org/
+  25. https://gcc.gnu.org/about.html
+  26. http://validator.w3.org/check/referer
--- gcc-6-6.3.0.orig/debian/NEWS.html
+++ gcc-6-6.3.0/debian/NEWS.html
@@ -0,0 +1,843 @@
+<?xml version="1.0" encoding="utf-8"?>
+  <!DOCTYPE html
+            PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+            "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+ 
+
+
+ 
+
+
+
+
+
+
+
+
+
+
+     <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
+  
+  
+   <head>
+ 
+    <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+    <link rev="made" href="mailto:gcc@gcc.gnu.org" />
+    <link rel="stylesheet" type="text/css" href="https://gcc.gnu.org/gcc.css" />
+  
+ <title>
+GCC 6 Release Series &mdash; Changes, New Features, and Fixes
+- GNU Project - Free Software Foundation (FSF)</title>
+   </head>
+ 
+
+<!-- GCC maintainers, please do not hesitate to update/contribute entries
+     concerning those part of GCC you maintain!  2002-03-23, Gerald.
+-->
+
+<body>
+
+
+
+<h1>GCC 6 Release Series<br />Changes, New Features, and Fixes</h1>
+
+<p>
+This page is a brief summary of some of the huge number of improvements in GCC 6.
+For more information, see the
+<a href="porting_to.html">Porting to GCC 6</a> page and the
+<a href="../onlinedocs/index.html#current">full GCC documentation</a>.
+</p>
+
+<!-- .................................................................. -->
+<h2>Caveats</h2>
+  <ul>
+    <li>The default mode for C++ is now <code>-std=gnu++14</code> instead of
+        <code>-std=gnu++98</code>.</li>
+
+    <li><p>Support for a number of older systems and recently
+    unmaintained or untested target ports of GCC has been declared
+    obsolete in GCC 6.  Unless there is activity to revive them, the
+    next release of GCC will have their sources permanently
+    <strong>removed</strong>.</p>
+
+    <p>The following ports for individual systems on
+    particular architectures have been obsoleted:</p>
+
+    <ul>
+	  <li>SH5 / SH64 (sh64-*-*) as announced
+	  <a href="https://gcc.gnu.org/ml/gcc/2015-08/msg00101.html">
+	      here</a>.</li>
+    </ul>
+    </li>
+
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="general">General Optimizer Improvements</h2>
+  <ul>
+    <li>UndefinedBehaviorSanitizer gained a new sanitization option,
+	<code>-fsanitize=bounds-strict</code>, which enables strict checking
+	of array bounds.  In particular, it enables
+	<code>-fsanitize=bounds</code> as well as instrumentation of
+	flexible array member-like arrays.</li>
+    <li>Type-based alias analysis now disambiguates accesses to different
+	pointers. This improves precision of the alias oracle by about 20-30%
+	on higher-level C++ programs. Programs doing invalid type punning
+	of pointer types may now need <code>-fno-strict-aliasing</code>
+	to work correctly.</li>
+    <li>Alias analysis now correctly supports <code>weakref</code> and
+	<code>alias</code> attributes. This makes it possible to access
+	both a variable and its alias in one translation unit which is common
+	with link-time optimization.</li>
+    <li>Value range propagation now assumes that the <code>this</code> pointer
+	of C++ member functions is non-null.  This eliminates
+	common null pointer checks
+	but also breaks some non-conforming code-bases (such as Qt-5, Chromium,
+	KDevelop). As a temporary work-around
+	<code>-fno-delete-null-pointer-checks</code> can be used. Wrong
+	code can be identified by using <code>-fsanitize=undefined</code>.</li>
+    <li>Link-time optimization improvements:
+    <ul>
+      <li><code>warning</code> and <code>error</code> attributes are now
+	  correctly preserved by declaration linking and thus
+	  <code>-D_FORTIFY_SOURCE=2</code> is now supported with <code>-flto</code>.</li>
+      <li><p>Type merging was fixed to handle C and Fortran interoperability
+	  rules as defined by the Fortran 2008 language standard.</p>
+	  <p>
+	  As an exception, <code>CHARACTER(KIND=C_CHAR)</code> is not inter-operable
+	  with <code>char</code> in all cases because it is an array while
+	  <code>char</code> is scalar.
+	  <code>INTEGER(KIND=C_SIGNED_CHAR)</code> should be used instead.
+	  In general, this inter-operability cannot be implemented, for
+	  example, on targets where function passing conventions of arrays
+	  differs from scalars.</p></li>
+      <li>More type information is now preserved at link time reducing
+	  the loss of accuracy of the type based alias analysis compared
+	  to builds without link-time optimization.</li>
+      <li>Invalid type punning on global variables and declarations is now
+	  reported with <code>-Wodr-type-mismatch</code>.</li>
+      <li>The size of LTO object files was reduced by about 11% (measured
+	  by compiling Firefox 46.0).</li>
+      <li>Link-time parallelization (enabled using <code>-flto=n</code>)
+	  was significantly improved by decreasing the size of streamed
+	  data when partitioning programs.  The size of streamed
+	  IL while compiling Firefox 46.0 was reduced by 66%.</li>
+      <li><p>The linker plugin was extended to pass information about type of
+	  binary produced to GCC back end (that can be also manually controlled
+	  by <code>-flinker-output</code>).  This makes it possible to
+	  properly configure the code generator and support incremental
+	  linking. Incremental linking of LTO objects by <code>gcc -r</code> is
+	  now supported on plugin-enabled setups.</p>
+	  <p>There are two ways to perform incremental linking:</p>
+	  <ol>
+	     <li>Linking by <code>ld -r</code> will result in an object file
+	     with all sections from individual object files mechanically merged.
+	     This delays the actual link time optimization to final linking step
+	     and thus permits whole program optimization.  Linking final binary
+	     with such object files is however slower.</li>
+	     <li>Linking by <code>gcc -r</code> will lead to link time optimization
+	     and produce final binary into the object file.  Linking such object
+	     file is fast but avoids any benefits from whole program optimization.</li>
+	  </ol>
+	  GCC 7 will support incremental link-time optimization with <code>gcc -r</code>.</li>
+    </ul></li>
+    <li>Inter-procedural optimization improvements:
+    <ul>
+      <li>Basic jump threading is now performed before profile construction
+	  and inline analysis, resulting in more realistic size and time estimates
+	  that drive the heuristics of the of inliner and function cloning passes.</li>
+      <li>Function cloning now more aggressively eliminates unused function
+	  parameters.</li>
+    </ul></li>
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="languages">New Languages and Language specific improvements</h2>
+
+<!-- <ul>
+  <li> -->Compared to GCC 5, the GCC 6 release series includes a much improved
+    implementation of the <a href="http://www.openacc.org/">OpenACC 2.0a
+      specification</a>.  Highlights are:
+    <ul>
+      <li>In addition to single-threaded host-fallback execution, offloading is
+	supported for nvptx (Nvidia GPUs) on x86_64 and PowerPC 64-bit
+	little-endian GNU/Linux host systems.  For nvptx offloading, with the
+	OpenACC parallel construct, the execution model allows for an arbitrary
+	number of gangs, up to 32 workers, and 32 vectors.</li>
+      <li>Initial support for parallelized execution of OpenACC kernels
+	constructs:
+	<ul>
+	  <li>Parallelization of a kernels region is switched on
+	    by <code>-fopenacc</code> combined with <code>-O2</code> or
+	    higher.</li>
+	  <li>Code is offloaded onto multiple gangs, but executes with just one
+	    worker, and a vector length of 1.</li>
+	  <li>Directives inside a kernels region are not supported.</li>
+	  <li>Loops with reductions can be parallelized.</li>
+	  <li>Only kernels regions with one loop nest are parallelized.</li>
+	  <li>Only the outer-most loop of a loop nest can be parallelized.</li>
+	  <li>Loop nests containing sibling loops are not parallelized.</li>
+	</ul>
+	Typically, using the OpenACC parallel construct gives much better
+	performance, compared to the initial support of the OpenACC kernels
+	construct.</li>
+      <li>The <code>device_type</code> clause is not supported.
+	The <code>bind</code> and <code>nohost</code> clauses are not
+	supported.  The <code>host_data</code> directive is not supported in
+	Fortran.</li>
+      <li>Nested parallelism (cf. CUDA dynamic parallelism) is not
+	supported.</li>
+      <li>Usage of OpenACC constructs inside multithreaded contexts (such as
+	created by OpenMP, or pthread programming) is not supported.</li>
+      <li>If a call to the <code>acc_on_device</code> function has a
+	compile-time constant argument, the function call evaluates to a
+	compile-time constant value only for C and C++ but not for
+	Fortran.</li>
+    </ul>
+    See the <a href="https://gcc.gnu.org/wiki/OpenACC">OpenACC</a>
+    and <a href="https://gcc.gnu.org/wiki/Offloading">Offloading</a> wiki pages
+    for further information.
+  <!-- </li>
+</ul> -->
+
+<!-- <h3 id="ada">Ada</h3> -->
+
+<h3 id="c-family">C family</h3>
+  <ul>
+    <li>Version 4.5 of the <a href="http://openmp.org/wp/openmp-specifications/"
+	>OpenMP specification</a> is now supported in the C and C++ compilers.</li>
+
+    <li>The C and C++ compilers now support attributes on enumerators.  For instance,
+	it is now possible to mark enumerators as deprecated:
+<blockquote><pre>
+enum {
+  newval,
+  oldval __attribute__ ((deprecated ("too old")))
+};
+</pre></blockquote></li>
+<li>Source locations for the C and C++ compilers are now tracked as ranges,
+  rather than just points, making it easier to identify the subexpression
+  of interest within a complicated expression.
+  For example:
+<blockquote><pre>
+<b>test.cc:</b> In function <b>'int test(int, int, foo, int, int)'</b>:
+<b>test.cc:5:16:</b> <span class="boldred">error:</span> no match for <b>'operator*'</b> (operand types are <b>'int'</b> and <b>'foo'</b>)
+   return p + <span class="boldred">q * r</span> * s + t;
+              <span class="boldred">~~^~~</span>
+</pre></blockquote>
+In addition, there is now initial support for precise diagnostic locations
+within strings:
+<blockquote><pre>
+<b>format-strings.c:3:14:</b> <span class="boldmagenta">warning:</span> field width specifier <b>'*'</b> expects a matching <b>'int'</b> argument [<span class="boldmagenta">-Wformat=</span>]
+   printf("%*d");
+            <span class="boldmagenta">^</span>
+</pre></blockquote></li>
+    <li>Diagnostics can now contain "fix-it hints", which are displayed
+      in context underneath the relevant source code.  For example:
+      <!-- this is currently the only example in the tree; various others are pending  -->
+<blockquote><pre>
+<b>fixits.c:</b> In function <b>'bad_deref'</b>:
+<b>fixits.c:11:13:</b> <span class="boldred">error:</span> <b>'ptr'</b> is a pointer; did you mean to use <b>'->'</b>?
+   return ptr<span class="boldred">.</span>x;
+             <span class="boldred">^</span>
+             <span class="boldred">-&gt;</span>
+</pre></blockquote></li>
+    <li>The C and C++ compilers now offer suggestions for misspelled field names:
+<blockquote><pre>
+<b>spellcheck-fields.cc:52:13:</b> <span class="boldred">error:</span> <b>'struct s'</b> has no member named <b>'colour'</b>; did you mean <b>'color'</b>?
+   return ptr-&gt;<span class="boldred">colour</span>;
+               <span class="boldred">^~~~~~</span>
+</pre></blockquote></li>
+    <!-- also, pending patch to add fix-it hints to the above -->
+    <li>New command-line options have been added for the C and C++ compilers:
+      <ul>
+        <li><code>-Wshift-negative-value</code> warns about left shifting a
+          negative value.</li>
+        <li><code>-Wshift-overflow</code> warns about left shift overflows.
+          This warning is enabled by default.
+          <code>-Wshift-overflow=2</code> also warns about left-shifting 1 into
+          the sign bit.</li>
+        <li><code>-Wtautological-compare</code> warns if a self-comparison
+          always evaluates to true or false.  This warning is enabled by
+          <code>-Wall</code>.</li>
+        <li><code>-Wnull-dereference</code> warns if the compiler detects paths
+          that trigger erroneous or undefined behavior due to dereferencing a
+          null pointer. This option is only active when
+          <code>-fdelete-null-pointer-checks</code> is active, which is enabled
+          by optimizations in most targets. The precision of the warnings
+          depends on the optimization options used.</li>
+        <li><code>-Wduplicated-cond</code> warns about duplicated conditions
+	  in an if-else-if chain.</li>
+        <li><code>-Wmisleading-indentation</code> warns about places where the
+          indentation of the code gives a misleading idea of the block
+          structure of the code to a human reader.  For example, given
+          <a href="https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2014-1266">CVE-2014-1266</a>:
+<blockquote><pre>
+<b>sslKeyExchange.c:</b> In function <b>'SSLVerifySignedServerKeyExchange'</b>:
+<b>sslKeyExchange.c:629:3:</b> <span class="boldmagenta">warning:</span> this <b>'if'</b> clause does not guard... [<span class="boldmagenta">-Wmisleading-indentation</span>]
+    <span class="boldcyan">if</span> ((err = SSLHashSHA1.update(&amp;hashCtx, &amp;signedParams)) != 0)
+    <span class="boldcyan">^~</span>
+<b>sslKeyExchange.c:631:5:</b> <span class="boldcyan">note:</span> ...this statement, but the latter is misleadingly indented as if it is guarded by the <b>'if'</b>
+        <span class="boldmagenta">goto</span> fail;
+        <span class="boldmagenta">^~~~</span>
+</pre></blockquote>
+          This warning is enabled by <code>-Wall</code>.</li>
+      </ul>
+    </li>
+    <li>The C and C++ compilers now emit saner error messages if
+      merge-conflict markers are present in a source file.
+<blockquote><pre>
+<b>test.c:3:1:</b> <span class="boldred">error:</span> version control conflict marker in file
+ <span class="boldred">&lt;&lt;&lt;&lt;&lt;&lt;&lt;</span> HEAD
+ <span class="boldred">^~~~~~~</span>
+</pre></blockquote></li>
+  </ul>
+
+<h3 id="c">C</h3>
+  <ul>
+    <li>It is possible to disable warnings when an initialized field of
+	a structure or a union with side effects is being overridden when
+	using designated initializers via a new warning option
+	<code>-Woverride-init-side-effects</code>.</li>
+   <li>A new type attribute <code>scalar_storage_order</code> applying to
+       structures and unions has been introduced.  It specifies the storage
+       order (aka endianness) in memory of scalar fields in structures
+       or unions.</li>
+  </ul>
+
+<h3 id="cxx">C++</h3>
+  <ul>
+    <li>The default mode has been changed to <code>-std=gnu++14</code>.</li>
+    <li><a href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4377.pdf">C++
+	Concepts</a> are now supported when compiling with
+        <code>-fconcepts</code>.</li>
+    <li><code>-flifetime-dse</code> is more
+    aggressive in dead-store elimination in situations where
+    a memory store to a location precedes a constructor to the
+    memory location.</li>
+    <li>G++ now supports
+        <a href="https://gcc.gnu.org/projects/cxx-status.html#cxx1z.html">C++17</a>
+        fold expressions, <code>u8</code> character literals,
+        extended <code>static_assert</code>, and nested namespace definitions.</li>
+    <li>G++ now allows constant evaluation for all non-type template arguments.</li>
+    <li>G++ now supports C++ Transactional Memory when compiling with
+        <code>-fgnu-tm</code>. </li>
+  </ul>
+
+<h4 id="libstdcxx">Runtime Library (libstdc++)</h4>
+  <ul>
+    <li>Extensions to the C++ Library to support mathematical special
+        functions (ISO/IEC 29124:2010), thanks to Edward Smith-Rowland. </li>
+    <li>Experimental support for C++17, including the following
+      new features:
+      <ul>
+        <li><code>std::uncaught_exceptions</code> function (this is also
+            available for <tt>-std=gnu++NN</tt> modes); </li>
+        <li>new member functions <code>try_emplace</code> and
+            <code>insert_or_assign</code> for unique_key maps;</li>
+        <li>non-member functions <code>std::size</code>,
+            <code>std::empty</code>, and <code>std::data</code> for
+            accessing containers and arrays;</li>
+        <li><code>std::invoke</code>;</li>
+        <li><code>std::shared_mutex</code>;</li>
+        <li><code>std::void_t</code> and <code>std::bool_constant</code>
+            metaprogramming utilities. </li>
+      </ul>
+      Thanks to Ville Voutilainen for contributing many of the C++17 features.
+    </li>
+    <li>An experimental implementation of the File System TS.</li>
+    <li>Experimental support for most features of the second version of the
+        Library Fundamentals TS. This includes polymorphic memory resources
+        and array support in <code>shared_ptr</code>, thanks to Fan You.</li>
+    <li>Some assertions checked by Debug Mode can now also be enabled by
+        <code>_GLIBCXX_ASSERTIONS</code>. The subset of checks enabled by
+        the new macro have less run-time overhead than the full
+        <code>_GLIBCXX_DEBUG</code> checks and don't affect the library
+        ABI, so can be enabled per-translation unit.
+    </li>
+    <li>Timed mutex types are supported on more targets, including Darwin.
+    </li>
+    <li>Improved <code>std::locale</code> support for DragonFly and FreeBSD,
+        thanks to John Marino and Andreas Tobler.
+    </li>
+  </ul>
+
+
+<h3 id="fortran">Fortran</h3>
+  <ul>
+    <li>The <code>MATMUL</code> intrinsic is now inlined for straightforward
+      cases if front-end optimization is active.  The maximum size for
+      inlining can be set to <code>n</code> with the
+      <code>-finline-matmul-limit=n</code> option and turned off
+      with <code>-finline-matmul-llimit=0</code>.</li>
+    <li>The <code>-Wconversion-extra</code> option will warn about
+      <code>REAL</code> constants which have excess precision for
+      their kind.</li>
+    <li>The <code>-Winteger-division</code> option has been added, which
+      warns about divisions of integer constants which are truncated.
+      This option is included in <code>-Wall</code> by default.</li>
+  </ul>
+
+<!-- <h3 id="go">Go</h3> -->
+
+<!-- <h3 id="java">Java (GCJ)</h3> -->
+
+
+<!-- .................................................................. -->
+<h2 id="jit">libgccjit</h2>
+  <ul>
+    <li>The driver code is now run in-process within libgccjit,
+      providing a small speed-up of the compilation process.</li>
+    <li>The API has gained entrypoints for
+      <ul>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/performance.html">timing how long was spent in different parts of code</a>,</li>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/functions.html#gcc_jit_block_end_with_switch">creating switch statements</a>,</li>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/contexts.html#gcc_jit_context_set_bool_allow_unreachable_blocks">allowing unreachable basic blocks in a function</a>, and</li>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/contexts.html#gcc_jit_context_add_command_line_option">adding arbitrary command-line options to a compilation</a>.</li>
+      </ul>
+    </li>
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="targets">New Targets and Target Specific Improvements</h2>
+
+<h3 id="aarch64">AArch64</h3>
+   <ul>
+     <li>
+       The new command line options <code>-march=native</code>,
+       <code>-mcpu=native</code> and <code>-mtune=native</code> are now
+       available on native AArch64 GNU/Linux systems.  Specifying
+       these options will cause GCC to auto-detect the host CPU and
+       rewrite these options to the optimal setting for that system.
+       If GCC is unable to detect the host CPU these options have no effect.
+     </li>
+     <li>
+       <code>-fpic</code> is now supported by the AArch64 target when generating
+       code for the small code model (<code>-mcmodel=small</code>).  The size of
+       the global offset table (GOT) is limited to 28KiB under the LP64 SysV ABI
+       , and 15KiB under the ILP32 SysV ABI.
+     </li>
+     <li>
+       The AArch64 port now supports target attributes and pragmas.  Please
+       refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes">
+       documentation</a> for details of available attributes and
+       pragmas as well as usage instructions.
+     </li>
+     <li>
+       Link-time optimization across translation units with different
+       target-specific options is now supported.
+     </li>
+   </ul>
+
+<h3 id="arm">ARM</h3>
+   <ul>
+     <li>
+       Support for revisions of the ARM architecture prior to ARMv4t has
+       been deprecated and will be removed in a future GCC release.
+       The <code>-mcpu</code> and <code>-mtune</code> values that are
+       deprecated are:
+       <code>arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7,
+       arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c,
+       arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi, arm8, arm810,
+       strongarm, strongarm110, strongarm1100, strongarm1110, fa526,
+       fa626</code>.  The value
+       <code>arm7tdmi</code> is still supported.
+       The values of <code>-march</code> that are deprecated are:
+       <code>armv2,armv2a,armv3,armv3m,armv4</code>.
+     </li>
+     <li>
+       The ARM port now supports target attributes and pragmas.  Please
+       refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/ARM-Function-Attributes.html#ARM-Function-Attributes">
+       documentation</a> for details of available attributes and
+       pragmas as well as usage instructions.
+     </li>
+     <li>
+       Support has been added for the following processors
+       (GCC identifiers in parentheses): ARM Cortex-A32
+       (<code>cortex-a32</code>), ARM Cortex-A35 (<code>cortex-a35</code>).
+       The GCC identifiers can be used
+       as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
+       for example: <code>-mcpu=cortex-a32</code> or
+       <code>-mtune=cortex-a35</code>.
+     </li>
+   </ul>
+<!-- <h3 id="avr">AVR</h3> -->
+
+<h3 id="hsa">Heterogeneous Systems Architecture</h3>
+   <ul>
+     <li><p>GCC can now generate HSAIL (Heterogeneous System Architecture
+       Intermediate Language) for simple OpenMP device constructs if
+       configured with <code>--enable-offload-targets=hsa</code>.  A new
+       libgomp plugin then runs the HSA GPU kernels implementing these
+       constructs on HSA capable GPUs via a standard HSA run time.</p>
+       
+       <p>If the HSA compilation back end determines it cannot output HSAIL
+       for a particular input, it gives a warning by default.  These
+       warnings can be suppressed with <code>-Wno-hsa</code>.  To give a few
+       examples, the HSA back end does not implement compilation of code
+       using function pointers, automatic allocation of variable sized
+       arrays, functions with variadic arguments as well as a number of
+       other less common programming constructs.</p>
+
+       <p>When compilation for HSA is enabled, the compiler attempts to
+       compile composite OpenMP constructs</p>
+	 <blockquote><pre>
+#pragma omp target teams distribute parallel for</pre></blockquote>
+       <p>into parallel HSA GPU kernels.</p>
+     </li>
+   </ul>
+
+<h3 id="x86">IA-32/x86-64</h3>
+   <ul>
+     <li>GCC now supports the Intel CPU named Skylake with AVX-512 extensions
+      through <code>-march=skylake-avx512</code>. The switch enables the following
+      ISA extensions: AVX-512F, AVX512VL, AVX-512CD, AVX-512BW, AVX-512DQ.
+     </li>
+     <li>
+       Support for new AMD instructions <code>monitorx</code> and
+       <code>mwaitx</code> has been added. This includes new intrinsic
+       and built-in support. It is enabled through option <code>-mmwaitx</code>.
+       The instructions <code>monitorx</code> and <code>mwaitx</code>
+       implement the same functionality as the old <code>monitor</code>
+       and <code>mwait</code> instructions. In addition <code>mwaitx</code>
+       adds a configurable timer. The timer value is received as third
+       argument and stored in register <code>%ebx</code>.
+     </li>
+     <li>
+       x86-64 targets now allow stack realignment from a word-aligned stack
+       pointer using the command-line option <code>-mstackrealign</code> or
+       <code>__attribute__ ((force_align_arg_pointer))</code>.  This allows
+       functions compiled with a vector-aligned stack to be invoked from
+       objects that keep only word-alignment.
+     </li>
+     <li>
+       Support for address spaces <code>__seg_fs</code>, <code>__seg_gs</code>,
+       and <code>__seg_tls</code>.  These can be used to access data via the
+       <code>%fs</code> and <code>%gs</code> segments without having to
+       resort to inline assembly.
+       Please refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/Named-Address-Spaces.html#Named-Address-Spaces">
+       documentation</a> for usage instructions.
+     </li>
+     <li>
+      Support for AMD Zen (family 17h) processors is now available through
+      the <code>-march=znver1</code> and <code>-mtune=znver1</code> options.
+     </li>
+   </ul>
+<!-- <h3 id="mips">MIPS</h3> -->
+
+<h3 id="mep">MeP</h3>
+  <ul>
+    <li><p>Support for the MeP (mep-elf) architecture has been
+      deprecated and will be removed in a future GCC release.</p>
+    </li>
+  </ul>
+
+<h3 id="msp430">MSP430</h3>
+  <ul>
+    <li><p>The MSP430 compiler now has the ability to automatically distribute code
+      and data between low memory (addresses below 64K) and high memory.  This only
+      applies to parts that actually have both memory regions and only if the
+      linker script for the part has been specifically set up to support this
+      feature.</p>
+
+      <p>A new attribute of <code>either</code> can be applied to both functions
+      and data, and this tells the compiler to place the object into low memory
+      if there is room and into high memory otherwise.  Two other new attributes
+      - <code>lower</code> and <code>upper</code> - can be used to explicitly
+      state that an object should be placed in the specified memory region.  If
+      there is not enough left in that region the compilation will fail.</p>
+
+      <p>Two new command-line options - <code>-mcode-region=[lower|upper|either]</code>
+      and <code>-mdata-region=[lower|upper|either]</code> - can be used to tell
+      the compiler what to do with objects that do not have one of these new
+      attributes.</p></li>
+  </ul>
+
+<!-- <h3 id="nds32">NDS32</h3> -->
+
+<h3 id="powerpc">PowerPC / PowerPC64 / RS6000</h3>
+  <ul>
+    <li><p>PowerPC64 now supports IEEE 128-bit floating-point using the
+	__float128 data type.  In GCC 6, this is NOT enabled by default,
+	but you can enable it with -mfloat128.  The IEEE 128-bit
+	floating-point support requires the use of the VSX instruction
+	set.  IEEE 128-bit floating-point values are passed and returned
+	as a single vector value.  The software emulator for IEEE 128-bit
+	floating-point support is only built on PowerPC Linux systems
+	where the default cpu is at least power7.  On future ISA 3.0
+	systems (power9 and later), you will be able to use the
+	-mfloat128-hardware option to use the ISA 3.0 instructions
+	that support IEEE 128-bit floating-point.  An additional type
+	(__ibm128) has been added to refer to the IBM extended double
+	type that normally implements long double.  This will allow
+	for a future transition to implementing long double with IEEE
+	128-bit floating-point.</p></li>
+    <li><p>Basic support has been added for POWER9 hardware that will use the
+	recently published OpenPOWER ISA 3.0 instructions.  The following
+	new switches are available:</p>
+	<ul>
+	  <li><p><u>-mcpu=power9</u>:  Implement all of the ISA 3.0
+	      instructions supported by the compiler.</p></li>
+	  <li><p><u>-mtune=power9</u>:  In the future, apply tuning for
+	      POWER9 systems.  Currently, POWER8 tunings are used.</p></li>
+	  <li><p><u>-mmodulo</u>:  Generate code using the ISA 3.0
+	      integer instructions (modulus, count trailing zeros, array
+	      index support, integer multiply/add).</p></li>
+	  <li><p><u>-mpower9-fusion</u>:  Generate code to suitably fuse
+	      instruction sequences for a POWER9 system.</p></li>
+	  <li><p><u>-mpower9-dform</u>:  Generate code to use the new D-form
+	      (register +offset) memory instructions for the vector
+	      registers.</p></li>
+	  <li><p><u>-mpower9-vector</u>:  Generate code using the new ISA
+	      3.0 vector (VSX or Altivec) instructions.</p></li>
+	  <li><p><u>-mpower9-minmax</u>:  Reserved for future development.
+	  </p></li>
+	  <li><p><u>-mtoc-fusion</u>:  Keep TOC entries together to provide
+	      more fusion opportunities.</p></li>
+	</ul></li>
+    <li><p>New constraints have been added to support IEEE 128-bit
+	floating-point and ISA 3.0 instructions:</p>
+	<ul>
+	  <li><p><u>wb</u>:  Altivec register if -mpower9-dform is
+	      enabled.</p></li>
+	  <li><p><u>we</u>:  VSX register if -mpower9-vector is enabled
+	      for 64-bit code generation.</p></li>
+	  <li><p><u>wo</u>:  VSX register if -mpower9-vector is
+	      enabled.</p></li>
+	  <li><p><u>wp</u>:  Reserved for future use if long double
+	      is implemented with IEEE 128-bit floating-point instead
+	      of IBM extended double.</p></li>
+	  <li><p><u>wq</u>:  VSX register if -mfloat128 is enabled.</p></li>
+	  <li><p><u>wF</u>:  Memory operand suitable for POWER9 fusion
+	      load/store.</p></li>
+	  <li><p><u>wG</u>:  Memory operand suitable for TOC fusion memory
+	      references.</p></li>
+	  <li><p><u>wL</u>:  Integer constant identifying the element
+	      number mfvsrld accesses within a vector.</p></li>
+	</ul></li>
+    <li><p>Support has been added for __builtin_cpu_is () and
+	__builtin_cpu_supports (), allowing for very fast access to
+	AT_PLATFORM, AT_HWCAP, and AT_HWCAP2 values.  This requires
+	use of glibc 2.23 or later.</p></li>
+    <li><p>All hardware transactional memory builtins now correctly
+	behave as memory barriers.  Programmers can use #ifdef __TM_FENCE__
+	to determine whether their "old" compiler treats the builtins
+	as barriers.</p></li>
+    <li><p>Split-stack support has been added for gccgo on PowerPC64
+	for both big- and little-endian (but NOT for 32-bit).  The gold
+	linker from at least binutils 2.25.1 must be available in the PATH
+	when configuring and building gccgo to enable split stack.  (The
+	requirement for binutils 2.25.1 applies to PowerPC64 only.)  The
+	split-stack feature allows a small initial stack size to be
+	allocated for each goroutine, which increases as needed.</p></li>
+    <li><p>GCC on PowerPC now supports the standard lround function.</p></li>
+    <li><p>A new configuration option -<code>--with-advance-toolchain=at</code>
+    was added for PowerPC 64-bit GNU/Linux systems to use the header files, library
+    files, and the dynamic linker from a specific Advance Toolchain release
+    instead of the default versions that are provided by the GNU/Linux
+    distribution.  In general, this option is intended for the developers of
+    GCC, and it is not intended for general use.</p></li>
+    <li><p>The "q", "S", "T", and "t" asm-constraints have been
+    removed.</p></li>
+    <li><p>The "b", "B", "m", "M", and "W" format modifiers have
+    been removed.</p></li>
+  </ul>
+
+<h3 id="s390">S/390, System z, IBM z Systems</h3>
+  <ul>
+    <li>Support for the IBM z13 processor has been added.  When using
+      the <code>-march=z13</code> option, the compiler will generate
+      code making use of the new instructions and registers introduced
+      with the vector extension facility.  The <code>-mtune=z13</code>
+      option enables z13 specific instruction scheduling without
+      making use of new instructions.<br/>
+
+      Compiling code with <code>-march=z13</code> reduces the default
+      alignment of vector types bigger than 8 bytes to 8.  This is an
+      ABI change and care must be taken when linking modules compiled
+      with different arch levels which interchange variables
+      containing vector type values.  For newly compiled code the GNU
+      linker will emit a warning.</li>
+
+    <li>The <code>-mzvector</code> option enables a C/C++ language
+      extension.  This extension provides a new
+      keyword <code>vector</code> which can be used to define vector
+      type variables.  (Note: This is not available when
+      enforcing strict standard compliance
+      e.g. with <code>-std=c99</code>.  Either enable GNU extensions
+      with e.g. <code>-std=gnu99</code> or use
+      <code>__vector</code> instead of <code>vector</code>.)<br/>
+
+      Additionally a set of overloaded builtins is provided which is
+      partially compatible to the PowerPC Altivec builtins.  In order
+      to make use of these builtins the <code>vecintrin.h</code>
+      header file needs to be included.</li>
+
+    <li>The new command line options <code>-march=native</code>,
+      and <code>-mtune=native</code> are now available on native IBM
+      z Systems.  Specifying these options will cause GCC to
+      auto-detect the host CPU and rewrite these options to the
+      optimal setting for that system.  If GCC is unable to detect
+      the host CPU these options have no effect.</li>
+
+    <li>The IBM z Systems port now supports target attributes and
+      pragmas.  Please refer to the
+      <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/S_002f390-Function-Attributes.html#S_002f390-Function-Attributes">
+	documentation</a> for details of available attributes and
+      pragmas as well as usage instructions.
+    </li>
+
+    <li><code>-fsplit-stack</code> is now supported as part of the IBM
+      z Systems port.  This feature requires a recent gold linker to
+      be used.</li>
+
+    <li>Support for the <code>g5</code> and <code>g6
+      -march=/-mtune=</code> CPU level switches has been deprecated
+      and will be removed in a future GCC release. <code>-m31</code>
+      from now on defaults to <code>-march=z900</code> if not
+      specified otherwise.  <code>-march=native</code> on a g5/g6
+      machine will default to <code>-march=z900</code>.</li>
+  </ul>
+
+<!-- <h3 id="rx">RX</h3> -->
+
+<h3 id="sh">SH</h3>
+  <ul>
+    <li>Support for SH5 / SH64 has been declared obsolete and will be removed
+    in future releases.</li>
+
+    <li>Support for the FDPIC ABI has been added.  It can be enabled using the
+    new <code>-mfdpic</code> target option and <code>--enable-fdpic</code>
+    configure option.</li>
+  </ul>
+
+<h3 id="sparc">SPARC</h3>
+  <ul>
+    <li>An ABI bug has been fixed in 64-bit mode.  Unfortunately, this change
+    will break binary compatibility with earlier releases for code it affects,
+    but this should be pretty rare in practice.  The conditions are: a 16-byte
+    structure containing a <code>double</code> or a 8-byte vector in the second
+    half is passed to a subprogram in slot #15, for example as 16th parameter
+    if the first 15 ones have at most 8 bytes.  The <code>double</code> or
+    vector was wrongly passed in floating-point register <code>%d32</code>
+    in lieu of on the stack as per the SPARC calling conventions.</li>
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="os">Operating Systems</h2>
+
+<!-- <h3 id="dragonfly">DragonFly BSD</h3> -->
+
+<!-- <h3 id="freebsd">FreeBSD</h3> -->
+
+<h3 id="linux">Linux</h3>
+  <ul>
+    <li>Support for the <a href="http://www.musl-libc.org">musl C library</a>
+    was added for the AArch64, ARM, MicroBlaze, MIPS, MIPS64, PowerPC,
+    PowerPC64, SH, i386, x32 and x86_64 targets.  It can be selected using the
+    new <code>-mmusl</code> option in case musl is not the default libc.  GCC
+    defaults to musl libc if it is built with a target triplet matching the
+    <code>*-linux-musl*</code> pattern.</li>
+  </ul>
+
+<h3 id="rtems">RTEMS</h3>
+  <ul>
+    <li>The RTEMS thread model implementation changed.  Mutexes now
+    use self-contained objects defined in Newlib &lt;sys/lock.h&gt;
+    instead of Classic API semaphores.  The keys for thread specific data and
+    the <code>once</code> function are directly defined via &lt;pthread.h&gt;.
+    Self-contained condition variables are provided via Newlib
+    &lt;sys/lock.h&gt;.  The RTEMS thread model also supports C++11
+    threads.</li>
+
+    <li>OpenMP support now uses self-contained objects provided by Newlib
+    &lt;sys/lock.h&gt; and offers a significantly better performance compared
+    to the POSIX configuration of <code>libgomp</code>.  It is possible to
+    configure thread pools for each scheduler instance via the environment
+    variable <code>GOMP_RTEMS_THREAD_POOLS</code>.</li>
+  </ul>
+
+<h3 id="aix">AIX</h3>
+  <ul>
+    <li>DWARF debugging support for AIX 7.1 has been enabled as an optional
+    debugging format.  A more recent Technology Level (TL) and GCC built
+    with that level are required for full exploitation of DWARF debugging
+    capabilities.</li>
+  </ul>
+
+<h3 id="solaris">Solaris</h3>
+  <ul>
+    <li>Solaris 12 is now fully supported.  Minimal support had already
+      been present in GCC 5.3.</li>
+    <li>Solaris 12 provides a full set of startup files (<code>crt1.o</code>,
+      <code>crti.o</code>, <code>crtn.o</code>), which GCC now prefers over
+      its own ones.</li>
+    <li>Position independent executables (PIE) are now supported on
+      Solaris 12.</li>
+    <li>Constructor priority is now supported on Solaris 12 with the system
+      linker.</li>
+    <li><code>libvtv</code> has been ported to Solaris 11 and up.</li>
+  </ul>
+
+<h3 id="windows">Windows</h3>
+  <ul>
+   <li>The option <code>-mstackrealign</code> is now automatically activated
+   in 32-bit mode whenever the use of SSE instructions is requested.</li>
+  </ul>
+<!-- <h3 id="vxmils">VxWorks MILS</h3> -->
+
+
+<!-- .................................................................. -->
+<!-- <h2>Documentation improvements</h2> -->
+
+
+<!-- .................................................................. -->
+<h2>Other significant improvements</h2>
+
+  <ul>
+    <li>The <code>gcc</code> and <code>g++</code> driver programs will now
+      provide suggestions for misspelled command line options.
+<blockquote><pre>
+$ gcc -static-libfortran test.f95
+gcc: <span class="boldred">error:</span> unrecognized command line option <b>'-static-libfortran'</b>; did you mean <b>'-static-libgfortran'</b>?
+</pre></blockquote></li>
+    <li>The <code>--enable-default-pie</code> configure option enables
+	generation of PIE by default.</li>
+  </ul>
+
+
+
+
+<!-- ==================================================================== -->
+
+<div class="copyright">
+
+<address>For questions related to the use of GCC,
+please consult these web pages and the
+<a href="https://gcc.gnu.org/onlinedocs/">GCC manuals</a>. If that fails,
+the <a href="mailto:gcc-help@gcc.gnu.org">gcc-help@gcc.gnu.org</a>
+mailing list might help.
+Comments on these web pages and the development of GCC are welcome on our
+developer list at <a href="mailto:gcc@gcc.gnu.org">gcc@gcc.gnu.org</a>.
+All of <a href="https://gcc.gnu.org/lists.html">our lists</a>
+have public archives.
+</address>
+
+<p>Copyright (C)
+<a href="http://www.fsf.org">Free Software Foundation, Inc.</a>
+Verbatim copying and distribution of this entire article is
+permitted in any medium, provided this notice is preserved.</p>
+
+<p>These pages are
+<a href="https://gcc.gnu.org/about.html">maintained by the GCC team</a>.
+Last modified 2016-04-27<!-- IGNORE DIFF
+--><a href="http://validator.w3.org/check/referer">.</a></p>
+
+</div>
+
+<!-- ==================================================================== -->
+
+</body>
+     </html>
+  
+ 
--- gcc-6-6.3.0.orig/debian/README.Bugs.m4
+++ gcc-6-6.3.0/debian/README.Bugs.m4
@@ -0,0 +1,333 @@
+Reporting Bugs in the GNU Compiler Collection for DIST
+========================================================
+
+Before reporting a bug, please
+------------------------------
+
+- Check that the behaviour really is a bug. Have a look into some
+  ANSI standards document.
+
+- Check the list of well known bugs: http://gcc.gnu.org/bugs.html#known
+
+- Try to reproduce the bug with a current GCC development snapshot. You
+  usually can get a recent development snapshot from the gcc-snapshot
+ifelse(DIST,`Debian',`dnl
+  package in the unstable (or experimental) distribution.
+
+  See: http://packages.debian.org/gcc-snapshot
+', DIST, `Ubuntu',`dnl
+  package in the current development distribution.
+
+  See: http://archive.ubuntu.com/ubuntu/pool/universe/g/gcc-snapshot/
+')dnl
+
+- Try to find out if the bug is a regression (an older GCC version does
+  not show the bug).
+
+- Check if the bug is already reported in the bug tracking systems.
+
+ifelse(DIST,`Debian',`dnl
+    Debian:   http://bugs.debian.org/debian-gcc@lists.debian.org
+', DIST, `Ubuntu',`dnl
+    Ubuntu:   https://bugs.launchpad.net/~ubuntu-toolchain/+packagebugs
+    Debian:   http://bugs.debian.org/debian-gcc@lists.debian.org
+')dnl
+    Upstream: http://gcc.gnu.org/bugzilla/
+
+
+Where to report a bug
+---------------------
+
+ifelse(DIST,`Debian',`dnl
+Please report bugs found in the packaging of GCC to the Debian bug tracking
+system. See http://www.debian.org/Bugs/ for instructions (or use the
+reportbug script).
+', DIST, `Ubuntu',`dnl
+Please report bugs found in the packaging of GCC to Launchpad. See below
+how issues should be reported.
+')dnl
+
+DIST's current policy is to closely follow the upstream development and
+only apply a minimal set of patches (which are summarized in the README.Debian
+document).
+
+ifelse(DIST,`Debian',`dnl
+If you think you have found an upstream bug, you did check the section
+above ("Before reporting a bug") and are able to provide a complete bug
+report (see below "How to report a bug"), then you may help the Debian
+GCC package maintainers, if you report the bug upstream and then submit
+a bug report to the Debian BTS and tell us the upstream report number.
+This way you are able to follow the upstream bug handling as well. If in
+doubt, report the bug to the Debian BTS (but read "How to report a bug"
+below).
+', DIST, `Ubuntu',`dnl
+If you think you have found an upstream bug, you did check the section
+above ("Before reporting a bug") and are able to provide a complete bug
+report (see below "How to report a bug"), then you may help the Ubuntu
+GCC package maintainers, if you report the bug upstream and then submit
+a bug report to Launchpad and tell us the upstream report number.
+This way you are able to follow the upstream bug handling as well. If in
+doubt, report the bug to Launchpad (but read "How to report a bug" below).
+
+Report the issue to https://bugs.launchpad.net/ubuntu/+source/SRCNAME.
+')dnl
+
+
+How to report a bug
+-------------------
+
+There are complete instructions in the gcc info manual (found in the
+gcc-doc package), section Bugs.
+
+The manual can be read using `M-x info' in Emacs, or if the GNU info
+program is installed on your system by `info --node "(gcc)Bugs"'. Or see
+the file BUGS included with the gcc source code.
+
+Online bug reporting instructions can be found at
+
+	http://gcc.gnu.org/bugs.html
+
+[Some paragraphs taken from the above URL]
+
+The main purpose of a bug report is to enable us to fix the bug. The
+most important prerequisite for this is that the report must be
+complete and self-contained, which we explain in detail below.
+
+Before you report a bug, please check the list of well-known bugs and,
+if possible in any way, try a current development snapshot.
+
+Summarized bug reporting instructions
+-------------------------------------
+
+What we need
+
+Please include in your bug report all of the following items, the
+first three of which can be obtained from the output of gcc -v:
+
+    * the exact version of GCC;
+    * the system type;
+    * the options given when GCC was configured/built;
+    * the complete command line that triggers the bug;
+    * the compiler output (error messages, warnings, etc.); and
+    * the preprocessed file (*.i*) that triggers the bug, generated by
+      adding -save-temps to the complete compilation command, or, in
+      the case of a bug report for the GNAT front end, a complete set
+      of source files (see below).
+
+What we do not want
+
+    * A source file that #includes header files that are left out
+      of the bug report (see above)
+    * That source file and a collection of header files.
+    * An attached archive (tar, zip, shar, whatever) containing all
+      (or some :-) of the above.
+    * A code snippet that won't cause the compiler to produce the
+      exact output mentioned in the bug report (e.g., a snippet with
+      just a few lines around the one that apparently triggers the
+      bug, with some pieces replaced with ellipses or comments for
+      extra obfuscation :-)
+    * The location (URL) of the package that failed to build (we won't
+      download it, anyway, since you've already given us what we need
+      to duplicate the bug, haven't you? :-)
+    * An error that occurs only some of the times a certain file is
+      compiled, such that retrying a sufficient number of times
+      results in a successful compilation; this is a symptom of a
+      hardware problem, not of a compiler bug (sorry)
+    * E-mail messages that complement previous, incomplete bug
+      reports. Post a new, self-contained, full bug report instead, if
+      possible as a follow-up to the original bug report
+    * Assembly files (*.s) produced by the compiler, or any binary files,
+      such as object files, executables, core files, or precompiled
+      header files
+    * Duplicate bug reports, or reports of bugs already fixed in the
+      development tree, especially those that have already been
+      reported as fixed last week :-)
+    * Bugs in the assembler, the linker or the C library. These are
+      separate projects, with separate mailing lists and different bug
+      reporting procedures
+    * Bugs in releases or snapshots of GCC not issued by the GNU
+      Project. Report them to whoever provided you with the release
+    * Questions about the correctness or the expected behavior of
+      certain constructs that are not GCC extensions. Ask them in
+      forums dedicated to the discussion of the programming language
+
+
+Known Bugs and Non-Bugs
+-----------------------
+
+[Please see /usr/share/doc/gcc/FAQ or http://gcc.gnu.org/faq.html first]
+
+
+C++ exceptions don't work with C libraries
+------------------------------------------
+
+[Taken from the closed bug report #22769] C++ exceptions don't work
+with C libraries, if the C code wasn't designed to be thrown through.
+A solution could be to translate all C libraries with -fexceptions.
+Mostly trying to throw an exception in a callback function (qsort,
+Tcl command callbacks, etc ...). Example:
+
+    #include <stdio.h>
+    #include <tcl.h>
+
+    class A {};
+
+    static
+    int SortCondition(void const*, void const*)
+    {
+        printf("throwing 'sortcondition' exception\n");
+        throw A();
+    }
+
+    int main(int argc, char *argv[])
+    {
+        int list[2];
+
+        try {
+            SortCondition(NULL,NULL);
+        } catch (A) {
+            printf("caught test-sortcondition exception\n");
+        }
+        try {
+            qsort(&list, sizeof(list)/sizeof(list[0]),sizeof(list[0]),
+                 &SortCondition);
+        } catch (A) {
+            printf("caught real-sortcondition exception\n");
+        }
+        return 0;
+}
+
+Andrew Macleod <amacleod@cygnus.com> responded:
+
+When compiled with the table driven exception handling, exception can only
+be thrown through functions which have been compiled with the table driven EH.
+If a function isn't compiled that way, then we do not have the frame
+unwinding information required to restore the registers when unwinding.
+
+I believe the setjmp/longjmp mechanism will throw through things like this, 
+but its produces much messier code.  (-fsjlj-exceptions)
+
+The C compiler does support exceptions, you just have to turn them on
+with -fexceptions.
+
+Your main options are to:
+  a) Don't use callbacks, or at least don't throw through them.
+  b) Get the source and compile the library with -fexceptions (You have to
+     explicitly turn on exceptions in the C compiler)
+  c) always use -fsjlj-exceptions (boo, bad choice :-)
+
+
+g++: "undefined reference" to static const array in class
+---------------------------------------------------------
+
+The following code compiles under GNU C++ 2.7.2 with correct results,
+but produces the same linker error with GNU C++ 2.95.2.
+Alexandre Oliva <oliva@lsd.ic.unicamp.br> responded:
+
+All of them are correct.  A static data member *must* be defined
+outside the class body even if it is initialized within the class
+body, but no diagnostic is required if the definition is missing.  It
+turns out that some releases do emit references to the missing symbol,
+while others optimize it away.
+
+#include <iostream>
+
+class Test
+{
+  public:
+    Test(const char *q);
+  protected:
+    static const unsigned char  Jam_signature[4]   = "JAM";
+};
+
+Test::Test(const char *q)
+{
+  if (memcmp(q, Jam_signature, sizeof(Jam_signature)) != 0)
+  cerr << "Hello world!\n";
+}
+
+int main(void)
+{
+  Test::Test("JAM");
+  return 0;
+}
+
+g++: g++ causes passing non const ptr to ptr to a func with const arg
+     to cause an error (not a bug)
+---------------------------------------------------------------------
+
+Example:
+
+#include <stdio.h>
+void test(const char **b){
+        printf ("%s\n",*b);
+}
+int main(void){
+        char *test1="aoeu";
+        test(&test1);
+}
+
+make const
+g++     const.cc   -o const
+const.cc: In function `int main()':
+const.cc:7: passing `char **' as argument 1 of `test(const char **)' adds cv-quals without intervening `const'
+make: *** [const] Error 1
+
+Answer from "Martin v. Loewis" <martin@loewis.home.cs.tu-berlin.de>:
+
+> ok... maybe I missed something.. I haven't really kept up with the latest in
+> C++ news.  But I've never heard anything even remotly close to passing a non
+> const var into a const arg being an error before.
+
+Thanks for your bug report. This is a not a bug in the compiler, but
+in your code. The standard, in 4.4/4, puts it that way
+
+# A conversion can add cv-qualifiers at levels other than the first in
+# multi-level pointers, subject to the following rules:
+# Two pointer types T1 and T2 are similar if there exists a type T and
+# integer n > 0 such that:
+#   T1 is cv(1,0) pointer to cv(1,1) pointer to ... cv(1,n-1)
+#   pointer to cv(1,n) T
+# and
+#   T2 is cv(2,0) pointer to cv(2,1) pointer to ... cv(2,n-1)
+#   pointer to cv(2,n) T
+# where each cv(i,j) is const, volatile, const volatile, or
+# nothing. The n-tuple of cv-qualifiers after the first in a pointer
+# type, e.g., cv(1,1) , cv(1,2) , ... , cv(1,n) in the pointer type
+# T1, is called the cv-qualification signature of the pointer type. An
+# expression of type T1 can be converted to type T2 if and only if the
+# following conditions are satisfied:
+#  - the pointer types are similar.
+#  - for every j > 0, if const is in cv(1,j) then const is in cv(2,j) ,
+#    and similarly for volatile.
+#  - if the cv(1,j) and cv(2,j) are different, then const is in every
+#    cv(2,k) for 0 < k < j.
+
+It is the last rule that your code violates. The standard gives then
+the following example as a rationale:
+
+# [Note: if a program could assign a pointer of type T** to a pointer
+# of type const T** (that is, if line //1 below was allowed), a
+# program could inadvertently modify a const object (as it is done on
+# line //2). For example,
+# int main() { 
+#   const char c = 'c'; 
+#   char* pc; 
+#   const char** pcc = &pc; //1: not allowed 
+#   *pcc = &c; 
+#   *pc = 'C'; //2: modifies a const object 
+# }
+# - end note]
+
+If you question this line of reasoning, please discuss it in one of
+the public C++ fora first, eg. comp.lang.c++.moderated, or
+comp.std.c++.
+
+
+cpp removes blank lines
+-----------------------
+
+With the new cpp, you need to add -traditional to the "cpp -P" args, else 
+blank lines get removed.
+
+[EDIT ME: scan Debian bug reports and write some nice summaries ...]
--- gcc-6-6.3.0.orig/debian/README.C++
+++ gcc-6-6.3.0/debian/README.C++
@@ -0,0 +1,35 @@
+libstdc++ is an implementation of the Standard C++ Library, including the
+Standard Template Library (i.e. as specified by ANSI and ISO).
+
+Some notes on porting applications from libstdc++-2.90 (or earlier versions)    
+to libstdc++-v3 can be found in the libstdc++6-4.3-doc package. After the
+installation of the package, look at:
+
+  file:///usr/share/doc/gcc-4.3-base/libstdc++/html/17_intro/porting-howto.html
+
+On Debian GNU/Linux you find additional documentation in the
+libstdc++6-4.3-doc package. After installing these packages,
+point your browser to
+
+  file:///usr/share/doc/libstdc++6-4.3-doc/libstdc++/html/index.html
+
+Other documentation can be found:
+
+    http://www.sgi.com/tech/stl/
+
+with a good, recent, book on C++.
+
+A great deal of useful C++ documentation can be found in the C++ FAQ-Lite,
+maintained by Marshall Cline <cline@parashift.com>.  It can be found at the
+mirror sites linked from the following URL (this was last updated on
+2010/09/11):
+
+     http://www.parashift.com/c++-faq/
+
+or use some search engin site to find it, e.g.:
+
+     http://www.google.com/search?q=c%2B%2B+faq+lite
+
+Be careful not to use outdated mirors.
+
+Please send updates to this list as bug report for the g++ package.
--- gcc-6-6.3.0.orig/debian/README.Debian
+++ gcc-6-6.3.0/debian/README.Debian
@@ -0,0 +1,45 @@
+               The Debian GNU Compiler Collection setup
+               ========================================
+
+Please see the README.Debian in /usr/share/doc/gcc, contained in the
+gcc package for a description of the setup of the different compiler
+versions.
+
+For general discussion about the Debian toolchain (GCC, glibc, binutils)
+please use the mailing list debian-toolchain@lists.debian.org; for GCC
+specific things, please use debian-gcc@lists.debian.org.  When in doubt
+use the debian-toolchain ML.
+
+
+Maintainers of these packages
+-----------------------------
+
+Matthias Klose <doko@debian.org>
+Ludovic Brenta <ludovic@ludovic-brenta.org>	(gnat)
+Iain Buclaw <ibuclaw@ubuntu.com>		(gdc)
+Aurelien Jarno <aurel32@debian.org>		(mips*-linux)
+Aurelien Jarno <aurel32@debian.org>		(s390X*-linux)
+
+The following ports lack maintenance in Debian: powerpc, ppc64,
+sparc, sparc64 (unmentioned ports are usually handled by the Debian
+porters).
+
+Former and/or inactive maintainers of these packages
+----------------------------------------------------
+
+Falk Hueffner <falk@debian.org>			(alpha-linux)
+Ray Dassen <jdassen@debian.org>
+Jeff Bailey <jbailey@nisa.net>			(hurd-i386)
+Joel Baker <fenton@debian.org>			(netbsd-i386)
+Randolph Chung <tausq@debian.org>		(ia64-linux)
+Philip Blundell <pb@debian.org>			(arm-linux)
+Ben Collins <bcollins@debian.org>		(sparc-linux)
+Dan Jacobowitz <dan@debian.org>			(powerpc-linux)
+Thiemo Seufer <ths@networkno.de>		(mips*-linux)
+Matt Taggart <taggart@carmen.fc.hp.com>		(hppa-linux)
+Gerhard Tonn <GerhardTonn@swol.de>		(s390-linux)
+Roman Zippel <zippel@linux-m68k.org>		(m68k-linux)
+Arthur Loiret <arthur.loiret@gmail.com>		(gdc)
+
+===============================================================================
+
--- gcc-6-6.3.0.orig/debian/README.cross
+++ gcc-6-6.3.0/debian/README.cross
@@ -0,0 +1,144 @@
+Building cross-compiler Debian packages
+---------------------------------------
+
+It is possible to build C and C++ cross compilers and support libraries
+from gcc-4.0 source package. This document describes how to do so.
+Cross-compiler build support is not perfect yet, please send fixes
+and improvements to debian-gcc@lists.debian.org and 
+debian-embedded@lists.debian.org
+
+Before you start, you should probably check available pre-built
+cross-toolchain debs. Available at http://www.emdebian.org
+
+Old patches could be reached at
+  http://zigzag.lvk.cs.msu.su/~nikita/debian/
+  
+If they are no longer there, you may check EmDebian web site at
+  http://www.emdebian.org/
+or ask debian-embedded@lists.debian.org for newer location.
+
+Please check http://bugs.debian.org/391445 if you are about building
+gcc-4.3 or above.
+
+Most of them has been merged with gcc debian sources.
+
+0. What's wrong with toolchain-source approach
+
+Package toolchain-source contains sources for binutils and gcc, as well as
+some support scripts to build cross-compiler packages. They seem to work.
+
+However, there is one fundamental problem with this approach.
+Gcc package is actively maintained and frequently updated. These updates
+do contain bug fixes and improvements, especially for non-x86 architectures.
+Cross-compilers built using toolchain-source will not get those fixes unless
+toolchain-source package is updated after each binutils and gcc update.
+The later is not hapenning in real life. For example, toolchain-source
+was upgraded from gcc-3.2 to gcc-3.3 half a year later than gcc-3.3 became
+Debian default compiler.
+
+Keeping toolchain-source package up-to-date requires lots of work, and seems
+to be a waste of time. It is much better to build cross-compilers directly
+from gcc source package.
+
+
+1. What is needed to build a cross-compiler from gcc-4.3 source
+
+1.1. dpkg-cross package
+
+Dpkg-cross package contains several tools to manage cross-compile environment.
+
+It can convert native debian library and lib-dev packages for the target
+architecture to binary-all packages that keep libraries and headers under
+/usr/$(TARGET)/.
+
+Also it contains helper tools for cross-compiling debian packages. Some of
+these tools are used while building libgcc1 and libstdc++ library packages.
+The resulting library packages follow the same convensions as library packages
+converted by dpkg-cross.
+
+Currently, at least version 1.18 of dpkg-cross is needed for cross-gcc
+package build. Version 1.32 of dpkg-cross is needed in order to build gcc-4.3.
+
+1.2. cross-binutils for the target
+
+You need cross-binutils for your target to build cross-compiler.
+Binutils-multiarch package will not work because it does not provide cross-
+assemblers.
+
+If you don't want to use pre-built cross-binutils packages, you may build
+your own from binutils debian source package, using patches posted to
+bug #231707. Please use the latest of patch versions available there.
+
+Alternatively, you may use toolchain-source package to build cross-binutils
+(but in this case you will probably also want to use toolchain-source
+to build cross-compiler itself). However, multilib'ed cross-compilers may
+not build or work with these binutils.
+
+1.3. libc for target
+
+You also need libc library and development packages for the target
+architecture installed.
+
+To get those, download linux-kernel-headers, libc6, and libc6-dev binary
+debs for your target, convert those using dpkg-cross -b, and install
+resulting -arch-cross debs. Consult dpkg-cross manual page for more
+information.
+
+Building with/for alternative libc's is not supported yet (but this is in
+TODO).
+
+Note that if you plan to use your cross-toolchain to develop kernel drivers
+or similar low-level things, you will probably also need kernel headers
+for the exact kernel version that your target hardware uses.
+
+
+2. Building cross-compiler packages
+
+Get gcc-4.3 source package.
+
+Unpack it using dpkg-source -x, and cd to the package directory.
+
+Set GCC_TARGET environment variable to the target architectire name. Note
+that currently you should use debian architecture name (i.e 'powerpc' or 'arm'),
+not GNU system type (i.e. 'powerpc-linux' or 'arm-linux'). Setting GCC_TARGET
+to GNU system type will cause cross-compiler build to fail.
+
+Instead of setting GCC_TARGET, target architecture name may be put into
+debian/target file. If both GCC_TARGET is defined and debian/target file
+exists, GCC_TARGET is used.
+
+Run debian/rules control. This will change debian/control file,
+adjusting build-depends.  By default, the packages will not depend on the
+system -base package. A variable DEB_CROSS_INDEPENDENT has been merged with DEB_CROSS variable.
+
+You can then build with either
+
+$ GCC_TARGET=[arch] dpkg-buildpackage -rfakeroot
+
+3. Using crosshurd
+
+Jeff Bailey <jbailey@raspberryginger.com> suggests alternate way to setup
+environment to build cross-compiler, using 'crosshurd' package. 
+Crosshurd is like debootstrap but cross-arch, and works on the Hurd,
+Linux and FreeBSD.  (The name is historical).
+
+If you setup your environment with crosshurd, you will need to fix symlinks
+in lib and usr/lib to be relative instead of absolute. For example:
+
+lrwxrwxrwx    1 root     root           20 2004-05-06 23:02 libcom_err.so -> /lib/libcom_err.so.2
+
+Needs to be changed to:
+
+lrwxrwxrwx    1 root     root           20 2004-05-06 23:02 libcom_err.so -> ../../lib/libcom_err.so.2
+
+Also, if you choose this method, set the environment variable 'with_sysroot'
+to point to the ABSOLUTE PATH where the crosshurd was done.
+
+Note however that build-depends of cross-gcc and dependencies in generated
+libgcc1 and libstdc++ packages assume that you use dpkg-cross to set up
+your environment, and may be wrong or incomplete if you use alternate methods.
+But probably you don't care.
+
+--
+Nikita V. Youshchenko <yoush@debian.org> - Jun 2004
+Hector Oron Martinez  <hector.oron@gmail.com> - Oct 2006
--- gcc-6-6.3.0.orig/debian/README.gnat
+++ gcc-6-6.3.0/debian/README.gnat
@@ -0,0 +1,35 @@
+If you want to develop Ada programs and libraries on Debian, please
+read the Debian Policy for Ada:
+
+http://people.debian.org/~lbrenta/debian-ada-policy.html
+
+The default Ada compiler is and always will be the package `gnat'.
+Debian contains many programs and libraries compiled with it, which
+are all ABI-compatible.
+
+Starting with gnat-4.2, Debian provides both zero-cost and
+setjump/longjump versions of the run-time library.  The zero-cost
+exception handling mechanism is the default as it provides the best
+performance.  The setjump/longjump exception handling mechanism is new
+and only provided as a static library.  It is necessary to use this
+exception handling mechanism in distributed (annex E) programs.  If
+you wish to use the new sjlj library:
+
+1) call gnatmake with --RTS=sjlj
+2) call gnatbind with -static
+
+Do NOT link your programs with libgnat-4.2.so, because it uses the ZCX
+mechanism.
+
+
+This package also includes small tools covering specific needs.
+
+* When linking objects compiled from both Ada and C sources, you need
+  to use compatible versions of the Ada and C compilers. The
+  /usr/bin/gnatgcc symbolic link targets a version of the C compiler
+  compatible with the default Ada compiler, and may differ from the
+  default C compiler /usr/bin/gcc.
+
+* When packaging Ada sources for Debian, you may want to read the
+  /usr/share/ada/debian_packaging.mk Makefile snippet and/or include
+  it from debian/rules in order to set sensible defaults.
--- gcc-6-6.3.0.orig/debian/README.libstdc++-baseline.in
+++ gcc-6-6.3.0/debian/README.libstdc++-baseline.in
@@ -0,0 +1,2 @@
+The libstdc++ baseline file is a list of symbols exported by the
+libstdc++ library.
--- gcc-6-6.3.0.orig/debian/README.maintainers
+++ gcc-6-6.3.0/debian/README.maintainers
@@ -0,0 +1,196 @@
+-*- Outline -*-
+
+Read this file if you are a Debian Developer or would like to become
+one, or if you would like to create your own binary packages of GCC.
+
+* Overview
+
+From the GCC sources, Debian currently builds 3 source packages and
+almost 100 binary packages, using a single set of build scripts.  The
+3 source packages are:
+
+gcc-x.y: C, C++, Fortran, Objective-C and Objective-C++, plus many
+         common libraries like libssp and libgcc.
+gcj-x.y: Java.
+gnat-x.y: Ada.
+
+The way we do this is quite peculiar, so listen up :)
+
+When we build from the gcc-x.y source package, we produce, among many
+others, a gcc-x.y-source binary package that contains the pristine
+upstream tarball and some Debian-specific patches.  Any user can then
+install this package on their Debian system, and will have the full
+souces in /usr/src/gcc-x.y/gcc-<timestamp>.tar.bz2, along with the
+Makefile snippets that unpack and patch them.
+
+The intended use for this package is twofold: (a) allow users to build
+their own cross-compilers, and (b) build the other two packages,
+gcj-x.y and gnat-x.y.
+
+- gcc-x.y requires only a C compiler to build and produces C, C++,
+  Fortran, Go and Objective-C compilers and libraries. It also
+  produces the binary package gcc-x.y-source containing all the
+  sources and patches in a tarball.
+
+- gcj-x.y build-depends on gcc-x.y-source and C++ and Java compilers.
+  Its .orig.tar.bz2 file only contains an empty directory; the real
+  sources from which it builds the binary packages are in
+  gcc-x.y-source.
+
+- gnat-x.y build-depends on gcc-x.y-source and an Ada compiler.  It
+  does not even have an .orig.tar.bz2 package; it is a Debian native
+  package.
+
+The benefits of this split are many:
+
+- bootstrapping a subset of languages is much faster than
+  bootstrapping all languages and libraries (which can take a full
+  week on slow architectures like mips or arm)
+
+- the language maintainers don't have to wait for each other
+
+- for new ports, the absence of a port of, say, gnat-x.y does not
+  block the porting of gcc-x.y.
+
+gcc-x.y-source is also intended for interested users to build
+cross-compiler packages.  Debian cannot provide all possible
+cross-compiler packages (i.e. all possible host, target, language and
+library combinations), so instead tries to facilitate building them.
+
+* The build sequence
+
+As for all other Debian packages, you build GCC by calling
+debian/rules.
+
+The first thing debian/rules does it to look at the top-most entry in
+debian/changelog: this tells it which source package it is building.
+For example, if the first entry in debian/changelog reads:
+
+gcj-4.3 (4.3-20070609-1) unstable; urgency=low
+
+  * Upload as gcj-4.3.
+
+ -- Ludovic Brenta <lbrenta@debian.org>  Tue, 26 Jun 2007 00:26:42 +0200
+
+then, debian/rules will build only the Java binary packages.
+
+The second step is to build debian/control from debian/control.m4 and
+a complex set of rules specified in debian/rules.conf.  The resulting
+control file contains only the binary packages to be built.
+
+The third step is to select which patches to apply (this is done in
+debian/rules.defs), and then to apply the selected patches (see
+debian/rules.patch).  The result of this step is a generated
+debian/patches/series file for use by quilt.
+
+The fourth step is to unpack the GCC source tarball.  This tarball is
+either in the build directory (when building gcc-x.y), or in
+/usr/src/gcc-x.y/gcc-x.y.z.tar.xz (when building the other source
+packages).
+
+The fifth step is to apply all patches to the unpacked sources with
+quilt.
+
+The sixth step is to create a "build" directory, cd into it, call
+../src/configure, and bootstrap the compiler and libraries selected.
+This is in debian/rules2.
+
+The seventh step is to call "make install" in the build directory:
+this installs the compiler and libraries into debian/tmp
+(i.e. debian/tmp/usr/bin/gcc, etc.)
+
+The eighth step is to run the GCC test suite.  This actually takes at
+least as much time as bootstrapping, and you can disable it by setting
+WITHOUT_CHECK to "yes" in the environment.
+
+The ninth step is to build the binary packages, i.e. the .debs.  This
+is done by a set of language- and architecture-dependent Makefile
+snippets in the debian/rules.d/ directory, which move files from the
+debian/tmp tree to the debian/<package> trees.
+
+* Making your own packages
+
+In this example, we will build our own gnat-x.y package.
+
+1) Install gcc-x.y-source, which contains the real sources:
+
+# aptitude install gcc-x.y-source
+
+2) Create a build directory:
+
+$ mkdir gnat-x.y-x.y.z; cd gnat-x.y-x.y.z
+
+3) Checkout from Subversion:
+
+$ svn checkout svn://svn.debian.org/gcccvs/branches/sid/gcc-x.y/debian
+
+4) Edit the debian/changelog file, adding a new entry at the top that
+   starts with "gnat-x.y".
+
+5) Generate the debian/control file, adjusted for gnat:
+
+$ debian/rules control
+
+8) Build:
+
+$ dpkg-buildpackage
+
+* Hints
+
+You need a powerful machine to build GCC.  The larger, the better.
+The build scripts take advantage of as many CPU threads as are
+available in your box (for example: 2 threads on a dual-core amd64; 4
+threads on a dual-core POWER5; 32 threads on an 8-core UltraSPARC T1,
+etc.).
+
+If you have 2 GB or more of physical RAM, you can achieve maximum
+performance by building in a tmpfs, like this:
+
+1) as root, create the new tmpfs:
+
+# mount -t tmpfs -o size=1280m none /home/lbrenta/src/debian/ram
+
+By default, the tmpfs will be limited to half your physical RAM.  The
+beauty of it is that it only consumes as much physical RAM as
+necessary to hold the files in it; deleting files frees up RAM.
+
+2) As your regular user, create the working directory in the tmpfs
+
+$ cp --archive ~/src/debian/gcc-x.y-x.y.z ~/src/debian/ram
+
+3) Build in there.  On my dual-core, 2 GHz amd64, it takes 34 minutes
+   to build gnat, and the tmpfs takes 992 MiB of physical RAM but
+   exceeds 1 GiB during the build.
+
+Note that the build process uses a lot of temporary files.  Your $TEMP
+directory should therefore also be in a ram disk.  You can achieve
+that either by mounting it as tmpfs, or by setting TEMP to point to
+~/src/debian/ram.
+
+Also note that each thread in your processor(s) will run a compiler in
+it and use up RAM.  Therefore your physical memory should be:
+
+Physical_RAM >= 1.2 + 0.4 * Threads (in GiB)
+
+(this is an estimate; your mileage may vary).  If you have less
+physical RAM than recommended, reduce the number of threads allocated
+to the build process, or do not use a tmpfs to build.
+
+* Patching GCC
+
+Debian applies a large number of patches to GCC as part of the build
+process.  It uses quilt but the necessary debian/patches/series is not
+part of the packaging scripts; instead, "debian/rules patch" generates
+this file by looking at debian/control (which is itself generated!),
+debian/changelog and other files.  Then it applies all the patches.
+At this point, you can use quilt as usual:
+
+$ cd ~/src/debian/gcc-x.y
+$ export QUILT_PATCHES=$PWD/debian/patches
+$ quilt series
+
+If you add new patches, remember to add them to the version control
+system too.
+
+-- 
+Ludovic Brenta, 2012-04-02.
--- gcc-6-6.3.0.orig/debian/README.snapshot
+++ gcc-6-6.3.0/debian/README.snapshot
@@ -0,0 +1,36 @@
+Debian gcc-snapshot package
+===========================
+
+This package contains  a recent development SNAPSHOT of all files
+contained in the GNU Compiler Collection (GCC).
+
+DO NOT USE THIS SNAPSHOT FOR BUILDING DEBIAN PACKAGES!
+
+This package will NEVER hit the testing distribution. It's used for
+tracking gcc bugs submitted to the Debian BTS in recent development
+versions of gcc.
+
+To use this snapshot, you should set the following environment variables:
+
+	LD_LIBRARY_PATH=/usr/lib/gcc-snapshot/lib:$LD_LIBRARY_PATH
+	PATH=/usr/lib/gcc-snapshot/bin:$PATH
+
+You might also like to use a shell script to wrap up this 
+funcationality, e.g. 
+ 
+place in /usr/local/bin/gcc-snapshot and chmod +x it 
+ 
+----------- snip ----------
+#! /bin/sh
+LD_LIBRARY_PATH=/usr/lib/gcc-snapshot/lib:$LD_LIBRARY_PATH
+PATH=/usr/lib/gcc-snapshot/bin:$PATH
+gcc "$@"
+----------- snip ----------
+
+Make the same for g++, g77, gij, gcj, cpp, ...
+ 
+Don't forget the quotes around the $@ or gcc will not parse it's 
+command line correctly! 
+
+Unset these variables before building Debian packages destined for an
+upload to ftp-master.debian.org.
--- gcc-6-6.3.0.orig/debian/README.source
+++ gcc-6-6.3.0/debian/README.source
@@ -0,0 +1,16 @@
+Patches applied to the Debian version of GCC
+--------------------------------------------
+
+Debian specific patches can be found in the debian/patches directory.
+Quilt is used as the patch system.  See /usr/share/doc/quilt/README.source
+for details about quilt.
+
+Patches are applied by calling `debian/rules patch'.  The `series'
+file is constructed on the fly based on the files found in the to
+debian/rules.patch "debian_patches" variable, configure scripts are
+regenerated in the `patch' target. The gcc source is unpacked under
+src/ this needs to be reflected in the patch header.
+
+The source packages gcj-x.y and gnat-x.y do not contain copies of the
+source code but build-depend on the appropriate gcc-x.y-source package
+instead.
--- gcc-6-6.3.0.orig/debian/README.ssp
+++ gcc-6-6.3.0/debian/README.ssp
@@ -0,0 +1,28 @@
+Stack smashing protection is a feature of GCC that enables a program to
+detect buffer overflows and immediately terminate execution, rather than
+continuing execution with corrupt internal data structures. It uses
+"canaries" and local variable reordering to reduce the likelihood of
+stack corruption through buffer overflows.
+
+Options that affect stack smashing protection:
+
+-fstack-protector
+    Enables protection for functions that are vulnerable to stack
+    smashing, such as those that call alloca() or use pointers.
+
+-fstack-protector-all
+    Enables protection for all functions.
+
+-Wstack-protector
+    Warns about functions that will not be protected. Only active when
+    -fstack-protector has been used.
+
+Applications built with stack smashing protection should link with the
+ssp library by using the option "-lssp" for systems with glibc-2.3.x or
+older; glibc-2.4 and newer versions provide this functionality in libc.
+
+The Debian architectures alpha, hppa, ia64, m68k, mips, mipsel do not
+have support for stack smashing protection.
+
+More documentation can be found at the project's website:
+http://researchweb.watson.ibm.com/trl/projects/security/ssp/
--- gcc-6-6.3.0.orig/debian/TODO
+++ gcc-6-6.3.0/debian/TODO
@@ -0,0 +1,50 @@
+(It is recommended to edit this file with emacs' todoo mode)
+Last updated: 2008-05-02
+
+* General
+
+- Clean up the sprawl of debian/rules.  I'm sure there are neater
+  ways to do some of it; perhaps split it up into some more files?
+  Partly done.
+
+- Make debian/rules control build the control file without unpacking
+  the sources or applying patches.  Currently, it unpacks the sources,
+  patches them, creates the control file, and a subsequent
+  dpkg-buildpackage deletes the sources, re-unpacks them, and
+  re-patches them.
+
+- Reorganise debian/rules.defs to decide which packages to build in a
+  more straightforward and less error-prone fashion: (1) start with
+  all languages; override the list of languages depending on the name
+  of the source package (gcc-4.3, gnat-4.3, gdc-4.3, gcj-4.3).  (2)
+  filter the list of languages depending on the target platform; (3)
+  depending on the languages to build, decide on which libraries to
+  build.
+
+o [Ludovic Brenta] Ada
+
+- Done: Link the gnat tools with libgnat.so, instead of statically.
+
+- Done: Build libgnatvsn containing parts of the compiler (version
+  string, etc.) under GNAT-Modified GPL.  Link the gnat tools with it.
+
+- Done: Build libgnatprj containing parts of the compiler (the project
+  manager) under pure GPL.  Link the gnat tools with it.
+
+- Done: Build both the zero-cost and setjump/longjump exceptions
+  versions of libgnat.  In particular, gnat-glade (distributed systems)
+  works best with SJLJ.
+
+- Done: Re-enable running the test suite.
+
+- Add support for building cross-compilers.
+
+- Add support for multilib (not yet supported upstream).
+
+* Fortran
+
+- gfortran man page generation
+
+* Java
+
+- build java-gcj-compat from the gcc source?
--- gcc-6-6.3.0.orig/debian/acats-killer.sh
+++ gcc-6-6.3.0/debian/acats-killer.sh
@@ -0,0 +1,62 @@
+#! /bin/sh
+
+# on ia64 systems, the acats hangs in unaligned memory accesses.
+# kill these testcases.
+
+pidfile=acats-killer.pid
+
+usage()
+{
+    echo >&2 "usage: `basename $0` [-p <pidfile>] <ada logfile> <next logfile>"
+    exit 1
+}
+
+while [ $# -gt 0 ]; do
+    case $1 in
+    -p)
+	pidfile=$2
+	shift
+	shift
+	;;
+    -*)
+	usage
+	;;
+    *)
+	break
+    esac
+done
+
+[ $# -eq 2 ] || usage
+
+logfile=$1
+stopfile=$2
+interval=30
+
+echo $$ > $pidfile
+
+while true; do
+    if [ -f "$stopfile" ]; then
+	echo "`basename $0`: finished."
+	rm -f $pidfile
+	exit 0
+    fi
+    sleep $interval
+    if [ ! -f "$logfile" ]; then
+	continue
+    fi
+    pids=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }')
+    if [ -n "$pids" ]; then
+	sleep $interval
+        pids2=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }')
+	if [ "$pids" = "$pids2" ]; then
+	    #echo kill: $pids
+	    kill $pids
+	    sleep 1
+            pids2=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }')
+	    if [ "$pids" = "$pids2" ]; then
+	        #echo kill -9: $pids
+	        kill -9 $pids
+	    fi
+	fi
+    fi
+done
--- gcc-6-6.3.0.orig/debian/ada/confirm_debian_bugs.py
+++ gcc-6-6.3.0/debian/ada/confirm_debian_bugs.py
@@ -0,0 +1,968 @@
+#!/usr/bin/env python
+
+# Helper when migrating bugs from a gnat version to another.
+
+from __future__ import print_function
+import os.path
+import re
+import shutil
+import subprocess
+import tempfile
+
+os.environ ['LC_ALL'] = 'C'
+
+# If == new_version, "reassign" -> "found" and "retitle" -> "fixed".
+# Once the bug tracking system is informed,
+# please update this number.
+old_version = "5"
+
+# The current version.
+new_version = "6"
+
+for line in subprocess.check_output (("dpkg", "--status", "gnat-" + new_version)).split ("\n"):
+    if line.startswith ("Version: "):
+        deb_version = line [len ("Version: "):]
+        break
+# Will cause an error later if deb_version is not defined.
+
+# Each bug has its own subdirectory in WORKSPACE.
+# Every bug subdir is removed if the bug is confirmed,
+# and WORKSPACE is removed if empty.
+workspace = tempfile.mkdtemp (suffix = "-gnat-" + deb_version + "-bugs")
+
+def attempt_to_reproduce (bug, make, sources):
+    tmp_dir = os.path.join (workspace, "bug{}".format (bug))
+    os.mkdir (tmp_dir)
+
+    for (name, contents) in sources:
+        with open (os.path.join (tmp_dir, name), "w") as f:
+            f.write (contents)
+
+    path = os.path.join (tmp_dir, "stderr.log")
+    with open (path, "w") as e:
+        status = subprocess.call (make, stderr=e, cwd=tmp_dir)
+    with open (path, "r") as e:
+        stderr = e.read ()
+    return tmp_dir, status, stderr
+
+def reassign_and_remove_dir (bug, tmp_dir):
+    if old_version == new_version:
+        print ("found {} {}".format (bug, deb_version))
+    else:
+        print ("reassign {} {} {}".format (bug, "gnat-" + new_version, deb_version))
+    shutil.rmtree (tmp_dir)
+
+def report (bug, message, output):
+    print ("# {}: {}.".format (bug, message))
+    for line in output.split ("\n"):
+        print ("# " + line)
+
+def report_and_retitle (bug, message, output):
+    report (bug, message, output)
+    if old_version == new_version:
+        print ("fixed {} {}".format (bug, deb_version))
+    else:
+        print ("retitle {} [Fixed in {}] <current title>".format (bug, new_version))
+
+def check_compiles_but_should_not (bug, make, sources):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status == 0:
+        reassign_and_remove_dir (bug, tmp_dir)
+    else:
+        report_and_retitle (bug, "now fails to compile (bug is fixed?)", stderr)
+
+def check_reports_an_error_but_should_not (bug, make, sources, regex):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status == 0:
+        report_and_retitle (bug, "now compiles (bug is fixed?)", stderr)
+    elif re.search (regex, stderr):
+        reassign_and_remove_dir (bug, tmp_dir)
+    else:
+        report (bug, "still fails to compile, but with a new stderr", stderr)
+
+def check_reports_error_but_forgets_one (bug, make, sources, regex):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status == 0:
+        report (bug, "now compiles (?)", stderr);
+    elif re.search (regex, stderr):
+        report_and_retitle (bug, "now reports the error (bug is fixed ?)", stderr)
+    else:
+        reassign_and_remove_dir (bug, tmp_dir)
+
+def check_produces_a_faulty_executable (bug, make, sources, regex, trigger):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status != 0:
+        report (bug, "cannot compile the trigger anymore", stderr)
+    else:
+        output = subprocess.check_output ((os.path.join (tmp_dir, trigger),), cwd=tmp_dir)
+        if re.search (regex, output):
+            reassign_and_remove_dir (bug, tmp_dir)
+        else:
+            report_and_retitle (bug, "output of the trigger changed (bug fixed?)", output)
+
+######################################################################
+
+check_reports_an_error_but_should_not (
+    bug = 244936,
+    make = ("gnatmake", "p"),
+    regex = 'p\.ads:3:25: "foo" is hidden within declaration of instance',
+    sources = (
+        ("foo.ads", """generic
+procedure foo;
+"""),
+        ("foo.adb", """procedure foo is
+begin
+   null;
+end foo;
+"""), ("p.ads", """with foo;
+package p is
+   procedure FOO is new foo;        -- OK
+end p;
+""")))
+
+check_compiles_but_should_not (
+    bug = 244970,
+    make = ("gnatmake", "pak5"),
+    sources = (
+        ("pak1.ads", """generic
+package pak1 is
+end pak1;
+"""),
+        ("pak1-pak2.ads", """generic
+package pak1.pak2 is
+end pak1.pak2;
+"""),
+        ("pak5.ads", """with pak1.pak2;
+generic
+   with package new_pak2 is new pak1.pak2;  -- ERROR: illegal use of pak1
+package pak5 is
+end pak5;
+""")))
+
+check_reports_an_error_but_should_not (
+    bug = 246187,
+    make = ("gnatmake", "test_43"),
+    regex = "Error detected at system.ads:156:5",
+    sources = (
+        ("test_43.ads", """package Test_43 is
+  type T1 is private;
+
+private
+
+   type T2 is record
+      a: T1;
+   end record;
+   type T2_Ptr is access T2;
+
+   type T1 is record
+      n: T2_Ptr := new T2;
+   end record;
+
+end Test_43;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247013,
+    make = ("gnatmake", "test_53"),
+    sources = (
+        ("test_53.ads", """generic
+   type T1 is private;
+package Test_53 is
+   type T2 (x: integer) is new T1;  -- ERROR: x not used
+end Test_53;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247017,
+    make = ("gnatmake", "test_59"),
+    sources = (
+        ("test_59.adb", """procedure Test_59 is
+
+    generic
+       type T1 (<>) is private;
+    procedure p1(x: out T1);
+
+    procedure p1 (x: out T1) is
+    b: boolean := x'constrained;   --ERROR: not a discriminated type
+    begin
+       null;
+    end p1;
+
+begin
+   null;
+end Test_59;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247018,
+    make = ("gnatmake", "test_60"),
+    sources = (
+        ("pak1.ads", """package pak1 is
+   generic
+   package pak2 is
+   end pak2;
+end pak1;
+"""),
+        ("test_60.ads", """with pak1;
+package Test_60 is
+   package PAK1 is new pak1.pak2;   --ERROR: illegal reference to pak1
+end Test_60;
+""")))
+
+check_compiles_but_should_not (
+    bug =  247019,
+    make = ("gnatmake", "test_61"),
+    sources = (
+        ("test_61.adb", """procedure Test_61 is
+   procedure p1;
+
+   generic
+   package pak1 is
+      procedure p2 renames p1;
+   end pak1;
+
+   package new_pak1 is new pak1;
+   procedure p1 renames new_pak1.p2;   --ERROR: circular renames
+begin
+   p1;
+end Test_61;
+"""),))
+
+check_produces_a_faulty_executable (
+    bug = 247569,
+    make = ("gnatmake", "test_75"),
+    trigger = "test_75",
+    regex = "failed: wrong p1 called",
+    sources = (
+        ("test_75.adb", """with text_io;
+procedure Test_75 is
+   generic
+   package pak1 is
+      type T1 is null record;
+   end pak1;
+
+   generic
+      with package A is new pak1(<>);
+      with package B is new pak1(<>);
+   package pak2 is
+      procedure p1(x: B.T1);
+      procedure p1(x: A.T1);
+   end pak2;
+
+   package body pak2 is
+
+      procedure p1(x: B.T1) is
+      begin
+         text_io.put_line("failed: wrong p1 called");
+      end p1;
+
+      procedure p1(x: A.T1) is
+      begin
+         text_io.put_line("passed");
+      end p1;
+
+      x: A.T1;
+   begin
+      p1(x);
+   end pak2;
+
+   package new_pak1 is new pak1;
+   package new_pak2 is new pak2(new_pak1, new_pak1); -- (1)
+
+begin
+   null;
+end Test_75;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247570,
+    make = ("gnatmake", "test_76"),
+    sources = (
+        ("test_76.adb", """procedure Test_76 is
+
+   generic
+   procedure p1;
+
+   pragma Convention (Ada, p1);
+
+   procedure p1 is
+   begin
+      null;
+   end p1;
+
+   procedure new_p1 is new p1;
+   pragma Convention (Ada, new_p1);    --ERROR: new_p1 already frozen
+
+begin
+   null;
+end Test_76;
+"""),))
+
+check_produces_a_faulty_executable (
+    bug =  247571,
+    make = ("gnatmake", "test_77"),
+    trigger = "test_77",
+    regex = "failed: wrong p1 called",
+    sources = (
+        ("pak.ads", """package pak is
+   procedure p1;
+   procedure p1(x: integer);
+   pragma export(ada, p1);
+end pak;
+"""),
+        ("pak.adb", """with text_io; use text_io;
+package body pak is
+   procedure p1 is
+   begin
+      put_line("passed");
+   end;
+
+   procedure p1(x: integer) is
+   begin
+      put_line("failed: wrong p1 called");
+   end;
+end pak;
+"""),
+        ("test_77.adb", """with pak;
+procedure Test_77 is
+   procedure p1;
+   pragma import(ada, p1);
+begin
+   p1;
+end Test_77;
+""")))
+
+check_compiles_but_should_not (
+    bug = 248166,
+    make = ("gnatmake", "test_82"),
+    sources = (
+        ("test_82.adb", """procedure Test_82 is
+   package pak1 is
+      type T1 is tagged null record;
+   end pak1;
+
+   package body pak1 is
+      -- type T1 is tagged null record;  -- line 7
+
+      function "=" (x, y : T1'class) return boolean is -- line 9
+      begin
+         return true;
+      end "=";
+
+      procedure proc (x, y : T1'class) is
+         b : boolean;
+      begin
+         b := x = y;     --ERROR: ambiguous "="
+      end proc;
+
+   end pak1;
+
+begin
+   null;
+end Test_82;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248168,
+    make = ("gnatmake", "test_84"),
+    sources = (
+        ("test_84.adb", """procedure Test_84 is
+   package pak1 is
+      type T1 is abstract tagged null record;
+      procedure p1(x: in out T1) is abstract;
+   end pak1;
+
+   type T2 is new pak1.T1 with null record;
+
+   protected type T3 is
+   end T3;
+
+   protected body T3 is
+   end T3;
+
+   procedure p1(x: in out T2) is    --ERROR: declared after body of T3
+   begin
+      null;
+   end p1;
+
+begin
+   null;
+end Test_84;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248678,
+    make = ("gnatmake", "test_80"),
+    sources = (
+        ("test_80.ads", """package Test_80 is
+   generic
+      type T1(<>) is private;
+      with function "=" (Left, Right : T1) return Boolean is <>;
+   package pak1 is
+   end pak1;
+
+   package pak2 is
+      type T2 is abstract tagged null record;
+      package new_pak1 is new pak1 (T2'Class);  --ERROR: no matching "="
+   end pak2;
+end Test_80;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248680,
+    make = ("gnatmake", "test_90"),
+    sources = (
+        ("test_90.adb", """procedure Test_90 is
+   type T1 is tagged null record;
+
+   procedure p1 (x : access T1) is
+      b: boolean;
+      y: aliased T1;
+   begin
+      B := Y'Access = X;     -- ERROR: no matching "="
+--    B := X = Y'Access;     -- line 11: error detected
+   end p1;
+
+begin
+   null;
+end Test_90;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248681,
+    make = ("gnatmake", "test_91"),
+    sources = (
+        ("test_91.adb", """--  RM 8.5.4(5)
+--  ...the convention of the renamed subprogram shall not be
+--  Intrinsic.
+with unchecked_deallocation;
+procedure Test_91 is
+   generic -- when non generic, we get the expected error
+   package pak1 is
+      type int_ptr is access integer;
+      procedure free(x: in out int_ptr);
+   end pak1;
+
+   package body pak1 is
+      procedure deallocate is new
+        unchecked_deallocation(integer, int_ptr);
+      procedure free(x: in out int_ptr) renames
+        deallocate;  --ERROR: renaming as body can't rename intrinsic
+   end pak1;
+begin
+   null;
+end Test_91;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248682,
+    make = ("gnatmake", "main"),
+    sources = (
+        ("main.adb", """--  RM 6.3.1(9)
+--  The default calling convention is Intrinsic for ...  an attribute
+--  that is a subprogram;
+
+--  RM 8.5.4(5)
+--  ...the convention of the renamed subprogram shall not be
+--  Intrinsic.
+procedure main is
+   package pak1 is
+      function f1(x: integer'base) return integer'base;
+   end pak1;
+
+   package body pak1 is
+      function f1(x: integer'base) return integer'base renames
+        integer'succ;  --ERROR: renaming as body can't rename intrinsic
+   end pak1;
+begin
+   null;
+end;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 253737,
+    make = ("gnatmake", "test_4"),
+    regex = 'test_4.ads:.:01: "pak2" not declared in "pak1"',
+    sources = (
+        ("parent.ads", """generic
+package parent is
+end parent;
+"""),
+        ("parent-pak2.ads", """generic
+package parent.pak2 is
+end parent.pak2;
+"""),
+        ("parent-pak2-pak3.ads", """generic
+package parent.pak2.pak3 is
+end parent.pak2.pak3;
+"""),
+        ("parent-pak2-pak4.ads", """with parent.pak2.pak3;
+generic
+package parent.pak2.pak4 is
+   package pak3 is new parent.pak2.pak3;
+end parent.pak2.pak4;
+"""),
+        ("pak1.ads", """with parent;
+package pak1 is new parent;
+"""),
+        ("pak6.ads", """with parent.pak2;
+with pak1;
+package pak6 is new pak1.pak2;
+"""),
+        ("test_4.ads", """with parent.pak2.pak4;
+with pak6;
+package Test_4 is new pak6.pak4;
+""")))
+
+check_compiles_but_should_not (
+    bug = 269948,
+    make = ("gnatmake", "test_119"),
+    sources = (
+        ("test_119.ads", """--  RM 3.9.3/11 A generic actual subprogram shall not be an abstract
+--  subprogram.  works OK if unrelated line (A) is commented out.
+package Test_119 is
+   generic
+      with function "=" (X, Y : integer) return Boolean is <>;   -- Removing this allows GCC to detect the problem.
+   package pak1 is
+      function "=" (X, Y: float) return Boolean is abstract;
+      generic
+         with function Equal (X, Y : float) return Boolean is "=";  --ERROR:
+      package pak2 is
+      end pak2;
+   end pak1;
+
+   package new_pak1 is new pak1;
+   package new_pak2 is new new_pak1.pak2;
+end Test_119;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 269951,
+    make = ("gnatmake", "test_118"),
+    sources = (
+        ("pak1.ads", """generic
+package pak1 is
+end pak1;
+"""),
+        ("pak1-foo.ads", """generic
+package pak1.foo is
+end pak1.foo;
+"""),
+        ("test_118.ads", """with pak1.foo;
+package Test_118 is
+   package pak3 is
+      foo: integer;
+   end pak3;
+   use pak3;
+
+   package new_pak1 is new pak1;
+   use new_pak1;
+
+   x: integer := foo;       -- ERROR: foo hidden by use clauses
+end Test_118;
+"""),))
+
+# As long as 24:14 is detected, it inhibits detection of 25:21.
+check_reports_error_but_forgets_one (
+    bug = 276224,
+    make = ("gnatmake", "test_121"),
+    regex = "test_121\.adb:25:21: dynamically tagged expression not allowed",
+    sources = (
+        ("test_121.adb", """--  If the expected type for an expression or name is some specific
+--  tagged type, then the expression or name shall not be dynamically
+--  tagged unless it is a controlling operand in a call on a
+--  dispatching operation.
+procedure Test_121 is
+   package pak1 is
+      type T1 is tagged null record;
+      function f1 (x1: T1) return T1;
+   end pak1;
+
+   package body pak1 is
+      function f1 (x1: T1) return T1 is
+      begin
+         return x1;
+      end;
+   end pak1;
+   use pak1;
+
+   type T2 is record
+      a1: T1;
+   end record;
+
+   z0: T1'class := T1'(null record);
+   z1: T1 := f1(z0);           -- ERROR: gnat correctly rejects
+   z2: T2 := (a1 => f1(z0));   -- ERROR: gnat mistakenly allows
+begin
+   null;
+end Test_121;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 276227,
+    make = ("gnatmake", "test_124"),
+    regex = 'test_124\.ads:6:35: size for "T_arr_constrained" too small, minimum allowed is 256',
+    sources = (
+        ("test_124.ads", """package Test_124 is
+   type T is range 1 .. 32;
+   type T_arr_unconstrained is array (T range <>) of boolean;
+   type T_arr_constrained is new T_arr_unconstrained (T);
+   pragma pack (T_arr_unconstrained);
+   for T_arr_constrained'size use 32;
+end Test_124;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 278687,
+    make = ("gnatmake", "test_127"),
+    regex = 'test_127\.adb:1.:21: expected type "T2" defined at line .',
+    sources = (
+        ("test_127.ads", """-- The second parameter of T2'Class'Read is of type T2'Class,
+-- which should match an object of type T3, which is derived
+-- from T2.
+package test_127 is
+   pragma elaborate_body;
+end test_127;
+"""),
+        ("test_127.adb", """with ada.streams;
+package body test_127 is
+   type T1 is access all ada.streams.root_stream_type'class;
+   type T2 is tagged null record;
+   type T3 is new T2 with null record;
+
+   x: T1;
+   y: T3;
+begin
+   T2'class'read(x, y);
+end test_127;
+""")))
+
+check_compiles_but_should_not (
+    bug = 278831,
+    make = ("gnatmake", "test_128"),
+    sources = (
+        ("test_128.ads", """package Test_128 is
+   package inner is
+   private
+      type T1;
+   end inner;
+   type T1_ptr is access inner.T1; -- line  9 ERROR: gnat mistakenly accepts
+end Test_128;
+"""),
+        ("test_128.adb", """package body test_128 is
+   package body inner is
+      type T1 is new Integer;
+   end inner;
+end Test_128;
+""")))
+
+# Note that we also check the absence of the next inhibited message.
+check_reports_an_error_but_should_not (
+    bug = 279893,
+    make = ("gnatmake", "test_129"),
+    regex = """^gcc-[0-9.]+ -c test_129\.ads
+test_129\.ads:1.:49: designated type of actual does not match that of formal "T2"
+test_129\.ads:1.:49: instantiation abandoned
+gnatmake: "test_129\.ads" compilation error$""",
+    sources = (
+        ("pak1.ads", """-- legal instantiation rejected; illegal instantiation accepted
+-- adapted from John Woodruff c.l.a. post
+
+generic
+   type T1 is private;
+package pak1 is
+   subtype T3 is T1;
+end pak1;
+"""),
+        ("pak2.ads", """with pak1;
+generic
+   type T2 is private;
+package pak2 is
+   package the_pak1 is new pak1 (T1 => T2);
+end pak2;
+"""),
+        ("pak2-pak3.ads", """generic
+   type T2 is access the_pak1.T3;
+package pak2.pak3 is
+end pak2.pak3;
+"""),
+        ("test_129.ads", """with pak1;
+with pak2.pak3;
+package Test_129 is
+
+   type T4 is null record;
+   type T5 is null record;
+   subtype T3 is T5; -- line 9: triggers the bug at line 16
+
+   type T4_ptr is access T4;
+   type T5_ptr is access T5;
+
+   package new_pak2 is new pak2 (T2 => T4);
+   package new_pak3a is new new_pak2.pak3(T2 => T4_ptr);  -- line 15: Legal
+   package new_pak3b is new new_pak2.pak3(T2 => T5_ptr);  -- line 16: Illegal
+end Test_129;
+""")))
+
+print ("# Please ignore the gnatlink message.")
+check_reports_an_error_but_should_not (
+    bug = 280939,
+    make = ("gnatmake", "test_130"),
+    regex = "test_130\.adb:\(\.text\+0x5\): undefined reference to \`p2\'",
+    sources = (
+        ("pak1.ads", """--  RM 10.1.5(4) "the pragma shall have an argument that is a name
+--  denoting that declaration."
+--  RM 8.1(16) "The children of a parent library unit are inside the
+--  parent's declarative region."
+
+package pak1 is
+   pragma Pure;
+end pak1;
+"""),
+        ("pak1-p2.ads", """procedure pak1.p2;
+pragma Pure (p2);          -- ERROR: need expanded name
+pragma Import (ada, p2);   -- ERROR: need expanded name
+pragma Inline (p2);        -- ERROR: need expanded name
+"""),
+        ("test_130.adb", """with Pak1.P2;
+procedure Test_130 is
+begin
+   Pak1.P2;
+end Test_130;
+""")))
+
+check_compiles_but_should_not (
+    bug = 283833,
+    make = ("gnatmake", "test_132"),
+    sources = (
+        ("pak1.ads", """-- RM 8.5.4(5)  the convention of the renamed subprogram shall not
+-- be Intrinsic, if the renaming-as-body completes that declaration
+-- after the subprogram it declares is frozen.
+
+-- RM 13.14(3)  the end of the declaration of a library package
+-- causes freezing of each entity declared within it.
+
+-- RM 6.3.1(7)  the default calling convention is Intrinsic for
+-- any other implicitly declared subprogram unless it is a
+-- dispatching operation of a tagged type.
+
+package pak1 is
+   type T1 is null record;
+   procedure p1 (x1: T1);
+   type T2 is new T1;
+end pak1;
+"""),
+        ("pak1.adb", """package body Pak1 is
+   procedure P1 (X1 : T1) is begin null; end P1;
+end Pak1;
+"""),
+        ("test_132.ads", """with pak1;
+package Test_132 is
+   procedure p2 (x2: pak1.T2);
+end Test_132;
+"""),
+        ("test_132.adb", """package body Test_132 is
+   procedure p2 (x2: pak1.T2) renames pak1.p1; --ERROR: can't rename intrinsic
+end Test_132;
+""")))
+
+check_compiles_but_should_not (
+    bug = 283835,
+    make = ("gnatmake", "test_133"),
+    sources = (
+        ("test_133.ads", """package Test_133 is
+   package pak1 is
+      type T1 is null record;
+   end pak1;
+
+   package pak2 is
+      subtype boolean is standard.boolean;
+      function "=" (x, y: pak1.T1) return boolean;
+   end pak2;
+
+   use pak1, pak2;
+
+   x1: pak1.T1;
+   b1: boolean := x1 /= x1;  -- ERROR: ambigous  (gnat misses)
+   --  b2: boolean := x1 = x1;   -- ERROR: ambigous
+end Test_133;
+"""),
+        ("test_133.adb", """package body test_133 is
+   package body pak2 is
+      function "=" (x, y: pak1.T1) return boolean is
+      begin
+         return true;
+      end "=";
+   end pak2;
+end test_133;
+""")))
+
+check_compiles_but_should_not (
+    bug = 416979,
+    make = ("gnatmake", "pak1"),
+    sources = (
+        ("pak1.ads", """package pak1 is
+   -- RM 7.3(13), 4.9.1(1)
+   -- check that discriminants statically match
+   type T1(x1: integer) is tagged null record;
+   x2: integer := 2;
+   x3: constant integer := x2;
+   type T2 is new T1 (x2) with private;
+   type T3 is new T1 (x3) with private;
+private
+   type T2 is new T1 (x2) with null record;  --ERROR: nonstatic discriminant
+   type T3 is new T1 (x3) with null record;  --ERROR: nonstatic discriminant
+end pak1;
+"""),))
+
+# Once the bug box disappears, check the executable.
+# check_produces_a_faulty_executable (
+check_reports_an_error_but_should_not (
+    bug = 427108,
+    make = ("gnatmake", "test1"),
+#     regex = "FAILED",
+    regex = "Program_Error exp_disp.adb:7842 explicit raise",
+    sources = (
+        ("test1.adb", """-- "For the execution of a call on an inherited subprogram,
+-- a call on the corresponding primitive subprogram of the
+-- parent or progenitor type is performed; the normal conversion
+-- of each actual parameter to the subtype of the corresponding
+-- formal parameter (see 6.4.1) performs any necessary type
+-- conversion as well."
+
+with Text_IO; use Text_IO;
+procedure Test1 is
+   package Pak1 is
+      type T1 is tagged null record;
+      function Eq(X, Y: T1) return Boolean renames "=";
+   end Pak1;
+
+   package Pak2 is
+      type T2 is new Pak1.T1 with record
+         F1: Integer;
+      end record;
+   end Pak2;
+
+   Z1: Pak2.T2 := (F1 => 1);
+   Z2: Pak2.T2 := (F1 => 2);
+begin
+   if Pak2.Eq(Z1, Z2) = Pak1.Eq(Pak1.T1(Z1), Pak1.T1(Z2))
+      then Put_Line("PASSED");
+      else Put_Line("FAILED");
+   end if;
+end Test1;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 660698,
+    make = ("gnatmake", "proc.adb"),
+    regex = 'proc\.adb:17:28: there is no applicable operator "And" for type "Standard\.Integer"',
+    sources = (
+        ("proc.adb", """procedure Proc is
+   package P1 is
+      type T is new Integer;
+      function "and" (L, R : in Integer) return T;
+   end P1;
+   package body P1 is
+      function "and" (L, R : in Integer) return T is
+         pragma Unreferenced (L, R);
+      begin
+         return 0;
+      end "and";
+   end P1;
+   use type P1.T;
+   package P2 is
+      use P1;
+   end P2;
+   G : P1.T := Integer'(1) and Integer'(2);
+begin
+   null;
+end Proc;
+"""), ))
+
+check_produces_a_faulty_executable (
+    bug = 737225,
+    make = ("gnatmake", "round_decimal"),
+    trigger = "round_decimal",
+    regex = "Bug reproduced.",
+    sources = (
+        ("round_decimal.adb", """with Ada.Text_IO;
+
+procedure Round_Decimal is
+
+   --  OJBECTIVE:
+   --    Check that 'Round of a decimal fixed point type does round
+   --    away from zero if the operand is of a decimal fixed point
+   --    type with a smaller delta.
+
+   Unexpected_Compiler_Bug : exception;
+
+   type Milli is delta 0.001 digits 9;
+   type Centi is delta 0.01 digits 9;
+
+   function Rounded (Value : Milli) return Centi;
+   --  Value, rounded using Centi'Round
+
+   function Rounded (Value : Milli) return Centi is
+   begin
+      return Centi'Round (Value);
+   end Rounded;
+
+begin
+   --  Operands used directly:
+   if not (Milli'Round (0.999) = Milli'(0.999)
+             and
+           Centi'Round (0.999) = Centi'(1.0)
+             and
+           Centi'Round (Milli'(0.999)) = Centi'(1.0))
+   then
+      raise Unexpected_Compiler_Bug;
+   end if;
+   if Rounded (Milli'(0.999)) /= Centi'(1.0) then
+      Ada.Text_IO.Put_Line ("Bug reproduced.");
+   end if;
+end Round_Decimal;
+"""),))
+
+# Even if an error is reported, the problem with the atomic variable
+# should be checked.
+check_reports_an_error_but_should_not (
+    bug = 643663,
+    make = ("gnatmake", "test"),
+    regex = 'test\.adb:4:25: no value supplied for component "Reserved"',
+    sources = (
+        ("pkg.ads", """package Pkg is
+   type Byte is mod 2**8;
+   type Reserved_24 is mod 2**24;
+
+   type Data_Record is
+      record
+         Data : Byte;
+         Reserved : Reserved_24;
+      end record;
+
+   for Data_Record use
+      record
+         Data at 0 range 0 .. 7;
+         Reserved at 0 range 8 .. 31;
+      end record;
+
+   for Data_Record'Size use 32;
+   for Data_Record'Alignment use 4;
+
+   Data_Register : Data_Record;
+   pragma Atomic (Data_Register);
+end Pkg;
+"""), ("test.adb", """with Pkg;
+procedure Test is
+begin
+   Pkg.Data_Register := (
+      Data => 255,
+      others => <> -- expected error: no value supplied for component "Reserved"
+   );
+end Test;
+""")))
+
+try:
+    os.rmdir (workspace)
+except:
+    print ("Some unconfirmed, not removing directory {}.".format (workspace))
--- gcc-6-6.3.0.orig/debian/ada/debian_packaging.mk
+++ gcc-6-6.3.0/debian/ada/debian_packaging.mk
@@ -0,0 +1,91 @@
+# Common settings for Ada Debian packaging.
+#
+#  Copyright (C) 2012-2014 Nicolas Boulenguez <nicolas@debian.org>
+#
+#  This program is free software: you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation, either version 3 of the
+#  License, or (at your option) any later version.
+#  This program is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+#  General Public License for more details.
+#  You should have received a copy of the GNU General Public License
+#  along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+# dpkg-dev (>= 1.16.1) provides /usr/share/dpkg/default.mk (or the
+# more specific buildflags.mk) to set standard variables like
+# DEB_HOST_MULTIARCH, CFLAGS, LDFLAGS...) according to the build
+# environment (DEB_BUILD_OPTIONS...) and the policy (hardening
+# flags...).
+# You must include it before this file.
+ifeq (,$(findstring /usr/share/dpkg/buildflags.mk,$(MAKEFILE_LIST)))
+  $(error Please include /usr/share/dpkg/default.mk (or the more specific \
+          buildflags.mk) before $(lastword $(MAKEFILE_LIST)))
+endif
+
+# Ada is not in dpkg-dev flag list. We add a sensible default here.
+
+# Format checking is meaningless for Ada sources.
+ADAFLAGS := $(filter-out -Wformat -Werror=format-security, $(CFLAGS))
+
+ifdef DPKG_EXPORT_BUILDFLAGS
+  export ADAFLAGS
+endif
+
+# Avoid dpkg-shlibdeps warning about depending on a library from which
+# no symbol is used, see http://wiki.debian.org/ToolChain/DSOLinking.
+# Gnatmake users must upgrade to >= 4.6.4-1 to circumvent #680292.
+LDFLAGS += -Wl,--as-needed
+
+# Warn during build time if undefined symbols.
+LDFLAGS += -Wl,-z,defs
+
+ifdef DPKG_EXPORT_BUILDFLAGS
+  export LDFLAGS
+endif
+
+######################################################################
+# C compiler version
+
+# GCC binaries must be compatible with GNAT at the binary level, use
+# the same version. This setting is mandatory for every upstream C
+# compilation ("export CC" is enough for dh_auto_configure with a
+# normal ./configure).
+
+CC := gnatgcc
+
+######################################################################
+# Options for gprbuild/gnatmake.
+
+# Let Make delegate parallelism to gnatmake/gprbuild.
+.NOTPARALLEL:
+
+# Use all processors unless parallel=n is set in DEB_BUILD_OPTIONS.
+# http://www.debian.org/doc/debian-policy/ch-source.html#s-debianrules-options
+BUILDER_JOBS := $(filter parallel=%,$(DEB_BUILD_OPTIONS))
+ifneq (,$(BUILDER_JOBS))
+  BUILDER_JOBS := $(subst parallel=,,$(BUILDER_JOBS))
+else
+  BUILDER_JOBS := $(shell getconf _NPROCESSORS_ONLN)
+endif
+BUILDER_OPTIONS += -j$(BUILDER_JOBS)
+
+BUILDER_OPTIONS += -R
+# Avoid lintian warning about setting an explicit library runpath.
+# http://wiki.debian.org/RpathIssue
+
+BUILDER_OPTIONS += -v
+# Make exact command lines available for automatic log checkers.
+
+BUILDER_OPTIONS += -eS
+# Tell gnatmake to echo commands to stdout instead of stderr, avoiding
+# buildds thinking it is inactive and killing it.
+# -eS is the default on gprbuild.
+
+# You may be interested in
+# -s  recompile if compilation switches have changed
+#     (bad default because of interactions between -amxs and standard library)
+# -we handle warnings as errors
+# -vP2 verbose when parsing projects.
--- gcc-6-6.3.0.orig/debian/bin-wrapper.in
+++ gcc-6-6.3.0/debian/bin-wrapper.in
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+# some build tools are linked with a new libstdc++ and fail to run
+# when building libstdc++.
+
+if [ -n "$LD_LIBRARY_PATH" ]; then
+  ma=$(dpkg-architecture -qDEB_BUILD_MULTIARCH)
+  export LD_LIBRARY_PATH="/lib/$ma:/usr/lib/$ma:/lib:/usr/lib:$LD_LIBRARY_PATH"
+fi
+
+exec /usr/bin/$(basename $0) "$@"
--- gcc-6-6.3.0.orig/debian/changelog
+++ gcc-6-6.3.0/debian/changelog
@@ -0,0 +1,2412 @@
+gcc-6 (6.3.0-9ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 16 Mar 2017 14:59:50 +0100
+
+gcc-6 (6.3.0-9) unstable; urgency=medium
+
+  * Update to SVN 20170316 (r246188) from the gcc-6-branch.
+    - Fix PR target/79261 (PPC), PR fortran/78474, PR libstdc++/79789,
+      PR target/79514 (x86), PR target/79544 (PPC), PR lto/79579,
+      PR target/79749 (sparc), PR target/79261 (PPC), PR fortran/78474,
+      PR fortran/78331, PR target/77850 (PA), PR target/79439 (PPC),
+      PR c++/79796, PR ada/79903, PR ada/79945, PR libstdc++/80034,
+      PR c++/79962, PR c++/79984, PR c/79756, PR tree-optimization/79732,
+      PR target/80019 (x86), PR target/79752 (PPC), PR middle-end/80004,
+      PR target/49244 (x86), PR tree-optimization/79977, PR middle-end/79971,
+      PR tree-optimization/79666, PR middle-end/79576, PR c++/72775,
+      PR c++/79900, PR c++/79687, PR c++/79264, PR c++/61636, PR fortran/79894.
+  * gcj-6: Fix ecj1 symlink on i386. Closes: #856903.
+  * Fix libcc1.so symlink for cross compilers. Addresses: #856875.
+  * dpkg-buildflags stopped fiddling around with spec files; remove
+    the code removing and warning about dpkg's specs.
+  * libstdc++6: Add break for libopenmpi1.6. Closes: #854881.
+  * Fix symlinks to man pages in the hppa64 package. Closes: #857583.
+  * Don't ship the gnatgcc manpage symlink when building GFDL packages.
+    Closes: #857384.
+  * Install the gcov-dump utility.
+  * Allow to use lld with -fuse-ld=ld.lld.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 16 Mar 2017 14:25:48 +0100
+
+gcc-6 (6.3.0-8ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 21 Feb 2017 15:05:42 +0100
+
+gcc-6 (6.3.0-8) unstable; urgency=medium
+
+  * Update to SVN 20170221 (r245621) from the gcc-6-branch.
+    - Fix ICEs PR middle-end/79537, PR sanitizer/79558, PR middle-end/79536.
+  * Fix ecj1 symlink for gcj cross compiler packages. Addresses: #855640.
+  * Bump binutils version requirement.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 21 Feb 2017 14:54:53 +0100
+
+gcc-6 (6.3.0-7) unstable; urgency=medium
+
+  * Update to SVN 20170218 (r245414) from the gcc-6-branch.
+    - Fix PR target/78945 (ARM), PR translation/79397,
+      PR tree-optimization/71824, PR tree-optimization/71824,
+      PR tree-optimization/77318, PR target/71017 (x86), PR c++/78897,
+      PR c++/78908, PR c++/79296 (closes: #854692), PR sanitizer/79562,
+      PR libstdc++/79114, PR libstdc++/59170, PR libstdc++/59161,
+      PR libstdc++/72792, PR libstdc++/72792, PR libstdc++/72793,
+      PR libstdc++/69321, PR libstdc++/69301, PR libstdc++/79114,
+      PR libstdc++/78702, PR libstdc++/78134, PR libstdc++/78273,
+      PR c/79431, PR target 79545 (PPC), PR target/76731 (x86), PR c/79428,
+      PR tree-optimization/79411, PR c/79431, PR middle-end/79399,
+      PR tree-optimization/79338, PR target/79197 (PPC), PR target/79079,
+      PR tree-optimization/79267, PR target/79495 (x86), PR c/79471,
+      PR c++/79429, PR c/79431, PR c++/79377.
+  * Update the Linaro support to the 6.3-2017.02 snapshot.
+  * Fix target architecture for sparc non-multilib builds (Adrian Glaubitz).
+    Closes: #855197.
+  * Bump binutils version requirement.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 18 Feb 2017 10:00:36 +0100
+
+gcc-6 (6.3.0-6ubuntu2) zesty; urgency=medium
+
+  * Update to SVN 20170211 (r245353) from the gcc-6-branch.
+    - Fix PR target/78945 (ARM), PR translation/79397,
+      PR tree-optimization/71824, PR tree-optimization/71824,
+      PR tree-optimization/77318, PR target/71017 (x86), PR c++/78897.
+  * Update the Linaro support to the 6.3-2017.02 snapshot.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 11 Feb 2017 02:13:55 +0100
+
+gcc-6 (6.3.0-6) unstable; urgency=medium
+
+  * Update to SVN 20170205 (r245197) from the gcc-6-branch.
+    - Fix PR libstdc++/78346, PR libstdc++/79195, PR libstdc++/79254,
+      PR target/78478, PR target/79268 (PPC, LP: #1661051), PR c++/79176,
+      PR middle-end/78742, PR target/77439 (ARM32), PR tree-optimization/79034,
+      PR fortran/70697, PR fortran/70696, PR fortran/79305, PR go/79037,
+      PR go/79281 (closes: #853223), PR target/78862 (tilegx), PR lto/79061,
+      PR target/65484 (PPC).
+
+  [ Aurelien Jarno ]
+  * Don't use disable madd4 on MIPS big-endian.
+  * Disable lxc1/sxc1 instruction on mips and mipsel.
+
+  [ Matthias Klose ]
+  * Configure with --enable-default-pie on sparc and sparc64 (James Clark).
+    Closes: #854090.
+  * Configure with --enable-default-pie on kfreebsd-* (Steven Chamberlain).
+  * Configure staged builds with --disable-libmpx (Helmut Grohne).
+    Closes: #854159.
+  * Fix suffix'd gnat binary names (Svante Signell). Closes: #814978.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 05 Feb 2017 21:16:42 +0100
+
+gcc-6 (6.3.0-5ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 24 Jan 2017 18:17:14 +0100
+
+gcc-6 (6.3.0-5) unstable; urgency=medium
+
+  * Update to SVN 20170124 (r244868) from the gcc-6-branch.
+    - Fix PR lto/69188, PR go/78763, PR target/78478 (RTEMS).
+  * Fix removing the RUNPATH from the asan, tsan, ubsan, cilkrts, gfortran
+    and gphobos runtime libraries.
+  * Let the gnatgcc symlinks point to the versioned names. Closes: #839209.
+  * Backport patches to disable madd4 instructions on mips* targets and
+    disable these by default (YunQiang Su). Closes. #852153.
+  * Update multiarch builds for a new sh3 target. Closes: #851869.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 24 Jan 2017 14:48:12 +0100
+
+gcc-6 (6.3.0-4ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 21 Jan 2017 21:35:25 +0100
+
+gcc-6 (6.3.0-4) unstable; urgency=medium
+
+  * Update to SVN 20170121 (r244748) from the gcc-6-branch.
+    - Fix PR target/77455 (AArch64), PR rtl-optimization/79121, PR ipa/79043,
+      PR ipa/71207, PR tree-optimization/72488, PR c++/77545, PR c++/77284.
+  * Fix gdc cross build.
+  * Fix symlinks to unprefixed man pages. Closes: #851886.
+  * Fix PR go/79037, proposed golang patch (John Paul Adrian Glaubitz).
+    Closes: #852091.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 21 Jan 2017 18:51:03 +0100
+
+gcc-6 (6.3.0-3ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 18 Jan 2017 22:18:31 +0100
+
+gcc-6 (6.3.0-3) unstable; urgency=medium
+
+  * Update to SVN 20170118 (r244586) from the gcc-6-branch.
+    - Fix PR tree-optimization/71055 (closes: #849032), PR driver/78863,
+      PR translation/78745, PR tree-optimization/78886,
+      PR tree-optimization/78428, PR libstdc++/78956, PR libstdc++/78991,
+      PR rtl-optimization/78255, PR target/78041 (ARM), PR pch/78970,
+      PR lto/79042, PR target/78900 (PPC), PR tree-optimization/78024,
+      PR sanitizer/65479 (PPC), PR c++/77812, PR libstdc++/78389,
+      PR libstdc++/78389, PR debug/78839, PR rtl-optimization/78617,
+      PR target/78253 (ARM), PR target/79044 (PPC), PR c++/78341, PR c++/78949,
+      PR c++/78693, PR c++/71182, PR fortran/78866, PR middle-end/50199.
+  * Always configure sparc builds --with-cpu-32=ultrasparc (James Clark).
+    Closes: #850250.
+  * Enable gccgo on m68k (John Paul Adrian Glaubitz). Closes: #850749.
+  * Reapply the fix for PR target/55947, and fix PR c++/72813, taken from
+    the trunk.
+  * Fix PR target/79044 (PPC), ICE (Bill Schmidt). Closes: #850777.
+  * Don't add the configured prefix to libcc1's compiler name.
+    Closes: #851146.
+  * Update the Linaro support to the 6.3-2017.01 snapshot.
+  * Apply the header changes for PR libstdc++/64735 on armel as well,
+    conditionalized to keep the headers unchanged for other architectures.
+    Closes: #851273.
+  * Install the unprefixed man pages for gcc-ar, -nm and ranlib.
+    Closes: #851698.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 18 Jan 2017 20:02:20 +0100
+
+gcc-6 (6.3.0-2ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 31 Dec 2016 06:18:31 +0100
+
+gcc-6 (6.3.0-2) unstable; urgency=medium
+
+  * Update gdc-driver-nophobos patch.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 31 Dec 2016 06:10:49 +0100
+
+gcc-6 (6.3.0-1) unstable; urgency=medium
+
+  * GCC 6.3.0 release.
+  * Update to SVN 20161229 (r243959) from the gcc-6-branch.
+    - Fix PR c/77767, PR ipa/77905, PR translation/78922, PR fortran/78239.
+
+  [ Matthias Klose ]
+  * Backport proposed patch for PR libstdc++/64735. Closes: #727621.
+  * Configure --with-cpu-32=ultrasparc on sparc. Closes: #845461.
+  * Update gdc to the GCC-6 branch (20161222).
+  * Don't mark libphobos multilib packages as M-A: same.
+  * Configure libphobos builds with --with-target-system-zlib.
+  * Stop applying PR c++/77379.
+  * Fix ignoring dpkg's pie specs when pie is not enabled (James Clarke).
+    Closes: #849542.
+  * Apply proposed patch for PR rtl-optimization/65618. Addresses: #781457.
+  * Bump requirement on binutils to 2.27.90 (gold now implementing -z bndplt).
+
+  [ Samuel Thibault ]
+  * libgo fixup for program invocation name.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 31 Dec 2016 04:46:10 +0100
+
+gcc-6 (6.2.1-7ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 15 Dec 2016 22:50:24 +0100
+
+gcc-6 (6.2.1-7) unstable; urgency=medium
+
+  * GCC 6.3.0 release candidate.
+  * Update to SVN 20161215 (r243686, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/78465, PR c++/78761, PR c++/78252, PR target/59874,
+      PR target/78796, PR tree-optimization/77673, PR target/72717 (PPC),
+      PR rtl-optimization/71496, PR c++/78701.
+  * Drop build dependency on g++-5.
+  * Fix PR c++/78774, proposed for the gcc-6-branch.
+  * Apply patches for zlib security issues CVE-2016-9840, CVE-2016-9841,
+    CVE-2016-9842, CVE-2016-9843.
+  * Ignore dpkg's pie specs when pie is not enabled. Addresses: #848129.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 15 Dec 2016 22:43:42 +0100
+
+gcc-6 (6.2.1-6ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 12 Dec 2016 17:17:23 +0100
+
+gcc-6 (6.2.1-6) unstable; urgency=high
+
+  * Update to SVN 20161212 (r243558, 6.2.1) from the gcc-6-branch.
+    - Fix PR target/78426 (SH), PR fortran/78500, PR target/78101 (PPC),
+      PR target/48863 (ARM32), PR inline-asm/70184, PR libstdc++/71856,
+      PR libstdc++/77459, PR libstdc++/78326, PR libstdc++/51960,
+      PR target/57438 (x86), PR target/77933 (ARM), PR c++/78550,
+      PR tree-optimization/78542, PR tree-optimization/78482, PR c++/71848,
+      PR middle-end/71762, PR tree-optimization/71575, PR bootstrap/78188,
+      PR tree-optimization/78224, PR tree-optimization/77646, PR target/77957,
+      PR middle-end/78540, PR rtl-optimization/78546, PR fortran/78298,
+      PR middle-end/69183, PR middle-end/78416, PR middle-end/67335,
+      PR middle-end/78419, PR rtl-optimization/78378, PR fortran/78299,
+      PR target/77834, PR target/78227, PR target/77834,
+      PR rtl-optimization/77919, PR rtl-optimization/77919, PR middle-end/78025,
+      PR fortran/77973, PR sanitizer/66343, PR fortran/77665,
+      PR middle-end/77624, PR target/77587, PR tree-optimization/78646,
+      PR target/72827, PR c++/78551, PR c++/78649, PR c++/72808, PR c++/77591,
+      PR c++/77739, PR c++/77285, PR c++/78089, PR c++/77467, PR c++/77722,
+      PR c++/77638, PR c++/77637, PR c++/77482, PR c++/77375, PR c++/71274,
+      PR c++/71515, PR c++/77907, PR c++/57728, PR fortran/78593,
+      PR fortran/77666, PR fortran/78443, PR libstdc++/70975,
+      PR libstdc++/71337, PR libstdc++/78111, PR rtl-optimization/77309,
+      PR target/77904 (ARM32).
+
+  [ Matthias Klose ]
+  * Fix dependency generation for libgphobos multilib builds.
+  * Install missing vecintrin.h header on s390x.
+  * Fix PR target/77267 (x86), taken from the trunk.
+  * Use --push-state/--pop-state for gold as well when linking libtsan.
+  * Fix the configure check for compressed debug section support in as and ld.
+    Enables the -gz option again. Taken from the trunk.
+  * In GCC ICE dumps, prefix each line with the PID of the driver.
+  * Stop ignoring the bootstrap comparison failures on mips targets now that
+    these are release architectures.
+
+  [ Svante Signell ]
+  * GNU/Hurd port for gccgo.
+
+  [ Iain Buclaw ]
+  * Use needsCodegen rather than isRoot for determining the static/extern of a
+    template symbol. Closes: #845377.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 12 Dec 2016 16:53:57 +0100
+
+gcc-6 (6.2.1-5ubuntu2) zesty; urgency=medium
+
+  * Update to SVN 20161202 (r243204, 6.2.1) from the gcc-6-branch.
+    - Fix PR target/78426 (SH), PR fortran/78500, PR target/78101 (PPC),
+      PR target/48863 (ARM32), PR inline-asm/70184.
+  * Fix dependency generation for libgphobos multilib builds.
+  * Install missing vecintrin.h header on s390x.
+  * Fix PR target/77267 (x86), taken from the trunk. LP: #1623418.
+  * Use --push-state/--pop-state for gold as well when linking libtsan.
+  * Fix the configure check for compressed debug section support in as and ld.
+    Enables the -gz option again. Taken from the trunk.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 02 Dec 2016 23:22:52 +0100
+
+gcc-6 (6.2.1-5ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 24 Nov 2016 13:36:19 +0100
+
+gcc-6 (6.2.1-5) unstable; urgency=medium
+
+  * Update to SVN 20161124 (r242827, 6.2.1) from the gcc-6-branch.
+    - Fix PR target/77822 (AArch64), PR fortran/58001, PR fortran/69741,
+      PR libstdc++/78490, PR lto/78472, PR middle-end/78305, PR ipa/78309,
+      PR middle-end/78333, PR tree-optimization/78228, PR middle-end/78185,
+      PR tree-optimization/77855, PR fortran/66227, PR fortran/78297,
+      PR middle-end/78429.
+  * Don't apply the ada patches for stage builds.
+  * Add pkg-config to the build dependencies.
+  * Drop the work around for PR libstdc++/65913.
+  * gdc: Link with the shared libgphobos runtime by default. Closes: #845377.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 24 Nov 2016 12:41:33 +0100
+
+gcc-6 (6.2.1-4ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 19 Nov 2016 12:39:00 +0100
+
+gcc-6 (6.2.1-4) unstable; urgency=medium
+
+  * Update to SVN 20161119 (r242621, 6.2.1) from the gcc-6-branch.
+    - Fix PR c++/67631.
+  * Build the GC enabled libobjc using the system libgc when available
+  * Always apply *all* the gnat patches whether or not gnat is built.
+  * Bump debhelper compat level to 9.
+  * Mark libgphobos symbols changing with the file location (sic!) as optional.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 19 Nov 2016 15:52:25 +0100
+
+gcc-6 (6.2.1-3) unstable; urgency=medium
+
+  * Build-depend on binutils (>= 2.27.51.20161118), required for sparc64.
+  * Always apply the gnat patches whether or not gnat is built.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 18 Nov 2016 16:34:00 +0100
+
+gcc-6 (6.2.1-2ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 18 Nov 2016 14:03:09 +0100
+
+gcc-6 (6.2.1-2) unstable; urgency=medium
+
+  * Update to SVN 20161118 (r242586, 6.2.1) from the gcc-6-branch.
+    - Fix PR c++/68377.
+  * Add Replaces for renamed lib*gphobos-dev packages.
+  * libphobos: Fix ARM32 multilib detection for system zlib.
+  * Update libgphobos symbols files for ARM32 targets.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 18 Nov 2016 13:32:28 +0100
+
+gcc-6 (6.2.1-1ubuntu2) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 17 Nov 2016 13:26:20 +0100
+
+gcc-6 (6.2.1-1) unstable; urgency=medium
+
+  * Update to SVN 20161116 (r241998, 6.2.1) from the gcc-6-branch.
+    - Fix PR sanitizer/78294, PR target/78310 (x86), PR target/77822 (s390x),
+      PR target/78262 (x86).
+  * Update gdc to the GCC-6 branch (20161116).
+  * Update libasan symbol files.
+  * Build libgfortran libraries when building without common libs.
+  * Avoid warning for libgcc symbols files.
+  * Add symbols for libobjc_gc library.
+  * Build shared phobos runtime libraries (not yet enabled by default).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 17 Nov 2016 12:42:56 +0100
+
+gcc-6 (6.2.0-13ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 09 Nov 2016 21:04:13 +0100
+
+gcc-6 (6.2.0-13) unstable; urgency=medium
+
+  * Update to SVN 20161109 (r241998, 6.2.1) from the gcc-6-branch.
+    - Fix PR c/71115, PR target/78229 (closes: #843379),
+      PR tree-optimization/77768, PR c++/78039 (closes: #841316),
+      PR libgcc/78064, PR driver/78206.
+  * Fix using the gcc-6-source package (Stephen Kitt). Closes: #843476.
+  * Fix PR target/77822 (AArch64), taken from the trunk. Closes: #839249.
+  * Fix PR target/77822 (s390x), proposed patch.
+  * Update libiberty to the trunk 20161108. Addresses security issues:
+    CVE-2016-6131, CVE-2016-4493, CVE-2016-4492, CVE-2016-4490,
+    CVE-2016-4489, CVE-2016-4488, CVE-2016-4487, CVE-2016-2226.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 09 Nov 2016 20:42:53 +0100
+
+gcc-6 (6.2.0-11ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 03 Nov 2016 15:27:16 +0100
+
+gcc-6 (6.2.0-11) unstable; urgency=medium
+
+  * Update to SVN 20161103 (r241817, 6.2.1) from the gcc-6-branch.
+    - Fix PR debug/77773, PR middle-end/72747, PR tree-optimization/78047,
+      PR tree-optimization/77879, PR tree-optimization/77839,
+      PR tree-optimization/77745, PR tree-optimization/77648,
+      PR target/78166 (PA), PR rtl-optimization/78038, PR middle-end/78128,
+      PR middle-end/71002, PR fortran/69544, PR fortran/78178,
+      PR fortran/71902, PR fortran/67219, PR fortran/71891, PR lto/78129,
+      PR libgfortran/78123.
+  * Fix symlinks for gcj manual pages. Closes: #842407.
+  * Fix ICE in tree_to_shwi, Linaro issue #2575.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 03 Nov 2016 14:10:24 +0100
+
+gcc-6 (6.2.0-10ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 27 Oct 2016 22:12:20 +0200
+
+gcc-6 (6.2.0-10) unstable; urgency=medium
+
+  * Update to SVN 20161027 (r241619, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77288, PR libstdc++/77727, PR libstdc++/78052,
+      PR tree-optimization/77550, PR tree-optimization/77916,
+      PR fortran/71895, PR fortran/77763, PR fortran/61420, PR fortran/78013,
+      PR fortran/78021, PR fortran/72832, PR fortran/78092, PR fortran/78108,
+      PR target/78057 (x86), PR target/78037 (x86).
+  * Include go-relocation-test-gcc620-sparc64.obj.uue to fix libgo's
+    debug/elf TestDWARFRelocations test case (James Clark).
+  * Reapply fix for PR c++/71912, apply proposed fix for PR c++/78039.
+    Closes: #841292.
+  * Don't install alternatives for go and gofmt. The preferred way to do that
+    is to install the golang-any package.
+  * For Debian builds, don't enable bind now by default when linking with pie
+    by default.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 27 Oct 2016 15:27:07 +0200
+
+gcc-6 (6.2.0-9) unstable; urgency=medium
+
+  * Regenerate the control file.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 20 Oct 2016 10:46:44 +0200
+
+gcc-6 (6.2.0-8ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 19 Oct 2016 18:47:57 +0200
+
+gcc-6 (6.2.0-8) unstable; urgency=medium
+
+  * Update to SVN 20161019 (r241346, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77990, PR target/77991 (x86).
+  * Install arm_fp16.h header on arm* architectures for Linaro builds.
+  * Backport upstream revisions from trunk (James Clark). Closes: #840574.
+    - r240457 (add getrandom for MIPS/SPARC)
+    - r241051 (fix getrandom on sparc64 and clone on sparc*)
+    - r241072 (make rawClone no_split_stack)
+    - r241084 (don't use pt_regs; unnecessary, and seemingly not defined by
+               the included headers on arm64)
+    - r241171 (sparc64 relocations, e1fc2925 in go master, now also in
+               gofrontend/gccgo)
+  * Revert fix for PR c++/71912, causing PR c++/78039. Addresses: #841292.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 19 Oct 2016 08:57:23 +0200
+
+gcc-6 (6.2.0-7ubuntu11) zesty; urgency=medium
+
+  * Build using the Linaro branch on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 18 Oct 2016 09:09:47 +0200
+
+gcc-6 (6.2.0-7) unstable; urgency=medium
+
+  * Update to SVN 20161018 (r241301, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77987, PR libstdc++/77322, PR libstdc++/72820,
+      PR libstdc++/77994, PR tree-optimization/77937, PR c++/71912,
+      PR tree-optimization/77937, PR tree-optimization/77943,
+      PR bootstrap/77995, PR fortran/77978, PR fortran/77915, PR fortran/77942.
+
+  [ Matthias Klose ]
+  * Backport Mips go closure support, taken from libffi. Closes: #839132.
+  * Configure with --enable-default-pie and pass -z now when pie is enabled;
+    on amd64 arm64 armel armhf i386 mips mipsel mips64el ppc64el s390x.
+    Closes: #835148.
+  * Update the Linaro support to the 6-2016.10 snapshot.
+
+  [ Aurelien Jarno ]
+  * Enable logwatch on mips64el.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 18 Oct 2016 13:53:00 +0200
+
+gcc-6 (6.2.0-6) unstable; urgency=medium
+
+  * Update to SVN 20161010 (r240906, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/68323, PR libstdc++/77794, PR libstdc++/77795,
+      PR libstdc++/77801, PR libgcc/77519, PR target/77756 (x86),
+      PR target/77670 (PPC), PR rtl-optimization/71709, PR c++/77804,
+      PR fortran/41922, PR fortran/60774, PR fortran/61318, PR fortran/68566,
+      PR fortran/69514, PR fortran/69867, PR fortran/69962, PR fortran/70006,
+      PR fortran/71067, PR fortran/71730, PR fortran/71799, PR fortran/71859,
+      PR fortran/71862, PR fortran/77260, PR fortran/77351, PR fortran/77372,
+      PR fortran/77380, PR fortran/77391, PR fortran/77420, PR fortran/77429,
+      PR fortran/77460, PR fortran/77506, PR fortran/77507, PR fortran/77612,
+      PR fortran/77694, PR libgfortran/77707, PR libstdc++/70101,
+      PR libstdc++/77864, PR libstdc++/70564, PR target/77874 (x86),
+      PR target/77759 (sparc), PR fortran/77406, PR fortran/58991,
+      PR fortran/58992.
+  * Really fix gij installation on hppa. Closes: #838111.
+  * Install alternatives for go and gofmt. Closes: #840190.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 10 Oct 2016 05:20:07 +0200
+
+gcc-6 (6.2.0-5ubuntu12) yakkety; urgency=medium
+
+  * Update to SVN 20161005 (r240765, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/68323, PR libstdc++/77794, PR libstdc++/77795,
+      PR libstdc++/77801, PR libgcc/77519, PR target/77756 (x86),
+      PR target/77670 (PPC), PR rtl-optimization/71709, PR c++/77804,
+      PR fortran/41922, PR fortran/60774, PR fortran/61318, PR fortran/68566,
+      PR fortran/69514, PR fortran/69867, PR fortran/69962, PR fortran/70006,
+      PR fortran/71067, PR fortran/71730, PR fortran/71799, PR fortran/71859,
+      PR fortran/71862, PR fortran/77260, PR fortran/77351, PR fortran/77372,
+      PR fortran/77380, PR fortran/77391, PR fortran/77420, PR fortran/77429,
+      PR fortran/77460, PR fortran/77506, PR fortran/77507, PR fortran/77612,
+      PR fortran/77694, PR libgfortran/77707.
+  * Really fix gij installation on hppa. Closes: #838111.
+  * Strip again the compiler binaries.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 05 Oct 2016 09:01:56 +0200
+
+gcc-6 (6.2.0-5ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Sep 2016 15:58:48 +0200
+
+gcc-6 (6.2.0-5) unstable; urgency=medium
+
+  * Update to SVN 20160927 (r240553, 6.2.1) from the gcc-6-branch.
+    - Fix PR sanitizer/77396, PR libstdc++/77645, PR libstdc++/77645,
+      PR target/77326 (AVR), PR target/77349 (PPC), PR middle-end/77594,
+      PR sanitizer/68260, PR fortran/77516, PR target/69255 (x86),
+      PR c++/77553, PR c++/77539, PR fortran/77500, PR c/77450,
+      PR middle-end/77436, PR tree-optimization/77514, PR middle-end/77544,
+      PR tree-optimization/77514, PR middle-end/77605, PR middle-end/77679,
+      PR tree-optimization/77621, PR target/77621 (x86), PR c++/71979.
+  * Fix gij installation on hppa. Closes: #838111.
+  * Fix PR rtl-optimization/71709, taken from the trunk. LP: #1628207.
+  * Apply workaround for PR libstdc++/77686. Addresses: #838438.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 28 Sep 2016 15:53:28 +0200
+
+gcc-6 (6.2.0-4) unstable; urgency=medium
+
+  * Update to SVN 20160914 (r240133, 6.2.1) from the gcc-6-branch.
+    - Fix PR rtl-optimization/77452, PR c++/77427.
+  * gcj: Depend on the ecj1 standalone binary.
+  * Configure native builds using --with-program-prefix.
+  * Fix ICE in gdc symbol mangling (Iain Buclaw). LP: #1620681.
+  * Backport from libffi trunk (Stefan Bühler):
+    - Always check for PaX MPROTECT on linux, make EMUTRAMP experimental.
+    - dlmmap_locked always needs locking as it always modifies execsize.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 15 Sep 2016 19:22:35 +0200
+
+gcc-6 (6.2.0-3ubuntu15) yakkety; urgency=medium
+
+  * Update to SVN 20160914 (r240133, 6.2.1) from the gcc-6-branch.
+    - PR c++/77427.
+  * Fix updating gcj-6-jdk. LP: #1623337.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 14 Sep 2016 13:33:20 +0200
+
+gcc-6 (6.2.0-3ubuntu14) yakkety; urgency=medium
+
+  * Update to SVN 20160910 (r240069, 6.2.1) from the gcc-6-branch.
+    - Fix PR rtl-optimization/77452.
+  * gcj: Depend on the ecj1 standalone binary.
+  * Configure native builds using --with-program-prefix.
+  * Fix ICE in gdc symbol mangling (Iain Buclaw). LP: #1620681.
+  * Restore the AArch64 vulcan support for non Linaro builds.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 11 Sep 2016 12:50:59 +0200
+
+gcc-6 (6.2.0-3ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 04 Sep 2016 13:28:31 +0200
+
+gcc-6 (6.2.0-3) unstable; urgency=medium
+
+  * Update to SVN 20160901 (r239944, 6.2.1) from the gcc-6-branch.
+    - Fix PR fortran/71014, PR libstdc++/77395, PR tree-optimization/72866,
+      PR debug/77363, PR middle-end/77377, PR middle-end/77259,
+      PR target/71910 (cygwin), PR target/77281 (ARM),
+      PR tree-optimization/71077, PR tree-optimization/68542, PR fortran/77352,
+      PR fortran/77374, PR fortran/71014, PR fortran/69281.
+  * Fix setting the stage1 C++ compiler.
+  * gdc: Always link with -ldl when linking with -lgphobos.
+    Closes: #835255, #835757.
+  * Fix building D code with external C++ references.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 04 Sep 2016 12:38:47 +0200
+
+gcc-6 (6.2.0-2ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 31 Aug 2016 12:38:54 +0200
+
+gcc-6 (6.2.0-2) unstable; urgency=medium
+
+  * Update to SVN 20160830 (r239868, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77334, PR tree-optimization/76783,
+      PR tree-optimization/72851, PR target/72867 (x86), PR middle-end/71700,
+      PR target/77403 (x86), PR target/77270 (x86), PR target/77270 (x86),
+      PR lto/70955, PR target/72863 (PPC), PR tree-optimization/76490,
+      PR fortran/77358.
+  * Call default_file_start from s390_asm_file_start, taken from the trunk.
+  * Update multiarch patches for mips* r6 (YunQiang Su).
+  * Fix install location of D header files for cross builds (YunQiang Su).
+    Closes: #835847.
+  * Fix PR c++/77379, taken from the trunk.
+  * Update the Linaro support to the 6-2016.08 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 31 Aug 2016 12:28:38 +0200
+
+gcc-6 (6.2.0-1ubuntu12) yakkety; urgency=medium
+
+  * Update to SVN 20160824 (r239726, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77334, PR tree-optimization/76783,
+      PR tree-optimization/72851, PR target/72867 (x86), PR middle-end/71700,
+  * Call default_file_start from s390_asm_file_start, taken from the trunk.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 24 Aug 2016 08:12:10 +0200
+
+gcc-6 (6.2.0-1ubuntu11) yakkety; urgency=medium
+
+  * GCC 6.2 release.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 22 Aug 2016 15:23:46 +0200
+
+gcc-6 (6.2.0-1) unstable; urgency=medium
+
+  * GCC 6.2 release.
+  * Update gdc to the gdc-6 branch 20160822.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 22 Aug 2016 14:15:21 +0200
+
+gcc-6 (6.1.1-12ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 15 Aug 2016 17:56:19 +0200
+
+gcc-6 (6.1.1-12) unstable; urgency=medium
+
+  * GCC 6.2 release candidate 1.
+  * Update to SVN 20160815 (r239482, 6.1.1) from the gcc-6-branch.
+    Fix PR target/71869 (PPC), PR target/72805 (x86), PR target/70677 (AVR),
+    PR c++/72415, PR sanitizer/71042, PR libstdc++/71964, PR libstdc++/70940,
+    PR c/67410, PR c/72816, PR driver/72765, PR debug/71906,
+    PR tree-optimization/73434, PR tree-optimization/72824, PR target/76342,
+    PR target/72843, PR c/71512, PR tree-optimization/71083, PR target/72819,
+    PR target/72853, PR tree-optimization/72824, PR ipa/71981, PR ipa/68273,
+    PR tree-optimization/71881, PR target/72802, PR target/72802,
+    PR rtl-optimization/71976, PR c++/71972, PR c++/72868, PR c++/73456,
+    PR c++/72800, PR c++/68724, PR debug/71906, PR fortran/71936,
+    PR fortran/72698, PR fortran/70524, PR fortran/71795, PR libgfortran/71123,
+    PR libgfortran/73142.
+
+  [ Matthias Klose ]
+  * Fix running the libjava testsuite.
+  * Revert fix for PR target/55947, causing PR libstdc++/72813. LP: #1610220.
+  * Update the Linaro support to the 6-2016.07 snapshot.
+
+  [ Aurelien Jarno ]
+  * Replace proposed fix for PR ipa/68273 by the corresponding patch taken
+    from trunk.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 15 Aug 2016 17:51:10 +0200
+
+gcc-6 (6.1.1-11ubuntu12) yakkety; urgency=medium
+
+  * Update to SVN 20160805 (r239167, 6.1.1) from the gcc-6-branch.
+    Fix PR target/71869 (PPC), PR target/72805 (x86), PR target/70677 (AVR),
+    PR c++/72415.
+
+  * Fix running the libjava testsuite.
+  * Revert fix for PR target/55947, causing PR libstdc++/72813. LP: #1610220.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 05 Aug 2016 15:09:39 +0200
+
+gcc-6 (6.1.1-11ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 03 Aug 2016 21:55:46 +0200
+
+gcc-6 (6.1.1-11) unstable; urgency=medium
+
+  * Update to SVN 20160802 (r238981, 6.1.1) from the gcc-6-branch.
+    - Fix PR target/72767 (AVR), PR target/71151 (AVR), PR c/7652,
+      PR target/71216 (PPC), PR target/72103 (PPC), PR c++/72457, PR c++/71576,
+      PR c++/71833, PR fortran/71883.
+
+  [ Nicolas Boulenguez ]
+  * debian/ada/confirm_debian_bugs.py: Update for GCC 6. Closes: #832799.
+
+  [ Matthias Klose ]
+  * Backport AArch64 Vulcan cost models (Dann Frazier). LP: #1603587.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 03 Aug 2016 21:53:37 +0200
+
+gcc-6 (6.1.1-10ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 24 Jul 2016 20:28:46 +0200
+
+gcc-6 (6.1.1-10) unstable; urgency=medium
+
+  * Update to SVN 20160724 (r238695, 6.1.1) from the gcc-6-branch.
+    - Fix PR libstdc++/71856, PR libstdc++/71320, PR c++/71214,
+      PR sanitizer/71953, PR fortran/71688, PR rtl-optimization/71916,
+      PR debug/71855, PR middle-end/71874, PR target/71493 (PPC),
+      PR rtl-optimization/71634, PR target/71733 (PPC), PR ipa/71624,
+      PR target/71805 (PPC), PR target/70098 (PPC), PR target/71763 (PPC),
+      PR middle-end/71758, PR tree-optimization/71823, PR middle-end/71606,
+      PR tree-optimization/71518, PR target/71806 (PPC), PR target/71720 (PPC),
+      PR middle-end/64516, PR tree-optimization/71264, PR middle-end/71423,
+      PR tree-optimization/71521, PR tree-optimization/71452, PR target/50739,
+      PR tree-optimization/71522, PR c++/55922, PR c++/63151, PR c++/70709,
+      PR c++/70778, PR c++/71738, PR c++/71350, PR c++/71748, PR c++/52746,
+      PR c++/69223, PR c++/71630, PR c++/71913, PR c++/71728, PR c++/71941,
+      PR c++/70822, PR c++/70106, PR c++/67565, PR c++/67579, PR c++/71843,
+      PR c++/70781, PR c++/71896, PR c++/71092, PR c++/71117, PR c++/71495,
+      PR c++/71511, PR c++/71513, PR c++/71604, PR c++/54430, PR c++/71711,
+      PR c++/71814, PR c++/71718, PR c++/70824, PR c++/71909, PR c++/71835,
+      PR c++/71828, PR c++/71822, PR c++/71871, PR c++/70869, PR c++/71054,
+      PR fortran/71807, PR fortran/70842, PR fortran/71764, PR fortran/71623,
+      PR fortran/71783.
+
+  [ Matthias Klose ]
+  * Build-depend on gnat-6 instead of gnat-5 on development distros.
+
+  [ Aurelien Jarno ]
+  * Replace libjava-mips64el-proposed.diff by the corresponding patch
+    taken from trunk.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 24 Jul 2016 19:42:10 +0200
+
+gcc-6 (6.1.1-9ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 05 Jul 2016 15:15:56 +0200
+
+gcc-6 (6.1.1-9) unstable; urgency=medium
+
+  * Update to SVN 20160705 (r237999, 6.1.1) from the gcc-6-branch.
+    - Fix PR fortran/71717, PR libstdc++/71313, PR c/71685, PR c++/71739,
+      PR target/71670 (PPC), PR middle-end/71626, PR target/71559 (x86),
+      PR target/71656 (PPC), PR target/71698 (PPC), PR driver/71651,
+      PR fortran/71687, PR fortran/71704, PR fortran/71705.
+  * Mark cross compilers as M-A: foreign. Addresses: #827136.
+  * On sparc64, configure with --with-cpu-32=ultrasparc, drop the
+    sparc-force-cpu patch. Closes: #809509.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 05 Jul 2016 11:19:50 +0200
+
+gcc-6 (6.1.1-8ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 30 Jun 2016 15:41:06 +0200
+
+gcc-6 (6.1.1-8) unstable; urgency=medium
+
+  * Update to SVN 20160630 (r237878, 6.1.1) from the gcc-6-branch.
+    - Fix PR tree-optimization/71647, PR target/30417 (AVR),
+      PR target/71103 (AVR), PR tree-optimization/71588, PR middle-end/71581,
+      PR c++/71528, PR fortran/70673, PR middle-end/71693.
+
+  [ Aurelien Jarno ]
+  * Apply proposed patch from Matthew Fortune to fix libjava on mips64el.
+
+  [ Matthias Klose ]
+  * Add AArch64 Vulcan cpu support (Dann Frazier). LP: #1594452.
+  * gfortran: Suggest libcoarrays-dev. Closes: #827995.
+  * cpp: Breaks libmagics++-dev (<< 2.28.0-4). Closes: #825278.
+  * Optimize for mips32r2 for o32 (YunQiang Su). Closes: #827801.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 30 Jun 2016 14:12:55 +0200
+
+gcc-6 (6.1.1-7ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 20 Jun 2016 20:27:58 +0200
+
+gcc-6 (6.1.1-7) unstable; urgency=medium
+
+  * Update to SVN 20160620 (r237590, 6.1.1) from the gcc-6-branch.
+    - Fix PR middle-end/71373, PR c/71381, PR libstdc++/71545, PR c/68657,
+      PR sanitizer/71498, PR middle-end/71529, PR target/71103 (AVR),
+      PR target/71554 (x86), PR middle-end/71494, PR c++/71448,
+      PR tree-optimization/71405, PR tree-optimization/71505,
+      PR target/71379 (s390), PR target/71186 (PPC), PR target/70915 (PPC),
+      PR c++/70572, PR c++/71516, PR c/71381.
+  * Fix libgnatprj build to avoid undefined symbols (YunQiang Su).
+    Closes: #826503.
+  * Add build support for tilegx (Helmut Grohne). Closes: #827578.
+  * Drop support for loongson 2f (YunQiang Su). Closes: #827554.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 20 Jun 2016 13:41:44 +0200
+
+gcc-6 (6.1.1-6ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 09 Jun 2016 19:27:27 +0200
+
+gcc-6 (6.1.1-6) unstable; urgency=medium
+
+  * Update to SVN 20160609 (r237267, 6.1.1) from the gcc-6-branch.
+    - Fix PR target/71389 (x86), PR tree-optimization/71259,
+      PR target/70830 (ARM), PR target/67310 (x86), PR c++/71442,
+      PR c++/70847, PR c++/71330, PR c++/71393, PR fortran/69659.
+  * gdc: Fix linking the runtime library. Addresses: #826645.
+  * Fix building libgnatprj on powerpc, and on PIE enabled builds (YunQiang Su).
+    Closes: #826365.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 09 Jun 2016 18:19:42 +0200
+
+gcc-6 (6.1.1-5ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 03 Jun 2016 19:46:59 +0200
+
+gcc-6 (6.1.1-5) unstable; urgency=medium
+
+  * Update to SVN 20160603 (r237075, 6.1.1) from the gcc-6-branch.
+    - Fix PR libstdc++/70762, PR libstdc++/69703, PR libstdc++/69703,
+      PR libstdc++/71038, PR libstdc++/71036, PR libstdc++/71037,
+      PR libstdc++/71005, PR libstdc++/71004, PR libstdc++/70609, PR c/71171,
+      PR middle-end/71279, PR c++/71147, PR c++/71257,
+      PR tree-optimization/70884, PR c++/71210, PR tree-optimization/71031,
+      PR c++/69872, PR c++/71257, PR c++/70344, PR c++/71184, PR fortran/66461,
+      PR fortran/71204, PR libffi/65567, PR c++/71349, PR target/71201,
+      PR middle-end/71371, PR debug/71057, PR target/71056 (ARM32),
+      PR tree-optimization/69068, PR middle-end/71002, PR bootstrap/71071,
+      PR c++/71372, PR c++/70972, PR c++/71166, PR c++/71227, PR c++/60095,
+      PR c++/69515, PR c++/69009, PR c++/71173, PR c++/70522, PR c++/70584,
+      PR c++/70735, PR c++/71306, PR c++/71349, PR c++/71105, PR c++/71147,
+      PR ada/71358, PR ada/71317, PR fortran/71156, PR middle-end/71387.
+  * Fix cross building libgnatprj on i386 targeting 64bit archs (YunQiang Su).
+    Closes: #823126.
+  * Detect hard float for non-linux or non-glibc arm-*-*eabihf builds (Helmut
+    Grohne). Closes: #823894.
+  * Update embedded timestamp setting patch, backported from the trunk.
+  * gccgo: Combine combine gccgo's ld() and ldShared() methods
+    in cmd/go (Michael Hudson-Doyle). LP: #1586872.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 03 Jun 2016 18:58:40 +0200
+
+gcc-6 (6.1.1-4ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 19 May 2016 17:24:36 +0200
+
+gcc-6 (6.1.1-4) unstable; urgency=medium
+
+  * Update to SVN 20160519 (r236478, 6.1.1) from the gcc-6-branch.
+    - Fix PR sanitizer/71160, PR c++/70498, PR target/71161 (x86),
+      PR fortran/70856, PR c++/71100, PR target/71145 (alpha), PR c++/70466,
+      PR target/70860 (nvptx), PR target/70809 (AArch64), PR hsa/70857,
+      PR driver/68463, PR target/70947 (PPC), PR ipa/70760, PR middle-end/70931,
+      PR middle-end/70941, PR tree-optimization/71006, PR target/70830 (ARM),
+      PR fortran/69603, PR fortran/71047, PR fortran/56226, PR ipa/70646.
+  * libgnat{prj,svn}-dev: Don't recommend gnat when building cross compiler
+    packages.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 19 May 2016 18:40:49 +0200
+
+gcc-6 (6.1.1-3ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 12 May 2016 02:33:19 +0200
+
+gcc-6 (6.1.1-3) unstable; urgency=medium
+
+  * Update to SVN 20160511 (r236071, 6.1.1) from the gcc-6-branch.
+    - Fix PR libstdc++/71049, PR middle-end/70877, PR tree-optimization/70876,
+      PR target/70963, PR tree-optimization/70916, PR debug/70935.
+  * Enable gdc for sh4.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 11 May 2016 22:35:33 +0200
+
+gcc-6 (6.1.1-2ubuntu12) yakkety; urgency=medium
+
+  * Fix package replacements with gccgo-6 packages. LP: #1578247, #1578250.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 10 May 2016 14:31:52 +0200
+
+gcc-6 (6.1.1-2) unstable; urgency=medium
+
+  * Update to SVN 20160510 (r236071, 6.1.1) from the gcc-6-branch.
+    - Fix PR tree-optimization/70956, PR sanitizer/70875, PR sanitizer/70342,
+      PR ada/70969, PR ada/70900.
+
+  [ Matthias Klose ]
+  * Call dh_makeshlibs with the --noscripts option when building a
+    cross compiler.
+  * Fix building cross gnat libs when not building the common libs.
+  * Fix building cross mips* multilibs when not building the common libs.
+  * Re-enable gnat build on some architectures for snapshot builds.
+  * Don't build gnat cross compilers on 32bit archs targeting 64bit targets.
+    Addresses: #823126.
+  * Avoid empty architecture lists in build dependencies. Closes: #823280.
+  * Tighten debhelper build dependency for cross build dependencies.
+  * Allow build dependencies for musl configurations (Helmut Grohne).
+    Closes: #823769.
+  * Fix dependency resolution for libraries not built anymore from
+    this source package.
+
+  [ Samuel Thibault ]
+  * patches/ada-hurd.diff: Fix Get_Page_Size type.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 10 May 2016 13:34:49 +0200
+
+gcc-6 (6.1.1-1) unstable; urgency=medium
+
+  * GCC 6.1.0 release.
+    - Fix PR bootstrap/70704, PR tree-optimization/70780, PR libgfortran/70684,
+      PR middle-end/70626, PR java/70839, PR target/70858, PR ada/70759,
+      PR ada/70786, PR c++/70540, PR middle-end/70626.
+  * Update to SVN 20160430 (r235678, 6.1.1) from the gcc-6-branch.
+    - Fix PR middle-end/70680, PR target/70750 (x86), PR ipa/70785,
+      PR sanitizer/70712, PR target/70728 (x86).
+    - Don't encode the minor version in the gcj abi version.
+
+  [ Aurelien Jarno ]
+  * Apply proposed patch for PR target/68273 (Wrong code on mips/mipsel due to
+    (invalid?) peeking at alignments in function_arg) on mips and mipsel.
+
+  [ Matthias Klose ]
+  * Always configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Stop building libcc1 and libgccjit0, when not building common libs.
+  * Rename libgccjit-5-dbg to libgccjit0-dbg.
+  * Fix libjava testsuite with dejagnu 1.6, taken from the trunk.
+  * Allow embedded timestamps by C/C++ macros to be set externally (Eduard
+    Sanou).
+  * Add missing libstdc++ symbol to symbols file.
+  * libstdc++-doc: Ignore warnings about formulas and long identifiers in
+    man pages.
+  * Default the 32bit x86 architectures to i686, keep i585 symlinks.
+    See https://lists.debian.org/debian-devel/2015/09/msg00589.html
+  * Build-depend on debhelper (>= 9) and dpkg-dev (>= 1.17.14).
+  * Update gdc to the gdc-6 branch 20160430.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 30 Apr 2016 13:31:12 +0200
+
+gcc-6 (6.1.1-0ubuntu12) yakkety; urgency=medium
+
+  * GCC 6.1.0 release.
+    - Fix PR bootstrap/70704, PR tree-optimization/70780, PR libgfortran/70684.
+  * Update to SVN 20160428 (r235548, 6.1.1) from the gcc-6-branch.
+    - Fix PR middle-end/70680, PR target/70750 (x86), PR ipa/70785,
+      PR sanitizer/70712, PR target/70728 (x86).
+    - Don't encode the minor version in the gcj abi version.
+  * Always configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Stop building libcc1 and libgccjit0, when not building common libs.
+  * Rename libgccjit-5-dbg to libgccjit0-dbg.
+  * Fix libjava testsuite with dejagnu 1.6, taken from the trunk.
+  * Re-enable running the tests.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 28 Apr 2016 10:33:38 +0200
+
+gcc-6 (6.0.1-2ubuntu12) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 23 Apr 2016 18:24:49 +0200
+
+gcc-6 (6.0.1-2) unstable; urgency=medium
+
+  * GCC 6.1 release candidate 2.
+  * Update gdc to the trunk 20160423.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 23 Apr 2016 17:56:52 +0200
+
+gcc-6 (6.0.1-1ubuntu11) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 15 Apr 2016 18:38:06 +0200
+
+gcc-6 (6.0.1-1) experimental; urgency=medium
+
+  * GCC 6 release candidate 1.
+
+  [ Michael Hudson-Doyle ]
+  * cmd/go: deduplicate gccgo afiles by package path, not *Package. LP: #1566552.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 15 Apr 2016 18:32:25 +0200
+
+gcc-6 (6-20160405-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160405.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 05 Apr 2016 17:10:35 +0200
+
+gcc-6 (6-20160319-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160319.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 19 Mar 2016 12:17:24 +0100
+
+gcc-6 (6-20160313-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160313.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 13 Mar 2016 10:19:12 +0100
+
+gcc-6 (6-20160227-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160227.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 27 Feb 2016 11:02:40 +0100
+
+gcc-6 (6-20160225-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160225.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 25 Feb 2016 02:09:51 +0100
+
+gcc-6 (6-20160225-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160225.
+  * Update gdc to the trunk 20160224.
+  * Install missing architecture specific plugin header files.
+  * Fix PR target/69885, bootstrap error on m68k.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 25 Feb 2016 02:00:57 +0100
+
+gcc-6 (6-20160220-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160220.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 20 Feb 2016 04:38:26 +0100
+
+gcc-6 (6-20160206-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160206.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 06 Feb 2016 12:07:51 +0100
+
+gcc-6 (6-20160205-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160205.
+    - Fix PR tree-optimization/69320. Closes: #811921.
+    - Fix PR c++/68782. Closes: #812287.
+    - Fix PR tree-optimization/69328. Closes: #812247.
+    - Fix PR target/69421. Closes: #812246.
+    - Fix PR c++/69379. Closes: #812068.
+    - Fix PR lto/69393. Closes: #812062.
+    - Fix PR tree-optimization/69166. Closes: #812061.
+  * Update gdc to the trunk 20160205.
+    - Fix data corruption bug when passing around longdoubles.
+      Closes: #812080.
+  * Add more conflicts to GCC 5's debug and doc packages. Closes: #813081.
+  * Fix dependency generation for armel/armhf multilib cross targets.
+  * Fix libc dependency generation for multilib cross targets.
+  * Build libitm on alpha, s390x, sh4, sparc64.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 05 Feb 2016 18:08:37 +0100
+
+gcc-6 (6-20160122-1) experimental; urgency=medium
+
+  * Fix gnat build failure on KFreeBSD (Steven Chamberlain). Closes: #811372.
+  * Fix dependencies on target libraries which are not built anymore
+    from this source.
+  * Bump libmpx soname. Closes: #812084.
+  * Apply proposed patch for PR target/69129. Closes: #810081.
+  * Apply proposed patch for PR go/66904, pass linker flags from
+    "#cgo pkg-config:" directives (Michael Hudson).
+  * Configure with --enable-fix-cortex-a53-843419 on AArch64.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 22 Jan 2016 13:33:19 +0100
+
+gcc-6 (6-20160117-1ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160117.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 17 Jan 2016 12:34:33 +0100
+
+gcc-6 (6-20160117-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160117.
+  * Update gdc to the trunk 20160115.
+  * Update libgnatvsn/libgnatprj conflicts. Closes: #810809.
+  * Fix gnat build failures on the Hurd and KFreeBSD (Svante Signell).
+    Closes: #811063.
+  * Build libstdc++-6-doc with a fixed doxygen. Closes: #810717.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 17 Jan 2016 12:14:39 +0100
+
+gcc-6 (6-20160109-1ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160109.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 09 Jan 2016 12:03:28 +0100
+
+gcc-6 (6-20160109-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160109.
+  * Install new header file pkuintrin.h. Closes: #809807.
+  * Fix libcc1-0 dependency for cross compilers.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 09 Jan 2016 11:49:50 +0100
+
+gcc-6 (6-20160105-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160105.
+  * Install new header file pkuintrin.h. Closes: #809807.
+  * Fix libgcc1-0 dependency for cross compilers.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 02 Jan 2016 15:55:27 +0100
+
+gcc-6 (6-20160103-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160101.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 03 Jan 2016 12:47:13 +0100
+
+gcc-6 (6-20160101-0ubuntu2) xenial; urgency=medium
+
+  * Bump the libgcj version.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 02 Jan 2016 15:55:27 +0100
+
+gcc-6 (6-20160101-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160101.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 01 Jan 2016 21:40:43 +0100
+
+gcc-6 (6-20151221-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151220.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 21 Dec 2015 15:56:05 +0100
+
+gcc-6 (6-20151220-1ubuntu1) xenial; urgency=medium
+
+  * Test build for xenial.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 20 Dec 2015 14:11:14 +0100
+
+gcc-6 (6-20151220-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151220.
+  * Update libstdc++-dbg conflicts. Closes: #807885.
+  * Set target tools and build dependencies for cross builds.
+  * Relax gcj-6-{jre,jre-headless,jdk} dependencies on libgcj16.
+  * Fix cross build issues.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 20 Dec 2015 13:46:12 +0100
+
+gcc-6 (6-20151219-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151219.
+  * Update libstdc++-dbg conflicts. Closes: #807885.
+  * Set target tools and build dependencies for cross builds.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 19 Dec 2015 10:17:25 +0100
+
+gcc-6 (6-20151213-1ubuntu2) xenial; urgency=medium
+
+  * Test build for xenial.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 13 Dec 2015 15:04:49 +0100
+
+gcc-6 (6-20151213-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151213.
+  * Update the ada-kfreebsd and ada-m68k patches.
+  * Fix cross-building without having the common cross libraries installed.
+  * Allow unstripped, non-optimized debug builds with setting DEB_BUILD_OPTIONS
+    including gccdebug.
+  * Remove obsolete libgccmath packaging support.
+  * Define SONAME macros whether the libraries are built or not.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 13 Dec 2015 13:24:55 +0100
+
+gcc-6 (6-20151211-1ubuntu3) xenial; urgency=medium
+
+  * Test build for xenial.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 11 Dec 2015 17:42:35 +0100
+
+gcc-6 (6-20151211-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151211.
+  * Update gnat and gdc patches, re-enable gnat and gdc.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 11 Dec 2015 12:35:03 +0100
+
+gcc-6 (6-20151210-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from 20151210.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 10 Dec 2015 22:09:13 +0100
+
+gcc-5 (5.3.1-3ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+    - Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 08 Dec 2015 02:21:55 +0100
+
+gcc-5 (5.3.1-3)  unstable; urgency=medium
+
+  * Update to SVN 20151207 (r231361, 5.3.1) from the gcc-5-branch.
+  * Remove upstreamed chunks from the ada-kfreebsd patch.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 08 Dec 2015 02:10:51 +0100
+
+gcc-5 (5.3.1-2ubuntu2) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+    - Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 07 Dec 2015 00:00:19 +0100
+
+gcc-5 (5.3.1-2) unstable; urgency=medium
+
+  * Update to SVN 20151206 (r231339, 5.3.1) from the gcc-5-branch.
+  * Re-enable building gdc/libphobos, fixing the profiled build.
+  * Fix PR sanitizer/67899, build failure on sparc/sparc64.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 06 Dec 2015 19:15:46 +0100
+
+gcc-5 (5.3.1-1ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+    - Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Dec 2015 11:40:27 +0100
+
+gcc-5 (5.3.1-1) unstable; urgency=medium
+
+  * Update to SVN 20151205 (r231314, 5.3.1) from the gcc-5-branch.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Dec 2015 11:36:26 +0100
+
+gcc-5 (5.3.1-0ubuntu2) xenial; urgency=medium
+
+  * Update libgcc symbols file.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 04 Dec 2015 18:52:20 +0100
+
+gcc-5 (5.3.1-0ubuntu1) xenial; urgency=medium
+
+  * Update to SVN 20151204 (r231267, 5.3.1) from the gcc-5-branch.
+  * Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 04 Dec 2015 15:04:01 +0100
+
+gcc-5 (5.3.0-3) unstable; urgency=medium
+
+  * Update libgcc symbols file.
+  * Restore libgcc.symbols.aebi.
+  * Disabled profiled bootstraps for backports.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Dec 2015 07:50:48 +0100
+
+gcc-5 (5.3.0-1) experimental; urgency=medium
+
+  * GCC 5.3 release.
+    - Fix PR libstdc++/65142 (CVE-2015-5276).
+  * Update gdc to the gcc-5 branch 20151130.
+  * Enable the profiled bootstrap on amd64, arm64, armel armhf, i386, powerpc,
+    ppc64, ppc64el, s390x, x32 (excluding builds from the Linaro branch).
+  * Move test summary into the gcc-test-results package.
+  * Simplify libatomic, libcilkrts, libgcc, libgfortran, libgomp, libitm,
+    libmpx, libquadmath symbols files using versioned symbol references.
+    Closes: #806784.
+  * Only build the hppa64 cross compiler when either building the native compiler,
+    or when cross building the native compiler. Closes: #806479.
+  * Configure staged build with --enable-linker-build-id.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 04 Dec 2015 12:01:04 +0100
+
+gcc-5 (5.2.1-27ubuntu1) xenial; urgency=medium
+
+  * Configure with --enable-default-pie on s390x.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 30 Nov 2015 00:49:40 +0100
+
+gcc-5 (5.2.1-27) unstable; urgency=medium
+
+  * Update to SVN 20151129 (r231053, 5.2.1) from the gcc-5-branch.
+  * Don't strip cc1plus when shipping with unstripped frontends.
+  * Relax libgnatvsn5-dev-*-cross and libgnatprj5-dev-*-cross dependencies
+    on gnat-5-*-linux-gnu.
+  * Fix setting the explicit libc dependency for cross builds.
+  * Don't build m4-nofpu multilibs on sh4, install the default multilib
+    into the standard location.
+  * Stop building gnat on mips64, see https://gcc.gnu.org/PR65337 (#806370).
+  * Update the patch for PR go/67508 and re-enable Go on sparc and sparc64.
+  * Fix gnat sparc/sparc64 architecture detection.
+  * Update libgcc and libstdc++ symbols files.
+  * Don't ship the gcov tools in the gcc-hppa64-linux-gnu package.
+  * Run the autoconf generation in parallel.
+  * Add --enable-default-pie option to GCC configure, taken from the trunk.
+  * Enable gnat for m68k cross builds.
+  * Link gnat tools, gnat libs and libgccjit with the defaults LDFLAGS.
+  * Skip non-default multilib and libstdc++-v3 debug builds in bootstrap builds.
+  * Ship an empty debian/rules.parameters in the gcc-5-source package.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 29 Nov 2015 23:48:58 +0100
+
+gcc-5 (5.2.1-26ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 25 Nov 2015 17:29:15 +0100
+
+gcc-5 (5.2.1-26) unstable; urgency=medium
+
+  * Update to SVN 20151125 (r230897, 5.2.1) from the gcc-5-branch.
+  * Fix the rtlibs stage build. Closes: #806186.
+  * Fix packaging the cross libphobos package.
+  * Build the hppa64 cross compiler on x86 architectures.
+  * gcc-5-hppa64-linux-gnu: Stop providing unversioned tools using
+    alternatives. Build a gcc-hppa64-linux-gnu package instead.
+  * Split out a gcc-5-test-results package from g++-5, allowing a post
+    build analysis, and reducing the size of the g++-5 package.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 25 Nov 2015 20:33:08 +0100
+
+gcc-5 (5.2.1-25ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 23 Nov 2015 06:06:11 +0100
+
+gcc-5 (5.2.1-25) unstable; urgency=medium
+
+  * Update to SVN 20151123 (r230734, 5.2.1) from the gcc-5-branch.
+  * Fix libgcc4-dbg dependency on libgcc4. Closes: #805839.
+  * Fix building epoch prefixed cross packages.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 23 Nov 2015 05:48:00 +0100
+
+gcc-5 (5.2.1-24ubuntu3) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 21 Nov 2015 12:21:06 +0100
+
+gcc-5 (5.2.1-24) unstable; urgency=medium
+
+  * Update to SVN 20151121 (r230703, 5.2.1) from the gcc-5-branch.
+  * Fix PR libstdc++/56158, taken from the trunk. Closes: #804521. LP: #1514309.
+  * Don't try to build a gnat cross compiler when there is no gnat compiler
+    for the build architecture.
+  * Update gnat build dependencies for backports.
+  * Parallelize building documentation and parallelize the packaging step.
+  * Update the Linaro support to the 5-2015.11 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 21 Nov 2015 11:22:16 +0100
+
+gcc-5 (5.2.1-23ubuntu1) xenial; urgency=medium
+
+  * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Oct 2015 12:18:49 +0100
+
+gcc-5 (5.2.1-23) unstable; urgency=medium
+
+  * Update to SVN 20151028 (r229478, 5.2.1) from the gcc-5-branch.
+
+  [ Matthias Klose ]
+  * Update the Linaro support to the 5-2015.10 snapshot.
+  * gcj: On ppc64el, use the same jvm archdir name as for openjdk (ppc64le).
+  * gcj: Fix priority of java alternatives. Closes: #803055.
+  * gnat-5: Reintroduce the unversioned gnatgcc name. Closes: #802838.
+
+  [ Aurelien Jarno ]
+  * Replace proposed patch for PR rtl-optimization/67736 by the one
+    committed on trunk.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 28 Oct 2015 10:36:54 +0100
+
+gcc-5 (5.2.1-22ubuntu5) xenial; urgency=medium
+
+  * Revert the fix for PR ipa/67056, causing an ICE.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 23 Oct 2015 19:13:51 +0200
+
+gcc-5 (5.2.1-22ubuntu4) xenial; urgency=medium
+
+  * Update to SVN 20151022 (r229176, 5.2.1) from the gcc-5-branch.
+  * Fix PR ipa/67056, taken from the trunk. Closes: #788299.
+  * Target POWER8 on ppc64el.
+  * Again, don't strip the compiler binaries for more verbose ICEs.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 22 Oct 2015 17:32:47 +0200
+
+gcc-5 (5.2.1-22ubuntu2) wily; urgency=medium
+
+  * Strip the compiler binaries for the release.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 16 Oct 2015 12:17:17 +0200
+
+gcc-5 (5.2.1-22ubuntu1) wily; urgency=medium
+
+  * gcj: On ppc64el, use the same jvm archdir name as for openjdk (ppc64le).
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 11 Oct 2015 10:13:52 +0200
+
+gcc-5 (5.2.1-22) unstable; urgency=medium
+
+  * Update to SVN 20151010 (r228681, 5.2.1) from the gcc-5-branch.
+    - Fix PR libstdc++/65913, PR libstdc++/67173, PR libstdc++/67747,
+      PR c/67730, PR middle-end/67563, PR lto/67699, PR tree-optimization/67821,
+      PR debug/58315.
+
+  [ Matthias Klose ]
+  * Restore the work around for PR libstdc++/65913, still needed at least
+    for powerpc.
+  * Rename gcc-5-hppa64 to gcc-5-hppa64-linux-gnu, update (build) dependency
+    on binutils. Closes: #800563.
+  * Adjust setting DH_COMPAT for dh_movefiles with updated debhelper supporting
+    globbing of arguments. Closes: #800250.
+  * Build-depend on gnat-5 instead of gnat-4.9.
+
+  [ Aurelien Jarno ]
+  * Do not Use --with-mips-plt on mips and mipsel. Closes: #799811.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 10 Oct 2015 22:17:09 +0200
+
+gcc-5 (5.2.1-21ubuntu2) wily; urgency=medium
+
+  * Restore the work around for PR libstdc++/65913, still needed at least
+    for powerpc.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 04 Oct 2015 02:21:30 +0200
+
+gcc-5 (5.2.1-21ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 03 Oct 2015 21:30:44 +0200
+
+gcc-5 (5.2.1-21) unstable; urgency=medium
+
+  * Update to SVN 20151003 (r228449, 5.2.1) from the gcc-5-branch.
+  * Fix building gnat. Closes: #800781.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 03 Oct 2015 17:28:45 +0200
+
+gcc-5 (5.2.1-20ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 02 Oct 2015 11:35:22 +0200
+
+gcc-5 (5.2.1-20) unstable; urgency=medium
+
+  * Update to SVN 20151002 (r228373, 5.2.1) from the gcc-5-branch.
+  * Fix packaging the ada cross library packages.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 02 Oct 2015 10:24:38 +0200
+
+gcc-5 (5.2.1-19ubuntu1) wily; urgency=medium
+
+  * Configure --with-arch=zEC12 on s390x Ubuntu.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 30 Sep 2015 22:55:14 +0200
+
+gcc-5 (5.2.1-19) unstable; urgency=medium
+
+  * Update to SVN 20150930 (r228302, 5.2.1) from the gcc-5-branch.
+    - Fix PR ipa/66424. Closes: #800318.
+
+  [ Matthias Klose ]
+  * Update the Linaro support to the 5-2015.09 snapshot.
+  * Fix PR libstdc++/67707, taken from the trunk. LP: #1499564.
+  * Ship libgcj.spec in gcj-5 instead of gcj-5-jdk. Closes: #800010.
+  * gcj-5: Suggest gcj-5-jdk.
+  * Fix base dependency for ada cross library packages.
+  * Add ${shlibs:Depends} for libgnatvsn and libgnatprj.
+  * Link lrealpath.o into libgnatprj. Closes: #800045.
+  * libgnat{svn,prj}-dev: For cross builds, move adainclude and adalib files
+    into the gcc libdir.
+  * Default to POWER8 on ppc64el.
+  * armv8: Fix slt lda missing conditional code (taken from the trunk).
+  * Fix lintian pre-depends-directly-on-multiarch-support warnings.
+
+  [ Aurelien Jarno ]
+  * Apply proposed patch for PR rtl-optimization/67736 when building for
+    mips64 or mips64el. Closes: #800321.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 30 Sep 2015 20:36:50 +0200
+
+gcc-5 (5.2.1-18ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 23 Sep 2015 03:10:37 +0200
+
+gcc-5 (5.2.1-18) unstable; urgency=medium
+
+  * Update to SVN 20150922 (r228023, 5.2.1) from the gcc-5-branch.
+
+  [ Matthias Klose ]
+  * gcc-5-plugin-dev: Depend on libmpc-dev. Closes: #798997.
+  * Fix PR libstdc++/65913, taken from the trunk. Closes: #797577.
+
+  [ YunQiang Su ]
+  * Build again the gnat-5-sjlj package. Closes: #798782.
+  * Fix gnat cross builds, and cross building gnat.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 22 Sep 2015 23:15:17 +0200
+
+gcc-5 (5.2.1-17ubuntu5) wily; urgency=medium
+
+  * Don't assume --push-state/--pop-state being available for every linker.
+    LP: #1496743.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 22 Sep 2015 20:54:29 +0200
+
+gcc-5 (5.2.1-17ubuntu4) wily; urgency=medium
+
+  * gcc-5-plugin-dev: Depend on libmpc-dev. Closes: #798997.
+  * Work around PR c++/65913, link with -latomic when linking with -lstdc++.
+    Closes: #797577.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 15 Sep 2015 17:57:31 +0200
+
+gcc-5 (5.2.1-17ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 11 Sep 2015 03:24:48 +0200
+
+gcc-5 (5.2.1-17) unstable; urgency=medium
+
+  * Update to SVN 20150911 (r227671, 5.2.1) from the gcc-5-branch.
+    - Fix PR c++/67369, ICE on valid code. LP: #1489173.
+
+  [ Matthias Klose ]
+  * Build-depend on linux-libc-dev [m68k] for gcc and gcc-snapshot builds.
+    Closes: #796906.
+  * Don't ignore anymore bootstrap comparison failures on sh4. Closes: #796939.
+  * Fix stage1 cross build for KFreeBSD. Closes: #796901.
+  * libgo: Fix PR go/67508, rewrite lfstack packing/unpacking to look more
+    like that in Go (Michael Hudson). LP: #1472650.
+  * Fix PR target/67143 (AArch64), ICE on valid code. LP: #1481333.
+
+  [ Aurelien Jarno ]
+  * Use --with-mips-plt on mips*.
+  * Build for R2 ISA on mips, mips64 and mips64el.
+  * Optimize for R2 ISA on mipsel.
+  * Only apply mips-fix-loongson2f-nop on mipsel.
+
+  [ YunQiang Su ]
+  * Fix running the acats tests. Closes: #798531.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 11 Sep 2015 03:17:20 +0200
+
+gcc-5 (5.2.1-16ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 03 Sep 2015 16:00:26 +0200
+
+gcc-5 (5.2.1-16) unstable; urgency=medium
+
+  * Update to SVN 20150903 (r227431, 5.2.1) from the gcc-5-branch.
+    - Backport the filesystem TS library.
+  * libstdc++-dev: Install libstdc++fs.a.
+  * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Apply proposed patch for PR target/67211 (ppc64el).
+  * libgo-dev: Install libgolibbegin.a.
+  * Apply proposed patch for PR target/67280 (ARM). LP: #1482320.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 03 Sep 2015 12:16:15 +0200
+
+gcc-5 (5.2.1-15ubuntu5) wily; urgency=medium
+
+  * Fix libstdc++-breaks (add version for the clustalx breaks).
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 25 Aug 2015 17:56:26 +0200
+
+gcc-5 (5.2.1-15ubuntu3) wily; urgency=medium
+
+  * Update to SVN 20150825 (r227166, 5.2.1) from the gcc-5-branch.
+    - Backport the filesystem TS library.
+  * libstdc++-dev: Install libstdc++fs.a.
+  * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Apply proposed patch for PR target/67211 (ppc64el).
+  * libgo-dev: Install libgolibbegin.a.
+  * Add the PR libstdc++/66145 breaks for wily.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 25 Aug 2015 15:56:11 +0200
+
+gcc-5 (5.2.1-15ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 09 Aug 2015 13:20:15 +0200
+
+gcc-5 (5.2.1-15) unstable; urgency=medium
+
+  * Update to SVN 20150808 (r226731, 5.2.1) from the gcc-5-branch.
+  * Adjust libstdc++-breaks: Break libantlr-dev instead of antlr;
+    adjust libreoffice version (closes: #794203), drop xxsd break (see
+    #793289), remove cython breaks (closes: #794511), add breaks for
+    packages built using cython (chemps2, fiona, guiqwt, htseq, imposm,
+    pysph, pytaglib, python-scipy, python-sfml, rasterio).
+  * Ignore missing libstdc++ symbols on sparc64 (work around #792204).
+
+ -- Matthias Klose <doko@debian.org>  Sat, 08 Aug 2015 11:18:24 +0200
+
+gcc-5 (5.2.1-14) unstable; urgency=high
+
+  * Fix libstdc++6 breaks.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 31 Jul 2015 04:12:08 +0200
+
+gcc-5 (5.2.1-13) unstable; urgency=high
+
+  * Upload to unstable (https://wiki.debian.org/GCC5). See also
+    https://lists.debian.org/debian-devel-announce/2015/07/msg00000.html
+  * Update to SVN 20150730 (r226411, 5.2.1) from the gcc-5-branch.
+    - Fix PR libstdc++/67015. Closes: #793784.
+  * Fix version macros in the plugin-header.h header. Closes: #793478.
+  * libstdc++6: Add breaks for issues tagged with gcc-pr66145.
+  * Add libcpprest2.4 to libstdc++6 breaks. Closes: #784655.
+  * Fix PR c++/66857, taken from the trunk.
+  * Ignore differences in gcc/real.o in the bootstrap build for
+    sh*-*linux-gnu targets.  According to PR 67002, "A rare indeterminacy
+    of the register choice.  Both codes are valid.  It seems very hard to
+    find where has this indeterminacy come from". Suggested by Adrian
+    Glaubitz.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 30 Jul 2015 21:51:25 +0200
+
+gcc-5 (5.2.1-12ubuntu2) wily; urgency=medium
+
+  * Update to SVN 20150729 (r226354, 5.2.1) from the gcc-5-branch.
+    - Fix PR libstdc++/67015. Closes: #793784.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 29 Jul 2015 17:59:18 +0200
+
+gcc-5 (5.2.1-12ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 22 Jul 2015 21:17:54 +0200
+
+gcc-5 (5.2.1-12) experimental; urgency=medium
+
+  * Update to SVN 20150723 (r226105, 5.2.1) from the gcc-5-branch.
+  * Fix PR libstdc++/66145, std::ios_base::failure objects thrown from
+    libstdc++.so using the gcc4-compatible ABI.
+    Just build src/c++11/functexcept.cc using the new ABI. It will break
+    code, which will be handled in the archive by adding Breaks for the
+    affected packages.  Third party code using such code will need a rebuild.
+  * Remove the work around to build with -O1 on sh4.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 23 Jul 2015 14:18:44 +0200
+
+gcc-5 (5.2.1-11ubuntu1) wily; urgency=medium
+
+  * Configure without --disable-libstdcxx-dual-abi.
+  * Configure with --with-default-libstdcxx-abi=new.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 17 Jul 2015 08:14:56 +0200
+
+gcc-5 (5.2.1-1ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 16 Jul 2015 16:58:50 +0200
+
+gcc-5 (5.2.1-1) experimental; urgency=medium
+
+  * GCC 5.2 release.
+  * Update to SVN 20150716 (r225880, 5.2.1) from the gcc-5-branch.
+  * Require version 5.2 for the libstdc++6 cxx symbols.
+  * Ignore missing libstdc++ symbols on sparc64 (work around #792204).
+  * Go escape analysis: analyze multiple result type assertions (taken
+    from the trunk).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 16 Jul 2015 15:35:44 +0200
+
+gcc-5 (5.1.1-14ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 11 Jul 2015 13:00:26 +0200
+
+gcc-5 (5.1.1-14) unstable; urgency=medium
+
+  * Update to SVN 20150711 (r225710, 5.1.1) from the gcc-5-branch.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 11 Jul 2015 11:57:19 +0200
+
+gcc-5 (5.1.1-13ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 07 Jul 2015 14:29:11 +0200
+
+gcc-5 (5.1.1-13) unstable; urgency=medium
+
+  * Update to SVN 20150706 (r225471, 5.1.1) from the gcc-5-branch.
+  * Update libasan symbol files.
+  * Configure --with-fp-32=xx on all mips targets, setting MIPS O32 default
+    to FPXX (YunQiang Su). Closes: #789612.
+  * Update libgccjit symbol file.
+  * Add x32 symbols files for libgcc1 and libstdc++6.
+  * libgccjit0: Add breaks for python-gccjit and python3-gccjit.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 06 Jul 2015 19:55:08 +0200
+
+gcc-5 (5.1.1-12ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 23 Jun 2015 12:53:45 +0200
+
+gcc-5 (5.1.1-12) unstable; urgency=medium
+
+  * Update to SVN 20150622 (r224724, 5.1.1) from the gcc-5-branch.
+  * Update symbols files for mips64 libatomic and libstdc++ (YunQiang Su).
+    Closes: #788990.
+  * Fix "empty-binary-package" lintian warnings.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 22 Jun 2015 14:37:49 +0200
+
+gcc-5 (5.1.1-11ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 17 Jun 2015 14:38:38 +0200
+
+gcc-5 (5.1.1-11) unstable; urgency=medium
+
+  * Update to SVN 20150616 (r224519, 5.1.1) from the gcc-5-branch.
+  * gccgo: escape: Analyze binary expressions (taken from the trunk).
+  * Explicitly build with -Wl,--no-relax on alpha again.
+  * Build with -O1 on sh4 (try to work around PR target/66358).
+
+ -- Matthias Klose <doko@debian.org>  Tue, 16 Jun 2015 16:11:59 +0200
+
+gcc-5 (5.1.1-10) unstable; urgency=medium
+
+  * Update to SVN 20150613 (r224454, 5.1.1) from the gcc-5-branch.
+  * Make removal of byte-compiled libstdc++ pretty printer files more
+    robust. Closes: #787630.
+  * Fix mips 32bit (o32) multilib builds (YunQiang Su).
+  * Build target libraries with -Wl,-z,relro.
+  * Build libstdc++6 when building the common libraries.
+  * Fix a bunch of lintian warnings.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 13 Jun 2015 12:59:17 +0200
+
+gcc-5 (5.1.1-9ubuntu2) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 03 Jun 2015 01:02:23 +0200
+
+gcc-5 (5.1.1-9) unstable; urgency=medium
+
+  * Update to SVN 20150602 (r224029, 5.1.1) from the gcc-5-branch.
+  * Remove byte-compiled libstdc++ pretty printer files on upgrade.
+    Closes: #785939.
+  * Fix dangling libgccjit.so symlink.
+  * Fix base dependency for rtlibs stage builds.
+  * Fix build failure of the hppa64 cross compiler, introduced by the
+    gnat cross patches. Closes: #786692.
+  * Update README.source (Michael Vogt).
+  * libgo: syscall.Sendfile(): Apply proposed patch for PR go/66378.
+    (Michael Vogt). LP: #1460530.
+  * Set CC and CXX matching the same GCC version for the stage1 build.
+  * Work around PR go/66368, build libgo with -fno-stack-protector.
+    LP: #1454183.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 03 Jun 2015 00:49:41 +0200
+
+gcc-5 (5.1.1-8ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 28 May 2015 12:51:48 +0200
+
+gcc-5 (5.1.1-8) unstable; urgency=medium
+
+  * Update to SVN 20150528 (r223816, 5.1.1) from the gcc-5-branch.
+  * Set the priorities of the *-dev-*-cross packages to extra.
+  * Prepare to change the base dependency for *-cross packages.
+  * Fix dependencies for stage1 and stage2 builds.
+  * Relax dependencies on binary indep *-dev-*-cross packages.
+  * Disable building gdc on sh4 (bootstrap comparison failure).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 28 May 2015 15:51:00 +0200
+
+gcc-5 (5.1.1-7) unstable; urgency=medium
+
+  * Update to SVN 20150522 (r223579, 5.1.1) from the gcc-5-branch.
+  * Add description for the ada-gnattools-cross patch (YunQiang Su).
+  * Provide a rtlibs stage to build a subset of target library packages.
+  * Make symbols file symlinking for cross builds more robust.
+  * Prefer gnatgcc-5 over gnatgcc when building native packages.
+  * Various fixes to build a gnat cross compiler:
+    - Fix dependencies of packages.
+    - Fix building libgnatprj and libgnatvsn (still needed to figure
+      out if these are target or host libraries).
+  * Fix building cross compilers with dpkg 1.18.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 22 May 2015 18:20:01 +0200
+
+gcc-5 (5.1.1-6ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+  * Fix dependencies for stage1 and stage2 builds.
+  * Disable building gdc on sh4.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 19 May 2015 18:29:02 +0200
+
+gcc-5 (5.1.1-6) unstable; urgency=medium
+
+  * Update to SVN 20150519 (r223346, 5.1.1) from the gcc-5-branch.
+  * Don't build gdc-multilib on armel.
+  * Remove old CFLAGS/LDFLAGS settings to build gdc.
+  * Remove reference to .ico file in NEWS.html.
+  * Fix gcc's dependency on libcc1-0 for native builds.
+  * Fix stripping the rpath when cross-building cross compilers.
+  * Remove work arounds to build 64bit multilibs on 32bit targets,
+    now properly fixed upstream.
+  * Partially apply patches to build a gnat cross compiler (submitted
+    by YunQiang Su).
+    - gnatmake: Call the versioned gnatbind and gnatlink commands.
+      Closes: #782257.
+    - Allow libgnatprj and libgnatvsn to cross build. Addresses: #783372.
+    - New patch ada-gnattools-cross.diff (no documentation).
+  * Backport patch for gccgo:
+    - gccgo: If unary & does not escape, the var does not escape.
+  * Apply the backported patches for the go escape analysis. Need to
+    be enabled with -fgo-optimize-alloc (this option may go away again).
+  * Re-enable running the tests.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 19 May 2015 10:33:40 +0200
+
+gcc-5 (5.1.1-5ubuntu4) wily; urgency=medium
+
+  * Update to SVN 20150513 (r223155, 5.1.1) from the gcc-5-branch.
+  * Don't build gdc-multilib on armel.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 13 May 2015 14:36:20 +0200
+
+gcc-5 (5.1.1-5ubuntu3) wily; urgency=medium
+
+  * Fix gnat build dependencies.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 10 May 2015 02:46:32 +0200
+
+gcc-5 (5.1.1-5ubuntu2) wily; urgency=medium
+
+  * Update to SVN 20150509 (r222970, 5.1.1) from the gcc-5-branch.
+  * Fix gotools configury.
+  * Configure with
+      --disable-libstdcxx-dual-abi --with-default-libstdcxx-abi=c++98
+    While libstdc++ provides a dual ABI to support both the c++98 and c++11
+    ABI, there is no committment on compatibility of the old experimental
+    c++11 ABI from GCC 4.9 and the stable c++11 ABI in GCC 5.
+    Closes: #784655.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 09 May 2015 19:24:57 +0200
+
+gcc-5 (5.1.1-5ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 05 May 2015 17:52:14 +0200
+
+gcc-5 (5.1.1-5) unstable; urgency=medium
+
+  * Update to SVN 20150507 (r222873, 5.1.1) from the gcc-5-branch.
+  * Fix 32bit libstdc++ symbols files for kfreebsd-amd64.
+  * libx32phobos-dev: Don't depend on libx32z-dev, when not available.
+  * Fix gotools configury.
+  * Configure with
+      --disable-libstdcxx-dual-abi --with-default-libstdcxx-abi=c++98
+    While libstdc++ provides a dual ABI to support both the c++98 and c++11
+    ABI, there is no committment on compatibility of the old experimental
+    c++11 ABI from GCC 4.9 and the stable c++11 ABI in GCC 5.
+    Closes: #784655.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 08 May 2015 18:48:49 +0200
+
+gcc-5 (5.1.1-4) unstable; urgency=medium
+
+  * Update to SVN 20150503 (r222751, 5.1.1) from the gcc-5-branch.
+    - Fix build failure on alpha.
+  * Fix applying the cross-biarch patch for stage1 builds.
+  * Fix libstdc++ symbols files for kfreebsd-amd64.
+  * Remove libn32phobos-5-dev from the control file.
+  * Really disable gnat on x32.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 02 May 2015 19:18:57 +0200
+
+gcc-5 (5.1.1-3) unstable; urgency=high
+
+  * Update to SVN 20150430 (r222660, 5.1.1) from the gcc-5-branch.
+  * Fix libstdc++ symbols files for kfreebsd-i386.
+  * PR libstdc++/62258, fix for std::uncaught_exception, taken from the trunk.
+    LP: #1439451.
+  * Backport patches for gccgo (not yet applied):
+    - Consider multi-result calls in escape analysis.
+    - Propagate escape info from closures to enclosed variables.
+    - Analyze function values and conversions.
+    - Use backend interface for stack allocation.
+  * More libstdc++ symbols updates for the Hurd and KFreeBSD.
+  * config-ml.in: Add D support.
+  * Update cross-biarch.diff to support D and Go.
+  * Apply the cross-biarch patch for every cross build.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 30 Apr 2015 15:42:05 +0200
+
+gcc-5 (5.1.1-2) unstable; urgency=medium
+
+  * Update to SVN 20150428 (r222550, 5.1.1) from the gcc-5-branch.
+  * Fix the gnat build dependency.
+  * Don't build go and gofmt for cross compilers.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 28 Apr 2015 23:57:14 +0200
+
+gcc-5 (5.1.1-1) unstable; urgency=medium
+
+  * GCC 5.1.0 release.
+  * Update to SVN 20150424 (r222416, 5.1.1) from the gcc-5-branch.
+  * Update NEWS files.
+  * Apply the ada-bootstrap-compare patch for snapshot builds as well.
+  * Update libasan, libgomp and libstdc++ symbols files.
+  * Don't ignore errors in dh_makeshlibs and dh_shlibdeps anymore, symbols
+    files should be uptodate now.
+  * Split out the sjlj build related things from the ada-acats patch into
+    a new ada-acats-sjlj patch.
+  * Don't build libx32phobos-5-dev when not building x32 multilibs.
+  * Fix standard C++ include directory for cross builds. Closes: #783241.
+  * Ignore bootstrap comparison failure on ia64. Filed upstream as
+    PR middle-end/65874.
+  * gccgo: Add (don't yet apply) a patch to implement escape analysis (taken
+    from the trunk). Turned off by default, enable with -fgo-optimize-alloc.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 24 Apr 2015 18:42:39 +0200
+
+gcc-5 (5.1.0-0ubuntu11) vivid; urgency=medium
+
+  * GCC 5.1.0 release.
+  * Update NEWS files.
+  * gccgo: Implement escape analysis (taken from the trunk). Turned off
+    by default, enable with -fgo-optimize-alloc.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 22 Apr 2015 14:54:11 +0200
+
+gcc-5 (5.1~rc2-0ubuntu12) vivid; urgency=medium
+
+  * Fix libasan symbols.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 22 Apr 2015 00:12:03 +0200
+
+gcc-5 (5.1~rc2-0ubuntu11) vivid; urgency=medium
+
+  * GCC 5.1 release candidate 2.
+  * Update to SVN 20150421 (r222253) from the gcc-5-branch.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 21 Apr 2015 18:53:06 +0200
+
+gcc-5 (5.1~rc1-0ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150419 (r222218) from the gcc-5-branch.
+  * Apply the ada-bootstrap-compare patch for snapshot builds as well.
+  * Update libasan, libgomp and libstdc++ symbols files.
+  * Don't ignore errors in dh_makeshlibs and dh_shlibdeps anymore, symbols
+    files should be uptodate now.
+  * Split out the sjlj build related things from the ada-acats patch into
+    a new ada-acats-sjlj patch.
+  * Ignore bootstrap comparison failure on ia64. Filed upstream as
+    PR middle-end/65874.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 19 Apr 2015 15:57:49 +0200
+
+gcc-5 (5.1~rc1-0ubuntu11) vivid; urgency=medium
+
+  * GCC 5.1 release candidate 1.
+  * Update to SVN 20150414 (r222066) from the gcc-5-branch.
+  * Update GDC to the gcc-5 branch, 20140414.
+  * Don't build libobjc, when not building the common libraries.
+  * Don't run the gccjit tests on KFreeBSD. Works around #782444:.
+  * Fix not building libs built by the next GCC version.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 14 Apr 2015 03:01:02 +0200
+
+gcc-5 (5-20150410-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150410.
+  * Fix /usr/include/c++/5.0.0 symlink.
+  * Re-enable building the D frontend. Closes: #782254.
+  * gccgo: Install libnetgo.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 11 Apr 2015 02:21:24 +0200
+
+gcc-5 (5-20150404-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150404.
+  * Don't explicitly configure --with-gxx-include-dir and an absolute path,
+    so the toolchain remains relocatible. Instead, canonicalize the include
+    path names at runtime.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 04 Apr 2015 23:34:58 +0200
+
+gcc-5 (5-20150401-0ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150401.
+  * Don't link libgnatprj using --no-allow-shlib-undefined on older releases.
+  * Don't build libmpx on older releases.
+  * Remove the work around to build libgccjit on arm64.
+  * Fix the libgccjit build using the just built compiler.
+  * Don't break other gcc, gcj, gnat -base packages for backports, only
+    needed for dist-upgrades.
+  * Don't add -gtoggle to STAGE3_CFLAGS (disabling the bootstrap comparison).
+    Instead, ignore the one differing file (gcc/ada/a-except.o) for now.
+    See #781457, PR ada/65618.
+  * Update libasan, libtsan, libgfortran and libstdc++ symbols files.
+  * Add symbols files for libmpx, libgccjit and libcc1.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 01 Apr 2015 11:27:39 +0200
+
+gcc-5 (5-20150329-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150329.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 29 Mar 2015 19:13:54 +0200
+
+gcc-5 (5-20150329-1) experimental; urgency=medium
+
+  * Update to SVN 20150329.
+  * Fix building the gnat-5-doc package.
+  * Fix gnat build dependencies.
+  * Fix installation of the gnat upstream ChangeLog. Closes: #781451.
+  * Restore the bootstrap-debug.mk patch to the ada-mips patch
+    for debugging purposes. See #781457.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 29 Mar 2015 18:53:29 +0200
+
+gcc-5 (5-20150328-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150328.
+  * Fix building the gnat-5-doc package.
+  * Fix installation of the gnat upstream ChangeLog. Closes: #781451.
+  * Restore the bootstrap-debug.mk patch to the ada-mips patch
+    for debugging purposes. See #781457.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 28 Mar 2015 15:08:55 +0100
+
+gcc-5 (5-20150327-1) experimental; urgency=medium
+
+  * Update to SVN 20150327.
+  * Update libcc1 build support.
+  * Fix syntax in libstdc++ symbols file. Closes: #780991.
+  * Fix PR go/65417: Add support for PPC32 relocs to debug/elf. LP: #1431388.
+  * Fix PR go/65462: Fix go get dependencies. LP: #1432497.
+  * Limit the omp.h multilib fix to Linux. Closes: #778440.
+  * For ICEs, dump the preprocessed source file to stderr when in a
+    distro build environment.
+  * Remove the bootstrap-debug.mk patch from the ada-mips patch.
+  * gnat related work (partly based on #780640):
+    - Update patches for GCC 5.
+    - Build the gnat packages from the gcc-5 source package.
+    - Don't build a gnat-base package from the gcc-5 source.
+    - Stop building the gnat-5-sjlj package for now, patch needs an update.
+    - Fix the packaging when not building the gnat-5-sjlj package.
+    - Don't apply the ada-symbolic-tracebacks, patch needs an update.
+    - Fix the libgnatprj build, build with -DIN_GCC.
+  * Replace cloog/ppl build bits with isl build bits.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 27 Mar 2015 21:05:16 +0100
+
+gcc-5 (5-20150321-1ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150321.
+  * Move the libcc1plugin from the gcc-5-plugin-dev package into the
+    gcc-5 package.
+  * Configure with --enable-checking=yes (instead of =release).
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 21 Mar 2015 15:28:30 +0100
+
+gcc-5 (5-20150316-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150316.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 16 Mar 2015 11:56:03 +0100
+
+gcc-5 (5-20150314-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150314.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 14 Mar 2015 14:29:28 +0100
+
+gcc-5 (5-20150312-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150312.
+    - PR go/65404, enable cgo on arm64 and powerpc. LP: #1431032.
+  * Fix libmpx multilib builds.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 12 Mar 2015 23:11:21 +0100
+
+gcc-5 (5-20150311-1ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150311.
+    - libgo: Add arm64 to the pointer size map (Michael Hudson).
+    - libgo: Add ppc to the pointer size map.
+  * Enable libmpx builds on amd64 and i386.
+  * Update the gcc-multiarch patch for mips64 (YunQiang Su).
+    Closes: #776402, #780271.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 11 Mar 2015 19:56:38 +0100
+
+gcc-5 (5-20150307-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150307.
+    - Update gccgo to Go 1.4.2.
+  * Enable libsanitizer for AArch64 and POWERPC LE (asan, ubsan).
+  * Remove the support to build empty libsanitizer packages on powerpc
+    and ppc64; libsanitizer should be stable on these architectures.
+  * Fix libcc1.so symlink. Closes: #779341.
+  * Revert the fix for PR65150 on armel and armhf to restore bootstrap.
+  * Don't strip the libgo library, or some things won't work as documented,
+    like runtime.Callers. Still keep the -dbg packages and check if some
+    debug information can be stripped.
+  * gccgo-5: Install alternatives for go and gofmt.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 07 Mar 2015 12:36:40 +0100
+
+gcc-5 (5-20150226-1) experimental; urgency=medium
+
+  * Update to SVN 20150226.
+    - Fix PR c/65040 (closes: #778514), PR tree-optimization/65053
+      (closes: #778070, #778071), PR c++/64898 (closes: #778472).
+  * Allow not to strip the compiler executables to be able to print backtraces
+    for ICEs.
+  * Fix gnat build on mips64el (James Cowgill). Addresses: #779191.
+  * Fix the hppa64 cross build (John David Anglin). Closes: #778658.
+  * Fix libstdc++ pretty printers for Python3. Closes: #778436.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 26 Feb 2015 08:18:23 +0100
+
+gcc-5 (5-20150205-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150205.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 05 Feb 2015 01:57:43 +0100
+
+gcc-5 (5-20150203-0ubuntu12) vivid; urgency=medium
+
+  * Don't disable bootstrap mode for the jit build on arm64, gets
+    miscompiled.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 03 Feb 2015 13:39:02 +0100
+
+gcc-5 (5-20150203-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150203.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 03 Feb 2015 13:39:02 +0100
+
+gcc-5 (5-20150129-0ubuntu2) vivid; urgency=medium
+
+  * Fix the libstdc++ build.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 29 Jan 2015 19:09:16 +0100
+
+gcc-5 (5-20150129-0ubuntu1) vivid; urgency=medium
+
+  * Update to SVN 20150129.
+  * Configure --with-default-libstdcxx-abi=c++11 for development,
+    --with-default-libstdcxx-abi=c++98 for backports.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 29 Jan 2015 17:47:03 +0100
+
+gcc-5 (5-20150128-0ubuntu1) vivid; urgency=medium
+
+  * Update to SVN 20150128.
+  * Update GDC for GCC 5.
+  * Build GDC multilib packages.
+  * Update cross-install-location.diff for gcc-5. Closes: #776100.
+  * Re-enable libgccjit on AArch64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Jan 2015 23:30:09 +0100
+
+gcc-5 (5-20150127-0ubuntu2) vivid; urgency=medium
+
+  * Disable libgccjit on AArch64, compiler issue
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 27 Jan 2015 18:05:12 +0100
+
+gcc-5 (5-20150127-0ubuntu1) vivid; urgency=medium
+
+  * Update to SVN 20150127.
+  * Disable libgccjit on AArch64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 27 Jan 2015 14:39:03 +0100
+
+gcc-5 (5-20150126-0ubuntu3) vivid; urgency=medium
+
+  * Update to SVN 20150126.
+  * More symbol file updates.
+  * Fix libbacktrace and libsanitizer multilib builds.
+  * Fix libssp builds on 64bit architectures.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 26 Jan 2015 18:22:53 +0100
+
+gcc-5 (5-20150121-0ubuntu2) vivid; urgency=medium
+
+  * GCC 5.
+  * Build new binary packages libcc1-0, libgccjit0, libgccjit-5-dev,
+    libgccjit-5-dbg, libgccjit-5-doc.
+  * Update symbols files (still incomplete).
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 20 Jan 2015 12:45:13 +0100
+
+gcc-4.9 (4.9.2-10ubuntu2) vivid; urgency=medium
+
+  * Update to SVN 20150116 (r219730) from the gcc-4_9-branch.
+    - Fix PR libstdc++/64476, PR libstdc++/60966, PR libstdc++/64239,
+      PR middle-end/63704 (ice on valid), PR target/64513 (x86),
+      PR rtl-optimization/64286 (wrong code), PR tree-optimization/64563 (ice),
+      PR middle-end/64391 (ice on valid), PR c++/54442 (ice on valid),
+      PR target/64358 (rs6000, wrong code), PR target/63424 (AArch64, ice on
+      valid), PR target/64479 (SH), PR rtl-optimization/64536, PR target/64505
+      (rs6000), PR target/61413 (ARM, wrong code), PR target/64507 (SH),
+      PR target/64409 (x32, ice on valid), PR c++/64487 (ice on valid),
+      PR c++/64352, PR c++/64251 (rejects valid), PR c++/64297 (ice on valid),
+      PR c++/64029 (ice on valid), PR c++/63657 (diagnostic), PR c++/38958
+      (diagnostic), PR c++/63658 (rejects valid), PR ada/64492 (build),
+      PR fortran/64528 (ice on valid), PR fortran/63733 (wrong code),
+      PR fortran/56867 (wrong code), PR fortran/64244 (ice on valid).
+  * Update the Linaro support to the 4.9-2015.01 release.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 16 Jan 2015 14:28:09 +0100
+
+gcc-4.9 (4.9.2-10ubuntu1) vivid; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 31 Dec 2014 04:54:06 +0100
+
+gcc-4.9 (4.9.2-10) unstable; urgency=medium
+
+  * Really add x32 multilib packages for i386 cross builds to the control file.
+    Closes: #773265.
+  * Use the final binutils 2.25 release.
+  * Tighten the gcc-4.9 dependency on libgcc-4.9-dev (YunQiang Su).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 25 Dec 2014 18:10:51 +0100
+
+gcc-4.9 (4.9.2-9) unstable; urgency=medium
+
+  * Update to SVN 20141220 (r218987) from the gcc-4_9-branch.
+    - Fix PR libstdc++/64302, PR libstdc++/64303, PR c++/60955,
+      PR rtl-optimization/64010 (wrong code), PR sanitizer/64265 (wrong code).
+  * Add x32 multilib packages for i386 cross builds to the control file.
+    Closes: #773265.
+  * Fix mips64el multilib cross builds. Closes: #772665.
+  * libphobos-4.x-dev: Stop providing libphobos-dev, now a real package.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 20 Dec 2014 07:47:15 +0100
+
+gcc-4.9 (4.9.2-8) unstable; urgency=medium
+
+  * Update to SVN 20141214 (r218721) from the gcc-4_9-branch.
+    - Fix PR tree-optimization/62021 (ice), PR middle-end/64225 (missed
+      optimization), PR libstdc++/64239, PR rtl-optimization/64037 (wrong
+      code), PR target/64200 (x86, ice), PR tree-optimization/64269 (ice).
+  * Don't build libphobos multilibs, there is no gdc-multilib build.
+  * Really disable the sanitizer libs on powerpc, ppc64 and ppc64el.
+  * Paste config.log files to stdout in case of build errors.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 14 Dec 2014 18:43:49 +0100
+
+gcc-4.9 (4.9.2-7ubuntu3) vivid; urgency=medium
+
+  * Fix the powerpc build.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 11 Dec 2014 15:52:15 +0100
+
+gcc-4.9 (4.9.2-7ubuntu2) vivid; urgency=medium
+
+  * Update to SVN 20141211 (r218620) from the gcc-4_9-branch.
+    - Fix PR tree-optimization/62021 (ice), PR middle-end/64225 (missed
+      optimization).
+  * Don't build libphobos multilibs, there is no gdc-multilib built.
+  * Really disable the sanitizer libs on powerpc, ppc64 and ppc64el.
+  * Paste config.log files to stdout in case of build errors.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 11 Dec 2014 12:04:13 +0100
+
+gcc-4.9 (4.9.2-7ubuntu1) vivid; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 10 Dec 2014 15:27:33 +0100
+
+gcc-4.9 (4.9.2-7) unstable; urgency=medium
+
+  * Update to SVN 20141210 (r218575) from the gcc-4_9-branch.
+    - Fix PR libstdc++/64203, PR target/55351 (SH), PR tree-optimization/61686,
+      PR bootstrap/64213.
+    - libgcc hppa backports.
+  * Fix cross builds with dpkg-architecture unconditionally exporting
+    target variables. For now specify the target architecture
+    in debian/target. This still needs to work with older dpkg versions,
+    so don't "simplify" the packaging. Closes: #768167.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 10 Dec 2014 13:32:42 +0100
+
+gcc-4.9 (4.9.2-6ubuntu1) vivid; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 09 Dec 2014 13:47:24 +0100
+
+# For older changelog entries, run 'apt-get changelog gcc-4.9-base'
--- gcc-6-6.3.0.orig/debian/compat
+++ gcc-6-6.3.0/debian/compat
@@ -0,0 +1 @@
+9
--- gcc-6-6.3.0.orig/debian/control
+++ gcc-6-6.3.0/debian/control
@@ -0,0 +1,3197 @@
+Source: gcc-6
+Section: devel
+Priority: optional
+Maintainer: Ubuntu Core developers <ubuntu-devel-discuss@lists.ubuntu.com>
+XSBC-Original-Maintainer: Debian GCC Maintainers <debian-gcc@lists.debian.org>
+Uploaders: Matthias Klose <doko@debian.org>
+Standards-Version: 3.9.8
+Build-Depends: debhelper (>= 9.20141010), dpkg-dev (>= 1.17.14), 
+  g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32] <!cross>, g++-6 [arm64] <!cross>, 
+  libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 mipsn32 mipsn32el mips64 mips64el s390x sparc64 x32], libn32gcc1 [mips mipsel mips64 mips64el], lib64gcc1 [i386 mips mipsel mipsn32 mipsn32el powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel mipsn32 mipsn32el], libc6-dev-mipsn32 [mips mipsel mips64 mips64el], libc6-dev-mips32 [mipsn32 mipsn32el mips64 mips64el], libc6-dev-x32 [amd64 i386], libx32gcc1 [amd64 i386], libc6-dev-armhf [armel], libhfgcc1 [armel], libc6-dev-armel [armhf], libsfgcc1 [armhf], libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg, 
+  kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], linux-libc-dev [m68k], 
+  m4, libtool, autoconf2.64, 
+  libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], 
+  autogen, gawk, lzma, xz-utils, patchutils, 
+  zlib1g-dev, systemtap-sdt-dev [linux-any kfreebsd-any hurd-any], 
+  binutils:native (>= 2.28) | binutils-multiarch:native (>= 2.28), binutils-hppa64-linux-gnu:native (>= 2.28) [hppa amd64 i386 x32], 
+  gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, 
+  gdb:native, 
+  texinfo (>= 4.3), locales, sharutils, 
+  procps, zlib1g-dev, libantlr-java, python:native, libffi-dev, fastjar, libmagic-dev, libecj-java (>= 3.3.0-2), zip, libasound2-dev [ !hurd-any !kfreebsd-any], libxtst-dev, libxt-dev, libgtk2.0-dev (>= 2.4.4-2), libart-2.0-dev, libcairo2-dev, gnat-6:native [!m32r !sh3 !sh3eb !sh4eb !powerpcspe !m68k !mips64 !x32], g++-6:native, netbase, 
+  libisl-dev, libmpc-dev (>= 1.0), libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), lib32z1-dev [amd64 kfreebsd-amd64], lib64z1-dev [i386], libx32z1-dev [amd64 kfreebsd-amd64 i386], 
+  dejagnu [!m68k], realpath (>= 1.9.12), chrpath, lsb-release, quilt, 
+  pkg-config, libgc-dev, 
+   g++-6-alpha-linux-gnu [alpha] <cross>, gobjc-6-alpha-linux-gnu [alpha] <cross>, gfortran-6-alpha-linux-gnu [alpha] <cross>, gcj-6-alpha-linux-gnu [alpha] <cross>, gdc-6-alpha-linux-gnu [alpha] <cross>, gccgo-6-alpha-linux-gnu [alpha] <cross>, gnat-6-alpha-linux-gnu [alpha] <cross>, g++-6-x86-64-linux-gnu [amd64] <cross>, gobjc-6-x86-64-linux-gnu [amd64] <cross>, gfortran-6-x86-64-linux-gnu [amd64] <cross>, gcj-6-x86-64-linux-gnu [amd64] <cross>, gdc-6-x86-64-linux-gnu [amd64] <cross>, gccgo-6-x86-64-linux-gnu [amd64] <cross>, gnat-6-x86-64-linux-gnu [amd64] <cross>, g++-6-arm-linux-gnueabi [armel] <cross>, gobjc-6-arm-linux-gnueabi [armel] <cross>, gfortran-6-arm-linux-gnueabi [armel] <cross>, gcj-6-arm-linux-gnueabi [armel] <cross>, gdc-6-arm-linux-gnueabi [armel] <cross>, gccgo-6-arm-linux-gnueabi [armel] <cross>, gnat-6-arm-linux-gnueabi [armel] <cross>, g++-6-arm-linux-gnueabihf [armhf] <cross>, gobjc-6-arm-linux-gnueabihf [armhf] <cross>, gfortran-6-arm-linux-gnueabihf [armhf] <cross>, gcj-6-arm-linux-gnueabihf [armhf] <cross>, gdc-6-arm-linux-gnueabihf [armhf] <cross>, gccgo-6-arm-linux-gnueabihf [armhf] <cross>, gnat-6-arm-linux-gnueabihf [armhf] <cross>, g++-6-aarch64-linux-gnu [arm64] <cross>, gobjc-6-aarch64-linux-gnu [arm64] <cross>, gfortran-6-aarch64-linux-gnu [arm64] <cross>, gcj-6-aarch64-linux-gnu [arm64] <cross>, gdc-6-aarch64-linux-gnu [arm64] <cross>, gccgo-6-aarch64-linux-gnu [arm64] <cross>, gnat-6-aarch64-linux-gnu [arm64] <cross>, g++-6-i686-linux-gnu [i386] <cross>, gobjc-6-i686-linux-gnu [i386] <cross>, gfortran-6-i686-linux-gnu [i386] <cross>, gcj-6-i686-linux-gnu [i386] <cross>, gdc-6-i686-linux-gnu [i386] <cross>, gccgo-6-i686-linux-gnu [i386] <cross>, gnat-6-i686-linux-gnu [i386] <cross>, g++-6-mips-linux-gnu [mips] <cross>, gobjc-6-mips-linux-gnu [mips] <cross>, gfortran-6-mips-linux-gnu [mips] <cross>, gcj-6-mips-linux-gnu [mips] <cross>, gdc-6-mips-linux-gnu [mips] <cross>, gccgo-6-mips-linux-gnu [mips] <cross>, gnat-6-mips-linux-gnu [mips] <cross>, g++-6-mipsel-linux-gnu [mipsel] <cross>, gobjc-6-mipsel-linux-gnu [mipsel] <cross>, gfortran-6-mipsel-linux-gnu [mipsel] <cross>, gcj-6-mipsel-linux-gnu [mipsel] <cross>, gdc-6-mipsel-linux-gnu [mipsel] <cross>, gccgo-6-mipsel-linux-gnu [mipsel] <cross>, gnat-6-mipsel-linux-gnu [mipsel] <cross>, g++-6-mips64-linux-gnuabi64 [mips64] <cross>, gobjc-6-mips64-linux-gnuabi64 [mips64] <cross>, gfortran-6-mips64-linux-gnuabi64 [mips64] <cross>, gcj-6-mips64-linux-gnuabi64 [mips64] <cross>, gdc-6-mips64-linux-gnuabi64 [mips64] <cross>, gccgo-6-mips64-linux-gnuabi64 [mips64] <cross>, g++-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gobjc-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gfortran-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gcj-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gdc-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gccgo-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gnat-6-mips64el-linux-gnuabi64 [mips64el] <cross>, g++-6-powerpc-linux-gnu [powerpc] <cross>, gobjc-6-powerpc-linux-gnu [powerpc] <cross>, gfortran-6-powerpc-linux-gnu [powerpc] <cross>, gcj-6-powerpc-linux-gnu [powerpc] <cross>, gdc-6-powerpc-linux-gnu [powerpc] <cross>, gccgo-6-powerpc-linux-gnu [powerpc] <cross>, gnat-6-powerpc-linux-gnu [powerpc] <cross>, g++-6-powerpc64-linux-gnu [ppc64] <cross>, gobjc-6-powerpc64-linux-gnu [ppc64] <cross>, gfortran-6-powerpc64-linux-gnu [ppc64] <cross>, gcj-6-powerpc64-linux-gnu [ppc64] <cross>, gdc-6-powerpc64-linux-gnu [ppc64] <cross>, gccgo-6-powerpc64-linux-gnu [ppc64] <cross>, gnat-6-powerpc64-linux-gnu [ppc64] <cross>, g++-6-powerpc64le-linux-gnu [ppc64el] <cross>, gobjc-6-powerpc64le-linux-gnu [ppc64el] <cross>, gfortran-6-powerpc64le-linux-gnu [ppc64el] <cross>, gcj-6-powerpc64le-linux-gnu [ppc64el] <cross>, gdc-6-powerpc64le-linux-gnu [ppc64el] <cross>, gccgo-6-powerpc64le-linux-gnu [ppc64el] <cross>, gnat-6-powerpc64le-linux-gnu [ppc64el] <cross>, g++-6-m68k-linux-gnu [m68k] <cross>, gobjc-6-m68k-linux-gnu [m68k] <cross>, gfortran-6-m68k-linux-gnu [m68k] <cross>, gcj-6-m68k-linux-gnu [m68k] <cross>, gdc-6-m68k-linux-gnu [m68k] <cross>, g++-6-sh4-linux-gnu [sh4] <cross>, gobjc-6-sh4-linux-gnu [sh4] <cross>, gfortran-6-sh4-linux-gnu [sh4] <cross>, gcj-6-sh4-linux-gnu [sh4] <cross>, g++-6-sparc64-linux-gnu [sparc64] <cross>, gobjc-6-sparc64-linux-gnu [sparc64] <cross>, gfortran-6-sparc64-linux-gnu [sparc64] <cross>, gcj-6-sparc64-linux-gnu [sparc64] <cross>, gdc-6-sparc64-linux-gnu [sparc64] <cross>, gccgo-6-sparc64-linux-gnu [sparc64] <cross>, g++-6-s390x-linux-gnu [s390x] <cross>, gobjc-6-s390x-linux-gnu [s390x] <cross>, gfortran-6-s390x-linux-gnu [s390x] <cross>, gcj-6-s390x-linux-gnu [s390x] <cross>, gdc-6-s390x-linux-gnu [s390x] <cross>, gccgo-6-s390x-linux-gnu [s390x] <cross>, gnat-6-s390x-linux-gnu [s390x] <cross>, g++-6-x86-64-linux-gnux32 [x32] <cross>, gobjc-6-x86-64-linux-gnux32 [x32] <cross>, gfortran-6-x86-64-linux-gnux32 [x32] <cross>, gcj-6-x86-64-linux-gnux32 [x32] <cross>, gdc-6-x86-64-linux-gnux32 [x32] <cross>, gccgo-6-x86-64-linux-gnux32 [x32] <cross>, 
+Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base, xsltproc, libxml2-utils, docbook-xsl-ns, 
+Homepage: http://gcc.gnu.org/
+Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-6/
+Vcs-Svn: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6
+
+Package: gcc-6-base
+Architecture: any
+Multi-Arch: same
+Section: libs
+Priority: required
+Depends: ${misc:Depends}
+Replaces: ${base:Replaces}
+Breaks: ${base:Breaks}
+Description: GCC, the GNU Compiler Collection (base package)
+ This package contains files common to all languages and libraries
+ contained in the GNU Compiler Collection (GCC).
+
+Package: libgcc1
+Architecture: any
+Section: libs
+Priority: required
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: libgcc1-armel [armel], libgcc1-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+Description: GCC support library
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libgcc1-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf]
+Multi-Arch: same
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: libgcc2
+Architecture: m68k
+Section: libs
+Priority: required
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+Description: GCC support library
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libgcc2-dbg
+Architecture: m68k
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgcc2 (= ${gcc:EpochVersion}), ${misc:Depends}
+Multi-Arch: same
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: libgcc-6-dev
+Architecture: any
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm},
+ ${dep:libatomic}, ${dep:libbtrace}, ${dep:libasan}, ${dep:liblsan},
+ ${dep:libtsan}, ${dep:libubsan}, ${dep:libcilkrts}, ${dep:libvtv},
+ ${dep:libmpx},
+ ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends}
+Multi-Arch: same
+Replaces: gccgo-6 (<< ${gcc:Version})
+Description: GCC support library (development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libgcc4
+Architecture: hppa
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+Section: libs
+Priority: required
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GCC support library
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libgcc4-dbg
+Architecture: hppa
+Multi-Arch: same
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgcc4 (= ${gcc:EpochVersion}), ${misc:Depends}
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: lib64gcc1
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: libgcc1 (<= 1:3.3-0pre9)
+Description: GCC support library (64bit)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: lib64gcc1-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: lib64gcc-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (64bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: lib32gcc1
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: GCC support library (32 bit Version)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: lib32gcc1-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: lib32gcc-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (32 bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libhfgcc1
+Architecture: armel
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: libgcc1-armhf [armel]
+Description: GCC support library (hard float ABI)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libhfgcc1-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Conflicts: libgcc1-dbg-armhf [armel]
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: libhfgcc-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (hard float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libsfgcc1
+Architecture: armhf
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: libgcc1-armel [armhf]
+Description: GCC support library (soft float ABI)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libsfgcc1-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Conflicts: libgcc1-dbg-armel [armhf]
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: libsfgcc-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (soft float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libn32gcc1
+Architecture: mips mipsel mips64 mips64el
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: libgcc1 (<= 1:3.3-0pre9)
+Description: GCC support library (n32)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libn32gcc1-dbg
+Architecture: mips mipsel mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: libn32gcc-6-dev
+Architecture: mips mipsel mips64 mips64el
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (n32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libx32gcc1
+Architecture: amd64 i386
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Description: GCC support library (x32)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libx32gcc1-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: libx32gcc-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (x32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: gcc-6
+Architecture: any
+Section: devel
+Priority: optional
+Depends: cpp-6 (= ${gcc:Version}), gcc-6-base (= ${gcc:Version}),
+    ${dep:libcc1}, 
+  binutils (>= ${binutils:Version}), 
+  ${dep:libgccdev}, ${shlibs:Depends}, ${misc:Depends}
+Recommends: ${dep:libcdev}
+Replaces: gccgo-6 (<< ${gcc:Version})
+Suggests: ${gcc:multilib}, gcc-6-doc (>= ${gcc:SoftVersion}),
+ gcc-6-locales (>= ${gcc:SoftVersion}),
+ libgcc1-dbg (>= ${libgcc:Version}),
+ libgomp1-dbg (>= ${gcc:Version}),
+ libitm1-dbg (>= ${gcc:Version}),
+ libatomic1-dbg (>= ${gcc:Version}),
+ libasan3-dbg (>= ${gcc:Version}),
+ liblsan0-dbg (>= ${gcc:Version}),
+ libtsan0-dbg (>= ${gcc:Version}),
+ libubsan0-dbg (>= ${gcc:Version}),
+ libcilkrts5-dbg (>= ${gcc:Version}),
+ libmpx2-dbg (>= ${gcc:Version}),
+ libquadmath0-dbg (>= ${gcc:Version})
+Provides: c-compiler
+Description: GNU C compiler
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+
+Package: gcc-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU C compiler (multilib support)
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gcc-6-test-results
+Architecture: any
+Section: devel
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), ${misc:Depends}
+Replaces: g++-5 (<< 5.2.1-28)
+Description: Test results for the GCC test suite
+ This package contains the test results for running the GCC test suite
+ for a post build analysis.
+
+Package: gcc-6-plugin-dev
+Architecture: any
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libgmp-dev (>= 2:5.0.1~), libmpc-dev (>= 1.0), ${shlibs:Depends}, ${misc:Depends}
+Description: Files for GNU GCC plugin development.
+ This package contains (header) files for GNU GCC plugin development. It
+ is only used for the development of GCC plugins, but not needed to run
+ plugins.
+
+Package: gcc-6-hppa64-linux-gnu
+Architecture: hppa amd64 i386 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}),
+  binutils-hppa64-linux-gnu | binutils-hppa64, 
+  ${shlibs:Depends}, ${misc:Depends}
+Description: GNU C compiler (cross compiler for hppa64)
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+
+Package: cpp-6
+Architecture: any
+Section: interpreters
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Suggests: gcc-6-locales (>= ${gcc:SoftVersion})
+Replaces: gccgo-6 (<< ${gcc:Version})
+Breaks: libmagics++-dev (<< 2.28.0-4), hardening-wrapper (<< 2.8+nmu3)
+Description: GNU C preprocessor
+ A macro processor that is used automatically by the GNU C compiler
+ to transform programs before actual compilation.
+ .
+ This package has been separated from gcc for the benefit of those who
+ require the preprocessor but not the compiler.
+
+Package: cpp-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU C preprocessor (cpp)
+ Documentation for the GNU C preprocessor in info format.
+
+Package: gcc-6-locales
+Architecture: all
+Section: devel
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), cpp-6 (>= ${gcc:SoftVersion}), ${misc:Depends}
+Recommends: gcc-6 (>= ${gcc:SoftVersion})
+Description: GCC, the GNU compiler collection (native language support files)
+ Native language support for GCC. Lets GCC speak your language,
+ if translations are available.
+ .
+ Please do NOT submit bug reports in other languages than "C".
+ Always reset your language settings to use the "C" locales.
+
+Package: g++-6
+Architecture: any
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: c++-compiler, c++abi2-dev
+Suggests: ${gxx:multilib}, gcc-6-doc (>= ${gcc:SoftVersion}), libstdc++6-6-dbg (>= ${gcc:Version})
+Description: GNU C++ compiler
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+
+Package: g++-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), g++-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libcxxbiarchdbg}
+Description: GNU C++ compiler (multilib support)
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: libgomp1
+Section: libs
+Architecture: any
+Provides: libgomp1-armel [armel], libgomp1-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libgomp1-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgomp1 (= ${gcc:Version}), ${misc:Depends}
+Provides: libgomp1-dbg-armel [armel], libgomp1-dbg-armhf [armhf]
+Multi-Arch: same
+Description: GCC OpenMP (GOMP) support library (debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib32gomp1
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: GCC OpenMP (GOMP) support library (32bit)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib32gomp1-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32gomp1 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library (32 bit debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib64gomp1
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library (64bit)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib64gomp1-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64gomp1 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library (64bit debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libn32gomp1
+Section: libs
+Architecture: mips mipsel mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library (n32)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libn32gomp1-dbg
+Architecture: mips mipsel mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libn32gomp1 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library (n32 debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+
+Package: libx32gomp1
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library (x32)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libx32gomp1-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32gomp1 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC OpenMP (GOMP) support library (x32 debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+
+Package: libhfgomp1
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libgomp1-armhf [armel]
+Description: GCC OpenMP (GOMP) support library (hard float ABI)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libhfgomp1-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfgomp1 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgomp1-dbg-armhf [armel]
+Description: GCC OpenMP (GOMP) support library (hard float ABI debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+
+Package: libsfgomp1
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libgomp1-armel [armhf]
+Description: GCC OpenMP (GOMP) support library (soft float ABI)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libsfgomp1-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfgomp1 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgomp1-dbg-armel [armhf]
+Description: GCC OpenMP (GOMP) support library (soft float ABI debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+
+Package: libitm1
+Section: libs
+Architecture: any
+Provides: libitm1-armel [armel], libitm1-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Transactional Memory Library
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libitm1-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libitm1 (= ${gcc:Version}), ${misc:Depends}
+Provides: libitm1-dbg-armel [armel], libitm1-dbg-armhf [armhf]
+Multi-Arch: same
+Description: GNU Transactional Memory Library (debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib32itm1
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: GNU Transactional Memory Library (32bit)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib32itm1-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32itm1 (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Transactional Memory Library (32 bit debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib64itm1
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Transactional Memory Library (64bit)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib64itm1-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64itm1 (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Transactional Memory Library (64bit debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+#Package: libn32itm`'ITM_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GNU Transactional Memory Library (n32)
+# GNU Transactional Memory Library (libitm) provides transaction support for
+# accesses to the memory of a process, enabling easy-to-use synchronization of
+# accesses to shared memory by several threads.
+
+#Package: libn32itm`'ITM_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(itm`'ITM_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GNU Transactional Memory Library (n32 debug symbols)
+# GNU Transactional Memory Library (libitm) provides transaction support for
+# accesses to the memory of a process, enabling easy-to-use synchronization of
+# accesses to shared memory by several threads.
+
+Package: libx32itm1
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Transactional Memory Library (x32)
+ This manual documents the usage and internals of libitm. It provides
+ transaction support for accesses to the memory of a process, enabling
+ easy-to-use synchronization of accesses to shared memory by several threads.
+
+Package: libx32itm1-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32itm1 (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Transactional Memory Library (x32 debug symbols)
+ This manual documents the usage and internals of libitm. It provides
+ transaction support for accesses to the memory of a process, enabling
+ easy-to-use synchronization of accesses to shared memory by several threads.
+
+Package: libhfitm1
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libitm1-armhf [armel]
+Description: GNU Transactional Memory Library (hard float ABI)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libhfitm1-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfitm1 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libitm1-armel [armhf]
+Description: GNU Transactional Memory Library (hard float ABI debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libsfitm1
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Transactional Memory Library (soft float ABI)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libsfitm1-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfitm1 (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Transactional Memory Library (soft float ABI debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libatomic1
+Section: libs
+Architecture: any
+Provides: libatomic1-armel [armel], libatomic1-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: support library providing __atomic built-in functions
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libatomic1-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libatomic1 (= ${gcc:Version}), ${misc:Depends}
+Provides: libatomic1-dbg-armel [armel], libatomic1-dbg-armhf [armhf]
+Multi-Arch: same
+Description: support library providing __atomic built-in functions (debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib32atomic1
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: support library providing __atomic built-in functions (32bit)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib32atomic1-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32atomic1 (= ${gcc:Version}), ${misc:Depends}
+Description: support library providing __atomic built-in functions (32 bit debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib64atomic1
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: support library providing __atomic built-in functions (64bit)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib64atomic1-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64atomic1 (= ${gcc:Version}), ${misc:Depends}
+Description: support library providing __atomic built-in functions (64bit debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libn32atomic1
+Section: libs
+Architecture: mips mipsel mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: support library providing __atomic built-in functions (n32)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libn32atomic1-dbg
+Architecture: mips mipsel mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libn32atomic1 (= ${gcc:Version}), ${misc:Depends}
+Description: support library providing __atomic built-in functions (n32 debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libx32atomic1
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: support library providing __atomic built-in functions (x32)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libx32atomic1-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32atomic1 (= ${gcc:Version}), ${misc:Depends}
+Description: support library providing __atomic built-in functions (x32 debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libhfatomic1
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libatomic1-armhf [armel]
+Description: support library providing __atomic built-in functions (hard float ABI)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libhfatomic1-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfatomic1 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libatomic1-armel [armhf]
+Description: support library providing __atomic built-in functions (hard float ABI debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libsfatomic1
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: support library providing __atomic built-in functions (soft float ABI)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libsfatomic1-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfatomic1 (= ${gcc:Version}), ${misc:Depends}
+Description: support library providing __atomic built-in functions (soft float ABI debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libasan3
+Section: libs
+Architecture: any
+Provides: libasan3-armel [armel], libasan3-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libasan3-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libasan3 (= ${gcc:Version}), ${misc:Depends}
+Provides: libasan3-dbg-armel [armel], libasan3-dbg-armhf [armhf]
+Multi-Arch: same
+Description: AddressSanitizer -- a fast memory error detector (debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan3
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: AddressSanitizer -- a fast memory error detector (32bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan3-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32asan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (32 bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan3
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (64bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan3-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64asan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (64bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(extra)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(asan`'ASAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32 debug symbols)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libx32asan3
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (x32)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libx32asan3-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32asan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (x32 debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libhfasan3
+Section: libs
+Architecture: armel
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libasan3-armhf [armel]
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libhfasan3-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfasan3 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libasan3-armel [armhf]
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libsfasan3
+Section: libs
+Architecture: armhf
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libsfasan3-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfasan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: liblsan0
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: LeakSanitizer -- a memory leak detector (runtime)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: liblsan0-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), liblsan0 (= ${gcc:Version}), ${misc:Depends}
+Multi-Arch: same
+Description: LeakSanitizer -- a memory leak detector (debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: lib32lsan0
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: LeakSanitizer -- a memory leak detector (32bit)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+Package: lib32lsan0-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32lsan0 (= ${gcc:Version}), ${misc:Depends}
+Description: LeakSanitizer -- a memory leak detector (32 bit debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+#Package: lib64lsan`'LSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (64bit)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+#Package: lib64lsan`'LSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(lsan`'LSAN_SO,64,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (64bit debug symbols)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+#Package: libn32lsan`'LSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (n32)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+#Package: libn32lsan`'LSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(lsan`'LSAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (n32 debug symbols)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+Package: libx32lsan0
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: LeakSanitizer -- a memory leak detector (x32)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+Package: libx32lsan0-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32lsan0 (= ${gcc:Version}), ${misc:Depends}
+Description: LeakSanitizer -- a memory leak detector (x32 debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+Package: libtsan0
+Section: libs
+Architecture: any
+Provides: libtsan0-armel [armel], libtsan0-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (runtime)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libtsan0-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libtsan0 (= ${gcc:Version}), ${misc:Depends}
+Provides: libtsan0-dbg-armel [armel], libtsan0-dbg-armhf [armhf]
+Multi-Arch: same
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libubsan0
+Section: libs
+Architecture: any
+Provides: libubsan0-armel [armel], libubsan0-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (runtime)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libubsan0-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libubsan0 (= ${gcc:Version}), ${misc:Depends}
+Provides: libubsan0-dbg-armel [armel], libubsan0-dbg-armhf [armhf]
+Multi-Arch: same
+Description: UBSan -- undefined behaviour sanitizer (debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib32ubsan0
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: UBSan -- undefined behaviour sanitizer (32bit)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib32ubsan0-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32ubsan0 (= ${gcc:Version}), ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (32 bit debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib64ubsan0
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (64bit)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib64ubsan0-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64ubsan0 (= ${gcc:Version}), ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (64bit debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+#Package: libn32ubsan`'UBSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: UBSan -- undefined behaviour sanitizer (n32)
+# UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+# Various computations will be instrumented to detect undefined behavior
+# at runtime. Available for C and C++.
+
+#Package: libn32ubsan`'UBSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: UBSan -- undefined behaviour sanitizer (n32 debug symbols)
+# UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+# Various computations will be instrumented to detect undefined behavior
+# at runtime. Available for C and C++.
+
+Package: libx32ubsan0
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (x32)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libx32ubsan0-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32ubsan0 (= ${gcc:Version}), ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (x32 debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libhfubsan0
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libubsan0-armhf [armel]
+Description: UBSan -- undefined behaviour sanitizer (hard float ABI)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libhfubsan0-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfubsan0 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libubsan0-armel [armhf]
+Description: UBSan -- undefined behaviour sanitizer (hard float ABI debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libsfubsan0
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (soft float ABI)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libsfubsan0-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfubsan0 (= ${gcc:Version}), ${misc:Depends}
+Description: UBSan -- undefined behaviour sanitizer (soft float ABI debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libcilkrts5
+Section: libs
+Architecture: any
+Provides: libcilkrts5-armel [armel], libcilkrts5-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Intel Cilk Plus language extensions (runtime)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libcilkrts5-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libcilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Provides: libcilkrts5-dbg-armel [armel], libcilkrts5-dbg-armhf [armhf]
+Multi-Arch: same
+Description: Intel Cilk Plus language extensions (debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib32cilkrts5
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: Intel Cilk Plus language extensions (32bit)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib32cilkrts5-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32cilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Description: Intel Cilk Plus language extensions (32 bit debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib64cilkrts5
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Intel Cilk Plus language extensions (64bit)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib64cilkrts5-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64cilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Description: Intel Cilk Plus language extensions (64bit debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libx32cilkrts5
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Intel Cilk Plus language extensions (x32)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libx32cilkrts5-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32cilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Description: Intel Cilk Plus language extensions (x32 debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libmpx2
+Section: libs
+Architecture: any
+Provides: libmpx2-armel [armel], libmpx2-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libmpx0 (<< 6-20160120-1)
+Description: Intel memory protection extensions (runtime)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libmpx2-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libmpx2 (= ${gcc:Version}), ${misc:Depends}
+Provides: libmpx2-dbg-armel [armel], libmpx2-dbg-armhf [armhf]
+Multi-Arch: same
+Description: Intel memory protection extensions (debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib32mpx2
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32mpx0 (<< 6-20160120-1)
+Description: Intel memory protection extensions (32bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib32mpx2-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32mpx2 (= ${gcc:Version}), ${misc:Depends}
+Description: Intel memory protection extensions (32 bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib64mpx2
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64mpx0 (<< 6-20160120-1)
+Description: Intel memory protection extensions (64bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib64mpx2-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64mpx2 (= ${gcc:Version}), ${misc:Depends}
+Description: Intel memory protection extensions (64bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libquadmath0
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GCC Quad-Precision Math Library
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libquadmath0-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libquadmath0 (= ${gcc:Version}), ${misc:Depends}
+Multi-Arch: same
+Description: GCC Quad-Precision Math Library (debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: lib32quadmath0
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: GCC Quad-Precision Math Library (32bit)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: lib32quadmath0-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32quadmath0 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC Quad-Precision Math Library (32 bit debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: lib64quadmath0
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GCC Quad-Precision Math Library  (64bit)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: lib64quadmath0-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64quadmath0 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC Quad-Precision Math Library  (64bit debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+#Package: libn32quadmath`'QMATH_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GCC Quad-Precision Math Library (n32)
+# A library, which provides quad-precision mathematical functions on targets
+# supporting the __float128 datatype. The library is used to provide on such
+# targets the REAL(16) type in the GNU Fortran compiler.
+
+#Package: libn32quadmath`'QMATH_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(quadmath`'QMATH_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GCC Quad-Precision Math Library (n32 debug symbols)
+# A library, which provides quad-precision mathematical functions on targets
+# supporting the __float128 datatype.
+
+Package: libx32quadmath0
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GCC Quad-Precision Math Library (x32)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libx32quadmath0-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32quadmath0 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC Quad-Precision Math Library (x32 debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: libhfquadmath0
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GCC Quad-Precision Math Library (hard float ABI)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libhfquadmath0-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfquadmath0 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC Quad-Precision Math Library (hard float ABI debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: libsfquadmath0
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: GCC Quad-Precision Math Library (soft float ABI)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libsfquadmath0-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfquadmath0 (= ${gcc:Version}), ${misc:Depends}
+Description: GCC Quad-Precision Math Library (hard float ABI debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: libcc1-0
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GCC cc1 plugin for GDB
+ libcc1 is a plugin for GDB.
+
+Package: libgccjit0
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Breaks: python-gccjit (<< 0.4-4), python3-gccjit (<< 0.4-4)
+Description: GCC just-in-time compilation (shared library)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit0-dbg
+Section: debug
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgccjit0 (= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Breaks: libgccjit-5-dbg, libgccjit-6-dbg
+Replaces: libgccjit-5-dbg, libgccjit-6-dbg
+Description: GCC just-in-time compilation (debug information)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit-6-doc
+Section: doc
+Architecture: all
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgccjit-5-doc
+Description: GCC just-in-time compilation (documentation)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit-6-dev
+Section: libdevel
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgccjit0 (>= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Suggests: libgccjit-6-dbg
+Description: GCC just-in-time compilation (development files)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: gobjc++-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gobjc-6 (= ${gcc:Version}), g++-6 (= ${gcc:Version}), ${shlibs:Depends}, libobjc-6-dev (= ${gcc:Version}), ${misc:Depends}
+Suggests: ${gobjcxx:multilib}, gcc-6-doc (>= ${gcc:SoftVersion})
+Provides: objc++-compiler
+Description: GNU Objective-C++ compiler
+ This is the GNU Objective-C++ compiler, which compiles
+ Objective-C++ on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+Package: gobjc++-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gobjc++-6 (= ${gcc:Version}), g++-6-multilib (= ${gcc:Version}), gobjc-6-multilib (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Objective-C++ compiler (multilib support)
+ This is the GNU Objective-C++ compiler, which compiles Objective-C++ on
+ platforms supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gobjc-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc-6-dev (= ${gcc:Version}), ${misc:Depends}
+Suggests: ${gobjc:multilib}, gcc-6-doc (>= ${gcc:SoftVersion}), libobjc4-dbg (>= ${gcc:Version})
+Provides: objc-compiler
+Description: GNU Objective-C compiler
+ This is the GNU Objective-C compiler, which compiles
+ Objective-C on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+Package: gobjc-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gobjc-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Objective-C compiler (multilib support)
+ This is the GNU Objective-C compiler, which compiles Objective-C on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: libobjc-6-dev
+Architecture: any
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcc-6-dev (= ${gcc:Version}), libobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Multi-Arch: same
+Description: Runtime library for GNU Objective-C applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib64objc-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc-6-dev (= ${gcc:Version}), lib64objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib32objc-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc-6-dev (= ${gcc:Version}), lib32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libn32objc-6-dev
+Architecture: mips mipsel mips64 mips64el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc-6-dev (= ${gcc:Version}), libn32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libx32objc-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc-6-dev (= ${gcc:Version}), libx32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libhfobjc-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc-6-dev (= ${gcc:Version}), libhfobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libsfobjc-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc-6-dev (= ${gcc:Version}), libsfobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (soft float development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libobjc4
+Section: libs
+Architecture: any
+Provides: libobjc4-armel [armel], libobjc4-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libobjc4-dbg
+Section: debug
+Architecture: any
+Provides: libobjc4-dbg-armel [armel], libobjc4-dbg-armhf [armhf]
+Multi-Arch: same
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libobjc4 (= ${gcc:Version}), libgcc1-dbg (>= ${libgcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib64objc4
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (64bit)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib64objc4-dbg
+Section: debug
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64objc4 (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (64 bit debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib32objc4
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: Runtime library for GNU Objective-C applications (32bit)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib32objc4-dbg
+Section: debug
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32objc4 (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (32 bit debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libn32objc4
+Section: libs
+Architecture: mips mipsel mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (n32)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libn32objc4-dbg
+Section: debug
+Architecture: mips mipsel mips64 mips64el
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libn32objc4 (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (n32 debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libx32objc4
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (x32)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libx32objc4-dbg
+Section: debug
+Architecture: amd64 i386
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32objc4 (= ${gcc:Version}), libx32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (x32 debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libhfobjc4
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libobjc4-armhf [armel]
+Description: Runtime library for GNU Objective-C applications (hard float ABI)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libhfobjc4-dbg
+Section: debug
+Architecture: armel
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfobjc4 (= ${gcc:Version}), libhfgcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Conflicts: libobjc4-dbg-armhf [armel]
+Description: Runtime library for GNU Objective-C applications (hard float ABI debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libsfobjc4
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libobjc4-armel [armhf]
+Description: Runtime library for GNU Objective-C applications (soft float ABI)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libsfobjc4-dbg
+Section: debug
+Architecture: armhf
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfobjc4 (= ${gcc:Version}), libsfgcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Conflicts: libobjc4-dbg-armel [armhf]
+Description: Runtime library for GNU Objective-C applications (soft float ABI debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: gfortran-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libgfortran-6-dev (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: fortran95-compiler, ${fortran:mod-version}
+Suggests: ${gfortran:multilib}, gfortran-6-doc,
+ libgfortran3-dbg (>= ${gcc:Version}),
+ libcoarrays-dev
+Description: GNU Fortran compiler
+ This is the GNU Fortran compiler, which compiles
+ Fortran on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+Package: gfortran-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gfortran-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Fortran compiler (multilib support)
+ This is the GNU Fortran compiler, which compiles Fortran on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gfortran-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU Fortran compiler (gfortran)
+ Documentation for the GNU Fortran compiler in info format.
+
+Package: libgfortran-6-dev
+Architecture: any
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcc-6-dev (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Multi-Arch: same
+Description: Runtime library for GNU Fortran applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib64gfortran-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc-6-dev (= ${gcc:Version}), lib64gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib32gfortran-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc-6-dev (= ${gcc:Version}), lib32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libn32gfortran-6-dev
+Architecture: mips mipsel mips64 mips64el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc-6-dev (= ${gcc:Version}), libn32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libx32gfortran-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc-6-dev (= ${gcc:Version}), libx32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libhfgfortran-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc-6-dev (= ${gcc:Version}), libhfgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libsfgfortran-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc-6-dev (= ${gcc:Version}), libsfgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (soft float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libgfortran3
+Section: libs
+Architecture: any
+Provides: libgfortran3-armel [armel], libgfortran3-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libgfortran3-dbg
+Section: debug
+Architecture: any
+Provides: libgfortran3-dbg-armel [armel], libgfortran3-dbg-armhf [armhf]
+Multi-Arch: same
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgfortran3 (= ${gcc:Version}), libgcc1-dbg (>= ${libgcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib64gfortran3
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (64bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib64gfortran3-dbg
+Section: debug
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (64bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib32gfortran3
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: Runtime library for GNU Fortran applications (32bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib32gfortran3-dbg
+Section: debug
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (32 bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libn32gfortran3
+Section: libs
+Architecture: mips mipsel mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (n32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libn32gfortran3-dbg
+Section: debug
+Architecture: mips mipsel mips64 mips64el
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libn32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (n32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libx32gfortran3
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (x32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libx32gfortran3-dbg
+Section: debug
+Architecture: amd64 i386
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (x32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libhfgfortran3
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libgfortran3-armhf [armel]
+Description: Runtime library for GNU Fortran applications (hard float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libhfgfortran3-dbg
+Section: debug
+Architecture: armel
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfgfortran3 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgfortran3-dbg-armhf [armel]
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libsfgfortran3
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libgfortran3-armel [armhf]
+Description: Runtime library for GNU Fortran applications (soft float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libsfgfortran3-dbg
+Section: debug
+Architecture: armhf
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfgfortran3 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgfortran3-dbg-armel [armhf]
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: gccgo-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libgo9 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: go-compiler
+Suggests: ${go:multilib}, gccgo-6-doc, libgo9-dbg (>= ${gcc:Version})
+Conflicts: ${golang:Conflicts}
+Description: GNU Go compiler
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler. It uses the gcc backend to generate optimized code.
+
+Package: gccgo-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gccgo-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libgobiarchdbg}
+Description: GNU Go compiler (multilib support)
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gccgo-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU Go compiler (gccgo)
+ Documentation for the GNU Go compiler in info format.
+
+Package: libgo9
+Section: libs
+Architecture: any
+Provides: libgo9-armel [armel], libgo9-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libgo3, libgo8
+Description: Runtime library for GNU Go applications
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libgo9-dbg
+Section: debug
+Architecture: any
+Provides: libgo9-dbg-armel [armel], libgo9-dbg-armhf [armhf]
+Multi-Arch: same
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgo9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: lib64go9
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64go3, lib64go8
+Description: Runtime library for GNU Go applications (64bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib64go9-dbg
+Section: debug
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (64bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: lib32go9
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32go3, lib32go8
+Description: Runtime library for GNU Go applications (32bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib32go9-dbg
+Section: debug
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (32 bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: libn32go9
+Section: libs
+Architecture: mips mipsel mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libn32go3, libn32go8
+Description: Runtime library for GNU Go applications (n32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libn32go9-dbg
+Section: debug
+Architecture: mips mipsel mips64 mips64el
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libn32go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (n32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: libx32go9
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32go3, libx32go8
+Description: Runtime library for GNU Go applications (x32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libx32go9-dbg
+Section: debug
+Architecture: amd64 i386
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (x32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: gcj-6
+Section: java
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:gcj}, ${dep:gcjcross}, ${dep:libcdev}, ${dep:ecj}, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Replaces: gcj-5-jdk (<< 5.2.1-19)
+Suggests: gcj-6-jdk
+Description: GCJ byte code and native compiler for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files.
+ .
+ Install the gcj-6-jdk package for a more complete SDK environment.
+
+Package: gcj-6-jdk
+Section: java
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:gcj}, ${dep:libcdev}, gcj-6 (= ${gcj:Version}), gcj-6-jre (= ${gcj:Version}), libgcj17-dev (>= ${gcj:Version}), fastjar, libgcj-bc, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Suggests: gcj-6-source (>= ${gcj:SoftVersion}), libgcj17-dbg (>= ${gcc:Version})
+Provides: java-compiler, java-sdk, java2-sdk, java5-sdk
+Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1)
+Replaces: libgcj11 (<< 4.5-20100101-1)
+Description: GCJ and Classpath development tools for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files. Other java development tools from classpath are included in this
+ package.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-SDK-like interface to the GCJ tool set.
+
+Package: gcj-6-jre-headless
+Priority: optional
+Section: java
+Architecture: any
+Depends: gcc-6-base (= ${gcc:Version}), gcj-6-jre-lib (>= ${gcj:SoftVersion}), libgcj17 (>= ${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: fastjar, gcj-6-jdk (= ${gcj:Version}), libgcj17-awt (>= ${gcj:Version})
+Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless
+Description: Java runtime environment using GIJ/Classpath (headless version)
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set,
+ limited to the headless tools and libraries.
+
+Package: gcj-6-jre
+Section: java
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcj-6-jre-headless (= ${gcj:Version}), libgcj17-awt (>= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime
+Description: Java runtime environment using GIJ/Classpath
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set.
+
+Package: libgcj17
+Section: libs
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends}
+Recommends: gcj-6-jre-lib (>= ${gcj:SoftVersion})
+Suggests: libgcj17-dbg (>= ${gcc:Version}), libgcj17-awt (= ${gcj:Version})
+Description: Java runtime library for use with gcj
+ This is the runtime that goes along with the gcj front end to
+ gcc. libgcj includes parts of the Java Class Libraries, plus glue to
+ connect the libraries to the compiler and the underlying OS.
+ .
+ To show file names and line numbers in stack traces, the packages
+ libgcj17-dbg and binutils are required.
+
+Package: gcj-6-jre-lib
+Section: java
+Architecture: all
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), libgcj17 (>= ${gcj:SoftVersion}), ${misc:Depends}
+Description: Java runtime library for use with gcj (jar files)
+ This is the jar file that goes along with the gcj front end to gcc.
+
+Package: libgcj17-awt
+Section: libs
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), libgcj17 (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${pkg:gcjqt}
+Description: AWT peer runtime libraries for use with gcj
+ These are runtime libraries holding the AWT peer implementations
+ for libgcj (currently the GTK+ based peer library is required, the
+ QT bases library is not built).
+
+Package: libgcj17-dev
+Section: libdevel
+Architecture: any
+Multi-Arch: same
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcj17-awt (= ${gcj:Version}), libgcj-bc, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Suggests: libgcj-doc
+Description: Java development headers for use with gcj
+ These are the development headers that go along with the gcj front end
+ to gcc. libgcj includes parts of the Java Class Libraries, plus glue
+ to connect the libraries to the compiler and the underlying OS.
+
+Package: libgcj17-dbg
+Section: debug
+Architecture: any
+Priority: extra
+Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+Depends: gcc-6-base (= ${gcc:Version}), libgcj17 (= ${gcj:Version}), ${misc:Depends}
+Recommends: binutils, libc6-dbg | libc-dbg
+Description: Debugging symbols for libraries provided in libgcj17-dev
+ The package provides debugging symbols for the libraries provided
+ in libgcj17-dev.
+ .
+ binutils is required to show file names and line numbers in stack traces.
+
+Package: gcj-6-source
+Section: java
+Architecture: all
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), gcj-6-jdk (>= ${gcj:SoftVersion}), ${misc:Depends}
+Description: GCJ java sources for use in IDEs like eclipse and netbeans
+ These are the java source files packaged as a zip file for use in development
+ environments like eclipse and netbeans.
+
+Package: libgcj-doc
+Section: doc
+Architecture: all
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Enhances: libgcj17-dev
+Provides: classpath-doc
+Description: libgcj API documentation and example programs
+ Autogenerated documentation describing the API of the libgcj library.
+ Sources and precompiled example programs from the Classpath library.
+
+Package: libstdc++6
+Architecture: any
+Section: libs
+Priority: important
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libc}, ${shlibs:Depends}, ${misc:Depends}
+Provides: libstdc++6-armel [armel], libstdc++6-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}, libantlr-dev (<= 2.7.7+dfsg-6), libaqsis1 (<= 1.8.2-1), libassimp3 (<= 3.0~dfsg-4), blockattack (<= 1.4.1+ds1-2.1build2), boo (<= 0.9.5~git20110729.r1.202a430-2), libboost-date-time1.55.0, libcpprest2.2 (<= 2.2.0-1), printer-driver-brlaser (<= 3-3), c++-annotations (<= 10.2.0-1), chromium-browser (<= 43.0.2357.130-0ubuntu2), clustalx (<= 2.1+lgpl-2), libdavix0 (<= 0.4.0-1build1), libdballe6 (<= 6.8-1), dff (<= 1.3.0+dfsg.1-4.1build2), libdiet-sed2.8 (<= 2.8.0-1build3), libdiet-client2.8 (<= 2.8.0-1build3), libdiet-admin2.8 (<= 2.8.0-1build3), libkgeomap2 (<= 4:15.04.2-0ubuntu1), libmediawiki1 (<= 1.0~digikam4.10.0-0ubuntu2), libkvkontakte1 (<= 1.0~digikam4.10.0-0ubuntu2), emscripten (<= 1.22.1-1), ergo (<= 3.4.0-1), fceux (<= 2.2.2+dfsg0-1), flush (<= 0.9.12-3.1ubuntu1), libfreefem++ (<= 3.37.1-1), freeorion (<= 0.4.4+git20150327-2), fslview (<= 4.0.1-4), fwbuilder (<= 5.1.0-4), libgazebo5 (<= 5.0.1+dfsg-2.1), libgetfem4++ (<= 4.2.1~beta1~svn4482~dfsg-3ubuntu3), libgmsh2 (<= 2.8.5+dfsg-1.1ubuntu1), gnote (<= 3.16.2-1), gnudatalanguage (<= 0.9.5-2build1), python-healpy (<= 1.8.1-1), innoextract (<= 1.4-1build1), libinsighttoolkit4.6 (<= 4.6.0-3ubuntu3), libdap17 (<= 3.14.0-2), libdapclient6 (<= 3.14.0-2), libdapserver7 (<= 3.14.0-2), libkolabxml1 (<= 1.1.0-3), libpqxx-4.0 (<= 4.0.1+dfsg-3ubuntu1), libreoffice-core (<= 1:4.4.4~rc3-0ubuntu1), librime1 (<= 1.2+dfsg-2), libwibble-dev (<= 1.1-1), lightspark (<= 0.7.2+git20150512-2), libmarisa0 (<= 0.2.4-8build1), mira-assembler (<= 4.9.5-1), mongodb (<= 1:2.6.3-0ubuntu7), mongodb-server (<= 1:2.6.3-0ubuntu7), ncbi-blast+ (<= 2.2.30-4), libogre-1.8.0 (<= 1.8.1+dfsg-0ubuntu5), libogre-1.9.0 (<= 1.9.0+dfsg1-4), openscad (<= 2014.03+dfsg-1build1), libopenwalnut1 (<= 1.4.0~rc1+hg3a3147463ee2-1ubuntu2), passepartout (<= 0.7.1-1.1), pdf2djvu (<= 0.7.19-1ubuntu2), photoprint (<= 0.4.2~pre2-2.3), plastimatch (<= 1.6.2+dfsg-1), plee-the-bear (<= 0.6.0-3.1), povray (<= 1:3.7.0.0-8), powertop (<= 2.6.1-1), psi4 (<= 4.0~beta5+dfsg-2build1), python3-taglib (<= 0.3.6+dfsg-2build2), realtimebattle (<= 1.0.8-14), ruby-passenger (<= 4.0.53-1), libapache2-mod-passenger (<= 4.0.53-1), sqlitebrowser (<= 3.5.1-3), tecnoballz (<= 0.93.1-6), wesnoth-1.12-core (<= 1:1.12.4-1), widelands (<= 1:18-3build1), libwreport2 (<= 2.14-1), xflr5 (<= 6.09.06-2), libxmltooling6 (<= 1.5.3-2.1), 
+Conflicts: scim (<< 1.4.2-1)
+Replaces: libstdc++6-6-dbg (<< 4.9.0-3)
+Description: GNU Standard C++ Library v3
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: lib32stdc++6
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: GNU Standard C++ Library v3 (32 bit Version)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+
+Package: lib64stdc++6
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Standard C++ Library v3 (64bit)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libn32stdc++6
+Architecture: mips mipsel mips64 mips64el
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Standard C++ Library v3 (n32)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libx32stdc++6
+Architecture: amd64 i386
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Standard C++ Library v3 (x32)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libhfstdc++6
+Architecture: armel
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libstdc++6-armhf [armel]
+Description: GNU Standard C++ Library v3 (hard float ABI)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libsfstdc++6
+Architecture: armhf
+Section: libs
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libstdc++6-armel [armhf]
+Description: GNU Standard C++ Library v3 (soft float ABI)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libstdc++-6-dev
+Architecture: any
+Multi-Arch: same
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcc-6-dev (= ${gcc:Version}),
+ libstdc++6 (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends}
+Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev,
+ libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev,
+ libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev
+Suggests: libstdc++-6-doc
+Provides: libstdc++-dev
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libstdc++-6-pic
+Architecture: any
+Multi-Arch: same
+Section: libdevel
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (shared library subset kit)
+ This is used to develop subsets of the libstdc++ shared libraries for
+ use on custom installation floppies and in embedded systems.
+ .
+ Unless you are making one of those, you will not need this package.
+
+Package: libstdc++6-6-dbg
+Architecture: any
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
+ libgcc1-dbg (>= ${libgcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: libstdc++6-6-dbg-armel [armel], libstdc++6-6-dbg-armhf [armhf]
+Multi-Arch: same
+Recommends: libstdc++-6-dev (= ${gcc:Version})
+Conflicts: libstdc++5-dbg, libstdc++5-3.3-dbg, libstdc++6-dbg,
+ libstdc++6-4.0-dbg, libstdc++6-4.1-dbg, libstdc++6-4.2-dbg,
+ libstdc++6-4.3-dbg, libstdc++6-4.4-dbg, libstdc++6-4.5-dbg,
+ libstdc++6-4.6-dbg, libstdc++6-4.7-dbg, libstdc++6-4.8-dbg,
+ libstdc++6-4.9-dbg, libstdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: lib32stdc++-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc-6-dev (= ${gcc:Version}),
+ lib32stdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: lib32stdc++6-6-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: lib32stdc++6-dbg, lib32stdc++6-4.0-dbg,
+ lib32stdc++6-4.1-dbg, lib32stdc++6-4.2-dbg, lib32stdc++6-4.3-dbg,
+ lib32stdc++6-4.4-dbg, lib32stdc++6-4.5-dbg, lib32stdc++6-4.6-dbg,
+ lib32stdc++6-4.7-dbg, lib32stdc++6-4.8-dbg, lib32stdc++6-4.9-dbg,
+ lib32stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: lib64stdc++-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc-6-dev (= ${gcc:Version}),
+ lib64stdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: lib64stdc++6-6-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: lib64stdc++6-dbg, lib64stdc++6-4.0-dbg,
+ lib64stdc++6-4.1-dbg, lib64stdc++6-4.2-dbg, lib64stdc++6-4.3-dbg,
+ lib64stdc++6-4.4-dbg, lib64stdc++6-4.5-dbg, lib64stdc++6-4.6-dbg,
+ lib64stdc++6-4.7-dbg, lib64stdc++6-4.8-dbg, lib64stdc++6-4.9-dbg,
+ lib64stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libn32stdc++-6-dev
+Architecture: mips mipsel mips64 mips64el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc-6-dev (= ${gcc:Version}),
+ libn32stdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libn32stdc++6-6-dbg
+Architecture: mips mipsel mips64 mips64el
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libn32stdc++6-dbg, libn32stdc++6-4.0-dbg,
+ libn32stdc++6-4.1-dbg, libn32stdc++6-4.2-dbg, libn32stdc++6-4.3-dbg,
+ libn32stdc++6-4.4-dbg, libn32stdc++6-4.5-dbg, libn32stdc++6-4.6-dbg,
+ libn32stdc++6-4.7-dbg, libn32stdc++6-4.8-dbg, libn32stdc++6-4.9-dbg,
+ libn32stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libx32stdc++-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc-6-dev (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libx32stdc++6-6-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libx32gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libx32stdc++6-dbg, libx32stdc++6-4.6-dbg,
+ libx32stdc++6-4.7-dbg, libx32stdc++6-4.8-dbg, libx32stdc++6-4.9-dbg,
+ libx32stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libhfstdc++-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc-6-dev (= ${gcc:Version}),
+ libhfstdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libhfstdc++6-6-dbg
+Architecture: armel
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfstdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libhfgcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libhfstdc++6-dbg, libhfstdc++6-4.3-dbg, libhfstdc++6-4.4-dbg, libhfstdc++6-4.5-dbg, libhfstdc++6-4.6-dbg, libhfstdc++6-4.7-dbg, libhfstdc++6-4.8-dbg, libhfstdc++6-4.9-dbg, libhfstdc++6-5-dbg, libstdc++6-armhf [armel]
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libsfstdc++-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc-6-dev (= ${gcc:Version}),
+ libsfstdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libsfstdc++6-6-dbg
+Architecture: armhf
+Section: debug
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfstdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libsfgcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libsfstdc++6-dbg, libsfstdc++6-4.3-dbg, libsfstdc++6-4.4-dbg, libsfstdc++6-4.5-dbg, libsfstdc++6-4.6-dbg, libsfstdc++6-4.7-dbg, libsfstdc++6-4.8-dbg, libsfstdc++6-4.9-dbg, libsfstdc++6-5-dbg, libstdc++6-armel [armhf]
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libstdc++-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Conflicts: libstdc++5-doc, libstdc++5-3.3-doc, libstdc++6-doc,
+ libstdc++6-4.0-doc, libstdc++6-4.1-doc, libstdc++6-4.2-doc, libstdc++6-4.3-doc,
+ libstdc++6-4.4-doc, libstdc++6-4.5-doc, libstdc++6-4.6-doc, libstdc++6-4.7-doc,
+ libstdc++-4.8-doc, libstdc++-4.9-doc, libstdc++-5-doc
+Description: GNU Standard C++ Library v3 (documentation files)
+ This package contains documentation files for the GNU stdc++ library.
+ .
+ One set is the distribution documentation, the other set is the
+ source documentation including a namespace list, class hierarchy,
+ alphabetical list, compound list, file list, namespace members,
+ compound members and file members.
+
+Package: gnat-6
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (>= ${gcc:SoftVersion}), ${dep:libgnat}, ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: gnat-6-doc, ada-reference-manual-2012, gnat-6-sjlj
+Breaks:   gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+Replaces: gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+# Takes over symlink from gnat (<< 4.6.1): /usr/bin/gnatgcc.
+# Takes over file from dh-ada-library (<< 6.0): debian_packaging.mk.
+# g-base 4.6.4-2, 4.9-20140330-1 contain debian_packaging.mk by mistake.
+# Newer versions of gnat and dh-ada-library will not provide these files.
+Conflicts: gnat (<< 4.1), gnat-3.1, gnat-3.2, gnat-3.3, gnat-3.4, gnat-3.5,
+ gnat-4.0, gnat-4.1, gnat-4.2, gnat-4.3, gnat-4.4, gnat-4.6, gnat-4.7, gnat-4.8,
+ gnat-4.9, gnat-5
+# These other packages will continue to provide /usr/bin/gnatmake and
+# other files.
+Description: GNU Ada compiler
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides the compiler, tools and runtime library that handles
+ exceptions using the default zero-cost mechanism.
+
+Package: gnat-6-sjlj
+Architecture: any
+Priority: extra
+Pre-Depends: ${misc:Pre-Depends}
+Depends: gcc-6-base (= ${gcc:Version}), gnat-6 (= ${gnat:Version}), ${misc:Depends}
+Description: GNU Ada compiler (setjump/longjump runtime library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides an alternative runtime library that handles
+ exceptions using the setjump/longjump mechanism (as a static library
+ only).  You can install it to supplement the normal compiler.
+
+Package: libgnat-6
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: runtime for applications compiled with GNAT (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnat-6-dbg
+Section: debug
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgnat-6 (= ${gnat:Version}), ${misc:Depends}
+Description: runtime for applications compiled with GNAT (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatvsn6-dev
+Section: libdevel
+Architecture: any
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), gnat-6 (= ${gnat:Version}),
+ libgnatvsn6 (= ${gnat:Version}), ${misc:Depends}
+Conflicts: libgnatvsn-dev (<< 6),
+ libgnatvsn4.1-dev, libgnatvsn4.3-dev, libgnatvsn4.4-dev,
+ libgnatvsn4.5-dev, libgnatvsn4.6-dev, libgnatvsn4.9-dev,
+ libgnatvsn5-dev,
+Description: GNU Ada compiler selected components (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatvsn6
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Section: libs
+Depends: gcc-6-base (= ${gcc:Version}), libgnat-6 (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Ada compiler selected components (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatvsn6-dbg
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: extra
+Section: debug
+Depends: gcc-6-base (= ${gcc:Version}), libgnatvsn6 (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+Description: GNU Ada compiler selected components (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatprj6-dev
+Section: libdevel
+Architecture: any
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), gnat-6 (= ${gnat:Version}),
+ libgnatprj6 (= ${gnat:Version}),
+ libgnatvsn6-dev (= ${gnat:Version}), ${misc:Depends}
+Conflicts: libgnatprj-dev (<< 6),
+ libgnatprj4.1-dev, libgnatprj4.3-dev, libgnatprj4.4-dev,
+ libgnatprj4.5-dev, libgnatprj4.6-dev, libgnatprj4.9-dev,
+ libgnatprj5-dev,
+Description: GNU Ada compiler Project Manager (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatprj6
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Section: libs
+Depends: gcc-6-base (= ${gcc:Version}), libgnat-6 (= ${gnat:Version}),
+ libgnatvsn6 (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Ada compiler Project Manager (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatprj6-dbg
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: extra
+Section: debug
+Depends: gcc-6-base (= ${gcc:Version}), libgnatprj6 (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+Description: GNU Ada compiler Project Manager (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the debugging symbols.
+
+Package: gnat-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Suggests: gnat-6
+Conflicts: gnat-4.1-doc, gnat-4.2-doc,
+  gnat-4.3-doc, gnat-4.4-doc, 
+  gnat-4.6-doc, gnat-4.9-doc, 
+  gnat-5-doc, 
+Description: GNU Ada compiler (documentation)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the documentation in info format.
+
+Package: gdc-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), g++-6 (>= ${gcc:SoftVersion}), ${dep:gdccross}, ${dep:phobosdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: gdc, d-compiler, d-v2-compiler
+Replaces: gdc (<< 4.4.6-5)
+Description: GNU D compiler (version 2)
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This compiler supports D language version 2.
+
+Package: gdc-6-multilib
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), gdc-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libphobosbiarchdev}${shlibs:Depends}, ${misc:Depends}
+Description: GNU D compiler (version 2, multilib support)
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: libgphobos-6-dev
+Architecture: amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+Multi-Arch: same
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgphobos68 (>= ${gdc:Version}),
+  zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libphobos-6-dev
+Description: Phobos D standard library
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos68
+Section: libs
+Architecture: amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+Multi-Arch: same
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos68-dbg
+Section: debug
+Architecture: amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+Multi-Arch: same
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libgphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gphobos68 (>= ${gdc:Version}),
+  lib64gcc-6-dev (= ${gcc:Version}), lib64z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64phobos-6-dev
+Description: Phobos D standard library (64bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos68
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos68-dbg
+Section: debug
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib64gphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gphobos68 (>= ${gdc:Version}),
+  lib32gcc-6-dev (= ${gcc:Version}), lib32z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib32phobos-6-dev
+Description: Phobos D standard library (32bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos68
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos68-dbg
+Section: debug
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), lib32gphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gphobos68 (>= ${gdc:Version}),
+  libx32gcc-6-dev (= ${gcc:Version}), ${dep:libx32z}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32gphobos-6-dev
+Description: Phobos D standard library (x32 development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos68
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos68-dbg
+Section: debug
+Architecture: amd64 i386
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libx32gphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgphobos68 (>= ${gdc:Version}),
+  libhfgcc-6-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libhfphobos-6-dev
+Description: Phobos D standard library (hard float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos68
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos68-dbg
+Section: debug
+Architecture: armel
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libhfgphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgphobos68 (>= ${gdc:Version}),
+  libsfgcc-6-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libsfphobos-6-dev
+Description: Phobos D standard library (soft float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos68
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos68-dbg
+Section: debug
+Architecture: armhf
+Priority: extra
+Depends: gcc-6-base (= ${gcc:Version}), libsfgphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+#Package: gcc`'PV-soft-float
+#Architecture: arm armel armhf
+#Priority: PRI(optional)
+#Depends: BASEDEP, depifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends}
+#Conflicts: gcc-4.4-soft-float, gcc-4.5-soft-float, gcc-4.6-soft-float
+#BUILT_USING`'dnl
+#Description: GCC soft-floating-point gcc libraries (ARM)
+# These are versions of basic static libraries such as libgcc.a compiled
+# with the -msoft-float option, for CPUs without a floating-point unit.
+
+Package: fixincludes
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Fix non-ANSI header files
+ FixIncludes was created to fix non-ANSI system header files. Many
+ system manufacturers supply proprietary headers that are not ANSI compliant.
+ The GNU compilers cannot compile non-ANSI headers. Consequently, the
+ FixIncludes shell script was written to fix the header files.
+ .
+ Not all packages with header files are installed on the system, when the
+ package is built, so we make fixincludes available at build time of other
+ packages, such that checking tools like lintian can make use of it.
+
+Package: gcc-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Conflicts: gcc-docs (<< 2.95.2)
+Replaces: gcc (<=2.7.2.3-4.3), gcc-docs (<< 2.95.2)
+Description: Documentation for the GNU compilers (gcc, gobjc, g++)
+ Documentation for the GNU compilers in info format.
+
+Package: gcc-6-source
+Architecture: all
+Priority: optional
+Depends: make, autoconf2.64, quilt, patchutils, sharutils, gawk, ${misc:Depends}
+Description: Source of the GNU Compiler Collection
+ This package contains the sources and patches which are needed to
+ build the GNU Compiler Collection (GCC).
--- gcc-6-6.3.0.orig/debian/control.m4
+++ gcc-6-6.3.0/debian/control.m4
@@ -0,0 +1,5478 @@
+divert(-1)
+
+define(`checkdef',`ifdef($1, , `errprint(`error: undefined macro $1
+')m4exit(1)')')
+define(`errexit',`errprint(`error: undefined macro `$1'
+')m4exit(1)')
+
+dnl The following macros must be defined, when called:
+dnl ifdef(`SRCNAME',	, errexit(`SRCNAME'))
+dnl ifdef(`PV',		, errexit(`PV'))
+dnl ifdef(`ARCH',		, errexit(`ARCH'))
+
+dnl The architecture will also be defined (-D__i386__, -D__powerpc__, etc.)
+
+define(`PN', `$1')
+ifdef(`PRI', `', `
+    define(`PRI', `$1')
+')
+define(`MAINTAINER', `Debian GCC Maintainers <debian-gcc@lists.debian.org>')
+
+define(`depifenabled', `ifelse(index(enabled_languages, `$1'), -1, `', `$2')')
+define(`ifenabled', `ifelse(index(enabled_languages, `$1'), -1, `dnl', `$2')')
+
+ifdef(`TARGET',`ifdef(`CROSS_ARCH',`',`undefine(`MULTIARCH')')')
+define(`CROSS_ARCH', ifdef(`CROSS_ARCH', CROSS_ARCH, `all'))
+define(`libdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+define(`libdevdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+define(`libidevdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+ifdef(`TARGET',`ifelse(CROSS_ARCH,`all',`
+define(`libidevdep', `lib$2$1`'LS`'AQ (>= ifelse(`$4',`',`${gcc:SoftVersion}',`$4'))')
+')')
+define(`libdbgdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+
+define(`BUILT_USING', ifelse(add_built_using,yes,`Built-Using: ${Built-Using}
+'))
+
+divert`'dnl
+dnl --------------------------------------------------------------------------
+Source: SRCNAME
+Section: devel
+Priority: PRI(optional)
+ifelse(DIST,`Ubuntu',`dnl
+ifelse(regexp(SRCNAME, `gnat\|gdc-'),0,`dnl
+Maintainer: Ubuntu MOTU Developers <ubuntu-motu@lists.ubuntu.com>
+', `dnl
+Maintainer: Ubuntu Core developers <ubuntu-devel-discuss@lists.ubuntu.com>
+')dnl SRCNAME
+XSBC-Original-Maintainer: MAINTAINER
+', `dnl
+Maintainer: MAINTAINER
+')dnl DIST
+ifelse(regexp(SRCNAME, `gnat'),0,`dnl
+Uploaders: Ludovic Brenta <lbrenta@debian.org>
+', regexp(SRCNAME, `gdc'),0,`dnl
+Uploaders: Iain Buclaw <ibuclaw@ubuntu.com>, Matthias Klose <doko@debian.org>
+', `dnl
+Uploaders: Matthias Klose <doko@debian.org>
+')dnl SRCNAME
+Standards-Version: 3.9.8
+ifdef(`TARGET',`dnl cross
+Build-Depends: DEBHELPER_BUILD_DEP DPKG_BUILD_DEP
+  LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP
+  kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], linux-libc-dev [m68k],
+  LIBUNWIND_BUILD_DEP LIBATOMIC_OPS_BUILD_DEP AUTO_BUILD_DEP
+  SOURCE_BUILD_DEP CROSS_BUILD_DEP
+  ISL_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP
+  autogen, zlib1g-dev, gawk, lzma, xz-utils, patchutils,
+  pkg-config, libgc-dev,
+  zlib1g-dev, SDT_BUILD_DEP
+  bison (>= 1:2.3), flex, realpath (>= 1.9.12), lsb-release, quilt
+',`dnl native
+Build-Depends: DEBHELPER_BUILD_DEP DPKG_BUILD_DEP
+  GCC_MULTILIB_BUILD_DEP
+  LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP LIBC_DBG_DEP
+  kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], linux-libc-dev [m68k],
+  AUTO_BUILD_DEP BASE_BUILD_DEP
+  libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64],
+  autogen, gawk, lzma, xz-utils, patchutils,
+  zlib1g-dev, SDT_BUILD_DEP
+  BINUTILS_BUILD_DEP,
+  gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext,
+  gdb`'NT,
+  texinfo (>= 4.3), locales, sharutils,
+  procps, FORTRAN_BUILD_DEP JAVA_BUILD_DEP GNAT_BUILD_DEP GO_BUILD_DEP GDC_BUILD_DEP
+  ISL_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP PHOBOS_BUILD_DEP
+  CHECK_BUILD_DEP realpath (>= 1.9.12), chrpath, lsb-release, quilt,
+  pkg-config, libgc-dev,
+  TARGET_TOOL_BUILD_DEP
+Build-Depends-Indep: LIBSTDCXX_BUILD_INDEP JAVA_BUILD_INDEP
+')dnl
+ifelse(regexp(SRCNAME, `gnat'),0,`dnl
+Homepage: http://gcc.gnu.org/
+', regexp(SRCNAME, `gdc'),0,`dnl
+Homepage: http://gdcproject.org/
+', `dnl
+Homepage: http://gcc.gnu.org/
+')dnl SRCNAME
+Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc`'PV/
+Vcs-Svn: svn://anonscm.debian.org/gcccvs/branches/sid/gcc`'PV
+
+ifelse(regexp(SRCNAME, `gcc-snapshot'),0,`dnl
+Package: gcc-snapshot`'TS
+Architecture: any
+Section: devel
+Priority: extra
+Depends: binutils`'TS (>= ${binutils:Version}), ${dep:libcbiarchdev}, ${dep:libcdev}, ${dep:libunwinddev}, ${snap:depends}, ${shlibs:Depends}, ${dep:ecj}, python, ${misc:Depends}
+Recommends: ${snap:recommends}
+Suggests: ${dep:gold}
+Provides: c++-compiler`'TS`'ifdef(`TARGET',`',`, c++abi2-dev')
+BUILT_USING`'dnl
+Description: SNAPSHOT of the GNU Compiler Collection
+ This package contains a recent development SNAPSHOT of all files
+ contained in the GNU Compiler Collection (GCC).
+ .
+ The source code for this package has been exported from SVN trunk.
+ .
+ DO NOT USE THIS SNAPSHOT FOR BUILDING DEBIAN PACKAGES!
+ .
+ This package will NEVER hit the testing distribution. It is used for
+ tracking gcc bugs submitted to the Debian BTS in recent development
+ versions of gcc.
+',`dnl gcc-X.Y
+
+dnl default base package dependencies
+define(`BASEDEP', `gcc`'PV`'TS-base (= ${gcc:Version})')
+define(`SOFTBASEDEP', `gcc`'PV`'TS-base (>= ${gcc:SoftVersion})')
+
+ifdef(`TARGET',`
+define(`BASELDEP', `gcc`'PV-cross-base`'GCC_PORTS_BUILD (= ${gcc:Version})')
+define(`SOFTBASELDEP', `gcc`'PV-cross-base`'GCC_PORTS_BUILD (>= ${gcc:SoftVersion})')
+',`dnl
+define(`BASELDEP', `BASEDEP')
+define(`SOFTBASELDEP', `SOFTBASEDEP')
+')
+
+dnl base, when building libgcc out of the gcj source; needed if new symbols
+dnl in libgcc are used in libgcj.
+ifelse(index(SRCNAME, `gcj'), 0, `
+define(`BASEDEP', `gcj`'PV-base (= ${gcj:Version})')
+define(`SOFTBASEDEP', `gcj`'PV-base (>= ${gcj:SoftVersion})')
+')
+
+ifelse(index(SRCNAME, `gnat'), 0, `
+define(`BASEDEP', `gnat`'PV-base (= ${gnat:Version})')
+define(`SOFTBASEDEP', `gnat`'PV-base (>= ${gnat:SoftVersion})')
+')
+
+ifenabled(`gccbase',`
+Package: gcc`'PV`'TS-base
+Architecture: any
+Multi-Arch: same
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',`PRI(required)')
+Depends: ${misc:Depends}
+Replaces: ${base:Replaces}
+Breaks: ${base:Breaks}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (base package)
+ This package contains files common to all languages and libraries
+ contained in the GNU Compiler Collection (GCC).
+ifdef(`BASE_ONLY', `dnl
+ .
+ This version of GCC is not yet available for this architecture.
+ Please use the compilers from the gcc-snapshot package for testing.
+')`'dnl
+')`'dnl gccbase
+
+ifenabled(`gcclbase',`
+Package: gcc`'PV-cross-base`'GCC_PORTS_BUILD
+Architecture: all
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',`PRI(required)')
+Depends: ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (library base package)
+ This empty package contains changelog and copyright files common to
+ all libraries contained in the GNU Compiler Collection (GCC).
+ifdef(`BASE_ONLY', `dnl
+ .
+ This version of GCC is not yet available for this architecture.
+ Please use the compilers from the gcc-snapshot package for testing.
+')`'dnl
+')`'dnl gcclbase
+
+ifenabled(`java',`
+ifdef(`TARGET', `', `
+ifenabled(`gcjbase',`
+Package: gcj`'PV-base
+Architecture: any
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: libs
+Priority: PRI(optional)
+Depends: ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (gcj base package)
+ This package contains files common to all java related packages
+ built from the GNU Compiler Collection (GCC).
+')`'dnl gccbase
+')`'dnl native
+
+ifenabled(`gcjxbase',`
+dnl override default base package dependencies to cross version
+dnl This creates a toolchain that doesnt depend on the system -base packages
+define(`BASEDEP', `gcj`'`PV`'TS'-base (= ${gcc:Version})')
+define(`SOFTBASEDEP', `gcj`'`PV`'TS'-base (>= ${gcc:SoftVersion})')
+
+Package: gcj`'`PV`'TS'-base
+Architecture: any
+Section: devel
+Priority: PRI(extra)
+Depends: ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (gcj base package)
+ This package contains files common to all java related packages
+ built from the GNU Compiler Collection (GCC).
+')`'dnl
+')`'dnl java
+
+ifenabled(`gnatbase',`
+Package: gnat`'PV-base`'TS
+Architecture: any
+# "all" causes build instabilities for "any" dependencies (see #748388).
+Section: libs
+Priority: PRI(optional)
+Depends: ${misc:Depends}
+Breaks: gcc-4.6 (<< 4.6.1-8~)
+BUILT_USING`'dnl
+Description: GNU Ada compiler (common files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package contains files common to all GNAT related packages.
+')`'dnl gnatbase
+
+ifenabled(`libgcc',`
+Package: libgcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',required)
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+Provides: ifdef(`TARGET',`libgcc1-TARGET-dcv1',`libgcc1-armel [armel], libgcc1-armhf [armhf]')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `')
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc1,,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf]
+')dnl
+ifdef(`MULTIARCH',`Multi-Arch: same
+')dnl
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc2`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',required)
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libgcc2-TARGET-dcv1
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `')
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc2-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc2,,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libgcc
+
+ifenabled(`cdev',`
+Package: libgcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm},
+ ${dep:libatomic}, ${dep:libbtrace}, ${dep:libasan}, ${dep:liblsan},
+ ${dep:libtsan}, ${dep:libubsan}, ${dep:libcilkrts}, ${dep:libvtv},
+ ${dep:libmpx},
+ ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Replaces: gccgo-6 (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl libgcc
+
+Package: libgcc4`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',required)
+Depends: ifdef(`STANDALONEJAVA',`gcj`'PV-base (>= ${gcj:Version})',`BASELDEP'), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `')
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc4-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc4,,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+ifenabled(`lib64gcc',`
+Package: lib64gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib64gcc1-TARGET-dcv1
+',`')`'dnl
+Conflicts: libdep(gcc`'GCC_SO,,<=,1:3.3-0pre9)
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (64bit)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib64gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc1,64,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib64gcc
+
+ifenabled(`cdev',`
+Package: lib64gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (64bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl cdev
+
+ifenabled(`lib32gcc',`
+Package: lib32gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+ifdef(`TARGET',`Provides: lib32gcc1-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library (32 bit Version)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib32gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc1,32,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib32gcc1
+
+ifenabled(`cdev',`
+Package: lib32gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (32 bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl cdev
+
+ifenabled(`libneongcc',`
+Package: libgcc1-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library [neon optimized]
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneongcc1
+
+ifenabled(`libhfgcc',`
+Package: libhfgcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libhfgcc1-TARGET-dcv1
+',`Conflicts: libgcc1-armhf [biarchhf_archs]
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libhfgcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc1,hf,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libhfgcc
+
+ifenabled(`cdev',`
+ifenabled(`armml',`
+Package: libhfgcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (hard float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl armml
+')`'dnl cdev
+
+ifenabled(`libsfgcc',`
+Package: libsfgcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libsfgcc1-TARGET-dcv1
+',`Conflicts: libgcc1-armel [biarchsf_archs]
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libsfgcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc1,sf,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libsfgcc
+
+ifenabled(`cdev',`
+ifenabled(`armml',`
+Package: libsfgcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (soft float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl armml
+')`'dnl cdev
+
+ifenabled(`libn32gcc',`
+Package: libn32gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: libdep(gcc`'GCC_SO,,<=,1:3.3-0pre9)
+ifdef(`TARGET',`Provides: libn32gcc1-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (n32)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libn32gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc1,n32,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libn32gcc
+
+ifenabled(`cdev',`
+Package: libn32gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (n32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl cdev
+
+ifenabled(`libx32gcc',`
+Package: libx32gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libx32gcc1-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (x32)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libx32gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gcc1,x32,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libx32gcc
+
+ifenabled(`cdev',`
+ifenabled(`x32dev',`
+Package: libx32gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (x32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl x32dev
+')`'dnl cdev
+
+ifenabled(`cdev',`
+Package: gcc`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: cpp`'PV`'TS (= ${gcc:Version}),ifenabled(`gccbase',` BASEDEP,')
+  ifenabled(`gccxbase',` BASEDEP,')
+  ${dep:libcc1},
+  binutils`'TS (>= ${binutils:Version}),
+  ${dep:libgccdev}, ${shlibs:Depends}, ${misc:Depends}
+Recommends: ${dep:libcdev}
+Replaces: gccgo-6 (<< ${gcc:Version})
+Suggests: ${gcc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}),
+ gcc`'PV-locales (>= ${gcc:SoftVersion}),
+ libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}),
+ libdbgdep(gomp`'GOMP_SO-dbg,),
+ libdbgdep(itm`'ITM_SO-dbg,),
+ libdbgdep(atomic`'ATOMIC_SO-dbg,),
+ libdbgdep(asan`'ASAN_SO-dbg,),
+ libdbgdep(lsan`'LSAN_SO-dbg,),
+ libdbgdep(tsan`'TSAN_SO-dbg,),
+ libdbgdep(ubsan`'UBSAN_SO-dbg,),
+ifenabled(`libvtv',`',`
+ libdbgdep(vtv`'VTV_SO-dbg,),
+')`'dnl
+ libdbgdep(cilkrts`'CILKRTS_SO-dbg,),
+ libdbgdep(mpx`'MPX_SO-dbg,),
+ libdbgdep(quadmath`'QMATH_SO-dbg,)
+Provides: c-compiler`'TS
+ifdef(`TARGET',`Conflicts: gcc-multilib
+')`'dnl
+BUILT_USING`'dnl
+Description: GNU C compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+ifdef(`TARGET', `dnl
+ .
+ This package contains C cross-compiler for TARGET architecture.
+')`'dnl
+
+ifenabled(`multilib',`
+Package: gcc`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU C compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`testresults',`
+Package: gcc`'PV-test-results
+Architecture: any
+Section: devel
+Priority: extra
+Depends: BASEDEP, ${misc:Depends}
+Replaces: g++-5 (<< 5.2.1-28)
+BUILT_USING`'dnl
+Description: Test results for the GCC test suite
+ This package contains the test results for running the GCC test suite
+ for a post build analysis.
+')`'dnl testresults
+
+ifenabled(`plugindev',`
+Package: gcc`'PV-plugin-dev`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), GMP_BUILD_DEP MPC_BUILD_DEP ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Files for GNU GCC plugin development.
+ This package contains (header) files for GNU GCC plugin development. It
+ is only used for the development of GCC plugins, but not needed to run
+ plugins.
+')`'dnl plugindev
+')`'dnl cdev
+
+ifenabled(`cdev',`
+Package: gcc`'PV-hppa64-linux-gnu
+Architecture: ifdef(`TARGET',`any',hppa amd64 i386 x32)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: PRI(optional)
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}),
+  binutils-hppa64-linux-gnu | binutils-hppa64,
+  ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU C compiler (cross compiler for hppa64)
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+')`'dnl cdev
+
+ifenabled(`cdev',`
+Package: cpp`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: ifdef(`TARGET',`devel',`interpreters')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+Suggests: gcc`'PV-locales (>= ${gcc:SoftVersion})
+Replaces: gccgo-6 (<< ${gcc:Version})
+Breaks: libmagics++-dev (<< 2.28.0-4)ifdef(`TARGET',`',`, hardening-wrapper (<< 2.8+nmu3)')
+BUILT_USING`'dnl
+Description: GNU C preprocessor
+ A macro processor that is used automatically by the GNU C compiler
+ to transform programs before actual compilation.
+ .
+ This package has been separated from gcc for the benefit of those who
+ require the preprocessor but not the compiler.
+ifdef(`TARGET', `dnl
+ .
+ This package contains preprocessor configured for TARGET architecture.
+')`'dnl
+
+ifdef(`TARGET', `', `
+ifenabled(`gfdldoc',`
+Package: cpp`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU C preprocessor (cpp)
+ Documentation for the GNU C preprocessor in info `format'.
+')`'dnl gfdldoc
+')`'dnl native
+
+ifdef(`TARGET', `', `
+Package: gcc`'PV-locales
+Architecture: all
+Section: devel
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, cpp`'PV (>= ${gcc:SoftVersion}), ${misc:Depends}
+Recommends: gcc`'PV (>= ${gcc:SoftVersion})
+Description: GCC, the GNU compiler collection (native language support files)
+ Native language support for GCC. Lets GCC speak your language,
+ if translations are available.
+ .
+ Please do NOT submit bug reports in other languages than "C".
+ Always reset your language settings to use the "C" locales.
+')`'dnl native
+')`'dnl cdev
+
+ifenabled(`c++',`
+ifenabled(`c++dev',`
+Package: g++`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libidevdep(stdc++`'PV-dev,,=), ${shlibs:Depends}, ${misc:Depends}
+Provides: c++-compiler`'TS`'ifdef(`TARGET)',`',`, c++abi2-dev')
+Suggests: ${gxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(stdc++CXX_SO`'PV-dbg,)
+BUILT_USING`'dnl
+Description: GNU C++ compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+ifdef(`TARGET', `dnl
+ .
+ This package contains C++ cross-compiler for TARGET architecture.
+')`'dnl
+
+ifenabled(`multilib',`
+Package: g++`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libcxxbiarchdbg}
+BUILT_USING`'dnl
+Description: GNU C++ compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+')`'dnl c++dev
+')`'dnl c++
+
+ifdef(`TARGET', `', `
+ifenabled(`ssp',`
+Package: libssp`'SSP_SO`'LS
+Architecture: any
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: lib32ssp`'SSP_SO`'LS
+Architecture: biarch32_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (32bit)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: lib64ssp`'SSP_SO`'LS
+Architecture: biarch64_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (64bit)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libn32ssp`'SSP_SO`'LS
+Architecture: biarchn32_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (n32)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libx32ssp`'SSP_SO`'LS
+Architecture: biarchx32_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (x32)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libhfssp`'SSP_SO`'LS
+Architecture: biarchhf_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (hard float ABI)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libsfssp`'SSP_SO`'LS
+Architecture: biarchsf_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (soft float ABI)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+')`'dnl
+')`'dnl native
+
+ifenabled(`libgomp',`
+Package: libgomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgomp'GOMP_SO`-armel [armel], libgomp'GOMP_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libgomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libgomp'GOMP_SO`-dbg-armel [armel], libgomp'GOMP_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib32gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (32bit)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib32gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (32 bit debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib64gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (64bit)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib64gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (64bit debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libn32gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (n32)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libn32gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (n32 debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+
+ifenabled(`libx32gomp',`
+Package: libx32gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (x32)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libx32gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (x32 debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+')`'dnl libx32gomp
+
+ifenabled(`libhfgomp',`
+Package: libhfgomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (hard float ABI)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libhfgomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (hard float ABI debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+')`'dnl libhfgomp
+
+ifenabled(`libsfgomp',`
+Package: libsfgomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (soft float ABI)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libsfgomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,sf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (soft float ABI debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+')`'dnl libsfgomp
+
+ifenabled(`libneongomp',`
+Package: libgomp`'GOMP_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library [neon optimized]
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneongomp
+')`'dnl libgomp
+
+ifenabled(`libitm',`
+Package: libitm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libitm'ITM_SO`-armel [armel], libitm'ITM_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libitm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(itm`'ITM_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libitm'ITM_SO`-dbg-armel [armel], libitm'ITM_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib32itm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (32bit)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib32itm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(itm`'ITM_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (32 bit debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib64itm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (64bit)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib64itm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(itm`'ITM_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (64bit debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+#Package: libn32itm`'ITM_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GNU Transactional Memory Library (n32)
+# GNU Transactional Memory Library (libitm) provides transaction support for
+# accesses to the memory of a process, enabling easy-to-use synchronization of
+# accesses to shared memory by several threads.
+
+#Package: libn32itm`'ITM_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(itm`'ITM_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GNU Transactional Memory Library (n32 debug symbols)
+# GNU Transactional Memory Library (libitm) provides transaction support for
+# accesses to the memory of a process, enabling easy-to-use synchronization of
+# accesses to shared memory by several threads.
+
+ifenabled(`libx32itm',`
+Package: libx32itm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (x32)
+ This manual documents the usage and internals of libitm. It provides
+ transaction support for accesses to the memory of a process, enabling
+ easy-to-use synchronization of accesses to shared memory by several threads.
+
+Package: libx32itm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(itm`'ITM_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (x32 debug symbols)
+ This manual documents the usage and internals of libitm. It provides
+ transaction support for accesses to the memory of a process, enabling
+ easy-to-use synchronization of accesses to shared memory by several threads.
+')`'dnl libx32itm
+
+ifenabled(`libhfitm',`
+Package: libhfitm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (hard float ABI)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libhfitm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(itm`'ITM_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (hard float ABI debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+')`'dnl libhfitm
+
+ifenabled(`libsfitm',`
+Package: libsfitm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (soft float ABI)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libsfitm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(itm`'ITM_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (soft float ABI debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+')`'dnl libsfitm
+
+ifenabled(`libneonitm',`
+Package: libitm`'ITM_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library [neon optimized]
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonitm
+')`'dnl libitm
+
+ifenabled(`libatomic',`
+Package: libatomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libatomic'ATOMIC_SO`-armel [armel], libatomic'ATOMIC_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libatomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libatomic'ATOMIC_SO`-dbg-armel [armel], libatomic'ATOMIC_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib32atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (32bit)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib32atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (32 bit debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib64atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (64bit)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib64atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (64bit debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libn32atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (n32)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libn32atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (n32 debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+ifenabled(`libx32atomic',`
+Package: libx32atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (x32)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libx32atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (x32 debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+')`'dnl libx32atomic
+
+ifenabled(`libhfatomic',`
+Package: libhfatomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libatomic'ATOMIC_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (hard float ABI)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libhfatomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libatomic'ATOMIC_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (hard float ABI debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+')`'dnl libhfatomic
+
+ifenabled(`libsfatomic',`
+Package: libsfatomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (soft float ABI)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libsfatomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (soft float ABI debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+')`'dnl libsfatomic
+
+ifenabled(`libneonatomic',`
+Package: libatomic`'ATOMIC_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions [neon optimized]
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonatomic
+')`'dnl libatomic
+
+ifenabled(`libasan',`
+Package: libasan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libasan'ASAN_SO`-armel [armel], libasan'ASAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libasan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(asan`'ASAN_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libasan'ASAN_SO`-dbg-armel [armel], libasan'ASAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (32bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(asan`'ASAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (32 bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (64bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(asan`'ASAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (64bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(extra)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(asan`'ASAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32 debug symbols)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+ifenabled(`libx32asan',`
+Package: libx32asan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (x32)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libx32asan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(asan`'ASAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (x32 debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+')`'dnl libx32asan
+
+ifenabled(`libhfasan',`
+Package: libhfasan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(extra)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libasan'ASAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libhfasan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(asan`'ASAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libasan'ASAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+')`'dnl libhfasan
+
+ifenabled(`libsfasan',`
+Package: libsfasan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(extra)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libsfasan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(asan`'ASAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+')`'dnl libsfasan
+
+ifenabled(`libneonasan',`
+Package: libasan`'ASAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector [neon optimized]
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonasan
+')`'dnl libasan
+
+ifenabled(`liblsan',`
+Package: liblsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (runtime)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: liblsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,,=), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+ifenabled(`lib32lsan',`
+Package: lib32lsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (32bit)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+Package: lib32lsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (32 bit debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+')`'dnl lib32lsan
+
+ifenabled(`lib64lsan',`
+#Package: lib64lsan`'LSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (64bit)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+#Package: lib64lsan`'LSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(lsan`'LSAN_SO,64,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (64bit debug symbols)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+')`'dnl lib64lsan
+
+ifenabled(`libn32lsan',`
+#Package: libn32lsan`'LSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (n32)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+#Package: libn32lsan`'LSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(lsan`'LSAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (n32 debug symbols)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+')`'dnl libn32lsan
+
+ifenabled(`libx32lsan',`
+Package: libx32lsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (x32)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+Package: libx32lsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (x32 debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+')`'dnl libx32lsan
+
+ifenabled(`libhflsan',`
+Package: libhflsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: liblsan'LSAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (hard float ABI)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: libhflsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: liblsan'LSAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (hard float ABI debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+')`'dnl libhflsan
+
+ifenabled(`libsflsan',`
+Package: libsflsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (soft float ABI)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: libsflsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (soft float ABI debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+')`'dnl libsflsan
+
+ifenabled(`libneonlsan',`
+Package: liblsan`'LSAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector [neon optimized]
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonlsan
+')`'dnl liblsan
+
+ifenabled(`libtsan',`
+Package: libtsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libtsan'TSAN_SO`-armel [armel], libtsan'TSAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (runtime)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libtsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libtsan'TSAN_SO`-dbg-armel [armel], libtsan'TSAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+ifenabled(`lib32tsan',`
+Package: lib32tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (32bit)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: lib32tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (32 bit debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl lib32tsan
+
+ifenabled(`lib64tsan',`
+Package: lib64tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (64bit)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: lib64tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (64bit debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl lib64tsan
+
+ifenabled(`libn32tsan',`
+Package: libn32tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (n32)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libn32tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (n32 debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl libn32tsan
+
+ifenabled(`libx32tsan',`
+Package: libx32tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (x32)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libx32tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (x32 debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl libx32tsan
+
+ifenabled(`libhftsan',`
+Package: libhftsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libtsan'TSAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (hard float ABI)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libhftsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libtsan'TSAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (hard float ABI debug symbols)
+')`'dnl libhftsan
+
+ifenabled(`libsftsan',`
+Package: libsftsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (soft float ABI)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libsftsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (soft float ABI debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl libsftsan
+
+ifenabled(`libneontsan',`
+Package: libtsan`'TSAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races [neon optimized]
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneontsan
+')`'dnl libtsan
+
+ifenabled(`libubsan',`
+Package: libubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libubsan'UBSAN_SO`-armel [armel], libubsan'UBSAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (runtime)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libubsan'UBSAN_SO`-dbg-armel [armel], libubsan'UBSAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+ifenabled(`lib32ubsan',`
+Package: lib32ubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (32bit)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib32ubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (32 bit debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl lib32ubsan
+
+ifenabled(`lib64ubsan',`
+Package: lib64ubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (64bit)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib64ubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (64bit debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl lib64ubsan
+
+ifenabled(`libn32ubsan',`
+#Package: libn32ubsan`'UBSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: UBSan -- undefined behaviour sanitizer (n32)
+# UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+# Various computations will be instrumented to detect undefined behavior
+# at runtime. Available for C and C++.
+
+#Package: libn32ubsan`'UBSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: UBSan -- undefined behaviour sanitizer (n32 debug symbols)
+# UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+# Various computations will be instrumented to detect undefined behavior
+# at runtime. Available for C and C++.
+')`'dnl libn32ubsan
+
+ifenabled(`libx32ubsan',`
+Package: libx32ubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (x32)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libx32ubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (x32 debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl libx32ubsan
+
+ifenabled(`libhfubsan',`
+Package: libhfubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libubsan'UBSAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (hard float ABI)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libhfubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libubsan'UBSAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (hard float ABI debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl libhfubsan
+
+ifenabled(`libsfubsan',`
+Package: libsfubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (soft float ABI)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libsfubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (soft float ABI debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl libsfubsan
+
+ifenabled(`libneonubsan',`
+Package: libubsan`'UBSAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer [neon optimized]
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonubsan
+')`'dnl libubsan
+
+ifenabled(`libvtv',`
+Package: libvtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (runtime)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libvtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(vtv`'VTV_SO,,=), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GNU vtable verification library (debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+ifenabled(`lib32vtv',`
+Package: lib32vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (32bit)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: lib32vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(vtv`'VTV_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (32 bit debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl lib32vtv
+
+ifenabled(`lib64vtv',`
+Package: lib64vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (64bit)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: lib64vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(vtv`'VTV_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (64bit debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl lib64vtv
+
+ifenabled(`libn32vtv',`
+Package: libn32vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (n32)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libn32vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(vtv`'VTV_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (n32 debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libn32vtv
+
+ifenabled(`libx32vtv',`
+Package: libx32vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (x32)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libx32vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(vtv`'VTV_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (x32 debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libx32vtv
+
+ifenabled(`libhfvtv',`
+Package: libhfvtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libvtv'VTV_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU vtable verification library (hard float ABI)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libhfvtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(vtv`'VTV_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libvtv'VTV_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU vtable verification library (hard float ABI debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libhfvtv
+
+ifenabled(`libsfvtv',`
+Package: libsfvtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (soft float ABI)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libsfvtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(vtv`'VTV_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (soft float ABI debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libsfvtv
+
+ifenabled(`libneonvtv',`
+Package: libvtv`'VTV_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library [neon optimized]
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonvtv
+')`'dnl libvtv
+
+ifenabled(`libcilkrts',`
+Package: libcilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libcilkrts'CILKRTS_SO`-armel [armel], libcilkrts'CILKRTS_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (runtime)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libcilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libcilkrts'CILKRTS_SO`-dbg-armel [armel], libcilkrts'CILKRTS_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+ifenabled(`lib32cilkrts',`
+Package: lib32cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (32bit)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib32cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (32 bit debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl lib32cilkrts
+
+ifenabled(`lib64cilkrts',`
+Package: lib64cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (64bit)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib64cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (64bit debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl lib64cilkrts
+
+ifenabled(`libn32cilkrts',`
+Package: libn32cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (n32)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libn32cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (n32 debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libn32cilkrts
+
+ifenabled(`libx32cilkrts',`
+Package: libx32cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (x32)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libx32cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (x32 debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libx32cilkrts
+
+ifenabled(`libhfcilkrts',`
+Package: libhfcilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libcilkrts'CILKRTS_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (hard float ABI)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libhfcilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libcilkrts'CILKRTS_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (hard float ABI debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libhfcilkrts
+
+ifenabled(`libsfcilkrts',`
+Package: libsfcilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (soft float ABI)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libsfcilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (soft float ABI debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libsfcilkrts
+
+ifenabled(`libneoncilkrts',`
+Package: libcilkrts`'CILKRTS_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions [neon optimized]
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneoncilkrts
+')`'dnl libcilkrts
+
+ifenabled(`libmpx',`
+Package: libmpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libmpx'MPX_SO`-armel [armel], libmpx'MPX_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libmpx0 (<< 6-20160120-1)
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (runtime)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libmpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(mpx`'MPX_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libmpx'MPX_SO`-dbg-armel [armel], libmpx'MPX_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+ifenabled(`lib32mpx',`
+Package: lib32mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32mpx0 (<< 6-20160120-1)
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (32bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib32mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(mpx`'MPX_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (32 bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl lib32mpx
+
+ifenabled(`lib64mpx',`
+Package: lib64mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64mpx0 (<< 6-20160120-1)
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (64bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib64mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(mpx`'MPX_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (64bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl lib64mpx
+
+ifenabled(`libn32mpx',`
+Package: libn32mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (n32)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libn32mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(mpx`'MPX_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (n32 debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libn32mpx
+
+ifenabled(`libx32mpx',`
+Package: libx32mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (x32)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libx32mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(mpx`'MPX_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (x32 debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libx32mpx
+
+ifenabled(`libhfmpx',`
+Package: libhfmpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libmpx'MPX_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (hard float ABI)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libhfmpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(mpx`'MPX_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libmpx'MPX_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (hard float ABI debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libhfmpx
+
+ifenabled(`libsfmpx',`
+Package: libsfmpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (soft float ABI)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libsfmpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(mpx`'MPX_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (soft float ABI debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libsfmpx
+')`'dnl libmpx
+
+ifenabled(`libbacktrace',`
+Package: libbacktrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libbacktrace'BTRACE_SO`-armel [armel], libbacktrace'BTRACE_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libbacktrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libbacktrace'BTRACE_SO`-dbg-armel [armel], libbacktrace'BTRACE_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: stack backtrace library (debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib32backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: stack backtrace library (32bit)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib32backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (32 bit debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib64backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (64bit)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib64backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (64bit debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libn32backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (n32)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libn32backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (n32 debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+ifenabled(`libx32backtrace',`
+Package: libx32backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (x32)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libx32backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (x32 debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+')`'dnl libx32backtrace
+
+ifenabled(`libhfbacktrace',`
+Package: libhfbacktrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libbacktrace'BTRACE_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: stack backtrace library (hard float ABI)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libhfbacktrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,hf,=), ${misc:Depends}
+wifdef(`TARGET',`dnl',`Conflicts: libbacktrace'BTRACE_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: stack backtrace library (hard float ABI debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+')`'dnl libhfbacktrace
+
+ifenabled(`libsfbacktrace',`
+Package: libsfbacktrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (soft float ABI)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libsfbacktrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (soft float ABI debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+')`'dnl libsfbacktrace
+
+ifenabled(`libneonbacktrace',`
+Package: libbacktrace`'BTRACE_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library [neon optimized]
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonbacktrace
+')`'dnl libbacktrace
+
+
+ifenabled(`libqmath',`
+Package: libquadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libquadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,,=), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: lib32quadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (32bit)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: lib32quadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (32 bit debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: lib64quadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library  (64bit)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: lib64quadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library  (64bit debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+#Package: libn32quadmath`'QMATH_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GCC Quad-Precision Math Library (n32)
+# A library, which provides quad-precision mathematical functions on targets
+# supporting the __float128 datatype. The library is used to provide on such
+# targets the REAL(16) type in the GNU Fortran compiler.
+
+#Package: libn32quadmath`'QMATH_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: extra
+#Depends: BASELDEP, libdep(quadmath`'QMATH_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GCC Quad-Precision Math Library (n32 debug symbols)
+# A library, which provides quad-precision mathematical functions on targets
+# supporting the __float128 datatype.
+
+ifenabled(`libx32qmath',`
+Package: libx32quadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (x32)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libx32quadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (x32 debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+')`'dnl libx32qmath
+
+ifenabled(`libhfqmath',`
+Package: libhfquadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (hard float ABI)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libhfquadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,hf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (hard float ABI debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+')`'dnl libhfqmath
+
+ifenabled(`libsfqmath',`
+Package: libsfquadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (soft float ABI)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libsfquadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (hard float ABI debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+')`'dnl libsfqmath
+')`'dnl libqmath
+
+ifenabled(`libcc1',`
+Package: libcc1-`'CC1_SO
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC cc1 plugin for GDB
+ libcc1 is a plugin for GDB.
+')`'dnl libcc1
+
+ifenabled(`libjit',`
+Package: libgccjit`'GCCJIT_SO
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+Breaks: python-gccjit (<< 0.4-4), python3-gccjit (<< 0.4-4)
+BUILT_USING`'dnl
+Description: GCC just-in-time compilation (shared library)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit`'GCCJIT_SO-dbg
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: extra
+Depends: BASEDEP, libgccjit`'GCCJIT_SO (= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Breaks: libgccjit-5-dbg, libgccjit-6-dbg
+Replaces: libgccjit-5-dbg, libgccjit-6-dbg
+BUILT_USING`'dnl
+Description: GCC just-in-time compilation (debug information)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+')`'dnl libjit
+
+ifenabled(`jit',`
+Package: libgccjit`'PV-doc
+Section: doc
+Architecture: all
+Priority: extra
+Depends: BASEDEP, ${misc:Depends}
+Conflicts: libgccjit-5-doc
+Description: GCC just-in-time compilation (documentation)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit`'PV-dev
+Section: ifdef(`TARGET',`devel',`libdevel')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, libgccjit`'GCCJIT_SO (>= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Suggests: libgccjit`'PV-dbg
+Description: GCC just-in-time compilation (development files)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+')`'dnl jit
+
+ifenabled(`objpp',`
+ifenabled(`objppdev',`
+Package: gobjc++`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), g++`'PV`'TS (= ${gcc:Version}), ${shlibs:Depends}, libidevdep(objc`'PV-dev,,=), ${misc:Depends}
+Suggests: ${gobjcxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion})
+Provides: objc++-compiler`'TS
+BUILT_USING`'dnl
+Description: GNU Objective-C++ compiler
+ This is the GNU Objective-C++ compiler, which compiles
+ Objective-C++ on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+')`'dnl obcppdev
+
+ifenabled(`multilib',`
+Package: gobjc++`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gobjc++`'PV`'TS (= ${gcc:Version}), g++`'PV-multilib`'TS (= ${gcc:Version}), gobjc`'PV-multilib`'TS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Objective-C++ compiler (multilib support)
+ This is the GNU Objective-C++ compiler, which compiles Objective-C++ on
+ platforms supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+')`'dnl obcpp
+
+ifenabled(`objc',`
+ifenabled(`objcdev',`
+Package: gobjc`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libidevdep(objc`'PV-dev,,=), ${misc:Depends}
+Suggests: ${gobjc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(objc`'OBJC_SO-dbg,)
+Provides: objc-compiler`'TS
+ifdef(`__sparc__',`Conflicts: gcc`'PV-sparc64', `dnl')
+BUILT_USING`'dnl
+Description: GNU Objective-C compiler
+ This is the GNU Objective-C compiler, which compiles
+ Objective-C on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+ifenabled(`multilib',`
+Package: gobjc`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Objective-C compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU Objective-C compiler, which compiles Objective-C on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+Package: libobjc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,), libdep(objc`'OBJC_SO,), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib64objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,64), libdep(objc`'OBJC_SO,64), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib32objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,32), libdep(objc`'OBJC_SO,32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libn32objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,n32), libdep(objc`'OBJC_SO,n32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+ifenabled(`x32dev',`
+Package: libx32objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,x32), libdep(objc`'OBJC_SO,x32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+')`'dnl libx32objc
+
+ifenabled(`armml',`
+Package: libhfobjc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,hf), libdep(objc`'OBJC_SO,hf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+')`'dnl armml
+
+ifenabled(`armml',`
+Package: libsfobjc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,sf), libdep(objc`'OBJC_SO,sf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (soft float development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+')`'dnl armml
+')`'dnl objcdev
+
+ifenabled(`libobjc',`
+Package: libobjc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libobjc'OBJC_SO`-armel [armel], libobjc'OBJC_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+ifelse(OBJC_SO,`2',`Breaks: ${multiarch:breaks}
+',`')')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libobjc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libobjc'OBJC_SO`-dbg-armel [armel], libobjc'OBJC_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: extra
+Depends: BASELDEP, libdep(objc`'OBJC_SO,,=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libobjc
+
+ifenabled(`lib64objc',`
+Package: lib64objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (64bit)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib64objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: extra
+Depends: BASELDEP, libdep(objc`'OBJC_SO,64,=), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (64 bit debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl lib64objc
+
+ifenabled(`lib32objc',`
+Package: lib32objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (32bit)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib32objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(objc`'OBJC_SO,32,=), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (32 bit debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl lib32objc
+
+ifenabled(`libn32objc',`
+Package: libn32objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (n32)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libn32objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(objc`'OBJC_SO,n32,=), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (n32 debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libn32objc
+
+ifenabled(`libx32objc',`
+Package: libx32objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (x32)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libx32objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(objc`'OBJC_SO,x32,=), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (x32 debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libx32objc
+
+ifenabled(`libhfobjc',`
+Package: libhfobjc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (hard float ABI)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libhfobjc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: extra
+Depends: BASELDEP, libdep(objc`'OBJC_SO,hf,=), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (hard float ABI debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libhfobjc
+
+ifenabled(`libsfobjc',`
+Package: libsfobjc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (soft float ABI)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libsfobjc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: extra
+Depends: BASELDEP, libdep(objc`'OBJC_SO,sf,=), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (soft float ABI debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libsfobjc
+
+ifenabled(`libneonobjc',`
+Package: libobjc`'OBJC_SO-neon`'LS
+Section: libs
+Architecture: NEON_ARCHS
+Priority: PRI(optional)
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications  [NEON version]
+ Library needed for GNU ObjC applications linked against the shared library.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonobjc
+')`'dnl objc
+
+ifenabled(`fortran',`
+ifenabled(`fdev',`
+Package: gfortran`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libidevdep(gfortran`'PV-dev,,=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: fortran95-compiler, ${fortran:mod-version}
+Suggests: ${gfortran:multilib}, gfortran`'PV-doc,
+ libdbgdep(gfortran`'FORTRAN_SO-dbg,),
+ libcoarrays-dev
+BUILT_USING`'dnl
+Description: GNU Fortran compiler
+ This is the GNU Fortran compiler, which compiles
+ Fortran on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+ifenabled(`multilib',`
+Package: gfortran`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gfortran`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Fortran compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU Fortran compiler, which compiles Fortran on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`gfdldoc',`
+Package: gfortran`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU Fortran compiler (gfortran)
+ Documentation for the GNU Fortran compiler in info `format'.
+')`'dnl gfdldoc
+
+Package: libgfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',), libdep(gfortran`'FORTRAN_SO,), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib64gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',64), libdep(gfortran`'FORTRAN_SO,64), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib32gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',32), libdep(gfortran`'FORTRAN_SO,32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libn32gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',n32), libdep(gfortran`'FORTRAN_SO,n32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+ifenabled(`x32dev',`
+Package: libx32gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',x32), libdep(gfortran`'FORTRAN_SO,x32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+')`'dnl libx32gfortran
+
+ifenabled(`armml',`
+Package: libhfgfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',hf), libdep(gfortran`'FORTRAN_SO,hf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+')`'dnl armml
+
+ifenabled(`armml',`
+Package: libsfgfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',sf), libdep(gfortran`'FORTRAN_SO,sf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (soft float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+')`'dnl armml
+')`'dnl fdev
+
+ifenabled(`libgfortran',`
+Package: libgfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgfortran'FORTRAN_SO`-armel [armel], libgfortran'FORTRAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libgfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgfortran'FORTRAN_SO`-dbg-armel [armel], libgfortran'FORTRAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: extra
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,,=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libgfortran
+
+ifenabled(`lib64gfortran',`
+Package: lib64gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (64bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib64gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: extra
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (64bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl lib64gfortran
+
+ifenabled(`lib32gfortran',`
+Package: lib32gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (32bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib32gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (32 bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl lib32gfortran
+
+ifenabled(`libn32gfortran',`
+Package: libn32gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (n32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libn32gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (n32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libn32gfortran
+
+ifenabled(`libx32gfortran',`
+Package: libx32gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (x32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libx32gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (x32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libx32gfortran
+
+ifenabled(`libhfgfortran',`
+Package: libhfgfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libhfgfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: extra
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libhfgfortran
+
+ifenabled(`libsfgfortran',`
+Package: libsfgfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (soft float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libsfgfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: extra
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,sf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libsfgfortran
+
+ifenabled(`libneongfortran',`
+Package: libgfortran`'FORTRAN_SO-neon`'LS
+Section: libs
+Architecture: NEON_ARCHS
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Priority: extra
+Depends: BASELDEP, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications [NEON version]
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneongfortran
+')`'dnl fortran
+
+ifenabled(`ggo',`
+ifenabled(`godev',`
+Package: gccgo`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ifdef(`STANDALONEGO',`${dep:libcc1}, ',`gcc`'PV`'TS (= ${gcc:Version}), ')libidevdep(go`'GO_SO,,>=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: go-compiler
+Suggests: ${go:multilib}, gccgo`'PV-doc, libdbgdep(go`'GO_SO-dbg,)
+Conflicts: ${golang:Conflicts}
+BUILT_USING`'dnl
+Description: GNU Go compiler
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler. It uses the gcc backend to generate optimized code.
+
+ifenabled(`multilib',`
+Package: gccgo`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gccgo`'PV`'TS (= ${gcc:Version}), ifdef(`STANDALONEGO',,`gcc`'PV-multilib`'TS (= ${gcc:Version}), ')${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libgobiarchdbg}
+BUILT_USING`'dnl
+Description: GNU Go compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`gfdldoc',`
+Package: gccgo`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Documentation for the GNU Go compiler (gccgo)
+ Documentation for the GNU Go compiler in info `format'.
+')`'dnl gfdldoc
+')`'dnl fdev
+
+ifenabled(`libggo',`
+Package: libgo`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgo'GO_SO`-armel [armel], libgo'GO_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libgo3`'LS, libgo8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libgo`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgo'GO_SO`-dbg-armel [armel], libgo'GO_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: extra
+Depends: BASELDEP, libdep(go`'GO_SO,,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl libgo
+
+ifenabled(`lib64ggo',`
+Package: lib64go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64go3`'LS, lib64go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (64bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib64go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: extra
+Depends: BASELDEP, libdep(go`'GO_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (64bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl lib64go
+
+ifenabled(`lib32ggo',`
+Package: lib32go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32go3`'LS, lib32go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (32bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib32go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(go`'GO_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (32 bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl lib32go
+
+ifenabled(`libn32ggo',`
+Package: libn32go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libn32go3`'LS, libn32go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (n32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libn32go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(go`'GO_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (n32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl libn32go
+
+ifenabled(`libx32ggo',`
+Package: libx32go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32go3`'LS, libx32go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (x32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libx32go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: extra
+Depends: BASELDEP, libdep(go`'GO_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (x32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl libx32go
+')`'dnl ggo
+
+ifenabled(`java',`
+ifenabled(`gcj',`
+Package: gcj`'PV`'TS
+Section: java
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ${dep:gcj}, ${dep:gcjcross}, ${dep:libcdev}, ${dep:ecj}, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Replaces: gcj-5-jdk (<< 5.2.1-19)
+Suggests: gcj`'PV-jdk
+BUILT_USING`'dnl
+Description: GCJ byte code and native compiler for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files.
+ .
+ifdef(`TARGET',`'dnl
+,` Install the gcj`'PV`'TS-jdk package for a more complete SDK environment.
+')`'dnl
+')`'dnl gcj
+
+ifenabled(`libgcj',`
+ifenabled(`libgcjcommon',`
+Package: libgcj-common
+Section: java
+Architecture: all
+Priority: PRI(optional)
+Depends: BASEDEP, ${misc:Depends}
+Conflicts: classpath (<= 0.04-4)
+Replaces: java-gcj-compat (<< 1.0.65-3), java-gcj-compat-dev (<< 1.0.65-3)
+BUILT_USING`'dnl
+Description: Java runtime library (common files)
+ This package contains files shared by Classpath and libgcj libraries.
+')`'dnl libgcjcommon
+
+
+Package: gcj`'PV-jdk`'TS
+Section: java
+Architecture: any
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ${dep:gcj}, ${dep:libcdev}, gcj`'PV`'TS (= ${gcj:Version}), gcj`'PV-jre`'TS (= ${gcj:Version}), libidevdep(gcj`'GCJ_SO-dev,,>=,${gcj:Version}), fastjar, libgcj-bc`'LS, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Suggests: gcj`'PV-source (>= ${gcj:SoftVersion}), libdbgdep(gcj`'GCJ_SO-dbg,)
+Provides: java-compiler, java-sdk, java2-sdk, java5-sdk
+Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1)
+Replaces: libgcj11 (<< 4.5-20100101-1)
+BUILT_USING`'dnl
+Description: GCJ and Classpath development tools for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files. Other java development tools from classpath are included in this
+ package.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-SDK-like interface to the GCJ tool set.
+
+Package: gcj`'PV-jre-headless`'TS
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Section: java
+Architecture: any
+Depends: BASEDEP, gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}), libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: fastjar, gcj`'PV-jdk`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,>=,${gcj:Version})
+Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless
+BUILT_USING`'dnl
+Description: Java runtime environment using GIJ/Classpath (headless version)
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set,
+ limited to the headless tools and libraries.
+
+Package: gcj`'PV-jre`'TS
+Section: java
+Architecture: any
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, gcj`'PV-jre-headless`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,>=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime
+BUILT_USING`'dnl
+Description: Java runtime environment using GIJ/Classpath
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set.
+
+Package: libgcj`'LIBGCJ_EXT`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends}
+Recommends: gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion})
+Suggests: libdbgdep(gcj`'GCJ_SO-dbg,), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version})
+BUILT_USING`'dnl
+Description: Java runtime library for use with gcj
+ This is the runtime that goes along with the gcj front end to
+ gcc. libgcj includes parts of the Java Class Libraries, plus glue to
+ connect the libraries to the compiler and the underlying OS.
+ .
+ To show file names and line numbers in stack traces, the packages
+ libgcj`'GCJ_SO-dbg and binutils are required.
+
+Package: gcj`'PV-jre-lib`'TS
+Section: java
+Architecture: all
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:SoftVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Java runtime library for use with gcj (jar files)
+ This is the jar file that goes along with the gcj front end to gcc.
+
+ifenabled(`gcjbc',`
+Package: libgcj-bc
+Section: java
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Link time only library for use with gcj
+ A fake library that is used at link time only.  It ensures that
+ binaries built with the BC-ABI link against a constant SONAME.
+ This way, BC-ABI binaries continue to work if the SONAME underlying
+ libgcj.so changes.
+')`'dnl gcjbc
+
+Package: libgcj`'LIBGCJ_EXT-awt`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${pkg:gcjqt}
+BUILT_USING`'dnl
+Description: AWT peer runtime libraries for use with gcj
+ These are runtime libraries holding the AWT peer implementations
+ for libgcj (currently the GTK+ based peer library is required, the
+ QT bases library is not built).
+
+ifenabled(`gtkpeer',`
+Package: libgcj`'GCJ_SO-awt-gtk`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libgcj`'LIBGCJ_EXT-awt`'LS (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AWT GTK+ peer runtime library for use with libgcj
+ This is the runtime library holding the GTK+ based AWT peer
+ implementation for libgcj.
+')`'dnl gtkpeer
+
+ifenabled(`qtpeer',`
+Package: libgcj`'GCJ_SO-awt-qt`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AWT QT peer runtime library for use with libgcj
+ This is the runtime library holding the QT based AWT peer
+ implementation for libgcj.
+')`'dnl qtpeer
+')`'dnl libgcj
+
+ifenabled(`libgcjdev',`
+Package: libgcj`'GCJ_SO-dev`'LS
+Section: libdevel
+Architecture: any
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: PRI(optional)
+Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), libgcj-bc`'LS, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Suggests: libgcj-doc
+BUILT_USING`'dnl
+Description: Java development headers for use with gcj
+ These are the development headers that go along with the gcj front end
+ to gcc. libgcj includes parts of the Java Class Libraries, plus glue
+ to connect the libraries to the compiler and the underlying OS.
+
+Package: libgcj`'GCJ_SO-dbg`'LS
+Section: debug
+Architecture: any
+Priority: extra
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${misc:Depends}
+Recommends: binutils, libc6-dbg | libc-dbg
+BUILT_USING`'dnl
+Description: Debugging symbols for libraries provided in libgcj`'GCJ_SO-dev
+ The package provides debugging symbols for the libraries provided
+ in libgcj`'GCJ_SO-dev.
+ .
+ binutils is required to show file names and line numbers in stack traces.
+
+ifenabled(`gcjsrc',`
+Package: gcj`'PV-source
+Section: java
+Architecture: all
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, gcj`'PV-jdk (>= ${gcj:SoftVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCJ java sources for use in IDEs like eclipse and netbeans
+ These are the java source files packaged as a zip file for use in development
+ environments like eclipse and netbeans.
+')`'dnl
+
+ifenabled(`gcjdoc',`
+Package: libgcj-doc
+Section: doc
+Architecture: all
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, ${misc:Depends}
+Enhances: libgcj`'GCJ_SO-dev
+Provides: classpath-doc
+BUILT_USING`'dnl
+Description: libgcj API documentation and example programs
+ Autogenerated documentation describing the API of the libgcj library.
+ Sources and precompiled example programs from the Classpath library.
+')`'dnl gcjdoc
+')`'dnl libgcjdev
+')`'dnl java
+
+ifenabled(`c++',`
+ifenabled(`libcxx',`
+Package: libstdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(important))
+Depends: BASELDEP, ${dep:libc}, ${shlibs:Depends}, ${misc:Depends}
+Provides: ifdef(`TARGET',`libstdc++CXX_SO-TARGET-dcv1',`libstdc++'CXX_SO`-armel [armel], libstdc++'CXX_SO`-armhf [armhf]')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}, PR66145BREAKS
+')`'dnl
+Conflicts: scim (<< 1.4.2-1)
+Replaces: libstdc++CXX_SO`'PV-dbg`'LS (<< 4.9.0-3)
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libcxx
+
+ifenabled(`lib32cxx',`
+Package: lib32stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdep(gcc1,32), ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (32 bit Version)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib32cxx
+
+ifenabled(`lib64cxx',`
+Package: lib64stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdep(gcc1,64), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (64bit)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib64cxx
+
+ifenabled(`libn32cxx',`
+Package: libn32stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdep(gcc1,n32), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (n32)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libn32cxx
+
+ifenabled(`libx32cxx',`
+Package: libx32stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdep(gcc1,x32), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (x32)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libx32cxx
+
+ifenabled(`libhfcxx',`
+Package: libhfstdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdep(gcc1,hf), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libhfcxx
+
+ifenabled(`libsfcxx',`
+Package: libsfstdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdep(gcc1,sf), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libsfcxx
+
+ifenabled(`libneoncxx',`
+Package: libstdc++CXX_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: extra
+Depends: BASELDEP, libc6-neon`'LS, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 [NEON version]
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl
+
+ifenabled(`c++dev',`
+Package: libstdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,,=),
+ libdep(stdc++CXX_SO,,>=), ${dep:libcdev}, ${misc:Depends}
+ifdef(`TARGET',`',`dnl native
+Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev,
+ libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev,
+ libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev
+Suggests: libstdc++`'PV-doc
+')`'dnl native
+Provides: libstdc++-dev`'LS`'ifdef(`TARGET',`, libstdc++-dev-TARGET-dcv1')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libstdc++`'PV-pic`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,),
+ libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+ifdef(`TARGET',`Provides: libstdc++-pic-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (shared library subset kit)`'ifdef(`TARGET)',` (TARGET)', `')
+ This is used to develop subsets of the libstdc++ shared libraries for
+ use on custom installation floppies and in embedded systems.
+ .
+ Unless you are making one of those, you will not need this package.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libstdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,),
+ libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: ifdef(`TARGET',`libstdc++CXX_SO-dbg-TARGET-dcv1',`libstdc++'CXX_SO`'PV`-dbg-armel [armel], libstdc++'CXX_SO`'PV`-dbg-armhf [armhf]')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Recommends: libdevdep(stdc++`'PV-dev,)
+Conflicts: libstdc++5-dbg`'LS, libstdc++5-3.3-dbg`'LS, libstdc++6-dbg`'LS,
+ libstdc++6-4.0-dbg`'LS, libstdc++6-4.1-dbg`'LS, libstdc++6-4.2-dbg`'LS,
+ libstdc++6-4.3-dbg`'LS, libstdc++6-4.4-dbg`'LS, libstdc++6-4.5-dbg`'LS,
+ libstdc++6-4.6-dbg`'LS, libstdc++6-4.7-dbg`'LS, libstdc++6-4.8-dbg`'LS,
+ libstdc++6-4.9-dbg`'LS, libstdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib32stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,32),
+ libdep(stdc++CXX_SO,32), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib32stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,32),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: lib32stdc++6-dbg`'LS, lib32stdc++6-4.0-dbg`'LS,
+ lib32stdc++6-4.1-dbg`'LS, lib32stdc++6-4.2-dbg`'LS, lib32stdc++6-4.3-dbg`'LS,
+ lib32stdc++6-4.4-dbg`'LS, lib32stdc++6-4.5-dbg`'LS, lib32stdc++6-4.6-dbg`'LS,
+ lib32stdc++6-4.7-dbg`'LS, lib32stdc++6-4.8-dbg`'LS, lib32stdc++6-4.9-dbg`'LS,
+ lib32stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib64stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,64),
+ libdep(stdc++CXX_SO,64), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib64stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,64),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: lib64stdc++6-dbg`'LS, lib64stdc++6-4.0-dbg`'LS,
+ lib64stdc++6-4.1-dbg`'LS, lib64stdc++6-4.2-dbg`'LS, lib64stdc++6-4.3-dbg`'LS,
+ lib64stdc++6-4.4-dbg`'LS, lib64stdc++6-4.5-dbg`'LS, lib64stdc++6-4.6-dbg`'LS,
+ lib64stdc++6-4.7-dbg`'LS, lib64stdc++6-4.8-dbg`'LS, lib64stdc++6-4.9-dbg`'LS,
+ lib64stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libn32stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,n32),
+ libdep(stdc++CXX_SO,n32), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libn32stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,n32),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: libn32stdc++6-dbg`'LS, libn32stdc++6-4.0-dbg`'LS,
+ libn32stdc++6-4.1-dbg`'LS, libn32stdc++6-4.2-dbg`'LS, libn32stdc++6-4.3-dbg`'LS,
+ libn32stdc++6-4.4-dbg`'LS, libn32stdc++6-4.5-dbg`'LS, libn32stdc++6-4.6-dbg`'LS,
+ libn32stdc++6-4.7-dbg`'LS, libn32stdc++6-4.8-dbg`'LS, libn32stdc++6-4.9-dbg`'LS,
+ libn32stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+ifenabled(`x32dev',`
+Package: libx32stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,x32), libdep(stdc++CXX_SO,x32),
+ libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl x32dev
+
+ifenabled(`libx32dbgcxx',`
+Package: libx32stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,x32),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: libx32stdc++6-dbg`'LS, libx32stdc++6-4.6-dbg`'LS,
+ libx32stdc++6-4.7-dbg`'LS, libx32stdc++6-4.8-dbg`'LS, libx32stdc++6-4.9-dbg`'LS,
+ libx32stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libx32dbgcxx
+
+ifenabled(`libhfdbgcxx',`
+Package: libhfstdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,hf),
+ libdep(stdc++CXX_SO,hf), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libhfstdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,hf),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libhfstdc++6-dbg`'LS, libhfstdc++6-4.3-dbg`'LS, libhfstdc++6-4.4-dbg`'LS, libhfstdc++6-4.5-dbg`'LS, libhfstdc++6-4.6-dbg`'LS, libhfstdc++6-4.7-dbg`'LS, libhfstdc++6-4.8-dbg`'LS, libhfstdc++6-4.9-dbg`'LS, libhfstdc++6-5-dbg`'LS, libstdc++'CXX_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libhfdbgcxx
+
+ifenabled(`libsfdbgcxx',`
+Package: libsfstdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,sf),
+ libdep(stdc++CXX_SO,sf), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libsfstdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: extra
+Depends: BASELDEP, libdep(stdc++CXX_SO,sf),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libsfstdc++6-dbg`'LS, libsfstdc++6-4.3-dbg`'LS, libsfstdc++6-4.4-dbg`'LS, libsfstdc++6-4.5-dbg`'LS, libsfstdc++6-4.6-dbg`'LS, libsfstdc++6-4.7-dbg`'LS, libsfstdc++6-4.8-dbg`'LS, libsfstdc++6-4.9-dbg`'LS, libsfstdc++6-5-dbg`'LS, libstdc++'CXX_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libsfdbgcxx
+
+ifdef(`TARGET', `', `
+Package: libstdc++`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Conflicts: libstdc++5-doc, libstdc++5-3.3-doc, libstdc++6-doc,
+ libstdc++6-4.0-doc, libstdc++6-4.1-doc, libstdc++6-4.2-doc, libstdc++6-4.3-doc,
+ libstdc++6-4.4-doc, libstdc++6-4.5-doc, libstdc++6-4.6-doc, libstdc++6-4.7-doc,
+ libstdc++-4.8-doc, libstdc++-4.9-doc, libstdc++-5-doc
+Description: GNU Standard C++ Library v3 (documentation files)
+ This package contains documentation files for the GNU stdc++ library.
+ .
+ One set is the distribution documentation, the other set is the
+ source documentation including a namespace list, class hierarchy,
+ alphabetical list, compound list, file list, namespace members,
+ compound members and file members.
+')`'dnl native
+')`'dnl c++dev
+')`'dnl c++
+
+ifenabled(`ada',`
+Package: gnat`'-GNAT_V`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Depends: BASEDEP, gcc`'PV`'TS (>= ${gcc:SoftVersion}), ${dep:libgnat}, ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: gnat`'PV-doc, ada-reference-manual-2012, gnat`'-GNAT_V-sjlj
+Breaks:   gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+Replaces: gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+# Takes over symlink from gnat (<< 4.6.1): /usr/bin/gnatgcc.
+# Takes over file from dh-ada-library (<< 6.0): debian_packaging.mk.
+# g-base 4.6.4-2, 4.9-20140330-1 contain debian_packaging.mk by mistake.
+# Newer versions of gnat and dh-ada-library will not provide these files.
+Conflicts: gnat (<< 4.1), gnat-3.1, gnat-3.2, gnat-3.3, gnat-3.4, gnat-3.5,
+ gnat-4.0, gnat-4.1, gnat-4.2, gnat-4.3, gnat-4.4, gnat-4.6, gnat-4.7, gnat-4.8,
+ gnat-4.9, gnat-5`'TS
+# These other packages will continue to provide /usr/bin/gnatmake and
+# other files.
+BUILT_USING`'dnl
+Description: GNU Ada compiler
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides the compiler, tools and runtime library that handles
+ exceptions using the default zero-cost mechanism.
+
+ifenabled(`adasjlj',`
+Package: gnat`'-GNAT_V-sjlj`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: extra
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Depends: BASEDEP, gnat`'-GNAT_V`'TS (= ${gnat:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Ada compiler (setjump/longjump runtime library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides an alternative runtime library that handles
+ exceptions using the setjump/longjump mechanism (as a static library
+ only).  You can install it to supplement the normal compiler.
+')`'dnl adasjlj
+
+ifenabled(`libgnat',`
+Package: libgnat`'-GNAT_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: runtime for applications compiled with GNAT (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnat`'-GNAT_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: extra
+Depends: BASELDEP, libgnat`'-GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: runtime for applications compiled with GNAT (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatvsn`'GNAT_V-dev`'LS
+Section: libdevel
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Priority: extra
+Depends: BASELDEP, ifdef(`TARGET',`',`gnat`'PV`'TS (ifdef(`TARGET',`>= ${gnat:SoftVersion}',`= ${gnat:Version}')),')
+ libgnatvsn`'GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+ifdef(`TARGET',`Recommends: gnat`'PV`'TS (>= ${gnat:SoftVersion})
+')`'dnl
+Conflicts: libgnatvsn-dev (<< `'GNAT_V),
+ libgnatvsn4.1-dev, libgnatvsn4.3-dev, libgnatvsn4.4-dev,
+ libgnatvsn4.5-dev, libgnatvsn4.6-dev, libgnatvsn4.9-dev,
+ libgnatvsn5-dev`'LS,
+BUILT_USING`'dnl
+Description: GNU Ada compiler selected components (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatvsn`'GNAT_V`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Section: ifdef(`TARGET',`devel',`libs')
+Depends: BASELDEP, libgnat`'-GNAT_V`'LS (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Ada compiler selected components (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatvsn`'GNAT_V-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: extra
+Section: debug
+Depends: BASELDEP, libgnatvsn`'GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+BUILT_USING`'dnl
+Description: GNU Ada compiler selected components (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatprj`'GNAT_V-dev`'LS
+Section: libdevel
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Priority: extra
+Depends: BASELDEP, ifdef(`TARGET',`',`gnat`'PV`'TS (ifdef(`TARGET',`>= ${gnat:SoftVersion}',`= ${gnat:Version}')),')
+ libgnatprj`'GNAT_V`'LS (= ${gnat:Version}),
+ libgnatvsn`'GNAT_V-dev`'LS (= ${gnat:Version}), ${misc:Depends}
+ifdef(`TARGET',`Recommends: gnat`'PV`'TS (>= ${gnat:SoftVersion})
+')`'dnl
+Conflicts: libgnatprj-dev (<< `'GNAT_V),
+ libgnatprj4.1-dev, libgnatprj4.3-dev, libgnatprj4.4-dev,
+ libgnatprj4.5-dev, libgnatprj4.6-dev, libgnatprj4.9-dev,
+ libgnatprj5-dev`'LS,
+BUILT_USING`'dnl
+Description: GNU Ada compiler Project Manager (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatprj`'GNAT_V`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Section: ifdef(`TARGET',`devel',`libs')
+Depends: BASELDEP, libgnat`'-GNAT_V`'LS (= ${gnat:Version}),
+ libgnatvsn`'GNAT_V`'LS (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Ada compiler Project Manager (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatprj`'GNAT_V-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: extra
+Section: debug
+Depends: BASELDEP, libgnatprj`'GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+BUILT_USING`'dnl
+Description: GNU Ada compiler Project Manager (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the debugging symbols.
+')`'dnl libgnat
+
+ifenabled(`lib64gnat',`
+Package: lib64gnat`'-GNAT_V
+Section: libs
+Architecture: biarch64_archs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: runtime for applications compiled with GNAT (64 bits shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the runtime shared library for 64 bits architectures.
+')`'dnl libgnat
+
+ifenabled(`gfdldoc',`
+Package: gnat`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Suggests: gnat`'PV
+Conflicts: gnat-4.1-doc, gnat-4.2-doc,
+  gnat-4.3-doc, gnat-4.4-doc,
+  gnat-4.6-doc, gnat-4.9-doc,
+  gnat-5-doc,
+BUILT_USING`'dnl
+Description: GNU Ada compiler (documentation)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the documentation in info `format'.
+')`'dnl gfdldoc
+')`'dnl ada
+
+ifenabled(`d ',`
+Package: gdc`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: SOFTBASEDEP, g++`'PV`'TS (>= ${gcc:SoftVersion}), ${dep:gdccross}, ${dep:phobosdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: gdc, d-compiler, d-v2-compiler
+Replaces: gdc (<< 4.4.6-5)
+BUILT_USING`'dnl
+Description: GNU D compiler (version 2)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This compiler supports D language version 2.
+
+ifenabled(`multilib',`
+Package: gdc`'PV-multilib`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: SOFTBASEDEP, gdc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libphobosbiarchdev}${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU D compiler (version 2, multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`libphobos',`
+Package: libgphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`libphobos_archs')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libgphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`libphobos_archs')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`libphobos_archs')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: extra
+Depends: BASELDEP, libgphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, lib64gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,64), lib64z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64phobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (64bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: extra
+Depends: BASELDEP, lib64gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, lib32gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,32), lib32z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib32phobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (32bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: extra
+Depends: BASELDEP, lib32gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+ifenabled(`libn32phobos',`
+Package: libn32gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libn32gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,n32), libn32z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libn32phobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (n32 development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libn32gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libn32gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: extra
+Depends: BASELDEP, libn32gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+')`'dnl libn32phobos
+
+ifenabled(`libx32phobos',`
+Package: libx32gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libx32gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,x32), ${dep:libx32z}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32gphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (x32 development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: extra
+Depends: BASELDEP, libx32gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+')`'dnl libx32phobos
+
+ifenabled(`armml',`
+Package: libhfgphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libhfgphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,hf), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libhfphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (hard float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: extra
+Depends: BASELDEP, libhfgphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, libsfgphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,sf), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libsfphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (soft float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: ifdef(`TARGET',`extra',PRI(optional))
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: extra
+Depends: BASELDEP, libsfgphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+')`'dnl armml
+')`'dnl libphobos
+')`'dnl d
+
+ifdef(`TARGET',`',`dnl
+ifenabled(`libs',`
+#Package: gcc`'PV-soft-float
+#Architecture: arm armel armhf
+#Priority: PRI(optional)
+#Depends: BASEDEP, depifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends}
+#Conflicts: gcc-4.4-soft-float, gcc-4.5-soft-float, gcc-4.6-soft-float
+#BUILT_USING`'dnl
+#Description: GCC soft-floating-point gcc libraries (ARM)
+# These are versions of basic static libraries such as libgcc.a compiled
+# with the -msoft-float option, for CPUs without a floating-point unit.
+')`'dnl commonlibs
+')`'dnl
+
+ifenabled(`fixincl',`
+Package: fixincludes
+Architecture: any
+Priority: PRI(optional)
+Depends: BASEDEP, gcc`'PV (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Fix non-ANSI header files
+ FixIncludes was created to fix non-ANSI system header files. Many
+ system manufacturers supply proprietary headers that are not ANSI compliant.
+ The GNU compilers cannot compile non-ANSI headers. Consequently, the
+ FixIncludes shell script was written to fix the header files.
+ .
+ Not all packages with header files are installed on the system, when the
+ package is built, so we make fixincludes available at build time of other
+ packages, such that checking tools like lintian can make use of it.
+')`'dnl fixincl
+
+ifenabled(`cdev',`
+ifdef(`TARGET', `', `
+ifenabled(`gfdldoc',`
+Package: gcc`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Conflicts: gcc-docs (<< 2.95.2)
+Replaces: gcc (<=2.7.2.3-4.3), gcc-docs (<< 2.95.2)
+Description: Documentation for the GNU compilers (gcc, gobjc, g++)
+ Documentation for the GNU compilers in info `format'.
+')`'dnl gfdldoc
+')`'dnl native
+')`'dnl cdev
+
+ifdef(`TARGET',`',`dnl
+ifenabled(`libnof',`
+#Package: gcc`'PV-nof
+#Architecture: powerpc
+#Priority: PRI(optional)
+#Depends: BASEDEP, ${shlibs:Depends}ifenabled(`cdev',`, gcc`'PV (= ${gcc:Version})'), ${misc:Depends}
+#Conflicts: gcc-3.2-nof
+#BUILT_USING`'dnl
+#Description: GCC no-floating-point gcc libraries (powerpc)
+# These are versions of basic static libraries such as libgcc.a compiled
+# with the -msoft-float option, for CPUs without a floating-point unit.
+')`'dnl libnof
+')`'dnl
+
+ifenabled(`source',`
+Package: gcc`'PV-source
+Architecture: all
+Priority: PRI(optional)
+Depends: make, autoconf2.64, quilt, patchutils, sharutils, gawk, ${misc:Depends}
+Description: Source of the GNU Compiler Collection
+ This package contains the sources and patches which are needed to
+ build the GNU Compiler Collection (GCC).
+')`'dnl source
+dnl
+')`'dnl gcc-X.Y
+dnl last line in file
--- gcc-6-6.3.0.orig/debian/copyright
+++ gcc-6-6.3.0/debian/copyright
@@ -0,0 +1,692 @@
+This is the Debian GNU/Linux prepackaged version of the GNU compiler
+collection, containing Ada, C, C++, Fortran 95, Java, Objective-C,
+Objective-C++, and Treelang compilers, documentation, and support
+libraries.  In addition, Debian provides the gdc compiler, either in
+the same source package, or built from a separate same source package.
+Packaging is done by the Debian GCC Maintainers
+<debian-gcc@lists.debian.org>, with sources obtained from:
+
+  ftp://gcc.gnu.org/pub/gcc/releases/  (for full releases)
+  svn://gcc.gnu.org/svn/gcc/           (for prereleases)
+  http://bitbucket.org/goshawk/gdc     (for D)
+
+The current gcc-6 source package is taken from the SVN gcc-6-branch.
+
+Changes: See changelog.Debian.gz
+
+Debian splits the GNU Compiler Collection into packages for each language,
+library, and documentation as follows:
+
+Language       Compiler package  Library package    Documentation
+---------------------------------------------------------------------------
+Ada            gnat-6          libgnat-6        gnat-6-doc
+C              gcc-6                              gcc-6-doc
+C++            g++-6           libstdc++6         libstdc++6-6-doc
+D              gdc-6
+Fortran 95     gfortran-6      libgfortran3       gfortran-6-doc
+Go             gccgo-6         libgo0
+Java           gcj-6           libgcj10           libgcj-doc
+Objective C    gobjc-6         libobjc2
+Objective C++  gobjc++-6
+
+For some language run-time libraries, Debian provides source files,
+development files, debugging symbols and libraries containing position-
+independent code in separate packages:
+
+Language  Sources      Development   Debugging            Position-Independent
+------------------------------------------------------------------------------
+C++                                  libstdc++6-6-dbg  libstdc++6-6-pic
+D         libphobos-6-dev
+Java      libgcj10-src libgcj10-dev  libgcj10-dbg
+
+Additional packages include:
+
+All languages:
+libgcc1, libgcc2, libgcc4       GCC intrinsics (platform-dependent)
+gcc-6-base                    Base files common to all compilers
+gcc-6-soft-float              Software floating point (ARM only)
+gcc-6-source                  The sources with patches
+
+Ada:
+libgnatvsn-dev, libgnatvsn6   GNAT version library
+libgnatprj-dev, libgnatprj6   GNAT Project Manager library
+
+C:
+cpp-6, cpp-6-doc            GNU C Preprocessor
+libssp0-dev, libssp0            GCC stack smashing protection library
+libquadmath0                    Math routines for the __float128 type
+fixincludes                     Fix non-ANSI header files
+
+Java:
+gij                             The Java bytecode interpreter and VM
+libgcj-common                   Common files for the Java run-time
+libgcj10-awt                    The Abstract Windowing Toolkit
+libgcj10-jar                    Java ARchive for the Java run-time
+
+C, C++ and Fortran 95:
+libgomp1-dev, libgomp1		GCC OpenMP (GOMP) support library
+libitm1-dev, libitm1		GNU Transactional Memory Library
+
+Biarch support: On some 64-bit platforms which can also run 32-bit code,
+Debian provides additional packages containing 32-bit versions of some
+libraries.  These packages have names beginning with 'lib32' instead of
+'lib', for example lib32stdc++6.  Similarly, on some 32-bit platforms which
+can also run 64-bit code, Debian provides additional packages with names
+beginning with 'lib64' instead of 'lib'.  These packages contain 64-bit
+versions of the libraries.  (At this time, not all platforms and not all
+libraries support biarch.)  The license terms for these lib32 or lib64
+packages are identical to the ones for the lib packages.
+
+
+COPYRIGHT STATEMENTS AND LICENSING TERMS
+
+
+GCC is Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994,
+1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
+2008, 2009, 2010, 2011, 2012, 2013, 2014 Free Software Foundation, Inc.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Files that have exception clauses are licensed under the terms of the
+GNU General Public License; either version 3, or (at your option) any
+later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 3 of this
+license in `/usr/share/common-licenses/GPL-3'.
+
+The following runtime libraries are licensed under the terms of the
+GNU General Public License (v3 or later) with version 3.1 of the GCC
+Runtime Library Exception (included in this file):
+
+ - libgcc (libgcc/, gcc/libgcc2.[ch], gcc/unwind*, gcc/gthr*,
+   gcc/coretypes.h, gcc/crtstuff.c, gcc/defaults.h, gcc/dwarf2.h,
+   gcc/emults.c, gcc/gbl-ctors.h, gcc/gcov-io.h, gcc/libgcov.c,
+   gcc/tsystem.h, gcc/typeclass.h).
+ - libatomic
+ - libdecnumber
+ - libgomp
+ - libitm
+ - libssp
+ - libstdc++-v3
+ - libobjc
+ - libgfortran
+ - The libgnat-6 Ada support library and libgnatvsn library.
+ - Various config files in gcc/config/ used in runtime libraries.
+ - libvtv
+
+In contrast, libgnatprj is licensed under the terms of the pure GNU
+General Public License.
+
+The libbacktrace library is licensed under the following terms:
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+    (1) Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer. 
+
+    (2) Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in
+    the documentation and/or other materials provided with the
+    distribution.  
+    
+    (3) The name of the author may not be used to
+    endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+
+The libsanitizer libraries (libasan, liblsan, libtsan, libubsan) are
+licensed under the following terms:
+
+Copyright (c) 2009-2014 by the LLVM contributors.
+
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+
+The libgcj library is licensed under the terms of the GNU General
+Public License, with a special exception:
+
+    Linking this library statically or dynamically with other modules
+    is making a combined work based on this library.  Thus, the terms
+    and conditions of the GNU General Public License cover the whole
+    combination.
+
+    As a special exception, the copyright holders of this library give
+    you permission to link this library with independent modules to
+    produce an executable, regardless of the license terms of these
+    independent modules, and to copy and distribute the resulting
+    executable under terms of your choice, provided that you also
+    meet, for each linked independent module, the terms and conditions
+    of the license of that module.  An independent module is a module
+    which is not derived from or based on this library.  If you modify
+    this library, you may extend this exception to your version of the
+    library, but you are not obligated to do so.  If you do not wish
+    to do so, delete this exception statement from your version.
+
+The libffi library is licensed under the following terms:
+
+    libffi - Copyright (c) 1996-2003  Red Hat, Inc.
+
+    Permission is hereby granted, free of charge, to any person obtaining
+    a copy of this software and associated documentation files (the
+    ``Software''), to deal in the Software without restriction, including
+    without limitation the rights to use, copy, modify, merge, publish,
+    distribute, sublicense, and/or sell copies of the Software, and to
+    permit persons to whom the Software is furnished to do so, subject to
+    the following conditions:
+
+    The above copyright notice and this permission notice shall be included
+    in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
+    OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+    IN NO EVENT SHALL CYGNUS SOLUTIONS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+    OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+    ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+    OTHER DEALINGS IN THE SOFTWARE.
+
+
+The documentation is licensed under the GNU Free Documentation License (v1.2).
+On Debian GNU/Linux systems, the complete text of this license is in
+`/usr/share/common-licenses/GFDL-1.2'.
+
+
+GCC RUNTIME LIBRARY EXCEPTION
+
+Version 3.1, 31 March 2009
+
+Copyright (C) 2009 Free Software Foundation, Inc. <http://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this
+license document, but changing it is not allowed.
+
+This GCC Runtime Library Exception ("Exception") is an additional
+permission under section 7 of the GNU General Public License, version
+3 ("GPLv3"). It applies to a given file (the "Runtime Library") that
+bears a notice placed by the copyright holder of the file stating that
+the file is governed by GPLv3 along with this Exception.
+
+When you use GCC to compile a program, GCC may combine portions of
+certain GCC header files and runtime libraries with the compiled
+program. The purpose of this Exception is to allow compilation of
+non-GPL (including proprietary) programs to use, in this way, the
+header files and runtime libraries covered by this Exception.
+
+0. Definitions.
+
+A file is an "Independent Module" if it either requires the Runtime
+Library for execution after a Compilation Process, or makes use of an
+interface provided by the Runtime Library, but is not otherwise based
+on the Runtime Library.
+
+"GCC" means a version of the GNU Compiler Collection, with or without
+modifications, governed by version 3 (or a specified later version) of
+the GNU General Public License (GPL) with the option of using any
+subsequent versions published by the FSF.
+
+"GPL-compatible Software" is software whose conditions of propagation,
+modification and use would permit combination with GCC in accord with
+the license of GCC.
+
+"Target Code" refers to output from any compiler for a real or virtual
+target processor architecture, in executable form or suitable for
+input to an assembler, loader, linker and/or execution
+phase. Notwithstanding that, Target Code does not include data in any
+format that is used as a compiler intermediate representation, or used
+for producing a compiler intermediate representation.
+
+The "Compilation Process" transforms code entirely represented in
+non-intermediate languages designed for human-written code, and/or in
+Java Virtual Machine byte code, into Target Code. Thus, for example,
+use of source code generators and preprocessors need not be considered
+part of the Compilation Process, since the Compilation Process can be
+understood as starting with the output of the generators or
+preprocessors.
+
+A Compilation Process is "Eligible" if it is done using GCC, alone or
+with other GPL-compatible software, or if it is done without using any
+work based on GCC. For example, using non-GPL-compatible Software to
+optimize any GCC intermediate representations would not qualify as an
+Eligible Compilation Process.
+
+1. Grant of Additional Permission.
+
+You have permission to propagate a work of Target Code formed by
+combining the Runtime Library with Independent Modules, even if such
+propagation would otherwise violate the terms of GPLv3, provided that
+all Target Code was generated by Eligible Compilation Processes. You
+may then convey such a combination under terms of your choice,
+consistent with the licensing of the Independent Modules.
+
+2. No Weakening of GCC Copyleft.
+
+The availability of this Exception does not imply any general
+presumption that third-party software is unaffected by the copyleft
+requirements of the license of GCC.
+
+
+libquadmath/*.[hc]:
+
+   Copyright (C) 2010 Free Software Foundation, Inc.
+   Written by Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+   Written by Tobias Burnus  <burnus@net-b.de>
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+libquadmath/gdtoa:
+
+The author of this software is David M. Gay.
+
+Copyright (C) 1998, 1999, 2000, 2001 by Lucent Technologies
+All Rights Reserved
+
+Permission to use, copy, modify, and distribute this software and
+its documentation for any purpose and without fee is hereby
+granted, provided that the above copyright notice appear in all
+copies and that both that the copyright notice and this
+permission notice and warranty disclaimer appear in supporting
+documentation, and that the name of Lucent or any of its entities
+not be used in advertising or publicity pertaining to
+distribution of the software without specific, written prior
+permission.
+
+LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.
+IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY
+SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
+IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
+THIS SOFTWARE.
+
+libquadmath/math:
+
+atanq.c, expm1q.c, j0q.c, j1q.c, log1pq.c, logq.c:
+    Copyright 2001 by Stephen L. Moshier <moshier@na-net.ornl.gov> 
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+coshq.c, erfq.c, jnq.c, lgammaq.c, powq.c, roundq.c:
+   Changes for 128-bit __float128 are
+   Copyright (C) 2001 Stephen L. Moshier <moshier@na-net.ornl.gov>
+   and are incorporated herein by permission of the author.  The author 
+   reserves the right to distribute this material elsewhere under different
+   copying permissions.  These modifications are distributed here under 
+   the following terms:
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+ldexpq.c:
+   * Conversion to long double by Ulrich Drepper,
+   * Cygnus Support, drepper@cygnus.com.
+
+cosq_kernel.c, expq.c, sincos_table.c, sincosq.c, sincosq_kernel.c,
+sinq_kernel.c, truncq.c:
+   Copyright (C) 1997, 1999 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+isinfq.c:
+ * Written by J.T. Conklin <jtc@netbsd.org>.
+ * Change for long double by Jakub Jelinek <jj@ultra.linux.cz>
+ * Public domain.
+
+llroundq.c, lroundq.c, tgammaq.c:
+   Copyright (C) 1997, 1999, 2002, 2004 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997 and
+                  Jakub Jelinek <jj@ultra.linux.cz>, 1999.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+log10q.c:
+   Cephes Math Library Release 2.2:  January, 1991
+   Copyright 1984, 1991 by Stephen L. Moshier
+   Adapted for glibc November, 2001
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+remaining files:
+
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+
+
+libjava/classpath/resource/gnu/java/locale/*
+
+They are copyrighted and covered by the terms of use:
+http://www.unicode.org/copyright.html
+
+EXHIBIT 1
+UNICODE, INC. LICENSE AGREEMENT - DATA FILES AND SOFTWARE
+
+ Unicode Data Files include all data files under the directories 
+http://www.unicode.org/Public/ and http://www.unicode.org/reports/. 
+Unicode Software includes any source code published in the Unicode Standard or 
+under the directories http://www.unicode.org/Public/ and 
+http://www.unicode.org/reports/.
+
+NOTICE TO USER: Carefully read the following legal agreement. BY DOWNLOADING, 
+INSTALLING, COPYING OR OTHERWISE USING UNICODE INC.'S DATA FILES ("DATA FILES"), 
+AND/OR SOFTWARE ("SOFTWARE"), YOU UNEQUIVOCALLY ACCEPT, AND AGREE TO BE BOUND BY, 
+ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT. IF YOU DO NOT AGREE, 
+DO NOT DOWNLOAD, INSTALL, COPY, DISTRIBUTE OR USE THE DATA FILES OR SOFTWARE.
+
+	    COPYRIGHT AND PERMISSION NOTICE
+
+Copyrigh (c) 1991-2011 Unicode, Inc. All rights reserved. 
+Distributed under the Terms of Use in http://www.unicode.org/copyright.html.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy 
+of the Unicode data files and any associated documentation (the "Data Files") 
+or Unicode software and any associated documentation (the "Software") to deal 
+in the Data Files or Software without restriction, including without limitation 
+the rights to use, copy, modify, merge, publish, distribute, and/or sell copies
+ of the Data Files or Software, and to permit persons to whom the Data Files 
+or Software are furnished to do so, provided that (a) the above copyright notice(s) 
+and this permission notice appear with all copies of the Data Files or Software, 
+(b) both the above copyright notice(s) and this permission notice appear 
+in associated documentation, and (c) there is clear notice in each modified 
+Data File or in the Software as well as in the documentation associated with 
+the Data File(s) or Software that the data or software has been modified.
+
+THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE LIABLE
+ FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES 
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF 
+CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 
+WITH THE USE OR PERFORMANCE OF THE DATA FILES OR SOFTWARE.
+
+Except as contained in this notice, the name of a copyright holder shall not be used
+ in advertising or otherwise to promote the sale, use or other dealings in these 
+Data Files or Software without prior written authorization of the copyright holder.
+
+Unicode and the Unicode logo are trademarks of Unicode, Inc., and may be registered
+ in some jurisdictions. All other trademarks and registered trademarks mentioned 
+herein are the property of their respective owners.
+
+
+gcc/go/gofrontend, libgo:
+
+Copyright (c) 2009 The Go Authors. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+   * Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following disclaimer
+in the documentation and/or other materials provided with the
+distribution.
+   * Neither the name of Google Inc. nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+libcilkrts, libmpx:
+ Copyright (C) 2009-2014, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+   * Neither the name of Intel Corporation nor the names of its
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
+ WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+
+D:
+gdc-6                         GNU D Compiler
+libphobos-6-dev               D standard runtime library
+
+The D source package is made up of the following components.
+
+The D front-end for GCC:
+ - d/*
+
+Copyright (C) 2004-2007 David Friedman
+Modified by Vincenzo Ampolo, Michael Parrot, Iain Buclaw, (C) 2009, 2010
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 2 of this
+license in `/usr/share/common-licenses/GPL-2'.
+
+
+The DMD Compiler implementation of the D programming language:
+ - d/dmd/*
+
+Copyright (c) 1999-2010 by Digital Mars
+All Rights Reserved
+written by Walter Bright
+http://www.digitalmars.com
+License for redistribution is by either the Artistic License or
+the GNU General Public License (v1).
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', the Artistic
+license in `/usr/share/common-licenses/Artistic'.
+
+
+The Zlib data compression library:
+ - d/phobos/etc/c/zlib/*
+
+ (C) 1995-2004 Jean-loup Gailly and Mark Adler
+
+  This software is provided 'as-is', without any express or implied
+  warranty.  In no event will the authors be held liable for any damages
+  arising from the use of this software.
+
+  Permission is granted to anyone to use this software for any purpose,
+  including commercial applications, and to alter it and redistribute it
+  freely, subject to the following restrictions:
+
+  1. The origin of this software must not be misrepresented; you must not
+     claim that you wrote the original software. If you use this software
+     in a product, an acknowledgment in the product documentation would be
+     appreciated but is not required.
+  2. Altered source versions must be plainly marked as such, and must not be
+     misrepresented as being the original software.
+  3. This notice may not be removed or altered from any source distribution.
+
+
+The Phobos standard runtime library:
+ - d/phobos/*
+
+Unless otherwise marked within the file, each file in the source
+is under the following licenses:
+
+Copyright (C) 2004-2005 by Digital Mars, www.digitalmars.com
+Written by Walter Bright
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any damages
+arising from the use of this software.
+
+Permission is granted to anyone to use this software for any purpose,
+including commercial applications, and to alter it and redistribute it
+freely, in both source and binary form, subject to the following
+restrictions:
+
+ o  The origin of this software must not be misrepresented; you must not
+    claim that you wrote the original software. If you use this software
+    in a product, an acknowledgment in the product documentation would be
+    appreciated but is not required.
+ o  Altered source versions must be plainly marked as such, and must not
+    be misrepresented as being the original software.
+ o  This notice may not be removed or altered from any source
+    distribution.
+
+By plainly marking modifications, something along the lines of adding to each
+file that has been changed a "Modified by Foo Bar" line
+underneath the "Written by" line would be adequate.
+
--- gcc-6-6.3.0.orig/debian/copyright.in
+++ gcc-6-6.3.0/debian/copyright.in
@@ -0,0 +1,692 @@
+This is the Debian GNU/Linux prepackaged version of the GNU compiler
+collection, containing Ada, C, C++, Fortran 95, Java, Objective-C,
+Objective-C++, and Treelang compilers, documentation, and support
+libraries.  In addition, Debian provides the gdc compiler, either in
+the same source package, or built from a separate same source package.
+Packaging is done by the Debian GCC Maintainers
+<debian-gcc@lists.debian.org>, with sources obtained from:
+
+  ftp://gcc.gnu.org/pub/gcc/releases/  (for full releases)
+  svn://gcc.gnu.org/svn/gcc/           (for prereleases)
+  http://bitbucket.org/goshawk/gdc     (for D)
+
+The current gcc-@BV@ source package is taken from the SVN @SVN_BRANCH@.
+
+Changes: See changelog.Debian.gz
+
+Debian splits the GNU Compiler Collection into packages for each language,
+library, and documentation as follows:
+
+Language       Compiler package  Library package    Documentation
+---------------------------------------------------------------------------
+Ada            gnat-@BV@          libgnat-@BV@        gnat-@BV@-doc
+C              gcc-@BV@                              gcc-@BV@-doc
+C++            g++-@BV@           libstdc++6         libstdc++6-@BV@-doc
+D              gdc-@BV@
+Fortran 95     gfortran-@BV@      libgfortran3       gfortran-@BV@-doc
+Go             gccgo-@BV@         libgo0
+Java           gcj-@BV@           libgcj10           libgcj-doc
+Objective C    gobjc-@BV@         libobjc2
+Objective C++  gobjc++-@BV@
+
+For some language run-time libraries, Debian provides source files,
+development files, debugging symbols and libraries containing position-
+independent code in separate packages:
+
+Language  Sources      Development   Debugging            Position-Independent
+------------------------------------------------------------------------------
+C++                                  libstdc++6-@BV@-dbg  libstdc++6-@BV@-pic
+D         libphobos-@BV@-dev
+Java      libgcj10-src libgcj10-dev  libgcj10-dbg
+
+Additional packages include:
+
+All languages:
+libgcc1, libgcc2, libgcc4       GCC intrinsics (platform-dependent)
+gcc-@BV@-base                    Base files common to all compilers
+gcc-@BV@-soft-float              Software floating point (ARM only)
+gcc-@BV@-source                  The sources with patches
+
+Ada:
+libgnatvsn-dev, libgnatvsn@BV@   GNAT version library
+libgnatprj-dev, libgnatprj@BV@   GNAT Project Manager library
+
+C:
+cpp-@BV@, cpp-@BV@-doc            GNU C Preprocessor
+libssp0-dev, libssp0            GCC stack smashing protection library
+libquadmath0                    Math routines for the __float128 type
+fixincludes                     Fix non-ANSI header files
+
+Java:
+gij                             The Java bytecode interpreter and VM
+libgcj-common                   Common files for the Java run-time
+libgcj10-awt                    The Abstract Windowing Toolkit
+libgcj10-jar                    Java ARchive for the Java run-time
+
+C, C++ and Fortran 95:
+libgomp1-dev, libgomp1		GCC OpenMP (GOMP) support library
+libitm1-dev, libitm1		GNU Transactional Memory Library
+
+Biarch support: On some 64-bit platforms which can also run 32-bit code,
+Debian provides additional packages containing 32-bit versions of some
+libraries.  These packages have names beginning with 'lib32' instead of
+'lib', for example lib32stdc++6.  Similarly, on some 32-bit platforms which
+can also run 64-bit code, Debian provides additional packages with names
+beginning with 'lib64' instead of 'lib'.  These packages contain 64-bit
+versions of the libraries.  (At this time, not all platforms and not all
+libraries support biarch.)  The license terms for these lib32 or lib64
+packages are identical to the ones for the lib packages.
+
+
+COPYRIGHT STATEMENTS AND LICENSING TERMS
+
+
+GCC is Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994,
+1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
+2008, 2009, 2010, 2011, 2012, 2013, 2014 Free Software Foundation, Inc.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Files that have exception clauses are licensed under the terms of the
+GNU General Public License; either version 3, or (at your option) any
+later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 3 of this
+license in `/usr/share/common-licenses/GPL-3'.
+
+The following runtime libraries are licensed under the terms of the
+GNU General Public License (v3 or later) with version 3.1 of the GCC
+Runtime Library Exception (included in this file):
+
+ - libgcc (libgcc/, gcc/libgcc2.[ch], gcc/unwind*, gcc/gthr*,
+   gcc/coretypes.h, gcc/crtstuff.c, gcc/defaults.h, gcc/dwarf2.h,
+   gcc/emults.c, gcc/gbl-ctors.h, gcc/gcov-io.h, gcc/libgcov.c,
+   gcc/tsystem.h, gcc/typeclass.h).
+ - libatomic
+ - libdecnumber
+ - libgomp
+ - libitm
+ - libssp
+ - libstdc++-v3
+ - libobjc
+ - libgfortran
+ - The libgnat-@BV@ Ada support library and libgnatvsn library.
+ - Various config files in gcc/config/ used in runtime libraries.
+ - libvtv
+
+In contrast, libgnatprj is licensed under the terms of the pure GNU
+General Public License.
+
+The libbacktrace library is licensed under the following terms:
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+    (1) Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer. 
+
+    (2) Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in
+    the documentation and/or other materials provided with the
+    distribution.  
+    
+    (3) The name of the author may not be used to
+    endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+
+The libsanitizer libraries (libasan, liblsan, libtsan, libubsan) are
+licensed under the following terms:
+
+Copyright (c) 2009-2014 by the LLVM contributors.
+
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+
+The libgcj library is licensed under the terms of the GNU General
+Public License, with a special exception:
+
+    Linking this library statically or dynamically with other modules
+    is making a combined work based on this library.  Thus, the terms
+    and conditions of the GNU General Public License cover the whole
+    combination.
+
+    As a special exception, the copyright holders of this library give
+    you permission to link this library with independent modules to
+    produce an executable, regardless of the license terms of these
+    independent modules, and to copy and distribute the resulting
+    executable under terms of your choice, provided that you also
+    meet, for each linked independent module, the terms and conditions
+    of the license of that module.  An independent module is a module
+    which is not derived from or based on this library.  If you modify
+    this library, you may extend this exception to your version of the
+    library, but you are not obligated to do so.  If you do not wish
+    to do so, delete this exception statement from your version.
+
+The libffi library is licensed under the following terms:
+
+    libffi - Copyright (c) 1996-2003  Red Hat, Inc.
+
+    Permission is hereby granted, free of charge, to any person obtaining
+    a copy of this software and associated documentation files (the
+    ``Software''), to deal in the Software without restriction, including
+    without limitation the rights to use, copy, modify, merge, publish,
+    distribute, sublicense, and/or sell copies of the Software, and to
+    permit persons to whom the Software is furnished to do so, subject to
+    the following conditions:
+
+    The above copyright notice and this permission notice shall be included
+    in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
+    OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+    IN NO EVENT SHALL CYGNUS SOLUTIONS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+    OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+    ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+    OTHER DEALINGS IN THE SOFTWARE.
+
+
+The documentation is licensed under the GNU Free Documentation License (v1.2).
+On Debian GNU/Linux systems, the complete text of this license is in
+`/usr/share/common-licenses/GFDL-1.2'.
+
+
+GCC RUNTIME LIBRARY EXCEPTION
+
+Version 3.1, 31 March 2009
+
+Copyright (C) 2009 Free Software Foundation, Inc. <http://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this
+license document, but changing it is not allowed.
+
+This GCC Runtime Library Exception ("Exception") is an additional
+permission under section 7 of the GNU General Public License, version
+3 ("GPLv3"). It applies to a given file (the "Runtime Library") that
+bears a notice placed by the copyright holder of the file stating that
+the file is governed by GPLv3 along with this Exception.
+
+When you use GCC to compile a program, GCC may combine portions of
+certain GCC header files and runtime libraries with the compiled
+program. The purpose of this Exception is to allow compilation of
+non-GPL (including proprietary) programs to use, in this way, the
+header files and runtime libraries covered by this Exception.
+
+0. Definitions.
+
+A file is an "Independent Module" if it either requires the Runtime
+Library for execution after a Compilation Process, or makes use of an
+interface provided by the Runtime Library, but is not otherwise based
+on the Runtime Library.
+
+"GCC" means a version of the GNU Compiler Collection, with or without
+modifications, governed by version 3 (or a specified later version) of
+the GNU General Public License (GPL) with the option of using any
+subsequent versions published by the FSF.
+
+"GPL-compatible Software" is software whose conditions of propagation,
+modification and use would permit combination with GCC in accord with
+the license of GCC.
+
+"Target Code" refers to output from any compiler for a real or virtual
+target processor architecture, in executable form or suitable for
+input to an assembler, loader, linker and/or execution
+phase. Notwithstanding that, Target Code does not include data in any
+format that is used as a compiler intermediate representation, or used
+for producing a compiler intermediate representation.
+
+The "Compilation Process" transforms code entirely represented in
+non-intermediate languages designed for human-written code, and/or in
+Java Virtual Machine byte code, into Target Code. Thus, for example,
+use of source code generators and preprocessors need not be considered
+part of the Compilation Process, since the Compilation Process can be
+understood as starting with the output of the generators or
+preprocessors.
+
+A Compilation Process is "Eligible" if it is done using GCC, alone or
+with other GPL-compatible software, or if it is done without using any
+work based on GCC. For example, using non-GPL-compatible Software to
+optimize any GCC intermediate representations would not qualify as an
+Eligible Compilation Process.
+
+1. Grant of Additional Permission.
+
+You have permission to propagate a work of Target Code formed by
+combining the Runtime Library with Independent Modules, even if such
+propagation would otherwise violate the terms of GPLv3, provided that
+all Target Code was generated by Eligible Compilation Processes. You
+may then convey such a combination under terms of your choice,
+consistent with the licensing of the Independent Modules.
+
+2. No Weakening of GCC Copyleft.
+
+The availability of this Exception does not imply any general
+presumption that third-party software is unaffected by the copyleft
+requirements of the license of GCC.
+
+
+libquadmath/*.[hc]:
+
+   Copyright (C) 2010 Free Software Foundation, Inc.
+   Written by Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+   Written by Tobias Burnus  <burnus@net-b.de>
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+libquadmath/gdtoa:
+
+The author of this software is David M. Gay.
+
+Copyright (C) 1998, 1999, 2000, 2001 by Lucent Technologies
+All Rights Reserved
+
+Permission to use, copy, modify, and distribute this software and
+its documentation for any purpose and without fee is hereby
+granted, provided that the above copyright notice appear in all
+copies and that both that the copyright notice and this
+permission notice and warranty disclaimer appear in supporting
+documentation, and that the name of Lucent or any of its entities
+not be used in advertising or publicity pertaining to
+distribution of the software without specific, written prior
+permission.
+
+LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.
+IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY
+SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
+IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
+THIS SOFTWARE.
+
+libquadmath/math:
+
+atanq.c, expm1q.c, j0q.c, j1q.c, log1pq.c, logq.c:
+    Copyright 2001 by Stephen L. Moshier <moshier@na-net.ornl.gov> 
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+coshq.c, erfq.c, jnq.c, lgammaq.c, powq.c, roundq.c:
+   Changes for 128-bit __float128 are
+   Copyright (C) 2001 Stephen L. Moshier <moshier@na-net.ornl.gov>
+   and are incorporated herein by permission of the author.  The author 
+   reserves the right to distribute this material elsewhere under different
+   copying permissions.  These modifications are distributed here under 
+   the following terms:
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+ldexpq.c:
+   * Conversion to long double by Ulrich Drepper,
+   * Cygnus Support, drepper@cygnus.com.
+
+cosq_kernel.c, expq.c, sincos_table.c, sincosq.c, sincosq_kernel.c,
+sinq_kernel.c, truncq.c:
+   Copyright (C) 1997, 1999 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+isinfq.c:
+ * Written by J.T. Conklin <jtc@netbsd.org>.
+ * Change for long double by Jakub Jelinek <jj@ultra.linux.cz>
+ * Public domain.
+
+llroundq.c, lroundq.c, tgammaq.c:
+   Copyright (C) 1997, 1999, 2002, 2004 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997 and
+                  Jakub Jelinek <jj@ultra.linux.cz>, 1999.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+log10q.c:
+   Cephes Math Library Release 2.2:  January, 1991
+   Copyright 1984, 1991 by Stephen L. Moshier
+   Adapted for glibc November, 2001
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+remaining files:
+
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+
+
+libjava/classpath/resource/gnu/java/locale/*
+
+They are copyrighted and covered by the terms of use:
+http://www.unicode.org/copyright.html
+
+EXHIBIT 1
+UNICODE, INC. LICENSE AGREEMENT - DATA FILES AND SOFTWARE
+
+ Unicode Data Files include all data files under the directories 
+http://www.unicode.org/Public/ and http://www.unicode.org/reports/. 
+Unicode Software includes any source code published in the Unicode Standard or 
+under the directories http://www.unicode.org/Public/ and 
+http://www.unicode.org/reports/.
+
+NOTICE TO USER: Carefully read the following legal agreement. BY DOWNLOADING, 
+INSTALLING, COPYING OR OTHERWISE USING UNICODE INC.'S DATA FILES ("DATA FILES"), 
+AND/OR SOFTWARE ("SOFTWARE"), YOU UNEQUIVOCALLY ACCEPT, AND AGREE TO BE BOUND BY, 
+ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT. IF YOU DO NOT AGREE, 
+DO NOT DOWNLOAD, INSTALL, COPY, DISTRIBUTE OR USE THE DATA FILES OR SOFTWARE.
+
+	    COPYRIGHT AND PERMISSION NOTICE
+
+Copyrigh (c) 1991-2011 Unicode, Inc. All rights reserved. 
+Distributed under the Terms of Use in http://www.unicode.org/copyright.html.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy 
+of the Unicode data files and any associated documentation (the "Data Files") 
+or Unicode software and any associated documentation (the "Software") to deal 
+in the Data Files or Software without restriction, including without limitation 
+the rights to use, copy, modify, merge, publish, distribute, and/or sell copies
+ of the Data Files or Software, and to permit persons to whom the Data Files 
+or Software are furnished to do so, provided that (a) the above copyright notice(s) 
+and this permission notice appear with all copies of the Data Files or Software, 
+(b) both the above copyright notice(s) and this permission notice appear 
+in associated documentation, and (c) there is clear notice in each modified 
+Data File or in the Software as well as in the documentation associated with 
+the Data File(s) or Software that the data or software has been modified.
+
+THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE LIABLE
+ FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES 
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF 
+CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 
+WITH THE USE OR PERFORMANCE OF THE DATA FILES OR SOFTWARE.
+
+Except as contained in this notice, the name of a copyright holder shall not be used
+ in advertising or otherwise to promote the sale, use or other dealings in these 
+Data Files or Software without prior written authorization of the copyright holder.
+
+Unicode and the Unicode logo are trademarks of Unicode, Inc., and may be registered
+ in some jurisdictions. All other trademarks and registered trademarks mentioned 
+herein are the property of their respective owners.
+
+
+gcc/go/gofrontend, libgo:
+
+Copyright (c) 2009 The Go Authors. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+   * Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following disclaimer
+in the documentation and/or other materials provided with the
+distribution.
+   * Neither the name of Google Inc. nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+libcilkrts, libmpx:
+ Copyright (C) 2009-2014, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+   * Neither the name of Intel Corporation nor the names of its
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
+ WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+
+D:
+gdc-@BV@                         GNU D Compiler
+libphobos-@BV@-dev               D standard runtime library
+
+The D source package is made up of the following components.
+
+The D front-end for GCC:
+ - d/*
+
+Copyright (C) 2004-2007 David Friedman
+Modified by Vincenzo Ampolo, Michael Parrot, Iain Buclaw, (C) 2009, 2010
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 2 of this
+license in `/usr/share/common-licenses/GPL-2'.
+
+
+The DMD Compiler implementation of the D programming language:
+ - d/dmd/*
+
+Copyright (c) 1999-2010 by Digital Mars
+All Rights Reserved
+written by Walter Bright
+http://www.digitalmars.com
+License for redistribution is by either the Artistic License or
+the GNU General Public License (v1).
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', the Artistic
+license in `/usr/share/common-licenses/Artistic'.
+
+
+The Zlib data compression library:
+ - d/phobos/etc/c/zlib/*
+
+ (C) 1995-2004 Jean-loup Gailly and Mark Adler
+
+  This software is provided 'as-is', without any express or implied
+  warranty.  In no event will the authors be held liable for any damages
+  arising from the use of this software.
+
+  Permission is granted to anyone to use this software for any purpose,
+  including commercial applications, and to alter it and redistribute it
+  freely, subject to the following restrictions:
+
+  1. The origin of this software must not be misrepresented; you must not
+     claim that you wrote the original software. If you use this software
+     in a product, an acknowledgment in the product documentation would be
+     appreciated but is not required.
+  2. Altered source versions must be plainly marked as such, and must not be
+     misrepresented as being the original software.
+  3. This notice may not be removed or altered from any source distribution.
+
+
+The Phobos standard runtime library:
+ - d/phobos/*
+
+Unless otherwise marked within the file, each file in the source
+is under the following licenses:
+
+Copyright (C) 2004-2005 by Digital Mars, www.digitalmars.com
+Written by Walter Bright
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any damages
+arising from the use of this software.
+
+Permission is granted to anyone to use this software for any purpose,
+including commercial applications, and to alter it and redistribute it
+freely, in both source and binary form, subject to the following
+restrictions:
+
+ o  The origin of this software must not be misrepresented; you must not
+    claim that you wrote the original software. If you use this software
+    in a product, an acknowledgment in the product documentation would be
+    appreciated but is not required.
+ o  Altered source versions must be plainly marked as such, and must not
+    be misrepresented as being the original software.
+ o  This notice may not be removed or altered from any source
+    distribution.
+
+By plainly marking modifications, something along the lines of adding to each
+file that has been changed a "Modified by Foo Bar" line
+underneath the "Written by" line would be adequate.
+
--- gcc-6-6.3.0.orig/debian/cpp-BV-CRB.preinst.in
+++ gcc-6-6.3.0/debian/cpp-BV-CRB.preinst.in
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-cpp /usr/bin/@TARGET@-cpp-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.3.0.orig/debian/cpp-BV-doc.doc-base.cpp
+++ gcc-6-6.3.0/debian/cpp-BV-doc.doc-base.cpp
@@ -0,0 +1,16 @@
+Document: cpp-@BV@
+Title: The GNU C preprocessor
+Author: Various
+Abstract: The C preprocessor is a "macro processor" that is used automatically
+ by the C compiler to transform your program before actual compilation.
+ It is called a macro processor because it allows you to define "macros",
+ which are brief abbreviations for longer constructs.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/cpp.html
+Files: /usr/share/doc/gcc-@BV@-base/cpp.html
+
+Format: info
+Index: /usr/share/info/cpp-@BV@.info.gz
+Files: /usr/share/info/cpp-@BV@*
--- gcc-6-6.3.0.orig/debian/cpp-BV-doc.doc-base.cppint
+++ gcc-6-6.3.0/debian/cpp-BV-doc.doc-base.cppint
@@ -0,0 +1,17 @@
+Document: cppinternals-@BV@
+Title: The GNU C preprocessor (internals)
+Author: Various
+Abstract: This brief manual documents the internals of cpplib, and
+ explains some of the tricky issues.  It is intended that, along with
+ the comments in the source code, a reasonably competent C programmer
+ should be able to figure out what the code is doing, and why things
+ have been implemented the way they have.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/cppinternals.html
+Files: /usr/share/doc/gcc-@BV@-base/cppinternals.html
+
+Format: info
+Index: /usr/share/info/cppinternals-@BV@.info.gz
+Files: /usr/share/info/cppinternals-@BV@*
--- gcc-6-6.3.0.orig/debian/dh_doclink
+++ gcc-6-6.3.0/debian/dh_doclink
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+pkg=`echo $1 | sed 's/^-p//'`
+target=$2
+
+[ -d debian/$pkg/usr/share/doc ] || mkdir -p debian/$pkg/usr/share/doc
+if [ -d debian/$pkg/usr/share/doc/$p -a ! -h debian/$pkg/usr/share/doc/$p ]
+then
+    echo "WARNING: removing doc directory  $pkg"
+    rm -rf debian/$pkg/usr/share/doc/$pkg
+fi
+ln -sf $target debian/$pkg/usr/share/doc/$pkg
--- gcc-6-6.3.0.orig/debian/dh_rmemptydirs
+++ gcc-6-6.3.0/debian/dh_rmemptydirs
@@ -0,0 +1,10 @@
+#! /bin/sh -e
+
+pkg=`echo $1 | sed 's/^-p//'`
+
+: # remove empty directories, when all components are in place
+for d in `find debian/$pkg -depth -type d -empty 2> /dev/null`; do \
+    while rmdir $d 2> /dev/null; do d=`dirname $d`; done; \
+done
+
+exit 0
--- gcc-6-6.3.0.orig/debian/dummy-man.1
+++ gcc-6-6.3.0/debian/dummy-man.1
@@ -0,0 +1,29 @@
+.TH @NAME@ 1 "May 24, 2003" @name@ "Debian Free Documentation"
+.SH NAME
+@name@ \- A program with a man page covered by the GFDL with invariant sections
+.SH SYNOPSIS
+@name@ [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fB@name@\fR is documented by a man page, which is covered by the "GNU
+Free Documentation License" (GFDL) containing invariant sections.
+.P
+In November 2002, version 1.2 of the GNU Free Documentation License (GNU
+FDL) was released by the Free Software Foundation after a long period
+of consultation. Unfortunately, some concerns raised by members of the
+Debian Project were not addressed, and as such the GNU FDL can apply
+to works that do not pass the Debian Free Software Guidelines (DFSG),
+and may thus only be included in the non-free component of the Debian
+archive, not the Debian distribution itself.
+
+.SH "SEE ALSO"
+.BR http://gcc.gnu.org/onlinedocs/
+for the complete documentation,
+.BR http://lists.debian.org/debian-legal/2003/debian-legal-200304/msg00307.html
+for a proposed statement of Debian with respect to the GFDL,
+.BR gfdl(7)
+
+.SH AUTHOR
+This manual page was written by the Debian GCC maintainers,
+for the Debian GNU/Linux system.
--- gcc-6-6.3.0.orig/debian/dummy.texi
+++ gcc-6-6.3.0/debian/dummy.texi
@@ -0,0 +1 @@
+@c This file is empty because the original one has a non DFSG free license (GFDL)
--- gcc-6-6.3.0.orig/debian/fixincludes.in
+++ gcc-6-6.3.0/debian/fixincludes.in
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+PATH="/@LIBEXECDIR@/install-tools:$PATH"
+
+TARGET_MACHINE=`dpkg-architecture -qDEB_HOST_GNU_TYPE`
+export TARGET_MACHINE
+
+exec fixinc.sh "$@"
--- gcc-6-6.3.0.orig/debian/g++-BV-CRB.preinst.in
+++ gcc-6-6.3.0/debian/g++-BV-CRB.preinst.in
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-g++ /usr/bin/@TARGET@-g++-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.3.0.orig/debian/gcc-BV-CRB.preinst.in
+++ gcc-6-6.3.0/debian/gcc-BV-CRB.preinst.in
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-gcc /usr/bin/@TARGET@-gcc-@BV@
+    update-alternatives --quiet --remove @TARGET@-gcov /usr/bin/@TARGET@-gcov-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.3.0.orig/debian/gcc-BV-doc.doc-base.gcc
+++ gcc-6-6.3.0/debian/gcc-BV-doc.doc-base.gcc
@@ -0,0 +1,14 @@
+Document: gcc-@BV@
+Title: The GNU C and C++ compiler
+Author: Various
+Abstract: This manual documents how to run, install and port the GNU compiler,
+ as well as its new features and incompatibilities, and how to report bugs.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/gcc.html
+Files: /usr/share/doc/gcc-@BV@-base/gcc.html
+
+Format: info
+Index: /usr/share/info/gcc-@BV@.info.gz
+Files: /usr/share/info/gcc-@BV@*
--- gcc-6-6.3.0.orig/debian/gcc-BV-doc.doc-base.gccint
+++ gcc-6-6.3.0/debian/gcc-BV-doc.doc-base.gccint
@@ -0,0 +1,17 @@
+Document: gccint-@BV@
+Title: Internals of the GNU C and C++ compiler
+Author: Various
+Abstract: This manual documents the internals of the GNU compilers,
+ including how to port them to new targets and some information about
+ how to write front ends for new languages.  It corresponds to GCC
+ version @BV@.x.  The use of the GNU compilers is documented in a
+ separate manual.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/gccint.html
+Files: /usr/share/doc/gcc-@BV@-base/gccint.html
+
+Format: info
+Index: /usr/share/info/gccint-@BV@.info.gz
+Files: /usr/share/info/gccint-@BV@*
--- gcc-6-6.3.0.orig/debian/gcc-BV-doc.doc-base.gomp
+++ gcc-6-6.3.0/debian/gcc-BV-doc.doc-base.gomp
@@ -0,0 +1,15 @@
+Document: gcc-@BV@-gomp
+Title: The GNU OpenMP Implementation (for GCC @BV@)
+Author: Various
+Abstract: This manual documents the usage of libgomp, the GNU implementation
+ of the OpenMP Application Programming Interface (API) for multi-platform
+ shared-memory parallel programming in C/C++ and Fortran.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/libgomp.html
+Files: /usr/share/doc/gcc-@BV@-base/libgomp.html
+
+Format: info
+Index: /usr/share/info/libgomp-@BV@.info.gz
+Files: /usr/share/info/libgomp-@BV@*
--- gcc-6-6.3.0.orig/debian/gcc-BV-doc.doc-base.itm
+++ gcc-6-6.3.0/debian/gcc-BV-doc.doc-base.itm
@@ -0,0 +1,16 @@
+Document: gcc-@BV@-itm
+Title: The GNU Transactional Memory Library (for GCC @BV@)
+Author: Various
+Abstract: This manual documents the usage and internals of libitm,
+ the GNU Transactional Memory Library. It provides transaction support
+ for accesses to a process' memory, enabling easy-to-use synchronization
+ of accesses to shared memory by several threads.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/libitm.html
+Files: /usr/share/doc/gcc-@BV@-base/libitm.html
+
+Format: info
+Index: /usr/share/info/libitm-@BV@.info.gz
+Files: /usr/share/info/libitm-@BV@*
--- gcc-6-6.3.0.orig/debian/gcc-BV-doc.doc-base.qmath
+++ gcc-6-6.3.0/debian/gcc-BV-doc.doc-base.qmath
@@ -0,0 +1,14 @@
+Document: gcc-@BV@-qmath
+Title: The GCC Quad-Precision Math Library (for GCC @BV@)
+Author: Various
+Abstract: This manual documents the usage of libquadmath, the GCC
+ Quad-Precision Math Library Application Programming Interface (API).
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/libquadmath.html
+Files: /usr/share/doc/gcc-@BV@-base/libquadmath.html
+
+Format: info
+Index: /usr/share/info/libquadmath-@BV@.info.gz
+Files: /usr/share/info/libquadmath-@BV@*
--- gcc-6-6.3.0.orig/debian/gcc-BV-hppa64-linux-gnu.overrides
+++ gcc-6-6.3.0/debian/gcc-BV-hppa64-linux-gnu.overrides
@@ -0,0 +1,2 @@
+gcc-@BV@-hppa64-linux-gnu binary: binary-from-other-architecture
+gcc-@BV@-hppa64-linux-gnu binary: binary-without-manpage
--- gcc-6-6.3.0.orig/debian/gcc-BV-multilib.overrides
+++ gcc-6-6.3.0/debian/gcc-BV-multilib.overrides
@@ -0,0 +1 @@
+gcc-@BV@-multilib binary: binary-from-other-architecture
--- gcc-6-6.3.0.orig/debian/gcc-BV-source.overrides
+++ gcc-6-6.3.0/debian/gcc-BV-source.overrides
@@ -0,0 +1,5 @@
+gcc-@BV@-source: changelog-file-not-compressed
+
+# these are patches taken over unmodified from 4.3
+gcc-@BV@-source: script-not-executable
+gcc-@BV@-source: shell-script-fails-syntax-check
--- gcc-6-6.3.0.orig/debian/gcc-XX-BV.1
+++ gcc-6-6.3.0/debian/gcc-XX-BV.1
@@ -0,0 +1,17 @@
+.TH GCC-@TOOL@-@BV@ 1 "May 8, 2012" gcc-@TOOL@-@BV@ ""
+.SH NAME
+gcc-@TOOL@ \- a wrapper around @TOOL@ adding the --plugin option
+
+.SH SYNOPSIS
+gcc-@TOOL@ [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgcc-@TOOL@\fR is a wrapper around @TOOL@(1) adding the appropriate
+\fB\-\-plugin\fR option for the GCC @BV@ compiler.
+
+.SH OPTIONS
+See @TOOL@(1) for a list of options that @TOOL@ understands.
+
+.SH "SEE ALSO"
+.BR @TOOL@(1)
--- gcc-6-6.3.0.orig/debian/gcc-dummy.texi
+++ gcc-6-6.3.0/debian/gcc-dummy.texi
@@ -0,0 +1,41 @@
+\input texinfo  @c -*-texinfo-*-
+@c %**start of header
+
+@settitle The GNU Compiler Collection (GCC)
+
+@c Create a separate index for command line options.
+@defcodeindex op
+@c Merge the standard indexes into a single one.
+@syncodeindex fn cp
+@syncodeindex vr cp
+@syncodeindex ky cp
+@syncodeindex pg cp
+@syncodeindex tp cp
+
+@paragraphindent 1
+
+@c %**end of header
+
+@copying
+The current documentation is licensed under the same terms as the Debian packaging.
+@end copying
+@ifnottex
+@dircategory Programming
+@direntry
+* @name@: (@name@).                  The GNU Compiler Collection (@name@).
+@end direntry
+@sp 1
+@end ifnottex
+
+@summarycontents
+@contents
+@page
+
+@node Top
+@top Introduction
+@cindex introduction
+The official GNU compilers' documentation is released under the terms
+of the GNU Free Documentation License with cover texts. This has been
+considered non free by the Debian Project. Thus you will find it in the
+non-free section of the Debian archive.
+@bye
--- gcc-6-6.3.0.orig/debian/gcc-snapshot.overrides
+++ gcc-6-6.3.0/debian/gcc-snapshot.overrides
@@ -0,0 +1,10 @@
+gcc-snapshot binary: bad-permissions-for-ali-file
+
+# keep patched ltdl copy
+gcc-snapshot binary: embedded-library
+
+gcc-snapshot binary: binary-from-other-architecture
+gcc-snapshot binary: extra-license-file
+gcc-snapshot binary: jar-not-in-usr-share
+gcc-snapshot binary: triplet-dir-and-architecture-mismatch
+gcc-snapshot binary: unstripped-binary-or-object
--- gcc-6-6.3.0.orig/debian/gcc-snapshot.prerm
+++ gcc-6-6.3.0/debian/gcc-snapshot.prerm
@@ -0,0 +1,5 @@
+#! /bin/sh -e
+
+rm -f /usr/lib/gcc-snapshot/share/python/*.py[co]
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/gccgo-BV-doc.doc-base
+++ gcc-6-6.3.0/debian/gccgo-BV-doc.doc-base
@@ -0,0 +1,17 @@
+Document: gccgo-@BV@
+Title: The GNU Go compiler (version @BV@)
+Author: Various
+Abstract: This manual describes how to use gccgo, the GNU compiler for
+ the Go programming language.  This manual is specifically about
+ gccgo.  For more information about the Go programming
+ language in general, including language specifications and standard
+ package documentation, see http://golang.org/.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/gccgo.html
+Files: /usr/share/doc/gcc-@BV@-base/gccgo.html
+
+Format: info
+Index: /usr/share/info/gccgo-@BV@.info.gz
+Files: /usr/share/info/gccgo-@BV@*
--- gcc-6-6.3.0.orig/debian/gcj-BV-jdk.doc-base
+++ gcc-6-6.3.0/debian/gcj-BV-jdk.doc-base
@@ -0,0 +1,15 @@
+Document: gcj-@BV@
+Title: The GNU Ahead-of-time Compiler for the Java Language
+Author: Various
+Abstract: This manual describes how to use gcj, the GNU compiler for
+ the Java programming language.  gcj can generate both .class files and
+ object files, and it can read both Java source code and .class files.
+Section: Programming/Java
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/java/gcj.html
+Files: /usr/share/doc/gcc-@BV@-base/java/gcj.html
+
+Format: info
+Index: /usr/share/info/gcj-@BV@.info.gz
+Files: /usr/share/info/gcj-@BV@*
--- gcc-6-6.3.0.orig/debian/gcj-BV-jdk.overrides
+++ gcc-6-6.3.0/debian/gcj-BV-jdk.overrides
@@ -0,0 +1 @@
+gcj-@BV@-jdk binary: wrong-name-for-upstream-changelog
--- gcc-6-6.3.0.orig/debian/gcj-BV-jdk.postinst
+++ gcc-6-6.3.0/debian/gcj-BV-jdk.postinst
@@ -0,0 +1,45 @@
+#! /bin/sh -e
+
+if [ -d /usr/share/doc/gcc-@BV@-base/java ] && [ ! -h /usr/share/doc/gcc-@BV@-base/java ]; then
+    rm -rf /usr/share/doc/gcc-@BV@-base/java
+    ln -s ../gcj-@BV@-base /usr/share/doc/gcc-@BV@-base/java
+fi
+
+prio=@java_priority@
+update-alternatives --quiet \
+    --install /usr/bin/javac javac /usr/bin/gcj-wrapper-@BV@ $prio \
+    @GFDL@--slave /usr/share/man/man1/javac.1.gz javac.1.gz /usr/share/man/man1/gcj-wrapper-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/jar jar /usr/bin/gjar-@BV@ $prio \
+    --slave /usr/share/man/man1/jar.1.gz jar.1.gz /usr/share/man/man1/gjar-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/jarsigner jarsigner /usr/bin/gjarsigner-@BV@ $prio \
+    --slave /usr/share/man/man1/jarsigner.1.gz jarsigner.1.gz /usr/share/man/man1/gjarsigner-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/javah javah /usr/bin/gjavah-@BV@ $prio \
+    --slave /usr/share/man/man1/javah.1.gz javah.1.gz /usr/share/man/man1/gjavah-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/javadoc javadoc /usr/bin/gjdoc-@BV@ $prio \
+    --slave /usr/share/man/man1/javadoc.1.gz javadoc.1.gz /usr/share/man/man1/gjdoc-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/native2ascii native2ascii /usr/bin/gnative2ascii-@BV@ $prio \
+    --slave /usr/share/man/man1/native2ascii.1.gz native2ascii.1.gz /usr/share/man/man1/gnative2ascii-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/rmic rmic /usr/bin/grmic-@BV@ $prio \
+    @GFDL@--slave /usr/share/man/man1/rmic.1.gz rmic.1.gz /usr/share/man/man1/grmic-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/serialver serialver /usr/bin/gserialver-@BV@ $prio \
+    --slave /usr/share/man/man1/serialver.1.gz serialver.1.gz /usr/share/man/man1/gserialver-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/tnameserv tnameserv /usr/bin/gtnameserv-@BV@ $prio \
+    --slave /usr/share/man/man1/tnameserv.1.gz tnameserv.1.gz /usr/share/man/man1/gtnameserv-@BV@.1.gz
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/gcj-BV-jdk.prerm
+++ gcc-6-6.3.0/debian/gcj-BV-jdk.prerm
@@ -0,0 +1,15 @@
+#! /bin/sh -e
+
+if [ "$1" = "remove" ] || [ "$1" = "deconfigure" ]; then
+    update-alternatives --quiet --remove javac /usr/bin/gcj-wrapper-@BV@
+    update-alternatives --quiet --remove jar /usr/bin/gjar-@BV@
+    update-alternatives --quiet --remove jarsigner /usr/bin/gjarsigner-@BV@
+    update-alternatives --quiet --remove javah /usr/bin/gjavah-@BV@
+    update-alternatives --quiet --remove javadoc /usr/bin/gjdoc-@BV@
+    update-alternatives --quiet --remove native2ascii /usr/bin/gnative2ascii-@BV@
+    update-alternatives --quiet --remove rmic /usr/bin/grmic-@BV@
+    update-alternatives --quiet --remove serialver /usr/bin/gserialver-@BV@
+    update-alternatives --quiet --remove tnameserv /usr/bin/gtnameserv-@BV@
+fi
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/gcj-BV-jre-headless.overrides
+++ gcc-6-6.3.0/debian/gcj-BV-jre-headless.overrides
@@ -0,0 +1,5 @@
+# pick up the exact version, in case another gcj version is installed
+gcj-@BV@-jre-headless binary: binary-or-shlib-defines-rpath
+
+# don't strip the binaries, keep the libgcj13-dbg package Multi-Arch: same
+gcj-@BV@-jre-headless binary: unstripped-binary-or-object
--- gcc-6-6.3.0.orig/debian/gcj-BV-jre-headless.postinst
+++ gcc-6-6.3.0/debian/gcj-BV-jre-headless.postinst
@@ -0,0 +1,48 @@
+#! /bin/sh -e
+
+prio=@java_priority@
+
+update-alternatives --quiet \
+    --install /usr/bin/java java /usr/bin/gij-@BV@ $prio \
+    @GFDL@--slave /usr/share/man/man1/java.1.gz java.1.gz /usr/share/man/man1/gij-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/rmiregistry rmiregistry /usr/bin/grmiregistry-@BV@ $prio \
+    --slave /usr/share/man/man1/rmiregistry.1.gz rmiregistry.1.gz /usr/share/man/man1/grmiregistry-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/keytool keytool /usr/bin/gkeytool-@BV@ $prio \
+    --slave /usr/share/man/man1/keytool.1.gz keytool.1.gz /usr/share/man/man1/gkeytool-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/orbd orbd /usr/bin/gorbd-@BV@ $prio \
+    --slave /usr/share/man/man1/orbd.1.gz orbd.1.gz /usr/share/man/man1/gorbd-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/rmid rmid /usr/bin/grmid-@BV@ $prio \
+    --slave /usr/share/man/man1/rmid.1.gz rmid.1.gz /usr/share/man/man1/grmid-@BV@.1.gz
+
+case "$1" in
+configure)
+    if [ ! -f /var/lib/gcj-@BV@/classmap.db ]; then
+	uname=$(uname -m)
+	mkdir -p /var/lib/gcj-@BV@
+	if gcj-dbtool-@BV@ -n /var/lib/gcj-@BV@/classmap.db; then
+	    case "$uname" in arm*|m68k|parisc*)
+	        echo >&2 "gcj-dbtool succeeded unexpectedly"
+	    esac
+	else
+	    case "$uname" in
+	    arm*|m68k|parisc*)
+	        echo >&2 "ERROR: gcj-dbtool did fail; known problem on $uname";;
+	    *)
+		exit 2
+	    esac
+	    touch /var/lib/gcj-@BV@/classmap.db
+	fi
+    fi
+esac
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.3.0.orig/debian/gcj-BV-jre-headless.postrm
+++ gcc-6-6.3.0/debian/gcj-BV-jre-headless.postrm
@@ -0,0 +1,10 @@
+#! /bin/sh -e
+
+case "$1" in
+    purge)
+	rm -f /var/lib/gcj-@BV@/classmap.db
+esac
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.3.0.orig/debian/gcj-BV-jre-headless.prerm
+++ gcc-6-6.3.0/debian/gcj-BV-jre-headless.prerm
@@ -0,0 +1,13 @@
+#! /bin/sh -e
+
+if [ "$1" = "remove" ] || [ "$1" = "deconfigure" ]; then
+    update-alternatives --quiet --remove java /usr/bin/gij-@BV@
+    update-alternatives --quiet --remove rmiregistry /usr/bin/grmiregistry-@BV@
+    update-alternatives --quiet --remove keytool /usr/bin/gkeytool-@BV@
+    update-alternatives --quiet --remove orbd /usr/bin/gorbd-@BV@
+    update-alternatives --quiet --remove rmid /usr/bin/grmid-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.3.0.orig/debian/gcj-wrapper-BV
+++ gcc-6-6.3.0/debian/gcj-wrapper-BV
@@ -0,0 +1,91 @@
+#!/usr/bin/perl -w
+#
+# Starts the GNU Java compiler.
+#
+# Command-line arguments should be in the style of Sun's Java compiler;
+# these will be converted to gcj arguments before being passed to the
+# gcj itself.
+#
+# Copyright (C) 2002-2003 by Ben Burton <bab@debian.org>
+# Based on the original gcj-wrapper-3.2 shell script.
+
+use strict;
+
+# The real Java compiler:
+my $javaCompiler = '/usr/bin/gcj-@BV@';
+
+# The command-line arguments to pass to the real Java compiler:
+my @commandLine;
+
+# The warning flags to pass to the GNU Java compiler:
+my $warnings = '-Wall';
+
+# Build the command-line from the arguments given.
+my $parsingOptions = 1;
+my $copyNextArg = 0;
+my $ignoreNextArg = 0;
+my $appendNextArg = '';
+foreach my $arg (@ARGV) {
+    # See if we already know what to do with this argument.
+    if ($ignoreNextArg) {
+        # Throw it away.
+        $ignoreNextArg = 0;
+        next;
+    } elsif ($copyNextArg or not $parsingOptions) {
+        # Copy it directly.
+        push @commandLine, $arg;
+        $copyNextArg = 0;
+        next;
+    } elsif ($appendNextArg) {
+        # Append it to $appendNextArg and then copy directly.
+        push @commandLine, ($appendNextArg . $arg);
+        $appendNextArg = '';
+        next;
+    }
+
+    # Try to interpret Sun-style options.
+    if ($arg eq '-version') {
+        push @commandLine, '--version';
+    } elsif ($arg eq '-h' or $arg eq '-help') {
+        push @commandLine, '--help';
+    } elsif ($arg eq '-classpath' or $arg eq '--classpath' or $arg eq '--cp') {
+        $appendNextArg = '--classpath=';
+    } elsif ($arg eq '-encoding' or $arg eq '-bootclasspath' or
+             $arg eq '-extdirs') {
+        $appendNextArg = '-' . $arg . '=';
+    } elsif ($arg eq '-d') {
+        push @commandLine, '-d';
+        $copyNextArg = 1;
+    } elsif ($arg eq '-nowarn') {
+        $warnings = '';
+    } elsif ($arg =~ /^-g/) {
+        # Some kind of debugging option - just switch debugging on.
+        push @commandLine, '-g' if ($arg ne '-g:none');
+    } elsif ($arg eq '-O') {
+        push @commandLine, '-O2';
+    } elsif ($arg eq '-Xss') {
+        push @commandLine, $arg;
+    } elsif ($arg =~ /^-X/) {
+        # An extended Sun option (which we don't support).
+        push @commandLine, '--help' if ($arg eq '-X');
+    } elsif ($arg eq '-source' or $arg eq '-sourcepath' or $arg eq '-target') {
+        # An unsupported option with a following argument.
+        $ignoreNextArg = 1;
+    } elsif ($arg =~ /^-/) {
+        # An unsupported standalone option.
+    } else {
+        # Some non-option argument has been given.
+        # Stop parsing options at this point.
+        push @commandLine, $arg;
+        $parsingOptions = 0;
+    }
+}
+
+# Was there a partial argument that was never completed?
+push @commandLine, $appendNextArg if ($appendNextArg);
+
+# Call the real Java compiler.
+my @fullCommandLine = ( $javaCompiler, '-C' );
+push @fullCommandLine, $warnings if ($warnings);
+push @fullCommandLine, @commandLine;
+exec @fullCommandLine or exit(1);
--- gcc-6-6.3.0.orig/debian/gcj-wrapper-BV.1
+++ gcc-6-6.3.0/debian/gcj-wrapper-BV.1
@@ -0,0 +1,20 @@
+.TH GCJ-WRAPPER 1 "June 6, 2002" gcj-wrapper "Java User's Manual"
+.SH NAME
+gcj-wrapper \- a wrapper around gcj
+
+.SH SYNOPSIS
+gcj-wrapper [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgcj-wrapper\fR is a wrapper around gcj(1) to be called as the java
+compiler. Options different for javac(1) and gcj(1) are translated,
+options unknown to gcj(1) are silently ignored.
+
+.SH OPTIONS
+See gcj-@BV@(1) for a list of options that gcj understands.
+
+.SH "SEE ALSO"
+.BR gcj-@BV@(1)
+,
+.BR javac(1)
--- gcc-6-6.3.0.orig/debian/gcjh-wrapper-BV
+++ gcc-6-6.3.0/debian/gcjh-wrapper-BV
@@ -0,0 +1,86 @@
+#!/usr/bin/perl -w
+#
+# Starts the GNU Java header generator.
+#
+# Command-line arguments should be in the style of Sun's javah command;
+# these will be converted to gcjh arguments before being passed to the
+# gcjh itself.
+#
+# Copyright (C) 2003 by Peter Hawkins <peterh@debian.org>
+# Haphazardly hacked up based on the gcj-wrapper perl script.
+# Copyright (C) 2002-2003 by Ben Burton <bab@debian.org>
+# Based on the original gcj-wrapper-3.2 shell script.
+
+use strict;
+
+# The real Java header generator:
+my $javaHeaderGen = '/usr/bin/gcjh-@BV@';
+
+# The command-line arguments to pass to the real Java compiler:
+my @commandLine;
+
+# Build the command-line from the arguments given.
+my $parsingOptions = 1;
+my $copyNextArg = 0;
+my $ignoreNextArg = 0;
+my $appendNextArg = '';
+foreach my $arg (@ARGV) {
+    # See if we already know what to do with this argument.
+    if ($ignoreNextArg) {
+        # Throw it away.
+        $ignoreNextArg = 0;
+        next;
+    } elsif ($copyNextArg or not $parsingOptions) {
+        # Copy it directly.
+        push @commandLine, $arg;
+        $copyNextArg = 0;
+        next;
+    } elsif ($appendNextArg) {
+        # Append it to $appendNextArg and then copy directly.
+        push @commandLine, ($appendNextArg . $arg);
+        $appendNextArg = '';
+        next;
+    }
+
+    # Try to interpret Sun-style options.
+    if ($arg eq '-version') {
+        push @commandLine, '--version';
+    } elsif ($arg eq '-h' or $arg eq '-help') {
+        push @commandLine, '--help';
+    } elsif ($arg eq '-verbose') {
+        push @commandLine, '--verbose';
+    } elsif ($arg eq '-classpath' or $arg eq '--classpath' or $arg eq '--cp') {
+        $appendNextArg = '--classpath=';
+    } elsif ($arg eq '-encoding' or $arg eq '-bootclasspath' or
+             $arg eq '-extdirs') {
+        $appendNextArg = "-".$arg . '=';
+    } elsif ($arg eq '-d') {
+        push @commandLine, '-d';
+        $copyNextArg = 1;
+    } elsif ($arg eq '-o') {
+        push @commandLine, '-o';
+        $copyNextArg = 1;
+    } elsif ($arg eq '-stubs') {
+        push @commandLine, '-stubs';
+    } elsif ($arg eq '-jni') {
+        push @commandLine, '-jni';
+    } elsif ($arg =~ /^-old/) {
+        # An extended Sun option (which we don't support).
+        push @commandLine, '--help' if ($arg eq '-old');
+    } elsif ($arg =~ /^-/) {
+        # An unsupported standalone option.
+    } else {
+        # Some non-option argument has been given.
+        # Stop parsing options at this point.
+        push @commandLine, $arg;
+        $parsingOptions = 0;
+    }
+}
+
+# Was there a partial argument that was never completed?
+push @commandLine, $appendNextArg if ($appendNextArg);
+
+# Call the real Java header generator.
+my @fullCommandLine = ( $javaHeaderGen );
+push @fullCommandLine, @commandLine;
+exec @fullCommandLine or exit(1);
--- gcc-6-6.3.0.orig/debian/gcjh-wrapper-BV.1
+++ gcc-6-6.3.0/debian/gcjh-wrapper-BV.1
@@ -0,0 +1,20 @@
+.TH GCJH-WRAPPER 1 "June 6, 2002" gcjh-wrapper "Java User's Manual"
+.SH NAME
+gcjh-wrapper \- a wrapper around gcjh
+
+.SH SYNOPSIS
+gcjh-wrapper [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgcjh-wrapper\fR is a wrapper around gcjh(1) to be called as the java header
+compiler. Options different for javah(1) and gcjh(1) are translated,
+options unknown to gcjh(1) are silently ignored.
+
+.SH OPTIONS
+See gcjh-@BV@(1) for a list of options that gcj understands.
+
+.SH "SEE ALSO"
+.BR gcjh-@BV@(1)
+,
+.BR javah(1)
--- gcc-6-6.3.0.orig/debian/gen-libstdc-breaks.sh
+++ gcc-6-6.3.0/debian/gen-libstdc-breaks.sh
@@ -0,0 +1,178 @@
+#! /bin/sh
+
+# https://bugs.debian.org/cgi-bin/pkgreport.cgi?tag=gcc-pr66145;users=debian-gcc@lists.debian.org
+
+vendor=Debian
+if dpkg-vendor --derives-from Ubuntu; then
+    vendor=Ubuntu
+fi
+
+if [ "$vendor" = Debian ]; then
+    :
+    pkgs=$(echo '
+antlr
+libaqsis1
+libassimp3
+blockattack
+boo
+libboost-date-time1.54.0
+libboost-date-time1.55.0
+libcpprest2.4
+printer-driver-brlaser
+c++-annotations
+clustalx
+libdavix0
+libdballe6
+dff
+libdiet-sed2.8
+libdiet-client2.8
+libdiet-admin2.8
+digikam-private-libs
+emscripten
+ergo
+fceux
+flush
+libfreefem++
+freeorion
+fslview
+fwbuilder
+libgazebo5
+libgetfem4++
+libgmsh2
+gnote
+gnudatalanguage
+python-healpy
+innoextract
+libinsighttoolkit4.7
+libdap17
+libdapclient6
+libdapserver7
+libkolabxml1
+libpqxx-4.0
+libreoffice-core
+librime1
+libwibble-dev
+lightspark
+libmarisa0
+mira-assembler
+mongodb
+mongodb-server
+ncbi-blast+
+libogre-1.8.0
+libogre-1.9.0
+openscad
+libopenwalnut1
+passepartout
+pdf2djvu
+photoprint
+plastimatch
+plee-the-bear
+povray
+powertop
+psi4
+python3-taglib
+realtimebattle
+ruby-passenger
+libapache2-mod-passenger
+schroot
+sqlitebrowser
+tecnoballz
+wesnoth-1.12-core
+widelands
+libwreport2
+xflr5
+libxmltooling6')
+else
+    pkgs=$(echo '
+antlr
+libaqsis1
+libassimp3
+blockattack
+boo
+libboost-date-time1.55.0
+libcpprest2.2
+printer-driver-brlaser
+c++-annotations
+chromium-browser
+clustalx
+libdavix0
+libdballe6
+dff
+libdiet-sed2.8
+libdiet-client2.8
+libdiet-admin2.8
+libkgeomap2
+libmediawiki1
+libkvkontakte1
+emscripten
+ergo
+fceux
+flush
+libfreefem++
+freeorion
+fslview
+fwbuilder
+libgazebo5
+libgetfem4++
+libgmsh2
+gnote
+gnudatalanguage
+python-healpy
+innoextract
+libinsighttoolkit4.6
+libdap17
+libdapclient6
+libdapserver7
+libkolabxml1
+libpqxx-4.0
+libreoffice-core
+librime1
+libwibble-dev
+lightspark
+libmarisa0
+mira-assembler
+mongodb
+mongodb-server
+ncbi-blast+
+libogre-1.8.0
+libogre-1.9.0
+openscad
+libopenwalnut1
+passepartout
+pdf2djvu
+photoprint
+plastimatch
+plee-the-bear
+povray
+powertop
+psi4
+python3-taglib
+realtimebattle
+ruby-passenger
+libapache2-mod-passenger
+sqlitebrowser
+tecnoballz
+wesnoth-1.12-core
+widelands
+libwreport2
+xflr5
+libxmltooling6')
+fi
+
+fn=debian/libstdc++-breaks.$vendor
+rm -f $fn
+echo $pkgs
+for p in $pkgs; do
+    #echo $p
+    if ! apt-cache show --no-all-versions $p >/dev/null; then
+	echo "not found: $p"
+    fi
+    v=$(apt-cache show --no-all-versions $p | awk '/^Version/ {print $2}')
+    case "$p" in
+    libboost-date-time*)
+      echo "$p," >> $fn
+      ;;
+    *)
+      echo "$p (<= $v)," >> $fn
+    esac
+done
--- gcc-6-6.3.0.orig/debian/gfortran-BV-CRB.preinst.in
+++ gcc-6-6.3.0/debian/gfortran-BV-CRB.preinst.in
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-gfortran /usr/bin/@TARGET@-gfortran-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.3.0.orig/debian/gfortran-BV-doc.doc-base
+++ gcc-6-6.3.0/debian/gfortran-BV-doc.doc-base
@@ -0,0 +1,14 @@
+Document: gfortran-@BV@
+Title: The GNU Fortran Compiler 
+Author: Various
+Abstract: This manual documents how to run, install and port `gfortran',
+ as well as its new features and incompatibilities, and how to report bugs.
+Section: Programming/Fortran
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/fortran/gfortran.html
+Files: /usr/share/doc/gcc-@BV@-base/fortran/gfortran.html
+
+Format: info
+Index: /usr/share/info/gfortran-@BV@.info.gz
+Files: /usr/share/info/gfortran-@BV@*
--- gcc-6-6.3.0.orig/debian/gij-hppa
+++ gcc-6-6.3.0/debian/gij-hppa
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+prctl=
+
+case "$(prctl --unaligned=)" in *signal)
+    echo >&2 "$(basename $0): ignore unaligned memory accesses"
+    prctl="prctl --unaligned=default"
+esac
+
+exec $prctl /usr/bin/gij-6.bin "$@"
--- gcc-6-6.3.0.orig/debian/gij-wrapper-BV
+++ gcc-6-6.3.0/debian/gij-wrapper-BV
@@ -0,0 +1,98 @@
+#!/usr/bin/perl -w
+#
+# Starts the GNU Java interpreter.
+#
+# Command-line arguments should be in the style of Sun's Java runtime;
+# these will be converted to gij arguments before being passed to the
+# gij itself.
+#
+# The Debian JNI module directory and any other specified JNI
+# directories will be included on the JNI search path.
+#
+# Copyright (C) 2002-2003 by Ben Burton <bab@debian.org>
+# Based on the original gij-wrapper-3.2 shell script.
+
+use strict;
+
+# The real Java runtime:
+my $javaRuntime = '/usr/bin/gij-@BV@';
+
+# The debian JNI module directory:
+my $debianJNIDir = '/usr/lib/jni';
+
+# The command-line arguments to pass to the real Java runtime:
+my @commandLine;
+
+# The full JNI search path to use:
+my $JNIPath = '';
+
+# Build the command-line from the arguments given.
+my $parsingOptions = 1;
+
+# Flag used to copy argument to -classpath or -cp.
+my $copyNext = 0;
+foreach my $arg (@ARGV) {
+  if (not $parsingOptions) {
+    # We're done parsing options; just copy all remaining arguments directly.
+    push @commandLine, $arg;
+    next;
+  }
+  if ($copyNext) {
+    push @commandLine, $arg;
+    $copyNext = 0;
+    next;
+  }
+
+  # Try to interpret Sun-style options.
+  if ($arg eq '-version') {
+    push @commandLine, '--version';
+  } elsif ($arg eq '-h' or $arg eq '-help') {
+    push @commandLine, '--help';
+  } elsif ($arg eq '-cp' or $arg eq '--cp') {
+    push @commandLine, '-cp';
+    $copyNext = 1;
+  } elsif ($arg eq '-classpath' or $arg eq '--classpath') {
+    push @commandLine, '-classpath';
+    $copyNext = 1;
+  } elsif ($arg =~ /^-Djava.library.path=(.+)$/) {
+    # A component of the JNI search path has been given.
+    if ($JNIPath) {
+      $JNIPath = $JNIPath . ':' . $1;
+    } else {
+      $JNIPath = $1;
+    }
+  } elsif ($arg eq '-jar' or $arg =~ /^-D/) {
+    # Copy the argument directly.
+    push @commandLine, $arg;
+  } elsif ($arg =~ /^-/) {
+    # An unrecognised option has been passed - just drop it.
+  } else {
+    # Some non-option argument has been given.
+    # Stop parsing options at this point.
+    push @commandLine, $arg;
+    $parsingOptions = 0;
+  }
+}
+
+# Add the debian JNI module directory to the JNI search path if it's not
+# already there.
+if ($JNIPath !~ /(^|:)$debianJNIDir($|:)/) {
+  if ($JNIPath) {
+    $JNIPath = $JNIPath . ':' . $debianJNIDir;
+  } else {
+    $JNIPath = $debianJNIDir;
+  }
+}
+
+# Use environment variable $LTDL_LIBRARY_PATH to store the JNI path,
+# since gij uses libltdl to dlopen JNI modules.
+if ($ENV{LTDL_LIBRARY_PATH}) {
+    $ENV{LTDL_LIBRARY_PATH} = $ENV{LTDL_LIBRARY_PATH} . ':' . $JNIPath;
+} else {
+    $ENV{LTDL_LIBRARY_PATH} = $JNIPath;
+}
+
+# Call the real Java runtime.
+my @fullCommandLine = ( $javaRuntime );
+push @fullCommandLine, @commandLine;
+exec @fullCommandLine or exit(1);
--- gcc-6-6.3.0.orig/debian/gij-wrapper-BV.1
+++ gcc-6-6.3.0/debian/gij-wrapper-BV.1
@@ -0,0 +1,22 @@
+.TH GIJ-WRAPPER 1 "August 11, 2001" gij-wrapper "Java User's Manual"
+.SH NAME
+gij-wrapper \- a wrapper around gij
+
+.SH SYNOPSIS
+gij-wrapper [\fB\s-1OPTION\s0\fR] ... \fI\s-1JARFILE\s0\fR [\fI\s-1ARGS\s0\fR...]
+.PP
+gij-wrapper [\fB\-jar\fR] [\fB\s-1OPTION\s0\fR] ... \fI\s-1CLASS\s0\fR [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgij-wrapper\fR is a wrapper around gij(1) to be called as the java
+interpreter. Options different for java(1) and gij(1) are translated,
+options unknown to gij(1) are silently ignored.
+
+.SH OPTIONS
+See gij-@BV@(1) for a list of options that gij understands.
+
+.SH "SEE ALSO"
+.BR gij-@BV@(1)
+,
+.BR java(1)
--- gcc-6-6.3.0.orig/debian/gnat-BV-doc.doc-base.rm
+++ gcc-6-6.3.0/debian/gnat-BV-doc.doc-base.rm
@@ -0,0 +1,16 @@
+Document: gnat-rm-@BV@
+Title: GNAT (GNU Ada) Reference Manual
+Author: Various
+Abstract: This manual contains useful information in writing programs
+ using the GNAT compiler.  It includes information on implementation
+ dependent characteristics of GNAT, including all the information
+ required by Annex M of the standard.
+Section: Programming/Ada
+
+Format: html
+Index: /usr/share/doc/gnat-@BV@-doc/gnat_rm.html
+Files: /usr/share/doc/gnat-@BV@-doc/gnat_rm.html
+
+Format: info
+Index: /usr/share/info/gnat_rm-@BV@.info.gz
+Files: /usr/share/info/gnat_rm-@BV@*
--- gcc-6-6.3.0.orig/debian/gnat-BV-doc.doc-base.style
+++ gcc-6-6.3.0/debian/gnat-BV-doc.doc-base.style
@@ -0,0 +1,16 @@
+Document: gnat-style-@BV@
+Title: GNAT Coding Style
+Author: Various
+Abstract: Most of GNAT is written in Ada using a consistent style to
+ ensure readability of the code.  This document has been written to
+ help maintain this consistent style, while having a large group of
+ developers work on the compiler.
+Section: Programming/Ada
+
+Format: html
+Index: /usr/share/doc/gnat-@BV@-doc/gnat-style.html
+Files: /usr/share/doc/gnat-@BV@-doc/gnat-style.html
+
+Format: info
+Index: /usr/share/info/gnat-style-@BV@.info.gz
+Files: /usr/share/info/gnat-style-@BV@*
--- gcc-6-6.3.0.orig/debian/gnat-BV-doc.doc-base.ug
+++ gcc-6-6.3.0/debian/gnat-BV-doc.doc-base.ug
@@ -0,0 +1,16 @@
+Document: gnat-ugn-@BV@
+Title: GNAT User's Guide for Unix Platforms
+Author: Various
+Abstract: This guide describes the use of GNAT, a compiler and
+ software development toolset for the full Ada 95 programming language.
+ It describes the features of the compiler and tools, and details how
+ to use them to build Ada 95 applications.
+Section: Programming/Ada
+
+Format: html
+Index: /usr/share/doc/gnat-@BV@-doc/gnat_ugn.html
+Files: /usr/share/doc/gnat-@BV@-doc/gnat_ugn.html
+
+Format: info
+Index: /usr/share/info/gnat_ugn-@BV@.info.gz
+Files: /usr/share/info/gnat_ugn-@BV@*
--- gcc-6-6.3.0.orig/debian/gnat-BV.overrides
+++ gcc-6-6.3.0/debian/gnat-BV.overrides
@@ -0,0 +1 @@
+gnat-@BV@ binary: quilt-build-dep-but-no-series-file
--- gcc-6-6.3.0.orig/debian/gnat.1
+++ gcc-6-6.3.0/debian/gnat.1
@@ -0,0 +1,43 @@
+.\" Hey, Emacs!  This is an -*- nroff -*- source file.
+.\"
+.\" Copyright (C) 1996 Erick Branderhorst <branderh@debian.org>
+.\" Copyright (C) 2011 Nicolas Boulenguez <nicolas.boulenguez@free.fr>
+.\"
+.\" This is free software; you can redistribute it and/or modify it under
+.\" the terms of the GNU General Public License as published by the Free
+.\" Software Foundation; either version 2, or (at your option) any later
+.\" version.
+.\"
+.\" This is distributed in the hope that it will be useful, but WITHOUT
+.\" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+.\" FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+.\" for more details.
+.\"
+.\" You should have received a copy of the GNU General Public License with
+.\" your Debian GNU/Linux system, in /usr/doc/copyright/GPL, or with the
+.\" dpkg source package as the file COPYING.  If not, write to the Free
+.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+.\"
+.\"
+.TH "GNAT TOOLBOX" 1 "Jun 2002" "Debian Project" "Debian Linux"
+.SH NAME
+gnat, gnatbind, gnatbl, gnatchop, gnatfind, gnathtml, gnatkr, gnatlink,
+gnatls, gnatmake, gnatprep, gnatpsta, gnatpsys, gnatxref \-
+GNAT toolbox
+.SH DESCRIPTION
+Those programs are part of GNU GNAT, a freely available Ada 95 compiler.
+.PP
+For accessing the full GNAT manuals, use
+.B info gnat-ug-4.8
+and
+.B info gnat-rm-4.8
+for the sections related to the reference manual.
+If those sections cannot be found, you will have to install the
+gnat-4.4-doc package as well (since these manuals contain invariant parts,
+the package is located in the non-free part of the Debian archive).
+You may also browse
+.B http://gcc.gnu.org/onlinedocs
+which provides the GCC online documentation.
+.SH AUTHOR
+This manpage has been written by Samuel Tardieu <sam@debian.org>, for the
+Debian GNU/Linux project.
--- gcc-6-6.3.0.orig/debian/gnatprj.gpr
+++ gcc-6-6.3.0/debian/gnatprj.gpr
@@ -0,0 +1,32 @@
+--  Project file for use with GNAT
+--  Copyright (c) 2005, 2008 Ludovic Brenta <ludovic@ludovic-brenta.org>
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  This project file is designed to help build applications that use
+--  GNAT project files.  Here is an example of how to use this project file:
+--
+--  with "gnatprj";
+--  project Example is
+--     for Object_Dir use "obj";
+--     for Exec_Dir use ".";
+--     for Main use ("example");
+--  end Example;
+
+with "gnatvsn.gpr";
+project Gnatprj is
+   for Library_Name use "gnatprj";
+   for Library_Dir use "/usr/lib";
+   for Library_Kind use "dynamic";
+   for Source_Dirs use ("/usr/share/ada/adainclude/gnatprj");
+   for Library_ALI_Dir use "/usr/lib/ada/adalib/gnatprj";
+   for Externally_Built use "true";
+end Gnatprj;
--- gcc-6-6.3.0.orig/debian/gnatvsn.gpr
+++ gcc-6-6.3.0/debian/gnatvsn.gpr
@@ -0,0 +1,31 @@
+--  Project file for use with GNAT
+--  Copyright (c) 2005, 2008 Ludovic Brenta <ludovic@ludovic-brenta.org>
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  This project file is designed to help build applications that use
+--  GNAT project files.  Here is an example of how to use this project file:
+--
+--  with "gnatvsn";
+--  project Example is
+--     for Object_Dir use "obj";
+--     for Exec_Dir use ".";
+--     for Main use ("example");
+--  end Example;
+
+project Gnatvsn is
+   for Library_Name use "gnatvsn";
+   for Library_Dir use "/usr/lib";
+   for Library_Kind use "dynamic";
+   for Source_Dirs use ("/usr/share/ada/adainclude/gnatvsn");
+   for Library_ALI_Dir use "/usr/lib/ada/adalib/gnatvsn";
+   for Externally_Built use "true";
+end Gnatvsn;
--- gcc-6-6.3.0.orig/debian/go-relocation-test-gcc620-sparc64.obj.uue
+++ gcc-6-6.3.0/debian/go-relocation-test-gcc620-sparc64.obj.uue
@@ -0,0 +1,136 @@
+begin 644 src/libgo/go/debug/elf/testdata/go-relocation-test-gcc620-sparc64.obj
+M?T5,1@("`0`````````````!`"L````!````````````````````````````
+M`!(``````@!```````!``!4`$IWCOU""$``8\G>HA\(GJ'\#````D!!@`$``
+M```!`````0```('/X`@!`````````&AE;&QO+"!W;W)L9`````-"``0`````
+M"`$`````#```````````````````````````````+``````"``````+8````
+M.`,(!P`````#`0@``````P('``````,$!P`````#`08``````P(%``````0$
+M!6EN=``#"`4``````@`````#@P```&D"``````.$````:0,(!P`````%"`8(
+M````E0,!!@`````'````E0@`````V`3Q```"'@D`````!/(```!B``D`````
+M!/<```"/"`D`````!/@```"/$`D`````!/D```"/&`D`````!/H```"/(`D`
+M````!/L```"/*`D`````!/P```"/,`D`````!/T```"/.`D`````!/X```"/
+M0`H`````!`$`````CT@*``````0!`0```(]0"@`````$`0(```"/6`H`````
+M!`$$```"5F`*``````0!!@```EQH"@`````$`0@```!B<`H`````!`$,````
+M8G0*``````0!#@```'!X"@`````$`1(```!&@`H`````!`$3````5((*````
+M``0!%````F*#"@`````$`1@```)RB`H`````!`$A````>Y`*``````0!*0``
+M`(V8"@`````$`2H```"-H`H`````!`$K````C:@*``````0!+````(VP"@``
+M```$`2X````MN`H`````!`$O````8L`*``````0!,0```GC$``L`````!)8(
+M`````!@$G````E8)``````2=```"5@`)``````2>```"7`@)``````2B````
+M8A``!@@```(E!@@```"A#````)4```)R#0```(8```8(```"'@P```"5```"
+MB`T```"&$P`.``````\`````!`$[```"B`\`````!`$\```"B`\`````!`$]
+M```"B`8(````G`<```*Q$``````%J@```EP0``````6K```"7!``````!:P`
+M``)<$``````&&@```&(,```"MP```O,1``<```+H$``````&&P```O,2````
+M``$$````````````````````+`&<```#/Q,``````00```!B`Y&``1,`````
+M`00```,_`Y&(`0`&"````(\``1$!)0X3"P,.&PX1`1('$!<```(6``,..@L[
+M"TD3```#)``+"SX+`PX```0D``L+/@L#"```!0\`"PL```8/``L+21,```<F
+M`$D3```($P$##@L+.@L["P$3```)#0`##CH+.PM)$S@+```*#0`##CH+.P5)
+M$S@+```+%@`##CH+.PL```P!`4D3`1,```TA`$D3+PL```X3``,./!D```\T
+M``,..@L[!4D3/QD\&0``$#0``PXZ"SL+21,_&3P9```1(0```!(N`3\9`PXZ
+M"SL+)QD1`1('0!B60AD!$P``$P4``PXZ"SL+21,"&````````"P``@`````(
+M```````````````````````````L`````````````````````````,\``@``
+M`+8$`?L.#0`!`0$!`````0```2]U<W(O;&EB+V=C8R]S<&%R8S8T+6QI;G5X
+M+6=N=2\V+VEN8VQU9&4`+W5S<B]I;F-L=61E+W-P87)C-C0M;&EN=7@M9VYU
+M+V)I=',`+W5S<B]I;F-L=61E``!H96QL;RYC`````'-T9&1E9BYH``$``'1Y
+M<&5S+F@``@``;&EB:6\N:``#``!S=&1I;RYH``,``'-Y<U]E<G)L:7-T+F@`
+M`@`````)`@``````````%DM+`@,``0%?24]?8G5F7V5N9`!?;VQD7V]F9G-E
+M=`!S>7-?;F5R<@!?24]?<V%V95]E;F0`<VAO<G0@:6YT`'-I>F5?=`!S:7IE
+M='EP90!?;V9F<V5T`%])3U]W<FET95]P='(`7V9L86=S`%])3U]B=69?8F%S
+M90!?;6%R:V5R<P!?24]?<F5A9%]E;F0`<W1D97)R`%]L;V-K`&QO;F<@:6YT
+M`$=.52!#,3$@-BXR+C`@,C`Q-C`Y,30@+6UC<'4]=CD@+6<@+69S=&%C:RUP
+M<F]T96-T;W(M<W1R;VYG`%]C=7)?8V]L=6UN`%])3U\R7S%?<W1D97)R7P!?
+M24]?1DE,15]P;'5S`%]P;W,`87)G=@!?<V)U9@!?24]?1DE,10!U;G-I9VYE
+M9"!C:&%R`&%R9V,`<VEG;F5D(&-H87(`7TE/7S)?,5]S=&1I;E\`=6YS:6=N
+M960@:6YT`%])3U]M87)K97(`7W-H;W)T8G5F`%])3U]W<FET95]B87-E`%]U
+M;G5S960R`%])3U]R96%D7W!T<@!S:&]R="!U;G-I9VYE9"!I;G0`8VAA<@!M
+M86EN`%]N97AT`%]?<&%D,0!?7W!A9#(`7U]P860S`%]?<&%D-`!?7W!A9#4`
+M;&]N9R!U;G-I9VYE9"!I;G0`7TE/7W=R:71E7V5N9`!?7V]F9C8T7W0`7TE/
+M7S)?,5]S=&1O=71?`%]?;V9F7W0`7V-H86EN`%])3U]B86-K=7!?8F%S90!S
+M=&1I;@!?9FQA9W,R`%]M;V1E`%])3U]R96%D7V)A<V4`7W9T86)L95]O9F9S
+M970`7TE/7W-A=F5?8F%S90!S>7-?97)R;&ES=`!?9FEL96YO`&AE;&QO+F,`
+M<W1D;W5T`"]T;7``7TE/7VQO8VM?=```1T-#.B`H1&5B:6%N(#8N,BXP+30K
+M<W!A<F,V-"D@-BXR+C`@,C`Q-C`Y,30`````%/____\!``1X#PP._P\`````
+M````````'``````````````````````````L02T)#Q\-'@``````````````
+M```````````````````````!!`#_\0```````````````````````````P``
+M`0```````````````````````````P```P``````````````````````````
+M`P``!````````````````````````````P``!0``````````````````````
+M`````P``!@```````````````````````````P``"```````````````````
+M`````````P``"0```````````````````````````P``"P``````````````
+M`````````````P``#0```````````````````````````P``#P``````````
+M`````````````````P``$````````````````````````````P``#@``````
+M```````````````````)$@```0```````````````````"P````.$```````
+M````````````````````:&5L;&\N8P!M86EN`'!U=',`````````````````
+M$`````4````)````````````````````%`````4````,````````````````
+M````&`````\````'````````````````````!@````<````7````````````
+M````````#`````H````7`````````)X`````````$0````H````7````````
+M`H0`````````%0````H````7`````````I,`````````&0````(````V````
+M````````````````*0````D````7````````````````````+@````H````7
+M`````````#@`````````.P````H````7`````````=@`````````0@````H`
+M```7`````````1T`````````20````H````7`````````9(`````````4```
+M``H````7`````````4L`````````5P````H````7`````````3``````````
+M7@````H````7`````````"X`````````;`````H````7`````````)4`````
+M````<0````H````7`````````A(`````````?`````H````7`````````?@`
+M````````B0````H````7`````````#\`````````F`````H````7````````
+M`:4`````````H@````H````7`````````10`````````K@````H````7````
+M`````%X`````````N@````H````7`````````84`````````Q@````H````7
+M`````````'L`````````T@````H````7`````````D4`````````W@````H`
+M```7`````````6T`````````Z@````H````7`````````%``````````]@``
+M``H````7`````````>H````````!`@````H````7`````````&4````````!
+M#@````H````7```````````````````!&@````H````7`````````F(`````
+M```!)P````H````7`````````B$````````!-`````H````7`````````"$`
+M```````!00````H````7`````````'(````````!3@````H````7````````
+M`AH````````!6P````H````7`````````GP````````!:`````H````7````
+M`````C<````````!=0````H````7``````````P````````!@@````H````7
+M`````````-H````````!CP````H````7`````````E,````````!G`````H`
+M```7`````````6,````````!J0````H````7`````````(\````````!M@``
+M``H````7`````````$@````````!PP````H````7`````````;4````````!
+MT`````H````7`````````;P````````!W0````H````7`````````<,`````
+M```!Z@````H````7`````````<H````````!]P````H````7`````````=$`
+M```````"!`````H````7`````````C\````````"$0````H````7````````
+M`7P````````"'P````H````7`````````I@````````")@````H````7````
+M`````5@````````",@````H````7`````````:\````````"/@````H````7
+M`````````0X````````"2@````H````7`````````00````````"B0````H`
+M```7`````````/8````````"C@````H````7`````````3P````````"F@``
+M``H````7`````````@(````````"I@````H````7`````````.8````````"
+MO0````H````7`````````C$````````"R`````H````7`````````HP`````
+M```"TP````H````7`````````(@````````"W@````H````7`````````!@`
+M```````"^0````H````7`````````G`````````#!`````H````7````````
+M`:H````````#"@````(````V```````````````````#(0````H````7````
+M`````2L````````#,`````H````7`````````0D`````````!@````8````7
+M````````````````````$`````(````V````````````````````PP````(`
+M```V````````````````````'`````P````7````````````````````(```
+M``(````V````````````+G-Y;71A8@`N<W1R=&%B`"YS:'-T<G1A8@`N<F5L
+M82YT97AT`"YD871A`"YB<W,`+G)O9&%T80`N<F5L82YD96)U9U]I;F9O`"YD
+M96)U9U]A8F)R978`+G)E;&$N9&5B=6=?87)A;F=E<P`N<F5L82YD96)U9U]L
+M:6YE`"YD96)U9U]S='(`+F-O;6UE;G0`+FYO=&4N1TY5+7-T86-K`"YR96QA
+M+F1E8G5G7V9R86UE````````````````````````````````````````````
+M`````````````````````````````````````````````````````"`````!
+M``````````8```````````````````!``````````"P`````````````````
+M```$```````````````;````!`````````!````````````````````*6```
+M``````!(````$P````$`````````"``````````8````)@````$`````````
+M`P```````````````````&P```````````````````````````````$`````
+M`````````"P````(``````````,```````````````````!L````````````
+M```````````````````!```````````````Q`````0`````````"````````
+M````````````<``````````-````````````````````"```````````````
+M/@````$``````````````````````````````'T````````#1@``````````
+M``````````$``````````````#D````$`````````$``````````````````
+M``J@````````!C`````3````!@`````````(`````````!@```!*`````0``
+M```````````````````````````#PP````````#Q````````````````````
+M`0``````````````70````$`````````````````````````````!+0`````
+M````,`````````````````````$``````````````%@````$`````````$``
+M`````````````````!#0`````````#`````3````"0`````````(````````
+M`!@```!Q`````0`````````````````````````````$Y`````````#3````
+M`````````````````0``````````````;`````0`````````0```````````
+M````````$0``````````&````!,````+``````````@`````````&````'T`
+M```!`````````#````````````````````6W`````````J,`````````````
+M```````!``````````$```"(`````0`````````P```````````````````(
+M6@`````````N`````````````````````0`````````!````D0````$`````
+M````````````````````````"(@```````````````````````````````$`
+M`````````````*8````!``````````````````````````````B(````````
+M`#@````````````````````(``````````````"A````!`````````!`````
+M```````````````1&``````````P````$P```!``````````"``````````8
+M````$0````,`````````````````````````````$4@`````````LP``````
+M``````````````$```````````````$````"````````````````````````
+M``````C``````````8`````4````#@`````````(`````````!@````)````
+M`P`````````````````````````````*0``````````3````````````````
+,`````0``````````
+`
+end
--- gcc-6-6.3.0.orig/debian/jdb.sh
+++ gcc-6-6.3.0/debian/jdb.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+# Placeholder script to fake a
+# JDK compatible JAVA_HOME directory.
+
+echo >&2 "This script is only a placeholder."
+echo >&2 "Some programs need a JDK rather than only a JRE to work."
+echo >&2 "They test for this tool to detect a JDK installation, but"
+echo >&2 "don't really need its functionality to work correctly."
--- gcc-6-6.3.0.orig/debian/lib32asan3.overrides
+++ gcc-6-6.3.0/debian/lib32asan3.overrides
@@ -0,0 +1,2 @@
+# automake gets it wrong for the multilib build
+lib32asan3 binary: binary-or-shlib-defines-rpath
--- gcc-6-6.3.0.orig/debian/lib32asan3.symbols
+++ gcc-6-6.3.0/debian/lib32asan3.symbols
@@ -0,0 +1,3 @@
+libasan.so.3 lib32asan3 #MINVER#
+#include "libasan.symbols.common"
+#include "libasan.symbols.32"
--- gcc-6-6.3.0.orig/debian/lib32gccLC.postinst
+++ gcc-6-6.3.0/debian/lib32gccLC.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib32gcc@LC@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/lib32gphobos68.lintian-overrides
+++ gcc-6-6.3.0/debian/lib32gphobos68.lintian-overrides
@@ -0,0 +1,2 @@
+# no usable zconf.h header in lib32z1-dev
+lib32gphobos68 binary: embedded-library
--- gcc-6-6.3.0.orig/debian/lib32stdc++6.symbols.amd64
+++ gcc-6-6.3.0/debian/lib32stdc++6.symbols.amd64
@@ -0,0 +1,14 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.3.0.orig/debian/lib32stdc++6.symbols.kfreebsd-amd64
+++ gcc-6-6.3.0/debian/lib32stdc++6.symbols.kfreebsd-amd64
@@ -0,0 +1,7 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.3.0.orig/debian/lib32stdc++6.symbols.ppc64
+++ gcc-6-6.3.0/debian/lib32stdc++6.symbols.ppc64
@@ -0,0 +1,9 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/lib32stdc++6.symbols.s390x
+++ gcc-6-6.3.0/debian/lib32stdc++6.symbols.s390x
@@ -0,0 +1,558 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.f128"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcmPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwmPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5.0
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5.0
+ _ZNSbIwSt11char_traitsIwESaIwEE10_S_compareEmm@GLIBCXX_3.4.16 4.7
+ _ZNKSt8valarrayImE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructEmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE14_M_replace_auxEmmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE15_M_replace_safeEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE18_S_construct_aux_2EmwRKS1_@GLIBCXX_3.4.14 4.5.0
+ _ZNSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep8_M_cloneERKS1_m@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep9_S_createEmmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEmm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_mw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7reserveEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwmw@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_mutateEmmm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EPKwmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_mmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EPKwmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_mmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi4readEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSi6ignoreEii@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi8readsomeEPci@GLIBCXX_3.4 4.1.1
+ _ZNSo5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSo5writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSo8_M_writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSs10_S_compareEmm@GLIBCXX_3.4.16 4.7
+ _ZNSs12_S_constructEmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs14_M_replace_auxEmmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs15_M_replace_safeEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs18_S_construct_aux_2EmcRKSaIcE@GLIBCXX_3.4.14 4.5.0
+ _ZNSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs4_Rep8_M_cloneERKSaIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep9_S_createEmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs5eraseEmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEm@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7_M_moveEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_moveEPcPKcm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_mc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs7reserveEm@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcmc@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcmc@GLIBCXX_3.4.5 4.1.1
+ _ZNSs9_M_mutateEmmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EPKcmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EPKcmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EPSt17__timepunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EPSt17__timepunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EPSt17__timepunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EPSt17__timepunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE7seekoffExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE8xsputn_2EPKciS2_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_allocEm@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_setupEPcS0_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPFPvmEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPFPvmEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE22_M_convert_to_externalEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4readEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEij@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE8readsomeEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE8_M_writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_gbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_pbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9pubsetbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_gbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_pbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9pubsetbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE8_M_pbumpEPcS4_x@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS4_x@GLIBCXX_3.4.16 4.7
+ _ZNSt15messages_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC1EmRKSt8valarrayImES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC2EmRKSt8valarrayImES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl16_M_install_cacheEPKNS_5facetEm@GLIBCXX_3.4.7 4.1.1
+ _ZNSt6locale5_ImplC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1ERKS0_m@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2ERKS0_m@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC1ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC2ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEixEm@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZSt11_Hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt15_Fnv_hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt17__copy_streambufsIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__copy_streambufsIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__verify_groupingPKcmRKSs@GLIBCXX_3.4.10 4.3
+ _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZThn8_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _Znam@GLIBCXX_3.4 4.1.1
+ _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwm@GLIBCXX_3.4 4.1.1
+ _ZnwmRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit.s390"
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.3.0.orig/debian/lib32stdc++6.symbols.sparc64
+++ gcc-6-6.3.0/debian/lib32stdc++6.symbols.sparc64
@@ -0,0 +1,9 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/lib32stdc++CXX.postinst
+++ gcc-6-6.3.0/debian/lib32stdc++CXX.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib32stdc++@CXX@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/lib64asan3.overrides
+++ gcc-6-6.3.0/debian/lib64asan3.overrides
@@ -0,0 +1,2 @@
+# automake gets it wrong for the multilib build
+lib64asan3 binary: binary-or-shlib-defines-rpath
--- gcc-6-6.3.0.orig/debian/lib64asan3.symbols
+++ gcc-6-6.3.0/debian/lib64asan3.symbols
@@ -0,0 +1,3 @@
+libasan.so.3 lib64asan3 #MINVER#
+#include "libasan.symbols.common"
+#include "libasan.symbols.64"
--- gcc-6-6.3.0.orig/debian/lib64gccLC.postinst
+++ gcc-6-6.3.0/debian/lib64gccLC.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib64gcc@LC@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/lib64gphobos68.lintian-overrides
+++ gcc-6-6.3.0/debian/lib64gphobos68.lintian-overrides
@@ -0,0 +1,2 @@
+# no usable zconf.h header in lib64z1-dev
+lib64gphobos68 binary: embedded-library
--- gcc-6-6.3.0.orig/debian/lib64stdc++6.symbols.i386
+++ gcc-6-6.3.0/debian/lib64stdc++6.symbols.i386
@@ -0,0 +1,40 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# acosl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# asinl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# atan2l@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# atanl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# ceill@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# coshl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# cosl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# expl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# floorl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# fmodl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# frexpl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# hypotl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# log10l@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# logl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# modfl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# powl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# sinhl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# sinl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# sqrtl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# tanhl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# tanl@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvmS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvmS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.3.0.orig/debian/lib64stdc++6.symbols.powerpc
+++ gcc-6-6.3.0/debian/lib64stdc++6.symbols.powerpc
@@ -0,0 +1,11 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.f128"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/lib64stdc++6.symbols.s390
+++ gcc-6-6.3.0/debian/lib64stdc++6.symbols.s390
@@ -0,0 +1,12 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/lib64stdc++6.symbols.sparc
+++ gcc-6-6.3.0/debian/lib64stdc++6.symbols.sparc
@@ -0,0 +1,11 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1
+# FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc.
+# #include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.3.0.orig/debian/lib64stdc++CXX.postinst
+++ gcc-6-6.3.0/debian/lib64stdc++CXX.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib64stdc++@CXX@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libasan.symbols.16
+++ gcc-6-6.3.0/debian/libasan.symbols.16
@@ -0,0 +1,38 @@
+ __sanitizer_syscall_post_impl_chown16@Base 5
+ __sanitizer_syscall_post_impl_fchown16@Base 5
+ __sanitizer_syscall_post_impl_getegid16@Base 5
+ __sanitizer_syscall_post_impl_geteuid16@Base 5
+ __sanitizer_syscall_post_impl_getgid16@Base 5
+ __sanitizer_syscall_post_impl_getgroups16@Base 5
+ __sanitizer_syscall_post_impl_getresgid16@Base 5
+ __sanitizer_syscall_post_impl_getresuid16@Base 5
+ __sanitizer_syscall_post_impl_getuid16@Base 5
+ __sanitizer_syscall_post_impl_lchown16@Base 5
+ __sanitizer_syscall_post_impl_setfsgid16@Base 5
+ __sanitizer_syscall_post_impl_setfsuid16@Base 5
+ __sanitizer_syscall_post_impl_setgid16@Base 5
+ __sanitizer_syscall_post_impl_setgroups16@Base 5
+ __sanitizer_syscall_post_impl_setregid16@Base 5
+ __sanitizer_syscall_post_impl_setresgid16@Base 5
+ __sanitizer_syscall_post_impl_setresuid16@Base 5
+ __sanitizer_syscall_post_impl_setreuid16@Base 5
+ __sanitizer_syscall_post_impl_setuid16@Base 5
+ __sanitizer_syscall_pre_impl_chown16@Base 5
+ __sanitizer_syscall_pre_impl_fchown16@Base 5
+ __sanitizer_syscall_pre_impl_getegid16@Base 5
+ __sanitizer_syscall_pre_impl_geteuid16@Base 5
+ __sanitizer_syscall_pre_impl_getgid16@Base 5
+ __sanitizer_syscall_pre_impl_getgroups16@Base 5
+ __sanitizer_syscall_pre_impl_getresgid16@Base 5
+ __sanitizer_syscall_pre_impl_getresuid16@Base 5
+ __sanitizer_syscall_pre_impl_getuid16@Base 5
+ __sanitizer_syscall_pre_impl_lchown16@Base 5
+ __sanitizer_syscall_pre_impl_setfsgid16@Base 5
+ __sanitizer_syscall_pre_impl_setfsuid16@Base 5
+ __sanitizer_syscall_pre_impl_setgid16@Base 5
+ __sanitizer_syscall_pre_impl_setgroups16@Base 5
+ __sanitizer_syscall_pre_impl_setregid16@Base 5
+ __sanitizer_syscall_pre_impl_setresgid16@Base 5
+ __sanitizer_syscall_pre_impl_setresuid16@Base 5
+ __sanitizer_syscall_pre_impl_setreuid16@Base 5
+ __sanitizer_syscall_pre_impl_setuid16@Base 5
--- gcc-6-6.3.0.orig/debian/libasan.symbols.32
+++ gcc-6-6.3.0/debian/libasan.symbols.32
@@ -0,0 +1,6 @@
+ _ZdaPvj@Base 5
+ _ZdlPvj@Base 5
+ _Znaj@Base 4.8
+ _ZnajRKSt9nothrow_t@Base 4.8
+ _Znwj@Base 4.8
+ _ZnwjRKSt9nothrow_t@Base 4.8
--- gcc-6-6.3.0.orig/debian/libasan.symbols.64
+++ gcc-6-6.3.0/debian/libasan.symbols.64
@@ -0,0 +1,8 @@
+ __interceptor_shmctl@Base 4.9
+ _ZdaPvm@Base 5
+ _ZdlPvm@Base 5
+ _Znam@Base 4.8
+ _ZnamRKSt9nothrow_t@Base 4.8
+ _Znwm@Base 4.8
+ _ZnwmRKSt9nothrow_t@Base 4.8
+ shmctl@Base 4.9
--- gcc-6-6.3.0.orig/debian/libasan.symbols.common
+++ gcc-6-6.3.0/debian/libasan.symbols.common
@@ -0,0 +1,1600 @@
+ _ZN11__sanitizer11CheckFailedEPKciS1_yy@Base 4.8
+ _ZN11__sanitizer7OnPrintEPKc@Base 4.9
+ _ZdaPv@Base 4.8
+ _ZdaPvRKSt9nothrow_t@Base 4.8
+ _ZdlPv@Base 4.8
+ _ZdlPvRKSt9nothrow_t@Base 4.8
+ __asan_addr_is_in_fake_stack@Base 5
+ __asan_address_is_poisoned@Base 4.8
+ __asan_after_dynamic_init@Base 4.8
+ __asan_alloca_poison@Base 6.2
+ __asan_allocas_unpoison@Base 6.2
+ __asan_backtrace_alloc@Base 4.9
+ __asan_backtrace_close@Base 4.9
+ __asan_backtrace_create_state@Base 4.9
+ __asan_backtrace_dwarf_add@Base 4.9
+ __asan_backtrace_free@Base 4.9
+ __asan_backtrace_get_view@Base 4.9
+ __asan_backtrace_initialize@Base 4.9
+ __asan_backtrace_open@Base 4.9
+ __asan_backtrace_pcinfo@Base 4.9
+ __asan_backtrace_qsort@Base 4.9
+ __asan_backtrace_release_view@Base 4.9
+ __asan_backtrace_syminfo@Base 4.9
+ __asan_backtrace_vector_finish@Base 4.9
+ __asan_backtrace_vector_grow@Base 4.9
+ __asan_backtrace_vector_release@Base 4.9
+ __asan_before_dynamic_init@Base 4.8
+ __asan_cplus_demangle_builtin_types@Base 4.9
+ __asan_cplus_demangle_fill_ctor@Base 4.9
+ __asan_cplus_demangle_fill_dtor@Base 4.9
+ __asan_cplus_demangle_fill_extended_operator@Base 4.9
+ __asan_cplus_demangle_fill_name@Base 4.9
+ __asan_cplus_demangle_init_info@Base 4.9
+ __asan_cplus_demangle_mangled_name@Base 4.9
+ __asan_cplus_demangle_operators@Base 4.9
+ __asan_cplus_demangle_print@Base 4.9
+ __asan_cplus_demangle_print_callback@Base 4.9
+ __asan_cplus_demangle_type@Base 4.9
+ __asan_cplus_demangle_v3@Base 4.9
+ __asan_cplus_demangle_v3_callback@Base 4.9
+ __asan_describe_address@Base 4.8
+ __asan_exp_load16@Base 6.2
+ __asan_exp_load1@Base 6.2
+ __asan_exp_load2@Base 6.2
+ __asan_exp_load4@Base 6.2
+ __asan_exp_load8@Base 6.2
+ __asan_exp_loadN@Base 6.2
+ __asan_exp_store16@Base 6.2
+ __asan_exp_store1@Base 6.2
+ __asan_exp_store2@Base 6.2
+ __asan_exp_store4@Base 6.2
+ __asan_exp_store8@Base 6.2
+ __asan_exp_storeN@Base 6.2
+ __asan_get_alloc_stack@Base 5
+ __asan_get_current_fake_stack@Base 5
+ __asan_get_free_stack@Base 5
+ __asan_get_report_access_size@Base 5
+ __asan_get_report_access_type@Base 5
+ __asan_get_report_address@Base 5
+ __asan_get_report_bp@Base 5
+ __asan_get_report_description@Base 5
+ __asan_get_report_pc@Base 5
+ __asan_get_report_sp@Base 5
+ __asan_get_shadow_mapping@Base 5
+ __asan_handle_no_return@Base 4.8
+ __asan_init@Base 6.2
+ __asan_internal_memcmp@Base 4.9
+ __asan_internal_memcpy@Base 4.9
+ __asan_internal_memset@Base 4.9
+ __asan_internal_strcmp@Base 4.9
+ __asan_internal_strlen@Base 4.9
+ __asan_internal_strncmp@Base 4.9
+ __asan_internal_strnlen@Base 4.9
+ __asan_is_gnu_v3_mangled_ctor@Base 4.9
+ __asan_is_gnu_v3_mangled_dtor@Base 4.9
+ __asan_java_demangle_v3@Base 4.9
+ __asan_java_demangle_v3_callback@Base 4.9
+ __asan_load16@Base 5
+ __asan_load16_noabort@Base 6.2
+ __asan_load1@Base 5
+ __asan_load1_noabort@Base 6.2
+ __asan_load2@Base 5
+ __asan_load2_noabort@Base 6.2
+ __asan_load4@Base 5
+ __asan_load4_noabort@Base 6.2
+ __asan_load8@Base 5
+ __asan_load8_noabort@Base 6.2
+ __asan_loadN@Base 5
+ __asan_loadN_noabort@Base 6.2
+ __asan_load_cxx_array_cookie@Base 5
+ __asan_locate_address@Base 5
+ __asan_memcpy@Base 5
+ __asan_memmove@Base 5
+ __asan_memset@Base 5
+ __asan_option_detect_stack_use_after_return@Base 4.9
+ __asan_poison_cxx_array_cookie@Base 5
+ __asan_poison_intra_object_redzone@Base 5
+ __asan_poison_memory_region@Base 4.8
+ __asan_poison_stack_memory@Base 4.8
+ __asan_print_accumulated_stats@Base 4.8
+ __asan_region_is_poisoned@Base 4.8
+ __asan_register_globals@Base 4.8
+ __asan_report_error@Base 4.8
+ __asan_report_exp_load16@Base 6.2
+ __asan_report_exp_load1@Base 6.2
+ __asan_report_exp_load2@Base 6.2
+ __asan_report_exp_load4@Base 6.2
+ __asan_report_exp_load8@Base 6.2
+ __asan_report_exp_load_n@Base 6.2
+ __asan_report_exp_store16@Base 6.2
+ __asan_report_exp_store1@Base 6.2
+ __asan_report_exp_store2@Base 6.2
+ __asan_report_exp_store4@Base 6.2
+ __asan_report_exp_store8@Base 6.2
+ __asan_report_exp_store_n@Base 6.2
+ __asan_report_load16@Base 4.8
+ __asan_report_load16_noabort@Base 6.2
+ __asan_report_load1@Base 4.8
+ __asan_report_load1_noabort@Base 6.2
+ __asan_report_load2@Base 4.8
+ __asan_report_load2_noabort@Base 6.2
+ __asan_report_load4@Base 4.8
+ __asan_report_load4_noabort@Base 6.2
+ __asan_report_load8@Base 4.8
+ __asan_report_load8_noabort@Base 6.2
+ __asan_report_load_n@Base 4.8
+ __asan_report_load_n_noabort@Base 6.2
+ __asan_report_present@Base 5
+ __asan_report_store16@Base 4.8
+ __asan_report_store16_noabort@Base 6.2
+ __asan_report_store1@Base 4.8
+ __asan_report_store1_noabort@Base 6.2
+ __asan_report_store2@Base 4.8
+ __asan_report_store2_noabort@Base 6.2
+ __asan_report_store4@Base 4.8
+ __asan_report_store4_noabort@Base 6.2
+ __asan_report_store8@Base 4.8
+ __asan_report_store8_noabort@Base 6.2
+ __asan_report_store_n@Base 4.8
+ __asan_report_store_n_noabort@Base 6.2
+ __asan_rt_version@Base 5
+ __asan_set_death_callback@Base 4.8
+ __asan_set_error_report_callback@Base 4.8
+ __asan_stack_free_0@Base 4.9
+ __asan_stack_free_10@Base 4.9
+ __asan_stack_free_1@Base 4.9
+ __asan_stack_free_2@Base 4.9
+ __asan_stack_free_3@Base 4.9
+ __asan_stack_free_4@Base 4.9
+ __asan_stack_free_5@Base 4.9
+ __asan_stack_free_6@Base 4.9
+ __asan_stack_free_7@Base 4.9
+ __asan_stack_free_8@Base 4.9
+ __asan_stack_free_9@Base 4.9
+ __asan_stack_malloc_0@Base 4.9
+ __asan_stack_malloc_10@Base 4.9
+ __asan_stack_malloc_1@Base 4.9
+ __asan_stack_malloc_2@Base 4.9
+ __asan_stack_malloc_3@Base 4.9
+ __asan_stack_malloc_4@Base 4.9
+ __asan_stack_malloc_5@Base 4.9
+ __asan_stack_malloc_6@Base 4.9
+ __asan_stack_malloc_7@Base 4.9
+ __asan_stack_malloc_8@Base 4.9
+ __asan_stack_malloc_9@Base 4.9
+ __asan_store16@Base 5
+ __asan_store16_noabort@Base 6.2
+ __asan_store1@Base 5
+ __asan_store1_noabort@Base 6.2
+ __asan_store2@Base 5
+ __asan_store2_noabort@Base 6.2
+ __asan_store4@Base 5
+ __asan_store4_noabort@Base 6.2
+ __asan_store8@Base 5
+ __asan_store8_noabort@Base 6.2
+ __asan_storeN@Base 5
+ __asan_storeN_noabort@Base 6.2
+ __asan_test_only_reported_buggy_pointer@Base 5
+ __asan_unpoison_intra_object_redzone@Base 5
+ __asan_unpoison_memory_region@Base 4.8
+ __asan_unpoison_stack_memory@Base 4.8
+ __asan_unregister_globals@Base 4.8
+ __asan_version_mismatch_check_v6@Base 6.2
+ __cxa_atexit@Base 4.9
+ __cxa_throw@Base 4.8
+ __getdelim@Base 5
+ __interceptor___cxa_atexit@Base 4.9
+ __interceptor___cxa_throw@Base 4.8
+ __interceptor___getdelim@Base 5
+ __interceptor___isoc99_fprintf@Base 5
+ __interceptor___isoc99_fscanf@Base 4.8
+ __interceptor___isoc99_printf@Base 5
+ __interceptor___isoc99_scanf@Base 4.8
+ __interceptor___isoc99_snprintf@Base 5
+ __interceptor___isoc99_sprintf@Base 5
+ __interceptor___isoc99_sscanf@Base 4.8
+ __interceptor___isoc99_vfprintf@Base 5
+ __interceptor___isoc99_vfscanf@Base 4.8
+ __interceptor___isoc99_vprintf@Base 5
+ __interceptor___isoc99_vscanf@Base 4.8
+ __interceptor___isoc99_vsnprintf@Base 5
+ __interceptor___isoc99_vsprintf@Base 5
+ __interceptor___isoc99_vsscanf@Base 4.8
+ __interceptor___libc_memalign@Base 4.8
+ __interceptor___overflow@Base 5
+ __interceptor___tls_get_addr@Base 5
+ __interceptor___uflow@Base 5
+ __interceptor___underflow@Base 5
+ __interceptor___woverflow@Base 5
+ __interceptor___wuflow@Base 5
+ __interceptor___wunderflow@Base 5
+ __interceptor___xpg_strerror_r@Base 4.9
+ __interceptor__exit@Base 4.9
+ __interceptor__longjmp@Base 4.8
+ __interceptor__obstack_begin@Base 5
+ __interceptor__obstack_begin_1@Base 5
+ __interceptor__obstack_newchunk@Base 5
+ __interceptor_accept4@Base 4.9
+ __interceptor_accept@Base 4.9
+ __interceptor_aligned_alloc@Base 5
+ __interceptor_asctime@Base 4.8
+ __interceptor_asctime_r@Base 4.8
+ __interceptor_asprintf@Base 5
+ __interceptor_atoi@Base 4.8
+ __interceptor_atol@Base 4.8
+ __interceptor_atoll@Base 4.8
+ __interceptor_backtrace@Base 4.9
+ __interceptor_backtrace_symbols@Base 4.9
+ __interceptor_calloc@Base 4.8
+ __interceptor_canonicalize_file_name@Base 4.9
+ __interceptor_capget@Base 5
+ __interceptor_capset@Base 5
+ __interceptor_cfree@Base 4.8
+ __interceptor_clock_getres@Base 4.9
+ __interceptor_clock_gettime@Base 4.9
+ __interceptor_clock_settime@Base 4.9
+ __interceptor_confstr@Base 4.9
+ __interceptor_ctime@Base 4.8
+ __interceptor_ctime_r@Base 4.8
+ __interceptor_dlclose@Base 5
+ __interceptor_dlopen@Base 5
+ __interceptor_drand48_r@Base 4.9
+ __interceptor_endgrent@Base 5
+ __interceptor_endpwent@Base 5
+ __interceptor_ether_aton@Base 4.9
+ __interceptor_ether_aton_r@Base 4.9
+ __interceptor_ether_hostton@Base 4.9
+ __interceptor_ether_line@Base 4.9
+ __interceptor_ether_ntoa@Base 4.9
+ __interceptor_ether_ntoa_r@Base 4.9
+ __interceptor_ether_ntohost@Base 4.9
+ __interceptor_fclose@Base 5
+ __interceptor_fdopen@Base 5
+ __interceptor_fflush@Base 5
+ __interceptor_fgetgrent@Base 5
+ __interceptor_fgetgrent_r@Base 5
+ __interceptor_fgetpwent@Base 5
+ __interceptor_fgetpwent_r@Base 5
+ __interceptor_fgetxattr@Base 5
+ __interceptor_flistxattr@Base 5
+ __interceptor_fmemopen@Base 5
+ __interceptor_fopen64@Base 5
+ __interceptor_fopen@Base 5
+ __interceptor_fopencookie@Base 6.2
+ __interceptor_fork@Base 5
+ __interceptor_fprintf@Base 5
+ __interceptor_free@Base 4.8
+ __interceptor_freopen64@Base 5
+ __interceptor_freopen@Base 5
+ __interceptor_frexp@Base 4.9
+ __interceptor_frexpf@Base 4.9
+ __interceptor_frexpl@Base 4.9
+ __interceptor_fscanf@Base 4.8
+ __interceptor_fstatfs64@Base 4.9
+ __interceptor_fstatfs@Base 4.9
+ __interceptor_fstatvfs64@Base 4.9
+ __interceptor_fstatvfs@Base 4.9
+ __interceptor_ftime@Base 5
+ __interceptor_get_current_dir_name@Base 4.9
+ __interceptor_getaddrinfo@Base 4.9
+ __interceptor_getcwd@Base 4.9
+ __interceptor_getdelim@Base 4.9
+ __interceptor_getgrent@Base 5
+ __interceptor_getgrent_r@Base 5
+ __interceptor_getgrgid@Base 4.9
+ __interceptor_getgrgid_r@Base 4.9
+ __interceptor_getgrnam@Base 4.9
+ __interceptor_getgrnam_r@Base 4.9
+ __interceptor_getgroups@Base 4.9
+ __interceptor_gethostbyaddr@Base 4.9
+ __interceptor_gethostbyaddr_r@Base 4.9
+ __interceptor_gethostbyname2@Base 4.9
+ __interceptor_gethostbyname2_r@Base 4.9
+ __interceptor_gethostbyname@Base 4.9
+ __interceptor_gethostbyname_r@Base 4.9
+ __interceptor_gethostent@Base 4.9
+ __interceptor_gethostent_r@Base 4.9
+ __interceptor_getifaddrs@Base 5
+ __interceptor_getitimer@Base 4.9
+ __interceptor_getline@Base 4.9
+ __interceptor_getmntent@Base 4.9
+ __interceptor_getmntent_r@Base 4.9
+ __interceptor_getnameinfo@Base 4.9
+ __interceptor_getpass@Base 5
+ __interceptor_getpeername@Base 4.9
+ __interceptor_getpwent@Base 5
+ __interceptor_getpwent_r@Base 5
+ __interceptor_getpwnam@Base 4.9
+ __interceptor_getpwnam_r@Base 4.9
+ __interceptor_getpwuid@Base 4.9
+ __interceptor_getpwuid_r@Base 4.9
+ __interceptor_getresgid@Base 5
+ __interceptor_getresuid@Base 5
+ __interceptor_getsockname@Base 4.9
+ __interceptor_getsockopt@Base 4.9
+ __interceptor_getxattr@Base 5
+ __interceptor_glob64@Base 4.9
+ __interceptor_glob@Base 4.9
+ __interceptor_gmtime@Base 4.8
+ __interceptor_gmtime_r@Base 4.8
+ __interceptor_iconv@Base 4.9
+ __interceptor_if_indextoname@Base 5
+ __interceptor_if_nametoindex@Base 5
+ __interceptor_index@Base 4.8
+ __interceptor_inet_aton@Base 4.9
+ __interceptor_inet_ntop@Base 4.9
+ __interceptor_inet_pton@Base 4.9
+ __interceptor_initgroups@Base 4.9
+ __interceptor_ioctl@Base 4.9
+ __interceptor_lgamma@Base 4.9
+ __interceptor_lgamma_r@Base 4.9
+ __interceptor_lgammaf@Base 4.9
+ __interceptor_lgammaf_r@Base 4.9
+ __interceptor_lgammal@Base 4.9
+ __interceptor_lgammal_r@Base 4.9
+ __interceptor_lgetxattr@Base 5
+ __interceptor_listxattr@Base 5
+ __interceptor_llistxattr@Base 5
+ __interceptor_localtime@Base 4.8
+ __interceptor_localtime_r@Base 4.8
+ __interceptor_longjmp@Base 4.8
+ __interceptor_lrand48_r@Base 4.9
+ __interceptor_mallinfo@Base 4.8
+ __interceptor_malloc@Base 4.8
+ __interceptor_malloc_stats@Base 4.8
+ __interceptor_malloc_usable_size@Base 4.8
+ __interceptor_mallopt@Base 4.8
+ __interceptor_mbsnrtowcs@Base 4.9
+ __interceptor_mbsrtowcs@Base 4.9
+ __interceptor_mbstowcs@Base 4.9
+ __interceptor_memalign@Base 4.8
+ __interceptor_memchr@Base 5
+ __interceptor_memcmp@Base 4.8
+ __interceptor_memcpy@Base 4.8
+ __interceptor_memmove@Base 4.8
+ __interceptor_memrchr@Base 5
+ __interceptor_memset@Base 4.8
+ __interceptor_mincore@Base 6.2
+ __interceptor_mktime@Base 5
+ __interceptor_mlock@Base 4.8
+ __interceptor_mlockall@Base 4.8
+ __interceptor_modf@Base 4.9
+ __interceptor_modff@Base 4.9
+ __interceptor_modfl@Base 4.9
+ __interceptor_munlock@Base 4.8
+ __interceptor_munlockall@Base 4.8
+ __interceptor_open_memstream@Base 5
+ __interceptor_open_wmemstream@Base 5
+ __interceptor_opendir@Base 6.2
+ __interceptor_poll@Base 4.9
+ __interceptor_posix_memalign@Base 4.8
+ __interceptor_ppoll@Base 4.9
+ __interceptor_prctl@Base 4.8
+ __interceptor_pread64@Base 4.8
+ __interceptor_pread@Base 4.8
+ __interceptor_preadv64@Base 4.9
+ __interceptor_preadv@Base 4.9
+ __interceptor_printf@Base 5
+ __interceptor_process_vm_readv@Base 6.2
+ __interceptor_process_vm_writev@Base 6.2
+ __interceptor_pthread_attr_getaffinity_np@Base 4.9
+ __interceptor_pthread_attr_getdetachstate@Base 4.9
+ __interceptor_pthread_attr_getguardsize@Base 4.9
+ __interceptor_pthread_attr_getinheritsched@Base 4.9
+ __interceptor_pthread_attr_getschedparam@Base 4.9
+ __interceptor_pthread_attr_getschedpolicy@Base 4.9
+ __interceptor_pthread_attr_getscope@Base 4.9
+ __interceptor_pthread_attr_getstack@Base 4.9
+ __interceptor_pthread_attr_getstacksize@Base 4.9
+ __interceptor_pthread_barrierattr_getpshared@Base 5
+ __interceptor_pthread_condattr_getclock@Base 5
+ __interceptor_pthread_condattr_getpshared@Base 5
+ __interceptor_pthread_create@Base 4.8
+ __interceptor_pthread_getschedparam@Base 4.9
+ __interceptor_pthread_join@Base 6.2
+ __interceptor_pthread_mutex_lock@Base 4.9
+ __interceptor_pthread_mutex_unlock@Base 4.9
+ __interceptor_pthread_mutexattr_getprioceiling@Base 5
+ __interceptor_pthread_mutexattr_getprotocol@Base 5
+ __interceptor_pthread_mutexattr_getpshared@Base 5
+ __interceptor_pthread_mutexattr_getrobust@Base 5
+ __interceptor_pthread_mutexattr_getrobust_np@Base 5
+ __interceptor_pthread_mutexattr_gettype@Base 5
+ __interceptor_pthread_rwlockattr_getkind_np@Base 5
+ __interceptor_pthread_rwlockattr_getpshared@Base 5
+ __interceptor_pthread_setcancelstate@Base 6.2
+ __interceptor_pthread_setcanceltype@Base 6.2
+ __interceptor_pthread_setname_np@Base 4.9
+ __interceptor_pvalloc@Base 4.8
+ __interceptor_pwrite64@Base 4.8
+ __interceptor_pwrite@Base 4.8
+ __interceptor_pwritev64@Base 4.9
+ __interceptor_pwritev@Base 4.9
+ __interceptor_rand_r@Base 5
+ __interceptor_random_r@Base 4.9
+ __interceptor_read@Base 4.8
+ __interceptor_readdir64@Base 4.9
+ __interceptor_readdir64_r@Base 4.9
+ __interceptor_readdir@Base 4.9
+ __interceptor_readdir_r@Base 4.9
+ __interceptor_readv@Base 4.9
+ __interceptor_realloc@Base 4.8
+ __interceptor_realpath@Base 4.9
+ __interceptor_recvmsg@Base 4.9
+ __interceptor_remquo@Base 4.9
+ __interceptor_remquof@Base 4.9
+ __interceptor_remquol@Base 4.9
+ __interceptor_scandir64@Base 4.9
+ __interceptor_scandir@Base 4.9
+ __interceptor_scanf@Base 4.8
+ __interceptor_sched_getaffinity@Base 4.9
+ __interceptor_sched_getparam@Base 6.2
+ __interceptor_sem_destroy@Base 6.2
+ __interceptor_sem_getvalue@Base 6.2
+ __interceptor_sem_init@Base 6.2
+ __interceptor_sem_post@Base 6.2
+ __interceptor_sem_timedwait@Base 6.2
+ __interceptor_sem_trywait@Base 6.2
+ __interceptor_sem_wait@Base 6.2
+ __interceptor_setgrent@Base 5
+ __interceptor_setitimer@Base 4.9
+ __interceptor_setlocale@Base 4.9
+ __interceptor_setpwent@Base 5
+ __interceptor_sigaction@Base 4.8
+ __interceptor_sigemptyset@Base 4.9
+ __interceptor_sigfillset@Base 4.9
+ __interceptor_siglongjmp@Base 4.8
+ __interceptor_signal@Base 4.8
+ __interceptor_sigpending@Base 4.9
+ __interceptor_sigprocmask@Base 4.9
+ __interceptor_sigtimedwait@Base 4.9
+ __interceptor_sigwait@Base 4.9
+ __interceptor_sigwaitinfo@Base 4.9
+ __interceptor_sincos@Base 4.9
+ __interceptor_sincosf@Base 4.9
+ __interceptor_sincosl@Base 4.9
+ __interceptor_snprintf@Base 5
+ __interceptor_sprintf@Base 5
+ __interceptor_sscanf@Base 4.8
+ __interceptor_statfs64@Base 4.9
+ __interceptor_statfs@Base 4.9
+ __interceptor_statvfs64@Base 4.9
+ __interceptor_statvfs@Base 4.9
+ __interceptor_strcasecmp@Base 4.8
+ __interceptor_strcasestr@Base 6.2
+ __interceptor_strcat@Base 4.8
+ __interceptor_strchr@Base 4.8
+ __interceptor_strcmp@Base 4.8
+ __interceptor_strcpy@Base 4.8
+ __interceptor_strcspn@Base 6.2
+ __interceptor_strdup@Base 4.8
+ __interceptor_strerror@Base 4.9
+ __interceptor_strerror_r@Base 4.9
+ __interceptor_strlen@Base 4.8
+ __interceptor_strncasecmp@Base 4.8
+ __interceptor_strncat@Base 4.8
+ __interceptor_strncmp@Base 4.8
+ __interceptor_strncpy@Base 4.8
+ __interceptor_strnlen@Base 4.8
+ __interceptor_strpbrk@Base 6.2
+ __interceptor_strptime@Base 4.9
+ __interceptor_strspn@Base 6.2
+ __interceptor_strstr@Base 6.2
+ __interceptor_strtoimax@Base 4.9
+ __interceptor_strtol@Base 4.8
+ __interceptor_strtoll@Base 4.8
+ __interceptor_strtoumax@Base 4.9
+ __interceptor_swapcontext@Base 4.8
+ __interceptor_sysinfo@Base 4.9
+ __interceptor_tcgetattr@Base 4.9
+ __interceptor_tempnam@Base 4.9
+ __interceptor_textdomain@Base 4.9
+ __interceptor_time@Base 4.9
+ __interceptor_timerfd_gettime@Base 5
+ __interceptor_timerfd_settime@Base 5
+ __interceptor_times@Base 4.9
+ __interceptor_tmpnam@Base 4.9
+ __interceptor_tmpnam_r@Base 4.9
+ __interceptor_tsearch@Base 5
+ __interceptor_valloc@Base 4.8
+ __interceptor_vasprintf@Base 5
+ __interceptor_vfprintf@Base 5
+ __interceptor_vfscanf@Base 4.8
+ __interceptor_vprintf@Base 5
+ __interceptor_vscanf@Base 4.8
+ __interceptor_vsnprintf@Base 5
+ __interceptor_vsprintf@Base 5
+ __interceptor_vsscanf@Base 4.8
+ __interceptor_wait3@Base 4.9
+ __interceptor_wait4@Base 4.9
+ __interceptor_wait@Base 4.9
+ __interceptor_waitid@Base 4.9
+ __interceptor_waitpid@Base 4.9
+ __interceptor_wcrtomb@Base 6.2
+ __interceptor_wcslen@Base 4.9
+ __interceptor_wcsnrtombs@Base 4.9
+ __interceptor_wcsrtombs@Base 4.9
+ __interceptor_wcstombs@Base 4.9
+ __interceptor_wordexp@Base 4.9
+ __interceptor_write@Base 4.8
+ __interceptor_writev@Base 4.9
+ __interceptor_xdr_bool@Base 5
+ __interceptor_xdr_bytes@Base 5
+ __interceptor_xdr_char@Base 5
+ __interceptor_xdr_double@Base 5
+ __interceptor_xdr_enum@Base 5
+ __interceptor_xdr_float@Base 5
+ __interceptor_xdr_hyper@Base 5
+ __interceptor_xdr_int16_t@Base 5
+ __interceptor_xdr_int32_t@Base 5
+ __interceptor_xdr_int64_t@Base 5
+ __interceptor_xdr_int8_t@Base 5
+ __interceptor_xdr_int@Base 5
+ __interceptor_xdr_long@Base 5
+ __interceptor_xdr_longlong_t@Base 5
+ __interceptor_xdr_quad_t@Base 5
+ __interceptor_xdr_short@Base 5
+ __interceptor_xdr_string@Base 5
+ __interceptor_xdr_u_char@Base 5
+ __interceptor_xdr_u_hyper@Base 5
+ __interceptor_xdr_u_int@Base 5
+ __interceptor_xdr_u_long@Base 5
+ __interceptor_xdr_u_longlong_t@Base 5
+ __interceptor_xdr_u_quad_t@Base 5
+ __interceptor_xdr_u_short@Base 5
+ __interceptor_xdr_uint16_t@Base 5
+ __interceptor_xdr_uint32_t@Base 5
+ __interceptor_xdr_uint64_t@Base 5
+ __interceptor_xdr_uint8_t@Base 5
+ __interceptor_xdrmem_create@Base 5
+ __interceptor_xdrstdio_create@Base 5
+ __isoc99_fprintf@Base 5
+ __isoc99_fscanf@Base 4.8
+ __isoc99_printf@Base 5
+ __isoc99_scanf@Base 4.8
+ __isoc99_snprintf@Base 5
+ __isoc99_sprintf@Base 5
+ __isoc99_sscanf@Base 4.8
+ __isoc99_vfprintf@Base 5
+ __isoc99_vfscanf@Base 4.8
+ __isoc99_vprintf@Base 5
+ __isoc99_vscanf@Base 4.8
+ __isoc99_vsnprintf@Base 5
+ __isoc99_vsprintf@Base 5
+ __isoc99_vsscanf@Base 4.8
+ __libc_memalign@Base 4.8
+ __lsan_disable@Base 4.9
+ __lsan_do_leak_check@Base 4.9
+ __lsan_do_recoverable_leak_check@Base 6.2
+ __lsan_enable@Base 4.9
+ __lsan_ignore_object@Base 4.9
+ __lsan_register_root_region@Base 5
+ __lsan_unregister_root_region@Base 5
+ __overflow@Base 5
+ __sanitizer_annotate_contiguous_container@Base 4.9
+ __sanitizer_contiguous_container_find_bad_address@Base 6.2
+ __sanitizer_cov@Base 4.9
+ __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_cov_trace_basic_block@Base 6.2
+ __sanitizer_cov_trace_cmp@Base 6.2
+ __sanitizer_cov_trace_func_enter@Base 6.2
+ __sanitizer_cov_trace_switch@Base 6.2
+ __sanitizer_cov_with_check@Base 6.2
+ __sanitizer_get_allocated_size@Base 5
+ __sanitizer_get_coverage_guards@Base 6.2
+ __sanitizer_get_current_allocated_bytes@Base 5
+ __sanitizer_get_estimated_allocated_size@Base 5
+ __sanitizer_get_free_bytes@Base 5
+ __sanitizer_get_heap_size@Base 5
+ __sanitizer_get_number_of_counters@Base 6.2
+ __sanitizer_get_ownership@Base 5
+ __sanitizer_get_total_unique_caller_callee_pairs@Base 6.2
+ __sanitizer_get_total_unique_coverage@Base 6.2
+ __sanitizer_get_unmapped_bytes@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_print_stack_trace@Base 4.9
+ __sanitizer_ptr_cmp@Base 5
+ __sanitizer_ptr_sub@Base 5
+ __sanitizer_report_error_summary@Base 4.8
+ __sanitizer_reset_coverage@Base 6.2
+ __sanitizer_sandbox_on_notify@Base 4.8
+ __sanitizer_set_death_callback@Base 6.2
+ __sanitizer_set_report_path@Base 4.8
+ __sanitizer_syscall_post_impl_accept4@Base 4.9
+ __sanitizer_syscall_post_impl_accept@Base 4.9
+ __sanitizer_syscall_post_impl_access@Base 4.9
+ __sanitizer_syscall_post_impl_acct@Base 4.9
+ __sanitizer_syscall_post_impl_add_key@Base 4.9
+ __sanitizer_syscall_post_impl_adjtimex@Base 4.9
+ __sanitizer_syscall_post_impl_alarm@Base 4.9
+ __sanitizer_syscall_post_impl_bdflush@Base 4.9
+ __sanitizer_syscall_post_impl_bind@Base 4.9
+ __sanitizer_syscall_post_impl_brk@Base 4.9
+ __sanitizer_syscall_post_impl_capget@Base 4.9
+ __sanitizer_syscall_post_impl_capset@Base 4.9
+ __sanitizer_syscall_post_impl_chdir@Base 4.9
+ __sanitizer_syscall_post_impl_chmod@Base 4.9
+ __sanitizer_syscall_post_impl_chown@Base 4.9
+ __sanitizer_syscall_post_impl_chroot@Base 4.9
+ __sanitizer_syscall_post_impl_clock_adjtime@Base 4.9
+ __sanitizer_syscall_post_impl_clock_getres@Base 4.9
+ __sanitizer_syscall_post_impl_clock_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_clock_nanosleep@Base 4.9
+ __sanitizer_syscall_post_impl_clock_settime@Base 4.9
+ __sanitizer_syscall_post_impl_close@Base 4.9
+ __sanitizer_syscall_post_impl_connect@Base 4.9
+ __sanitizer_syscall_post_impl_creat@Base 4.9
+ __sanitizer_syscall_post_impl_delete_module@Base 4.9
+ __sanitizer_syscall_post_impl_dup2@Base 4.9
+ __sanitizer_syscall_post_impl_dup3@Base 4.9
+ __sanitizer_syscall_post_impl_dup@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_create1@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_create@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_ctl@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_pwait@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_wait@Base 4.9
+ __sanitizer_syscall_post_impl_eventfd2@Base 4.9
+ __sanitizer_syscall_post_impl_eventfd@Base 4.9
+ __sanitizer_syscall_post_impl_exit@Base 4.9
+ __sanitizer_syscall_post_impl_exit_group@Base 4.9
+ __sanitizer_syscall_post_impl_faccessat@Base 4.9
+ __sanitizer_syscall_post_impl_fchdir@Base 4.9
+ __sanitizer_syscall_post_impl_fchmod@Base 4.9
+ __sanitizer_syscall_post_impl_fchmodat@Base 4.9
+ __sanitizer_syscall_post_impl_fchown@Base 4.9
+ __sanitizer_syscall_post_impl_fchownat@Base 4.9
+ __sanitizer_syscall_post_impl_fcntl64@Base 4.9
+ __sanitizer_syscall_post_impl_fcntl@Base 4.9
+ __sanitizer_syscall_post_impl_fdatasync@Base 4.9
+ __sanitizer_syscall_post_impl_fgetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_flistxattr@Base 4.9
+ __sanitizer_syscall_post_impl_flock@Base 4.9
+ __sanitizer_syscall_post_impl_fork@Base 4.9
+ __sanitizer_syscall_post_impl_fremovexattr@Base 4.9
+ __sanitizer_syscall_post_impl_fsetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_fstat64@Base 4.9
+ __sanitizer_syscall_post_impl_fstat@Base 4.9
+ __sanitizer_syscall_post_impl_fstatat64@Base 4.9
+ __sanitizer_syscall_post_impl_fstatfs64@Base 4.9
+ __sanitizer_syscall_post_impl_fstatfs@Base 4.9
+ __sanitizer_syscall_post_impl_fsync@Base 4.9
+ __sanitizer_syscall_post_impl_ftruncate@Base 4.9
+ __sanitizer_syscall_post_impl_futimesat@Base 4.9
+ __sanitizer_syscall_post_impl_get_mempolicy@Base 4.9
+ __sanitizer_syscall_post_impl_get_robust_list@Base 4.9
+ __sanitizer_syscall_post_impl_getcpu@Base 4.9
+ __sanitizer_syscall_post_impl_getcwd@Base 4.9
+ __sanitizer_syscall_post_impl_getdents64@Base 4.9
+ __sanitizer_syscall_post_impl_getdents@Base 4.9
+ __sanitizer_syscall_post_impl_getegid@Base 4.9
+ __sanitizer_syscall_post_impl_geteuid@Base 4.9
+ __sanitizer_syscall_post_impl_getgid@Base 4.9
+ __sanitizer_syscall_post_impl_getgroups@Base 4.9
+ __sanitizer_syscall_post_impl_gethostname@Base 4.9
+ __sanitizer_syscall_post_impl_getitimer@Base 4.9
+ __sanitizer_syscall_post_impl_getpeername@Base 4.9
+ __sanitizer_syscall_post_impl_getpgid@Base 4.9
+ __sanitizer_syscall_post_impl_getpgrp@Base 4.9
+ __sanitizer_syscall_post_impl_getpid@Base 4.9
+ __sanitizer_syscall_post_impl_getppid@Base 4.9
+ __sanitizer_syscall_post_impl_getpriority@Base 4.9
+ __sanitizer_syscall_post_impl_getresgid@Base 4.9
+ __sanitizer_syscall_post_impl_getresuid@Base 4.9
+ __sanitizer_syscall_post_impl_getrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_getrusage@Base 4.9
+ __sanitizer_syscall_post_impl_getsid@Base 4.9
+ __sanitizer_syscall_post_impl_getsockname@Base 4.9
+ __sanitizer_syscall_post_impl_getsockopt@Base 4.9
+ __sanitizer_syscall_post_impl_gettid@Base 4.9
+ __sanitizer_syscall_post_impl_gettimeofday@Base 4.9
+ __sanitizer_syscall_post_impl_getuid@Base 4.9
+ __sanitizer_syscall_post_impl_getxattr@Base 4.9
+ __sanitizer_syscall_post_impl_init_module@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_add_watch@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_init1@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_init@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_rm_watch@Base 4.9
+ __sanitizer_syscall_post_impl_io_cancel@Base 4.9
+ __sanitizer_syscall_post_impl_io_destroy@Base 4.9
+ __sanitizer_syscall_post_impl_io_getevents@Base 4.9
+ __sanitizer_syscall_post_impl_io_setup@Base 4.9
+ __sanitizer_syscall_post_impl_io_submit@Base 4.9
+ __sanitizer_syscall_post_impl_ioctl@Base 4.9
+ __sanitizer_syscall_post_impl_ioperm@Base 4.9
+ __sanitizer_syscall_post_impl_ioprio_get@Base 4.9
+ __sanitizer_syscall_post_impl_ioprio_set@Base 4.9
+ __sanitizer_syscall_post_impl_ipc@Base 4.9
+ __sanitizer_syscall_post_impl_kexec_load@Base 4.9
+ __sanitizer_syscall_post_impl_keyctl@Base 4.9
+ __sanitizer_syscall_post_impl_kill@Base 4.9
+ __sanitizer_syscall_post_impl_lchown@Base 4.9
+ __sanitizer_syscall_post_impl_lgetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_link@Base 4.9
+ __sanitizer_syscall_post_impl_linkat@Base 4.9
+ __sanitizer_syscall_post_impl_listen@Base 4.9
+ __sanitizer_syscall_post_impl_listxattr@Base 4.9
+ __sanitizer_syscall_post_impl_llistxattr@Base 4.9
+ __sanitizer_syscall_post_impl_llseek@Base 4.9
+ __sanitizer_syscall_post_impl_lookup_dcookie@Base 4.9
+ __sanitizer_syscall_post_impl_lremovexattr@Base 4.9
+ __sanitizer_syscall_post_impl_lseek@Base 4.9
+ __sanitizer_syscall_post_impl_lsetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_lstat64@Base 4.9
+ __sanitizer_syscall_post_impl_lstat@Base 4.9
+ __sanitizer_syscall_post_impl_madvise@Base 4.9
+ __sanitizer_syscall_post_impl_mbind@Base 4.9
+ __sanitizer_syscall_post_impl_migrate_pages@Base 4.9
+ __sanitizer_syscall_post_impl_mincore@Base 4.9
+ __sanitizer_syscall_post_impl_mkdir@Base 4.9
+ __sanitizer_syscall_post_impl_mkdirat@Base 4.9
+ __sanitizer_syscall_post_impl_mknod@Base 4.9
+ __sanitizer_syscall_post_impl_mknodat@Base 4.9
+ __sanitizer_syscall_post_impl_mlock@Base 4.9
+ __sanitizer_syscall_post_impl_mlockall@Base 4.9
+ __sanitizer_syscall_post_impl_mmap_pgoff@Base 4.9
+ __sanitizer_syscall_post_impl_mount@Base 4.9
+ __sanitizer_syscall_post_impl_move_pages@Base 4.9
+ __sanitizer_syscall_post_impl_mprotect@Base 4.9
+ __sanitizer_syscall_post_impl_mq_getsetattr@Base 4.9
+ __sanitizer_syscall_post_impl_mq_notify@Base 4.9
+ __sanitizer_syscall_post_impl_mq_open@Base 4.9
+ __sanitizer_syscall_post_impl_mq_timedreceive@Base 4.9
+ __sanitizer_syscall_post_impl_mq_timedsend@Base 4.9
+ __sanitizer_syscall_post_impl_mq_unlink@Base 4.9
+ __sanitizer_syscall_post_impl_mremap@Base 4.9
+ __sanitizer_syscall_post_impl_msgctl@Base 4.9
+ __sanitizer_syscall_post_impl_msgget@Base 4.9
+ __sanitizer_syscall_post_impl_msgrcv@Base 4.9
+ __sanitizer_syscall_post_impl_msgsnd@Base 4.9
+ __sanitizer_syscall_post_impl_msync@Base 4.9
+ __sanitizer_syscall_post_impl_munlock@Base 4.9
+ __sanitizer_syscall_post_impl_munlockall@Base 4.9
+ __sanitizer_syscall_post_impl_munmap@Base 4.9
+ __sanitizer_syscall_post_impl_name_to_handle_at@Base 4.9
+ __sanitizer_syscall_post_impl_nanosleep@Base 4.9
+ __sanitizer_syscall_post_impl_newfstat@Base 4.9
+ __sanitizer_syscall_post_impl_newfstatat@Base 4.9
+ __sanitizer_syscall_post_impl_newlstat@Base 4.9
+ __sanitizer_syscall_post_impl_newstat@Base 4.9
+ __sanitizer_syscall_post_impl_newuname@Base 4.9
+ __sanitizer_syscall_post_impl_ni_syscall@Base 4.9
+ __sanitizer_syscall_post_impl_nice@Base 4.9
+ __sanitizer_syscall_post_impl_old_getrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_old_mmap@Base 4.9
+ __sanitizer_syscall_post_impl_old_readdir@Base 4.9
+ __sanitizer_syscall_post_impl_old_select@Base 4.9
+ __sanitizer_syscall_post_impl_oldumount@Base 4.9
+ __sanitizer_syscall_post_impl_olduname@Base 4.9
+ __sanitizer_syscall_post_impl_open@Base 4.9
+ __sanitizer_syscall_post_impl_open_by_handle_at@Base 4.9
+ __sanitizer_syscall_post_impl_openat@Base 4.9
+ __sanitizer_syscall_post_impl_pause@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_iobase@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_read@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_write@Base 4.9
+ __sanitizer_syscall_post_impl_perf_event_open@Base 4.9
+ __sanitizer_syscall_post_impl_personality@Base 4.9
+ __sanitizer_syscall_post_impl_pipe2@Base 4.9
+ __sanitizer_syscall_post_impl_pipe@Base 4.9
+ __sanitizer_syscall_post_impl_pivot_root@Base 4.9
+ __sanitizer_syscall_post_impl_poll@Base 4.9
+ __sanitizer_syscall_post_impl_ppoll@Base 4.9
+ __sanitizer_syscall_post_impl_pread64@Base 4.9
+ __sanitizer_syscall_post_impl_preadv@Base 4.9
+ __sanitizer_syscall_post_impl_prlimit64@Base 4.9
+ __sanitizer_syscall_post_impl_process_vm_readv@Base 4.9
+ __sanitizer_syscall_post_impl_process_vm_writev@Base 4.9
+ __sanitizer_syscall_post_impl_pselect6@Base 4.9
+ __sanitizer_syscall_post_impl_ptrace@Base 4.9
+ __sanitizer_syscall_post_impl_pwrite64@Base 4.9
+ __sanitizer_syscall_post_impl_pwritev@Base 4.9
+ __sanitizer_syscall_post_impl_quotactl@Base 4.9
+ __sanitizer_syscall_post_impl_read@Base 4.9
+ __sanitizer_syscall_post_impl_readlink@Base 4.9
+ __sanitizer_syscall_post_impl_readlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_readv@Base 4.9
+ __sanitizer_syscall_post_impl_reboot@Base 4.9
+ __sanitizer_syscall_post_impl_recv@Base 4.9
+ __sanitizer_syscall_post_impl_recvfrom@Base 4.9
+ __sanitizer_syscall_post_impl_recvmmsg@Base 4.9
+ __sanitizer_syscall_post_impl_recvmsg@Base 4.9
+ __sanitizer_syscall_post_impl_remap_file_pages@Base 4.9
+ __sanitizer_syscall_post_impl_removexattr@Base 4.9
+ __sanitizer_syscall_post_impl_rename@Base 4.9
+ __sanitizer_syscall_post_impl_renameat@Base 4.9
+ __sanitizer_syscall_post_impl_request_key@Base 4.9
+ __sanitizer_syscall_post_impl_restart_syscall@Base 4.9
+ __sanitizer_syscall_post_impl_rmdir@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigpending@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigprocmask@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigqueueinfo@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigtimedwait@Base 4.9
+ __sanitizer_syscall_post_impl_rt_tgsigqueueinfo@Base 4.9
+ __sanitizer_syscall_post_impl_sched_get_priority_max@Base 4.9
+ __sanitizer_syscall_post_impl_sched_get_priority_min@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getaffinity@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getparam@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getscheduler@Base 4.9
+ __sanitizer_syscall_post_impl_sched_rr_get_interval@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setaffinity@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setparam@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setscheduler@Base 4.9
+ __sanitizer_syscall_post_impl_sched_yield@Base 4.9
+ __sanitizer_syscall_post_impl_select@Base 4.9
+ __sanitizer_syscall_post_impl_semctl@Base 4.9
+ __sanitizer_syscall_post_impl_semget@Base 4.9
+ __sanitizer_syscall_post_impl_semop@Base 4.9
+ __sanitizer_syscall_post_impl_semtimedop@Base 4.9
+ __sanitizer_syscall_post_impl_send@Base 4.9
+ __sanitizer_syscall_post_impl_sendfile64@Base 4.9
+ __sanitizer_syscall_post_impl_sendfile@Base 4.9
+ __sanitizer_syscall_post_impl_sendmmsg@Base 4.9
+ __sanitizer_syscall_post_impl_sendmsg@Base 4.9
+ __sanitizer_syscall_post_impl_sendto@Base 4.9
+ __sanitizer_syscall_post_impl_set_mempolicy@Base 4.9
+ __sanitizer_syscall_post_impl_set_robust_list@Base 4.9
+ __sanitizer_syscall_post_impl_set_tid_address@Base 4.9
+ __sanitizer_syscall_post_impl_setdomainname@Base 4.9
+ __sanitizer_syscall_post_impl_setfsgid@Base 4.9
+ __sanitizer_syscall_post_impl_setfsuid@Base 4.9
+ __sanitizer_syscall_post_impl_setgid@Base 4.9
+ __sanitizer_syscall_post_impl_setgroups@Base 4.9
+ __sanitizer_syscall_post_impl_sethostname@Base 4.9
+ __sanitizer_syscall_post_impl_setitimer@Base 4.9
+ __sanitizer_syscall_post_impl_setns@Base 4.9
+ __sanitizer_syscall_post_impl_setpgid@Base 4.9
+ __sanitizer_syscall_post_impl_setpriority@Base 4.9
+ __sanitizer_syscall_post_impl_setregid@Base 4.9
+ __sanitizer_syscall_post_impl_setresgid@Base 4.9
+ __sanitizer_syscall_post_impl_setresuid@Base 4.9
+ __sanitizer_syscall_post_impl_setreuid@Base 4.9
+ __sanitizer_syscall_post_impl_setrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_setsid@Base 4.9
+ __sanitizer_syscall_post_impl_setsockopt@Base 4.9
+ __sanitizer_syscall_post_impl_settimeofday@Base 4.9
+ __sanitizer_syscall_post_impl_setuid@Base 4.9
+ __sanitizer_syscall_post_impl_setxattr@Base 4.9
+ __sanitizer_syscall_post_impl_sgetmask@Base 4.9
+ __sanitizer_syscall_post_impl_shmat@Base 4.9
+ __sanitizer_syscall_post_impl_shmctl@Base 4.9
+ __sanitizer_syscall_post_impl_shmdt@Base 4.9
+ __sanitizer_syscall_post_impl_shmget@Base 4.9
+ __sanitizer_syscall_post_impl_shutdown@Base 4.9
+ __sanitizer_syscall_post_impl_signal@Base 4.9
+ __sanitizer_syscall_post_impl_signalfd4@Base 4.9
+ __sanitizer_syscall_post_impl_signalfd@Base 4.9
+ __sanitizer_syscall_post_impl_sigpending@Base 4.9
+ __sanitizer_syscall_post_impl_sigprocmask@Base 4.9
+ __sanitizer_syscall_post_impl_socket@Base 4.9
+ __sanitizer_syscall_post_impl_socketcall@Base 4.9
+ __sanitizer_syscall_post_impl_socketpair@Base 4.9
+ __sanitizer_syscall_post_impl_splice@Base 4.9
+ __sanitizer_syscall_post_impl_spu_create@Base 4.9
+ __sanitizer_syscall_post_impl_spu_run@Base 4.9
+ __sanitizer_syscall_post_impl_ssetmask@Base 4.9
+ __sanitizer_syscall_post_impl_stat64@Base 4.9
+ __sanitizer_syscall_post_impl_stat@Base 4.9
+ __sanitizer_syscall_post_impl_statfs64@Base 4.9
+ __sanitizer_syscall_post_impl_statfs@Base 4.9
+ __sanitizer_syscall_post_impl_stime@Base 4.9
+ __sanitizer_syscall_post_impl_swapoff@Base 4.9
+ __sanitizer_syscall_post_impl_swapon@Base 4.9
+ __sanitizer_syscall_post_impl_symlink@Base 4.9
+ __sanitizer_syscall_post_impl_symlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_sync@Base 4.9
+ __sanitizer_syscall_post_impl_syncfs@Base 4.9
+ __sanitizer_syscall_post_impl_sysctl@Base 4.9
+ __sanitizer_syscall_post_impl_sysfs@Base 4.9
+ __sanitizer_syscall_post_impl_sysinfo@Base 4.9
+ __sanitizer_syscall_post_impl_syslog@Base 4.9
+ __sanitizer_syscall_post_impl_tee@Base 4.9
+ __sanitizer_syscall_post_impl_tgkill@Base 4.9
+ __sanitizer_syscall_post_impl_time@Base 4.9
+ __sanitizer_syscall_post_impl_timer_create@Base 4.9
+ __sanitizer_syscall_post_impl_timer_delete@Base 4.9
+ __sanitizer_syscall_post_impl_timer_getoverrun@Base 4.9
+ __sanitizer_syscall_post_impl_timer_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_timer_settime@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_create@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_settime@Base 4.9
+ __sanitizer_syscall_post_impl_times@Base 4.9
+ __sanitizer_syscall_post_impl_tkill@Base 4.9
+ __sanitizer_syscall_post_impl_truncate@Base 4.9
+ __sanitizer_syscall_post_impl_umask@Base 4.9
+ __sanitizer_syscall_post_impl_umount@Base 4.9
+ __sanitizer_syscall_post_impl_uname@Base 4.9
+ __sanitizer_syscall_post_impl_unlink@Base 4.9
+ __sanitizer_syscall_post_impl_unlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_unshare@Base 4.9
+ __sanitizer_syscall_post_impl_uselib@Base 4.9
+ __sanitizer_syscall_post_impl_ustat@Base 4.9
+ __sanitizer_syscall_post_impl_utime@Base 4.9
+ __sanitizer_syscall_post_impl_utimensat@Base 4.9
+ __sanitizer_syscall_post_impl_utimes@Base 4.9
+ __sanitizer_syscall_post_impl_vfork@Base 4.9
+ __sanitizer_syscall_post_impl_vhangup@Base 4.9
+ __sanitizer_syscall_post_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_post_impl_wait4@Base 4.9
+ __sanitizer_syscall_post_impl_waitid@Base 4.9
+ __sanitizer_syscall_post_impl_waitpid@Base 4.9
+ __sanitizer_syscall_post_impl_write@Base 4.9
+ __sanitizer_syscall_post_impl_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_accept4@Base 4.9
+ __sanitizer_syscall_pre_impl_accept@Base 4.9
+ __sanitizer_syscall_pre_impl_access@Base 4.9
+ __sanitizer_syscall_pre_impl_acct@Base 4.9
+ __sanitizer_syscall_pre_impl_add_key@Base 4.9
+ __sanitizer_syscall_pre_impl_adjtimex@Base 4.9
+ __sanitizer_syscall_pre_impl_alarm@Base 4.9
+ __sanitizer_syscall_pre_impl_bdflush@Base 4.9
+ __sanitizer_syscall_pre_impl_bind@Base 4.9
+ __sanitizer_syscall_pre_impl_brk@Base 4.9
+ __sanitizer_syscall_pre_impl_capget@Base 4.9
+ __sanitizer_syscall_pre_impl_capset@Base 4.9
+ __sanitizer_syscall_pre_impl_chdir@Base 4.9
+ __sanitizer_syscall_pre_impl_chmod@Base 4.9
+ __sanitizer_syscall_pre_impl_chown@Base 4.9
+ __sanitizer_syscall_pre_impl_chroot@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_adjtime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_getres@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_close@Base 4.9
+ __sanitizer_syscall_pre_impl_connect@Base 4.9
+ __sanitizer_syscall_pre_impl_creat@Base 4.9
+ __sanitizer_syscall_pre_impl_delete_module@Base 4.9
+ __sanitizer_syscall_pre_impl_dup2@Base 4.9
+ __sanitizer_syscall_pre_impl_dup3@Base 4.9
+ __sanitizer_syscall_pre_impl_dup@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create1@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_ctl@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_pwait@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_wait@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd2@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd@Base 4.9
+ __sanitizer_syscall_pre_impl_exit@Base 4.9
+ __sanitizer_syscall_pre_impl_exit_group@Base 4.9
+ __sanitizer_syscall_pre_impl_faccessat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchdir@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmod@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmodat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchown@Base 4.9
+ __sanitizer_syscall_pre_impl_fchownat@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl64@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl@Base 4.9
+ __sanitizer_syscall_pre_impl_fdatasync@Base 4.9
+ __sanitizer_syscall_pre_impl_fgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flock@Base 4.9
+ __sanitizer_syscall_pre_impl_fork@Base 4.9
+ __sanitizer_syscall_pre_impl_fremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs@Base 4.9
+ __sanitizer_syscall_pre_impl_fsync@Base 4.9
+ __sanitizer_syscall_pre_impl_ftruncate@Base 4.9
+ __sanitizer_syscall_pre_impl_futimesat@Base 4.9
+ __sanitizer_syscall_pre_impl_get_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_get_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_getcpu@Base 4.9
+ __sanitizer_syscall_pre_impl_getcwd@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents64@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents@Base 4.9
+ __sanitizer_syscall_pre_impl_getegid@Base 4.9
+ __sanitizer_syscall_pre_impl_geteuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_gethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_getitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_getpeername@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgrp@Base 4.9
+ __sanitizer_syscall_pre_impl_getpid@Base 4.9
+ __sanitizer_syscall_pre_impl_getppid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_getresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_getrusage@Base 4.9
+ __sanitizer_syscall_pre_impl_getsid@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockname@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_gettid@Base 4.9
+ __sanitizer_syscall_pre_impl_gettimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_getuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_init_module@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_add_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init1@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_rm_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_io_cancel@Base 4.9
+ __sanitizer_syscall_pre_impl_io_destroy@Base 4.9
+ __sanitizer_syscall_pre_impl_io_getevents@Base 4.9
+ __sanitizer_syscall_pre_impl_io_setup@Base 4.9
+ __sanitizer_syscall_pre_impl_io_submit@Base 4.9
+ __sanitizer_syscall_pre_impl_ioctl@Base 4.9
+ __sanitizer_syscall_pre_impl_ioperm@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_get@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_set@Base 4.9
+ __sanitizer_syscall_pre_impl_ipc@Base 4.9
+ __sanitizer_syscall_pre_impl_kexec_load@Base 4.9
+ __sanitizer_syscall_pre_impl_keyctl@Base 4.9
+ __sanitizer_syscall_pre_impl_kill@Base 4.9
+ __sanitizer_syscall_pre_impl_lchown@Base 4.9
+ __sanitizer_syscall_pre_impl_lgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_link@Base 4.9
+ __sanitizer_syscall_pre_impl_linkat@Base 4.9
+ __sanitizer_syscall_pre_impl_listen@Base 4.9
+ __sanitizer_syscall_pre_impl_listxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lookup_dcookie@Base 4.9
+ __sanitizer_syscall_pre_impl_lremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat@Base 4.9
+ __sanitizer_syscall_pre_impl_madvise@Base 4.9
+ __sanitizer_syscall_pre_impl_mbind@Base 4.9
+ __sanitizer_syscall_pre_impl_migrate_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mincore@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdir@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdirat@Base 4.9
+ __sanitizer_syscall_pre_impl_mknod@Base 4.9
+ __sanitizer_syscall_pre_impl_mknodat@Base 4.9
+ __sanitizer_syscall_pre_impl_mlock@Base 4.9
+ __sanitizer_syscall_pre_impl_mlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_mmap_pgoff@Base 4.9
+ __sanitizer_syscall_pre_impl_mount@Base 4.9
+ __sanitizer_syscall_pre_impl_move_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mprotect@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_getsetattr@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_notify@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_open@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedreceive@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedsend@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_mremap@Base 4.9
+ __sanitizer_syscall_pre_impl_msgctl@Base 4.9
+ __sanitizer_syscall_pre_impl_msgget@Base 4.9
+ __sanitizer_syscall_pre_impl_msgrcv@Base 4.9
+ __sanitizer_syscall_pre_impl_msgsnd@Base 4.9
+ __sanitizer_syscall_pre_impl_msync@Base 4.9
+ __sanitizer_syscall_pre_impl_munlock@Base 4.9
+ __sanitizer_syscall_pre_impl_munlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_munmap@Base 4.9
+ __sanitizer_syscall_pre_impl_name_to_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstatat@Base 4.9
+ __sanitizer_syscall_pre_impl_newlstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newuname@Base 4.9
+ __sanitizer_syscall_pre_impl_ni_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_nice@Base 4.9
+ __sanitizer_syscall_pre_impl_old_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_old_mmap@Base 4.9
+ __sanitizer_syscall_pre_impl_old_readdir@Base 4.9
+ __sanitizer_syscall_pre_impl_old_select@Base 4.9
+ __sanitizer_syscall_pre_impl_oldumount@Base 4.9
+ __sanitizer_syscall_pre_impl_olduname@Base 4.9
+ __sanitizer_syscall_pre_impl_open@Base 4.9
+ __sanitizer_syscall_pre_impl_open_by_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_openat@Base 4.9
+ __sanitizer_syscall_pre_impl_pause@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_iobase@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_read@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_write@Base 4.9
+ __sanitizer_syscall_pre_impl_perf_event_open@Base 4.9
+ __sanitizer_syscall_pre_impl_personality@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe2@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe@Base 4.9
+ __sanitizer_syscall_pre_impl_pivot_root@Base 4.9
+ __sanitizer_syscall_pre_impl_poll@Base 4.9
+ __sanitizer_syscall_pre_impl_ppoll@Base 4.9
+ __sanitizer_syscall_pre_impl_pread64@Base 4.9
+ __sanitizer_syscall_pre_impl_preadv@Base 4.9
+ __sanitizer_syscall_pre_impl_prlimit64@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_pselect6@Base 4.9
+ __sanitizer_syscall_pre_impl_ptrace@Base 4.9
+ __sanitizer_syscall_pre_impl_pwrite64@Base 4.9
+ __sanitizer_syscall_pre_impl_pwritev@Base 4.9
+ __sanitizer_syscall_pre_impl_quotactl@Base 4.9
+ __sanitizer_syscall_pre_impl_read@Base 4.9
+ __sanitizer_syscall_pre_impl_readlink@Base 4.9
+ __sanitizer_syscall_pre_impl_readlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_reboot@Base 4.9
+ __sanitizer_syscall_pre_impl_recv@Base 4.9
+ __sanitizer_syscall_pre_impl_recvfrom@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_remap_file_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_removexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_rename@Base 4.9
+ __sanitizer_syscall_pre_impl_renameat@Base 4.9
+ __sanitizer_syscall_pre_impl_request_key@Base 4.9
+ __sanitizer_syscall_pre_impl_restart_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_rmdir@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigtimedwait@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_tgsigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_max@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_min@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_rr_get_interval@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_yield@Base 4.9
+ __sanitizer_syscall_pre_impl_select@Base 4.9
+ __sanitizer_syscall_pre_impl_semctl@Base 4.9
+ __sanitizer_syscall_pre_impl_semget@Base 4.9
+ __sanitizer_syscall_pre_impl_semop@Base 4.9
+ __sanitizer_syscall_pre_impl_semtimedop@Base 4.9
+ __sanitizer_syscall_pre_impl_send@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile64@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendto@Base 4.9
+ __sanitizer_syscall_pre_impl_set_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_set_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_set_tid_address@Base 4.9
+ __sanitizer_syscall_pre_impl_setdomainname@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_sethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_setitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_setns@Base 4.9
+ __sanitizer_syscall_pre_impl_setpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_setregid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setreuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_setsid@Base 4.9
+ __sanitizer_syscall_pre_impl_setsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_settimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_setuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_sgetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_shmat@Base 4.9
+ __sanitizer_syscall_pre_impl_shmctl@Base 4.9
+ __sanitizer_syscall_pre_impl_shmdt@Base 4.9
+ __sanitizer_syscall_pre_impl_shmget@Base 4.9
+ __sanitizer_syscall_pre_impl_shutdown@Base 4.9
+ __sanitizer_syscall_pre_impl_signal@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd4@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd@Base 4.9
+ __sanitizer_syscall_pre_impl_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_socket@Base 4.9
+ __sanitizer_syscall_pre_impl_socketcall@Base 4.9
+ __sanitizer_syscall_pre_impl_socketpair@Base 4.9
+ __sanitizer_syscall_pre_impl_splice@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_create@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_run@Base 4.9
+ __sanitizer_syscall_pre_impl_ssetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_stat64@Base 4.9
+ __sanitizer_syscall_pre_impl_stat@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs@Base 4.9
+ __sanitizer_syscall_pre_impl_stime@Base 4.9
+ __sanitizer_syscall_pre_impl_swapoff@Base 4.9
+ __sanitizer_syscall_pre_impl_swapon@Base 4.9
+ __sanitizer_syscall_pre_impl_symlink@Base 4.9
+ __sanitizer_syscall_pre_impl_symlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_sync@Base 4.9
+ __sanitizer_syscall_pre_impl_syncfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysctl@Base 4.9
+ __sanitizer_syscall_pre_impl_sysfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_syslog@Base 4.9
+ __sanitizer_syscall_pre_impl_tee@Base 4.9
+ __sanitizer_syscall_pre_impl_tgkill@Base 4.9
+ __sanitizer_syscall_pre_impl_time@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_delete@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_getoverrun@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_times@Base 4.9
+ __sanitizer_syscall_pre_impl_tkill@Base 4.9
+ __sanitizer_syscall_pre_impl_truncate@Base 4.9
+ __sanitizer_syscall_pre_impl_umask@Base 4.9
+ __sanitizer_syscall_pre_impl_umount@Base 4.9
+ __sanitizer_syscall_pre_impl_uname@Base 4.9
+ __sanitizer_syscall_pre_impl_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_unlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_unshare@Base 4.9
+ __sanitizer_syscall_pre_impl_uselib@Base 4.9
+ __sanitizer_syscall_pre_impl_ustat@Base 4.9
+ __sanitizer_syscall_pre_impl_utime@Base 4.9
+ __sanitizer_syscall_pre_impl_utimensat@Base 4.9
+ __sanitizer_syscall_pre_impl_utimes@Base 4.9
+ __sanitizer_syscall_pre_impl_vfork@Base 4.9
+ __sanitizer_syscall_pre_impl_vhangup@Base 4.9
+ __sanitizer_syscall_pre_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_pre_impl_wait4@Base 4.9
+ __sanitizer_syscall_pre_impl_waitid@Base 4.9
+ __sanitizer_syscall_pre_impl_waitpid@Base 4.9
+ __sanitizer_syscall_pre_impl_write@Base 4.9
+ __sanitizer_syscall_pre_impl_writev@Base 4.9
+ __sanitizer_unaligned_load16@Base 4.9
+ __sanitizer_unaligned_load32@Base 4.9
+ __sanitizer_unaligned_load64@Base 4.9
+ __sanitizer_unaligned_store16@Base 4.9
+ __sanitizer_unaligned_store32@Base 4.9
+ __sanitizer_unaligned_store64@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6.2
+ __sanitizer_verify_contiguous_container@Base 5
+ __tls_get_addr@Base 5
+ __uflow@Base 5
+ __underflow@Base 5
+ __woverflow@Base 5
+ __wuflow@Base 5
+ __wunderflow@Base 5
+ __xpg_strerror_r@Base 4.9
+ _exit@Base 4.9
+ _longjmp@Base 4.8
+ _obstack_begin@Base 5
+ _obstack_begin_1@Base 5
+ _obstack_newchunk@Base 5
+ accept4@Base 4.9
+ accept@Base 4.9
+ aligned_alloc@Base 5
+ asctime@Base 4.8
+ asctime_r@Base 4.8
+ asprintf@Base 5
+ atoi@Base 4.8
+ atol@Base 4.8
+ atoll@Base 4.8
+ backtrace@Base 4.9
+ backtrace_symbols@Base 4.9
+ calloc@Base 4.8
+ canonicalize_file_name@Base 4.9
+ capget@Base 5
+ capset@Base 5
+ cfree@Base 4.8
+ clock_getres@Base 4.9
+ clock_gettime@Base 4.9
+ clock_settime@Base 4.9
+ confstr@Base 4.9
+ ctime@Base 4.8
+ ctime_r@Base 4.8
+ dlclose@Base 5
+ dlopen@Base 5
+ drand48_r@Base 4.9
+ endgrent@Base 5
+ endpwent@Base 5
+ ether_aton@Base 4.9
+ ether_aton_r@Base 4.9
+ ether_hostton@Base 4.9
+ ether_line@Base 4.9
+ ether_ntoa@Base 4.9
+ ether_ntoa_r@Base 4.9
+ ether_ntohost@Base 4.9
+ fclose@Base 5
+ fdopen@Base 5
+ fflush@Base 5
+ fgetgrent@Base 5
+ fgetgrent_r@Base 5
+ fgetpwent@Base 5
+ fgetpwent_r@Base 5
+ fgetxattr@Base 5
+ flistxattr@Base 5
+ fmemopen@Base 5
+ fopen64@Base 5
+ fopen@Base 5
+ fopencookie@Base 6.2
+ fork@Base 5
+ fprintf@Base 5
+ free@Base 4.8
+ freopen64@Base 5
+ freopen@Base 5
+ frexp@Base 4.9
+ frexpf@Base 4.9
+ frexpl@Base 4.9
+ fscanf@Base 4.8
+ fstatfs64@Base 4.9
+ fstatfs@Base 4.9
+ fstatvfs64@Base 4.9
+ fstatvfs@Base 4.9
+ ftime@Base 5
+ get_current_dir_name@Base 4.9
+ getaddrinfo@Base 4.9
+ getcwd@Base 4.9
+ getdelim@Base 4.9
+ getgrent@Base 5
+ getgrent_r@Base 5
+ getgrgid@Base 4.9
+ getgrgid_r@Base 4.9
+ getgrnam@Base 4.9
+ getgrnam_r@Base 4.9
+ getgroups@Base 4.9
+ gethostbyaddr@Base 4.9
+ gethostbyaddr_r@Base 4.9
+ gethostbyname2@Base 4.9
+ gethostbyname2_r@Base 4.9
+ gethostbyname@Base 4.9
+ gethostbyname_r@Base 4.9
+ gethostent@Base 4.9
+ gethostent_r@Base 4.9
+ getifaddrs@Base 5
+ getitimer@Base 4.9
+ getline@Base 4.9
+ getmntent@Base 4.9
+ getmntent_r@Base 4.9
+ getnameinfo@Base 4.9
+ getpass@Base 5
+ getpeername@Base 4.9
+ getpwent@Base 5
+ getpwent_r@Base 5
+ getpwnam@Base 4.9
+ getpwnam_r@Base 4.9
+ getpwuid@Base 4.9
+ getpwuid_r@Base 4.9
+ getresgid@Base 5
+ getresuid@Base 5
+ getsockname@Base 4.9
+ getsockopt@Base 4.9
+ getxattr@Base 5
+ glob64@Base 4.9
+ glob@Base 4.9
+ gmtime@Base 4.8
+ gmtime_r@Base 4.8
+ iconv@Base 4.9
+ if_indextoname@Base 5
+ if_nametoindex@Base 5
+ index@Base 4.8
+ inet_aton@Base 4.9
+ inet_ntop@Base 4.9
+ inet_pton@Base 4.9
+ initgroups@Base 4.9
+ ioctl@Base 4.9
+ lgamma@Base 4.9
+ lgamma_r@Base 4.9
+ lgammaf@Base 4.9
+ lgammaf_r@Base 4.9
+ lgammal@Base 4.9
+ lgammal_r@Base 4.9
+ lgetxattr@Base 5
+ listxattr@Base 5
+ llistxattr@Base 5
+ localtime@Base 4.8
+ localtime_r@Base 4.8
+ longjmp@Base 4.8
+ lrand48_r@Base 4.9
+ mallinfo@Base 4.8
+ malloc@Base 4.8
+ malloc_stats@Base 4.8
+ malloc_usable_size@Base 4.8
+ mallopt@Base 4.8
+ mbsnrtowcs@Base 4.9
+ mbsrtowcs@Base 4.9
+ mbstowcs@Base 4.9
+ memalign@Base 4.8
+ memchr@Base 5
+ memcmp@Base 4.8
+ memcpy@Base 4.8
+ memmove@Base 4.8
+ memrchr@Base 5
+ memset@Base 4.8
+ mincore@Base 6.2
+ mktime@Base 5
+ mlock@Base 4.8
+ mlockall@Base 4.8
+ modf@Base 4.9
+ modff@Base 4.9
+ modfl@Base 4.9
+ munlock@Base 4.8
+ munlockall@Base 4.8
+ open_memstream@Base 5
+ open_wmemstream@Base 5
+ opendir@Base 6.2
+ poll@Base 4.9
+ posix_memalign@Base 4.8
+ ppoll@Base 4.9
+ prctl@Base 4.8
+ pread64@Base 4.8
+ pread@Base 4.8
+ preadv64@Base 4.9
+ preadv@Base 4.9
+ printf@Base 5
+ process_vm_readv@Base 6.2
+ process_vm_writev@Base 6.2
+ pthread_attr_getaffinity_np@Base 4.9
+ pthread_attr_getdetachstate@Base 4.9
+ pthread_attr_getguardsize@Base 4.9
+ pthread_attr_getinheritsched@Base 4.9
+ pthread_attr_getschedparam@Base 4.9
+ pthread_attr_getschedpolicy@Base 4.9
+ pthread_attr_getscope@Base 4.9
+ pthread_attr_getstack@Base 4.9
+ pthread_attr_getstacksize@Base 4.9
+ pthread_barrierattr_getpshared@Base 5
+ pthread_condattr_getclock@Base 5
+ pthread_condattr_getpshared@Base 5
+ pthread_create@Base 4.8
+ pthread_getschedparam@Base 4.9
+ pthread_join@Base 6.2
+ pthread_mutex_lock@Base 4.9
+ pthread_mutex_unlock@Base 4.9
+ pthread_mutexattr_getprioceiling@Base 5
+ pthread_mutexattr_getprotocol@Base 5
+ pthread_mutexattr_getpshared@Base 5
+ pthread_mutexattr_getrobust@Base 5
+ pthread_mutexattr_getrobust_np@Base 5
+ pthread_mutexattr_gettype@Base 5
+ pthread_rwlockattr_getkind_np@Base 5
+ pthread_rwlockattr_getpshared@Base 5
+ pthread_setcancelstate@Base 6.2
+ pthread_setcanceltype@Base 6.2
+ pthread_setname_np@Base 4.9
+ pvalloc@Base 4.8
+ pwrite64@Base 4.8
+ pwrite@Base 4.8
+ pwritev64@Base 4.9
+ pwritev@Base 4.9
+ rand_r@Base 5
+ random_r@Base 4.9
+ read@Base 4.8
+ readdir64@Base 4.9
+ readdir64_r@Base 4.9
+ readdir@Base 4.9
+ readdir_r@Base 4.9
+ readv@Base 4.9
+ realloc@Base 4.8
+ realpath@Base 4.9
+ recvmsg@Base 4.9
+ remquo@Base 4.9
+ remquof@Base 4.9
+ remquol@Base 4.9
+ scandir64@Base 4.9
+ scandir@Base 4.9
+ scanf@Base 4.8
+ sched_getaffinity@Base 4.9
+ sched_getparam@Base 6.2
+ sem_destroy@Base 6.2
+ sem_getvalue@Base 6.2
+ sem_init@Base 6.2
+ sem_post@Base 6.2
+ sem_timedwait@Base 6.2
+ sem_trywait@Base 6.2
+ sem_wait@Base 6.2
+ setgrent@Base 5
+ setitimer@Base 4.9
+ setlocale@Base 4.9
+ setpwent@Base 5
+ sigaction@Base 4.8
+ sigemptyset@Base 4.9
+ sigfillset@Base 4.9
+ siglongjmp@Base 4.8
+ signal@Base 4.8
+ sigpending@Base 4.9
+ sigprocmask@Base 4.9
+ sigtimedwait@Base 4.9
+ sigwait@Base 4.9
+ sigwaitinfo@Base 4.9
+ sincos@Base 4.9
+ sincosf@Base 4.9
+ sincosl@Base 4.9
+ snprintf@Base 5
+ sprintf@Base 5
+ sscanf@Base 4.8
+ statfs64@Base 4.9
+ statfs@Base 4.9
+ statvfs64@Base 4.9
+ statvfs@Base 4.9
+ strcasecmp@Base 4.8
+ strcasestr@Base 6.2
+ strcat@Base 4.8
+ strchr@Base 4.8
+ strcmp@Base 4.8
+ strcpy@Base 4.8
+ strcspn@Base 6.2
+ strdup@Base 4.8
+ strerror@Base 4.9
+ strerror_r@Base 4.9
+ strlen@Base 4.8
+ strncasecmp@Base 4.8
+ strncat@Base 4.8
+ strncmp@Base 4.8
+ strncpy@Base 4.8
+ strnlen@Base 4.8
+ strpbrk@Base 6.2
+ strptime@Base 4.9
+ strspn@Base 6.2
+ strstr@Base 6.2
+ strtoimax@Base 4.9
+ strtol@Base 4.8
+ strtoll@Base 4.8
+ strtoumax@Base 4.9
+ swapcontext@Base 4.8
+ sysinfo@Base 4.9
+ tcgetattr@Base 4.9
+ tempnam@Base 4.9
+ textdomain@Base 4.9
+ time@Base 4.9
+ timerfd_gettime@Base 5
+ timerfd_settime@Base 5
+ times@Base 4.9
+ tmpnam@Base 4.9
+ tmpnam_r@Base 4.9
+ tsearch@Base 5
+ valloc@Base 4.8
+ vasprintf@Base 5
+ vfprintf@Base 5
+ vfscanf@Base 4.8
+ vprintf@Base 5
+ vscanf@Base 4.8
+ vsnprintf@Base 5
+ vsprintf@Base 5
+ vsscanf@Base 4.8
+ wait3@Base 4.9
+ wait4@Base 4.9
+ wait@Base 4.9
+ waitid@Base 4.9
+ waitpid@Base 4.9
+ wcrtomb@Base 6.2
+ wcslen@Base 4.9
+ wcsnrtombs@Base 4.9
+ wcsrtombs@Base 4.9
+ wcstombs@Base 4.9
+ wordexp@Base 4.9
+ write@Base 4.8
+ writev@Base 4.9
+ xdr_bool@Base 5
+ xdr_bytes@Base 5
+ xdr_char@Base 5
+ xdr_double@Base 5
+ xdr_enum@Base 5
+ xdr_float@Base 5
+ xdr_hyper@Base 5
+ xdr_int16_t@Base 5
+ xdr_int32_t@Base 5
+ xdr_int64_t@Base 5
+ xdr_int8_t@Base 5
+ xdr_int@Base 5
+ xdr_long@Base 5
+ xdr_longlong_t@Base 5
+ xdr_quad_t@Base 5
+ xdr_short@Base 5
+ xdr_string@Base 5
+ xdr_u_char@Base 5
+ xdr_u_hyper@Base 5
+ xdr_u_int@Base 5
+ xdr_u_long@Base 5
+ xdr_u_longlong_t@Base 5
+ xdr_u_quad_t@Base 5
+ xdr_u_short@Base 5
+ xdr_uint16_t@Base 5
+ xdr_uint32_t@Base 5
+ xdr_uint64_t@Base 5
+ xdr_uint8_t@Base 5
+ xdrmem_create@Base 5
+ xdrstdio_create@Base 5
--- gcc-6-6.3.0.orig/debian/libasan3.symbols
+++ gcc-6-6.3.0/debian/libasan3.symbols
@@ -0,0 +1,20 @@
+libasan.so.3 libasan3 #MINVER#
+#include "libasan.symbols.common"
+(arch=!arm64 !alpha !amd64 !ia64 !ppc64 !ppc64el !s390x !sparc64 !kfreebsd-amd64)#include "libasan.symbols.32"
+(arch=arm64 alpha amd64 ia64 ppc64 ppc64el s390x sparc64 kfreebsd-amd64)#include "libasan.symbols.64"
+(arch=armel armhf sparc64 x32)#include "libasan.symbols.16"
+# these are missing on some archs ...
+ (arch=!arm64 !armel !armhf !i386 !powerpc !ppc64 !ppc64el !sparc !sparc64)__interceptor_ptrace@Base 4.9
+ (arch=!arm64 !armel !armhf !i386 !powerpc !ppc64 !ppc64el !sparc !sparc64)ptrace@Base 4.9
+ (arch=armel armhf)__interceptor___aeabi_memclr4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memclr8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memclr@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memcpy4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memcpy8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memcpy@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memmove4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memmove8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memmove@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memset4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memset8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memset@Base 5
--- gcc-6-6.3.0.orig/debian/libatomic.symbols
+++ gcc-6-6.3.0/debian/libatomic.symbols
@@ -0,0 +1,4 @@
+libatomic.so.1 #PACKAGE# #MINVER#
+ (symver)LIBATOMIC_1.0 4.8
+ (symver)LIBATOMIC_1.1 4.9
+ (symver)LIBATOMIC_1.2 6
--- gcc-6-6.3.0.orig/debian/libcc1-0.symbols
+++ gcc-6-6.3.0/debian/libcc1-0.symbols
@@ -0,0 +1,61 @@
+libcc1.so.0 libcc1-0 #MINVER#
+ (optional=abi_c++98)_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag@Base 5
+ (optional=abi_c++98)_ZNSt6vectorISsSaISsEE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPSsS1_EERKSs@Base 5
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEEvDpOT_@Base 6
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS5_S7_EERKS5_@Base 5
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE19_M_emplace_back_auxIJRKS5_EEEvDpOT_@Base 6
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE19_M_emplace_back_auxIJS5_EEEvDpOT_@Base 6
+ _xexit_cleanup@Base 5
+ concat@Base 5
+ concat_copy2@Base 5
+ concat_copy@Base 5
+ concat_length@Base 5
+ gcc_c_fe_context@Base 5
+ htab_clear_slot@Base 5
+ htab_collisions@Base 5
+ htab_create@Base 5
+ htab_create_alloc@Base 5
+ htab_create_alloc_ex@Base 5
+ htab_create_typed_alloc@Base 5
+ htab_delete@Base 5
+ htab_elements@Base 5
+ htab_empty@Base 5
+ htab_eq_pointer@Base 5
+ htab_find@Base 5
+ htab_find_slot@Base 5
+ htab_find_slot_with_hash@Base 5
+ htab_find_with_hash@Base 5
+ htab_hash_pointer@Base 5
+ htab_hash_string@Base 5
+ htab_remove_elt@Base 5
+ htab_remove_elt_with_hash@Base 5
+ htab_set_functions_ex@Base 5
+ htab_size@Base 5
+ htab_traverse@Base 5
+ htab_traverse_noresize@Base 5
+ htab_try_create@Base 5
+ iterative_hash@Base 5
+ libiberty_concat_ptr@Base 5
+ reconcat@Base 5
+ xcalloc@Base 5
+ xexit@Base 5
+ xmalloc@Base 5
+ xmalloc_failed@Base 5
+ xmalloc_set_program_name@Base 5
+ xre_comp@Base 5
+ xre_compile_fastmap@Base 5
+ xre_compile_pattern@Base 5
+ xre_exec@Base 5
+ xre_match@Base 5
+ xre_match_2@Base 5
+ xre_max_failures@Base 5
+ xre_search@Base 5
+ xre_search_2@Base 5
+ xre_set_registers@Base 5
+ xre_set_syntax@Base 5
+ xre_syntax_options@Base 5
+ xrealloc@Base 5
+ xregcomp@Base 5
+ xregerror@Base 5
+ xregexec@Base 5
+ xregfree@Base 5
--- gcc-6-6.3.0.orig/debian/libcilkrts.symbols
+++ gcc-6-6.3.0/debian/libcilkrts.symbols
@@ -0,0 +1,4 @@
+libcilkrts.so.5 #PACKAGE# #MINVER#
+ (symver)CILKABI0 4.9
+ (symver)CILKABI1 4.9
+ (symver)CILKLIB1.02 4.9
--- gcc-6-6.3.0.orig/debian/libgcc.symbols
+++ gcc-6-6.3.0/debian/libgcc.symbols
@@ -0,0 +1,25 @@
+libgcc_s.so.1 #PACKAGE# #MINVER#
+ (symver)GCC_3.0 1:3.0
+ (symver)GCC_3.3 1:3.3
+ (symver)GCC_3.3.1 1:3.3.1
+# __gcc_personality_sj0, __gcc_personality_v0
+#(symver|optional)GCC_3.3.2 1:3.3.2
+ (symver|arch=armel armhf mips mipsel mips64el powerpc powerpcspe sh4)GCC_3.3.4 1:3.3.4
+ (symver)GCC_3.4 1:3.4
+ (symver)GCC_3.4.2 1:3.4.2
+#(symver|arch-bits=32)GCC_3.4.4 1:3.4.4
+ (symver|arch=!armel !armhf !any-i386 !mips !mipsel !powerpc !powerpcspe !s390 !sh4 !sparc)GCC_3.4.4 1:3.4.4
+ (symver|arch=armel armhf|ignore-blacklist)GCC_3.5 1:3.5
+ (symver)GCC_4.0.0 1:4.0
+ (symver|arch=powerpc)GCC_4.1.0 1:4.1
+ (symver)GCC_4.2.0 1:4.2
+ (symver)GCC_4.3.0 1:4.3
+ (symver|arch=any-i386 mips mipsel mips64el)GCC_4.4.0 1:4.4
+ (symver|arch=arm64 any-i386 mips64el)GCC_4.5.0 1:4.5
+#(symver|optional)GCC_4.6.0 1:4.6
+ (symver)GCC_4.7.0 1:4.7
+ (symver|arch=any-amd64 any-i386 x32)GCC_4.8.0 1:4.8
+ (symver|arch=!any-amd64 !x32)GLIBC_2.0 1:4.2
+ (symver|arch=s390x sh4 sparc64)GLIBC_2.2 1:4.2
+ (symver|arch=sparc)GCC_LDBL_3.0@GCC_LDBL_3.0 1:3.0
+ (symver|arch=alpha sparc)GCC_LDBL_4.0.0@GCC_LDBL_4.0.0 1:4.0
--- gcc-6-6.3.0.orig/debian/libgcc.symbols.aeabi
+++ gcc-6-6.3.0/debian/libgcc.symbols.aeabi
@@ -0,0 +1,69 @@
+ __aeabi_cdcmpeq@GCC_3.5 1:3.5
+ __aeabi_cdcmple@GCC_3.5 1:3.5
+ __aeabi_cdrcmple@GCC_3.5 1:3.5
+ __aeabi_cfcmpeq@GCC_3.5 1:3.5
+ __aeabi_cfcmple@GCC_3.5 1:3.5
+ __aeabi_cfrcmple@GCC_3.5 1:3.5
+ __aeabi_d2f@GCC_3.5 1:3.5
+ __aeabi_d2iz@GCC_3.5 1:3.5
+ __aeabi_d2lz@GCC_3.5 1:3.5
+ __aeabi_d2uiz@GCC_3.5 1:3.5
+ __aeabi_d2ulz@GCC_3.5 1:3.5
+ __aeabi_dadd@GCC_3.5 1:3.5
+ __aeabi_dcmpeq@GCC_3.5 1:3.5
+ __aeabi_dcmpge@GCC_3.5 1:3.5
+ __aeabi_dcmpgt@GCC_3.5 1:3.5
+ __aeabi_dcmple@GCC_3.5 1:3.5
+ __aeabi_dcmplt@GCC_3.5 1:3.5
+ __aeabi_dcmpun@GCC_3.5 1:3.5
+ __aeabi_ddiv@GCC_3.5 1:3.5
+ __aeabi_dmul@GCC_3.5 1:3.5
+ __aeabi_dneg@GCC_3.5 1:3.5
+ __aeabi_drsub@GCC_3.5 1:3.5
+ __aeabi_dsub@GCC_3.5 1:3.5
+ __aeabi_f2d@GCC_3.5 1:3.5
+ __aeabi_f2iz@GCC_3.5 1:3.5
+ __aeabi_f2lz@GCC_3.5 1:3.5
+ __aeabi_f2uiz@GCC_3.5 1:3.5
+ __aeabi_f2ulz@GCC_3.5 1:3.5
+ __aeabi_fadd@GCC_3.5 1:3.5
+ __aeabi_fcmpeq@GCC_3.5 1:3.5
+ __aeabi_fcmpge@GCC_3.5 1:3.5
+ __aeabi_fcmpgt@GCC_3.5 1:3.5
+ __aeabi_fcmple@GCC_3.5 1:3.5
+ __aeabi_fcmplt@GCC_3.5 1:3.5
+ __aeabi_fcmpun@GCC_3.5 1:3.5
+ __aeabi_fdiv@GCC_3.5 1:3.5
+ __aeabi_fmul@GCC_3.5 1:3.5
+ __aeabi_fneg@GCC_3.5 1:3.5
+ __aeabi_frsub@GCC_3.5 1:3.5
+ __aeabi_fsub@GCC_3.5 1:3.5
+ __aeabi_i2d@GCC_3.5 1:3.5
+ __aeabi_i2f@GCC_3.5 1:3.5
+ __aeabi_idiv@GCC_3.5 1:3.5
+ __aeabi_idiv0@GCC_3.5 1:4.5.0
+ __aeabi_idivmod@GCC_3.5 1:3.5
+ __aeabi_l2d@GCC_3.5 1:3.5
+ __aeabi_l2f@GCC_3.5 1:3.5
+ __aeabi_lasr@GCC_3.5 1:3.5
+ __aeabi_lcmp@GCC_3.5 1:3.5
+ __aeabi_ldivmod@GCC_3.5 1:3.5
+ __aeabi_ldiv0@GCC_3.5 1:4.5.0
+ __aeabi_llsl@GCC_3.5 1:3.5
+ __aeabi_llsr@GCC_3.5 1:3.5
+ __aeabi_lmul@GCC_3.5 1:3.5
+ __aeabi_ui2d@GCC_3.5 1:3.5
+ __aeabi_ui2f@GCC_3.5 1:3.5
+ __aeabi_uidiv@GCC_3.5 1:3.5
+ __aeabi_uidivmod@GCC_3.5 1:3.5
+ __aeabi_ul2d@GCC_3.5 1:3.5
+ __aeabi_ul2f@GCC_3.5 1:3.5
+ __aeabi_ulcmp@GCC_3.5 1:3.5
+ __aeabi_uldivmod@GCC_3.5 1:3.5
+ __aeabi_unwind_cpp_pr0@GCC_3.5 1:3.5
+ __aeabi_unwind_cpp_pr1@GCC_3.5 1:3.5
+ __aeabi_unwind_cpp_pr2@GCC_3.5 1:3.5
+ __aeabi_uread4@GCC_3.5 1:3.5
+ __aeabi_uread8@GCC_3.5 1:3.5
+ __aeabi_uwrite4@GCC_3.5 1:3.5
+ __aeabi_uwrite8@GCC_3.5 1:3.5
--- gcc-6-6.3.0.orig/debian/libgcc2.symbols.m68k
+++ gcc-6-6.3.0/debian/libgcc2.symbols.m68k
@@ -0,0 +1,162 @@
+libgcc_s.so.2 libgcc2 #MINVER#
+ GCC_3.0@GCC_3.0 4.2.1
+ GCC_3.3.1@GCC_3.3.1 4.2.1
+ GCC_3.3.4@GCC_3.3.4 4.4.5
+ GCC_3.3@GCC_3.3 4.2.1
+ GCC_3.4.2@GCC_3.4.2 4.2.1
+ GCC_3.4@GCC_3.4 4.2.1
+ GCC_4.0.0@GCC_4.0.0 4.2.1
+ GCC_4.2.0@GCC_4.2.0 4.2.1
+ GCC_4.3.0@GCC_4.3.0 4.3.0
+ GCC_4.5.0@GCC_4.5.0 4.5
+ GCC_4.7.0@GCC_4.7.0 4.7
+ GLIBC_2.0@GLIBC_2.0 4.2.1
+ _Unwind_Backtrace@GCC_3.3 4.2.1
+ _Unwind_DeleteException@GCC_3.0 4.2.1
+ _Unwind_FindEnclosingFunction@GCC_3.3 4.2.1
+ _Unwind_Find_FDE@GCC_3.0 4.2.1
+ _Unwind_ForcedUnwind@GCC_3.0 4.2.1
+ _Unwind_GetCFA@GCC_3.3 4.2.1
+ _Unwind_GetDataRelBase@GCC_3.0 4.2.1
+ _Unwind_GetGR@GCC_3.0 4.2.1
+ _Unwind_GetIP@GCC_3.0 4.2.1
+ _Unwind_GetIPInfo@GCC_4.2.0 4.2.1
+ _Unwind_GetLanguageSpecificData@GCC_3.0 4.2.1
+ _Unwind_GetRegionStart@GCC_3.0 4.2.1
+ _Unwind_GetTextRelBase@GCC_3.0 4.2.1
+ _Unwind_RaiseException@GCC_3.0 4.2.1
+ _Unwind_Resume@GCC_3.0 4.2.1
+ _Unwind_Resume_or_Rethrow@GCC_3.3 4.2.1
+ _Unwind_SetGR@GCC_3.0 4.2.1
+ _Unwind_SetIP@GCC_3.0 4.2.1
+ __absvdi2@GCC_3.0 4.2.1
+ __absvsi2@GCC_3.0 4.2.1
+ __adddf3@GCC_3.0 4.4.5
+ __addsf3@GCC_3.0 4.4.5
+ __addvdi3@GCC_3.0 4.2.1
+ __addvsi3@GCC_3.0 4.2.1
+ __addxf3@GCC_3.0 4.4.5
+ __ashldi3@GCC_3.0 4.2.1
+ __ashrdi3@GCC_3.0 4.2.1
+ __bswapdi2@GCC_4.3.0 4.3.0
+ __bswapsi2@GCC_4.3.0 4.3.0
+ __clear_cache@GCC_3.0 4.2.1
+  __clrsbdi2@GCC_4.7.0 4.7
+  __clrsbsi2@GCC_4.7.0 4.7
+ __clzdi2@GCC_3.4 4.2.1
+ __clzsi2@GCC_3.4 4.2.1
+ __cmpdi2@GCC_3.0 4.2.1
+ __ctzdi2@GCC_3.4 4.2.1
+ __ctzsi2@GCC_3.4 4.2.1
+ __deregister_frame@GLIBC_2.0 4.2.1
+ __deregister_frame_info@GLIBC_2.0 4.2.1
+ __deregister_frame_info_bases@GCC_3.0 4.2.1
+ __divdc3@GCC_4.0.0 4.2.1
+ __divdf3@GCC_3.0 4.4.5
+ __divdi3@GLIBC_2.0 4.2.1
+ __divsc3@GCC_4.0.0 4.2.1
+ __divsf3@GCC_3.0 4.4.5
+ __divsi3@GCC_3.0 4.4.5
+ __divxc3@GCC_4.0.0 4.2.1
+ __divxf3@GCC_3.0 4.4.5
+ __emutls_get_address@GCC_4.3.0 4.3.0
+ __emutls_register_common@GCC_4.3.0 4.3.0
+ __enable_execute_stack@GCC_3.4.2 4.2.1
+ __eqdf2@GCC_3.0 4.4.5
+ __eqsf2@GCC_3.0 4.4.5
+ __eqxf2@GCC_3.0 4.4.5
+ __extenddfxf2@GCC_3.0 4.4.5
+ __extendsfdf2@GCC_3.0 4.4.5
+ __extendsfxf2@GCC_3.0 4.4.5
+ __ffsdi2@GCC_3.0 4.2.1
+ __ffssi2@GCC_4.3.0 4.3.0
+ __fixdfdi@GCC_3.0 4.2.1
+ __fixdfsi@GCC_3.0 4.4.5
+ __fixsfdi@GCC_3.0 4.2.1
+ __fixsfsi@GCC_3.0 4.4.5
+ __fixunsdfdi@GCC_3.0 4.2.1
+ __fixunsdfsi@GCC_3.0 4.2.1
+ __fixunssfdi@GCC_3.0 4.2.1
+ __fixunssfsi@GCC_3.0 4.2.1
+ __fixunsxfdi@GCC_3.0 4.2.1
+ __fixunsxfsi@GCC_3.0 4.2.1
+ __fixxfdi@GCC_3.0 4.2.1
+ __fixxfsi@GCC_3.0 4.4.5
+ __floatdidf@GCC_3.0 4.2.1
+ __floatdisf@GCC_3.0 4.2.1
+ __floatdixf@GCC_3.0 4.2.1
+ __floatsidf@GCC_3.0 4.4.5
+ __floatsisf@GCC_3.0 4.4.5
+ __floatsixf@GCC_3.0 4.4.5
+ __floatundidf@GCC_4.2.0 4.2.1
+ __floatundisf@GCC_4.2.0 4.2.1
+ __floatundixf@GCC_4.2.0 4.2.1
+ __floatunsidf@GCC_4.2.0 4.4.5
+ __floatunsisf@GCC_4.2.0 4.4.5
+ __floatunsixf@GCC_4.2.0 4.4.5
+ __frame_state_for@GLIBC_2.0 4.2.1
+ __gcc_personality_v0@GCC_3.3.1 4.2.1
+ __gedf2@GCC_3.0 4.4.5
+ __gesf2@GCC_3.0 4.4.5
+ __gexf2@GCC_3.0 4.4.5
+ __gtdf2@GCC_3.0 4.4.5
+ __gtsf2@GCC_3.0 4.4.5
+ __gtxf2@GCC_3.0 4.4.5
+ __ledf2@GCC_3.0 4.4.5
+ __lesf2@GCC_3.0 4.4.5
+ __lexf2@GCC_3.0 4.4.5
+ __lshrdi3@GCC_3.0 4.2.1
+ __ltdf2@GCC_3.0 4.4.5
+ __ltsf2@GCC_3.0 4.4.5
+ __ltxf2@GCC_3.0 4.4.5
+ __moddi3@GLIBC_2.0 4.2.1
+ __modsi3@GCC_3.0 4.4.5
+ __muldc3@GCC_4.0.0 4.2.1
+ __muldf3@GCC_3.0 4.4.5
+ __muldi3@GCC_3.0 4.2.1
+ __mulsc3@GCC_4.0.0 4.2.1
+ __mulsf3@GCC_3.0 4.4.5
+ __mulsi3@GCC_3.0 4.4.5
+ __mulvdi3@GCC_3.0 4.2.1
+ __mulvsi3@GCC_3.0 4.2.1
+ __mulxc3@GCC_4.0.0 4.2.1
+ __mulxf3@GCC_3.0 4.4.5
+ __nedf2@GCC_3.0 4.4.5
+ __negdf2@GCC_3.0 4.4.5
+ __negdi2@GCC_3.0 4.2.1
+ __negsf2@GCC_3.0 4.4.5
+ __negvdi2@GCC_3.0 4.2.1
+ __negvsi2@GCC_3.0 4.2.1
+ __negxf2@GCC_3.0 4.4.5
+ __nesf2@GCC_3.0 4.4.5
+ __nexf2@GCC_3.0 4.4.5
+ __paritydi2@GCC_3.4 4.2.1
+ __paritysi2@GCC_3.4 4.2.1
+ __popcountdi2@GCC_3.4 4.2.1
+ __popcountsi2@GCC_3.4 4.2.1
+ __powidf2@GCC_4.0.0 4.2.1
+ __powisf2@GCC_4.0.0 4.2.1
+ __powixf2@GCC_4.0.0 4.2.1
+ __register_frame@GLIBC_2.0 4.2.1
+ __register_frame_info@GLIBC_2.0 4.2.1
+ __register_frame_info_bases@GCC_3.0 4.2.1
+ __register_frame_info_table@GLIBC_2.0 4.2.1
+ __register_frame_info_table_bases@GCC_3.0 4.2.1
+ __register_frame_table@GLIBC_2.0 4.2.1
+ __subdf3@GCC_3.0 4.4.5
+ __subsf3@GCC_3.0 4.4.5
+ __subvdi3@GCC_3.0 4.2.1
+ __subvsi3@GCC_3.0 4.2.1
+ __subxf3@GCC_3.0 4.4.5
+ __truncdfsf2@GCC_3.0 4.4.5
+ __truncxfdf2@GCC_3.0 4.4.5
+ __truncxfsf2@GCC_3.0 4.4.5
+ __ucmpdi2@GCC_3.0 4.2.1
+ __udivdi3@GLIBC_2.0 4.2.1
+ __udivmoddi4@GCC_3.0 4.2.1
+ __udivsi3@GCC_3.0 4.4.5
+ __umoddi3@GLIBC_2.0 4.2.1
+ __umodsi3@GCC_3.0 4.4.5
+ __unorddf2@GCC_3.3.4 4.4.5
+ __unordsf2@GCC_3.3.4 4.4.5
+ __unordxf2@GCC_4.5.0 4.7
--- gcc-6-6.3.0.orig/debian/libgcc4.symbols.hppa
+++ gcc-6-6.3.0/debian/libgcc4.symbols.hppa
@@ -0,0 +1,96 @@
+libgcc_s.so.4 libgcc4 #MINVER#
+ GCC_3.0@GCC_3.0 4.1.1
+ GCC_3.3.1@GCC_3.3.1 4.1.1
+ GCC_3.3@GCC_3.3 4.1.1
+ GCC_3.4.2@GCC_3.4.2 4.1.1
+ GCC_3.4@GCC_3.4 4.1.1
+ GCC_4.0.0@GCC_4.0.0 4.1.1
+ GCC_4.2.0@GCC_4.2.0 4.1.1
+ GCC_4.3.0@GCC_4.3.0 4.3
+ GCC_4.7.0@GCC_4.7.0 1:4.7
+ GLIBC_2.0@GLIBC_2.0 4.1.1
+ _Unwind_Backtrace@GCC_3.3 4.1.1
+ _Unwind_DeleteException@GCC_3.0 4.1.1
+ _Unwind_FindEnclosingFunction@GCC_3.3 4.1.1
+ _Unwind_Find_FDE@GCC_3.0 4.1.1
+ _Unwind_ForcedUnwind@GCC_3.0 4.1.1
+ _Unwind_GetCFA@GCC_3.3 4.1.1
+ _Unwind_GetDataRelBase@GCC_3.0 4.1.1
+ _Unwind_GetGR@GCC_3.0 4.1.1
+ _Unwind_GetIP@GCC_3.0 4.1.1
+ _Unwind_GetIPInfo@GCC_4.2.0 4.1.1
+ _Unwind_GetLanguageSpecificData@GCC_3.0 4.1.1
+ _Unwind_GetRegionStart@GCC_3.0 4.1.1
+ _Unwind_GetTextRelBase@GCC_3.0 4.1.1
+ _Unwind_RaiseException@GCC_3.0 4.1.1
+ _Unwind_Resume@GCC_3.0 4.1.1
+ _Unwind_Resume_or_Rethrow@GCC_3.3 4.1.1
+ _Unwind_SetGR@GCC_3.0 4.1.1
+ _Unwind_SetIP@GCC_3.0 4.1.1
+ __absvdi2@GCC_3.0 4.1.1
+ __absvsi2@GCC_3.0 4.1.1
+ __addvdi3@GCC_3.0 4.1.1
+ __addvsi3@GCC_3.0 4.1.1
+ __ashldi3@GCC_3.0 4.1.1
+ __ashrdi3@GCC_3.0 4.1.1
+ __bswapdi2@GCC_4.3.0 4.3
+ __bswapsi2@GCC_4.3.0 4.3
+ __clear_cache@GCC_3.0 4.1.1
+ __clrsbdi2@GCC_4.7.0 4.7
+ __clrsbsi2@GCC_4.7.0 4.7
+ __clzdi2@GCC_3.4 4.1.1
+ __clzsi2@GCC_3.4 4.1.1
+ __cmpdi2@GCC_3.0 4.1.1
+ __ctzdi2@GCC_3.4 4.1.1
+ __ctzsi2@GCC_3.4 4.1.1
+ __deregister_frame@GLIBC_2.0 4.1.1
+ __deregister_frame_info@GLIBC_2.0 4.1.1
+ __deregister_frame_info_bases@GCC_3.0 4.1.1
+ __divdc3@GCC_4.0.0 4.1.1
+ __divdi3@GLIBC_2.0 4.1.1
+ __divsc3@GCC_4.0.0 4.1.1
+ __emutls_get_address@GCC_4.3.0 4.3
+ __emutls_register_common@GCC_4.3.0 4.3
+ __enable_execute_stack@GCC_3.4.2 4.1.1
+ __ffsdi2@GCC_3.0 4.1.1
+ __ffssi2@GCC_4.3.0 4.3
+ __fixdfdi@GCC_3.0 4.1.1
+ __fixsfdi@GCC_3.0 4.1.1
+ __fixunsdfdi@GCC_3.0 4.1.1
+ __fixunsdfsi@GCC_3.0 4.1.1
+ __fixunssfdi@GCC_3.0 4.1.1
+ __fixunssfsi@GCC_3.0 4.1.1
+ __floatdidf@GCC_3.0 4.1.1
+ __floatdisf@GCC_3.0 4.1.1
+ __floatundidf@GCC_4.2.0 4.2.1
+ __floatundisf@GCC_4.2.0 4.2.1
+ __frame_state_for@GLIBC_2.0 4.1.1
+ __gcc_personality_v0@GCC_3.3.1 4.1.1
+ __lshrdi3@GCC_3.0 4.1.1
+ __moddi3@GLIBC_2.0 4.1.1
+ __muldc3@GCC_4.0.0 4.1.1
+ __muldi3@GCC_3.0 4.1.1
+ __mulsc3@GCC_4.0.0 4.1.1
+ __mulvdi3@GCC_3.0 4.1.1
+ __mulvsi3@GCC_3.0 4.1.1
+ __negdi2@GCC_3.0 4.1.1
+ __negvdi2@GCC_3.0 4.1.1
+ __negvsi2@GCC_3.0 4.1.1
+ __paritydi2@GCC_3.4 4.1.1
+ __paritysi2@GCC_3.4 4.1.1
+ __popcountdi2@GCC_3.4 4.1.1
+ __popcountsi2@GCC_3.4 4.1.1
+ __powidf2@GCC_4.0.0 4.1.1
+ __powisf2@GCC_4.0.0 4.1.1
+ __register_frame@GLIBC_2.0 4.1.1
+ __register_frame_info@GLIBC_2.0 4.1.1
+ __register_frame_info_bases@GCC_3.0 4.1.1
+ __register_frame_info_table@GLIBC_2.0 4.1.1
+ __register_frame_info_table_bases@GCC_3.0 4.1.1
+ __register_frame_table@GLIBC_2.0 4.1.1
+ __subvdi3@GCC_3.0 4.1.1
+ __subvsi3@GCC_3.0 4.1.1
+ __ucmpdi2@GCC_3.0 4.1.1
+ __udivdi3@GLIBC_2.0 4.1.1
+ __udivmoddi4@GCC_3.0 4.1.1
+ __umoddi3@GLIBC_2.0 4.1.1
--- gcc-6-6.3.0.orig/debian/libgccLC.postinst
+++ gcc-6-6.3.0/debian/libgccLC.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libgcc@LC@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libgccjit0.symbols
+++ gcc-6-6.3.0/debian/libgccjit0.symbols
@@ -0,0 +1,7 @@
+libgccjit.so.0 #PACKAGE# #MINVER#
+ (symver)LIBGCCJIT_ABI_0 5.1
+ (symver)LIBGCCJIT_ABI_1 5.1
+ (symver)LIBGCCJIT_ABI_2 5.1
+ (symver)LIBGCCJIT_ABI_3 5.1
+ (symver)LIBGCCJIT_ABI_4 6
+ (symver)LIBGCCJIT_ABI_5 6
--- gcc-6-6.3.0.orig/debian/libgcj-common.postinst
+++ gcc-6-6.3.0/debian/libgcj-common.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libgcj-common
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcj-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libgcj-common.preinst
+++ gcc-6-6.3.0/debian/libgcj-common.preinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    upgrade|install)
+	if [ -n "$2" ] && [ -h /usr/share/doc/libgcj-common ] \
+	   && dpkg --compare-versions "$2" lt 1:4.0.2-10
+	then
+	    rm -f /usr/share/doc/libgcj-common
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libgcj-doc.doc-base
+++ gcc-6-6.3.0/debian/libgcj-doc.doc-base
@@ -0,0 +1,10 @@
+Document: libgcj-doc
+Title: The GNU LibGCJ Classpath library
+Author: Various
+Abstract: Autogenerated documentation describing the libgcj
+ library (GCC 5), based on the classpath library.
+Section: Programming/Java
+
+Format: html
+Index: /usr/share/doc/gcc-6-base/api/index.html
+Files: /usr/share/doc/gcc-6-base/api/*.html
--- gcc-6-6.3.0.orig/debian/libgcjGCJ-awt.overrides
+++ gcc-6-6.3.0/debian/libgcjGCJ-awt.overrides
@@ -0,0 +1,2 @@
+# pick up the exact version, in case another gcj version is installed
+libgcj@GCJ@-awt binary: binary-or-shlib-defines-rpath
--- gcc-6-6.3.0.orig/debian/libgcjGCJ-dev.overrides
+++ gcc-6-6.3.0/debian/libgcjGCJ-dev.overrides
@@ -0,0 +1 @@
+libgcj@GCJ@-dev binary: library-not-linked-against-libc
--- gcc-6-6.3.0.orig/debian/libgcjGCJ.overrides
+++ gcc-6-6.3.0/debian/libgcjGCJ.overrides
@@ -0,0 +1,9 @@
+# pick up the exact version, in case another gcj version is installed
+libgcj@GCJ@ binary: binary-or-shlib-defines-rpath
+
+# intended
+libgcj@GCJ@ binary: unused-shlib-entry-in-control-file
+libgcj@GCJ@ binary: shlibs-declares-dependency-on-other-package
+
+# keep patched ltdl copy
+libgcj@GCJ@ binary: embedded-library
--- gcc-6-6.3.0.orig/debian/libgcjLGCJ.postinst
+++ gcc-6-6.3.0/debian/libgcjLGCJ.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libgcj@GCJ@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	  rm -rf /usr/share/doc/libgcj@GCJ@
+	  ln -s gcj-@BV@-base /usr/share/doc/libgcj@GCJ@
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libgcjLGCJ.postrm
+++ gcc-6-6.3.0/debian/libgcjLGCJ.postrm
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    remove|purge)
+        # only purge if no other library is installed.
+        if [ -z "$(ls /usr/lib/libgcj.so.@GCJ@* 2>/dev/null)" ]; then
+	    rm -f /var/lib/gcj-@BV@/classmap.db
+	    rmdir --ignore-fail-on-non-empty /var/lib/gcj-@BV@ 2>/dev/null || true
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libgfortran.symbols
+++ gcc-6-6.3.0/debian/libgfortran.symbols
@@ -0,0 +1,12 @@
+libgfortran.so.3 #PACKAGE# #MINVER#
+ (symver)F2C_1.0 4.3
+ (symver)GFORTRAN_C99_1.0 4.3
+ (symver)GFORTRAN_C99_1.1 4.5
+ (symver)GFORTRAN_1.0 4.3
+ (symver)GFORTRAN_1.1 4.4
+ (symver)GFORTRAN_1.2 4.5
+ (symver)GFORTRAN_1.3 4.6
+ (symver)GFORTRAN_1.4 4.6
+ (symver)GFORTRAN_1.5 4.8
+ (symver)GFORTRAN_1.6 5
+ (symver)GFORTRAN_1.7 6
--- gcc-6-6.3.0.orig/debian/libgnat-BV.overrides
+++ gcc-6-6.3.0/debian/libgnat-BV.overrides
@@ -0,0 +1 @@
+libgnat-@BV@ binary: package-name-doesnt-match-sonames
--- gcc-6-6.3.0.orig/debian/libgnatprjBV.overrides
+++ gcc-6-6.3.0/debian/libgnatprjBV.overrides
@@ -0,0 +1 @@
+libgnatprj@BV@ binary: missing-dependency-on-libc
--- gcc-6-6.3.0.orig/debian/libgnatvsnBV.overrides
+++ gcc-6-6.3.0/debian/libgnatvsnBV.overrides
@@ -0,0 +1 @@
+libgnatvsn@BV@ binary: missing-dependency-on-libc
--- gcc-6-6.3.0.orig/debian/libgomp.symbols
+++ gcc-6-6.3.0/debian/libgomp.symbols
@@ -0,0 +1,18 @@
+libgomp.so.1 #PACKAGE# #MINVER#
+ (symver)GOACC_2.0 5
+ (symver)GOACC_2.0.1 6
+ (symver)GOMP_1.0 4.2.1
+ (symver)GOMP_2.0 4.4
+ (symver)GOMP_3.0 4.7
+ (symver)GOMP_4.0 4.9
+ (symver)GOMP_4.0.1 5
+ (symver)GOMP_4.5 6
+ (symver)GOMP_PLUGIN_1.0 5
+ (symver)GOMP_PLUGIN_1.1 6
+ (symver)OACC_2.0 5
+ (symver)OMP_1.0 4.2.1
+ (symver)OMP_2.0 4.2.1
+ (symver)OMP_3.0 4.4
+ (symver)OMP_3.1 4.7
+ (symver)OMP_4.0 4.9
+ (symver)OMP_4.5 6
--- gcc-6-6.3.0.orig/debian/libgphobos.symbols
+++ gcc-6-6.3.0/debian/libgphobos.symbols
@@ -0,0 +1,12 @@
+libgdruntime.so.68 #PACKAGE# #MINVER#
+#(arch-bits=32)#include "libgphobos.symbols.rt32"
+#(arch-bits=64)#include "libgphobos.symbols.rt64"
+(arch=i386 x32 kfreebsd-i386)#include "libgphobos.symbols.rt32"
+(arch=amd64 kfreebsd-amd64)#include "libgphobos.symbols.rt64"
+(arch=armel armhf)#include "libgphobos.symbols.rtarm32"
+libgphobos.so.68 #PACKAGE# #MINVER#
+#(arch-bits=32)#include "libgphobos.symbols.32"
+#(arch-bits=64)#include "libgphobos.symbols.64"
+(arch=i386 x32 kfreebsd-i386)#include "libgphobos.symbols.32"
+(arch=amd64 kfreebsd-amd64)#include "libgphobos.symbols.64"
+(arch=armel armhf)#include "libgphobos.symbols.arm32"
--- gcc-6-6.3.0.orig/debian/libgphobos.symbols.32
+++ gcc-6-6.3.0/debian/libgphobos.symbols.32
@@ -0,0 +1,10380 @@
+ ZLIB_VERNUM@Base 6
+ ZLIB_VERSION@Base 6
+ Z_NULL@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__initZ@Base 6
+ _D101TypeInfo_S3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D102TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D103TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D106TypeInfo_S3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D106TypeInfo_S3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D109TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D113TypeInfo_S3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D114TypeInfo_PS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D115TypeInfo_S3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6__initZ@Base 6
+ _D115TypeInfo_S3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D116TypeInfo_PS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D116TypeInfo_xS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D119TypeInfo_S3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6__initZ@Base 6
+ _D11TypeInfo_Pa6__initZ@Base 6
+ _D11TypeInfo_Pb6__initZ@Base 6
+ _D11TypeInfo_Pd6__initZ@Base 6
+ _D11TypeInfo_Pe6__initZ@Base 6
+ _D11TypeInfo_Pf6__initZ@Base 6
+ _D11TypeInfo_Pg6__initZ@Base 6
+ _D11TypeInfo_Ph6__initZ@Base 6
+ _D11TypeInfo_Pi6__initZ@Base 6
+ _D11TypeInfo_Pk6__initZ@Base 6
+ _D11TypeInfo_Pl6__initZ@Base 6
+ _D11TypeInfo_Pm6__initZ@Base 6
+ _D11TypeInfo_Ps6__initZ@Base 6
+ _D11TypeInfo_Pt6__initZ@Base 6
+ _D11TypeInfo_Pv6__initZ@Base 6
+ _D11TypeInfo_xa6__initZ@Base 6
+ _D11TypeInfo_xb6__initZ@Base 6
+ _D11TypeInfo_xd6__initZ@Base 6
+ _D11TypeInfo_xe6__initZ@Base 6
+ _D11TypeInfo_xf6__initZ@Base 6
+ _D11TypeInfo_xh6__initZ@Base 6
+ _D11TypeInfo_xi6__initZ@Base 6
+ _D11TypeInfo_xk6__initZ@Base 6
+ _D11TypeInfo_xl6__initZ@Base 6
+ _D11TypeInfo_xm6__initZ@Base 6
+ _D11TypeInfo_xs6__initZ@Base 6
+ _D11TypeInfo_xt6__initZ@Base 6
+ _D11TypeInfo_xu6__initZ@Base 6
+ _D11TypeInfo_xv6__initZ@Base 6
+ _D11TypeInfo_xw6__initZ@Base 6
+ _D11TypeInfo_ya6__initZ@Base 6
+ _D11TypeInfo_yb6__initZ@Base 6
+ _D11TypeInfo_yd6__initZ@Base 6
+ _D11TypeInfo_ye6__initZ@Base 6
+ _D11TypeInfo_yf6__initZ@Base 6
+ _D11TypeInfo_yh6__initZ@Base 6
+ _D11TypeInfo_yi6__initZ@Base 6
+ _D11TypeInfo_yk6__initZ@Base 6
+ _D11TypeInfo_yl6__initZ@Base 6
+ _D11TypeInfo_ym6__initZ@Base 6
+ _D11TypeInfo_ys6__initZ@Base 6
+ _D11TypeInfo_yt6__initZ@Base 6
+ _D11TypeInfo_yu6__initZ@Base 6
+ _D11TypeInfo_yw6__initZ@Base 6
+ _D120TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_xS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D122TypeInfo_xS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D122TypeInfo_xS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D124TypeInfo_S3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D124TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D125TypeInfo_xS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D125TypeInfo_xS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D127TypeInfo_S3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__initZ@Base 6
+ _D12TypeInfo_AAf6__initZ@Base 6
+ _D12TypeInfo_Axf6__initZ@Base 6
+ _D12TypeInfo_Axh6__initZ@Base 6
+ _D12TypeInfo_Axk6__initZ@Base 6
+ _D12TypeInfo_Axu6__initZ@Base 6
+ _D12TypeInfo_Axv6__initZ@Base 6
+ _D12TypeInfo_Axw6__initZ@Base 6
+ _D12TypeInfo_Ayh6__initZ@Base 6
+ _D12TypeInfo_Ayk6__initZ@Base 6
+ _D12TypeInfo_Ayu6__initZ@Base 6
+ _D12TypeInfo_Ayw6__initZ@Base 6
+ _D12TypeInfo_FZv6__initZ@Base 6
+ _D12TypeInfo_G2k6__initZ@Base 6
+ _D12TypeInfo_G3k6__initZ@Base 6
+ _D12TypeInfo_G4a6__initZ@Base 6
+ _D12TypeInfo_G4k6__initZ@Base 6
+ _D12TypeInfo_Hkk6__initZ@Base 6
+ _D12TypeInfo_Hlh6__initZ@Base 6
+ _D12TypeInfo_Oxa6__initZ@Base 6
+ _D12TypeInfo_Oxd6__initZ@Base 6
+ _D12TypeInfo_Oxe6__initZ@Base 6
+ _D12TypeInfo_Oxf6__initZ@Base 6
+ _D12TypeInfo_Oxh6__initZ@Base 6
+ _D12TypeInfo_Oxi6__initZ@Base 6
+ _D12TypeInfo_Oxk6__initZ@Base 6
+ _D12TypeInfo_Oxl6__initZ@Base 6
+ _D12TypeInfo_Oxm6__initZ@Base 6
+ _D12TypeInfo_Oxs6__initZ@Base 6
+ _D12TypeInfo_Oxt6__initZ@Base 6
+ _D12TypeInfo_Oxu6__initZ@Base 6
+ _D12TypeInfo_Oxw6__initZ@Base 6
+ _D12TypeInfo_PAa6__initZ@Base 6
+ _D12TypeInfo_PAu6__initZ@Base 6
+ _D12TypeInfo_PAw6__initZ@Base 6
+ _D12TypeInfo_Pxa6__initZ@Base 6
+ _D12TypeInfo_Pxd6__initZ@Base 6
+ _D12TypeInfo_Pxk6__initZ@Base 6
+ _D12TypeInfo_Pxv6__initZ@Base 6
+ _D12TypeInfo_xAa6__initZ@Base 6
+ _D12TypeInfo_xAf6__initZ@Base 6
+ _D12TypeInfo_xAh6__initZ@Base 6
+ _D12TypeInfo_xAk6__initZ@Base 6
+ _D12TypeInfo_xAu6__initZ@Base 6
+ _D12TypeInfo_xAv6__initZ@Base 6
+ _D12TypeInfo_xAw6__initZ@Base 6
+ _D12TypeInfo_xPa6__initZ@Base 6
+ _D12TypeInfo_xPd6__initZ@Base 6
+ _D12TypeInfo_xPk6__initZ@Base 6
+ _D12TypeInfo_xPv6__initZ@Base 6
+ _D12TypeInfo_yAa6__initZ@Base 6
+ _D133TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D133TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D134TypeInfo_S3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D135TypeInfo_xS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6__initZ@Base 6
+ _D137TypeInfo_E3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11MatchResult6__initZ@Base 6
+ _D137TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D138TypeInfo_S3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D138TypeInfo_S3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D138TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D138TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D13TypeInfo_AAya6__initZ@Base 6
+ _D13TypeInfo_APxa6__initZ@Base 6
+ _D13TypeInfo_DFZv6__initZ@Base 6
+ _D13TypeInfo_G24h6__initZ@Base 6
+ _D13TypeInfo_Hkxk6__initZ@Base 6
+ _D13TypeInfo_PAyh6__initZ@Base 6
+ _D13TypeInfo_xAya6__initZ@Base 6
+ _D13TypeInfo_xAyh6__initZ@Base 6
+ _D13TypeInfo_xAyk6__initZ@Base 6
+ _D13TypeInfo_xG2k6__initZ@Base 6
+ _D13TypeInfo_xG3k6__initZ@Base 6
+ _D13TypeInfo_xG4a6__initZ@Base 6
+ _D13TypeInfo_xG4k6__initZ@Base 6
+ _D13TypeInfo_xHkk6__initZ@Base 6
+ _D141TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D142TypeInfo_S3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D142TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D143TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D143TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D145TypeInfo_S3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6__initZ@Base 6
+ _D146TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D146TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D146TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D149TypeInfo_E3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11MatchResult6__initZ@Base 6
+ _D14TypeInfo_AxAya6__initZ@Base 6
+ _D14TypeInfo_FPvZv6__initZ@Base 6
+ _D14TypeInfo_PG24h6__initZ@Base 6
+ _D14TypeInfo_UPvZv6__initZ@Base 6
+ _D14TypeInfo_xAAya6__initZ@Base 6
+ _D14TypeInfo_xDFZv6__initZ@Base 6
+ _D152TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D153TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D154TypeInfo_S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D154TypeInfo_S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D156TypeInfo_S3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine6__initZ@Base 6
+ _D15TypeInfo_PFPvZv6__initZ@Base 6
+ _D15TypeInfo_PUPvZv6__initZ@Base 6
+ _D160TypeInfo_S3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack6__initZ@Base 6
+ _D161TypeInfo_S3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D161TypeInfo_S3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D162TypeInfo_S3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D162TypeInfo_S3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D162TypeInfo_xS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D162TypeInfo_xS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D163TypeInfo_S3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult6__initZ@Base 6
+ _D165TypeInfo_S3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value6__initZ@Base 6
+ _D167TypeInfo_S3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D168TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__initZ@Base 6
+ _D168TypeInfo_S3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__initZ@Base 6
+ _D169TypeInfo_S3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D16TypeInfo_HAyaAya6__initZ@Base 6
+ _D16TypeInfo_xPFPvZv6__initZ@Base 6
+ _D16TypeInfo_xPUPvZv6__initZ@Base 6
+ _D170TypeInfo_S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D170TypeInfo_S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_G2S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_G2S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_S3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__initZ@Base 6
+ _D173TypeInfo_S3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D173TypeInfo_xG2S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D173TypeInfo_xG2S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D174TypeInfo_FNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D174TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D174TypeInfo_xS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D175TypeInfo_PFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_xPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D178TypeInfo_S3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D179TypeInfo_xS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D17TypeInfo_HAyaxAya6__initZ@Base 6
+ _D17TypeInfo_xHAyaAya6__initZ@Base 6
+ _D180TypeInfo_AxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D180TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__initZ@Base 6
+ _D180TypeInfo_xAS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D182TypeInfo_S3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D183TypeInfo_xS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D186TypeInfo_FNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D186TypeInfo_S3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D186TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D187TypeInfo_PFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D187TypeInfo_xS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D188TypeInfo_xPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D18TypeInfo_xC6Object6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D215TypeInfo_S3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_S3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D21TypeInfo_xC9Exception6__initZ@Base 6
+ _D220TypeInfo_xS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D235TypeInfo_S3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D237TypeInfo_S3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__initZ@Base 6
+ _D23TypeInfo_E3std3uni4Mode6__initZ@Base 6
+ _D240TypeInfo_S3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__initZ@Base 6
+ _D242TypeInfo_S3std9algorithm7sorting201__T11TimSortImplS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ5Slice6__initZ@Base 6
+ _D243TypeInfo_HS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D246TypeInfo_S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D24TypeInfo_AC3std3xml4Item6__initZ@Base 6
+ _D24TypeInfo_AC3std3xml4Text6__initZ@Base 6
+ _D24TypeInfo_E3std6system2OS6__initZ@Base 6
+ _D24TypeInfo_S3std4uuid4UUID6__initZ@Base 6
+ _D25TypeInfo_AC3std3xml5CData6__initZ@Base 6
+ _D25TypeInfo_E3std6stream3BOM6__initZ@Base 6
+ _D25TypeInfo_S3etc1c4curl3_N26__initZ@Base 6
+ _D25TypeInfo_S3std5stdio4File6__initZ@Base 6
+ _D262TypeInfo_S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D264TypeInfo_G4S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D265TypeInfo_xG4S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D267TypeInfo_S3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult6__initZ@Base 6
+ _D26TypeInfo_E3std3xml7TagType6__initZ@Base 6
+ _D26TypeInfo_HAyaC3std3xml3Tag6__initZ@Base 6
+ _D26TypeInfo_S3etc1c4curl4_N286__initZ@Base 6
+ _D26TypeInfo_S3etc1c4curl4_N316__initZ@Base 6
+ _D26TypeInfo_S3std3uni7unicode6__initZ@Base 6
+ _D26TypeInfo_S3std5stdio5lines6__initZ@Base 6
+ _D26TypeInfo_S3std8typecons2No6__initZ@Base 6
+ _D26TypeInfo_xS3std5stdio4File6__initZ@Base 6
+ _D270TypeInfo_S3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D27TypeInfo_AC3std3xml7Comment6__initZ@Base 6
+ _D27TypeInfo_AC3std3xml7Element6__initZ@Base 6
+ _D27TypeInfo_E3etc1c4curl5CurlM6__initZ@Base 6
+ _D27TypeInfo_S3std3net4curl3FTP6__initZ@Base 6
+ _D27TypeInfo_S3std3uni8GcPolicy6__initZ@Base 6
+ _D27TypeInfo_S3std3uni8Grapheme6__initZ@Base 6
+ _D27TypeInfo_S3std7process4Pipe6__initZ@Base 6
+ _D27TypeInfo_S3std8typecons3Yes6__initZ@Base 6
+ _D27TypeInfo_xC3std7process3Pid6__initZ@Base 6
+ _D28TypeInfo_E3std3csv9Malformed6__initZ@Base 6
+ _D28TypeInfo_E3std4file8SpanMode6__initZ@Base 6
+ _D28TypeInfo_E3std6format6Mangle6__initZ@Base 6
+ _D28TypeInfo_E3std6getopt6config6__initZ@Base 6
+ _D28TypeInfo_E3std6system6Endian6__initZ@Base 6
+ _D28TypeInfo_OC6object9Throwable6__initZ@Base 6
+ _D28TypeInfo_PC6object9Throwable6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4Curl6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4HTTP6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4SMTP6__initZ@Base 6
+ _D28TypeInfo_S3std4file8DirEntry6__initZ@Base 6
+ _D28TypeInfo_S3std6bigint6BigInt6__initZ@Base 6
+ _D28TypeInfo_S3std6digest2md3MD56__initZ@Base 6
+ _D28TypeInfo_S3std6getopt6Option6__initZ@Base 6
+ _D28TypeInfo_S3std6socket6Linger6__initZ@Base 6
+ _D28TypeInfo_S3std8datetime4Date6__initZ@Base 6
+ _D28TypeInfo_xC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_AC4core6thread5Fiber6__initZ@Base 6
+ _D29TypeInfo_AS3std4file8DirEntry6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlFtp6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlMsg6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlVer6__initZ@Base 6
+ _D29TypeInfo_E3std4json9JSON_TYPE6__initZ@Base 6
+ _D29TypeInfo_E3std5stdio8LockType6__initZ@Base 6
+ _D29TypeInfo_E3std6stream7SeekPos6__initZ@Base 6
+ _D29TypeInfo_E3std7process6Config6__initZ@Base 6
+ _D29TypeInfo_E3std8datetime5Month6__initZ@Base 6
+ _D29TypeInfo_POC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_S3etc1c4curl7CURLMsg6__initZ@Base 6
+ _D29TypeInfo_S3std4json9JSONValue6__initZ@Base 6
+ _D29TypeInfo_S3std4math9IeeeFlags6__initZ@Base 6
+ _D29TypeInfo_S3std5range8NullSink6__initZ@Base 6
+ _D29TypeInfo_S3std6socket7TimeVal6__initZ@Base 6
+ _D29TypeInfo_xE3std4file8SpanMode6__initZ@Base 6
+ _D29TypeInfo_xS3std3net4curl4Curl6__initZ@Base 6
+ _D29TypeInfo_xS3std4file8DirEntry6__initZ@Base 6
+ _D29TypeInfo_xS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_AC3std6socket7Address6__initZ@Base 6
+ _D30TypeInfo_AxS3std4file8DirEntry6__initZ@Base 6
+ _D30TypeInfo_AxS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlAuth6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlForm6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlInfo6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlPoll6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlSeek6__initZ@Base 6
+ _D30TypeInfo_E3std3xml10DecodeMode6__initZ@Base 6
+ _D30TypeInfo_E3std6socket8socket_t6__initZ@Base 6
+ _D30TypeInfo_E3std6stream8FileMode6__initZ@Base 6
+ _D30TypeInfo_E3std6traits8Variadic6__initZ@Base 6
+ _D30TypeInfo_E3std8compiler6Vendor6__initZ@Base 6
+ _D30TypeInfo_S3etc1c4zlib8z_stream6__initZ@Base 6
+ _D30TypeInfo_S3std5stdio4File4Impl6__initZ@Base 6
+ _D30TypeInfo_xAS3std4file8DirEntry6__initZ@Base 6
+ _D30TypeInfo_xAS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_xC3std6socket7Address6__initZ@Base 6
+ _D30TypeInfo_xS3std4json9JSONValue6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlError6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlIoCmd6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlPause6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlProto6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlProxy6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlRedir6__initZ@Base 6
+ _D31TypeInfo_E3std4math10RealFormat6__initZ@Base 6
+ _D31TypeInfo_E3std7process8Redirect6__initZ@Base 6
+ _D31TypeInfo_S3etc1c4zlib9gz_header6__initZ@Base 6
+ _D31TypeInfo_S3std11concurrency3Tid6__initZ@Base 6
+ _D31TypeInfo_S3std3net4curl7CurlAPI6__initZ@Base 6
+ _D31TypeInfo_S3std6digest3crc5CRC326__initZ@Base 6
+ _D31TypeInfo_S3std8datetime7SysTime6__initZ@Base 6
+ _D31TypeInfo_xS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_AS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_E3std4json11JSONOptions6__initZ@Base 6
+ _D32TypeInfo_E3std4uuid4UUID7Variant6__initZ@Base 6
+ _D32TypeInfo_E3std4uuid4UUID7Version6__initZ@Base 6
+ _D32TypeInfo_E3std5ascii10LetterCase6__initZ@Base 6
+ _D32TypeInfo_E3std8datetime8PopFirst6__initZ@Base 6
+ _D32TypeInfo_PS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_PxS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_S3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D32TypeInfo_S3std3net7isemail5Token6__initZ@Base 6
+ _D32TypeInfo_S3std3uni7unicode5block6__initZ@Base 6
+ _D32TypeInfo_S3std4file11DirIterator6__initZ@Base 6
+ _D32TypeInfo_S3std5stdio10ChunksImpl6__initZ@Base 6
+ _D32TypeInfo_S3std8bitmanip8BitArray6__initZ@Base 6
+ _D32TypeInfo_S3std8bitmanip8FloatRep6__initZ@Base 6
+ _D32TypeInfo_S3std8datetime8DateTime6__initZ@Base 6
+ _D32TypeInfo_xE3std7process8Redirect6__initZ@Base 6
+ _D32TypeInfo_xPS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_xS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_xS3std8datetime7SysTime6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlFtpSSL6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlGlobal6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlKHStat6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlKHType6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlOption6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlUseSSL6__initZ@Base 6
+ _D33TypeInfo_E3std4zlib12HeaderFormat6__initZ@Base 6
+ _D33TypeInfo_E3std6mmfile6MmFile4Mode6__initZ@Base 6
+ _D33TypeInfo_E3std6socket10SocketType6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9AutoStart6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9DayOfWeek6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9Direction6__initZ@Base 6
+ _D33TypeInfo_E3std8encoding9AsciiChar6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_forms6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_khkey6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_slist6__initZ@Base 6
+ _D33TypeInfo_S3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D33TypeInfo_S3std3net4curl4SMTP4Impl6__initZ@Base 6
+ _D33TypeInfo_S3std3uni13ReallocPolicy6__initZ@Base 6
+ _D33TypeInfo_S3std3uni7unicode6script6__initZ@Base 6
+ _D33TypeInfo_S3std5stdio4File7ByChunk6__initZ@Base 6
+ _D33TypeInfo_S3std8bitmanip9DoubleRep6__initZ@Base 6
+ _D33TypeInfo_S3std8datetime9StopWatch6__initZ@Base 6
+ _D33TypeInfo_S3std8datetime9TimeOfDay6__initZ@Base 6
+ _D33TypeInfo_xC3std8datetime8TimeZone6__initZ@Base 6
+ _D33TypeInfo_xS3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D33TypeInfo_xS3std4file11DirIterator6__initZ@Base 6
+ _D33TypeInfo_yC3std8datetime8TimeZone6__initZ@Base 6
+ _D34TypeInfo_AE3std8encoding9AsciiChar6__initZ@Base 6
+ _D34TypeInfo_C3std6stream11InputStream6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlCSelect6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlFormAdd6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlFtpAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlIoError6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlKHMatch6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlMOption6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlRtspReq6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlSeekPos6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlShError6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlSshAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlTlsAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlVersion6__initZ@Base 6
+ _D34TypeInfo_E3std4path13CaseSensitive6__initZ@Base 6
+ _D34TypeInfo_E3std5range12SearchPolicy6__initZ@Base 6
+ _D34TypeInfo_E3std6digest6digest5Order6__initZ@Base 6
+ _D34TypeInfo_E3std6socket11SocketFlags6__initZ@Base 6
+ _D34TypeInfo_HAyaxS3std4json9JSONValue6__initZ@Base 6
+ _D34TypeInfo_HS3std11concurrency3Tidxb6__initZ@Base 6
+ _D34TypeInfo_S3std3uni14MatcherConcept6__initZ@Base 6
+ _D34TypeInfo_S3std6socket11AddressInfo6__initZ@Base 6
+ _D34TypeInfo_xE3std6socket10SocketType6__initZ@Base 6
+ _D34TypeInfo_xHAyaS3std4json9JSONValue6__initZ@Base 6
+ _D34TypeInfo_xHS3std11concurrency3Tidb6__initZ@Base 6
+ _D34TypeInfo_xS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D34TypeInfo_xS3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D35TypeInfo_AS3std6socket11AddressInfo6__initZ@Base 6
+ _D35TypeInfo_C3std6digest6digest6Digest6__initZ@Base 6
+ _D35TypeInfo_C3std6stream12OutputStream6__initZ@Base 6
+ _D35TypeInfo_C3std8typecons10Structural6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlFileType6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlLockData6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlReadFunc6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlShOption6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlSockType6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlTimeCond6__initZ@Base 6
+ _D35TypeInfo_E3std11concurrency7MsgType6__initZ@Base 6
+ _D35TypeInfo_E3std3net4curl4HTTP6Method6__initZ@Base 6
+ _D35TypeInfo_E3std3net7isemail8CheckDns6__initZ@Base 6
+ _D35TypeInfo_E3std5regex8internal2ir2IR6__initZ@Base 6
+ _D35TypeInfo_E3std6socket12ProtocolType6__initZ@Base 6
+ _D35TypeInfo_E3std6socket12SocketOption6__initZ@Base 6
+ _D35TypeInfo_E3std8encoding10Latin1Char6__initZ@Base 6
+ _D35TypeInfo_HAyaS3std11concurrency3Tid6__initZ@Base 6
+ _D35TypeInfo_PxS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D35TypeInfo_S3std11concurrency7Message6__initZ@Base 6
+ _D35TypeInfo_S3std3net4curl7CurlAPI3API6__initZ@Base 6
+ _D35TypeInfo_S3std4json9JSONValue5Store6__initZ@Base 6
+ _D35TypeInfo_S3std6getopt12GetoptResult6__initZ@Base 6
+ _D35TypeInfo_xPS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D35TypeInfo_xS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_AE3std8encoding10Latin1Char6__initZ@Base 6
+ _D36TypeInfo_AxS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_E3etc1c4curl13CurlFtpMethod6__initZ@Base 6
+ _D36TypeInfo_E3etc1c4curl13CurlIpResolve6__initZ@Base 6
+ _D36TypeInfo_E3std3net7isemail9EmailPart6__initZ@Base 6
+ _D36TypeInfo_E3std5range14StoppingPolicy6__initZ@Base 6
+ _D36TypeInfo_E3std6socket13AddressFamily6__initZ@Base 6
+ _D36TypeInfo_FC3std3xml13ElementParserZv6__initZ@Base 6
+ _D36TypeInfo_HS3std11concurrency3TidAAya6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_certinfo6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_fileinfo6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_httppost6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_sockaddr6__initZ@Base 6
+ _D36TypeInfo_S3std4file15DirIteratorImpl6__initZ@Base 6
+ _D36TypeInfo_S3std6getopt13configuration6__initZ@Base 6
+ _D36TypeInfo_S3std7process12ProcessPipes6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D36TypeInfo_xAS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_xE3std11concurrency7MsgType6__initZ@Base 6
+ _D36TypeInfo_xE3std3net4curl4HTTP6Method6__initZ@Base 6
+ _D36TypeInfo_xE3std6socket12ProtocolType6__initZ@Base 6
+ _D36TypeInfo_xS3std11concurrency7Message6__initZ@Base 6
+ _D37TypeInfo_C3std11concurrency9Scheduler6__initZ@Base 6
+ _D37TypeInfo_DFC3std3xml13ElementParserZv6__initZ@Base 6
+ _D37TypeInfo_E3etc1c4curl14CurlLockAccess6__initZ@Base 6
+ _D37TypeInfo_E3etc1c4curl14CurlSslVersion6__initZ@Base 6
+ _D37TypeInfo_E3std3uni17NormalizationForm6__initZ@Base 6
+ _D37TypeInfo_E3std3zip17CompressionMethod6__initZ@Base 6
+ _D37TypeInfo_E3std4json16JSONFloatLiteral6__initZ@Base 6
+ _D37TypeInfo_E3std6socket14SocketShutdown6__initZ@Base 6
+ _D37TypeInfo_E3std8typecons12TypeModifier6__initZ@Base 6
+ _D37TypeInfo_HAyaC3std3zip13ArchiveMember6__initZ@Base 6
+ _D37TypeInfo_S3etc1c7sqlite311sqlite3_vfs6__initZ@Base 6
+ _D37TypeInfo_S3std3net4curl12AutoProtocol6__initZ@Base 6
+ _D37TypeInfo_S3std3uni17CodepointInterval6__initZ@Base 6
+ _D37TypeInfo_S3std7numeric5bsr64FmZ5Ulong6__initZ@Base 6
+ _D37TypeInfo_S3std9container5dlist6DRange6__initZ@Base 6
+ _D37TypeInfo_xC3std11parallelism8TaskPool6__initZ@Base 6
+ _D37TypeInfo_xE3std6socket13AddressFamily6__initZ@Base 6
+ _D37TypeInfo_xS3std4file15DirIteratorImpl6__initZ@Base 6
+ _D37TypeInfo_xS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_AS3std3uni17CodepointInterval6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlClosePolicy6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlFnMAtchFunc6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlHttpVersion6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlNetRcOption6__initZ@Base 6
+ _D38TypeInfo_E3std3net7isemail10AsciiToken6__initZ@Base 6
+ _D38TypeInfo_E3std5stdio4File11Orientation6__initZ@Base 6
+ _D38TypeInfo_PxS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_S3etc1c7sqlite312sqlite3_file6__initZ@Base 6
+ _D38TypeInfo_S3etc1c7sqlite312sqlite3_vtab6__initZ@Base 6
+ _D38TypeInfo_S3std6digest6ripemd9RIPEMD1606__initZ@Base 6
+ _D38TypeInfo_xPS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_xS3std3uni17CodepointInterval6__initZ@Base 6
+ _D399TypeInfo_S3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlCallbackInfo6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlChunkBgnFunc6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlChunkEndFunc6__initZ@Base 6
+ _D39TypeInfo_E3std11concurrency10OnCrowding6__initZ@Base 6
+ _D39TypeInfo_E3std11parallelism10TaskStatus6__initZ@Base 6
+ _D39TypeInfo_E3std5range17TransverseOptions6__initZ@Base 6
+ _D39TypeInfo_E3std6socket16AddressInfoFlags6__initZ@Base 6
+ _D39TypeInfo_HE3std6format6MangleC8TypeInfo6__initZ@Base 6
+ _D39TypeInfo_S3std11concurrency10ThreadInfo6__initZ@Base 6
+ _D39TypeInfo_S3std3net7isemail11EmailStatus6__initZ@Base 6
+ _D39TypeInfo_S3std5stdio17LockingTextReader6__initZ@Base 6
+ _D39TypeInfo_S3std9container5dlist8BaseNode6__initZ@Base 6
+ _D3etc1c4curl10CurlGlobal6__initZ@Base 6
+ _D3etc1c4curl10CurlOption6__initZ@Base 6
+ _D3etc1c4curl10curl_forms6__initZ@Base 6
+ _D3etc1c4curl10curl_khkey6__initZ@Base 6
+ _D3etc1c4curl10curl_slist6__initZ@Base 6
+ _D3etc1c4curl11CurlCSelect6__initZ@Base 6
+ _D3etc1c4curl11CurlMOption6__initZ@Base 6
+ _D3etc1c4curl11CurlSshAuth6__initZ@Base 6
+ _D3etc1c4curl11CurlVersion6__initZ@Base 6
+ _D3etc1c4curl12CurlReadFunc6__initZ@Base 6
+ _D3etc1c4curl12__ModuleInfoZ@Base 6
+ _D3etc1c4curl13curl_certinfo6__initZ@Base 6
+ _D3etc1c4curl13curl_fileinfo6__initZ@Base 6
+ _D3etc1c4curl13curl_httppost6__initZ@Base 6
+ _D3etc1c4curl13curl_sockaddr6__initZ@Base 6
+ _D3etc1c4curl18CurlFInfoFlagKnown6__initZ@Base 6
+ _D3etc1c4curl3_N26__initZ@Base 6
+ _D3etc1c4curl4_N286__initZ@Base 6
+ _D3etc1c4curl4_N316__initZ@Base 6
+ _D3etc1c4curl5CurlM6__initZ@Base 6
+ _D3etc1c4curl7CURLMsg6__initZ@Base 6
+ _D3etc1c4curl9CurlPause6__initZ@Base 6
+ _D3etc1c4curl9CurlProto6__initZ@Base 6
+ _D3etc1c4zlib12__ModuleInfoZ@Base 6
+ _D3etc1c4zlib8z_stream6__initZ@Base 6
+ _D3etc1c4zlib9gz_header6__initZ@Base 6
+ _D3etc1c7sqlite311sqlite3_vfs6__initZ@Base 6
+ _D3etc1c7sqlite312__ModuleInfoZ@Base 6
+ _D3etc1c7sqlite312sqlite3_file6__initZ@Base 6
+ _D3etc1c7sqlite312sqlite3_vtab6__initZ@Base 6
+ _D3etc1c7sqlite314sqlite3_module6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info11__xopEqualsFKxS3etc1c7sqlite318sqlite3_index_infoKxS3etc1c7sqlite318sqlite3_index_infoZb@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info9__xtoHashFNbNeKxS3etc1c7sqlite318sqlite3_index_infoZk@Base 6
+ _D3etc1c7sqlite318sqlite3_io_methods6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_mem_methods6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_pcache_page6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_vtab_cursor6__initZ@Base 6
+ _D3etc1c7sqlite321sqlite3_mutex_methods6__initZ@Base 6
+ _D3etc1c7sqlite322sqlite3_pcache_methods6__initZ@Base 6
+ _D3etc1c7sqlite322sqlite3_rtree_geometry6__initZ@Base 6
+ _D3etc1c7sqlite323sqlite3_pcache_methods26__initZ@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info11__xopEqualsFKxS3etc1c7sqlite324sqlite3_rtree_query_infoKxS3etc1c7sqlite324sqlite3_rtree_query_infoZb@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info6__initZ@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info9__xtoHashFNbNeKxS3etc1c7sqlite324sqlite3_rtree_query_infoZk@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ11initializedAk@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ4memoAS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value11__xopEqualsFKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZb@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value6__initZ@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value9__xtoHashFNbNeKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZk@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std10functional11_ctfeSkipOpFKAyaZk@Base 6
+ _D3std10functional12__ModuleInfoZ@Base 6
+ _D3std10functional13_ctfeSkipNameFKAyaAyaZk@Base 6
+ _D3std10functional15_ctfeMatchUnaryFAyaAyaZk@Base 6
+ _D3std10functional16_ctfeMatchBinaryFAyaAyaAyaZk@Base 6
+ _D3std10functional16_ctfeSkipIntegerFKAyaZk@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTiTiZ6safeOpFNaNbNiNfKiKiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTkTiZ6safeOpFNaNbNiNfKkKiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTkTkZ6safeOpFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTlTkZ6safeOpFNaNbNiNfKlKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTkTykZ6safeOpFNaNbNiNfKkKykZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTyiTkZ6safeOpFNaNbNiNfKyiKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTykTkZ6safeOpFNaNbNiNfKykKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T6safeOpTykTykZ6safeOpFNaNbNiNfKykKykZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T8unsafeOpTkTiZ8unsafeOpFNaNbNiNfkiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T8unsafeOpTlTkZ8unsafeOpFNaNbNiNflkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ18__T8unsafeOpTyiTkZ8unsafeOpFNaNbNiNfyikZb@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfS3std3uni17CodepointIntervalZk@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfS3std3uni17CodepointIntervalZk@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_74727565VAyaa1_61Z15__T8unaryFunTwZ8unaryFunFNaNbNiNfKwZb@Base 6
+ _D3std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z55__T8unaryFunTyS3std8internal14unicode_tables9CompEntryZ8unaryFunFNaNbNiNfKyS3std8internal14unicode_tables9CompEntryZyw@Base 6
+ _D3std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z62__T8unaryFunTyS3std8internal14unicode_tables15UnicodePropertyZ8unaryFunFNaNbNiNfKyS3std8internal14unicode_tables15UnicodePropertyZyAa@Base 6
+ _D3std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z19__T9binaryFunTxkTkZ9binaryFunFNaNbNiNfKxkKkZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61202b2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZk@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTiZ9binaryFunFNaNbNiNfKkKiZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTwZ9binaryFunFNaNbNiNfKwKwZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTywTwZ9binaryFunFNaNbNiNfKywKwZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z20__T9binaryFunTxhTxhZ9binaryFunFNaNbNiNfKxhKxhZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTAyaTAyaZ9binaryFunFNaNbNiNfKAyaKAyaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203c3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTkTyiZ9binaryFunFNaNbNiNfKkKyiZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z144__T9binaryFunTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ9binaryFunFNaNbNiNfKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunThThZ9binaryFunFNaNbNiNfKhKhZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTaZ9binaryFunFNaNbNiNfKwKaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTaZ9binaryFunFNaNbNiNfwKaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTwZ9binaryFunFNaNbNiNfwwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTyhTwZ9binaryFunFNaNbNiNfKyhKwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTyhTwZ9binaryFunFNaNbNiNfKyhwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTAyaTAyaZ9binaryFunFNaNbNiNfKAyaKAyaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTyAaTAyaZ9binaryFunFNaNbNiNfKyAaKAyaZb@Base 6
+ _D3std10functional52__T8unaryFunVAyaa11_6120213d20612e4f70656eVAyaa1_61Z74__T8unaryFunTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ8unaryFunFNaNbNiNfKE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std10functional52__T8unaryFunVAyaa11_615b305d203e2030783830VAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfKS3std3uni17CodepointIntervalZb@Base 6
+ _D3std10functional54__T8unaryFunVAyaa12_61203d3d20612e556e696f6eVAyaa1_61Z74__T8unaryFunTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ8unaryFunFNaNbNiNfKE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z59__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTiZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKiZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10LeapSecondTyiZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10LeapSecondKyiZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTyiZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKyiZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTylZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKylZb@Base 6
+ _D3std10functional70__T9binaryFunVAyaa15_612e6e616d65203c20622e6e616d65VAyaa1_61VAyaa1_62Z86__T9binaryFunTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ9binaryFunFNaNbNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z106__T9binaryFunTS3std8datetime13PosixTimeZone14TempTransitionTS3std8datetime13PosixTimeZone14TempTransitionZ9binaryFunFNaNbNiNfKS3std8datetime13PosixTimeZone14TempTransitionKS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z98__T9binaryFunTS3std8datetime13PosixTimeZone10LeapSecondTS3std8datetime13PosixTimeZone10LeapSecondZ9binaryFunFNaNbNiNfKS3std8datetime13PosixTimeZone10LeapSecondKS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std11concurrency10MessageBox10setMaxMsgsMFkPFS3std11concurrency3TidZbZv@Base 6
+ _D3std11concurrency10MessageBox12isControlMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox13isLinkDeadMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox13isPriorityMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox14updateMsgCountMFZv@Base 6
+ _D3std11concurrency10MessageBox160__T3getTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3getMFMDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbMDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency10MessageBox181__T3getTS4core4time8DurationTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3getMFMS4core4time8DurationMDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbMDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency10MessageBox36__T3getTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ3getMFMDFNaNbNiAyhZvMDFNaNbNiNfbZvZb@Base 6
+ _D3std11concurrency10MessageBox3putMFKS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency10MessageBox5closeMFZ13onLinkDeadMsgMFKS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency10MessageBox5closeMFZv@Base 6
+ _D3std11concurrency10MessageBox6__ctorMFNeZC3std11concurrency10MessageBox@Base 6
+ _D3std11concurrency10MessageBox6__initZ@Base 6
+ _D3std11concurrency10MessageBox6__vtblZ@Base 6
+ _D3std11concurrency10MessageBox7__ClassZ@Base 6
+ _D3std11concurrency10MessageBox8isClosedMFNdZb@Base 6
+ _D3std11concurrency10MessageBox8isClosedMxFNdZb@Base 6
+ _D3std11concurrency10MessageBox8mboxFullMFZb@Base 6
+ _D3std11concurrency10ThreadInfo11__xopEqualsFKxS3std11concurrency10ThreadInfoKxS3std11concurrency10ThreadInfoZb@Base 6
+ _D3std11concurrency10ThreadInfo6__initZ@Base 6
+ _D3std11concurrency10ThreadInfo7cleanupMFZv@Base 6
+ _D3std11concurrency10ThreadInfo8thisInfoFNbNcNdNiNfZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency10ThreadInfo8thisInfoFNbNcNdZ3valS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency10ThreadInfo9__xtoHashFNbNeKxS3std11concurrency10ThreadInfoZk@Base 6
+ _D3std11concurrency10namesByTidHS3std11concurrency3TidAAya@Base 6
+ _D3std11concurrency10unregisterFAyaZb@Base 6
+ _D3std11concurrency11IsGenerator11__InterfaceZ@Base 6
+ _D3std11concurrency11MailboxFull6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency11MailboxFull@Base 6
+ _D3std11concurrency11MailboxFull6__initZ@Base 6
+ _D3std11concurrency11MailboxFull6__vtblZ@Base 6
+ _D3std11concurrency11MailboxFull7__ClassZ@Base 6
+ _D3std11concurrency12__ModuleInfoZ@Base 6
+ _D3std11concurrency12_staticDtor1FZv@Base 6
+ _D3std11concurrency12initOnceLockFNdZ4lockC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12initOnceLockFNdZC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12registryLockC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12unregisterMeFZv@Base 6
+ _D3std11concurrency13__T4sendTAyhZ4sendFS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency14FiberScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition13switchContextMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition4waitMFNbS4core4time8DurationZb@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition4waitMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__ctorMFNbC4core4sync5mutex5MutexZC3std11concurrency14FiberScheduler14FiberCondition@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6notifyMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition7__ClassZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition9notifyAllMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler5spawnMFNbDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler5startMFDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler5yieldMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler6createMFNbDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler7__ClassZ@Base 6
+ _D3std11concurrency14FiberScheduler8dispatchMFZv@Base 6
+ _D3std11concurrency14FiberScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__ctorMFNbDFZvZC3std11concurrency14FiberScheduler9InfoFiber@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber7__ClassZ@Base 6
+ _D3std11concurrency14LinkTerminated6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency14LinkTerminated@Base 6
+ _D3std11concurrency14LinkTerminated6__initZ@Base 6
+ _D3std11concurrency14LinkTerminated6__vtblZ@Base 6
+ _D3std11concurrency14LinkTerminated7__ClassZ@Base 6
+ _D3std11concurrency14__T5_sendTAyhZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency14__T5_sendTAyhZ5_sendFS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency15MessageMismatch6__ctorMFAyaZC3std11concurrency15MessageMismatch@Base 6
+ _D3std11concurrency15MessageMismatch6__initZ@Base 6
+ _D3std11concurrency15MessageMismatch6__vtblZ@Base 6
+ _D3std11concurrency15MessageMismatch7__ClassZ@Base 6
+ _D3std11concurrency15OwnerTerminated6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency15OwnerTerminated@Base 6
+ _D3std11concurrency15OwnerTerminated6__initZ@Base 6
+ _D3std11concurrency15OwnerTerminated6__vtblZ@Base 6
+ _D3std11concurrency15OwnerTerminated7__ClassZ@Base 6
+ _D3std11concurrency15ThreadScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D3std11concurrency15ThreadScheduler5spawnMFDFZvZv@Base 6
+ _D3std11concurrency15ThreadScheduler5startMFDFZvZv@Base 6
+ _D3std11concurrency15ThreadScheduler5yieldMFNbZv@Base 6
+ _D3std11concurrency15ThreadScheduler6__initZ@Base 6
+ _D3std11concurrency15ThreadScheduler6__vtblZ@Base 6
+ _D3std11concurrency15ThreadScheduler7__ClassZ@Base 6
+ _D3std11concurrency15ThreadScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency15onCrowdingBlockFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency15onCrowdingThrowFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency164__T7receiveTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ7receiveFDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZv@Base 6
+ _D3std11concurrency165__T8checkopsTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ8checkopsFNaNbNiNfDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZv@Base 6
+ _D3std11concurrency16onCrowdingIgnoreFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency172__T14receiveTimeoutTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ14receiveTimeoutFS4core4time8DurationDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency17setMaxMailboxSizeFS3std11concurrency3TidkE3std11concurrency10OnCrowdingZv@Base 6
+ _D3std11concurrency17setMaxMailboxSizeFS3std11concurrency3TidkPFS3std11concurrency3TidZbZv@Base 6
+ _D3std11concurrency18_sharedStaticCtor8FZv@Base 6
+ _D3std11concurrency19TidMissingException6__ctorMFAyaAyakZC3std11concurrency19TidMissingException@Base 6
+ _D3std11concurrency19TidMissingException6__initZ@Base 6
+ _D3std11concurrency19TidMissingException6__vtblZ@Base 6
+ _D3std11concurrency19TidMissingException7__ClassZ@Base 6
+ _D3std11concurrency24PriorityMessageException11__fieldDtorMFZv@Base 6
+ _D3std11concurrency24PriorityMessageException6__ctorMFS3std7variant18__T8VariantNVki24Z8VariantNZC3std11concurrency24PriorityMessageException@Base 6
+ _D3std11concurrency24PriorityMessageException6__initZ@Base 6
+ _D3std11concurrency24PriorityMessageException6__vtblZ@Base 6
+ _D3std11concurrency24PriorityMessageException7__ClassZ@Base 6
+ _D3std11concurrency33__T5_sendTS3std11concurrency3TidZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidS3std11concurrency3TidZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFNaNbNiNfKS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4ListZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFNaNbNiNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node11__fieldDtorMFZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node11__xopEqualsFKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node15__fieldPostblitMFZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__ctorMFNcS3std11concurrency7MessageZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node8opAssignMFNcNjS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node9__xtoHashFNbNeKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZk@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5frontMFNaNcNdNfZS3std11concurrency7Message@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5frontMFNdS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__ctorMFNaNbNcNiNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range8popFrontMFNaNfZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5clearMFNaNbNiNfZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7newNodeMFS3std11concurrency7MessageZPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7opSliceMFNaNbNiZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7sm_headOPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7sm_lockOS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock4lockMOFNbZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6unlockMOFNaNbNiZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8freeNodeMFPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8removeAtMFS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5RangeZv@Base 6
+ _D3std11concurrency3Tid11__xopEqualsFKxS3std11concurrency3TidKxS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency3Tid6__ctorMFNcNfC3std11concurrency10MessageBoxZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency3Tid6__initZ@Base 6
+ _D3std11concurrency3Tid8toStringMFMDFAxaZvZv@Base 6
+ _D3std11concurrency3Tid9__xtoHashFNbNeKxS3std11concurrency3TidZk@Base 6
+ _D3std11concurrency40__T7receiveTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ7receiveFDFNaNbNiAyhZvDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency41__T8checkopsTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ8checkopsFNaNbNiNfDFNaNbNiAyhZvDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvC4core4sync5mutex5MutexZ4flagOb@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvC4core4sync5mutex5MutexZPv@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvZPv@Base 6
+ _D3std11concurrency5yieldFNbZv@Base 6
+ _D3std11concurrency6locateFAyaZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency7Message11__fieldDtorMFZv@Base 6
+ _D3std11concurrency7Message11__xopEqualsFKxS3std11concurrency7MessageKxS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency7Message15__T6__ctorTAyhZ6__ctorMFNcE3std11concurrency7MsgTypeAyhZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message15__fieldPostblitMFZv@Base 6
+ _D3std11concurrency7Message18__T10convertsToTbZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message20__T10convertsToTAyhZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message22__T3mapTDFNaNbNiAyhZvZ3mapMFDFNaNbNiAyhZvZv@Base 6
+ _D3std11concurrency7Message22__T3mapTDFNaNbNiNfbZvZ3mapMFDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency7Message27__T3getTC6object9ThrowableZ3getMFNdZC6object9Throwable@Base 6
+ _D3std11concurrency7Message28__T3getTOC6object9ThrowableZ3getMFNdZOC6object9Throwable@Base 6
+ _D3std11concurrency7Message31__T3getTS3std11concurrency3TidZ3getMFNdZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency7Message34__T6__ctorTS3std11concurrency3TidZ6__ctorMFNcE3std11concurrency7MsgTypeS3std11concurrency3TidZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message35__T10convertsToTC6object9ThrowableZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message36__T10convertsToTOC6object9ThrowableZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message39__T10convertsToTS3std11concurrency3TidZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message46__T6__ctorTC3std11concurrency14LinkTerminatedZ6__ctorMFNcE3std11concurrency7MsgTypeC3std11concurrency14LinkTerminatedZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message47__T6__ctorTC3std11concurrency15OwnerTerminatedZ6__ctorMFNcE3std11concurrency7MsgTypeC3std11concurrency15OwnerTerminatedZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message6__initZ@Base 6
+ _D3std11concurrency7Message83__T3mapTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3mapMFDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency7Message85__T3mapTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbZ3mapMFDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency7Message85__T6__ctorTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ6__ctorMFNcE3std11concurrency7MsgTypeS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message88__T10convertsToTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message8opAssignMFNcNjS3std11concurrency7MessageZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message90__T10convertsToTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message9__xtoHashFNbNeKxS3std11concurrency7MessageZk@Base 6
+ _D3std11concurrency7thisTidFNdNfZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency83__T4sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ4sendFS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency84__T5_sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency84__T5_sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5_sendFS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency8ownerTidFNdZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency8registerFAyaS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency8thisInfoFNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency9Scheduler11__InterfaceZ@Base 6
+ _D3std11concurrency9schedulerC3std11concurrency9Scheduler@Base 6
+ _D3std11concurrency9tidByNameHAyaS3std11concurrency3Tid@Base 6
+ _D3std11mathspecial11logmdigammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial12__ModuleInfoZ@Base 6
+ _D3std11mathspecial14betaIncompleteFNaNbNiNfeeeZe@Base 6
+ _D3std11mathspecial15gammaIncompleteFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial18logmdigammaInverseFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial18normalDistributionFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial20gammaIncompleteComplFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial21betaIncompleteInverseFNaNbNiNfeeeZe@Base 6
+ _D3std11mathspecial25normalDistributionInverseFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial27gammaIncompleteComplInverseFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial3erfFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial4betaFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial4erfcFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial5gammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial7digammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial8logGammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial8sgnGammaFNaNbNiNfeZe@Base 6
+ _D3std11parallelism10addToChainFNaNbC6object9ThrowableKC6object9ThrowableKC6object9ThrowableZv@Base 6
+ _D3std11parallelism10foreachErrFZv@Base 6
+ _D3std11parallelism12AbstractTask11__xopEqualsFKxS3std11parallelism12AbstractTaskKxS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism12AbstractTask3jobMFZv@Base 6
+ _D3std11parallelism12AbstractTask4doneMFNdZb@Base 6
+ _D3std11parallelism12AbstractTask6__initZ@Base 6
+ _D3std11parallelism12AbstractTask9__xtoHashFNbNeKxS3std11parallelism12AbstractTaskZk@Base 6
+ _D3std11parallelism12__ModuleInfoZ@Base 6
+ _D3std11parallelism13__T3runTDFZvZ3runFDFZvZv@Base 6
+ _D3std11parallelism16submitAndExecuteFC3std11parallelism8TaskPoolMDFZvZv@Base 6
+ _D3std11parallelism17ParallelismThread6__ctorMFDFZvZC3std11parallelism17ParallelismThread@Base 6
+ _D3std11parallelism17ParallelismThread6__initZ@Base 6
+ _D3std11parallelism17ParallelismThread6__vtblZ@Base 6
+ _D3std11parallelism17ParallelismThread7__ClassZ@Base 6
+ _D3std11parallelism17findLastExceptionFNaNbC6object9ThrowableZC6object9Throwable@Base 6
+ _D3std11parallelism18_sharedStaticCtor2FZv@Base 6
+ _D3std11parallelism18_sharedStaticCtor9FZv@Base 6
+ _D3std11parallelism18_sharedStaticDtor7FZv@Base 6
+ _D3std11parallelism18defaultPoolThreadsFNdNeZk@Base 6
+ _D3std11parallelism18defaultPoolThreadsFNdNekZv@Base 6
+ _D3std11parallelism19_defaultPoolThreadsOk@Base 6
+ _D3std11parallelism20ParallelForeachError6__ctorMFZC3std11parallelism20ParallelForeachError@Base 6
+ _D3std11parallelism20ParallelForeachError6__initZ@Base 6
+ _D3std11parallelism20ParallelForeachError6__vtblZ@Base 6
+ _D3std11parallelism20ParallelForeachError7__ClassZ@Base 6
+ _D3std11parallelism21__T10scopedTaskTDFZvZ10scopedTaskFNfMDFZvZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism22__T14atomicSetUbyteThZ14atomicSetUbyteFNaNbNiKhhZv@Base 6
+ _D3std11parallelism23__T15atomicReadUbyteThZ15atomicReadUbyteFNaNbNiKhZh@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task10yieldForceMFNcNdNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task11__xopEqualsFKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZb@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task11enforcePoolMFNaNfZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task18executeInNewThreadMFNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task18executeInNewThreadMFNeiZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task4doneMFNdNeZb@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task4implFPvZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__ctorMFNaNbNcNiNfDFZvZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__dtorMFNfZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__initZ@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task7basePtrMFNaNbNdNiNfZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task8opAssignMFNfS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9__xtoHashFNbNeKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZk@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9spinForceMFNcNdNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9workForceMFNcNdNeZv@Base 6
+ _D3std11parallelism58__T14atomicCasUbyteTE3std11parallelism8TaskPool9PoolStateZ14atomicCasUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D3std11parallelism58__T14atomicSetUbyteTE3std11parallelism8TaskPool9PoolStateZ14atomicSetUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZv@Base 6
+ _D3std11parallelism59__T15atomicReadUbyteTE3std11parallelism8TaskPool9PoolStateZ15atomicReadUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateZh@Base 6
+ _D3std11parallelism8TaskPool10deleteItemMFPS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism8TaskPool10waiterLockMFZv@Base 6
+ _D3std11parallelism8TaskPool11abstractPutMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool11queueUnlockMFZv@Base 6
+ _D3std11parallelism8TaskPool11threadIndexk@Base 6
+ _D3std11parallelism8TaskPool11workerIndexMxFNbNdNfZk@Base 6
+ _D3std11parallelism8TaskPool12doSingleTaskMFZv@Base 6
+ _D3std11parallelism8TaskPool12waiterUnlockMFZv@Base 6
+ _D3std11parallelism8TaskPool13notifyWaitersMFZv@Base 6
+ _D3std11parallelism8TaskPool13startWorkLoopMFZv@Base 6
+ _D3std11parallelism8TaskPool15executeWorkLoopMFZv@Base 6
+ _D3std11parallelism8TaskPool16deleteItemNoSyncMFPS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism8TaskPool16tryDeleteExecuteMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool17abstractPutNoSyncMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool17nextInstanceIndexk@Base 6
+ _D3std11parallelism8TaskPool19defaultWorkUnitSizeMxFNaNbNfkZk@Base 6
+ _D3std11parallelism8TaskPool19waitUntilCompletionMFZv@Base 6
+ _D3std11parallelism8TaskPool22abstractPutGroupNoSyncMFPS3std11parallelism12AbstractTaskPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool3popMFZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism8TaskPool4sizeMxFNaNbNdNfZk@Base 6
+ _D3std11parallelism8TaskPool4stopMFNeZv@Base 6
+ _D3std11parallelism8TaskPool4waitMFZv@Base 6
+ _D3std11parallelism8TaskPool5doJobMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFNeZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFNekZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFPS3std11parallelism12AbstractTaskiZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__initZ@Base 6
+ _D3std11parallelism8TaskPool6__vtblZ@Base 6
+ _D3std11parallelism8TaskPool6finishMFNebZv@Base 6
+ _D3std11parallelism8TaskPool6notifyMFZv@Base 6
+ _D3std11parallelism8TaskPool7__ClassZ@Base 6
+ _D3std11parallelism8TaskPool8isDaemonMFNdNeZb@Base 6
+ _D3std11parallelism8TaskPool8isDaemonMFNdNebZv@Base 6
+ _D3std11parallelism8TaskPool8priorityMFNdNeZi@Base 6
+ _D3std11parallelism8TaskPool8priorityMFNdNeiZv@Base 6
+ _D3std11parallelism8TaskPool9notifyAllMFZv@Base 6
+ _D3std11parallelism8TaskPool9popNoSyncMFZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism8TaskPool9queueLockMFZv@Base 6
+ _D3std11parallelism8taskPoolFNdNeZ11initializedb@Base 6
+ _D3std11parallelism8taskPoolFNdNeZ4poolC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8taskPoolFNdNeZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism9totalCPUsyk@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger10logMsgPartMFNfAxaZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11__fieldDtorMFNeZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11beginLogMsgMFNfAyaiAyaAyaAyaE3std12experimental6logger4core8LogLevelS3std11concurrency3TidS3std8datetime7SysTimeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11getFilenameMFZAya@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger12finishLogMsgMFNfZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger4fileMFNdNfZS3std5stdio4File@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__ctorMFNfS3std5stdio4FilexE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__ctorMFNfxAyaxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__initZ@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__vtblZ@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger7__ClassZ@Base 6
+ _D3std12experimental6logger10filelogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger11writeLogMsgMFNiNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10nulllogger10NullLogger@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__initZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__vtblZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger7__ClassZ@Base 6
+ _D3std12experimental6logger10nulllogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger12insertLoggerMFNfAyaC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger12removeLoggerMFNfxAaZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger11multilogger11MultiLogger@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__initZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__vtblZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger7__ClassZ@Base 6
+ _D3std12experimental6logger11multilogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry11__xopEqualsFKxS3std12experimental6logger11multilogger16MultiLoggerEntryKxS3std12experimental6logger11multilogger16MultiLoggerEntryZb@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry9__xtoHashFNbNeKxS3std12experimental6logger11multilogger16MultiLoggerEntryZk@Base 6
+ _D3std12experimental6logger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger4core10TestLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core10TestLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core10TestLogger@Base 6
+ _D3std12experimental6logger4core10TestLogger6__initZ@Base 6
+ _D3std12experimental6logger4core10TestLogger6__vtblZ@Base 6
+ _D3std12experimental6logger4core10TestLogger7__ClassZ@Base 6
+ _D3std12experimental6logger4core12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger4core14globalLogLevelFNdNfE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core14globalLogLevelFNdNiNfZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core15stdSharedLoggerOC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core16StdForwardLogger@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__initZ@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__vtblZ@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger7__ClassZ@Base 6
+ _D3std12experimental6logger4core17stdThreadLocalLogFNdNfC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core17stdThreadLocalLogFNdNfZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core18_sharedStaticCtor1FZv@Base 6
+ _D3std12experimental6logger4core20stdSharedLoggerMutexC4core4sync5mutex5Mutex@Base 6
+ _D3std12experimental6logger4core21stdLoggerThreadLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core21stdThreadLocalLogImplFNdNeZ7_bufferG96h@Base 6
+ _D3std12experimental6logger4core21stdThreadLocalLogImplFNdNeZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core22__T16isLoggingEnabledZ16isLoggingEnabledFNaNfE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelLbZb@Base 6
+ _D3std12experimental6logger4core22stdSharedDefaultLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core23defaultSharedLoggerImplFNdNeZ7_bufferG116h@Base 6
+ _D3std12experimental6logger4core23defaultSharedLoggerImplFNdNeZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core23stdLoggerGlobalLogLevelOE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core28stdLoggerDefaultThreadLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core58__T11trustedLoadTE3std12experimental6logger4core8LogLevelZ11trustedLoadFNaNbNiNeKOE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core59__T11trustedLoadTxE3std12experimental6logger4core8LogLevelZ11trustedLoadFNaNbNiNeKOxE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core59__T12trustedStoreTE3std12experimental6logger4core8LogLevelZ12trustedStoreFNaNbNiNeKOE3std12experimental6logger4core8LogLevelKE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core60__T18systimeToISOStringTS3std5stdio4File17LockingTextWriterZ18systimeToISOStringFNfS3std5stdio4File17LockingTextWriterKxS3std8datetime7SysTimeZv@Base 6
+ _D3std12experimental6logger4core6Logger10forwardMsgMFNeKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core6Logger10logMsgPartMFNfAxaZv@Base 6
+ _D3std12experimental6logger4core6Logger11beginLogMsgMFNfAyaiAyaAyaAyaE3std12experimental6logger4core8LogLevelS3std11concurrency3TidS3std8datetime7SysTimeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core6Logger12fatalHandlerMFNdNiNfDFNfZvZv@Base 6
+ _D3std12experimental6logger4core6Logger12fatalHandlerMFNdNiNfZDFZv@Base 6
+ _D3std12experimental6logger4core6Logger12finishLogMsgMFNfZv@Base 6
+ _D3std12experimental6logger4core6Logger6__ctorMFNfE3std12experimental6logger4core8LogLevelZ9__lambda3FNbNeZC4core4sync5mutex5Mutex@Base 6
+ _D3std12experimental6logger4core6Logger6__ctorMFNfE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core6Logger6__initZ@Base 6
+ _D3std12experimental6logger4core6Logger6__vtblZ@Base 6
+ _D3std12experimental6logger4core6Logger7__ClassZ@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry11__xopEqualsFKxS3std12experimental6logger4core6Logger8LogEntryKxS3std12experimental6logger4core6Logger8LogEntryZb@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry6__initZ@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry8opAssignMFNaNbNcNjNfS3std12experimental6logger4core6Logger8LogEntryZS3std12experimental6logger4core6Logger8LogEntry@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry9__xtoHashFNbNeKxS3std12experimental6logger4core6Logger8LogEntryZk@Base 6
+ _D3std12experimental6logger4core6Logger8logLevelMFNdNiNfxE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core6Logger8logLevelMxFNaNdNiNfZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D3std12experimental6logger4core8MsgRange11__xopEqualsFKxS3std12experimental6logger4core8MsgRangeKxS3std12experimental6logger4core8MsgRangeZb@Base 6
+ _D3std12experimental6logger4core8MsgRange3putMFNfwZv@Base 6
+ _D3std12experimental6logger4core8MsgRange6__ctorMFNcNfC3std12experimental6logger4core6LoggerZS3std12experimental6logger4core8MsgRange@Base 6
+ _D3std12experimental6logger4core8MsgRange6__initZ@Base 6
+ _D3std12experimental6logger4core8MsgRange9__xtoHashFNbNeKxS3std12experimental6logger4core8MsgRangeZk@Base 6
+ _D3std12experimental6logger4core8parentOfFAyaZAya@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNfZ11trustedLoadFNaNbNiNeKOC3std12experimental6logger4core6LoggerZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNfZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12socketstream12SocketStream10writeBlockMFxPvkZk@Base 6
+ _D3std12socketstream12SocketStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std12socketstream12SocketStream5closeMFZv@Base 6
+ _D3std12socketstream12SocketStream6__ctorMFC3std6socket6SocketE3std6stream8FileModeZC3std12socketstream12SocketStream@Base 6
+ _D3std12socketstream12SocketStream6__ctorMFC3std6socket6SocketZC3std12socketstream12SocketStream@Base 6
+ _D3std12socketstream12SocketStream6__initZ@Base 6
+ _D3std12socketstream12SocketStream6__vtblZ@Base 6
+ _D3std12socketstream12SocketStream6socketMFZC3std6socket6Socket@Base 6
+ _D3std12socketstream12SocketStream7__ClassZ@Base 6
+ _D3std12socketstream12SocketStream8toStringMFZAya@Base 6
+ _D3std12socketstream12SocketStream9readBlockMFPvkZk@Base 6
+ _D3std12socketstream12__ModuleInfoZ@Base 6
+ _D3std1c4fenv12__ModuleInfoZ@Base 6
+ _D3std1c4math12__ModuleInfoZ@Base 6
+ _D3std1c4time12__ModuleInfoZ@Base 6
+ _D3std1c5linux11linuxextern12__ModuleInfoZ@Base 6
+ _D3std1c5linux4tipc12__ModuleInfoZ@Base 6
+ _D3std1c5linux5linux12__ModuleInfoZ@Base 6
+ _D3std1c5linux5linux13struct_stat646__initZ@Base 6
+ _D3std1c5linux6socket12__ModuleInfoZ@Base 6
+ _D3std1c5linux7pthread12__ModuleInfoZ@Base 6
+ _D3std1c5linux7termios12__ModuleInfoZ@Base 6
+ _D3std1c5stdio12__ModuleInfoZ@Base 6
+ _D3std1c6locale12__ModuleInfoZ@Base 6
+ _D3std1c6stdarg12__ModuleInfoZ@Base 6
+ _D3std1c6stddef12__ModuleInfoZ@Base 6
+ _D3std1c6stdlib12__ModuleInfoZ@Base 6
+ _D3std1c6string12__ModuleInfoZ@Base 6
+ _D3std1c6wcharh12__ModuleInfoZ@Base 6
+ _D3std1c7process12__ModuleInfoZ@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyaAyakC6object9ThrowableZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyaC6object9ThrowableAyakZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyakkC6object9ThrowableAyakZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__initZ@Base 6
+ _D3std3csv12CSVException6__vtblZ@Base 6
+ _D3std3csv12CSVException7__ClassZ@Base 6
+ _D3std3csv12CSVException8toStringMFNaNfZAya@Base 6
+ _D3std3csv12__ModuleInfoZ@Base 6
+ _D3std3csv23HeaderMismatchException6__ctorMFNaNfAyaAyakC6object9ThrowableZC3std3csv23HeaderMismatchException@Base 6
+ _D3std3csv23HeaderMismatchException6__ctorMFNaNfAyaC6object9ThrowableAyakZC3std3csv23HeaderMismatchException@Base 6
+ _D3std3csv23HeaderMismatchException6__initZ@Base 6
+ _D3std3csv23HeaderMismatchException6__vtblZ@Base 6
+ _D3std3csv23HeaderMismatchException7__ClassZ@Base 6
+ _D3std3csv23IncompleteCellException6__ctorMFNaNfAyaAyakC6object9ThrowableZC3std3csv23IncompleteCellException@Base 6
+ _D3std3csv23IncompleteCellException6__ctorMFNaNfAyaC6object9ThrowableAyakZC3std3csv23IncompleteCellException@Base 6
+ _D3std3csv23IncompleteCellException6__initZ@Base 6
+ _D3std3csv23IncompleteCellException6__vtblZ@Base 6
+ _D3std3csv23IncompleteCellException7__ClassZ@Base 6
+ _D3std3net4curl12AutoProtocol6__initZ@Base 6
+ _D3std3net4curl12__ModuleInfoZ@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool3popMFNaNfZAh@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool4pushMFNaNbNfAhZv@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry11__xopEqualsFKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryZb@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry9__xtoHashFNbNeKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryZk@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool6__initZ@Base 6
+ _D3std3net4curl13CurlException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3net4curl13CurlException@Base 6
+ _D3std3net4curl13CurlException6__initZ@Base 6
+ _D3std3net4curl13CurlException6__vtblZ@Base 6
+ _D3std3net4curl13CurlException7__ClassZ@Base 6
+ _D3std3net4curl19__T11CurlMessageTbZ11CurlMessage6__initZ@Base 6
+ _D3std3net4curl19_receiveAsyncChunksFAhKAhS3std3net4curl12__T4PoolTAhZ4PoolKAhS3std11concurrency3TidKbZk@Base 6
+ _D3std3net4curl20AsyncChunkInputRange11__xopEqualsFKxS3std3net4curl20AsyncChunkInputRangeKxS3std3net4curl20AsyncChunkInputRangeZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange6__ctorMFNcS3std11concurrency3TidkkZS3std3net4curl20AsyncChunkInputRange@Base 6
+ _D3std3net4curl20AsyncChunkInputRange6__initZ@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin514tryEnsureUnitsMFZv@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin54waitMFS4core4time8DurationZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin55emptyMFNdZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin55frontMFNdZAh@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin58popFrontMFZv@Base 6
+ _D3std3net4curl20AsyncChunkInputRange9__xtoHashFNbNeKxS3std3net4curl20AsyncChunkInputRangeZk@Base 6
+ _D3std3net4curl20CurlTimeoutException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3net4curl20CurlTimeoutException@Base 6
+ _D3std3net4curl20CurlTimeoutException6__initZ@Base 6
+ _D3std3net4curl20CurlTimeoutException6__vtblZ@Base 6
+ _D3std3net4curl20CurlTimeoutException7__ClassZ@Base 6
+ _D3std3net4curl20_finalizeAsyncChunksFAhKAhS3std11concurrency3TidZv@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage11__xopEqualsFKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZb@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage6__initZ@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage9__xtoHashFNbNeKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZk@Base 6
+ _D3std3net4curl21__T11curlMessageTAyhZ11curlMessageFNaNbNiNfAyhZS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage@Base 6
+ _D3std3net4curl3FTP10addCommandMFAxaZv@Base 6
+ _D3std3net4curl3FTP10initializeMFZv@Base 6
+ _D3std3net4curl3FTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl3FTP11__xopEqualsFKxS3std3net4curl3FTPKxS3std3net4curl3FTPZb@Base 6
+ _D3std3net4curl3FTP13clearCommandsMFZv@Base 6
+ _D3std3net4curl3FTP13contentLengthMFNdkZv@Base 6
+ _D3std3net4curl3FTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl3FTP3dupMFZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP4Impl11__xopEqualsFKxS3std3net4curl3FTP4ImplKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std3net4curl3FTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D3std3net4curl3FTP4Impl8opAssignMFNcNjS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std3net4curl3FTP4Impl9__xtoHashFNbNeKxS3std3net4curl3FTP4ImplZk@Base 6
+ _D3std3net4curl3FTP6__initZ@Base 6
+ _D3std3net4curl3FTP6opCallFAxaZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP6opCallFZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl3FTP8encodingMFNdAyaZv@Base 6
+ _D3std3net4curl3FTP8encodingMFNdZAya@Base 6
+ _D3std3net4curl3FTP8opAssignMFNcNjS3std3net4curl3FTPZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP9__mixin1210dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210verifyHostMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1211dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl3FTP9__mixin1214connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1214localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin1216operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1217setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1222setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1228defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl3FTP9__mixin125proxyMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin126handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl3FTP9__mixin126onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl3FTP9__mixin127verboseMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin128shutdownMFZv@Base 6
+ _D3std3net4curl3FTP9__mixin129isStoppedMFNdZb@Base 6
+ _D3std3net4curl3FTP9__mixin129localPortMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin129onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl3FTP9__mixin129proxyPortMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin129proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl3FTP9__xtoHashFNbNeKxS3std3net4curl3FTPZk@Base 6
+ _D3std3net4curl4Curl10initializeMFZv@Base 6
+ _D3std3net4curl4Curl10onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl4Curl11errorStringMFiZAya@Base 6
+ _D3std3net4curl4Curl13_seekCallbackUPvliZi@Base 6
+ _D3std3net4curl4Curl13_sendCallbackUPakkPvZk@Base 6
+ _D3std3net4curl4Curl14onSocketOptionMFNdDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiZv@Base 6
+ _D3std3net4curl4Curl14throwOnStoppedMFAyaZv@Base 6
+ _D3std3net4curl4Curl15onReceiveHeaderMFNdDFxAaZvZv@Base 6
+ _D3std3net4curl4Curl16_receiveCallbackUxPakkPvZk@Base 6
+ _D3std3net4curl4Curl16clearIfSupportedMFE3etc1c4curl10CurlOptionZv@Base 6
+ _D3std3net4curl4Curl17_progressCallbackUPvddddZi@Base 6
+ _D3std3net4curl4Curl21_socketOptionCallbackUPvE3std6socket8socket_tiZi@Base 6
+ _D3std3net4curl4Curl22_receiveHeaderCallbackUxPakkPvZk@Base 6
+ _D3std3net4curl4Curl3dupMFZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionAxaZv@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionPvZv@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionlZv@Base 6
+ _D3std3net4curl4Curl4curlFNcNdZS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl4Curl5clearMFE3etc1c4curl10CurlOptionZv@Base 6
+ _D3std3net4curl4Curl5pauseMFbbZv@Base 6
+ _D3std3net4curl4Curl6__initZ@Base 6
+ _D3std3net4curl4Curl6_checkMFiZv@Base 6
+ _D3std3net4curl4Curl6onSeekMFNdDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekZv@Base 6
+ _D3std3net4curl4Curl6onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl4Curl7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4Curl7performMFbZi@Base 6
+ _D3std3net4curl4Curl8shutdownMFZv@Base 6
+ _D3std3net4curl4Curl9onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl4HTTP10StatusLine11__xopEqualsFKxS3std3net4curl4HTTP10StatusLineKxS3std3net4curl4HTTP10StatusLineZb@Base 6
+ _D3std3net4curl4HTTP10StatusLine5resetMFNfZv@Base 6
+ _D3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D3std3net4curl4HTTP10StatusLine8toStringMFZAya@Base 6
+ _D3std3net4curl4HTTP10StatusLine9__xtoHashFNbNeKxS3std3net4curl4HTTP10StatusLineZk@Base 6
+ _D3std3net4curl4HTTP10initializeMFZv@Base 6
+ _D3std3net4curl4HTTP10statusLineMFNdZS3std3net4curl4HTTP10StatusLine@Base 6
+ _D3std3net4curl4HTTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl4HTTP11__xopEqualsFKxS3std3net4curl4HTTPKxS3std3net4curl4HTTPZb@Base 6
+ _D3std3net4curl4HTTP11setPostDataMFAxvAyaZv@Base 6
+ _D3std3net4curl4HTTP12maxRedirectsMFNdkZv@Base 6
+ _D3std3net4curl4HTTP12setCookieJarMFAxaZv@Base 6
+ _D3std3net4curl4HTTP12setUserAgentMFAxaZv@Base 6
+ _D3std3net4curl4HTTP13contentLengthMFNdkZv@Base 6
+ _D3std3net4curl4HTTP14flushCookieJarMFZv@Base 6
+ _D3std3net4curl4HTTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl4HTTP15clearAllCookiesMFZv@Base 6
+ _D3std3net4curl4HTTP15onReceiveHeaderMFNdDFxAaxAaZvZv@Base 6
+ _D3std3net4curl4HTTP15responseHeadersMFNdZHAyaAya@Base 6
+ _D3std3net4curl4HTTP16addRequestHeaderMFAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZ3bufG63a@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZ9userAgentAya@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZAya@Base 6
+ _D3std3net4curl4HTTP16setTimeConditionMFE3etc1c4curl12CurlTimeCondS3std8datetime7SysTimeZv@Base 6
+ _D3std3net4curl4HTTP19clearRequestHeadersMFZv@Base 6
+ _D3std3net4curl4HTTP19clearSessionCookiesMFZv@Base 6
+ _D3std3net4curl4HTTP19defaultMaxRedirectsk@Base 6
+ _D3std3net4curl4HTTP19onReceiveStatusLineMFNdDFS3std3net4curl4HTTP10StatusLineZvZv@Base 6
+ _D3std3net4curl4HTTP20authenticationMethodMFNdE3etc1c4curl8CurlAuthZv@Base 6
+ _D3std3net4curl4HTTP3dupMFZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP4Impl11__xopEqualsFKxS3std3net4curl4HTTP4ImplKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std3net4curl4HTTP4Impl15onReceiveHeaderMFNdDFxAaxAaZvZv@Base 6
+ _D3std3net4curl4HTTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D3std3net4curl4HTTP4Impl8opAssignMFNcNjS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std3net4curl4HTTP4Impl9__xtoHashFNbNeKxS3std3net4curl4HTTP4ImplZk@Base 6
+ _D3std3net4curl4HTTP6__initZ@Base 6
+ _D3std3net4curl4HTTP6caInfoMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP6methodMFNdE3std3net4curl4HTTP6MethodZv@Base 6
+ _D3std3net4curl4HTTP6methodMFNdZE3std3net4curl4HTTP6Method@Base 6
+ _D3std3net4curl4HTTP6opCallFAxaZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP6opCallFZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4HTTP8opAssignMFNcNjS3std3net4curl4HTTPZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP8postDataMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP8postDataMFNdAxvZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510verifyHostMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3511dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3514connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3514localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3516operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3517setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3522setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3528defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl4HTTP9__mixin355proxyMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin356handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4HTTP9__mixin356onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl4HTTP9__mixin357verboseMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin358shutdownMFZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359isStoppedMFNdZb@Base 6
+ _D3std3net4curl4HTTP9__mixin359localPortMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359proxyPortMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl4HTTP9__xtoHashFNbNeKxS3std3net4curl4HTTPZk@Base 6
+ _D3std3net4curl4HTTP9setCookieMFAxaZv@Base 6
+ _D3std3net4curl4SMTP10initializeMFZv@Base 6
+ _D3std3net4curl4SMTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl4SMTP11__xopEqualsFKxS3std3net4curl4SMTPKxS3std3net4curl4SMTPZb@Base 6
+ _D3std3net4curl4SMTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl4SMTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl4SMTP4Impl6__initZ@Base 6
+ _D3std3net4curl4SMTP4Impl7messageMFNdAyaZv@Base 6
+ _D3std3net4curl4SMTP4Impl8opAssignMFNcNjS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std3net4curl4SMTP6__initZ@Base 6
+ _D3std3net4curl4SMTP6opCallFAxaZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP6opCallFZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP7messageMFNdAyaZv@Base 6
+ _D3std3net4curl4SMTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4SMTP8opAssignMFNcNjS3std3net4curl4SMTPZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP9__mixin1010dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010verifyHostMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1011dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1014connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1014localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1016operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1017setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1022setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1028defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl4SMTP9__mixin105proxyMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin106handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4SMTP9__mixin106onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl4SMTP9__mixin107verboseMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin108shutdownMFZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109isStoppedMFNdZb@Base 6
+ _D3std3net4curl4SMTP9__mixin109localPortMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109proxyPortMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl4SMTP9__xtoHashFNbNeKxS3std3net4curl4SMTPZk@Base 6
+ _D3std3net4curl7CurlAPI19_sharedStaticDtor18FZv@Base 6
+ _D3std3net4curl7CurlAPI3API6__initZ@Base 6
+ _D3std3net4curl7CurlAPI4_apiS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl7CurlAPI6__initZ@Base 6
+ _D3std3net4curl7CurlAPI7_handlePv@Base 6
+ _D3std3net4curl7CurlAPI7loadAPIFZ5namesyAAa@Base 6
+ _D3std3net4curl7CurlAPI7loadAPIFZPv@Base 6
+ _D3std3net4curl7CurlAPI8instanceFNcNdZS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl8isFTPUrlFAxaZb@Base 6
+ _D3std3net7isemail10AsciiToken6__initZ@Base 6
+ _D3std3net7isemail11EmailStatus10domainPartMxFNdZAya@Base 6
+ _D3std3net7isemail11EmailStatus10statusCodeMxFNdZE3std3net7isemail15EmailStatusCode@Base 6
+ _D3std3net7isemail11EmailStatus11__xopEqualsFKxS3std3net7isemail11EmailStatusKxS3std3net7isemail11EmailStatusZb@Base 6
+ _D3std3net7isemail11EmailStatus5validMxFNdZb@Base 6
+ _D3std3net7isemail11EmailStatus6__ctorMFNcbAyaAyaE3std3net7isemail15EmailStatusCodeZS3std3net7isemail11EmailStatus@Base 6
+ _D3std3net7isemail11EmailStatus6__initZ@Base 6
+ _D3std3net7isemail11EmailStatus6statusMxFNdZAya@Base 6
+ _D3std3net7isemail11EmailStatus8toStringMxFZAya@Base 6
+ _D3std3net7isemail11EmailStatus9__xtoHashFNbNeKxS3std3net7isemail11EmailStatusZk@Base 6
+ _D3std3net7isemail11EmailStatus9localPartMxFNdZAya@Base 6
+ _D3std3net7isemail12__ModuleInfoZ@Base 6
+ _D3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D3std3net7isemail21statusCodeDescriptionFE3std3net7isemail15EmailStatusCodeZAya@Base 6
+ _D3std3net7isemail5Token6__initZ@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ20__T12toCaseLengthTaZ12toCaseLengthFNaNfxAaZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ20__T12toCaseLengthTuZ12toCaseLengthFNaNfxAuZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ20__T12toCaseLengthTwZ12toCaseLengthFNaNfxAwZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ20__T12toCaseLengthTaZ12toCaseLengthFNaNfxAaZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ20__T12toCaseLengthTuZ12toCaseLengthFNaNfxAuZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ20__T12toCaseLengthTwZ12toCaseLengthFNaNfxAwZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZ6moveToFNaNbNiNfAakkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZ6moveToFNaNbNiNfAukkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZ6moveToFNaNbNiNfAwkkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZ6moveToFNaNbNiNfAakkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZ6moveToFNaNbNiNfAukkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZ6moveToFNaNbNiNfAwkkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTaZ18toCaseInPlaceAllocFNaNeKAakkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTuZ18toCaseInPlaceAllocFNaNeKAukkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTwZ18toCaseInPlaceAllocFNaNeKAwkkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTaZ18toCaseInPlaceAllocFNaNeKAakkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTuZ18toCaseInPlaceAllocFNaNeKAukkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTwZ18toCaseInPlaceAllocFNaNeKAwkkZv@Base 6
+ _D3std3uni10compressToFNaNbNfkKAhZv@Base 6
+ _D3std3uni10isPowerOf2FNaNbNiNfkZb@Base 6
+ _D3std3uni10nfkcQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkcQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10numberTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10numberTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10safeRead24FNaNbNiNexPhkZk@Base 6
+ _D3std3uni10symbolTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10symbolTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10toLowerTabFNaNbNiNekZw@Base 6
+ _D3std3uni10toTitleTabFNaNbNiNekZw@Base 6
+ _D3std3uni10toUpperTabFNaNbNiNekZw@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayZS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieKxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZt@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni113__T23switchUniformLowerBoundS753std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z9binaryFunTAxkTkZ23switchUniformLowerBoundFNaNbNiNfAxkkZk@Base 6
+ _D3std3uni11composeJamoFNaNbNiNewwwZw@Base 6
+ _D3std3uni11isGraphicalFNaNbNiNfwZb@Base 6
+ _D3std3uni11isSurrogateFNaNbNiNfwZb@Base 6
+ _D3std3uni11safeWrite24FNaNbNiNePhkkZv@Base 6
+ _D3std3uni11toTitlecaseFNaNbNiNfwZw@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder109__T14deduceMaxIndexTS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki1TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki0TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki1TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder19__T8addValueVki1TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder60__T8addValueVki0TS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder109__T14deduceMaxIndexTS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekktZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki0TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder19__T8addValueVki1TtZ8addValueMFNaNbNetkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNektZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder60__T8addValueVki0TS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVki1TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVki1TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni121__T11findSetNameS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni124__T11findSetNameS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZi@Base 6
+ _D3std3uni127__T11findSetNameS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZi@Base 6
+ _D3std3uni12__ModuleInfoZ@Base 6
+ _D3std3uni12ceilPowerOf2FNaNbNiNfkZk@Base 6
+ _D3std3uni12fullCaseTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni12fullCaseTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni12isPrivateUseFNaNbNiNfwZb@Base 6
+ _D3std3uni12toLowerIndexFNaNbNiNewZt@Base 6
+ _D3std3uni12toTitleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni12toUpperIndexFNaNbNiNewZt@Base 6
+ _D3std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZi@Base 6
+ _D3std3uni13ReallocPolicy12__T5allocTkZ5allocFNekZAk@Base 6
+ _D3std3uni13ReallocPolicy14__T7destroyTkZ7destroyFNbNiNeKAkZv@Base 6
+ _D3std3uni13ReallocPolicy14__T7reallocTkZ7reallocFNeAkkZAk@Base 6
+ _D3std3uni13ReallocPolicy15__T6appendTkTiZ6appendFNeKAkiZv@Base 6
+ _D3std3uni13ReallocPolicy6__initZ@Base 6
+ _D3std3uni13floorPowerOf2FNaNbNiNfkZk@Base 6
+ _D3std3uni13graphicalTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13graphicalTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13isPunctuationFNaNbNiNfwZb@Base 6
+ _D3std3uni13isSurrogateHiFNaNbNiNfwZb@Base 6
+ _D3std3uni13isSurrogateLoFNaNbNiNfwZb@Base 6
+ _D3std3uni13lowerCaseTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13lowerCaseTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13upperCaseTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13upperCaseTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni14MatcherConcept6__initZ@Base 6
+ _D3std3uni14__T5forceTkTiZ5forceFNaNbNiNfiZk@Base 6
+ _D3std3uni14combiningClassFNaNbNiNfwZh@Base 6
+ _D3std3uni14decompressFromFNaNfAxhKkZk@Base 6
+ _D3std3uni14isNonCharacterFNaNbNiNfwZb@Base 6
+ _D3std3uni14simpleCaseTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni14simpleCaseTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAaZv@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAuZv@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAwZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAaZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAuZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAwZv@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayZS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZh@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZt@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni15__T7toLowerTAaZ7toLowerFNaNeAaZAa@Base 6
+ _D3std3uni15decomposeHangulFNewZS3std3uni8Grapheme@Base 6
+ _D3std3uni15hangulRecomposeFNaNbNiNeAwZv@Base 6
+ _D3std3uni15punctuationTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni15punctuationTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni15unalignedRead24FNaNbNiNexPhkZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki14Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder19__T8addValueVki2ThZ8addValueMFNaNbNehkZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNehZS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder89__T15spillToNextPageVki2TS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder93__T19spillToNextPageImplVki2TS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekktZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TtZ8addValueMFNaNbNetkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNektZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki16Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekktZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TtZ8addValueMFNaNbNetkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNektZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni16__T7toLowerTAxaZ7toLowerFNaNeAxaZAxa@Base 6
+ _D3std3uni16__T7toLowerTAyaZ7toLowerFNaNeAyaZAya@Base 6
+ _D3std3uni16__T7toLowerTAyuZ7toLowerFNaNeAyuZAyu@Base 6
+ _D3std3uni16__T7toLowerTAywZ7toLowerFNaNbNeAywZAyw@Base 6
+ _D3std3uni16__T7toUpperTAyaZ7toUpperFNaNeAyaZAya@Base 6
+ _D3std3uni16__T7toUpperTAyuZ7toUpperFNaNeAyuZAyu@Base 6
+ _D3std3uni16__T7toUpperTAywZ7toUpperFNaNbNeAywZAyw@Base 6
+ _D3std3uni16canonMappingTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16canonMappingTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16nonCharacterTrieFNaNbNdNiNfZ3resyS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16nonCharacterTrieFNaNbNdNiNfZyS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toLowerIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toLowerIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toTitleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toTitleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toUpperIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toUpperIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16unalignedWrite24FNaNbNiNePhkkZv@Base 6
+ _D3std3uni17CodepointInterval11__xopEqualsFKxS3std3uni17CodepointIntervalKxS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni17CodepointInterval1aMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std3uni17CodepointInterval1bMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std3uni17CodepointInterval43__T8opEqualsTxS3std3uni17CodepointIntervalZ8opEqualsMxFNaNbNiNfxS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni17CodepointInterval6__ctorMFNaNbNcNiNfkkZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni17CodepointInterval6__initZ@Base 6
+ _D3std3uni17__T4icmpTAxaTAxaZ4icmpFNaNeAxaAxaZi@Base 6
+ _D3std3uni17__T4icmpTAxuTAxuZ4icmpFNaNeAxuAxuZi@Base 6
+ _D3std3uni17__T4icmpTAxwTAxwZ4icmpFNaNbNiNeAxwAxwZi@Base 6
+ _D3std3uni17__T8spaceForVki1Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni17__T8spaceForVki7Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni17__T8spaceForVki8Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni17compatMappingTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni17compatMappingTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki3Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki3Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki3Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki3Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki3Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni189__T14loadUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni18__T5sicmpTAxaTAxaZ5sicmpFNaNeAxaAxaZi@Base 6
+ _D3std3uni18__T5sicmpTAxuTAxuZ5sicmpFNaNeAxuAxuZi@Base 6
+ _D3std3uni18__T5sicmpTAxwTAxwZ5sicmpFNaNeAxwAxwZi@Base 6
+ _D3std3uni18__T8spaceForVki11Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki12Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki13Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki14Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki15Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki16Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18combiningClassTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18combiningClassTrieFNaNbNdNiNfZyS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18graphemeExtendTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18graphemeExtendTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18simpleCaseFoldingsFNaNbNewZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range5emptyMxFNaNbNdZb@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range5frontMxFNaNbNdZw@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__ctorMFNaNbNckkZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__ctorMFNaNbNcwZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__initZ@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6lengthMxFNaNbNdZk@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range7isSmallMxFNaNbNdZb@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range8popFrontMFNaNbZv@Base 6
+ _D3std3uni18toLowerSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni18toTitleSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni18toUpperSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni192__T14loadUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni195__T14loadUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni199__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni199__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni19compositionJumpTrieFNaNbNdNiNfZ3resyS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni19compositionJumpTrieFNaNbNdNiNfZyS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni19decompressIntervalsFNaNfAxhZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni19hangulSyllableIndexFNaNbNiNewZi@Base 6
+ _D3std3uni19isRegionalIndicatorFNfwZb@Base 6
+ _D3std3uni20__T9BitPackedTbVki1Z9BitPacked6__initZ@Base 6
+ _D3std3uni20__T9BitPackedTkVki7Z9BitPacked6__initZ@Base 6
+ _D3std3uni20__T9BitPackedTkVki8Z9BitPacked6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki3TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki3Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki2TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki3TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki2TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder19__T8addValueVki3TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder201__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki7Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki11Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki2TS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni21DecompressedIntervals11__xopEqualsFKxS3std3uni21DecompressedIntervalsKxS3std3uni21DecompressedIntervalsZb@Base 6
+ _D3std3uni21DecompressedIntervals4saveMFNaNdNfZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni21DecompressedIntervals5emptyMxFNaNdNfZb@Base 6
+ _D3std3uni21DecompressedIntervals5frontMFNaNdNfZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni21DecompressedIntervals6__ctorMFNaNcNfAxhZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D3std3uni21DecompressedIntervals8popFrontMFNaNfZv@Base 6
+ _D3std3uni21DecompressedIntervals9__xtoHashFNbNeKxS3std3uni21DecompressedIntervalsZk@Base 6
+ _D3std3uni21__T11copyForwardTiTkZ11copyForwardFNaNbNiNfAiAkZv@Base 6
+ _D3std3uni21__T11copyForwardTkTkZ11copyForwardFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni21__T9BitPackedTkVki11Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki12Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki13Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki14Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki15Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki16Z9BitPacked6__initZ@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxaZ12fullCasedCmpFNaNewwKAxaZi@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxuZ12fullCasedCmpFNaNewwKAxuZi@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxwZ12fullCasedCmpFNaNbNiNewwKAxwZi@Base 6
+ _D3std3uni22__T14toLowerInPlaceTaZ14toLowerInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni22__T14toLowerInPlaceTuZ14toLowerInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni22__T14toLowerInPlaceTwZ14toLowerInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTaZ14toUpperInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTuZ14toUpperInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTwZ14toUpperInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni22__T6asTrieTtVii12Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits6__initZ@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni23__T13copyBackwardsTkTkZ13copyBackwardsFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni23__T15packedArrayViewThZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T15packedArrayViewTtZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23genUnrolledSwitchSearchFkZAya@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii4Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii5Vii8Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii6Vii7Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieThVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii8Vii5Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNetkZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNetkZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T16propertyNameLessTaTaZ16propertyNameLessFNaNfAxaAxaZb@Base 6
+ _D3std3uni27__T13replicateBitsVki4Vki8Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki1Vki32Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki2Vki16Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki32Vki1Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T20isPrettyPropertyNameTaZ20isPrettyPropertyNameFNaNfxAaZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZi@Base 6
+ _D3std3uni29__T6asTrieTbVii7Vii4Vii4Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T16codepointSetTrieVii13Vii8Z87__T16codepointSetTrieTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16codepointSetTrieFNaNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNehkkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl77__T8opEqualsTS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl78__T8opEqualsTxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNetkZv@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNetkkZv@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl78__T8opEqualsTS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl79__T8opEqualsTxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray10__postblitMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray11__T6appendZ6appendMFNaNbNeAkXv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray11__xopEqualsFKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray12__T7opIndexZ7opIndexMxFNaNbNiNekZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray13__T8opEqualsZ8opEqualsMxFNaNbNiNeKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray13opIndexAssignMFNaNbNekkZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray14__T6__ctorTAkZ6__ctorMFNaNbNcNeAkZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray16dupThisReferenceMFNaNbNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray17freeThisReferenceMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray5reuseFNaNbNeAkZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray673__T6__ctorTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ6__ctorMFNaNcNeS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__dtorMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6lengthMFNaNbNdNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMFNaNbNeZAk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMFNaNbNekkZAk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMxFNaNbNiNeZAxk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMxFNaNbNiNekkZAxk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8opAssignMFNaNbNcNiNjNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8refCountMFNaNbNdNiNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8refCountMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray9__xtoHashFNbNeKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList10byIntervalMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11addIntervalMFNaNbNeiikZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange5frontMxFNaNbNdNiNeZw@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__ctorMFNaNbNcNiNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12__T7scanForZ7scanForMxFNaNbNiNewZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ41__T6bisectTAS3std3uni17CodepointIntervalZ6bisectFAS3std3uni17CodepointIntervalkAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ47__T11binaryScopeTAS3std3uni17CodepointIntervalZ11binaryScopeFAS3std3uni17CodepointIntervalAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ47__T11linearScopeTAS3std3uni17CodepointIntervalZ11linearScopeFNaNfAS3std3uni17CodepointIntervalAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals13opIndexAssignMFNaNbNiNeS3std3uni17CodepointIntervalkZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4backMFNaNbNdNiNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4backMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4saveMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5frontMFNaNbNdNiNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5frontMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__ctorMFNaNbNcNiNeAkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__ctorMFNaNbNcNiNeAkkkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7opIndexMxFNaNbNiNekZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7opSliceMFNaNbNiNekkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7popBackMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList19__T13fromIntervalsZ13fromIntervalsFNaNbNeAkXS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList27__T10opOpAssignVAyaa1_7cTkZ10opOpAssignMFNaNbNcNekZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList27__T10opOpAssignVAyaa1_7cTwZ10opOpAssignMFNaNbNcNewZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList52__T13fromIntervalsTS3std3uni21DecompressedIntervalsZ13fromIntervalsFNaNeS3std3uni21DecompressedIntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals13opIndexAssignMFNaNbNeS3std3uni17CodepointIntervalkZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4backMFNaNbNdNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4backMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4saveMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5frontMFNaNbNdNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5frontMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__ctorMFNaNbNcNiNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__ctorMFNaNbNcNiNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraykkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7opIndexMxFNaNbNiNekZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7opSliceMFNaNbNiNekkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7popBackMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList73__T3addTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ3addMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList73__T3subTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ3subMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList76__T6__ctorTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ6__ctorMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList79__T9intersectTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ9intersectMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList7opIndexMxFNaNbNiNekZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList7subCharMFNaNbNcNewZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList87__T8opBinaryVAyaa1_26TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ8opBinaryMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList87__T8opBinaryVAyaa1_7cTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ8opBinaryMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8__T3addZ3addMFNaNbNcNekkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8dropUpToMFNaNbNekkZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8invertedMFNaNbNdNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ72__T9__lambda1TS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ9__lambda1FNaNbNiNfS3std3uni17CodepointIntervalS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8skipUpToMFNaNbNekkZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8toStringMFNeMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_26TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_2dTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_7cTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_7eTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray10__postblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray11__xopEqualsFKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray13__T8opEqualsZ8opEqualsMxFNaNbNiNeKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray13opIndexAssignMFNekkZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray16dupThisReferenceMFNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray17freeThisReferenceMFNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray5reuseFNeAkZS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__dtorMFNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__initZ@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6lengthMFNdNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMFNeZAk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMFNekkZAk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMxFNaNbNiNeZAxk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMxFNaNbNiNekkZAxk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8opAssignMFNbNcNiNjNeS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8refCountMFNaNbNdNiNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8refCountMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray9__xtoHashFNbNeKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZk@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed11__xopEqualsFKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed13opIndexAssignMFNaNbNiNfwkZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4backMFNaNbNdNiNfwZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4backMxFNaNbNdNiNfZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4saveMNgFNaNbNdNiNfZNgS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5frontMFNaNbNdNiNfwZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5frontMxFNaNbNdNiNfZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6__initZ@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opIndexMxFNaNbNiNfkZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opSliceMFNaNbNiNfZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opSliceMFNaNbNiNfkkZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7popBackMFNaNbNiNfZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed85__T8opEqualsTxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZ8opEqualsMxFNaNbNiNfKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed8opDollarMxFNaNbNiNfZk@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3uni41__T16sliceOverIndexedTS3std3uni8GraphemeZ16sliceOverIndexedFNaNbNiNfkkPS3std3uni8GraphemeZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni4icmpFNaNfAxaAxaZi@Base 6
+ _D3std3uni4icmpFNaNfAxuAxuZi@Base 6
+ _D3std3uni4icmpFNaNfAxwAxwZi@Base 6
+ _D3std3uni51__T10assumeSizeS28_D3std3uni5low_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D3std3uni52__T10sharMethodS333std3uni23switchUniformLowerBoundZ37__T10sharMethodVAyaa4_613c3d62TAxkTkZ10sharMethodFNaNbNiNfAxkkZk@Base 6
+ _D3std3uni54__T10assumeSizeS31_D3std3uni8midlow_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D3std3uni54__T5forceTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni54__T5forceTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni5asSetFNaNfAxhZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni5low_8FNaNbNiNfkZk@Base 6
+ _D3std3uni5sicmpFNaNfAxaAxaZi@Base 6
+ _D3std3uni5sicmpFNaNfAxuAxuZi@Base 6
+ _D3std3uni5sicmpFNaNfAxwAxwZi@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayZk@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTkVki7Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki11Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki14Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki16Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl11simpleWriteMFNaNbNiNebkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl13opIndexAssignMFNaNbNiNebkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni6hangLVFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6hangLVFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6isMarkFNaNbNiNfwZb@Base 6
+ _D3std3uni6mcTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6mcTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6read24FNaNbNiNfxPhkZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl117__T8opEqualsTS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNebkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNebkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni78__T14genericReplaceTvTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayTAiZ14genericReplaceFNaNbNeKS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraykkAiZk@Base 6
+ _D3std3uni78__T14genericReplaceTvTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayTAkZ14genericReplaceFNaNbNeKS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraykkAkZk@Base 6
+ _D3std3uni7composeFNaNbNewwZw@Base 6
+ _D3std3uni7hangLVTFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni7hangLVTFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni7isAlphaFNaNbNiNfwZb@Base 6
+ _D3std3uni7isJamoLFNaNbNiNewZb@Base 6
+ _D3std3uni7isJamoTFNaNbNiNewZb@Base 6
+ _D3std3uni7isJamoVFNaNbNiNewZb@Base 6
+ _D3std3uni7isLowerFNaNbNiNfwZb@Base 6
+ _D3std3uni7isSpaceFNaNbNiNfwZb@Base 6
+ _D3std3uni7isUpperFNaNbNiNfwZb@Base 6
+ _D3std3uni7isWhiteFNaNbNiNfwZb@Base 6
+ _D3std3uni7toLowerFNaNbNiNfwZw@Base 6
+ _D3std3uni7toLowerFNaNfAyaZAya@Base 6
+ _D3std3uni7toLowerFNaNfAyuZAyu@Base 6
+ _D3std3uni7toLowerFNaNfAywZAyw@Base 6
+ _D3std3uni7toUpperFNaNbNiNfwZw@Base 6
+ _D3std3uni7toUpperFNaNfAyaZAya@Base 6
+ _D3std3uni7toUpperFNaNfAyuZAyu@Base 6
+ _D3std3uni7toUpperFNaNfAywZAyw@Base 6
+ _D3std3uni7unicode13__T6opCallTaZ6opCallFNaNfxAaZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode18hangulSyllableType6__initZ@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4c43Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d63Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d65Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d6eZ10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4e64Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_5063Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode44__T10opDispatchVAyaa10_416c7068616265746963Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode46__T10opDispatchVAyaa11_57686974655f5370616365Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode5block6__initZ@Base 6
+ _D3std3uni7unicode6__initZ@Base 6
+ _D3std3uni7unicode6script6__initZ@Base 6
+ _D3std3uni7unicode79__T7loadAnyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ7loadAnyFNaNfxAaZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode7findAnyFNfAyaZb@Base 6
+ _D3std3uni7write24FNaNbNiNfPhkkZv@Base 6
+ _D3std3uni85__T12loadPropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ12loadPropertyFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni8GcPolicy12__T5allocTkZ5allocFNaNbNekZAk@Base 6
+ _D3std3uni8GcPolicy14__T7reallocTkZ7reallocFNaNbNeAkkZAk@Base 6
+ _D3std3uni8GcPolicy15__T6appendTkTiZ6appendFNaNbNeKAkiZv@Base 6
+ _D3std3uni8GcPolicy15__T7destroyTAkZ7destroyFNaNbNiNeKAkZv@Base 6
+ _D3std3uni8GcPolicy6__initZ@Base 6
+ _D3std3uni8Grapheme10__postblitMFNeZv@Base 6
+ _D3std3uni8Grapheme11smallLengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni8Grapheme12convertToBigMFNeZv@Base 6
+ _D3std3uni8Grapheme13__T6__ctorTiZ6__ctorMFNcNexAiXS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme13__T6__ctorTwZ6__ctorMFNcNexAwXS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme13opIndexAssignMFNaNbNiNewkZv@Base 6
+ _D3std3uni8Grapheme25__T10opOpAssignVAyaa1_7eZ10opOpAssignMFNcNewZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxiZ10opOpAssignMFNcNeAxiZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxwZ10opOpAssignMFNcNeAxwZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme5isBigMxFNaNbNdNiNeZh@Base 6
+ _D3std3uni8Grapheme6__dtorMFNeZv@Base 6
+ _D3std3uni8Grapheme6__initZ@Base 6
+ _D3std3uni8Grapheme6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni8Grapheme6setBigMFNaNbNiNeZv@Base 6
+ _D3std3uni8Grapheme7opIndexMxFNaNbNiNekZw@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNiZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNikkZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme8opAssignMFNcNjNeS3std3uni8GraphemeZS3std3uni8Grapheme@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAakwZk@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAwkwZk@Base 6
+ _D3std3uni8encodeToFNaNeAukwZk@Base 6
+ _D3std3uni8isFormatFNaNbNiNfwZb@Base 6
+ _D3std3uni8isNumberFNaNbNiNfwZb@Base 6
+ _D3std3uni8isSymbolFNaNbNiNfwZb@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8midlow_8FNaNbNiNfkZk@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni20__T9BitPackedTkVki7Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVki7Z9BitPackedZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVki8Z9BitPackedZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki11Z9BitPackedZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki12Z9BitPackedZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki13Z9BitPackedZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki14Z9BitPackedZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki15Z9BitPackedZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki16Z9BitPackedZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni97__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAaZ6toCaseFNaNeAaZAa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAxaZ6toCaseFNaNeAxaZAxa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9isControlFNaNbNiNfwZb@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9recomposeFNaNbNekAwAhZk@Base 6
+ _D3std3uri10URI_EncodeFAywkZAya@Base 6
+ _D3std3uri12URIException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3uri12URIException@Base 6
+ _D3std3uri12URIException6__initZ@Base 6
+ _D3std3uri12URIException6__vtblZ@Base 6
+ _D3std3uri12URIException7__ClassZ@Base 6
+ _D3std3uri12__ModuleInfoZ@Base 6
+ _D3std3uri18_sharedStaticCtor1FZ6helperFyAakZv@Base 6
+ _D3std3uri18_sharedStaticCtor1FZv@Base 6
+ _D3std3uri9ascii2hexFwZk@Base 6
+ _D3std3uri9hex2asciiyG16a@Base 6
+ _D3std3uri9uri_flagsG128h@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNeKAyaJkZw@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNfKAyaZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFKAaKkZ17__T9exceptionTAaZ9exceptionFNaNfAaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFNaKAaKkZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ10decodeImplFNaKAuKkZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ10decodeImplFNaKAwKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFKAxaKkZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFNaKAxaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ10decodeImplFNaKAxuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ10decodeImplFNaKAxwKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFKAyaKkZ18__T9exceptionTAyaZ9exceptionFNaNfAyaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFNaKAyaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFKxAaKkZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFNaKxAaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ10decodeImplFNaKxAuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ10decodeImplFNaKxAwKkZw@Base 6
+ _D3std3utf10strideImplFNaNeakZk@Base 6
+ _D3std3utf12UTFException11setSequenceMFNaNbNiNfAkXC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNfAyakAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__initZ@Base 6
+ _D3std3utf12UTFException6__vtblZ@Base 6
+ _D3std3utf12UTFException7__ClassZ@Base 6
+ _D3std3utf12UTFException8toStringMFZAya@Base 6
+ _D3std3utf12__ModuleInfoZ@Base 6
+ _D3std3utf12isValidDcharFNaNbNiNfwZb@Base 6
+ _D3std3utf14__T6byCharTAaZ6byCharFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf14__T6strideTAaZ6strideFNaNfAaZk@Base 6
+ _D3std3utf14__T6toUTFzTPaZ15__T6toUTFzTAyaZ6toUTFzFNaNbNfAyaZPa@Base 6
+ _D3std3utf15__T6byCharTAxaZ6byCharFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6byCharTAyaZ6byCharFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfAxakZk@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfKAxakZk@Base 6
+ _D3std3utf15__T6strideTAyaZ6strideFNaNfKAyakZk@Base 6
+ _D3std3utf16__T7byDcharTAyaZ7byDcharFNaNbNiNfAyaZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf17__T8validateTAxaZ8validateFNaNfxAaZv@Base 6
+ _D3std3utf17__T8validateTAxuZ8validateFNaNfxAuZv@Base 6
+ _D3std3utf17__T8validateTAxwZ8validateFNaNfxAwZv@Base 6
+ _D3std3utf18__T10codeLengthTaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTuZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTwZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10toUCSindexTaZ10toUCSindexFNaNfAxakZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10codeLengthTyaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10strideBackTAxaZ10strideBackFNaNfKAxakZk@Base 6
+ _D3std3utf20__T10strideBackTAyaZ10strideBackFNaNfKAyakZk@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAxaZ10toUTFzImplFNaNbNfAxaZPa@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAyaZ10toUTFzImplFNaNbNfAyaZPa@Base 6
+ _D3std3utf28__T20canSearchInCodeUnitsTaZ20canSearchInCodeUnitsFNaNbNiNfwZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNaNbNiNfS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl11__xopEqualsFKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl4saveMFNaNbNdNiNfZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl5frontMFNaNbNdNiNfZa@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl6__ctorMFNaNbNcNiNfKS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl6__initZ@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl9__xtoHashFNbNeKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZk@Base 6
+ _D3std3utf6encodeFNaNfKAawZv@Base 6
+ _D3std3utf6encodeFNaNfKAuwZv@Base 6
+ _D3std3utf6encodeFNaNfKAwwZv@Base 6
+ _D3std3utf6encodeFNaNfKG2uwZk@Base 6
+ _D3std3utf6encodeFNaNfKG4awZk@Base 6
+ _D3std3utf6toUTF8FNaNbNiNfNkJG4awZAa@Base 6
+ _D3std3utf6toUTF8FNaNfxAaZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAuZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAwZAya@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl11__xopEqualsFKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl4saveMFNaNbNdNiNfZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5frontMFNaNbNdNiNfZw@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__ctorMFNaNbNcNiNfKS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl9__xtoHashFNbNeKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZk@Base 6
+ _D3std3utf7toUTF16FNaNbNiNfNkKG2uwZAu@Base 6
+ _D3std3utf7toUTF16FNaNfxAaZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAuZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAwZAyu@Base 6
+ _D3std3utf7toUTF32FNaNfxAaZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAuZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAwZAyw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ6decodeFNaNeKAaKkZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ6decodeFNaNeKAuKkZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ6decodeFNaNeKAwKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ6decodeFNaNeKAxaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ6decodeFNaNeKAxuKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ6decodeFNaNeKAxwKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ6decodeFNaNeKAyaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ6decodeFNaNeKxAaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ6decodeFNaNeKxAuKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ6decodeFNaNeKxAwKkZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNeKAaJkZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNfKAaZw@Base 6
+ _D3std3xml10DigitTableyAi@Base 6
+ _D3std3xml10checkCharsFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkCharsFKAyaZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZv@Base 6
+ _D3std3xml10isBaseCharFwZb@Base 6
+ _D3std3xml10isExtenderFwZb@Base 6
+ _D3std3xml111__T4starS99_D3std3xml76__T3seqS29_D3std3xml10checkSpaceFKAyaZvS33_D3std3xml14checkAttributeFKAyaZvZ3seqFKAyaZvZ4starFKAyaZv@Base 6
+ _D3std3xml112__T3seqS35_D3std3xml16checkDocTypeDeclFKAyaZvS63_D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZvZ3seqFKAyaZv@Base 6
+ _D3std3xml11PIException6__ctorMFAyaZC3std3xml11PIException@Base 6
+ _D3std3xml11PIException6__initZ@Base 6
+ _D3std3xml11PIException6__vtblZ@Base 6
+ _D3std3xml11PIException7__ClassZ@Base 6
+ _D3std3xml11XIException6__ctorMFAyaZC3std3xml11XIException@Base 6
+ _D3std3xml11XIException6__initZ@Base 6
+ _D3std3xml11XIException6__vtblZ@Base 6
+ _D3std3xml11XIException7__ClassZ@Base 6
+ _D3std3xml11checkCDSectFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkCDSectFKAyaZv@Base 6
+ _D3std3xml11checkPrologFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkPrologFKAyaZv@Base 6
+ _D3std3xml11checkSDDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkSDDeclFKAyaZv@Base 6
+ _D3std3xml12TagException6__ctorMFAyaZC3std3xml12TagException@Base 6
+ _D3std3xml12TagException6__initZ@Base 6
+ _D3std3xml12TagException6__vtblZ@Base 6
+ _D3std3xml12TagException7__ClassZ@Base 6
+ _D3std3xml12XMLException6__ctorMFAyaZC3std3xml12XMLException@Base 6
+ _D3std3xml12XMLException6__initZ@Base 6
+ _D3std3xml12XMLException6__vtblZ@Base 6
+ _D3std3xml12XMLException7__ClassZ@Base 6
+ _D3std3xml12__ModuleInfoZ@Base 6
+ _D3std3xml12checkCharRefFKAyaJwZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkCharRefFKAyaJwZv@Base 6
+ _D3std3xml12checkCommentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkCommentFKAyaZv@Base 6
+ _D3std3xml12checkContentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkContentFKAyaZv@Base 6
+ _D3std3xml12checkElementFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkElementFKAyaZv@Base 6
+ _D3std3xml12checkEncNameFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkEncNameFKAyaZv@Base 6
+ _D3std3xml12checkLiteralFAyaKAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkLiteralFAyaKAyaZv@Base 6
+ _D3std3xml12checkXMLDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkXMLDeclFKAyaZv@Base 6
+ _D3std3xml13BaseCharTableyAi@Base 6
+ _D3std3xml13ElementParser3tagMxFNdZxC3std3xml3Tag@Base 6
+ _D3std3xml13ElementParser4onPIMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser4onXIMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser5parseMFZv@Base 6
+ _D3std3xml13ElementParser6__ctorMFC3std3xml13ElementParserZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__ctorMFC3std3xml3TagPAyaZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__ctorMFZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__initZ@Base 6
+ _D3std3xml13ElementParser6__vtblZ@Base 6
+ _D3std3xml13ElementParser6onTextMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser7__ClassZ@Base 6
+ _D3std3xml13ElementParser7onCDataMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser8toStringMxFZAya@Base 6
+ _D3std3xml13ElementParser9onCommentMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser9onTextRawMFDFAyaZvZv@Base 6
+ _D3std3xml13ExtenderTableyAi@Base 6
+ _D3std3xml13TextException6__ctorMFAyaZC3std3xml13TextException@Base 6
+ _D3std3xml13TextException6__initZ@Base 6
+ _D3std3xml13TextException6__vtblZ@Base 6
+ _D3std3xml13TextException7__ClassZ@Base 6
+ _D3std3xml13checkAttValueFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkAttValueFKAyaZv@Base 6
+ _D3std3xml13checkCharDataFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkCharDataFKAyaZv@Base 6
+ _D3std3xml13checkDocumentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkDocumentFKAyaZv@Base 6
+ _D3std3xml13isIdeographicFwZb@Base 6
+ _D3std3xml148__T3optS136_D3std3xml112__T3seqS35_D3std3xml16checkDocTypeDeclFKAyaZvS63_D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZvZ3seqFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml14CDataException6__ctorMFAyaZC3std3xml14CDataException@Base 6
+ _D3std3xml14CDataException6__initZ@Base 6
+ _D3std3xml14CDataException6__vtblZ@Base 6
+ _D3std3xml14CDataException7__ClassZ@Base 6
+ _D3std3xml14CheckException6__ctorMFAyaAyaC3std3xml14CheckExceptionZC3std3xml14CheckException@Base 6
+ _D3std3xml14CheckException6__initZ@Base 6
+ _D3std3xml14CheckException6__vtblZ@Base 6
+ _D3std3xml14CheckException7__ClassZ@Base 6
+ _D3std3xml14CheckException8completeMFAyaZv@Base 6
+ _D3std3xml14CheckException8toStringMxFZAya@Base 6
+ _D3std3xml14DocumentParser6__ctorMFAyaZC3std3xml14DocumentParser@Base 6
+ _D3std3xml14DocumentParser6__initZ@Base 6
+ _D3std3xml14DocumentParser6__vtblZ@Base 6
+ _D3std3xml14DocumentParser7__ClassZ@Base 6
+ _D3std3xml14XMLInstruction10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml14XMLInstruction5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml14XMLInstruction6__ctorMFAyaZC3std3xml14XMLInstruction@Base 6
+ _D3std3xml14XMLInstruction6__initZ@Base 6
+ _D3std3xml14XMLInstruction6__vtblZ@Base 6
+ _D3std3xml14XMLInstruction6toHashMxFNbNfZk@Base 6
+ _D3std3xml14XMLInstruction7__ClassZ@Base 6
+ _D3std3xml14XMLInstruction8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml14XMLInstruction8toStringMxFZAya@Base 6
+ _D3std3xml14checkAttributeFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkAttributeFKAyaZv@Base 6
+ _D3std3xml14checkEntityRefFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkEntityRefFKAyaZv@Base 6
+ _D3std3xml14checkReferenceFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkReferenceFKAyaZv@Base 6
+ _D3std3xml15DecodeException6__ctorMFAyaZC3std3xml15DecodeException@Base 6
+ _D3std3xml15DecodeException6__initZ@Base 6
+ _D3std3xml15DecodeException6__vtblZ@Base 6
+ _D3std3xml15DecodeException7__ClassZ@Base 6
+ _D3std3xml15__T6encodeTAyaZ6encodeFNaNbNfAyaZAya@Base 6
+ _D3std3xml15checkVersionNumFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml15checkVersionNumFKAyaZv@Base 6
+ _D3std3xml15isCombiningCharFwZb@Base 6
+ _D3std3xml16CommentException6__ctorMFAyaZC3std3xml16CommentException@Base 6
+ _D3std3xml16CommentException6__initZ@Base 6
+ _D3std3xml16CommentException6__vtblZ@Base 6
+ _D3std3xml16CommentException7__ClassZ@Base 6
+ _D3std3xml16IdeographicTableyAi@Base 6
+ _D3std3xml16checkDocTypeDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml16checkDocTypeDeclFKAyaZv@Base 6
+ _D3std3xml16checkVersionInfoFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml16checkVersionInfoFKAyaZv@Base 6
+ _D3std3xml17checkEncodingDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml17checkEncodingDeclFKAyaZv@Base 6
+ _D3std3xml18CombiningCharTableyAi@Base 6
+ _D3std3xml20InvalidTypeException6__ctorMFAyaZC3std3xml20InvalidTypeException@Base 6
+ _D3std3xml20InvalidTypeException6__initZ@Base 6
+ _D3std3xml20InvalidTypeException6__vtblZ@Base 6
+ _D3std3xml20InvalidTypeException7__ClassZ@Base 6
+ _D3std3xml21ProcessingInstruction10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml21ProcessingInstruction5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml21ProcessingInstruction6__ctorMFAyaZC3std3xml21ProcessingInstruction@Base 6
+ _D3std3xml21ProcessingInstruction6__initZ@Base 6
+ _D3std3xml21ProcessingInstruction6__vtblZ@Base 6
+ _D3std3xml21ProcessingInstruction6toHashMxFNbNfZk@Base 6
+ _D3std3xml21ProcessingInstruction7__ClassZ@Base 6
+ _D3std3xml21ProcessingInstruction8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml21ProcessingInstruction8toStringMxFZAya@Base 6
+ _D3std3xml26__T6toTypeTxC3std3xml3TagZ6toTypeFC6ObjectZxC3std3xml3Tag@Base 6
+ _D3std3xml27__T6toTypeTxC3std3xml4ItemZ6toTypeFC6ObjectZxC3std3xml4Item@Base 6
+ _D3std3xml30__T6toTypeTxC3std3xml7ElementZ6toTypeFC6ObjectZxC3std3xml7Element@Base 6
+ _D3std3xml31__T6toTypeTxC3std3xml8DocumentZ6toTypeFC6ObjectZxC3std3xml8Document@Base 6
+ _D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZv@Base 6
+ _D3std3xml3Tag11__invariantMxFZv@Base 6
+ _D3std3xml3Tag11toEndStringMxFZAya@Base 6
+ _D3std3xml3Tag12__invariant6MxFZv@Base 6
+ _D3std3xml3Tag13toEmptyStringMxFZAya@Base 6
+ _D3std3xml3Tag13toStartStringMxFZAya@Base 6
+ _D3std3xml3Tag14toNonEndStringMxFZAya@Base 6
+ _D3std3xml3Tag5isEndMxFNdZb@Base 6
+ _D3std3xml3Tag5opCmpMxFC6ObjectZi@Base 6
+ _D3std3xml3Tag6__ctorMFAyaE3std3xml7TagTypeZC3std3xml3Tag@Base 6
+ _D3std3xml3Tag6__ctorMFKAyabZC3std3xml3Tag@Base 6
+ _D3std3xml3Tag6__initZ@Base 6
+ _D3std3xml3Tag6__vtblZ@Base 6
+ _D3std3xml3Tag6toHashMxFNbNfZk@Base 6
+ _D3std3xml3Tag7__ClassZ@Base 6
+ _D3std3xml3Tag7isEmptyMxFNdZb@Base 6
+ _D3std3xml3Tag7isStartMxFNdZb@Base 6
+ _D3std3xml3Tag8opEqualsMxFC6ObjectZb@Base 6
+ _D3std3xml3Tag8toStringMxFZAya@Base 6
+ _D3std3xml40__T3optS29_D3std3xml10checkSpaceFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml41__T3optS30_D3std3xml11checkSDDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml42__T3optS31_D3std3xml12checkXMLDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml45__T6quotedS31_D3std3xml12checkEncNameFKAyaZvZ6quotedFKAyaZv@Base 6
+ _D3std3xml47__T3optS36_D3std3xml17checkEncodingDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml48__T6quotedS34_D3std3xml15checkVersionNumFKAyaZvZ6quotedFKAyaZv@Base 6
+ _D3std3xml4Item6__initZ@Base 6
+ _D3std3xml4Item6__vtblZ@Base 6
+ _D3std3xml4Item6prettyMxFkZAAya@Base 6
+ _D3std3xml4Item7__ClassZ@Base 6
+ _D3std3xml4Text10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml4Text5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml4Text6__ctorMFAyaZC3std3xml4Text@Base 6
+ _D3std3xml4Text6__initZ@Base 6
+ _D3std3xml4Text6__vtblZ@Base 6
+ _D3std3xml4Text6toHashMxFNbNfZk@Base 6
+ _D3std3xml4Text7__ClassZ@Base 6
+ _D3std3xml4Text8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml4Text8toStringMxFZAya@Base 6
+ _D3std3xml4chopFKAyakZAya@Base 6
+ _D3std3xml4exitFAyaZv@Base 6
+ _D3std3xml4hashFNbNeAyakZk@Base 6
+ _D3std3xml4optcFKAyaaZb@Base 6
+ _D3std3xml4reqcFKAyaaZv@Base 6
+ _D3std3xml5CData10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml5CData5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml5CData6__ctorMFAyaZC3std3xml5CData@Base 6
+ _D3std3xml5CData6__initZ@Base 6
+ _D3std3xml5CData6__vtblZ@Base 6
+ _D3std3xml5CData6toHashMxFNbNfZk@Base 6
+ _D3std3xml5CData7__ClassZ@Base 6
+ _D3std3xml5CData8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml5CData8toStringMxFZAya@Base 6
+ _D3std3xml5checkFAyaZv@Base 6
+ _D3std3xml6decodeFAyaE3std3xml10DecodeModeZAya@Base 6
+ _D3std3xml6isCharFwZb@Base 6
+ _D3std3xml6lookupFAxiiZb@Base 6
+ _D3std3xml76__T3seqS29_D3std3xml10checkSpaceFKAyaZvS33_D3std3xml14checkAttributeFKAyaZvZ3seqFKAyaZv@Base 6
+ _D3std3xml7Comment10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml7Comment5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml7Comment6__ctorMFAyaZC3std3xml7Comment@Base 6
+ _D3std3xml7Comment6__initZ@Base 6
+ _D3std3xml7Comment6__vtblZ@Base 6
+ _D3std3xml7Comment6toHashMxFNbNfZk@Base 6
+ _D3std3xml7Comment7__ClassZ@Base 6
+ _D3std3xml7Comment8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml7Comment8toStringMxFZAya@Base 6
+ _D3std3xml7Element10appendItemMFC3std3xml4ItemZv@Base 6
+ _D3std3xml7Element10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml21ProcessingInstructionZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml4TextZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml5CDataZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml7CommentZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml7ElementZv@Base 6
+ _D3std3xml7Element4textMxFE3std3xml10DecodeModeZAya@Base 6
+ _D3std3xml7Element5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml7Element5parseMFC3std3xml13ElementParserZv@Base 6
+ _D3std3xml7Element6__ctorMFAyaAyaZC3std3xml7Element@Base 6
+ _D3std3xml7Element6__ctorMFxC3std3xml3TagZC3std3xml7Element@Base 6
+ _D3std3xml7Element6__initZ@Base 6
+ _D3std3xml7Element6__vtblZ@Base 6
+ _D3std3xml7Element6prettyMxFkZAAya@Base 6
+ _D3std3xml7Element6toHashMxFNbNfZk@Base 6
+ _D3std3xml7Element7__ClassZ@Base 6
+ _D3std3xml7Element8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml7Element8toStringMxFZAya@Base 6
+ _D3std3xml7checkEqFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml7checkEqFKAyaZv@Base 6
+ _D3std3xml7checkPIFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml7checkPIFKAyaZv@Base 6
+ _D3std3xml7isDigitFwZb@Base 6
+ _D3std3xml7isSpaceFwZb@Base 6
+ _D3std3xml7startOfFAyaZAya@Base 6
+ _D3std3xml8Document5opCmpMxFC6ObjectZi@Base 6
+ _D3std3xml8Document6__ctorMFAyaZC3std3xml8Document@Base 6
+ _D3std3xml8Document6__ctorMFxC3std3xml3TagZC3std3xml8Document@Base 6
+ _D3std3xml8Document6__initZ@Base 6
+ _D3std3xml8Document6__vtblZ@Base 6
+ _D3std3xml8Document6toHashMxFNbNeZk@Base 6
+ _D3std3xml8Document7__ClassZ@Base 6
+ _D3std3xml8Document8opEqualsMxFC6ObjectZb@Base 6
+ _D3std3xml8Document8toStringMxFZAya@Base 6
+ _D3std3xml8checkEndFAyaKAyaZv@Base 6
+ _D3std3xml8checkTagFKAyaJAyaJAyaZ8__mixin44failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml8checkTagFKAyaJAyaJAyaZv@Base 6
+ _D3std3xml8isLetterFwZb@Base 6
+ _D3std3xml9CharTableyAi@Base 6
+ _D3std3xml9checkETagFKAyaJAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkETagFKAyaJAyaZv@Base 6
+ _D3std3xml9checkMiscFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkMiscFKAyaZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZ8__mixin34failMFZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZv@Base 6
+ _D3std3zip10ZipArchive10diskNumberMFNdZk@Base 6
+ _D3std3zip10ZipArchive10numEntriesMFNdZk@Base 6
+ _D3std3zip10ZipArchive12deleteMemberMFC3std3zip13ArchiveMemberZv@Base 6
+ _D3std3zip10ZipArchive12diskStartDirMFNdZk@Base 6
+ _D3std3zip10ZipArchive12eocd64Lengthxi@Base 6
+ _D3std3zip10ZipArchive12totalEntriesMFNdZk@Base 6
+ _D3std3zip10ZipArchive14digiSignLengthxi@Base 6
+ _D3std3zip10ZipArchive15eocd64LocLengthxi@Base 6
+ _D3std3zip10ZipArchive19zip64ExtractVersionxt@Base 6
+ _D3std3zip10ZipArchive4dataMFNdZAh@Base 6
+ _D3std3zip10ZipArchive5buildMFZAv@Base 6
+ _D3std3zip10ZipArchive6__ctorMFAvZC3std3zip10ZipArchive@Base 6
+ _D3std3zip10ZipArchive6__ctorMFZC3std3zip10ZipArchive@Base 6
+ _D3std3zip10ZipArchive6__initZ@Base 6
+ _D3std3zip10ZipArchive6__vtblZ@Base 6
+ _D3std3zip10ZipArchive6expandMFC3std3zip13ArchiveMemberZAh@Base 6
+ _D3std3zip10ZipArchive7__ClassZ@Base 6
+ _D3std3zip10ZipArchive7getUintMFiZk@Base 6
+ _D3std3zip10ZipArchive7isZip64MFNdZb@Base 6
+ _D3std3zip10ZipArchive7isZip64MFNdbZv@Base 6
+ _D3std3zip10ZipArchive7putUintMFikZv@Base 6
+ _D3std3zip10ZipArchive8getUlongMFiZm@Base 6
+ _D3std3zip10ZipArchive8putUlongMFimZv@Base 6
+ _D3std3zip10ZipArchive9addMemberMFC3std3zip13ArchiveMemberZv@Base 6
+ _D3std3zip10ZipArchive9directoryMFNdZHAyaC3std3zip13ArchiveMember@Base 6
+ _D3std3zip10ZipArchive9getUshortMFiZt@Base 6
+ _D3std3zip10ZipArchive9putUshortMFitZv@Base 6
+ _D3std3zip12ZipException6__ctorMFAyaZC3std3zip12ZipException@Base 6
+ _D3std3zip12ZipException6__initZ@Base 6
+ _D3std3zip12ZipException6__vtblZ@Base 6
+ _D3std3zip12ZipException7__ClassZ@Base 6
+ _D3std3zip12__ModuleInfoZ@Base 6
+ _D3std3zip13ArchiveMember10diskNumberMFNdZt@Base 6
+ _D3std3zip13ArchiveMember11madeVersionMNgFNaNbNcNdNfZNgt@Base 6
+ _D3std3zip13ArchiveMember12expandedDataMFNdAhZv@Base 6
+ _D3std3zip13ArchiveMember12expandedDataMFNdZAh@Base 6
+ _D3std3zip13ArchiveMember12expandedSizeMFNdZk@Base 6
+ _D3std3zip13ArchiveMember14compressedDataMFNdZAh@Base 6
+ _D3std3zip13ArchiveMember14compressedSizeMFNdZk@Base 6
+ _D3std3zip13ArchiveMember14extractVersionMFNdZt@Base 6
+ _D3std3zip13ArchiveMember14fileAttributesMFNdkZv@Base 6
+ _D3std3zip13ArchiveMember14fileAttributesMxFNdZk@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdE3std3zip17CompressionMethodZv@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdZE3std3zip17CompressionMethod@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdtZv@Base 6
+ _D3std3zip13ArchiveMember18externalAttributesMNgFNaNbNcNdNfZNgk@Base 6
+ _D3std3zip13ArchiveMember4timeMFNdS3std8datetime7SysTimeZv@Base 6
+ _D3std3zip13ArchiveMember4timeMFNdkZv@Base 6
+ _D3std3zip13ArchiveMember4timeMxFNdZk@Base 6
+ _D3std3zip13ArchiveMember5crc32MFNdZk@Base 6
+ _D3std3zip13ArchiveMember6__initZ@Base 6
+ _D3std3zip13ArchiveMember6__vtblZ@Base 6
+ _D3std3zip13ArchiveMember7__ClassZ@Base 6
+ _D3std4conv103__T7emplaceTC3std12experimental6logger4core16StdForwardLoggerTE3std12experimental6logger4core8LogLevelZ7emplaceFAvE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core16StdForwardLogger@Base 6
+ _D3std4conv104__T8textImplTAyaTAyaTPvTAyaTiTAyaTiTAyaTaTAyaThTAyaThTAyaTbTAyaTbTAyaTbTAyaTbTAyaTbTAyaTAxaTAyaTAxaTAyaZ8textImplFNaNfAyaPvAyaiAyaiAyaaAyahAyahAyabAyabAyabAyabAyabAyaAxaAyaAxaAyaZAya@Base 6
+ _D3std4conv10parseErrorFNaNfLAyaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTAaZ2toFNaNbNfAaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTPaZ2toFNaNbPaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTPvZ2toFNaNfPvZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxaZ2toFNaNfxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxdZ2toFNfxdZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxlZ2toFNaNbNfxlZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxmZ2toFNaNbNfxmZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTyhZ2toFNaNbNfyhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ114__T2toTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ2toFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAxaZ2toFNaNbNfAxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAyaZ2toFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAyhZ2toFNaNfAyhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTPxaZ2toFNaNbPxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTPxhZ2toFNaNfPxhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ30__T2toTS3std11concurrency3TidZ2toFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv11__T2toTAyaZ34__T2toTE3std5regex8internal2ir2IRZ2toFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv11__T2toTAyaZ34__T2toTE3std6socket12SocketOptionZ2toFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv11__T2toTAyaZ41__T2toTPS3std11parallelism12AbstractTaskZ2toFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv11__T2toTAyaZ42__T2toTC3std11concurrency14LinkTerminatedZ2toFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv11__T2toTAyaZ43__T2toTC3std11concurrency15OwnerTerminatedZ2toFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTaZ2toFNaNfaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTbZ2toFNaNbNiNfbZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toThZ2toFNaNbNfhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTiZ2toFNaNbNfiZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTkZ2toFNaNbNfkZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTtZ2toFNaNbNftZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTwZ2toFNaNfwZAya@Base 6
+ _D3std4conv121__T5toStrTAyaTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5toStrFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv121__T7emplaceTC3std12experimental6logger10filelogger10FileLoggerTS3std5stdio4FileTE3std12experimental6logger4core8LogLevelZ7emplaceFAvKS3std5stdio4FileE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std4conv122__T6toImplTAyaTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ6toImplFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv12__ModuleInfoZ@Base 6
+ _D3std4conv13ConvException6__ctorMFNaNbNfAyaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv13ConvException6__initZ@Base 6
+ _D3std4conv13ConvException6__vtblZ@Base 6
+ _D3std4conv13ConvException7__ClassZ@Base 6
+ _D3std4conv13__T4textTAyaZ4textFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv15__T4textTAyaTaZ4textFNaNfAyaaZAya@Base 6
+ _D3std4conv15__T6toImplTiThZ6toImplFNaNbNiNfhZi@Base 6
+ _D3std4conv15__T6toImplTiTiZ6toImplFNaNbNiNfiZi@Base 6
+ _D3std4conv15__T6toImplTiTkZ6toImplFNaNfkZi@Base 6
+ _D3std4conv15__T6toImplTiTlZ6toImplFNaNflZi@Base 6
+ _D3std4conv15__T6toImplTiTlZ6toImplFlZ16__T9__lambda2TlZ9__lambda2FNaNbNiNeKlZi@Base 6
+ _D3std4conv15__T6toImplTiTsZ6toImplFNaNbNiNfsZi@Base 6
+ _D3std4conv15__T6toImplTiTtZ6toImplFNaNbNiNftZi@Base 6
+ _D3std4conv15__T6toImplTkTkZ6toImplFNaNbNiNfkZk@Base 6
+ _D3std4conv15__T6toImplTkTlZ6toImplFNaNflZk@Base 6
+ _D3std4conv15__T6toImplTkTlZ6toImplFlZ16__T9__lambda2TlZ9__lambda2FNaNbNiNeKlZk@Base 6
+ _D3std4conv15__T6toImplTkTmZ6toImplFNaNfmZk@Base 6
+ _D3std4conv15__T6toImplTkTmZ6toImplFmZ16__T9__lambda2TmZ9__lambda2FNaNbNiNeKmZk@Base 6
+ _D3std4conv15__T6toImplTlTmZ6toImplFNaNfmZl@Base 6
+ _D3std4conv15__T6toImplTmTkZ6toImplFNaNbNiNfkZm@Base 6
+ _D3std4conv15__T8unsignedThZ8unsignedFNaNbNiNfhZh@Base 6
+ _D3std4conv15__T8unsignedTiZ8unsignedFNaNbNiNfiZk@Base 6
+ _D3std4conv15__T8unsignedTkZ8unsignedFNaNbNiNfkZk@Base 6
+ _D3std4conv15__T8unsignedTtZ8unsignedFNaNbNiNftZt@Base 6
+ _D3std4conv16__T4textTAyaTxaZ4textFNaNfAyaxaZAya@Base 6
+ _D3std4conv16__T5parseThTAxaZ5parseFNaNfKAxaZh@Base 6
+ _D3std4conv16__T5parseThTAxaZ5parseFNaNfKAxakZh@Base 6
+ _D3std4conv16__T5parseTiTAxaZ5parseFNaNfKAxaZi@Base 6
+ _D3std4conv16__T5parseTkTAxaZ5parseFNaNfKAxaZk@Base 6
+ _D3std4conv16__T5parseTtTAxaZ5parseFNaNfKAxaZt@Base 6
+ _D3std4conv16__T5toStrTAyaTaZ5toStrFNaNfaZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTbZ5toStrFNaNbNiNfbZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTwZ5toStrFNaNfwZAya@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFNaNfxkZh@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFxkZ17__T9__lambda2TxkZ9__lambda2FNaNbNiNeKxkZh@Base 6
+ _D3std4conv16__T6toImplTiTxhZ6toImplFNaNbNiNfxhZi@Base 6
+ _D3std4conv16__T6toImplTiTxkZ6toImplFNaNfxkZi@Base 6
+ _D3std4conv16__T6toImplTiTxsZ6toImplFNaNbNiNfxsZi@Base 6
+ _D3std4conv16__T6toImplTiTykZ6toImplFNaNfykZi@Base 6
+ _D3std4conv16__T8unsignedTxkZ8unsignedFNaNbNiNfxkZk@Base 6
+ _D3std4conv16__T8unsignedTxlZ8unsignedFNaNbNiNfxlZm@Base 6
+ _D3std4conv16__T8unsignedTxmZ8unsignedFNaNbNiNfxmZm@Base 6
+ _D3std4conv16__T8unsignedTyhZ8unsignedFNaNbNiNfyhZh@Base 6
+ _D3std4conv16testEmplaceChunkFNaNbNiAvkkAyaZv@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ69__T11emplaceImplTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv17__T4textTAyaTAxaZ4textFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv17__T4textTAyaTAyaZ4textFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTPvZ5toStrFNaNfPvZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxaZ5toStrFNaNfxaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxdZ5toStrFNfxdZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTaZ6toImplFNaNfaZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTbZ6toImplFNaNbNiNfbZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNehkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNfhZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNeikE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNfiZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNekkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNfkZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNetkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNftZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTwZ6toImplFNaNfwZAya@Base 6
+ _D3std4conv17__T6toImplTtTAxaZ6toImplFNaNfAxaZt@Base 6
+ _D3std4conv181__T18emplaceInitializerTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ18emplaceInitializerFNaNbNcNiNeKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv18__T5toStrTAyaTAyhZ5toStrFNaNfAyhZAya@Base 6
+ _D3std4conv18__T5toStrTAyaTPxhZ5toStrFNaNfPxhZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTAaZ6toImplFNaNbNfAaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPaZ6toImplFNaNbPaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPvZ6toImplFNaNfPvZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxaZ6toImplFNaNfxaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxdZ6toImplFNfxdZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNexlkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNfxlZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNexmkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNfxmZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNeyhkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNfyhZAya@Base 6
+ _D3std4conv19__T11emplaceImplTaZ19__T11emplaceImplTaZ11emplaceImplFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv19__T11emplaceImplThZ19__T11emplaceImplThZ11emplaceImplFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv19__T11emplaceImplTwZ19__T11emplaceImplTwZ11emplaceImplFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv19__T4textTAyaTAyaTkZ4textFNaNbNfAyaAyakZAya@Base 6
+ _D3std4conv19__T4textTAyaTkTAyaZ4textFNaNbNfAyakAyaZAya@Base 6
+ _D3std4conv19__T4textTAyaTwTAyaZ4textFNaNfAyawAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAxaZ6toImplFNaNbNfAxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyaZ6toImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyhZ6toImplFNaNfAyhZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxaZ6toImplFNaNbPxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxhZ6toImplFNaNfPxhZAya@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaaZa@Base 6
+ _D3std4conv20__T10emplaceRefThThZ10emplaceRefFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv20__T10emplaceRefTwTwZ10emplaceRefFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv20__T11emplaceImplTxaZ20__T11emplaceImplTxaZ11emplaceImplFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv20__T4textTAyaTxaTAyaZ4textFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv20__T9convErrorTAxaThZ9convErrorFNaNfAxaiAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTiZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTkZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTtZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20isOctalLiteralStringFAyaZb@Base 6
+ _D3std4conv20strippedOctalLiteralFAyaZAya@Base 6
+ _D3std4conv21ConvOverflowException6__ctorMFNaNbNfAyaAyakZC3std4conv21ConvOverflowException@Base 6
+ _D3std4conv21ConvOverflowException6__initZ@Base 6
+ _D3std4conv21ConvOverflowException6__vtblZ@Base 6
+ _D3std4conv21ConvOverflowException7__ClassZ@Base 6
+ _D3std4conv21__T11emplaceImplTAxaZ21__T11emplaceImplTAxaZ11emplaceImplFNaNbNcNiNfKAxaKAxaZAxa@Base 6
+ _D3std4conv21__T11emplaceImplTAyaZ21__T11emplaceImplTAyaZ11emplaceImplFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv21__T4textTAxaTAyaTAxaZ4textFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAxaTAyaZ4textFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAyaTAyaZ4textFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTkTAyaTkZ4textFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv21__T4textTPxhTAyaTPxhZ4textFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv21__T8textImplTAyaTAyaZ8textImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv221__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv23__T8textImplTAyaTAyaTaZ8textImplFNaNfAyaaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTAyaTAyaZ10emplaceRefFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTxaTaTxaZ10emplaceRefFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv24__T8textImplTAyaTAyaTxaZ8textImplFNaNfAyaxaZAya@Base 6
+ _D3std4conv25__T4textTAyaTkTAyaTkTAyaZ4textFNaNbNfAyakAyakAyaZAya@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363630Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363636Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_373737Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAxaZ8textImplFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv27__T4textTAyaTAyaTAyaTiTAyaZ4textFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTAyaTkZ8textImplFNaNbNfAyaAyakZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTkTAyaZ8textImplFNaNbNfAyakAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTwTAyaZ8textImplFNaNfAyawAyaZAya@Base 6
+ _D3std4conv28__T8textImplTAyaTAyaTxaTAyaZ8textImplFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTAyaTAxaTAyaZ4textFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTiTAyaTiTAyaZ4textFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAxaTAyaTAxaZ8textImplFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTkTAyaTkZ8textImplFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTPxhTAyaTPxhZ8textImplFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv30__T20convError_unexpectedTAxaZ20convError_unexpectedFNaNfAxaZAya@Base 6
+ _D3std4conv326__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv33__T8textImplTAyaTAyaTkTAyaTkTAyaZ8textImplFNaNbNfAyakAyakAyaZAya@Base 6
+ _D3std4conv34__T6toImplTiTE3std8datetime5MonthZ6toImplFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T6toImplTiTxE3std8datetime5MonthZ6toImplFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T8textImplTAyaTAyaTAyaTAyaTiTAyaZ8textImplFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv36__T4textTE3std5regex8internal2ir2IRZ4textFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv36__T7emplaceTS3std3net4curl3FTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl3FTP4ImplZPS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv37__T11emplaceImplTS3std4file8DirEntryZ37__T11emplaceImplTS3std4file8DirEntryZ11emplaceImplFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv37__T5toStrTAyaTS3std11concurrency3TidZ5toStrFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4HTTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4HTTP4ImplZPS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4SMTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4SMTP4ImplZPS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTiTAyaTiTAyaZ8textImplFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv38__T6toImplTAyaTS3std11concurrency3TidZ6toImplFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv40__T7emplaceTS3std4file15DirIteratorImplZ7emplaceFNaNbNiNfPS3std4file15DirIteratorImplZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv41__T11emplaceImplTS3std3net4curl3FTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std5regex8internal2ir2IRZ5toStrFNaNfE3std5regex8internal2ir2IRZyAa@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std6socket12SocketOptionZ5toStrFNaNfE3std6socket12SocketOptionZyAa@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4HTTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4SMTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std5regex8internal2ir2IRZ6toImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std6socket12SocketOptionZ6toImplFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv43__T11emplaceImplTS3std6socket11AddressInfoZ43__T11emplaceImplTS3std6socket11AddressInfoZ11emplaceImplFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv44__T8textImplTAyaTE3std5regex8internal2ir2IRZ8textImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ43__T11emplaceImplTAyaTE3std4file8SpanModeTbZ11emplaceImplFNcKS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv46__T11emplaceImplTS3std3uni17CodepointIntervalZ46__T11emplaceImplTS3std3uni17CodepointIntervalZ11emplaceImplFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl3FTP4ImplZ4inityS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T5toStrTAyaTPS3std11parallelism12AbstractTaskZ5toStrFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv48__T6toImplTiTE3std3net7isemail15EmailStatusCodeZ6toImplFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4HTTP4ImplZ4inityS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4SMTP4ImplZ4inityS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T5toStrTAyaTC3std11concurrency14LinkTerminatedZ5toStrFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv49__T6toImplTAyaTPS3std11parallelism12AbstractTaskZ6toImplFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv50__T5toStrTAyaTC3std11concurrency15OwnerTerminatedZ5toStrFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv50__T6toImplTAyaTC3std11concurrency14LinkTerminatedZ6toImplFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv51__T6toImplTAyaTC3std11concurrency15OwnerTerminatedZ6toImplFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNeKS3std4file15DirIteratorImplZ4inityS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNiNeKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv56__T10emplaceRefTS3std4file8DirEntryTS3std4file8DirEntryZ10emplaceRefFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir12__T5RegexTaZ5RegexKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std4conv65__T6toImplTiTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6toImplFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv66__T7emplaceTS3std4file15DirIteratorImplTAyaTE3std4file8SpanModeTbZ7emplaceFPS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv68__T10emplaceRefTS3std6socket11AddressInfoTS3std6socket11AddressInfoZ10emplaceRefFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni1Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni2Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni3Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni4Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni5Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni6Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni7Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni8Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni9Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni10Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni13Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni16Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni17Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni18Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni19Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni20Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni21Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni26Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni30Z7enumRepyAa@Base 6
+ _D3std4conv74__T10emplaceRefTS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ10emplaceRefFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi128Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi129Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi130Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi132Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi133Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi134Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi136Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi137Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi138Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi140Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi141Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi142Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi144Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi145Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi146Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi148Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi149Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi150Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi152Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi153Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi154Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi156Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi157Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi158Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi160Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi161Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi162Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi164Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi168Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi172Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi176Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi180Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi184Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi188Z7enumRepyAa@Base 6
+ _D3std4conv79__T4textTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ4textFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv82__T10emplaceRefTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv87__T8textImplTAyaTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ8textImplFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv88__T10emplaceRefTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv92__T10emplaceRefTS3std4file15DirIteratorImpl9DirHandleTS3std4file15DirIteratorImpl9DirHandleZ10emplaceRefFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv96__T4textTAyaTPvTAyaTiTAyaTiTAyaTaTAyaThTAyaThTAyaTbTAyaTbTAyaTbTAyaTbTAyaTbTAyaTAxaTAyaTAxaTAyaZ4textFNaNfAyaPvAyaiAyaiAyaaAyahAyahAyabAyabAyabAyabAyabAyaAxaAyaAxaAyaZAya@Base 6
+ _D3std4conv9__T2toThZ10__T2toTxkZ2toFNaNfxkZh@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxhZ2toFNaNbNiNfxhZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxkZ2toFNaNfxkZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxsZ2toFNaNbNiNfxsZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTykZ2toFNaNfykZi@Base 6
+ _D3std4conv9__T2toTiZ28__T2toTE3std8datetime5MonthZ2toFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ29__T2toTxE3std8datetime5MonthZ2toFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ42__T2toTE3std3net7isemail15EmailStatusCodeZ2toFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv9__T2toTiZ59__T2toTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ2toFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toThZ2toFNaNbNiNfhZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTiZ2toFNaNbNiNfiZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTkZ2toFNaNfkZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTlZ2toFNaNflZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTsZ2toFNaNbNiNfsZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTtZ2toFNaNbNiNftZi@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTkZ2toFNaNbNiNfkZk@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTlZ2toFNaNflZk@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTmZ2toFNaNfmZk@Base 6
+ _D3std4conv9__T2toTlZ9__T2toTmZ2toFNaNfmZl@Base 6
+ _D3std4conv9__T2toTmZ9__T2toTkZ2toFNaNbNiNfkZm@Base 6
+ _D3std4conv9__T2toTtZ11__T2toTAxaZ2toFNaNfAxaZt@Base 6
+ _D3std4file10attrIsFileFNaNbNiNfkZb@Base 6
+ _D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZb@Base 6
+ _D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std4file10dirEntriesFAyaE3std4file8SpanModebZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator11__fieldDtorMFZv@Base 6
+ _D3std4file11DirIterator11__xopEqualsFKxS3std4file11DirIteratorKxS3std4file11DirIteratorZb@Base 6
+ _D3std4file11DirIterator15__fieldPostblitMFNbZv@Base 6
+ _D3std4file11DirIterator5emptyMFNdZb@Base 6
+ _D3std4file11DirIterator5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std4file11DirIterator6__ctorMFNcAyaE3std4file8SpanModebZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator6__initZ@Base 6
+ _D3std4file11DirIterator8opAssignMFNcNjS3std4file11DirIteratorZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator8popFrontMFZv@Base 6
+ _D3std4file11DirIterator9__xtoHashFNbNeKxS3std4file11DirIteratorZk@Base 6
+ _D3std4file11thisExePathFNeZAya@Base 6
+ _D3std4file12__ModuleInfoZ@Base 6
+ _D3std4file12mkdirRecurseFxAaZv@Base 6
+ _D3std4file12rmdirRecurseFKS3std4file8DirEntryZv@Base 6
+ _D3std4file12rmdirRecurseFS3std4file8DirEntryZv@Base 6
+ _D3std4file12rmdirRecurseFxAaZv@Base 6
+ _D3std4file13FileException6__ctorMFNaNfxAaxAaAyakZC3std4file13FileException@Base 6
+ _D3std4file13FileException6__ctorMFNexAakAyakZC3std4file13FileException@Base 6
+ _D3std4file13FileException6__initZ@Base 6
+ _D3std4file13FileException6__vtblZ@Base 6
+ _D3std4file13FileException7__ClassZ@Base 6
+ _D3std4file13attrIsSymlinkFNaNbNiNfkZb@Base 6
+ _D3std4file13getAttributesFNfxAaZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file13getAttributesFNfxAaZk@Base 6
+ _D3std4file13setAttributesFNfxAakZ12trustedChmodFNbNiNexAakZi@Base 6
+ _D3std4file13setAttributesFNfxAakZv@Base 6
+ _D3std4file15DirIteratorImpl11__xopEqualsFKxS3std4file15DirIteratorImplKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std4file15DirIteratorImpl11popDirStackMFZv@Base 6
+ _D3std4file15DirIteratorImpl15releaseDirStackMFZv@Base 6
+ _D3std4file15DirIteratorImpl4nextMFZb@Base 6
+ _D3std4file15DirIteratorImpl5emptyMFNdZb@Base 6
+ _D3std4file15DirIteratorImpl5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std4file15DirIteratorImpl6__ctorMFNcAyaE3std4file8SpanModebZS3std4file15DirIteratorImpl@Base 6
+ _D3std4file15DirIteratorImpl6__dtorMFZv@Base 6
+ _D3std4file15DirIteratorImpl6__initZ@Base 6
+ _D3std4file15DirIteratorImpl6stepInMFAyaZb@Base 6
+ _D3std4file15DirIteratorImpl8hasExtraMFZb@Base 6
+ _D3std4file15DirIteratorImpl8opAssignMFNcNjS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4file15DirIteratorImpl8popExtraMFZS3std4file8DirEntry@Base 6
+ _D3std4file15DirIteratorImpl8popFrontMFZv@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle11__xopEqualsFKxS3std4file15DirIteratorImpl9DirHandleKxS3std4file15DirIteratorImpl9DirHandleZb@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle9__xtoHashFNbNeKxS3std4file15DirIteratorImpl9DirHandleZk@Base 6
+ _D3std4file15DirIteratorImpl9__xtoHashFNbNeKxS3std4file15DirIteratorImplZk@Base 6
+ _D3std4file15DirIteratorImpl9mayStepInMFZb@Base 6
+ _D3std4file15DirIteratorImpl9pushExtraMFS3std4file8DirEntryZv@Base 6
+ _D3std4file15__T8cenforceTbZ8cenforceFNfbLAxaAyakZb@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZ15trustedReadlinkFNbNiNeAxaAaZi@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZ19trustedAssumeUniqueFNaNbNiNeKAaZAya@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZAya@Base 6
+ _D3std4file15ensureDirExistsFxAaZb@Base 6
+ _D3std4file16__T8cenforceTPaZ8cenforceFNfPaLAxaAyakZPa@Base 6
+ _D3std4file16timeLastModifiedFNfxAaS3std8datetime7SysTimeZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file16timeLastModifiedFNfxAaS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std4file16timeLastModifiedFNfxAaZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file16timeLastModifiedFNfxAaZS3std8datetime7SysTime@Base 6
+ _D3std4file17getLinkAttributesFNfxAaZ12trustedLstatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file17getLinkAttributesFNfxAaZk@Base 6
+ _D3std4file42__T8cenforceTPS4core3sys5posix6dirent3DIRZ8cenforceFNfPS4core3sys5posix6dirent3DIRLAxaAyakZPS4core3sys5posix6dirent3DIR@Base 6
+ _D3std4file4copyFxAaxAaE3std8typecons53__T4FlagVAyaa18_707265736572766541747472696275746573Z4FlagZv@Base 6
+ _D3std4file4readFNexAakZAv@Base 6
+ _D3std4file5chdirFNfxAaZ12trustedChdirFNbNiNexAaZi@Base 6
+ _D3std4file5chdirFNfxAaZv@Base 6
+ _D3std4file5isDirFNdNfxAaZb@Base 6
+ _D3std4file5mkdirFNfxAaZ12trustedMkdirFNbNiNexAakZi@Base 6
+ _D3std4file5mkdirFNfxAaZv@Base 6
+ _D3std4file5rmdirFxAaZv@Base 6
+ _D3std4file5writeFNexAaxAvZv@Base 6
+ _D3std4file6appendFNexAaxAvZv@Base 6
+ _D3std4file6existsFNbNiNexAaZb@Base 6
+ _D3std4file6getcwdFZAya@Base 6
+ _D3std4file6isFileFNdNfxAaZb@Base 6
+ _D3std4file6removeFNexAaZv@Base 6
+ _D3std4file6renameFNexAaxAaZv@Base 6
+ _D3std4file7getSizeFNfxAaZ11trustedStatFNbNiNexAaPS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file7getSizeFNfxAaZ18ptrOfLocalVariableFNeNkKS4core3sys5posix3sys4stat6stat_tZPS4core3sys5posix3sys4stat6stat_t@Base 6
+ _D3std4file7getSizeFNfxAaZm@Base 6
+ _D3std4file7tempDirFNeZ45__T15findExistingDirTAyaTAyaTAyaTAyaTAyaTAyaZ15findExistingDirFNfLAyaLAyaLAyaLAyaLAyaLAyaZAya@Base 6
+ _D3std4file7tempDirFNeZ5cacheAya@Base 6
+ _D3std4file7tempDirFNeZAya@Base 6
+ _D3std4file8DirEntry10attributesMFNdZk@Base 6
+ _D3std4file8DirEntry11__xopEqualsFKxS3std4file8DirEntryKxS3std4file8DirEntryZb@Base 6
+ _D3std4file8DirEntry14linkAttributesMFNdZk@Base 6
+ _D3std4file8DirEntry15_ensureStatDoneMFNfZ11trustedStatFNbNiNexAaPS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file8DirEntry15_ensureStatDoneMFNfZv@Base 6
+ _D3std4file8DirEntry16_ensureLStatDoneMFZv@Base 6
+ _D3std4file8DirEntry16timeLastAccessedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry16timeLastModifiedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry17timeStatusChangedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry22_ensureStatOrLStatDoneMFZv@Base 6
+ _D3std4file8DirEntry4nameMxFNaNbNdZAya@Base 6
+ _D3std4file8DirEntry4sizeMFNdZm@Base 6
+ _D3std4file8DirEntry5isDirMFNdZb@Base 6
+ _D3std4file8DirEntry6__ctorMFNcAyaPS4core3sys5posix6dirent6direntZS3std4file8DirEntry@Base 6
+ _D3std4file8DirEntry6__ctorMFNcAyaZS3std4file8DirEntry@Base 6
+ _D3std4file8DirEntry6__initZ@Base 6
+ _D3std4file8DirEntry6isFileMFNdZb@Base 6
+ _D3std4file8DirEntry7statBufMFNdZS4core3sys5posix3sys4stat6stat_t@Base 6
+ _D3std4file8DirEntry9__xtoHashFNbNeKxS3std4file8DirEntryZk@Base 6
+ _D3std4file8DirEntry9isSymlinkMFNdZb@Base 6
+ _D3std4file8deletemeFNdNfZ6_firstb@Base 6
+ _D3std4file8deletemeFNdNfZ9_deletemeAya@Base 6
+ _D3std4file8deletemeFNdNfZAya@Base 6
+ _D3std4file8dirEntryFxAaZS3std4file8DirEntry@Base 6
+ _D3std4file8getTimesFNfxAaJS3std8datetime7SysTimeJS3std8datetime7SysTimeZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file8getTimesFNfxAaJS3std8datetime7SysTimeJS3std8datetime7SysTimeZv@Base 6
+ _D3std4file8setTimesFNfxAaS3std8datetime7SysTimeS3std8datetime7SysTimeZ13trustedUtimesFNbNiNexAaKxG2S4core3sys5posix3sys4time7timevalZi@Base 6
+ _D3std4file8setTimesFNfxAaS3std8datetime7SysTimeS3std8datetime7SysTimeZv@Base 6
+ _D3std4file9attrIsDirFNaNbNiNfkZb@Base 6
+ _D3std4file9isSymlinkFNdNfxAaZb@Base 6
+ _D3std4file9writeImplFNexAaxAvxkZv@Base 6
+ _D3std4json12__ModuleInfoZ@Base 6
+ _D3std4json13JSONException6__ctorMFNaNbNfAyaAyakZC3std4json13JSONException@Base 6
+ _D3std4json13JSONException6__ctorMFNaNbNfAyaiiZC3std4json13JSONException@Base 6
+ _D3std4json13JSONException6__initZ@Base 6
+ _D3std4json13JSONException6__vtblZ@Base 6
+ _D3std4json13JSONException7__ClassZ@Base 6
+ _D3std4json14appendJSONCharFPS3std5array17__T8AppenderTAyaZ8AppenderwMDFAyaZvZv@Base 6
+ _D3std4json16JSONFloatLiteral6__initZ@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ13putCharAndEOLMFaZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ6putEOLMFZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ7putTabsMFmZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ8toStringMFAyaZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue13__T6assignTdZ6assignMFNaNbNiNfdZv@Base 6
+ _D3std4json9JSONValue13__T6assignTlZ6assignMFNaNbNiNflZv@Base 6
+ _D3std4json9JSONValue13__T6assignTmZ6assignMFNaNbNiNfmZv@Base 6
+ _D3std4json9JSONValue14toPrettyStringMxFxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue15__T6assignTAyaZ6assignMFNaNbNiNfAyaZv@Base 6
+ _D3std4json9JSONValue33__T6assignTAS3std4json9JSONValueZ6assignMFNaNbNiNfAS3std4json9JSONValueZv@Base 6
+ _D3std4json9JSONValue36__T6assignTHAyaS3std4json9JSONValueZ6assignMFNaNbNiNfHAyaS3std4json9JSONValueZv@Base 6
+ _D3std4json9JSONValue3strMFNaNbNdNiAyaZAya@Base 6
+ _D3std4json9JSONValue3strMNgFNaNdZNgAya@Base 6
+ _D3std4json9JSONValue4typeMFNdE3std4json9JSON_TYPEZE3std4json9JSON_TYPE@Base 6
+ _D3std4json9JSONValue4typeMxFNaNbNdNiNfZE3std4json9JSON_TYPE@Base 6
+ _D3std4json9JSONValue5Store6__initZ@Base 6
+ _D3std4json9JSONValue5arrayMFNaNbNdNiAS3std4json9JSONValueZAS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue5arrayMNgFNaNcNdZNgAS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue6__initZ@Base 6
+ _D3std4json9JSONValue6isNullMxFNaNbNdNiNfZb@Base 6
+ _D3std4json9JSONValue6objectMFNaNbNdNiHAyaS3std4json9JSONValueZHAyaS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue6objectMNgFNaNcNdZNgHAyaS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue7integerMFNaNbNdNiNflZl@Base 6
+ _D3std4json9JSONValue7integerMNgFNaNdNfZNgl@Base 6
+ _D3std4json9JSONValue7opApplyMFDFAyaKS3std4json9JSONValueZiZi@Base 6
+ _D3std4json9JSONValue7opApplyMFDFkKS3std4json9JSONValueZiZi@Base 6
+ _D3std4json9JSONValue7opIndexMNgFNaNcAyaZNgS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue7opIndexMNgFNaNckZNgS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue8floatingMFNaNbNdNiNfdZd@Base 6
+ _D3std4json9JSONValue8floatingMNgFNaNdNfZNgd@Base 6
+ _D3std4json9JSONValue8opEqualsMxFNaNbNiKxS3std4json9JSONValueZb@Base 6
+ _D3std4json9JSONValue8opEqualsMxFNaNbNixS3std4json9JSONValueZb@Base 6
+ _D3std4json9JSONValue8toStringMxFxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue8uintegerMFNaNbNdNiNfmZm@Base 6
+ _D3std4json9JSONValue8uintegerMNgFNaNdNfZNgm@Base 6
+ _D3std4math10__T3absTeZ3absFNaNbNiNfeZe@Base 6
+ _D3std4math11isIdenticalFNaNbNiNeeeZb@Base 6
+ _D3std4math12__ModuleInfoZ@Base 6
+ _D3std4math12__T3powTeTeZ3powFNaNbNiNeeeZ4implFNaNbNiNfeeZe@Base 6
+ _D3std4math12__T3powTeTeZ3powFNaNbNiNeeeZe@Base 6
+ _D3std4math12__T3powTeTlZ3powFNaNbNiNeelZe@Base 6
+ _D3std4math12__T3powTiTiZ3powFNaNbNiNeiiZi@Base 6
+ _D3std4math12__T5frexpTeZ5frexpFNaNbNiNexeJiZe@Base 6
+ _D3std4math12__T5isNaNTdZ5isNaNFNaNbNiNedZb@Base 6
+ _D3std4math12__T5isNaNTeZ5isNaNFNaNbNiNeeZb@Base 6
+ _D3std4math12__T5isNaNTfZ5isNaNFNaNbNiNefZb@Base 6
+ _D3std4math13__T4polyTeTeZ4polyFNaNbNiNeexAeZe@Base 6
+ _D3std4math13__T5isNaNTxdZ5isNaNFNaNbNiNexdZb@Base 6
+ _D3std4math13__T5isNaNTxeZ5isNaNFNaNbNiNexeZb@Base 6
+ _D3std4math13getNaNPayloadFNaNbNiNeeZm@Base 6
+ _D3std4math14__T4polyTyeTeZ4polyFNaNbNiNeyexAeZe@Base 6
+ _D3std4math14__T7signbitTeZ7signbitFNaNbNiNeeZi@Base 6
+ _D3std4math14resetIeeeFlagsFZv@Base 6
+ _D3std4math15__T7signbitTxeZ7signbitFNaNbNiNexeZi@Base 6
+ _D3std4math15__T7signbitTyeZ7signbitFNaNbNiNeyeZi@Base 6
+ _D3std4math15__T8ieeeMeanTeZ8ieeeMeanFNaNbNiNexexeZe@Base 6
+ _D3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZd@Base 6
+ _D3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZe@Base 6
+ _D3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZf@Base 6
+ _D3std4math17__T8copysignTdTeZ8copysignFNaNbNiNedeZd@Base 6
+ _D3std4math17__T8copysignTeTeZ8copysignFNaNbNiNeeeZe@Base 6
+ _D3std4math17__T8copysignTeTiZ8copysignFNaNbNiNeieZe@Base 6
+ _D3std4math18__T10isInfinityTdZ10isInfinityFNaNbNiNedZb@Base 6
+ _D3std4math18__T10isInfinityTeZ10isInfinityFNaNbNiNeeZb@Base 6
+ _D3std4math18__T10isInfinityTfZ10isInfinityFNaNbNiNefZb@Base 6
+ _D3std4math19__T10isInfinityTxdZ10isInfinityFNaNbNiNexdZb@Base 6
+ _D3std4math20FloatingPointControl10initializeMFNiZv@Base 6
+ _D3std4math20FloatingPointControl15clearExceptionsFNiZv@Base 6
+ _D3std4math20FloatingPointControl15getControlStateFNbNiNeZt@Base 6
+ _D3std4math20FloatingPointControl15setControlStateFNbNiNetZv@Base 6
+ _D3std4math20FloatingPointControl16enableExceptionsMFNikZv@Base 6
+ _D3std4math20FloatingPointControl17disableExceptionsMFNikZv@Base 6
+ _D3std4math20FloatingPointControl17enabledExceptionsFNdNiZk@Base 6
+ _D3std4math20FloatingPointControl17hasExceptionTrapsFNbNdNiNfZb@Base 6
+ _D3std4math20FloatingPointControl6__dtorMFNiZv@Base 6
+ _D3std4math20FloatingPointControl6__initZ@Base 6
+ _D3std4math20FloatingPointControl8opAssignMFNcNiNjS3std4math20FloatingPointControlZS3std4math20FloatingPointControl@Base 6
+ _D3std4math20FloatingPointControl8roundingFNdNiZk@Base 6
+ _D3std4math20FloatingPointControl8roundingMFNdNikZv@Base 6
+ _D3std4math22__T12polyImplBaseTeTeZ12polyImplBaseFNaNbNiNeexAeZe@Base 6
+ _D3std4math3NaNFNaNbNiNemZe@Base 6
+ _D3std4math3cosFNaNbNiNfcZc@Base 6
+ _D3std4math3cosFNaNbNiNfdZd@Base 6
+ _D3std4math3cosFNaNbNiNffZf@Base 6
+ _D3std4math3cosFNaNbNiNfjZe@Base 6
+ _D3std4math3expFNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math3expFNaNbNiNeeZ1QyG4e@Base 6
+ _D3std4math3expFNaNbNiNeeZe@Base 6
+ _D3std4math3expFNaNbNiNfdZd@Base 6
+ _D3std4math3expFNaNbNiNffZf@Base 6
+ _D3std4math3fmaFNaNbNiNfeeeZe@Base 6
+ _D3std4math3logFNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math3logFNaNbNiNfeZe@Base 6
+ _D3std4math3sinFNaNbNiNfcZc@Base 6
+ _D3std4math3sinFNaNbNiNfdZd@Base 6
+ _D3std4math3sinFNaNbNiNffZf@Base 6
+ _D3std4math3sinFNaNbNiNfjZj@Base 6
+ _D3std4math3tanFNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math3tanFNaNbNiNeeZ1QyG5e@Base 6
+ _D3std4math3tanFNaNbNiNeeZe@Base 6
+ _D3std4math4acosFNaNbNiNfdZd@Base 6
+ _D3std4math4acosFNaNbNiNfeZe@Base 6
+ _D3std4math4acosFNaNbNiNffZf@Base 6
+ _D3std4math4asinFNaNbNiNfdZd@Base 6
+ _D3std4math4asinFNaNbNiNfeZe@Base 6
+ _D3std4math4asinFNaNbNiNffZf@Base 6
+ _D3std4math4atanFNaNbNiNfdZd@Base 6
+ _D3std4math4atanFNaNbNiNfeZ1PyG5e@Base 6
+ _D3std4math4atanFNaNbNiNfeZ1QyG6e@Base 6
+ _D3std4math4atanFNaNbNiNfeZe@Base 6
+ _D3std4math4atanFNaNbNiNffZf@Base 6
+ _D3std4math4cbrtFNbNiNeeZe@Base 6
+ _D3std4math4ceilFNaNbNiNedZd@Base 6
+ _D3std4math4ceilFNaNbNiNeeZe@Base 6
+ _D3std4math4ceilFNaNbNiNefZf@Base 6
+ _D3std4math4coshFNaNbNiNfdZd@Base 6
+ _D3std4math4coshFNaNbNiNfeZe@Base 6
+ _D3std4math4coshFNaNbNiNffZf@Base 6
+ _D3std4math4exp2FNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math4exp2FNaNbNiNeeZ1QyG4e@Base 6
+ _D3std4math4exp2FNaNbNiNeeZe@Base 6
+ _D3std4math4expiFNaNbNiNeeZc@Base 6
+ _D3std4math4fabsFNaNbNiNfdZd@Base 6
+ _D3std4math4fabsFNaNbNiNffZf@Base 6
+ _D3std4math4fdimFNaNbNiNfeeZe@Base 6
+ _D3std4math4fmaxFNaNbNiNfeeZe@Base 6
+ _D3std4math4fminFNaNbNiNfeeZe@Base 6
+ _D3std4math4fmodFNbNiNeeeZe@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math4log2FNaNbNiNfeZe@Base 6
+ _D3std4math4logbFNbNiNeeZe@Base 6
+ _D3std4math4modfFNbNiNeeKeZe@Base 6
+ _D3std4math4rintFNaNbNiNfdZd@Base 6
+ _D3std4math4rintFNaNbNiNffZf@Base 6
+ _D3std4math4sinhFNaNbNiNfdZd@Base 6
+ _D3std4math4sinhFNaNbNiNfeZe@Base 6
+ _D3std4math4sinhFNaNbNiNffZf@Base 6
+ _D3std4math4sqrtFNaNbNiNfcZc@Base 6
+ _D3std4math4tanhFNaNbNiNfdZd@Base 6
+ _D3std4math4tanhFNaNbNiNfeZe@Base 6
+ _D3std4math4tanhFNaNbNiNffZf@Base 6
+ _D3std4math5acoshFNaNbNiNfdZd@Base 6
+ _D3std4math5acoshFNaNbNiNfeZe@Base 6
+ _D3std4math5acoshFNaNbNiNffZf@Base 6
+ _D3std4math5asinhFNaNbNiNfdZd@Base 6
+ _D3std4math5asinhFNaNbNiNfeZe@Base 6
+ _D3std4math5asinhFNaNbNiNffZf@Base 6
+ _D3std4math5atan2FNaNbNiNeeeZe@Base 6
+ _D3std4math5atan2FNaNbNiNfddZd@Base 6
+ _D3std4math5atan2FNaNbNiNfffZf@Base 6
+ _D3std4math5atanhFNaNbNiNfdZd@Base 6
+ _D3std4math5atanhFNaNbNiNfeZe@Base 6
+ _D3std4math5atanhFNaNbNiNffZf@Base 6
+ _D3std4math5expm1FNaNbNiNeeZ1PyG5e@Base 6
+ _D3std4math5expm1FNaNbNiNeeZ1QyG6e@Base 6
+ _D3std4math5expm1FNaNbNiNeeZe@Base 6
+ _D3std4math5floorFNaNbNiNedZd@Base 6
+ _D3std4math5floorFNaNbNiNeeZe@Base 6
+ _D3std4math5floorFNaNbNiNefZf@Base 6
+ _D3std4math5hypotFNaNbNiNfeeZe@Base 6
+ _D3std4math5ilogbFNbNiNeeZi@Base 6
+ _D3std4math5ldexpFNaNbNiNfdiZd@Base 6
+ _D3std4math5ldexpFNaNbNiNffiZf@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math5log10FNaNbNiNfeZe@Base 6
+ _D3std4math5log1pFNaNbNiNfeZe@Base 6
+ _D3std4math5lrintFNaNbNiNeeZl@Base 6
+ _D3std4math5roundFNbNiNeeZe@Base 6
+ _D3std4math5truncFNbNiNeeZe@Base 6
+ _D3std4math6lroundFNbNiNeeZl@Base 6
+ _D3std4math6nextUpFNaNbNiNedZd@Base 6
+ _D3std4math6nextUpFNaNbNiNeeZe@Base 6
+ _D3std4math6nextUpFNaNbNiNefZf@Base 6
+ _D3std4math6remquoFNbNiNeeeJiZe@Base 6
+ _D3std4math6rndtolFNaNbNiNfdZl@Base 6
+ _D3std4math6rndtolFNaNbNiNffZl@Base 6
+ _D3std4math6scalbnFNbNiNeeiZe@Base 6
+ _D3std4math8nextDownFNaNbNiNfdZd@Base 6
+ _D3std4math8nextDownFNaNbNiNfeZe@Base 6
+ _D3std4math8nextDownFNaNbNiNffZf@Base 6
+ _D3std4math8polyImplFNaNbNiNeexAeZe@Base 6
+ _D3std4math9IeeeFlags12getIeeeFlagsFZk@Base 6
+ _D3std4math9IeeeFlags14resetIeeeFlagsFZv@Base 6
+ _D3std4math9IeeeFlags6__initZ@Base 6
+ _D3std4math9IeeeFlags7inexactMFNdZb@Base 6
+ _D3std4math9IeeeFlags7invalidMFNdZb@Base 6
+ _D3std4math9IeeeFlags8overflowMFNdZb@Base 6
+ _D3std4math9IeeeFlags9divByZeroMFNdZb@Base 6
+ _D3std4math9IeeeFlags9underflowMFNdZb@Base 6
+ _D3std4math9coshisinhFNaNbNiNfeZc@Base 6
+ _D3std4math9ieeeFlagsFNdZS3std4math9IeeeFlags@Base 6
+ _D3std4math9nearbyintFNbNiNeeZe@Base 6
+ _D3std4math9remainderFNbNiNeeeZe@Base 6
+ _D3std4meta12__ModuleInfoZ@Base 6
+ _D3std4path109__T9globMatchVE3std4path13CaseSensitivei1TaTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ9globMatchFNaNbNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplAxaZb@Base 6
+ _D3std4path11expandTildeFNbAyaZ18expandFromDatabaseFNbAyaZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZ21combineCPathWithDPathFNbPaAyakZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZ21expandFromEnvironmentFNbAyaZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZAya@Base 6
+ _D3std4path12__ModuleInfoZ@Base 6
+ _D3std4path12absolutePathFNaNfAyaLAyaZAya@Base 6
+ _D3std4path14isDirSeparatorFNaNbNiNfwZb@Base 6
+ _D3std4path16__T7dirNameTAxaZ7dirNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path16__T9buildPathTaZ9buildPathFNaNbNfAAxaXAya@Base 6
+ _D3std4path16isDriveSeparatorFNaNbNiNfwZb@Base 6
+ _D3std4path17__T8baseNameTAxaZ8baseNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path17__T8baseNameTAyaZ8baseNameFNaNbNiNfAyaZAya@Base 6
+ _D3std4path17__T8isRootedTAxaZ8isRootedFNaNbNiNfAxaZb@Base 6
+ _D3std4path17__T8isRootedTAyaZ8isRootedFNaNbNiNfAyaZb@Base 6
+ _D3std4path17__T8rootNameTAxaZ8rootNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path18__T9extensionTAyaZ9extensionFNaNbNiNfAyaZAya@Base 6
+ _D3std4path19__T9buildPathTAAxaZ9buildPathFAAxaZ24__T11trustedCastTAyaTAaZ11trustedCastFNaNbNiNeAaZAya@Base 6
+ _D3std4path19__T9buildPathTAAxaZ9buildPathFNaNbNfAAxaZAya@Base 6
+ _D3std4path20__T10stripDriveTAxaZ10stripDriveFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path20__T10stripDriveTAyaZ10stripDriveFNaNbNiNfAyaZAya@Base 6
+ _D3std4path21__T9chainPathTAaTAxaZ9chainPathFNaNbNiNfAaAxaZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter11__xopEqualsFKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterZb@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter4backMFNaNbNdNiNfZAxa@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter4saveMFNaNbNdNiNfZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5frontMFNaNbNdNiNfZAxa@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5ltrimMFNaNbNiNfkkZk@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5rtrimMFNaNbNiNfkkZk@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__ctorMFNaNbNcNiNfAxaZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter7popBackMFNaNbNiNfZv@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter9__xtoHashFNbNeKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterZk@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFNaNbNiNfAxaZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T9chainPathTAxaTAxaZ9chainPathFNaNbNiNfAxaAxaZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path22__T9chainPathTAyaTAyaZ9chainPathFNaNbNiNfAyaAyaZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path23__T13lastSeparatorTAxaZ13lastSeparatorFNaNbNiNfAxaZi@Base 6
+ _D3std4path23__T13lastSeparatorTAyaZ13lastSeparatorFNaNbNiNfAyaZi@Base 6
+ _D3std4path25__T15extSeparatorPosTAyaZ15extSeparatorPosFNaNbNiNfxAyaZi@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result11__xopEqualsFKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result11getElement0MFNaNbNiNfZa@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result4saveMFNaNbNdNiNfZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5frontMFNaNbNdNiNfZa@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5isDotFNaNbNiNfAxaZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__ctorMFNaNbNcNiNfAxaZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__initZ@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result8isDotDotFNaNbNiNfAxaZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result9__xtoHashFNbNeKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZk@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFNaNbNiNfAxaZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path27__T19buildNormalizedPathTaZ19buildNormalizedPathFNaNbNeAxAaXAya@Base 6
+ _D3std4path28__T18rtrimDirSeparatorsTAxaZ18rtrimDirSeparatorsFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path28__T18rtrimDirSeparatorsTAyaZ18rtrimDirSeparatorsFNaNbNiNfAyaZAya@Base 6
+ _D3std4path48__T9globMatchVE3std4path13CaseSensitivei1TaTAyaZ9globMatchFNaNbNfAyaAxaZb@Base 6
+ _D3std4path49__T15filenameCharCmpVE3std4path13CaseSensitivei1Z15filenameCharCmpFNaNbNiNfwwZi@Base 6
+ _D3std4uuid10randomUUIDFNfZS3std4uuid4UUID@Base 6
+ _D3std4uuid12__ModuleInfoZ@Base 6
+ _D3std4uuid164__T10randomUUIDTS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngineZ10randomUUIDFNaNbNfKS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngineZS3std4uuid4UUID@Base 6
+ _D3std4uuid20UUIDParsingException6__ctorMFNaNeAyakE3std4uuid20UUIDParsingException6ReasonAyaC6object9ThrowableAyakZC3std4uuid20UUIDParsingException@Base 6
+ _D3std4uuid20UUIDParsingException6__initZ@Base 6
+ _D3std4uuid20UUIDParsingException6__vtblZ@Base 6
+ _D3std4uuid20UUIDParsingException7__ClassZ@Base 6
+ _D3std4uuid4UUID11uuidVersionMxFNaNbNdNiNfZE3std4uuid4UUID7Version@Base 6
+ _D3std4uuid4UUID13__T6__ctorTaZ6__ctorMFNaNcNfxAaZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID16__T9asArrayOfTkZ9asArrayOfMFNaNbNcNiNjNeZG4k@Base 6
+ _D3std4uuid4UUID4swapMFNaNbNiNfKS3std4uuid4UUIDZv@Base 6
+ _D3std4uuid4UUID5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std4uuid4UUID5opCmpMxFNaNbNiNfKxS3std4uuid4UUIDZi@Base 6
+ _D3std4uuid4UUID5opCmpMxFNaNbNiNfxS3std4uuid4UUIDZi@Base 6
+ _D3std4uuid4UUID6__ctorMFNaNbNcNiNfKxG16hZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID6__ctorMFNaNbNcNiNfxG16hZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID6__initZ@Base 6
+ _D3std4uuid4UUID6toCharMxFNaNbNfkZa@Base 6
+ _D3std4uuid4UUID6toHashMxFNaNbNiNfZk@Base 6
+ _D3std4uuid4UUID7Version6__initZ@Base 6
+ _D3std4uuid4UUID7variantMxFNaNbNdNiNfZE3std4uuid4UUID7Variant@Base 6
+ _D3std4uuid4UUID8opEqualsMxFNaNbNiNfKxS3std4uuid4UUIDZb@Base 6
+ _D3std4uuid4UUID8opEqualsMxFNaNbNiNfxS3std4uuid4UUIDZb@Base 6
+ _D3std4uuid4UUID8toStringMxFMDFAxaZvZv@Base 6
+ _D3std4uuid4UUID8toStringMxFNaNbNfZAya@Base 6
+ _D3std4uuid4UUID9_toStringMxFNaNbNfZG36a@Base 6
+ _D3std4uuid7md5UUIDFNaNbNiNfxAaxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid7md5UUIDFNaNbNiNfxAhxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid8sha1UUIDFNaNbNiNfxAaxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid8sha1UUIDFNaNbNiNfxAhxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4zlib10UnCompress10uncompressMFAxvZAxv@Base 6
+ _D3std4zlib10UnCompress5errorMFiZv@Base 6
+ _D3std4zlib10UnCompress5flushMFZAv@Base 6
+ _D3std4zlib10UnCompress6__ctorMFE3std4zlib12HeaderFormatZC3std4zlib10UnCompress@Base 6
+ _D3std4zlib10UnCompress6__ctorMFkZC3std4zlib10UnCompress@Base 6
+ _D3std4zlib10UnCompress6__dtorMFZv@Base 6
+ _D3std4zlib10UnCompress6__initZ@Base 6
+ _D3std4zlib10UnCompress6__vtblZ@Base 6
+ _D3std4zlib10UnCompress7__ClassZ@Base 6
+ _D3std4zlib10uncompressFAvkiZAv@Base 6
+ _D3std4zlib12__ModuleInfoZ@Base 6
+ _D3std4zlib13ZlibException6__ctorMFiZC3std4zlib13ZlibException@Base 6
+ _D3std4zlib13ZlibException6__initZ@Base 6
+ _D3std4zlib13ZlibException6__vtblZ@Base 6
+ _D3std4zlib13ZlibException7__ClassZ@Base 6
+ _D3std4zlib5crc32FkAxvZk@Base 6
+ _D3std4zlib7adler32FkAxvZk@Base 6
+ _D3std4zlib8Compress5errorMFiZv@Base 6
+ _D3std4zlib8Compress5flushMFiZAv@Base 6
+ _D3std4zlib8Compress6__ctorMFE3std4zlib12HeaderFormatZC3std4zlib8Compress@Base 6
+ _D3std4zlib8Compress6__ctorMFiE3std4zlib12HeaderFormatZC3std4zlib8Compress@Base 6
+ _D3std4zlib8Compress6__dtorMFZv@Base 6
+ _D3std4zlib8Compress6__initZ@Base 6
+ _D3std4zlib8Compress6__vtblZ@Base 6
+ _D3std4zlib8Compress7__ClassZ@Base 6
+ _D3std4zlib8Compress8compressMFAxvZAxv@Base 6
+ _D3std4zlib8compressFAxvZAxv@Base 6
+ _D3std4zlib8compressFAxviZAxv@Base 6
+ _D3std5array102__T5arrayTS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZ5arrayFNaNbNfS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZAAya@Base 6
+ _D3std5array118__T13insertInPlaceTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir8BytecodekS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array12__ModuleInfoZ@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNeANgvANgvZ3maxFNaNbNiNfPNgvPNgvZPNgv@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNeANgvANgvZ3minFNaNbNiNfPNgvPNgvZPNgv@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNiNeANgvANgvZANgv@Base 6
+ _D3std5array154__T5arrayTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZ5arrayFNaNbNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data11__xopEqualsFKxS3std5array16__T8AppenderTAaZ8Appender4DataKxS3std5array16__T8AppenderTAaZ8Appender4DataZb@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data6__initZ@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data9__xtoHashFNbNeKxS3std5array16__T8AppenderTAaZ8Appender4DataZk@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4dataMNgFNaNbNdNiNeZANga@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender6__ctorMFNaNbNcNeAaZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender6__initZ@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender10__T3putThZ3putMFNaNbNfhZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender11__T3putTAhZ3putMFNaNbNfAhZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data11__xopEqualsFKxS3std5array16__T8AppenderTAhZ8Appender4DataKxS3std5array16__T8AppenderTAhZ8Appender4DataZb@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data6__initZ@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data9__xtoHashFNbNeKxS3std5array16__T8AppenderTAhZ8Appender4DataZk@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4dataMNgFNaNbNdNiNeZANgh@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender6__ctorMFNaNbNcNeAhZS3std5array16__T8AppenderTAhZ8Appender@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender6__initZ@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array16__T8appenderTAaZ8appenderFNaNbNfZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array16__T8appenderTAhZ8appenderFNaNbNfZS3std5array16__T8AppenderTAhZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAxaZ8Appender4DataKxS3std5array17__T8AppenderTAxaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAxaZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4dataMNgFNaNbNdNiNeZANgxa@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender6__ctorMFNaNbNcNeAxaZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTxaZ3putMFNaNbNfxaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTxwZ3putMFNaNfxwZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTyaZ3putMFNaNbNfyaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAyaZ8Appender4DataKxS3std5array17__T8AppenderTAyaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAyaZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4dataMNgFNaNbNdNiNeZAya@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcAaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcNeAyaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender11__T3putTAuZ3putMFNaNbNfAuZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAyuZ8Appender4DataKxS3std5array17__T8AppenderTAyuZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAyuZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4dataMNgFNaNbNdNiNeZAyu@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcAuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcNeAyuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender10__T3putTwZ3putMFNaNbNfwZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAywZ8Appender4DataKxS3std5array17__T8AppenderTAywZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAywZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4dataMNgFNaNbNdNiNeZAyw@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcAwZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcNeAywZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTxaZ3putMFNaNbNfxaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTxwZ3putMFNaNfxwZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTyaZ3putMFNaNbNfyaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTyAaZ8Appender4DataKxS3std5array17__T8AppenderTyAaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTyAaZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4dataMNgFNaNbNdNiNeZAya@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcAaZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcNeAyaZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8appenderTAxaZ8appenderFNaNbNfZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array17__T8appenderTAyaZ8appenderFNaNbNfZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8appenderTyAaZ8appenderFNaNbNfZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array18__T5splitTAyaTAyaZ5splitFNaNbNfAyaAyaZAAya@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data11__xopEqualsFKxS3std5array18__T8AppenderTAAyaZ8Appender4DataKxS3std5array18__T8AppenderTAAyaZ8Appender4DataZb@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data6__initZ@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data9__xtoHashFNbNeKxS3std5array18__T8AppenderTAAyaZ8Appender4DataZk@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4dataMNgFNaNbNdNiNeZANgAya@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender6__ctorMFNaNbNcNeAAyaZS3std5array18__T8AppenderTAAyaZ8Appender@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender6__initZ@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array18__T8appenderTAAyaZ8appenderFNaNbNfZS3std5array18__T8AppenderTAAyaZ8Appender@Base 6
+ _D3std5array19__T8appenderHTAaTaZ8appenderFNaNbNfAaZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAxaTxaZ8appenderFNaNbNfAxaZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAyaTyaZ8appenderFNaNbNfAyaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAyuTyuZ8appenderFNaNbNfAyuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAywTywZ8appenderFNaNbNfAywZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array23__T7replaceTxaTAyaTAyaZ7replaceFNaNbNfAxaAyaAyaZAxa@Base 6
+ _D3std5array23__T7replaceTyaTAyaTAyaZ7replaceFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAaTkZ14arrayAllocImplFNaNbkZAa@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAfTkZ14arrayAllocImplFNaNbkZAf@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAhTkZ14arrayAllocImplFNaNbkZAh@Base 6
+ _D3std5array29__T18uninitializedArrayTAaTkZ18uninitializedArrayFNaNbNekZAa@Base 6
+ _D3std5array29__T18uninitializedArrayTAfTkZ18uninitializedArrayFNaNbNekZAf@Base 6
+ _D3std5array29__T19appenderNewCapacityVki1Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array29__T19appenderNewCapacityVki2Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array29__T19appenderNewCapacityVki4Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array29__T19appenderNewCapacityVki8Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array30__T18uninitializedArrayTAhTykZ18uninitializedArrayFNaNbNeykZAh@Base 6
+ _D3std5array30__T19appenderNewCapacityVki12Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array30__T19appenderNewCapacityVki24Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array31__T19appenderNewCapacityVki112Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender28__T3putTS3std4file8DirEntryZ3putMFNaNbNfS3std4file8DirEntryZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data11__xopEqualsFKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataZb@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data6__initZ@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data9__xtoHashFNbNeKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataZk@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4dataMNgFNaNbNdNiNeZANgS3std4file8DirEntry@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__ctorMFNaNbNcNeAS3std4file8DirEntryZS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array405__T5arrayTS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZ5arrayFNaNbNfS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZAxa@Base 6
+ _D3std5array405__T5arrayTS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZ5arrayFNaNbNfS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZAxa@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender34__T3putTS3std6socket11AddressInfoZ3putMFNaNbNfS3std6socket11AddressInfoZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data11__xopEqualsFKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataZb@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data6__initZ@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data9__xtoHashFNbNeKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataZk@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4dataMNgFNaNbNdNiNeZANgS3std6socket11AddressInfo@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender52__T10opOpAssignHVAyaa1_7eTS3std6socket11AddressInfoZ10opOpAssignMFNaNbNfS3std6socket11AddressInfoZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__ctorMFNaNbNcNeAS3std6socket11AddressInfoZS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__initZ@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array40__T8appenderTAS3std6socket11AddressInfoZ8appenderFNaNbNfZS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender@Base 6
+ _D3std5array52__T13copyBackwardsTS3std5regex8internal2ir8BytecodeZ13copyBackwardsFNaNbNiAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender46__T3putTS3std4file15DirIteratorImpl9DirHandleZ3putMFNaNbNfS3std4file15DirIteratorImpl9DirHandleZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data11__xopEqualsFKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataZb@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data6__initZ@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data9__xtoHashFNbNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataZk@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4dataMNgFNaNbNdNiNeZANgS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__ctorMFNaNbNcNeAS3std4file15DirIteratorImpl9DirHandleZS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array55__T13copyBackwardsTS3std5regex8internal2ir10NamedGroupZ13copyBackwardsFNaNbNiAS3std5regex8internal2ir10NamedGroupAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5array55__T8appenderHTAS3std4file8DirEntryTS3std4file8DirEntryZ8appenderFNaNbNfAS3std4file8DirEntryZS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender@Base 6
+ _D3std5array56__T14arrayAllocImplVbi0TAS3std3uni17CodepointIntervalTkZ14arrayAllocImplFNaNbkZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array56__T18uninitializedArrayTAS3std3uni17CodepointIntervalTkZ18uninitializedArrayFNaNbNekZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array57__T18uninitializedArrayTAS3std3uni17CodepointIntervalTyiZ18uninitializedArrayFNaNbNeyiZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array68__T11replaceIntoTxaTS3std5array17__T8AppenderTAxaZ8AppenderTAyaTAyaZ11replaceIntoFNaNbNfS3std5array17__T8AppenderTAxaZ8AppenderAxaAyaAyaZv@Base 6
+ _D3std5array68__T11replaceIntoTyaTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTAyaZ11replaceIntoFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderAyaAyaAyaZv@Base 6
+ _D3std5array79__T5arrayTS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZ5arrayFNaNbNfS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZAa@Base 6
+ _D3std5array85__T13insertInPlaceTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir8BytecodekS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array892__T5arrayTS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZ5arrayFNaNbNfS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZAa@Base 6
+ _D3std5array91__T13insertInPlaceTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir10NamedGroupkS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5array91__T8appenderHTAS3std4file15DirIteratorImpl9DirHandleTS3std4file15DirIteratorImpl9DirHandleZ8appenderFNaNbNfAS3std4file15DirIteratorImpl9DirHandleZS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender@Base 6
+ _D3std5ascii10isAlphaNumFNaNbNiNfwZb@Base 6
+ _D3std5ascii10isHexDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii10whitespaceyAa@Base 6
+ _D3std5ascii11isGraphicalFNaNbNiNfwZb@Base 6
+ _D3std5ascii11isPrintableFNaNbNiNfwZb@Base 6
+ _D3std5ascii11octalDigitsyAa@Base 6
+ _D3std5ascii12__ModuleInfoZ@Base 6
+ _D3std5ascii12isOctalDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii13fullHexDigitsyAa@Base 6
+ _D3std5ascii13isPunctuationFNaNbNiNfwZb@Base 6
+ _D3std5ascii14__T7toLowerTwZ7toLowerFNaNbNiNfwZw@Base 6
+ _D3std5ascii14lowerHexDigitsyAa@Base 6
+ _D3std5ascii15__T7toLowerTxaZ7toLowerFNaNbNiNfxaZa@Base 6
+ _D3std5ascii15__T7toLowerTxwZ7toLowerFNaNbNiNfxwZw@Base 6
+ _D3std5ascii15__T7toLowerTyaZ7toLowerFNaNbNiNfyaZa@Base 6
+ _D3std5ascii6digitsyAa@Base 6
+ _D3std5ascii7isASCIIFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isAlphaFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isLowerFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isUpperFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isWhiteFNaNbNiNfwZb@Base 6
+ _D3std5ascii7lettersyAa@Base 6
+ _D3std5ascii7newlineyAa@Base 6
+ _D3std5ascii9hexDigitsyAa@Base 6
+ _D3std5ascii9isControlFNaNbNiNfwZb@Base 6
+ _D3std5ascii9lowercaseyAa@Base 6
+ _D3std5ascii9uppercaseyAa@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange11__xopEqualsFKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZb@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4saveMFNaNbNdNiNfZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__ctorMFNaNbNcNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opIndexMFNaNbNcNiNfkZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7releaseMFNaNbNiZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange9__xtoHashFNbNeKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZk@Base 6
+ _D3std5range103__T12assumeSortedVAyaa17_612e74696d6554203c20622e74696d6554TAS3std8datetime13PosixTimeZone10LeapSecondZ12assumeSortedFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange11__xopEqualsFKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZb@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4saveMFNaNbNdNiNfZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__ctorMFNaNbNcNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opIndexMFNaNbNcNiNfkZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7releaseMFNaNbNiZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange9__xtoHashFNbNeKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZk@Base 6
+ _D3std5range107__T12assumeSortedVAyaa17_612e74696d6554203c20622e74696d6554TAS3std8datetime13PosixTimeZone14TempTransitionZ12assumeSortedFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range10interfaces12__ModuleInfoZ@Base 6
+ _D3std5range10primitives107__T6moveAtTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTkZ6moveAtFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalskZS3std3uni17CodepointInterval@Base 6
+ _D3std5range10primitives11__T4backThZ4backFNaNbNcNdNiNfAhZh@Base 6
+ _D3std5range10primitives11__T4backTkZ4backFNaNbNcNdNiNfAkZk@Base 6
+ _D3std5range10primitives11__T4saveTaZ4saveFNaNbNdNiNfAaZAa@Base 6
+ _D3std5range10primitives11__T4saveTfZ4saveFNaNbNdNiNfAfZAf@Base 6
+ _D3std5range10primitives11__T4saveThZ4saveFNaNbNdNiNfAhZAh@Base 6
+ _D3std5range10primitives11__T4saveTkZ4saveFNaNbNdNiNfAkZAk@Base 6
+ _D3std5range10primitives12__ModuleInfoZ@Base 6
+ _D3std5range10primitives12__T4backTxaZ4backFNaNdNfAxaZw@Base 6
+ _D3std5range10primitives12__T4backTxhZ4backFNaNbNcNdNiNfAxhZxh@Base 6
+ _D3std5range10primitives12__T4backTyaZ4backFNaNdNfAyaZw@Base 6
+ _D3std5range10primitives12__T4saveTxaZ4saveFNaNbNdNiNfAxaZAxa@Base 6
+ _D3std5range10primitives12__T4saveTxhZ4saveFNaNbNdNiNfAxhZAxh@Base 6
+ _D3std5range10primitives12__T4saveTxuZ4saveFNaNbNdNiNfAxuZAxu@Base 6
+ _D3std5range10primitives12__T4saveTyaZ4saveFNaNbNdNiNfAyaZAya@Base 6
+ _D3std5range10primitives12__T5emptyTaZ5emptyFNaNbNdNiNfxAaZb@Base 6
+ _D3std5range10primitives12__T5emptyTbZ5emptyFNaNbNdNiNfxAbZb@Base 6
+ _D3std5range10primitives12__T5emptyThZ5emptyFNaNbNdNiNfxAhZb@Base 6
+ _D3std5range10primitives12__T5emptyTkZ5emptyFNaNbNdNiNfxAkZb@Base 6
+ _D3std5range10primitives12__T5emptyTuZ5emptyFNaNbNdNiNfxAuZb@Base 6
+ _D3std5range10primitives12__T5emptyTwZ5emptyFNaNbNdNiNfxAwZb@Base 6
+ _D3std5range10primitives12__T5frontTaZ5frontFNaNdNfAaZw@Base 6
+ _D3std5range10primitives12__T5frontThZ5frontFNaNbNcNdNiNfAhZh@Base 6
+ _D3std5range10primitives12__T5frontTkZ5frontFNaNbNcNdNiNfAkZk@Base 6
+ _D3std5range10primitives138__T6moveAtTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultTkZ6moveAtFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZk@Base 6
+ _D3std5range10primitives138__T6moveAtTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultTkZ6moveAtFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZk@Base 6
+ _D3std5range10primitives139__T9moveFrontTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ9moveFrontFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZk@Base 6
+ _D3std5range10primitives139__T9moveFrontTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ9moveFrontFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZk@Base 6
+ _D3std5range10primitives13__T3putTAkTkZ3putFNaNbNiNfKAkkZv@Base 6
+ _D3std5range10primitives13__T4backTAyaZ4backFNaNbNcNdNiNfAAyaZAya@Base 6
+ _D3std5range10primitives13__T4saveTAxaZ4saveFNaNbNdNiNfAAxaZAAxa@Base 6
+ _D3std5range10primitives13__T4saveTAyaZ4saveFNaNbNdNiNfAAyaZAAya@Base 6
+ _D3std5range10primitives13__T5frontTxaZ5frontFNaNdNfAxaZw@Base 6
+ _D3std5range10primitives13__T5frontTxhZ5frontFNaNbNcNdNiNfAxhZxh@Base 6
+ _D3std5range10primitives13__T5frontTxuZ5frontFNaNdNfAxuZw@Base 6
+ _D3std5range10primitives13__T5frontTxwZ5frontFNaNbNcNdNiNfAxwZxw@Base 6
+ _D3std5range10primitives13__T5frontTyaZ5frontFNaNdNfAyaZw@Base 6
+ _D3std5range10primitives13__T5frontTyhZ5frontFNaNbNcNdNiNfAyhZyh@Base 6
+ _D3std5range10primitives13__T5frontTywZ5frontFNaNbNcNdNiNfAywZyw@Base 6
+ _D3std5range10primitives14__T5emptyTAxaZ5emptyFNaNbNdNiNfxAAaZb@Base 6
+ _D3std5range10primitives14__T5emptyTAyaZ5emptyFNaNbNdNiNfxAAyaZb@Base 6
+ _D3std5range10primitives14__T5frontTAyaZ5frontFNaNbNcNdNiNfAAyaZAya@Base 6
+ _D3std5range10primitives14__T5frontTyAaZ5frontFNaNbNcNdNiNfAyAaZyAa@Base 6
+ _D3std5range10primitives14__T7popBackThZ7popBackFNaNbNiNfKAhZv@Base 6
+ _D3std5range10primitives14__T7popBackTkZ7popBackFNaNbNiNfKAkZv@Base 6
+ _D3std5range10primitives15__T5doPutTAkTkZ5doPutFNaNbNiNfKAkKkZv@Base 6
+ _D3std5range10primitives15__T7popBackTxhZ7popBackFNaNbNiNfKAxhZv@Base 6
+ _D3std5range10primitives15__T7popBackTyaZ7popBackFNaNfKAyaZv@Base 6
+ _D3std5range10primitives15__T8popFrontTaZ8popFrontFNaNbNiNeKAaZv@Base 6
+ _D3std5range10primitives15__T8popFrontTkZ8popFrontFNaNbNiNfKAkZv@Base 6
+ _D3std5range10primitives16__T7popBackTAyaZ7popBackFNaNbNiNfKAAyaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxaZ8popFrontFNaNbNiNeKAxaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxhZ8popFrontFNaNbNiNfKAxhZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxuZ8popFrontFNaNbNiNeKAxuZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxwZ8popFrontFNaNbNiNfKAxwZv@Base 6
+ _D3std5range10primitives16__T8popFrontTyaZ8popFrontFNaNbNiNeKAyaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTyhZ8popFrontFNaNbNiNfKAyhZv@Base 6
+ _D3std5range10primitives16__T8popFrontTywZ8popFrontFNaNbNiNfKAywZv@Base 6
+ _D3std5range10primitives17__T6moveAtTAxhTkZ6moveAtFNaNbNiNfAxhkZxh@Base 6
+ _D3std5range10primitives17__T8moveBackTAxhZ8moveBackFNaNbNiNfAxhZxh@Base 6
+ _D3std5range10primitives17__T8moveBackTAyaZ8moveBackFNaNfAyaZw@Base 6
+ _D3std5range10primitives17__T8popFrontTAyaZ8popFrontFNaNbNiNfKAAyaZv@Base 6
+ _D3std5range10primitives17__T8popFrontTyAaZ8popFrontFNaNbNiNfKAyAaZv@Base 6
+ _D3std5range10primitives17__T9popFrontNTAhZ9popFrontNFNaNbNiNfKAhkZk@Base 6
+ _D3std5range10primitives18__T3putTDFAxaZvTaZ3putFKDFAxaZvaZ16__T9__lambda3TaZ9__lambda3FNaNbNiNeKaZAa@Base 6
+ _D3std5range10primitives18__T3putTDFAxaZvTaZ3putFKDFAxaZvaZv@Base 6
+ _D3std5range10primitives18__T9moveFrontTAxhZ9moveFrontFNaNbNiNfAxhZxh@Base 6
+ _D3std5range10primitives18__T9moveFrontTAyaZ9moveFrontFNaNfAyaZw@Base 6
+ _D3std5range10primitives192__T9moveFrontTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ9moveFrontFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZw@Base 6
+ _D3std5range10primitives19__T10walkLengthTAhZ10walkLengthFNaNbNiNfAhZk@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTAaZ3putFKDFAxaZvAaZv@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTxaZ3putFKDFAxaZvxaZ17__T9__lambda3TxaZ9__lambda3FNaNbNiNeKxaZAxa@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTxaZ3putFKDFAxaZvxaZv@Base 6
+ _D3std5range10primitives20__T10walkLengthTAyaZ10walkLengthFNaNbNiNfAyaZk@Base 6
+ _D3std5range10primitives20__T3putTDFAxaZvTAxaZ3putFKDFAxaZvAxaZv@Base 6
+ _D3std5range10primitives20__T3putTDFAxaZvTAyaZ3putFKDFAxaZvAyaZv@Base 6
+ _D3std5range10primitives21__T5doPutTDFAxaZvTAaZ5doPutFKDFAxaZvAaZv@Base 6
+ _D3std5range10primitives21__T5doPutTDFAxaZvTAaZ5doPutFKDFAxaZvKAaZv@Base 6
+ _D3std5range10primitives223__T10walkLengthTS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZ10walkLengthFNaNbNiNfS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakexkZk@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAxaZ5doPutFKDFAxaZvAxaZv@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAxaZ5doPutFKDFAxaZvKAxaZv@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAyaZ5doPutFKDFAxaZvKAyaZv@Base 6
+ _D3std5range10primitives24__T3putTDFNaNbNfAxaZvTaZ3putFKDFNaNbNfAxaZvaZ16__T9__lambda3TaZ9__lambda3FNaNbNiNeKaZAa@Base 6
+ _D3std5range10primitives24__T3putTDFNaNbNfAxaZvTaZ3putFNaNbNfKDFNaNbNfAxaZvaZv@Base 6
+ _D3std5range10primitives25__T14popBackExactlyTAAyaZ14popBackExactlyFNaNbNiNfKAAyakZv@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTAaZ3putFNaNbNfKDFNaNbNfAxaZvAaZv@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTxaZ3putFKDFNaNbNfAxaZvxaZ17__T9__lambda3TxaZ9__lambda3FNaNbNiNeKxaZAxa@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTxaZ3putFNaNbNfKDFNaNbNfAxaZvxaZv@Base 6
+ _D3std5range10primitives26__T15popFrontExactlyTAAyaZ15popFrontExactlyFNaNbNiNfKAAyakZv@Base 6
+ _D3std5range10primitives26__T3putTDFNaNbNfAxaZvTAxaZ3putFNaNbNfKDFNaNbNfAxaZvAxaZv@Base 6
+ _D3std5range10primitives26__T3putTDFNaNbNfAxaZvTAyaZ3putFNaNbNfKDFNaNbNfAxaZvAyaZv@Base 6
+ _D3std5range10primitives27__T5doPutTDFNaNbNfAxaZvTAaZ5doPutFNaNbNfKDFNaNbNfAxaZvAaZv@Base 6
+ _D3std5range10primitives27__T5doPutTDFNaNbNfAxaZvTAaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAxaZ5doPutFNaNbNfKDFNaNbNfAxaZvAxaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAxaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAxaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAyaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAyaZv@Base 6
+ _D3std5range10primitives30__T5emptyTS3std4file8DirEntryZ5emptyFNaNbNdNiNfxAS3std4file8DirEntryZb@Base 6
+ _D3std5range10primitives31__T5emptyTS3std4json9JSONValueZ5emptyFNaNbNdNiNfxAS3std4json9JSONValueZb@Base 6
+ _D3std5range10primitives41__T14popBackExactlyTAC4core6thread5FiberZ14popBackExactlyFNaNbNiNfKAC4core6thread5FiberkZv@Base 6
+ _D3std5range10primitives42__T15popFrontExactlyTAC4core6thread5FiberZ15popFrontExactlyFNaNbNiNfKAC4core6thread5FiberkZv@Base 6
+ _D3std5range10primitives43__T5emptyTS3std5regex8internal2ir8BytecodeZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir8BytecodeZb@Base 6
+ _D3std5range10primitives45__T4backTS3std5regex8internal2ir10NamedGroupZ4backFNaNbNcNdNiNfAS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives45__T4saveTS3std5regex8internal2ir10NamedGroupZ4saveFNaNbNdNiNfAS3std5regex8internal2ir10NamedGroupZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives46__T3putTS3std5stdio4File17LockingTextWriterTaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriteraZv@Base 6
+ _D3std5range10primitives46__T3putTS3std5stdio4File17LockingTextWriterTwZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterwZv@Base 6
+ _D3std5range10primitives46__T5emptyTS3std5regex8internal2ir10NamedGroupZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5range10primitives46__T5frontTS3std5regex8internal2ir10NamedGroupZ5frontFNaNbNcNdNiNfAS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTAaZ3putFNfKS3std5stdio4File17LockingTextWriterAaZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTxaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterxaZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTxwZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterxwZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTyaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriteryaZv@Base 6
+ _D3std5range10primitives47__T6moveAtTS3std5range13__T6RepeatTiZ6RepeatTkZ6moveAtFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatkZi@Base 6
+ _D3std5range10primitives48__T3putTS3std5stdio4File17LockingTextWriterTAxaZ3putFNfKS3std5stdio4File17LockingTextWriterAxaZv@Base 6
+ _D3std5range10primitives48__T3putTS3std5stdio4File17LockingTextWriterTAyaZ3putFNfKS3std5stdio4File17LockingTextWriterAyaZv@Base 6
+ _D3std5range10primitives48__T5doPutTS3std5stdio4File17LockingTextWriterTaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKaZv@Base 6
+ _D3std5range10primitives48__T5doPutTS3std5stdio4File17LockingTextWriterTwZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKwZv@Base 6
+ _D3std5range10primitives48__T5emptyTS3std4file15DirIteratorImpl9DirHandleZ5emptyFNaNbNdNiNfxAS3std4file15DirIteratorImpl9DirHandleZb@Base 6
+ _D3std5range10primitives48__T7popBackTS3std5regex8internal2ir10NamedGroupZ7popBackFNaNbNiNfKAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5range10primitives48__T9moveFrontTS3std5range13__T6RepeatTiZ6RepeatZ9moveFrontFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatZi@Base 6
+ _D3std5range10primitives48__T9popFrontNTAS3std5regex8internal2ir8BytecodeZ9popFrontNFNaNbNiNfKAS3std5regex8internal2ir8BytecodekZk@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTAaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAaZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTxaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKxaZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTxwZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKxwZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTyaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKyaZv@Base 6
+ _D3std5range10primitives49__T5emptyTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5emptyFNaNbNdNiNfxAS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std5range10primitives49__T8popFrontTS3std5regex8internal2ir10NamedGroupZ8popFrontFNaNbNiNfKAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderaZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTwZ3putFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderwZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderaZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTwZ3putFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderwZv@Base 6
+ _D3std5range10primitives50__T5doPutTS3std5stdio4File17LockingTextWriterTAxaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAxaZv@Base 6
+ _D3std5range10primitives50__T5doPutTS3std5stdio4File17LockingTextWriterTAyaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAyaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTxaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderxaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTxwZ3putFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderxwZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTyaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderyaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTxaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderxaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTxwZ3putFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderxwZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTyaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderyaZv@Base 6
+ _D3std5range10primitives51__T4backTS3std8datetime13PosixTimeZone10LeapSecondZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives51__T4backTS3std8datetime13PosixTimeZone10TransitionZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives51__T4backTyS3std8internal14unicode_tables9CompEntryZ4backFNaNbNcNdNiNfAyS3std8internal14unicode_tables9CompEntryZyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives51__T4saveTS3std8datetime13PosixTimeZone10LeapSecondZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives51__T4saveTS3std8datetime13PosixTimeZone10TransitionZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone10TransitionZAS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives51__T4saveTyS3std8internal14unicode_tables9CompEntryZ4saveFNaNbNdNiNfAyS3std8internal14unicode_tables9CompEntryZAyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives51__T5emptyTS3std8internal14unicode_tables9CompEntryZ5emptyFNaNbNdNiNfxAS3std8internal14unicode_tables9CompEntryZb@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAxaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAxaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAyaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAyaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAxaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAxaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAyaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAyaZv@Base 6
+ _D3std5range10primitives52__T4backTyS3std8datetime13PosixTimeZone10LeapSecondZ4backFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives52__T4backTyS3std8datetime13PosixTimeZone10TransitionZ4backFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10TransitionZyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKaZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTwZ5doPutFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKwZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKaZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTwZ5doPutFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKwZv@Base 6
+ _D3std5range10primitives52__T5emptyTS3std8datetime13PosixTimeZone10LeapSecondZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std5range10primitives52__T5emptyTS3std8datetime13PosixTimeZone10TransitionZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone10TransitionZb@Base 6
+ _D3std5range10primitives52__T5frontTS3std8datetime13PosixTimeZone10LeapSecondZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives52__T5frontTS3std8datetime13PosixTimeZone10TransitionZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives52__T5frontTyS3std8internal14unicode_tables9CompEntryZ5frontFNaNbNcNdNiNfAyS3std8internal14unicode_tables9CompEntryZyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKxaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTxwZ5doPutFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKxwZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKyaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKxaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTxwZ5doPutFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKxwZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKyaZv@Base 6
+ _D3std5range10primitives53__T5frontTyS3std8datetime13PosixTimeZone10LeapSecondZ5frontFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAxaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAyaZv@Base 6
+ _D3std5range10primitives54__T5emptyTS3std5regex8internal2ir12__T5GroupTkZ5GroupZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5range10primitives54__T7popBackTS3std8datetime13PosixTimeZone10LeapSecondZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std5range10primitives54__T7popBackTS3std8datetime13PosixTimeZone10TransitionZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range10primitives54__T7popBackTyS3std8internal14unicode_tables9CompEntryZ7popBackFNaNbNiNfKAyS3std8internal14unicode_tables9CompEntryZv@Base 6
+ _D3std5range10primitives55__T4backTS3std8datetime13PosixTimeZone14TempTransitionZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives55__T4saveTS3std8datetime13PosixTimeZone14TempTransitionZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives55__T8popFrontTS3std8datetime13PosixTimeZone10LeapSecondZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std5range10primitives55__T8popFrontTS3std8datetime13PosixTimeZone10TransitionZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range10primitives55__T8popFrontTyS3std8internal14unicode_tables9CompEntryZ8popFrontFNaNbNiNfKAyS3std8internal14unicode_tables9CompEntryZv@Base 6
+ _D3std5range10primitives56__T5emptyTS3std8datetime13PosixTimeZone14TempTransitionZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std5range10primitives56__T5frontTS3std8datetime13PosixTimeZone14TempTransitionZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives56__T6moveAtTAS3std8datetime13PosixTimeZone10TransitionTkZ6moveAtFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionkZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives56__T8moveBackTAS3std8datetime13PosixTimeZone10TransitionZ8moveBackFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives57__T9moveFrontTAS3std8datetime13PosixTimeZone10TransitionZ9moveFrontFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives58__T4backTyS3std8internal14unicode_tables15UnicodePropertyZ4backFNaNbNcNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives58__T4saveTyS3std8internal14unicode_tables15UnicodePropertyZ4saveFNaNbNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives58__T5emptyTS3std8internal14unicode_tables15UnicodePropertyZ5emptyFNaNbNdNiNfxAS3std8internal14unicode_tables15UnicodePropertyZb@Base 6
+ _D3std5range10primitives58__T7popBackTS3std8datetime13PosixTimeZone14TempTransitionZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std5range10primitives59__T5frontTyS3std8internal14unicode_tables15UnicodePropertyZ5frontFNaNbNcNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives59__T8popFrontTS3std8datetime13PosixTimeZone14TempTransitionZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std5range10primitives61__T7popBackTyS3std8internal14unicode_tables15UnicodePropertyZ7popBackFNaNbNiNfKAyS3std8internal14unicode_tables15UnicodePropertyZv@Base 6
+ _D3std5range10primitives62__T6moveAtTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTkZ6moveAtFNaNbNiNfS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultkZa@Base 6
+ _D3std5range10primitives62__T8moveBackTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZ8moveBackFNaNbNiNfS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZa@Base 6
+ _D3std5range10primitives62__T8popFrontTyS3std8internal14unicode_tables15UnicodePropertyZ8popFrontFNaNbNiNfKAyS3std8internal14unicode_tables15UnicodePropertyZv@Base 6
+ _D3std5range10primitives63__T9moveFrontTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZ9moveFrontFNaNbNiNfS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZa@Base 6
+ _D3std5range10primitives673__T3putTAkTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ3putFNaNfKAkS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZv@Base 6
+ _D3std5range10primitives678__T10walkLengthTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ10walkLengthFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZk@Base 6
+ _D3std5range10primitives67__T4backTS3std12experimental6logger11multilogger16MultiLoggerEntryZ4backFNaNbNcNdNiNfAS3std12experimental6logger11multilogger16MultiLoggerEntryZS3std12experimental6logger11multilogger16MultiLoggerEntry@Base 6
+ _D3std5range10primitives70__T7popBackTS3std12experimental6logger11multilogger16MultiLoggerEntryZ7popBackFNaNbNiNfKAS3std12experimental6logger11multilogger16MultiLoggerEntryZv@Base 6
+ _D3std5range10primitives71__T5emptyTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5emptyFNaNbNdNiNfxAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std5range10primitives75__T5emptyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5emptyFNaNbNdNiNfxAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std5range10primitives76__T6moveAtTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTkZ6moveAtFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplkZa@Base 6
+ _D3std5range10primitives76__T8moveBackTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZa@Base 6
+ _D3std5range10primitives77__T9moveFrontTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZa@Base 6
+ _D3std5range10primitives78__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaZ3putFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkaZv@Base 6
+ _D3std5range10primitives78__T5emptyTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZ5emptyFNaNbNdNiNfxAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZb@Base 6
+ _D3std5range10primitives78__T6moveAtTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTkZ6moveAtFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplkZxa@Base 6
+ _D3std5range10primitives78__T6moveAtTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTkZ6moveAtFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplkZya@Base 6
+ _D3std5range10primitives78__T8moveBackTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZxa@Base 6
+ _D3std5range10primitives78__T8moveBackTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZya@Base 6
+ _D3std5range10primitives79__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAaZ3putFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkAaZv@Base 6
+ _D3std5range10primitives79__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTxaZ3putFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxaZv@Base 6
+ _D3std5range10primitives79__T9moveFrontTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZxa@Base 6
+ _D3std5range10primitives79__T9moveFrontTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZya@Base 6
+ _D3std5range10primitives80__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAxaZ3putFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkAxaZv@Base 6
+ _D3std5range10primitives80__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaZ5doPutFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKaZv@Base 6
+ _D3std5range10primitives81__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAaZ5doPutFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKAaZv@Base 6
+ _D3std5range10primitives81__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTxaZ5doPutFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKxaZv@Base 6
+ _D3std5range10primitives82__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAxaZ5doPutFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKAxaZv@Base 6
+ _D3std5range11__T4iotaTkZ4iotaFNaNbNiNfkZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range11__T4onlyTaZ4onlyFNaNbNiNfaZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range12__ModuleInfoZ@Base 6
+ _D3std5range12__T4takeTAhZ4takeFNaNbNiNfAhkZAh@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4backMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4saveMFNaNbNdNiNfZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5frontMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6moveAtMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7opIndexMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8moveBackMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9moveFrontMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4backMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4saveMFNaNbNdNiNfZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5frontMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6moveAtMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7opIndexMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8moveBackMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9moveFrontMFNfZk@Base 6
+ _D3std5range134__T4takeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4takeFNaNbNiNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4takeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4takeFNaNbNiNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFNaNbNiNfkkZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result4backMNgFNaNbNdNiNfZNgk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result4saveMFNaNbNdNiNfZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result5frontMNgFNaNbNdNiNfZNgk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6__ctorMFNaNbNcNiNfkkZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6__initZ@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7opIndexMNgFNaNbNiNfmZNgk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7opSliceMNgFNaNbNiNfZNgS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7opSliceMNgFNaNbNiNfmmZNgS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat11DollarToken6__initZ@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat4backMNgFNaNbNdNiNfZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat4saveMNgFNaNbNdNiNfZNgS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat5frontMNgFNaNbNdNiNfZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat6__initZ@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opIndexMNgFNaNbNiNfkZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opSliceMFNaNbNfkkZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opSliceMNgFNaNbNiNfkS3std5range13__T6RepeatTiZ6Repeat11DollarTokenZNgS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6repeatTiZ6repeatFNaNbNiNfiZS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result10retroIndexMFNaNbNiNfkZk@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result4backMFNaNbNcNdNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result5frontMFNaNbNcNdNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6moveAtMFNaNbNiNfkZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7opIndexMFNaNbNcNiNfkZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7opSliceMFNaNbNiNfkkZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result8moveBackMFNaNbNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultZk@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result9moveFrontMFNaNbNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFNaNbNiNfAxhZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result4backMFNaNdNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result5frontMFNaNdNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result8moveBackMFNaNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZk@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result9moveFrontMFNaNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFNaNbNiNfAyaZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11DollarToken6__initZ@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11DollarToken9momLengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11__xopEqualsFKxS3std5range14__T6ChunksTAhZ6ChunksKxS3std5range14__T6ChunksTAhZ6ChunksZb@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks4backMFNaNbNdNiNfZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks4saveMFNaNbNdNiNfZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks5frontMFNaNbNdNiNfZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6__ctorMFNaNbNcNiNfAhkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6__initZ@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opIndexMFNaNbNiNfkZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfkS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfkkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks8opDollarMFNaNbNiNfZS3std5range14__T6ChunksTAhZ6Chunks11DollarToken@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks9__xtoHashFNbNeKxS3std5range14__T6ChunksTAhZ6ChunksZk@Base 6
+ _D3std5range14__T6chunksTAhZ6chunksFNaNbNiNfAhkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take11__xopEqualsFKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZb@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take4saveMFNaNbNdNiNfZS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take5frontMFNaNbNdNiNfZw@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take6__initZ@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9__xtoHashFNbNeKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZk@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9moveFrontMFNaNbNiNfZw@Base 6
+ _D3std5range187__T4takeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4takeFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkZS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfkZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfkZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfkkZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZk@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfkkZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfkkZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange13__T3geqTywTwZ3geqMFNaNbNiNfywwZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange287__T18getTransitionIndexVE3std5range12SearchPolicyi3S2293std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange3geqTwZ18getTransitionIndexMFNaNbNiNfwZk@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi3TwZ10lowerBoundMFNaNbNiNfwZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange4backMFNaNbNdNiNfZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNdNiNfZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNiNfkZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeZk@Base 6
+ _D3std5range200__T12assumeSortedVAyaa5_61203c2062TS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZ12assumeSortedFNaNbNiNfS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange11__xopEqualsFKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeZb@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange4backMFNaNbNdNiNfZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange4saveMFNaNbNdNiNfZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange5frontMFNaNbNdNiNfZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__ctorMFNaNbNcNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__initZ@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7opIndexMFNaNbNiNfkZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7releaseMFNaNbNiZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange9__xtoHashFNbNeKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeZk@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult11__T6__ctorZ6__ctorMFNaNbNcNiNfKaZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult4backMFNaNbNdNiNfZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult4saveMFNaNbNdNiNfZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult5frontMFNaNbNdNiNfZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6__initZ@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7opIndexMFNaNbNiNfkZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7opSliceMFNaNbNiNfZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7opSliceMFNaNbNiNfkkZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFNaNbNiNfS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result11__xopEqualsFKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZb@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result4saveMFNaNdNfZS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result5emptyMFNaNdNfZb@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result5frontMFNaNdNfZk@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result6__initZ@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result9__xtoHashFNbNeKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange11__xopEqualsFKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange121__T18getTransitionIndexVE3std5range12SearchPolicyi3S643std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange3geqTkZ18getTransitionIndexMFNaNbNiNfkZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange12__T3geqTkTkZ3geqMFNaNbNiNfkkZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi3TkZ10lowerBoundMFNaNbNiNfkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange4saveMFNaNbNdNiNfZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__initZ@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7opIndexMFNaNbNcNiNfkZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange9__xtoHashFNbNeKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeZk@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange455__T18getTransitionIndexVE3std5range12SearchPolicyi3S3953std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZk@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZk@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange458__T18getTransitionIndexVE3std5range12SearchPolicyi3S3983std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZk@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZk@Base 6
+ _D3std5range36__T12assumeSortedVAyaa4_613c3d62TAkZ12assumeSortedFNaNbNiNfAkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange461__T18getTransitionIndexVE3std5range12SearchPolicyi3S4013std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZk@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange123__T18getTransitionIndexVE3std5range12SearchPolicyi2S663std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange3geqTiZ18getTransitionIndexMFNaNbNiNfiZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange123__T18getTransitionIndexVE3std5range12SearchPolicyi3S663std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange3geqTiZ18getTransitionIndexMFNaNbNiNfiZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange12__T3geqTkTiZ3geqMFNaNbNiNfkiZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi2TiZ10lowerBoundMFNaNbNiNfiZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNcNiNfkZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeZk@Base 6
+ _D3std5range38__T12assumeSortedVAyaa5_61203c2062TAkZ12assumeSortedFNaNbNiNfAkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange4backMFNaNbNcNdNiNfZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNcNdNiNfZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNcNiNfkZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZAAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange11__xopEqualsFKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange126__T18getTransitionIndexVE3std5range12SearchPolicyi3S683std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange3geqTyiZ18getTransitionIndexMFNaNbNiNfyiZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange13__T3geqTkTyiZ3geqMFNaNbNiNfkyiZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange47__T10lowerBoundVE3std5range12SearchPolicyi3TyiZ10lowerBoundMFNaNbNiNfyiZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__initZ@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7opIndexMFNaNbNcNiNfkZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange9__xtoHashFNbNeKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeZk@Base 6
+ _D3std5range40__T12assumeSortedVAyaa5_61203c2062TAAyaZ12assumeSortedFNaNbNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range40__T12assumeSortedVAyaa6_61203c3d2062TAkZ12assumeSortedFNaNbNiNfAkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take4backMFNaNbNdNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take4saveMFNaNbNdNiNfZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take5frontMFNaNbNdNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6__initZ@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6moveAtMFNaNbNiNfkZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take7opIndexMFNaNbNiNfkZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take8moveBackMFNaNbNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take9moveFrontMFNaNbNiNfZi@Base 6
+ _D3std5range51__T11takeExactlyTS3std5range13__T6RepeatTiZ6RepeatZ11takeExactlyFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatkZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result10retroIndexMFNaNbNiNfkZk@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result13opIndexAssignMFNaNbNiNfS3std8datetime13PosixTimeZone10TransitionkZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4backMFNaNbNdNiNfS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5frontMFNaNbNdNiNfS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6moveAtMFNaNbNiNfkZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7opIndexMFNaNbNcNiNfkZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7opSliceMFNaNbNiNfkkZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result8moveBackMFNaNbNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultZk@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result9moveFrontMFNaNbNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range69__T5retroTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ5retroFNaNbNiNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZAya@Base 6
+ _D3std5range8NullSink6__initZ@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange11__xopEqualsFKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange213__T18getTransitionIndexVE3std5range12SearchPolicyi3S1213std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange3geqTS3std5regex8internal2ir10NamedGroupZ18getTransitionIndexMFNaNbNiNfS3std5regex8internal2ir10NamedGroupZk@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange4backMFNaNbNcNdNiNfZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange4saveMFNaNbNdNiNfZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange5frontMFNaNbNcNdNiNfZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__ctorMFNaNbNcNiNfAS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__initZ@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7opIndexMFNaNbNcNiNfkZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7releaseMFNaNbNiZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange80__T10lowerBoundVE3std5range12SearchPolicyi3TS3std5regex8internal2ir10NamedGroupZ10lowerBoundMFNaNbNiNfS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange80__T3geqTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ3geqMFNaNbNiNfS3std5regex8internal2ir10NamedGroupS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange9__xtoHashFNbNeKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeZk@Base 6
+ _D3std5range93__T12assumeSortedVAyaa15_612e6e616d65203c20622e6e616d65TAS3std5regex8internal2ir10NamedGroupZ12assumeSortedFNaNbNiNfAS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5regex12__ModuleInfoZ@Base 6
+ _D3std5regex14__T5regexTAyaZ5regexFNeAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures10newMatchesMFNaNbNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures11__xopEqualsFKxS3std5regex18__T8CapturesTAaTkZ8CapturesKxS3std5regex18__T8CapturesTAaTkZ8CapturesZb@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures12__T7opIndexZ7opIndexMFNaNbNekZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures3hitMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures3preMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures4backMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures4postMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures59__T6__ctorS453std5regex8internal8thompson15ThompsonMatcherZ6__ctorMFNaNbNcNeKS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures5frontMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures6__initZ@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures7matchesMFNaNbNdNiNeZAS3std5regex8internal2ir12__T5GroupTkZ5Group@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures7popBackMFNaNbNiNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures8capturesMFNaNbNcNdNiNeZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures8popFrontMFNaNbNiNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures9__xtoHashFNbNeKxS3std5regex18__T8CapturesTAaTkZ8CapturesZk@Base 6
+ _D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures10newMatchesMFNaNbNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures11__xopEqualsFKxS3std5regex19__T8CapturesTAxaTkZ8CapturesKxS3std5regex19__T8CapturesTAxaTkZ8CapturesZb@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures12__T7opIndexZ7opIndexMFNaNbNekZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures3hitMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures3preMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures4backMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures4postMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures59__T6__ctorS453std5regex8internal8thompson15ThompsonMatcherZ6__ctorMFNaNbNcNeKS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures5frontMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures6__initZ@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures7matchesMFNaNbNdNiNeZAS3std5regex8internal2ir12__T5GroupTkZ5Group@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures7popBackMFNaNbNiNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures8capturesMFNaNbNcNdNiNeZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures8popFrontMFNaNbNiNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures9__xtoHashFNbNeKxS3std5regex19__T8CapturesTAxaTkZ8CapturesZk@Base 6
+ _D3std5regex57__T5matchTAaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ5matchFNfAaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex58__T5matchTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ5matchFNfAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch10__postblitMFNaNbNiNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch11__xopEqualsFKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZb@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3hitMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3preMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4postMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4saveMFNaNbNiNeZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch55__T6__ctorTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ6__ctorMFNcNeAaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5frontMFNaNbNdNiNeZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__dtorMFNbNiNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch7counterMFNaNbNcNdNiNeZk@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8capturesMFNaNbNdNiNeZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8opAssignMFNbNcNiNjNeS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8popFrontMFNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch9__xtoHashFNbNeKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZk@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch10__postblitMFNaNbNiNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch11__xopEqualsFKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZb@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3hitMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3preMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4postMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4saveMFNaNbNiNeZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch55__T6__ctorTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ6__ctorMFNcNeAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5frontMFNaNbNdNiNeZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__dtorMFNbNiNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch7counterMFNaNbNcNdNiNeZk@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8capturesMFNaNbNdNiNeZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8opAssignMFNbNcNiNjNeS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8popFrontMFNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch9__xtoHashFNbNeKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZk@Base 6
+ _D3std5regex8internal12backtracking10__T5ctSubZ5ctSubFNaNbNiNeAyaZAya@Base 6
+ _D3std5regex8internal12backtracking12__ModuleInfoZ@Base 6
+ _D3std5regex8internal12backtracking12__T5ctSubTiZ5ctSubFNaNbNeAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking12__T5ctSubTkZ5ctSubFNaNbNeAyakZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTAyaZ5ctSubFNaNbNeAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTiTiZ5ctSubFNaNbNeAyaiiZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTkTiZ5ctSubFNaNbNeAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTkTkZ5ctSubFNaNbNeAyakkZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTAyaTiZ5ctSubFNaNbNeAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTiTAyaZ5ctSubFNaNbNeAyaiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTiTkTiZ5ctSubFNaNbNeAyaikiZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTkTAyaZ5ctSubFNaNbNeAyakAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTAyaTkTiZ5ctSubFNaNbNeAyaAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTiTAyaTiZ5ctSubFNaNbNeAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTiTiTAyaZ5ctSubFNaNbNeAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTkTiTkTiZ5ctSubFNaNbNeAyakikiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTAyaTAyaTiZ5ctSubFNaNbNeAyaAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTiTiTAyaTiZ5ctSubFNaNbNeAyaiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTkTAyaTAyaZ5ctSubFNaNbNeAyakAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTkTAyaTkTiZ5ctSubFNaNbNeAyakAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTiTiTAyaZ5ctSubFNaNbNeAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTiTAyaTAyaTiZ5ctSubFNaNbNeAyaiAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTkTiTiTAyaTiZ5ctSubFNaNbNeAyakiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTAyaTiTiTAyaTiZ5ctSubFNaNbNeAyaAyaiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTkTAyaTAyaTAyaZ5ctSubFNaNbNeAyakAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTAyaTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyakiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10bwdMatcherMFNaNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10fwdMatcherMFNaNbNiNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10initializeMFNaNbNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10stackAvailMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher11__xopEqualsFKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher13matchFinalizeMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher4nextMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5atEndMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__ctorMFNaNbNcNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvwkZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__ctorMFNaNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6searchMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher8newStackMFNbNiNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9__xtoHashFNbNeKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9matchImplMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9prevStackMFNbNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9stackSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10bwdMatcherMFNaNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10fwdMatcherMFNaNbNiNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10initializeMFNaNbNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10stackAvailMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher11__xopEqualsFKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher13matchFinalizeMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher4nextMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5atEndMFNaNdNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__ctorMFNaNbNcNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvwkZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__ctorMFNaNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6searchMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher8newStackMFNbNiNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9__xtoHashFNbNeKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9matchImplMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9prevStackMFNbNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9stackSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking30__T5ctSubTiTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTiTiTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiiiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking34__T5ctSubTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking36__T5ctSubTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking36__T5ctSubTiTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking38__T5ctSubTiTiTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiiiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking40__T5ctSubTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking42__T5ctSubTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking46__T5ctSubTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking50__T5ctSubTAyaTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking52__T5ctSubTiTAyaTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctAtomCodeMFAS3std5regex8internal2ir8BytecodeiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenBlockMFAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenGroupMFKAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenRegExMFAS3std5regex8internal2ir8BytecodeZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10lookaroundMFkkZS3std5regex8internal12backtracking9CtContext@Base 6
+ _D3std5regex8internal12backtracking9CtContext11ctQuickTestMFAS3std5regex8internal2ir8BytecodeiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext11restoreCodeMFZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext14ctGenFixupCodeMFAS3std5regex8internal2ir8BytecodeiiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext14ctGenFixupCodeMFKAS3std5regex8internal2ir8BytecodeiiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext16ctGenAlternationMFAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext6__initZ@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState11__xopEqualsFKxS3std5regex8internal12backtracking9CtContext7CtStateKxS3std5regex8internal12backtracking9CtContext7CtStateZb@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState9__xtoHashFNbNeKxS3std5regex8internal12backtracking9CtContext7CtStateZk@Base 6
+ _D3std5regex8internal12backtracking9CtContext8saveCodeMFkAyaZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext9ctGenAtomMFKAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal2ir10NamedGroup11__xopEqualsFKxS3std5regex8internal2ir10NamedGroupKxS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D3std5regex8internal2ir10NamedGroup9__xtoHashFNbNeKxS3std5regex8internal2ir10NamedGroupZk@Base 6
+ _D3std5regex8internal2ir10lengthOfIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir11RegexOption6__initZ@Base 6
+ _D3std5regex8internal2ir11disassembleFNexAS3std5regex8internal2ir8BytecodekxAS3std5regex8internal2ir10NamedGroupZAya@Base 6
+ _D3std5regex8internal2ir12__ModuleInfoZ@Base 6
+ _D3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper11__xopEqualsFKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper5atEndMFNaNdNfZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper5resetMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__ctorMFNaNbNcNiNfS3std5regex8internal2ir12__T5InputTaZ5InputkZS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper7opSliceMFNaNbNiNfkkZAxa@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper8loopBackMFNaNbNiNfkZS3std5regex8internal2ir12__T5InputTaZ5Input@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper8nextCharMFNaNeKwKkZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZk@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper9lastIndexMFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input11__xopEqualsFKxS3std5regex8internal2ir12__T5InputTaZ5InputKxS3std5regex8internal2ir12__T5InputTaZ5InputZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input5atEndMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input5resetMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input66__T6searchTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZ6searchMFNaNfKS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrKwKkZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input6__ctorMFNaNbNcNiNfAxakZS3std5regex8internal2ir12__T5InputTaZ5Input@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input7opSliceMFNaNbNiNfkkZAxa@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input8loopBackMFNaNbNiNfkZS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input8nextCharMFNaNfKwKkZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5InputTaZ5InputZk@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input9lastIndexMFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex11__xopEqualsFKxS3std5regex8internal2ir12__T5RegexTaZ5RegexKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNaNbNdNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange11__xopEqualsFKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange4backMFNaNbNdNiNfZAya@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange4saveMFNaNbNdNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange5frontMFNaNbNdNiNfZAya@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__ctorMFNaNbNcNiNfAS3std5regex8internal2ir10NamedGroupkkZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7opSliceMFNaNbNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7opSliceMFNaNbNiNfkkZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex14checkIfOneShotMFZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex9isBackrefMFNaNbNiNfkZk@Base 6
+ _D3std5regex8internal2ir13wordCharacterFNdZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir14RegexException6__ctorMFNeAyaAyakZC3std5regex8internal2ir14RegexException@Base 6
+ _D3std5regex8internal2ir14RegexException6__initZ@Base 6
+ _D3std5regex8internal2ir14RegexException6__vtblZ@Base 6
+ _D3std5regex8internal2ir14RegexException7__ClassZ@Base 6
+ _D3std5regex8internal2ir14__T9endOfLineZ9endOfLineFNaNbNiNfwbZb@Base 6
+ _D3std5regex8internal2ir16lengthOfPairedIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir17__T11startOfLineZ11startOfLineFNaNbNiNfwbZb@Base 6
+ _D3std5regex8internal2ir17immediateParamsIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex11__xopEqualsFKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexZb@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__ctorMFNaNbNcNiNfS3std5regex8internal2ir12__T5RegexTaZ5RegexPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZbZS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__initZ@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex9__xtoHashFNbNeKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexZk@Base 6
+ _D3std5regex8internal2ir19__T11mallocArrayTkZ11mallocArrayFNbNikZAk@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZ11initializedb@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZ4slotS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir20__T12arrayInChunkTkZ12arrayInChunkFNaNbNikKAvZAk@Base 6
+ _D3std5regex8internal2ir2IR6__initZ@Base 6
+ _D3std5regex8internal2ir62__T12quickTestFwdTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ12quickTestFwdFNaNbNiNfkwKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZi@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZ11initializedb@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZ4slotS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir7getTrieFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir7isEndIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8Bytecode11indexOfPairMxFkZk@Base 6
+ _D3std5regex8internal2ir8Bytecode11setLocalRefMFZv@Base 6
+ _D3std5regex8internal2ir8Bytecode12pairedLengthMxFNdZk@Base 6
+ _D3std5regex8internal2ir8Bytecode13__T8mnemonicZ8mnemonicMxFNaNdNeZAya@Base 6
+ _D3std5regex8internal2ir8Bytecode13__T8sequenceZ8sequenceMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir8Bytecode13backreferenceMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode14setBackrefenceMFZv@Base 6
+ _D3std5regex8internal2ir8Bytecode4argsMxFNdZi@Base 6
+ _D3std5regex8internal2ir8Bytecode5isEndMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode6__ctorMFNcE3std5regex8internal2ir2IRkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode6__ctorMFNcE3std5regex8internal2ir2IRkkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D3std5regex8internal2ir8Bytecode6isAtomMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode6lengthMxFNdZk@Base 6
+ _D3std5regex8internal2ir8Bytecode6pairedMxFNdZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode7fromRawFkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode7hotspotMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode7isStartMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode8localRefMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode9__T4codeZ4codeMxFNaNbNdNiNfZE3std5regex8internal2ir2IR@Base 6
+ _D3std5regex8internal2ir8Bytecode9__T4dataZ4dataMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir8hasMergeFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8isAtomIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8pairedIRFE3std5regex8internal2ir2IRZE3std5regex8internal2ir2IR@Base 6
+ _D3std5regex8internal2ir8wordTrieFNdZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir9RegexInfo6__initZ@Base 6
+ _D3std5regex8internal2ir9isStartIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir9trieCacheHS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal5tests12__ModuleInfoZ@Base 6
+ _D3std5regex8internal6parser11caseEncloseFNaS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser12__ModuleInfoZ@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack11__xopEqualsFKxS3std5regex8internal6parser12__T5StackTkZ5StackKxS3std5regex8internal6parser12__T5StackTkZ5StackZb@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack3popMFNbNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack3topMFNaNbNcNdNiNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack4pushMFNaNbNekZv@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser12__T5StackTkZ5StackZk@Base 6
+ _D3std5regex8internal6parser13getUnicodeSetFNexAabbZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser10parseRegexMFNeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11__xopEqualsFKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11charsetToIrMFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11isOpenGroupMFNaNbNiNfkZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11markBackrefMFNaNbNfkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11parseEscapeMFNeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ101__T11unrollWhileS813std10functional54__T8unaryFunVAyaa12_61203d3d20612e556e696f6eVAyaa1_61Z8unaryFunZ11unrollWhileFNfKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ5applyFNfE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ99__T11unrollWhileS793std10functional52__T8unaryFunVAyaa11_6120213d20612e4f70656eVAyaa1_61Z8unaryFunZ11unrollWhileFNfKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseDecimalMFNfZk@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13fixLookaroundMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13genLookaroundMFE3std5regex8internal2ir2IRZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ12addWithFlagsFNaNbKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListkkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ18twinSymbolOperatorFNaNbNiNfwZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser15__T6__ctorTAxaZ6__ctorMFNcNeAyaAxaZS3std5regex8internal6parser15__T6ParserTAyaZ6Parser@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser15parseQuantifierMFNekZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser16parseControlCodeMFNaNfZw@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser17finishAlternationMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser20__T10parseFlagsTAxaZ10parseFlagsMFNeAxaZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser24parseUnicodePropertySpecMFNfbZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser3putMFNaNfS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser4nextMFNaNfZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser5_nextMFNaNfZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser5errorMFNeAyaZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser6__initZ@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser6putRawMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser7currentMFNaNbNdNiNfZw@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser7programMFNdNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9__xtoHashFNbNeKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZk@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9parseAtomMFZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9skipSpaceMFNaNfZv@Base 6
+ _D3std5regex8internal6parser18__T9makeRegexTAyaZ9makeRegexFNfS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex8internal6parser20__T11parseUniHexTyaZ11parseUniHexFNaNfKAyakZw@Base 6
+ _D3std5regex8internal6parser21__T15reverseBytecodeZ15reverseBytecodeFNeAS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack11__xopEqualsFKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackZb@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack3popMFNaNbNiNfZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack3topMFNaNbNcNdNiNfZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack4pushMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack6__initZ@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack9__xtoHashFNbNeKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZv@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack11__xopEqualsFKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackZb@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack3popMFNbNeZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack3topMFNaNbNcNdNiNeZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack4pushMFNaNbNeS3std8typecons16__T5TupleTkTkTkZ5TupleZv@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackZk@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack11__xopEqualsFKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack3popMFNbNeZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack3topMFNaNbNcNdNiNeZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack4pushMFNaNbNeE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZv@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZk@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack11__xopEqualsFKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZb@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack3popMFNbNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack3topMFNaNbNcNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack4pushMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZv@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZk@Base 6
+ _D3std5regex8internal6parser7getTrieFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal6parser9trieCacheHS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal8thompson12__ModuleInfoZ@Base 6
+ _D3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList10insertBackMFNaNbNiNfPS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange5frontMFNaNbNdNiNfZPxS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange6__ctorMFNaNbNcNiNfS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadListZS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange8popFrontMFNaNbNdNiNfZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11insertFrontMFNaNbNiNfPS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList5fetchMFNaNbNiNfZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList7opSliceMFNaNbNiNfZS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11__xopEqualsFKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11createStartMFNaNbNiNekkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher12matchOneShotMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupkZE3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11MatchResult@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13__T4evalVbi0Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13__T4evalVbi1Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13getThreadSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher15prepareFreeListMFNaNbNiNekKAvZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher16__T10bwdMatcherZ10bwdMatcherMFNaNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher16__T10fwdMatcherZ10fwdMatcherMFNaNbNiNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18__T9matchImplVbi0Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18__T9matchImplVbi1Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher4forkMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadkkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher4nextMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher55__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5InputZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5InputZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5atEndMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher67__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5InputZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6finishMFNaNbNiNePxS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6searchMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7recycleMFNaNbNiNeKS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadListZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7recycleMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher8allocateMFNaNbNiNeZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher9__xtoHashFNbNeKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherZk@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11__xopEqualsFKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11createStartMFNaNbNiNekkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher12matchOneShotMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupkZE3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11MatchResult@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13__T4evalVbi0Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13__T4evalVbi1Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13getThreadSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher15prepareFreeListMFNaNbNiNekKAvZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher16__T10bwdMatcherZ10bwdMatcherMFNaNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher16__T10fwdMatcherZ10fwdMatcherMFNaNbNiNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher18__T9matchImplVbi0Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher4forkMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadkkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher4nextMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher55__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5InputZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5atEndMFNaNdNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher67__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6__initZ@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6finishMFNaNbNiNePxS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7recycleMFNaNbNiNeKS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadListZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7recycleMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher8allocateMFNaNbNiNeZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher9__xtoHashFNbNeKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherZk@Base 6
+ _D3std5regex8internal9generator12__ModuleInfoZ@Base 6
+ _D3std5regex8internal9kickstart12__ModuleInfoZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread105__T3setS94_D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread10setInvMaskMFNaNbNiNfkkZvZ3setMFNaNfwZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread10setInvMaskMFNaNbNiNfkkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread11__xopEqualsFKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread3addMFNaNfwZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread4fullMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__ctorMFNaNbNcNiNfkkAkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread7advanceMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread7setMaskMFNaNbNiNfkkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread9__xtoHashFNbNeKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11__xopEqualsFKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr4forkFNaNbNiNfS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadkkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr5fetchFNbNeKAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__ctorMFNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexAkZ10codeBoundsyAi@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__ctorMFNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexAkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6searchMFNaNeAxakZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr7charLenFNaNbNiNfkZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr9__xtoHashFNbNeKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZk@Base 6
+ _D3std5regex8internal9kickstart21__T13effectiveSizeTaZ13effectiveSizeFNaNbNiNfZk@Base 6
+ _D3std5stdio10ChunksImpl11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio10ChunksImpl11__xopEqualsFKxS3std5stdio10ChunksImplKxS3std5stdio10ChunksImplZb@Base 6
+ _D3std5stdio10ChunksImpl15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio10ChunksImpl6__ctorMFNcS3std5stdio4FilekZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio10ChunksImpl6__initZ@Base 6
+ _D3std5stdio10ChunksImpl8opAssignMFNcNjNeS3std5stdio10ChunksImplZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio10ChunksImpl9__xtoHashFNbNeKxS3std5stdio10ChunksImplZk@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZ1nk@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZ7lineptrPa@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZk@Base 6
+ _D3std5stdio11openNetworkFAyatZS3std5stdio4File@Base 6
+ _D3std5stdio12__ModuleInfoZ@Base 6
+ _D3std5stdio13trustedStdoutFNdNeZS3std5stdio4File@Base 6
+ _D3std5stdio14StdioException6__ctorMFAyakZC3std5stdio14StdioException@Base 6
+ _D3std5stdio14StdioException6__initZ@Base 6
+ _D3std5stdio14StdioException6__vtblZ@Base 6
+ _D3std5stdio14StdioException6opCallFAyaZv@Base 6
+ _D3std5stdio14StdioException6opCallFZv@Base 6
+ _D3std5stdio14StdioException7__ClassZ@Base 6
+ _D3std5stdio17LockingTextReader10__aggrDtorMFZv@Base 6
+ _D3std5stdio17LockingTextReader10__postblitMFZv@Base 6
+ _D3std5stdio17LockingTextReader11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio17LockingTextReader11__xopEqualsFKxS3std5stdio17LockingTextReaderKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std5stdio17LockingTextReader14__aggrPostblitMFZv@Base 6
+ _D3std5stdio17LockingTextReader15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio17LockingTextReader5emptyMFNdZb@Base 6
+ _D3std5stdio17LockingTextReader5frontMFNdZw@Base 6
+ _D3std5stdio17LockingTextReader6__ctorMFNcS3std5stdio4FileZS3std5stdio17LockingTextReader@Base 6
+ _D3std5stdio17LockingTextReader6__dtorMFZv@Base 6
+ _D3std5stdio17LockingTextReader6__initZ@Base 6
+ _D3std5stdio17LockingTextReader8opAssignMFS3std5stdio17LockingTextReaderZv@Base 6
+ _D3std5stdio17LockingTextReader8popFrontMFZv@Base 6
+ _D3std5stdio17LockingTextReader9__xtoHashFNbNeKxS3std5stdio17LockingTextReaderZk@Base 6
+ _D3std5stdio17LockingTextReader9readFrontMFZv@Base 6
+ _D3std5stdio17LockingTextReader9takeFrontMFNkKG4aZAa@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ10stderrImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ10stdoutImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ9stdinImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio4File10__postblitMFNbNfZv@Base 6
+ _D3std5stdio4File11__xopEqualsFKxS3std5stdio4FileKxS3std5stdio4FileZb@Base 6
+ _D3std5stdio4File13__T6readlnTaZ6readlnMFKAawZk@Base 6
+ _D3std5stdio4File14__T7rawReadTaZ7rawReadMFAaZAa@Base 6
+ _D3std5stdio4File14__T7rawReadTbZ7rawReadMFAbZAb@Base 6
+ _D3std5stdio4File14__T7rawReadThZ7rawReadMFAhZAh@Base 6
+ _D3std5stdio4File14__T7rawReadTiZ7rawReadMFAiZAi@Base 6
+ _D3std5stdio4File14__T7rawReadTlZ7rawReadMFAlZAl@Base 6
+ _D3std5stdio4File15__T6readlnTAyaZ6readlnMFwZAya@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNbNiNfaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNfaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNfaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNbNiNfwZv@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNfwZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNfwZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__postblitMFNeZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTAaZ3putMFAaZ13trustedFwriteFNbNiNexPvkkPOS4core4stdc5stdio8_IO_FILEZk@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTAaZ3putMFNfAaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNbNiNfxaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNfxaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNfxaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNbNiNfxwZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNfxwZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNfxwZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNbNiNfyaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNfyaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNfyaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAxaZ3putMFAxaZ13trustedFwriteFNbNiNexPvkkPOS4core4stdc5stdio8_IO_FILEZk@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAxaZ3putMFNfAxaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAyaZ3putMFAyaZ13trustedFwriteFNbNiNexPvkkPOS4core4stdc5stdio8_IO_FILEZk@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAyaZ3putMFNfAyaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter6__ctorMFNcNeKS3std5stdio4FileZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File17LockingTextWriter6__dtorMFNeZv@Base 6
+ _D3std5stdio4File17LockingTextWriter6__initZ@Base 6
+ _D3std5stdio4File17LockingTextWriter8opAssignMFNcNjNeS3std5stdio4File17LockingTextWriterZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File17lockingTextWriterMFNfZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File3eofMxFNaNdNeZb@Base 6
+ _D3std5stdio4File4Impl6__initZ@Base 6
+ _D3std5stdio4File4lockMFE3std5stdio8LockTypemmZv@Base 6
+ _D3std5stdio4File4nameMxFNaNbNdNfZAya@Base 6
+ _D3std5stdio4File4openMFNfAyaxAaZv@Base 6
+ _D3std5stdio4File4seekMFNeliZv@Base 6
+ _D3std5stdio4File4sizeMFNdNfZm@Base 6
+ _D3std5stdio4File4syncMFNeZv@Base 6
+ _D3std5stdio4File4tellMxFNdNeZm@Base 6
+ _D3std5stdio4File5closeMFNeZv@Base 6
+ _D3std5stdio4File5errorMxFNaNbNdNeZb@Base 6
+ _D3std5stdio4File5flushMFNeZv@Base 6
+ _D3std5stdio4File5getFPMFNaNfZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio4File5popenMFNfAyaxAaZv@Base 6
+ _D3std5stdio4File6__ctorMFNcNePOS4core4stdc5stdio8_IO_FILEAyakbZS3std5stdio4File@Base 6
+ _D3std5stdio4File6__ctorMFNcNfAyaxAaZS3std5stdio4File@Base 6
+ _D3std5stdio4File6__dtorMFNfZv@Base 6
+ _D3std5stdio4File6__initZ@Base 6
+ _D3std5stdio4File6detachMFNfZv@Base 6
+ _D3std5stdio4File6fdopenMFNeixAaAyaZv@Base 6
+ _D3std5stdio4File6fdopenMFNfixAaZv@Base 6
+ _D3std5stdio4File6filenoMxFNdNeZi@Base 6
+ _D3std5stdio4File6isOpenMxFNaNbNdNfZb@Base 6
+ _D3std5stdio4File6rewindMFNfZv@Base 6
+ _D3std5stdio4File6unlockMFmmZv@Base 6
+ _D3std5stdio4File7ByChunk11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio4File7ByChunk11__xopEqualsFKxS3std5stdio4File7ByChunkKxS3std5stdio4File7ByChunkZb@Base 6
+ _D3std5stdio4File7ByChunk15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio4File7ByChunk5emptyMxFNbNdZb@Base 6
+ _D3std5stdio4File7ByChunk5frontMFNbNdZAh@Base 6
+ _D3std5stdio4File7ByChunk5primeMFZv@Base 6
+ _D3std5stdio4File7ByChunk6__ctorMFNcS3std5stdio4FileAhZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk6__ctorMFNcS3std5stdio4FilekZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk6__initZ@Base 6
+ _D3std5stdio4File7ByChunk8opAssignMFNcNjNeS3std5stdio4File7ByChunkZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk8popFrontMFZv@Base 6
+ _D3std5stdio4File7ByChunk9__xtoHashFNbNeKxS3std5stdio4File7ByChunkZk@Base 6
+ _D3std5stdio4File7byChunkMFAhZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7byChunkMFkZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7setvbufMFNeAviZv@Base 6
+ _D3std5stdio4File7setvbufMFNekiZv@Base 6
+ _D3std5stdio4File7tmpfileFNfZS3std5stdio4File@Base 6
+ _D3std5stdio4File7tryLockMFE3std5stdio8LockTypemmZb@Base 6
+ _D3std5stdio4File8clearerrMFNaNbNfZv@Base 6
+ _D3std5stdio4File8lockImplMFismmZi@Base 6
+ _D3std5stdio4File8opAssignMFNfS3std5stdio4FileZv@Base 6
+ _D3std5stdio4File8wrapFileFNfPOS4core4stdc5stdio8_IO_FILEZS3std5stdio4File@Base 6
+ _D3std5stdio4File9__xtoHashFNbNeKxS3std5stdio4FileZk@Base 6
+ _D3std5stdio5fopenFNbNiNexAaxAaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio5lines11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio5lines11__xopEqualsFKxS3std5stdio5linesKxS3std5stdio5linesZb@Base 6
+ _D3std5stdio5lines15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio5lines6__ctorMFNcS3std5stdio4FilewZS3std5stdio5lines@Base 6
+ _D3std5stdio5lines6__initZ@Base 6
+ _D3std5stdio5lines8opAssignMFNcNjNeS3std5stdio5linesZS3std5stdio5lines@Base 6
+ _D3std5stdio5lines9__xtoHashFNbNeKxS3std5stdio5linesZk@Base 6
+ _D3std5stdio5popenFNbNiNexAaxAaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio5stdinS3std5stdio4File@Base 6
+ _D3std5stdio6chunksFS3std5stdio4FilekZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio6stderrS3std5stdio4File@Base 6
+ _D3std5stdio6stdoutS3std5stdio4File@Base 6
+ _D3std6base6412__ModuleInfoZ@Base 6
+ _D3std6base6415Base64Exception6__ctorMFNaNbNfAyaAyakZC3std6base6415Base64Exception@Base 6
+ _D3std6base6415Base64Exception6__initZ@Base 6
+ _D3std6base6415Base64Exception6__vtblZ@Base 6
+ _D3std6base6415Base64Exception7__ClassZ@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z12decodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z12encodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z9DecodeMapyG256i@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z9EncodeMapyAa@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z12decodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z12encodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z9DecodeMapyG256i@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z9EncodeMapyAa@Base 6
+ _D3std6bigint12__ModuleInfoZ@Base 6
+ _D3std6bigint15toDecimalStringFxS3std6bigint6BigIntZAya@Base 6
+ _D3std6bigint5toHexFxS3std6bigint6BigIntZAya@Base 6
+ _D3std6bigint6BigInt10isNegativeMxFNaNbNiNfZb@Base 6
+ _D3std6bigint6BigInt10uintLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std6bigint6BigInt11__xopEqualsFKxS3std6bigint6BigIntKxS3std6bigint6BigIntZb@Base 6
+ _D3std6bigint6BigInt11ulongLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std6bigint6BigInt13__T8opEqualsZ8opEqualsMxFNaNbNiNfKxS3std6bigint6BigIntZb@Base 6
+ _D3std6bigint6BigInt14checkDivByZeroMxFNaNbNfZv@Base 6
+ _D3std6bigint6BigInt31__T5opCmpHTS3std6bigint6BigIntZ5opCmpMxFNaNbNiNfxS3std6bigint6BigIntZi@Base 6
+ _D3std6bigint6BigInt5opCmpMxFNaNbNiKxS3std6bigint6BigIntZi@Base 6
+ _D3std6bigint6BigInt5toIntMxFNaNbNiNfZi@Base 6
+ _D3std6bigint6BigInt6__initZ@Base 6
+ _D3std6bigint6BigInt6isZeroMxFNaNbNiNfZb@Base 6
+ _D3std6bigint6BigInt6negateMFNaNbNiNfZv@Base 6
+ _D3std6bigint6BigInt6toHashMxFNbNfZk@Base 6
+ _D3std6bigint6BigInt6toLongMxFNaNbNiNfZl@Base 6
+ _D3std6bigint6BigInt8toStringMxFMDFAxaZvAyaZv@Base 6
+ _D3std6bigint6BigInt8toStringMxFMDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6digest2md10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest2md12__ModuleInfoZ@Base 6
+ _D3std6digest2md3MD51FFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD52FFFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52GGFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52HHFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52IIFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD53putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest2md3MD55startMFNaNbNiNfZv@Base 6
+ _D3std6digest2md3MD56__initZ@Base 6
+ _D3std6digest2md3MD56finishMFNaNbNiNeZG16h@Base 6
+ _D3std6digest2md3MD58_paddingyG64h@Base 6
+ _D3std6digest2md3MD59transformMFNaNbNiPxG64hZv@Base 6
+ _D3std6digest3crc11crc32_tableyG256k@Base 6
+ _D3std6digest3crc12__ModuleInfoZ@Base 6
+ _D3std6digest3crc5CRC323putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3crc5CRC324peekMxFNaNbNiNfZG4h@Base 6
+ _D3std6digest3crc5CRC325startMFNaNbNiNfZv@Base 6
+ _D3std6digest3crc5CRC326__initZ@Base 6
+ _D3std6digest3crc5CRC326finishMFNaNbNiNfZG4h@Base 6
+ _D3std6digest3sha10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest3sha11rotateRightFNaNbNiNfkkZk@Base 6
+ _D3std6digest3sha11rotateRightFNaNbNiNfmkZm@Base 6
+ _D3std6digest3sha12__ModuleInfoZ@Base 6
+ _D3std6digest3sha17bigEndianToNativeFNaNbNiNeG4hZk@Base 6
+ _D3std6digest3sha17bigEndianToNativeFNaNbNiNeG8hZm@Base 6
+ _D3std6digest3sha17nativeToBigEndianFNaNbNiNekZG4h@Base 6
+ _D3std6digest3sha17nativeToBigEndianFNaNbNiNemZG8h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6finishMFNaNbNiNeZG20h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6finishMFNaNbNiNeZG48h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6finishMFNaNbNiNeZG64h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9constantsyG80m@Base 6
+ _D3std6digest6digest12__ModuleInfoZ@Base 6
+ _D3std6digest6digest18__T7asArrayVki4ThZ7asArrayFNaNbNcNiKAhAyaZG4h@Base 6
+ _D3std6digest6digest19__T7asArrayVki16ThZ7asArrayFNaNbNcNiKAhAyaZG16h@Base 6
+ _D3std6digest6digest19__T7asArrayVki20ThZ7asArrayFNaNbNcNiKAhAyaZG20h@Base 6
+ _D3std6digest6digest19__T7asArrayVki28ThZ7asArrayFNaNbNcNiKAhAyaZG28h@Base 6
+ _D3std6digest6digest19__T7asArrayVki32ThZ7asArrayFNaNbNcNiKAhAyaZG32h@Base 6
+ _D3std6digest6digest19__T7asArrayVki48ThZ7asArrayFNaNbNcNiKAhAyaZG48h@Base 6
+ _D3std6digest6digest19__T7asArrayVki64ThZ7asArrayFNaNbNcNiKAhAyaZG64h@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest6Digest11__InterfaceZ@Base 6
+ _D3std6digest6digest6Digest6digestMFNbNeMAxAvXAh@Base 6
+ _D3std6digest6digest71__T11toHexStringVE3std6digest6digest5Orderi1VE3std5ascii10LetterCasei0Z11toHexStringFNaNbxAhZAya@Base 6
+ _D3std6digest6digest76__T11toHexStringVE3std6digest6digest5Orderi1Vki16VE3std5ascii10LetterCasei0Z11toHexStringFNaNbNiNfxG16hZG32a@Base 6
+ _D3std6digest6ripemd10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest6ripemd12__ModuleInfoZ@Base 6
+ _D3std6digest6ripemd9RIPEMD1601FFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601JFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1602FFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602GGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602HHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602IIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602JJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603FFFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603GGGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603HHHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603IIIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603JJJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest6ripemd9RIPEMD1605startMFNaNbNiNfZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1606__initZ@Base 6
+ _D3std6digest6ripemd9RIPEMD1606finishMFNaNbNiNeZG20h@Base 6
+ _D3std6digest6ripemd9RIPEMD1608_paddingyG64h@Base 6
+ _D3std6digest6ripemd9RIPEMD1609transformMFNaNbNiPxG64hZv@Base 6
+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckbAyaAyaE3std3net7isemail15EmailStatusCodeZv@Base 6
+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckbAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZk@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda13FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda15FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda17FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda14TkZ10__lambda14FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda16TkZ10__lambda16FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda18TkZ10__lambda18FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ19__T10__lambda10TykZ10__lambda10FNaNbNiNeKykZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ19__T10__lambda12TykZ10__lambda12FNaNbNiNeKykZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZk@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T9__lambda9TbZ9__lambda9FNaNbNiNeKbZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ20__T10__lambda11TAyaZ10__lambda11FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ20__T10__lambda13TAyaZ10__lambda13FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ51__T10__lambda15TE3std3net7isemail15EmailStatusCodeZ10__lambda15FNaNbNiNeKE3std3net7isemail15EmailStatusCodeZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format111__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std3net4curl20AsyncChunkInputRange8__mixin55StateKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format113__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format117__T6formatTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6formatFNaNfxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZAya@Base 6
+ _D3std6format118__T9getNthIntTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9getNthIntFNaNfkE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std6format12__ModuleInfoZ@Base 6
+ _D3std6format137__T22enforceValidFormatSpecTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoPaZ6skipCIFNaNbNiNfC8TypeInfoZC8TypeInfo@Base 6
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoPaZ9formatArgMFaZ6getManFNaNbNiNfC8TypeInfoZE3std6format6Mangle@Base 6
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoPaZv@Base 6
+ _D3std6format14__T9getNthIntZ9getNthIntFNaNfkZi@Base 6
+ _D3std6format15FormatException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6format15FormatException@Base 6
+ _D3std6format15FormatException6__ctorMFNaNbNfZC3std6format15FormatException@Base 6
+ _D3std6format15FormatException6__initZ@Base 6
+ _D3std6format15FormatException6__vtblZ@Base 6
+ _D3std6format15FormatException7__ClassZ@Base 6
+ _D3std6format15__T6formatTaTiZ6formatFNaNfxAaiZAya@Base 6
+ _D3std6format15__T6formatTaTkZ6formatFNaNfxAakZAya@Base 6
+ _D3std6format15__T6formatTaTwZ6formatFNaNfxAawZAya@Base 6
+ _D3std6format160__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZv@Base 6
+ _D3std6format160__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format166__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZk@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ66__T9__lambda7TE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda7FNaNbNiNeKE3std3net4curl20AsyncChunkInputRange8__mixin55StateZxPv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ66__T9__lambda9TE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda9FNaNbNiNeKE3std3net4curl20AsyncChunkInputRange8__mixin55StateZxPv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format167__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format16__T6formatTaTxsZ6formatFNaNfxAaxsZAya@Base 6
+ _D3std6format16__T9getNthIntTaZ9getNthIntFNaNfkaZi@Base 6
+ _D3std6format16__T9getNthIntTiZ9getNthIntFNaNfkiZi@Base 6
+ _D3std6format16__T9getNthIntTkZ9getNthIntFNaNfkkZi@Base 6
+ _D3std6format16__T9getNthIntTtZ9getNthIntFNaNfktZi@Base 6
+ _D3std6format16__T9getNthIntTwZ9getNthIntFNaNfkwZi@Base 6
+ _D3std6format17__T6formatTaTAyaZ6formatFNaNfxAaAyaZAya@Base 6
+ _D3std6format17__T6formatTaTiTiZ6formatFNaNfxAaiiZAya@Base 6
+ _D3std6format17__T6formatTaTkTkZ6formatFNaNfxAakkZAya@Base 6
+ _D3std6format17__T9getNthIntTPvZ9getNthIntFNaNfkPvZi@Base 6
+ _D3std6format17__T9getNthIntTxhZ9getNthIntFNaNfkxhZi@Base 6
+ _D3std6format17__T9getNthIntTxkZ9getNthIntFNaNfkxkZi@Base 6
+ _D3std6format17__T9getNthIntTxsZ9getNthIntFNaNfkxsZi@Base 6
+ _D3std6format17primitiveTypeInfoFE3std6format6MangleZ3dicHE3std6format6MangleC8TypeInfo@Base 6
+ _D3std6format17primitiveTypeInfoFE3std6format6MangleZC8TypeInfo@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec11__xopEqualsFKxS3std6format18__T10FormatSpecTaZ10FormatSpecKxS3std6format18__T10FormatSpecTaZ10FormatSpecZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec12getCurFmtStrMxFNaNfZAya@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec16headUpToNextSpecMFNaZAxa@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec31__T17writeUpToNextSpecTDFAxaZvZ17writeUpToNextSpecMFDFAxaZvZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec37__T17writeUpToNextSpecTDFNaNbNfAxaZvZ17writeUpToNextSpecMFNaNfDFNaNbNfAxaZvZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec59__T17writeUpToNextSpecTS3std5stdio4File17LockingTextWriterZ17writeUpToNextSpecMFNfS3std5stdio4File17LockingTextWriterZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec63__T17writeUpToNextSpecTS3std5array17__T8AppenderTAyaZ8AppenderZ17writeUpToNextSpecMFNaNfS3std5array17__T8AppenderTAyaZ8AppenderZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec63__T17writeUpToNextSpecTS3std5array17__T8AppenderTyAaZ8AppenderZ17writeUpToNextSpecMFNaNfS3std5array17__T8AppenderTyAaZ8AppenderZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6__ctorMFNaNbNcNiNfxAaZS3std6format18__T10FormatSpecTaZ10FormatSpec@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6__initZ@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6fillUpMFNaNfZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flDashMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flDashMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flHashMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flHashMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flPlusMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flPlusMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flZeroMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flZeroMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec7flSpaceMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec7flSpaceMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec8toStringMFNaNfZAya@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec91__T17writeUpToNextSpecTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkZ17writeUpToNextSpecMFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec9__xtoHashFNbNeKxS3std6format18__T10FormatSpecTaZ10FormatSpecZk@Base 6
+ _D3std6format18__T6formatTaTAyAaZ6formatFNaNfxAaAyAaZAya@Base 6
+ _D3std6format18__T9getNthIntTAxaZ9getNthIntFNaNfkAxaZi@Base 6
+ _D3std6format18__T9getNthIntTAyaZ9getNthIntFNaNfkAyaZi@Base 6
+ _D3std6format18__T9getNthIntThTiZ9getNthIntFNaNfkhiZi@Base 6
+ _D3std6format18__T9getNthIntTiTiZ9getNthIntFNaNfkiiZi@Base 6
+ _D3std6format18__T9getNthIntTkTkZ9getNthIntFNaNfkkkZi@Base 6
+ _D3std6format18__T9getNthIntTtTtZ9getNthIntFNaNfkttZi@Base 6
+ _D3std6format18__T9getNthIntTwTkZ9getNthIntFNaNfkwkZi@Base 6
+ _D3std6format19__T6formatTaTAaTPvZ6formatFNaNfxAaAaPvZAya@Base 6
+ _D3std6format19__T6formatTaTAyaTkZ6formatFNaNfxAaAyakZAya@Base 6
+ _D3std6format19__T6formatTaTxkTxkZ6formatFNaNfxAaxkxkZAya@Base 6
+ _D3std6format19__T9getNthIntTAyAaZ9getNthIntFNaNfkAyAaZi@Base 6
+ _D3std6format20__T9getNthIntTAaTPvZ9getNthIntFNaNfkAaPvZi@Base 6
+ _D3std6format20__T9getNthIntTAxhTaZ9getNthIntFNaNfkAxhaZi@Base 6
+ _D3std6format20__T9getNthIntTAyaTiZ9getNthIntFNaNfkAyaiZi@Base 6
+ _D3std6format20__T9getNthIntTAyaTkZ9getNthIntFNaNfkAyakZi@Base 6
+ _D3std6format20__T9getNthIntThThTiZ9getNthIntFNaNfkhhiZi@Base 6
+ _D3std6format20__T9getNthIntTkTAyaZ9getNthIntFNaNfkkAyaZi@Base 6
+ _D3std6format20__T9getNthIntTkTkTkZ9getNthIntFNaNfkkkkZi@Base 6
+ _D3std6format20__T9getNthIntTwTkTkZ9getNthIntFNaNfkwkkZi@Base 6
+ _D3std6format20__T9getNthIntTxhTxhZ9getNthIntFNaNfkxhxhZi@Base 6
+ _D3std6format20__T9getNthIntTxkTxkZ9getNthIntFNaNfkxkxkZi@Base 6
+ _D3std6format21__T6formatTaTAxaTAxaZ6formatFNaNfxAaAxaAxaZAya@Base 6
+ _D3std6format21__T6formatTaTAyaTAyaZ6formatFNaNfxAaAyaAyaZAya@Base 6
+ _D3std6format21__T6formatTaTAyaTkTkZ6formatFNaNfxAaAyakkZAya@Base 6
+ _D3std6format21__T9getNthIntTAyaTxhZ9getNthIntFNaNfkAyaxhZi@Base 6
+ _D3std6format22__T6formatTaTxhTxhTxhZ6formatFNaNfxAaxhxhxhZAya@Base 6
+ _D3std6format22__T9getNthIntTAxaTAxaZ9getNthIntFNaNfkAxaAxaZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTAyaZ9getNthIntFNaNfkAyaAyaZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTkTkZ9getNthIntFNaNfkAyakkZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTtTtZ9getNthIntFNaNfkAyattZi@Base 6
+ _D3std6format22__T9getNthIntThThThTiZ9getNthIntFNaNfkhhhiZi@Base 6
+ _D3std6format23__T6formatTaTAyaTAyaTkZ6formatFNaNfxAaAyaAyakZAya@Base 6
+ _D3std6format23__T6formatTaTAyaTkTAyaZ6formatFNaNfxAaAyakAyaZAya@Base 6
+ _D3std6format23__T6formatTaTtTAyaTtTtZ6formatFNaNfxAatAyattZAya@Base 6
+ _D3std6format23__T6formatTaTxsTAyaTxhZ6formatFNaNfxAaxsAyaxhZAya@Base 6
+ _D3std6format23__T9getNthIntTxhTxhTxhZ9getNthIntFNaNfkxhxhxhZi@Base 6
+ _D3std6format23__T9getNthIntTxkTxkTxkZ9getNthIntFNaNfkxkxkxkZi@Base 6
+ _D3std6format23__T9getNthIntTykTkTkTkZ9getNthIntFNaNfkykkkkZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTAyaTiZ9getNthIntFNaNfkAyaAyaiZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTAyaTkZ9getNthIntFNaNfkAyaAyakZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTkTAyaZ9getNthIntFNaNfkAyakAyaZi@Base 6
+ _D3std6format24__T9getNthIntThThThThTiZ9getNthIntFNaNfkhhhhiZi@Base 6
+ _D3std6format24__T9getNthIntTkTAyaTAyaZ9getNthIntFNaNfkkAyaAyaZi@Base 6
+ _D3std6format24__T9getNthIntTtTAyaTtTtZ9getNthIntFNaNfktAyattZi@Base 6
+ _D3std6format24__T9getNthIntTxsTAyaTxhZ9getNthIntFNaNfkxsAyaxhZi@Base 6
+ _D3std6format25__T6formatTaTAyaTAyaTAyaZ6formatFNaNfxAaAyaAyaAyaZAya@Base 6
+ _D3std6format25__T6formatTaTxhTxhTxhTxhZ6formatFNaNfxAaxhxhxhxhZAya@Base 6
+ _D3std6format25__T9getNthIntTkTxkTxkTxkZ9getNthIntFNaNfkkxkxkxkZi@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNbNfAxaZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfAxuZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfAxwZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfwZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink6__initZ@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFNaNfAaxAaykykkkkZAa@Base 6
+ _D3std6format26__T9getNthIntTAyaTAyaTAyaZ9getNthIntFNaNfkAyaAyaAyaZi@Base 6
+ _D3std6format26__T9getNthIntTxhTxhTxhTxhZ9getNthIntFNaNfkxhxhxhxhZi@Base 6
+ _D3std6format26__T9getNthIntTykTykTkTkTkZ9getNthIntFNaNfkykykkkkZi@Base 6
+ _D3std6format28__T9getNthIntTAyaTkTAyaTAyaZ9getNthIntFNaNfkAyakAyaAyaZi@Base 6
+ _D3std6format29__T11formatValueTDFAxaZvTkTaZ11formatValueFDFAxaZvkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format29__T11formatValueTDFAxaZvTkTaZ11formatValueFDFAxaZvkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxeTaZ11formatValueFDFAxaZvxeKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxeZ9__lambda4FNaNbNiNeKxeZAxa@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxeTaZ11formatValueFDFAxaZvxeKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxmTaZ11formatValueFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxmZ9__lambda4FNaNbNiNeKxmZAxa@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxmTaZ11formatValueFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T9getNthIntTkTAyaTkTAyaTAyaZ9getNthIntFNaNfkkAyakAyaAyaZi@Base 6
+ _D3std6format32__T14formatIntegralTDFAxaZvTmTaZ14formatIntegralFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format32__T14formatUnsignedTDFAxaZvTmTaZ14formatUnsignedFDFAxaZvmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format34__T6formatTaTE3std8datetime5MonthZ6formatFNaNfxAaE3std8datetime5MonthZAya@Base 6
+ _D3std6format34__T9getNthIntTAyaTkTAyaTkTAyaTAyaZ9getNthIntFNaNfkAyakAyakAyaAyaZi@Base 6
+ _D3std6format35__T9getNthIntTE3std8datetime5MonthZ9getNthIntFNaNfkE3std8datetime5MonthZi@Base 6
+ _D3std6format36__T11formatValueTDFNaNbNfAxaZvTyhTaZ11formatValueFDFNaNbNfAxaZvyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TyhZ9__lambda4FNaNbNiNeKyhZAxa@Base 6
+ _D3std6format36__T11formatValueTDFNaNbNfAxaZvTyhTaZ11formatValueFNaNfDFNaNbNfAxaZvyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format36__T9getNthIntTkTAyaTkTAyaTkTAyaTAyaZ9getNthIntFNaNfkkAyakAyakAyaAyaZi@Base 6
+ _D3std6format37__T11formatRangeTDFNaNbNfAxaZvTAyhTaZ11formatRangeFNaNfKDFNaNbNfAxaZvKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format37__T11formatValueTDFNaNbNfAxaZvTAyhTaZ11formatValueFNaNfDFNaNbNfAxaZvAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format37__T9getNthIntTE3std8datetime5MonthTiZ9getNthIntFNaNfkE3std8datetime5MonthiZi@Base 6
+ _D3std6format38__T13formatElementTDFNaNbNfAxaZvTyhTaZ13formatElementFNaNfDFNaNbNfAxaZvKyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format38__T14formatIntegralTDFNaNbNfAxaZvTmTaZ14formatIntegralFNaNbNfDFNaNbNfAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format38__T14formatUnsignedTDFNaNbNfAxaZvTmTaZ14formatUnsignedFNaNbNfDFNaNbNfAxaZvmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format38__T6formatTaTiTE3std8datetime5MonthTiZ6formatFNaNfxAaiE3std8datetime5MonthiZAya@Base 6
+ _D3std6format39__T13formatElementTDFNaNbNfAxaZvTAyhTaZ13formatElementFNaNfDFNaNbNfAxaZvKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format39__T9getNthIntTiTE3std8datetime5MonthTiZ9getNthIntFNaNfkiE3std8datetime5MonthiZi@Base 6
+ _D3std6format39__T9getNthIntTxE3std8datetime5MonthTxhZ9getNthIntFNaNfkxE3std8datetime5MonthxhZi@Base 6
+ _D3std6format41__T6formatTaTxsTxE3std8datetime5MonthTxhZ6formatFNaNfxAaxsxE3std8datetime5MonthxhZAya@Base 6
+ _D3std6format42__T9getNthIntTxsTxE3std8datetime5MonthTxhZ9getNthIntFNaNfkxsxE3std8datetime5MonthxhZi@Base 6
+ _D3std6format45__T9getNthIntTE3std8datetime5MonthThThThThTiZ9getNthIntFNaNfkE3std8datetime5MonthhhhhiZi@Base 6
+ _D3std6format46__T9getNthIntTPC3std11concurrency10MessageBoxZ9getNthIntFNaNfkPC3std11concurrency10MessageBoxZi@Base 6
+ _D3std6format47__T9getNthIntTsTE3std8datetime5MonthThThThThTiZ9getNthIntFNaNfksE3std8datetime5MonthhhhhiZi@Base 6
+ _D3std6format49__T9getNthIntTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format52__T10formatCharTS3std5stdio4File17LockingTextWriterZ10formatCharFNfS3std5stdio4File17LockingTextWriterxwxaZv@Base 6
+ _D3std6format53__T22enforceValidFormatSpecTS3std11concurrency3TidTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format53__T9getNthIntTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format54__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZv@Base 6
+ _D3std6format54__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T10formatCharTS3std5array17__T8AppenderTAyaZ8AppenderZ10formatCharFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxwxaZv@Base 6
+ _D3std6format56__T10formatCharTS3std5array17__T8AppenderTyAaZ8AppenderZ10formatCharFNaNfS3std5array17__T8AppenderTyAaZ8AppenderxwxaZv@Base 6
+ _D3std6format56__T11formatValueTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ11formatValueFDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format56__T9formatNthTDFAxaZvTaTPC3std11concurrency10MessageBoxZ9formatNthFDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpeckPC3std11concurrency10MessageBoxZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T9formatNthTDFAxaZvTaTPC3std11concurrency10MessageBoxZ9formatNthFDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpeckPC3std11concurrency10MessageBoxZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAxaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAxaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterThTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterThTaZ11formatValueFS3std5stdio4File17LockingTextWriterhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTiTaZ11formatValueFNfS3std5stdio4File17LockingTextWriteriKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTiTaZ11formatValueFS3std5stdio4File17LockingTextWriteriKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTkTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTkTaZ11formatValueFS3std5stdio4File17LockingTextWriterkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTsTaZ11formatValueFNfS3std5stdio4File17LockingTextWritersKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTsTaZ11formatValueFS3std5stdio4File17LockingTextWritersKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TsZ9__lambda4FNaNbNiNeKsZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTwTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T12formatObjectTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ12formatObjectFKDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T9getNthIntTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkAyaAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format58__T11formatValueTS3std5stdio4File17LockingTextWriterTxaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T11formatValueTS3std5stdio4File17LockingTextWriterTyaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriteryaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T13formatElementTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ13formatElementFDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T6formatTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ6formatFNaNfxAabAyaAyaE3std3net7isemail15EmailStatusCodeZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ9formatNthFNaNfS3std5array17__T8AppenderTyAaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ9formatNthFS3std5array17__T8AppenderTyAaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T11formatRangeTS3std5stdio4File17LockingTextWriterTAxaTaZ11formatRangeFNfKS3std5stdio4File17LockingTextWriterKAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatRangeTS3std5stdio4File17LockingTextWriterTAyaTaZ11formatRangeFNfKS3std5stdio4File17LockingTextWriterKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTDFAxaZvTPC3std11concurrency10MessageBoxTaZ11formatValueFDFAxaZvPC3std11concurrency10MessageBoxKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTS3std5stdio4File17LockingTextWriterTAxaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTS3std5stdio4File17LockingTextWriterTAyaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatElementTS3std5stdio4File17LockingTextWriterTwTaZ13formatElementFNfS3std5stdio4File17LockingTextWriterwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterThTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTiTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTkTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTsTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T9getNthIntTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkbAyaAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format60__T14formatIntegralTS3std5stdio4File17LockingTextWriterTlTaZ14formatIntegralFNfS3std5stdio4File17LockingTextWriterxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format60__T14formatIntegralTS3std5stdio4File17LockingTextWriterTmTaZ14formatIntegralFNfS3std5stdio4File17LockingTextWriterxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format60__T14formatUnsignedTS3std5stdio4File17LockingTextWriterTmTaZ14formatUnsignedFNfS3std5stdio4File17LockingTextWritermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAakZk@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiiZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiiZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTbTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderbKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderThTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderThTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppendertKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppendertKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TtZ9__lambda4FNaNbNiNeKtZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderThTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderThTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTiTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTiTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTwTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTDFAxaZvTPC3std11concurrency10MessageBoxTaZ13formatGenericFDFAxaZvPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTS3std5stdio4File17LockingTextWriterTAxaTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTS3std5stdio4File17LockingTextWriterTAyaTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyAaZv@Base 6
+ _D3std6format61__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyAaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPvTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxdTaZ11formatValueFNfS3std5array17__T8AppenderTAyaZ8AppenderxdKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxdTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxdKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxdZ9__lambda4FNaNbNiNeKxdZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxhZ9__lambda4FNaNbNiNeKxhZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxiTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxiTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxiZ9__lambda4FNaNbNiNeKxiZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxkZ9__lambda4FNaNbNiNeKxkZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxmTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxmTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxmZ9__lambda4FNaNbNiNeKxmZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxsKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxsKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxsZ9__lambda4FNaNbNiNeKxsZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TyhZ9__lambda4FNaNbNiNeKyhZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZ46__T9__lambda6TPC3std11concurrency10MessageBoxZ9__lambda6FNaNbNiNeKPC3std11concurrency10MessageBoxZxPv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZ9__lambda5FNaNbNiNeZPFNaNbNfDFAxaZvPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAxaZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAxaZ18__T9__lambda6TAxaZ9__lambda6FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAxaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAyaZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaZ18__T9__lambda6TAyaZ9__lambda6FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAaPvZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAaPvZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxhaZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxhaZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkkZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkkZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkxkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkxkZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaiZv@Base 6
+ _D3std6format62__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaiZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyhTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTyAaZ8AppenderTAyaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTAyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatElementTS3std5array17__T8AppenderTyAaZ8AppenderTwTaZ13formatElementFNaNfS3std5array17__T8AppenderTyAaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTbTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ13formatGenericFNaS3std5array17__T8AppenderTyAaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTPvTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ13formatGenericFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTAyaZ8AppenderTlTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTyAaZ8AppenderTlTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTyAaZ8AppenderTmTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatUnsignedTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ14formatUnsignedFNaNbNfS3std5array17__T8AppenderTAyaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format64__T14formatUnsignedTS3std5array17__T8AppenderTyAaZ8AppenderTmTaZ14formatUnsignedFNaNbNfS3std5array17__T8AppenderTyAaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiZ16__T9__lambda6TiZ9__lambda6FNaNbNiNeKiZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawZ16__T9__lambda6TwZ9__lambda6FNaNbNiNeKwZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTyAaZ8AppenderxAakZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTyAaZ8AppenderxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTyAaZ8AppenderxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaAxaZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaAxaZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakkZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakkZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format65__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZk@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZ17__T9__lambda6TxkZ9__lambda6FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZk@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZ17__T9__lambda6TxsZ9__lambda6FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T22enforceValidFormatSpecTC3std11concurrency14LinkTerminatedTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhZv@Base 6
+ _D3std6format65__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZ18__T9__lambda6TAyaZ9__lambda6FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ16__T9__lambda7TiZ9__lambda7FNaNbNiNeKiZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ16__T9__lambda9TiZ9__lambda9FNaNbNiNeKiZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakkZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ16__T9__lambda7TkZ9__lambda7FNaNbNiNeKkZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawkZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ16__T9__lambda7TwZ9__lambda7FNaNbNiNeKwZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T22enforceValidFormatSpecTC3std11concurrency15OwnerTerminatedTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyakZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyakZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakAyaZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakAyaZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecktAyattZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecktAyattZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsAyaxhZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsAyaxhZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9getNthIntTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9getNthIntFNaNfkE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZk@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZ19__T9__lambda6TAyAaZ9__lambda6FNaNbNiNeKAyAaZxPv@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format67__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkxkxkxkZv@Base 6
+ _D3std6format67__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkxkxkxkZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ17__T9__lambda7TAaZ9__lambda7FNaNbNiNeKAaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ17__T9__lambda9TPvZ9__lambda9FNaNbNiNeKPvZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ16__T9__lambda9TaZ9__lambda9FNaNbNiNeKaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ18__T9__lambda7TAxhZ9__lambda7FNaNbNiNeKAxhZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ18__T9__lambda7TAyaZ9__lambda7FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ16__T9__lambda8TkZ9__lambda8FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ16__T9__lambda8TwZ9__lambda8FNaNbNiNeKwZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ17__T9__lambda7TxkZ9__lambda7FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ17__T9__lambda9TxkZ9__lambda9FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAyaAyaiZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ18__T10__lambda12TiZ10__lambda12FNaNbNiNeKiZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaAyaZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaAyaZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhxhZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhxhZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format6Mangle6__initZ@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ18__T9__lambda7TAxaZ9__lambda7FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ18__T9__lambda9TAxaZ9__lambda9FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ18__T9__lambda7TAyaZ9__lambda7FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ18__T9__lambda9TAyaZ9__lambda9FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZk@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ17__T9__lambda8TxhZ9__lambda8FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ19__T10__lambda10TxhZ10__lambda10FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ20__T10__lambda12TAyaZ10__lambda12FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ16__T9__lambda9TtZ9__lambda9FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ18__T10__lambda13TtZ10__lambda13FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ18__T10__lambda15TtZ10__lambda15FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ20__T10__lambda11TAyaZ10__lambda11FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ17__T9__lambda8TxsZ9__lambda8FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZk@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda11TxkZ10__lambda11FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda13TxkZ10__lambda13FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda15TxkZ10__lambda15FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZk@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ20__T10__lambda12TAyaZ10__lambda12FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZk@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ17__T9__lambda9TxhZ9__lambda9FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda11TxhZ10__lambda11FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda13TxhZ10__lambda13FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda15TxhZ10__lambda15FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkAyakAyakAyaAyaZv@Base 6
+ _D3std6format74__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkAyakAyakAyaAyaZ16__T7gencodeVki7Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format76__T11formatValueTS3std5stdio4File17LockingTextWriterTE3std8datetime5MonthTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format77__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std8datetime5MonthZv@Base 6
+ _D3std6format77__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std8datetime5MonthZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format78__T13formatGenericTS3std5stdio4File17LockingTextWriterTE3std8datetime5MonthTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std8datetime5MonthTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZk@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda13FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda15FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda17FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda19FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda21FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda23FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ18__T10__lambda16TkZ10__lambda16FNaNbNiNeKkZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ18__T10__lambda20TkZ10__lambda20FNaNbNiNeKkZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda14TAyaZ10__lambda14FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda18TAyaZ10__lambda18FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda22TAyaZ10__lambda22FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda24TAyaZ10__lambda24FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format81__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxE3std8datetime5MonthTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format81__T22enforceValidFormatSpecTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format81__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiE3std8datetime5MonthiZv@Base 6
+ _D3std6format81__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiE3std8datetime5MonthiZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format82__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTS3std11concurrency3TidTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format82__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std8datetime5MonthTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTS3std11concurrency3TidTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxE3std8datetime5MonthTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZk@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZ35__T9__lambda6TE3std8datetime5MonthZ9__lambda6FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format84__T11formatValueTDFNaNbNfAxaZvTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ11formatValueFNaNfDFNaNbNfAxaZvKS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format84__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsxE3std8datetime5MonthxhZv@Base 6
+ _D3std6format84__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsxE3std8datetime5MonthxhZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format85__T9formatNthTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecksE3std8datetime5MonthhhhhiZv@Base 6
+ _D3std6format85__T9formatNthTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecksE3std8datetime5MonthhhhhiZ16__T7gencodeVki7Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format86__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTE3std5regex8internal2ir2IRTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderE3std5regex8internal2ir2IRKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format86__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTE3std6socket12SocketOptionTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderE3std6socket12SocketOptionKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format86__T13formatElementTDFNaNbNfAxaZvTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ13formatElementFNaNfDFNaNbNfAxaZvKS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZk@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ16__T9__lambda8TiZ9__lambda8FNaNbNiNeKiZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ18__T10__lambda12TiZ10__lambda12FNaNbNiNeKiZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ37__T10__lambda10TE3std8datetime5MonthZ10__lambda10FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format89__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ11formatValueFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format89__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ11formatValueFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format90__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ11formatValueFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkykKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ11formatValueFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkykKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TykZ9__lambda4FNaNbNiNeKykZAxa@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZk@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ17__T9__lambda8TxsZ9__lambda8FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ38__T10__lambda10TxE3std8datetime5MonthZ10__lambda10FNaNbNiNeKxE3std8datetime5MonthZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T13formatGenericTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ13formatGenericFNaS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZk@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda13FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda15FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda17FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda19FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda21FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda23FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda12TsZ10__lambda12FNaNbNiNeKsZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda16ThZ10__lambda16FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda18ThZ10__lambda18FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda20ThZ10__lambda20FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda22ThZ10__lambda22FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda24TiZ10__lambda24FNaNbNiNeKiZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ37__T10__lambda14TE3std8datetime5MonthZ10__lambda14FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format92__T13formatGenericTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ13formatGenericFNaS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format92__T14formatIntegralTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTmTaZ14formatIntegralFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format92__T14formatUnsignedTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTmTaZ14formatUnsignedFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format93__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPS3std11parallelism12AbstractTaskTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPS3std11parallelism12AbstractTaskKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format94__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency14LinkTerminatedTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderC3std11concurrency14LinkTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format94__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net7isemail15EmailStatusCodeTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std3net7isemail15EmailStatusCodeKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format95__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency15OwnerTerminatedTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderC3std11concurrency15OwnerTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format95__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency14LinkTerminatedTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKC3std11concurrency14LinkTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency15OwnerTerminatedTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKC3std11concurrency15OwnerTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net7isemail15EmailStatusCodeTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T9formatNthTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ9formatNthFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKS3std6format18__T10FormatSpecTaZ10FormatSpeckykykkkkZv@Base 6
+ _D3std6format96__T9formatNthTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ9formatNthFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKS3std6format18__T10FormatSpecTaZ10FormatSpeckykykkkkZ16__T7gencodeVki5Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6getopt10assignCharw@Base 6
+ _D3std6getopt10optionCharw@Base 6
+ _D3std6getopt11splitAndGetFNaNbNeAyaZS3std6getopt6Option@Base 6
+ _D3std6getopt12GetoptResult11__xopEqualsFKxS3std6getopt12GetoptResultKxS3std6getopt12GetoptResultZb@Base 6
+ _D3std6getopt12GetoptResult6__initZ@Base 6
+ _D3std6getopt12GetoptResult9__xtoHashFNbNeKxS3std6getopt12GetoptResultZk@Base 6
+ _D3std6getopt12__ModuleInfoZ@Base 6
+ _D3std6getopt12endOfOptionsAya@Base 6
+ _D3std6getopt13configuration11passThroughMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration11passThroughMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration13caseSensitiveMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration13caseSensitiveMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration16keepEndOfOptionsMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration16keepEndOfOptionsMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration20stopOnFirstNonOptionMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration20stopOnFirstNonOptionMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration6__initZ@Base 6
+ _D3std6getopt13configuration8bundlingMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration8bundlingMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration8requiredMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration8requiredMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt15GetOptException6__ctorMFNaNbNfAyaAyakZC3std6getopt15GetOptException@Base 6
+ _D3std6getopt15GetOptException6__initZ@Base 6
+ _D3std6getopt15GetOptException6__vtblZ@Base 6
+ _D3std6getopt15GetOptException7__ClassZ@Base 6
+ _D3std6getopt20defaultGetoptPrinterFAyaAS3std6getopt6OptionZv@Base 6
+ _D3std6getopt64__T22defaultGetoptFormatterTS3std5stdio4File17LockingTextWriterZ22defaultGetoptFormatterFNfS3std5stdio4File17LockingTextWriterAyaAS3std6getopt6OptionZv@Base 6
+ _D3std6getopt6Option11__xopEqualsFKxS3std6getopt6OptionKxS3std6getopt6OptionZb@Base 6
+ _D3std6getopt6Option6__initZ@Base 6
+ _D3std6getopt6Option9__xtoHashFNbNeKxS3std6getopt6OptionZk@Base 6
+ _D3std6getopt8arraySepAya@Base 6
+ _D3std6getopt8optMatchFAyaAyaKAyaS3std6getopt13configurationZb@Base 6
+ _D3std6getopt9setConfigFKS3std6getopt13configurationE3std6getopt6configZv@Base 6
+ _D3std6mmfile12__ModuleInfoZ@Base 6
+ _D3std6mmfile6MmFile12ensureMappedMFmZv@Base 6
+ _D3std6mmfile6MmFile12ensureMappedMFmmZv@Base 6
+ _D3std6mmfile6MmFile13opIndexAssignMFhmZh@Base 6
+ _D3std6mmfile6MmFile3mapMFmkZv@Base 6
+ _D3std6mmfile6MmFile4modeMFZE3std6mmfile6MmFile4Mode@Base 6
+ _D3std6mmfile6MmFile5flushMFZv@Base 6
+ _D3std6mmfile6MmFile5unmapMFZv@Base 6
+ _D3std6mmfile6MmFile6__ctorMFAyaE3std6mmfile6MmFile4ModemPvkZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFAyaZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFS3std5stdio4FileE3std6mmfile6MmFile4ModemPvkZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFiE3std6mmfile6MmFile4ModemPvkZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__dtorMFZv@Base 6
+ _D3std6mmfile6MmFile6__initZ@Base 6
+ _D3std6mmfile6MmFile6__vtblZ@Base 6
+ _D3std6mmfile6MmFile6lengthMxFNdZm@Base 6
+ _D3std6mmfile6MmFile6mappedMFmZi@Base 6
+ _D3std6mmfile6MmFile7__ClassZ@Base 6
+ _D3std6mmfile6MmFile7opIndexMFmZh@Base 6
+ _D3std6mmfile6MmFile7opSliceMFZAv@Base 6
+ _D3std6mmfile6MmFile7opSliceMFmmZAv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine134__T4seedTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4seedMFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine4saveMFNaNbNdNiNfZS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine5frontMFNaNbNdNfZk@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine6__ctorMFNaNbNcNfkZS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine6__initZ@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine8popFrontMFNaNbNfZ5mag01yG2k@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine8popFrontMFNaNbNfZv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine9__T4seedZ4seedMFNaNbNfkZv@Base 6
+ _D3std6random12__ModuleInfoZ@Base 6
+ _D3std6random17unpredictableSeedFNdNeZ4randS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random17unpredictableSeedFNdNeZ6seededb@Base 6
+ _D3std6random17unpredictableSeedFNdNeZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG5kZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngineZb@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG6kZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngineZb@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG3kZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngineZb@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG4kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG1kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG2kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine16primeFactorsOnlyFNaNbNiNfmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine34properLinearCongruentialParametersFNaNbNiNfmmmZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine3gcdFNaNbNiNfmmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine4saveMFNaNbNdNiNfZS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine4seedMFNaNfkZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__ctorMFNaNcNfkZS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine8opEqualsMxFNaNbNiNfKxS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngineZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine16primeFactorsOnlyFNaNbNiNfmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine34properLinearCongruentialParametersFNaNbNiNfmmmZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine3gcdFNaNbNiNfmmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine4saveMFNaNbNdNiNfZS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine4seedMFNaNfkZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__ctorMFNaNcNfkZS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine8opEqualsMxFNaNbNiNfKxS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngineZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random6rndGenFNcNdNfZ11initializedb@Base 6
+ _D3std6random6rndGenFNcNdNfZ16__T9__lambda3TiZ9__lambda3FNfiZk@Base 6
+ _D3std6random6rndGenFNcNdNfZ16__T9__lambda4TiZ9__lambda4FNfiZk@Base 6
+ _D3std6random6rndGenFNcNdNfZ6resultS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6random6rndGenFNcNdNfZS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6socket10SocketType6__initZ@Base 6
+ _D3std6socket10getAddressFNfxAatZAC3std6socket7Address@Base 6
+ _D3std6socket10getAddressFNfxAaxAaZAC3std6socket7Address@Base 6
+ _D3std6socket10socketPairFNeZG2C3std6socket6Socket@Base 6
+ _D3std6socket11AddressInfo11__xopEqualsFKxS3std6socket11AddressInfoKxS3std6socket11AddressInfoZb@Base 6
+ _D3std6socket11AddressInfo6__initZ@Base 6
+ _D3std6socket11AddressInfo9__xtoHashFNbNeKxS3std6socket11AddressInfoZk@Base 6
+ _D3std6socket11UnixAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket11UnixAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket11UnixAddress4pathMxFNaNdNeZAya@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNbNiNfS4core3sys5posix3sys2un11sockaddr_unZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNbNiNfZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNexAaZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__initZ@Base 6
+ _D3std6socket11UnixAddress6__vtblZ@Base 6
+ _D3std6socket11UnixAddress7__ClassZ@Base 6
+ _D3std6socket11UnixAddress7nameLenMxFNaNbNdNiNeZk@Base 6
+ _D3std6socket11UnixAddress8toStringMxFNaNfZAya@Base 6
+ _D3std6socket12InternetHost12validHostentMFNfxPS4core3sys5posix5netdb7hostentZv@Base 6
+ _D3std6socket12InternetHost13getHostByAddrMFNekZb@Base 6
+ _D3std6socket12InternetHost13getHostByAddrMFNexAaZb@Base 6
+ _D3std6socket12InternetHost13getHostByNameMFNexAaZb@Base 6
+ _D3std6socket12InternetHost174__T7getHostVAyaa75_0a202020202020202020202020202020206175746f206865203d20676574686f737462796e616d6528706172616d2e74656d7043537472696e672829293b0a202020202020202020202020TAxaZ7getHostMFAxaZb@Base 6
+ _D3std6socket12InternetHost181__T13getHostNoSyncVAyaa75_0a202020202020202020202020202020206175746f206865203d20676574686f737462796e616d6528706172616d2e74656d7043537472696e672829293b0a202020202020202020202020TAxaZ13getHostNoSyncMFAxaZb@Base 6
+ _D3std6socket12InternetHost257__T7getHostVAyaa117_0a2020202020202020202020206175746f2078203d2068746f6e6c28706172616d293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TkZ7getHostMFkZb@Base 6
+ _D3std6socket12InternetHost264__T13getHostNoSyncVAyaa117_0a2020202020202020202020206175746f2078203d2068746f6e6c28706172616d293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TkZ13getHostNoSyncMFkZb@Base 6
+ _D3std6socket12InternetHost513__T7getHostVAyaa244_0a2020202020202020202020206175746f2078203d20696e65745f6164647228706172616d2e74656d7043537472696e672829293b0a202020202020202020202020656e666f726365287820213d20494e414444525f4e4f4e452c0a202020202020202020202020202020206e657720536f636b6574506172616d65746572457863657074696f6e2822496e76616c6964204950763420616464726573732229293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TAxaZ7getHostMFAxaZb@Base 6
+ _D3std6socket12InternetHost520__T13getHostNoSyncVAyaa244_0a2020202020202020202020206175746f2078203d20696e65745f6164647228706172616d2e74656d7043537472696e672829293b0a202020202020202020202020656e666f726365287820213d20494e414444525f4e4f4e452c0a202020202020202020202020202020206e657720536f636b6574506172616d65746572457863657074696f6e2822496e76616c6964204950763420616464726573732229293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TAxaZ13getHostNoSyncMFAxaZb@Base 6
+ _D3std6socket12InternetHost6__initZ@Base 6
+ _D3std6socket12InternetHost6__vtblZ@Base 6
+ _D3std6socket12InternetHost7__ClassZ@Base 6
+ _D3std6socket12InternetHost8populateMFNaNbPS4core3sys5posix5netdb7hostentZv@Base 6
+ _D3std6socket12SocketOption6__initZ@Base 6
+ _D3std6socket12__ModuleInfoZ@Base 6
+ _D3std6socket12parseAddressFNfxAatZC3std6socket7Address@Base 6
+ _D3std6socket12parseAddressFNfxAaxAaZC3std6socket7Address@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaAyakC6object9ThrowableiZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaC6object9ThrowableAyakiZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaiAyakC6object9ThrowableZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__initZ@Base 6
+ _D3std6socket13HostException6__vtblZ@Base 6
+ _D3std6socket13HostException7__ClassZ@Base 6
+ _D3std6socket13_SOCKET_ERRORxi@Base 6
+ _D3std6socket13serviceToPortFNfxAaZt@Base 6
+ _D3std6socket14UnknownAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket14UnknownAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket14UnknownAddress6__initZ@Base 6
+ _D3std6socket14UnknownAddress6__vtblZ@Base 6
+ _D3std6socket14UnknownAddress7__ClassZ@Base 6
+ _D3std6socket14UnknownAddress7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket14formatGaiErrorFNeiZ13__critsec1889G28g@Base 6
+ _D3std6socket14formatGaiErrorFNeiZAya@Base 6
+ _D3std6socket15InternetAddress12addrToStringFNbNekZAya@Base 6
+ _D3std6socket15InternetAddress12toAddrStringMxFNeZAya@Base 6
+ _D3std6socket15InternetAddress12toPortStringMxFNfZAya@Base 6
+ _D3std6socket15InternetAddress16toHostNameStringMxFNfZAya@Base 6
+ _D3std6socket15InternetAddress4addrMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket15InternetAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket15InternetAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket15InternetAddress4portMxFNaNbNdNiNfZt@Base 6
+ _D3std6socket15InternetAddress5parseFNbNexAaZk@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfS4core3sys5posix7netinet3in_11sockaddr_inZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfktZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNftZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNfxAatZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__initZ@Base 6
+ _D3std6socket15InternetAddress6__vtblZ@Base 6
+ _D3std6socket15InternetAddress7__ClassZ@Base 6
+ _D3std6socket15InternetAddress7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket15InternetAddress8opEqualsMxFNfC6ObjectZb@Base 6
+ _D3std6socket15SocketException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6socket15SocketException@Base 6
+ _D3std6socket15SocketException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC3std6socket15SocketException@Base 6
+ _D3std6socket15SocketException6__initZ@Base 6
+ _D3std6socket15SocketException6__vtblZ@Base 6
+ _D3std6socket15SocketException7__ClassZ@Base 6
+ _D3std6socket15lastSocketErrorFNdNfZAya@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaAyakC6object9ThrowableiZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaC6object9ThrowableAyakiZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaiAyakC6object9ThrowableZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__initZ@Base 6
+ _D3std6socket16AddressException6__vtblZ@Base 6
+ _D3std6socket16AddressException7__ClassZ@Base 6
+ _D3std6socket16AddressInfoFlags6__initZ@Base 6
+ _D3std6socket16Internet6Address4addrMxFNaNbNdNiNfZG16h@Base 6
+ _D3std6socket16Internet6Address4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket16Internet6Address4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket16Internet6Address4portMxFNaNbNdNiNfZt@Base 6
+ _D3std6socket16Internet6Address5parseFNexAaZG16h@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfG16htZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfS4core3sys5posix7netinet3in_12sockaddr_in6ZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNftZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNexAaxAaZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNfxAatZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__initZ@Base 6
+ _D3std6socket16Internet6Address6__vtblZ@Base 6
+ _D3std6socket16Internet6Address7__ClassZ@Base 6
+ _D3std6socket16Internet6Address7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket16Internet6Address8ADDR_ANYFNaNbNcNdNiNfZxG16h@Base 6
+ _D3std6socket16wouldHaveBlockedFNbNiNfZb@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaAyakC6object9ThrowableiPFNeiZAyaZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaC6object9ThrowableAyakiPFNeiZAyaZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaiPFNeiZAyaAyakC6object9ThrowableZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__initZ@Base 6
+ _D3std6socket17SocketOSException6__vtblZ@Base 6
+ _D3std6socket17SocketOSException7__ClassZ@Base 6
+ _D3std6socket17SocketOptionLevel6__initZ@Base 6
+ _D3std6socket17formatSocketErrorFNeiZAya@Base 6
+ _D3std6socket18_sharedStaticCtor1FZv@Base 6
+ _D3std6socket18_sharedStaticDtor2FNbNiZv@Base 6
+ _D3std6socket18getAddressInfoImplFxAaxAaPS4core3sys5posix5netdb8addrinfoZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket18getaddrinfoPointeryPUNbNiPxaPxaPxS4core3sys5posix5netdb8addrinfoPPS4core3sys5posix5netdb8addrinfoZi@Base 6
+ _D3std6socket18getnameinfoPointeryPUNbNiPxS4core3sys5posix3sys6socket8sockaddrkPakPakiZi@Base 6
+ _D3std6socket19freeaddrinfoPointeryPUNbNiPS4core3sys5posix5netdb8addrinfoZv@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaAyakC6object9ThrowableiZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaC6object9ThrowableAyakiZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaiAyakC6object9ThrowableZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__initZ@Base 6
+ _D3std6socket21SocketAcceptException6__vtblZ@Base 6
+ _D3std6socket21SocketAcceptException7__ClassZ@Base 6
+ _D3std6socket22SocketFeatureException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6socket22SocketFeatureException@Base 6
+ _D3std6socket22SocketFeatureException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC3std6socket22SocketFeatureException@Base 6
+ _D3std6socket22SocketFeatureException6__initZ@Base 6
+ _D3std6socket22SocketFeatureException6__vtblZ@Base 6
+ _D3std6socket22SocketFeatureException7__ClassZ@Base 6
+ _D3std6socket23UnknownAddressReference4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket23UnknownAddressReference4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket23UnknownAddressReference6__ctorMFNaNbNiNfPS4core3sys5posix3sys6socket8sockaddrkZC3std6socket23UnknownAddressReference@Base 6
+ _D3std6socket23UnknownAddressReference6__ctorMFNaNbPxS4core3sys5posix3sys6socket8sockaddrkZC3std6socket23UnknownAddressReference@Base 6
+ _D3std6socket23UnknownAddressReference6__initZ@Base 6
+ _D3std6socket23UnknownAddressReference6__vtblZ@Base 6
+ _D3std6socket23UnknownAddressReference7__ClassZ@Base 6
+ _D3std6socket23UnknownAddressReference7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket24SocketParameterException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6socket24SocketParameterException@Base 6
+ _D3std6socket24SocketParameterException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC3std6socket24SocketParameterException@Base 6
+ _D3std6socket24SocketParameterException6__initZ@Base 6
+ _D3std6socket24SocketParameterException6__vtblZ@Base 6
+ _D3std6socket24SocketParameterException7__ClassZ@Base 6
+ _D3std6socket24__T14getAddressInfoTAxaZ14getAddressInfoFNexAaAxaZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket51__T14getAddressInfoTE3std6socket16AddressInfoFlagsZ14getAddressInfoFNexAaE3std6socket16AddressInfoFlagsZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket52__T14getAddressInfoTAxaTE3std6socket13AddressFamilyZ14getAddressInfoFNexAaAxaE3std6socket13AddressFamilyZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket55__T14getAddressInfoTAxaTE3std6socket16AddressInfoFlagsZ14getAddressInfoFNexAaAxaE3std6socket16AddressInfoFlagsZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket6Linger6__initZ@Base 6
+ _D3std6socket6Linger8__mixin22onMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket6Linger8__mixin22onMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket6Linger8__mixin34timeMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket6Linger8__mixin34timeMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNeAvE3std6socket11SocketFlagsKC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNeAvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNfAvKC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNfAvZi@Base 6
+ _D3std6socket6Socket12getErrorTextMFNfZAya@Base 6
+ _D3std6socket6Socket12localAddressMFNdNeZC3std6socket7Address@Base 6
+ _D3std6socket6Socket12setKeepAliveMFNeiiZv@Base 6
+ _D3std6socket6Socket13addressFamilyMFNdNfZE3std6socket13AddressFamily@Base 6
+ _D3std6socket6Socket13createAddressMFNaNbNfZC3std6socket7Address@Base 6
+ _D3std6socket6Socket13remoteAddressMFNdNeZC3std6socket7Address@Base 6
+ _D3std6socket6Socket4bindMFNeC3std6socket7AddressZv@Base 6
+ _D3std6socket6Socket4sendMFNeAxvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket4sendMFNfAxvZi@Base 6
+ _D3std6socket6Socket5closeMFNbNiNeZv@Base 6
+ _D3std6socket6Socket6__ctorMFNaNbNiNfE3std6socket8socket_tE3std6socket13AddressFamilyZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNaNbNiNfZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNeE3std6socket13AddressFamilyE3std6socket10SocketTypeE3std6socket12ProtocolTypeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNeE3std6socket13AddressFamilyE3std6socket10SocketTypexAaZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNfE3std6socket13AddressFamilyE3std6socket10SocketTypeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNfxS3std6socket11AddressInfoZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__dtorMFNbNiNfZv@Base 6
+ _D3std6socket6Socket6__initZ@Base 6
+ _D3std6socket6Socket6__vtblZ@Base 6
+ _D3std6socket6Socket6_closeFNbNiE3std6socket8socket_tZv@Base 6
+ _D3std6socket6Socket6acceptMFNeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6handleMxFNaNbNdNiNfZE3std6socket8socket_t@Base 6
+ _D3std6socket6Socket6listenMFNeiZv@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetPS3std6socket7TimeValZi@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetS4core4time8DurationZi@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetlZi@Base 6
+ _D3std6socket6Socket6selectFNfC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetZi@Base 6
+ _D3std6socket6Socket6sendToMFNeAxvE3std6socket11SocketFlagsC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket6sendToMFNeAxvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket6sendToMFNfAxvC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket6sendToMFNfAxvZi@Base 6
+ _D3std6socket6Socket7__ClassZ@Base 6
+ _D3std6socket6Socket7connectMFNeC3std6socket7AddressZv@Base 6
+ _D3std6socket6Socket7isAliveMxFNdNeZb@Base 6
+ _D3std6socket6Socket7receiveMFNeAvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket7receiveMFNfAvZi@Base 6
+ _D3std6socket6Socket7setSockMFNfE3std6socket8socket_tZv@Base 6
+ _D3std6socket6Socket8blockingMFNdNebZv@Base 6
+ _D3std6socket6Socket8blockingMxFNbNdNiNeZb@Base 6
+ _D3std6socket6Socket8hostNameFNdNeZAya@Base 6
+ _D3std6socket6Socket8shutdownMFNbNiNeE3std6socket14SocketShutdownZv@Base 6
+ _D3std6socket6Socket9acceptingMFNaNbNfZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionAvZi@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJS3std6socket6LingerZi@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJS4core4time8DurationZv@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJiZi@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionAvZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionS3std6socket6LingerZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionS4core4time8DurationZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptioniZv@Base 6
+ _D3std6socket7Address12toAddrStringMxFNfZAya@Base 6
+ _D3std6socket7Address12toHostStringMxFNebZAya@Base 6
+ _D3std6socket7Address12toPortStringMxFNfZAya@Base 6
+ _D3std6socket7Address13addressFamilyMxFNaNbNdNiNfZE3std6socket13AddressFamily@Base 6
+ _D3std6socket7Address15toServiceStringMxFNebZAya@Base 6
+ _D3std6socket7Address16toHostNameStringMxFNfZAya@Base 6
+ _D3std6socket7Address19toServiceNameStringMxFNfZAya@Base 6
+ _D3std6socket7Address6__initZ@Base 6
+ _D3std6socket7Address6__vtblZ@Base 6
+ _D3std6socket7Address7__ClassZ@Base 6
+ _D3std6socket7Address8toStringMxFNfZAya@Base 6
+ _D3std6socket7Service16getServiceByNameMFNbNexAaxAaZb@Base 6
+ _D3std6socket7Service16getServiceByPortMFNbNetxAaZb@Base 6
+ _D3std6socket7Service6__initZ@Base 6
+ _D3std6socket7Service6__vtblZ@Base 6
+ _D3std6socket7Service7__ClassZ@Base 6
+ _D3std6socket7Service8populateMFNaNbPS4core3sys5posix5netdb7serventZv@Base 6
+ _D3std6socket7TimeVal6__initZ@Base 6
+ _D3std6socket7TimeVal8__mixin47secondsMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket7TimeVal8__mixin47secondsMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket7TimeVal8__mixin512microsecondsMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket7TimeVal8__mixin512microsecondsMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket8Protocol17getProtocolByNameMFNbNexAaZb@Base 6
+ _D3std6socket8Protocol17getProtocolByTypeMFNbNeE3std6socket12ProtocolTypeZb@Base 6
+ _D3std6socket8Protocol6__initZ@Base 6
+ _D3std6socket8Protocol6__vtblZ@Base 6
+ _D3std6socket8Protocol7__ClassZ@Base 6
+ _D3std6socket8Protocol8populateMFNaNbPS4core3sys5posix5netdb8protoentZv@Base 6
+ _D3std6socket8_lasterrFNbNiNfZi@Base 6
+ _D3std6socket8socket_t6__initZ@Base 6
+ _D3std6socket9SocketSet14setMinCapacityMFNaNbNfkZv@Base 6
+ _D3std6socket9SocketSet3addMFNaNbNeE3std6socket8socket_tZv@Base 6
+ _D3std6socket9SocketSet3addMFNaNbNfC3std6socket6SocketZv@Base 6
+ _D3std6socket9SocketSet3maxMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket9SocketSet4maskFNaNbNiNfkZi@Base 6
+ _D3std6socket9SocketSet5isSetMxFNaNbNiNfC3std6socket6SocketZi@Base 6
+ _D3std6socket9SocketSet5isSetMxFNaNbNiNfE3std6socket8socket_tZi@Base 6
+ _D3std6socket9SocketSet5resetMFNaNbNiNfZv@Base 6
+ _D3std6socket9SocketSet6__ctorMFNaNbNfkZC3std6socket9SocketSet@Base 6
+ _D3std6socket9SocketSet6__initZ@Base 6
+ _D3std6socket9SocketSet6__vtblZ@Base 6
+ _D3std6socket9SocketSet6removeMFNaNbNfC3std6socket6SocketZv@Base 6
+ _D3std6socket9SocketSet6removeMFNaNbNfE3std6socket8socket_tZv@Base 6
+ _D3std6socket9SocketSet6resizeMFNaNbNfkZv@Base 6
+ _D3std6socket9SocketSet7__ClassZ@Base 6
+ _D3std6socket9SocketSet7selectnMxFNaNbNiNfZi@Base 6
+ _D3std6socket9SocketSet8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket9SocketSet8toFd_setMFNaNbNiNeZPS4core3sys5posix3sys6select6fd_set@Base 6
+ _D3std6socket9SocketSet9lengthForFNaNbNiNfkZk@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfC3std6socket7AddressZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfE3std6socket13AddressFamilyZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__initZ@Base 6
+ _D3std6socket9TcpSocket6__vtblZ@Base 6
+ _D3std6socket9TcpSocket7__ClassZ@Base 6
+ _D3std6socket9UdpSocket6__ctorMFNfE3std6socket13AddressFamilyZC3std6socket9UdpSocket@Base 6
+ _D3std6socket9UdpSocket6__ctorMFNfZC3std6socket9UdpSocket@Base 6
+ _D3std6socket9UdpSocket6__initZ@Base 6
+ _D3std6socket9UdpSocket6__vtblZ@Base 6
+ _D3std6socket9UdpSocket7__ClassZ@Base 6
+ _D3std6stdint12__ModuleInfoZ@Base 6
+ _D3std6stream11InputStream11__InterfaceZ@Base 6
+ _D3std6stream11SliceStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream11SliceStream11__invariantMxFZv@Base 6
+ _D3std6stream11SliceStream13__invariant11MxFZv@Base 6
+ _D3std6stream11SliceStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream11SliceStream6__ctorMFC3std6stream6StreammZC3std6stream11SliceStream@Base 6
+ _D3std6stream11SliceStream6__ctorMFC3std6stream6StreammmZC3std6stream11SliceStream@Base 6
+ _D3std6stream11SliceStream6__initZ@Base 6
+ _D3std6stream11SliceStream6__vtblZ@Base 6
+ _D3std6stream11SliceStream7__ClassZ@Base 6
+ _D3std6stream11SliceStream9availableMFNdZk@Base 6
+ _D3std6stream11SliceStream9readBlockMFPvkZk@Base 6
+ _D3std6stream12BufferedFile4openMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream12BufferedFile6__ctorMFAyaE3std6stream8FileModekZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFC3std6stream4FilekZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFiE3std6stream8FileModekZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__initZ@Base 6
+ _D3std6stream12BufferedFile6__vtblZ@Base 6
+ _D3std6stream12BufferedFile6createMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream12BufferedFile7__ClassZ@Base 6
+ _D3std6stream12EndianStream10fixBlockBOMFPvkkZv@Base 6
+ _D3std6stream12EndianStream11readStringWMFkZAu@Base 6
+ _D3std6stream12EndianStream12writeStringWMFAxuZv@Base 6
+ _D3std6stream12EndianStream3eofMFNdZb@Base 6
+ _D3std6stream12EndianStream4readMFJaZv@Base 6
+ _D3std6stream12EndianStream4readMFJcZv@Base 6
+ _D3std6stream12EndianStream4readMFJdZv@Base 6
+ _D3std6stream12EndianStream4readMFJeZv@Base 6
+ _D3std6stream12EndianStream4readMFJfZv@Base 6
+ _D3std6stream12EndianStream4readMFJgZv@Base 6
+ _D3std6stream12EndianStream4readMFJhZv@Base 6
+ _D3std6stream12EndianStream4readMFJiZv@Base 6
+ _D3std6stream12EndianStream4readMFJjZv@Base 6
+ _D3std6stream12EndianStream4readMFJkZv@Base 6
+ _D3std6stream12EndianStream4readMFJlZv@Base 6
+ _D3std6stream12EndianStream4readMFJmZv@Base 6
+ _D3std6stream12EndianStream4readMFJoZv@Base 6
+ _D3std6stream12EndianStream4readMFJpZv@Base 6
+ _D3std6stream12EndianStream4readMFJqZv@Base 6
+ _D3std6stream12EndianStream4readMFJrZv@Base 6
+ _D3std6stream12EndianStream4readMFJsZv@Base 6
+ _D3std6stream12EndianStream4readMFJtZv@Base 6
+ _D3std6stream12EndianStream4readMFJuZv@Base 6
+ _D3std6stream12EndianStream4readMFJwZv@Base 6
+ _D3std6stream12EndianStream4sizeMFNdZm@Base 6
+ _D3std6stream12EndianStream5fixBOMFPxvkZv@Base 6
+ _D3std6stream12EndianStream5getcwMFZu@Base 6
+ _D3std6stream12EndianStream5writeMFaZv@Base 6
+ _D3std6stream12EndianStream5writeMFcZv@Base 6
+ _D3std6stream12EndianStream5writeMFdZv@Base 6
+ _D3std6stream12EndianStream5writeMFeZv@Base 6
+ _D3std6stream12EndianStream5writeMFfZv@Base 6
+ _D3std6stream12EndianStream5writeMFgZv@Base 6
+ _D3std6stream12EndianStream5writeMFhZv@Base 6
+ _D3std6stream12EndianStream5writeMFiZv@Base 6
+ _D3std6stream12EndianStream5writeMFjZv@Base 6
+ _D3std6stream12EndianStream5writeMFkZv@Base 6
+ _D3std6stream12EndianStream5writeMFlZv@Base 6
+ _D3std6stream12EndianStream5writeMFmZv@Base 6
+ _D3std6stream12EndianStream5writeMFoZv@Base 6
+ _D3std6stream12EndianStream5writeMFpZv@Base 6
+ _D3std6stream12EndianStream5writeMFqZv@Base 6
+ _D3std6stream12EndianStream5writeMFrZv@Base 6
+ _D3std6stream12EndianStream5writeMFsZv@Base 6
+ _D3std6stream12EndianStream5writeMFtZv@Base 6
+ _D3std6stream12EndianStream5writeMFuZv@Base 6
+ _D3std6stream12EndianStream5writeMFwZv@Base 6
+ _D3std6stream12EndianStream6__ctorMFC3std6stream6StreamE3std6system6EndianZC3std6stream12EndianStream@Base 6
+ _D3std6stream12EndianStream6__initZ@Base 6
+ _D3std6stream12EndianStream6__vtblZ@Base 6
+ _D3std6stream12EndianStream7__ClassZ@Base 6
+ _D3std6stream12EndianStream7readBOMMFiZi@Base 6
+ _D3std6stream12EndianStream8writeBOMMFE3std6stream3BOMZv@Base 6
+ _D3std6stream12FilterStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream12FilterStream11resetSourceMFZv@Base 6
+ _D3std6stream12FilterStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream12FilterStream5closeMFZv@Base 6
+ _D3std6stream12FilterStream5flushMFZv@Base 6
+ _D3std6stream12FilterStream6__ctorMFC3std6stream6StreamZC3std6stream12FilterStream@Base 6
+ _D3std6stream12FilterStream6__initZ@Base 6
+ _D3std6stream12FilterStream6__vtblZ@Base 6
+ _D3std6stream12FilterStream6sourceMFC3std6stream6StreamZv@Base 6
+ _D3std6stream12FilterStream6sourceMFZC3std6stream6Stream@Base 6
+ _D3std6stream12FilterStream7__ClassZ@Base 6
+ _D3std6stream12FilterStream9availableMFNdZk@Base 6
+ _D3std6stream12FilterStream9readBlockMFPvkZk@Base 6
+ _D3std6stream12MemoryStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAaZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAgZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAhZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__initZ@Base 6
+ _D3std6stream12MemoryStream6__vtblZ@Base 6
+ _D3std6stream12MemoryStream7__ClassZ@Base 6
+ _D3std6stream12MemoryStream7reserveMFkZv@Base 6
+ _D3std6stream12MmFileStream5closeMFZv@Base 6
+ _D3std6stream12MmFileStream5flushMFZv@Base 6
+ _D3std6stream12MmFileStream6__ctorMFC3std6mmfile6MmFileZC3std6stream12MmFileStream@Base 6
+ _D3std6stream12MmFileStream6__initZ@Base 6
+ _D3std6stream12MmFileStream6__vtblZ@Base 6
+ _D3std6stream12MmFileStream7__ClassZ@Base 6
+ _D3std6stream12OutputStream11__InterfaceZ@Base 6
+ _D3std6stream12__ModuleInfoZ@Base 6
+ _D3std6stream13OpenException6__ctorMFAyaZC3std6stream13OpenException@Base 6
+ _D3std6stream13OpenException6__initZ@Base 6
+ _D3std6stream13OpenException6__vtblZ@Base 6
+ _D3std6stream13OpenException7__ClassZ@Base 6
+ _D3std6stream13ReadException6__ctorMFAyaZC3std6stream13ReadException@Base 6
+ _D3std6stream13ReadException6__initZ@Base 6
+ _D3std6stream13ReadException6__vtblZ@Base 6
+ _D3std6stream13ReadException7__ClassZ@Base 6
+ _D3std6stream13SeekException6__ctorMFAyaZC3std6stream13SeekException@Base 6
+ _D3std6stream13SeekException6__initZ@Base 6
+ _D3std6stream13SeekException6__vtblZ@Base 6
+ _D3std6stream13SeekException7__ClassZ@Base 6
+ _D3std6stream14BufferedStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream14BufferedStream11__invariantMxFZv@Base 6
+ _D3std6stream14BufferedStream11resetSourceMFZv@Base 6
+ _D3std6stream14BufferedStream12__invariant3MxFZv@Base 6
+ _D3std6stream14BufferedStream16__T9TreadLineTaZ8readLineMFAaZAa@Base 6
+ _D3std6stream14BufferedStream16__T9TreadLineTuZ8readLineMFAuZAu@Base 6
+ _D3std6stream14BufferedStream3eofMFNdZb@Base 6
+ _D3std6stream14BufferedStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream14BufferedStream4sizeMFNdZm@Base 6
+ _D3std6stream14BufferedStream5flushMFZv@Base 6
+ _D3std6stream14BufferedStream6__ctorMFC3std6stream6StreamkZC3std6stream14BufferedStream@Base 6
+ _D3std6stream14BufferedStream6__initZ@Base 6
+ _D3std6stream14BufferedStream6__vtblZ@Base 6
+ _D3std6stream14BufferedStream7__ClassZ@Base 6
+ _D3std6stream14BufferedStream8readLineMFAaZAa@Base 6
+ _D3std6stream14BufferedStream9availableMFNdZk@Base 6
+ _D3std6stream14BufferedStream9readBlockMFPvkZk@Base 6
+ _D3std6stream14BufferedStream9readLineWMFAuZAu@Base 6
+ _D3std6stream14ByteOrderMarksyG5Ah@Base 6
+ _D3std6stream14WriteException6__ctorMFAyaZC3std6stream14WriteException@Base 6
+ _D3std6stream14WriteException6__initZ@Base 6
+ _D3std6stream14WriteException6__vtblZ@Base 6
+ _D3std6stream14WriteException7__ClassZ@Base 6
+ _D3std6stream15StreamException6__ctorMFAyaZC3std6stream15StreamException@Base 6
+ _D3std6stream15StreamException6__initZ@Base 6
+ _D3std6stream15StreamException6__vtblZ@Base 6
+ _D3std6stream15StreamException7__ClassZ@Base 6
+ _D3std6stream19StreamFileException6__ctorMFAyaZC3std6stream19StreamFileException@Base 6
+ _D3std6stream19StreamFileException6__initZ@Base 6
+ _D3std6stream19StreamFileException6__vtblZ@Base 6
+ _D3std6stream19StreamFileException7__ClassZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream11__invariantMxFNaNbNiNfZv@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream15__invariant2473MxFNaNbNiNfZv@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream4dataMFNdZAh@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__ctorMFAhZC3std6stream21__T12TArrayStreamTAhZ12TArrayStream@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__initZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__vtblZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream7__ClassZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream8toStringMFZAya@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9availableMFNdZk@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9readBlockMFPvkZk@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream11__invariantMxFZv@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream15__invariant2474MxFZv@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream4dataMFNdZAh@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__ctorMFC3std6mmfile6MmFileZC3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__initZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__vtblZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream7__ClassZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream8toStringMFZAya@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9availableMFNdZk@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9readBlockMFPvkZk@Base 6
+ _D3std6stream4File10writeBlockMFxPvkZk@Base 6
+ _D3std6stream4File4openMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream4File4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream4File5closeMFZv@Base 6
+ _D3std6stream4File6__ctorMFAyaE3std6stream8FileModeZC3std6stream4File@Base 6
+ _D3std6stream4File6__ctorMFZC3std6stream4File@Base 6
+ _D3std6stream4File6__ctorMFiE3std6stream8FileModeZC3std6stream4File@Base 6
+ _D3std6stream4File6__dtorMFZv@Base 6
+ _D3std6stream4File6__initZ@Base 6
+ _D3std6stream4File6__vtblZ@Base 6
+ _D3std6stream4File6createMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream4File6createMFAyaZv@Base 6
+ _D3std6stream4File6handleMFZi@Base 6
+ _D3std6stream4File7__ClassZ@Base 6
+ _D3std6stream4File9availableMFNdZk@Base 6
+ _D3std6stream4File9parseModeMFiJiJiJiZv@Base 6
+ _D3std6stream4File9readBlockMFPvkZk@Base 6
+ _D3std6stream6Stream10readStringMFkZAa@Base 6
+ _D3std6stream6Stream10writeExactMFxPvkZv@Base 6
+ _D3std6stream6Stream10writeLineWMFAxuZv@Base 6
+ _D3std6stream6Stream11readStringWMFkZAu@Base 6
+ _D3std6stream6Stream11writeStringMFAxaZv@Base 6
+ _D3std6stream6Stream12writeStringWMFAxuZv@Base 6
+ _D3std6stream6Stream14assertReadableMFZv@Base 6
+ _D3std6stream6Stream14assertSeekableMFZv@Base 6
+ _D3std6stream6Stream14ungetAvailableMFZb@Base 6
+ _D3std6stream6Stream15assertWriteableMFZv@Base 6
+ _D3std6stream6Stream16doFormatCallbackMFwZv@Base 6
+ _D3std6stream6Stream3eofMFNdZb@Base 6
+ _D3std6stream6Stream4getcMFZa@Base 6
+ _D3std6stream6Stream4readMFAhZk@Base 6
+ _D3std6stream6Stream4readMFJAaZv@Base 6
+ _D3std6stream6Stream4readMFJAuZv@Base 6
+ _D3std6stream6Stream4readMFJaZv@Base 6
+ _D3std6stream6Stream4readMFJcZv@Base 6
+ _D3std6stream6Stream4readMFJdZv@Base 6
+ _D3std6stream6Stream4readMFJeZv@Base 6
+ _D3std6stream6Stream4readMFJfZv@Base 6
+ _D3std6stream6Stream4readMFJgZv@Base 6
+ _D3std6stream6Stream4readMFJhZv@Base 6
+ _D3std6stream6Stream4readMFJiZv@Base 6
+ _D3std6stream6Stream4readMFJjZv@Base 6
+ _D3std6stream6Stream4readMFJkZv@Base 6
+ _D3std6stream6Stream4readMFJlZv@Base 6
+ _D3std6stream6Stream4readMFJmZv@Base 6
+ _D3std6stream6Stream4readMFJoZv@Base 6
+ _D3std6stream6Stream4readMFJpZv@Base 6
+ _D3std6stream6Stream4readMFJqZv@Base 6
+ _D3std6stream6Stream4readMFJrZv@Base 6
+ _D3std6stream6Stream4readMFJsZv@Base 6
+ _D3std6stream6Stream4readMFJtZv@Base 6
+ _D3std6stream6Stream4readMFJuZv@Base 6
+ _D3std6stream6Stream4readMFJwZv@Base 6
+ _D3std6stream6Stream4sizeMFNdZm@Base 6
+ _D3std6stream6Stream5closeMFZv@Base 6
+ _D3std6stream6Stream5flushMFZv@Base 6
+ _D3std6stream6Stream5getcwMFZu@Base 6
+ _D3std6stream6Stream5readfMFYi@Base 6
+ _D3std6stream6Stream5writeMFAxaZv@Base 6
+ _D3std6stream6Stream5writeMFAxhZk@Base 6
+ _D3std6stream6Stream5writeMFAxuZv@Base 6
+ _D3std6stream6Stream5writeMFaZv@Base 6
+ _D3std6stream6Stream5writeMFcZv@Base 6
+ _D3std6stream6Stream5writeMFdZv@Base 6
+ _D3std6stream6Stream5writeMFeZv@Base 6
+ _D3std6stream6Stream5writeMFfZv@Base 6
+ _D3std6stream6Stream5writeMFgZv@Base 6
+ _D3std6stream6Stream5writeMFhZv@Base 6
+ _D3std6stream6Stream5writeMFiZv@Base 6
+ _D3std6stream6Stream5writeMFjZv@Base 6
+ _D3std6stream6Stream5writeMFkZv@Base 6
+ _D3std6stream6Stream5writeMFlZv@Base 6
+ _D3std6stream6Stream5writeMFmZv@Base 6
+ _D3std6stream6Stream5writeMFoZv@Base 6
+ _D3std6stream6Stream5writeMFpZv@Base 6
+ _D3std6stream6Stream5writeMFqZv@Base 6
+ _D3std6stream6Stream5writeMFrZv@Base 6
+ _D3std6stream6Stream5writeMFsZv@Base 6
+ _D3std6stream6Stream5writeMFtZv@Base 6
+ _D3std6stream6Stream5writeMFuZv@Base 6
+ _D3std6stream6Stream5writeMFwZv@Base 6
+ _D3std6stream6Stream6__ctorMFZC3std6stream6Stream@Base 6
+ _D3std6stream6Stream6__initZ@Base 6
+ _D3std6stream6Stream6__vtblZ@Base 6
+ _D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _D3std6stream6Stream6printfMFAxaYk@Base 6
+ _D3std6stream6Stream6toHashMFNbNeZk@Base 6
+ _D3std6stream6Stream6toHashMFNeZ8resUnion6__initZ@Base 6
+ _D3std6stream6Stream6ungetcMFaZa@Base 6
+ _D3std6stream6Stream6vreadfMFAC8TypeInfoPaZi@Base 6
+ _D3std6stream6Stream6writefMFYC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream7__ClassZ@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKAaZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKAuZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKmKAaZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKmKAuZiZi@Base 6
+ _D3std6stream6Stream7seekCurMFlZm@Base 6
+ _D3std6stream6Stream7seekEndMFlZm@Base 6
+ _D3std6stream6Stream7seekSetMFlZm@Base 6
+ _D3std6stream6Stream7ungetcwMFuZu@Base 6
+ _D3std6stream6Stream7vprintfMFAxaPaZk@Base 6
+ _D3std6stream6Stream7writefxMFAC8TypeInfoPaiZC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream8copyFromMFC3std6stream6StreamZv@Base 6
+ _D3std6stream6Stream8copyFromMFC3std6stream6StreammZv@Base 6
+ _D3std6stream6Stream8positionMFNdZm@Base 6
+ _D3std6stream6Stream8positionMFNdmZv@Base 6
+ _D3std6stream6Stream8readLineMFAaZAa@Base 6
+ _D3std6stream6Stream8readLineMFZAa@Base 6
+ _D3std6stream6Stream8toStringMFZAya@Base 6
+ _D3std6stream6Stream8writeflnMFYC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream9availableMFNdZk@Base 6
+ _D3std6stream6Stream9readExactMFPvkZv@Base 6
+ _D3std6stream6Stream9readLineWMFAuZAu@Base 6
+ _D3std6stream6Stream9readLineWMFZAu@Base 6
+ _D3std6stream6Stream9writeLineMFAxaZv@Base 6
+ _D3std6stream8FileMode6__initZ@Base 6
+ _D3std6stream9BOMEndianyG5E3std6system6Endian@Base 6
+ _D3std6string11fromStringzFNaNbNiPNgaZANga@Base 6
+ _D3std6string12__ModuleInfoZ@Base 6
+ _D3std6string14__T5chompTAxaZ5chompFNaNbNiNfAxaZAxa@Base 6
+ _D3std6string14__T5stripTAyaZ5stripFNaNfAyaZAya@Base 6
+ _D3std6string14makeTransTableFNaNbNiNfxAaxAaZG256a@Base 6
+ _D3std6string15StringException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6string15StringException@Base 6
+ _D3std6string15StringException6__initZ@Base 6
+ _D3std6string15StringException6__vtblZ@Base 6
+ _D3std6string15StringException7__ClassZ@Base 6
+ _D3std6string16__T7indexOfTAyaZ7indexOfFNaNbNiNfAyaxwxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZi@Base 6
+ _D3std6string18__T5munchTAyaTAyaZ5munchFNaNiNfKAyaAyaZAya@Base 6
+ _D3std6string18__T7indexOfTAyaTaZ7indexOfFAyaAxaxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZ18__T9__lambda4TwTwZ9__lambda4FNaNbNiNfwwZb@Base 6
+ _D3std6string18__T7indexOfTAyaTaZ7indexOfFNaNfAyaAxaxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZi@Base 6
+ _D3std6string18__T9inPatternTAyaZ9inPatternFNaNiNfwxAyaZb@Base 6
+ _D3std6string18__T9soundexerTAxaZ9soundexerFAxaZ3dexyAa@Base 6
+ _D3std6string18__T9soundexerTAxaZ9soundexerFNaNbNiNfAxaZG4a@Base 6
+ _D3std6string18__T9stripLeftTAyaZ9stripLeftFNaNfAyaZAya@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result10initializeMFNaNbNiNfZv@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result11__xopEqualsFKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZb@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result4saveMFNaNbNdNiNfZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result5frontMFNaNbNdNiNfZw@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__ctorMFNaNbNcNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__initZ@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result9__xtoHashFNbNeKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZk@Base 6
+ _D3std6string19__T11lastIndexOfTaZ11lastIndexOfFNaNiNfAxaxwxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZi@Base 6
+ _D3std6string20__T10stripRightTAyaZ10stripRightFNaNiNfAyaZAya@Base 6
+ _D3std6string22__T12rightJustifyTAyaZ12rightJustifyFNaNbNfAyakwZAya@Base 6
+ _D3std6string23__T14representationTyaZ14representationFNaNbNiNfAyaZAyh@Base 6
+ _D3std6string24__T14rightJustifierTAyaZ14rightJustifierFNaNbNiNfAyakwZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std6string6abbrevFNaNfAAyaZHAyaAya@Base 6
+ _D3std6string7soundexFNaNbNfAxaAaZAa@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda3TAxaTAyaZ9__lambda3FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda4TAxaTAyaZ9__lambda4FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda5TAxaTAyaZ9__lambda5FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZb@Base 6
+ _D3std6string9makeTransFNaNbNexAaxAaZAya@Base 6
+ _D3std6string9toStringzFNaNbNeAxaZPya@Base 6
+ _D3std6string9toStringzFNaNbNexAyaZPya@Base 6
+ _D3std6system12__ModuleInfoZ@Base 6
+ _D3std6system2OS6__initZ@Base 6
+ _D3std6system2osyE3std6system2OS@Base 6
+ _D3std6system6endianyE3std6system6Endian@Base 6
+ _D3std6traits12__ModuleInfoZ@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle11__xopEqualsFKxS3std6traits15__T8DemangleTkZ8DemangleKxS3std6traits15__T8DemangleTkZ8DemangleZb@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle6__initZ@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle9__xtoHashFNbNeKxS3std6traits15__T8DemangleTkZ8DemangleZk@Base 6
+ _D3std6traits19removeDummyEnvelopeFAyaZAya@Base 6
+ _D3std6traits23__InoutWorkaroundStruct6__initZ@Base 6
+ _D3std6traits26demangleFunctionAttributesFAyaZS3std6traits15__T8DemangleTkZ8Demangle@Base 6
+ _D3std6traits29demangleParameterStorageClassFAyaZS3std6traits15__T8DemangleTkZ8Demangle@Base 6
+ _D3std7complex12__ModuleInfoZ@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex11__xopEqualsFKxS3std7complex14__T7ComplexTeZ7ComplexKxS3std7complex14__T7ComplexTeZ7ComplexZb@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex15__T8toStringTaZ8toStringMxFMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex16__T8opEqualsHTeZ8opEqualsMxFNaNbNiNfS3std7complex14__T7ComplexTeZ7ComplexZb@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex17__T6__ctorHTeHTeZ6__ctorMFNaNbNcNiNfeeZS3std7complex14__T7ComplexTeZ7Complex@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex6__initZ@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex8toStringMxFZAya@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex9__xtoHashFNbNeKxS3std7complex14__T7ComplexTeZ7ComplexZk@Base 6
+ _D3std7complex4expiFNaNbNiNeeZS3std7complex14__T7ComplexTeZ7Complex@Base 6
+ _D3std7cstream12__ModuleInfoZ@Base 6
+ _D3std7cstream18_sharedStaticCtor2FZv@Base 6
+ _D3std7cstream3dinC3std7cstream5CFile@Base 6
+ _D3std7cstream4derrC3std7cstream5CFile@Base 6
+ _D3std7cstream4doutC3std7cstream5CFile@Base 6
+ _D3std7cstream5CFile10writeBlockMFxPvkZk@Base 6
+ _D3std7cstream5CFile10writeLineWMFAxuZv@Base 6
+ _D3std7cstream5CFile3eofMFZb@Base 6
+ _D3std7cstream5CFile4fileMFNdPOS4core4stdc5stdio8_IO_FILEZv@Base 6
+ _D3std7cstream5CFile4fileMFNdZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std7cstream5CFile4getcMFZa@Base 6
+ _D3std7cstream5CFile4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std7cstream5CFile5closeMFZv@Base 6
+ _D3std7cstream5CFile5flushMFZv@Base 6
+ _D3std7cstream5CFile6__ctorMFPOS4core4stdc5stdio8_IO_FILEE3std6stream8FileModebZC3std7cstream5CFile@Base 6
+ _D3std7cstream5CFile6__dtorMFZv@Base 6
+ _D3std7cstream5CFile6__initZ@Base 6
+ _D3std7cstream5CFile6__vtblZ@Base 6
+ _D3std7cstream5CFile6ungetcMFaZa@Base 6
+ _D3std7cstream5CFile7__ClassZ@Base 6
+ _D3std7cstream5CFile9readBlockMFPvkZk@Base 6
+ _D3std7cstream5CFile9writeLineMFAxaZv@Base 6
+ _D3std7numeric12__ModuleInfoZ@Base 6
+ _D3std7numeric12isPowerOfTwoFkZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride11__xopEqualsFKxS3std7numeric14__T6StrideTAfZ6StrideKxS3std7numeric14__T6StrideTAfZ6StrideZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride11doubleStepsMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride4saveMFNaNbNdNiNfZS3std7numeric14__T6StrideTAfZ6Stride@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride5frontMFNaNbNdNiNfZf@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6__ctorMFNaNbNcNiNfAfkZS3std7numeric14__T6StrideTAfZ6Stride@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6__initZ@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6nStepsMFNaNbNdNiNfkZk@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6nStepsMxFNaNbNdNiNfZk@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride7opIndexMFNaNbNiNfkZf@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride7popHalfMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride8popFrontMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride9__xtoHashFNbNeKxS3std7numeric14__T6StrideTAfZ6StrideZk@Base 6
+ _D3std7numeric16CustomFloatFlags6__initZ@Base 6
+ _D3std7numeric19roundDownToPowerOf2FkZk@Base 6
+ _D3std7numeric24__T13oppositeSignsTyeTeZ13oppositeSignsFNaNbNiNfyeeZb@Base 6
+ _D3std7numeric29__T8findRootTeTDFNaNbNiNfeZeZ8findRootFMDFNaNbNiNfeZexexeZ9__lambda4FNaNbNiNfeeZb@Base 6
+ _D3std7numeric29__T8findRootTeTDFNaNbNiNfeZeZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexeZe@Base 6
+ _D3std7numeric3Fft4sizeMxFNdZk@Base 6
+ _D3std7numeric3Fft6__ctorMFAfZC3std7numeric3Fft@Base 6
+ _D3std7numeric3Fft6__ctorMFkZC3std7numeric3Fft@Base 6
+ _D3std7numeric3Fft6__initZ@Base 6
+ _D3std7numeric3Fft6__vtblZ@Base 6
+ _D3std7numeric3Fft7__ClassZ@Base 6
+ _D3std7numeric44__T8findRootTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexeMPFNaNbNiNfeeZbZe@Base 6
+ _D3std7numeric46__T8findRootTeTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFMDFNaNbNiNfeZexexexexeMPFNaNbNiNfeeZbZ18secant_interpolateFNaNbNiNfeeeeZe@Base 6
+ _D3std7numeric46__T8findRootTeTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexexexeMPFNaNbNiNfeeZbZS3std8typecons18__T5TupleTeTeTeTeZ5Tuple@Base 6
+ _D3std7numeric5bsr64FmZ5Ulong6__initZ@Base 6
+ _D3std7numeric5bsr64FmZi@Base 6
+ _D3std7process10setCLOEXECFibZv@Base 6
+ _D3std7process10spawnShellFNexAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process10spawnShellFNexAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process10toAStringzFxAAyaPPxaZv@Base 6
+ _D3std7process11environment13opIndexAssignFNeNgAaxAaZANga@Base 6
+ _D3std7process11environment3getFNfxAaAyaZAya@Base 6
+ _D3std7process11environment4toAAFNeZHAyaAya@Base 6
+ _D3std7process11environment6__initZ@Base 6
+ _D3std7process11environment6__vtblZ@Base 6
+ _D3std7process11environment6removeFNbNiNexAaZv@Base 6
+ _D3std7process11environment7__ClassZ@Base 6
+ _D3std7process11environment7getImplFNexAaJAyaZ10lastResultAya@Base 6
+ _D3std7process11environment7getImplFNexAaJAyaZb@Base 6
+ _D3std7process11environment7opIndexFNfxAaZAya@Base 6
+ _D3std7process11pipeProcessFNfxAAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process11pipeProcessFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process11shellSwitchyAa@Base 6
+ _D3std7process12ProcessPipes11__fieldDtorMFNeZv@Base 6
+ _D3std7process12ProcessPipes11__xopEqualsFKxS3std7process12ProcessPipesKxS3std7process12ProcessPipesZb@Base 6
+ _D3std7process12ProcessPipes15__fieldPostblitMFNeZv@Base 6
+ _D3std7process12ProcessPipes3pidMFNbNdNfZC3std7process3Pid@Base 6
+ _D3std7process12ProcessPipes5stdinMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes6__initZ@Base 6
+ _D3std7process12ProcessPipes6stderrMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes6stdoutMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes8opAssignMFNcNjNeS3std7process12ProcessPipesZS3std7process12ProcessPipes@Base 6
+ _D3std7process12ProcessPipes9__xtoHashFNbNeKxS3std7process12ProcessPipesZk@Base 6
+ _D3std7process12__ModuleInfoZ@Base 6
+ _D3std7process12executeShellFNexAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process12isExecutableFNbNiNexAaZb@Base 6
+ _D3std7process12spawnProcessFNexAAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process136__T11executeImplS111_D3std7process9pipeShellFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipesTAxaZ11executeImplFAxaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process13charAllocatorFNaNbNfkZAa@Base 6
+ _D3std7process13searchPathForFNexAaZAya@Base 6
+ _D3std7process13thisProcessIDFNbNdNeZi@Base 6
+ _D3std7process16ProcessException12newFromErrnoFAyaAyakZC3std7process16ProcessException@Base 6
+ _D3std7process16ProcessException6__ctorMFAyaAyakZC3std7process16ProcessException@Base 6
+ _D3std7process16ProcessException6__initZ@Base 6
+ _D3std7process16ProcessException6__vtblZ@Base 6
+ _D3std7process16ProcessException7__ClassZ@Base 6
+ _D3std7process16spawnProcessImplFNexAAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process18escapeShellCommandFNaNfxAAaXAya@Base 6
+ _D3std7process19escapePosixArgumentFNaNbNexAaZAya@Base 6
+ _D3std7process19escapeShellFileNameFNaNbNexAaZAya@Base 6
+ _D3std7process20escapeShellArgumentsFNaNbNexAAaX9allocatorMFNaNbNfkZAa@Base 6
+ _D3std7process20escapeShellArgumentsFNaNbNexAAaXAya@Base 6
+ _D3std7process21escapeWindowsArgumentFNaNbNexAaZAya@Base 6
+ _D3std7process24escapeShellCommandStringFNaNfAyaZAya@Base 6
+ _D3std7process25escapeWindowsShellCommandFNaNfxAaZAya@Base 6
+ _D3std7process3Pid11performWaitMFNebZi@Base 6
+ _D3std7process3Pid6__ctorMFNaNbNfiZC3std7process3Pid@Base 6
+ _D3std7process3Pid6__initZ@Base 6
+ _D3std7process3Pid6__vtblZ@Base 6
+ _D3std7process3Pid7__ClassZ@Base 6
+ _D3std7process3Pid8osHandleMFNaNbNdNfZi@Base 6
+ _D3std7process3Pid9processIDMxFNaNbNdNfZi@Base 6
+ _D3std7process49__T11executeImplS253std7process11pipeProcessTAxaZ11executeImplFAxaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process4Pipe11__fieldDtorMFNeZv@Base 6
+ _D3std7process4Pipe11__xopEqualsFKxS3std7process4PipeKxS3std7process4PipeZb@Base 6
+ _D3std7process4Pipe15__fieldPostblitMFNeZv@Base 6
+ _D3std7process4Pipe5closeMFNfZv@Base 6
+ _D3std7process4Pipe6__initZ@Base 6
+ _D3std7process4Pipe7readEndMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process4Pipe8opAssignMFNcNjNeS3std7process4PipeZS3std7process4Pipe@Base 6
+ _D3std7process4Pipe8writeEndMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process4Pipe9__xtoHashFNbNeKxS3std7process4PipeZk@Base 6
+ _D3std7process4killFC3std7process3PidZv@Base 6
+ _D3std7process4killFC3std7process3PidiZv@Base 6
+ _D3std7process4pipeFNeZS3std7process4Pipe@Base 6
+ _D3std7process4waitFNfC3std7process3PidZi@Base 6
+ _D3std7process50__T11executeImplS253std7process11pipeProcessTAxAaZ11executeImplFAxAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process52__T15pipeProcessImplS243std7process10spawnShellTAxaZ15pipeProcessImplFNeAxaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process54__T15pipeProcessImplS263std7process12spawnProcessTAxaZ15pipeProcessImplFNeAxaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process55__T15pipeProcessImplS263std7process12spawnProcessTAxAaZ15pipeProcessImplFNeAxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process5execvFxAyaxAAyaZi@Base 6
+ _D3std7process5shellFAyaZAya@Base 6
+ _D3std7process6browseFAyaZv@Base 6
+ _D3std7process6execv_FxAyaxAAyaZi@Base 6
+ _D3std7process6execveFxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process6execvpFxAyaxAAyaZi@Base 6
+ _D3std7process6getenvFNbxAaZ10lastResultAya@Base 6
+ _D3std7process6getenvFNbxAaZAya@Base 6
+ _D3std7process6setenvFxAaxAabZv@Base 6
+ _D3std7process6systemFAyaZi@Base 6
+ _D3std7process72__T23escapePosixArgumentImplS40_D3std7process13charAllocatorFNaNbNfkZAaZ23escapePosixArgumentImplFNaNbNfxAaZAa@Base 6
+ _D3std7process74__T25escapeWindowsArgumentImplS40_D3std7process13charAllocatorFNaNbNfkZAaZ25escapeWindowsArgumentImplFNaNbNfxAaZAa@Base 6
+ _D3std7process7executeFNexAAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process7executeFNexAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process7execve_FxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process7execvp_FxAyaxAAyaZi@Base 6
+ _D3std7process7execvpeFxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process7spawnvpFiAyaAAyaZi@Base 6
+ _D3std7process7tryWaitFNfC3std7process3PidZS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple@Base 6
+ _D3std7process8Redirect6__initZ@Base 6
+ _D3std7process8_spawnvpFixPaxPPaZi@Base 6
+ _D3std7process8execvpe_FxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process8unsetenvFxAaZv@Base 6
+ _D3std7process9createEnvFxHAyaAyabZPxPa@Base 6
+ _D3std7process9pipeShellFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process9userShellFNdNfZAya@Base 6
+ _D3std7signals12__ModuleInfoZ@Base 6
+ _D3std7signals6linkinFZv@Base 6
+ _D3std7variant12__ModuleInfoZ@Base 6
+ _D3std7variant16VariantException6__ctorMFAyaZC3std7variant16VariantException@Base 6
+ _D3std7variant16VariantException6__ctorMFC8TypeInfoC8TypeInfoZC3std7variant16VariantException@Base 6
+ _D3std7variant16VariantException6__initZ@Base 6
+ _D3std7variant16VariantException6__vtblZ@Base 6
+ _D3std7variant16VariantException7__ClassZ@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN10__T3getTbZ3getMNgFNdZNgb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN10__T3getTiZ3getMNgFNdZNgi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN10__T3getTkZ3getMNgFNdZNgk@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN10__postblitMFZv@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN113__T3getTS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ3getMNgFNdZNgS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN115__T3getTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ3getMNgFNdZNgS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN118__T6__ctorTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ6__ctorMFNcS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ10tryPuttingFPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ6getPtrFNaNbNiPvZPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ7compareFPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TuplePS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleE3std7variant18__T8VariantNVki24Z8VariantN4OpIDZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN11SizeChecker6__initZ@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN11__T3getTyhZ3getMNgFNdZyh@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN11__T4peekTvZ4peekMNgFNdZPNgv@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN11__xopEqualsFKxS3std7variant18__T8VariantNVki24Z8VariantNKxS3std7variant18__T8VariantNVki24Z8VariantNZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN120__T8opAssignTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opAssignMFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN121__T10convertsToTS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN123__T10convertsToTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN12__T3getTAyhZ3getMNgFNdZNgAyh@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN15__T6__ctorTAyhZ6__ctorMFNcAyhZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN15__T7handlerHTvZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ10tryPuttingFPyhC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ6getPtrFNaNbNiPvZPyh@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ7compareFNaNbNiNfPyhPyhE3std7variant18__T8VariantNVki24Z8VariantN4OpIDZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ10tryPuttingFPAyhC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ6getPtrFNaNbNiPvZPAyh@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ7compareFNaNbNiNfPAyhPAyhE3std7variant18__T8VariantNVki24Z8VariantN4OpIDZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN16__T8opAssignTyhZ8opAssignMFyhZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN17__T8opAssignTAyhZ8opAssignMFAyhZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN18__T10convertsToTbZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN18__T10convertsToTiZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN19__T10convertsToTyhZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN20__T10convertsToTAyhZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN27__T3getTC6object9ThrowableZ3getMNgFNdZNgC6object9Throwable@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN28__T3getTOC6object9ThrowableZ3getMNgFNdZONgC6object9Throwable@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN31__T3getTS3std11concurrency3TidZ3getMNgFNdZNgS3std11concurrency3Tid@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN34__T6__ctorTS3std11concurrency3TidZ6__ctorMFNcS3std11concurrency3TidZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN35__T10convertsToTC6object9ThrowableZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ10tryPuttingFPS3std11concurrency3TidC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ6getPtrFNaNbNiPvZPS3std11concurrency3Tid@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ7compareFPS3std11concurrency3TidPS3std11concurrency3TidE3std7variant18__T8VariantNVki24Z8VariantN4OpIDZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN36__T10convertsToTOC6object9ThrowableZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN36__T8opAssignTS3std11concurrency3TidZ8opAssignMFS3std11concurrency3TidZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN39__T10convertsToTS3std11concurrency3TidZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN46__T6__ctorTC3std11concurrency14LinkTerminatedZ6__ctorMFNcC3std11concurrency14LinkTerminatedZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN47__T6__ctorTC3std11concurrency15OwnerTerminatedZ6__ctorMFNcC3std11concurrency15OwnerTerminatedZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ10tryPuttingFPC3std11concurrency14LinkTerminatedC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ6getPtrFNaNbNiPvZPC3std11concurrency14LinkTerminated@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ7compareFPC3std11concurrency14LinkTerminatedPC3std11concurrency14LinkTerminatedE3std7variant18__T8VariantNVki24Z8VariantN4OpIDZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ10tryPuttingFPC3std11concurrency15OwnerTerminatedC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ6getPtrFNaNbNiPvZPC3std11concurrency15OwnerTerminated@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZ7compareFPC3std11concurrency15OwnerTerminatedPC3std11concurrency15OwnerTerminatedE3std7variant18__T8VariantNVki24Z8VariantN4OpIDZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki24Z8VariantN4OpIDPG24hPvZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN48__T8opAssignTC3std11concurrency14LinkTerminatedZ8opAssignMFC3std11concurrency14LinkTerminatedZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN49__T8opAssignTC3std11concurrency15OwnerTerminatedZ8opAssignMFC3std11concurrency15OwnerTerminatedZS3std7variant18__T8VariantNVki24Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN4typeMxFNbNdNeZC8TypeInfo@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN53__T5opCmpTS3std7variant18__T8VariantNVki24Z8VariantNZ5opCmpMFS3std7variant18__T8VariantNVki24Z8VariantNZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN56__T8opEqualsTS3std7variant18__T8VariantNVki24Z8VariantNZ8opEqualsMxFKS3std7variant18__T8VariantNVki24Z8VariantNZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN57__T8opEqualsTxS3std7variant18__T8VariantNVki24Z8VariantNZ8opEqualsMxFKxS3std7variant18__T8VariantNVki24Z8VariantNZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN5opCmpMxFKxS3std7variant18__T8VariantNVki24Z8VariantNZi@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN6__dtorMFZv@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN6__initZ@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN6lengthMFNdZk@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN6toHashMxFNbNfZk@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN8hasValueMxFNaNbNdNiNfZb@Base 6
+ _D3std7variant18__T8VariantNVki24Z8VariantN8toStringMFZAya@Base 6
+ _D3std7windows7charset12__ModuleInfoZ@Base 6
+ _D3std7windows8iunknown12__ModuleInfoZ@Base 6
+ _D3std7windows8registry12__ModuleInfoZ@Base 6
+ _D3std7windows8syserror12__ModuleInfoZ@Base 6
+ _D3std8bitmanip10myToStringFmZAya@Base 6
+ _D3std8bitmanip11myToStringxFmZAya@Base 6
+ _D3std8bitmanip12__ModuleInfoZ@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet4saveMFNaNbNdNiNfZS3std8bitmanip14__T7BitsSetTkZ7BitsSet@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet5frontMFNaNbNdNiNfZk@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet6__ctorMFNaNbNcNiNfkkZS3std8bitmanip14__T7BitsSetTkZ7BitsSet@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet6__initZ@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNekZk@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNemZm@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNftZt@Base 6
+ _D3std8bitmanip15getBitsForAlignFmZm@Base 6
+ _D3std8bitmanip18__T10swapEndianTaZ10swapEndianFNaNbNiNfaZa@Base 6
+ _D3std8bitmanip18__T10swapEndianTbZ10swapEndianFNaNbNiNfbZb@Base 6
+ _D3std8bitmanip18__T10swapEndianThZ10swapEndianFNaNbNiNfhZh@Base 6
+ _D3std8bitmanip18__T10swapEndianTiZ10swapEndianFNaNbNiNfiZi@Base 6
+ _D3std8bitmanip18__T10swapEndianTlZ10swapEndianFNaNbNiNflZl@Base 6
+ _D3std8bitmanip18__T10swapEndianTmZ10swapEndianFNaNbNiNfmZm@Base 6
+ _D3std8bitmanip20__T12countBitsSetTkZ12countBitsSetFNaNbNiNfkZk@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTaZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTbZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperThZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTiZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTkZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTlZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTmZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTtZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip22__T13EndianSwapperTxkZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip26__T18countTrailingZerosTkZ18countTrailingZerosFNaNbNiNfkZk@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTkZ20nativeToLittleEndianFNaNbNiNfkZG4h@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTmZ20nativeToLittleEndianFNaNbNiNfmZG8h@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTtZ20nativeToLittleEndianFNaNbNiNftZG2h@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTaVki1Z17bigEndianToNativeFNaNbNiNfG1hZa@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTbVki1Z17bigEndianToNativeFNaNbNiNfG1hZb@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeThVki1Z17bigEndianToNativeFNaNbNiNfG1hZh@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTiVki4Z17bigEndianToNativeFNaNbNiNfG4hZi@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTlVki8Z17bigEndianToNativeFNaNbNiNfG8hZl@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTmVki8Z17bigEndianToNativeFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip29__T20nativeToLittleEndianTxkZ20nativeToLittleEndianFNaNbNiNfxkZG4h@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTkVki4Z20littleEndianToNativeFNaNbNiNfG4hZk@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTmVki8Z20littleEndianToNativeFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTtVki2Z20littleEndianToNativeFNaNbNiNfG2hZt@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTkZ24nativeToLittleEndianImplFNaNbNiNfkZG4h@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTmZ24nativeToLittleEndianImplFNaNbNiNfmZG8h@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTtZ24nativeToLittleEndianImplFNaNbNiNftZG2h@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTaVki1Z21bigEndianToNativeImplFNaNbNiNfG1hZa@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTbVki1Z21bigEndianToNativeImplFNaNbNiNfG1hZb@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplThVki1Z21bigEndianToNativeImplFNaNbNiNfG1hZh@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTiVki4Z21bigEndianToNativeImplFNaNbNiNfG4hZi@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTlVki8Z21bigEndianToNativeImplFNaNbNiNfG8hZl@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTmVki8Z21bigEndianToNativeImplFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip33__T24nativeToLittleEndianImplTxkZ24nativeToLittleEndianImplFNaNbNiNfxkZG4h@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTkVki4Z24littleEndianToNativeImplFNaNbNiNfG4hZk@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTmVki8Z24littleEndianToNativeImplFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTtVki2Z24littleEndianToNativeImplFNaNbNiNfG2hZt@Base 6
+ _D3std8bitmanip8BitArray11opCatAssignMFNaNbS3std8bitmanip8BitArrayZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray11opCatAssignMFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray13opIndexAssignMFNaNbNibkZb@Base 6
+ _D3std8bitmanip8BitArray14formatBitArrayMxFMDFAxaZvZv@Base 6
+ _D3std8bitmanip8BitArray15formatBitStringMxFMDFAxaZvZv@Base 6
+ _D3std8bitmanip8BitArray3dimMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray3dupMxFNaNbNdZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray4initMFNaNbAbZv@Base 6
+ _D3std8bitmanip8BitArray4initMFNaNbAvkZv@Base 6
+ _D3std8bitmanip8BitArray4sortMFNaNbNdNiZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCatMxFNaNbS3std8bitmanip8BitArrayZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCatMxFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCmpMxFNaNbNiS3std8bitmanip8BitArrayZi@Base 6
+ _D3std8bitmanip8BitArray5opComMxFNaNbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNaNbNcAbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNaNbNcAvkZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNckPkZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__initZ@Base 6
+ _D3std8bitmanip8BitArray6lengthMFNaNbNdkZk@Base 6
+ _D3std8bitmanip8BitArray6lengthMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray6toHashMxFNaNbNiZk@Base 6
+ _D3std8bitmanip8BitArray7bitsSetMxFNaNbNdZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std8bitmanip8BitArray7endBitsMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray7endMaskMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray7opApplyMFMDFKbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMFMDFkKbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMxFMDFbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMxFMDFkbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opCat_rMxFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray7opIndexMxFNaNbNikZb@Base 6
+ _D3std8bitmanip8BitArray7reverseMFNaNbNdNiZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray8lenToDimFNaNbNikZk@Base 6
+ _D3std8bitmanip8BitArray8opEqualsMxFNaNbNiKxS3std8bitmanip8BitArrayZb@Base 6
+ _D3std8bitmanip8BitArray8toStringMxFMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std8bitmanip8BitArray9fullWordsMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8FloatRep11__xopEqualsFKxS3std8bitmanip8FloatRepKxS3std8bitmanip8FloatRepZb@Base 6
+ _D3std8bitmanip8FloatRep4signMFNaNbNdNiNfbZv@Base 6
+ _D3std8bitmanip8FloatRep4signMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip8FloatRep6__initZ@Base 6
+ _D3std8bitmanip8FloatRep8exponentMFNaNbNdNiNfhZv@Base 6
+ _D3std8bitmanip8FloatRep8exponentMxFNaNbNdNiNfZh@Base 6
+ _D3std8bitmanip8FloatRep8fractionMFNaNbNdNiNfkZv@Base 6
+ _D3std8bitmanip8FloatRep8fractionMxFNaNbNdNiNfZk@Base 6
+ _D3std8bitmanip8FloatRep9__xtoHashFNbNeKxS3std8bitmanip8FloatRepZk@Base 6
+ _D3std8bitmanip9DoubleRep11__xopEqualsFKxS3std8bitmanip9DoubleRepKxS3std8bitmanip9DoubleRepZb@Base 6
+ _D3std8bitmanip9DoubleRep4signMFNaNbNdNiNfbZv@Base 6
+ _D3std8bitmanip9DoubleRep4signMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip9DoubleRep6__initZ@Base 6
+ _D3std8bitmanip9DoubleRep8exponentMFNaNbNdNiNftZv@Base 6
+ _D3std8bitmanip9DoubleRep8exponentMxFNaNbNdNiNfZt@Base 6
+ _D3std8bitmanip9DoubleRep8fractionMFNaNbNdNiNfmZv@Base 6
+ _D3std8bitmanip9DoubleRep8fractionMxFNaNbNdNiNfZm@Base 6
+ _D3std8bitmanip9DoubleRep9__xtoHashFNbNeKxS3std8bitmanip9DoubleRepZk@Base 6
+ _D3std8compiler12__ModuleInfoZ@Base 6
+ _D3std8compiler13version_majoryk@Base 6
+ _D3std8compiler13version_minoryk@Base 6
+ _D3std8compiler4nameyAa@Base 6
+ _D3std8compiler6vendoryE3std8compiler6Vendor@Base 6
+ _D3std8compiler7D_majoryk@Base 6
+ _D3std8compiler7D_minoryk@Base 6
+ _D3std8datetime11_monthNamesyG12Aa@Base 6
+ _D3std8datetime11lastDayLeapyG13i@Base 6
+ _D3std8datetime11setTZEnvVarFNbNeAyaZv@Base 6
+ _D3std8datetime11timeStringsyAAa@Base 6
+ _D3std8datetime12__ModuleInfoZ@Base 6
+ _D3std8datetime12cmpTimeUnitsFNaNfAyaAyaZi@Base 6
+ _D3std8datetime12getDayOfWeekFNaNbNfiZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime13PosixTimeZone10LeapSecond6__ctorMFNaNcNfliZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone10TempTTInfo6__ctorMFNaNcNfibhZS3std8datetime13PosixTimeZone10TempTTInfo@Base 6
+ _D3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone10Transition6__ctorMFNaNcNflPyS3std8datetime13PosixTimeZone6TTInfoZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime13PosixTimeZone11getTimeZoneFNeAyaAyaZyC3std8datetime13PosixTimeZone@Base 6
+ _D3std8datetime13PosixTimeZone14TempTransition6__ctorMFNaNcNflPyS3std8datetime13PosixTimeZone6TTInfoPS3std8datetime13PosixTimeZone14TransitionTypeZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone14TransitionType6__ctorMFNaNcNfbbZS3std8datetime13PosixTimeZone14TransitionType@Base 6
+ _D3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTaZ7readValFNeKS3std5stdio4FileZa@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTbZ7readValFNeKS3std5stdio4FileZb@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValThZ7readValFNeKS3std5stdio4FileZh@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTiZ7readValFNeKS3std5stdio4FileZi@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTlZ7readValFNeKS3std5stdio4FileZl@Base 6
+ _D3std8datetime13PosixTimeZone15__T7readValTAaZ7readValFNeKS3std5stdio4FilekZAa@Base 6
+ _D3std8datetime13PosixTimeZone15__T7readValTAhZ7readValFNeKS3std5stdio4FilekZAh@Base 6
+ _D3std8datetime13PosixTimeZone19_enforceValidTZFileFNaNfbkZv@Base 6
+ _D3std8datetime13PosixTimeZone19getInstalledTZNamesFNeAyaAyaZAAya@Base 6
+ _D3std8datetime13PosixTimeZone20calculateLeapSecondsMxFNaNbNflZi@Base 6
+ _D3std8datetime13PosixTimeZone54__T7readValTS3std8datetime13PosixTimeZone10TempTTInfoZ7readValFNfKS3std5stdio4FileZS3std8datetime13PosixTimeZone10TempTTInfo@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo11__xopEqualsFKxS3std8datetime13PosixTimeZone6TTInfoKxS3std8datetime13PosixTimeZone6TTInfoZb@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo6__ctorMyFNaNcNfxS3std8datetime13PosixTimeZone10TempTTInfoAyaZyS3std8datetime13PosixTimeZone6TTInfo@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo9__xtoHashFNbNeKxS3std8datetime13PosixTimeZone6TTInfoZk@Base 6
+ _D3std8datetime13PosixTimeZone6__ctorMyFNaNfyAS3std8datetime13PosixTimeZone10TransitionyAS3std8datetime13PosixTimeZone10LeapSecondAyaAyaAyabZyC3std8datetime13PosixTimeZone@Base 6
+ _D3std8datetime13PosixTimeZone6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone6__vtblZ@Base 6
+ _D3std8datetime13PosixTimeZone6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime13PosixTimeZone7__ClassZ@Base 6
+ _D3std8datetime13PosixTimeZone7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime13PosixTimeZone7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime13clearTZEnvVarFNbNeZv@Base 6
+ _D3std8datetime13monthToStringFNaNfE3std8datetime5MonthZAya@Base 6
+ _D3std8datetime13monthsToMonthFNaNfiiZi@Base 6
+ _D3std8datetime14SimpleTimeZone11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime14SimpleTimeZone11toISOStringFNaNfS4core4time8DurationZAya@Base 6
+ _D3std8datetime14SimpleTimeZone11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime14SimpleTimeZone6__ctorMyFNaNfS4core4time8DurationAyaZyC3std8datetime14SimpleTimeZone@Base 6
+ _D3std8datetime14SimpleTimeZone6__ctorMyFNaNfiAyaZyC3std8datetime14SimpleTimeZone@Base 6
+ _D3std8datetime14SimpleTimeZone6__initZ@Base 6
+ _D3std8datetime14SimpleTimeZone6__vtblZ@Base 6
+ _D3std8datetime14SimpleTimeZone6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime14SimpleTimeZone7__ClassZ@Base 6
+ _D3std8datetime14SimpleTimeZone7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime14SimpleTimeZone7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime14SimpleTimeZone9utcOffsetMxFNaNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime14lastDayNonLeapyG13i@Base 6
+ _D3std8datetime14validTimeUnitsFNaNbNfAAyaXb@Base 6
+ _D3std8datetime14yearIsLeapYearFNaNbNfiZb@Base 6
+ _D3std8datetime15daysToDayOfWeekFNaNbNfE3std8datetime9DayOfWeekE3std8datetime9DayOfWeekZi@Base 6
+ _D3std8datetime15monthFromStringFNaNfAyaZE3std8datetime5Month@Base 6
+ _D3std8datetime16cmpTimeUnitsCTFEFNaNbNfAyaAyaZi@Base 6
+ _D3std8datetime17stdTimeToUnixTimeFNaNbNflZi@Base 6
+ _D3std8datetime17unixTimeToStdTimeFNaNbNfiZl@Base 6
+ _D3std8datetime19fracSecsToISOStringFNaNbNfiZAya@Base 6
+ _D3std8datetime20DosFileTimeToSysTimeFNfkyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime20SysTimeToDosFileTimeFNfS3std8datetime7SysTimeZk@Base 6
+ _D3std8datetime24ComparingBenchmarkResult10targetTimeMxFNaNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime24ComparingBenchmarkResult5pointMxFNaNbNdNfZe@Base 6
+ _D3std8datetime24ComparingBenchmarkResult6__ctorMFNaNbNcNfS4core4time12TickDurationS4core4time12TickDurationZS3std8datetime24ComparingBenchmarkResult@Base 6
+ _D3std8datetime24ComparingBenchmarkResult6__initZ@Base 6
+ _D3std8datetime24ComparingBenchmarkResult8baseTimeMxFNaNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime25__T5validVAyaa4_64617973Z5validFNaNbNfiiiZb@Base 6
+ _D3std8datetime27__T5validVAyaa5_686f757273Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime29__T5validVAyaa6_6d6f6e746873Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime29tzDatabaseNameToWindowsTZNameFNaNbNiNfAyaZAya@Base 6
+ _D3std8datetime29windowsTZNameToTZDatabaseNameFNaNbNiNfAyaZAya@Base 6
+ _D3std8datetime31__T5validVAyaa7_6d696e75746573Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime31__T5validVAyaa7_7365636f6e6473Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime33__T12enforceValidVAyaa4_64617973Z12enforceValidFNaNfiE3std8datetime5MonthiAyakZv@Base 6
+ _D3std8datetime35__T12enforceValidVAyaa5_686f757273Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime37__T12enforceValidVAyaa6_6d6f6e746873Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime39__T12enforceValidVAyaa7_6d696e75746573Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime39__T12enforceValidVAyaa7_7365636f6e6473Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime39__T18getUnitsFromHNSecsVAyaa4_64617973Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime3UTC11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime3UTC11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime3UTC4_utcyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC6__ctorMyFNaNfZyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC6__initZ@Base 6
+ _D3std8datetime3UTC6__vtblZ@Base 6
+ _D3std8datetime3UTC6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime3UTC6opCallFNaNbNfZyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC7__ClassZ@Base 6
+ _D3std8datetime3UTC7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime3UTC7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime41__T18getUnitsFromHNSecsVAyaa5_686f757273Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime41__T20splitUnitsFromHNSecsVAyaa4_64617973Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime42__T21removeUnitsFromHNSecsVAyaa4_64617973Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime44__T21removeUnitsFromHNSecsVAyaa5_686f757273Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime45__T18getUnitsFromHNSecsVAyaa7_6d696e75746573Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime48__T21removeUnitsFromHNSecsVAyaa7_6d696e75746573Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime48__T21removeUnitsFromHNSecsVAyaa7_7365636f6e6473Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime4Date10diffMonthsMxFNaNbNfxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date10endOfMonthMxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date10isLeapYearMxFNaNbNdNfZb@Base 6
+ _D3std8datetime4Date11__invariantMxFNaNfZv@Base 6
+ _D3std8datetime4Date11daysInMonthMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date12modJulianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime4Date14__invariant173MxFNaNfZv@Base 6
+ _D3std8datetime4Date14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date14toSimpleStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date17dayOfGregorianCalMFNaNbNdNfiZv@Base 6
+ _D3std8datetime4Date17dayOfGregorianCalMxFNaNbNdNfZi@Base 6
+ _D3std8datetime4Date22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNfxS3std8datetime4DateZS4core4time8Duration@Base 6
+ _D3std8datetime4Date3dayMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date3dayMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date3maxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date3minFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date4isADMxFNaNbNdNfZb@Base 6
+ _D3std8datetime4Date4yearMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date4yearMxFNaNbNdNfZs@Base 6
+ _D3std8datetime4Date5monthMFNaNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime4Date5monthMxFNaNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime4Date5opCmpMxFNaNbNfxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date6__ctorMFNaNbNcNfiZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date6__ctorMFNaNcNfiiiZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date6__initZ@Base 6
+ _D3std8datetime4Date6_validFNaNbNfiiiZb@Base 6
+ _D3std8datetime4Date6yearBCMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date6yearBCMxFNaNdNfZt@Base 6
+ _D3std8datetime4Date7isoWeekMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date8__xopCmpFKxS3std8datetime4DateKxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date8_addDaysMFNaNbNcNjNflZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date8toStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date9dayOfWeekMxFNaNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime4Date9dayOfYearMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date9dayOfYearMxFNaNbNdNfZt@Base 6
+ _D3std8datetime4Date9julianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime5Clock11currAppTickFNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime5Clock11currStdTimeFNdNeZl@Base 6
+ _D3std8datetime5Clock14currSystemTickFNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime5Clock6__ctorMFZC3std8datetime5Clock@Base 6
+ _D3std8datetime5Clock6__initZ@Base 6
+ _D3std8datetime5Clock6__vtblZ@Base 6
+ _D3std8datetime5Clock7__ClassZ@Base 6
+ _D3std8datetime5Clock8currTimeFNfyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime5Month6__initZ@Base 6
+ _D3std8datetime6maxDayFNaNbNfiiZh@Base 6
+ _D3std8datetime7SysTime10diffMonthsMxFNbNfxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime10endOfMonthMxFNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime10isLeapYearMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime10toUnixTimeMxFNaNbNfZi@Base 6
+ _D3std8datetime7SysTime11daysInMonthMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime11dstInEffectMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime11toISOStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime11toLocalTimeMxFNaNbNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime12modJulianDayMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime14toISOExtStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime14toSimpleStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime17dayOfGregorianCalMFNbNdNfiZv@Base 6
+ _D3std8datetime7SysTime17dayOfGregorianCalMxFNbNdNfZi@Base 6
+ _D3std8datetime7SysTime31__T6opCastTS3std8datetime4DateZ6opCastMxFNbNfZS3std8datetime4Date@Base 6
+ _D3std8datetime7SysTime35__T6opCastTS3std8datetime8DateTimeZ6opCastMxFNbNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime7SysTime3dayMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime3dayMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime3maxFNaNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime3minFNaNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime4hourMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime4hourMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime4isADMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime4toTMMxFNbNfZS4core4stdc4time2tm@Base 6
+ _D3std8datetime7SysTime4yearMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime4yearMxFNbNdNfZs@Base 6
+ _D3std8datetime7SysTime5monthMFNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime7SysTime5monthMxFNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime7SysTime5opCmpMxFNaNbNfxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime5toUTCMxFNaNbNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNaNbNcNflyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNbNcNfxS3std8datetime4DateyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNbNcNfxS3std8datetime8DateTimeyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNcNfxS3std8datetime8DateTimexS4core4time7FracSecyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNcNfxS3std8datetime8DateTimexS4core4time8DurationyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__initZ@Base 6
+ _D3std8datetime7SysTime6minuteMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6minuteMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime6secondMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6secondMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime6yearBCMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6yearBCMxFNdNfZt@Base 6
+ _D3std8datetime7SysTime7adjTimeMFNbNdNflZv@Base 6
+ _D3std8datetime7SysTime7adjTimeMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime7fracSecMFNdNfS4core4time7FracSecZv@Base 6
+ _D3std8datetime7SysTime7fracSecMxFNbNdNfZS4core4time7FracSec@Base 6
+ _D3std8datetime7SysTime7isoWeekMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime7stdTimeMFNaNbNdNflZv@Base 6
+ _D3std8datetime7SysTime7stdTimeMxFNaNbNdNfZl@Base 6
+ _D3std8datetime7SysTime8__xopCmpFKxS3std8datetime7SysTimeKxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime8fracSecsMFNdNfS4core4time8DurationZv@Base 6
+ _D3std8datetime7SysTime8fracSecsMxFNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime7SysTime8opAssignMFNaNbNcNjNfKxS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime8opAssignMFNaNbNcNjNfS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime8opEqualsMxFNaNbNfKxS3std8datetime7SysTimeZb@Base 6
+ _D3std8datetime7SysTime8opEqualsMxFNaNbNfxS3std8datetime7SysTimeZb@Base 6
+ _D3std8datetime7SysTime8timezoneMFNaNbNdNfyC3std8datetime8TimeZoneZv@Base 6
+ _D3std8datetime7SysTime8timezoneMxFNaNbNdNfZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime7SysTime8toStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime9__xtoHashFNbNeKxS3std8datetime7SysTimeZk@Base 6
+ _D3std8datetime7SysTime9dayOfWeekMxFNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime7SysTime9dayOfYearMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime9dayOfYearMxFNbNdNfZt@Base 6
+ _D3std8datetime7SysTime9julianDayMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime9toOtherTZMxFNaNbNfyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime9toTimeValMxFNaNbNfZS4core3sys5posix3sys4time7timeval@Base 6
+ _D3std8datetime7SysTime9utcOffsetMxFNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime8DateTime10diffMonthsMxFNaNbNfxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime10endOfMonthMxFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime10isLeapYearMxFNaNbNdNfZb@Base 6
+ _D3std8datetime8DateTime11_addSecondsMFNaNbNcNjNflZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime11daysInMonthMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime12modJulianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime8DateTime14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime14toSimpleStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime17dayOfGregorianCalMFNaNbNdNfiZv@Base 6
+ _D3std8datetime8DateTime17dayOfGregorianCalMxFNaNbNdNfZi@Base 6
+ _D3std8datetime8DateTime3dayMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime3dayMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime3maxFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime3minFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime4dateMFNaNbNdNfxS3std8datetime4DateZv@Base 6
+ _D3std8datetime8DateTime4dateMxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime8DateTime4hourMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime4hourMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime4isADMxFNaNbNdNfZb@Base 6
+ _D3std8datetime8DateTime4yearMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime4yearMxFNaNbNdNfZs@Base 6
+ _D3std8datetime8DateTime5monthMFNaNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime8DateTime5monthMxFNaNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime8DateTime5opCmpMxFNaNbNfxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime6__ctorMFNaNbNcNfxS3std8datetime4DatexS3std8datetime9TimeOfDayZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime6__ctorMFNaNcNfiiiiiiZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime6__initZ@Base 6
+ _D3std8datetime8DateTime6minuteMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6minuteMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime6secondMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6secondMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime6yearBCMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6yearBCMxFNaNdNfZs@Base 6
+ _D3std8datetime8DateTime7isoWeekMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime8__xopCmpFKxS3std8datetime8DateTimeKxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime8toStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime9dayOfWeekMxFNaNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime8DateTime9dayOfYearMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime9dayOfYearMxFNaNbNdNfZt@Base 6
+ _D3std8datetime8DateTime9julianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime8DateTime9timeOfDayMFNaNbNdNfxS3std8datetime9TimeOfDayZv@Base 6
+ _D3std8datetime8DateTime9timeOfDayMxFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime8TimeZone11_getOldNameFNaNbNfAyaZAya@Base 6
+ _D3std8datetime8TimeZone11getTimeZoneFNfAyaZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime8TimeZone11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime8TimeZone19getInstalledTZNamesFNfAyaZAAya@Base 6
+ _D3std8datetime8TimeZone4nameMxFNbNdNfZAya@Base 6
+ _D3std8datetime8TimeZone6__ctorMyFNaNfAyaAyaAyaZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime8TimeZone6__initZ@Base 6
+ _D3std8datetime8TimeZone6__vtblZ@Base 6
+ _D3std8datetime8TimeZone7__ClassZ@Base 6
+ _D3std8datetime8TimeZone7dstNameMxFNbNdNfZAya@Base 6
+ _D3std8datetime8TimeZone7stdNameMxFNbNdNfZAya@Base 6
+ _D3std8datetime9LocalTime10_localTimeyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime11dstInEffectMxFNbNelZb@Base 6
+ _D3std8datetime9LocalTime15_tzsetWasCalledOb@Base 6
+ _D3std8datetime9LocalTime6__ctorMyFNaNfZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime6__initZ@Base 6
+ _D3std8datetime9LocalTime6__vtblZ@Base 6
+ _D3std8datetime9LocalTime6hasDSTMxFNbNdNeZb@Base 6
+ _D3std8datetime9LocalTime6opCallFNaNbNeZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime7__ClassZ@Base 6
+ _D3std8datetime9LocalTime7dstNameMxFNbNdNeZAya@Base 6
+ _D3std8datetime9LocalTime7stdNameMxFNbNdNeZAya@Base 6
+ _D3std8datetime9LocalTime7tzToUTCMxFNbNelZl@Base 6
+ _D3std8datetime9LocalTime7utcToTZMxFNbNelZl@Base 6
+ _D3std8datetime9LocalTime8_lowLockb@Base 6
+ _D3std8datetime9LocalTime9singletonFNeZ13__critsec2792G28g@Base 6
+ _D3std8datetime9LocalTime9singletonFNeZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9StopWatch11setMeasuredMFNfS4core4time12TickDurationZv@Base 6
+ _D3std8datetime9StopWatch4peekMxFNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime9StopWatch4stopMFNfZv@Base 6
+ _D3std8datetime9StopWatch5resetMFNfZv@Base 6
+ _D3std8datetime9StopWatch5startMFNfZv@Base 6
+ _D3std8datetime9StopWatch6__ctorMFNcNfE3std8datetime9AutoStartZS3std8datetime9StopWatch@Base 6
+ _D3std8datetime9StopWatch6__initZ@Base 6
+ _D3std8datetime9StopWatch7runningMxFNaNbNdNfZb@Base 6
+ _D3std8datetime9StopWatch8opEqualsMxFNaNbNfKxS3std8datetime9StopWatchZb@Base 6
+ _D3std8datetime9StopWatch8opEqualsMxFNaNbNfxS3std8datetime9StopWatchZb@Base 6
+ _D3std8datetime9TimeOfDay11__invariantMxFNaNfZv@Base 6
+ _D3std8datetime9TimeOfDay11_addSecondsMFNaNbNcNjNflZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime9TimeOfDay14__invariant201MxFNaNfZv@Base 6
+ _D3std8datetime9TimeOfDay14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime9TimeOfDay22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfxS3std8datetime9TimeOfDayZS4core4time8Duration@Base 6
+ _D3std8datetime9TimeOfDay3maxFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay3minFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay4hourMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay4hourMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay5opCmpMxFNaNbNfxS3std8datetime9TimeOfDayZi@Base 6
+ _D3std8datetime9TimeOfDay6__ctorMFNaNcNfiiiZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay6__initZ@Base 6
+ _D3std8datetime9TimeOfDay6_validFNaNbNfiiiZb@Base 6
+ _D3std8datetime9TimeOfDay6minuteMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay6minuteMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay6secondMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay6secondMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay8__xopCmpFKxS3std8datetime9TimeOfDayKxS3std8datetime9TimeOfDayZi@Base 6
+ _D3std8datetime9TimeOfDay8toStringMxFNaNbNfZAya@Base 6
+ _D3std8demangle12__ModuleInfoZ@Base 6
+ _D3std8demangle8demangleFAyaZAya@Base 6
+ _D3std8encoding12__ModuleInfoZ@Base 6
+ _D3std8encoding13__T6encodeTaZ6encodeFwAaZk@Base 6
+ _D3std8encoding13__T6encodeTuZ6encodeFwAuZk@Base 6
+ _D3std8encoding13__T6encodeTwZ6encodeFwAwZk@Base 6
+ _D3std8encoding14EncodingScheme11validLengthMFAxhZk@Base 6
+ _D3std8encoding14EncodingScheme13firstSequenceMFAxhZk@Base 6
+ _D3std8encoding14EncodingScheme5countMFAxhZk@Base 6
+ _D3std8encoding14EncodingScheme5indexMFAxhkZi@Base 6
+ _D3std8encoding14EncodingScheme6__initZ@Base 6
+ _D3std8encoding14EncodingScheme6__vtblZ@Base 6
+ _D3std8encoding14EncodingScheme6createFAyaZC3std8encoding14EncodingScheme@Base 6
+ _D3std8encoding14EncodingScheme7__ClassZ@Base 6
+ _D3std8encoding14EncodingScheme7isValidMFAxhZb@Base 6
+ _D3std8encoding14EncodingScheme8registerFAyaZv@Base 6
+ _D3std8encoding14EncodingScheme8sanitizeMFAyhZAyh@Base 6
+ _D3std8encoding14EncodingScheme9supportedHAyaAya@Base 6
+ _D3std8encoding14__T7isValidTaZ7isValidFAxaZb@Base 6
+ _D3std8encoding15__T6decodeTAxaZ6decodeFKAxaZw@Base 6
+ _D3std8encoding15__T6decodeTAxuZ6decodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding15__T6decodeTAxwZ6decodeFNbKAxwZw@Base 6
+ _D3std8encoding16__T9canEncodeTaZ9canEncodeFwZb@Base 6
+ _D3std8encoding16__T9canEncodeTuZ9canEncodeFwZb@Base 6
+ _D3std8encoding16__T9canEncodeTwZ9canEncodeFwZb@Base 6
+ _D3std8encoding16isValidCodePointFwZb@Base 6
+ _D3std8encoding17EncodingException6__ctorMFAyaZC3std8encoding17EncodingException@Base 6
+ _D3std8encoding17EncodingException6__initZ@Base 6
+ _D3std8encoding17EncodingException6__vtblZ@Base 6
+ _D3std8encoding17EncodingException7__ClassZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf810safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding18EncodingSchemeUtf813encodedLengthMxFwZk@Base 6
+ _D3std8encoding18EncodingSchemeUtf819_sharedStaticCtor18FZv@Base 6
+ _D3std8encoding18EncodingSchemeUtf819replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding18EncodingSchemeUtf85namesMxFZAAya@Base 6
+ _D3std8encoding18EncodingSchemeUtf86__initZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf86__vtblZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf86decodeMxFKAxhZw@Base 6
+ _D3std8encoding18EncodingSchemeUtf86encodeMxFwAhZk@Base 6
+ _D3std8encoding18EncodingSchemeUtf87__ClassZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf88toStringMxFZAya@Base 6
+ _D3std8encoding18EncodingSchemeUtf89canEncodeMxFwZb@Base 6
+ _D3std8encoding18__T9transcodeTaTwZ9transcodeFAyaJAywZv@Base 6
+ _D3std8encoding19EncodingSchemeASCII10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding19EncodingSchemeASCII13encodedLengthMxFwZk@Base 6
+ _D3std8encoding19EncodingSchemeASCII19_sharedStaticCtor15FZv@Base 6
+ _D3std8encoding19EncodingSchemeASCII19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding19EncodingSchemeASCII5namesMxFZAAya@Base 6
+ _D3std8encoding19EncodingSchemeASCII6__initZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII6__vtblZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII6decodeMxFKAxhZw@Base 6
+ _D3std8encoding19EncodingSchemeASCII6encodeMxFwAhZk@Base 6
+ _D3std8encoding19EncodingSchemeASCII7__ClassZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII8toStringMxFZAya@Base 6
+ _D3std8encoding19EncodingSchemeASCII9canEncodeMxFwZb@Base 6
+ _D3std8encoding19__T11validLengthTaZ11validLengthFAxaZk@Base 6
+ _D3std8encoding20EncodingSchemeLatin110safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding20EncodingSchemeLatin113encodedLengthMxFwZk@Base 6
+ _D3std8encoding20EncodingSchemeLatin119_sharedStaticCtor16FZv@Base 6
+ _D3std8encoding20EncodingSchemeLatin119replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding20EncodingSchemeLatin15namesMxFZAAya@Base 6
+ _D3std8encoding20EncodingSchemeLatin16__initZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin16__vtblZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin16decodeMxFKAxhZw@Base 6
+ _D3std8encoding20EncodingSchemeLatin16encodeMxFwAhZk@Base 6
+ _D3std8encoding20EncodingSchemeLatin17__ClassZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin18toStringMxFZAya@Base 6
+ _D3std8encoding20EncodingSchemeLatin19canEncodeMxFwZb@Base 6
+ _D3std8encoding20__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding20__T10safeDecodeTAxuZ10safeDecodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding20__T10safeDecodeTAxwZ10safeDecodeFKAxwZw@Base 6
+ _D3std8encoding21__T13encodedLengthTaZ13encodedLengthFwZk@Base 6
+ _D3std8encoding21__T13encodedLengthTuZ13encodedLengthFwZk@Base 6
+ _D3std8encoding21__T13encodedLengthTwZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ15isValidCodeUnitFaZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ19replacementSequenceFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ5tailsFaZi@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin1513decodeReverseFKAxaZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin1520__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin154skipFKAxaZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwDFaZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwKAaZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwZAa@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9canEncodeFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9tailTableyG128h@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ15isValidCodeUnitFuZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ19replacementSequenceFNdZAyu@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin1313decodeReverseFKAxuZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin134skipFKAxuZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwDFuZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwKAuZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwZAu@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9canEncodeFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ15isValidCodeUnitFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ19replacementSequenceFNdZAyw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin1313decodeReverseFKAxwZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin134skipFKAxwZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwDFwZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwKAwZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwZAw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9canEncodeFwZb@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native13encodedLengthMxFwZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native19_sharedStaticCtor19FZv@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native5namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6__initZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6encodeMxFwAhZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native7__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native8toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native9canEncodeMxFwZb@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native13encodedLengthMxFwZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native19_sharedStaticCtor21FZv@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native5namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6__initZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6encodeMxFwAhZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native7__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native8toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native9canEncodeMxFwZb@Base 6
+ _D3std8encoding25EncodingSchemeWindows125210safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeWindows125213encodedLengthMxFwZk@Base 6
+ _D3std8encoding25EncodingSchemeWindows125219_sharedStaticCtor17FZv@Base 6
+ _D3std8encoding25EncodingSchemeWindows125219replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeWindows12525namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526__initZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526encodeMxFwAhZk@Base 6
+ _D3std8encoding25EncodingSchemeWindows12527__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12528toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeWindows12529canEncodeMxFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ13encodedLengthFwZk@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ15isValidCodeUnitFaZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ19replacementSequenceFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ5tailsFaZi@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1513decodeReverseFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1515__T6decodeTAxaZ6decodeFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1520__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin154skipFKAxaZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwDFaZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwKAaZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwZAa@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9canEncodeFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9tailTableyG128h@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ13encodedLengthFwZk@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ15isValidCodeUnitFuZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ19replacementSequenceFNdZAyu@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1313decodeReverseFKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1315__T6decodeTAxuZ6decodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1320__T10safeDecodeTAxuZ10safeDecodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin134skipFKAxuZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwDFuZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwKAuZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwZAu@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9canEncodeFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ13encodedLengthFwZk@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ15isValidCodeUnitFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ19replacementSequenceFNdZAyw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1313decodeReverseFKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1315__T6decodeTAxwZ6decodeFNaNbNiNfKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1320__T10safeDecodeTAxwZ10safeDecodeFKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin134skipFKAxwZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwDFwZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwKAwZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwZAw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9canEncodeFwZb@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__ctorMFAyaZC3std8encoding29UnrecognizedEncodingException@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__initZ@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__vtblZ@Base 6
+ _D3std8encoding29UnrecognizedEncodingException7__ClassZ@Base 6
+ _D3std8encoding36__T6encodeTE3std8encoding9AsciiCharZ6encodeFwAE3std8encoding9AsciiCharZk@Base 6
+ _D3std8encoding38__T6decodeTAxE3std8encoding9AsciiCharZ6decodeFNbKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding38__T6encodeTE3std8encoding10Latin1CharZ6encodeFwAE3std8encoding10Latin1CharZk@Base 6
+ _D3std8encoding39__T9canEncodeTE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding40__T6decodeTAxE3std8encoding10Latin1CharZ6decodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding41__T9canEncodeTE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding43__T10safeDecodeTAxE3std8encoding9AsciiCharZ10safeDecodeFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding43__T6encodeTE3std8encoding15Windows1252CharZ6encodeFwAE3std8encoding15Windows1252CharZk@Base 6
+ _D3std8encoding44__T13encodedLengthTE3std8encoding9AsciiCharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding45__T10safeDecodeTAxE3std8encoding10Latin1CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding45__T6decodeTAxE3std8encoding15Windows1252CharZ6decodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding46__T13encodedLengthTE3std8encoding10Latin1CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding46__T9canEncodeTE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ15isValidCodeUnitFE3std8encoding9AsciiCharZb@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ19replacementSequenceFNdZAyE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin1413decodeReverseFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin144skipFKAxE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwDFE3std8encoding9AsciiCharZvZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwKAE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwZAE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ15isValidCodeUnitFE3std8encoding9AsciiCharZb@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ19replacementSequenceFNdZAyE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1413decodeReverseFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1438__T6decodeTAxE3std8encoding9AsciiCharZ6decodeFNaNbNiNfKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1443__T10safeDecodeTAxE3std8encoding9AsciiCharZ10safeDecodeFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin144skipFKAxE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwDFE3std8encoding9AsciiCharZvZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwKAE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwZAE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ15isValidCodeUnitFE3std8encoding10Latin1CharZb@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ19replacementSequenceFNdZAyE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin1313decodeReverseFKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin134skipFKAxE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwDFE3std8encoding10Latin1CharZvZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwKAE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwZAE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding50__T10safeDecodeTAxE3std8encoding15Windows1252CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ15isValidCodeUnitFE3std8encoding10Latin1CharZb@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ19replacementSequenceFNdZAyE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1313decodeReverseFKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1340__T6decodeTAxE3std8encoding10Latin1CharZ6decodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1345__T10safeDecodeTAxE3std8encoding10Latin1CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin134skipFKAxE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwDFE3std8encoding10Latin1CharZvZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwKAE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwZAE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding51__T13encodedLengthTE3std8encoding15Windows1252CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ15isValidCodeUnitFE3std8encoding15Windows1252CharZb@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ19replacementSequenceFNdZAyE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ7charMapyAu@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin1413decodeReverseFKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin144skipFKAxE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwDFE3std8encoding15Windows1252CharZvZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwKAE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwZAE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ15isValidCodeUnitFE3std8encoding15Windows1252CharZb@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ19replacementSequenceFNdZAyE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ7charMapyAu@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1413decodeReverseFKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1445__T6decodeTAxE3std8encoding15Windows1252CharZ6decodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin144skipFKAxE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1450__T10safeDecodeTAxE3std8encoding15Windows1252CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwDFE3std8encoding15Windows1252CharZvZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwKAE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwZAE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8internal11processinit12__ModuleInfoZ@Base 6
+ _D3std8internal11scopebuffer12__ModuleInfoZ@Base 6
+ _D3std8internal12unicode_comp12__ModuleInfoZ@Base 6
+ _D3std8internal12unicode_comp16compositionTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std8internal12unicode_comp16compositionTableFNaNbNdNiNfZyAS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std8internal12unicode_norm12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_decomp12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_decomp16decompCanonTableFNaNbNdNiNfZ1tyAw@Base 6
+ _D3std8internal14unicode_decomp16decompCanonTableFNaNbNdNiNfZyAw@Base 6
+ _D3std8internal14unicode_decomp17decompCompatTableFNaNbNdNiNfZ1tyAw@Base 6
+ _D3std8internal14unicode_decomp17decompCompatTableFNaNbNdNiNfZyAw@Base 6
+ _D3std8internal14unicode_tables10isSpaceGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables10isWhiteGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables11isFormatGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_tables12isControlGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables12toLowerTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toLowerTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables12toTitleTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toTitleTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables12toUpperTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toUpperTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables13FullCaseEntry5valueMxFNaNbNdNiNjNeZAxw@Base 6
+ _D3std8internal14unicode_tables13FullCaseEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables13fullCaseTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables13FullCaseEntry@Base 6
+ _D3std8internal14unicode_tables13fullCaseTableFNaNbNdNiNfZyAS3std8internal14unicode_tables13FullCaseEntry@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry4sizeMxFNaNbNdNiNfZh@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry7isLowerMxFNaNbNdNiNfZi@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry7isUpperMxFNaNbNdNiNfZi@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty11__xopEqualsFKxS3std8internal14unicode_tables15UnicodePropertyKxS3std8internal14unicode_tables15UnicodePropertyZb@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty9__xtoHashFNbNeKxS3std8internal14unicode_tables15UnicodePropertyZk@Base 6
+ _D3std8internal14unicode_tables15simpleCaseTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables15SimpleCaseEntry@Base 6
+ _D3std8internal14unicode_tables15simpleCaseTableFNaNbNdNiNfZyAS3std8internal14unicode_tables15SimpleCaseEntry@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables6blocks10DevanagariyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10GlagoliticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10KharoshthiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10Old_ItalicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10Old_TurkicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10PhoenicianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10SaurashtrayAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Basic_LatinyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Box_DrawingyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11CJK_StrokesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Hangul_JamoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11New_Tai_LueyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Old_PersianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Yi_RadicalsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Domino_TilesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Meetei_MayekyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Number_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Sora_SompengyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Syloti_NagriyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Yi_SyllablesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Khmer_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Mahjong_TilesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Phaistos_DiscyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Playing_CardsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Aegean_NumbersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Block_ElementsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Greek_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14IPA_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Low_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Vertical_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Ancient_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15High_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Kana_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Kangxi_RadicalsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Musical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Bamum_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Braille_PatternsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Control_PicturesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Currency_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Geometric_ShapesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Greek_and_CopticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Hangul_SyllablesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Imperial_AramaicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_CyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_DyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Meroitic_CursiveyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Private_Use_AreayAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Vedic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Arabic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Arabic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Bopomofo_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17CJK_CompatibilityyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Cypriot_SyllabaryyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Ethiopic_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Old_South_ArabianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Alchemical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Latin_1_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Letterlike_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Linear_B_IdeogramsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Linear_B_SyllabaryyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Myanmar_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Devanagari_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Ethiopic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Ethiopic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19General_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Georgian_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Phonetic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Small_Form_VariantsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Variation_SelectorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Combining_Half_MarksyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Egyptian_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Meroitic_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Rumi_Numeral_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Sundanese_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Ancient_Greek_NumbersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Counting_Rod_NumeralsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Inscriptional_PahlaviyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Miscellaneous_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Modifier_Tone_LettersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Supplemental_Arrows_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Supplemental_Arrows_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Tai_Xuan_Jing_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22CJK_Unified_IdeographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Enclosed_AlphanumericsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Hangul_Jamo_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Hangul_Jamo_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Inscriptional_ParthianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Mathematical_OperatorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23CJK_Compatibility_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23CJK_Radicals_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Meetei_Mayek_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Miscellaneous_TechnicalyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Yijing_Hexagram_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks24Spacing_Modifier_LettersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks24Supplemental_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Byzantine_Musical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Common_Indic_Number_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Hangul_Compatibility_JamoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Latin_Extended_AdditionalyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Transport_And_Map_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Arabic_Presentation_Forms_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Arabic_Presentation_Forms_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks27CJK_Symbols_and_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Combining_Diacritical_MarksyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27High_Private_Use_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Superscripts_and_SubscriptsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks28CJK_Compatibility_IdeographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks28Katakana_Phonetic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Alphabetic_Presentation_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Halfwidth_and_Fullwidth_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Optical_Character_RecognitionyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Ancient_Greek_Musical_NotationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Phonetic_Extensions_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Variation_Selectors_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks31Enclosed_CJK_Letters_and_MonthsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks31Enclosed_Ideographic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Enclosed_Alphanumeric_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Miscellaneous_Symbols_and_ArrowsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Supplementary_Private_Use_Area_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Supplementary_Private_Use_Area_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks33Cuneiform_Numbers_and_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks33Mathematical_Alphanumeric_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_CyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_DyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34Ideographic_Description_CharactersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks35Supplemental_Mathematical_OperatorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks36Miscellaneous_Mathematical_Symbols_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks36Miscellaneous_Mathematical_Symbols_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks37Miscellaneous_Symbols_And_PictographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks37Unified_Canadian_Aboriginal_SyllabicsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks38Arabic_Mathematical_Alphabetic_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks38Combining_Diacritical_Marks_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks39CJK_Compatibility_Ideographs_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks39Combining_Diacritical_Marks_for_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3LaoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3NKoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3VaiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6blocks46Unified_Canadian_Aboriginal_Syllabics_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4ChamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4LisuyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4MiaoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4TagsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4ThaiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6blocks5BamumyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5BatakyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5BuhidyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5KhmeryAh@Base 6
+ _D3std8internal14unicode_tables6blocks5LimbuyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5OghamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5OriyayAh@Base 6
+ _D3std8internal14unicode_tables6blocks5RunicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5TakriyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5TamilyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ArabicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ArrowsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6BrahmiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6CarianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ChakmayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6CopticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6GothicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6HebrewyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6KaithiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6KanbunyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LepchayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LycianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LydianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6RejangyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6SyriacyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6Tai_LeyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6TeluguyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ThaanayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6__initZ@Base 6
+ _D3std8internal14unicode_tables6blocks7AvestanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7BengaliyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7DeseretyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7HanunooyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7KannadayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7MandaicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7MyanmaryAh@Base 6
+ _D3std8internal14unicode_tables6blocks7OsmanyayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7SharadayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7ShavianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7SinhalayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7TagalogyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7TibetanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8ArmenianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BalineseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BopomofoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BugineseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8CherokeeyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8CyrillicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8DingbatsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8EthiopicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GeorgianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GujaratiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GurmukhiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8HiraganayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8JavaneseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8KatakanayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Kayah_LiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Ol_ChikiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Phags_payAh@Base 6
+ _D3std8internal14unicode_tables6blocks8SpecialsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8TagbanwayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Tai_ThamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Tai_VietyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8TifinaghyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8UgariticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9CuneiformyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9EmoticonsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9MalayalamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9MongolianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9SamaritanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9SundaneseyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1LyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1TyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1VyAh@Base 6
+ _D3std8internal14unicode_tables6hangul2LVyAh@Base 6
+ _D3std8internal14unicode_tables6hangul3LVTyAh@Base 6
+ _D3std8internal14unicode_tables6hangul3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6hangul4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6hangul6__initZ@Base 6
+ _D3std8internal14unicode_tables7isHangLFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7isHangTFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7isHangVFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7scripts10DevanagariyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10GlagoliticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10KharoshthiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10Old_ItalicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10Old_TurkicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10PhoenicianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10SaurashtrayAh@Base 6
+ _D3std8internal14unicode_tables7scripts11New_Tai_LueyAh@Base 6
+ _D3std8internal14unicode_tables7scripts11Old_PersianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Meetei_MayekyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Sora_SompengyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Syloti_NagriyAh@Base 6
+ _D3std8internal14unicode_tables7scripts16Imperial_AramaicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts16Meroitic_CursiveyAh@Base 6
+ _D3std8internal14unicode_tables7scripts17Old_South_ArabianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts19Canadian_AboriginalyAh@Base 6
+ _D3std8internal14unicode_tables7scripts20Egyptian_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables7scripts20Meroitic_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables7scripts21Inscriptional_PahlaviyAh@Base 6
+ _D3std8internal14unicode_tables7scripts22Inscriptional_ParthianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts2YiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3HanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3LaoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3NkoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3VaiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables7scripts4ChamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4LisuyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4MiaoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4ThaiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables7scripts5BamumyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5BatakyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5BuhidyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5GreekyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5KhmeryAh@Base 6
+ _D3std8internal14unicode_tables7scripts5LatinyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5LimbuyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5OghamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5OriyayAh@Base 6
+ _D3std8internal14unicode_tables7scripts5RunicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5TakriyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5TamilyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ArabicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6BrahmiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CarianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ChakmayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CommonyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CopticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6GothicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6HangulyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6HebrewyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6KaithiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LepchayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LycianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LydianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6RejangyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6SyriacyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6Tai_LeyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6TeluguyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ThaanayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6__initZ@Base 6
+ _D3std8internal14unicode_tables7scripts7AvestanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7BengaliyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7BrailleyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7CypriotyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7DeseretyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7HanunooyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7KannadayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7MandaicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7MyanmaryAh@Base 6
+ _D3std8internal14unicode_tables7scripts7OsmanyayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7SharadayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7ShavianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7SinhalayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7TagalogyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7TibetanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8ArmenianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BalineseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BopomofoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BugineseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8CherokeeyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8CyrillicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8EthiopicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GeorgianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GujaratiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GurmukhiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8HiraganayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8JavaneseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8KatakanayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Kayah_LiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Linear_ByAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Ol_ChikiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Phags_PayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8TagbanwayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Tai_ThamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Tai_VietyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8TifinaghyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8UgariticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9CuneiformyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9InheritedyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9MalayalamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9MongolianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9SamaritanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9SundaneseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10AlphabeticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10DeprecatedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10Other_MathyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11ID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11IdeographicyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11Soft_DottedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11White_SpaceyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12Bidi_ControlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12Join_ControlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12XID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps13Grapheme_BaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps13Grapheme_LinkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Case_IgnorableyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Other_ID_StartyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Pattern_SyntaxyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Quotation_MarkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15ASCII_Hex_DigityAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Grapheme_ExtendyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Other_LowercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Other_UppercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps16Other_AlphabeticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps17Other_ID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps17Unified_IdeographyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps18Variation_SelectoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps19IDS_Binary_OperatoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps19Pattern_White_SpaceyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps20IDS_Trinary_OperatoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps20Terminal_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps21Other_Grapheme_ExtendyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps23Logical_Order_ExceptionyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps23Noncharacter_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps28Default_Ignorable_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CcyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CfyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CnyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LmyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LtyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LuyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2McyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2MeyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2MnyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NdyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PcyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PdyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PeyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PfyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PiyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ScyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SmyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZpyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps34Other_Default_Ignorable_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables8uniProps4DashyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps4MathyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables8uniProps5CasedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps5STermyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps6HyphenyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps6__initZ@Base 6
+ _D3std8internal14unicode_tables8uniProps7RadicalyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps8ExtenderyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps8ID_StartyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9DiacriticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9Hex_DigityAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9LowercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9UppercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9XID_StartyAh@Base 6
+ _D3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D3std8internal16unicode_grapheme12__ModuleInfoZ@Base 6
+ _D3std8internal4math10biguintx8612__ModuleInfoZ@Base 6
+ _D3std8internal4math11biguintcore10CACHELIMITyk@Base 6
+ _D3std8internal4math11biguintcore10inplaceSubFNaNbAkAxkAxkZb@Base 6
+ _D3std8internal4math11biguintcore11blockDivModFNaNbAkAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore11includeSignFNaNbNfAxkkbZAk@Base 6
+ _D3std8internal4math11biguintcore11mulInternalFNaNbAkAxkAxkZv@Base 6
+ _D3std8internal4math11biguintcore12FASTDIVLIMITyk@Base 6
+ _D3std8internal4math11biguintcore12__ModuleInfoZ@Base 6
+ _D3std8internal4math11biguintcore12biguintToHexFNaNbNfAaxAkaZAa@Base 6
+ _D3std8internal4math11biguintcore12mulKaratsubaFNaNbAkAxkAxkAkZv@Base 6
+ _D3std8internal4math11biguintcore12squareSimpleFNaNbAkAxkZv@Base 6
+ _D3std8internal4math11biguintcore13__T6intpowTkZ6intpowFNaNbNiNfkmZk@Base 6
+ _D3std8internal4math11biguintcore14divModInternalFNaNbAkAkxAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore14itoaZeroPaddedFNaNbNfAakiZv@Base 6
+ _D3std8internal4math11biguintcore14squareInternalFNaNbAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore14twosComplementFNaNbNfAxkAkZv@Base 6
+ _D3std8internal4math11biguintcore15addAssignSimpleFNaNbAkAxkZk@Base 6
+ _D3std8internal4math11biguintcore15adjustRemainderFNaNbAkAkAxkiAkbZv@Base 6
+ _D3std8internal4math11biguintcore15recursiveDivModFNaNbAkAkAxkAkbZv@Base 6
+ _D3std8internal4math11biguintcore15squareKaratsubaFNaNbAkxAkAkZv@Base 6
+ _D3std8internal4math11biguintcore15subAssignSimpleFNaNbAkAxkZk@Base 6
+ _D3std8internal4math11biguintcore15toHexZeroPaddedFNaNbNfAakZ9hexDigitsyAa@Base 6
+ _D3std8internal4math11biguintcore15toHexZeroPaddedFNaNbNfAakZv@Base 6
+ _D3std8internal4math11biguintcore16biguintToDecimalFNaNbAaAkZk@Base 6
+ _D3std8internal4math11biguintcore16schoolbookDivModFNaNbAkAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore17firstNonZeroDigitFNaNbNiNfxAkZi@Base 6
+ _D3std8internal4math11biguintcore18_sharedStaticCtor1FZv@Base 6
+ _D3std8internal4math11biguintcore18biguintFromDecimalFNaAkAxaZi@Base 6
+ _D3std8internal4math11biguintcore18removeLeadingZerosFNaNbNfANgkZANgk@Base 6
+ _D3std8internal4math11biguintcore20addOrSubAssignSimpleFNaNbAkAxkbZk@Base 6
+ _D3std8internal4math11biguintcore21highestDifferentDigitFNaNbNiNfxAkxAkZk@Base 6
+ _D3std8internal4math11biguintcore24highestPowerBelowUintMaxFNaNbNfkZ6maxpwryG22h@Base 6
+ _D3std8internal4math11biguintcore24highestPowerBelowUintMaxFNaNbNfkZi@Base 6
+ _D3std8internal4math11biguintcore25highestPowerBelowUlongMaxFNaNbNfkZ6maxpwryG39h@Base 6
+ _D3std8internal4math11biguintcore25highestPowerBelowUlongMaxFNaNbNfkZi@Base 6
+ _D3std8internal4math11biguintcore25karatsubaRequiredBuffSizeFNaNbNfkZk@Base 6
+ _D3std8internal4math11biguintcore3ONEyAk@Base 6
+ _D3std8internal4math11biguintcore3TENyAk@Base 6
+ _D3std8internal4math11biguintcore3TWOyAk@Base 6
+ _D3std8internal4math11biguintcore3addFNaNbxAkxAkZAk@Base 6
+ _D3std8internal4math11biguintcore3subFNaNbxAkxAkPbZAk@Base 6
+ _D3std8internal4math11biguintcore4ZEROyAk@Base 6
+ _D3std8internal4math11biguintcore4lessFNaNbAxkAxkZb@Base 6
+ _D3std8internal4math11biguintcore6addIntFNaNbxAkmZAk@Base 6
+ _D3std8internal4math11biguintcore6subIntFNaNbxAkmZAk@Base 6
+ _D3std8internal4math11biguintcore7BigUint10uintLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint11__invariantMxFNaZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint11__xopEqualsFKxS3std8internal4math11biguintcore7BigUintKxS3std8internal4math11biguintcore7BigUintZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint11toHexStringMxFNaNbNfiaiaZAa@Base 6
+ _D3std8internal4math11biguintcore7BigUint11ulongLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__T5opCmpTvZ5opCmpMxFNaNbNiNfxS3std8internal4math11biguintcore7BigUintZi@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__T5opShlTmZ5opShlMxFNaNbNfmZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__invariant2MxFNaZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint13fromHexStringMFNaNbNfAxaZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint14__T6divIntTykZ6divIntFNaNbNfS3std8internal4math11biguintcore7BigUintykZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint14__T6modIntTykZ6modIntFNaNbNfS3std8internal4math11biguintcore7BigUintykZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opAssignTmZ8opAssignMFNaNbNfmZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opEqualsTvZ8opEqualsMxFNaNbNiNfKxS3std8internal4math11biguintcore7BigUintZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opEqualsTvZ8opEqualsMxFNaNbNiNfmZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__funcliteral31FNaNbNiNeAkZAyk@Base 6
+ _D3std8internal4math11biguintcore7BigUint15toDecimalStringMxFNaNbiZAa@Base 6
+ _D3std8internal4math11biguintcore7BigUint17fromDecimalStringMFNaNeAxaZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint3divFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3modFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3mulFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3powFNaNbS3std8internal4math11biguintcore7BigUintmZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint6__ctorMFNaNbNcNiNfAykZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint6__initZ@Base 6
+ _D3std8internal4math11biguintcore7BigUint6isZeroMxFNaNbNiNfZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint6toHashMxFNbNeZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint8__xopCmpFKxS3std8internal4math11biguintcore7BigUintKxS3std8internal4math11biguintcore7BigUintZi@Base 6
+ _D3std8internal4math11biguintcore7BigUint8addOrSubFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintbPbZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint8numBytesMxFNaNbNiNfZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint8peekUintMxFNaNbNiNfiZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint9peekUlongMxFNaNbNiNfiZm@Base 6
+ _D3std8internal4math11biguintcore9addSimpleFNaNbAkxAkxAkZk@Base 6
+ _D3std8internal4math11biguintcore9mulSimpleFNaNbAkAxkAxkZv@Base 6
+ _D3std8internal4math11biguintcore9subSimpleFNaNbAkAxkAxkZk@Base 6
+ _D3std8internal4math12biguintnoasm12__ModuleInfoZ@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteMulFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteShlFNaNbNiNfAkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteShrFNaNbNiNfAkAxkkZv@Base 6
+ _D3std8internal4math12biguintnoasm15multibyteSquareFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm18multibyteDivAssignFNaNbNiNfAkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai43Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai45Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai43Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai45Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteAddDiagonalSquaresFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteMultiplyAccumulateFNaNbNiNfAkAxkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteTriangleAccumulateFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai43Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai45Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math13errorfunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13errorfunction1PyG10e@Base 6
+ _D3std8internal4math13errorfunction1QyG11e@Base 6
+ _D3std8internal4math13errorfunction1RyG5e@Base 6
+ _D3std8internal4math13errorfunction1SyG6e@Base 6
+ _D3std8internal4math13errorfunction1TyG7e@Base 6
+ _D3std8internal4math13errorfunction1UyG7e@Base 6
+ _D3std8internal4math13errorfunction20__T12rationalPolyTeZ12rationalPolyFNaNbNiNfeAxeAxeZe@Base 6
+ _D3std8internal4math13errorfunction22normalDistributionImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction3erfFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction4erfcFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5EXP_2ye@Base 6
+ _D3std8internal4math13errorfunction5erfceFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5expx2FNaNbNiNfeiZe@Base 6
+ _D3std8internal4math13gammafunction10EULERGAMMAye@Base 6
+ _D3std8internal4math13gammafunction11logmdigammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19LargeStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19SmallStirlingCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction14betaIncompleteFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction15gammaIncompleteFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction16GammaSmallCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZ4coefyG13Ae@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction17betaIncompleteInvFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction17logGammaNumeratoryG7e@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion1FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion2FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18logmdigammaInverseFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction19GammaSmallNegCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction19betaDistPowerSeriesFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction19logGammaDenominatoryG8e@Base 6
+ _D3std8internal4math13gammafunction20GammaNumeratorCoeffsyG8e@Base 6
+ _D3std8internal4math13gammafunction20gammaIncompleteComplFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction22GammaDenominatorCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction22logGammaStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction23gammaIncompleteComplInvFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction4Bn_nyG7e@Base 6
+ _D3std8internal4math13gammafunction5gammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction7digammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction8logGammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4test10dummyrange12__ModuleInfoZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange13opIndexAssignMFNaNbNiNfkkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMNgFNaNbNcNiNfkZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfkkZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMxFNaNbNiNfkZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfkkZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal6digest9sha_SSSE312__ModuleInfoZ@Base 6
+ _D3std8internal7cstring12__ModuleInfoZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3ResZS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFNbNiAxaZS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3ResZS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFNbNiAyaZS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3ResZS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFNbNiANgaZS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res@Base 6
+ _D3std8internal7windows8advapi3212__ModuleInfoZ@Base 6
+ _D3std8syserror12__ModuleInfoZ@Base 6
+ _D3std8syserror8SysError3msgFkZAya@Base 6
+ _D3std8syserror8SysError6__initZ@Base 6
+ _D3std8syserror8SysError6__vtblZ@Base 6
+ _D3std8syserror8SysError7__ClassZ@Base 6
+ _D3std8typecons10Structural11__InterfaceZ@Base 6
+ _D3std8typecons10__T5tupleZ135__T5tupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZS3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ136__T5tupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5tupleFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ137__T5tupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ16__T5tupleTkTkTkZ5tupleFNaNbNiNfkkkZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ22__T5tupleTAyaTAyaTAyaZ5tupleFNaNbNiNfAyaAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPbZ5tupleFNaNbNiNfC8TypeInfoPbZS3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPiZ5tupleFNaNbNiNfC8TypeInfoPiZS3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPkZ5tupleFNaNbNiNfC8TypeInfoPkZS3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ33__T5tupleTC14TypeInfo_ArrayTPAyhZ5tupleFNaNbNiNfC14TypeInfo_ArrayPAyhZS3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ34__T5tupleTC14TypeInfo_ArrayTPG24hZ5tupleFNaNbNiNfC14TypeInfo_ArrayPG24hZS3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG24hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ34__T5tupleTC14TypeInfo_ClassTPG24hZ5tupleFNaNbNiNfC14TypeInfo_ClassPG24hZS3std8typecons34__T5TupleTC14TypeInfo_ClassTPG24hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ35__T5tupleTC15TypeInfo_StructTPG24hZ5tupleFNaNbNiNfC15TypeInfo_StructPG24hZS3std8typecons35__T5TupleTC15TypeInfo_StructTPG24hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ35__T5tupleTC18TypeInfo_InvariantTPhZ5tupleFNaNbNiNfC18TypeInfo_InvariantPhZS3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ38__T5tupleTC18TypeInfo_InvariantTPG24hZ5tupleFNaNbNiNfC18TypeInfo_InvariantPG24hZS3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG24hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ48__T5tupleTC14TypeInfo_ClassTPC6object9ThrowableZ5tupleFNaNbNiNfC14TypeInfo_ClassPC6object9ThrowableZS3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ50__T5tupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5tupleFNaNbNiNfC15TypeInfo_SharedPOC6object9ThrowableZS3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ53__T5tupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std11concurrency3TidZS3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple@Base 6
+ _D3std8typecons12__ModuleInfoZ@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZS3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple11__xopEqualsFKxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleKxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZb@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple174__T8opEqualsTxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZb@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__ctorMFNaNbNcNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__initZ@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons14__T5TupleTbTiZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple11__xopEqualsFKxS3std8typecons14__T5TupleTbTiZ5TupleKxS3std8typecons14__T5TupleTbTiZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple48__T5opCmpTxS3std8typecons14__T5TupleTbTiZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons14__T5TupleTbTiZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple51__T8opEqualsTxS3std8typecons14__T5TupleTbTiZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons14__T5TupleTbTiZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6__ctorMFNaNbNcNiNfbiZS3std8typecons14__T5TupleTbTiZ5Tuple@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6__initZ@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple8__xopCmpFKxS3std8typecons14__T5TupleTbTiZ5TupleKxS3std8typecons14__T5TupleTbTiZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTkTkZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple11__xopEqualsFKxS3std8typecons14__T5TupleTkTkZ5TupleKxS3std8typecons14__T5TupleTkTkZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple48__T5opCmpTxS3std8typecons14__T5TupleTkTkZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons14__T5TupleTkTkZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple51__T8opEqualsTxS3std8typecons14__T5TupleTkTkZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons14__T5TupleTkTkZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple6__ctorMFNaNbNcNiNfkkZS3std8typecons14__T5TupleTkTkZ5Tuple@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple6__initZ@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple8__xopCmpFKxS3std8typecons14__T5TupleTkTkZ5TupleKxS3std8typecons14__T5TupleTkTkZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple11__xopEqualsFKxS3std8typecons16__T5TupleTiTAyaZ5TupleKxS3std8typecons16__T5TupleTiTAyaZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple50__T5opCmpTxS3std8typecons16__T5TupleTiTAyaZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons16__T5TupleTiTAyaZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple53__T8opEqualsTxS3std8typecons16__T5TupleTiTAyaZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons16__T5TupleTiTAyaZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6__ctorMFNaNbNcNiNfiAyaZS3std8typecons16__T5TupleTiTAyaZ5Tuple@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6__initZ@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple8__xopCmpFKxS3std8typecons16__T5TupleTiTAyaZ5TupleKxS3std8typecons16__T5TupleTiTAyaZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple11__xopEqualsFKxS3std8typecons16__T5TupleTkTkTkZ5TupleKxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple50__T5opCmpTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons16__T5TupleTkTkTkZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple53__T8opEqualsTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6__ctorMFNaNbNcNiNfkkkZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple8__xopCmpFKxS3std8typecons16__T5TupleTkTkTkZ5TupleKxS3std8typecons16__T5TupleTkTkTkZ5TupleZi@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple11__xopEqualsFKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZb@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple52__T5opCmpTxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZi@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple55__T8opEqualsTxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZb@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__ctorMFNaNbNcNiNfeeeeZS3std8typecons18__T5TupleTeTeTeTeZ5Tuple@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__initZ@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple8__xopCmpFKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZi@Base 6
+ _D3std8typecons19NotImplementedError6__ctorMFAyaZC3std8typecons19NotImplementedError@Base 6
+ _D3std8typecons19NotImplementedError6__initZ@Base 6
+ _D3std8typecons19NotImplementedError6__vtblZ@Base 6
+ _D3std8typecons19NotImplementedError7__ClassZ@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple11__xopEqualsFKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZb@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple56__T5opCmpTxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZi@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple59__T8opEqualsTxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZb@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__ctorMFNaNbNcNiNfAyaAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__initZ@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple8__xopCmpFKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZi@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPbZS3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPiZS3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPkZS3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPvZS3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons2No6__initZ@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ArrayPAyhZS3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__initZ@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG24hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG24hZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ArrayPG24hZS3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG24hZ5Tuple@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG24hZ5Tuple6__initZ@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG24hZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG24hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG24hZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ClassPG24hZS3std8typecons34__T5TupleTC14TypeInfo_ClassTPG24hZ5Tuple@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG24hZ5Tuple6__initZ@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG24hZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG24hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG24hZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPG24hZS3std8typecons35__T5TupleTC15TypeInfo_StructTPG24hZ5Tuple@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG24hZ5Tuple6__initZ@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG24hZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__ctorMFNaNbNcNiNfC18TypeInfo_InvariantPhZS3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__initZ@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG24hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG24hZ5Tuple6__ctorMFNaNbNcNiNfC18TypeInfo_InvariantPG24hZS3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG24hZ5Tuple@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG24hZ5Tuple6__initZ@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG24hZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons3Yes6__initZ@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple11__xopEqualsFKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZb@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons14__T5TupleTkTkZ5Tuple@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6__ctorMFNaNbNcNiNfkkZS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6__initZ@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple74__T5opCmpTxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZi@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple77__T8opEqualsTxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZb@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple8__xopCmpFKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZi@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable11__xopEqualsFKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZb@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin13getMNgFNaNbNcNdNiNeZyC3std8datetime8TimeZone@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin16__ctorMFNaNbNcNiNeyC3std8datetime8TimeZoneZS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin18opAssignMFNaNbNiNeS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZv@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin18opAssignMFNaNbNiNeyC3std8datetime8TimeZoneZv@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable9__xtoHashFNbNeKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZk@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ClassPC6object9ThrowableZS3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_SharedPOC6object9ThrowableZS3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std11concurrency3TidZS3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__initZ@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple11__xopEqualsFKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZb@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons16__T5TupleTiTAyaZ5Tuple@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__ctorMFNaNbNcNiNfiAyaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__initZ@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple88__T5opCmpTxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZi@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple8__xopCmpFKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZi@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple91__T8opEqualsTxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZb@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple11__xopEqualsFKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZb@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons14__T5TupleTbTiZ5Tuple@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__ctorMFNaNbNcNiNfbiZS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__initZ@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple8__xopCmpFKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZi@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple95__T5opCmpTxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZi@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple98__T8opEqualsTxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple119__T8opEqualsTxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ8opEqualsMxFxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple11__xopEqualsFKxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleKxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__ctorMFNaNbNcNiNfS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6toHashMxFNaNbNeZk@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZk@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl3FTP4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl3FTP4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl3FTP4ImplZS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZk@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl4HTTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl4HTTP4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl4SMTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl4SMTP4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple11__xopEqualsFKxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple120__T8opAssignTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opAssignMFNaNbNiNfKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple120__T8opEqualsTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opEqualsMFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple121__T8opEqualsTxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opEqualsMxFxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple27__T8toStringTDFNaNbNfAxaZvZ8toStringMFMDFNaNbNfAxaZvZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__ctorMFNaNbNcNiNfS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6toHashMxFNaNbNeZk@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore42__T10initializeTAyaTE3std4file8SpanModeTbZ10initializeMFKAyaKE3std4file8SpanModeKbZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZk@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4moveMFNbNiKS3std4file15DirIteratorImplZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std4file15DirIteratorImpl@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted37__T6__ctorTAyaTE3std4file8SpanModeTbZ6__ctorMFNcKAyaKE3std4file8SpanModeKbZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__ctorMFNcS3std4file15DirIteratorImplZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted8opAssignMFS3std4file15DirIteratorImplZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted8opAssignMFS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCountedZv@Base 6
+ _D3std8typelist12__ModuleInfoZ@Base 6
+ _D3std9algorithm10comparison12__ModuleInfoZ@Base 6
+ _D3std9algorithm10comparison12__T3maxTiTiZ3maxFNaNbNiNfiiZi@Base 6
+ _D3std9algorithm10comparison12__T3maxTkTiZ3maxFNaNbNiNfkiZk@Base 6
+ _D3std9algorithm10comparison12__T3maxTkTkZ3maxFNaNbNiNfkkZk@Base 6
+ _D3std9algorithm10comparison12__T3minTkTiZ3minFNaNbNiNfkiZi@Base 6
+ _D3std9algorithm10comparison12__T3minTkTkZ3minFNaNbNiNfkkZk@Base 6
+ _D3std9algorithm10comparison12__T3minTlTkZ3minFNaNbNiNflkZl@Base 6
+ _D3std9algorithm10comparison13__T3minTkTykZ3minFNaNbNiNfkykZk@Base 6
+ _D3std9algorithm10comparison13__T3minTyiTkZ3minFNaNbNiNfyikZyi@Base 6
+ _D3std9algorithm10comparison13__T3minTykTkZ3minFNaNbNiNfykkZyk@Base 6
+ _D3std9algorithm10comparison14__T3maxTkTkTkZ3maxFNaNbNiNfkkkZk@Base 6
+ _D3std9algorithm10comparison14__T3minTykTykZ3minFNaNbNiNfykykZyk@Base 6
+ _D3std9algorithm10comparison20__T5amongVai45Vai43Z13__T5amongTxaZ5amongFNaNbNiNfxaZk@Base 6
+ _D3std9algorithm10comparison20__T5amongVai95Vai44Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison21__T5amongVai101Vai69Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison21__T5amongVai105Vai73Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison32__T5amongVai117Vai108Vai85Vai76Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison33__T3cmpVAyaa5_61203c2062TAxhTAxhZ3cmpFNaNbNiNfAxhAxhZi@Base 6
+ _D3std9algorithm10comparison43__T5amongVai108Vai76Vai102Vai70Vai105Vai73Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison489__T3cmpVAyaa5_61203c2062TS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultTS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZ3cmpFNaNfS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZi@Base 6
+ _D3std9algorithm10comparison6EditOp6__initZ@Base 6
+ _D3std9algorithm12__ModuleInfoZ@Base 6
+ _D3std9algorithm6setops12__ModuleInfoZ@Base 6
+ _D3std9algorithm7sorting103__T12HeapSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ13__T8heapSortZ8heapSortFNaNbNiNfAAyaZv@Base 6
+ _D3std9algorithm7sorting103__T12HeapSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ9__T4siftZ4siftFNaNbNiNfAAyakykZv@Base 6
+ _D3std9algorithm7sorting104__T13quickSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ13quickSortImplFNaNbNiNfAAyakZv@Base 6
+ _D3std9algorithm7sorting114__T23optimisticInsertionSortS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ23optimisticInsertionSortFNaNbNiNfAAyaZv@Base 6
+ _D3std9algorithm7sorting12__ModuleInfoZ@Base 6
+ _D3std9algorithm7sorting135__T4sortVAyaa17_612e74696d6554203c20622e74696d6554VE3std9algorithm8mutation12SwapStrategyi0TAS3std8datetime13PosixTimeZone10LeapSecondZ4sortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std9algorithm7sorting139__T4sortVAyaa17_612e74696d6554203c20622e74696d6554VE3std9algorithm8mutation12SwapStrategyi0TAS3std8datetime13PosixTimeZone14TempTransitionZ4sortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std9algorithm7sorting162__T8getPivotS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ8getPivotFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZk@Base 6
+ _D3std9algorithm7sorting162__T8isSortedS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ8isSortedFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std9algorithm7sorting166__T8getPivotS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ8getPivotFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZk@Base 6
+ _D3std9algorithm7sorting166__T8isSortedS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ8isSortedFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9algorithm7sorting167__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ13__T8heapSortZ8heapSortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm7sorting167__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ9__T4siftZ4siftFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondkykZv@Base 6
+ _D3std9algorithm7sorting168__T13quickSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ13quickSortImplFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondkZv@Base 6
+ _D3std9algorithm7sorting171__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ13__T8heapSortZ8heapSortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm7sorting171__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ9__T4siftZ4siftFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionkykZv@Base 6
+ _D3std9algorithm7sorting172__T13quickSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ13quickSortImplFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionkZv@Base 6
+ _D3std9algorithm7sorting178__T23optimisticInsertionSortS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ23optimisticInsertionSortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm7sorting182__T23optimisticInsertionSortS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ23optimisticInsertionSortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm7sorting201__T11TimSortImplS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ5Slice6__initZ@Base 6
+ _D3std9algorithm7sorting72__T4sortVAyaa5_61203c2062VE3std9algorithm8mutation12SwapStrategyi0TAAyaZ4sortFNaNbNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std9algorithm7sorting98__T8getPivotS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ8getPivotFNaNbNiNfAAyaZk@Base 6
+ _D3std9algorithm7sorting98__T8isSortedS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ8isSortedFNaNbNiNfAAyaZb@Base 6
+ _D3std9algorithm8internal12__ModuleInfoZ@Base 6
+ _D3std9algorithm8mutation103__T4moveTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ4moveFNaNbNiKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std9algorithm8mutation105__T6swapAtTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ6swapAtFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalskkZv@Base 6
+ _D3std9algorithm8mutation106__T7reverseTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ7reverseFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZv@Base 6
+ _D3std9algorithm8mutation12__ModuleInfoZ@Base 6
+ _D3std9algorithm8mutation12__T4moveTAkZ4moveFNaNbNiKAkZAk@Base 6
+ _D3std9algorithm8mutation133__T4copyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTAS3std3uni17CodepointIntervalZ4copyFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZAS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation133__T4copyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTAS3std3uni17CodepointIntervalZ4copyFS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZ11genericImplFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZAS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation13__T4moveTAyaZ4moveFNaNbNiNfKAyaKAyaZv@Base 6
+ _D3std9algorithm8mutation13__T4swapTAyaZ4swapFNaNbNiNeKAyaKAyaZv@Base 6
+ _D3std9algorithm8mutation144__T4swapTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation145__T4swapTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation145__T4swapTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation148__T4swapTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation14__T4moveTAAyaZ4moveFNaNbNiKAAyaZAAya@Base 6
+ _D3std9algorithm8mutation14__T4swapTAAyaZ4swapFNaNbNiNeKAAyaKAAyaZv@Base 6
+ _D3std9algorithm8mutation15__T4copyTAiTAkZ4copyFAiAkZ11genericImplFNaNbNiNfAiAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAiTAkZ4copyFNaNbNiNfAiAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAkTAkZ4copyFAkAkZ11genericImplFNaNbNiNfAkAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAkTAkZ4copyFNaNbNiNfAkAkZAk@Base 6
+ _D3std9algorithm8mutation16__T6swapAtTAAyaZ6swapAtFNaNbNiNfAAyakkZv@Base 6
+ _D3std9algorithm8mutation174__T4moveTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZ4moveFNaNbNiKS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm8mutation183__T4moveTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZ4moveFNaNbNiKS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm8mutation26__T4swapTS3std5stdio4FileZ4swapFNaNbNiNeKS3std5stdio4FileKS3std5stdio4FileZv@Base 6
+ _D3std9algorithm8mutation29__T4moveTC4core6thread5FiberZ4moveFNaNbNiNfKC4core6thread5FiberKC4core6thread5FiberZv@Base 6
+ _D3std9algorithm8mutation33__T4moveTS3std3net4curl3FTP4ImplZ4moveFKS3std3net4curl3FTP4ImplKS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std9algorithm8mutation34__T4moveTS3std3net4curl4HTTP4ImplZ4moveFKS3std3net4curl4HTTP4ImplKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std9algorithm8mutation34__T4moveTS3std3net4curl4SMTP4ImplZ4moveFKS3std3net4curl4SMTP4ImplKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std9algorithm8mutation37__T4moveTS3std4file15DirIteratorImplZ4moveFKS3std4file15DirIteratorImplKS3std4file15DirIteratorImplZv@Base 6
+ _D3std9algorithm8mutation38__T4moveTS3std3uni17CodepointIntervalZ4moveFNaNbNiNfKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation40__T4swapTS3std5stdio17LockingTextReaderZ4swapFNaNbNiNeKS3std5stdio17LockingTextReaderKS3std5stdio17LockingTextReaderZv@Base 6
+ _D3std9algorithm8mutation46__T4moveTAS3std5regex8internal2ir10NamedGroupZ4moveFNaNbNiKAS3std5regex8internal2ir10NamedGroupZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std9algorithm8mutation51__T4swapTS3std8datetime13PosixTimeZone10LeapSecondZ4swapFNaNbNiNeKS3std8datetime13PosixTimeZone10LeapSecondKS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm8mutation52__T4moveTAS3std8datetime13PosixTimeZone10LeapSecondZ4moveFNaNbNiKAS3std8datetime13PosixTimeZone10LeapSecondZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std9algorithm8mutation52__T4swapTAS3std8datetime13PosixTimeZone10LeapSecondZ4swapFNaNbNiNeKAS3std8datetime13PosixTimeZone10LeapSecondKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm8mutation54__T6swapAtTAS3std8datetime13PosixTimeZone10LeapSecondZ6swapAtFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondkkZv@Base 6
+ _D3std9algorithm8mutation54__T7moveAllTAC4core6thread5FiberTAC4core6thread5FiberZ7moveAllFNaNfAC4core6thread5FiberAC4core6thread5FiberZAC4core6thread5Fiber@Base 6
+ _D3std9algorithm8mutation55__T4swapTS3std8datetime13PosixTimeZone14TempTransitionZ4swapFNaNbNiNeKS3std8datetime13PosixTimeZone14TempTransitionKS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm8mutation56__T4moveTAS3std8datetime13PosixTimeZone14TempTransitionZ4moveFNaNbNiKAS3std8datetime13PosixTimeZone14TempTransitionZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std9algorithm8mutation56__T4swapTAS3std8datetime13PosixTimeZone14TempTransitionZ4swapFNaNbNiNeKAS3std8datetime13PosixTimeZone14TempTransitionKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm8mutation58__T6swapAtTAS3std8datetime13PosixTimeZone14TempTransitionZ6swapAtFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionkkZv@Base 6
+ _D3std9algorithm8mutation59__T6removeVE3std9algorithm8mutation12SwapStrategyi0TAAyaTiZ6removeFNaNbNiNfAAyaiZAAya@Base 6
+ _D3std9algorithm8mutation674__T4copyTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultTAkZ4copyFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZAk@Base 6
+ _D3std9algorithm8mutation674__T4copyTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultTAkZ4copyFS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZ11genericImplFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZAk@Base 6
+ _D3std9algorithm8mutation75__T6removeVE3std9algorithm8mutation12SwapStrategyi2TAC4core6thread5FiberTkZ6removeFNaNfAC4core6thread5FiberkZAC4core6thread5Fiber@Base 6
+ _D3std9algorithm8mutation77__T4copyTAS3std5regex8internal2ir8BytecodeTAS3std5regex8internal2ir8BytecodeZ4copyFAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZ11genericImplFNaNbNiNfAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZAS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std9algorithm8mutation77__T4copyTAS3std5regex8internal2ir8BytecodeTAS3std5regex8internal2ir8BytecodeZ4copyFNaNbNiNfAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZAS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std9algorithm9iteration105__T6filterS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbZ88__T6filterTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ6filterFNaNfS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult4saveMFNaNbNdNiZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult5frontMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult6__ctorMFNaNbNcNiS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult7opSliceMFNaNbNiNfZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult4saveMFNaNdNfZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5emptyMFNaNdNfZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5frontMFNaNdNfZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__ctorMFNaNbNcNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult4saveMFNaNdNfZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5emptyMFNaNdNfZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5frontMFNaNdNfZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__ctorMFNaNbNcNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration11__T3sumTAkZ3sumFNaNbNiNfAkZk@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult11__fieldDtorMFZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult11__xopEqualsFKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZb@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult15__fieldPostblitMFNbZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult5emptyMFNdZb@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__ctorMFNcS3std4file11DirIteratorZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult7opSliceMFNbZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult8opAssignMFNcNjS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult8popFrontMFZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult9__xtoHashFNbNeKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZk@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult12__T7popBackZ7popBackMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult5frontMFNaNbNdNiNfZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__ctorMFNaNbNcNiNfAyS3std8internal14unicode_tables9CompEntryZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult7opIndexMFNaNbNiNfkZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult7opSliceMFNaNbNiNfkkZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult9__T4backZ4backMFNaNbNdNiNfZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration12__ModuleInfoZ@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult12__T7popBackZ7popBackMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__ctorMFNaNbNcNiNfAyS3std8internal14unicode_tables15UnicodePropertyZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult7opSliceMFNaNbNiNfkkZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult9__T4backZ4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration13__T3sumTAkTkZ3sumFNaNbNiNfAkkZk@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult11__xopEqualsFKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZb@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult4saveMFNaNdNfZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult5frontMFNaNdNfZw@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__ctorMFNaNcNfS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult7opSliceMFNaNbNiNfZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult9__xtoHashFNbNeKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZk@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult4saveMFNaNbNdNiZS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult5frontMFNaNbNdNiZS3std8bitmanip14__T7BitsSetTkZ7BitsSet@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult6__ctorMFNaNbNcNiNfS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration23__T3mapVAyaa4_615b305dZ41__T3mapTS3std3uni21DecompressedIntervalsZ3mapFNaNbNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration23__T3mapVAyaa4_615b315dZ41__T3mapTS3std3uni21DecompressedIntervalsZ3mapFNaNbNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration25__T3mapVAyaa5_612e726873Z51__T3mapTAyS3std8internal14unicode_tables9CompEntryZ3mapFNaNbNiNfAyS3std8internal14unicode_tables9CompEntryZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFNaNbNiS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result4saveMFNaNbNdNiZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result5frontMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result6__ctorMFNaNbNcNiS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration27__T3mapVAyaa6_612e6e616d65Z58__T3mapTAyS3std8internal14unicode_tables15UnicodePropertyZ3mapFNaNbNiNfAyS3std8internal14unicode_tables15UnicodePropertyZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z16__T6reduceTkTAkZ6reduceFNaNbNiNfkAkZk@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z24__T13reducePreImplTAkTkZ13reducePreImplFNaNbNiNfAkKkZk@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z25__T10reduceImplVbi0TAkTkZ10reduceImplFNaNbNiNfAkKkZk@Base 6
+ _D3std9algorithm9iteration29__T3mapS183std5ascii7toLowerZ12__T3mapTAxaZ3mapFNaNbNiNfAxaZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result11__xopEqualsFKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultZb@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result11lastIndexOfFNaNfAyaaZk@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result4backMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result4saveMFNaNbNdNiNfZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result5frontMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__ctorMFNaNbNcNiNfAyaaZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result7popBackMFNaNfZv@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result9__xtoHashFNbNeKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultZk@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFNaNbNiNfAyaaZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult5frontMFNaNdNfZw@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__ctorMFNaNbNcNiNfAxaZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result11__xopEqualsFKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZb@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result15separatorLengthMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result16ensureBackLengthMFNaNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result17ensureFrontLengthMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result4backMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result4saveMFNaNbNdNiNfZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result5frontMFNaNbNdNiNfZAya@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__ctorMFNaNbNcNiNfAyaAyaZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result7popBackMFNaNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result9__xtoHashFNbNeKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZk@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFNaNbNiNfAyaAyaZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult5frontMFNdNfZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__ctorMFNaNbNcNiNfS3std5range13__T6RepeatTiZ6RepeatZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opIndexMFNfkZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarTokenZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult5frontMFNdNfZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__ctorMFNaNbNcNiNfS3std5range13__T6RepeatTiZ6RepeatZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opIndexMFNfkZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarTokenZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9searching12__ModuleInfoZ@Base 6
+ _D3std9algorithm9searching12__T7canFindZ20__T7canFindTAyhTAyaZ7canFindFNaNfAyhAyaZb@Base 6
+ _D3std9algorithm9searching12__T7canFindZ21__T7canFindTAyAaTAyaZ7canFindFNaNbNiNfAyAaAyaZb@Base 6
+ _D3std9algorithm9searching146__T4findVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ4findFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching159__T16simpleMindedFindVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ16simpleMindedFindFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching166__T10countUntilVAyaa6_61203d3d2062TAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10countUntilFNaNbNiNfAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZi@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxaTAywZ8skipOverFKAxaAywZ19__T9__lambda3TwTywZ9__lambda3FNaNbNiNfwywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxaTAywZ8skipOverFNaNfKAxaAywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxuTAywZ8skipOverFKAxuAywZ19__T9__lambda3TwTywZ9__lambda3FNaNbNiNfwywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxuTAywZ8skipOverFNaNfKAxuAywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxwTAywZ8skipOverFNaNbNiNfKAxwAywZb@Base 6
+ _D3std9algorithm9searching26__T14balancedParensTAxaTaZ14balancedParensFNaNfAxaaakZb@Base 6
+ _D3std9algorithm9searching29__T5countVAyaa4_74727565TAyaZ5countFNaNiNfAyaZk@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAhTAhZ4findFNaNbNiNfAhAhZAh@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAyaTaZ4findFAyaaZ13trustedMemchrFNaNbNiNeKAyaKaZAya@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAyaTaZ4findFNaNfAyaaZAya@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ16__T5forceTAhTAaZ5forceFNaNbNiNeAaZAh@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFNaNbNiNfAyaAaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAhTAxaZ5forceFNaNbNiNeAxaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAxaTAhZ5forceFNaNbNiNeAhZAxa@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFNaNbNiNfAxaAyaZAxa@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAhTAxaZ5forceFNaNbNiNeAxaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFNaNbNiNfAyaAxaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFAyaAyaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFAyaAyaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFNaNbNiNfAyaAyaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyhTAyaZ4findFNaNfAyhAyaZAyh@Base 6
+ _D3std9algorithm9searching37__T4findVAyaa6_61203d3d2062TAyAaTAyaZ4findFNaNbNiNfAyAaAyaZAyAa@Base 6
+ _D3std9algorithm9searching37__T5countVAyaa6_61203d3d2062TAyaTAyaZ5countFNaNbNiNfAyaAyaZk@Base 6
+ _D3std9algorithm9searching40__T10countUntilVAyaa6_61203d3d2062TAaTaZ10countUntilFNaNiNfAaaZi@Base 6
+ _D3std9algorithm9searching40__T10countUntilVAyaa6_61203d3d2062TAkTkZ10countUntilFNaNbNiNfAkkZi@Base 6
+ _D3std9algorithm9searching40__T8findSkipVAyaa6_61203d3d2062TAyaTAyaZ8findSkipFNaNbNiNfKAyaAyaZb@Base 6
+ _D3std9algorithm9searching41__T10startsWithVAyaa6_61203d3d2062TAhTAhZ10startsWithFNaNbNiNfAhAhZb@Base 6
+ _D3std9algorithm9searching41__T10startsWithVAyaa6_61203d3d2062TAxaTaZ10startsWithFNaNfAxaaZb@Base 6
+ _D3std9algorithm9searching41__T9findSplitVAyaa6_61203d3d2062TAyaTAyaZ9findSplitFNaNbNiNfAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAxaTAyaZ10startsWithFNaNbNiNfAxaAyaZb@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAyaTAyaZ10startsWithFNaNbNiNfAyaAyaZb@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAyhTAyaZ10startsWithFNaNfAyhAyaZb@Base 6
+ _D3std9algorithm9searching44__T10countUntilVAyaa6_61203d3d2062TAAyaTAyaZ10countUntilFNaNbNiNfAAyaAyaZi@Base 6
+ _D3std9algorithm9searching44__T10countUntilVAyaa6_61203d3d2062TAyAaTAyaZ10countUntilFNaNbNiNfAyAaAyaZi@Base 6
+ _D3std9algorithm9searching47__T10startsWithVAyaa6_61203d3d2062TAxaTAyaTAyaZ10startsWithFNaNfAxaAyaAyaZk@Base 6
+ _D3std9algorithm9searching50__T3anyS39_D3std4path14isDirSeparatorFNaNbNiNfwZbZ12__T3anyTAxaZ3anyFNaNfAxaZb@Base 6
+ _D3std9algorithm9searching51__T10startsWithVAyaa6_61203d3d2062TAxaTAyaTAyaTAyaZ10startsWithFNaNfAxaAyaAyaAyaZk@Base 6
+ _D3std9algorithm9searching55__T4findS39_D3std4path14isDirSeparatorFNaNbNiNfwZbTAxaZ4findFNaNfAxaZAxa@Base 6
+ _D3std9algorithm9searching76__T10countUntilVAyaa11_615b305d203e2030783830TAS3std3uni17CodepointIntervalZ10countUntilFNaNbNiNfAS3std3uni17CodepointIntervalZi@Base 6
+ _D3std9algorithm9searching89__T4findVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTaZ4findFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultaZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching92__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTiZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitioniZi@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10LeapSecondTyiZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10LeapSecondyiZi@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTyiZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionyiZi@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTylZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionylZi@Base 6
+ _D3std9container10binaryheap12__ModuleInfoZ@Base 6
+ _D3std9container12__ModuleInfoZ@Base 6
+ _D3std9container4util12__ModuleInfoZ@Base 6
+ _D3std9container5array12__ModuleInfoZ@Base 6
+ _D3std9container5dlist12__ModuleInfoZ@Base 6
+ _D3std9container5dlist6DRange4backMFNaNbNdNfZPS3std9container5dlist8BaseNode@Base 6
+ _D3std9container5dlist6DRange4saveMFNaNbNdNfZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange5emptyMxFNaNbNdNfZb@Base 6
+ _D3std9container5dlist6DRange5frontMFNaNbNdNfZPS3std9container5dlist8BaseNode@Base 6
+ _D3std9container5dlist6DRange6__ctorMFNaNbNcNfPS3std9container5dlist8BaseNodePS3std9container5dlist8BaseNodeZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange6__ctorMFNaNbNcNfPS3std9container5dlist8BaseNodeZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange6__initZ@Base 6
+ _D3std9container5dlist6DRange7popBackMFNaNbNfZv@Base 6
+ _D3std9container5dlist6DRange8popFrontMFNaNbNfZv@Base 6
+ _D3std9container5dlist8BaseNode6__initZ@Base 6
+ _D3std9container5dlist8BaseNode7connectFNaNbNfPS3std9container5dlist8BaseNodePS3std9container5dlist8BaseNodeZv@Base 6
+ _D3std9container5slist12__ModuleInfoZ@Base 6
+ _D3std9container6rbtree12__ModuleInfoZ@Base 6
+ _D3std9exception104__T11doesPointToTPyS3std8datetime13PosixTimeZone6TTInfoTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPyS3std8datetime13PosixTimeZone6TTInfoKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception104__T11doesPointToTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception105__T11doesPointToTAS3std8datetime13PosixTimeZone10LeapSecondTAS3std8datetime13PosixTimeZone10LeapSecondTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone10LeapSecondKxAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std9exception111__T11doesPointToTPxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception111__T11doesPointToTS3std8datetime13PosixTimeZone14TempTransitionTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxS3std8datetime13PosixTimeZone14TempTransitionKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTAS3std8datetime13PosixTimeZone14TempTransitionTAS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone14TempTransitionKxAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTPxS3std8datetime13PosixTimeZone14TransitionTypeTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPS3std8datetime13PosixTimeZone14TransitionTypeKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception115__T11doesPointToTkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception117__T11doesPointToTAxkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxAkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception118__T18isUnionAliasedImplTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception122__T11doesPointToTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception122__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki674Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki676Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki681Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki749Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki891Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki949Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki994Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception123__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1010Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception123__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1088Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception123__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1124Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception123__T12errnoEnforceTbVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1155Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception124__T12errnoEnforceTbVAyaa45_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki146Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception124__T12errnoEnforceTbVAyaa45_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki308Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception124__T12errnoEnforceTbVAyaa45_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki315Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception124__T12errnoEnforceTbVAyaa45_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki341Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception124__T12errnoEnforceTbVAyaa45_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki372Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception124__T12errnoEnforceTbVAyaa45_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki397Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception124__T12errnoEnforceTbVAyaa45_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki482Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception127__T12errnoEnforceTbVAyaa46_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f70726f636573732e64Vki2907Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception129__T11doesPointToTPxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception12__ModuleInfoZ@Base 6
+ _D3std9exception149__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki385Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception149__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki455Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception14ErrnoException5errnoMFNdZk@Base 6
+ _D3std9exception14ErrnoException6__ctorMFNeAyaAyakZC3std9exception14ErrnoException@Base 6
+ _D3std9exception14ErrnoException6__initZ@Base 6
+ _D3std9exception14ErrnoException6__vtblZ@Base 6
+ _D3std9exception14ErrnoException7__ClassZ@Base 6
+ _D3std9exception14RangePrimitive6__initZ@Base 6
+ _D3std9exception14__T7enforceTbZ7enforceFNaNfbLC6object9ThrowableZb@Base 6
+ _D3std9exception150__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1588Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTbVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfbLAyaZb@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTiVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfiLAyaZi@Base 6
+ (optional)_D3std9exception203__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception207__T11doesPointToTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiKAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTkZ12assumeUniqueFNaNbNiKAkZAyk@Base 6
+ _D3std9exception25__T11doesPointToTAkTAkTvZ11doesPointToFNaNbNiNeKxAkKxAkZb@Base 6
+ _D3std9exception25__T7bailOutHTC9ExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTiZ7enforceFNaNfiLAxaAyakZi@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTkZ7enforceFNaNfkLAxaAyakZk@Base 6
+ _D3std9exception289__T11doesPointToTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception28__T7enforceHTC9ExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception297__T11doesPointToTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception29__T11doesPointToTAAyaTAAyaTvZ11doesPointToFNaNbNiNeKxAAyaKxAAyaZb@Base 6
+ _D3std9exception37__T16collectExceptionHTC9ExceptionTmZ16collectExceptionFNaNbNfLmZC9Exception@Base 6
+ _D3std9exception39__T7bailOutHTC3std4json13JSONExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception40__T11doesPointToTAyaTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio4FileZb@Base 6
+ _D3std9exception40__T7bailOutHTC4core4time13TimeExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception41__T18isUnionAliasedImplTS3std5stdio4FileZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception41__T7enforceHTC3std4json13JSONExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception41__T9enforceExHTC3std4json13JSONExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception42__T7enforceHTC4core4time13TimeExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception43__T7bailOutHTC3std3net4curl13CurlExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std3net4curl4CurlZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std4file8DirEntryZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T7enforceTPS4core3sys5posix5netdb7hostentZ7enforceFNaNfPS4core3sys5posix5netdb7hostentLC6object9ThrowableZPS4core3sys5posix5netdb7hostent@Base 6
+ _D3std9exception45__T11doesPointToTbTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception45__T7enforceHTC3std3net4curl13CurlExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTkZ9enforceExFNaNfkLAyaAyakZk@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTtTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxtKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T7enforceHTC3std3net4curl13CurlExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception47__T11doesPointToTAyaTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception47__T11doesPointToTPxvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception48__T18isUnionAliasedImplTS3std3net4curl3FTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T11doesPointToTbTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxbKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToThTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxhKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTiTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxiKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTkTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxkKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTlTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxlKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTmTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxmKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTtTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxtKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4HTTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4SMTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAhZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAvZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T7bailOutHTC3std3net4curl20CurlTimeoutExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception51__T11doesPointToTAyaTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFxAaZvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFkkkkZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTwTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxwKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception52__T18isUnionAliasedImplTS3std4file15DirIteratorImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception52__T7enforceHTC3std3net4curl20CurlTimeoutExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception53__T11doesPointToTDFkkkkZiTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTDFkkkkZiTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTHAyaxAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxHAyaAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTS3std5stdio4FileTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio4FileZb@Base 6
+ _D3std9exception53__T7bailOutHTC3std11concurrency19TidMissingExceptionZ7bailOutFAyakxAaZv@Base 6
+ _D3std9exception54__T11doesPointToTAyaTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception54__T7enforceHTC9ExceptionTPOS4core4stdc5stdio8_IO_FILEZ7enforceFNaNfPOS4core4stdc5stdio8_IO_FILELAxaAyakZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception55__T18isUnionAliasedImplTS3std5stdio17LockingTextReaderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception55__T7enforceHTC3std11concurrency19TidMissingExceptionTbZ7enforceFbLAxaAyakZb@Base 6
+ _D3std9exception56__T18isUnionAliasedImplTS3std3net4curl4HTTP10StatusLineZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception57__T18isUnionAliasedImplTS4core3sys5posix3sys4stat6stat_tZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception60__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio4FileZb@Base 6
+ _D3std9exception63__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception63__T7enforceHTC3std4json13JSONExceptionTPNgS3std4json9JSONValueZ7enforceFNaNfPNgS3std4json9JSONValueLAxaAyakZPNgS3std4json9JSONValue@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTE3std4file8SpanModeTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxE3std4file8SpanModeKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std3net4curl3FTP4ImplTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl3FTP4ImplKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std4file8DirEntryTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std4file8DirEntryKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std5stdio4FileTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception67__T11doesPointToTlTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxlKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4HTTP4ImplTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP4ImplKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4SMTP4ImplTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4SMTP4ImplKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception70__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception70__T18isUnionAliasedImplTS3std8datetime13PosixTimeZone14TempTransitionZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception71__T11doesPointToTE3std3net4curl4HTTP6MethodTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxE3std3net4curl4HTTP6MethodKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception71__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception74__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception75__T11doesPointToTS3std4file15DirIteratorImplTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNeKxS3std4file15DirIteratorImplKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception76__T11doesPointToTS3std3net4curl4HTTP10StatusLineTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP10StatusLineKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTDFS3std3net4curl4HTTP10StatusLineZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFS3std3net4curl4HTTP10StatusLineZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTS4core3sys5posix3sys4stat6stat_tTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS4core3sys5posix3sys4stat6stat_tKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception81__T11doesPointToTS3std5stdio17LockingTextReaderTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio17LockingTextReaderKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception81__T18isUnionAliasedImplTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception93__T11doesPointToTAS3std5regex8internal2ir10NamedGroupTAS3std5regex8internal2ir10NamedGroupTvZ11doesPointToFNaNbNiNeKxAS3std5regex8internal2ir10NamedGroupKxAS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std9exception93__T7enforceHTC9ExceptionTPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZ7enforceFNaNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeLAxaAyakZPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std9exception94__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception96__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception96__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception99__T18isUnionAliasedImplTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9outbuffer12__ModuleInfoZ@Base 6
+ _D3std9outbuffer9OutBuffer11__invariantMxFZv@Base 6
+ _D3std9outbuffer9OutBuffer12__invariant1MxFZv@Base 6
+ _D3std9outbuffer9OutBuffer5fill0MFNaNbNfkZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeAxwZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNedZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeeZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNefZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNekZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNemZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNetZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeuZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNexAaZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNexAuZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfAxhZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfC3std9outbuffer9OutBufferZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfaZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfgZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfhZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfiZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNflZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfsZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfwZv@Base 6
+ _D3std9outbuffer9OutBuffer6__ctorMFNaNbNfZC3std9outbuffer9OutBuffer@Base 6
+ _D3std9outbuffer9OutBuffer6__initZ@Base 6
+ _D3std9outbuffer9OutBuffer6__vtblZ@Base 6
+ _D3std9outbuffer9OutBuffer6align2MFNaNbNfZv@Base 6
+ _D3std9outbuffer9OutBuffer6align4MFNaNbNfZv@Base 6
+ _D3std9outbuffer9OutBuffer6printfMFNeAyaYv@Base 6
+ _D3std9outbuffer9OutBuffer6spreadMFNaNbNfkkZv@Base 6
+ _D3std9outbuffer9OutBuffer7__ClassZ@Base 6
+ _D3std9outbuffer9OutBuffer7reserveMFNaNbNekZv@Base 6
+ _D3std9outbuffer9OutBuffer7toBytesMFNaNbNfZAh@Base 6
+ _D3std9outbuffer9OutBuffer7vprintfMFNbNeAyaPaZv@Base 6
+ _D3std9outbuffer9OutBuffer8toStringMxFNaNbNfZAya@Base 6
+ _D3std9outbuffer9OutBuffer9alignSizeMFNaNbNfkZv@Base 6
+ _D3std9stdiobase12__ModuleInfoZ@Base 6
+ _D3std9stdiobase18_sharedStaticCtor1FZv@Base 6
+ _D3std9typetuple12__ModuleInfoZ@Base 6
+ _D401TypeInfo_S3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D403TypeInfo_S3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D403TypeInfo_S3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D404TypeInfo_S3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D407TypeInfo_S3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D40TypeInfo_C3std11concurrency11IsGenerator6__initZ@Base 6
+ _D40TypeInfo_E3std3uni20UnicodeDecomposition6__initZ@Base 6
+ _D40TypeInfo_E3std6socket17SocketOptionLevel6__initZ@Base 6
+ _D40TypeInfo_E3std6traits17FunctionAttribute6__initZ@Base 6
+ _D40TypeInfo_E3std7numeric16CustomFloatFlags6__initZ@Base 6
+ _D40TypeInfo_E3std8encoding15Windows1252Char6__initZ@Base 6
+ _D40TypeInfo_E3std9exception14RangePrimitive6__initZ@Base 6
+ _D40TypeInfo_S3etc1c7sqlite314sqlite3_module6__initZ@Base 6
+ _D40TypeInfo_S3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D40TypeInfo_xC3std11concurrency10MessageBox6__initZ@Base 6
+ _D41TypeInfo_AE3std8encoding15Windows1252Char6__initZ@Base 6
+ _D41TypeInfo_E3etc1c4curl18CurlFInfoFlagKnown6__initZ@Base 6
+ _D41TypeInfo_E3std8datetime16AllowDayOverflow6__initZ@Base 6
+ _D41TypeInfo_HAyaDFC3std3xml13ElementParserZv6__initZ@Base 6
+ _D41TypeInfo_S3std11parallelism12AbstractTask6__initZ@Base 6
+ _D41TypeInfo_S3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D41TypeInfo_S3std4math20FloatingPointControl6__initZ@Base 6
+ _D41TypeInfo_S3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D41TypeInfo_xS3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D426TypeInfo_S3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__initZ@Base 6
+ _D427TypeInfo_xS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__initZ@Base 6
+ _D42TypeInfo_AC3std3xml21ProcessingInstruction6__initZ@Base 6
+ _D42TypeInfo_AS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D42TypeInfo_E3std5regex8internal2ir9RegexInfo6__initZ@Base 6
+ _D42TypeInfo_HaE3std6traits17FunctionAttribute6__initZ@Base 6
+ _D42TypeInfo_S3std3net4curl12__T4PoolTAhZ4Pool6__initZ@Base 6
+ _D42TypeInfo_S3std5range13__T6RepeatTiZ6Repeat6__initZ@Base 6
+ _D42TypeInfo_xS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D42TypeInfo_xS3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D42TypeInfo_xS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D42TypeInfo_xS4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D43TypeInfo_AxS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D43TypeInfo_E3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D43TypeInfo_E3std9algorithm10comparison6EditOp6__initZ@Base 6
+ _D43TypeInfo_FS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D43TypeInfo_PxS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D43TypeInfo_S3std1c5linux5linux13struct_stat646__initZ@Base 6
+ _D43TypeInfo_S3std5range14__T6ChunksTAhZ6Chunks6__initZ@Base 6
+ _D43TypeInfo_xAS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D43TypeInfo_xPS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D44TypeInfo_DFS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D44TypeInfo_E3std6traits21ParameterStorageClass6__initZ@Base 6
+ _D44TypeInfo_E3std9algorithm7sorting10SortOutput6__initZ@Base 6
+ _D44TypeInfo_E3std9algorithm9searching9OpenRight6__initZ@Base 6
+ _D44TypeInfo_S3etc1c7sqlite318sqlite3_index_info6__initZ@Base 6
+ _D44TypeInfo_S3etc1c7sqlite318sqlite3_io_methods6__initZ@Base 6
+ _D44TypeInfo_S3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D44TypeInfo_S3std5stdio4File17LockingTextWriter6__initZ@Base 6
+ _D44TypeInfo_xC3std11concurrency14LinkTerminated6__initZ@Base 6
+ _D44TypeInfo_xE3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D45TypeInfo_AS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D45TypeInfo_E3std5regex8internal2ir11RegexOption6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_mem_methods6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_pcache_page6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_vtab_cursor6__initZ@Base 6
+ _D45TypeInfo_S3std3net4curl20AsyncChunkInputRange6__initZ@Base 6
+ _D45TypeInfo_S3std7numeric14__T6StrideTAfZ6Stride6__initZ@Base 6
+ _D45TypeInfo_S3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D45TypeInfo_S3std8typecons14__T5TupleTbTiZ5Tuple6__initZ@Base 6
+ _D45TypeInfo_S3std8typecons14__T5TupleTkTkZ5Tuple6__initZ@Base 6
+ _D45TypeInfo_xC3std11concurrency15OwnerTerminated6__initZ@Base 6
+ _D45TypeInfo_xDFS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D45TypeInfo_xS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_AxS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_E3std11parallelism8TaskPool9PoolState6__initZ@Base 6
+ _D46TypeInfo_S3std3uni7unicode18hangulSyllableType6__initZ@Base 6
+ _D46TypeInfo_S3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D46TypeInfo_S3std6traits23__InoutWorkaroundStruct6__initZ@Base 6
+ _D46TypeInfo_S3std7complex14__T7ComplexTeZ7Complex6__initZ@Base 6
+ _D46TypeInfo_S3std8internal14unicode_tables6blocks6__initZ@Base 6
+ _D46TypeInfo_S3std8internal14unicode_tables6hangul6__initZ@Base 6
+ _D46TypeInfo_xAS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_yS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D47TypeInfo_AC3std11parallelism17ParallelismThread6__initZ@Base 6
+ _D47TypeInfo_AS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D47TypeInfo_E3std8internal4test10dummyrange6Length6__initZ@Base 6
+ _D47TypeInfo_E3std9algorithm8mutation12SwapStrategy6__initZ@Base 6
+ _D47TypeInfo_PyS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D47TypeInfo_S3etc1c7sqlite321sqlite3_mutex_methods6__initZ@Base 6
+ _D47TypeInfo_S3std5array16__T8AppenderTAaZ8Appender6__initZ@Base 6
+ _D47TypeInfo_S3std5array16__T8AppenderTAhZ8Appender6__initZ@Base 6
+ _D47TypeInfo_S3std6traits15__T8DemangleTkZ8Demangle6__initZ@Base 6
+ _D47TypeInfo_S3std8bitmanip14__T7BitsSetTkZ7BitsSet6__initZ@Base 6
+ _D47TypeInfo_S3std8internal14unicode_tables7scripts6__initZ@Base 6
+ _D47TypeInfo_S3std8typecons16__T5TupleTiTAyaZ5Tuple6__initZ@Base 6
+ _D47TypeInfo_S3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D47TypeInfo_xS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_APyS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D48TypeInfo_AS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D48TypeInfo_AxS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_E3std4uuid20UUIDParsingException6Reason6__initZ@Base 6
+ _D48TypeInfo_S3etc1c7sqlite322sqlite3_pcache_methods6__initZ@Base 6
+ _D48TypeInfo_S3etc1c7sqlite322sqlite3_rtree_geometry6__initZ@Base 6
+ _D48TypeInfo_S3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAxaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAyaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAyuZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAywZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTyAaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std8internal14unicode_tables8uniProps6__initZ@Base 6
+ _D48TypeInfo_xAS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_xC3std12experimental6logger4core6Logger6__initZ@Base 6
+ _D48TypeInfo_xS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_AxS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_E3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D49TypeInfo_E3std8internal4test10dummyrange8ReturnBy6__initZ@Base 6
+ _D49TypeInfo_E3std8typecons24RefCountedAutoInitialize6__initZ@Base 6
+ _D49TypeInfo_S3etc1c7sqlite323sqlite3_pcache_methods26__initZ@Base 6
+ _D49TypeInfo_S3std12experimental6logger4core8MsgRange6__initZ@Base 6
+ _D49TypeInfo_S3std3uni18simpleCaseFoldingsFNewZ5Range6__initZ@Base 6
+ _D49TypeInfo_S3std5array18__T8AppenderTAAyaZ8Appender6__initZ@Base 6
+ _D49TypeInfo_S3std5regex18__T8CapturesTAaTkZ8Captures6__initZ@Base 6
+ _D49TypeInfo_S3std6stream6Stream6toHashMFNeZ8resUnion6__initZ@Base 6
+ _D49TypeInfo_S3std8datetime24ComparingBenchmarkResult6__initZ@Base 6
+ _D49TypeInfo_S3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D49TypeInfo_S3std8internal4math11biguintcore7BigUint6__initZ@Base 6
+ _D49TypeInfo_S3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_xAS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_xS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D4core4stdc6stdarg11__T6va_argZ6va_argFNaNbNiKPaC8TypeInfoPvZv@Base 6
+ _D4core4time12TickDuration22__T8opBinaryVAyaa1_2bZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration25__T10opOpAssignVAyaa1_2bZ10opOpAssignMFNaNbNcNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_6d73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T18getUnitsFromHNSecsVAyaa6_686e73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7573656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa6_686e73656373VAyaa4_64617973Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time48__T7convertVAyaa4_64617973VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_686f757273VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7573656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_686f757273Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa5_686f757273VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_6d696e75746573Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time7FracSec28__T4fromVAyaa6_686e73656373Z4fromFNaNflZS4core4time7FracSec@Base 6
+ _D4core4time8Duration27__T5totalVAyaa5_6d73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration29__T5totalVAyaa6_686e73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration31__T5totalVAyaa7_7365636f6e6473Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration43__T8opBinaryVAyaa1_2bTS4core4time8DurationZ8opBinaryMxFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration44__T8opBinaryVAyaa1_2bTxS4core4time8DurationZ8opBinaryMxFNaNbNiNfxS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration44__T8opBinaryVAyaa1_2bTyS4core4time8DurationZ8opBinaryMxFNaNbNiNfyS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z14__T5splitTiTiZ5splitMxFNaNbNiNfJiJiZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z14__T5splitTiTiZ5splitMxFNaNbNiNfJiJiZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration48__T8opBinaryVAyaa1_2dTS4core4time12TickDurationZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration51__T10opOpAssignVAyaa1_2dTS4core4time12TickDurationZ10opOpAssignMFNaNbNcNiNfxS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration54__T13opBinaryRightVAyaa1_2bTS4core4time12TickDurationZ13opBinaryRightMxFNaNbNiNfS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core6atomic122__T11atomicStoreVE4core6atomic11MemoryOrderi5TE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateZ11atomicStoreFNaNbNiKOE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZv@Base 6
+ _D4core6atomic122__T3casTE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateZ3casFNaNbNiPOE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D4core6atomic125__T11atomicStoreVE4core6atomic11MemoryOrderi3TC3std12experimental6logger4core6LoggerTOC3std12experimental6logger4core6LoggerZ11atomicStoreFNaNbNiKOC3std12experimental6logger4core6LoggerOC3std12experimental6logger4core6LoggerZv@Base 6
+ _D4core6atomic128__T11atomicStoreVE4core6atomic11MemoryOrderi3TE3std12experimental6logger4core8LogLevelTE3std12experimental6logger4core8LogLevelZ11atomicStoreFNaNbNiKOE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D4core6atomic128__T7casImplTE3std11parallelism8TaskPool9PoolStateTxE3std11parallelism8TaskPool9PoolStateTxE3std11parallelism8TaskPool9PoolStateZ7casImplFNaNbNiPOE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D4core6atomic14__T3casTbTbTbZ3casFNaNbNiPObxbxbZb@Base 6
+ _D4core6atomic20__T7casImplTbTxbTxbZ7casImplFNaNbNiPObxbxbZb@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi2TbZ10atomicLoadFNaNbNiKOxbZb@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5ThZ10atomicLoadFNaNbNiKOxhZh@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5TkZ10atomicLoadFNaNbNiKOxkZk@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi3TbTbZ11atomicStoreFNaNbNiKObbZv@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi5ThThZ11atomicStoreFNaNbNiKOhhZv@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi5TkTkZ11atomicStoreFNaNbNiKOkkZv@Base 6
+ _D4core6atomic58__T3casTC4core4sync5mutex5MutexTnTC4core4sync5mutex5MutexZ3casFNaNbNiPOC4core4sync5mutex5MutexOxnOC4core4sync5mutex5MutexZb@Base 6
+ _D4core6atomic65__T7casImplTC4core4sync5mutex5MutexTOxnTOC4core4sync5mutex5MutexZ7casImplFNaNbNiPOC4core4sync5mutex5MutexOxnOC4core4sync5mutex5MutexZb@Base 6
+ _D4core6atomic69__T10atomicLoadVE4core6atomic11MemoryOrderi2TC4core4sync5mutex5MutexZ10atomicLoadFNaNbNiKOxC4core4sync5mutex5MutexZC4core4sync5mutex5Mutex@Base 6
+ _D4core6atomic83__T10atomicLoadVE4core6atomic11MemoryOrderi5TE3std11parallelism8TaskPool9PoolStateZ10atomicLoadFNaNbNiKOxE3std11parallelism8TaskPool9PoolStateZE3std11parallelism8TaskPool9PoolState@Base 6
+ _D4core6atomic84__T10atomicLoadVE4core6atomic11MemoryOrderi2TC3std12experimental6logger4core6LoggerZ10atomicLoadFNaNbNiKOxC3std12experimental6logger4core6LoggerZC3std12experimental6logger4core6Logger@Base 6
+ _D4core6atomic86__T10atomicLoadVE4core6atomic11MemoryOrderi2TE3std12experimental6logger4core8LogLevelZ10atomicLoadFNaNbNiKOxE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D4core8internal4hash15__T6hashOfTAxaZ6hashOfFNaNbNfKAxakZk@Base 6
+ _D4core8internal4hash15__T6hashOfTAyaZ6hashOfFNaNbNfKAyakZk@Base 6
+ _D4core8internal7convert15__T7toUbyteTxaZ7toUbyteFNaNbNiNeAxaZAxh@Base 6
+ _D4core8internal7convert15__T7toUbyteTyaZ7toUbyteFNaNbNiNeAyaZAxh@Base 6
+ _D50TypeInfo_E3std8internal4test10dummyrange9RangeType6__initZ@Base 6
+ _D50TypeInfo_PxS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D50TypeInfo_S3etc1c7sqlite324sqlite3_rtree_query_info6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTbVki1Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTkVki7Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTkVki8Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std5regex19__T8CapturesTAxaTkZ8Captures6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D50TypeInfo_xE3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D50TypeInfo_xPS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D50TypeInfo_xS3std5regex18__T8CapturesTAaTkZ8Captures6__initZ@Base 6
+ _D50TypeInfo_yS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D51TypeInfo_AyS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki11Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki12Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki13Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki14Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki15Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki16Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii160Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std7variant18__T8VariantNVki24Z8VariantN6__initZ@Base 6
+ _D51TypeInfo_xS3std5regex19__T8CapturesTAxaTkZ8Captures6__initZ@Base 6
+ _D51TypeInfo_xS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_xS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D51TypeInfo_yS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_yS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_AxS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_AxS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_AyS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_AyS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std5array16__T8AppenderTAaZ8Appender4Data6__initZ@Base 6
+ _D52TypeInfo_S3std5array16__T8AppenderTAhZ8Appender4Data6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D52TypeInfo_xAS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_xAS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_xAyS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D52TypeInfo_xS3std7variant18__T8VariantNVki24Z8VariantN6__initZ@Base 6
+ _D53TypeInfo_AS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAxaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAyaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAyuZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAywZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTyAaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5regex8internal12backtracking9CtContext6__initZ@Base 6
+ _D53TypeInfo_S3std6format18__T10FormatSpecTaZ10FormatSpec6__initZ@Base 6
+ _D53TypeInfo_S3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D54TypeInfo_AxS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D54TypeInfo_G3S3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std5array18__T8AppenderTAAyaZ8Appender4Data6__initZ@Base 6
+ _D54TypeInfo_S3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D54TypeInfo_S3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D54TypeInfo_S3std8internal14unicode_tables13FullCaseEntry6__initZ@Base 6
+ _D54TypeInfo_xAS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D55TypeInfo_AS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D55TypeInfo_PS3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D55TypeInfo_S3std5range13__T6RepeatTiZ6Repeat11DollarToken6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_xG3S3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D55TypeInfo_xS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D56TypeInfo_APS3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D56TypeInfo_AxS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D56TypeInfo_E3std7variant18__T8VariantNVki24Z8VariantN4OpID6__initZ@Base 6
+ _D56TypeInfo_S3std12experimental6logger4core6Logger8LogEntry6__initZ@Base 6
+ _D56TypeInfo_S3std5range14__T6ChunksTAhZ6Chunks11DollarToken6__initZ@Base 6
+ _D56TypeInfo_S3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D56TypeInfo_S3std8internal14unicode_tables15SimpleCaseEntry6__initZ@Base 6
+ _D56TypeInfo_S3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D56TypeInfo_xAS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D57TypeInfo_S3std3net4curl19__T11CurlMessageTbZ11CurlMessage6__initZ@Base 6
+ _D57TypeInfo_S3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6__initZ@Base 6
+ _D57TypeInfo_xS3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D57TypeInfo_yS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D581TypeInfo_S3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result6__initZ@Base 6
+ _D58TypeInfo_AyS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D58TypeInfo_E3std8typecons28__T4FlagVAyaa6_756e73616665Z4Flag6__initZ@Base 6
+ _D58TypeInfo_xS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6__initZ@Base 6
+ _D59TypeInfo_S3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage6__initZ@Base 6
+ _D59TypeInfo_xAyS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D60TypeInfo_E3std3net4curl20AsyncChunkInputRange8__mixin55State6__initZ@Base 6
+ _D60TypeInfo_S3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D60TypeInfo_S3std5regex8internal6parser15__T6ParserTAyaZ6Parser6__initZ@Base 6
+ _D60TypeInfo_S3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D61TypeInfo_S3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D61TypeInfo_S3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D61TypeInfo_S3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTaZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTbZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperThZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTiZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTkZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTlZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTmZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTtZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_xE3std3net4curl20AsyncChunkInputRange8__mixin55State6__initZ@Base 6
+ _D61TypeInfo_xS3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D62TypeInfo_AS3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D62TypeInfo_PxS3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D62TypeInfo_S3std8bitmanip22__T13EndianSwapperTxkZ13EndianSwapper6__initZ@Base 6
+ _D62TypeInfo_xPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D62TypeInfo_xS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D63TypeInfo_S3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D64TypeInfo_E3std8typecons34__T4FlagVAyaa9_706970654f6e506f70Z4Flag6__initZ@Base 6
+ _D64TypeInfo_S3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D64TypeInfo_S3std7variant18__T8VariantNVki24Z8VariantN11SizeChecker6__initZ@Base 6
+ _D64TypeInfo_S3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__initZ@Base 6
+ _D64TypeInfo_xS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D65TypeInfo_S3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D65TypeInfo_S3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG24hZ5Tuple6__initZ@Base 6
+ _D65TypeInfo_S3std8typecons34__T5TupleTC14TypeInfo_ClassTPG24hZ5Tuple6__initZ@Base 6
+ _D65TypeInfo_xS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D66TypeInfo_S3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D66TypeInfo_S3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__initZ@Base 6
+ _D66TypeInfo_S3std8typecons35__T5TupleTC15TypeInfo_StructTPG24hZ5Tuple6__initZ@Base 6
+ _D66TypeInfo_S3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__initZ@Base 6
+ _D66TypeInfo_xS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D670TypeInfo_S3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result6__initZ@Base 6
+ _D67TypeInfo_AS3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D67TypeInfo_S3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D67TypeInfo_S3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__initZ@Base 6
+ _D67TypeInfo_S3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6__initZ@Base 6
+ _D67TypeInfo_S3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result6__initZ@Base 6
+ _D68TypeInfo_xS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D69TypeInfo_E3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D69TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG24hZ5Tuple6__initZ@Base 6
+ _D69TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D6object102__T11_trustedDupTS3std8datetime13PosixTimeZone10LeapSecondTyS3std8datetime13PosixTimeZone10LeapSecondZ11_trustedDupFNaNbNeAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object102__T11_trustedDupTS3std8datetime13PosixTimeZone10TransitionTyS3std8datetime13PosixTimeZone10TransitionZ11_trustedDupFNaNbNeAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object10__T3dupTaZ3dupFNaNbNdNfAxaZAa@Base 6
+ _D6object10__T3dupThZ3dupFNaNbNdNfAxhZAh@Base 6
+ _D6object10__T3dupTkZ3dupFNaNbNdNfAxkZAk@Base 6
+ _D6object11__T4idupTaZ4idupFNaNbNdNfAaZAya@Base 6
+ _D6object12__T3dupTAyaZ3dupFNaNbNdNfAxAyaZAAya@Base 6
+ _D6object12__T3getTkTkZ3getFNaNfNgHkkkLNgkZNgk@Base 6
+ _D6object12__T4idupTxaZ4idupFNaNbNdNfAxaZAya@Base 6
+ _D6object12__T4idupTxhZ4idupFNaNbNdNfAxhZAyh@Base 6
+ _D6object12__T4idupTxuZ4idupFNaNbNdNfAxuZAyu@Base 6
+ _D6object12__T4idupTxwZ4idupFNaNbNdNfAxwZAyw@Base 6
+ _D6object14__T4_dupTaTyaZ4_dupFNaNbAaZAya@Base 6
+ _D6object14__T4_dupTxaTaZ4_dupFNaNbAxaZAa@Base 6
+ _D6object14__T4_dupTxhThZ4_dupFNaNbAxhZAh@Base 6
+ _D6object14__T4_dupTxkTkZ4_dupFNaNbAxkZAk@Base 6
+ _D6object14__T7_rawDupTaZ7_rawDupFNaNbANgaZANga@Base 6
+ _D6object14__T7_rawDupThZ7_rawDupFNaNbANghZANgh@Base 6
+ _D6object14__T7_rawDupTkZ7_rawDupFNaNbANgkZANgk@Base 6
+ _D6object14__T7_rawDupTuZ7_rawDupFNaNbANguZANgu@Base 6
+ _D6object14__T7_rawDupTwZ7_rawDupFNaNbANgwZANgw@Base 6
+ _D6object14__T7reserveTaZ7reserveFNaNbNeKAakZk@Base 6
+ _D6object15__T4_dupTxaTyaZ4_dupFNaNbAxaZAya@Base 6
+ _D6object15__T4_dupTxhTyhZ4_dupFNaNbAxhZAyh@Base 6
+ _D6object15__T4_dupTxuTyuZ4_dupFNaNbAxuZAyu@Base 6
+ _D6object15__T4_dupTxwTywZ4_dupFNaNbAxwZAyw@Base 6
+ _D6object15__T6hashOfTAxaZ6hashOfFNaNbNfKAxakZk@Base 6
+ _D6object15__T6hashOfTAyaZ6hashOfFNaNbNfKAyakZk@Base 6
+ _D6object15__T8capacityTaZ8capacityFNaNbNdAaZk@Base 6
+ _D6object15__T8capacityThZ8capacityFNaNbNdAhZk@Base 6
+ _D6object15__T8capacityTiZ8capacityFNaNbNdAiZk@Base 6
+ _D6object16__T7_rawDupTAyaZ7_rawDupFNaNbANgAyaZANgAya@Base 6
+ _D6object17__T8capacityTAyaZ8capacityFNaNbNdAAyaZk@Base 6
+ _D6object18__T4_dupTxAyaTAyaZ4_dupFNaNbAxAyaZAAya@Base 6
+ _D6object19__T11_doPostblitTaZ11_doPostblitFNaNbNiNfAaZv@Base 6
+ _D6object19__T11_doPostblitThZ11_doPostblitFNaNbNiNfAhZv@Base 6
+ _D6object19__T11_doPostblitTkZ11_doPostblitFNaNbNiNfAkZv@Base 6
+ _D6object20__T11_doPostblitTyaZ11_doPostblitFNaNbNiNfAyaZv@Base 6
+ _D6object20__T11_doPostblitTyhZ11_doPostblitFNaNbNiNfAyhZv@Base 6
+ _D6object20__T11_doPostblitTyuZ11_doPostblitFNaNbNiNfAyuZv@Base 6
+ _D6object20__T11_doPostblitTywZ11_doPostblitFNaNbNiNfAywZv@Base 6
+ _D6object20__T12_getPostblitTaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKaZv@Base 6
+ _D6object20__T12_getPostblitThZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKhZv@Base 6
+ _D6object20__T12_getPostblitTkZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKkZv@Base 6
+ _D6object21__T11_doPostblitTAyaZ11_doPostblitFNaNbNiNfAAyaZv@Base 6
+ _D6object21__T12_getPostblitTyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyaZv@Base 6
+ _D6object21__T12_getPostblitTyhZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyhZv@Base 6
+ _D6object21__T12_getPostblitTyuZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyuZv@Base 6
+ _D6object21__T12_getPostblitTywZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKywZv@Base 6
+ _D6object22__T11_trustedDupTaTyaZ11_trustedDupFNaNbNeAaZAya@Base 6
+ _D6object22__T11_trustedDupTxaTaZ11_trustedDupFNaNbNeAxaZAa@Base 6
+ _D6object22__T11_trustedDupTxhThZ11_trustedDupFNaNbNeAxhZAh@Base 6
+ _D6object22__T11_trustedDupTxkTkZ11_trustedDupFNaNbNeAxkZAk@Base 6
+ _D6object22__T12_getPostblitTAyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKAyaZv@Base 6
+ _D6object23__T11_trustedDupTxaTyaZ11_trustedDupFNaNbNeAxaZAya@Base 6
+ _D6object23__T11_trustedDupTxhTyhZ11_trustedDupFNaNbNeAxhZAyh@Base 6
+ _D6object23__T11_trustedDupTxuTyuZ11_trustedDupFNaNbNeAxuZAyu@Base 6
+ _D6object23__T11_trustedDupTxwTywZ11_trustedDupFNaNbNeAxwZAyw@Base 6
+ _D6object24__T16assumeSafeAppendTkZ16assumeSafeAppendFNbNcKNgAkZNgAk@Base 6
+ _D6object26__T11_trustedDupTxAyaTAyaZ11_trustedDupFNaNbNeAxAyaZAAya@Base 6
+ _D6object29__T7destroyTS3std5stdio4FileZ7destroyFNfKS3std5stdio4FileZv@Base 6
+ _D6object33__T8capacityTS3std4file8DirEntryZ8capacityFNaNbNdAS3std4file8DirEntryZk@Base 6
+ _D6object36__T7destroyTS3std3net4curl3FTP4ImplZ7destroyFKS3std3net4curl3FTP4ImplZv@Base 6
+ _D6object37__T7destroyTS3std3net4curl4HTTP4ImplZ7destroyFKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D6object37__T7destroyTS3std3net4curl4SMTP4ImplZ7destroyFKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D6object39__T16_destructRecurseTS3std5stdio4FileZ16_destructRecurseFNfKS3std5stdio4FileZv@Base 6
+ _D6object39__T7destroyTS3std11concurrency7MessageZ7destroyFKS3std11concurrency7MessageZv@Base 6
+ _D6object39__T8capacityTS3std6socket11AddressInfoZ8capacityFNaNbNdAS3std6socket11AddressInfoZk@Base 6
+ _D6object40__T11_doPostblitTS3std11concurrency3TidZ11_doPostblitFNaNbNiNfAS3std11concurrency3TidZv@Base 6
+ _D6object40__T7destroyTS3std4file15DirIteratorImplZ7destroyFKS3std4file15DirIteratorImplZv@Base 6
+ _D6object41__T12_getPostblitTS3std11concurrency3TidZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKS3std11concurrency3TidZv@Base 6
+ _D6object45__T7reserveTS3std5regex8internal2ir8BytecodeZ7reserveFNaNbNeKAS3std5regex8internal2ir8BytecodekZk@Base 6
+ _D6object46__T16_destructRecurseTS3std3net4curl3FTP4ImplZ16_destructRecurseFKS3std3net4curl3FTP4ImplZv@Base 6
+ _D6object47__T16_destructRecurseTS3std3net4curl4HTTP4ImplZ16_destructRecurseFKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D6object47__T16_destructRecurseTS3std3net4curl4SMTP4ImplZ16_destructRecurseFKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D6object49__T16_destructRecurseTS3std11concurrency7MessageZ16_destructRecurseFKS3std11concurrency7MessageZv@Base 6
+ _D6object50__T16_destructRecurseTS3std4file15DirIteratorImplZ16_destructRecurseFKS3std4file15DirIteratorImplZv@Base 6
+ _D6object51__T4idupTS3std8datetime13PosixTimeZone10LeapSecondZ4idupFNaNbNdNfAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object51__T4idupTS3std8datetime13PosixTimeZone10TransitionZ4idupFNaNbNdNfAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object51__T8capacityTS3std4file15DirIteratorImpl9DirHandleZ8capacityFNaNbNdAS3std4file15DirIteratorImpl9DirHandleZk@Base 6
+ _D6object54__T7_rawDupTS3std8datetime13PosixTimeZone10LeapSecondZ7_rawDupFNaNbANgS3std8datetime13PosixTimeZone10LeapSecondZANgS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object54__T7_rawDupTS3std8datetime13PosixTimeZone10TransitionZ7_rawDupFNaNbANgS3std8datetime13PosixTimeZone10TransitionZANgS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object57__T8_ArrayEqTxS3std4json9JSONValueTxS3std4json9JSONValueZ8_ArrayEqFNaNbNiAxS3std4json9JSONValueAxS3std4json9JSONValueZb@Base 6
+ _D6object60__T11_doPostblitTyS3std8datetime13PosixTimeZone10LeapSecondZ11_doPostblitFNaNbNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D6object60__T11_doPostblitTyS3std8datetime13PosixTimeZone10TransitionZ11_doPostblitFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D6object60__T4keysHTHS3std11concurrency3TidbTbTS3std11concurrency3TidZ4keysFNaNbNdHS3std11concurrency3TidbZAS3std11concurrency3Tid@Base 6
+ _D6object61__T12_getPostblitTyS3std8datetime13PosixTimeZone10LeapSecondZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKyS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D6object61__T12_getPostblitTyS3std8datetime13PosixTimeZone10TransitionZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D6object61__T16assumeSafeAppendTS3std8typecons16__T5TupleTkTkTkZ5TupleZ16assumeSafeAppendFNbNcKNgAS3std8typecons16__T5TupleTkTkTkZ5TupleZNgAS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D6object62__T4keysHTxHAyaS3std4json9JSONValueTxS3std4json9JSONValueTAyaZ4keysFNaNbNdxHAyaS3std4json9JSONValueZAAya@Base 6
+ _D6object83__T16assumeSafeAppendTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ16assumeSafeAppendFNbNcKNgAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZNgAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D6object87__T16assumeSafeAppendTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16assumeSafeAppendFNbNcKNgAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZNgAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D6object90__T16assumeSafeAppendTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZ16assumeSafeAppendFNbNcKNgAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZNgAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D6object93__T8_ArrayEqTxS3std8typecons16__T5TupleTkTkTkZ5TupleTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ8_ArrayEqFNaNbNiNfAxS3std8typecons16__T5TupleTkTkTkZ5TupleAxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D6object94__T4_dupTS3std8datetime13PosixTimeZone10LeapSecondTyS3std8datetime13PosixTimeZone10LeapSecondZ4_dupFNaNbAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object94__T4_dupTS3std8datetime13PosixTimeZone10TransitionTyS3std8datetime13PosixTimeZone10TransitionZ4_dupFNaNbAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D70TypeInfo_AE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D70TypeInfo_S3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D70TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6__initZ@Base 6
+ _D70TypeInfo_S3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data6__initZ@Base 6
+ _D70TypeInfo_S3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__initZ@Base 6
+ _D70TypeInfo_S3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6__initZ@Base 6
+ _D70TypeInfo_S3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList6__initZ@Base 6
+ _D70TypeInfo_xE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_AxE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_E3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4Flag6__initZ@Base 6
+ _D71TypeInfo_S3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D71TypeInfo_S3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__initZ@Base 6
+ _D71TypeInfo_S3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6__initZ@Base 6
+ _D71TypeInfo_xAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_xS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D71TypeInfo_xS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList6__initZ@Base 6
+ _D72TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D72TypeInfo_S3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__initZ@Base 6
+ _D72TypeInfo_S3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D72TypeInfo_S3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D72TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D72TypeInfo_xS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D73TypeInfo_E3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4Flag6__initZ@Base 6
+ _D73TypeInfo_S3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D73TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D73TypeInfo_S3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D73TypeInfo_S3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D74TypeInfo_AS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D74TypeInfo_S3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D74TypeInfo_S3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__initZ@Base 6
+ _D74TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D74TypeInfo_xS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D74TypeInfo_xS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D75TypeInfo_AxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D75TypeInfo_E3std8typecons45__T4FlagVAyaa14_6b6565705465726d696e61746f72Z4Flag6__initZ@Base 6
+ _D75TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D75TypeInfo_xAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D76TypeInfo_S3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D76TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__initZ@Base 6
+ _D76TypeInfo_S3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D76TypeInfo_S3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data6__initZ@Base 6
+ _D76TypeInfo_S3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D76TypeInfo_S3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink6__initZ@Base 6
+ _D76TypeInfo_S3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry6__initZ@Base 6
+ _D76TypeInfo_xS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_AS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D77TypeInfo_PxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_S3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__initZ@Base 6
+ _D77TypeInfo_xPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_xS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D77TypeInfo_xS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D78TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D78TypeInfo_S3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__initZ@Base 6
+ _D78TypeInfo_S3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__initZ@Base 6
+ _D78TypeInfo_S3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D78TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D79TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6__initZ@Base 6
+ _D79TypeInfo_S3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6__initZ@Base 6
+ _D79TypeInfo_S3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D79TypeInfo_S3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D79TypeInfo_xS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D80TypeInfo_S3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__initZ@Base 6
+ _D80TypeInfo_S3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D83TypeInfo_E3std8typecons53__T4FlagVAyaa18_707265736572766541747472696275746573Z4Flag6__initZ@Base 6
+ _D83TypeInfo_S3std3uni51__T10assumeSizeS28_D3std3uni5low_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D83TypeInfo_S3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D83TypeInfo_S3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange6__initZ@Base 6
+ _D83TypeInfo_S3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry6__initZ@Base 6
+ _D84TypeInfo_E3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ5State6__initZ@Base 6
+ _D84TypeInfo_S3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__initZ@Base 6
+ _D84TypeInfo_xS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D85TypeInfo_E3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flag6__initZ@Base 6
+ _D85TypeInfo_S3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__initZ@Base 6
+ _D85TypeInfo_S3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D86TypeInfo_S3std3uni54__T10assumeSizeS31_D3std3uni8midlow_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D86TypeInfo_xS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D88TypeInfo_S3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data6__initZ@Base 6
+ _D890TypeInfo_S3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl6__initZ@Base 6
+ _D91TypeInfo_S3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__initZ@Base 6
+ _D92TypeInfo_S3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__initZ@Base 6
+ _D93TypeInfo_S3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D93TypeInfo_S3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6__initZ@Base 6
+ _D94TypeInfo_xS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D96TypeInfo_S3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__initZ@Base 6
+ _DT100_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT100_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT100_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT100_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT100_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT20_D3std11concurrency14FiberScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _DT20_D3std11concurrency14FiberScheduler5spawnMFNbDFZvZv@Base 6
+ _DT20_D3std11concurrency14FiberScheduler5startMFDFZvZv@Base 6
+ _DT20_D3std11concurrency14FiberScheduler5yieldMFNbZv@Base 6
+ _DT20_D3std11concurrency14FiberScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT24_D3std6stream11SliceStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream12EndianStream11readStringWMFkZAu@Base 6
+ _DT24_D3std6stream12EndianStream3eofMFNdZb@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJaZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJcZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJdZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJeZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJfZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJgZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJhZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJiZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJjZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJkZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJlZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJmZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJoZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJpZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJqZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJrZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJsZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJtZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJuZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJwZv@Base 6
+ _DT24_D3std6stream12EndianStream5getcwMFZu@Base 6
+ _DT24_D3std6stream12FilterStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream14BufferedStream3eofMFNdZb@Base 6
+ _DT24_D3std6stream14BufferedStream8readLineMFAaZAa@Base 6
+ _DT24_D3std6stream14BufferedStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream14BufferedStream9readLineWMFAuZAu@Base 6
+ _DT24_D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream4File9availableMFNdZk@Base 6
+ _DT24_D3std6stream6Stream10readStringMFkZAa@Base 6
+ _DT24_D3std6stream6Stream11readStringWMFkZAu@Base 6
+ _DT24_D3std6stream6Stream3eofMFNdZb@Base 6
+ _DT24_D3std6stream6Stream4getcMFZa@Base 6
+ _DT24_D3std6stream6Stream4readMFAhZk@Base 6
+ _DT24_D3std6stream6Stream4readMFJAaZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJAuZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJaZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJcZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJdZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJeZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJfZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJgZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJhZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJiZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJjZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJkZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJlZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJmZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJoZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJpZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJqZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJrZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJsZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJtZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJuZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJwZv@Base 6
+ _DT24_D3std6stream6Stream5getcwMFZu@Base 6
+ _DT24_D3std6stream6Stream5readfMFYi@Base 6
+ _DT24_D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _DT24_D3std6stream6Stream6ungetcMFaZa@Base 6
+ _DT24_D3std6stream6Stream6vreadfMFAC8TypeInfoPaZi@Base 6
+ _DT24_D3std6stream6Stream7opApplyMFMDFKAaZiZi@Base 6
+ _DT24_D3std6stream6Stream7opApplyMFMDFKAuZiZi@Base 6
+ _DT24_D3std6stream6Stream7opApplyMFMDFKmKAaZiZi@Base 6
+ _DT24_D3std6stream6Stream7opApplyMFMDFKmKAuZiZi@Base 6
+ _DT24_D3std6stream6Stream7ungetcwMFuZu@Base 6
+ _DT24_D3std6stream6Stream8readLineMFAaZAa@Base 6
+ _DT24_D3std6stream6Stream8readLineMFZAa@Base 6
+ _DT24_D3std6stream6Stream9availableMFNdZk@Base 6
+ _DT24_D3std6stream6Stream9readExactMFPvkZv@Base 6
+ _DT24_D3std6stream6Stream9readLineWMFAuZAu@Base 6
+ _DT24_D3std6stream6Stream9readLineWMFZAu@Base 6
+ _DT24_D3std7cstream5CFile3eofMFZb@Base 6
+ _DT24_D3std7cstream5CFile4getcMFZa@Base 6
+ _DT24_D3std7cstream5CFile6ungetcMFaZa@Base 6
+ _DT28_D3std12socketstream12SocketStream5closeMFZv@Base 6
+ _DT28_D3std6stream12EndianStream12writeStringWMFAxuZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFaZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFcZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFdZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFeZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFfZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFgZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFhZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFiZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFjZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFkZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFlZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFmZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFoZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFpZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFqZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFrZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFsZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFtZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFuZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFwZv@Base 6
+ _DT28_D3std6stream12FilterStream5closeMFZv@Base 6
+ _DT28_D3std6stream12FilterStream5flushMFZv@Base 6
+ _DT28_D3std6stream12MmFileStream5closeMFZv@Base 6
+ _DT28_D3std6stream12MmFileStream5flushMFZv@Base 6
+ _DT28_D3std6stream14BufferedStream5flushMFZv@Base 6
+ _DT28_D3std6stream4File5closeMFZv@Base 6
+ _DT28_D3std6stream6Stream10writeExactMFxPvkZv@Base 6
+ _DT28_D3std6stream6Stream10writeLineWMFAxuZv@Base 6
+ _DT28_D3std6stream6Stream11writeStringMFAxaZv@Base 6
+ _DT28_D3std6stream6Stream12writeStringWMFAxuZv@Base 6
+ _DT28_D3std6stream6Stream5closeMFZv@Base 6
+ _DT28_D3std6stream6Stream5flushMFZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFAxaZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFAxhZk@Base 6
+ _DT28_D3std6stream6Stream5writeMFAxuZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFaZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFcZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFdZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFeZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFfZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFgZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFhZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFiZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFjZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFkZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFlZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFmZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFoZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFpZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFqZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFrZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFsZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFtZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFuZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFwZv@Base 6
+ _DT28_D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _DT28_D3std6stream6Stream6printfMFAxaYk@Base 6
+ _DT28_D3std6stream6Stream6writefMFYC3std6stream12OutputStream@Base 6
+ _DT28_D3std6stream6Stream7vprintfMFAxaPaZk@Base 6
+ _DT28_D3std6stream6Stream7writefxMFAC8TypeInfoPaiZC3std6stream12OutputStream@Base 6
+ _DT28_D3std6stream6Stream8writeflnMFYC3std6stream12OutputStream@Base 6
+ _DT28_D3std6stream6Stream9writeLineMFAxaZv@Base 6
+ _DT28_D3std7cstream5CFile10writeLineWMFAxuZv@Base 6
+ _DT28_D3std7cstream5CFile5closeMFZv@Base 6
+ _DT28_D3std7cstream5CFile5flushMFZv@Base 6
+ _DT28_D3std7cstream5CFile9writeLineMFAxaZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler5spawnMFDFZvZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler5startMFDFZvZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler5yieldMFNbZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ __mod_ref__D3etc1c4curl12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc1c4zlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc1c7sqlite312__ModuleInfoZ@Base 6
+ __mod_ref__D3std10functional12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11concurrency12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11mathspecial12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11parallelism12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger10filelogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger10nulllogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger11multilogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger4core12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12socketstream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4fenv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4math12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4time12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux11linuxextern12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux4tipc12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux5linux12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux7pthread12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6locale12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stdarg12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stddef12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6string12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6wcharh12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c7process12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3csv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3net4curl12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3net7isemail12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3uni12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3uri12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3utf12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3xml12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3zip12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4conv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4file12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4json12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4math12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4meta12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4path12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4uuid12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4zlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5array12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5ascii12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range10interfaces12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range10primitives12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal12backtracking12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal2ir12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal5tests12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal6parser12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal8thompson12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal9generator12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal9kickstart12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6base6412__ModuleInfoZ@Base 6
+ __mod_ref__D3std6bigint12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest2md12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest3crc12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest3sha12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest6digest12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest6ripemd12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6format12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6getopt12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6mmfile12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6random12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6stdint12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6stream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6string12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6system12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6traits12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7complex12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7cstream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7numeric12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7process12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7signals12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7variant12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows7charset12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8iunknown12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8registry12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8syserror12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8bitmanip12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8compiler12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8datetime12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8demangle12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8encoding12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal11processinit12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal11scopebuffer12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal12unicode_comp12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal12unicode_norm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal14unicode_decomp12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal14unicode_tables12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal16unicode_grapheme12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math10biguintx8612__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math11biguintcore12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math12biguintnoasm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math13errorfunction12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math13gammafunction12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4test10dummyrange12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal6digest9sha_SSSE312__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal7cstring12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal7windows8advapi3212__ModuleInfoZ@Base 6
+ __mod_ref__D3std8syserror12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8typecons12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8typelist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm10comparison12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm6setops12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm7sorting12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm8internal12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm8mutation12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm9iteration12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm9searching12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container10binaryheap12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container4util12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5array12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5dlist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5slist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container6rbtree12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9outbuffer12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9stdiobase12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9typetuple12__ModuleInfoZ@Base 6
+ _arraySliceComSliceAssign_k@Base 6
+ deflateInit2@Base 6
+ deflateInit@Base 6
+ inflateBackInit@Base 6
+ inflateInit2@Base 6
+ inflateInit@Base 6
+ std_stdio_static_this@Base 6
--- gcc-6-6.3.0.orig/debian/libgphobos.symbols.64
+++ gcc-6-6.3.0/debian/libgphobos.symbols.64
@@ -0,0 +1,10427 @@
+ ZLIB_VERNUM@Base 6
+ ZLIB_VERSION@Base 6
+ Z_NULL@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__initZ@Base 6
+ _D101TypeInfo_S3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D102TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D103TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D106TypeInfo_S3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D106TypeInfo_S3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D109TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D113TypeInfo_S3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D114TypeInfo_PS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D115TypeInfo_S3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6__initZ@Base 6
+ _D115TypeInfo_S3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D116TypeInfo_PS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D116TypeInfo_xS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D119TypeInfo_S3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6__initZ@Base 6
+ _D11TypeInfo_Ob6__initZ@Base 6
+ _D11TypeInfo_Pa6__initZ@Base 6
+ _D11TypeInfo_Pb6__initZ@Base 6
+ _D11TypeInfo_Pd6__initZ@Base 6
+ _D11TypeInfo_Pe6__initZ@Base 6
+ _D11TypeInfo_Pf6__initZ@Base 6
+ _D11TypeInfo_Pg6__initZ@Base 6
+ _D11TypeInfo_Ph6__initZ@Base 6
+ _D11TypeInfo_Pi6__initZ@Base 6
+ _D11TypeInfo_Pk6__initZ@Base 6
+ _D11TypeInfo_Pl6__initZ@Base 6
+ _D11TypeInfo_Pm6__initZ@Base 6
+ _D11TypeInfo_Ps6__initZ@Base 6
+ _D11TypeInfo_Pt6__initZ@Base 6
+ _D11TypeInfo_Pv6__initZ@Base 6
+ _D11TypeInfo_xa6__initZ@Base 6
+ _D11TypeInfo_xb6__initZ@Base 6
+ _D11TypeInfo_xd6__initZ@Base 6
+ _D11TypeInfo_xe6__initZ@Base 6
+ _D11TypeInfo_xf6__initZ@Base 6
+ _D11TypeInfo_xh6__initZ@Base 6
+ _D11TypeInfo_xi6__initZ@Base 6
+ _D11TypeInfo_xk6__initZ@Base 6
+ _D11TypeInfo_xl6__initZ@Base 6
+ _D11TypeInfo_xm6__initZ@Base 6
+ _D11TypeInfo_xs6__initZ@Base 6
+ _D11TypeInfo_xt6__initZ@Base 6
+ _D11TypeInfo_xu6__initZ@Base 6
+ _D11TypeInfo_xv6__initZ@Base 6
+ _D11TypeInfo_xw6__initZ@Base 6
+ _D11TypeInfo_ya6__initZ@Base 6
+ _D11TypeInfo_yb6__initZ@Base 6
+ _D11TypeInfo_yd6__initZ@Base 6
+ _D11TypeInfo_ye6__initZ@Base 6
+ _D11TypeInfo_yf6__initZ@Base 6
+ _D11TypeInfo_yh6__initZ@Base 6
+ _D11TypeInfo_yi6__initZ@Base 6
+ _D11TypeInfo_yk6__initZ@Base 6
+ _D11TypeInfo_yl6__initZ@Base 6
+ _D11TypeInfo_ym6__initZ@Base 6
+ _D11TypeInfo_ys6__initZ@Base 6
+ _D11TypeInfo_yt6__initZ@Base 6
+ _D11TypeInfo_yu6__initZ@Base 6
+ _D11TypeInfo_yw6__initZ@Base 6
+ _D120TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_xS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D122TypeInfo_xS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D122TypeInfo_xS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D124TypeInfo_S3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D124TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D125TypeInfo_xS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D125TypeInfo_xS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D127TypeInfo_S3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__initZ@Base 6
+ _D12TypeInfo_AAf6__initZ@Base 6
+ _D12TypeInfo_Axf6__initZ@Base 6
+ _D12TypeInfo_Axh6__initZ@Base 6
+ _D12TypeInfo_Axk6__initZ@Base 6
+ _D12TypeInfo_Axm6__initZ@Base 6
+ _D12TypeInfo_Axu6__initZ@Base 6
+ _D12TypeInfo_Axv6__initZ@Base 6
+ _D12TypeInfo_Axw6__initZ@Base 6
+ _D12TypeInfo_Ayh6__initZ@Base 6
+ _D12TypeInfo_Ayk6__initZ@Base 6
+ _D12TypeInfo_Ayu6__initZ@Base 6
+ _D12TypeInfo_Ayw6__initZ@Base 6
+ _D12TypeInfo_FZv6__initZ@Base 6
+ _D12TypeInfo_G2m6__initZ@Base 6
+ _D12TypeInfo_G3m6__initZ@Base 6
+ _D12TypeInfo_G4a6__initZ@Base 6
+ _D12TypeInfo_G4m6__initZ@Base 6
+ _D12TypeInfo_Hlh6__initZ@Base 6
+ _D12TypeInfo_Hmm6__initZ@Base 6
+ _D12TypeInfo_Oxa6__initZ@Base 6
+ _D12TypeInfo_Oxd6__initZ@Base 6
+ _D12TypeInfo_Oxe6__initZ@Base 6
+ _D12TypeInfo_Oxf6__initZ@Base 6
+ _D12TypeInfo_Oxh6__initZ@Base 6
+ _D12TypeInfo_Oxi6__initZ@Base 6
+ _D12TypeInfo_Oxk6__initZ@Base 6
+ _D12TypeInfo_Oxl6__initZ@Base 6
+ _D12TypeInfo_Oxm6__initZ@Base 6
+ _D12TypeInfo_Oxs6__initZ@Base 6
+ _D12TypeInfo_Oxt6__initZ@Base 6
+ _D12TypeInfo_Oxu6__initZ@Base 6
+ _D12TypeInfo_Oxw6__initZ@Base 6
+ _D12TypeInfo_PAa6__initZ@Base 6
+ _D12TypeInfo_PAu6__initZ@Base 6
+ _D12TypeInfo_PAw6__initZ@Base 6
+ _D12TypeInfo_Pxa6__initZ@Base 6
+ _D12TypeInfo_Pxd6__initZ@Base 6
+ _D12TypeInfo_Pxk6__initZ@Base 6
+ _D12TypeInfo_Pxv6__initZ@Base 6
+ _D12TypeInfo_xAa6__initZ@Base 6
+ _D12TypeInfo_xAf6__initZ@Base 6
+ _D12TypeInfo_xAh6__initZ@Base 6
+ _D12TypeInfo_xAk6__initZ@Base 6
+ _D12TypeInfo_xAm6__initZ@Base 6
+ _D12TypeInfo_xAu6__initZ@Base 6
+ _D12TypeInfo_xAv6__initZ@Base 6
+ _D12TypeInfo_xAw6__initZ@Base 6
+ _D12TypeInfo_xPa6__initZ@Base 6
+ _D12TypeInfo_xPd6__initZ@Base 6
+ _D12TypeInfo_xPk6__initZ@Base 6
+ _D12TypeInfo_xPv6__initZ@Base 6
+ _D12TypeInfo_yAa6__initZ@Base 6
+ _D133TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D133TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D134TypeInfo_S3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D135TypeInfo_xS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6__initZ@Base 6
+ _D137TypeInfo_E3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11MatchResult6__initZ@Base 6
+ _D137TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D138TypeInfo_S3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D138TypeInfo_S3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D138TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D138TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D13TypeInfo_AAya6__initZ@Base 6
+ _D13TypeInfo_APxa6__initZ@Base 6
+ _D13TypeInfo_DFZv6__initZ@Base 6
+ _D13TypeInfo_G32h6__initZ@Base 6
+ _D13TypeInfo_Hmxm6__initZ@Base 6
+ _D13TypeInfo_PAyh6__initZ@Base 6
+ _D13TypeInfo_xAya6__initZ@Base 6
+ _D13TypeInfo_xAyh6__initZ@Base 6
+ _D13TypeInfo_xAyk6__initZ@Base 6
+ _D13TypeInfo_xG2m6__initZ@Base 6
+ _D13TypeInfo_xG3m6__initZ@Base 6
+ _D13TypeInfo_xG4a6__initZ@Base 6
+ _D13TypeInfo_xG4m6__initZ@Base 6
+ _D13TypeInfo_xHmm6__initZ@Base 6
+ _D141TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D142TypeInfo_S3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D142TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D143TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D143TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D145TypeInfo_S3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6__initZ@Base 6
+ _D146TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D146TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D146TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D149TypeInfo_E3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11MatchResult6__initZ@Base 6
+ _D14TypeInfo_AxAya6__initZ@Base 6
+ _D14TypeInfo_FPvZv6__initZ@Base 6
+ _D14TypeInfo_PG32h6__initZ@Base 6
+ _D14TypeInfo_UPvZv6__initZ@Base 6
+ _D14TypeInfo_xAAya6__initZ@Base 6
+ _D14TypeInfo_xDFZv6__initZ@Base 6
+ _D152TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D153TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D154TypeInfo_S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D154TypeInfo_S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D156TypeInfo_S3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine6__initZ@Base 6
+ _D15TypeInfo_PFPvZv6__initZ@Base 6
+ _D15TypeInfo_PUPvZv6__initZ@Base 6
+ _D160TypeInfo_S3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack6__initZ@Base 6
+ _D161TypeInfo_S3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D161TypeInfo_S3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D162TypeInfo_S3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D162TypeInfo_S3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D162TypeInfo_xS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D162TypeInfo_xS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D163TypeInfo_S3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult6__initZ@Base 6
+ _D165TypeInfo_S3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value6__initZ@Base 6
+ _D167TypeInfo_S3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D168TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__initZ@Base 6
+ _D168TypeInfo_S3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__initZ@Base 6
+ _D169TypeInfo_S3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D16TypeInfo_HAyaAya6__initZ@Base 6
+ _D16TypeInfo_xPFPvZv6__initZ@Base 6
+ _D16TypeInfo_xPUPvZv6__initZ@Base 6
+ _D170TypeInfo_S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D170TypeInfo_S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_G2S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_G2S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_S3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__initZ@Base 6
+ _D173TypeInfo_S3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D173TypeInfo_xG2S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D173TypeInfo_xG2S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D174TypeInfo_FNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D174TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D174TypeInfo_xS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D175TypeInfo_PFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_xPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D178TypeInfo_S3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D179TypeInfo_xS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D17TypeInfo_HAyaxAya6__initZ@Base 6
+ _D17TypeInfo_xHAyaAya6__initZ@Base 6
+ _D180TypeInfo_AxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D180TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__initZ@Base 6
+ _D180TypeInfo_xAS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D182TypeInfo_S3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D183TypeInfo_xS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D186TypeInfo_FNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D186TypeInfo_S3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D186TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D187TypeInfo_PFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D187TypeInfo_xS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D188TypeInfo_xPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D18TypeInfo_xC6Object6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D215TypeInfo_S3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_S3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D21TypeInfo_xC9Exception6__initZ@Base 6
+ _D220TypeInfo_xS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D235TypeInfo_S3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D237TypeInfo_S3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__initZ@Base 6
+ _D23TypeInfo_E3std3uni4Mode6__initZ@Base 6
+ _D240TypeInfo_S3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__initZ@Base 6
+ _D242TypeInfo_S3std9algorithm7sorting201__T11TimSortImplS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ5Slice6__initZ@Base 6
+ _D243TypeInfo_HS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D246TypeInfo_S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D24TypeInfo_AC3std3xml4Item6__initZ@Base 6
+ _D24TypeInfo_AC3std3xml4Text6__initZ@Base 6
+ _D24TypeInfo_E3std6system2OS6__initZ@Base 6
+ _D24TypeInfo_S3std4uuid4UUID6__initZ@Base 6
+ _D25TypeInfo_AC3std3xml5CData6__initZ@Base 6
+ _D25TypeInfo_E3std6stream3BOM6__initZ@Base 6
+ _D25TypeInfo_S3etc1c4curl3_N26__initZ@Base 6
+ _D25TypeInfo_S3std5stdio4File6__initZ@Base 6
+ _D262TypeInfo_S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D264TypeInfo_G4S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D265TypeInfo_xG4S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D267TypeInfo_S3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult6__initZ@Base 6
+ _D26TypeInfo_E3std3xml7TagType6__initZ@Base 6
+ _D26TypeInfo_HAyaC3std3xml3Tag6__initZ@Base 6
+ _D26TypeInfo_S3etc1c4curl4_N286__initZ@Base 6
+ _D26TypeInfo_S3etc1c4curl4_N316__initZ@Base 6
+ _D26TypeInfo_S3std3uni7unicode6__initZ@Base 6
+ _D26TypeInfo_S3std5stdio5lines6__initZ@Base 6
+ _D26TypeInfo_S3std8typecons2No6__initZ@Base 6
+ _D26TypeInfo_xS3std5stdio4File6__initZ@Base 6
+ _D270TypeInfo_S3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D27TypeInfo_AC3std3xml7Comment6__initZ@Base 6
+ _D27TypeInfo_AC3std3xml7Element6__initZ@Base 6
+ _D27TypeInfo_E3etc1c4curl5CurlM6__initZ@Base 6
+ _D27TypeInfo_S3std3net4curl3FTP6__initZ@Base 6
+ _D27TypeInfo_S3std3uni8GcPolicy6__initZ@Base 6
+ _D27TypeInfo_S3std3uni8Grapheme6__initZ@Base 6
+ _D27TypeInfo_S3std7process4Pipe6__initZ@Base 6
+ _D27TypeInfo_S3std8typecons3Yes6__initZ@Base 6
+ _D27TypeInfo_xC3std7process3Pid6__initZ@Base 6
+ _D28TypeInfo_E3std3csv9Malformed6__initZ@Base 6
+ _D28TypeInfo_E3std4file8SpanMode6__initZ@Base 6
+ _D28TypeInfo_E3std6format6Mangle6__initZ@Base 6
+ _D28TypeInfo_E3std6getopt6config6__initZ@Base 6
+ _D28TypeInfo_E3std6system6Endian6__initZ@Base 6
+ _D28TypeInfo_OC6object9Throwable6__initZ@Base 6
+ _D28TypeInfo_PC6object9Throwable6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4Curl6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4HTTP6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4SMTP6__initZ@Base 6
+ _D28TypeInfo_S3std4file8DirEntry6__initZ@Base 6
+ _D28TypeInfo_S3std6bigint6BigInt6__initZ@Base 6
+ _D28TypeInfo_S3std6digest2md3MD56__initZ@Base 6
+ _D28TypeInfo_S3std6getopt6Option6__initZ@Base 6
+ _D28TypeInfo_S3std6socket6Linger6__initZ@Base 6
+ _D28TypeInfo_S3std8datetime4Date6__initZ@Base 6
+ _D28TypeInfo_xC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_AC4core6thread5Fiber6__initZ@Base 6
+ _D29TypeInfo_AS3std4file8DirEntry6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlFtp6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlMsg6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlVer6__initZ@Base 6
+ _D29TypeInfo_E3std4json9JSON_TYPE6__initZ@Base 6
+ _D29TypeInfo_E3std5stdio8LockType6__initZ@Base 6
+ _D29TypeInfo_E3std6stream7SeekPos6__initZ@Base 6
+ _D29TypeInfo_E3std7process6Config6__initZ@Base 6
+ _D29TypeInfo_E3std8datetime5Month6__initZ@Base 6
+ _D29TypeInfo_POC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_S3etc1c4curl7CURLMsg6__initZ@Base 6
+ _D29TypeInfo_S3std4json9JSONValue6__initZ@Base 6
+ _D29TypeInfo_S3std4math9IeeeFlags6__initZ@Base 6
+ _D29TypeInfo_S3std5range8NullSink6__initZ@Base 6
+ _D29TypeInfo_S3std6socket7TimeVal6__initZ@Base 6
+ _D29TypeInfo_xE3std4file8SpanMode6__initZ@Base 6
+ _D29TypeInfo_xS3std3net4curl4Curl6__initZ@Base 6
+ _D29TypeInfo_xS3std4file8DirEntry6__initZ@Base 6
+ _D29TypeInfo_xS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_AC3std6socket7Address6__initZ@Base 6
+ _D30TypeInfo_AxS3std4file8DirEntry6__initZ@Base 6
+ _D30TypeInfo_AxS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlAuth6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlForm6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlInfo6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlPoll6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlSeek6__initZ@Base 6
+ _D30TypeInfo_E3std3xml10DecodeMode6__initZ@Base 6
+ _D30TypeInfo_E3std6socket8socket_t6__initZ@Base 6
+ _D30TypeInfo_E3std6stream8FileMode6__initZ@Base 6
+ _D30TypeInfo_E3std6traits8Variadic6__initZ@Base 6
+ _D30TypeInfo_E3std8compiler6Vendor6__initZ@Base 6
+ _D30TypeInfo_S3etc1c4zlib8z_stream6__initZ@Base 6
+ _D30TypeInfo_S3std5stdio4File4Impl6__initZ@Base 6
+ _D30TypeInfo_xAS3std4file8DirEntry6__initZ@Base 6
+ _D30TypeInfo_xAS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_xC3std6socket7Address6__initZ@Base 6
+ _D30TypeInfo_xS3std4json9JSONValue6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlError6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlIoCmd6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlPause6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlProto6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlProxy6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlRedir6__initZ@Base 6
+ _D31TypeInfo_E3std4math10RealFormat6__initZ@Base 6
+ _D31TypeInfo_E3std7process8Redirect6__initZ@Base 6
+ _D31TypeInfo_S3etc1c4zlib9gz_header6__initZ@Base 6
+ _D31TypeInfo_S3std11concurrency3Tid6__initZ@Base 6
+ _D31TypeInfo_S3std3net4curl7CurlAPI6__initZ@Base 6
+ _D31TypeInfo_S3std6digest3crc5CRC326__initZ@Base 6
+ _D31TypeInfo_S3std8datetime7SysTime6__initZ@Base 6
+ _D31TypeInfo_xS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_AS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_E3std4json11JSONOptions6__initZ@Base 6
+ _D32TypeInfo_E3std4uuid4UUID7Variant6__initZ@Base 6
+ _D32TypeInfo_E3std4uuid4UUID7Version6__initZ@Base 6
+ _D32TypeInfo_E3std5ascii10LetterCase6__initZ@Base 6
+ _D32TypeInfo_E3std8datetime8PopFirst6__initZ@Base 6
+ _D32TypeInfo_PS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_PxS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_S3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D32TypeInfo_S3std3net7isemail5Token6__initZ@Base 6
+ _D32TypeInfo_S3std3uni7unicode5block6__initZ@Base 6
+ _D32TypeInfo_S3std4file11DirIterator6__initZ@Base 6
+ _D32TypeInfo_S3std5stdio10ChunksImpl6__initZ@Base 6
+ _D32TypeInfo_S3std8bitmanip8BitArray6__initZ@Base 6
+ _D32TypeInfo_S3std8bitmanip8FloatRep6__initZ@Base 6
+ _D32TypeInfo_S3std8datetime8DateTime6__initZ@Base 6
+ _D32TypeInfo_xE3std7process8Redirect6__initZ@Base 6
+ _D32TypeInfo_xPS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_xS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_xS3std8datetime7SysTime6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlFtpSSL6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlGlobal6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlKHStat6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlKHType6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlOption6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlUseSSL6__initZ@Base 6
+ _D33TypeInfo_E3std4zlib12HeaderFormat6__initZ@Base 6
+ _D33TypeInfo_E3std6mmfile6MmFile4Mode6__initZ@Base 6
+ _D33TypeInfo_E3std6socket10SocketType6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9AutoStart6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9DayOfWeek6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9Direction6__initZ@Base 6
+ _D33TypeInfo_E3std8encoding9AsciiChar6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_forms6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_khkey6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_slist6__initZ@Base 6
+ _D33TypeInfo_S3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D33TypeInfo_S3std3net4curl4SMTP4Impl6__initZ@Base 6
+ _D33TypeInfo_S3std3uni13ReallocPolicy6__initZ@Base 6
+ _D33TypeInfo_S3std3uni7unicode6script6__initZ@Base 6
+ _D33TypeInfo_S3std5stdio4File7ByChunk6__initZ@Base 6
+ _D33TypeInfo_S3std8bitmanip9DoubleRep6__initZ@Base 6
+ _D33TypeInfo_S3std8datetime9StopWatch6__initZ@Base 6
+ _D33TypeInfo_S3std8datetime9TimeOfDay6__initZ@Base 6
+ _D33TypeInfo_xC3std8datetime8TimeZone6__initZ@Base 6
+ _D33TypeInfo_xS3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D33TypeInfo_xS3std4file11DirIterator6__initZ@Base 6
+ _D33TypeInfo_yC3std8datetime8TimeZone6__initZ@Base 6
+ _D34TypeInfo_AE3std8encoding9AsciiChar6__initZ@Base 6
+ _D34TypeInfo_C3std6stream11InputStream6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlCSelect6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlFormAdd6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlFtpAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlIoError6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlKHMatch6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlMOption6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlRtspReq6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlSeekPos6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlShError6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlSshAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlTlsAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlVersion6__initZ@Base 6
+ _D34TypeInfo_E3std4path13CaseSensitive6__initZ@Base 6
+ _D34TypeInfo_E3std5range12SearchPolicy6__initZ@Base 6
+ _D34TypeInfo_E3std6digest6digest5Order6__initZ@Base 6
+ _D34TypeInfo_E3std6socket11SocketFlags6__initZ@Base 6
+ _D34TypeInfo_HAyaxS3std4json9JSONValue6__initZ@Base 6
+ _D34TypeInfo_HS3std11concurrency3Tidxb6__initZ@Base 6
+ _D34TypeInfo_S3std3uni14MatcherConcept6__initZ@Base 6
+ _D34TypeInfo_S3std6socket11AddressInfo6__initZ@Base 6
+ _D34TypeInfo_xE3std6socket10SocketType6__initZ@Base 6
+ _D34TypeInfo_xHAyaS3std4json9JSONValue6__initZ@Base 6
+ _D34TypeInfo_xHS3std11concurrency3Tidb6__initZ@Base 6
+ _D34TypeInfo_xS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D34TypeInfo_xS3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D35TypeInfo_AS3std6socket11AddressInfo6__initZ@Base 6
+ _D35TypeInfo_C3std6digest6digest6Digest6__initZ@Base 6
+ _D35TypeInfo_C3std6stream12OutputStream6__initZ@Base 6
+ _D35TypeInfo_C3std8typecons10Structural6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlFileType6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlLockData6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlReadFunc6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlShOption6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlSockType6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlTimeCond6__initZ@Base 6
+ _D35TypeInfo_E3std11concurrency7MsgType6__initZ@Base 6
+ _D35TypeInfo_E3std3net4curl4HTTP6Method6__initZ@Base 6
+ _D35TypeInfo_E3std3net7isemail8CheckDns6__initZ@Base 6
+ _D35TypeInfo_E3std5regex8internal2ir2IR6__initZ@Base 6
+ _D35TypeInfo_E3std6socket12ProtocolType6__initZ@Base 6
+ _D35TypeInfo_E3std6socket12SocketOption6__initZ@Base 6
+ _D35TypeInfo_E3std8encoding10Latin1Char6__initZ@Base 6
+ _D35TypeInfo_HAyaS3std11concurrency3Tid6__initZ@Base 6
+ _D35TypeInfo_PxS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D35TypeInfo_S3std11concurrency7Message6__initZ@Base 6
+ _D35TypeInfo_S3std3net4curl7CurlAPI3API6__initZ@Base 6
+ _D35TypeInfo_S3std4json9JSONValue5Store6__initZ@Base 6
+ _D35TypeInfo_S3std6getopt12GetoptResult6__initZ@Base 6
+ _D35TypeInfo_xPS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D35TypeInfo_xS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_AE3std8encoding10Latin1Char6__initZ@Base 6
+ _D36TypeInfo_AxS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_E3etc1c4curl13CurlFtpMethod6__initZ@Base 6
+ _D36TypeInfo_E3etc1c4curl13CurlIpResolve6__initZ@Base 6
+ _D36TypeInfo_E3std3net7isemail9EmailPart6__initZ@Base 6
+ _D36TypeInfo_E3std5range14StoppingPolicy6__initZ@Base 6
+ _D36TypeInfo_E3std6socket13AddressFamily6__initZ@Base 6
+ _D36TypeInfo_FC3std3xml13ElementParserZv6__initZ@Base 6
+ _D36TypeInfo_HS3std11concurrency3TidAAya6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_certinfo6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_fileinfo6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_httppost6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_sockaddr6__initZ@Base 6
+ _D36TypeInfo_S3std4file15DirIteratorImpl6__initZ@Base 6
+ _D36TypeInfo_S3std6getopt13configuration6__initZ@Base 6
+ _D36TypeInfo_S3std7process12ProcessPipes6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D36TypeInfo_xAS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_xE3std11concurrency7MsgType6__initZ@Base 6
+ _D36TypeInfo_xE3std3net4curl4HTTP6Method6__initZ@Base 6
+ _D36TypeInfo_xE3std6socket12ProtocolType6__initZ@Base 6
+ _D36TypeInfo_xS3std11concurrency7Message6__initZ@Base 6
+ _D37TypeInfo_C3std11concurrency9Scheduler6__initZ@Base 6
+ _D37TypeInfo_DFC3std3xml13ElementParserZv6__initZ@Base 6
+ _D37TypeInfo_E3etc1c4curl14CurlLockAccess6__initZ@Base 6
+ _D37TypeInfo_E3etc1c4curl14CurlSslVersion6__initZ@Base 6
+ _D37TypeInfo_E3std3uni17NormalizationForm6__initZ@Base 6
+ _D37TypeInfo_E3std3zip17CompressionMethod6__initZ@Base 6
+ _D37TypeInfo_E3std4json16JSONFloatLiteral6__initZ@Base 6
+ _D37TypeInfo_E3std6socket14SocketShutdown6__initZ@Base 6
+ _D37TypeInfo_E3std8typecons12TypeModifier6__initZ@Base 6
+ _D37TypeInfo_HAyaC3std3zip13ArchiveMember6__initZ@Base 6
+ _D37TypeInfo_S3etc1c7sqlite311sqlite3_vfs6__initZ@Base 6
+ _D37TypeInfo_S3std3net4curl12AutoProtocol6__initZ@Base 6
+ _D37TypeInfo_S3std3uni17CodepointInterval6__initZ@Base 6
+ _D37TypeInfo_S3std7numeric5bsr64FmZ5Ulong6__initZ@Base 6
+ _D37TypeInfo_S3std9container5dlist6DRange6__initZ@Base 6
+ _D37TypeInfo_xC3std11parallelism8TaskPool6__initZ@Base 6
+ _D37TypeInfo_xE3std6socket13AddressFamily6__initZ@Base 6
+ _D37TypeInfo_xS3std4file15DirIteratorImpl6__initZ@Base 6
+ _D37TypeInfo_xS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_AS3std3uni17CodepointInterval6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlClosePolicy6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlFnMAtchFunc6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlHttpVersion6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlNetRcOption6__initZ@Base 6
+ _D38TypeInfo_E3std3net7isemail10AsciiToken6__initZ@Base 6
+ _D38TypeInfo_E3std5stdio4File11Orientation6__initZ@Base 6
+ _D38TypeInfo_PxS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_S3etc1c7sqlite312sqlite3_file6__initZ@Base 6
+ _D38TypeInfo_S3etc1c7sqlite312sqlite3_vtab6__initZ@Base 6
+ _D38TypeInfo_S3std6digest6ripemd9RIPEMD1606__initZ@Base 6
+ _D38TypeInfo_xPS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_xS3std3uni17CodepointInterval6__initZ@Base 6
+ _D399TypeInfo_S3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlCallbackInfo6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlChunkBgnFunc6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlChunkEndFunc6__initZ@Base 6
+ _D39TypeInfo_E3std11concurrency10OnCrowding6__initZ@Base 6
+ _D39TypeInfo_E3std11parallelism10TaskStatus6__initZ@Base 6
+ _D39TypeInfo_E3std5range17TransverseOptions6__initZ@Base 6
+ _D39TypeInfo_E3std6socket16AddressInfoFlags6__initZ@Base 6
+ _D39TypeInfo_HE3std6format6MangleC8TypeInfo6__initZ@Base 6
+ _D39TypeInfo_S3std11concurrency10ThreadInfo6__initZ@Base 6
+ _D39TypeInfo_S3std3net7isemail11EmailStatus6__initZ@Base 6
+ _D39TypeInfo_S3std5stdio17LockingTextReader6__initZ@Base 6
+ _D39TypeInfo_S3std9container5dlist8BaseNode6__initZ@Base 6
+ _D3etc1c4curl10CurlGlobal6__initZ@Base 6
+ _D3etc1c4curl10CurlOption6__initZ@Base 6
+ _D3etc1c4curl10curl_forms6__initZ@Base 6
+ _D3etc1c4curl10curl_khkey6__initZ@Base 6
+ _D3etc1c4curl10curl_slist6__initZ@Base 6
+ _D3etc1c4curl11CurlCSelect6__initZ@Base 6
+ _D3etc1c4curl11CurlMOption6__initZ@Base 6
+ _D3etc1c4curl11CurlSshAuth6__initZ@Base 6
+ _D3etc1c4curl11CurlVersion6__initZ@Base 6
+ _D3etc1c4curl12CurlReadFunc6__initZ@Base 6
+ _D3etc1c4curl12__ModuleInfoZ@Base 6
+ _D3etc1c4curl13curl_certinfo6__initZ@Base 6
+ _D3etc1c4curl13curl_fileinfo6__initZ@Base 6
+ _D3etc1c4curl13curl_httppost6__initZ@Base 6
+ _D3etc1c4curl13curl_sockaddr6__initZ@Base 6
+ _D3etc1c4curl18CurlFInfoFlagKnown6__initZ@Base 6
+ _D3etc1c4curl3_N26__initZ@Base 6
+ _D3etc1c4curl4_N286__initZ@Base 6
+ _D3etc1c4curl4_N316__initZ@Base 6
+ _D3etc1c4curl5CurlM6__initZ@Base 6
+ _D3etc1c4curl7CURLMsg6__initZ@Base 6
+ _D3etc1c4curl9CurlPause6__initZ@Base 6
+ _D3etc1c4curl9CurlProto6__initZ@Base 6
+ _D3etc1c4zlib12__ModuleInfoZ@Base 6
+ _D3etc1c4zlib8z_stream6__initZ@Base 6
+ _D3etc1c4zlib9gz_header6__initZ@Base 6
+ _D3etc1c7sqlite311sqlite3_vfs6__initZ@Base 6
+ _D3etc1c7sqlite312__ModuleInfoZ@Base 6
+ _D3etc1c7sqlite312sqlite3_file6__initZ@Base 6
+ _D3etc1c7sqlite312sqlite3_vtab6__initZ@Base 6
+ _D3etc1c7sqlite314sqlite3_module6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info11__xopEqualsFKxS3etc1c7sqlite318sqlite3_index_infoKxS3etc1c7sqlite318sqlite3_index_infoZb@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info9__xtoHashFNbNeKxS3etc1c7sqlite318sqlite3_index_infoZm@Base 6
+ _D3etc1c7sqlite318sqlite3_io_methods6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_mem_methods6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_pcache_page6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_vtab_cursor6__initZ@Base 6
+ _D3etc1c7sqlite321sqlite3_mutex_methods6__initZ@Base 6
+ _D3etc1c7sqlite322sqlite3_pcache_methods6__initZ@Base 6
+ _D3etc1c7sqlite322sqlite3_rtree_geometry6__initZ@Base 6
+ _D3etc1c7sqlite323sqlite3_pcache_methods26__initZ@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info11__xopEqualsFKxS3etc1c7sqlite324sqlite3_rtree_query_infoKxS3etc1c7sqlite324sqlite3_rtree_query_infoZb@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info6__initZ@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info9__xtoHashFNbNeKxS3etc1c7sqlite324sqlite3_rtree_query_infoZm@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ11initializedAm@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ4memoAS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value11__xopEqualsFKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZb@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value6__initZ@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value9__xtoHashFNbNeKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZm@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std10functional11_ctfeSkipOpFKAyaZk@Base 6
+ _D3std10functional12__ModuleInfoZ@Base 6
+ _D3std10functional13_ctfeSkipNameFKAyaAyaZk@Base 6
+ _D3std10functional15_ctfeMatchUnaryFAyaAyaZk@Base 6
+ _D3std10functional16_ctfeMatchBinaryFAyaAyaAyaZk@Base 6
+ _D3std10functional16_ctfeSkipIntegerFKAyaZk@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTiTiZ6safeOpFNaNbNiNfKiKiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTkTkZ6safeOpFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTlTmZ6safeOpFNaNbNiNfKlKmZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTmTiZ6safeOpFNaNbNiNfKmKiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTmTmZ6safeOpFNaNbNiNfKmKmZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTmTymZ6safeOpFNaNbNiNfKmKymZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTyiTmZ6safeOpFNaNbNiNfKyiKmZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTymTmZ6safeOpFNaNbNiNfKymKmZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T6safeOpTymTymZ6safeOpFNaNbNiNfKymKymZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T8unsafeOpTlTmZ8unsafeOpFNaNbNiNflmZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T8unsafeOpTmTiZ8unsafeOpFNaNbNiNfmiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ18__T8unsafeOpTyiTmZ8unsafeOpFNaNbNiNfyimZb@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfS3std3uni17CodepointIntervalZk@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfS3std3uni17CodepointIntervalZk@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_74727565VAyaa1_61Z15__T8unaryFunTwZ8unaryFunFNaNbNiNfKwZb@Base 6
+ _D3std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z55__T8unaryFunTyS3std8internal14unicode_tables9CompEntryZ8unaryFunFNaNbNiNfKyS3std8internal14unicode_tables9CompEntryZyw@Base 6
+ _D3std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z62__T8unaryFunTyS3std8internal14unicode_tables15UnicodePropertyZ8unaryFunFNaNbNiNfKyS3std8internal14unicode_tables15UnicodePropertyZyAa@Base 6
+ _D3std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z19__T9binaryFunTxkTkZ9binaryFunFNaNbNiNfKxkKkZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61202b2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZk@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTiZ9binaryFunFNaNbNiNfKkKiZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTwZ9binaryFunFNaNbNiNfKwKwZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTywTwZ9binaryFunFNaNbNiNfKywKwZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z20__T9binaryFunTxhTxhZ9binaryFunFNaNbNiNfKxhKxhZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTAyaTAyaZ9binaryFunFNaNbNiNfKAyaKAyaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203c3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTkTyiZ9binaryFunFNaNbNiNfKkKyiZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z144__T9binaryFunTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ9binaryFunFNaNbNiNfKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunThThZ9binaryFunFNaNbNiNfKhKhZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTaZ9binaryFunFNaNbNiNfKwKaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTaZ9binaryFunFNaNbNiNfwKaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTwZ9binaryFunFNaNbNiNfwwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTyhTwZ9binaryFunFNaNbNiNfKyhKwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTyhTwZ9binaryFunFNaNbNiNfKyhwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTAyaTAyaZ9binaryFunFNaNbNiNfKAyaKAyaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTyAaTAyaZ9binaryFunFNaNbNiNfKyAaKAyaZb@Base 6
+ _D3std10functional52__T8unaryFunVAyaa11_6120213d20612e4f70656eVAyaa1_61Z74__T8unaryFunTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ8unaryFunFNaNbNiNfKE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std10functional52__T8unaryFunVAyaa11_615b305d203e2030783830VAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfKS3std3uni17CodepointIntervalZb@Base 6
+ _D3std10functional54__T8unaryFunVAyaa12_61203d3d20612e556e696f6eVAyaa1_61Z74__T8unaryFunTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ8unaryFunFNaNbNiNfKE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z59__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTlZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKlZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10LeapSecondTylZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10LeapSecondKylZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTylZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKylZb@Base 6
+ _D3std10functional70__T9binaryFunVAyaa15_612e6e616d65203c20622e6e616d65VAyaa1_61VAyaa1_62Z86__T9binaryFunTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ9binaryFunFNaNbNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z106__T9binaryFunTS3std8datetime13PosixTimeZone14TempTransitionTS3std8datetime13PosixTimeZone14TempTransitionZ9binaryFunFNaNbNiNfKS3std8datetime13PosixTimeZone14TempTransitionKS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z98__T9binaryFunTS3std8datetime13PosixTimeZone10LeapSecondTS3std8datetime13PosixTimeZone10LeapSecondZ9binaryFunFNaNbNiNfKS3std8datetime13PosixTimeZone10LeapSecondKS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std11concurrency10MessageBox10setMaxMsgsMFmPFS3std11concurrency3TidZbZv@Base 6
+ _D3std11concurrency10MessageBox12isControlMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox13isLinkDeadMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox13isPriorityMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox14updateMsgCountMFZv@Base 6
+ _D3std11concurrency10MessageBox160__T3getTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3getMFMDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbMDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency10MessageBox181__T3getTS4core4time8DurationTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3getMFMS4core4time8DurationMDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbMDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency10MessageBox36__T3getTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ3getMFMDFNaNbNiAyhZvMDFNaNbNiNfbZvZb@Base 6
+ _D3std11concurrency10MessageBox3putMFKS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency10MessageBox5closeMFZ13onLinkDeadMsgMFKS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency10MessageBox5closeMFZv@Base 6
+ _D3std11concurrency10MessageBox6__ctorMFNeZC3std11concurrency10MessageBox@Base 6
+ _D3std11concurrency10MessageBox6__initZ@Base 6
+ _D3std11concurrency10MessageBox6__vtblZ@Base 6
+ _D3std11concurrency10MessageBox7__ClassZ@Base 6
+ _D3std11concurrency10MessageBox8isClosedMFNdZb@Base 6
+ _D3std11concurrency10MessageBox8isClosedMxFNdZb@Base 6
+ _D3std11concurrency10MessageBox8mboxFullMFZb@Base 6
+ _D3std11concurrency10ThreadInfo11__xopEqualsFKxS3std11concurrency10ThreadInfoKxS3std11concurrency10ThreadInfoZb@Base 6
+ _D3std11concurrency10ThreadInfo6__initZ@Base 6
+ _D3std11concurrency10ThreadInfo7cleanupMFZv@Base 6
+ _D3std11concurrency10ThreadInfo8thisInfoFNbNcNdNiNfZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency10ThreadInfo8thisInfoFNbNcNdZ3valS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency10ThreadInfo9__xtoHashFNbNeKxS3std11concurrency10ThreadInfoZm@Base 6
+ _D3std11concurrency10namesByTidHS3std11concurrency3TidAAya@Base 6
+ _D3std11concurrency10unregisterFAyaZb@Base 6
+ _D3std11concurrency11IsGenerator11__InterfaceZ@Base 6
+ _D3std11concurrency11MailboxFull6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency11MailboxFull@Base 6
+ _D3std11concurrency11MailboxFull6__initZ@Base 6
+ _D3std11concurrency11MailboxFull6__vtblZ@Base 6
+ _D3std11concurrency11MailboxFull7__ClassZ@Base 6
+ _D3std11concurrency12__ModuleInfoZ@Base 6
+ _D3std11concurrency12_staticDtor1FZv@Base 6
+ _D3std11concurrency12initOnceLockFNdZ4lockC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12initOnceLockFNdZC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12registryLockC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12unregisterMeFZv@Base 6
+ _D3std11concurrency13__T4sendTAyhZ4sendFS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency14FiberScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition13switchContextMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition4waitMFNbS4core4time8DurationZb@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition4waitMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__ctorMFNbC4core4sync5mutex5MutexZC3std11concurrency14FiberScheduler14FiberCondition@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6notifyMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition7__ClassZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition9notifyAllMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler5spawnMFNbDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler5startMFDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler5yieldMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler6createMFNbDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler7__ClassZ@Base 6
+ _D3std11concurrency14FiberScheduler8dispatchMFZv@Base 6
+ _D3std11concurrency14FiberScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__ctorMFNbDFZvZC3std11concurrency14FiberScheduler9InfoFiber@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber7__ClassZ@Base 6
+ _D3std11concurrency14LinkTerminated6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency14LinkTerminated@Base 6
+ _D3std11concurrency14LinkTerminated6__initZ@Base 6
+ _D3std11concurrency14LinkTerminated6__vtblZ@Base 6
+ _D3std11concurrency14LinkTerminated7__ClassZ@Base 6
+ _D3std11concurrency14__T5_sendTAyhZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency14__T5_sendTAyhZ5_sendFS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency15MessageMismatch6__ctorMFAyaZC3std11concurrency15MessageMismatch@Base 6
+ _D3std11concurrency15MessageMismatch6__initZ@Base 6
+ _D3std11concurrency15MessageMismatch6__vtblZ@Base 6
+ _D3std11concurrency15MessageMismatch7__ClassZ@Base 6
+ _D3std11concurrency15OwnerTerminated6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency15OwnerTerminated@Base 6
+ _D3std11concurrency15OwnerTerminated6__initZ@Base 6
+ _D3std11concurrency15OwnerTerminated6__vtblZ@Base 6
+ _D3std11concurrency15OwnerTerminated7__ClassZ@Base 6
+ _D3std11concurrency15ThreadScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D3std11concurrency15ThreadScheduler5spawnMFDFZvZv@Base 6
+ _D3std11concurrency15ThreadScheduler5startMFDFZvZv@Base 6
+ _D3std11concurrency15ThreadScheduler5yieldMFNbZv@Base 6
+ _D3std11concurrency15ThreadScheduler6__initZ@Base 6
+ _D3std11concurrency15ThreadScheduler6__vtblZ@Base 6
+ _D3std11concurrency15ThreadScheduler7__ClassZ@Base 6
+ _D3std11concurrency15ThreadScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency15onCrowdingBlockFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency15onCrowdingThrowFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency164__T7receiveTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ7receiveFDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZv@Base 6
+ _D3std11concurrency165__T8checkopsTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ8checkopsFNaNbNiNfDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZv@Base 6
+ _D3std11concurrency16onCrowdingIgnoreFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency172__T14receiveTimeoutTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ14receiveTimeoutFS4core4time8DurationDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency17setMaxMailboxSizeFS3std11concurrency3TidmE3std11concurrency10OnCrowdingZv@Base 6
+ _D3std11concurrency17setMaxMailboxSizeFS3std11concurrency3TidmPFS3std11concurrency3TidZbZv@Base 6
+ _D3std11concurrency18_sharedStaticCtor8FZv@Base 6
+ _D3std11concurrency19TidMissingException6__ctorMFAyaAyamZC3std11concurrency19TidMissingException@Base 6
+ _D3std11concurrency19TidMissingException6__initZ@Base 6
+ _D3std11concurrency19TidMissingException6__vtblZ@Base 6
+ _D3std11concurrency19TidMissingException7__ClassZ@Base 6
+ _D3std11concurrency24PriorityMessageException11__fieldDtorMFZv@Base 6
+ _D3std11concurrency24PriorityMessageException6__ctorMFS3std7variant18__T8VariantNVmi32Z8VariantNZC3std11concurrency24PriorityMessageException@Base 6
+ _D3std11concurrency24PriorityMessageException6__initZ@Base 6
+ _D3std11concurrency24PriorityMessageException6__vtblZ@Base 6
+ _D3std11concurrency24PriorityMessageException7__ClassZ@Base 6
+ _D3std11concurrency33__T5_sendTS3std11concurrency3TidZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidS3std11concurrency3TidZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFNaNbNiNfKS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4ListZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFNaNbNiNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node11__fieldDtorMFZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node11__xopEqualsFKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node15__fieldPostblitMFZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__ctorMFNcS3std11concurrency7MessageZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node8opAssignMFNcNjS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node9__xtoHashFNbNeKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZm@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5frontMFNaNcNdNfZS3std11concurrency7Message@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5frontMFNdS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__ctorMFNaNbNcNiNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range8popFrontMFNaNfZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5clearMFNaNbNiNfZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7newNodeMFS3std11concurrency7MessageZPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7opSliceMFNaNbNiZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7sm_headOPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7sm_lockOS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock4lockMOFNbZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6unlockMOFNaNbNiZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8freeNodeMFPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8removeAtMFS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5RangeZv@Base 6
+ _D3std11concurrency3Tid11__xopEqualsFKxS3std11concurrency3TidKxS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency3Tid6__ctorMFNcNfC3std11concurrency10MessageBoxZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency3Tid6__initZ@Base 6
+ _D3std11concurrency3Tid8toStringMFMDFAxaZvZv@Base 6
+ _D3std11concurrency3Tid9__xtoHashFNbNeKxS3std11concurrency3TidZm@Base 6
+ _D3std11concurrency40__T7receiveTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ7receiveFDFNaNbNiAyhZvDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency41__T8checkopsTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ8checkopsFNaNbNiNfDFNaNbNiAyhZvDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvC4core4sync5mutex5MutexZ4flagOb@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvC4core4sync5mutex5MutexZPv@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvZPv@Base 6
+ _D3std11concurrency5yieldFNbZv@Base 6
+ _D3std11concurrency6locateFAyaZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency7Message11__fieldDtorMFZv@Base 6
+ _D3std11concurrency7Message11__xopEqualsFKxS3std11concurrency7MessageKxS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency7Message15__T6__ctorTAyhZ6__ctorMFNcE3std11concurrency7MsgTypeAyhZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message15__fieldPostblitMFZv@Base 6
+ _D3std11concurrency7Message18__T10convertsToTbZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message20__T10convertsToTAyhZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message22__T3mapTDFNaNbNiAyhZvZ3mapMFDFNaNbNiAyhZvZv@Base 6
+ _D3std11concurrency7Message22__T3mapTDFNaNbNiNfbZvZ3mapMFDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency7Message27__T3getTC6object9ThrowableZ3getMFNdZC6object9Throwable@Base 6
+ _D3std11concurrency7Message28__T3getTOC6object9ThrowableZ3getMFNdZOC6object9Throwable@Base 6
+ _D3std11concurrency7Message31__T3getTS3std11concurrency3TidZ3getMFNdZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency7Message34__T6__ctorTS3std11concurrency3TidZ6__ctorMFNcE3std11concurrency7MsgTypeS3std11concurrency3TidZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message35__T10convertsToTC6object9ThrowableZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message36__T10convertsToTOC6object9ThrowableZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message39__T10convertsToTS3std11concurrency3TidZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message46__T6__ctorTC3std11concurrency14LinkTerminatedZ6__ctorMFNcE3std11concurrency7MsgTypeC3std11concurrency14LinkTerminatedZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message47__T6__ctorTC3std11concurrency15OwnerTerminatedZ6__ctorMFNcE3std11concurrency7MsgTypeC3std11concurrency15OwnerTerminatedZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message6__initZ@Base 6
+ _D3std11concurrency7Message83__T3mapTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3mapMFDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency7Message85__T3mapTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbZ3mapMFDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency7Message85__T6__ctorTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ6__ctorMFNcE3std11concurrency7MsgTypeS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message88__T10convertsToTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message8opAssignMFNcNjS3std11concurrency7MessageZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message90__T10convertsToTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message9__xtoHashFNbNeKxS3std11concurrency7MessageZm@Base 6
+ _D3std11concurrency7thisTidFNdNfZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency83__T4sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ4sendFS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency84__T5_sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency84__T5_sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5_sendFS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency8ownerTidFNdZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency8registerFAyaS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency8thisInfoFNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency9Scheduler11__InterfaceZ@Base 6
+ _D3std11concurrency9schedulerC3std11concurrency9Scheduler@Base 6
+ _D3std11concurrency9tidByNameHAyaS3std11concurrency3Tid@Base 6
+ _D3std11mathspecial11logmdigammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial12__ModuleInfoZ@Base 6
+ _D3std11mathspecial14betaIncompleteFNaNbNiNfeeeZe@Base 6
+ _D3std11mathspecial15gammaIncompleteFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial18logmdigammaInverseFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial18normalDistributionFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial20gammaIncompleteComplFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial21betaIncompleteInverseFNaNbNiNfeeeZe@Base 6
+ _D3std11mathspecial25normalDistributionInverseFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial27gammaIncompleteComplInverseFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial3erfFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial4betaFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial4erfcFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial5gammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial7digammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial8logGammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial8sgnGammaFNaNbNiNfeZe@Base 6
+ _D3std11parallelism10addToChainFNaNbC6object9ThrowableKC6object9ThrowableKC6object9ThrowableZv@Base 6
+ _D3std11parallelism10foreachErrFZv@Base 6
+ _D3std11parallelism12AbstractTask11__xopEqualsFKxS3std11parallelism12AbstractTaskKxS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism12AbstractTask3jobMFZv@Base 6
+ _D3std11parallelism12AbstractTask4doneMFNdZb@Base 6
+ _D3std11parallelism12AbstractTask6__initZ@Base 6
+ _D3std11parallelism12AbstractTask9__xtoHashFNbNeKxS3std11parallelism12AbstractTaskZm@Base 6
+ _D3std11parallelism12__ModuleInfoZ@Base 6
+ _D3std11parallelism13__T3runTDFZvZ3runFDFZvZv@Base 6
+ _D3std11parallelism16submitAndExecuteFC3std11parallelism8TaskPoolMDFZvZv@Base 6
+ _D3std11parallelism17ParallelismThread6__ctorMFDFZvZC3std11parallelism17ParallelismThread@Base 6
+ _D3std11parallelism17ParallelismThread6__initZ@Base 6
+ _D3std11parallelism17ParallelismThread6__vtblZ@Base 6
+ _D3std11parallelism17ParallelismThread7__ClassZ@Base 6
+ _D3std11parallelism17findLastExceptionFNaNbC6object9ThrowableZC6object9Throwable@Base 6
+ _D3std11parallelism18_sharedStaticCtor2FZv@Base 6
+ _D3std11parallelism18_sharedStaticCtor9FZv@Base 6
+ _D3std11parallelism18_sharedStaticDtor7FZv@Base 6
+ _D3std11parallelism18defaultPoolThreadsFNdNeZk@Base 6
+ _D3std11parallelism18defaultPoolThreadsFNdNekZv@Base 6
+ _D3std11parallelism19_defaultPoolThreadsOk@Base 6
+ _D3std11parallelism20ParallelForeachError6__ctorMFZC3std11parallelism20ParallelForeachError@Base 6
+ _D3std11parallelism20ParallelForeachError6__initZ@Base 6
+ _D3std11parallelism20ParallelForeachError6__vtblZ@Base 6
+ _D3std11parallelism20ParallelForeachError7__ClassZ@Base 6
+ _D3std11parallelism21__T10scopedTaskTDFZvZ10scopedTaskFNfMDFZvZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism22__T14atomicSetUbyteThZ14atomicSetUbyteFNaNbNiKhhZv@Base 6
+ _D3std11parallelism23__T15atomicReadUbyteThZ15atomicReadUbyteFNaNbNiKhZh@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task10yieldForceMFNcNdNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task11__xopEqualsFKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZb@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task11enforcePoolMFNaNfZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task18executeInNewThreadMFNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task18executeInNewThreadMFNeiZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task4doneMFNdNeZb@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task4implFPvZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__ctorMFNaNbNcNiNfDFZvZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__dtorMFNfZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__initZ@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task7basePtrMFNaNbNdNiNfZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task8opAssignMFNfS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9__xtoHashFNbNeKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZm@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9spinForceMFNcNdNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9workForceMFNcNdNeZv@Base 6
+ _D3std11parallelism58__T14atomicCasUbyteTE3std11parallelism8TaskPool9PoolStateZ14atomicCasUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D3std11parallelism58__T14atomicSetUbyteTE3std11parallelism8TaskPool9PoolStateZ14atomicSetUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZv@Base 6
+ _D3std11parallelism59__T15atomicReadUbyteTE3std11parallelism8TaskPool9PoolStateZ15atomicReadUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateZh@Base 6
+ _D3std11parallelism8TaskPool10deleteItemMFPS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism8TaskPool10waiterLockMFZv@Base 6
+ _D3std11parallelism8TaskPool11abstractPutMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool11queueUnlockMFZv@Base 6
+ _D3std11parallelism8TaskPool11threadIndexm@Base 6
+ _D3std11parallelism8TaskPool11workerIndexMxFNbNdNfZm@Base 6
+ _D3std11parallelism8TaskPool12doSingleTaskMFZv@Base 6
+ _D3std11parallelism8TaskPool12waiterUnlockMFZv@Base 6
+ _D3std11parallelism8TaskPool13notifyWaitersMFZv@Base 6
+ _D3std11parallelism8TaskPool13startWorkLoopMFZv@Base 6
+ _D3std11parallelism8TaskPool15executeWorkLoopMFZv@Base 6
+ _D3std11parallelism8TaskPool16deleteItemNoSyncMFPS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism8TaskPool16tryDeleteExecuteMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool17abstractPutNoSyncMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool17nextInstanceIndexm@Base 6
+ _D3std11parallelism8TaskPool19defaultWorkUnitSizeMxFNaNbNfmZm@Base 6
+ _D3std11parallelism8TaskPool19waitUntilCompletionMFZv@Base 6
+ _D3std11parallelism8TaskPool22abstractPutGroupNoSyncMFPS3std11parallelism12AbstractTaskPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool3popMFZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism8TaskPool4sizeMxFNaNbNdNfZm@Base 6
+ _D3std11parallelism8TaskPool4stopMFNeZv@Base 6
+ _D3std11parallelism8TaskPool4waitMFZv@Base 6
+ _D3std11parallelism8TaskPool5doJobMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFNeZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFNemZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFPS3std11parallelism12AbstractTaskiZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__initZ@Base 6
+ _D3std11parallelism8TaskPool6__vtblZ@Base 6
+ _D3std11parallelism8TaskPool6finishMFNebZv@Base 6
+ _D3std11parallelism8TaskPool6notifyMFZv@Base 6
+ _D3std11parallelism8TaskPool7__ClassZ@Base 6
+ _D3std11parallelism8TaskPool8isDaemonMFNdNeZb@Base 6
+ _D3std11parallelism8TaskPool8isDaemonMFNdNebZv@Base 6
+ _D3std11parallelism8TaskPool8priorityMFNdNeZi@Base 6
+ _D3std11parallelism8TaskPool8priorityMFNdNeiZv@Base 6
+ _D3std11parallelism8TaskPool9notifyAllMFZv@Base 6
+ _D3std11parallelism8TaskPool9popNoSyncMFZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism8TaskPool9queueLockMFZv@Base 6
+ _D3std11parallelism8taskPoolFNdNeZ11initializedb@Base 6
+ _D3std11parallelism8taskPoolFNdNeZ4poolC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8taskPoolFNdNeZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism9totalCPUsyk@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger10logMsgPartMFNfAxaZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11__fieldDtorMFNeZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11beginLogMsgMFNfAyaiAyaAyaAyaE3std12experimental6logger4core8LogLevelS3std11concurrency3TidS3std8datetime7SysTimeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11getFilenameMFZAya@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger12finishLogMsgMFNfZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger4fileMFNdNfZS3std5stdio4File@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__ctorMFNfS3std5stdio4FilexE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__ctorMFNfxAyaxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__initZ@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__vtblZ@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger7__ClassZ@Base 6
+ _D3std12experimental6logger10filelogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger11writeLogMsgMFNiNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10nulllogger10NullLogger@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__initZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__vtblZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger7__ClassZ@Base 6
+ _D3std12experimental6logger10nulllogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger12insertLoggerMFNfAyaC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger12removeLoggerMFNfxAaZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger11multilogger11MultiLogger@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__initZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__vtblZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger7__ClassZ@Base 6
+ _D3std12experimental6logger11multilogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry11__xopEqualsFKxS3std12experimental6logger11multilogger16MultiLoggerEntryKxS3std12experimental6logger11multilogger16MultiLoggerEntryZb@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry9__xtoHashFNbNeKxS3std12experimental6logger11multilogger16MultiLoggerEntryZm@Base 6
+ _D3std12experimental6logger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger4core10TestLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core10TestLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core10TestLogger@Base 6
+ _D3std12experimental6logger4core10TestLogger6__initZ@Base 6
+ _D3std12experimental6logger4core10TestLogger6__vtblZ@Base 6
+ _D3std12experimental6logger4core10TestLogger7__ClassZ@Base 6
+ _D3std12experimental6logger4core12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger4core14globalLogLevelFNdNfE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core14globalLogLevelFNdNiNfZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core15stdSharedLoggerOC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core16StdForwardLogger@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__initZ@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__vtblZ@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger7__ClassZ@Base 6
+ _D3std12experimental6logger4core17stdThreadLocalLogFNdNfC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core17stdThreadLocalLogFNdNfZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core18_sharedStaticCtor1FZv@Base 6
+ _D3std12experimental6logger4core20stdSharedLoggerMutexC4core4sync5mutex5Mutex@Base 6
+ _D3std12experimental6logger4core21stdLoggerThreadLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core21stdThreadLocalLogImplFNdNeZ7_bufferG184h@Base 6
+ _D3std12experimental6logger4core21stdThreadLocalLogImplFNdNeZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core22__T16isLoggingEnabledZ16isLoggingEnabledFNaNfE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelLbZb@Base 6
+ _D3std12experimental6logger4core22stdSharedDefaultLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core23defaultSharedLoggerImplFNdNeZ7_bufferG224h@Base 6
+ _D3std12experimental6logger4core23defaultSharedLoggerImplFNdNeZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core23stdLoggerGlobalLogLevelOE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core28stdLoggerDefaultThreadLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core58__T11trustedLoadTE3std12experimental6logger4core8LogLevelZ11trustedLoadFNaNbNiNeKOE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core59__T11trustedLoadTxE3std12experimental6logger4core8LogLevelZ11trustedLoadFNaNbNiNeKOxE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core59__T12trustedStoreTE3std12experimental6logger4core8LogLevelZ12trustedStoreFNaNbNiNeKOE3std12experimental6logger4core8LogLevelKE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core60__T18systimeToISOStringTS3std5stdio4File17LockingTextWriterZ18systimeToISOStringFNfS3std5stdio4File17LockingTextWriterKxS3std8datetime7SysTimeZv@Base 6
+ _D3std12experimental6logger4core6Logger10forwardMsgMFNeKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core6Logger10logMsgPartMFNfAxaZv@Base 6
+ _D3std12experimental6logger4core6Logger11beginLogMsgMFNfAyaiAyaAyaAyaE3std12experimental6logger4core8LogLevelS3std11concurrency3TidS3std8datetime7SysTimeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core6Logger12fatalHandlerMFNdNiNfDFNfZvZv@Base 6
+ _D3std12experimental6logger4core6Logger12fatalHandlerMFNdNiNfZDFZv@Base 6
+ _D3std12experimental6logger4core6Logger12finishLogMsgMFNfZv@Base 6
+ _D3std12experimental6logger4core6Logger6__ctorMFNfE3std12experimental6logger4core8LogLevelZ9__lambda3FNbNeZC4core4sync5mutex5Mutex@Base 6
+ _D3std12experimental6logger4core6Logger6__ctorMFNfE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core6Logger6__initZ@Base 6
+ _D3std12experimental6logger4core6Logger6__vtblZ@Base 6
+ _D3std12experimental6logger4core6Logger7__ClassZ@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry11__xopEqualsFKxS3std12experimental6logger4core6Logger8LogEntryKxS3std12experimental6logger4core6Logger8LogEntryZb@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry6__initZ@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry8opAssignMFNaNbNcNjNfS3std12experimental6logger4core6Logger8LogEntryZS3std12experimental6logger4core6Logger8LogEntry@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry9__xtoHashFNbNeKxS3std12experimental6logger4core6Logger8LogEntryZm@Base 6
+ _D3std12experimental6logger4core6Logger8logLevelMFNdNiNfxE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core6Logger8logLevelMxFNaNdNiNfZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D3std12experimental6logger4core8MsgRange11__xopEqualsFKxS3std12experimental6logger4core8MsgRangeKxS3std12experimental6logger4core8MsgRangeZb@Base 6
+ _D3std12experimental6logger4core8MsgRange3putMFNfwZv@Base 6
+ _D3std12experimental6logger4core8MsgRange6__ctorMFNcNfC3std12experimental6logger4core6LoggerZS3std12experimental6logger4core8MsgRange@Base 6
+ _D3std12experimental6logger4core8MsgRange6__initZ@Base 6
+ _D3std12experimental6logger4core8MsgRange9__xtoHashFNbNeKxS3std12experimental6logger4core8MsgRangeZm@Base 6
+ _D3std12experimental6logger4core8parentOfFAyaZAya@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNfZ11trustedLoadFNaNbNiNeKOC3std12experimental6logger4core6LoggerZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNfZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12socketstream12SocketStream10writeBlockMFxPvmZm@Base 6
+ _D3std12socketstream12SocketStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std12socketstream12SocketStream5closeMFZv@Base 6
+ _D3std12socketstream12SocketStream6__ctorMFC3std6socket6SocketE3std6stream8FileModeZC3std12socketstream12SocketStream@Base 6
+ _D3std12socketstream12SocketStream6__ctorMFC3std6socket6SocketZC3std12socketstream12SocketStream@Base 6
+ _D3std12socketstream12SocketStream6__initZ@Base 6
+ _D3std12socketstream12SocketStream6__vtblZ@Base 6
+ _D3std12socketstream12SocketStream6socketMFZC3std6socket6Socket@Base 6
+ _D3std12socketstream12SocketStream7__ClassZ@Base 6
+ _D3std12socketstream12SocketStream8toStringMFZAya@Base 6
+ _D3std12socketstream12SocketStream9readBlockMFPvmZm@Base 6
+ _D3std12socketstream12__ModuleInfoZ@Base 6
+ _D3std1c4fenv12__ModuleInfoZ@Base 6
+ _D3std1c4math12__ModuleInfoZ@Base 6
+ _D3std1c4time12__ModuleInfoZ@Base 6
+ _D3std1c5linux11linuxextern12__ModuleInfoZ@Base 6
+ _D3std1c5linux4tipc12__ModuleInfoZ@Base 6
+ _D3std1c5linux5linux12__ModuleInfoZ@Base 6
+ _D3std1c5linux5linux13struct_stat646__initZ@Base 6
+ _D3std1c5linux6socket12__ModuleInfoZ@Base 6
+ _D3std1c5linux7pthread12__ModuleInfoZ@Base 6
+ _D3std1c5linux7termios12__ModuleInfoZ@Base 6
+ _D3std1c5stdio12__ModuleInfoZ@Base 6
+ _D3std1c6locale12__ModuleInfoZ@Base 6
+ _D3std1c6stdarg12__ModuleInfoZ@Base 6
+ _D3std1c6stddef12__ModuleInfoZ@Base 6
+ _D3std1c6stdlib12__ModuleInfoZ@Base 6
+ _D3std1c6string12__ModuleInfoZ@Base 6
+ _D3std1c6wcharh12__ModuleInfoZ@Base 6
+ _D3std1c7process12__ModuleInfoZ@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyaAyamC6object9ThrowableZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyaC6object9ThrowableAyamZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyammC6object9ThrowableAyamZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__initZ@Base 6
+ _D3std3csv12CSVException6__vtblZ@Base 6
+ _D3std3csv12CSVException7__ClassZ@Base 6
+ _D3std3csv12CSVException8toStringMFNaNfZAya@Base 6
+ _D3std3csv12__ModuleInfoZ@Base 6
+ _D3std3csv23HeaderMismatchException6__ctorMFNaNfAyaAyamC6object9ThrowableZC3std3csv23HeaderMismatchException@Base 6
+ _D3std3csv23HeaderMismatchException6__ctorMFNaNfAyaC6object9ThrowableAyamZC3std3csv23HeaderMismatchException@Base 6
+ _D3std3csv23HeaderMismatchException6__initZ@Base 6
+ _D3std3csv23HeaderMismatchException6__vtblZ@Base 6
+ _D3std3csv23HeaderMismatchException7__ClassZ@Base 6
+ _D3std3csv23IncompleteCellException6__ctorMFNaNfAyaAyamC6object9ThrowableZC3std3csv23IncompleteCellException@Base 6
+ _D3std3csv23IncompleteCellException6__ctorMFNaNfAyaC6object9ThrowableAyamZC3std3csv23IncompleteCellException@Base 6
+ _D3std3csv23IncompleteCellException6__initZ@Base 6
+ _D3std3csv23IncompleteCellException6__vtblZ@Base 6
+ _D3std3csv23IncompleteCellException7__ClassZ@Base 6
+ _D3std3net4curl12AutoProtocol6__initZ@Base 6
+ _D3std3net4curl12__ModuleInfoZ@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool3popMFNaNfZAh@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool4pushMFNaNbNfAhZv@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry11__xopEqualsFKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryZb@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry9__xtoHashFNbNeKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryZm@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool6__initZ@Base 6
+ _D3std3net4curl13CurlException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std3net4curl13CurlException@Base 6
+ _D3std3net4curl13CurlException6__initZ@Base 6
+ _D3std3net4curl13CurlException6__vtblZ@Base 6
+ _D3std3net4curl13CurlException7__ClassZ@Base 6
+ _D3std3net4curl19__T11CurlMessageTbZ11CurlMessage6__initZ@Base 6
+ _D3std3net4curl19_receiveAsyncChunksFAhKAhS3std3net4curl12__T4PoolTAhZ4PoolKAhS3std11concurrency3TidKbZm@Base 6
+ _D3std3net4curl20AsyncChunkInputRange11__xopEqualsFKxS3std3net4curl20AsyncChunkInputRangeKxS3std3net4curl20AsyncChunkInputRangeZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange6__ctorMFNcS3std11concurrency3TidmmZS3std3net4curl20AsyncChunkInputRange@Base 6
+ _D3std3net4curl20AsyncChunkInputRange6__initZ@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin514tryEnsureUnitsMFZv@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin54waitMFS4core4time8DurationZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin55emptyMFNdZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin55frontMFNdZAh@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin58popFrontMFZv@Base 6
+ _D3std3net4curl20AsyncChunkInputRange9__xtoHashFNbNeKxS3std3net4curl20AsyncChunkInputRangeZm@Base 6
+ _D3std3net4curl20CurlTimeoutException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std3net4curl20CurlTimeoutException@Base 6
+ _D3std3net4curl20CurlTimeoutException6__initZ@Base 6
+ _D3std3net4curl20CurlTimeoutException6__vtblZ@Base 6
+ _D3std3net4curl20CurlTimeoutException7__ClassZ@Base 6
+ _D3std3net4curl20_finalizeAsyncChunksFAhKAhS3std11concurrency3TidZv@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage11__xopEqualsFKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZb@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage6__initZ@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage9__xtoHashFNbNeKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZm@Base 6
+ _D3std3net4curl21__T11curlMessageTAyhZ11curlMessageFNaNbNiNfAyhZS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage@Base 6
+ _D3std3net4curl3FTP10addCommandMFAxaZv@Base 6
+ _D3std3net4curl3FTP10initializeMFZv@Base 6
+ _D3std3net4curl3FTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl3FTP11__xopEqualsFKxS3std3net4curl3FTPKxS3std3net4curl3FTPZb@Base 6
+ _D3std3net4curl3FTP13clearCommandsMFZv@Base 6
+ _D3std3net4curl3FTP13contentLengthMFNdmZv@Base 6
+ _D3std3net4curl3FTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl3FTP3dupMFZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP4Impl11__xopEqualsFKxS3std3net4curl3FTP4ImplKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std3net4curl3FTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D3std3net4curl3FTP4Impl8opAssignMFNcNjS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std3net4curl3FTP4Impl9__xtoHashFNbNeKxS3std3net4curl3FTP4ImplZm@Base 6
+ _D3std3net4curl3FTP6__initZ@Base 6
+ _D3std3net4curl3FTP6opCallFAxaZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP6opCallFZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl3FTP8encodingMFNdAyaZv@Base 6
+ _D3std3net4curl3FTP8encodingMFNdZAya@Base 6
+ _D3std3net4curl3FTP8opAssignMFNcNjS3std3net4curl3FTPZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP9__mixin1210dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210onProgressMFNdDFmmmmZiZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210verifyHostMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1211dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl3FTP9__mixin1214connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1214localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin1216operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1217setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1222setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1228defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl3FTP9__mixin125proxyMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin126handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl3FTP9__mixin126onSendMFNdDFAvZmZv@Base 6
+ _D3std3net4curl3FTP9__mixin127verboseMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin128shutdownMFZv@Base 6
+ _D3std3net4curl3FTP9__mixin129isStoppedMFNdZb@Base 6
+ _D3std3net4curl3FTP9__mixin129localPortMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin129onReceiveMFNdDFAhZmZv@Base 6
+ _D3std3net4curl3FTP9__mixin129proxyPortMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin129proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl3FTP9__xtoHashFNbNeKxS3std3net4curl3FTPZm@Base 6
+ _D3std3net4curl4Curl10initializeMFZv@Base 6
+ _D3std3net4curl4Curl10onProgressMFNdDFmmmmZiZv@Base 6
+ _D3std3net4curl4Curl11errorStringMFiZAya@Base 6
+ _D3std3net4curl4Curl13_seekCallbackUPvliZi@Base 6
+ _D3std3net4curl4Curl13_sendCallbackUPammPvZm@Base 6
+ _D3std3net4curl4Curl14onSocketOptionMFNdDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiZv@Base 6
+ _D3std3net4curl4Curl14throwOnStoppedMFAyaZv@Base 6
+ _D3std3net4curl4Curl15onReceiveHeaderMFNdDFxAaZvZv@Base 6
+ _D3std3net4curl4Curl16_receiveCallbackUxPammPvZm@Base 6
+ _D3std3net4curl4Curl16clearIfSupportedMFE3etc1c4curl10CurlOptionZv@Base 6
+ _D3std3net4curl4Curl17_progressCallbackUPvddddZi@Base 6
+ _D3std3net4curl4Curl21_socketOptionCallbackUPvE3std6socket8socket_tiZi@Base 6
+ _D3std3net4curl4Curl22_receiveHeaderCallbackUxPammPvZm@Base 6
+ _D3std3net4curl4Curl3dupMFZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionAxaZv@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionPvZv@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionlZv@Base 6
+ _D3std3net4curl4Curl4curlFNcNdZS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl4Curl5clearMFE3etc1c4curl10CurlOptionZv@Base 6
+ _D3std3net4curl4Curl5pauseMFbbZv@Base 6
+ _D3std3net4curl4Curl6__initZ@Base 6
+ _D3std3net4curl4Curl6_checkMFiZv@Base 6
+ _D3std3net4curl4Curl6onSeekMFNdDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekZv@Base 6
+ _D3std3net4curl4Curl6onSendMFNdDFAvZmZv@Base 6
+ _D3std3net4curl4Curl7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4Curl7performMFbZi@Base 6
+ _D3std3net4curl4Curl8shutdownMFZv@Base 6
+ _D3std3net4curl4Curl9onReceiveMFNdDFAhZmZv@Base 6
+ _D3std3net4curl4HTTP10StatusLine11__xopEqualsFKxS3std3net4curl4HTTP10StatusLineKxS3std3net4curl4HTTP10StatusLineZb@Base 6
+ _D3std3net4curl4HTTP10StatusLine5resetMFNfZv@Base 6
+ _D3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D3std3net4curl4HTTP10StatusLine8toStringMFZAya@Base 6
+ _D3std3net4curl4HTTP10StatusLine9__xtoHashFNbNeKxS3std3net4curl4HTTP10StatusLineZm@Base 6
+ _D3std3net4curl4HTTP10initializeMFZv@Base 6
+ _D3std3net4curl4HTTP10statusLineMFNdZS3std3net4curl4HTTP10StatusLine@Base 6
+ _D3std3net4curl4HTTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl4HTTP11__xopEqualsFKxS3std3net4curl4HTTPKxS3std3net4curl4HTTPZb@Base 6
+ _D3std3net4curl4HTTP11setPostDataMFAxvAyaZv@Base 6
+ _D3std3net4curl4HTTP12maxRedirectsMFNdkZv@Base 6
+ _D3std3net4curl4HTTP12setCookieJarMFAxaZv@Base 6
+ _D3std3net4curl4HTTP12setUserAgentMFAxaZv@Base 6
+ _D3std3net4curl4HTTP13contentLengthMFNdmZv@Base 6
+ _D3std3net4curl4HTTP14flushCookieJarMFZv@Base 6
+ _D3std3net4curl4HTTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl4HTTP15clearAllCookiesMFZv@Base 6
+ _D3std3net4curl4HTTP15onReceiveHeaderMFNdDFxAaxAaZvZv@Base 6
+ _D3std3net4curl4HTTP15responseHeadersMFNdZHAyaAya@Base 6
+ _D3std3net4curl4HTTP16addRequestHeaderMFAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZ3bufG63a@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZ9userAgentAya@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZAya@Base 6
+ _D3std3net4curl4HTTP16setTimeConditionMFE3etc1c4curl12CurlTimeCondS3std8datetime7SysTimeZv@Base 6
+ _D3std3net4curl4HTTP19clearRequestHeadersMFZv@Base 6
+ _D3std3net4curl4HTTP19clearSessionCookiesMFZv@Base 6
+ _D3std3net4curl4HTTP19defaultMaxRedirectsk@Base 6
+ _D3std3net4curl4HTTP19onReceiveStatusLineMFNdDFS3std3net4curl4HTTP10StatusLineZvZv@Base 6
+ _D3std3net4curl4HTTP20authenticationMethodMFNdE3etc1c4curl8CurlAuthZv@Base 6
+ _D3std3net4curl4HTTP3dupMFZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP4Impl11__xopEqualsFKxS3std3net4curl4HTTP4ImplKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std3net4curl4HTTP4Impl15onReceiveHeaderMFNdDFxAaxAaZvZv@Base 6
+ _D3std3net4curl4HTTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D3std3net4curl4HTTP4Impl8opAssignMFNcNjS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std3net4curl4HTTP4Impl9__xtoHashFNbNeKxS3std3net4curl4HTTP4ImplZm@Base 6
+ _D3std3net4curl4HTTP6__initZ@Base 6
+ _D3std3net4curl4HTTP6caInfoMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP6methodMFNdE3std3net4curl4HTTP6MethodZv@Base 6
+ _D3std3net4curl4HTTP6methodMFNdZE3std3net4curl4HTTP6Method@Base 6
+ _D3std3net4curl4HTTP6opCallFAxaZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP6opCallFZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4HTTP8opAssignMFNcNjS3std3net4curl4HTTPZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP8postDataMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP8postDataMFNdAxvZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510onProgressMFNdDFmmmmZiZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510verifyHostMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3511dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3514connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3514localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3516operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3517setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3522setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3528defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl4HTTP9__mixin355proxyMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin356handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4HTTP9__mixin356onSendMFNdDFAvZmZv@Base 6
+ _D3std3net4curl4HTTP9__mixin357verboseMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin358shutdownMFZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359isStoppedMFNdZb@Base 6
+ _D3std3net4curl4HTTP9__mixin359localPortMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359onReceiveMFNdDFAhZmZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359proxyPortMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl4HTTP9__xtoHashFNbNeKxS3std3net4curl4HTTPZm@Base 6
+ _D3std3net4curl4HTTP9setCookieMFAxaZv@Base 6
+ _D3std3net4curl4SMTP10initializeMFZv@Base 6
+ _D3std3net4curl4SMTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl4SMTP11__xopEqualsFKxS3std3net4curl4SMTPKxS3std3net4curl4SMTPZb@Base 6
+ _D3std3net4curl4SMTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl4SMTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl4SMTP4Impl6__initZ@Base 6
+ _D3std3net4curl4SMTP4Impl7messageMFNdAyaZv@Base 6
+ _D3std3net4curl4SMTP4Impl8opAssignMFNcNjS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std3net4curl4SMTP6__initZ@Base 6
+ _D3std3net4curl4SMTP6opCallFAxaZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP6opCallFZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP7messageMFNdAyaZv@Base 6
+ _D3std3net4curl4SMTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4SMTP8opAssignMFNcNjS3std3net4curl4SMTPZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP9__mixin1010dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010onProgressMFNdDFmmmmZiZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010verifyHostMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1011dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1014connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1014localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1016operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1017setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1022setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1028defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl4SMTP9__mixin105proxyMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin106handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4SMTP9__mixin106onSendMFNdDFAvZmZv@Base 6
+ _D3std3net4curl4SMTP9__mixin107verboseMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin108shutdownMFZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109isStoppedMFNdZb@Base 6
+ _D3std3net4curl4SMTP9__mixin109localPortMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109onReceiveMFNdDFAhZmZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109proxyPortMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl4SMTP9__xtoHashFNbNeKxS3std3net4curl4SMTPZm@Base 6
+ _D3std3net4curl7CurlAPI19_sharedStaticDtor18FZv@Base 6
+ _D3std3net4curl7CurlAPI3API6__initZ@Base 6
+ _D3std3net4curl7CurlAPI4_apiS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl7CurlAPI6__initZ@Base 6
+ _D3std3net4curl7CurlAPI7_handlePv@Base 6
+ _D3std3net4curl7CurlAPI7loadAPIFZ5namesyAAa@Base 6
+ _D3std3net4curl7CurlAPI7loadAPIFZPv@Base 6
+ _D3std3net4curl7CurlAPI8instanceFNcNdZS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl8isFTPUrlFAxaZb@Base 6
+ _D3std3net7isemail10AsciiToken6__initZ@Base 6
+ _D3std3net7isemail11EmailStatus10domainPartMxFNdZAya@Base 6
+ _D3std3net7isemail11EmailStatus10statusCodeMxFNdZE3std3net7isemail15EmailStatusCode@Base 6
+ _D3std3net7isemail11EmailStatus11__xopEqualsFKxS3std3net7isemail11EmailStatusKxS3std3net7isemail11EmailStatusZb@Base 6
+ _D3std3net7isemail11EmailStatus5validMxFNdZb@Base 6
+ _D3std3net7isemail11EmailStatus6__ctorMFNcbAyaAyaE3std3net7isemail15EmailStatusCodeZS3std3net7isemail11EmailStatus@Base 6
+ _D3std3net7isemail11EmailStatus6__initZ@Base 6
+ _D3std3net7isemail11EmailStatus6statusMxFNdZAya@Base 6
+ _D3std3net7isemail11EmailStatus8toStringMxFZAya@Base 6
+ _D3std3net7isemail11EmailStatus9__xtoHashFNbNeKxS3std3net7isemail11EmailStatusZm@Base 6
+ _D3std3net7isemail11EmailStatus9localPartMxFNdZAya@Base 6
+ _D3std3net7isemail12__ModuleInfoZ@Base 6
+ _D3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D3std3net7isemail21statusCodeDescriptionFE3std3net7isemail15EmailStatusCodeZAya@Base 6
+ _D3std3net7isemail5Token6__initZ@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZm@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNemZwZ20__T12toCaseLengthTaZ12toCaseLengthFNaNfxAaZm@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNemZwZ20__T12toCaseLengthTuZ12toCaseLengthFNaNfxAuZm@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNemZwZ20__T12toCaseLengthTwZ12toCaseLengthFNaNfxAwZm@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNemZwZ20__T12toCaseLengthTaZ12toCaseLengthFNaNfxAaZm@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNemZwZ20__T12toCaseLengthTuZ12toCaseLengthFNaNfxAuZm@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNemZwZ20__T12toCaseLengthTwZ12toCaseLengthFNaNfxAwZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray12__T3ptrVmi2Z3ptrMNgFNaNbNdNiZNgS3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray14__T5sliceVmi2Z5sliceMNgFNaNbNdNiZNgS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray15__T6lengthVmi2Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray15__T6lengthVmi2Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray16__T7raw_ptrVmi2Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArrayZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray12__T3ptrVmi2Z3ptrMNgFNaNbNdNiZNgS3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray14__T5sliceVmi2Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray15__T6lengthVmi2Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray15__T6lengthVmi2Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi2Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArrayZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray14__T5sliceVmi2Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray15__T6lengthVmi2Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray15__T6lengthVmi2Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi2Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArrayZm@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTaZ13toCaseInPlaceFNaNeKAaZ6moveToFNaNbNiNfAammmZm@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTaZ13toCaseInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTuZ13toCaseInPlaceFNaNeKAuZ6moveToFNaNbNiNfAummmZm@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTuZ13toCaseInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTwZ13toCaseInPlaceFNaNeKAwZ6moveToFNaNbNiNfAwmmmZm@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTwZ13toCaseInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTaZ13toCaseInPlaceFNaNeKAaZ6moveToFNaNbNiNfAammmZm@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTaZ13toCaseInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTuZ13toCaseInPlaceFNaNeKAuZ6moveToFNaNbNiNfAummmZm@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTuZ13toCaseInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTwZ13toCaseInPlaceFNaNeKAwZ6moveToFNaNbNiNfAwmmmZm@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTwZ13toCaseInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNemZwZ26__T18toCaseInPlaceAllocTaZ18toCaseInPlaceAllocFNaNeKAammZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNemZwZ26__T18toCaseInPlaceAllocTuZ18toCaseInPlaceAllocFNaNeKAummZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNemZwZ26__T18toCaseInPlaceAllocTwZ18toCaseInPlaceAllocFNaNeKAwmmZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNemZwZ26__T18toCaseInPlaceAllocTaZ18toCaseInPlaceAllocFNaNeKAammZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNemZwZ26__T18toCaseInPlaceAllocTuZ18toCaseInPlaceAllocFNaNeKAummZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNemZwZ26__T18toCaseInPlaceAllocTwZ18toCaseInPlaceAllocFNaNeKAwmmZv@Base 6
+ _D3std3uni10compressToFNaNbNfkKAhZv@Base 6
+ _D3std3uni10isPowerOf2FNaNbNiNfmZb@Base 6
+ _D3std3uni10nfkcQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkcQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10numberTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10numberTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10safeRead24FNaNbNiNexPhmZk@Base 6
+ _D3std3uni10symbolTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10symbolTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10toLowerTabFNaNbNiNemZw@Base 6
+ _D3std3uni10toTitleTabFNaNbNiNemZw@Base 6
+ _D3std3uni10toUpperTabFNaNbNiNemZw@Base 6
+ _D3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArrayZS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4TrieKxS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZt@Base 6
+ _D3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni113__T23switchUniformLowerBoundS753std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z9binaryFunTAxkTkZ23switchUniformLowerBoundFNaNbNiNfAxkkZm@Base 6
+ _D3std3uni11composeJamoFNaNbNiNewwwZw@Base 6
+ _D3std3uni11isGraphicalFNaNbNiNfwZb@Base 6
+ _D3std3uni11isSurrogateFNaNbNiNfwZb@Base 6
+ _D3std3uni11safeWrite24FNaNbNiNePhkmZv@Base 6
+ _D3std3uni11toTitlecaseFNaNbNiNfwZw@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder109__T14deduceMaxIndexTS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilderKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi1TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi0TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVmi1TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder19__T8addValueVmi1TbZ8addValueMFNaNbNebmZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNembZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder60__T8addValueVmi0TS3std3uni21__T9BitPackedTkVmi13Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi13Z9BitPackedmZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder109__T14deduceMaxIndexTS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilderKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi0TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder19__T8addValueVmi1TtZ8addValueMFNaNbNetmZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNemtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder60__T8addValueVmi0TS3std3uni21__T9BitPackedTkVmi12Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi12Z9BitPackedmZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVmi1TS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVmi1TS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni121__T11findSetNameS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni124__T11findSetNameS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZl@Base 6
+ _D3std3uni127__T11findSetNameS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZl@Base 6
+ _D3std3uni12__ModuleInfoZ@Base 6
+ _D3std3uni12ceilPowerOf2FNaNbNiNfmZm@Base 6
+ _D3std3uni12fullCaseTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni12fullCaseTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni12isPrivateUseFNaNbNiNfwZb@Base 6
+ _D3std3uni12toLowerIndexFNaNbNiNewZt@Base 6
+ _D3std3uni12toTitleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni12toUpperIndexFNaNbNiNewZt@Base 6
+ _D3std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZl@Base 6
+ _D3std3uni13ReallocPolicy12__T5allocTkZ5allocFNemZAk@Base 6
+ _D3std3uni13ReallocPolicy14__T7destroyTkZ7destroyFNbNiNeKAkZv@Base 6
+ _D3std3uni13ReallocPolicy14__T7reallocTkZ7reallocFNeAkmZAk@Base 6
+ _D3std3uni13ReallocPolicy15__T6appendTkTiZ6appendFNeKAkiZv@Base 6
+ _D3std3uni13ReallocPolicy6__initZ@Base 6
+ _D3std3uni13floorPowerOf2FNaNbNiNfmZm@Base 6
+ _D3std3uni13graphicalTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13graphicalTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13isPunctuationFNaNbNiNfwZb@Base 6
+ _D3std3uni13isSurrogateHiFNaNbNiNfwZb@Base 6
+ _D3std3uni13isSurrogateLoFNaNbNiNfwZb@Base 6
+ _D3std3uni13lowerCaseTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13lowerCaseTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13upperCaseTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13upperCaseTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi2Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi2Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi2Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZm@Base 6
+ _D3std3uni14MatcherConcept6__initZ@Base 6
+ _D3std3uni14__T5forceTkTiZ5forceFNaNbNiNfiZk@Base 6
+ _D3std3uni14combiningClassFNaNbNiNfwZh@Base 6
+ _D3std3uni14decompressFromFNaNfAxhKmZk@Base 6
+ _D3std3uni14isNonCharacterFNaNbNiNfwZb@Base 6
+ _D3std3uni14simpleCaseTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni14simpleCaseTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAaZv@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAuZv@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAwZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAaZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAuZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAwZv@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4TrieKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedThZ10MultiArrayZS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZh@Base 6
+ _D3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTtZ10MultiArrayZS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTtZ10MultiArrayZS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZt@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni15__T7toLowerTAaZ7toLowerFNaNeAaZAa@Base 6
+ _D3std3uni15decomposeHangulFNewZS3std3uni8Grapheme@Base 6
+ _D3std3uni15hangulRecomposeFNaNbNiNeAwZv@Base 6
+ _D3std3uni15punctuationTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni15punctuationTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni15unalignedRead24FNaNbNiNexPhmZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder12__T3idxVmi2Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVmi2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder19__T8addValueVmi2TbZ8addValueMFNaNbNebmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder59__T8addValueVmi0TS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNembZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder60__T8addValueVmi1TS3std3uni21__T9BitPackedTkVmi14Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi14Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder12__T3idxVmi2Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVmi2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder19__T8addValueVmi2TbZ8addValueMFNaNbNebmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder59__T8addValueVmi0TS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNembZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder60__T8addValueVmi1TS3std3uni21__T9BitPackedTkVmi13Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi13Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder12__T3idxVmi2Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVmi2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder19__T8addValueVmi2TbZ8addValueMFNaNbNebmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder59__T8addValueVmi0TS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNembZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder60__T8addValueVmi1TS3std3uni21__T9BitPackedTkVmi12Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi12Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi2Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder19__T8addValueVmi2ThZ8addValueMFNaNbNehmZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder59__T8addValueVmi0TS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNemhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder60__T8addValueVmi1TS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi15Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNehZS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder89__T15spillToNextPageVmi2TS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder93__T19spillToNextPageImplVmi2TS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder12__T3idxVmi2Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder19__T8addValueVmi2TtZ8addValueMFNaNbNetmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder59__T8addValueVmi0TS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNemtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder60__T8addValueVmi1TS3std3uni21__T9BitPackedTkVmi16Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi16Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVmi2TS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVmi2TS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi2Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder19__T8addValueVmi2TtZ8addValueMFNaNbNetmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder59__T8addValueVmi0TS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNemtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder60__T8addValueVmi1TS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi15Z9BitPackedmZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVmi2TS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVmi2TS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni16__T7toLowerTAxaZ7toLowerFNaNeAxaZAxa@Base 6
+ _D3std3uni16__T7toLowerTAyaZ7toLowerFNaNeAyaZAya@Base 6
+ _D3std3uni16__T7toLowerTAyuZ7toLowerFNaNeAyuZAyu@Base 6
+ _D3std3uni16__T7toLowerTAywZ7toLowerFNaNbNeAywZAyw@Base 6
+ _D3std3uni16__T7toUpperTAyaZ7toUpperFNaNeAyaZAya@Base 6
+ _D3std3uni16__T7toUpperTAyuZ7toUpperFNaNeAyuZAyu@Base 6
+ _D3std3uni16__T7toUpperTAywZ7toUpperFNaNbNeAywZAyw@Base 6
+ _D3std3uni16canonMappingTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16canonMappingTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16nonCharacterTrieFNaNbNdNiNfZ3resyS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16nonCharacterTrieFNaNbNdNiNfZyS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toLowerIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toLowerIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toTitleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toTitleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toUpperIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toUpperIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16unalignedWrite24FNaNbNiNePhkmZv@Base 6
+ _D3std3uni17CodepointInterval11__xopEqualsFKxS3std3uni17CodepointIntervalKxS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni17CodepointInterval1aMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std3uni17CodepointInterval1bMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std3uni17CodepointInterval43__T8opEqualsTxS3std3uni17CodepointIntervalZ8opEqualsMxFNaNbNiNfxS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni17CodepointInterval6__ctorMFNaNbNcNiNfkkZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni17CodepointInterval6__initZ@Base 6
+ _D3std3uni17__T4icmpTAxaTAxaZ4icmpFNaNeAxaAxaZi@Base 6
+ _D3std3uni17__T4icmpTAxuTAxuZ4icmpFNaNeAxuAxuZi@Base 6
+ _D3std3uni17__T4icmpTAxwTAxwZ4icmpFNaNbNiNeAxwAxwZi@Base 6
+ _D3std3uni17__T8spaceForVmi1Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni17__T8spaceForVmi7Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni17__T8spaceForVmi8Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni17compatMappingTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni17compatMappingTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi2Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray12__T3ptrVmi3Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi2Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray14__T5sliceVmi3Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi2Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi3Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray15__T6lengthVmi3Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi2Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray16__T7raw_ptrVmi3Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZm@Base 6
+ _D3std3uni189__T14loadUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni18__T5sicmpTAxaTAxaZ5sicmpFNaNeAxaAxaZi@Base 6
+ _D3std3uni18__T5sicmpTAxuTAxuZ5sicmpFNaNeAxuAxuZi@Base 6
+ _D3std3uni18__T5sicmpTAxwTAxwZ5sicmpFNaNeAxwAxwZi@Base 6
+ _D3std3uni18__T8spaceForVmi11Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni18__T8spaceForVmi12Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni18__T8spaceForVmi13Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni18__T8spaceForVmi14Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni18__T8spaceForVmi15Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni18__T8spaceForVmi16Z8spaceForFNaNbNiNfmZm@Base 6
+ _D3std3uni18combiningClassTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18combiningClassTrieFNaNbNdNiNfZyS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18graphemeExtendTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18graphemeExtendTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18simpleCaseFoldingsFNaNbNewZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range5emptyMxFNaNbNdZb@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range5frontMxFNaNbNdZw@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__ctorMFNaNbNckkZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__ctorMFNaNbNcwZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__initZ@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6lengthMxFNaNbNdZk@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range7isSmallMxFNaNbNdZb@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range8popFrontMFNaNbZv@Base 6
+ _D3std3uni18toLowerSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni18toTitleSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni18toUpperSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni192__T14loadUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni195__T14loadUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni199__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZm@Base 6
+ _D3std3uni199__T12mapTrieIndexTS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZm@Base 6
+ _D3std3uni19compositionJumpTrieFNaNbNdNiNfZ3resyS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni19compositionJumpTrieFNaNbNdNiNfZyS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni19decompressIntervalsFNaNfAxhZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni19hangulSyllableIndexFNaNbNiNewZi@Base 6
+ _D3std3uni19isRegionalIndicatorFNfwZb@Base 6
+ _D3std3uni20__T9BitPackedTbVmi1Z9BitPacked6__initZ@Base 6
+ _D3std3uni20__T9BitPackedTkVmi7Z9BitPacked6__initZ@Base 6
+ _D3std3uni20__T9BitPackedTkVmi8Z9BitPacked6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNemmbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVmi3TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi0Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi1Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi2Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder12__T3idxVmi3Z3idxMFNaNbNcNdNiNeZm@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVmi2TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVmi3TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVmi2TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder19__T8addValueVmi3TbZ8addValueMFNaNbNebmZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder201__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZm@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder59__T8addValueVmi0TS3std3uni20__T9BitPackedTkVmi7Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi7Z9BitPackedmZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNembZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder60__T8addValueVmi1TS3std3uni21__T9BitPackedTkVmi11Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi11Z9BitPackedmZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder60__T8addValueVmi2TS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVmi15Z9BitPackedmZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ11TrieBuilderZm@Base 6
+ _D3std3uni21DecompressedIntervals11__xopEqualsFKxS3std3uni21DecompressedIntervalsKxS3std3uni21DecompressedIntervalsZb@Base 6
+ _D3std3uni21DecompressedIntervals4saveMFNaNdNfZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni21DecompressedIntervals5emptyMxFNaNdNfZb@Base 6
+ _D3std3uni21DecompressedIntervals5frontMFNaNdNfZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni21DecompressedIntervals6__ctorMFNaNcNfAxhZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D3std3uni21DecompressedIntervals8popFrontMFNaNfZv@Base 6
+ _D3std3uni21DecompressedIntervals9__xtoHashFNbNeKxS3std3uni21DecompressedIntervalsZm@Base 6
+ _D3std3uni21__T11copyForwardTiTkZ11copyForwardFNaNbNiNfAiAkZv@Base 6
+ _D3std3uni21__T11copyForwardTkTkZ11copyForwardFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni21__T11copyForwardTmTmZ11copyForwardFNaNbNiNfAmAmZv@Base 6
+ _D3std3uni21__T9BitPackedTkVmi11Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVmi12Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVmi13Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVmi14Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVmi15Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVmi16Z9BitPacked6__initZ@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxaZ12fullCasedCmpFNaNewwKAxaZi@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxuZ12fullCasedCmpFNaNewwKAxuZi@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxwZ12fullCasedCmpFNaNbNiNewwKAxwZi@Base 6
+ _D3std3uni22__T14toLowerInPlaceTaZ14toLowerInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni22__T14toLowerInPlaceTuZ14toLowerInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni22__T14toLowerInPlaceTwZ14toLowerInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTaZ14toUpperInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTuZ14toUpperInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTwZ14toUpperInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni22__T6asTrieTtVii12Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZxS3std3uni112__T4TrieTtTwVmi1114112TS3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBits6__initZ@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni23__T13copyBackwardsTkTkZ13copyBackwardsFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni23__T13copyBackwardsTmTmZ13copyBackwardsFNaNbNiNfAmAmZv@Base 6
+ _D3std3uni23__T15packedArrayViewThZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T15packedArrayViewTtZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23genUnrolledSwitchSearchFmZAya@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ10MultiArrayZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxmAxmAxmZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4TrieZm@Base 6
+ _D3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBits6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZh@Base 6
+ _D3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl11simpleWriteMFNaNbNiNehmZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNehmZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZh@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii4Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii5Vii8Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii6Vii7Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieThVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieThTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii8Vii5Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZxS3std3uni158__T4TrieTtTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZt@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl11simpleWriteMFNaNbNiNetmZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNetmZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZt@Base 6
+ _D3std3uni26__T16propertyNameLessTaTaZ16propertyNameLessFNaNfAxaAxaZb@Base 6
+ _D3std3uni27__T13replicateBitsVmi8Vmi8Z13replicateBitsFNaNbNiNfmZm@Base 6
+ _D3std3uni28__T13replicateBitsVmi1Vmi64Z13replicateBitsFNaNbNiNfmZm@Base 6
+ _D3std3uni28__T13replicateBitsVmi2Vmi32Z13replicateBitsFNaNbNiNfmZm@Base 6
+ _D3std3uni28__T13replicateBitsVmi4Vmi16Z13replicateBitsFNaNbNiNfmZm@Base 6
+ _D3std3uni28__T13replicateBitsVmi64Vmi1Z13replicateBitsFNaNbNiNfmZm@Base 6
+ _D3std3uni28__T20isPrettyPropertyNameTaZ20isPrettyPropertyNameFNaNfxAaZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZi@Base 6
+ _D3std3uni29__T6asTrieTbVii7Vii4Vii4Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBitsTS3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBitsTS3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T16codepointSetTrieVii13Vii8Z87__T16codepointSetTrieTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16codepointSetTrieFNaNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplKxS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNehmZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNehmmZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl77__T8opEqualsTS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl78__T8opEqualsTxS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZh@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplKxS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNetmZv@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNetmmZv@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl78__T8opEqualsTS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl79__T8opEqualsTxS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZt@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray10__postblitMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray11__T6appendZ6appendMFNaNbNeAkXv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray11__xopEqualsFKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray12__T7opIndexZ7opIndexMxFNaNbNiNemZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray13__T8opEqualsZ8opEqualsMxFNaNbNiNeKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray13opIndexAssignMFNaNbNekmZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray14__T6__ctorTAkZ6__ctorMFNaNbNcNeAkZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray16dupThisReferenceMFNaNbNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray17freeThisReferenceMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray5reuseFNaNbNeAkZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray673__T6__ctorTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ6__ctorMFNaNcNeS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__dtorMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6lengthMFNaNbNdNemZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMFNaNbNeZAk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMFNaNbNemmZAk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMxFNaNbNiNeZAxk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMxFNaNbNiNemmZAxk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8opAssignMFNaNbNcNiNjNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8refCountMFNaNbNdNiNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8refCountMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray9__xtoHashFNbNeKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList10byIntervalMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11addIntervalMFNaNbNeiimZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange5frontMxFNaNbNdNiNeZw@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__ctorMFNaNbNcNiNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12__T7scanForZ7scanForMxFNaNbNiNewZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ41__T6bisectTAS3std3uni17CodepointIntervalZ6bisectFAS3std3uni17CodepointIntervalmAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ47__T11binaryScopeTAS3std3uni17CodepointIntervalZ11binaryScopeFAS3std3uni17CodepointIntervalAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ47__T11linearScopeTAS3std3uni17CodepointIntervalZ11linearScopeFNaNfAS3std3uni17CodepointIntervalAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals13opIndexAssignMFNaNbNiNeS3std3uni17CodepointIntervalmZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4backMFNaNbNdNiNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4backMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4saveMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5frontMFNaNbNdNiNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5frontMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__ctorMFNaNbNcNiNeAkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__ctorMFNaNbNcNiNeAkmmZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7opIndexMxFNaNbNiNemZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7opSliceMFNaNbNiNemmZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7popBackMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList19__T13fromIntervalsZ13fromIntervalsFNaNbNeAkXS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList27__T10opOpAssignVAyaa1_7cTkZ10opOpAssignMFNaNbNcNekZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList27__T10opOpAssignVAyaa1_7cTwZ10opOpAssignMFNaNbNcNewZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList52__T13fromIntervalsTS3std3uni21DecompressedIntervalsZ13fromIntervalsFNaNeS3std3uni21DecompressedIntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals13opIndexAssignMFNaNbNeS3std3uni17CodepointIntervalmZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4backMFNaNbNdNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4backMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4saveMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5frontMFNaNbNdNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5frontMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__ctorMFNaNbNcNiNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__ctorMFNaNbNcNiNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraymmZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7opIndexMxFNaNbNiNemZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7opSliceMFNaNbNiNemmZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7popBackMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6lengthMFNaNbNdNiNeZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList73__T3addTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ3addMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList73__T3subTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ3subMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList76__T6__ctorTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ6__ctorMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList79__T9intersectTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ9intersectMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList7opIndexMxFNaNbNiNekZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList7subCharMFNaNbNcNewZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList87__T8opBinaryVAyaa1_26TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ8opBinaryMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList87__T8opBinaryVAyaa1_7cTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ8opBinaryMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8__T3addZ3addMFNaNbNcNekkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8dropUpToMFNaNbNekmZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8invertedMFNaNbNdNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ72__T9__lambda1TS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ9__lambda1FNaNbNiNfS3std3uni17CodepointIntervalS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8skipUpToMFNaNbNekmZm@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8toStringMFNeMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_26TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_2dTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_7cTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_7eTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZm@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray10__postblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray11__xopEqualsFKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray13__T8opEqualsZ8opEqualsMxFNaNbNiNeKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray13opIndexAssignMFNekmZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray16dupThisReferenceMFNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray17freeThisReferenceMFNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray5reuseFNeAkZS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__dtorMFNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__initZ@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6lengthMFNdNemZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMFNeZAk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMFNemmZAk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMxFNaNbNiNeZAxk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMxFNaNbNiNemmZAxk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8opAssignMFNbNcNiNjNeS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8refCountMFNaNbNdNiNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8refCountMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray9__xtoHashFNbNeKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZm@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed11__xopEqualsFKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed13opIndexAssignMFNaNbNiNfwmZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4backMFNaNbNdNiNfwZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4backMxFNaNbNdNiNfZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4saveMNgFNaNbNdNiNfZNgS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5frontMFNaNbNdNiNfwZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5frontMxFNaNbNdNiNfZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6__initZ@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opIndexMxFNaNbNiNfmZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opSliceMFNaNbNiNfZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opSliceMFNaNbNiNfmmZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7popBackMFNaNbNiNfZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed85__T8opEqualsTxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZ8opEqualsMxFNaNbNiNfKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed8opDollarMxFNaNbNiNfZm@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3uni41__T16sliceOverIndexedTS3std3uni8GraphemeZ16sliceOverIndexedFNaNbNiNfmmPS3std3uni8GraphemeZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni4icmpFNaNfAxaAxaZi@Base 6
+ _D3std3uni4icmpFNaNfAxuAxuZi@Base 6
+ _D3std3uni4icmpFNaNfAxwAxwZi@Base 6
+ _D3std3uni51__T10assumeSizeS28_D3std3uni5low_8FNaNbNiNfkZkVmi8Z10assumeSize6__initZ@Base 6
+ _D3std3uni52__T10sharMethodS333std3uni23switchUniformLowerBoundZ37__T10sharMethodVAyaa4_613c3d62TAxkTkZ10sharMethodFNaNbNiNfAxkkZm@Base 6
+ _D3std3uni54__T10assumeSizeS31_D3std3uni8midlow_8FNaNbNiNfkZkVmi8Z10assumeSize6__initZ@Base 6
+ _D3std3uni54__T5forceTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni20__T9BitPackedTkVmi7Z9BitPacked@Base 6
+ _D3std3uni54__T5forceTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni20__T9BitPackedTkVmi8Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni21__T9BitPackedTkVmi11Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni21__T9BitPackedTkVmi12Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni21__T9BitPackedTkVmi13Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni21__T9BitPackedTkVmi14Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni21__T9BitPackedTkVmi15Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTmZ5forceFNaNbNiNfmZS3std3uni21__T9BitPackedTkVmi16Z9BitPacked@Base 6
+ _D3std3uni5asSetFNaNfAxhZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni5low_8FNaNbNiNfkZk@Base 6
+ _D3std3uni5sicmpFNaNfAxaAxaZi@Base 6
+ _D3std3uni5sicmpFNaNfAxuAxuZi@Base 6
+ _D3std3uni5sicmpFNaNfAxwAxwZi@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArrayKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray12__T3ptrVmi0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray12__T3ptrVmi1Z3ptrMNgFNaNbNdNiZNgS3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray14__T5sliceVmi0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray14__T5sliceVmi1Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray15__T6lengthVmi0Z6lengthMFNaNbNdmZv@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray15__T6lengthVmi0Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray15__T6lengthVmi1Z6lengthMFNaNbNdNfmZv@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray15__T6lengthVmi1Z6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi0Z7raw_ptrMNgFNaNbNdNiNfZPNgm@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray16__T7raw_ptrVmi1Z7raw_ptrMNgFNaNbNdNiZPNgm@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAmXS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxmAxmAxmZxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArrayZm@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedZ15packedArrayViewFNaNbNiNePNgmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTbVmi1Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl11simpleWriteMFNaNbNiNebmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVmi1Z9BitPackedmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl13opIndexAssignMFNaNbNiNebmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTbVmi1Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTkVmi7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi7Z9BitPackedmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTkVmi7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTkVmi8Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTkVmi8Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi11Z9BitPackedmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi12Z9BitPackedmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi13Z9BitPackedmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi14Z9BitPackedmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi15Z9BitPackedmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi16Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi16Z9BitPackedmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgmZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z13PackedPtrImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi16Z9BitPacked@Base 6
+ _D3std3uni6hangLVFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6hangLVFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6isMarkFNaNbNiNfwZb@Base 6
+ _D3std3uni6mcTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6mcTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6read24FNaNbNiNfxPhmZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl117__T8opEqualsTS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVmi1Z9BitPackedmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNebmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVmi1Z9BitPackedmmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNebmmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTbVmi1Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi7Z9BitPackedmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi7Z9BitPackedmmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTkVmi7Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVmi8Z9BitPackedmmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni20__T9BitPackedTkVmi8Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedVmi8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi11Z9BitPackedmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi11Z9BitPackedmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi11Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi12Z9BitPackedmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi12Z9BitPackedmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi12Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi13Z9BitPackedmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi13Z9BitPackedmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi13Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi14Z9BitPackedmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi14Z9BitPackedmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi14Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi15Z9BitPackedmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi15Z9BitPackedmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi15Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi16Z9BitPackedmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVmi16Z9BitPackedmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekmmZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNemZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl5zerosMFNaNbNiNemmZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgmmmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNemZS3std3uni21__T9BitPackedTkVmi16Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNemmZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedVmi16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni78__T14genericReplaceTvTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayTAiZ14genericReplaceFNaNbNeKS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraymmAiZm@Base 6
+ _D3std3uni78__T14genericReplaceTvTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayTAkZ14genericReplaceFNaNbNeKS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraymmAkZm@Base 6
+ _D3std3uni7composeFNaNbNewwZw@Base 6
+ _D3std3uni7hangLVTFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni7hangLVTFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni7isAlphaFNaNbNiNfwZb@Base 6
+ _D3std3uni7isJamoLFNaNbNiNewZb@Base 6
+ _D3std3uni7isJamoTFNaNbNiNewZb@Base 6
+ _D3std3uni7isJamoVFNaNbNiNewZb@Base 6
+ _D3std3uni7isLowerFNaNbNiNfwZb@Base 6
+ _D3std3uni7isSpaceFNaNbNiNfwZb@Base 6
+ _D3std3uni7isUpperFNaNbNiNfwZb@Base 6
+ _D3std3uni7isWhiteFNaNbNiNfwZb@Base 6
+ _D3std3uni7toLowerFNaNbNiNfwZw@Base 6
+ _D3std3uni7toLowerFNaNfAyaZAya@Base 6
+ _D3std3uni7toLowerFNaNfAyuZAyu@Base 6
+ _D3std3uni7toLowerFNaNfAywZAyw@Base 6
+ _D3std3uni7toUpperFNaNbNiNfwZw@Base 6
+ _D3std3uni7toUpperFNaNfAyaZAya@Base 6
+ _D3std3uni7toUpperFNaNfAyuZAyu@Base 6
+ _D3std3uni7toUpperFNaNfAywZAyw@Base 6
+ _D3std3uni7unicode13__T6opCallTaZ6opCallFNaNfxAaZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode18hangulSyllableType6__initZ@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4c43Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d63Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d65Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d6eZ10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4e64Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_5063Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode44__T10opDispatchVAyaa10_416c7068616265746963Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode46__T10opDispatchVAyaa11_57686974655f5370616365Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode5block6__initZ@Base 6
+ _D3std3uni7unicode6__initZ@Base 6
+ _D3std3uni7unicode6script6__initZ@Base 6
+ _D3std3uni7unicode79__T7loadAnyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ7loadAnyFNaNfxAaZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode7findAnyFNfAyaZb@Base 6
+ _D3std3uni7write24FNaNbNiNfPhkmZv@Base 6
+ _D3std3uni85__T12loadPropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ12loadPropertyFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni8GcPolicy12__T5allocTkZ5allocFNaNbNemZAk@Base 6
+ _D3std3uni8GcPolicy14__T7reallocTkZ7reallocFNaNbNeAkmZAk@Base 6
+ _D3std3uni8GcPolicy15__T6appendTkTiZ6appendFNaNbNeKAkiZv@Base 6
+ _D3std3uni8GcPolicy15__T7destroyTAkZ7destroyFNaNbNiNeKAkZv@Base 6
+ _D3std3uni8GcPolicy6__initZ@Base 6
+ _D3std3uni8Grapheme10__postblitMFNeZv@Base 6
+ _D3std3uni8Grapheme11smallLengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni8Grapheme12convertToBigMFNeZv@Base 6
+ _D3std3uni8Grapheme13__T6__ctorTiZ6__ctorMFNcNexAiXS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme13__T6__ctorTwZ6__ctorMFNcNexAwXS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme13opIndexAssignMFNaNbNiNewmZv@Base 6
+ _D3std3uni8Grapheme25__T10opOpAssignVAyaa1_7eZ10opOpAssignMFNcNewZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxiZ10opOpAssignMFNcNeAxiZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxwZ10opOpAssignMFNcNeAxwZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme5isBigMxFNaNbNdNiNeZh@Base 6
+ _D3std3uni8Grapheme6__dtorMFNeZv@Base 6
+ _D3std3uni8Grapheme6__initZ@Base 6
+ _D3std3uni8Grapheme6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni8Grapheme6setBigMFNaNbNiNeZv@Base 6
+ _D3std3uni8Grapheme7opIndexMxFNaNbNiNemZw@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNiZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNimmZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme8opAssignMFNcNjNeS3std3uni8GraphemeZS3std3uni8Grapheme@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAamwZm@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAwmwZm@Base 6
+ _D3std3uni8encodeToFNaNeAumwZm@Base 6
+ _D3std3uni8isFormatFNaNbNiNfwZb@Base 6
+ _D3std3uni8isNumberFNaNbNiNfwZb@Base 6
+ _D3std3uni8isSymbolFNaNbNiNfwZb@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8midlow_8FNaNbNiNfkZk@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVmi7Z9BitPackedZS3std3uni20__T9BitPackedTkVmi7Z9BitPacked@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZS3std3uni20__T9BitPackedTkVmi8Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi11Z9BitPackedZS3std3uni21__T9BitPackedTkVmi11Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi12Z9BitPackedZS3std3uni21__T9BitPackedTkVmi12Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi13Z9BitPackedZS3std3uni21__T9BitPackedTkVmi13Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi14Z9BitPackedZS3std3uni21__T9BitPackedTkVmi14Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZS3std3uni21__T9BitPackedTkVmi15Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi16Z9BitPackedZS3std3uni21__T9BitPackedTkVmi16Z9BitPacked@Base 6
+ _D3std3uni97__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAaZ6toCaseFNaNeAaZAa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAxaZ6toCaseFNaNeAxaZAxa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9isControlFNaNbNiNfwZb@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9recomposeFNaNbNemAwAhZm@Base 6
+ _D3std3uri10URI_EncodeFAywkZAya@Base 6
+ _D3std3uri12URIException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std3uri12URIException@Base 6
+ _D3std3uri12URIException6__initZ@Base 6
+ _D3std3uri12URIException6__vtblZ@Base 6
+ _D3std3uri12URIException7__ClassZ@Base 6
+ _D3std3uri12__ModuleInfoZ@Base 6
+ _D3std3uri18_sharedStaticCtor1FZ6helperFyAakZv@Base 6
+ _D3std3uri18_sharedStaticCtor1FZv@Base 6
+ _D3std3uri9ascii2hexFwZk@Base 6
+ _D3std3uri9hex2asciiyG16a@Base 6
+ _D3std3uri9uri_flagsG128h@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNeKAyaJmZw@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNfKAyaZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFKAaKmZ17__T9exceptionTAaZ9exceptionFNaNfAaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFNaKAaKmZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ10decodeImplFNaKAuKmZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ10decodeImplFNaKAwKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFKAxaKmZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFNaKAxaKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ10decodeImplFNaKAxuKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ10decodeImplFNaKAxwKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFKAyaKmZ18__T9exceptionTAyaZ9exceptionFNaNfAyaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFNaKAyaKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFKxAaKmZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFNaKxAaKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ10decodeImplFNaKxAuKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ10decodeImplFNaKxAwKmZw@Base 6
+ _D3std3utf10strideImplFNaNeamZk@Base 6
+ _D3std3utf12UTFException11setSequenceMFNaNbNiNfAkXC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNfAyamAyamC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__initZ@Base 6
+ _D3std3utf12UTFException6__vtblZ@Base 6
+ _D3std3utf12UTFException7__ClassZ@Base 6
+ _D3std3utf12UTFException8toStringMFZAya@Base 6
+ _D3std3utf12__ModuleInfoZ@Base 6
+ _D3std3utf12isValidDcharFNaNbNiNfwZb@Base 6
+ _D3std3utf14__T6byCharTAaZ6byCharFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf14__T6strideTAaZ6strideFNaNfAaZk@Base 6
+ _D3std3utf14__T6toUTFzTPaZ15__T6toUTFzTAyaZ6toUTFzFNaNbNfAyaZPa@Base 6
+ _D3std3utf15__T6byCharTAxaZ6byCharFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6byCharTAyaZ6byCharFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfAxamZk@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfKAxamZk@Base 6
+ _D3std3utf15__T6strideTAyaZ6strideFNaNfKAyamZk@Base 6
+ _D3std3utf16__T7byDcharTAyaZ7byDcharFNaNbNiNfAyaZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf17__T8validateTAxaZ8validateFNaNfxAaZv@Base 6
+ _D3std3utf17__T8validateTAxuZ8validateFNaNfxAuZv@Base 6
+ _D3std3utf17__T8validateTAxwZ8validateFNaNfxAwZv@Base 6
+ _D3std3utf18__T10codeLengthTaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTuZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTwZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10toUCSindexTaZ10toUCSindexFNaNfAxamZm@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfmZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfmmZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZm@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10codeLengthTyaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfmZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfmmZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfmZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfmmZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10strideBackTAxaZ10strideBackFNaNfKAxamZk@Base 6
+ _D3std3utf20__T10strideBackTAyaZ10strideBackFNaNfKAyamZk@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAxaZ10toUTFzImplFNaNbNfAxaZPa@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAyaZ10toUTFzImplFNaNbNfAyaZPa@Base 6
+ _D3std3utf28__T20canSearchInCodeUnitsTaZ20canSearchInCodeUnitsFNaNbNiNfwZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNaNbNiNfS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl11__xopEqualsFKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl4saveMFNaNbNdNiNfZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl5frontMFNaNbNdNiNfZa@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl6__ctorMFNaNbNcNiNfKS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl6__initZ@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl9__xtoHashFNbNeKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplZm@Base 6
+ _D3std3utf6encodeFNaNfKAawZv@Base 6
+ _D3std3utf6encodeFNaNfKAuwZv@Base 6
+ _D3std3utf6encodeFNaNfKAwwZv@Base 6
+ _D3std3utf6encodeFNaNfKG2uwZm@Base 6
+ _D3std3utf6encodeFNaNfKG4awZm@Base 6
+ _D3std3utf6toUTF8FNaNbNiNfNkJG4awZAa@Base 6
+ _D3std3utf6toUTF8FNaNfxAaZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAuZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAwZAya@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl11__xopEqualsFKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl4saveMFNaNbNdNiNfZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5frontMFNaNbNdNiNfZw@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__ctorMFNaNbNcNiNfKS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl9__xtoHashFNbNeKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZm@Base 6
+ _D3std3utf7toUTF16FNaNbNiNfNkKG2uwZAu@Base 6
+ _D3std3utf7toUTF16FNaNfxAaZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAuZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAwZAyu@Base 6
+ _D3std3utf7toUTF32FNaNfxAaZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAuZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAwZAyw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ6decodeFNaNeKAaKmZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ6decodeFNaNeKAuKmZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ6decodeFNaNeKAwKmZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ6decodeFNaNeKAxaKmZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ6decodeFNaNeKAxuKmZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ6decodeFNaNeKAxwKmZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ6decodeFNaNeKAyaKmZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ6decodeFNaNeKxAaKmZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ6decodeFNaNeKxAuKmZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ6decodeFNaNeKxAwKmZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNeKAaJmZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNfKAaZw@Base 6
+ _D3std3xml10DigitTableyAi@Base 6
+ _D3std3xml10checkCharsFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkCharsFKAyaZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZv@Base 6
+ _D3std3xml10isBaseCharFwZb@Base 6
+ _D3std3xml10isExtenderFwZb@Base 6
+ _D3std3xml111__T4starS99_D3std3xml76__T3seqS29_D3std3xml10checkSpaceFKAyaZvS33_D3std3xml14checkAttributeFKAyaZvZ3seqFKAyaZvZ4starFKAyaZv@Base 6
+ _D3std3xml112__T3seqS35_D3std3xml16checkDocTypeDeclFKAyaZvS63_D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZvZ3seqFKAyaZv@Base 6
+ _D3std3xml11PIException6__ctorMFAyaZC3std3xml11PIException@Base 6
+ _D3std3xml11PIException6__initZ@Base 6
+ _D3std3xml11PIException6__vtblZ@Base 6
+ _D3std3xml11PIException7__ClassZ@Base 6
+ _D3std3xml11XIException6__ctorMFAyaZC3std3xml11XIException@Base 6
+ _D3std3xml11XIException6__initZ@Base 6
+ _D3std3xml11XIException6__vtblZ@Base 6
+ _D3std3xml11XIException7__ClassZ@Base 6
+ _D3std3xml11checkCDSectFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkCDSectFKAyaZv@Base 6
+ _D3std3xml11checkPrologFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkPrologFKAyaZv@Base 6
+ _D3std3xml11checkSDDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkSDDeclFKAyaZv@Base 6
+ _D3std3xml12TagException6__ctorMFAyaZC3std3xml12TagException@Base 6
+ _D3std3xml12TagException6__initZ@Base 6
+ _D3std3xml12TagException6__vtblZ@Base 6
+ _D3std3xml12TagException7__ClassZ@Base 6
+ _D3std3xml12XMLException6__ctorMFAyaZC3std3xml12XMLException@Base 6
+ _D3std3xml12XMLException6__initZ@Base 6
+ _D3std3xml12XMLException6__vtblZ@Base 6
+ _D3std3xml12XMLException7__ClassZ@Base 6
+ _D3std3xml12__ModuleInfoZ@Base 6
+ _D3std3xml12checkCharRefFKAyaJwZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkCharRefFKAyaJwZv@Base 6
+ _D3std3xml12checkCommentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkCommentFKAyaZv@Base 6
+ _D3std3xml12checkContentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkContentFKAyaZv@Base 6
+ _D3std3xml12checkElementFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkElementFKAyaZv@Base 6
+ _D3std3xml12checkEncNameFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkEncNameFKAyaZv@Base 6
+ _D3std3xml12checkLiteralFAyaKAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkLiteralFAyaKAyaZv@Base 6
+ _D3std3xml12checkXMLDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkXMLDeclFKAyaZv@Base 6
+ _D3std3xml13BaseCharTableyAi@Base 6
+ _D3std3xml13ElementParser3tagMxFNdZxC3std3xml3Tag@Base 6
+ _D3std3xml13ElementParser4onPIMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser4onXIMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser5parseMFZv@Base 6
+ _D3std3xml13ElementParser6__ctorMFC3std3xml13ElementParserZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__ctorMFC3std3xml3TagPAyaZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__ctorMFZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__initZ@Base 6
+ _D3std3xml13ElementParser6__vtblZ@Base 6
+ _D3std3xml13ElementParser6onTextMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser7__ClassZ@Base 6
+ _D3std3xml13ElementParser7onCDataMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser8toStringMxFZAya@Base 6
+ _D3std3xml13ElementParser9onCommentMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser9onTextRawMFDFAyaZvZv@Base 6
+ _D3std3xml13ExtenderTableyAi@Base 6
+ _D3std3xml13TextException6__ctorMFAyaZC3std3xml13TextException@Base 6
+ _D3std3xml13TextException6__initZ@Base 6
+ _D3std3xml13TextException6__vtblZ@Base 6
+ _D3std3xml13TextException7__ClassZ@Base 6
+ _D3std3xml13checkAttValueFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkAttValueFKAyaZv@Base 6
+ _D3std3xml13checkCharDataFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkCharDataFKAyaZv@Base 6
+ _D3std3xml13checkDocumentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkDocumentFKAyaZv@Base 6
+ _D3std3xml13isIdeographicFwZb@Base 6
+ _D3std3xml148__T3optS136_D3std3xml112__T3seqS35_D3std3xml16checkDocTypeDeclFKAyaZvS63_D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZvZ3seqFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml14CDataException6__ctorMFAyaZC3std3xml14CDataException@Base 6
+ _D3std3xml14CDataException6__initZ@Base 6
+ _D3std3xml14CDataException6__vtblZ@Base 6
+ _D3std3xml14CDataException7__ClassZ@Base 6
+ _D3std3xml14CheckException6__ctorMFAyaAyaC3std3xml14CheckExceptionZC3std3xml14CheckException@Base 6
+ _D3std3xml14CheckException6__initZ@Base 6
+ _D3std3xml14CheckException6__vtblZ@Base 6
+ _D3std3xml14CheckException7__ClassZ@Base 6
+ _D3std3xml14CheckException8completeMFAyaZv@Base 6
+ _D3std3xml14CheckException8toStringMxFZAya@Base 6
+ _D3std3xml14DocumentParser6__ctorMFAyaZC3std3xml14DocumentParser@Base 6
+ _D3std3xml14DocumentParser6__initZ@Base 6
+ _D3std3xml14DocumentParser6__vtblZ@Base 6
+ _D3std3xml14DocumentParser7__ClassZ@Base 6
+ _D3std3xml14XMLInstruction10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml14XMLInstruction5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml14XMLInstruction6__ctorMFAyaZC3std3xml14XMLInstruction@Base 6
+ _D3std3xml14XMLInstruction6__initZ@Base 6
+ _D3std3xml14XMLInstruction6__vtblZ@Base 6
+ _D3std3xml14XMLInstruction6toHashMxFNbNfZm@Base 6
+ _D3std3xml14XMLInstruction7__ClassZ@Base 6
+ _D3std3xml14XMLInstruction8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml14XMLInstruction8toStringMxFZAya@Base 6
+ _D3std3xml14checkAttributeFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkAttributeFKAyaZv@Base 6
+ _D3std3xml14checkEntityRefFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkEntityRefFKAyaZv@Base 6
+ _D3std3xml14checkReferenceFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkReferenceFKAyaZv@Base 6
+ _D3std3xml15DecodeException6__ctorMFAyaZC3std3xml15DecodeException@Base 6
+ _D3std3xml15DecodeException6__initZ@Base 6
+ _D3std3xml15DecodeException6__vtblZ@Base 6
+ _D3std3xml15DecodeException7__ClassZ@Base 6
+ _D3std3xml15__T6encodeTAyaZ6encodeFNaNbNfAyaZAya@Base 6
+ _D3std3xml15checkVersionNumFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml15checkVersionNumFKAyaZv@Base 6
+ _D3std3xml15isCombiningCharFwZb@Base 6
+ _D3std3xml16CommentException6__ctorMFAyaZC3std3xml16CommentException@Base 6
+ _D3std3xml16CommentException6__initZ@Base 6
+ _D3std3xml16CommentException6__vtblZ@Base 6
+ _D3std3xml16CommentException7__ClassZ@Base 6
+ _D3std3xml16IdeographicTableyAi@Base 6
+ _D3std3xml16checkDocTypeDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml16checkDocTypeDeclFKAyaZv@Base 6
+ _D3std3xml16checkVersionInfoFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml16checkVersionInfoFKAyaZv@Base 6
+ _D3std3xml17checkEncodingDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml17checkEncodingDeclFKAyaZv@Base 6
+ _D3std3xml18CombiningCharTableyAi@Base 6
+ _D3std3xml20InvalidTypeException6__ctorMFAyaZC3std3xml20InvalidTypeException@Base 6
+ _D3std3xml20InvalidTypeException6__initZ@Base 6
+ _D3std3xml20InvalidTypeException6__vtblZ@Base 6
+ _D3std3xml20InvalidTypeException7__ClassZ@Base 6
+ _D3std3xml21ProcessingInstruction10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml21ProcessingInstruction5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml21ProcessingInstruction6__ctorMFAyaZC3std3xml21ProcessingInstruction@Base 6
+ _D3std3xml21ProcessingInstruction6__initZ@Base 6
+ _D3std3xml21ProcessingInstruction6__vtblZ@Base 6
+ _D3std3xml21ProcessingInstruction6toHashMxFNbNfZm@Base 6
+ _D3std3xml21ProcessingInstruction7__ClassZ@Base 6
+ _D3std3xml21ProcessingInstruction8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml21ProcessingInstruction8toStringMxFZAya@Base 6
+ _D3std3xml26__T6toTypeTxC3std3xml3TagZ6toTypeFC6ObjectZxC3std3xml3Tag@Base 6
+ _D3std3xml27__T6toTypeTxC3std3xml4ItemZ6toTypeFC6ObjectZxC3std3xml4Item@Base 6
+ _D3std3xml30__T6toTypeTxC3std3xml7ElementZ6toTypeFC6ObjectZxC3std3xml7Element@Base 6
+ _D3std3xml31__T6toTypeTxC3std3xml8DocumentZ6toTypeFC6ObjectZxC3std3xml8Document@Base 6
+ _D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZv@Base 6
+ _D3std3xml3Tag11__invariantMxFZv@Base 6
+ _D3std3xml3Tag11toEndStringMxFZAya@Base 6
+ _D3std3xml3Tag12__invariant6MxFZv@Base 6
+ _D3std3xml3Tag13toEmptyStringMxFZAya@Base 6
+ _D3std3xml3Tag13toStartStringMxFZAya@Base 6
+ _D3std3xml3Tag14toNonEndStringMxFZAya@Base 6
+ _D3std3xml3Tag5isEndMxFNdZb@Base 6
+ _D3std3xml3Tag5opCmpMxFC6ObjectZi@Base 6
+ _D3std3xml3Tag6__ctorMFAyaE3std3xml7TagTypeZC3std3xml3Tag@Base 6
+ _D3std3xml3Tag6__ctorMFKAyabZC3std3xml3Tag@Base 6
+ _D3std3xml3Tag6__initZ@Base 6
+ _D3std3xml3Tag6__vtblZ@Base 6
+ _D3std3xml3Tag6toHashMxFNbNfZm@Base 6
+ _D3std3xml3Tag7__ClassZ@Base 6
+ _D3std3xml3Tag7isEmptyMxFNdZb@Base 6
+ _D3std3xml3Tag7isStartMxFNdZb@Base 6
+ _D3std3xml3Tag8opEqualsMxFC6ObjectZb@Base 6
+ _D3std3xml3Tag8toStringMxFZAya@Base 6
+ _D3std3xml40__T3optS29_D3std3xml10checkSpaceFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml41__T3optS30_D3std3xml11checkSDDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml42__T3optS31_D3std3xml12checkXMLDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml45__T6quotedS31_D3std3xml12checkEncNameFKAyaZvZ6quotedFKAyaZv@Base 6
+ _D3std3xml47__T3optS36_D3std3xml17checkEncodingDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml48__T6quotedS34_D3std3xml15checkVersionNumFKAyaZvZ6quotedFKAyaZv@Base 6
+ _D3std3xml4Item6__initZ@Base 6
+ _D3std3xml4Item6__vtblZ@Base 6
+ _D3std3xml4Item6prettyMxFkZAAya@Base 6
+ _D3std3xml4Item7__ClassZ@Base 6
+ _D3std3xml4Text10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml4Text5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml4Text6__ctorMFAyaZC3std3xml4Text@Base 6
+ _D3std3xml4Text6__initZ@Base 6
+ _D3std3xml4Text6__vtblZ@Base 6
+ _D3std3xml4Text6toHashMxFNbNfZm@Base 6
+ _D3std3xml4Text7__ClassZ@Base 6
+ _D3std3xml4Text8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml4Text8toStringMxFZAya@Base 6
+ _D3std3xml4chopFKAyamZAya@Base 6
+ _D3std3xml4exitFAyaZv@Base 6
+ _D3std3xml4hashFNbNeAyamZm@Base 6
+ _D3std3xml4optcFKAyaaZb@Base 6
+ _D3std3xml4reqcFKAyaaZv@Base 6
+ _D3std3xml5CData10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml5CData5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml5CData6__ctorMFAyaZC3std3xml5CData@Base 6
+ _D3std3xml5CData6__initZ@Base 6
+ _D3std3xml5CData6__vtblZ@Base 6
+ _D3std3xml5CData6toHashMxFNbNfZm@Base 6
+ _D3std3xml5CData7__ClassZ@Base 6
+ _D3std3xml5CData8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml5CData8toStringMxFZAya@Base 6
+ _D3std3xml5checkFAyaZv@Base 6
+ _D3std3xml6decodeFAyaE3std3xml10DecodeModeZAya@Base 6
+ _D3std3xml6isCharFwZb@Base 6
+ _D3std3xml6lookupFAxiiZb@Base 6
+ _D3std3xml76__T3seqS29_D3std3xml10checkSpaceFKAyaZvS33_D3std3xml14checkAttributeFKAyaZvZ3seqFKAyaZv@Base 6
+ _D3std3xml7Comment10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml7Comment5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml7Comment6__ctorMFAyaZC3std3xml7Comment@Base 6
+ _D3std3xml7Comment6__initZ@Base 6
+ _D3std3xml7Comment6__vtblZ@Base 6
+ _D3std3xml7Comment6toHashMxFNbNfZm@Base 6
+ _D3std3xml7Comment7__ClassZ@Base 6
+ _D3std3xml7Comment8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml7Comment8toStringMxFZAya@Base 6
+ _D3std3xml7Element10appendItemMFC3std3xml4ItemZv@Base 6
+ _D3std3xml7Element10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml21ProcessingInstructionZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml4TextZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml5CDataZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml7CommentZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml7ElementZv@Base 6
+ _D3std3xml7Element4textMxFE3std3xml10DecodeModeZAya@Base 6
+ _D3std3xml7Element5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml7Element5parseMFC3std3xml13ElementParserZv@Base 6
+ _D3std3xml7Element6__ctorMFAyaAyaZC3std3xml7Element@Base 6
+ _D3std3xml7Element6__ctorMFxC3std3xml3TagZC3std3xml7Element@Base 6
+ _D3std3xml7Element6__initZ@Base 6
+ _D3std3xml7Element6__vtblZ@Base 6
+ _D3std3xml7Element6prettyMxFkZAAya@Base 6
+ _D3std3xml7Element6toHashMxFNbNfZm@Base 6
+ _D3std3xml7Element7__ClassZ@Base 6
+ _D3std3xml7Element8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml7Element8toStringMxFZAya@Base 6
+ _D3std3xml7checkEqFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml7checkEqFKAyaZv@Base 6
+ _D3std3xml7checkPIFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml7checkPIFKAyaZv@Base 6
+ _D3std3xml7isDigitFwZb@Base 6
+ _D3std3xml7isSpaceFwZb@Base 6
+ _D3std3xml7startOfFAyaZAya@Base 6
+ _D3std3xml8Document5opCmpMxFC6ObjectZi@Base 6
+ _D3std3xml8Document6__ctorMFAyaZC3std3xml8Document@Base 6
+ _D3std3xml8Document6__ctorMFxC3std3xml3TagZC3std3xml8Document@Base 6
+ _D3std3xml8Document6__initZ@Base 6
+ _D3std3xml8Document6__vtblZ@Base 6
+ _D3std3xml8Document6toHashMxFNbNeZm@Base 6
+ _D3std3xml8Document7__ClassZ@Base 6
+ _D3std3xml8Document8opEqualsMxFC6ObjectZb@Base 6
+ _D3std3xml8Document8toStringMxFZAya@Base 6
+ _D3std3xml8checkEndFAyaKAyaZv@Base 6
+ _D3std3xml8checkTagFKAyaJAyaJAyaZ8__mixin44failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml8checkTagFKAyaJAyaJAyaZv@Base 6
+ _D3std3xml8isLetterFwZb@Base 6
+ _D3std3xml9CharTableyAi@Base 6
+ _D3std3xml9checkETagFKAyaJAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkETagFKAyaJAyaZv@Base 6
+ _D3std3xml9checkMiscFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkMiscFKAyaZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZ8__mixin34failMFZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZv@Base 6
+ _D3std3zip10ZipArchive10diskNumberMFNdZk@Base 6
+ _D3std3zip10ZipArchive10numEntriesMFNdZk@Base 6
+ _D3std3zip10ZipArchive12deleteMemberMFC3std3zip13ArchiveMemberZv@Base 6
+ _D3std3zip10ZipArchive12diskStartDirMFNdZk@Base 6
+ _D3std3zip10ZipArchive12eocd64Lengthxi@Base 6
+ _D3std3zip10ZipArchive12totalEntriesMFNdZk@Base 6
+ _D3std3zip10ZipArchive14digiSignLengthxi@Base 6
+ _D3std3zip10ZipArchive15eocd64LocLengthxi@Base 6
+ _D3std3zip10ZipArchive19zip64ExtractVersionxt@Base 6
+ _D3std3zip10ZipArchive4dataMFNdZAh@Base 6
+ _D3std3zip10ZipArchive5buildMFZAv@Base 6
+ _D3std3zip10ZipArchive6__ctorMFAvZC3std3zip10ZipArchive@Base 6
+ _D3std3zip10ZipArchive6__ctorMFZC3std3zip10ZipArchive@Base 6
+ _D3std3zip10ZipArchive6__initZ@Base 6
+ _D3std3zip10ZipArchive6__vtblZ@Base 6
+ _D3std3zip10ZipArchive6expandMFC3std3zip13ArchiveMemberZAh@Base 6
+ _D3std3zip10ZipArchive7__ClassZ@Base 6
+ _D3std3zip10ZipArchive7getUintMFiZk@Base 6
+ _D3std3zip10ZipArchive7isZip64MFNdZb@Base 6
+ _D3std3zip10ZipArchive7isZip64MFNdbZv@Base 6
+ _D3std3zip10ZipArchive7putUintMFikZv@Base 6
+ _D3std3zip10ZipArchive8getUlongMFiZm@Base 6
+ _D3std3zip10ZipArchive8putUlongMFimZv@Base 6
+ _D3std3zip10ZipArchive9addMemberMFC3std3zip13ArchiveMemberZv@Base 6
+ _D3std3zip10ZipArchive9directoryMFNdZHAyaC3std3zip13ArchiveMember@Base 6
+ _D3std3zip10ZipArchive9getUshortMFiZt@Base 6
+ _D3std3zip10ZipArchive9putUshortMFitZv@Base 6
+ _D3std3zip12ZipException6__ctorMFAyaZC3std3zip12ZipException@Base 6
+ _D3std3zip12ZipException6__initZ@Base 6
+ _D3std3zip12ZipException6__vtblZ@Base 6
+ _D3std3zip12ZipException7__ClassZ@Base 6
+ _D3std3zip12__ModuleInfoZ@Base 6
+ _D3std3zip13ArchiveMember10diskNumberMFNdZt@Base 6
+ _D3std3zip13ArchiveMember11madeVersionMNgFNaNbNcNdNfZNgt@Base 6
+ _D3std3zip13ArchiveMember12expandedDataMFNdAhZv@Base 6
+ _D3std3zip13ArchiveMember12expandedDataMFNdZAh@Base 6
+ _D3std3zip13ArchiveMember12expandedSizeMFNdZk@Base 6
+ _D3std3zip13ArchiveMember14compressedDataMFNdZAh@Base 6
+ _D3std3zip13ArchiveMember14compressedSizeMFNdZk@Base 6
+ _D3std3zip13ArchiveMember14extractVersionMFNdZt@Base 6
+ _D3std3zip13ArchiveMember14fileAttributesMFNdkZv@Base 6
+ _D3std3zip13ArchiveMember14fileAttributesMxFNdZk@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdE3std3zip17CompressionMethodZv@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdZE3std3zip17CompressionMethod@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdtZv@Base 6
+ _D3std3zip13ArchiveMember18externalAttributesMNgFNaNbNcNdNfZNgk@Base 6
+ _D3std3zip13ArchiveMember4timeMFNdS3std8datetime7SysTimeZv@Base 6
+ _D3std3zip13ArchiveMember4timeMFNdkZv@Base 6
+ _D3std3zip13ArchiveMember4timeMxFNdZk@Base 6
+ _D3std3zip13ArchiveMember5crc32MFNdZk@Base 6
+ _D3std3zip13ArchiveMember6__initZ@Base 6
+ _D3std3zip13ArchiveMember6__vtblZ@Base 6
+ _D3std3zip13ArchiveMember7__ClassZ@Base 6
+ _D3std4conv103__T7emplaceTC3std12experimental6logger4core16StdForwardLoggerTE3std12experimental6logger4core8LogLevelZ7emplaceFAvE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core16StdForwardLogger@Base 6
+ _D3std4conv104__T8textImplTAyaTAyaTPvTAyaTiTAyaTiTAyaTaTAyaThTAyaThTAyaTbTAyaTbTAyaTbTAyaTbTAyaTbTAyaTAxaTAyaTAxaTAyaZ8textImplFNaNfAyaPvAyaiAyaiAyaaAyahAyahAyabAyabAyabAyabAyabAyaAxaAyaAxaAyaZAya@Base 6
+ _D3std4conv10parseErrorFNaNfLAyaAyamZC3std4conv13ConvException@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTAaZ2toFNaNbNfAaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTPaZ2toFNaNbPaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTPvZ2toFNaNfPvZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxaZ2toFNaNfxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxdZ2toFNfxdZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxlZ2toFNaNbNfxlZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxmZ2toFNaNbNfxmZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTyhZ2toFNaNbNfyhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ114__T2toTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ2toFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAxaZ2toFNaNbNfAxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAyaZ2toFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAyhZ2toFNaNfAyhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTPxaZ2toFNaNbPxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTPxhZ2toFNaNfPxhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ30__T2toTS3std11concurrency3TidZ2toFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv11__T2toTAyaZ34__T2toTE3std5regex8internal2ir2IRZ2toFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv11__T2toTAyaZ34__T2toTE3std6socket12SocketOptionZ2toFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv11__T2toTAyaZ41__T2toTPS3std11parallelism12AbstractTaskZ2toFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv11__T2toTAyaZ42__T2toTC3std11concurrency14LinkTerminatedZ2toFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv11__T2toTAyaZ43__T2toTC3std11concurrency15OwnerTerminatedZ2toFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTaZ2toFNaNfaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTbZ2toFNaNbNiNfbZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toThZ2toFNaNbNfhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTiZ2toFNaNbNfiZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTkZ2toFNaNbNfkZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTmZ2toFNaNbNfmZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTtZ2toFNaNbNftZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTwZ2toFNaNfwZAya@Base 6
+ _D3std4conv121__T5toStrTAyaTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5toStrFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv121__T7emplaceTC3std12experimental6logger10filelogger10FileLoggerTS3std5stdio4FileTE3std12experimental6logger4core8LogLevelZ7emplaceFAvKS3std5stdio4FileE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std4conv122__T6toImplTAyaTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ6toImplFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv12__ModuleInfoZ@Base 6
+ _D3std4conv13ConvException6__ctorMFNaNbNfAyaAyamZC3std4conv13ConvException@Base 6
+ _D3std4conv13ConvException6__initZ@Base 6
+ _D3std4conv13ConvException6__vtblZ@Base 6
+ _D3std4conv13ConvException7__ClassZ@Base 6
+ _D3std4conv13__T4textTAyaZ4textFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv15__T4textTAyaTaZ4textFNaNfAyaaZAya@Base 6
+ _D3std4conv15__T6toImplTiThZ6toImplFNaNbNiNfhZi@Base 6
+ _D3std4conv15__T6toImplTiTiZ6toImplFNaNbNiNfiZi@Base 6
+ _D3std4conv15__T6toImplTiTkZ6toImplFNaNfkZi@Base 6
+ _D3std4conv15__T6toImplTiTmZ6toImplFNaNfmZi@Base 6
+ _D3std4conv15__T6toImplTiTmZ6toImplFmZ16__T9__lambda2TmZ9__lambda2FNaNbNiNeKmZi@Base 6
+ _D3std4conv15__T6toImplTiTsZ6toImplFNaNbNiNfsZi@Base 6
+ _D3std4conv15__T6toImplTiTtZ6toImplFNaNbNiNftZi@Base 6
+ _D3std4conv15__T6toImplTkTkZ6toImplFNaNbNiNfkZk@Base 6
+ _D3std4conv15__T6toImplTkTmZ6toImplFNaNfmZk@Base 6
+ _D3std4conv15__T6toImplTkTmZ6toImplFmZ16__T9__lambda2TmZ9__lambda2FNaNbNiNeKmZk@Base 6
+ _D3std4conv15__T6toImplTlTlZ6toImplFNaNbNiNflZl@Base 6
+ _D3std4conv15__T6toImplTlTmZ6toImplFNaNfmZl@Base 6
+ _D3std4conv15__T6toImplTmTkZ6toImplFNaNbNiNfkZm@Base 6
+ _D3std4conv15__T6toImplTmTmZ6toImplFNaNbNiNfmZm@Base 6
+ _D3std4conv15__T8unsignedThZ8unsignedFNaNbNiNfhZh@Base 6
+ _D3std4conv15__T8unsignedTiZ8unsignedFNaNbNiNfiZk@Base 6
+ _D3std4conv15__T8unsignedTkZ8unsignedFNaNbNiNfkZk@Base 6
+ _D3std4conv15__T8unsignedTmZ8unsignedFNaNbNiNfmZm@Base 6
+ _D3std4conv15__T8unsignedTtZ8unsignedFNaNbNiNftZt@Base 6
+ _D3std4conv16__T4textTAyaTxaZ4textFNaNfAyaxaZAya@Base 6
+ _D3std4conv16__T5parseThTAxaZ5parseFNaNfKAxaZh@Base 6
+ _D3std4conv16__T5parseThTAxaZ5parseFNaNfKAxakZh@Base 6
+ _D3std4conv16__T5parseTiTAxaZ5parseFNaNfKAxaZi@Base 6
+ _D3std4conv16__T5parseTkTAxaZ5parseFNaNfKAxaZk@Base 6
+ _D3std4conv16__T5parseTtTAxaZ5parseFNaNfKAxaZt@Base 6
+ _D3std4conv16__T5toStrTAyaTaZ5toStrFNaNfaZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTbZ5toStrFNaNbNiNfbZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTwZ5toStrFNaNfwZAya@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFNaNfxkZh@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFxkZ17__T9__lambda2TxkZ9__lambda2FNaNbNiNeKxkZh@Base 6
+ _D3std4conv16__T6toImplTiTxhZ6toImplFNaNbNiNfxhZi@Base 6
+ _D3std4conv16__T6toImplTiTxkZ6toImplFNaNfxkZi@Base 6
+ _D3std4conv16__T6toImplTiTxmZ6toImplFNaNfxmZi@Base 6
+ _D3std4conv16__T6toImplTiTxmZ6toImplFxmZ17__T9__lambda2TxmZ9__lambda2FNaNbNiNeKxmZi@Base 6
+ _D3std4conv16__T6toImplTiTxsZ6toImplFNaNbNiNfxsZi@Base 6
+ _D3std4conv16__T6toImplTiTykZ6toImplFNaNfykZi@Base 6
+ _D3std4conv16__T8unsignedTxlZ8unsignedFNaNbNiNfxlZm@Base 6
+ _D3std4conv16__T8unsignedTxmZ8unsignedFNaNbNiNfxmZm@Base 6
+ _D3std4conv16__T8unsignedTyhZ8unsignedFNaNbNiNfyhZh@Base 6
+ _D3std4conv16testEmplaceChunkFNaNbNiAvmmAyaZv@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ69__T11emplaceImplTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv17__T4textTAyaTAxaZ4textFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv17__T4textTAyaTAyaZ4textFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTPvZ5toStrFNaNfPvZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxaZ5toStrFNaNfxaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxdZ5toStrFNfxdZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTaZ6toImplFNaNfaZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTbZ6toImplFNaNbNiNfbZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNehkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNfhZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNeikE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNfiZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNekkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNfkZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTmZ6toImplFNaNbNemkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTmZ6toImplFNaNbNfmZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNetkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNftZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTwZ6toImplFNaNfwZAya@Base 6
+ _D3std4conv17__T6toImplTtTAxaZ6toImplFNaNfAxaZt@Base 6
+ _D3std4conv181__T18emplaceInitializerTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ18emplaceInitializerFNaNbNcNiNeKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv18__T5toStrTAyaTAyhZ5toStrFNaNfAyhZAya@Base 6
+ _D3std4conv18__T5toStrTAyaTPxhZ5toStrFNaNfPxhZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTAaZ6toImplFNaNbNfAaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPaZ6toImplFNaNbPaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPvZ6toImplFNaNfPvZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxaZ6toImplFNaNfxaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxdZ6toImplFNfxdZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNexlkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNfxlZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNexmkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNfxmZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNeyhkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNfyhZAya@Base 6
+ _D3std4conv19__T11emplaceImplTaZ19__T11emplaceImplTaZ11emplaceImplFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv19__T11emplaceImplThZ19__T11emplaceImplThZ11emplaceImplFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv19__T11emplaceImplTwZ19__T11emplaceImplTwZ11emplaceImplFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv19__T4textTAyaTAyaTmZ4textFNaNbNfAyaAyamZAya@Base 6
+ _D3std4conv19__T4textTAyaTmTAyaZ4textFNaNbNfAyamAyaZAya@Base 6
+ _D3std4conv19__T4textTAyaTwTAyaZ4textFNaNfAyawAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAxaZ6toImplFNaNbNfAxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyaZ6toImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyhZ6toImplFNaNfAyhZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxaZ6toImplFNaNbPxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxhZ6toImplFNaNfPxhZAya@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaaZa@Base 6
+ _D3std4conv20__T10emplaceRefThThZ10emplaceRefFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv20__T10emplaceRefTwTwZ10emplaceRefFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv20__T11emplaceImplTxaZ20__T11emplaceImplTxaZ11emplaceImplFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv20__T4textTAyaTxaTAyaZ4textFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv20__T9convErrorTAxaThZ9convErrorFNaNfAxaiAyamZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTiZ9convErrorFNaNfAxaAyamZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTkZ9convErrorFNaNfAxaAyamZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTtZ9convErrorFNaNfAxaAyamZC3std4conv13ConvException@Base 6
+ _D3std4conv20isOctalLiteralStringFAyaZb@Base 6
+ _D3std4conv20strippedOctalLiteralFAyaZAya@Base 6
+ _D3std4conv21ConvOverflowException6__ctorMFNaNbNfAyaAyamZC3std4conv21ConvOverflowException@Base 6
+ _D3std4conv21ConvOverflowException6__initZ@Base 6
+ _D3std4conv21ConvOverflowException6__vtblZ@Base 6
+ _D3std4conv21ConvOverflowException7__ClassZ@Base 6
+ _D3std4conv21__T11emplaceImplTAxaZ21__T11emplaceImplTAxaZ11emplaceImplFNaNbNcNiNfKAxaKAxaZAxa@Base 6
+ _D3std4conv21__T11emplaceImplTAyaZ21__T11emplaceImplTAyaZ11emplaceImplFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv21__T4textTAxaTAyaTAxaZ4textFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAxaTAyaZ4textFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAyaTAyaZ4textFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTkTAyaTkZ4textFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv21__T4textTAyaTmTAyaTmZ4textFNaNbNfAyamAyamZAya@Base 6
+ _D3std4conv21__T4textTPxhTAyaTPxhZ4textFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv21__T8textImplTAyaTAyaZ8textImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv221__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv23__T8textImplTAyaTAyaTaZ8textImplFNaNfAyaaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTAyaTAyaZ10emplaceRefFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTxaTaTxaZ10emplaceRefFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv24__T8textImplTAyaTAyaTxaZ8textImplFNaNfAyaxaZAya@Base 6
+ _D3std4conv25__T4textTAyaTkTAyaTmTAyaZ4textFNaNbNfAyakAyamAyaZAya@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363630Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363636Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_373737Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAxaZ8textImplFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv27__T4textTAyaTAyaTAyaTiTAyaZ4textFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTAyaTmZ8textImplFNaNbNfAyaAyamZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTmTAyaZ8textImplFNaNbNfAyamAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTwTAyaZ8textImplFNaNfAyawAyaZAya@Base 6
+ _D3std4conv28__T8textImplTAyaTAyaTxaTAyaZ8textImplFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTAyaTAxaTAyaZ4textFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTiTAyaTiTAyaZ4textFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAxaTAyaTAxaZ8textImplFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTkTAyaTkZ8textImplFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTmTAyaTmZ8textImplFNaNbNfAyamAyamZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTPxhTAyaTPxhZ8textImplFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv30__T20convError_unexpectedTAxaZ20convError_unexpectedFNaNfAxaZAya@Base 6
+ _D3std4conv326__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv33__T8textImplTAyaTAyaTkTAyaTmTAyaZ8textImplFNaNbNfAyakAyamAyaZAya@Base 6
+ _D3std4conv34__T6toImplTiTE3std8datetime5MonthZ6toImplFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T6toImplTiTxE3std8datetime5MonthZ6toImplFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T8textImplTAyaTAyaTAyaTAyaTiTAyaZ8textImplFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv36__T4textTE3std5regex8internal2ir2IRZ4textFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv36__T7emplaceTS3std3net4curl3FTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl3FTP4ImplZPS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv37__T11emplaceImplTS3std4file8DirEntryZ37__T11emplaceImplTS3std4file8DirEntryZ11emplaceImplFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv37__T5toStrTAyaTS3std11concurrency3TidZ5toStrFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4HTTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4HTTP4ImplZPS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4SMTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4SMTP4ImplZPS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTiTAyaTiTAyaZ8textImplFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv38__T6toImplTAyaTS3std11concurrency3TidZ6toImplFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv40__T7emplaceTS3std4file15DirIteratorImplZ7emplaceFNaNbNiNfPS3std4file15DirIteratorImplZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv41__T11emplaceImplTS3std3net4curl3FTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std5regex8internal2ir2IRZ5toStrFNaNfE3std5regex8internal2ir2IRZyAa@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std6socket12SocketOptionZ5toStrFNaNfE3std6socket12SocketOptionZyAa@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4HTTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4SMTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std5regex8internal2ir2IRZ6toImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std6socket12SocketOptionZ6toImplFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv43__T11emplaceImplTS3std6socket11AddressInfoZ43__T11emplaceImplTS3std6socket11AddressInfoZ11emplaceImplFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv44__T8textImplTAyaTE3std5regex8internal2ir2IRZ8textImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ43__T11emplaceImplTAyaTE3std4file8SpanModeTbZ11emplaceImplFNcKS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv46__T11emplaceImplTS3std3uni17CodepointIntervalZ46__T11emplaceImplTS3std3uni17CodepointIntervalZ11emplaceImplFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl3FTP4ImplZ4inityS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T5toStrTAyaTPS3std11parallelism12AbstractTaskZ5toStrFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv48__T6toImplTiTE3std3net7isemail15EmailStatusCodeZ6toImplFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4HTTP4ImplZ4inityS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4SMTP4ImplZ4inityS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T5toStrTAyaTC3std11concurrency14LinkTerminatedZ5toStrFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv49__T6toImplTAyaTPS3std11parallelism12AbstractTaskZ6toImplFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv50__T5toStrTAyaTC3std11concurrency15OwnerTerminatedZ5toStrFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv50__T6toImplTAyaTC3std11concurrency14LinkTerminatedZ6toImplFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv51__T6toImplTAyaTC3std11concurrency15OwnerTerminatedZ6toImplFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNeKS3std4file15DirIteratorImplZ4inityS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNiNeKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv56__T10emplaceRefTS3std4file8DirEntryTS3std4file8DirEntryZ10emplaceRefFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir12__T5RegexTaZ5RegexKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std4conv65__T6toImplTiTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6toImplFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv66__T7emplaceTS3std4file15DirIteratorImplTAyaTE3std4file8SpanModeTbZ7emplaceFPS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv68__T10emplaceRefTS3std6socket11AddressInfoTS3std6socket11AddressInfoZ10emplaceRefFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni1Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni2Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni3Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni4Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni5Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni6Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni7Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni8Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni9Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni10Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni13Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni16Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni17Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni18Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni19Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni20Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni21Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni26Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni30Z7enumRepyAa@Base 6
+ _D3std4conv74__T10emplaceRefTS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ10emplaceRefFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi128Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi129Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi130Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi132Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi133Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi134Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi136Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi137Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi138Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi140Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi141Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi142Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi144Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi145Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi146Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi148Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi149Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi150Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi152Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi153Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi154Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi156Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi157Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi158Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi160Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi161Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi162Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi164Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi168Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi172Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi176Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi180Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi184Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi188Z7enumRepyAa@Base 6
+ _D3std4conv79__T4textTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ4textFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv82__T10emplaceRefTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv87__T8textImplTAyaTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ8textImplFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv88__T10emplaceRefTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv92__T10emplaceRefTS3std4file15DirIteratorImpl9DirHandleTS3std4file15DirIteratorImpl9DirHandleZ10emplaceRefFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv96__T4textTAyaTPvTAyaTiTAyaTiTAyaTaTAyaThTAyaThTAyaTbTAyaTbTAyaTbTAyaTbTAyaTbTAyaTAxaTAyaTAxaTAyaZ4textFNaNfAyaPvAyaiAyaiAyaaAyahAyahAyabAyabAyabAyabAyabAyaAxaAyaAxaAyaZAya@Base 6
+ _D3std4conv9__T2toThZ10__T2toTxkZ2toFNaNfxkZh@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxhZ2toFNaNbNiNfxhZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxkZ2toFNaNfxkZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxmZ2toFNaNfxmZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxsZ2toFNaNbNiNfxsZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTykZ2toFNaNfykZi@Base 6
+ _D3std4conv9__T2toTiZ28__T2toTE3std8datetime5MonthZ2toFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ29__T2toTxE3std8datetime5MonthZ2toFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ42__T2toTE3std3net7isemail15EmailStatusCodeZ2toFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv9__T2toTiZ59__T2toTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ2toFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toThZ2toFNaNbNiNfhZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTiZ2toFNaNbNiNfiZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTkZ2toFNaNfkZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTmZ2toFNaNfmZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTsZ2toFNaNbNiNfsZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTtZ2toFNaNbNiNftZi@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTkZ2toFNaNbNiNfkZk@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTmZ2toFNaNfmZk@Base 6
+ _D3std4conv9__T2toTlZ9__T2toTlZ2toFNaNbNiNflZl@Base 6
+ _D3std4conv9__T2toTlZ9__T2toTmZ2toFNaNfmZl@Base 6
+ _D3std4conv9__T2toTmZ9__T2toTkZ2toFNaNbNiNfkZm@Base 6
+ _D3std4conv9__T2toTmZ9__T2toTmZ2toFNaNbNiNfmZm@Base 6
+ _D3std4conv9__T2toTtZ11__T2toTAxaZ2toFNaNfAxaZt@Base 6
+ _D3std4file10attrIsFileFNaNbNiNfkZb@Base 6
+ _D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZb@Base 6
+ _D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std4file10dirEntriesFAyaE3std4file8SpanModebZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator11__fieldDtorMFZv@Base 6
+ _D3std4file11DirIterator11__xopEqualsFKxS3std4file11DirIteratorKxS3std4file11DirIteratorZb@Base 6
+ _D3std4file11DirIterator15__fieldPostblitMFNbZv@Base 6
+ _D3std4file11DirIterator5emptyMFNdZb@Base 6
+ _D3std4file11DirIterator5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std4file11DirIterator6__ctorMFNcAyaE3std4file8SpanModebZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator6__initZ@Base 6
+ _D3std4file11DirIterator8opAssignMFNcNjS3std4file11DirIteratorZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator8popFrontMFZv@Base 6
+ _D3std4file11DirIterator9__xtoHashFNbNeKxS3std4file11DirIteratorZm@Base 6
+ _D3std4file11thisExePathFNeZAya@Base 6
+ _D3std4file12__ModuleInfoZ@Base 6
+ _D3std4file12mkdirRecurseFxAaZv@Base 6
+ _D3std4file12rmdirRecurseFKS3std4file8DirEntryZv@Base 6
+ _D3std4file12rmdirRecurseFS3std4file8DirEntryZv@Base 6
+ _D3std4file12rmdirRecurseFxAaZv@Base 6
+ _D3std4file13FileException6__ctorMFNaNfxAaxAaAyamZC3std4file13FileException@Base 6
+ _D3std4file13FileException6__ctorMFNexAakAyamZC3std4file13FileException@Base 6
+ _D3std4file13FileException6__initZ@Base 6
+ _D3std4file13FileException6__vtblZ@Base 6
+ _D3std4file13FileException7__ClassZ@Base 6
+ _D3std4file13attrIsSymlinkFNaNbNiNfkZb@Base 6
+ _D3std4file13getAttributesFNfxAaZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file13getAttributesFNfxAaZk@Base 6
+ _D3std4file13setAttributesFNfxAakZ12trustedChmodFNbNiNexAakZi@Base 6
+ _D3std4file13setAttributesFNfxAakZv@Base 6
+ _D3std4file15DirIteratorImpl11__xopEqualsFKxS3std4file15DirIteratorImplKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std4file15DirIteratorImpl11popDirStackMFZv@Base 6
+ _D3std4file15DirIteratorImpl15releaseDirStackMFZv@Base 6
+ _D3std4file15DirIteratorImpl4nextMFZb@Base 6
+ _D3std4file15DirIteratorImpl5emptyMFNdZb@Base 6
+ _D3std4file15DirIteratorImpl5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std4file15DirIteratorImpl6__ctorMFNcAyaE3std4file8SpanModebZS3std4file15DirIteratorImpl@Base 6
+ _D3std4file15DirIteratorImpl6__dtorMFZv@Base 6
+ _D3std4file15DirIteratorImpl6__initZ@Base 6
+ _D3std4file15DirIteratorImpl6stepInMFAyaZb@Base 6
+ _D3std4file15DirIteratorImpl8hasExtraMFZb@Base 6
+ _D3std4file15DirIteratorImpl8opAssignMFNcNjS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4file15DirIteratorImpl8popExtraMFZS3std4file8DirEntry@Base 6
+ _D3std4file15DirIteratorImpl8popFrontMFZv@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle11__xopEqualsFKxS3std4file15DirIteratorImpl9DirHandleKxS3std4file15DirIteratorImpl9DirHandleZb@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle9__xtoHashFNbNeKxS3std4file15DirIteratorImpl9DirHandleZm@Base 6
+ _D3std4file15DirIteratorImpl9__xtoHashFNbNeKxS3std4file15DirIteratorImplZm@Base 6
+ _D3std4file15DirIteratorImpl9mayStepInMFZb@Base 6
+ _D3std4file15DirIteratorImpl9pushExtraMFS3std4file8DirEntryZv@Base 6
+ _D3std4file15__T8cenforceTbZ8cenforceFNfbLAxaAyamZb@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZ15trustedReadlinkFNbNiNeAxaAaZl@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZ19trustedAssumeUniqueFNaNbNiNeKAaZAya@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZAya@Base 6
+ _D3std4file15ensureDirExistsFxAaZb@Base 6
+ _D3std4file16__T8cenforceTPaZ8cenforceFNfPaLAxaAyamZPa@Base 6
+ _D3std4file16timeLastModifiedFNfxAaS3std8datetime7SysTimeZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file16timeLastModifiedFNfxAaS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std4file16timeLastModifiedFNfxAaZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file16timeLastModifiedFNfxAaZS3std8datetime7SysTime@Base 6
+ _D3std4file17getLinkAttributesFNfxAaZ12trustedLstatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file17getLinkAttributesFNfxAaZk@Base 6
+ _D3std4file42__T8cenforceTPS4core3sys5posix6dirent3DIRZ8cenforceFNfPS4core3sys5posix6dirent3DIRLAxaAyamZPS4core3sys5posix6dirent3DIR@Base 6
+ _D3std4file4copyFxAaxAaE3std8typecons53__T4FlagVAyaa18_707265736572766541747472696275746573Z4FlagZv@Base 6
+ _D3std4file4readFNexAamZAv@Base 6
+ _D3std4file5chdirFNfxAaZ12trustedChdirFNbNiNexAaZi@Base 6
+ _D3std4file5chdirFNfxAaZv@Base 6
+ _D3std4file5isDirFNdNfxAaZb@Base 6
+ _D3std4file5mkdirFNfxAaZ12trustedMkdirFNbNiNexAakZi@Base 6
+ _D3std4file5mkdirFNfxAaZv@Base 6
+ _D3std4file5rmdirFxAaZv@Base 6
+ _D3std4file5writeFNexAaxAvZv@Base 6
+ _D3std4file6appendFNexAaxAvZv@Base 6
+ _D3std4file6existsFNbNiNexAaZb@Base 6
+ _D3std4file6getcwdFZAya@Base 6
+ _D3std4file6isFileFNdNfxAaZb@Base 6
+ _D3std4file6removeFNexAaZv@Base 6
+ _D3std4file6renameFNexAaxAaZv@Base 6
+ _D3std4file7getSizeFNfxAaZ11trustedStatFNbNiNexAaPS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file7getSizeFNfxAaZ18ptrOfLocalVariableFNeNkKS4core3sys5posix3sys4stat6stat_tZPS4core3sys5posix3sys4stat6stat_t@Base 6
+ _D3std4file7getSizeFNfxAaZm@Base 6
+ _D3std4file7tempDirFNeZ45__T15findExistingDirTAyaTAyaTAyaTAyaTAyaTAyaZ15findExistingDirFNfLAyaLAyaLAyaLAyaLAyaLAyaZAya@Base 6
+ _D3std4file7tempDirFNeZ5cacheAya@Base 6
+ _D3std4file7tempDirFNeZAya@Base 6
+ _D3std4file8DirEntry10attributesMFNdZk@Base 6
+ _D3std4file8DirEntry11__xopEqualsFKxS3std4file8DirEntryKxS3std4file8DirEntryZb@Base 6
+ _D3std4file8DirEntry14linkAttributesMFNdZk@Base 6
+ _D3std4file8DirEntry15_ensureStatDoneMFNfZ11trustedStatFNbNiNexAaPS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file8DirEntry15_ensureStatDoneMFNfZv@Base 6
+ _D3std4file8DirEntry16_ensureLStatDoneMFZv@Base 6
+ _D3std4file8DirEntry16timeLastAccessedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry16timeLastModifiedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry17timeStatusChangedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry22_ensureStatOrLStatDoneMFZv@Base 6
+ _D3std4file8DirEntry4nameMxFNaNbNdZAya@Base 6
+ _D3std4file8DirEntry4sizeMFNdZm@Base 6
+ _D3std4file8DirEntry5isDirMFNdZb@Base 6
+ _D3std4file8DirEntry6__ctorMFNcAyaPS4core3sys5posix6dirent6direntZS3std4file8DirEntry@Base 6
+ _D3std4file8DirEntry6__ctorMFNcAyaZS3std4file8DirEntry@Base 6
+ _D3std4file8DirEntry6__initZ@Base 6
+ _D3std4file8DirEntry6isFileMFNdZb@Base 6
+ _D3std4file8DirEntry7statBufMFNdZS4core3sys5posix3sys4stat6stat_t@Base 6
+ _D3std4file8DirEntry9__xtoHashFNbNeKxS3std4file8DirEntryZm@Base 6
+ _D3std4file8DirEntry9isSymlinkMFNdZb@Base 6
+ _D3std4file8deletemeFNdNfZ6_firstb@Base 6
+ _D3std4file8deletemeFNdNfZ9_deletemeAya@Base 6
+ _D3std4file8deletemeFNdNfZAya@Base 6
+ _D3std4file8dirEntryFxAaZS3std4file8DirEntry@Base 6
+ _D3std4file8getTimesFNfxAaJS3std8datetime7SysTimeJS3std8datetime7SysTimeZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file8getTimesFNfxAaJS3std8datetime7SysTimeJS3std8datetime7SysTimeZv@Base 6
+ _D3std4file8setTimesFNfxAaS3std8datetime7SysTimeS3std8datetime7SysTimeZ13trustedUtimesFNbNiNexAaKxG2S4core3sys5posix3sys4time7timevalZi@Base 6
+ _D3std4file8setTimesFNfxAaS3std8datetime7SysTimeS3std8datetime7SysTimeZv@Base 6
+ _D3std4file9attrIsDirFNaNbNiNfkZb@Base 6
+ _D3std4file9isSymlinkFNdNfxAaZb@Base 6
+ _D3std4file9writeImplFNexAaxAvxkZv@Base 6
+ _D3std4json12__ModuleInfoZ@Base 6
+ _D3std4json13JSONException6__ctorMFNaNbNfAyaAyamZC3std4json13JSONException@Base 6
+ _D3std4json13JSONException6__ctorMFNaNbNfAyaiiZC3std4json13JSONException@Base 6
+ _D3std4json13JSONException6__initZ@Base 6
+ _D3std4json13JSONException6__vtblZ@Base 6
+ _D3std4json13JSONException7__ClassZ@Base 6
+ _D3std4json14appendJSONCharFPS3std5array17__T8AppenderTAyaZ8AppenderwMDFAyaZvZv@Base 6
+ _D3std4json16JSONFloatLiteral6__initZ@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ13putCharAndEOLMFaZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ6putEOLMFZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ7putTabsMFmZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ8toStringMFAyaZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue13__T6assignTdZ6assignMFNaNbNiNfdZv@Base 6
+ _D3std4json9JSONValue13__T6assignTlZ6assignMFNaNbNiNflZv@Base 6
+ _D3std4json9JSONValue13__T6assignTmZ6assignMFNaNbNiNfmZv@Base 6
+ _D3std4json9JSONValue14toPrettyStringMxFxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue15__T6assignTAyaZ6assignMFNaNbNiNfAyaZv@Base 6
+ _D3std4json9JSONValue33__T6assignTAS3std4json9JSONValueZ6assignMFNaNbNiNfAS3std4json9JSONValueZv@Base 6
+ _D3std4json9JSONValue36__T6assignTHAyaS3std4json9JSONValueZ6assignMFNaNbNiNfHAyaS3std4json9JSONValueZv@Base 6
+ _D3std4json9JSONValue3strMFNaNbNdNiAyaZAya@Base 6
+ _D3std4json9JSONValue3strMNgFNaNdZNgAya@Base 6
+ _D3std4json9JSONValue4typeMFNdE3std4json9JSON_TYPEZE3std4json9JSON_TYPE@Base 6
+ _D3std4json9JSONValue4typeMxFNaNbNdNiNfZE3std4json9JSON_TYPE@Base 6
+ _D3std4json9JSONValue5Store6__initZ@Base 6
+ _D3std4json9JSONValue5arrayMFNaNbNdNiAS3std4json9JSONValueZAS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue5arrayMNgFNaNcNdZNgAS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue6__initZ@Base 6
+ _D3std4json9JSONValue6isNullMxFNaNbNdNiNfZb@Base 6
+ _D3std4json9JSONValue6objectMFNaNbNdNiHAyaS3std4json9JSONValueZHAyaS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue6objectMNgFNaNcNdZNgHAyaS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue7integerMFNaNbNdNiNflZl@Base 6
+ _D3std4json9JSONValue7integerMNgFNaNdNfZNgl@Base 6
+ _D3std4json9JSONValue7opApplyMFDFAyaKS3std4json9JSONValueZiZi@Base 6
+ _D3std4json9JSONValue7opApplyMFDFmKS3std4json9JSONValueZiZi@Base 6
+ _D3std4json9JSONValue7opIndexMNgFNaNcAyaZNgS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue7opIndexMNgFNaNcmZNgS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue8floatingMFNaNbNdNiNfdZd@Base 6
+ _D3std4json9JSONValue8floatingMNgFNaNdNfZNgd@Base 6
+ _D3std4json9JSONValue8opEqualsMxFNaNbNiKxS3std4json9JSONValueZb@Base 6
+ _D3std4json9JSONValue8opEqualsMxFNaNbNixS3std4json9JSONValueZb@Base 6
+ _D3std4json9JSONValue8toStringMxFxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue8uintegerMFNaNbNdNiNfmZm@Base 6
+ _D3std4json9JSONValue8uintegerMNgFNaNdNfZNgm@Base 6
+ _D3std4math10__T3absTeZ3absFNaNbNiNfeZe@Base 6
+ _D3std4math11isIdenticalFNaNbNiNeeeZb@Base 6
+ _D3std4math12__ModuleInfoZ@Base 6
+ _D3std4math12__T3powTeTeZ3powFNaNbNiNeeeZ4implFNaNbNiNfeeZe@Base 6
+ _D3std4math12__T3powTeTeZ3powFNaNbNiNeeeZe@Base 6
+ _D3std4math12__T3powTeTlZ3powFNaNbNiNeelZe@Base 6
+ _D3std4math12__T3powTiTiZ3powFNaNbNiNeiiZi@Base 6
+ _D3std4math12__T5frexpTeZ5frexpFNaNbNiNexeJiZe@Base 6
+ _D3std4math12__T5isNaNTdZ5isNaNFNaNbNiNedZb@Base 6
+ _D3std4math12__T5isNaNTeZ5isNaNFNaNbNiNeeZb@Base 6
+ _D3std4math12__T5isNaNTfZ5isNaNFNaNbNiNefZb@Base 6
+ _D3std4math13__T4polyTeTeZ4polyFNaNbNiNeexAeZe@Base 6
+ _D3std4math13__T5isNaNTxdZ5isNaNFNaNbNiNexdZb@Base 6
+ _D3std4math13__T5isNaNTxeZ5isNaNFNaNbNiNexeZb@Base 6
+ _D3std4math13getNaNPayloadFNaNbNiNeeZm@Base 6
+ _D3std4math14__T4polyTyeTeZ4polyFNaNbNiNeyexAeZe@Base 6
+ _D3std4math14__T7signbitTeZ7signbitFNaNbNiNeeZi@Base 6
+ _D3std4math14resetIeeeFlagsFZv@Base 6
+ _D3std4math15__T7signbitTxeZ7signbitFNaNbNiNexeZi@Base 6
+ _D3std4math15__T7signbitTyeZ7signbitFNaNbNiNeyeZi@Base 6
+ _D3std4math15__T8ieeeMeanTeZ8ieeeMeanFNaNbNiNexexeZe@Base 6
+ _D3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZd@Base 6
+ _D3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZe@Base 6
+ _D3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZf@Base 6
+ _D3std4math17__T8copysignTdTeZ8copysignFNaNbNiNedeZd@Base 6
+ _D3std4math17__T8copysignTeTeZ8copysignFNaNbNiNeeeZe@Base 6
+ _D3std4math17__T8copysignTeTiZ8copysignFNaNbNiNeieZe@Base 6
+ _D3std4math18__T10isInfinityTdZ10isInfinityFNaNbNiNedZb@Base 6
+ _D3std4math18__T10isInfinityTeZ10isInfinityFNaNbNiNeeZb@Base 6
+ _D3std4math18__T10isInfinityTfZ10isInfinityFNaNbNiNefZb@Base 6
+ _D3std4math19__T10isInfinityTxdZ10isInfinityFNaNbNiNexdZb@Base 6
+ _D3std4math20FloatingPointControl10initializeMFNiZv@Base 6
+ _D3std4math20FloatingPointControl15clearExceptionsFNiZv@Base 6
+ _D3std4math20FloatingPointControl15getControlStateFNbNiNeZt@Base 6
+ _D3std4math20FloatingPointControl15setControlStateFNbNiNetZv@Base 6
+ _D3std4math20FloatingPointControl16enableExceptionsMFNikZv@Base 6
+ _D3std4math20FloatingPointControl17disableExceptionsMFNikZv@Base 6
+ _D3std4math20FloatingPointControl17enabledExceptionsFNdNiZk@Base 6
+ _D3std4math20FloatingPointControl17hasExceptionTrapsFNbNdNiNfZb@Base 6
+ _D3std4math20FloatingPointControl6__dtorMFNiZv@Base 6
+ _D3std4math20FloatingPointControl6__initZ@Base 6
+ _D3std4math20FloatingPointControl8opAssignMFNcNiNjS3std4math20FloatingPointControlZS3std4math20FloatingPointControl@Base 6
+ _D3std4math20FloatingPointControl8roundingFNdNiZk@Base 6
+ _D3std4math20FloatingPointControl8roundingMFNdNikZv@Base 6
+ _D3std4math22__T12polyImplBaseTeTeZ12polyImplBaseFNaNbNiNeexAeZe@Base 6
+ _D3std4math3NaNFNaNbNiNemZe@Base 6
+ _D3std4math3cosFNaNbNiNfcZc@Base 6
+ _D3std4math3cosFNaNbNiNfdZd@Base 6
+ _D3std4math3cosFNaNbNiNffZf@Base 6
+ _D3std4math3cosFNaNbNiNfjZe@Base 6
+ _D3std4math3expFNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math3expFNaNbNiNeeZ1QyG4e@Base 6
+ _D3std4math3expFNaNbNiNeeZe@Base 6
+ _D3std4math3expFNaNbNiNfdZd@Base 6
+ _D3std4math3expFNaNbNiNffZf@Base 6
+ _D3std4math3fmaFNaNbNiNfeeeZe@Base 6
+ _D3std4math3logFNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math3logFNaNbNiNfeZe@Base 6
+ _D3std4math3sinFNaNbNiNfcZc@Base 6
+ _D3std4math3sinFNaNbNiNfdZd@Base 6
+ _D3std4math3sinFNaNbNiNffZf@Base 6
+ _D3std4math3sinFNaNbNiNfjZj@Base 6
+ _D3std4math3tanFNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math3tanFNaNbNiNeeZ1QyG5e@Base 6
+ _D3std4math3tanFNaNbNiNeeZe@Base 6
+ _D3std4math4acosFNaNbNiNfdZd@Base 6
+ _D3std4math4acosFNaNbNiNfeZe@Base 6
+ _D3std4math4acosFNaNbNiNffZf@Base 6
+ _D3std4math4asinFNaNbNiNfdZd@Base 6
+ _D3std4math4asinFNaNbNiNfeZe@Base 6
+ _D3std4math4asinFNaNbNiNffZf@Base 6
+ _D3std4math4atanFNaNbNiNfdZd@Base 6
+ _D3std4math4atanFNaNbNiNfeZ1PyG5e@Base 6
+ _D3std4math4atanFNaNbNiNfeZ1QyG6e@Base 6
+ _D3std4math4atanFNaNbNiNfeZe@Base 6
+ _D3std4math4atanFNaNbNiNffZf@Base 6
+ _D3std4math4cbrtFNbNiNeeZe@Base 6
+ _D3std4math4ceilFNaNbNiNedZd@Base 6
+ _D3std4math4ceilFNaNbNiNeeZe@Base 6
+ _D3std4math4ceilFNaNbNiNefZf@Base 6
+ _D3std4math4coshFNaNbNiNfdZd@Base 6
+ _D3std4math4coshFNaNbNiNfeZe@Base 6
+ _D3std4math4coshFNaNbNiNffZf@Base 6
+ _D3std4math4exp2FNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math4exp2FNaNbNiNeeZ1QyG4e@Base 6
+ _D3std4math4exp2FNaNbNiNeeZe@Base 6
+ _D3std4math4expiFNaNbNiNeeZc@Base 6
+ _D3std4math4fabsFNaNbNiNfdZd@Base 6
+ _D3std4math4fabsFNaNbNiNffZf@Base 6
+ _D3std4math4fdimFNaNbNiNfeeZe@Base 6
+ _D3std4math4fmaxFNaNbNiNfeeZe@Base 6
+ _D3std4math4fminFNaNbNiNfeeZe@Base 6
+ _D3std4math4fmodFNbNiNeeeZe@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math4log2FNaNbNiNfeZe@Base 6
+ _D3std4math4logbFNbNiNeeZe@Base 6
+ _D3std4math4modfFNbNiNeeKeZe@Base 6
+ _D3std4math4rintFNaNbNiNfdZd@Base 6
+ _D3std4math4rintFNaNbNiNffZf@Base 6
+ _D3std4math4sinhFNaNbNiNfdZd@Base 6
+ _D3std4math4sinhFNaNbNiNfeZe@Base 6
+ _D3std4math4sinhFNaNbNiNffZf@Base 6
+ _D3std4math4sqrtFNaNbNiNfcZc@Base 6
+ _D3std4math4tanhFNaNbNiNfdZd@Base 6
+ _D3std4math4tanhFNaNbNiNfeZe@Base 6
+ _D3std4math4tanhFNaNbNiNffZf@Base 6
+ _D3std4math5acoshFNaNbNiNfdZd@Base 6
+ _D3std4math5acoshFNaNbNiNfeZe@Base 6
+ _D3std4math5acoshFNaNbNiNffZf@Base 6
+ _D3std4math5asinhFNaNbNiNfdZd@Base 6
+ _D3std4math5asinhFNaNbNiNfeZe@Base 6
+ _D3std4math5asinhFNaNbNiNffZf@Base 6
+ _D3std4math5atan2FNaNbNiNeeeZe@Base 6
+ _D3std4math5atan2FNaNbNiNfddZd@Base 6
+ _D3std4math5atan2FNaNbNiNfffZf@Base 6
+ _D3std4math5atanhFNaNbNiNfdZd@Base 6
+ _D3std4math5atanhFNaNbNiNfeZe@Base 6
+ _D3std4math5atanhFNaNbNiNffZf@Base 6
+ _D3std4math5expm1FNaNbNiNeeZ1PyG5e@Base 6
+ _D3std4math5expm1FNaNbNiNeeZ1QyG6e@Base 6
+ _D3std4math5expm1FNaNbNiNeeZe@Base 6
+ _D3std4math5floorFNaNbNiNedZd@Base 6
+ _D3std4math5floorFNaNbNiNeeZe@Base 6
+ _D3std4math5floorFNaNbNiNefZf@Base 6
+ _D3std4math5hypotFNaNbNiNfeeZe@Base 6
+ _D3std4math5ilogbFNbNiNeeZi@Base 6
+ _D3std4math5ldexpFNaNbNiNfdiZd@Base 6
+ _D3std4math5ldexpFNaNbNiNffiZf@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math5log10FNaNbNiNfeZe@Base 6
+ _D3std4math5log1pFNaNbNiNfeZe@Base 6
+ _D3std4math5lrintFNaNbNiNeeZl@Base 6
+ _D3std4math5roundFNbNiNeeZe@Base 6
+ _D3std4math5truncFNbNiNeeZe@Base 6
+ _D3std4math6lroundFNbNiNeeZl@Base 6
+ _D3std4math6nextUpFNaNbNiNedZd@Base 6
+ _D3std4math6nextUpFNaNbNiNeeZe@Base 6
+ _D3std4math6nextUpFNaNbNiNefZf@Base 6
+ _D3std4math6remquoFNbNiNeeeJiZe@Base 6
+ _D3std4math6rndtolFNaNbNiNfdZl@Base 6
+ _D3std4math6rndtolFNaNbNiNffZl@Base 6
+ _D3std4math6scalbnFNbNiNeeiZe@Base 6
+ _D3std4math8nextDownFNaNbNiNfdZd@Base 6
+ _D3std4math8nextDownFNaNbNiNfeZe@Base 6
+ _D3std4math8nextDownFNaNbNiNffZf@Base 6
+ _D3std4math8polyImplFNaNbNiNeexAeZe@Base 6
+ _D3std4math9IeeeFlags12getIeeeFlagsFZk@Base 6
+ _D3std4math9IeeeFlags14resetIeeeFlagsFZv@Base 6
+ _D3std4math9IeeeFlags6__initZ@Base 6
+ _D3std4math9IeeeFlags7inexactMFNdZb@Base 6
+ _D3std4math9IeeeFlags7invalidMFNdZb@Base 6
+ _D3std4math9IeeeFlags8overflowMFNdZb@Base 6
+ _D3std4math9IeeeFlags9divByZeroMFNdZb@Base 6
+ _D3std4math9IeeeFlags9underflowMFNdZb@Base 6
+ _D3std4math9coshisinhFNaNbNiNfeZc@Base 6
+ _D3std4math9ieeeFlagsFNdZS3std4math9IeeeFlags@Base 6
+ _D3std4math9nearbyintFNbNiNeeZe@Base 6
+ _D3std4math9remainderFNbNiNeeeZe@Base 6
+ _D3std4meta12__ModuleInfoZ@Base 6
+ _D3std4path109__T9globMatchVE3std4path13CaseSensitivei1TaTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ9globMatchFNaNbNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplAxaZb@Base 6
+ _D3std4path11expandTildeFNbAyaZ18expandFromDatabaseFNbAyaZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZ21combineCPathWithDPathFNbPaAyamZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZ21expandFromEnvironmentFNbAyaZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZAya@Base 6
+ _D3std4path12__ModuleInfoZ@Base 6
+ _D3std4path12absolutePathFNaNfAyaLAyaZAya@Base 6
+ _D3std4path14isDirSeparatorFNaNbNiNfwZb@Base 6
+ _D3std4path16__T7dirNameTAxaZ7dirNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path16__T9buildPathTaZ9buildPathFNaNbNfAAxaXAya@Base 6
+ _D3std4path16isDriveSeparatorFNaNbNiNfwZb@Base 6
+ _D3std4path17__T8baseNameTAxaZ8baseNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path17__T8baseNameTAyaZ8baseNameFNaNbNiNfAyaZAya@Base 6
+ _D3std4path17__T8isRootedTAxaZ8isRootedFNaNbNiNfAxaZb@Base 6
+ _D3std4path17__T8isRootedTAyaZ8isRootedFNaNbNiNfAyaZb@Base 6
+ _D3std4path17__T8rootNameTAxaZ8rootNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path18__T9extensionTAyaZ9extensionFNaNbNiNfAyaZAya@Base 6
+ _D3std4path19__T9buildPathTAAxaZ9buildPathFAAxaZ24__T11trustedCastTAyaTAaZ11trustedCastFNaNbNiNeAaZAya@Base 6
+ _D3std4path19__T9buildPathTAAxaZ9buildPathFNaNbNfAAxaZAya@Base 6
+ _D3std4path20__T10stripDriveTAxaZ10stripDriveFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path20__T10stripDriveTAyaZ10stripDriveFNaNbNiNfAyaZAya@Base 6
+ _D3std4path21__T9chainPathTAaTAxaZ9chainPathFNaNbNiNfAaAxaZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter11__xopEqualsFKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterZb@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter4backMFNaNbNdNiNfZAxa@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter4saveMFNaNbNdNiNfZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5frontMFNaNbNdNiNfZAxa@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5ltrimMFNaNbNiNfmmZm@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5rtrimMFNaNbNiNfmmZm@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__ctorMFNaNbNcNiNfAxaZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter7popBackMFNaNbNiNfZv@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter9__xtoHashFNbNeKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterZm@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFNaNbNiNfAxaZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T9chainPathTAxaTAxaZ9chainPathFNaNbNiNfAxaAxaZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path22__T9chainPathTAyaTAyaZ9chainPathFNaNbNiNfAyaAyaZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path23__T13lastSeparatorTAxaZ13lastSeparatorFNaNbNiNfAxaZl@Base 6
+ _D3std4path23__T13lastSeparatorTAyaZ13lastSeparatorFNaNbNiNfAyaZl@Base 6
+ _D3std4path25__T15extSeparatorPosTAyaZ15extSeparatorPosFNaNbNiNfxAyaZl@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result11__xopEqualsFKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result11getElement0MFNaNbNiNfZa@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result4saveMFNaNbNdNiNfZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5frontMFNaNbNdNiNfZa@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5isDotFNaNbNiNfAxaZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__ctorMFNaNbNcNiNfAxaZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__initZ@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result8isDotDotFNaNbNiNfAxaZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result9__xtoHashFNbNeKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZm@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFNaNbNiNfAxaZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path27__T19buildNormalizedPathTaZ19buildNormalizedPathFNaNbNeAxAaXAya@Base 6
+ _D3std4path28__T18rtrimDirSeparatorsTAxaZ18rtrimDirSeparatorsFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path28__T18rtrimDirSeparatorsTAyaZ18rtrimDirSeparatorsFNaNbNiNfAyaZAya@Base 6
+ _D3std4path48__T9globMatchVE3std4path13CaseSensitivei1TaTAyaZ9globMatchFNaNbNfAyaAxaZb@Base 6
+ _D3std4path49__T15filenameCharCmpVE3std4path13CaseSensitivei1Z15filenameCharCmpFNaNbNiNfwwZi@Base 6
+ _D3std4uuid10randomUUIDFNfZS3std4uuid4UUID@Base 6
+ _D3std4uuid12__ModuleInfoZ@Base 6
+ _D3std4uuid164__T10randomUUIDTS3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngineZ10randomUUIDFNaNbNfKS3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngineZS3std4uuid4UUID@Base 6
+ _D3std4uuid20UUIDParsingException6__ctorMFNaNeAyamE3std4uuid20UUIDParsingException6ReasonAyaC6object9ThrowableAyamZC3std4uuid20UUIDParsingException@Base 6
+ _D3std4uuid20UUIDParsingException6__initZ@Base 6
+ _D3std4uuid20UUIDParsingException6__vtblZ@Base 6
+ _D3std4uuid20UUIDParsingException7__ClassZ@Base 6
+ _D3std4uuid4UUID11uuidVersionMxFNaNbNdNiNfZE3std4uuid4UUID7Version@Base 6
+ _D3std4uuid4UUID13__T6__ctorTaZ6__ctorMFNaNcNfxAaZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID16__T9asArrayOfTkZ9asArrayOfMFNaNbNcNiNjNeZG4k@Base 6
+ _D3std4uuid4UUID4swapMFNaNbNiNfKS3std4uuid4UUIDZv@Base 6
+ _D3std4uuid4UUID5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std4uuid4UUID5opCmpMxFNaNbNiNfKxS3std4uuid4UUIDZi@Base 6
+ _D3std4uuid4UUID5opCmpMxFNaNbNiNfxS3std4uuid4UUIDZi@Base 6
+ _D3std4uuid4UUID6__ctorMFNaNbNcNiNfKxG16hZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID6__ctorMFNaNbNcNiNfxG16hZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID6__initZ@Base 6
+ _D3std4uuid4UUID6toCharMxFNaNbNfmZa@Base 6
+ _D3std4uuid4UUID6toHashMxFNaNbNiNfZm@Base 6
+ _D3std4uuid4UUID7Version6__initZ@Base 6
+ _D3std4uuid4UUID7variantMxFNaNbNdNiNfZE3std4uuid4UUID7Variant@Base 6
+ _D3std4uuid4UUID8opEqualsMxFNaNbNiNfKxS3std4uuid4UUIDZb@Base 6
+ _D3std4uuid4UUID8opEqualsMxFNaNbNiNfxS3std4uuid4UUIDZb@Base 6
+ _D3std4uuid4UUID8toStringMxFMDFAxaZvZv@Base 6
+ _D3std4uuid4UUID8toStringMxFNaNbNfZAya@Base 6
+ _D3std4uuid4UUID9_toStringMxFNaNbNfZG36a@Base 6
+ _D3std4uuid7md5UUIDFNaNbNiNfxAaxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid7md5UUIDFNaNbNiNfxAhxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid8sha1UUIDFNaNbNiNfxAaxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid8sha1UUIDFNaNbNiNfxAhxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4zlib10UnCompress10uncompressMFAxvZAxv@Base 6
+ _D3std4zlib10UnCompress5errorMFiZv@Base 6
+ _D3std4zlib10UnCompress5flushMFZAv@Base 6
+ _D3std4zlib10UnCompress6__ctorMFE3std4zlib12HeaderFormatZC3std4zlib10UnCompress@Base 6
+ _D3std4zlib10UnCompress6__ctorMFkZC3std4zlib10UnCompress@Base 6
+ _D3std4zlib10UnCompress6__dtorMFZv@Base 6
+ _D3std4zlib10UnCompress6__initZ@Base 6
+ _D3std4zlib10UnCompress6__vtblZ@Base 6
+ _D3std4zlib10UnCompress7__ClassZ@Base 6
+ _D3std4zlib10uncompressFAvmiZAv@Base 6
+ _D3std4zlib12__ModuleInfoZ@Base 6
+ _D3std4zlib13ZlibException6__ctorMFiZC3std4zlib13ZlibException@Base 6
+ _D3std4zlib13ZlibException6__initZ@Base 6
+ _D3std4zlib13ZlibException6__vtblZ@Base 6
+ _D3std4zlib13ZlibException7__ClassZ@Base 6
+ _D3std4zlib5crc32FkAxvZk@Base 6
+ _D3std4zlib7adler32FkAxvZk@Base 6
+ _D3std4zlib8Compress5errorMFiZv@Base 6
+ _D3std4zlib8Compress5flushMFiZAv@Base 6
+ _D3std4zlib8Compress6__ctorMFE3std4zlib12HeaderFormatZC3std4zlib8Compress@Base 6
+ _D3std4zlib8Compress6__ctorMFiE3std4zlib12HeaderFormatZC3std4zlib8Compress@Base 6
+ _D3std4zlib8Compress6__dtorMFZv@Base 6
+ _D3std4zlib8Compress6__initZ@Base 6
+ _D3std4zlib8Compress6__vtblZ@Base 6
+ _D3std4zlib8Compress7__ClassZ@Base 6
+ _D3std4zlib8Compress8compressMFAxvZAxv@Base 6
+ _D3std4zlib8compressFAxvZAxv@Base 6
+ _D3std4zlib8compressFAxviZAxv@Base 6
+ _D3std5array102__T5arrayTS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZ5arrayFNaNbNfS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZAAya@Base 6
+ _D3std5array118__T13insertInPlaceTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir8BytecodemS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array12__ModuleInfoZ@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNeANgvANgvZ3maxFNaNbNiNfPNgvPNgvZPNgv@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNeANgvANgvZ3minFNaNbNiNfPNgvPNgvZPNgv@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNiNeANgvANgvZANgv@Base 6
+ _D3std5array154__T5arrayTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZ5arrayFNaNbNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data11__xopEqualsFKxS3std5array16__T8AppenderTAaZ8Appender4DataKxS3std5array16__T8AppenderTAaZ8Appender4DataZb@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data6__initZ@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data9__xtoHashFNbNeKxS3std5array16__T8AppenderTAaZ8Appender4DataZm@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4dataMNgFNaNbNdNiNeZANga@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender6__ctorMFNaNbNcNeAaZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender6__initZ@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender8shrinkToMFNaNemZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender10__T3putThZ3putMFNaNbNfhZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender11__T3putTAhZ3putMFNaNbNfAhZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data11__xopEqualsFKxS3std5array16__T8AppenderTAhZ8Appender4DataKxS3std5array16__T8AppenderTAhZ8Appender4DataZb@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data6__initZ@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data9__xtoHashFNbNeKxS3std5array16__T8AppenderTAhZ8Appender4DataZm@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4dataMNgFNaNbNdNiNeZANgh@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender6__ctorMFNaNbNcNeAhZS3std5array16__T8AppenderTAhZ8Appender@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender6__initZ@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender8shrinkToMFNaNemZv@Base 6
+ _D3std5array16__T8appenderTAaZ8appenderFNaNbNfZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array16__T8appenderTAhZ8appenderFNaNbNfZS3std5array16__T8AppenderTAhZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAxaZ8Appender4DataKxS3std5array17__T8AppenderTAxaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAxaZ8Appender4DataZm@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4dataMNgFNaNbNdNiNeZANgxa@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender6__ctorMFNaNbNcNeAxaZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTxaZ3putMFNaNbNfxaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTxwZ3putMFNaNfxwZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTyaZ3putMFNaNbNfyaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAyaZ8Appender4DataKxS3std5array17__T8AppenderTAyaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAyaZ8Appender4DataZm@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4dataMNgFNaNbNdNiNeZAya@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcAaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcNeAyaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender11__T3putTAuZ3putMFNaNbNfAuZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAyuZ8Appender4DataKxS3std5array17__T8AppenderTAyuZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAyuZ8Appender4DataZm@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4dataMNgFNaNbNdNiNeZAyu@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcAuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcNeAyuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender10__T3putTwZ3putMFNaNbNfwZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAywZ8Appender4DataKxS3std5array17__T8AppenderTAywZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAywZ8Appender4DataZm@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4dataMNgFNaNbNdNiNeZAyw@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcAwZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcNeAywZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTxaZ3putMFNaNbNfxaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTxwZ3putMFNaNfxwZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTyaZ3putMFNaNbNfyaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTyAaZ8Appender4DataKxS3std5array17__T8AppenderTyAaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTyAaZ8Appender4DataZm@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4dataMNgFNaNbNdNiNeZAya@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcAaZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcNeAyaZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array17__T8appenderTAxaZ8appenderFNaNbNfZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array17__T8appenderTAyaZ8appenderFNaNbNfZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8appenderTyAaZ8appenderFNaNbNfZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array18__T5splitTAyaTAyaZ5splitFNaNbNfAyaAyaZAAya@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data11__xopEqualsFKxS3std5array18__T8AppenderTAAyaZ8Appender4DataKxS3std5array18__T8AppenderTAAyaZ8Appender4DataZb@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data6__initZ@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data9__xtoHashFNbNeKxS3std5array18__T8AppenderTAAyaZ8Appender4DataZm@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4dataMNgFNaNbNdNiNeZANgAya@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender6__ctorMFNaNbNcNeAAyaZS3std5array18__T8AppenderTAAyaZ8Appender@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender6__initZ@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender8shrinkToMFNaNemZv@Base 6
+ _D3std5array18__T8appenderTAAyaZ8appenderFNaNbNfZS3std5array18__T8AppenderTAAyaZ8Appender@Base 6
+ _D3std5array19__T8appenderHTAaTaZ8appenderFNaNbNfAaZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAxaTxaZ8appenderFNaNbNfAxaZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAyaTyaZ8appenderFNaNbNfAyaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAyuTyuZ8appenderFNaNbNfAyuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAywTywZ8appenderFNaNbNfAywZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array23__T7replaceTxaTAyaTAyaZ7replaceFNaNbNfAxaAyaAyaZAxa@Base 6
+ _D3std5array23__T7replaceTyaTAyaTAyaZ7replaceFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAaTmZ14arrayAllocImplFNaNbmZAa@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAfTmZ14arrayAllocImplFNaNbmZAf@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAhTmZ14arrayAllocImplFNaNbmZAh@Base 6
+ _D3std5array29__T18uninitializedArrayTAaTmZ18uninitializedArrayFNaNbNemZAa@Base 6
+ _D3std5array29__T18uninitializedArrayTAfTmZ18uninitializedArrayFNaNbNemZAf@Base 6
+ _D3std5array29__T19appenderNewCapacityVmi1Z19appenderNewCapacityFNaNbNiNfmmZm@Base 6
+ _D3std5array29__T19appenderNewCapacityVmi2Z19appenderNewCapacityFNaNbNiNfmmZm@Base 6
+ _D3std5array29__T19appenderNewCapacityVmi4Z19appenderNewCapacityFNaNbNiNfmmZm@Base 6
+ _D3std5array30__T18uninitializedArrayTAhTymZ18uninitializedArrayFNaNbNeymZAh@Base 6
+ _D3std5array30__T19appenderNewCapacityVmi16Z19appenderNewCapacityFNaNbNiNfmmZm@Base 6
+ _D3std5array30__T19appenderNewCapacityVmi24Z19appenderNewCapacityFNaNbNiNfmmZm@Base 6
+ _D3std5array30__T19appenderNewCapacityVmi40Z19appenderNewCapacityFNaNbNiNfmmZm@Base 6
+ _D3std5array31__T19appenderNewCapacityVmi168Z19appenderNewCapacityFNaNbNiNfmmZm@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender28__T3putTS3std4file8DirEntryZ3putMFNaNbNfS3std4file8DirEntryZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data11__xopEqualsFKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataZb@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data6__initZ@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data9__xtoHashFNbNeKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataZm@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4dataMNgFNaNbNdNiNeZANgS3std4file8DirEntry@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__ctorMFNaNbNcNeAS3std4file8DirEntryZS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender8shrinkToMFNaNemZv@Base 6
+ _D3std5array405__T5arrayTS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZ5arrayFNaNbNfS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZAxa@Base 6
+ _D3std5array405__T5arrayTS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZ5arrayFNaNbNfS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZAxa@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender34__T3putTS3std6socket11AddressInfoZ3putMFNaNbNfS3std6socket11AddressInfoZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data11__xopEqualsFKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataZb@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data6__initZ@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data9__xtoHashFNbNeKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataZm@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4dataMNgFNaNbNdNiNeZANgS3std6socket11AddressInfo@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender52__T10opOpAssignHVAyaa1_7eTS3std6socket11AddressInfoZ10opOpAssignMFNaNbNfS3std6socket11AddressInfoZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__ctorMFNaNbNcNeAS3std6socket11AddressInfoZS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__initZ@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender8shrinkToMFNaNemZv@Base 6
+ _D3std5array40__T8appenderTAS3std6socket11AddressInfoZ8appenderFNaNbNfZS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender@Base 6
+ _D3std5array52__T13copyBackwardsTS3std5regex8internal2ir8BytecodeZ13copyBackwardsFNaNbNiAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender13ensureAddableMFNaNbNemZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender46__T3putTS3std4file15DirIteratorImpl9DirHandleZ3putMFNaNbNfS3std4file15DirIteratorImpl9DirHandleZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data11__xopEqualsFKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataZb@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data6__initZ@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data9__xtoHashFNbNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataZm@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4dataMNgFNaNbNdNiNeZANgS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__ctorMFNaNbNcNeAS3std4file15DirIteratorImpl9DirHandleZS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender7reserveMFNaNbNfmZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender8shrinkToMFNaNemZv@Base 6
+ _D3std5array55__T13copyBackwardsTS3std5regex8internal2ir10NamedGroupZ13copyBackwardsFNaNbNiAS3std5regex8internal2ir10NamedGroupAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5array55__T8appenderHTAS3std4file8DirEntryTS3std4file8DirEntryZ8appenderFNaNbNfAS3std4file8DirEntryZS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender@Base 6
+ _D3std5array56__T14arrayAllocImplVbi0TAS3std3uni17CodepointIntervalTmZ14arrayAllocImplFNaNbmZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array56__T18uninitializedArrayTAS3std3uni17CodepointIntervalTmZ18uninitializedArrayFNaNbNemZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array57__T18uninitializedArrayTAS3std3uni17CodepointIntervalTyiZ18uninitializedArrayFNaNbNeyiZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array68__T11replaceIntoTxaTS3std5array17__T8AppenderTAxaZ8AppenderTAyaTAyaZ11replaceIntoFNaNbNfS3std5array17__T8AppenderTAxaZ8AppenderAxaAyaAyaZv@Base 6
+ _D3std5array68__T11replaceIntoTyaTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTAyaZ11replaceIntoFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderAyaAyaAyaZv@Base 6
+ _D3std5array79__T5arrayTS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZ5arrayFNaNbNfS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZAa@Base 6
+ _D3std5array85__T13insertInPlaceTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir8BytecodemS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array892__T5arrayTS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplZ5arrayFNaNbNfS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplZAa@Base 6
+ _D3std5array91__T13insertInPlaceTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir10NamedGroupmS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5array91__T8appenderHTAS3std4file15DirIteratorImpl9DirHandleTS3std4file15DirIteratorImpl9DirHandleZ8appenderFNaNbNfAS3std4file15DirIteratorImpl9DirHandleZS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender@Base 6
+ _D3std5ascii10isAlphaNumFNaNbNiNfwZb@Base 6
+ _D3std5ascii10isHexDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii10whitespaceyAa@Base 6
+ _D3std5ascii11isGraphicalFNaNbNiNfwZb@Base 6
+ _D3std5ascii11isPrintableFNaNbNiNfwZb@Base 6
+ _D3std5ascii11octalDigitsyAa@Base 6
+ _D3std5ascii12__ModuleInfoZ@Base 6
+ _D3std5ascii12isOctalDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii13fullHexDigitsyAa@Base 6
+ _D3std5ascii13isPunctuationFNaNbNiNfwZb@Base 6
+ _D3std5ascii14__T7toLowerTwZ7toLowerFNaNbNiNfwZw@Base 6
+ _D3std5ascii14lowerHexDigitsyAa@Base 6
+ _D3std5ascii15__T7toLowerTxaZ7toLowerFNaNbNiNfxaZa@Base 6
+ _D3std5ascii15__T7toLowerTxwZ7toLowerFNaNbNiNfxwZw@Base 6
+ _D3std5ascii15__T7toLowerTyaZ7toLowerFNaNbNiNfyaZa@Base 6
+ _D3std5ascii6digitsyAa@Base 6
+ _D3std5ascii7isASCIIFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isAlphaFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isLowerFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isUpperFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isWhiteFNaNbNiNfwZb@Base 6
+ _D3std5ascii7lettersyAa@Base 6
+ _D3std5ascii7newlineyAa@Base 6
+ _D3std5ascii9hexDigitsyAa@Base 6
+ _D3std5ascii9isControlFNaNbNiNfwZb@Base 6
+ _D3std5ascii9lowercaseyAa@Base 6
+ _D3std5ascii9uppercaseyAa@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange11__xopEqualsFKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZb@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4saveMFNaNbNdNiNfZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__ctorMFNaNbNcNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opIndexMFNaNbNcNiNfmZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7releaseMFNaNbNiZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange9__xtoHashFNbNeKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZm@Base 6
+ _D3std5range103__T12assumeSortedVAyaa17_612e74696d6554203c20622e74696d6554TAS3std8datetime13PosixTimeZone10LeapSecondZ12assumeSortedFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange11__xopEqualsFKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZb@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4saveMFNaNbNdNiNfZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__ctorMFNaNbNcNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opIndexMFNaNbNcNiNfmZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7releaseMFNaNbNiZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange9__xtoHashFNbNeKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZm@Base 6
+ _D3std5range107__T12assumeSortedVAyaa17_612e74696d6554203c20622e74696d6554TAS3std8datetime13PosixTimeZone14TempTransitionZ12assumeSortedFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range10interfaces12__ModuleInfoZ@Base 6
+ _D3std5range10primitives107__T6moveAtTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTmZ6moveAtFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsmZS3std3uni17CodepointInterval@Base 6
+ _D3std5range10primitives11__T4backThZ4backFNaNbNcNdNiNfAhZh@Base 6
+ _D3std5range10primitives11__T4backTkZ4backFNaNbNcNdNiNfAkZk@Base 6
+ _D3std5range10primitives11__T4saveTaZ4saveFNaNbNdNiNfAaZAa@Base 6
+ _D3std5range10primitives11__T4saveTfZ4saveFNaNbNdNiNfAfZAf@Base 6
+ _D3std5range10primitives11__T4saveThZ4saveFNaNbNdNiNfAhZAh@Base 6
+ _D3std5range10primitives11__T4saveTkZ4saveFNaNbNdNiNfAkZAk@Base 6
+ _D3std5range10primitives12__ModuleInfoZ@Base 6
+ _D3std5range10primitives12__T4backTxaZ4backFNaNdNfAxaZw@Base 6
+ _D3std5range10primitives12__T4backTxhZ4backFNaNbNcNdNiNfAxhZxh@Base 6
+ _D3std5range10primitives12__T4backTyaZ4backFNaNdNfAyaZw@Base 6
+ _D3std5range10primitives12__T4saveTxaZ4saveFNaNbNdNiNfAxaZAxa@Base 6
+ _D3std5range10primitives12__T4saveTxhZ4saveFNaNbNdNiNfAxhZAxh@Base 6
+ _D3std5range10primitives12__T4saveTxuZ4saveFNaNbNdNiNfAxuZAxu@Base 6
+ _D3std5range10primitives12__T4saveTyaZ4saveFNaNbNdNiNfAyaZAya@Base 6
+ _D3std5range10primitives12__T5emptyTaZ5emptyFNaNbNdNiNfxAaZb@Base 6
+ _D3std5range10primitives12__T5emptyTbZ5emptyFNaNbNdNiNfxAbZb@Base 6
+ _D3std5range10primitives12__T5emptyThZ5emptyFNaNbNdNiNfxAhZb@Base 6
+ _D3std5range10primitives12__T5emptyTkZ5emptyFNaNbNdNiNfxAkZb@Base 6
+ _D3std5range10primitives12__T5emptyTuZ5emptyFNaNbNdNiNfxAuZb@Base 6
+ _D3std5range10primitives12__T5emptyTwZ5emptyFNaNbNdNiNfxAwZb@Base 6
+ _D3std5range10primitives12__T5frontTaZ5frontFNaNdNfAaZw@Base 6
+ _D3std5range10primitives12__T5frontThZ5frontFNaNbNcNdNiNfAhZh@Base 6
+ _D3std5range10primitives12__T5frontTkZ5frontFNaNbNcNdNiNfAkZk@Base 6
+ _D3std5range10primitives138__T6moveAtTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultTmZ6moveAtFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultmZk@Base 6
+ _D3std5range10primitives138__T6moveAtTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultTmZ6moveAtFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultmZk@Base 6
+ _D3std5range10primitives139__T9moveFrontTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ9moveFrontFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZk@Base 6
+ _D3std5range10primitives139__T9moveFrontTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ9moveFrontFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZk@Base 6
+ _D3std5range10primitives13__T3putTAkTkZ3putFNaNbNiNfKAkkZv@Base 6
+ _D3std5range10primitives13__T4backTAyaZ4backFNaNbNcNdNiNfAAyaZAya@Base 6
+ _D3std5range10primitives13__T4saveTAxaZ4saveFNaNbNdNiNfAAxaZAAxa@Base 6
+ _D3std5range10primitives13__T4saveTAyaZ4saveFNaNbNdNiNfAAyaZAAya@Base 6
+ _D3std5range10primitives13__T5frontTxaZ5frontFNaNdNfAxaZw@Base 6
+ _D3std5range10primitives13__T5frontTxhZ5frontFNaNbNcNdNiNfAxhZxh@Base 6
+ _D3std5range10primitives13__T5frontTxuZ5frontFNaNdNfAxuZw@Base 6
+ _D3std5range10primitives13__T5frontTxwZ5frontFNaNbNcNdNiNfAxwZxw@Base 6
+ _D3std5range10primitives13__T5frontTyaZ5frontFNaNdNfAyaZw@Base 6
+ _D3std5range10primitives13__T5frontTyhZ5frontFNaNbNcNdNiNfAyhZyh@Base 6
+ _D3std5range10primitives13__T5frontTywZ5frontFNaNbNcNdNiNfAywZyw@Base 6
+ _D3std5range10primitives14__T5emptyTAxaZ5emptyFNaNbNdNiNfxAAaZb@Base 6
+ _D3std5range10primitives14__T5emptyTAyaZ5emptyFNaNbNdNiNfxAAyaZb@Base 6
+ _D3std5range10primitives14__T5frontTAyaZ5frontFNaNbNcNdNiNfAAyaZAya@Base 6
+ _D3std5range10primitives14__T5frontTyAaZ5frontFNaNbNcNdNiNfAyAaZyAa@Base 6
+ _D3std5range10primitives14__T7popBackThZ7popBackFNaNbNiNfKAhZv@Base 6
+ _D3std5range10primitives14__T7popBackTkZ7popBackFNaNbNiNfKAkZv@Base 6
+ _D3std5range10primitives15__T5doPutTAkTkZ5doPutFNaNbNiNfKAkKkZv@Base 6
+ _D3std5range10primitives15__T7popBackTxhZ7popBackFNaNbNiNfKAxhZv@Base 6
+ _D3std5range10primitives15__T7popBackTyaZ7popBackFNaNfKAyaZv@Base 6
+ _D3std5range10primitives15__T8popFrontTaZ8popFrontFNaNbNiNeKAaZv@Base 6
+ _D3std5range10primitives15__T8popFrontTkZ8popFrontFNaNbNiNfKAkZv@Base 6
+ _D3std5range10primitives16__T7popBackTAyaZ7popBackFNaNbNiNfKAAyaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxaZ8popFrontFNaNbNiNeKAxaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxhZ8popFrontFNaNbNiNfKAxhZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxuZ8popFrontFNaNbNiNeKAxuZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxwZ8popFrontFNaNbNiNfKAxwZv@Base 6
+ _D3std5range10primitives16__T8popFrontTyaZ8popFrontFNaNbNiNeKAyaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTyhZ8popFrontFNaNbNiNfKAyhZv@Base 6
+ _D3std5range10primitives16__T8popFrontTywZ8popFrontFNaNbNiNfKAywZv@Base 6
+ _D3std5range10primitives17__T6moveAtTAxhTmZ6moveAtFNaNbNiNfAxhmZxh@Base 6
+ _D3std5range10primitives17__T8moveBackTAxhZ8moveBackFNaNbNiNfAxhZxh@Base 6
+ _D3std5range10primitives17__T8moveBackTAyaZ8moveBackFNaNfAyaZw@Base 6
+ _D3std5range10primitives17__T8popFrontTAyaZ8popFrontFNaNbNiNfKAAyaZv@Base 6
+ _D3std5range10primitives17__T8popFrontTyAaZ8popFrontFNaNbNiNfKAyAaZv@Base 6
+ _D3std5range10primitives17__T9popFrontNTAhZ9popFrontNFNaNbNiNfKAhmZm@Base 6
+ _D3std5range10primitives18__T3putTDFAxaZvTaZ3putFKDFAxaZvaZ16__T9__lambda3TaZ9__lambda3FNaNbNiNeKaZAa@Base 6
+ _D3std5range10primitives18__T3putTDFAxaZvTaZ3putFKDFAxaZvaZv@Base 6
+ _D3std5range10primitives18__T9moveFrontTAxhZ9moveFrontFNaNbNiNfAxhZxh@Base 6
+ _D3std5range10primitives18__T9moveFrontTAyaZ9moveFrontFNaNfAyaZw@Base 6
+ _D3std5range10primitives192__T9moveFrontTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ9moveFrontFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZw@Base 6
+ _D3std5range10primitives19__T10walkLengthTAhZ10walkLengthFNaNbNiNfAhZm@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTAaZ3putFKDFAxaZvAaZv@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTxaZ3putFKDFAxaZvxaZ17__T9__lambda3TxaZ9__lambda3FNaNbNiNeKxaZAxa@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTxaZ3putFKDFAxaZvxaZv@Base 6
+ _D3std5range10primitives20__T10walkLengthTAyaZ10walkLengthFNaNbNiNfAyaZm@Base 6
+ _D3std5range10primitives20__T3putTDFAxaZvTAxaZ3putFKDFAxaZvAxaZv@Base 6
+ _D3std5range10primitives20__T3putTDFAxaZvTAyaZ3putFKDFAxaZvAyaZv@Base 6
+ _D3std5range10primitives21__T5doPutTDFAxaZvTAaZ5doPutFKDFAxaZvAaZv@Base 6
+ _D3std5range10primitives21__T5doPutTDFAxaZvTAaZ5doPutFKDFAxaZvKAaZv@Base 6
+ _D3std5range10primitives223__T10walkLengthTS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZ10walkLengthFNaNbNiNfS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakexmZm@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAxaZ5doPutFKDFAxaZvAxaZv@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAxaZ5doPutFKDFAxaZvKAxaZv@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAyaZ5doPutFKDFAxaZvKAyaZv@Base 6
+ _D3std5range10primitives24__T3putTDFNaNbNfAxaZvTaZ3putFKDFNaNbNfAxaZvaZ16__T9__lambda3TaZ9__lambda3FNaNbNiNeKaZAa@Base 6
+ _D3std5range10primitives24__T3putTDFNaNbNfAxaZvTaZ3putFNaNbNfKDFNaNbNfAxaZvaZv@Base 6
+ _D3std5range10primitives25__T14popBackExactlyTAAyaZ14popBackExactlyFNaNbNiNfKAAyamZv@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTAaZ3putFNaNbNfKDFNaNbNfAxaZvAaZv@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTxaZ3putFKDFNaNbNfAxaZvxaZ17__T9__lambda3TxaZ9__lambda3FNaNbNiNeKxaZAxa@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTxaZ3putFNaNbNfKDFNaNbNfAxaZvxaZv@Base 6
+ _D3std5range10primitives26__T15popFrontExactlyTAAyaZ15popFrontExactlyFNaNbNiNfKAAyamZv@Base 6
+ _D3std5range10primitives26__T3putTDFNaNbNfAxaZvTAxaZ3putFNaNbNfKDFNaNbNfAxaZvAxaZv@Base 6
+ _D3std5range10primitives26__T3putTDFNaNbNfAxaZvTAyaZ3putFNaNbNfKDFNaNbNfAxaZvAyaZv@Base 6
+ _D3std5range10primitives27__T5doPutTDFNaNbNfAxaZvTAaZ5doPutFNaNbNfKDFNaNbNfAxaZvAaZv@Base 6
+ _D3std5range10primitives27__T5doPutTDFNaNbNfAxaZvTAaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAxaZ5doPutFNaNbNfKDFNaNbNfAxaZvAxaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAxaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAxaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAyaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAyaZv@Base 6
+ _D3std5range10primitives30__T5emptyTS3std4file8DirEntryZ5emptyFNaNbNdNiNfxAS3std4file8DirEntryZb@Base 6
+ _D3std5range10primitives31__T5emptyTS3std4json9JSONValueZ5emptyFNaNbNdNiNfxAS3std4json9JSONValueZb@Base 6
+ _D3std5range10primitives41__T14popBackExactlyTAC4core6thread5FiberZ14popBackExactlyFNaNbNiNfKAC4core6thread5FibermZv@Base 6
+ _D3std5range10primitives42__T15popFrontExactlyTAC4core6thread5FiberZ15popFrontExactlyFNaNbNiNfKAC4core6thread5FibermZv@Base 6
+ _D3std5range10primitives43__T5emptyTS3std5regex8internal2ir8BytecodeZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir8BytecodeZb@Base 6
+ _D3std5range10primitives45__T4backTS3std5regex8internal2ir10NamedGroupZ4backFNaNbNcNdNiNfAS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives45__T4saveTS3std5regex8internal2ir10NamedGroupZ4saveFNaNbNdNiNfAS3std5regex8internal2ir10NamedGroupZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives46__T3putTS3std5stdio4File17LockingTextWriterTaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriteraZv@Base 6
+ _D3std5range10primitives46__T3putTS3std5stdio4File17LockingTextWriterTwZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterwZv@Base 6
+ _D3std5range10primitives46__T5emptyTS3std5regex8internal2ir10NamedGroupZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5range10primitives46__T5frontTS3std5regex8internal2ir10NamedGroupZ5frontFNaNbNcNdNiNfAS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTAaZ3putFNfKS3std5stdio4File17LockingTextWriterAaZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTxaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterxaZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTxwZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterxwZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTyaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriteryaZv@Base 6
+ _D3std5range10primitives47__T6moveAtTS3std5range13__T6RepeatTiZ6RepeatTmZ6moveAtFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatmZi@Base 6
+ _D3std5range10primitives48__T3putTS3std5stdio4File17LockingTextWriterTAxaZ3putFNfKS3std5stdio4File17LockingTextWriterAxaZv@Base 6
+ _D3std5range10primitives48__T3putTS3std5stdio4File17LockingTextWriterTAyaZ3putFNfKS3std5stdio4File17LockingTextWriterAyaZv@Base 6
+ _D3std5range10primitives48__T5doPutTS3std5stdio4File17LockingTextWriterTaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKaZv@Base 6
+ _D3std5range10primitives48__T5doPutTS3std5stdio4File17LockingTextWriterTwZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKwZv@Base 6
+ _D3std5range10primitives48__T5emptyTS3std4file15DirIteratorImpl9DirHandleZ5emptyFNaNbNdNiNfxAS3std4file15DirIteratorImpl9DirHandleZb@Base 6
+ _D3std5range10primitives48__T7popBackTS3std5regex8internal2ir10NamedGroupZ7popBackFNaNbNiNfKAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5range10primitives48__T9moveFrontTS3std5range13__T6RepeatTiZ6RepeatZ9moveFrontFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatZi@Base 6
+ _D3std5range10primitives48__T9popFrontNTAS3std5regex8internal2ir8BytecodeZ9popFrontNFNaNbNiNfKAS3std5regex8internal2ir8BytecodemZm@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTAaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAaZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTxaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKxaZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTxwZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKxwZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTyaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKyaZv@Base 6
+ _D3std5range10primitives49__T5emptyTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5emptyFNaNbNdNiNfxAS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std5range10primitives49__T8popFrontTS3std5regex8internal2ir10NamedGroupZ8popFrontFNaNbNiNfKAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderaZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTwZ3putFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderwZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderaZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTwZ3putFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderwZv@Base 6
+ _D3std5range10primitives50__T5doPutTS3std5stdio4File17LockingTextWriterTAxaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAxaZv@Base 6
+ _D3std5range10primitives50__T5doPutTS3std5stdio4File17LockingTextWriterTAyaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAyaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTxaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderxaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTxwZ3putFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderxwZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTyaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderyaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTxaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderxaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTxwZ3putFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderxwZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTyaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderyaZv@Base 6
+ _D3std5range10primitives51__T4backTS3std8datetime13PosixTimeZone10LeapSecondZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives51__T4backTS3std8datetime13PosixTimeZone10TransitionZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives51__T4backTyS3std8internal14unicode_tables9CompEntryZ4backFNaNbNcNdNiNfAyS3std8internal14unicode_tables9CompEntryZyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives51__T4saveTS3std8datetime13PosixTimeZone10LeapSecondZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives51__T4saveTS3std8datetime13PosixTimeZone10TransitionZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone10TransitionZAS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives51__T4saveTyS3std8internal14unicode_tables9CompEntryZ4saveFNaNbNdNiNfAyS3std8internal14unicode_tables9CompEntryZAyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives51__T5emptyTS3std8internal14unicode_tables9CompEntryZ5emptyFNaNbNdNiNfxAS3std8internal14unicode_tables9CompEntryZb@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAxaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAxaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAyaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAyaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAxaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAxaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAyaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAyaZv@Base 6
+ _D3std5range10primitives52__T4backTyS3std8datetime13PosixTimeZone10LeapSecondZ4backFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives52__T4backTyS3std8datetime13PosixTimeZone10TransitionZ4backFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10TransitionZyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKaZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTwZ5doPutFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKwZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKaZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTwZ5doPutFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKwZv@Base 6
+ _D3std5range10primitives52__T5emptyTS3std8datetime13PosixTimeZone10LeapSecondZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std5range10primitives52__T5emptyTS3std8datetime13PosixTimeZone10TransitionZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone10TransitionZb@Base 6
+ _D3std5range10primitives52__T5frontTS3std8datetime13PosixTimeZone10LeapSecondZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives52__T5frontTS3std8datetime13PosixTimeZone10TransitionZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives52__T5frontTyS3std8internal14unicode_tables9CompEntryZ5frontFNaNbNcNdNiNfAyS3std8internal14unicode_tables9CompEntryZyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKxaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTxwZ5doPutFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKxwZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKyaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKxaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTxwZ5doPutFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKxwZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKyaZv@Base 6
+ _D3std5range10primitives53__T5frontTyS3std8datetime13PosixTimeZone10LeapSecondZ5frontFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAxaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAyaZv@Base 6
+ _D3std5range10primitives54__T5emptyTS3std5regex8internal2ir12__T5GroupTmZ5GroupZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5range10primitives54__T7popBackTS3std8datetime13PosixTimeZone10LeapSecondZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std5range10primitives54__T7popBackTS3std8datetime13PosixTimeZone10TransitionZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range10primitives54__T7popBackTyS3std8internal14unicode_tables9CompEntryZ7popBackFNaNbNiNfKAyS3std8internal14unicode_tables9CompEntryZv@Base 6
+ _D3std5range10primitives55__T4backTS3std8datetime13PosixTimeZone14TempTransitionZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives55__T4saveTS3std8datetime13PosixTimeZone14TempTransitionZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives55__T8popFrontTS3std8datetime13PosixTimeZone10LeapSecondZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std5range10primitives55__T8popFrontTS3std8datetime13PosixTimeZone10TransitionZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range10primitives55__T8popFrontTyS3std8internal14unicode_tables9CompEntryZ8popFrontFNaNbNiNfKAyS3std8internal14unicode_tables9CompEntryZv@Base 6
+ _D3std5range10primitives56__T5emptyTS3std8datetime13PosixTimeZone14TempTransitionZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std5range10primitives56__T5frontTS3std8datetime13PosixTimeZone14TempTransitionZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives56__T6moveAtTAS3std8datetime13PosixTimeZone10TransitionTmZ6moveAtFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionmZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives56__T8moveBackTAS3std8datetime13PosixTimeZone10TransitionZ8moveBackFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives57__T9moveFrontTAS3std8datetime13PosixTimeZone10TransitionZ9moveFrontFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives58__T4backTyS3std8internal14unicode_tables15UnicodePropertyZ4backFNaNbNcNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives58__T4saveTyS3std8internal14unicode_tables15UnicodePropertyZ4saveFNaNbNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives58__T5emptyTS3std8internal14unicode_tables15UnicodePropertyZ5emptyFNaNbNdNiNfxAS3std8internal14unicode_tables15UnicodePropertyZb@Base 6
+ _D3std5range10primitives58__T7popBackTS3std8datetime13PosixTimeZone14TempTransitionZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std5range10primitives59__T5frontTyS3std8internal14unicode_tables15UnicodePropertyZ5frontFNaNbNcNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives59__T8popFrontTS3std8datetime13PosixTimeZone14TempTransitionZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std5range10primitives61__T7popBackTyS3std8internal14unicode_tables15UnicodePropertyZ7popBackFNaNbNiNfKAyS3std8internal14unicode_tables15UnicodePropertyZv@Base 6
+ _D3std5range10primitives62__T6moveAtTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTmZ6moveAtFNaNbNiNfS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultmZa@Base 6
+ _D3std5range10primitives62__T8moveBackTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultZ8moveBackFNaNbNiNfS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultZa@Base 6
+ _D3std5range10primitives62__T8popFrontTyS3std8internal14unicode_tables15UnicodePropertyZ8popFrontFNaNbNiNfKAyS3std8internal14unicode_tables15UnicodePropertyZv@Base 6
+ _D3std5range10primitives63__T9moveFrontTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultZ9moveFrontFNaNbNiNfS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultZa@Base 6
+ _D3std5range10primitives673__T3putTAkTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ3putFNaNfKAkS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZv@Base 6
+ _D3std5range10primitives678__T10walkLengthTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ10walkLengthFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZm@Base 6
+ _D3std5range10primitives67__T4backTS3std12experimental6logger11multilogger16MultiLoggerEntryZ4backFNaNbNcNdNiNfAS3std12experimental6logger11multilogger16MultiLoggerEntryZS3std12experimental6logger11multilogger16MultiLoggerEntry@Base 6
+ _D3std5range10primitives70__T7popBackTS3std12experimental6logger11multilogger16MultiLoggerEntryZ7popBackFNaNbNiNfKAS3std12experimental6logger11multilogger16MultiLoggerEntryZv@Base 6
+ _D3std5range10primitives71__T5emptyTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5emptyFNaNbNdNiNfxAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std5range10primitives75__T5emptyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5emptyFNaNbNdNiNfxAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std5range10primitives76__T6moveAtTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTmZ6moveAtFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplmZa@Base 6
+ _D3std5range10primitives76__T8moveBackTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZa@Base 6
+ _D3std5range10primitives77__T9moveFrontTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZa@Base 6
+ _D3std5range10primitives78__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaZ3putFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkaZv@Base 6
+ _D3std5range10primitives78__T5emptyTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZ5emptyFNaNbNdNiNfxAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZb@Base 6
+ _D3std5range10primitives78__T6moveAtTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTmZ6moveAtFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplmZxa@Base 6
+ _D3std5range10primitives78__T6moveAtTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTmZ6moveAtFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplmZya@Base 6
+ _D3std5range10primitives78__T8moveBackTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZxa@Base 6
+ _D3std5range10primitives78__T8moveBackTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZya@Base 6
+ _D3std5range10primitives79__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAaZ3putFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkAaZv@Base 6
+ _D3std5range10primitives79__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTxaZ3putFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxaZv@Base 6
+ _D3std5range10primitives79__T9moveFrontTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZxa@Base 6
+ _D3std5range10primitives79__T9moveFrontTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZya@Base 6
+ _D3std5range10primitives80__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAxaZ3putFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkAxaZv@Base 6
+ _D3std5range10primitives80__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaZ5doPutFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKaZv@Base 6
+ _D3std5range10primitives81__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAaZ5doPutFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKAaZv@Base 6
+ _D3std5range10primitives81__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTxaZ5doPutFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKxaZv@Base 6
+ _D3std5range10primitives82__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAxaZ5doPutFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKAxaZv@Base 6
+ _D3std5range11__T4iotaTmZ4iotaFNaNbNiNfmZS3std5range13__T4iotaTmTmZ4iotaFmmZ6Result@Base 6
+ _D3std5range11__T4onlyTaZ4onlyFNaNbNiNfaZS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult@Base 6
+ _D3std5range12__ModuleInfoZ@Base 6
+ _D3std5range12__T4takeTAhZ4takeFNaNbNiNfAhmZAh@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4backMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4saveMFNaNbNdNiNfZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5frontMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6moveAtMFNfmZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7opIndexMFNfmZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8moveBackMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9maxLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9moveFrontMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4backMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4saveMFNaNbNdNiNfZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5frontMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6moveAtMFNfmZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7opIndexMFNfmZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8moveBackMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9maxLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9moveFrontMFNfZk@Base 6
+ _D3std5range134__T4takeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4takeFNaNbNiNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultmZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4takeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4takeFNaNbNiNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultmZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFNaNbNiNfmmZS3std5range13__T4iotaTmTmZ4iotaFmmZ6Result@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result4backMNgFNaNbNdNiNfZNgm@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result4saveMFNaNbNdNiNfZS3std5range13__T4iotaTmTmZ4iotaFmmZ6Result@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result5frontMNgFNaNbNdNiNfZNgm@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result6__ctorMFNaNbNcNiNfmmZS3std5range13__T4iotaTmTmZ4iotaFmmZ6Result@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result6__initZ@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result7opIndexMNgFNaNbNiNfmZNgm@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result7opSliceMNgFNaNbNiNfZNgS3std5range13__T4iotaTmTmZ4iotaFmmZ6Result@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result7opSliceMNgFNaNbNiNfmmZNgS3std5range13__T4iotaTmTmZ4iotaFmmZ6Result@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range13__T4iotaTmTmZ4iotaFmmZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat11DollarToken6__initZ@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat4backMNgFNaNbNdNiNfZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat4saveMNgFNaNbNdNiNfZNgS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat5frontMNgFNaNbNdNiNfZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat6__initZ@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opIndexMNgFNaNbNiNfmZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opSliceMFNaNbNfmmZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opSliceMNgFNaNbNiNfmS3std5range13__T6RepeatTiZ6Repeat11DollarTokenZNgS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6repeatTiZ6repeatFNaNbNiNfiZS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result10retroIndexMFNaNbNiNfmZm@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result4backMFNaNbNcNdNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result5frontMFNaNbNcNdNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6moveAtMFNaNbNiNfmZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7opIndexMFNaNbNcNiNfmZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7opSliceMFNaNbNiNfmmZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result8moveBackMFNaNbNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultZm@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result9moveFrontMFNaNbNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFNaNbNiNfAxhZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result4backMFNaNdNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result5frontMFNaNdNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result8moveBackMFNaNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZm@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result9moveFrontMFNaNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFNaNbNiNfAyaZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11DollarToken6__initZ@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11DollarToken9momLengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11__xopEqualsFKxS3std5range14__T6ChunksTAhZ6ChunksKxS3std5range14__T6ChunksTAhZ6ChunksZb@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks4backMFNaNbNdNiNfZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks4saveMFNaNbNdNiNfZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks5frontMFNaNbNdNiNfZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6__ctorMFNaNbNcNiNfAhmZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6__initZ@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opIndexMFNaNbNiNfmZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenmZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfmS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfmmZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks8opDollarMFNaNbNiNfZS3std5range14__T6ChunksTAhZ6Chunks11DollarToken@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks9__xtoHashFNbNeKxS3std5range14__T6ChunksTAhZ6ChunksZm@Base 6
+ _D3std5range14__T6chunksTAhZ6chunksFNaNbNiNfAhmZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take11__xopEqualsFKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZb@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take4saveMFNaNbNdNiNfZS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take5frontMFNaNbNdNiNfZw@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take6__initZ@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9__xtoHashFNbNeKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZm@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9maxLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9moveFrontMFNaNbNiNfZw@Base 6
+ _D3std5range187__T4takeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4takeFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmZS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfmZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfmZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfmmZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZm@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfmZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfmZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfmmZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZm@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfmZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfmZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfmmZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZm@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange13__T3geqTywTwZ3geqMFNaNbNiNfywwZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange287__T18getTransitionIndexVE3std5range12SearchPolicyi3S2293std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange3geqTwZ18getTransitionIndexMFNaNbNiNfwZm@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi3TwZ10lowerBoundMFNaNbNiNfwZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange4backMFNaNbNdNiNfZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNdNiNfZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNiNfmZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeZm@Base 6
+ _D3std5range200__T12assumeSortedVAyaa5_61203c2062TS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZ12assumeSortedFNaNbNiNfS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange11__xopEqualsFKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeZb@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange4backMFNaNbNdNiNfZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange4saveMFNaNbNdNiNfZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange5frontMFNaNbNdNiNfZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__ctorMFNaNbNcNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__initZ@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7opIndexMFNaNbNiNfmZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7releaseMFNaNbNiZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange9__xtoHashFNbNeKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeZm@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult11__T6__ctorZ6__ctorMFNaNbNcNiNfKaZS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult4backMFNaNbNdNiNfZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult4saveMFNaNbNdNiNfZS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult5frontMFNaNbNdNiNfZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult6__initZ@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult7opIndexMFNaNbNiNfmZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult7opSliceMFNaNbNiNfZS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult7opSliceMFNaNbNiNfmmZS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFNaNbNiNfS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result11__xopEqualsFKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZb@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result4saveMFNaNdNfZS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result5emptyMFNaNdNfZb@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result5frontMFNaNdNfZk@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result6__initZ@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result9__xtoHashFNbNeKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZm@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange11__xopEqualsFKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange121__T18getTransitionIndexVE3std5range12SearchPolicyi3S643std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange3geqTkZ18getTransitionIndexMFNaNbNiNfkZm@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange12__T3geqTkTkZ3geqMFNaNbNiNfkkZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi3TkZ10lowerBoundMFNaNbNiNfkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange4saveMFNaNbNdNiNfZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__initZ@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7opIndexMFNaNbNcNiNfmZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange9__xtoHashFNbNeKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeZm@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange455__T18getTransitionIndexVE3std5range12SearchPolicyi3S3953std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZm@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfmZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZm@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange458__T18getTransitionIndexVE3std5range12SearchPolicyi3S3983std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZm@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfmZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZm@Base 6
+ _D3std5range36__T12assumeSortedVAyaa4_613c3d62TAkZ12assumeSortedFNaNbNiNfAkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange461__T18getTransitionIndexVE3std5range12SearchPolicyi3S4013std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZm@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfmZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZm@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange123__T18getTransitionIndexVE3std5range12SearchPolicyi2S663std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange3geqTiZ18getTransitionIndexMFNaNbNiNfiZm@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange123__T18getTransitionIndexVE3std5range12SearchPolicyi3S663std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange3geqTiZ18getTransitionIndexMFNaNbNiNfiZm@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange12__T3geqTkTiZ3geqMFNaNbNiNfkiZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi2TiZ10lowerBoundMFNaNbNiNfiZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNcNiNfmZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeZm@Base 6
+ _D3std5range38__T12assumeSortedVAyaa5_61203c2062TAkZ12assumeSortedFNaNbNiNfAkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange4backMFNaNbNcNdNiNfZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNcNdNiNfZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNcNiNfmZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZAAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeZm@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange11__xopEqualsFKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange126__T18getTransitionIndexVE3std5range12SearchPolicyi3S683std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange3geqTyiZ18getTransitionIndexMFNaNbNiNfyiZm@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange13__T3geqTkTyiZ3geqMFNaNbNiNfkyiZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange47__T10lowerBoundVE3std5range12SearchPolicyi3TyiZ10lowerBoundMFNaNbNiNfyiZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__initZ@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7opIndexMFNaNbNcNiNfmZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange9__xtoHashFNbNeKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeZm@Base 6
+ _D3std5range40__T12assumeSortedVAyaa5_61203c2062TAAyaZ12assumeSortedFNaNbNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range40__T12assumeSortedVAyaa6_61203c3d2062TAkZ12assumeSortedFNaNbNiNfAkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take4backMFNaNbNdNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take4saveMFNaNbNdNiNfZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take5frontMFNaNbNdNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6__initZ@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6moveAtMFNaNbNiNfmZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take7opIndexMFNaNbNiNfmZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take8moveBackMFNaNbNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take9maxLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take9moveFrontMFNaNbNiNfZi@Base 6
+ _D3std5range51__T11takeExactlyTS3std5range13__T6RepeatTiZ6RepeatZ11takeExactlyFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatmZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result10retroIndexMFNaNbNiNfmZm@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result13opIndexAssignMFNaNbNiNfS3std8datetime13PosixTimeZone10TransitionmZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4backMFNaNbNdNiNfS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5frontMFNaNbNdNiNfS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6moveAtMFNaNbNiNfmZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7opIndexMFNaNbNcNiNfmZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7opSliceMFNaNbNiNfmmZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result8moveBackMFNaNbNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultZm@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result9moveFrontMFNaNbNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range69__T5retroTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ5retroFNaNbNiNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZAya@Base 6
+ _D3std5range8NullSink6__initZ@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange11__xopEqualsFKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange213__T18getTransitionIndexVE3std5range12SearchPolicyi3S1213std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange3geqTS3std5regex8internal2ir10NamedGroupZ18getTransitionIndexMFNaNbNiNfS3std5regex8internal2ir10NamedGroupZm@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange4backMFNaNbNcNdNiNfZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange4saveMFNaNbNdNiNfZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange5frontMFNaNbNcNdNiNfZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__ctorMFNaNbNcNiNfAS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__initZ@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7opIndexMFNaNbNcNiNfmZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7opSliceMFNaNbNiNfmmZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7releaseMFNaNbNiZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange80__T10lowerBoundVE3std5range12SearchPolicyi3TS3std5regex8internal2ir10NamedGroupZ10lowerBoundMFNaNbNiNfS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange80__T3geqTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ3geqMFNaNbNiNfS3std5regex8internal2ir10NamedGroupS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange9__xtoHashFNbNeKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeZm@Base 6
+ _D3std5range93__T12assumeSortedVAyaa15_612e6e616d65203c20622e6e616d65TAS3std5regex8internal2ir10NamedGroupZ12assumeSortedFNaNbNiNfAS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5regex12__ModuleInfoZ@Base 6
+ _D3std5regex14__T5regexTAyaZ5regexFNeAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures10newMatchesMFNaNbNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures11__xopEqualsFKxS3std5regex18__T8CapturesTAaTmZ8CapturesKxS3std5regex18__T8CapturesTAaTmZ8CapturesZb@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures12__T7opIndexZ7opIndexMFNaNbNemZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures3hitMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures3preMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures4backMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures4postMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures59__T6__ctorS453std5regex8internal8thompson15ThompsonMatcherZ6__ctorMFNaNbNcNeKS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex18__T8CapturesTAaTmZ8Captures@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures5frontMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures6__initZ@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures7matchesMFNaNbNdNiNeZAS3std5regex8internal2ir12__T5GroupTmZ5Group@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures7popBackMFNaNbNiNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures8capturesMFNaNbNcNdNiNeZS3std5regex18__T8CapturesTAaTmZ8Captures@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures8popFrontMFNaNbNiNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTmZ8Captures9__xtoHashFNbNeKxS3std5regex18__T8CapturesTAaTmZ8CapturesZm@Base 6
+ _D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures10newMatchesMFNaNbNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures11__xopEqualsFKxS3std5regex19__T8CapturesTAxaTmZ8CapturesKxS3std5regex19__T8CapturesTAxaTmZ8CapturesZb@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures12__T7opIndexZ7opIndexMFNaNbNemZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures3hitMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures3preMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures4backMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures4postMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures59__T6__ctorS453std5regex8internal8thompson15ThompsonMatcherZ6__ctorMFNaNbNcNeKS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex19__T8CapturesTAxaTmZ8Captures@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures5frontMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures6__initZ@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures7matchesMFNaNbNdNiNeZAS3std5regex8internal2ir12__T5GroupTmZ5Group@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures7popBackMFNaNbNiNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures8capturesMFNaNbNcNdNiNeZS3std5regex19__T8CapturesTAxaTmZ8Captures@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures8popFrontMFNaNbNiNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTmZ8Captures9__xtoHashFNbNeKxS3std5regex19__T8CapturesTAxaTmZ8CapturesZm@Base 6
+ _D3std5regex57__T5matchTAaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ5matchFNfAaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex58__T5matchTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ5matchFNfAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch10__postblitMFNaNbNiNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch11__xopEqualsFKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZb@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3hitMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3preMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4postMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4saveMFNaNbNiNeZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch55__T6__ctorTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ6__ctorMFNcNeAaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5frontMFNaNbNdNiNeZS3std5regex18__T8CapturesTAaTmZ8Captures@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__dtorMFNbNiNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch7counterMFNaNbNcNdNiNeZm@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8capturesMFNaNbNdNiNeZS3std5regex18__T8CapturesTAaTmZ8Captures@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8opAssignMFNbNcNiNjNeS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8popFrontMFNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch9__xtoHashFNbNeKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZm@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch10__postblitMFNaNbNiNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch11__xopEqualsFKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZb@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3hitMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3preMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4postMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4saveMFNaNbNiNeZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch55__T6__ctorTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ6__ctorMFNcNeAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5frontMFNaNbNdNiNeZS3std5regex19__T8CapturesTAxaTmZ8Captures@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__dtorMFNbNiNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch7counterMFNaNbNcNdNiNeZm@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8capturesMFNaNbNdNiNeZS3std5regex19__T8CapturesTAxaTmZ8Captures@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8opAssignMFNbNcNiNjNeS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8popFrontMFNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch9__xtoHashFNbNeKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZm@Base 6
+ _D3std5regex8internal12backtracking10__T5ctSubZ5ctSubFNaNbNiNeAyaZAya@Base 6
+ _D3std5regex8internal12backtracking12__ModuleInfoZ@Base 6
+ _D3std5regex8internal12backtracking12__T5ctSubTiZ5ctSubFNaNbNeAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking12__T5ctSubTkZ5ctSubFNaNbNeAyakZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTAyaZ5ctSubFNaNbNeAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTiTiZ5ctSubFNaNbNeAyaiiZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTkTiZ5ctSubFNaNbNeAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTkTkZ5ctSubFNaNbNeAyakkZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTAyaTiZ5ctSubFNaNbNeAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTiTAyaZ5ctSubFNaNbNeAyaiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTiTkTiZ5ctSubFNaNbNeAyaikiZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTkTAyaZ5ctSubFNaNbNeAyakAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTAyaTkTiZ5ctSubFNaNbNeAyaAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTiTAyaTiZ5ctSubFNaNbNeAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTiTiTAyaZ5ctSubFNaNbNeAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTkTiTkTiZ5ctSubFNaNbNeAyakikiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTAyaTAyaTiZ5ctSubFNaNbNeAyaAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTiTiTAyaTiZ5ctSubFNaNbNeAyaiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTkTAyaTAyaZ5ctSubFNaNbNeAyakAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTkTAyaTkTiZ5ctSubFNaNbNeAyakAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTiTiTAyaZ5ctSubFNaNbNeAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTiTAyaTAyaTiZ5ctSubFNaNbNeAyaiAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTkTiTiTAyaTiZ5ctSubFNaNbNeAyakiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTAyaTiTiTAyaTiZ5ctSubFNaNbNeAyaAyaiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTkTAyaTAyaTAyaZ5ctSubFNaNbNeAyakAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTAyaTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyakiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10bwdMatcherMFNaNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10fwdMatcherMFNaNbNiNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10initializeMFNaNbNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10stackAvailMFNaNbNdNiNeZm@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher11__xopEqualsFKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher13matchFinalizeMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher4nextMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5atEndMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__ctorMFNaNbNcNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvwmZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__ctorMFNaNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6searchMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher8newStackMFNbNiNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9__xtoHashFNbNeKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZm@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9matchImplMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9prevStackMFNbNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9stackSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10bwdMatcherMFNaNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10fwdMatcherMFNaNbNiNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10initializeMFNaNbNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10stackAvailMFNaNbNdNiNeZm@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher11__xopEqualsFKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher13matchFinalizeMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher4nextMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5atEndMFNaNdNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__ctorMFNaNbNcNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvwmZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__ctorMFNaNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6searchMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher8newStackMFNbNiNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9__xtoHashFNbNeKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZm@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9matchImplMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9prevStackMFNbNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9stackSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal12backtracking30__T5ctSubTiTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTiTiTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiiiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking34__T5ctSubTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking36__T5ctSubTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking36__T5ctSubTiTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking38__T5ctSubTiTiTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiiiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking40__T5ctSubTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking42__T5ctSubTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking46__T5ctSubTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking50__T5ctSubTAyaTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking52__T5ctSubTiTAyaTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctAtomCodeMFAS3std5regex8internal2ir8BytecodeiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenBlockMFAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenGroupMFKAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenRegExMFAS3std5regex8internal2ir8BytecodeZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10lookaroundMFkkZS3std5regex8internal12backtracking9CtContext@Base 6
+ _D3std5regex8internal12backtracking9CtContext11ctQuickTestMFAS3std5regex8internal2ir8BytecodeiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext11restoreCodeMFZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext14ctGenFixupCodeMFAS3std5regex8internal2ir8BytecodeiiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext14ctGenFixupCodeMFKAS3std5regex8internal2ir8BytecodeiiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext16ctGenAlternationMFAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext6__initZ@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState11__xopEqualsFKxS3std5regex8internal12backtracking9CtContext7CtStateKxS3std5regex8internal12backtracking9CtContext7CtStateZb@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState9__xtoHashFNbNeKxS3std5regex8internal12backtracking9CtContext7CtStateZm@Base 6
+ _D3std5regex8internal12backtracking9CtContext8saveCodeMFkAyaZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext9ctGenAtomMFKAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal2ir10NamedGroup11__xopEqualsFKxS3std5regex8internal2ir10NamedGroupKxS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D3std5regex8internal2ir10NamedGroup9__xtoHashFNbNeKxS3std5regex8internal2ir10NamedGroupZm@Base 6
+ _D3std5regex8internal2ir10lengthOfIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir11RegexOption6__initZ@Base 6
+ _D3std5regex8internal2ir11disassembleFNexAS3std5regex8internal2ir8BytecodekxAS3std5regex8internal2ir10NamedGroupZAya@Base 6
+ _D3std5regex8internal2ir12__ModuleInfoZ@Base 6
+ _D3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper11__xopEqualsFKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper5atEndMFNaNdNfZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper5resetMFNaNbNiNfmZv@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__ctorMFNaNbNcNiNfS3std5regex8internal2ir12__T5InputTaZ5InputmZS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper7opSliceMFNaNbNiNfmmZAxa@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper8loopBackMFNaNbNiNfmZS3std5regex8internal2ir12__T5InputTaZ5Input@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper8nextCharMFNaNeKwKmZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZm@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper9lastIndexMFNaNbNdNiNfZm@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input11__xopEqualsFKxS3std5regex8internal2ir12__T5InputTaZ5InputKxS3std5regex8internal2ir12__T5InputTaZ5InputZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input5atEndMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input5resetMFNaNbNiNfmZv@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input66__T6searchTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZ6searchMFNaNfKS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrKwKmZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input6__ctorMFNaNbNcNiNfAxamZS3std5regex8internal2ir12__T5InputTaZ5Input@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input7opSliceMFNaNbNiNfmmZAxa@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input8loopBackMFNaNbNiNfmZS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input8nextCharMFNaNfKwKmZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5InputTaZ5InputZm@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input9lastIndexMFNaNbNdNiNfZm@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex11__xopEqualsFKxS3std5regex8internal2ir12__T5RegexTaZ5RegexKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNaNbNdNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange11__xopEqualsFKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange4backMFNaNbNdNiNfZAya@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange4saveMFNaNbNdNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange5frontMFNaNbNdNiNfZAya@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__ctorMFNaNbNcNiNfAS3std5regex8internal2ir10NamedGroupmmZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7opSliceMFNaNbNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7opSliceMFNaNbNiNfmmZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeZm@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex14checkIfOneShotMFZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex9isBackrefMFNaNbNiNfkZk@Base 6
+ _D3std5regex8internal2ir13wordCharacterFNdZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir14RegexException6__ctorMFNeAyaAyamZC3std5regex8internal2ir14RegexException@Base 6
+ _D3std5regex8internal2ir14RegexException6__initZ@Base 6
+ _D3std5regex8internal2ir14RegexException6__vtblZ@Base 6
+ _D3std5regex8internal2ir14RegexException7__ClassZ@Base 6
+ _D3std5regex8internal2ir14__T9endOfLineZ9endOfLineFNaNbNiNfwbZb@Base 6
+ _D3std5regex8internal2ir16lengthOfPairedIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir17__T11startOfLineZ11startOfLineFNaNbNiNfwbZb@Base 6
+ _D3std5regex8internal2ir17immediateParamsIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex11__xopEqualsFKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexZb@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__ctorMFNaNbNcNiNfS3std5regex8internal2ir12__T5RegexTaZ5RegexPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZbZS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__initZ@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex9__xtoHashFNbNeKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexZm@Base 6
+ _D3std5regex8internal2ir19__T11mallocArrayTmZ11mallocArrayFNbNimZAm@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZ11initializedb@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZ4slotS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir20__T12arrayInChunkTmZ12arrayInChunkFNaNbNimKAvZAm@Base 6
+ _D3std5regex8internal2ir2IR6__initZ@Base 6
+ _D3std5regex8internal2ir62__T12quickTestFwdTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ12quickTestFwdFNaNbNiNfkwKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZi@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZ11initializedb@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZ4slotS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir7getTrieFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir7isEndIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8Bytecode11indexOfPairMxFkZk@Base 6
+ _D3std5regex8internal2ir8Bytecode11setLocalRefMFZv@Base 6
+ _D3std5regex8internal2ir8Bytecode12pairedLengthMxFNdZk@Base 6
+ _D3std5regex8internal2ir8Bytecode13__T8mnemonicZ8mnemonicMxFNaNdNeZAya@Base 6
+ _D3std5regex8internal2ir8Bytecode13__T8sequenceZ8sequenceMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir8Bytecode13backreferenceMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode14setBackrefenceMFZv@Base 6
+ _D3std5regex8internal2ir8Bytecode4argsMxFNdZi@Base 6
+ _D3std5regex8internal2ir8Bytecode5isEndMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode6__ctorMFNcE3std5regex8internal2ir2IRkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode6__ctorMFNcE3std5regex8internal2ir2IRkkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D3std5regex8internal2ir8Bytecode6isAtomMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode6lengthMxFNdZk@Base 6
+ _D3std5regex8internal2ir8Bytecode6pairedMxFNdZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode7fromRawFkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode7hotspotMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode7isStartMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode8localRefMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode9__T4codeZ4codeMxFNaNbNdNiNfZE3std5regex8internal2ir2IR@Base 6
+ _D3std5regex8internal2ir8Bytecode9__T4dataZ4dataMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir8hasMergeFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8isAtomIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8pairedIRFE3std5regex8internal2ir2IRZE3std5regex8internal2ir2IR@Base 6
+ _D3std5regex8internal2ir8wordTrieFNdZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir9RegexInfo6__initZ@Base 6
+ _D3std5regex8internal2ir9isStartIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir9trieCacheHS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal5tests12__ModuleInfoZ@Base 6
+ _D3std5regex8internal6parser11caseEncloseFNaS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser12__ModuleInfoZ@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack11__xopEqualsFKxS3std5regex8internal6parser12__T5StackTkZ5StackKxS3std5regex8internal6parser12__T5StackTkZ5StackZb@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack3popMFNbNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack3topMFNaNbNcNdNiNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack4pushMFNaNbNekZv@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack6lengthMFNaNbNdNiNeZm@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser12__T5StackTkZ5StackZm@Base 6
+ _D3std5regex8internal6parser13getUnicodeSetFNexAabbZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser10parseRegexMFNeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11__xopEqualsFKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11charsetToIrMFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11isOpenGroupMFNaNbNiNfkZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11markBackrefMFNaNbNfkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11parseEscapeMFNeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ101__T11unrollWhileS813std10functional54__T8unaryFunVAyaa12_61203d3d20612e556e696f6eVAyaa1_61Z8unaryFunZ11unrollWhileFNfKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ5applyFNfE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ99__T11unrollWhileS793std10functional52__T8unaryFunVAyaa11_6120213d20612e4f70656eVAyaa1_61Z8unaryFunZ11unrollWhileFNfKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseDecimalMFNfZk@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13fixLookaroundMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13genLookaroundMFE3std5regex8internal2ir2IRZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ12addWithFlagsFNaNbKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListkkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ18twinSymbolOperatorFNaNbNiNfwZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser15__T6__ctorTAxaZ6__ctorMFNcNeAyaAxaZS3std5regex8internal6parser15__T6ParserTAyaZ6Parser@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser15parseQuantifierMFNekZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser16parseControlCodeMFNaNfZw@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser17finishAlternationMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser20__T10parseFlagsTAxaZ10parseFlagsMFNeAxaZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser24parseUnicodePropertySpecMFNfbZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser3putMFNaNfS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser4nextMFNaNfZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser5_nextMFNaNfZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser5errorMFNeAyaZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser6__initZ@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser6putRawMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser7currentMFNaNbNdNiNfZw@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser7programMFNdNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9__xtoHashFNbNeKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZm@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9parseAtomMFZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9skipSpaceMFNaNfZv@Base 6
+ _D3std5regex8internal6parser18__T9makeRegexTAyaZ9makeRegexFNfS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex8internal6parser20__T11parseUniHexTyaZ11parseUniHexFNaNfKAyamZw@Base 6
+ _D3std5regex8internal6parser21__T15reverseBytecodeZ15reverseBytecodeFNeAS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack11__xopEqualsFKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackZb@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack3popMFNaNbNiNfZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack3topMFNaNbNcNdNiNfZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack4pushMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack6__initZ@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack9__xtoHashFNbNeKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackZm@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZv@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack11__xopEqualsFKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackZb@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack3popMFNbNeZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack3topMFNaNbNcNdNiNeZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack4pushMFNaNbNeS3std8typecons16__T5TupleTkTkTkZ5TupleZv@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6lengthMFNaNbNdNiNeZm@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackZm@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack11__xopEqualsFKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack3popMFNbNeZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack3topMFNaNbNcNdNiNeZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack4pushMFNaNbNeE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZv@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6lengthMFNaNbNdNiNeZm@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZm@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack11__xopEqualsFKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZb@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack3popMFNbNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack3topMFNaNbNcNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack4pushMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZv@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6lengthMFNaNbNdNiNeZm@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZm@Base 6
+ _D3std5regex8internal6parser7getTrieFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal6parser9trieCacheHS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal8thompson12__ModuleInfoZ@Base 6
+ _D3std5regex8internal8thompson13__T6ThreadTmZ6Thread6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList10insertBackMFNaNbNiNfPS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange5frontMFNaNbNdNiNfZPxS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange6__ctorMFNaNbNcNiNfS3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadListZS3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange8popFrontMFNaNbNdNiNfZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11insertFrontMFNaNbNiNfPS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList5fetchMFNaNbNiNfZPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList7opSliceMFNaNbNiNfZS3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11__xopEqualsFKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11createStartMFNaNbNiNemkZPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher12matchOneShotMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupkZE3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11MatchResult@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13__T4evalVbi0Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadAS3std5regex8internal2ir12__T5GroupTmZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13__T4evalVbi1Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadAS3std5regex8internal2ir12__T5GroupTmZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13getThreadSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher15prepareFreeListMFNaNbNiNemKAvZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher16__T10bwdMatcherZ10bwdMatcherMFNaNeAS3std5regex8internal2ir8BytecodemZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher16__T10fwdMatcherZ10fwdMatcherMFNaNbNiNeAS3std5regex8internal2ir8BytecodemZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18__T9matchImplVbi0Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18__T9matchImplVbi1Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher4forkMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadkkZPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher4nextMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher55__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5InputZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5InputZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5atEndMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher67__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5InputZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6finishMFNaNbNiNePxS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadAS3std5regex8internal2ir12__T5GroupTmZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6searchMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7recycleMFNaNbNiNeKS3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadListZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7recycleMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher8allocateMFNaNbNiNeZPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher9__xtoHashFNbNeKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherZm@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11__xopEqualsFKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11createStartMFNaNbNiNemkZPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher12matchOneShotMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupkZE3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11MatchResult@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13__T4evalVbi0Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadAS3std5regex8internal2ir12__T5GroupTmZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13__T4evalVbi1Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadAS3std5regex8internal2ir12__T5GroupTmZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13getThreadSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZm@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher15prepareFreeListMFNaNbNiNemKAvZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher16__T10bwdMatcherZ10bwdMatcherMFNaNeAS3std5regex8internal2ir8BytecodemZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher16__T10fwdMatcherZ10fwdMatcherMFNaNbNiNeAS3std5regex8internal2ir8BytecodemZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher18__T9matchImplVbi0Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher4forkMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadkkZPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher4nextMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher55__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5InputZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5atEndMFNaNdNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTmZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher67__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6__initZ@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6finishMFNaNbNiNePxS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadAS3std5regex8internal2ir12__T5GroupTmZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7recycleMFNaNbNiNeKS3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadListZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7recycleMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTmZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher8allocateMFNaNbNiNeZPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher9__xtoHashFNbNeKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherZm@Base 6
+ _D3std5regex8internal9generator12__ModuleInfoZ@Base 6
+ _D3std5regex8internal9kickstart12__ModuleInfoZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread105__T3setS94_D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread10setInvMaskMFNaNbNiNfkkZvZ3setMFNaNfwZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread10setInvMaskMFNaNbNiNfkkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread11__xopEqualsFKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread3addMFNaNfwZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread4fullMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__ctorMFNaNbNcNiNfkkAkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread7advanceMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread7setMaskMFNaNbNiNfkkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread9__xtoHashFNbNeKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZm@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11__xopEqualsFKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr4forkFNaNbNiNfS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadkkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr5fetchFNbNeKAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__ctorMFNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexAkZ10codeBoundsyAi@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__ctorMFNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexAkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6searchMFNaNeAxamZm@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr7charLenFNaNbNiNfkZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr9__xtoHashFNbNeKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZm@Base 6
+ _D3std5regex8internal9kickstart21__T13effectiveSizeTaZ13effectiveSizeFNaNbNiNfZk@Base 6
+ _D3std5stdio10ChunksImpl11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio10ChunksImpl11__xopEqualsFKxS3std5stdio10ChunksImplKxS3std5stdio10ChunksImplZb@Base 6
+ _D3std5stdio10ChunksImpl15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio10ChunksImpl6__ctorMFNcS3std5stdio4FilemZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio10ChunksImpl6__initZ@Base 6
+ _D3std5stdio10ChunksImpl8opAssignMFNcNjNeS3std5stdio10ChunksImplZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio10ChunksImpl9__xtoHashFNbNeKxS3std5stdio10ChunksImplZm@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZ1nm@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZ7lineptrPa@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZm@Base 6
+ _D3std5stdio11openNetworkFAyatZS3std5stdio4File@Base 6
+ _D3std5stdio12__ModuleInfoZ@Base 6
+ _D3std5stdio13trustedStdoutFNdNeZS3std5stdio4File@Base 6
+ _D3std5stdio14StdioException6__ctorMFAyakZC3std5stdio14StdioException@Base 6
+ _D3std5stdio14StdioException6__initZ@Base 6
+ _D3std5stdio14StdioException6__vtblZ@Base 6
+ _D3std5stdio14StdioException6opCallFAyaZv@Base 6
+ _D3std5stdio14StdioException6opCallFZv@Base 6
+ _D3std5stdio14StdioException7__ClassZ@Base 6
+ _D3std5stdio17LockingTextReader10__aggrDtorMFZv@Base 6
+ _D3std5stdio17LockingTextReader10__postblitMFZv@Base 6
+ _D3std5stdio17LockingTextReader11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio17LockingTextReader11__xopEqualsFKxS3std5stdio17LockingTextReaderKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std5stdio17LockingTextReader14__aggrPostblitMFZv@Base 6
+ _D3std5stdio17LockingTextReader15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio17LockingTextReader5emptyMFNdZb@Base 6
+ _D3std5stdio17LockingTextReader5frontMFNdZw@Base 6
+ _D3std5stdio17LockingTextReader6__ctorMFNcS3std5stdio4FileZS3std5stdio17LockingTextReader@Base 6
+ _D3std5stdio17LockingTextReader6__dtorMFZv@Base 6
+ _D3std5stdio17LockingTextReader6__initZ@Base 6
+ _D3std5stdio17LockingTextReader8opAssignMFS3std5stdio17LockingTextReaderZv@Base 6
+ _D3std5stdio17LockingTextReader8popFrontMFZv@Base 6
+ _D3std5stdio17LockingTextReader9__xtoHashFNbNeKxS3std5stdio17LockingTextReaderZm@Base 6
+ _D3std5stdio17LockingTextReader9readFrontMFZv@Base 6
+ _D3std5stdio17LockingTextReader9takeFrontMFNkKG4aZAa@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ10stderrImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ10stdoutImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ9stdinImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio4File10__postblitMFNbNfZv@Base 6
+ _D3std5stdio4File11__xopEqualsFKxS3std5stdio4FileKxS3std5stdio4FileZb@Base 6
+ _D3std5stdio4File13__T6readlnTaZ6readlnMFKAawZm@Base 6
+ _D3std5stdio4File14__T7rawReadTaZ7rawReadMFAaZAa@Base 6
+ _D3std5stdio4File14__T7rawReadTbZ7rawReadMFAbZAb@Base 6
+ _D3std5stdio4File14__T7rawReadThZ7rawReadMFAhZAh@Base 6
+ _D3std5stdio4File14__T7rawReadTiZ7rawReadMFAiZAi@Base 6
+ _D3std5stdio4File14__T7rawReadTlZ7rawReadMFAlZAl@Base 6
+ _D3std5stdio4File15__T6readlnTAyaZ6readlnMFwZAya@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNbNiNfaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNfaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNfaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNbNiNfwZv@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNfwZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNfwZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__postblitMFNeZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTAaZ3putMFAaZ13trustedFwriteFNbNiNexPvmmPOS4core4stdc5stdio8_IO_FILEZm@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTAaZ3putMFNfAaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNbNiNfxaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNfxaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNfxaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNbNiNfxwZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNfxwZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNfxwZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNbNiNfyaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNfyaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNfyaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAxaZ3putMFAxaZ13trustedFwriteFNbNiNexPvmmPOS4core4stdc5stdio8_IO_FILEZm@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAxaZ3putMFNfAxaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAyaZ3putMFAyaZ13trustedFwriteFNbNiNexPvmmPOS4core4stdc5stdio8_IO_FILEZm@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAyaZ3putMFNfAyaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter6__ctorMFNcNeKS3std5stdio4FileZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File17LockingTextWriter6__dtorMFNeZv@Base 6
+ _D3std5stdio4File17LockingTextWriter6__initZ@Base 6
+ _D3std5stdio4File17LockingTextWriter8opAssignMFNcNjNeS3std5stdio4File17LockingTextWriterZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File17lockingTextWriterMFNfZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File3eofMxFNaNdNeZb@Base 6
+ _D3std5stdio4File4Impl6__initZ@Base 6
+ _D3std5stdio4File4lockMFE3std5stdio8LockTypemmZv@Base 6
+ _D3std5stdio4File4nameMxFNaNbNdNfZAya@Base 6
+ _D3std5stdio4File4openMFNfAyaxAaZv@Base 6
+ _D3std5stdio4File4seekMFNeliZv@Base 6
+ _D3std5stdio4File4sizeMFNdNfZm@Base 6
+ _D3std5stdio4File4syncMFNeZv@Base 6
+ _D3std5stdio4File4tellMxFNdNeZm@Base 6
+ _D3std5stdio4File5closeMFNeZv@Base 6
+ _D3std5stdio4File5errorMxFNaNbNdNeZb@Base 6
+ _D3std5stdio4File5flushMFNeZv@Base 6
+ _D3std5stdio4File5getFPMFNaNfZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio4File5popenMFNfAyaxAaZv@Base 6
+ _D3std5stdio4File6__ctorMFNcNePOS4core4stdc5stdio8_IO_FILEAyakbZS3std5stdio4File@Base 6
+ _D3std5stdio4File6__ctorMFNcNfAyaxAaZS3std5stdio4File@Base 6
+ _D3std5stdio4File6__dtorMFNfZv@Base 6
+ _D3std5stdio4File6__initZ@Base 6
+ _D3std5stdio4File6detachMFNfZv@Base 6
+ _D3std5stdio4File6fdopenMFNeixAaAyaZv@Base 6
+ _D3std5stdio4File6fdopenMFNfixAaZv@Base 6
+ _D3std5stdio4File6filenoMxFNdNeZi@Base 6
+ _D3std5stdio4File6isOpenMxFNaNbNdNfZb@Base 6
+ _D3std5stdio4File6rewindMFNfZv@Base 6
+ _D3std5stdio4File6unlockMFmmZv@Base 6
+ _D3std5stdio4File7ByChunk11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio4File7ByChunk11__xopEqualsFKxS3std5stdio4File7ByChunkKxS3std5stdio4File7ByChunkZb@Base 6
+ _D3std5stdio4File7ByChunk15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio4File7ByChunk5emptyMxFNbNdZb@Base 6
+ _D3std5stdio4File7ByChunk5frontMFNbNdZAh@Base 6
+ _D3std5stdio4File7ByChunk5primeMFZv@Base 6
+ _D3std5stdio4File7ByChunk6__ctorMFNcS3std5stdio4FileAhZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk6__ctorMFNcS3std5stdio4FilemZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk6__initZ@Base 6
+ _D3std5stdio4File7ByChunk8opAssignMFNcNjNeS3std5stdio4File7ByChunkZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk8popFrontMFZv@Base 6
+ _D3std5stdio4File7ByChunk9__xtoHashFNbNeKxS3std5stdio4File7ByChunkZm@Base 6
+ _D3std5stdio4File7byChunkMFAhZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7byChunkMFmZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7setvbufMFNeAviZv@Base 6
+ _D3std5stdio4File7setvbufMFNemiZv@Base 6
+ _D3std5stdio4File7tmpfileFNfZS3std5stdio4File@Base 6
+ _D3std5stdio4File7tryLockMFE3std5stdio8LockTypemmZb@Base 6
+ _D3std5stdio4File8clearerrMFNaNbNfZv@Base 6
+ _D3std5stdio4File8lockImplMFismmZi@Base 6
+ _D3std5stdio4File8opAssignMFNfS3std5stdio4FileZv@Base 6
+ _D3std5stdio4File8wrapFileFNfPOS4core4stdc5stdio8_IO_FILEZS3std5stdio4File@Base 6
+ _D3std5stdio4File9__xtoHashFNbNeKxS3std5stdio4FileZm@Base 6
+ _D3std5stdio5fopenFNbNiNexAaxAaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio5lines11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio5lines11__xopEqualsFKxS3std5stdio5linesKxS3std5stdio5linesZb@Base 6
+ _D3std5stdio5lines15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio5lines6__ctorMFNcS3std5stdio4FilewZS3std5stdio5lines@Base 6
+ _D3std5stdio5lines6__initZ@Base 6
+ _D3std5stdio5lines8opAssignMFNcNjNeS3std5stdio5linesZS3std5stdio5lines@Base 6
+ _D3std5stdio5lines9__xtoHashFNbNeKxS3std5stdio5linesZm@Base 6
+ _D3std5stdio5popenFNbNiNexAaxAaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio5stdinS3std5stdio4File@Base 6
+ _D3std5stdio6chunksFS3std5stdio4FilemZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio6stderrS3std5stdio4File@Base 6
+ _D3std5stdio6stdoutS3std5stdio4File@Base 6
+ _D3std6base6412__ModuleInfoZ@Base 6
+ _D3std6base6415Base64Exception6__ctorMFNaNbNfAyaAyamZC3std6base6415Base64Exception@Base 6
+ _D3std6base6415Base64Exception6__initZ@Base 6
+ _D3std6base6415Base64Exception6__vtblZ@Base 6
+ _D3std6base6415Base64Exception7__ClassZ@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z12decodeLengthFNaNbNfxmZm@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z12encodeLengthFNaNbNfxmZm@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z9DecodeMapyG256i@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z9EncodeMapyAa@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z12decodeLengthFNaNbNfxmZm@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z12encodeLengthFNaNbNfxmZm@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z9DecodeMapyG256i@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z9EncodeMapyAa@Base 6
+ _D3std6bigint12__ModuleInfoZ@Base 6
+ _D3std6bigint15toDecimalStringFxS3std6bigint6BigIntZAya@Base 6
+ _D3std6bigint5toHexFxS3std6bigint6BigIntZAya@Base 6
+ _D3std6bigint6BigInt10isNegativeMxFNaNbNiNfZb@Base 6
+ _D3std6bigint6BigInt10uintLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std6bigint6BigInt11__xopEqualsFKxS3std6bigint6BigIntKxS3std6bigint6BigIntZb@Base 6
+ _D3std6bigint6BigInt11ulongLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std6bigint6BigInt13__T8opEqualsZ8opEqualsMxFNaNbNiNfKxS3std6bigint6BigIntZb@Base 6
+ _D3std6bigint6BigInt14checkDivByZeroMxFNaNbNfZv@Base 6
+ _D3std6bigint6BigInt31__T5opCmpHTS3std6bigint6BigIntZ5opCmpMxFNaNbNiNfxS3std6bigint6BigIntZi@Base 6
+ _D3std6bigint6BigInt5opCmpMxFNaNbNiKxS3std6bigint6BigIntZi@Base 6
+ _D3std6bigint6BigInt5toIntMxFNaNbNiNfZi@Base 6
+ _D3std6bigint6BigInt6__initZ@Base 6
+ _D3std6bigint6BigInt6isZeroMxFNaNbNiNfZb@Base 6
+ _D3std6bigint6BigInt6negateMFNaNbNiNfZv@Base 6
+ _D3std6bigint6BigInt6toHashMxFNbNfZm@Base 6
+ _D3std6bigint6BigInt6toLongMxFNaNbNiNfZl@Base 6
+ _D3std6bigint6BigInt8toStringMxFMDFAxaZvAyaZv@Base 6
+ _D3std6bigint6BigInt8toStringMxFMDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6digest2md10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest2md12__ModuleInfoZ@Base 6
+ _D3std6digest2md3MD51FFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD52FFFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52GGFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52HHFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52IIFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD53putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest2md3MD55startMFNaNbNiNfZv@Base 6
+ _D3std6digest2md3MD56__initZ@Base 6
+ _D3std6digest2md3MD56finishMFNaNbNiNeZG16h@Base 6
+ _D3std6digest2md3MD58_paddingyG64h@Base 6
+ _D3std6digest2md3MD59transformMFNaNbNiPxG64hZv@Base 6
+ _D3std6digest3crc11crc32_tableyG256k@Base 6
+ _D3std6digest3crc12__ModuleInfoZ@Base 6
+ _D3std6digest3crc5CRC323putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3crc5CRC324peekMxFNaNbNiNfZG4h@Base 6
+ _D3std6digest3crc5CRC325startMFNaNbNiNfZv@Base 6
+ _D3std6digest3crc5CRC326__initZ@Base 6
+ _D3std6digest3crc5CRC326finishMFNaNbNiNfZG4h@Base 6
+ _D3std6digest3sha10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest3sha11rotateRightFNaNbNiNfkkZk@Base 6
+ _D3std6digest3sha11rotateRightFNaNbNiNfmkZm@Base 6
+ _D3std6digest3sha12__ModuleInfoZ@Base 6
+ _D3std6digest3sha17bigEndianToNativeFNaNbNiNeG4hZk@Base 6
+ _D3std6digest3sha17bigEndianToNativeFNaNbNiNeG8hZm@Base 6
+ _D3std6digest3sha17nativeToBigEndianFNaNbNiNekZG4h@Base 6
+ _D3std6digest3sha17nativeToBigEndianFNaNbNiNemZG8h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6finishMFNaNbNiNeZG20h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6finishMFNaNbNiNeZG48h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6finishMFNaNbNiNeZG64h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9constantsyG80m@Base 6
+ _D3std6digest6digest12__ModuleInfoZ@Base 6
+ _D3std6digest6digest18__T7asArrayVmi4ThZ7asArrayFNaNbNcNiKAhAyaZG4h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi16ThZ7asArrayFNaNbNcNiKAhAyaZG16h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi20ThZ7asArrayFNaNbNcNiKAhAyaZG20h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi28ThZ7asArrayFNaNbNcNiKAhAyaZG28h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi32ThZ7asArrayFNaNbNcNiKAhAyaZG32h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi48ThZ7asArrayFNaNbNcNiKAhAyaZG48h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi64ThZ7asArrayFNaNbNcNiKAhAyaZG64h@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest6Digest11__InterfaceZ@Base 6
+ _D3std6digest6digest6Digest6digestMFNbNeMAxAvXAh@Base 6
+ _D3std6digest6digest71__T11toHexStringVE3std6digest6digest5Orderi1VE3std5ascii10LetterCasei0Z11toHexStringFNaNbxAhZAya@Base 6
+ _D3std6digest6digest76__T11toHexStringVE3std6digest6digest5Orderi1Vmi16VE3std5ascii10LetterCasei0Z11toHexStringFNaNbNiNfxG16hZG32a@Base 6
+ _D3std6digest6ripemd10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest6ripemd12__ModuleInfoZ@Base 6
+ _D3std6digest6ripemd9RIPEMD1601FFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601JFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1602FFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602GGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602HHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602IIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602JJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603FFFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603GGGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603HHHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603IIIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603JJJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest6ripemd9RIPEMD1605startMFNaNbNiNfZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1606__initZ@Base 6
+ _D3std6digest6ripemd9RIPEMD1606finishMFNaNbNiNeZG20h@Base 6
+ _D3std6digest6ripemd9RIPEMD1608_paddingyG64h@Base 6
+ _D3std6digest6ripemd9RIPEMD1609transformMFNaNbNiPxG64hZv@Base 6
+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmbAyaAyaE3std3net7isemail15EmailStatusCodeZv@Base 6
+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmbAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T7gencodeVmi4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZk@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda13FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda15FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda17FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda14TkZ10__lambda14FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda16TkZ10__lambda16FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda18TkZ10__lambda18FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ19__T10__lambda10TykZ10__lambda10FNaNbNiNeKykZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ19__T10__lambda12TykZ10__lambda12FNaNbNiNeKykZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZk@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T9__lambda9TbZ9__lambda9FNaNbNiNeKbZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ20__T10__lambda11TAyaZ10__lambda11FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ20__T10__lambda13TAyaZ10__lambda13FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ51__T10__lambda15TE3std3net7isemail15EmailStatusCodeZ10__lambda15FNaNbNiNeKE3std3net7isemail15EmailStatusCodeZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format111__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std3net4curl20AsyncChunkInputRange8__mixin55StateKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format113__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format117__T6formatTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6formatFNaNfxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZAya@Base 6
+ _D3std6format118__T9getNthIntTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9getNthIntFNaNfkE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std6format12__ModuleInfoZ@Base 6
+ _D3std6format137__T22enforceValidFormatSpecTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoG1S3gcc8builtins13__va_list_tagZ6skipCIFNaNbNiNfC8TypeInfoZC8TypeInfo@Base 6
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoG1S3gcc8builtins13__va_list_tagZ9formatArgMFaZ6getManFNaNbNiNfC8TypeInfoZE3std6format6Mangle@Base 6
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoG1S3gcc8builtins13__va_list_tagZv@Base 6
+ _D3std6format14__T9getNthIntZ9getNthIntFNaNfkZi@Base 6
+ _D3std6format15FormatException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std6format15FormatException@Base 6
+ _D3std6format15FormatException6__ctorMFNaNbNfZC3std6format15FormatException@Base 6
+ _D3std6format15FormatException6__initZ@Base 6
+ _D3std6format15FormatException6__vtblZ@Base 6
+ _D3std6format15FormatException7__ClassZ@Base 6
+ _D3std6format15__T6formatTaTiZ6formatFNaNfxAaiZAya@Base 6
+ _D3std6format15__T6formatTaTkZ6formatFNaNfxAakZAya@Base 6
+ _D3std6format15__T6formatTaTmZ6formatFNaNfxAamZAya@Base 6
+ _D3std6format15__T6formatTaTwZ6formatFNaNfxAawZAya@Base 6
+ _D3std6format160__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZv@Base 6
+ _D3std6format160__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format166__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZk@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ66__T9__lambda7TE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda7FNaNbNiNeKE3std3net4curl20AsyncChunkInputRange8__mixin55StateZxPv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ66__T9__lambda9TE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda9FNaNbNiNeKE3std3net4curl20AsyncChunkInputRange8__mixin55StateZxPv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format167__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format16__T6formatTaTxsZ6formatFNaNfxAaxsZAya@Base 6
+ _D3std6format16__T9getNthIntTaZ9getNthIntFNaNfkaZi@Base 6
+ _D3std6format16__T9getNthIntTiZ9getNthIntFNaNfkiZi@Base 6
+ _D3std6format16__T9getNthIntTkZ9getNthIntFNaNfkkZi@Base 6
+ _D3std6format16__T9getNthIntTmZ9getNthIntFNaNfkmZi@Base 6
+ _D3std6format16__T9getNthIntTtZ9getNthIntFNaNfktZi@Base 6
+ _D3std6format16__T9getNthIntTwZ9getNthIntFNaNfkwZi@Base 6
+ _D3std6format17__T6formatTaTAyaZ6formatFNaNfxAaAyaZAya@Base 6
+ _D3std6format17__T6formatTaTiTiZ6formatFNaNfxAaiiZAya@Base 6
+ _D3std6format17__T6formatTaTmTmZ6formatFNaNfxAammZAya@Base 6
+ _D3std6format17__T9getNthIntTPvZ9getNthIntFNaNfkPvZi@Base 6
+ _D3std6format17__T9getNthIntTxhZ9getNthIntFNaNfkxhZi@Base 6
+ _D3std6format17__T9getNthIntTxkZ9getNthIntFNaNfkxkZi@Base 6
+ _D3std6format17__T9getNthIntTxmZ9getNthIntFNaNfkxmZi@Base 6
+ _D3std6format17__T9getNthIntTxsZ9getNthIntFNaNfkxsZi@Base 6
+ _D3std6format17primitiveTypeInfoFE3std6format6MangleZ3dicHE3std6format6MangleC8TypeInfo@Base 6
+ _D3std6format17primitiveTypeInfoFE3std6format6MangleZC8TypeInfo@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec11__xopEqualsFKxS3std6format18__T10FormatSpecTaZ10FormatSpecKxS3std6format18__T10FormatSpecTaZ10FormatSpecZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec12getCurFmtStrMxFNaNfZAya@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec16headUpToNextSpecMFNaZAxa@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec31__T17writeUpToNextSpecTDFAxaZvZ17writeUpToNextSpecMFDFAxaZvZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec37__T17writeUpToNextSpecTDFNaNbNfAxaZvZ17writeUpToNextSpecMFNaNfDFNaNbNfAxaZvZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec59__T17writeUpToNextSpecTS3std5stdio4File17LockingTextWriterZ17writeUpToNextSpecMFNfS3std5stdio4File17LockingTextWriterZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec63__T17writeUpToNextSpecTS3std5array17__T8AppenderTAyaZ8AppenderZ17writeUpToNextSpecMFNaNfS3std5array17__T8AppenderTAyaZ8AppenderZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec63__T17writeUpToNextSpecTS3std5array17__T8AppenderTyAaZ8AppenderZ17writeUpToNextSpecMFNaNfS3std5array17__T8AppenderTyAaZ8AppenderZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6__ctorMFNaNbNcNiNfxAaZS3std6format18__T10FormatSpecTaZ10FormatSpec@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6__initZ@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6fillUpMFNaNfZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flDashMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flDashMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flHashMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flHashMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flPlusMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flPlusMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flZeroMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flZeroMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec7flSpaceMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec7flSpaceMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec8toStringMFNaNfZAya@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec91__T17writeUpToNextSpecTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkZ17writeUpToNextSpecMFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec9__xtoHashFNbNeKxS3std6format18__T10FormatSpecTaZ10FormatSpecZm@Base 6
+ _D3std6format18__T6formatTaTAyAaZ6formatFNaNfxAaAyAaZAya@Base 6
+ _D3std6format18__T9getNthIntTAxaZ9getNthIntFNaNfkAxaZi@Base 6
+ _D3std6format18__T9getNthIntTAyaZ9getNthIntFNaNfkAyaZi@Base 6
+ _D3std6format18__T9getNthIntThTiZ9getNthIntFNaNfkhiZi@Base 6
+ _D3std6format18__T9getNthIntTiTiZ9getNthIntFNaNfkiiZi@Base 6
+ _D3std6format18__T9getNthIntTkTkZ9getNthIntFNaNfkkkZi@Base 6
+ _D3std6format18__T9getNthIntTmTmZ9getNthIntFNaNfkmmZi@Base 6
+ _D3std6format18__T9getNthIntTtTtZ9getNthIntFNaNfkttZi@Base 6
+ _D3std6format18__T9getNthIntTwTkZ9getNthIntFNaNfkwkZi@Base 6
+ _D3std6format19__T6formatTaTAaTPvZ6formatFNaNfxAaAaPvZAya@Base 6
+ _D3std6format19__T6formatTaTAyaTkZ6formatFNaNfxAaAyakZAya@Base 6
+ _D3std6format19__T6formatTaTAyaTmZ6formatFNaNfxAaAyamZAya@Base 6
+ _D3std6format19__T6formatTaTxmTxmZ6formatFNaNfxAaxmxmZAya@Base 6
+ _D3std6format19__T9getNthIntTAyAaZ9getNthIntFNaNfkAyAaZi@Base 6
+ _D3std6format20__T9getNthIntTAaTPvZ9getNthIntFNaNfkAaPvZi@Base 6
+ _D3std6format20__T9getNthIntTAxhTaZ9getNthIntFNaNfkAxhaZi@Base 6
+ _D3std6format20__T9getNthIntTAyaTiZ9getNthIntFNaNfkAyaiZi@Base 6
+ _D3std6format20__T9getNthIntTAyaTkZ9getNthIntFNaNfkAyakZi@Base 6
+ _D3std6format20__T9getNthIntTAyaTmZ9getNthIntFNaNfkAyamZi@Base 6
+ _D3std6format20__T9getNthIntThThTiZ9getNthIntFNaNfkhhiZi@Base 6
+ _D3std6format20__T9getNthIntTkTAyaZ9getNthIntFNaNfkkAyaZi@Base 6
+ _D3std6format20__T9getNthIntTkTkTkZ9getNthIntFNaNfkkkkZi@Base 6
+ _D3std6format20__T9getNthIntTwTkTkZ9getNthIntFNaNfkwkkZi@Base 6
+ _D3std6format20__T9getNthIntTxhTxhZ9getNthIntFNaNfkxhxhZi@Base 6
+ _D3std6format20__T9getNthIntTxkTxkZ9getNthIntFNaNfkxkxkZi@Base 6
+ _D3std6format20__T9getNthIntTxmTxmZ9getNthIntFNaNfkxmxmZi@Base 6
+ _D3std6format21__T6formatTaTAxaTAxaZ6formatFNaNfxAaAxaAxaZAya@Base 6
+ _D3std6format21__T6formatTaTAyaTAyaZ6formatFNaNfxAaAyaAyaZAya@Base 6
+ _D3std6format21__T6formatTaTAyaTkTkZ6formatFNaNfxAaAyakkZAya@Base 6
+ _D3std6format21__T9getNthIntTAyaTxhZ9getNthIntFNaNfkAyaxhZi@Base 6
+ _D3std6format22__T6formatTaTxhTxhTxhZ6formatFNaNfxAaxhxhxhZAya@Base 6
+ _D3std6format22__T9getNthIntTAxaTAxaZ9getNthIntFNaNfkAxaAxaZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTAyaZ9getNthIntFNaNfkAyaAyaZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTkTkZ9getNthIntFNaNfkAyakkZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTtTtZ9getNthIntFNaNfkAyattZi@Base 6
+ _D3std6format22__T9getNthIntThThThTiZ9getNthIntFNaNfkhhhiZi@Base 6
+ _D3std6format23__T6formatTaTAyaTAyaTmZ6formatFNaNfxAaAyaAyamZAya@Base 6
+ _D3std6format23__T6formatTaTAyaTkTAyaZ6formatFNaNfxAaAyakAyaZAya@Base 6
+ _D3std6format23__T6formatTaTtTAyaTtTtZ6formatFNaNfxAatAyattZAya@Base 6
+ _D3std6format23__T6formatTaTxsTAyaTxhZ6formatFNaNfxAaxsAyaxhZAya@Base 6
+ _D3std6format23__T9getNthIntTxhTxhTxhZ9getNthIntFNaNfkxhxhxhZi@Base 6
+ _D3std6format23__T9getNthIntTxkTxkTxkZ9getNthIntFNaNfkxkxkxkZi@Base 6
+ _D3std6format23__T9getNthIntTykTkTkTkZ9getNthIntFNaNfkykkkkZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTAyaTiZ9getNthIntFNaNfkAyaAyaiZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTAyaTmZ9getNthIntFNaNfkAyaAyamZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTkTAyaZ9getNthIntFNaNfkAyakAyaZi@Base 6
+ _D3std6format24__T9getNthIntThThThThTiZ9getNthIntFNaNfkhhhhiZi@Base 6
+ _D3std6format24__T9getNthIntTmTAyaTAyaZ9getNthIntFNaNfkmAyaAyaZi@Base 6
+ _D3std6format24__T9getNthIntTtTAyaTtTtZ9getNthIntFNaNfktAyattZi@Base 6
+ _D3std6format24__T9getNthIntTxsTAyaTxhZ9getNthIntFNaNfkxsAyaxhZi@Base 6
+ _D3std6format25__T6formatTaTAyaTAyaTAyaZ6formatFNaNfxAaAyaAyaAyaZAya@Base 6
+ _D3std6format25__T6formatTaTxhTxhTxhTxhZ6formatFNaNfxAaxhxhxhxhZAya@Base 6
+ _D3std6format25__T9getNthIntTkTxkTxkTxkZ9getNthIntFNaNfkkxkxkxkZi@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNbNfAxaZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfAxuZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfAxwZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfwZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink6__initZ@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFNaNfAaxAaykykkkkZAa@Base 6
+ _D3std6format26__T9getNthIntTAyaTAyaTAyaZ9getNthIntFNaNfkAyaAyaAyaZi@Base 6
+ _D3std6format26__T9getNthIntTxhTxhTxhTxhZ9getNthIntFNaNfkxhxhxhxhZi@Base 6
+ _D3std6format26__T9getNthIntTykTykTkTkTkZ9getNthIntFNaNfkykykkkkZi@Base 6
+ _D3std6format28__T9getNthIntTAyaTmTAyaTAyaZ9getNthIntFNaNfkAyamAyaAyaZi@Base 6
+ _D3std6format29__T11formatValueTDFAxaZvTkTaZ11formatValueFDFAxaZvkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format29__T11formatValueTDFAxaZvTkTaZ11formatValueFDFAxaZvkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxeTaZ11formatValueFDFAxaZvxeKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxeZ9__lambda4FNaNbNiNeKxeZAxa@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxeTaZ11formatValueFDFAxaZvxeKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxmTaZ11formatValueFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxmZ9__lambda4FNaNbNiNeKxmZAxa@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxmTaZ11formatValueFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T9getNthIntTmTAyaTmTAyaTAyaZ9getNthIntFNaNfkmAyamAyaAyaZi@Base 6
+ _D3std6format32__T14formatIntegralTDFAxaZvTmTaZ14formatIntegralFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format32__T14formatUnsignedTDFAxaZvTmTaZ14formatUnsignedFDFAxaZvmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format34__T6formatTaTE3std8datetime5MonthZ6formatFNaNfxAaE3std8datetime5MonthZAya@Base 6
+ _D3std6format34__T9getNthIntTAyaTmTAyaTmTAyaTAyaZ9getNthIntFNaNfkAyamAyamAyaAyaZi@Base 6
+ _D3std6format35__T9getNthIntTE3std8datetime5MonthZ9getNthIntFNaNfkE3std8datetime5MonthZi@Base 6
+ _D3std6format36__T11formatValueTDFNaNbNfAxaZvTyhTaZ11formatValueFDFNaNbNfAxaZvyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TyhZ9__lambda4FNaNbNiNeKyhZAxa@Base 6
+ _D3std6format36__T11formatValueTDFNaNbNfAxaZvTyhTaZ11formatValueFNaNfDFNaNbNfAxaZvyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format36__T9getNthIntTmTAyaTmTAyaTmTAyaTAyaZ9getNthIntFNaNfkmAyamAyamAyaAyaZi@Base 6
+ _D3std6format37__T11formatRangeTDFNaNbNfAxaZvTAyhTaZ11formatRangeFNaNfKDFNaNbNfAxaZvKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format37__T11formatValueTDFNaNbNfAxaZvTAyhTaZ11formatValueFNaNfDFNaNbNfAxaZvAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format37__T9getNthIntTE3std8datetime5MonthTiZ9getNthIntFNaNfkE3std8datetime5MonthiZi@Base 6
+ _D3std6format38__T13formatElementTDFNaNbNfAxaZvTyhTaZ13formatElementFNaNfDFNaNbNfAxaZvKyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format38__T14formatIntegralTDFNaNbNfAxaZvTmTaZ14formatIntegralFNaNbNfDFNaNbNfAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format38__T14formatUnsignedTDFNaNbNfAxaZvTmTaZ14formatUnsignedFNaNbNfDFNaNbNfAxaZvmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format38__T6formatTaTiTE3std8datetime5MonthTiZ6formatFNaNfxAaiE3std8datetime5MonthiZAya@Base 6
+ _D3std6format39__T13formatElementTDFNaNbNfAxaZvTAyhTaZ13formatElementFNaNfDFNaNbNfAxaZvKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format39__T9getNthIntTiTE3std8datetime5MonthTiZ9getNthIntFNaNfkiE3std8datetime5MonthiZi@Base 6
+ _D3std6format39__T9getNthIntTxE3std8datetime5MonthTxhZ9getNthIntFNaNfkxE3std8datetime5MonthxhZi@Base 6
+ _D3std6format41__T6formatTaTxsTxE3std8datetime5MonthTxhZ6formatFNaNfxAaxsxE3std8datetime5MonthxhZAya@Base 6
+ _D3std6format42__T9getNthIntTxsTxE3std8datetime5MonthTxhZ9getNthIntFNaNfkxsxE3std8datetime5MonthxhZi@Base 6
+ _D3std6format45__T9getNthIntTE3std8datetime5MonthThThThThTiZ9getNthIntFNaNfkE3std8datetime5MonthhhhhiZi@Base 6
+ _D3std6format46__T9getNthIntTPC3std11concurrency10MessageBoxZ9getNthIntFNaNfkPC3std11concurrency10MessageBoxZi@Base 6
+ _D3std6format47__T9getNthIntTsTE3std8datetime5MonthThThThThTiZ9getNthIntFNaNfksE3std8datetime5MonthhhhhiZi@Base 6
+ _D3std6format49__T9getNthIntTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format52__T10formatCharTS3std5stdio4File17LockingTextWriterZ10formatCharFNfS3std5stdio4File17LockingTextWriterxwxaZv@Base 6
+ _D3std6format53__T22enforceValidFormatSpecTS3std11concurrency3TidTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format53__T9getNthIntTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format54__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmkZv@Base 6
+ _D3std6format54__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmkZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T10formatCharTS3std5array17__T8AppenderTAyaZ8AppenderZ10formatCharFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxwxaZv@Base 6
+ _D3std6format56__T10formatCharTS3std5array17__T8AppenderTyAaZ8AppenderZ10formatCharFNaNfS3std5array17__T8AppenderTyAaZ8AppenderxwxaZv@Base 6
+ _D3std6format56__T11formatValueTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ11formatValueFDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format56__T9formatNthTDFAxaZvTaTPC3std11concurrency10MessageBoxZ9formatNthFDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpecmPC3std11concurrency10MessageBoxZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T9formatNthTDFAxaZvTaTPC3std11concurrency10MessageBoxZ9formatNthFDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpecmPC3std11concurrency10MessageBoxZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAxaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmAxaZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAxaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmAxaZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterThTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterThTaZ11formatValueFS3std5stdio4File17LockingTextWriterhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTiTaZ11formatValueFNfS3std5stdio4File17LockingTextWriteriKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTiTaZ11formatValueFS3std5stdio4File17LockingTextWriteriKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTkTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTkTaZ11formatValueFS3std5stdio4File17LockingTextWriterkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTmTaZ11formatValueFNfS3std5stdio4File17LockingTextWritermKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTmTaZ11formatValueFS3std5stdio4File17LockingTextWritermKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TmZ9__lambda4FNaNbNiNeKmZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTsTaZ11formatValueFNfS3std5stdio4File17LockingTextWritersKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTsTaZ11formatValueFS3std5stdio4File17LockingTextWritersKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TsZ9__lambda4FNaNbNiNeKsZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTwTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T12formatObjectTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ12formatObjectFKDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T9getNthIntTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkAyaAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format58__T11formatValueTS3std5stdio4File17LockingTextWriterTxaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T11formatValueTS3std5stdio4File17LockingTextWriterTyaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriteryaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T13formatElementTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ13formatElementFDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T6formatTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ6formatFNaNfxAabAyaAyaE3std3net7isemail15EmailStatusCodeZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmiZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmiZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTmZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmmZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTmZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmmZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmwZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmwZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ9formatNthFNaNfS3std5array17__T8AppenderTyAaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ9formatNthFS3std5array17__T8AppenderTyAaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T11formatRangeTS3std5stdio4File17LockingTextWriterTAxaTaZ11formatRangeFNfKS3std5stdio4File17LockingTextWriterKAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatRangeTS3std5stdio4File17LockingTextWriterTAyaTaZ11formatRangeFNfKS3std5stdio4File17LockingTextWriterKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTDFAxaZvTPC3std11concurrency10MessageBoxTaZ11formatValueFDFAxaZvPC3std11concurrency10MessageBoxKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTS3std5stdio4File17LockingTextWriterTAxaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTS3std5stdio4File17LockingTextWriterTAyaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatElementTS3std5stdio4File17LockingTextWriterTwTaZ13formatElementFNfS3std5stdio4File17LockingTextWriterwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterThTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTiTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTkTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTmTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTsTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxkZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxkZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxsZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxsZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T9getNthIntTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkbAyaAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format60__T14formatIntegralTS3std5stdio4File17LockingTextWriterTlTaZ14formatIntegralFNfS3std5stdio4File17LockingTextWriterxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format60__T14formatIntegralTS3std5stdio4File17LockingTextWriterTmTaZ14formatIntegralFNfS3std5stdio4File17LockingTextWriterxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format60__T14formatUnsignedTS3std5stdio4File17LockingTextWriterTmTaZ14formatUnsignedFNfS3std5stdio4File17LockingTextWritermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAakZk@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmiiZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmiiZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTmTmZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmmmZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTmTmZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmmmZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmwkZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmwkZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTbTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderbKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderThTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderThTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TmZ9__lambda4FNaNbNiNeKmZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppendertKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppendertKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TtZ9__lambda4FNaNbNiNeKtZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderThTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderThTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTiTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTiTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTwTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTDFAxaZvTPC3std11concurrency10MessageBoxTaZ13formatGenericFDFAxaZvPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTS3std5stdio4File17LockingTextWriterTAxaTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTS3std5stdio4File17LockingTextWriterTAyaTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyAaZv@Base 6
+ _D3std6format61__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyAaZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPvTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxdTaZ11formatValueFNfS3std5array17__T8AppenderTAyaZ8AppenderxdKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxdTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxdKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxdZ9__lambda4FNaNbNiNeKxdZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxhZ9__lambda4FNaNbNiNeKxhZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxiTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxiTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxiZ9__lambda4FNaNbNiNeKxiZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxkZ9__lambda4FNaNbNiNeKxkZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxmTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxmTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxmZ9__lambda4FNaNbNiNeKxmZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxsKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxsKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxsZ9__lambda4FNaNbNiNeKxsZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TyhZ9__lambda4FNaNbNiNeKyhZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZ46__T9__lambda6TPC3std11concurrency10MessageBoxZ9__lambda6FNaNbNiNeKPC3std11concurrency10MessageBoxZxPv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZ9__lambda5FNaNbNiNeZPFNaNbNfDFAxaZvPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAxaZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAxaZ18__T9__lambda6TAxaZ9__lambda6FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAxaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAyaZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaZ18__T9__lambda6TAyaZ9__lambda6FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAaPvZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAaPvZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAxhaZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAxhaZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyakZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyakZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTmZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyamZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTmZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyamZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkkkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkkkZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmwkkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmwkkZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxmTxmZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxmxmZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxmTxmZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxmxmZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyaiZv@Base 6
+ _D3std6format62__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyaiZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyhTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTyAaZ8AppenderTAyaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTAyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatElementTS3std5array17__T8AppenderTyAaZ8AppenderTwTaZ13formatElementFNaNfS3std5array17__T8AppenderTyAaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTbTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ13formatGenericFNaS3std5array17__T8AppenderTyAaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTPvTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ13formatGenericFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxmTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTAyaZ8AppenderTlTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTyAaZ8AppenderTlTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTyAaZ8AppenderTmTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatUnsignedTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ14formatUnsignedFNaNbNfS3std5array17__T8AppenderTAyaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format64__T14formatUnsignedTS3std5array17__T8AppenderTyAaZ8AppenderTmTaZ14formatUnsignedFNaNbNfS3std5array17__T8AppenderTyAaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiZ16__T9__lambda6TiZ9__lambda6FNaNbNiNeKiZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAamZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAamZ16__T9__lambda6TmZ9__lambda6FNaNbNiNeKmZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAamZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawZ16__T9__lambda6TwZ9__lambda6FNaNbNiNeKwZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTyAaZ8AppenderxAakZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTyAaZ8AppenderxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTyAaZ8AppenderxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAxaAxaZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAxaAxaZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyaZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyaZ16__T7gencodeVmi2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyakkZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyakkZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format65__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZk@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZ17__T9__lambda6TxkZ9__lambda6FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZk@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZ17__T9__lambda6TxsZ9__lambda6FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T22enforceValidFormatSpecTC3std11concurrency14LinkTerminatedTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxhxhxhZv@Base 6
+ _D3std6format65__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxhxhxhZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZ18__T9__lambda6TAyaZ9__lambda6FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ16__T9__lambda7TiZ9__lambda7FNaNbNiNeKiZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ16__T9__lambda9TiZ9__lambda9FNaNbNiNeKiZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmTmZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAammZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAammZ16__T9__lambda7TmZ9__lambda7FNaNbNiNeKmZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAammZ16__T9__lambda9TmZ9__lambda9FNaNbNiNeKmZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAammZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTmTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAammZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawkZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ16__T9__lambda7TwZ9__lambda7FNaNbNiNeKwZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T22enforceValidFormatSpecTC3std11concurrency15OwnerTerminatedTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyamZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyamZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyakAyaZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyakAyaZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmtAyattZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmtAyattZ16__T7gencodeVmi4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxsAyaxhZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxsAyaxhZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9getNthIntTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9getNthIntFNaNfkE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZk@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZ19__T9__lambda6TAyAaZ9__lambda6FNaNbNiNeKAyAaZxPv@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format67__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkxkxkxkZv@Base 6
+ _D3std6format67__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmkxkxkxkZ16__T7gencodeVmi4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ17__T9__lambda7TAaZ9__lambda7FNaNbNiNeKAaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ17__T9__lambda9TPvZ9__lambda9FNaNbNiNeKPvZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ16__T9__lambda9TaZ9__lambda9FNaNbNiNeKaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ18__T9__lambda7TAxhZ9__lambda7FNaNbNiNeKAxhZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ18__T9__lambda7TAyaZ9__lambda7FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTmZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyamZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyamZ16__T9__lambda9TmZ9__lambda9FNaNbNiNeKmZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyamZ18__T9__lambda7TAyaZ9__lambda7FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyamZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyamZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ16__T9__lambda8TkZ9__lambda8FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ16__T9__lambda8TwZ9__lambda8FNaNbNiNeKwZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxmTxmZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxmxmZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxmTxmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxmxmZ17__T9__lambda7TxmZ9__lambda7FNaNbNiNeKxmZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxmTxmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxmxmZ17__T9__lambda9TxmZ9__lambda9FNaNbNiNeKxmZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxmTxmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxmxmZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxmTxmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxmxmZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAyaAyaiZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ18__T10__lambda12TiZ10__lambda12FNaNbNiNeKiZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyaAyaZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmAyaAyaAyaZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxhxhxhxhZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxhxhxhxhZ16__T7gencodeVmi4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format6Mangle6__initZ@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ18__T9__lambda7TAxaZ9__lambda7FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ18__T9__lambda9TAxaZ9__lambda9FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ18__T9__lambda7TAyaZ9__lambda7FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ18__T9__lambda9TAyaZ9__lambda9FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZk@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ17__T9__lambda8TxhZ9__lambda8FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ19__T10__lambda10TxhZ10__lambda10FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyamZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyamZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyamZ18__T10__lambda12TmZ10__lambda12FNaNbNiNeKmZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyamZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyamZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyamZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTmZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyamZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ20__T10__lambda12TAyaZ10__lambda12FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ16__T9__lambda9TtZ9__lambda9FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ18__T10__lambda13TtZ10__lambda13FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ18__T10__lambda15TtZ10__lambda15FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ20__T10__lambda11TAyaZ10__lambda11FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ17__T9__lambda8TxsZ9__lambda8FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZk@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda11TxkZ10__lambda11FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda13TxkZ10__lambda13FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda15TxkZ10__lambda15FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZk@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ20__T10__lambda12TAyaZ10__lambda12FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZk@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ17__T9__lambda9TxhZ9__lambda9FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda11TxhZ10__lambda11FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda13TxhZ10__lambda13FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda15TxhZ10__lambda15FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T9formatNthTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmmAyamAyamAyaAyaZv@Base 6
+ _D3std6format74__T9formatNthTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmmAyamAyamAyaAyaZ16__T7gencodeVmi7Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format76__T11formatValueTS3std5stdio4File17LockingTextWriterTE3std8datetime5MonthTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format77__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmE3std8datetime5MonthZv@Base 6
+ _D3std6format77__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmE3std8datetime5MonthZ16__T7gencodeVmi1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format78__T13formatGenericTS3std5stdio4File17LockingTextWriterTE3std8datetime5MonthTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std8datetime5MonthTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZk@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ10__lambda13FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ10__lambda15FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ10__lambda17FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ10__lambda19FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ10__lambda21FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ10__lambda23FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ18__T10__lambda12TmZ10__lambda12FNaNbNiNeKmZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ18__T10__lambda16TmZ10__lambda16FNaNbNiNeKmZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ18__T10__lambda20TmZ10__lambda20FNaNbNiNeKmZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ20__T10__lambda14TAyaZ10__lambda14FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ20__T10__lambda18TAyaZ10__lambda18FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ20__T10__lambda22TAyaZ10__lambda22FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTmTAyaTmTAyaTmTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAamAyamAyamAyaAyaZ20__T10__lambda24TAyaZ10__lambda24FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format81__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxE3std8datetime5MonthTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format81__T22enforceValidFormatSpecTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format81__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmiE3std8datetime5MonthiZv@Base 6
+ _D3std6format81__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmiE3std8datetime5MonthiZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format82__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTS3std11concurrency3TidTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format82__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std8datetime5MonthTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTS3std11concurrency3TidTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxE3std8datetime5MonthTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZk@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZ35__T9__lambda6TE3std8datetime5MonthZ9__lambda6FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format84__T11formatValueTDFNaNbNfAxaZvTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ11formatValueFNaNfDFNaNbNfAxaZvKS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format84__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxsxE3std8datetime5MonthxhZv@Base 6
+ _D3std6format84__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmxsxE3std8datetime5MonthxhZ16__T7gencodeVmi3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format85__T9formatNthTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmsE3std8datetime5MonthhhhhiZv@Base 6
+ _D3std6format85__T9formatNthTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecmsE3std8datetime5MonthhhhhiZ16__T7gencodeVmi7Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format86__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTE3std5regex8internal2ir2IRTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderE3std5regex8internal2ir2IRKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format86__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTE3std6socket12SocketOptionTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderE3std6socket12SocketOptionKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format86__T13formatElementTDFNaNbNfAxaZvTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ13formatElementFNaNfDFNaNbNfAxaZvKS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZk@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ16__T9__lambda8TiZ9__lambda8FNaNbNiNeKiZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ18__T10__lambda12TiZ10__lambda12FNaNbNiNeKiZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ37__T10__lambda10TE3std8datetime5MonthZ10__lambda10FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format89__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ11formatValueFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format89__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ11formatValueFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format90__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ11formatValueFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkykKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ11formatValueFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkykKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TykZ9__lambda4FNaNbNiNeKykZAxa@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZk@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ17__T9__lambda8TxsZ9__lambda8FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ38__T10__lambda10TxE3std8datetime5MonthZ10__lambda10FNaNbNiNeKxE3std8datetime5MonthZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T13formatGenericTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ13formatGenericFNaS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZk@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda13FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda15FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda17FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda19FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda21FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda23FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda12TsZ10__lambda12FNaNbNiNeKsZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda16ThZ10__lambda16FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda18ThZ10__lambda18FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda20ThZ10__lambda20FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda22ThZ10__lambda22FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda24TiZ10__lambda24FNaNbNiNeKiZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ37__T10__lambda14TE3std8datetime5MonthZ10__lambda14FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format92__T13formatGenericTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ13formatGenericFNaS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format92__T14formatIntegralTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTmTaZ14formatIntegralFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format92__T14formatUnsignedTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTmTaZ14formatUnsignedFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format93__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPS3std11parallelism12AbstractTaskTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPS3std11parallelism12AbstractTaskKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format94__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency14LinkTerminatedTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderC3std11concurrency14LinkTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format94__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net7isemail15EmailStatusCodeTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std3net7isemail15EmailStatusCodeKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format95__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency15OwnerTerminatedTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderC3std11concurrency15OwnerTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format95__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency14LinkTerminatedTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKC3std11concurrency14LinkTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency15OwnerTerminatedTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKC3std11concurrency15OwnerTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net7isemail15EmailStatusCodeTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T9formatNthTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ9formatNthFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKS3std6format18__T10FormatSpecTaZ10FormatSpecmykykkkkZv@Base 6
+ _D3std6format96__T9formatNthTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ9formatNthFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKS3std6format18__T10FormatSpecTaZ10FormatSpecmykykkkkZ16__T7gencodeVmi5Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6getopt10assignCharw@Base 6
+ _D3std6getopt10optionCharw@Base 6
+ _D3std6getopt11splitAndGetFNaNbNeAyaZS3std6getopt6Option@Base 6
+ _D3std6getopt12GetoptResult11__xopEqualsFKxS3std6getopt12GetoptResultKxS3std6getopt12GetoptResultZb@Base 6
+ _D3std6getopt12GetoptResult6__initZ@Base 6
+ _D3std6getopt12GetoptResult9__xtoHashFNbNeKxS3std6getopt12GetoptResultZm@Base 6
+ _D3std6getopt12__ModuleInfoZ@Base 6
+ _D3std6getopt12endOfOptionsAya@Base 6
+ _D3std6getopt13configuration11passThroughMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration11passThroughMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration13caseSensitiveMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration13caseSensitiveMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration16keepEndOfOptionsMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration16keepEndOfOptionsMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration20stopOnFirstNonOptionMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration20stopOnFirstNonOptionMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration6__initZ@Base 6
+ _D3std6getopt13configuration8bundlingMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration8bundlingMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration8requiredMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration8requiredMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt15GetOptException6__ctorMFNaNbNfAyaAyamZC3std6getopt15GetOptException@Base 6
+ _D3std6getopt15GetOptException6__initZ@Base 6
+ _D3std6getopt15GetOptException6__vtblZ@Base 6
+ _D3std6getopt15GetOptException7__ClassZ@Base 6
+ _D3std6getopt20defaultGetoptPrinterFAyaAS3std6getopt6OptionZv@Base 6
+ _D3std6getopt64__T22defaultGetoptFormatterTS3std5stdio4File17LockingTextWriterZ22defaultGetoptFormatterFNfS3std5stdio4File17LockingTextWriterAyaAS3std6getopt6OptionZv@Base 6
+ _D3std6getopt6Option11__xopEqualsFKxS3std6getopt6OptionKxS3std6getopt6OptionZb@Base 6
+ _D3std6getopt6Option6__initZ@Base 6
+ _D3std6getopt6Option9__xtoHashFNbNeKxS3std6getopt6OptionZm@Base 6
+ _D3std6getopt8arraySepAya@Base 6
+ _D3std6getopt8optMatchFAyaAyaKAyaS3std6getopt13configurationZb@Base 6
+ _D3std6getopt9setConfigFKS3std6getopt13configurationE3std6getopt6configZv@Base 6
+ _D3std6mmfile12__ModuleInfoZ@Base 6
+ _D3std6mmfile6MmFile12ensureMappedMFmZv@Base 6
+ _D3std6mmfile6MmFile12ensureMappedMFmmZv@Base 6
+ _D3std6mmfile6MmFile13opIndexAssignMFhmZh@Base 6
+ _D3std6mmfile6MmFile3mapMFmmZv@Base 6
+ _D3std6mmfile6MmFile4modeMFZE3std6mmfile6MmFile4Mode@Base 6
+ _D3std6mmfile6MmFile5flushMFZv@Base 6
+ _D3std6mmfile6MmFile5unmapMFZv@Base 6
+ _D3std6mmfile6MmFile6__ctorMFAyaE3std6mmfile6MmFile4ModemPvmZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFAyaZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFS3std5stdio4FileE3std6mmfile6MmFile4ModemPvmZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFiE3std6mmfile6MmFile4ModemPvmZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__dtorMFZv@Base 6
+ _D3std6mmfile6MmFile6__initZ@Base 6
+ _D3std6mmfile6MmFile6__vtblZ@Base 6
+ _D3std6mmfile6MmFile6lengthMxFNdZm@Base 6
+ _D3std6mmfile6MmFile6mappedMFmZi@Base 6
+ _D3std6mmfile6MmFile7__ClassZ@Base 6
+ _D3std6mmfile6MmFile7opIndexMFmZh@Base 6
+ _D3std6mmfile6MmFile7opSliceMFZAv@Base 6
+ _D3std6mmfile6MmFile7opSliceMFmmZAv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine134__T4seedTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4seedMFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine4saveMFNaNbNdNiNfZS3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine5frontMFNaNbNdNfZk@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine6__ctorMFNaNbNcNfkZS3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine6__initZ@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine8popFrontMFNaNbNfZ5mag01yG2k@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine8popFrontMFNaNbNfZv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine9__T4seedZ4seedMFNaNbNfkZv@Base 6
+ _D3std6random12__ModuleInfoZ@Base 6
+ _D3std6random17unpredictableSeedFNdNeZ4randS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random17unpredictableSeedFNdNeZ6seededb@Base 6
+ _D3std6random17unpredictableSeedFNdNeZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG5kZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngineZb@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG6kZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngineZb@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG3kZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngineZb@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG4kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG1kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG2kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine16primeFactorsOnlyFNaNbNiNfmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine34properLinearCongruentialParametersFNaNbNiNfmmmZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine3gcdFNaNbNiNfmmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine4saveMFNaNbNdNiNfZS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine4seedMFNaNfkZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__ctorMFNaNcNfkZS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine8opEqualsMxFNaNbNiNfKxS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngineZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine16primeFactorsOnlyFNaNbNiNfmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine34properLinearCongruentialParametersFNaNbNiNfmmmZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine3gcdFNaNbNiNfmmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine4saveMFNaNbNdNiNfZS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine4seedMFNaNfkZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__ctorMFNaNcNfkZS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine8opEqualsMxFNaNbNiNfKxS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngineZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random6rndGenFNcNdNfZ11initializedb@Base 6
+ _D3std6random6rndGenFNcNdNfZ16__T9__lambda3TiZ9__lambda3FNfiZk@Base 6
+ _D3std6random6rndGenFNcNdNfZ16__T9__lambda4TiZ9__lambda4FNfiZk@Base 6
+ _D3std6random6rndGenFNcNdNfZ6resultS3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine@Base 6
+ _D3std6random6rndGenFNcNdNfZS3std6random109__T21MersenneTwisterEngineTkVmi32Vmi624Vmi397Vmi31Vki2567483615Vmi11Vmi7Vki2636928640Vmi15Vki4022730752Vmi18Z21MersenneTwisterEngine@Base 6
+ _D3std6socket10SocketType6__initZ@Base 6
+ _D3std6socket10getAddressFNfxAatZAC3std6socket7Address@Base 6
+ _D3std6socket10getAddressFNfxAaxAaZAC3std6socket7Address@Base 6
+ _D3std6socket10socketPairFNeZG2C3std6socket6Socket@Base 6
+ _D3std6socket11AddressInfo11__xopEqualsFKxS3std6socket11AddressInfoKxS3std6socket11AddressInfoZb@Base 6
+ _D3std6socket11AddressInfo6__initZ@Base 6
+ _D3std6socket11AddressInfo9__xtoHashFNbNeKxS3std6socket11AddressInfoZm@Base 6
+ _D3std6socket11UnixAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket11UnixAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket11UnixAddress4pathMxFNaNdNeZAya@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNbNiNfS4core3sys5posix3sys2un11sockaddr_unZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNbNiNfZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNexAaZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__initZ@Base 6
+ _D3std6socket11UnixAddress6__vtblZ@Base 6
+ _D3std6socket11UnixAddress7__ClassZ@Base 6
+ _D3std6socket11UnixAddress7nameLenMxFNaNbNdNiNeZk@Base 6
+ _D3std6socket11UnixAddress8toStringMxFNaNfZAya@Base 6
+ _D3std6socket12InternetHost12validHostentMFNfxPS4core3sys5posix5netdb7hostentZv@Base 6
+ _D3std6socket12InternetHost13getHostByAddrMFNekZb@Base 6
+ _D3std6socket12InternetHost13getHostByAddrMFNexAaZb@Base 6
+ _D3std6socket12InternetHost13getHostByNameMFNexAaZb@Base 6
+ _D3std6socket12InternetHost174__T7getHostVAyaa75_0a202020202020202020202020202020206175746f206865203d20676574686f737462796e616d6528706172616d2e74656d7043537472696e672829293b0a202020202020202020202020TAxaZ7getHostMFAxaZb@Base 6
+ _D3std6socket12InternetHost181__T13getHostNoSyncVAyaa75_0a202020202020202020202020202020206175746f206865203d20676574686f737462796e616d6528706172616d2e74656d7043537472696e672829293b0a202020202020202020202020TAxaZ13getHostNoSyncMFAxaZb@Base 6
+ _D3std6socket12InternetHost257__T7getHostVAyaa117_0a2020202020202020202020206175746f2078203d2068746f6e6c28706172616d293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TkZ7getHostMFkZb@Base 6
+ _D3std6socket12InternetHost264__T13getHostNoSyncVAyaa117_0a2020202020202020202020206175746f2078203d2068746f6e6c28706172616d293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TkZ13getHostNoSyncMFkZb@Base 6
+ _D3std6socket12InternetHost513__T7getHostVAyaa244_0a2020202020202020202020206175746f2078203d20696e65745f6164647228706172616d2e74656d7043537472696e672829293b0a202020202020202020202020656e666f726365287820213d20494e414444525f4e4f4e452c0a202020202020202020202020202020206e657720536f636b6574506172616d65746572457863657074696f6e2822496e76616c6964204950763420616464726573732229293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TAxaZ7getHostMFAxaZb@Base 6
+ _D3std6socket12InternetHost520__T13getHostNoSyncVAyaa244_0a2020202020202020202020206175746f2078203d20696e65745f6164647228706172616d2e74656d7043537472696e672829293b0a202020202020202020202020656e666f726365287820213d20494e414444525f4e4f4e452c0a202020202020202020202020202020206e657720536f636b6574506172616d65746572457863657074696f6e2822496e76616c6964204950763420616464726573732229293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TAxaZ13getHostNoSyncMFAxaZb@Base 6
+ _D3std6socket12InternetHost6__initZ@Base 6
+ _D3std6socket12InternetHost6__vtblZ@Base 6
+ _D3std6socket12InternetHost7__ClassZ@Base 6
+ _D3std6socket12InternetHost8populateMFNaNbPS4core3sys5posix5netdb7hostentZv@Base 6
+ _D3std6socket12SocketOption6__initZ@Base 6
+ _D3std6socket12__ModuleInfoZ@Base 6
+ _D3std6socket12parseAddressFNfxAatZC3std6socket7Address@Base 6
+ _D3std6socket12parseAddressFNfxAaxAaZC3std6socket7Address@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaAyamC6object9ThrowableiZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaC6object9ThrowableAyamiZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaiAyamC6object9ThrowableZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__initZ@Base 6
+ _D3std6socket13HostException6__vtblZ@Base 6
+ _D3std6socket13HostException7__ClassZ@Base 6
+ _D3std6socket13_SOCKET_ERRORxi@Base 6
+ _D3std6socket13serviceToPortFNfxAaZt@Base 6
+ _D3std6socket14UnknownAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket14UnknownAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket14UnknownAddress6__initZ@Base 6
+ _D3std6socket14UnknownAddress6__vtblZ@Base 6
+ _D3std6socket14UnknownAddress7__ClassZ@Base 6
+ _D3std6socket14UnknownAddress7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket14formatGaiErrorFNeiZ13__critsec1889G48g@Base 6
+ _D3std6socket14formatGaiErrorFNeiZAya@Base 6
+ _D3std6socket15InternetAddress12addrToStringFNbNekZAya@Base 6
+ _D3std6socket15InternetAddress12toAddrStringMxFNeZAya@Base 6
+ _D3std6socket15InternetAddress12toPortStringMxFNfZAya@Base 6
+ _D3std6socket15InternetAddress16toHostNameStringMxFNfZAya@Base 6
+ _D3std6socket15InternetAddress4addrMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket15InternetAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket15InternetAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket15InternetAddress4portMxFNaNbNdNiNfZt@Base 6
+ _D3std6socket15InternetAddress5parseFNbNexAaZk@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfS4core3sys5posix7netinet3in_11sockaddr_inZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfktZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNftZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNfxAatZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__initZ@Base 6
+ _D3std6socket15InternetAddress6__vtblZ@Base 6
+ _D3std6socket15InternetAddress7__ClassZ@Base 6
+ _D3std6socket15InternetAddress7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket15InternetAddress8opEqualsMxFNfC6ObjectZb@Base 6
+ _D3std6socket15SocketException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std6socket15SocketException@Base 6
+ _D3std6socket15SocketException6__ctorMFNaNbNfAyaC6object9ThrowableAyamZC3std6socket15SocketException@Base 6
+ _D3std6socket15SocketException6__initZ@Base 6
+ _D3std6socket15SocketException6__vtblZ@Base 6
+ _D3std6socket15SocketException7__ClassZ@Base 6
+ _D3std6socket15lastSocketErrorFNdNfZAya@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaAyamC6object9ThrowableiZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaC6object9ThrowableAyamiZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaiAyamC6object9ThrowableZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__initZ@Base 6
+ _D3std6socket16AddressException6__vtblZ@Base 6
+ _D3std6socket16AddressException7__ClassZ@Base 6
+ _D3std6socket16AddressInfoFlags6__initZ@Base 6
+ _D3std6socket16Internet6Address4addrMxFNaNbNdNiNfZG16h@Base 6
+ _D3std6socket16Internet6Address4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket16Internet6Address4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket16Internet6Address4portMxFNaNbNdNiNfZt@Base 6
+ _D3std6socket16Internet6Address5parseFNexAaZG16h@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfG16htZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfS4core3sys5posix7netinet3in_12sockaddr_in6ZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNftZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNexAaxAaZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNfxAatZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__initZ@Base 6
+ _D3std6socket16Internet6Address6__vtblZ@Base 6
+ _D3std6socket16Internet6Address7__ClassZ@Base 6
+ _D3std6socket16Internet6Address7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket16Internet6Address8ADDR_ANYFNaNbNcNdNiNfZxG16h@Base 6
+ _D3std6socket16wouldHaveBlockedFNbNiNfZb@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaAyamC6object9ThrowableiPFNeiZAyaZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaC6object9ThrowableAyamiPFNeiZAyaZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaiPFNeiZAyaAyamC6object9ThrowableZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__initZ@Base 6
+ _D3std6socket17SocketOSException6__vtblZ@Base 6
+ _D3std6socket17SocketOSException7__ClassZ@Base 6
+ _D3std6socket17SocketOptionLevel6__initZ@Base 6
+ _D3std6socket17formatSocketErrorFNeiZAya@Base 6
+ _D3std6socket18_sharedStaticCtor1FZv@Base 6
+ _D3std6socket18_sharedStaticDtor2FNbNiZv@Base 6
+ _D3std6socket18getAddressInfoImplFxAaxAaPS4core3sys5posix5netdb8addrinfoZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket18getaddrinfoPointeryPUNbNiPxaPxaPxS4core3sys5posix5netdb8addrinfoPPS4core3sys5posix5netdb8addrinfoZi@Base 6
+ _D3std6socket18getnameinfoPointeryPUNbNiPxS4core3sys5posix3sys6socket8sockaddrkPakPakiZi@Base 6
+ _D3std6socket19freeaddrinfoPointeryPUNbNiPS4core3sys5posix5netdb8addrinfoZv@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaAyamC6object9ThrowableiZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaC6object9ThrowableAyamiZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaiAyamC6object9ThrowableZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__initZ@Base 6
+ _D3std6socket21SocketAcceptException6__vtblZ@Base 6
+ _D3std6socket21SocketAcceptException7__ClassZ@Base 6
+ _D3std6socket22SocketFeatureException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std6socket22SocketFeatureException@Base 6
+ _D3std6socket22SocketFeatureException6__ctorMFNaNbNfAyaC6object9ThrowableAyamZC3std6socket22SocketFeatureException@Base 6
+ _D3std6socket22SocketFeatureException6__initZ@Base 6
+ _D3std6socket22SocketFeatureException6__vtblZ@Base 6
+ _D3std6socket22SocketFeatureException7__ClassZ@Base 6
+ _D3std6socket23UnknownAddressReference4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket23UnknownAddressReference4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket23UnknownAddressReference6__ctorMFNaNbNiNfPS4core3sys5posix3sys6socket8sockaddrkZC3std6socket23UnknownAddressReference@Base 6
+ _D3std6socket23UnknownAddressReference6__ctorMFNaNbPxS4core3sys5posix3sys6socket8sockaddrkZC3std6socket23UnknownAddressReference@Base 6
+ _D3std6socket23UnknownAddressReference6__initZ@Base 6
+ _D3std6socket23UnknownAddressReference6__vtblZ@Base 6
+ _D3std6socket23UnknownAddressReference7__ClassZ@Base 6
+ _D3std6socket23UnknownAddressReference7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket24SocketParameterException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std6socket24SocketParameterException@Base 6
+ _D3std6socket24SocketParameterException6__ctorMFNaNbNfAyaC6object9ThrowableAyamZC3std6socket24SocketParameterException@Base 6
+ _D3std6socket24SocketParameterException6__initZ@Base 6
+ _D3std6socket24SocketParameterException6__vtblZ@Base 6
+ _D3std6socket24SocketParameterException7__ClassZ@Base 6
+ _D3std6socket24__T14getAddressInfoTAxaZ14getAddressInfoFNexAaAxaZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket51__T14getAddressInfoTE3std6socket16AddressInfoFlagsZ14getAddressInfoFNexAaE3std6socket16AddressInfoFlagsZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket52__T14getAddressInfoTAxaTE3std6socket13AddressFamilyZ14getAddressInfoFNexAaAxaE3std6socket13AddressFamilyZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket55__T14getAddressInfoTAxaTE3std6socket16AddressInfoFlagsZ14getAddressInfoFNexAaAxaE3std6socket16AddressInfoFlagsZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket6Linger6__initZ@Base 6
+ _D3std6socket6Linger8__mixin22onMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket6Linger8__mixin22onMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket6Linger8__mixin34timeMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket6Linger8__mixin34timeMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNeAvE3std6socket11SocketFlagsKC3std6socket7AddressZl@Base 6
+ _D3std6socket6Socket11receiveFromMFNeAvE3std6socket11SocketFlagsZl@Base 6
+ _D3std6socket6Socket11receiveFromMFNfAvKC3std6socket7AddressZl@Base 6
+ _D3std6socket6Socket11receiveFromMFNfAvZl@Base 6
+ _D3std6socket6Socket12getErrorTextMFNfZAya@Base 6
+ _D3std6socket6Socket12localAddressMFNdNeZC3std6socket7Address@Base 6
+ _D3std6socket6Socket12setKeepAliveMFNeiiZv@Base 6
+ _D3std6socket6Socket13addressFamilyMFNdNfZE3std6socket13AddressFamily@Base 6
+ _D3std6socket6Socket13createAddressMFNaNbNfZC3std6socket7Address@Base 6
+ _D3std6socket6Socket13remoteAddressMFNdNeZC3std6socket7Address@Base 6
+ _D3std6socket6Socket4bindMFNeC3std6socket7AddressZv@Base 6
+ _D3std6socket6Socket4sendMFNeAxvE3std6socket11SocketFlagsZl@Base 6
+ _D3std6socket6Socket4sendMFNfAxvZl@Base 6
+ _D3std6socket6Socket5closeMFNbNiNeZv@Base 6
+ _D3std6socket6Socket6__ctorMFNaNbNiNfE3std6socket8socket_tE3std6socket13AddressFamilyZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNaNbNiNfZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNeE3std6socket13AddressFamilyE3std6socket10SocketTypeE3std6socket12ProtocolTypeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNeE3std6socket13AddressFamilyE3std6socket10SocketTypexAaZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNfE3std6socket13AddressFamilyE3std6socket10SocketTypeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNfxS3std6socket11AddressInfoZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__dtorMFNbNiNfZv@Base 6
+ _D3std6socket6Socket6__initZ@Base 6
+ _D3std6socket6Socket6__vtblZ@Base 6
+ _D3std6socket6Socket6_closeFNbNiE3std6socket8socket_tZv@Base 6
+ _D3std6socket6Socket6acceptMFNeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6handleMxFNaNbNdNiNfZE3std6socket8socket_t@Base 6
+ _D3std6socket6Socket6listenMFNeiZv@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetPS3std6socket7TimeValZi@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetS4core4time8DurationZi@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetlZi@Base 6
+ _D3std6socket6Socket6selectFNfC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetZi@Base 6
+ _D3std6socket6Socket6sendToMFNeAxvE3std6socket11SocketFlagsC3std6socket7AddressZl@Base 6
+ _D3std6socket6Socket6sendToMFNeAxvE3std6socket11SocketFlagsZl@Base 6
+ _D3std6socket6Socket6sendToMFNfAxvC3std6socket7AddressZl@Base 6
+ _D3std6socket6Socket6sendToMFNfAxvZl@Base 6
+ _D3std6socket6Socket7__ClassZ@Base 6
+ _D3std6socket6Socket7connectMFNeC3std6socket7AddressZv@Base 6
+ _D3std6socket6Socket7isAliveMxFNdNeZb@Base 6
+ _D3std6socket6Socket7receiveMFNeAvE3std6socket11SocketFlagsZl@Base 6
+ _D3std6socket6Socket7receiveMFNfAvZl@Base 6
+ _D3std6socket6Socket7setSockMFNfE3std6socket8socket_tZv@Base 6
+ _D3std6socket6Socket8blockingMFNdNebZv@Base 6
+ _D3std6socket6Socket8blockingMxFNbNdNiNeZb@Base 6
+ _D3std6socket6Socket8hostNameFNdNeZAya@Base 6
+ _D3std6socket6Socket8shutdownMFNbNiNeE3std6socket14SocketShutdownZv@Base 6
+ _D3std6socket6Socket9acceptingMFNaNbNfZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionAvZi@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJS3std6socket6LingerZi@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJS4core4time8DurationZv@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJiZi@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionAvZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionS3std6socket6LingerZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionS4core4time8DurationZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptioniZv@Base 6
+ _D3std6socket7Address12toAddrStringMxFNfZAya@Base 6
+ _D3std6socket7Address12toHostStringMxFNebZAya@Base 6
+ _D3std6socket7Address12toPortStringMxFNfZAya@Base 6
+ _D3std6socket7Address13addressFamilyMxFNaNbNdNiNfZE3std6socket13AddressFamily@Base 6
+ _D3std6socket7Address15toServiceStringMxFNebZAya@Base 6
+ _D3std6socket7Address16toHostNameStringMxFNfZAya@Base 6
+ _D3std6socket7Address19toServiceNameStringMxFNfZAya@Base 6
+ _D3std6socket7Address6__initZ@Base 6
+ _D3std6socket7Address6__vtblZ@Base 6
+ _D3std6socket7Address7__ClassZ@Base 6
+ _D3std6socket7Address8toStringMxFNfZAya@Base 6
+ _D3std6socket7Service16getServiceByNameMFNbNexAaxAaZb@Base 6
+ _D3std6socket7Service16getServiceByPortMFNbNetxAaZb@Base 6
+ _D3std6socket7Service6__initZ@Base 6
+ _D3std6socket7Service6__vtblZ@Base 6
+ _D3std6socket7Service7__ClassZ@Base 6
+ _D3std6socket7Service8populateMFNaNbPS4core3sys5posix5netdb7serventZv@Base 6
+ _D3std6socket7TimeVal6__initZ@Base 6
+ _D3std6socket7TimeVal8__mixin47secondsMFNaNbNdNiNflZl@Base 6
+ _D3std6socket7TimeVal8__mixin47secondsMxFNaNbNdNiNfZl@Base 6
+ _D3std6socket7TimeVal8__mixin512microsecondsMFNaNbNdNiNflZl@Base 6
+ _D3std6socket7TimeVal8__mixin512microsecondsMxFNaNbNdNiNfZl@Base 6
+ _D3std6socket8Protocol17getProtocolByNameMFNbNexAaZb@Base 6
+ _D3std6socket8Protocol17getProtocolByTypeMFNbNeE3std6socket12ProtocolTypeZb@Base 6
+ _D3std6socket8Protocol6__initZ@Base 6
+ _D3std6socket8Protocol6__vtblZ@Base 6
+ _D3std6socket8Protocol7__ClassZ@Base 6
+ _D3std6socket8Protocol8populateMFNaNbPS4core3sys5posix5netdb8protoentZv@Base 6
+ _D3std6socket8_lasterrFNbNiNfZi@Base 6
+ _D3std6socket8socket_t6__initZ@Base 6
+ _D3std6socket9SocketSet14setMinCapacityMFNaNbNfmZv@Base 6
+ _D3std6socket9SocketSet3addMFNaNbNeE3std6socket8socket_tZv@Base 6
+ _D3std6socket9SocketSet3addMFNaNbNfC3std6socket6SocketZv@Base 6
+ _D3std6socket9SocketSet3maxMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket9SocketSet4maskFNaNbNiNfkZl@Base 6
+ _D3std6socket9SocketSet5isSetMxFNaNbNiNfC3std6socket6SocketZi@Base 6
+ _D3std6socket9SocketSet5isSetMxFNaNbNiNfE3std6socket8socket_tZi@Base 6
+ _D3std6socket9SocketSet5resetMFNaNbNiNfZv@Base 6
+ _D3std6socket9SocketSet6__ctorMFNaNbNfmZC3std6socket9SocketSet@Base 6
+ _D3std6socket9SocketSet6__initZ@Base 6
+ _D3std6socket9SocketSet6__vtblZ@Base 6
+ _D3std6socket9SocketSet6removeMFNaNbNfC3std6socket6SocketZv@Base 6
+ _D3std6socket9SocketSet6removeMFNaNbNfE3std6socket8socket_tZv@Base 6
+ _D3std6socket9SocketSet6resizeMFNaNbNfmZv@Base 6
+ _D3std6socket9SocketSet7__ClassZ@Base 6
+ _D3std6socket9SocketSet7selectnMxFNaNbNiNfZi@Base 6
+ _D3std6socket9SocketSet8capacityMxFNaNbNdNiNfZm@Base 6
+ _D3std6socket9SocketSet8toFd_setMFNaNbNiNeZPS4core3sys5posix3sys6select6fd_set@Base 6
+ _D3std6socket9SocketSet9lengthForFNaNbNiNfmZm@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfC3std6socket7AddressZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfE3std6socket13AddressFamilyZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__initZ@Base 6
+ _D3std6socket9TcpSocket6__vtblZ@Base 6
+ _D3std6socket9TcpSocket7__ClassZ@Base 6
+ _D3std6socket9UdpSocket6__ctorMFNfE3std6socket13AddressFamilyZC3std6socket9UdpSocket@Base 6
+ _D3std6socket9UdpSocket6__ctorMFNfZC3std6socket9UdpSocket@Base 6
+ _D3std6socket9UdpSocket6__initZ@Base 6
+ _D3std6socket9UdpSocket6__vtblZ@Base 6
+ _D3std6socket9UdpSocket7__ClassZ@Base 6
+ _D3std6stdint12__ModuleInfoZ@Base 6
+ _D3std6stream11InputStream11__InterfaceZ@Base 6
+ _D3std6stream11SliceStream10writeBlockMFxPvmZm@Base 6
+ _D3std6stream11SliceStream11__invariantMxFZv@Base 6
+ _D3std6stream11SliceStream13__invariant11MxFZv@Base 6
+ _D3std6stream11SliceStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream11SliceStream6__ctorMFC3std6stream6StreammZC3std6stream11SliceStream@Base 6
+ _D3std6stream11SliceStream6__ctorMFC3std6stream6StreammmZC3std6stream11SliceStream@Base 6
+ _D3std6stream11SliceStream6__initZ@Base 6
+ _D3std6stream11SliceStream6__vtblZ@Base 6
+ _D3std6stream11SliceStream7__ClassZ@Base 6
+ _D3std6stream11SliceStream9availableMFNdZm@Base 6
+ _D3std6stream11SliceStream9readBlockMFPvmZm@Base 6
+ _D3std6stream12BufferedFile4openMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream12BufferedFile6__ctorMFAyaE3std6stream8FileModemZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFC3std6stream4FilemZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFiE3std6stream8FileModemZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__initZ@Base 6
+ _D3std6stream12BufferedFile6__vtblZ@Base 6
+ _D3std6stream12BufferedFile6createMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream12BufferedFile7__ClassZ@Base 6
+ _D3std6stream12EndianStream10fixBlockBOMFPvkmZv@Base 6
+ _D3std6stream12EndianStream11readStringWMFmZAu@Base 6
+ _D3std6stream12EndianStream12writeStringWMFAxuZv@Base 6
+ _D3std6stream12EndianStream3eofMFNdZb@Base 6
+ _D3std6stream12EndianStream4readMFJaZv@Base 6
+ _D3std6stream12EndianStream4readMFJcZv@Base 6
+ _D3std6stream12EndianStream4readMFJdZv@Base 6
+ _D3std6stream12EndianStream4readMFJeZv@Base 6
+ _D3std6stream12EndianStream4readMFJfZv@Base 6
+ _D3std6stream12EndianStream4readMFJgZv@Base 6
+ _D3std6stream12EndianStream4readMFJhZv@Base 6
+ _D3std6stream12EndianStream4readMFJiZv@Base 6
+ _D3std6stream12EndianStream4readMFJjZv@Base 6
+ _D3std6stream12EndianStream4readMFJkZv@Base 6
+ _D3std6stream12EndianStream4readMFJlZv@Base 6
+ _D3std6stream12EndianStream4readMFJmZv@Base 6
+ _D3std6stream12EndianStream4readMFJoZv@Base 6
+ _D3std6stream12EndianStream4readMFJpZv@Base 6
+ _D3std6stream12EndianStream4readMFJqZv@Base 6
+ _D3std6stream12EndianStream4readMFJrZv@Base 6
+ _D3std6stream12EndianStream4readMFJsZv@Base 6
+ _D3std6stream12EndianStream4readMFJtZv@Base 6
+ _D3std6stream12EndianStream4readMFJuZv@Base 6
+ _D3std6stream12EndianStream4readMFJwZv@Base 6
+ _D3std6stream12EndianStream4sizeMFNdZm@Base 6
+ _D3std6stream12EndianStream5fixBOMFPxvmZv@Base 6
+ _D3std6stream12EndianStream5getcwMFZu@Base 6
+ _D3std6stream12EndianStream5writeMFaZv@Base 6
+ _D3std6stream12EndianStream5writeMFcZv@Base 6
+ _D3std6stream12EndianStream5writeMFdZv@Base 6
+ _D3std6stream12EndianStream5writeMFeZv@Base 6
+ _D3std6stream12EndianStream5writeMFfZv@Base 6
+ _D3std6stream12EndianStream5writeMFgZv@Base 6
+ _D3std6stream12EndianStream5writeMFhZv@Base 6
+ _D3std6stream12EndianStream5writeMFiZv@Base 6
+ _D3std6stream12EndianStream5writeMFjZv@Base 6
+ _D3std6stream12EndianStream5writeMFkZv@Base 6
+ _D3std6stream12EndianStream5writeMFlZv@Base 6
+ _D3std6stream12EndianStream5writeMFmZv@Base 6
+ _D3std6stream12EndianStream5writeMFoZv@Base 6
+ _D3std6stream12EndianStream5writeMFpZv@Base 6
+ _D3std6stream12EndianStream5writeMFqZv@Base 6
+ _D3std6stream12EndianStream5writeMFrZv@Base 6
+ _D3std6stream12EndianStream5writeMFsZv@Base 6
+ _D3std6stream12EndianStream5writeMFtZv@Base 6
+ _D3std6stream12EndianStream5writeMFuZv@Base 6
+ _D3std6stream12EndianStream5writeMFwZv@Base 6
+ _D3std6stream12EndianStream6__ctorMFC3std6stream6StreamE3std6system6EndianZC3std6stream12EndianStream@Base 6
+ _D3std6stream12EndianStream6__initZ@Base 6
+ _D3std6stream12EndianStream6__vtblZ@Base 6
+ _D3std6stream12EndianStream7__ClassZ@Base 6
+ _D3std6stream12EndianStream7readBOMMFiZi@Base 6
+ _D3std6stream12EndianStream8writeBOMMFE3std6stream3BOMZv@Base 6
+ _D3std6stream12FilterStream10writeBlockMFxPvmZm@Base 6
+ _D3std6stream12FilterStream11resetSourceMFZv@Base 6
+ _D3std6stream12FilterStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream12FilterStream5closeMFZv@Base 6
+ _D3std6stream12FilterStream5flushMFZv@Base 6
+ _D3std6stream12FilterStream6__ctorMFC3std6stream6StreamZC3std6stream12FilterStream@Base 6
+ _D3std6stream12FilterStream6__initZ@Base 6
+ _D3std6stream12FilterStream6__vtblZ@Base 6
+ _D3std6stream12FilterStream6sourceMFC3std6stream6StreamZv@Base 6
+ _D3std6stream12FilterStream6sourceMFZC3std6stream6Stream@Base 6
+ _D3std6stream12FilterStream7__ClassZ@Base 6
+ _D3std6stream12FilterStream9availableMFNdZm@Base 6
+ _D3std6stream12FilterStream9readBlockMFPvmZm@Base 6
+ _D3std6stream12MemoryStream10writeBlockMFxPvmZm@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAaZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAgZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAhZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__initZ@Base 6
+ _D3std6stream12MemoryStream6__vtblZ@Base 6
+ _D3std6stream12MemoryStream7__ClassZ@Base 6
+ _D3std6stream12MemoryStream7reserveMFmZv@Base 6
+ _D3std6stream12MmFileStream5closeMFZv@Base 6
+ _D3std6stream12MmFileStream5flushMFZv@Base 6
+ _D3std6stream12MmFileStream6__ctorMFC3std6mmfile6MmFileZC3std6stream12MmFileStream@Base 6
+ _D3std6stream12MmFileStream6__initZ@Base 6
+ _D3std6stream12MmFileStream6__vtblZ@Base 6
+ _D3std6stream12MmFileStream7__ClassZ@Base 6
+ _D3std6stream12OutputStream11__InterfaceZ@Base 6
+ _D3std6stream12__ModuleInfoZ@Base 6
+ _D3std6stream13OpenException6__ctorMFAyaZC3std6stream13OpenException@Base 6
+ _D3std6stream13OpenException6__initZ@Base 6
+ _D3std6stream13OpenException6__vtblZ@Base 6
+ _D3std6stream13OpenException7__ClassZ@Base 6
+ _D3std6stream13ReadException6__ctorMFAyaZC3std6stream13ReadException@Base 6
+ _D3std6stream13ReadException6__initZ@Base 6
+ _D3std6stream13ReadException6__vtblZ@Base 6
+ _D3std6stream13ReadException7__ClassZ@Base 6
+ _D3std6stream13SeekException6__ctorMFAyaZC3std6stream13SeekException@Base 6
+ _D3std6stream13SeekException6__initZ@Base 6
+ _D3std6stream13SeekException6__vtblZ@Base 6
+ _D3std6stream13SeekException7__ClassZ@Base 6
+ _D3std6stream14BufferedStream10writeBlockMFxPvmZm@Base 6
+ _D3std6stream14BufferedStream11__invariantMxFZv@Base 6
+ _D3std6stream14BufferedStream11resetSourceMFZv@Base 6
+ _D3std6stream14BufferedStream12__invariant3MxFZv@Base 6
+ _D3std6stream14BufferedStream16__T9TreadLineTaZ8readLineMFAaZAa@Base 6
+ _D3std6stream14BufferedStream16__T9TreadLineTuZ8readLineMFAuZAu@Base 6
+ _D3std6stream14BufferedStream3eofMFNdZb@Base 6
+ _D3std6stream14BufferedStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream14BufferedStream4sizeMFNdZm@Base 6
+ _D3std6stream14BufferedStream5flushMFZv@Base 6
+ _D3std6stream14BufferedStream6__ctorMFC3std6stream6StreammZC3std6stream14BufferedStream@Base 6
+ _D3std6stream14BufferedStream6__initZ@Base 6
+ _D3std6stream14BufferedStream6__vtblZ@Base 6
+ _D3std6stream14BufferedStream7__ClassZ@Base 6
+ _D3std6stream14BufferedStream8readLineMFAaZAa@Base 6
+ _D3std6stream14BufferedStream9availableMFNdZm@Base 6
+ _D3std6stream14BufferedStream9readBlockMFPvmZm@Base 6
+ _D3std6stream14BufferedStream9readLineWMFAuZAu@Base 6
+ _D3std6stream14ByteOrderMarksyG5Ah@Base 6
+ _D3std6stream14WriteException6__ctorMFAyaZC3std6stream14WriteException@Base 6
+ _D3std6stream14WriteException6__initZ@Base 6
+ _D3std6stream14WriteException6__vtblZ@Base 6
+ _D3std6stream14WriteException7__ClassZ@Base 6
+ _D3std6stream15StreamException6__ctorMFAyaZC3std6stream15StreamException@Base 6
+ _D3std6stream15StreamException6__initZ@Base 6
+ _D3std6stream15StreamException6__vtblZ@Base 6
+ _D3std6stream15StreamException7__ClassZ@Base 6
+ _D3std6stream19StreamFileException6__ctorMFAyaZC3std6stream19StreamFileException@Base 6
+ _D3std6stream19StreamFileException6__initZ@Base 6
+ _D3std6stream19StreamFileException6__vtblZ@Base 6
+ _D3std6stream19StreamFileException7__ClassZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream10writeBlockMFxPvmZm@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream11__invariantMxFNaNbNiNfZv@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream15__invariant2467MxFNaNbNiNfZv@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream4dataMFNdZAh@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__ctorMFAhZC3std6stream21__T12TArrayStreamTAhZ12TArrayStream@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__initZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__vtblZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream7__ClassZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream8toStringMFZAya@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9availableMFNdZm@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9readBlockMFPvmZm@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream10writeBlockMFxPvmZm@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream11__invariantMxFZv@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream15__invariant2468MxFZv@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream4dataMFNdZAh@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__ctorMFC3std6mmfile6MmFileZC3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__initZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__vtblZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream7__ClassZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream8toStringMFZAya@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9availableMFNdZm@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9readBlockMFPvmZm@Base 6
+ _D3std6stream4File10writeBlockMFxPvmZm@Base 6
+ _D3std6stream4File4openMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream4File4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream4File5closeMFZv@Base 6
+ _D3std6stream4File6__ctorMFAyaE3std6stream8FileModeZC3std6stream4File@Base 6
+ _D3std6stream4File6__ctorMFZC3std6stream4File@Base 6
+ _D3std6stream4File6__ctorMFiE3std6stream8FileModeZC3std6stream4File@Base 6
+ _D3std6stream4File6__dtorMFZv@Base 6
+ _D3std6stream4File6__initZ@Base 6
+ _D3std6stream4File6__vtblZ@Base 6
+ _D3std6stream4File6createMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream4File6createMFAyaZv@Base 6
+ _D3std6stream4File6handleMFZi@Base 6
+ _D3std6stream4File7__ClassZ@Base 6
+ _D3std6stream4File9availableMFNdZm@Base 6
+ _D3std6stream4File9parseModeMFiJiJiJiZv@Base 6
+ _D3std6stream4File9readBlockMFPvmZm@Base 6
+ _D3std6stream6Stream10readStringMFmZAa@Base 6
+ _D3std6stream6Stream10writeExactMFxPvmZv@Base 6
+ _D3std6stream6Stream10writeLineWMFAxuZv@Base 6
+ _D3std6stream6Stream11readStringWMFmZAu@Base 6
+ _D3std6stream6Stream11writeStringMFAxaZv@Base 6
+ _D3std6stream6Stream12writeStringWMFAxuZv@Base 6
+ _D3std6stream6Stream14assertReadableMFZv@Base 6
+ _D3std6stream6Stream14assertSeekableMFZv@Base 6
+ _D3std6stream6Stream14ungetAvailableMFZb@Base 6
+ _D3std6stream6Stream15assertWriteableMFZv@Base 6
+ _D3std6stream6Stream16doFormatCallbackMFwZv@Base 6
+ _D3std6stream6Stream3eofMFNdZb@Base 6
+ _D3std6stream6Stream4getcMFZa@Base 6
+ _D3std6stream6Stream4readMFAhZm@Base 6
+ _D3std6stream6Stream4readMFJAaZv@Base 6
+ _D3std6stream6Stream4readMFJAuZv@Base 6
+ _D3std6stream6Stream4readMFJaZv@Base 6
+ _D3std6stream6Stream4readMFJcZv@Base 6
+ _D3std6stream6Stream4readMFJdZv@Base 6
+ _D3std6stream6Stream4readMFJeZv@Base 6
+ _D3std6stream6Stream4readMFJfZv@Base 6
+ _D3std6stream6Stream4readMFJgZv@Base 6
+ _D3std6stream6Stream4readMFJhZv@Base 6
+ _D3std6stream6Stream4readMFJiZv@Base 6
+ _D3std6stream6Stream4readMFJjZv@Base 6
+ _D3std6stream6Stream4readMFJkZv@Base 6
+ _D3std6stream6Stream4readMFJlZv@Base 6
+ _D3std6stream6Stream4readMFJmZv@Base 6
+ _D3std6stream6Stream4readMFJoZv@Base 6
+ _D3std6stream6Stream4readMFJpZv@Base 6
+ _D3std6stream6Stream4readMFJqZv@Base 6
+ _D3std6stream6Stream4readMFJrZv@Base 6
+ _D3std6stream6Stream4readMFJsZv@Base 6
+ _D3std6stream6Stream4readMFJtZv@Base 6
+ _D3std6stream6Stream4readMFJuZv@Base 6
+ _D3std6stream6Stream4readMFJwZv@Base 6
+ _D3std6stream6Stream4sizeMFNdZm@Base 6
+ _D3std6stream6Stream5closeMFZv@Base 6
+ _D3std6stream6Stream5flushMFZv@Base 6
+ _D3std6stream6Stream5getcwMFZu@Base 6
+ _D3std6stream6Stream5readfMFYi@Base 6
+ _D3std6stream6Stream5writeMFAxaZv@Base 6
+ _D3std6stream6Stream5writeMFAxhZm@Base 6
+ _D3std6stream6Stream5writeMFAxuZv@Base 6
+ _D3std6stream6Stream5writeMFaZv@Base 6
+ _D3std6stream6Stream5writeMFcZv@Base 6
+ _D3std6stream6Stream5writeMFdZv@Base 6
+ _D3std6stream6Stream5writeMFeZv@Base 6
+ _D3std6stream6Stream5writeMFfZv@Base 6
+ _D3std6stream6Stream5writeMFgZv@Base 6
+ _D3std6stream6Stream5writeMFhZv@Base 6
+ _D3std6stream6Stream5writeMFiZv@Base 6
+ _D3std6stream6Stream5writeMFjZv@Base 6
+ _D3std6stream6Stream5writeMFkZv@Base 6
+ _D3std6stream6Stream5writeMFlZv@Base 6
+ _D3std6stream6Stream5writeMFmZv@Base 6
+ _D3std6stream6Stream5writeMFoZv@Base 6
+ _D3std6stream6Stream5writeMFpZv@Base 6
+ _D3std6stream6Stream5writeMFqZv@Base 6
+ _D3std6stream6Stream5writeMFrZv@Base 6
+ _D3std6stream6Stream5writeMFsZv@Base 6
+ _D3std6stream6Stream5writeMFtZv@Base 6
+ _D3std6stream6Stream5writeMFuZv@Base 6
+ _D3std6stream6Stream5writeMFwZv@Base 6
+ _D3std6stream6Stream6__ctorMFZC3std6stream6Stream@Base 6
+ _D3std6stream6Stream6__initZ@Base 6
+ _D3std6stream6Stream6__vtblZ@Base 6
+ _D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _D3std6stream6Stream6printfMFAxaYm@Base 6
+ _D3std6stream6Stream6toHashMFNbNeZm@Base 6
+ _D3std6stream6Stream6toHashMFNeZ8resUnion6__initZ@Base 6
+ _D3std6stream6Stream6ungetcMFaZa@Base 6
+ _D3std6stream6Stream6vreadfMFAC8TypeInfoG1S3gcc8builtins13__va_list_tagZi@Base 6
+ _D3std6stream6Stream6writefMFYC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream7__ClassZ@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKAaZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKAuZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKmKAaZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKmKAuZiZi@Base 6
+ _D3std6stream6Stream7seekCurMFlZm@Base 6
+ _D3std6stream6Stream7seekEndMFlZm@Base 6
+ _D3std6stream6Stream7seekSetMFlZm@Base 6
+ _D3std6stream6Stream7ungetcwMFuZu@Base 6
+ _D3std6stream6Stream7vprintfMFAxaG1S3gcc8builtins13__va_list_tagZm@Base 6
+ _D3std6stream6Stream7writefxMFAC8TypeInfoG1S3gcc8builtins13__va_list_tagiZC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream8copyFromMFC3std6stream6StreamZv@Base 6
+ _D3std6stream6Stream8copyFromMFC3std6stream6StreammZv@Base 6
+ _D3std6stream6Stream8positionMFNdZm@Base 6
+ _D3std6stream6Stream8positionMFNdmZv@Base 6
+ _D3std6stream6Stream8readLineMFAaZAa@Base 6
+ _D3std6stream6Stream8readLineMFZAa@Base 6
+ _D3std6stream6Stream8toStringMFZAya@Base 6
+ _D3std6stream6Stream8writeflnMFYC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream9availableMFNdZm@Base 6
+ _D3std6stream6Stream9readExactMFPvmZv@Base 6
+ _D3std6stream6Stream9readLineWMFAuZAu@Base 6
+ _D3std6stream6Stream9readLineWMFZAu@Base 6
+ _D3std6stream6Stream9writeLineMFAxaZv@Base 6
+ _D3std6stream8FileMode6__initZ@Base 6
+ _D3std6stream9BOMEndianyG5E3std6system6Endian@Base 6
+ _D3std6string11fromStringzFNaNbNiPNgaZANga@Base 6
+ _D3std6string12__ModuleInfoZ@Base 6
+ _D3std6string14__T5chompTAxaZ5chompFNaNbNiNfAxaZAxa@Base 6
+ _D3std6string14__T5stripTAyaZ5stripFNaNfAyaZAya@Base 6
+ _D3std6string14makeTransTableFNaNbNiNfxAaxAaZG256a@Base 6
+ _D3std6string15StringException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std6string15StringException@Base 6
+ _D3std6string15StringException6__initZ@Base 6
+ _D3std6string15StringException6__vtblZ@Base 6
+ _D3std6string15StringException7__ClassZ@Base 6
+ _D3std6string16__T7indexOfTAyaZ7indexOfFNaNbNiNfAyaxwxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZl@Base 6
+ _D3std6string18__T5munchTAyaTAyaZ5munchFNaNiNfKAyaAyaZAya@Base 6
+ _D3std6string18__T7indexOfTAyaTaZ7indexOfFAyaAxaxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZ18__T9__lambda4TwTwZ9__lambda4FNaNbNiNfwwZb@Base 6
+ _D3std6string18__T7indexOfTAyaTaZ7indexOfFNaNfAyaAxaxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZl@Base 6
+ _D3std6string18__T9inPatternTAyaZ9inPatternFNaNiNfwxAyaZb@Base 6
+ _D3std6string18__T9soundexerTAxaZ9soundexerFAxaZ3dexyAa@Base 6
+ _D3std6string18__T9soundexerTAxaZ9soundexerFNaNbNiNfAxaZG4a@Base 6
+ _D3std6string18__T9stripLeftTAyaZ9stripLeftFNaNfAyaZAya@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result10initializeMFNaNbNiNfZv@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result11__xopEqualsFKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZb@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result4saveMFNaNbNdNiNfZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result5frontMFNaNbNdNiNfZw@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result6__ctorMFNaNbNcNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result6__initZ@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result9__xtoHashFNbNeKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZm@Base 6
+ _D3std6string19__T11lastIndexOfTaZ11lastIndexOfFNaNiNfAxaxwxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZl@Base 6
+ _D3std6string20__T10stripRightTAyaZ10stripRightFNaNiNfAyaZAya@Base 6
+ _D3std6string22__T12rightJustifyTAyaZ12rightJustifyFNaNbNfAyamwZAya@Base 6
+ _D3std6string23__T14representationTyaZ14representationFNaNbNiNfAyaZAyh@Base 6
+ _D3std6string24__T14rightJustifierTAyaZ14rightJustifierFNaNbNiNfAyamwZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl@Base 6
+ _D3std6string6abbrevFNaNfAAyaZHAyaAya@Base 6
+ _D3std6string7soundexFNaNbNfAxaAaZAa@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda3TAxaTAyaZ9__lambda3FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda4TAxaTAyaZ9__lambda4FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda5TAxaTAyaZ9__lambda5FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZb@Base 6
+ _D3std6string9makeTransFNaNbNexAaxAaZAya@Base 6
+ _D3std6string9toStringzFNaNbNeAxaZPya@Base 6
+ _D3std6string9toStringzFNaNbNexAyaZPya@Base 6
+ _D3std6system12__ModuleInfoZ@Base 6
+ _D3std6system2OS6__initZ@Base 6
+ _D3std6system2osyE3std6system2OS@Base 6
+ _D3std6system6endianyE3std6system6Endian@Base 6
+ _D3std6traits12__ModuleInfoZ@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle11__xopEqualsFKxS3std6traits15__T8DemangleTkZ8DemangleKxS3std6traits15__T8DemangleTkZ8DemangleZb@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle6__initZ@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle9__xtoHashFNbNeKxS3std6traits15__T8DemangleTkZ8DemangleZm@Base 6
+ _D3std6traits19removeDummyEnvelopeFAyaZAya@Base 6
+ _D3std6traits23__InoutWorkaroundStruct6__initZ@Base 6
+ _D3std6traits26demangleFunctionAttributesFAyaZS3std6traits15__T8DemangleTkZ8Demangle@Base 6
+ _D3std6traits29demangleParameterStorageClassFAyaZS3std6traits15__T8DemangleTkZ8Demangle@Base 6
+ _D3std7complex12__ModuleInfoZ@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex11__xopEqualsFKxS3std7complex14__T7ComplexTeZ7ComplexKxS3std7complex14__T7ComplexTeZ7ComplexZb@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex15__T8toStringTaZ8toStringMxFMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex16__T8opEqualsHTeZ8opEqualsMxFNaNbNiNfS3std7complex14__T7ComplexTeZ7ComplexZb@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex17__T6__ctorHTeHTeZ6__ctorMFNaNbNcNiNfeeZS3std7complex14__T7ComplexTeZ7Complex@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex6__initZ@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex8toStringMxFZAya@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex9__xtoHashFNbNeKxS3std7complex14__T7ComplexTeZ7ComplexZm@Base 6
+ _D3std7complex4expiFNaNbNiNeeZS3std7complex14__T7ComplexTeZ7Complex@Base 6
+ _D3std7cstream12__ModuleInfoZ@Base 6
+ _D3std7cstream18_sharedStaticCtor2FZv@Base 6
+ _D3std7cstream3dinC3std7cstream5CFile@Base 6
+ _D3std7cstream4derrC3std7cstream5CFile@Base 6
+ _D3std7cstream4doutC3std7cstream5CFile@Base 6
+ _D3std7cstream5CFile10writeBlockMFxPvmZm@Base 6
+ _D3std7cstream5CFile10writeLineWMFAxuZv@Base 6
+ _D3std7cstream5CFile3eofMFZb@Base 6
+ _D3std7cstream5CFile4fileMFNdPOS4core4stdc5stdio8_IO_FILEZv@Base 6
+ _D3std7cstream5CFile4fileMFNdZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std7cstream5CFile4getcMFZa@Base 6
+ _D3std7cstream5CFile4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std7cstream5CFile5closeMFZv@Base 6
+ _D3std7cstream5CFile5flushMFZv@Base 6
+ _D3std7cstream5CFile6__ctorMFPOS4core4stdc5stdio8_IO_FILEE3std6stream8FileModebZC3std7cstream5CFile@Base 6
+ _D3std7cstream5CFile6__dtorMFZv@Base 6
+ _D3std7cstream5CFile6__initZ@Base 6
+ _D3std7cstream5CFile6__vtblZ@Base 6
+ _D3std7cstream5CFile6ungetcMFaZa@Base 6
+ _D3std7cstream5CFile7__ClassZ@Base 6
+ _D3std7cstream5CFile9readBlockMFPvmZm@Base 6
+ _D3std7cstream5CFile9writeLineMFAxaZv@Base 6
+ _D3std7numeric12__ModuleInfoZ@Base 6
+ _D3std7numeric12isPowerOfTwoFmZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride11__xopEqualsFKxS3std7numeric14__T6StrideTAfZ6StrideKxS3std7numeric14__T6StrideTAfZ6StrideZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride11doubleStepsMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride4saveMFNaNbNdNiNfZS3std7numeric14__T6StrideTAfZ6Stride@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride5frontMFNaNbNdNiNfZf@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6__ctorMFNaNbNcNiNfAfmZS3std7numeric14__T6StrideTAfZ6Stride@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6__initZ@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6nStepsMFNaNbNdNiNfmZm@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6nStepsMxFNaNbNdNiNfZm@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride7opIndexMFNaNbNiNfmZf@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride7popHalfMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride8popFrontMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride9__xtoHashFNbNeKxS3std7numeric14__T6StrideTAfZ6StrideZm@Base 6
+ _D3std7numeric16CustomFloatFlags6__initZ@Base 6
+ _D3std7numeric19roundDownToPowerOf2FmZm@Base 6
+ _D3std7numeric24__T13oppositeSignsTyeTeZ13oppositeSignsFNaNbNiNfyeeZb@Base 6
+ _D3std7numeric29__T8findRootTeTDFNaNbNiNfeZeZ8findRootFMDFNaNbNiNfeZexexeZ9__lambda4FNaNbNiNfeeZb@Base 6
+ _D3std7numeric29__T8findRootTeTDFNaNbNiNfeZeZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexeZe@Base 6
+ _D3std7numeric3Fft4sizeMxFNdZm@Base 6
+ _D3std7numeric3Fft6__ctorMFAfZC3std7numeric3Fft@Base 6
+ _D3std7numeric3Fft6__ctorMFmZC3std7numeric3Fft@Base 6
+ _D3std7numeric3Fft6__initZ@Base 6
+ _D3std7numeric3Fft6__vtblZ@Base 6
+ _D3std7numeric3Fft7__ClassZ@Base 6
+ _D3std7numeric44__T8findRootTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexeMPFNaNbNiNfeeZbZe@Base 6
+ _D3std7numeric46__T8findRootTeTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFMDFNaNbNiNfeZexexexexeMPFNaNbNiNfeeZbZ18secant_interpolateFNaNbNiNfeeeeZe@Base 6
+ _D3std7numeric46__T8findRootTeTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexexexeMPFNaNbNiNfeeZbZS3std8typecons18__T5TupleTeTeTeTeZ5Tuple@Base 6
+ _D3std7numeric5bsr64FmZ5Ulong6__initZ@Base 6
+ _D3std7numeric5bsr64FmZi@Base 6
+ _D3std7process10setCLOEXECFibZv@Base 6
+ _D3std7process10spawnShellFNexAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process10spawnShellFNexAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process10toAStringzFxAAyaPPxaZv@Base 6
+ _D3std7process11environment13opIndexAssignFNeNgAaxAaZANga@Base 6
+ _D3std7process11environment3getFNfxAaAyaZAya@Base 6
+ _D3std7process11environment4toAAFNeZHAyaAya@Base 6
+ _D3std7process11environment6__initZ@Base 6
+ _D3std7process11environment6__vtblZ@Base 6
+ _D3std7process11environment6removeFNbNiNexAaZv@Base 6
+ _D3std7process11environment7__ClassZ@Base 6
+ _D3std7process11environment7getImplFNexAaJAyaZ10lastResultAya@Base 6
+ _D3std7process11environment7getImplFNexAaJAyaZb@Base 6
+ _D3std7process11environment7opIndexFNfxAaZAya@Base 6
+ _D3std7process11pipeProcessFNfxAAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process11pipeProcessFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process11shellSwitchyAa@Base 6
+ _D3std7process12ProcessPipes11__fieldDtorMFNeZv@Base 6
+ _D3std7process12ProcessPipes11__xopEqualsFKxS3std7process12ProcessPipesKxS3std7process12ProcessPipesZb@Base 6
+ _D3std7process12ProcessPipes15__fieldPostblitMFNeZv@Base 6
+ _D3std7process12ProcessPipes3pidMFNbNdNfZC3std7process3Pid@Base 6
+ _D3std7process12ProcessPipes5stdinMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes6__initZ@Base 6
+ _D3std7process12ProcessPipes6stderrMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes6stdoutMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes8opAssignMFNcNjNeS3std7process12ProcessPipesZS3std7process12ProcessPipes@Base 6
+ _D3std7process12ProcessPipes9__xtoHashFNbNeKxS3std7process12ProcessPipesZm@Base 6
+ _D3std7process12__ModuleInfoZ@Base 6
+ _D3std7process12executeShellFNexAaxHAyaAyaE3std7process6ConfigmxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process12isExecutableFNbNiNexAaZb@Base 6
+ _D3std7process12spawnProcessFNexAAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process136__T11executeImplS111_D3std7process9pipeShellFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipesTAxaZ11executeImplFAxaxHAyaAyaE3std7process6ConfigmxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process13charAllocatorFNaNbNfmZAa@Base 6
+ _D3std7process13searchPathForFNexAaZAya@Base 6
+ _D3std7process13thisProcessIDFNbNdNeZi@Base 6
+ _D3std7process16ProcessException12newFromErrnoFAyaAyamZC3std7process16ProcessException@Base 6
+ _D3std7process16ProcessException6__ctorMFAyaAyamZC3std7process16ProcessException@Base 6
+ _D3std7process16ProcessException6__initZ@Base 6
+ _D3std7process16ProcessException6__vtblZ@Base 6
+ _D3std7process16ProcessException7__ClassZ@Base 6
+ _D3std7process16spawnProcessImplFNexAAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process18escapeShellCommandFNaNfxAAaXAya@Base 6
+ _D3std7process19escapePosixArgumentFNaNbNexAaZAya@Base 6
+ _D3std7process19escapeShellFileNameFNaNbNexAaZAya@Base 6
+ _D3std7process20escapeShellArgumentsFNaNbNexAAaX9allocatorMFNaNbNfmZAa@Base 6
+ _D3std7process20escapeShellArgumentsFNaNbNexAAaXAya@Base 6
+ _D3std7process21escapeWindowsArgumentFNaNbNexAaZAya@Base 6
+ _D3std7process24escapeShellCommandStringFNaNfAyaZAya@Base 6
+ _D3std7process25escapeWindowsShellCommandFNaNfxAaZAya@Base 6
+ _D3std7process3Pid11performWaitMFNebZi@Base 6
+ _D3std7process3Pid6__ctorMFNaNbNfiZC3std7process3Pid@Base 6
+ _D3std7process3Pid6__initZ@Base 6
+ _D3std7process3Pid6__vtblZ@Base 6
+ _D3std7process3Pid7__ClassZ@Base 6
+ _D3std7process3Pid8osHandleMFNaNbNdNfZi@Base 6
+ _D3std7process3Pid9processIDMxFNaNbNdNfZi@Base 6
+ _D3std7process49__T11executeImplS253std7process11pipeProcessTAxaZ11executeImplFAxaxHAyaAyaE3std7process6ConfigmxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process4Pipe11__fieldDtorMFNeZv@Base 6
+ _D3std7process4Pipe11__xopEqualsFKxS3std7process4PipeKxS3std7process4PipeZb@Base 6
+ _D3std7process4Pipe15__fieldPostblitMFNeZv@Base 6
+ _D3std7process4Pipe5closeMFNfZv@Base 6
+ _D3std7process4Pipe6__initZ@Base 6
+ _D3std7process4Pipe7readEndMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process4Pipe8opAssignMFNcNjNeS3std7process4PipeZS3std7process4Pipe@Base 6
+ _D3std7process4Pipe8writeEndMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process4Pipe9__xtoHashFNbNeKxS3std7process4PipeZm@Base 6
+ _D3std7process4killFC3std7process3PidZv@Base 6
+ _D3std7process4killFC3std7process3PidiZv@Base 6
+ _D3std7process4pipeFNeZS3std7process4Pipe@Base 6
+ _D3std7process4waitFNfC3std7process3PidZi@Base 6
+ _D3std7process50__T11executeImplS253std7process11pipeProcessTAxAaZ11executeImplFAxAaxHAyaAyaE3std7process6ConfigmxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process52__T15pipeProcessImplS243std7process10spawnShellTAxaZ15pipeProcessImplFNeAxaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process54__T15pipeProcessImplS263std7process12spawnProcessTAxaZ15pipeProcessImplFNeAxaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process55__T15pipeProcessImplS263std7process12spawnProcessTAxAaZ15pipeProcessImplFNeAxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process5execvFxAyaxAAyaZi@Base 6
+ _D3std7process5shellFAyaZAya@Base 6
+ _D3std7process6browseFAyaZv@Base 6
+ _D3std7process6execv_FxAyaxAAyaZi@Base 6
+ _D3std7process6execveFxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process6execvpFxAyaxAAyaZi@Base 6
+ _D3std7process6getenvFNbxAaZ10lastResultAya@Base 6
+ _D3std7process6getenvFNbxAaZAya@Base 6
+ _D3std7process6setenvFxAaxAabZv@Base 6
+ _D3std7process6systemFAyaZi@Base 6
+ _D3std7process72__T23escapePosixArgumentImplS40_D3std7process13charAllocatorFNaNbNfmZAaZ23escapePosixArgumentImplFNaNbNfxAaZAa@Base 6
+ _D3std7process74__T25escapeWindowsArgumentImplS40_D3std7process13charAllocatorFNaNbNfmZAaZ25escapeWindowsArgumentImplFNaNbNfxAaZAa@Base 6
+ _D3std7process7executeFNexAAaxHAyaAyaE3std7process6ConfigmxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process7executeFNexAaxHAyaAyaE3std7process6ConfigmxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process7execve_FxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process7execvp_FxAyaxAAyaZi@Base 6
+ _D3std7process7execvpeFxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process7spawnvpFiAyaAAyaZi@Base 6
+ _D3std7process7tryWaitFNfC3std7process3PidZS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple@Base 6
+ _D3std7process8Redirect6__initZ@Base 6
+ _D3std7process8_spawnvpFixPaxPPaZi@Base 6
+ _D3std7process8execvpe_FxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process8unsetenvFxAaZv@Base 6
+ _D3std7process9createEnvFxHAyaAyabZPxPa@Base 6
+ _D3std7process9pipeShellFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process9userShellFNdNfZAya@Base 6
+ _D3std7signals12__ModuleInfoZ@Base 6
+ _D3std7signals6linkinFZv@Base 6
+ _D3std7variant12__ModuleInfoZ@Base 6
+ _D3std7variant16VariantException6__ctorMFAyaZC3std7variant16VariantException@Base 6
+ _D3std7variant16VariantException6__ctorMFC8TypeInfoC8TypeInfoZC3std7variant16VariantException@Base 6
+ _D3std7variant16VariantException6__initZ@Base 6
+ _D3std7variant16VariantException6__vtblZ@Base 6
+ _D3std7variant16VariantException7__ClassZ@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN10__T3getTbZ3getMNgFNdZNgb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN10__T3getTiZ3getMNgFNdZNgi@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN10__T3getTmZ3getMNgFNdZNgm@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN10__postblitMFZv@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN113__T3getTS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ3getMNgFNdZNgS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN115__T3getTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ3getMNgFNdZNgS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN118__T6__ctorTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ6__ctorMFNcS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ10tryPuttingFPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ6getPtrFNaNbNiPvZPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ7compareFPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TuplePS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN11SizeChecker6__initZ@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN11__T3getTyhZ3getMNgFNdZyh@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN11__T4peekTvZ4peekMNgFNdZPNgv@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN11__xopEqualsFKxS3std7variant18__T8VariantNVmi32Z8VariantNKxS3std7variant18__T8VariantNVmi32Z8VariantNZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN120__T8opAssignTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opAssignMFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN121__T10convertsToTS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN123__T10convertsToTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN12__T3getTAyhZ3getMNgFNdZNgAyh@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN15__T6__ctorTAyhZ6__ctorMFNcAyhZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN15__T7handlerHTvZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ10tryPuttingFPyhC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ6getPtrFNaNbNiPvZPyh@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ7compareFNaNbNiNfPyhPyhE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ10tryPuttingFPAyhC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ6getPtrFNaNbNiPvZPAyh@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ7compareFNaNbNiNfPAyhPAyhE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN16__T8opAssignTyhZ8opAssignMFyhZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN17__T8opAssignTAyhZ8opAssignMFAyhZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN18__T10convertsToTbZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN18__T10convertsToTiZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN19__T10convertsToTyhZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN20__T10convertsToTAyhZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN27__T3getTC6object9ThrowableZ3getMNgFNdZNgC6object9Throwable@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN28__T3getTOC6object9ThrowableZ3getMNgFNdZONgC6object9Throwable@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN31__T3getTS3std11concurrency3TidZ3getMNgFNdZNgS3std11concurrency3Tid@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN34__T6__ctorTS3std11concurrency3TidZ6__ctorMFNcS3std11concurrency3TidZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN35__T10convertsToTC6object9ThrowableZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ10tryPuttingFPS3std11concurrency3TidC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ6getPtrFNaNbNiPvZPS3std11concurrency3Tid@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ7compareFPS3std11concurrency3TidPS3std11concurrency3TidE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN36__T10convertsToTOC6object9ThrowableZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN36__T8opAssignTS3std11concurrency3TidZ8opAssignMFS3std11concurrency3TidZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN39__T10convertsToTS3std11concurrency3TidZ10convertsToMxFNdZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN46__T6__ctorTC3std11concurrency14LinkTerminatedZ6__ctorMFNcC3std11concurrency14LinkTerminatedZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN47__T6__ctorTC3std11concurrency15OwnerTerminatedZ6__ctorMFNcC3std11concurrency15OwnerTerminatedZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ10tryPuttingFPC3std11concurrency14LinkTerminatedC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ6getPtrFNaNbNiPvZPC3std11concurrency14LinkTerminated@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ7compareFPC3std11concurrency14LinkTerminatedPC3std11concurrency14LinkTerminatedE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ10tryPuttingFPC3std11concurrency15OwnerTerminatedC8TypeInfoPvZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ6getPtrFNaNbNiPvZPC3std11concurrency15OwnerTerminated@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZ7compareFPC3std11concurrency15OwnerTerminatedPC3std11concurrency15OwnerTerminatedE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVmi32Z8VariantN4OpIDPG32hPvZl@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN48__T8opAssignTC3std11concurrency14LinkTerminatedZ8opAssignMFC3std11concurrency14LinkTerminatedZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN49__T8opAssignTC3std11concurrency15OwnerTerminatedZ8opAssignMFC3std11concurrency15OwnerTerminatedZS3std7variant18__T8VariantNVmi32Z8VariantN@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN4typeMxFNbNdNeZC8TypeInfo@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN53__T5opCmpTS3std7variant18__T8VariantNVmi32Z8VariantNZ5opCmpMFS3std7variant18__T8VariantNVmi32Z8VariantNZi@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN56__T8opEqualsTS3std7variant18__T8VariantNVmi32Z8VariantNZ8opEqualsMxFKS3std7variant18__T8VariantNVmi32Z8VariantNZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN57__T8opEqualsTxS3std7variant18__T8VariantNVmi32Z8VariantNZ8opEqualsMxFKxS3std7variant18__T8VariantNVmi32Z8VariantNZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN5opCmpMxFKxS3std7variant18__T8VariantNVmi32Z8VariantNZi@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN6__dtorMFZv@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN6__initZ@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN6lengthMFNdZm@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN6toHashMxFNbNfZm@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN8hasValueMxFNaNbNdNiNfZb@Base 6
+ _D3std7variant18__T8VariantNVmi32Z8VariantN8toStringMFZAya@Base 6
+ _D3std7windows7charset12__ModuleInfoZ@Base 6
+ _D3std7windows8iunknown12__ModuleInfoZ@Base 6
+ _D3std7windows8registry12__ModuleInfoZ@Base 6
+ _D3std7windows8syserror12__ModuleInfoZ@Base 6
+ _D3std8bitmanip10myToStringFmZAya@Base 6
+ _D3std8bitmanip11myToStringxFmZAya@Base 6
+ _D3std8bitmanip12__ModuleInfoZ@Base 6
+ _D3std8bitmanip14__T7BitsSetTmZ7BitsSet4saveMFNaNbNdNiNfZS3std8bitmanip14__T7BitsSetTmZ7BitsSet@Base 6
+ _D3std8bitmanip14__T7BitsSetTmZ7BitsSet5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip14__T7BitsSetTmZ7BitsSet5frontMFNaNbNdNiNfZm@Base 6
+ _D3std8bitmanip14__T7BitsSetTmZ7BitsSet6__ctorMFNaNbNcNiNfmmZS3std8bitmanip14__T7BitsSetTmZ7BitsSet@Base 6
+ _D3std8bitmanip14__T7BitsSetTmZ7BitsSet6__initZ@Base 6
+ _D3std8bitmanip14__T7BitsSetTmZ7BitsSet6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std8bitmanip14__T7BitsSetTmZ7BitsSet8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNekZk@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNemZm@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNftZt@Base 6
+ _D3std8bitmanip15getBitsForAlignFmZm@Base 6
+ _D3std8bitmanip18__T10swapEndianTaZ10swapEndianFNaNbNiNfaZa@Base 6
+ _D3std8bitmanip18__T10swapEndianTbZ10swapEndianFNaNbNiNfbZb@Base 6
+ _D3std8bitmanip18__T10swapEndianThZ10swapEndianFNaNbNiNfhZh@Base 6
+ _D3std8bitmanip18__T10swapEndianTiZ10swapEndianFNaNbNiNfiZi@Base 6
+ _D3std8bitmanip18__T10swapEndianTlZ10swapEndianFNaNbNiNflZl@Base 6
+ _D3std8bitmanip18__T10swapEndianTmZ10swapEndianFNaNbNiNfmZm@Base 6
+ _D3std8bitmanip20__T12countBitsSetTmZ12countBitsSetFNaNbNiNfmZk@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTaZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTbZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperThZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTiZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTkZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTlZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTmZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTtZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip22__T13EndianSwapperTxkZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip26__T18countTrailingZerosTmZ18countTrailingZerosFNaNbNiNfmZk@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTkZ20nativeToLittleEndianFNaNbNiNfkZG4h@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTmZ20nativeToLittleEndianFNaNbNiNfmZG8h@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTtZ20nativeToLittleEndianFNaNbNiNftZG2h@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTaVmi1Z17bigEndianToNativeFNaNbNiNfG1hZa@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTbVmi1Z17bigEndianToNativeFNaNbNiNfG1hZb@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeThVmi1Z17bigEndianToNativeFNaNbNiNfG1hZh@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTiVmi4Z17bigEndianToNativeFNaNbNiNfG4hZi@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTlVmi8Z17bigEndianToNativeFNaNbNiNfG8hZl@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTmVmi8Z17bigEndianToNativeFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip29__T20nativeToLittleEndianTxkZ20nativeToLittleEndianFNaNbNiNfxkZG4h@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTkVmi4Z20littleEndianToNativeFNaNbNiNfG4hZk@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTmVmi8Z20littleEndianToNativeFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTtVmi2Z20littleEndianToNativeFNaNbNiNfG2hZt@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTkZ24nativeToLittleEndianImplFNaNbNiNfkZG4h@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTmZ24nativeToLittleEndianImplFNaNbNiNfmZG8h@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTtZ24nativeToLittleEndianImplFNaNbNiNftZG2h@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTaVmi1Z21bigEndianToNativeImplFNaNbNiNfG1hZa@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTbVmi1Z21bigEndianToNativeImplFNaNbNiNfG1hZb@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplThVmi1Z21bigEndianToNativeImplFNaNbNiNfG1hZh@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTiVmi4Z21bigEndianToNativeImplFNaNbNiNfG4hZi@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTlVmi8Z21bigEndianToNativeImplFNaNbNiNfG8hZl@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTmVmi8Z21bigEndianToNativeImplFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip33__T24nativeToLittleEndianImplTxkZ24nativeToLittleEndianImplFNaNbNiNfxkZG4h@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTkVmi4Z24littleEndianToNativeImplFNaNbNiNfG4hZk@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTmVmi8Z24littleEndianToNativeImplFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTtVmi2Z24littleEndianToNativeImplFNaNbNiNfG2hZt@Base 6
+ _D3std8bitmanip8BitArray11opCatAssignMFNaNbS3std8bitmanip8BitArrayZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray11opCatAssignMFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray13opIndexAssignMFNaNbNibmZb@Base 6
+ _D3std8bitmanip8BitArray14formatBitArrayMxFMDFAxaZvZv@Base 6
+ _D3std8bitmanip8BitArray15formatBitStringMxFMDFAxaZvZv@Base 6
+ _D3std8bitmanip8BitArray3dimMxFNaNbNdNiZm@Base 6
+ _D3std8bitmanip8BitArray3dupMxFNaNbNdZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray4initMFNaNbAbZv@Base 6
+ _D3std8bitmanip8BitArray4initMFNaNbAvmZv@Base 6
+ _D3std8bitmanip8BitArray4sortMFNaNbNdNiZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCatMxFNaNbS3std8bitmanip8BitArrayZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCatMxFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCmpMxFNaNbNiS3std8bitmanip8BitArrayZi@Base 6
+ _D3std8bitmanip8BitArray5opComMxFNaNbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNaNbNcAbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNaNbNcAvmZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNcmPmZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__initZ@Base 6
+ _D3std8bitmanip8BitArray6lengthMFNaNbNdmZm@Base 6
+ _D3std8bitmanip8BitArray6lengthMxFNaNbNdNiZm@Base 6
+ _D3std8bitmanip8BitArray6toHashMxFNaNbNiZm@Base 6
+ _D3std8bitmanip8BitArray7bitsSetMxFNaNbNdZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std8bitmanip8BitArray7endBitsMxFNaNbNdNiZm@Base 6
+ _D3std8bitmanip8BitArray7endMaskMxFNaNbNdNiZm@Base 6
+ _D3std8bitmanip8BitArray7opApplyMFMDFKbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMFMDFmKbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMxFMDFbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMxFMDFmbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opCat_rMxFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray7opIndexMxFNaNbNimZb@Base 6
+ _D3std8bitmanip8BitArray7reverseMFNaNbNdNiZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray8lenToDimFNaNbNimZm@Base 6
+ _D3std8bitmanip8BitArray8opEqualsMxFNaNbNiKxS3std8bitmanip8BitArrayZb@Base 6
+ _D3std8bitmanip8BitArray8toStringMxFMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std8bitmanip8BitArray9fullWordsMxFNaNbNdNiZm@Base 6
+ _D3std8bitmanip8FloatRep11__xopEqualsFKxS3std8bitmanip8FloatRepKxS3std8bitmanip8FloatRepZb@Base 6
+ _D3std8bitmanip8FloatRep4signMFNaNbNdNiNfbZv@Base 6
+ _D3std8bitmanip8FloatRep4signMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip8FloatRep6__initZ@Base 6
+ _D3std8bitmanip8FloatRep8exponentMFNaNbNdNiNfhZv@Base 6
+ _D3std8bitmanip8FloatRep8exponentMxFNaNbNdNiNfZh@Base 6
+ _D3std8bitmanip8FloatRep8fractionMFNaNbNdNiNfkZv@Base 6
+ _D3std8bitmanip8FloatRep8fractionMxFNaNbNdNiNfZk@Base 6
+ _D3std8bitmanip8FloatRep9__xtoHashFNbNeKxS3std8bitmanip8FloatRepZm@Base 6
+ _D3std8bitmanip9DoubleRep11__xopEqualsFKxS3std8bitmanip9DoubleRepKxS3std8bitmanip9DoubleRepZb@Base 6
+ _D3std8bitmanip9DoubleRep4signMFNaNbNdNiNfbZv@Base 6
+ _D3std8bitmanip9DoubleRep4signMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip9DoubleRep6__initZ@Base 6
+ _D3std8bitmanip9DoubleRep8exponentMFNaNbNdNiNftZv@Base 6
+ _D3std8bitmanip9DoubleRep8exponentMxFNaNbNdNiNfZt@Base 6
+ _D3std8bitmanip9DoubleRep8fractionMFNaNbNdNiNfmZv@Base 6
+ _D3std8bitmanip9DoubleRep8fractionMxFNaNbNdNiNfZm@Base 6
+ _D3std8bitmanip9DoubleRep9__xtoHashFNbNeKxS3std8bitmanip9DoubleRepZm@Base 6
+ _D3std8compiler12__ModuleInfoZ@Base 6
+ _D3std8compiler13version_majoryk@Base 6
+ _D3std8compiler13version_minoryk@Base 6
+ _D3std8compiler4nameyAa@Base 6
+ _D3std8compiler6vendoryE3std8compiler6Vendor@Base 6
+ _D3std8compiler7D_majoryk@Base 6
+ _D3std8compiler7D_minoryk@Base 6
+ _D3std8datetime11_monthNamesyG12Aa@Base 6
+ _D3std8datetime11lastDayLeapyG13i@Base 6
+ _D3std8datetime11setTZEnvVarFNbNeAyaZv@Base 6
+ _D3std8datetime11timeStringsyAAa@Base 6
+ _D3std8datetime12__ModuleInfoZ@Base 6
+ _D3std8datetime12cmpTimeUnitsFNaNfAyaAyaZi@Base 6
+ _D3std8datetime12getDayOfWeekFNaNbNfiZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime13PosixTimeZone10LeapSecond6__ctorMFNaNcNfliZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone10TempTTInfo6__ctorMFNaNcNfibhZS3std8datetime13PosixTimeZone10TempTTInfo@Base 6
+ _D3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone10Transition6__ctorMFNaNcNflPyS3std8datetime13PosixTimeZone6TTInfoZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime13PosixTimeZone11getTimeZoneFNeAyaAyaZyC3std8datetime13PosixTimeZone@Base 6
+ _D3std8datetime13PosixTimeZone14TempTransition6__ctorMFNaNcNflPyS3std8datetime13PosixTimeZone6TTInfoPS3std8datetime13PosixTimeZone14TransitionTypeZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone14TransitionType6__ctorMFNaNcNfbbZS3std8datetime13PosixTimeZone14TransitionType@Base 6
+ _D3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTaZ7readValFNeKS3std5stdio4FileZa@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTbZ7readValFNeKS3std5stdio4FileZb@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValThZ7readValFNeKS3std5stdio4FileZh@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTiZ7readValFNeKS3std5stdio4FileZi@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTlZ7readValFNeKS3std5stdio4FileZl@Base 6
+ _D3std8datetime13PosixTimeZone15__T7readValTAaZ7readValFNeKS3std5stdio4FilemZAa@Base 6
+ _D3std8datetime13PosixTimeZone15__T7readValTAhZ7readValFNeKS3std5stdio4FilemZAh@Base 6
+ _D3std8datetime13PosixTimeZone19_enforceValidTZFileFNaNfbmZv@Base 6
+ _D3std8datetime13PosixTimeZone19getInstalledTZNamesFNeAyaAyaZAAya@Base 6
+ _D3std8datetime13PosixTimeZone20calculateLeapSecondsMxFNaNbNflZi@Base 6
+ _D3std8datetime13PosixTimeZone54__T7readValTS3std8datetime13PosixTimeZone10TempTTInfoZ7readValFNfKS3std5stdio4FileZS3std8datetime13PosixTimeZone10TempTTInfo@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo11__xopEqualsFKxS3std8datetime13PosixTimeZone6TTInfoKxS3std8datetime13PosixTimeZone6TTInfoZb@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo6__ctorMyFNaNcNfxS3std8datetime13PosixTimeZone10TempTTInfoAyaZyS3std8datetime13PosixTimeZone6TTInfo@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo9__xtoHashFNbNeKxS3std8datetime13PosixTimeZone6TTInfoZm@Base 6
+ _D3std8datetime13PosixTimeZone6__ctorMyFNaNfyAS3std8datetime13PosixTimeZone10TransitionyAS3std8datetime13PosixTimeZone10LeapSecondAyaAyaAyabZyC3std8datetime13PosixTimeZone@Base 6
+ _D3std8datetime13PosixTimeZone6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone6__vtblZ@Base 6
+ _D3std8datetime13PosixTimeZone6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime13PosixTimeZone7__ClassZ@Base 6
+ _D3std8datetime13PosixTimeZone7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime13PosixTimeZone7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime13clearTZEnvVarFNbNeZv@Base 6
+ _D3std8datetime13monthToStringFNaNfE3std8datetime5MonthZAya@Base 6
+ _D3std8datetime13monthsToMonthFNaNfiiZi@Base 6
+ _D3std8datetime14SimpleTimeZone11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime14SimpleTimeZone11toISOStringFNaNfS4core4time8DurationZAya@Base 6
+ _D3std8datetime14SimpleTimeZone11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime14SimpleTimeZone6__ctorMyFNaNfS4core4time8DurationAyaZyC3std8datetime14SimpleTimeZone@Base 6
+ _D3std8datetime14SimpleTimeZone6__ctorMyFNaNfiAyaZyC3std8datetime14SimpleTimeZone@Base 6
+ _D3std8datetime14SimpleTimeZone6__initZ@Base 6
+ _D3std8datetime14SimpleTimeZone6__vtblZ@Base 6
+ _D3std8datetime14SimpleTimeZone6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime14SimpleTimeZone7__ClassZ@Base 6
+ _D3std8datetime14SimpleTimeZone7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime14SimpleTimeZone7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime14SimpleTimeZone9utcOffsetMxFNaNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime14lastDayNonLeapyG13i@Base 6
+ _D3std8datetime14validTimeUnitsFNaNbNfAAyaXb@Base 6
+ _D3std8datetime14yearIsLeapYearFNaNbNfiZb@Base 6
+ _D3std8datetime15daysToDayOfWeekFNaNbNfE3std8datetime9DayOfWeekE3std8datetime9DayOfWeekZi@Base 6
+ _D3std8datetime15monthFromStringFNaNfAyaZE3std8datetime5Month@Base 6
+ _D3std8datetime16cmpTimeUnitsCTFEFNaNbNfAyaAyaZi@Base 6
+ _D3std8datetime17stdTimeToUnixTimeFNaNbNflZl@Base 6
+ _D3std8datetime17unixTimeToStdTimeFNaNbNflZl@Base 6
+ _D3std8datetime19fracSecsToISOStringFNaNbNfiZAya@Base 6
+ _D3std8datetime20DosFileTimeToSysTimeFNfkyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime20SysTimeToDosFileTimeFNfS3std8datetime7SysTimeZk@Base 6
+ _D3std8datetime24ComparingBenchmarkResult10targetTimeMxFNaNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime24ComparingBenchmarkResult5pointMxFNaNbNdNfZe@Base 6
+ _D3std8datetime24ComparingBenchmarkResult6__ctorMFNaNbNcNfS4core4time12TickDurationS4core4time12TickDurationZS3std8datetime24ComparingBenchmarkResult@Base 6
+ _D3std8datetime24ComparingBenchmarkResult6__initZ@Base 6
+ _D3std8datetime24ComparingBenchmarkResult8baseTimeMxFNaNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime25__T5validVAyaa4_64617973Z5validFNaNbNfiiiZb@Base 6
+ _D3std8datetime27__T5validVAyaa5_686f757273Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime29__T5validVAyaa6_6d6f6e746873Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime29tzDatabaseNameToWindowsTZNameFNaNbNiNfAyaZAya@Base 6
+ _D3std8datetime29windowsTZNameToTZDatabaseNameFNaNbNiNfAyaZAya@Base 6
+ _D3std8datetime31__T5validVAyaa7_6d696e75746573Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime31__T5validVAyaa7_7365636f6e6473Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime33__T12enforceValidVAyaa4_64617973Z12enforceValidFNaNfiE3std8datetime5MonthiAyamZv@Base 6
+ _D3std8datetime35__T12enforceValidVAyaa5_686f757273Z12enforceValidFNaNfiAyamZv@Base 6
+ _D3std8datetime37__T12enforceValidVAyaa6_6d6f6e746873Z12enforceValidFNaNfiAyamZv@Base 6
+ _D3std8datetime39__T12enforceValidVAyaa7_6d696e75746573Z12enforceValidFNaNfiAyamZv@Base 6
+ _D3std8datetime39__T12enforceValidVAyaa7_7365636f6e6473Z12enforceValidFNaNfiAyamZv@Base 6
+ _D3std8datetime39__T18getUnitsFromHNSecsVAyaa4_64617973Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime3UTC11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime3UTC11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime3UTC4_utcyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC6__ctorMyFNaNfZyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC6__initZ@Base 6
+ _D3std8datetime3UTC6__vtblZ@Base 6
+ _D3std8datetime3UTC6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime3UTC6opCallFNaNbNfZyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC7__ClassZ@Base 6
+ _D3std8datetime3UTC7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime3UTC7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime41__T18getUnitsFromHNSecsVAyaa5_686f757273Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime41__T20splitUnitsFromHNSecsVAyaa4_64617973Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime42__T21removeUnitsFromHNSecsVAyaa4_64617973Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime44__T21removeUnitsFromHNSecsVAyaa5_686f757273Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime45__T18getUnitsFromHNSecsVAyaa7_6d696e75746573Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime48__T21removeUnitsFromHNSecsVAyaa7_6d696e75746573Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime48__T21removeUnitsFromHNSecsVAyaa7_7365636f6e6473Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime4Date10diffMonthsMxFNaNbNfxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date10endOfMonthMxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date10isLeapYearMxFNaNbNdNfZb@Base 6
+ _D3std8datetime4Date11__invariantMxFNaNfZv@Base 6
+ _D3std8datetime4Date11daysInMonthMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date12modJulianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime4Date14__invariant173MxFNaNfZv@Base 6
+ _D3std8datetime4Date14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date14toSimpleStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date17dayOfGregorianCalMFNaNbNdNfiZv@Base 6
+ _D3std8datetime4Date17dayOfGregorianCalMxFNaNbNdNfZi@Base 6
+ _D3std8datetime4Date22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNfxS3std8datetime4DateZS4core4time8Duration@Base 6
+ _D3std8datetime4Date3dayMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date3dayMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date3maxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date3minFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date4isADMxFNaNbNdNfZb@Base 6
+ _D3std8datetime4Date4yearMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date4yearMxFNaNbNdNfZs@Base 6
+ _D3std8datetime4Date5monthMFNaNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime4Date5monthMxFNaNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime4Date5opCmpMxFNaNbNfxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date6__ctorMFNaNbNcNfiZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date6__ctorMFNaNcNfiiiZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date6__initZ@Base 6
+ _D3std8datetime4Date6_validFNaNbNfiiiZb@Base 6
+ _D3std8datetime4Date6yearBCMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date6yearBCMxFNaNdNfZt@Base 6
+ _D3std8datetime4Date7isoWeekMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date8__xopCmpFKxS3std8datetime4DateKxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date8_addDaysMFNaNbNcNjNflZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date8toStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date9dayOfWeekMxFNaNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime4Date9dayOfYearMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date9dayOfYearMxFNaNbNdNfZt@Base 6
+ _D3std8datetime4Date9julianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime5Clock11currAppTickFNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime5Clock11currStdTimeFNdNeZl@Base 6
+ _D3std8datetime5Clock14currSystemTickFNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime5Clock6__ctorMFZC3std8datetime5Clock@Base 6
+ _D3std8datetime5Clock6__initZ@Base 6
+ _D3std8datetime5Clock6__vtblZ@Base 6
+ _D3std8datetime5Clock7__ClassZ@Base 6
+ _D3std8datetime5Clock8currTimeFNfyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime5Month6__initZ@Base 6
+ _D3std8datetime6maxDayFNaNbNfiiZh@Base 6
+ _D3std8datetime7SysTime10diffMonthsMxFNbNfxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime10endOfMonthMxFNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime10isLeapYearMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime10toUnixTimeMxFNaNbNfZl@Base 6
+ _D3std8datetime7SysTime11daysInMonthMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime11dstInEffectMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime11toISOStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime11toLocalTimeMxFNaNbNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime12modJulianDayMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime14toISOExtStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime14toSimpleStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime17dayOfGregorianCalMFNbNdNfiZv@Base 6
+ _D3std8datetime7SysTime17dayOfGregorianCalMxFNbNdNfZi@Base 6
+ _D3std8datetime7SysTime31__T6opCastTS3std8datetime4DateZ6opCastMxFNbNfZS3std8datetime4Date@Base 6
+ _D3std8datetime7SysTime35__T6opCastTS3std8datetime8DateTimeZ6opCastMxFNbNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime7SysTime3dayMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime3dayMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime3maxFNaNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime3minFNaNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime4hourMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime4hourMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime4isADMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime4toTMMxFNbNfZS4core4stdc4time2tm@Base 6
+ _D3std8datetime7SysTime4yearMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime4yearMxFNbNdNfZs@Base 6
+ _D3std8datetime7SysTime5monthMFNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime7SysTime5monthMxFNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime7SysTime5opCmpMxFNaNbNfxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime5toUTCMxFNaNbNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNaNbNcNflyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNbNcNfxS3std8datetime4DateyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNbNcNfxS3std8datetime8DateTimeyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNcNfxS3std8datetime8DateTimexS4core4time7FracSecyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNcNfxS3std8datetime8DateTimexS4core4time8DurationyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__initZ@Base 6
+ _D3std8datetime7SysTime6minuteMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6minuteMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime6secondMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6secondMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime6yearBCMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6yearBCMxFNdNfZt@Base 6
+ _D3std8datetime7SysTime7adjTimeMFNbNdNflZv@Base 6
+ _D3std8datetime7SysTime7adjTimeMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime7fracSecMFNdNfS4core4time7FracSecZv@Base 6
+ _D3std8datetime7SysTime7fracSecMxFNbNdNfZS4core4time7FracSec@Base 6
+ _D3std8datetime7SysTime7isoWeekMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime7stdTimeMFNaNbNdNflZv@Base 6
+ _D3std8datetime7SysTime7stdTimeMxFNaNbNdNfZl@Base 6
+ _D3std8datetime7SysTime8__xopCmpFKxS3std8datetime7SysTimeKxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime8fracSecsMFNdNfS4core4time8DurationZv@Base 6
+ _D3std8datetime7SysTime8fracSecsMxFNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime7SysTime8opAssignMFNaNbNcNjNfKxS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime8opAssignMFNaNbNcNjNfS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime8opEqualsMxFNaNbNfKxS3std8datetime7SysTimeZb@Base 6
+ _D3std8datetime7SysTime8opEqualsMxFNaNbNfxS3std8datetime7SysTimeZb@Base 6
+ _D3std8datetime7SysTime8timezoneMFNaNbNdNfyC3std8datetime8TimeZoneZv@Base 6
+ _D3std8datetime7SysTime8timezoneMxFNaNbNdNfZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime7SysTime8toStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime9__xtoHashFNbNeKxS3std8datetime7SysTimeZm@Base 6
+ _D3std8datetime7SysTime9dayOfWeekMxFNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime7SysTime9dayOfYearMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime9dayOfYearMxFNbNdNfZt@Base 6
+ _D3std8datetime7SysTime9julianDayMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime9toOtherTZMxFNaNbNfyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime9toTimeValMxFNaNbNfZS4core3sys5posix3sys4time7timeval@Base 6
+ _D3std8datetime7SysTime9utcOffsetMxFNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime8DateTime10diffMonthsMxFNaNbNfxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime10endOfMonthMxFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime10isLeapYearMxFNaNbNdNfZb@Base 6
+ _D3std8datetime8DateTime11_addSecondsMFNaNbNcNjNflZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime11daysInMonthMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime12modJulianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime8DateTime14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime14toSimpleStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime17dayOfGregorianCalMFNaNbNdNfiZv@Base 6
+ _D3std8datetime8DateTime17dayOfGregorianCalMxFNaNbNdNfZi@Base 6
+ _D3std8datetime8DateTime3dayMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime3dayMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime3maxFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime3minFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime4dateMFNaNbNdNfxS3std8datetime4DateZv@Base 6
+ _D3std8datetime8DateTime4dateMxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime8DateTime4hourMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime4hourMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime4isADMxFNaNbNdNfZb@Base 6
+ _D3std8datetime8DateTime4yearMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime4yearMxFNaNbNdNfZs@Base 6
+ _D3std8datetime8DateTime5monthMFNaNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime8DateTime5monthMxFNaNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime8DateTime5opCmpMxFNaNbNfxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime6__ctorMFNaNbNcNfxS3std8datetime4DatexS3std8datetime9TimeOfDayZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime6__ctorMFNaNcNfiiiiiiZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime6__initZ@Base 6
+ _D3std8datetime8DateTime6minuteMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6minuteMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime6secondMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6secondMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime6yearBCMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6yearBCMxFNaNdNfZs@Base 6
+ _D3std8datetime8DateTime7isoWeekMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime8__xopCmpFKxS3std8datetime8DateTimeKxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime8toStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime9dayOfWeekMxFNaNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime8DateTime9dayOfYearMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime9dayOfYearMxFNaNbNdNfZt@Base 6
+ _D3std8datetime8DateTime9julianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime8DateTime9timeOfDayMFNaNbNdNfxS3std8datetime9TimeOfDayZv@Base 6
+ _D3std8datetime8DateTime9timeOfDayMxFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime8TimeZone11_getOldNameFNaNbNfAyaZAya@Base 6
+ _D3std8datetime8TimeZone11getTimeZoneFNfAyaZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime8TimeZone11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime8TimeZone19getInstalledTZNamesFNfAyaZAAya@Base 6
+ _D3std8datetime8TimeZone4nameMxFNbNdNfZAya@Base 6
+ _D3std8datetime8TimeZone6__ctorMyFNaNfAyaAyaAyaZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime8TimeZone6__initZ@Base 6
+ _D3std8datetime8TimeZone6__vtblZ@Base 6
+ _D3std8datetime8TimeZone7__ClassZ@Base 6
+ _D3std8datetime8TimeZone7dstNameMxFNbNdNfZAya@Base 6
+ _D3std8datetime8TimeZone7stdNameMxFNbNdNfZAya@Base 6
+ _D3std8datetime9LocalTime10_localTimeyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime11dstInEffectMxFNbNelZb@Base 6
+ _D3std8datetime9LocalTime15_tzsetWasCalledOb@Base 6
+ _D3std8datetime9LocalTime6__ctorMyFNaNfZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime6__initZ@Base 6
+ _D3std8datetime9LocalTime6__vtblZ@Base 6
+ _D3std8datetime9LocalTime6hasDSTMxFNbNdNeZb@Base 6
+ _D3std8datetime9LocalTime6opCallFNaNbNeZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime7__ClassZ@Base 6
+ _D3std8datetime9LocalTime7dstNameMxFNbNdNeZAya@Base 6
+ _D3std8datetime9LocalTime7stdNameMxFNbNdNeZAya@Base 6
+ _D3std8datetime9LocalTime7tzToUTCMxFNbNelZl@Base 6
+ _D3std8datetime9LocalTime7utcToTZMxFNbNelZl@Base 6
+ _D3std8datetime9LocalTime8_lowLockb@Base 6
+ _D3std8datetime9LocalTime9singletonFNeZ13__critsec2791G48g@Base 6
+ _D3std8datetime9LocalTime9singletonFNeZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9StopWatch11setMeasuredMFNfS4core4time12TickDurationZv@Base 6
+ _D3std8datetime9StopWatch4peekMxFNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime9StopWatch4stopMFNfZv@Base 6
+ _D3std8datetime9StopWatch5resetMFNfZv@Base 6
+ _D3std8datetime9StopWatch5startMFNfZv@Base 6
+ _D3std8datetime9StopWatch6__ctorMFNcNfE3std8datetime9AutoStartZS3std8datetime9StopWatch@Base 6
+ _D3std8datetime9StopWatch6__initZ@Base 6
+ _D3std8datetime9StopWatch7runningMxFNaNbNdNfZb@Base 6
+ _D3std8datetime9StopWatch8opEqualsMxFNaNbNfKxS3std8datetime9StopWatchZb@Base 6
+ _D3std8datetime9StopWatch8opEqualsMxFNaNbNfxS3std8datetime9StopWatchZb@Base 6
+ _D3std8datetime9TimeOfDay11__invariantMxFNaNfZv@Base 6
+ _D3std8datetime9TimeOfDay11_addSecondsMFNaNbNcNjNflZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime9TimeOfDay14__invariant201MxFNaNfZv@Base 6
+ _D3std8datetime9TimeOfDay14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime9TimeOfDay22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfxS3std8datetime9TimeOfDayZS4core4time8Duration@Base 6
+ _D3std8datetime9TimeOfDay3maxFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay3minFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay4hourMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay4hourMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay5opCmpMxFNaNbNfxS3std8datetime9TimeOfDayZi@Base 6
+ _D3std8datetime9TimeOfDay6__ctorMFNaNcNfiiiZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay6__initZ@Base 6
+ _D3std8datetime9TimeOfDay6_validFNaNbNfiiiZb@Base 6
+ _D3std8datetime9TimeOfDay6minuteMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay6minuteMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay6secondMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay6secondMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay8__xopCmpFKxS3std8datetime9TimeOfDayKxS3std8datetime9TimeOfDayZi@Base 6
+ _D3std8datetime9TimeOfDay8toStringMxFNaNbNfZAya@Base 6
+ _D3std8demangle12__ModuleInfoZ@Base 6
+ _D3std8demangle8demangleFAyaZAya@Base 6
+ _D3std8encoding12__ModuleInfoZ@Base 6
+ _D3std8encoding13__T6encodeTaZ6encodeFwAaZm@Base 6
+ _D3std8encoding13__T6encodeTuZ6encodeFwAuZm@Base 6
+ _D3std8encoding13__T6encodeTwZ6encodeFwAwZm@Base 6
+ _D3std8encoding14EncodingScheme11validLengthMFAxhZm@Base 6
+ _D3std8encoding14EncodingScheme13firstSequenceMFAxhZm@Base 6
+ _D3std8encoding14EncodingScheme5countMFAxhZm@Base 6
+ _D3std8encoding14EncodingScheme5indexMFAxhmZl@Base 6
+ _D3std8encoding14EncodingScheme6__initZ@Base 6
+ _D3std8encoding14EncodingScheme6__vtblZ@Base 6
+ _D3std8encoding14EncodingScheme6createFAyaZC3std8encoding14EncodingScheme@Base 6
+ _D3std8encoding14EncodingScheme7__ClassZ@Base 6
+ _D3std8encoding14EncodingScheme7isValidMFAxhZb@Base 6
+ _D3std8encoding14EncodingScheme8registerFAyaZv@Base 6
+ _D3std8encoding14EncodingScheme8sanitizeMFAyhZAyh@Base 6
+ _D3std8encoding14EncodingScheme9supportedHAyaAya@Base 6
+ _D3std8encoding14__T7isValidTaZ7isValidFAxaZb@Base 6
+ _D3std8encoding15__T6decodeTAxaZ6decodeFKAxaZw@Base 6
+ _D3std8encoding15__T6decodeTAxuZ6decodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding15__T6decodeTAxwZ6decodeFNbKAxwZw@Base 6
+ _D3std8encoding16__T9canEncodeTaZ9canEncodeFwZb@Base 6
+ _D3std8encoding16__T9canEncodeTuZ9canEncodeFwZb@Base 6
+ _D3std8encoding16__T9canEncodeTwZ9canEncodeFwZb@Base 6
+ _D3std8encoding16isValidCodePointFwZb@Base 6
+ _D3std8encoding17EncodingException6__ctorMFAyaZC3std8encoding17EncodingException@Base 6
+ _D3std8encoding17EncodingException6__initZ@Base 6
+ _D3std8encoding17EncodingException6__vtblZ@Base 6
+ _D3std8encoding17EncodingException7__ClassZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf810safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding18EncodingSchemeUtf813encodedLengthMxFwZm@Base 6
+ _D3std8encoding18EncodingSchemeUtf819_sharedStaticCtor18FZv@Base 6
+ _D3std8encoding18EncodingSchemeUtf819replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding18EncodingSchemeUtf85namesMxFZAAya@Base 6
+ _D3std8encoding18EncodingSchemeUtf86__initZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf86__vtblZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf86decodeMxFKAxhZw@Base 6
+ _D3std8encoding18EncodingSchemeUtf86encodeMxFwAhZm@Base 6
+ _D3std8encoding18EncodingSchemeUtf87__ClassZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf88toStringMxFZAya@Base 6
+ _D3std8encoding18EncodingSchemeUtf89canEncodeMxFwZb@Base 6
+ _D3std8encoding18__T9transcodeTaTwZ9transcodeFAyaJAywZv@Base 6
+ _D3std8encoding19EncodingSchemeASCII10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding19EncodingSchemeASCII13encodedLengthMxFwZm@Base 6
+ _D3std8encoding19EncodingSchemeASCII19_sharedStaticCtor15FZv@Base 6
+ _D3std8encoding19EncodingSchemeASCII19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding19EncodingSchemeASCII5namesMxFZAAya@Base 6
+ _D3std8encoding19EncodingSchemeASCII6__initZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII6__vtblZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII6decodeMxFKAxhZw@Base 6
+ _D3std8encoding19EncodingSchemeASCII6encodeMxFwAhZm@Base 6
+ _D3std8encoding19EncodingSchemeASCII7__ClassZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII8toStringMxFZAya@Base 6
+ _D3std8encoding19EncodingSchemeASCII9canEncodeMxFwZb@Base 6
+ _D3std8encoding19__T11validLengthTaZ11validLengthFAxaZm@Base 6
+ _D3std8encoding20EncodingSchemeLatin110safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding20EncodingSchemeLatin113encodedLengthMxFwZm@Base 6
+ _D3std8encoding20EncodingSchemeLatin119_sharedStaticCtor16FZv@Base 6
+ _D3std8encoding20EncodingSchemeLatin119replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding20EncodingSchemeLatin15namesMxFZAAya@Base 6
+ _D3std8encoding20EncodingSchemeLatin16__initZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin16__vtblZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin16decodeMxFKAxhZw@Base 6
+ _D3std8encoding20EncodingSchemeLatin16encodeMxFwAhZm@Base 6
+ _D3std8encoding20EncodingSchemeLatin17__ClassZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin18toStringMxFZAya@Base 6
+ _D3std8encoding20EncodingSchemeLatin19canEncodeMxFwZb@Base 6
+ _D3std8encoding20__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding20__T10safeDecodeTAxuZ10safeDecodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding20__T10safeDecodeTAxwZ10safeDecodeFKAxwZw@Base 6
+ _D3std8encoding21__T13encodedLengthTaZ13encodedLengthFwZm@Base 6
+ _D3std8encoding21__T13encodedLengthTuZ13encodedLengthFwZm@Base 6
+ _D3std8encoding21__T13encodedLengthTwZ13encodedLengthFwZm@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ13encodedLengthFwZm@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ15isValidCodeUnitFaZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ19replacementSequenceFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ5tailsFaZi@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin1513decodeReverseFKAxaZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin1520__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin154skipFKAxaZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwDFaZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwKAaZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwZAa@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9canEncodeFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9tailTableyG128h@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ13encodedLengthFwZm@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ15isValidCodeUnitFuZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ19replacementSequenceFNdZAyu@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin1313decodeReverseFKAxuZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin134skipFKAxuZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwDFuZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwKAuZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwZAu@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9canEncodeFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ13encodedLengthFwZm@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ15isValidCodeUnitFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ19replacementSequenceFNdZAyw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin1313decodeReverseFKAxwZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin134skipFKAxwZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwDFwZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwKAwZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwZAw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9canEncodeFwZb@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native13encodedLengthMxFwZm@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native19_sharedStaticCtor19FZv@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native5namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6__initZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6encodeMxFwAhZm@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native7__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native8toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native9canEncodeMxFwZb@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native13encodedLengthMxFwZm@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native19_sharedStaticCtor21FZv@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native5namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6__initZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6encodeMxFwAhZm@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native7__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native8toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native9canEncodeMxFwZb@Base 6
+ _D3std8encoding25EncodingSchemeWindows125210safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeWindows125213encodedLengthMxFwZm@Base 6
+ _D3std8encoding25EncodingSchemeWindows125219_sharedStaticCtor17FZv@Base 6
+ _D3std8encoding25EncodingSchemeWindows125219replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeWindows12525namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526__initZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526encodeMxFwAhZm@Base 6
+ _D3std8encoding25EncodingSchemeWindows12527__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12528toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeWindows12529canEncodeMxFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ13encodedLengthFwZm@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ15isValidCodeUnitFaZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ19replacementSequenceFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ5tailsFaZi@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1513decodeReverseFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1515__T6decodeTAxaZ6decodeFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1520__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin154skipFKAxaZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwDFaZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwKAaZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwZAa@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9canEncodeFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9tailTableyG128h@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ13encodedLengthFwZm@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ15isValidCodeUnitFuZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ19replacementSequenceFNdZAyu@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1313decodeReverseFKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1315__T6decodeTAxuZ6decodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1320__T10safeDecodeTAxuZ10safeDecodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin134skipFKAxuZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwDFuZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwKAuZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwZAu@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9canEncodeFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ13encodedLengthFwZm@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ15isValidCodeUnitFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ19replacementSequenceFNdZAyw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1313decodeReverseFKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1315__T6decodeTAxwZ6decodeFNaNbNiNfKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1320__T10safeDecodeTAxwZ10safeDecodeFKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin134skipFKAxwZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwDFwZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwKAwZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwZAw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9canEncodeFwZb@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__ctorMFAyaZC3std8encoding29UnrecognizedEncodingException@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__initZ@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__vtblZ@Base 6
+ _D3std8encoding29UnrecognizedEncodingException7__ClassZ@Base 6
+ _D3std8encoding36__T6encodeTE3std8encoding9AsciiCharZ6encodeFwAE3std8encoding9AsciiCharZm@Base 6
+ _D3std8encoding38__T6decodeTAxE3std8encoding9AsciiCharZ6decodeFNbKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding38__T6encodeTE3std8encoding10Latin1CharZ6encodeFwAE3std8encoding10Latin1CharZm@Base 6
+ _D3std8encoding39__T9canEncodeTE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding40__T6decodeTAxE3std8encoding10Latin1CharZ6decodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding41__T9canEncodeTE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding43__T10safeDecodeTAxE3std8encoding9AsciiCharZ10safeDecodeFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding43__T6encodeTE3std8encoding15Windows1252CharZ6encodeFwAE3std8encoding15Windows1252CharZm@Base 6
+ _D3std8encoding44__T13encodedLengthTE3std8encoding9AsciiCharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding45__T10safeDecodeTAxE3std8encoding10Latin1CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding45__T6decodeTAxE3std8encoding15Windows1252CharZ6decodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding46__T13encodedLengthTE3std8encoding10Latin1CharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding46__T9canEncodeTE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ15isValidCodeUnitFE3std8encoding9AsciiCharZb@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ19replacementSequenceFNdZAyE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin1413decodeReverseFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin144skipFKAxE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwDFE3std8encoding9AsciiCharZvZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwKAE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwZAE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ15isValidCodeUnitFE3std8encoding9AsciiCharZb@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ19replacementSequenceFNdZAyE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1413decodeReverseFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1438__T6decodeTAxE3std8encoding9AsciiCharZ6decodeFNaNbNiNfKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1443__T10safeDecodeTAxE3std8encoding9AsciiCharZ10safeDecodeFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin144skipFKAxE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwDFE3std8encoding9AsciiCharZvZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwKAE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwZAE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ15isValidCodeUnitFE3std8encoding10Latin1CharZb@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ19replacementSequenceFNdZAyE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin1313decodeReverseFKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin134skipFKAxE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwDFE3std8encoding10Latin1CharZvZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwKAE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwZAE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding50__T10safeDecodeTAxE3std8encoding15Windows1252CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ15isValidCodeUnitFE3std8encoding10Latin1CharZb@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ19replacementSequenceFNdZAyE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1313decodeReverseFKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1340__T6decodeTAxE3std8encoding10Latin1CharZ6decodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1345__T10safeDecodeTAxE3std8encoding10Latin1CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin134skipFKAxE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwDFE3std8encoding10Latin1CharZvZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwKAE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwZAE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding51__T13encodedLengthTE3std8encoding15Windows1252CharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ15isValidCodeUnitFE3std8encoding15Windows1252CharZb@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ19replacementSequenceFNdZAyE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ7charMapyAu@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin1413decodeReverseFKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin144skipFKAxE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwDFE3std8encoding15Windows1252CharZvZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwKAE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwZAE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ13encodedLengthFwZm@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ15isValidCodeUnitFE3std8encoding15Windows1252CharZb@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ19replacementSequenceFNdZAyE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ7charMapyAu@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1413decodeReverseFKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1445__T6decodeTAxE3std8encoding15Windows1252CharZ6decodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin144skipFKAxE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1450__T10safeDecodeTAxE3std8encoding15Windows1252CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwDFE3std8encoding15Windows1252CharZvZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwKAE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwZAE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8internal11processinit12__ModuleInfoZ@Base 6
+ _D3std8internal11scopebuffer12__ModuleInfoZ@Base 6
+ _D3std8internal12unicode_comp12__ModuleInfoZ@Base 6
+ _D3std8internal12unicode_comp16compositionTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std8internal12unicode_comp16compositionTableFNaNbNdNiNfZyAS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std8internal12unicode_norm12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_decomp12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_decomp16decompCanonTableFNaNbNdNiNfZ1tyAw@Base 6
+ _D3std8internal14unicode_decomp16decompCanonTableFNaNbNdNiNfZyAw@Base 6
+ _D3std8internal14unicode_decomp17decompCompatTableFNaNbNdNiNfZ1tyAw@Base 6
+ _D3std8internal14unicode_decomp17decompCompatTableFNaNbNdNiNfZyAw@Base 6
+ _D3std8internal14unicode_tables10isSpaceGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables10isWhiteGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables11isFormatGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_tables12isControlGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables12toLowerTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toLowerTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables12toTitleTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toTitleTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables12toUpperTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toUpperTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables13FullCaseEntry5valueMxFNaNbNdNiNjNeZAxw@Base 6
+ _D3std8internal14unicode_tables13FullCaseEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables13fullCaseTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables13FullCaseEntry@Base 6
+ _D3std8internal14unicode_tables13fullCaseTableFNaNbNdNiNfZyAS3std8internal14unicode_tables13FullCaseEntry@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry4sizeMxFNaNbNdNiNfZh@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry7isLowerMxFNaNbNdNiNfZi@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry7isUpperMxFNaNbNdNiNfZi@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty11__xopEqualsFKxS3std8internal14unicode_tables15UnicodePropertyKxS3std8internal14unicode_tables15UnicodePropertyZb@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty9__xtoHashFNbNeKxS3std8internal14unicode_tables15UnicodePropertyZm@Base 6
+ _D3std8internal14unicode_tables15simpleCaseTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables15SimpleCaseEntry@Base 6
+ _D3std8internal14unicode_tables15simpleCaseTableFNaNbNdNiNfZyAS3std8internal14unicode_tables15SimpleCaseEntry@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZm@Base 6
+ _D3std8internal14unicode_tables6blocks10DevanagariyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10GlagoliticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10KharoshthiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10Old_ItalicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10Old_TurkicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10PhoenicianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10SaurashtrayAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Basic_LatinyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Box_DrawingyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11CJK_StrokesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Hangul_JamoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11New_Tai_LueyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Old_PersianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Yi_RadicalsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Domino_TilesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Meetei_MayekyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Number_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Sora_SompengyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Syloti_NagriyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Yi_SyllablesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Khmer_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Mahjong_TilesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Phaistos_DiscyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Playing_CardsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Aegean_NumbersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Block_ElementsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Greek_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14IPA_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Low_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Vertical_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Ancient_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15High_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Kana_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Kangxi_RadicalsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Musical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Bamum_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Braille_PatternsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Control_PicturesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Currency_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Geometric_ShapesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Greek_and_CopticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Hangul_SyllablesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Imperial_AramaicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_CyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_DyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Meroitic_CursiveyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Private_Use_AreayAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Vedic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Arabic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Arabic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Bopomofo_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17CJK_CompatibilityyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Cypriot_SyllabaryyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Ethiopic_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Old_South_ArabianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Alchemical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Latin_1_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Letterlike_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Linear_B_IdeogramsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Linear_B_SyllabaryyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Myanmar_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Devanagari_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Ethiopic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Ethiopic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19General_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Georgian_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Phonetic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Small_Form_VariantsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Variation_SelectorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Combining_Half_MarksyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Egyptian_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Meroitic_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Rumi_Numeral_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Sundanese_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Ancient_Greek_NumbersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Counting_Rod_NumeralsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Inscriptional_PahlaviyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Miscellaneous_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Modifier_Tone_LettersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Supplemental_Arrows_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Supplemental_Arrows_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Tai_Xuan_Jing_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22CJK_Unified_IdeographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Enclosed_AlphanumericsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Hangul_Jamo_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Hangul_Jamo_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Inscriptional_ParthianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Mathematical_OperatorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23CJK_Compatibility_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23CJK_Radicals_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Meetei_Mayek_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Miscellaneous_TechnicalyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Yijing_Hexagram_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks24Spacing_Modifier_LettersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks24Supplemental_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Byzantine_Musical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Common_Indic_Number_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Hangul_Compatibility_JamoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Latin_Extended_AdditionalyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Transport_And_Map_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Arabic_Presentation_Forms_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Arabic_Presentation_Forms_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks27CJK_Symbols_and_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Combining_Diacritical_MarksyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27High_Private_Use_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Superscripts_and_SubscriptsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks28CJK_Compatibility_IdeographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks28Katakana_Phonetic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Alphabetic_Presentation_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Halfwidth_and_Fullwidth_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Optical_Character_RecognitionyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Ancient_Greek_Musical_NotationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Phonetic_Extensions_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Variation_Selectors_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks31Enclosed_CJK_Letters_and_MonthsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks31Enclosed_Ideographic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Enclosed_Alphanumeric_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Miscellaneous_Symbols_and_ArrowsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Supplementary_Private_Use_Area_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Supplementary_Private_Use_Area_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks33Cuneiform_Numbers_and_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks33Mathematical_Alphanumeric_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_CyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_DyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34Ideographic_Description_CharactersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks35Supplemental_Mathematical_OperatorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks36Miscellaneous_Mathematical_Symbols_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks36Miscellaneous_Mathematical_Symbols_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks37Miscellaneous_Symbols_And_PictographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks37Unified_Canadian_Aboriginal_SyllabicsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks38Arabic_Mathematical_Alphabetic_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks38Combining_Diacritical_Marks_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks39CJK_Compatibility_Ideographs_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks39Combining_Diacritical_Marks_for_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3LaoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3NKoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3VaiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6blocks46Unified_Canadian_Aboriginal_Syllabics_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4ChamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4LisuyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4MiaoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4TagsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4ThaiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6blocks5BamumyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5BatakyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5BuhidyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5KhmeryAh@Base 6
+ _D3std8internal14unicode_tables6blocks5LimbuyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5OghamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5OriyayAh@Base 6
+ _D3std8internal14unicode_tables6blocks5RunicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5TakriyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5TamilyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ArabicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ArrowsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6BrahmiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6CarianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ChakmayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6CopticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6GothicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6HebrewyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6KaithiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6KanbunyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LepchayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LycianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LydianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6RejangyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6SyriacyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6Tai_LeyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6TeluguyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ThaanayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6__initZ@Base 6
+ _D3std8internal14unicode_tables6blocks7AvestanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7BengaliyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7DeseretyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7HanunooyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7KannadayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7MandaicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7MyanmaryAh@Base 6
+ _D3std8internal14unicode_tables6blocks7OsmanyayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7SharadayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7ShavianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7SinhalayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7TagalogyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7TibetanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8ArmenianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BalineseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BopomofoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BugineseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8CherokeeyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8CyrillicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8DingbatsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8EthiopicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GeorgianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GujaratiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GurmukhiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8HiraganayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8JavaneseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8KatakanayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Kayah_LiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Ol_ChikiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Phags_payAh@Base 6
+ _D3std8internal14unicode_tables6blocks8SpecialsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8TagbanwayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Tai_ThamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Tai_VietyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8TifinaghyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8UgariticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9CuneiformyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9EmoticonsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9MalayalamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9MongolianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9SamaritanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9SundaneseyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1LyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1TyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1VyAh@Base 6
+ _D3std8internal14unicode_tables6hangul2LVyAh@Base 6
+ _D3std8internal14unicode_tables6hangul3LVTyAh@Base 6
+ _D3std8internal14unicode_tables6hangul3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6hangul4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6hangul6__initZ@Base 6
+ _D3std8internal14unicode_tables7isHangLFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7isHangTFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7isHangVFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7scripts10DevanagariyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10GlagoliticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10KharoshthiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10Old_ItalicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10Old_TurkicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10PhoenicianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10SaurashtrayAh@Base 6
+ _D3std8internal14unicode_tables7scripts11New_Tai_LueyAh@Base 6
+ _D3std8internal14unicode_tables7scripts11Old_PersianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Meetei_MayekyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Sora_SompengyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Syloti_NagriyAh@Base 6
+ _D3std8internal14unicode_tables7scripts16Imperial_AramaicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts16Meroitic_CursiveyAh@Base 6
+ _D3std8internal14unicode_tables7scripts17Old_South_ArabianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts19Canadian_AboriginalyAh@Base 6
+ _D3std8internal14unicode_tables7scripts20Egyptian_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables7scripts20Meroitic_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables7scripts21Inscriptional_PahlaviyAh@Base 6
+ _D3std8internal14unicode_tables7scripts22Inscriptional_ParthianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts2YiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3HanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3LaoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3NkoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3VaiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables7scripts4ChamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4LisuyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4MiaoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4ThaiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables7scripts5BamumyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5BatakyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5BuhidyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5GreekyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5KhmeryAh@Base 6
+ _D3std8internal14unicode_tables7scripts5LatinyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5LimbuyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5OghamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5OriyayAh@Base 6
+ _D3std8internal14unicode_tables7scripts5RunicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5TakriyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5TamilyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ArabicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6BrahmiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CarianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ChakmayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CommonyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CopticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6GothicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6HangulyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6HebrewyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6KaithiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LepchayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LycianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LydianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6RejangyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6SyriacyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6Tai_LeyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6TeluguyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ThaanayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6__initZ@Base 6
+ _D3std8internal14unicode_tables7scripts7AvestanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7BengaliyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7BrailleyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7CypriotyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7DeseretyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7HanunooyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7KannadayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7MandaicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7MyanmaryAh@Base 6
+ _D3std8internal14unicode_tables7scripts7OsmanyayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7SharadayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7ShavianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7SinhalayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7TagalogyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7TibetanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8ArmenianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BalineseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BopomofoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BugineseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8CherokeeyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8CyrillicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8EthiopicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GeorgianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GujaratiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GurmukhiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8HiraganayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8JavaneseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8KatakanayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Kayah_LiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Linear_ByAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Ol_ChikiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Phags_PayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8TagbanwayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Tai_ThamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Tai_VietyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8TifinaghyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8UgariticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9CuneiformyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9InheritedyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9MalayalamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9MongolianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9SamaritanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9SundaneseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10AlphabeticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10DeprecatedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10Other_MathyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11ID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11IdeographicyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11Soft_DottedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11White_SpaceyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12Bidi_ControlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12Join_ControlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12XID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps13Grapheme_BaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps13Grapheme_LinkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Case_IgnorableyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Other_ID_StartyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Pattern_SyntaxyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Quotation_MarkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15ASCII_Hex_DigityAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Grapheme_ExtendyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Other_LowercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Other_UppercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps16Other_AlphabeticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps17Other_ID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps17Unified_IdeographyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps18Variation_SelectoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps19IDS_Binary_OperatoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps19Pattern_White_SpaceyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps20IDS_Trinary_OperatoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps20Terminal_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps21Other_Grapheme_ExtendyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps23Logical_Order_ExceptionyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps23Noncharacter_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps28Default_Ignorable_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CcyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CfyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CnyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LmyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LtyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LuyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2McyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2MeyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2MnyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NdyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PcyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PdyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PeyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PfyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PiyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ScyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SmyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZpyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps34Other_Default_Ignorable_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables8uniProps4DashyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps4MathyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables8uniProps5CasedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps5STermyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps6HyphenyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps6__initZ@Base 6
+ _D3std8internal14unicode_tables8uniProps7RadicalyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps8ExtenderyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps8ID_StartyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9DiacriticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9Hex_DigityAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9LowercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9UppercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9XID_StartyAh@Base 6
+ _D3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D3std8internal16unicode_grapheme12__ModuleInfoZ@Base 6
+ _D3std8internal4math10biguintx8612__ModuleInfoZ@Base 6
+ _D3std8internal4math11biguintcore10CACHELIMITym@Base 6
+ _D3std8internal4math11biguintcore10inplaceSubFNaNbAkAxkAxkZb@Base 6
+ _D3std8internal4math11biguintcore11blockDivModFNaNbAkAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore11includeSignFNaNbNfAxkmbZAk@Base 6
+ _D3std8internal4math11biguintcore11mulInternalFNaNbAkAxkAxkZv@Base 6
+ _D3std8internal4math11biguintcore12FASTDIVLIMITym@Base 6
+ _D3std8internal4math11biguintcore12__ModuleInfoZ@Base 6
+ _D3std8internal4math11biguintcore12biguintToHexFNaNbNfAaxAkaZAa@Base 6
+ _D3std8internal4math11biguintcore12mulKaratsubaFNaNbAkAxkAxkAkZv@Base 6
+ _D3std8internal4math11biguintcore12squareSimpleFNaNbAkAxkZv@Base 6
+ _D3std8internal4math11biguintcore13__T6intpowTkZ6intpowFNaNbNiNfkmZk@Base 6
+ _D3std8internal4math11biguintcore14divModInternalFNaNbAkAkxAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore14itoaZeroPaddedFNaNbNfAakiZv@Base 6
+ _D3std8internal4math11biguintcore14squareInternalFNaNbAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore14twosComplementFNaNbNfAxkAkZv@Base 6
+ _D3std8internal4math11biguintcore15addAssignSimpleFNaNbAkAxkZk@Base 6
+ _D3std8internal4math11biguintcore15adjustRemainderFNaNbAkAkAxklAkbZv@Base 6
+ _D3std8internal4math11biguintcore15recursiveDivModFNaNbAkAkAxkAkbZv@Base 6
+ _D3std8internal4math11biguintcore15squareKaratsubaFNaNbAkxAkAkZv@Base 6
+ _D3std8internal4math11biguintcore15subAssignSimpleFNaNbAkAxkZk@Base 6
+ _D3std8internal4math11biguintcore15toHexZeroPaddedFNaNbNfAakZ9hexDigitsyAa@Base 6
+ _D3std8internal4math11biguintcore15toHexZeroPaddedFNaNbNfAakZv@Base 6
+ _D3std8internal4math11biguintcore16biguintToDecimalFNaNbAaAkZm@Base 6
+ _D3std8internal4math11biguintcore16schoolbookDivModFNaNbAkAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore17firstNonZeroDigitFNaNbNiNfxAkZi@Base 6
+ _D3std8internal4math11biguintcore18_sharedStaticCtor1FZv@Base 6
+ _D3std8internal4math11biguintcore18biguintFromDecimalFNaAkAxaZi@Base 6
+ _D3std8internal4math11biguintcore18removeLeadingZerosFNaNbNfANgkZANgk@Base 6
+ _D3std8internal4math11biguintcore20addOrSubAssignSimpleFNaNbAkAxkbZk@Base 6
+ _D3std8internal4math11biguintcore21highestDifferentDigitFNaNbNiNfxAkxAkZm@Base 6
+ _D3std8internal4math11biguintcore24highestPowerBelowUintMaxFNaNbNfkZ6maxpwryG22h@Base 6
+ _D3std8internal4math11biguintcore24highestPowerBelowUintMaxFNaNbNfkZi@Base 6
+ _D3std8internal4math11biguintcore25highestPowerBelowUlongMaxFNaNbNfkZ6maxpwryG39h@Base 6
+ _D3std8internal4math11biguintcore25highestPowerBelowUlongMaxFNaNbNfkZi@Base 6
+ _D3std8internal4math11biguintcore25karatsubaRequiredBuffSizeFNaNbNfmZm@Base 6
+ _D3std8internal4math11biguintcore3ONEyAk@Base 6
+ _D3std8internal4math11biguintcore3TENyAk@Base 6
+ _D3std8internal4math11biguintcore3TWOyAk@Base 6
+ _D3std8internal4math11biguintcore3addFNaNbxAkxAkZAk@Base 6
+ _D3std8internal4math11biguintcore3subFNaNbxAkxAkPbZAk@Base 6
+ _D3std8internal4math11biguintcore4ZEROyAk@Base 6
+ _D3std8internal4math11biguintcore4lessFNaNbAxkAxkZb@Base 6
+ _D3std8internal4math11biguintcore6addIntFNaNbxAkmZAk@Base 6
+ _D3std8internal4math11biguintcore6subIntFNaNbxAkmZAk@Base 6
+ _D3std8internal4math11biguintcore7BigUint10uintLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4math11biguintcore7BigUint11__invariantMxFNaZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint11__xopEqualsFKxS3std8internal4math11biguintcore7BigUintKxS3std8internal4math11biguintcore7BigUintZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint11toHexStringMxFNaNbNfiaiaZAa@Base 6
+ _D3std8internal4math11biguintcore7BigUint11ulongLengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__T5opCmpTvZ5opCmpMxFNaNbNiNfxS3std8internal4math11biguintcore7BigUintZi@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__T5opShlTmZ5opShlMxFNaNbNfmZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__invariant2MxFNaZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint13fromHexStringMFNaNbNfAxaZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint14__T6divIntTykZ6divIntFNaNbNfS3std8internal4math11biguintcore7BigUintykZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint14__T6modIntTykZ6modIntFNaNbNfS3std8internal4math11biguintcore7BigUintykZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opAssignTmZ8opAssignMFNaNbNfmZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opEqualsTvZ8opEqualsMxFNaNbNiNfKxS3std8internal4math11biguintcore7BigUintZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opEqualsTvZ8opEqualsMxFNaNbNiNfmZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__funcliteral31FNaNbNiNeAkZAyk@Base 6
+ _D3std8internal4math11biguintcore7BigUint15toDecimalStringMxFNaNbiZAa@Base 6
+ _D3std8internal4math11biguintcore7BigUint17fromDecimalStringMFNaNeAxaZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint3divFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3modFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3mulFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3powFNaNbS3std8internal4math11biguintcore7BigUintmZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint6__ctorMFNaNbNcNiNfAykZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint6__initZ@Base 6
+ _D3std8internal4math11biguintcore7BigUint6isZeroMxFNaNbNiNfZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint6toHashMxFNbNeZm@Base 6
+ _D3std8internal4math11biguintcore7BigUint8__xopCmpFKxS3std8internal4math11biguintcore7BigUintKxS3std8internal4math11biguintcore7BigUintZi@Base 6
+ _D3std8internal4math11biguintcore7BigUint8addOrSubFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintbPbZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint8numBytesMxFNaNbNiNfZm@Base 6
+ _D3std8internal4math11biguintcore7BigUint8peekUintMxFNaNbNiNfiZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint9peekUlongMxFNaNbNiNfiZm@Base 6
+ _D3std8internal4math11biguintcore9addSimpleFNaNbAkxAkxAkZk@Base 6
+ _D3std8internal4math11biguintcore9mulSimpleFNaNbAkAxkAxkZv@Base 6
+ _D3std8internal4math11biguintcore9subSimpleFNaNbAkAxkAxkZk@Base 6
+ _D3std8internal4math12biguintnoasm12__ModuleInfoZ@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteMulFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteShlFNaNbNiNfAkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteShrFNaNbNiNfAkAxkkZv@Base 6
+ _D3std8internal4math12biguintnoasm15multibyteSquareFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm18multibyteDivAssignFNaNbNiNfAkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai43Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai45Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai43Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai45Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteAddDiagonalSquaresFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteMultiplyAccumulateFNaNbNiNfAkAxkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteTriangleAccumulateFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai43Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai45Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math13errorfunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13errorfunction1PyG10e@Base 6
+ _D3std8internal4math13errorfunction1QyG11e@Base 6
+ _D3std8internal4math13errorfunction1RyG5e@Base 6
+ _D3std8internal4math13errorfunction1SyG6e@Base 6
+ _D3std8internal4math13errorfunction1TyG7e@Base 6
+ _D3std8internal4math13errorfunction1UyG7e@Base 6
+ _D3std8internal4math13errorfunction20__T12rationalPolyTeZ12rationalPolyFNaNbNiNfeAxeAxeZe@Base 6
+ _D3std8internal4math13errorfunction22normalDistributionImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction3erfFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction4erfcFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5EXP_2ye@Base 6
+ _D3std8internal4math13errorfunction5erfceFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5expx2FNaNbNiNfeiZe@Base 6
+ _D3std8internal4math13gammafunction10EULERGAMMAye@Base 6
+ _D3std8internal4math13gammafunction11logmdigammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19LargeStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19SmallStirlingCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction14betaIncompleteFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction15gammaIncompleteFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction16GammaSmallCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZ4coefyG13Ae@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction17betaIncompleteInvFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction17logGammaNumeratoryG7e@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion1FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion2FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18logmdigammaInverseFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction19GammaSmallNegCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction19betaDistPowerSeriesFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction19logGammaDenominatoryG8e@Base 6
+ _D3std8internal4math13gammafunction20GammaNumeratorCoeffsyG8e@Base 6
+ _D3std8internal4math13gammafunction20gammaIncompleteComplFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction22GammaDenominatorCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction22logGammaStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction23gammaIncompleteComplInvFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction4Bn_nyG7e@Base 6
+ _D3std8internal4math13gammafunction5gammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction7digammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction8logGammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4test10dummyrange12__ModuleInfoZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange13opIndexAssignMFNaNbNiNfkmZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMNgFNaNbNcNiNfmZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfmmZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMxFNaNbNiNfmZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfmmZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZm@Base 6
+ _D3std8internal6digest9sha_SSSE312__ModuleInfoZ@Base 6
+ _D3std8internal7cstring12__ModuleInfoZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3ResZS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFNbNiAxaZS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3ResZS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFNbNiAyaZS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3ResZS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFNbNiANgaZS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res@Base 6
+ _D3std8internal7windows8advapi3212__ModuleInfoZ@Base 6
+ _D3std8syserror12__ModuleInfoZ@Base 6
+ _D3std8syserror8SysError3msgFkZAya@Base 6
+ _D3std8syserror8SysError6__initZ@Base 6
+ _D3std8syserror8SysError6__vtblZ@Base 6
+ _D3std8syserror8SysError7__ClassZ@Base 6
+ _D3std8typecons10Structural11__InterfaceZ@Base 6
+ _D3std8typecons10__T5tupleZ135__T5tupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZS3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ136__T5tupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5tupleFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ137__T5tupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ16__T5tupleTkTkTkZ5tupleFNaNbNiNfkkkZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ22__T5tupleTAyaTAyaTAyaZ5tupleFNaNbNiNfAyaAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPbZ5tupleFNaNbNiNfC8TypeInfoPbZS3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPiZ5tupleFNaNbNiNfC8TypeInfoPiZS3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPmZ5tupleFNaNbNiNfC8TypeInfoPmZS3std8typecons24__T5TupleTC8TypeInfoTPmZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ33__T5tupleTC14TypeInfo_ArrayTPAyhZ5tupleFNaNbNiNfC14TypeInfo_ArrayPAyhZS3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ34__T5tupleTC14TypeInfo_ArrayTPG32hZ5tupleFNaNbNiNfC14TypeInfo_ArrayPG32hZS3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG32hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ34__T5tupleTC14TypeInfo_ClassTPG32hZ5tupleFNaNbNiNfC14TypeInfo_ClassPG32hZS3std8typecons34__T5TupleTC14TypeInfo_ClassTPG32hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ35__T5tupleTC15TypeInfo_StructTPG32hZ5tupleFNaNbNiNfC15TypeInfo_StructPG32hZS3std8typecons35__T5TupleTC15TypeInfo_StructTPG32hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ35__T5tupleTC18TypeInfo_InvariantTPhZ5tupleFNaNbNiNfC18TypeInfo_InvariantPhZS3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ38__T5tupleTC18TypeInfo_InvariantTPG32hZ5tupleFNaNbNiNfC18TypeInfo_InvariantPG32hZS3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG32hZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ48__T5tupleTC14TypeInfo_ClassTPC6object9ThrowableZ5tupleFNaNbNiNfC14TypeInfo_ClassPC6object9ThrowableZS3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ50__T5tupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5tupleFNaNbNiNfC15TypeInfo_SharedPOC6object9ThrowableZS3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ53__T5tupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std11concurrency3TidZS3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple@Base 6
+ _D3std8typecons12__ModuleInfoZ@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZS3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple11__xopEqualsFKxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleKxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZb@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple174__T8opEqualsTxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZb@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__ctorMFNaNbNcNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__initZ@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons14__T5TupleTbTiZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple11__xopEqualsFKxS3std8typecons14__T5TupleTbTiZ5TupleKxS3std8typecons14__T5TupleTbTiZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple48__T5opCmpTxS3std8typecons14__T5TupleTbTiZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons14__T5TupleTbTiZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple51__T8opEqualsTxS3std8typecons14__T5TupleTbTiZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons14__T5TupleTbTiZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6__ctorMFNaNbNcNiNfbiZS3std8typecons14__T5TupleTbTiZ5Tuple@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6__initZ@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple8__xopCmpFKxS3std8typecons14__T5TupleTbTiZ5TupleKxS3std8typecons14__T5TupleTbTiZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTmTmZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons14__T5TupleTmTmZ5Tuple11__xopEqualsFKxS3std8typecons14__T5TupleTmTmZ5TupleKxS3std8typecons14__T5TupleTmTmZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTmTmZ5Tuple48__T5opCmpTxS3std8typecons14__T5TupleTmTmZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons14__T5TupleTmTmZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTmTmZ5Tuple51__T8opEqualsTxS3std8typecons14__T5TupleTmTmZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons14__T5TupleTmTmZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTmTmZ5Tuple6__ctorMFNaNbNcNiNfmmZS3std8typecons14__T5TupleTmTmZ5Tuple@Base 6
+ _D3std8typecons14__T5TupleTmTmZ5Tuple6__initZ@Base 6
+ _D3std8typecons14__T5TupleTmTmZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons14__T5TupleTmTmZ5Tuple8__xopCmpFKxS3std8typecons14__T5TupleTmTmZ5TupleKxS3std8typecons14__T5TupleTmTmZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple11__xopEqualsFKxS3std8typecons16__T5TupleTiTAyaZ5TupleKxS3std8typecons16__T5TupleTiTAyaZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple50__T5opCmpTxS3std8typecons16__T5TupleTiTAyaZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons16__T5TupleTiTAyaZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple53__T8opEqualsTxS3std8typecons16__T5TupleTiTAyaZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons16__T5TupleTiTAyaZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6__ctorMFNaNbNcNiNfiAyaZS3std8typecons16__T5TupleTiTAyaZ5Tuple@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6__initZ@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple8__xopCmpFKxS3std8typecons16__T5TupleTiTAyaZ5TupleKxS3std8typecons16__T5TupleTiTAyaZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple11__xopEqualsFKxS3std8typecons16__T5TupleTkTkTkZ5TupleKxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple50__T5opCmpTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons16__T5TupleTkTkTkZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple53__T8opEqualsTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6__ctorMFNaNbNcNiNfkkkZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple8__xopCmpFKxS3std8typecons16__T5TupleTkTkTkZ5TupleKxS3std8typecons16__T5TupleTkTkTkZ5TupleZi@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple11__xopEqualsFKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZb@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple52__T5opCmpTxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZi@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple55__T8opEqualsTxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZb@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__ctorMFNaNbNcNiNfeeeeZS3std8typecons18__T5TupleTeTeTeTeZ5Tuple@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__initZ@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple8__xopCmpFKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZi@Base 6
+ _D3std8typecons19NotImplementedError6__ctorMFAyaZC3std8typecons19NotImplementedError@Base 6
+ _D3std8typecons19NotImplementedError6__initZ@Base 6
+ _D3std8typecons19NotImplementedError6__vtblZ@Base 6
+ _D3std8typecons19NotImplementedError7__ClassZ@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple11__xopEqualsFKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZb@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple56__T5opCmpTxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZi@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple59__T8opEqualsTxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZb@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__ctorMFNaNbNcNiNfAyaAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__initZ@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple8__xopCmpFKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZi@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPbZS3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPiZS3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPmZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPmZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPmZS3std8typecons24__T5TupleTC8TypeInfoTPmZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPmZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPmZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPvZS3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons2No6__initZ@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ArrayPAyhZS3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__initZ@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG32hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG32hZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ArrayPG32hZS3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG32hZ5Tuple@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG32hZ5Tuple6__initZ@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG32hZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG32hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG32hZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ClassPG32hZS3std8typecons34__T5TupleTC14TypeInfo_ClassTPG32hZ5Tuple@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG32hZ5Tuple6__initZ@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG32hZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG32hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG32hZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPG32hZS3std8typecons35__T5TupleTC15TypeInfo_StructTPG32hZ5Tuple@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG32hZ5Tuple6__initZ@Base 6
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG32hZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__ctorMFNaNbNcNiNfC18TypeInfo_InvariantPhZS3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__initZ@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG32hZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG32hZ5Tuple6__ctorMFNaNbNcNiNfC18TypeInfo_InvariantPG32hZS3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG32hZ5Tuple@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG32hZ5Tuple6__initZ@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG32hZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons3Yes6__initZ@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple11__xopEqualsFKxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleKxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleZb@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons14__T5TupleTmTmZ5Tuple@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple6__ctorMFNaNbNcNiNfmmZS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple6__initZ@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple74__T5opCmpTxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleZi@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple77__T8opEqualsTxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleZb@Base 6
+ _D3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple8__xopCmpFKxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleKxS3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5TupleZi@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable11__xopEqualsFKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZb@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin13getMNgFNaNbNcNdNiNeZyC3std8datetime8TimeZone@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin16__ctorMFNaNbNcNiNeyC3std8datetime8TimeZoneZS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin18opAssignMFNaNbNiNeS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZv@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin18opAssignMFNaNbNiNeyC3std8datetime8TimeZoneZv@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable9__xtoHashFNbNeKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZm@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ClassPC6object9ThrowableZS3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_SharedPOC6object9ThrowableZS3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std11concurrency3TidZS3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__initZ@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple11__xopEqualsFKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZb@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons16__T5TupleTiTAyaZ5Tuple@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__ctorMFNaNbNcNiNfiAyaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__initZ@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple88__T5opCmpTxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZi@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple8__xopCmpFKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZi@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple91__T8opEqualsTxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZb@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple11__xopEqualsFKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZb@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons14__T5TupleTbTiZ5Tuple@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__ctorMFNaNbNcNiNfbiZS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__initZ@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6toHashMxFNbNeZm@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple8__xopCmpFKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZi@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple95__T5opCmpTxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZi@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple98__T8opEqualsTxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple119__T8opEqualsTxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ8opEqualsMxFxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple11__xopEqualsFKxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleKxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__ctorMFNaNbNcNiNfS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6toHashMxFNaNbNeZm@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZm@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZm@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl3FTP4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl3FTP4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl3FTP4ImplZS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZm@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZm@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl4HTTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl4HTTP4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZm@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl4SMTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl4SMTP4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple11__xopEqualsFKxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple120__T8opAssignTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opAssignMFNaNbNiNfKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple120__T8opEqualsTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opEqualsMFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple121__T8opEqualsTxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opEqualsMxFxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple27__T8toStringTDFNaNbNfAxaZvZ8toStringMFMDFNaNbNfAxaZvZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__ctorMFNaNbNcNiNfS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6toHashMxFNaNbNeZm@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore42__T10initializeTAyaTE3std4file8SpanModeTbZ10initializeMFKAyaKE3std4file8SpanModeKbZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZm@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4moveMFNbNiKS3std4file15DirIteratorImplZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZm@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std4file15DirIteratorImpl@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted37__T6__ctorTAyaTE3std4file8SpanModeTbZ6__ctorMFNcKAyaKE3std4file8SpanModeKbZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__ctorMFNcS3std4file15DirIteratorImplZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted8opAssignMFS3std4file15DirIteratorImplZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted8opAssignMFS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCountedZv@Base 6
+ _D3std8typelist12__ModuleInfoZ@Base 6
+ _D3std9algorithm10comparison12__ModuleInfoZ@Base 6
+ _D3std9algorithm10comparison12__T3maxTiTiZ3maxFNaNbNiNfiiZi@Base 6
+ _D3std9algorithm10comparison12__T3maxTkTkZ3maxFNaNbNiNfkkZk@Base 6
+ _D3std9algorithm10comparison12__T3maxTmTiZ3maxFNaNbNiNfmiZm@Base 6
+ _D3std9algorithm10comparison12__T3maxTmTmZ3maxFNaNbNiNfmmZm@Base 6
+ _D3std9algorithm10comparison12__T3minTkTkZ3minFNaNbNiNfkkZk@Base 6
+ _D3std9algorithm10comparison12__T3minTlTmZ3minFNaNbNiNflmZl@Base 6
+ _D3std9algorithm10comparison12__T3minTmTiZ3minFNaNbNiNfmiZi@Base 6
+ _D3std9algorithm10comparison12__T3minTmTmZ3minFNaNbNiNfmmZm@Base 6
+ _D3std9algorithm10comparison13__T3minTmTymZ3minFNaNbNiNfmymZm@Base 6
+ _D3std9algorithm10comparison13__T3minTyiTmZ3minFNaNbNiNfyimZyi@Base 6
+ _D3std9algorithm10comparison13__T3minTymTmZ3minFNaNbNiNfymmZym@Base 6
+ _D3std9algorithm10comparison14__T3maxTmTmTmZ3maxFNaNbNiNfmmmZm@Base 6
+ _D3std9algorithm10comparison14__T3minTymTymZ3minFNaNbNiNfymymZym@Base 6
+ _D3std9algorithm10comparison20__T5amongVai45Vai43Z13__T5amongTxaZ5amongFNaNbNiNfxaZk@Base 6
+ _D3std9algorithm10comparison20__T5amongVai95Vai44Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison21__T5amongVai101Vai69Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison21__T5amongVai105Vai73Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison32__T5amongVai117Vai108Vai85Vai76Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison33__T3cmpVAyaa5_61203c2062TAxhTAxhZ3cmpFNaNbNiNfAxhAxhZi@Base 6
+ _D3std9algorithm10comparison43__T5amongVai108Vai76Vai102Vai70Vai105Vai73Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison489__T3cmpVAyaa5_61203c2062TS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultTS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZ3cmpFNaNfS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZi@Base 6
+ _D3std9algorithm10comparison6EditOp6__initZ@Base 6
+ _D3std9algorithm12__ModuleInfoZ@Base 6
+ _D3std9algorithm6setops12__ModuleInfoZ@Base 6
+ _D3std9algorithm7sorting103__T12HeapSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ13__T8heapSortZ8heapSortFNaNbNiNfAAyaZv@Base 6
+ _D3std9algorithm7sorting103__T12HeapSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ9__T4siftZ4siftFNaNbNiNfAAyamymZv@Base 6
+ _D3std9algorithm7sorting104__T13quickSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ13quickSortImplFNaNbNiNfAAyamZv@Base 6
+ _D3std9algorithm7sorting114__T23optimisticInsertionSortS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ23optimisticInsertionSortFNaNbNiNfAAyaZv@Base 6
+ _D3std9algorithm7sorting12__ModuleInfoZ@Base 6
+ _D3std9algorithm7sorting135__T4sortVAyaa17_612e74696d6554203c20622e74696d6554VE3std9algorithm8mutation12SwapStrategyi0TAS3std8datetime13PosixTimeZone10LeapSecondZ4sortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std9algorithm7sorting139__T4sortVAyaa17_612e74696d6554203c20622e74696d6554VE3std9algorithm8mutation12SwapStrategyi0TAS3std8datetime13PosixTimeZone14TempTransitionZ4sortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std9algorithm7sorting162__T8getPivotS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ8getPivotFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZm@Base 6
+ _D3std9algorithm7sorting162__T8isSortedS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ8isSortedFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std9algorithm7sorting166__T8getPivotS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ8getPivotFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZm@Base 6
+ _D3std9algorithm7sorting166__T8isSortedS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ8isSortedFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9algorithm7sorting167__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ13__T8heapSortZ8heapSortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm7sorting167__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ9__T4siftZ4siftFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondmymZv@Base 6
+ _D3std9algorithm7sorting168__T13quickSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ13quickSortImplFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondmZv@Base 6
+ _D3std9algorithm7sorting171__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ13__T8heapSortZ8heapSortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm7sorting171__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ9__T4siftZ4siftFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionmymZv@Base 6
+ _D3std9algorithm7sorting172__T13quickSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ13quickSortImplFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionmZv@Base 6
+ _D3std9algorithm7sorting178__T23optimisticInsertionSortS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ23optimisticInsertionSortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm7sorting182__T23optimisticInsertionSortS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ23optimisticInsertionSortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm7sorting201__T11TimSortImplS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ5Slice6__initZ@Base 6
+ _D3std9algorithm7sorting72__T4sortVAyaa5_61203c2062VE3std9algorithm8mutation12SwapStrategyi0TAAyaZ4sortFNaNbNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std9algorithm7sorting98__T8getPivotS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ8getPivotFNaNbNiNfAAyaZm@Base 6
+ _D3std9algorithm7sorting98__T8isSortedS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ8isSortedFNaNbNiNfAAyaZb@Base 6
+ _D3std9algorithm8internal12__ModuleInfoZ@Base 6
+ _D3std9algorithm8mutation103__T4moveTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ4moveFNaNbNiKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std9algorithm8mutation105__T6swapAtTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ6swapAtFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsmmZv@Base 6
+ _D3std9algorithm8mutation106__T7reverseTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ7reverseFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZv@Base 6
+ _D3std9algorithm8mutation12__ModuleInfoZ@Base 6
+ _D3std9algorithm8mutation12__T4moveTAkZ4moveFNaNbNiKAkZAk@Base 6
+ _D3std9algorithm8mutation133__T4copyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTAS3std3uni17CodepointIntervalZ4copyFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZAS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation133__T4copyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTAS3std3uni17CodepointIntervalZ4copyFS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZ11genericImplFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZAS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation13__T4moveTAyaZ4moveFNaNbNiNfKAyaKAyaZv@Base 6
+ _D3std9algorithm8mutation13__T4swapTAyaZ4swapFNaNbNiNeKAyaKAyaZv@Base 6
+ _D3std9algorithm8mutation144__T4swapTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation145__T4swapTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation145__T4swapTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation148__T4swapTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation14__T4moveTAAyaZ4moveFNaNbNiKAAyaZAAya@Base 6
+ _D3std9algorithm8mutation14__T4swapTAAyaZ4swapFNaNbNiNeKAAyaKAAyaZv@Base 6
+ _D3std9algorithm8mutation15__T4copyTAiTAkZ4copyFAiAkZ11genericImplFNaNbNiNfAiAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAiTAkZ4copyFNaNbNiNfAiAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAkTAkZ4copyFAkAkZ11genericImplFNaNbNiNfAkAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAkTAkZ4copyFNaNbNiNfAkAkZAk@Base 6
+ _D3std9algorithm8mutation16__T6swapAtTAAyaZ6swapAtFNaNbNiNfAAyammZv@Base 6
+ _D3std9algorithm8mutation174__T4moveTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZ4moveFNaNbNiKS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm8mutation183__T4moveTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZ4moveFNaNbNiKS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm8mutation26__T4swapTS3std5stdio4FileZ4swapFNaNbNiNeKS3std5stdio4FileKS3std5stdio4FileZv@Base 6
+ _D3std9algorithm8mutation29__T4moveTC4core6thread5FiberZ4moveFNaNbNiNfKC4core6thread5FiberKC4core6thread5FiberZv@Base 6
+ _D3std9algorithm8mutation33__T4moveTS3std3net4curl3FTP4ImplZ4moveFKS3std3net4curl3FTP4ImplKS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std9algorithm8mutation34__T4moveTS3std3net4curl4HTTP4ImplZ4moveFKS3std3net4curl4HTTP4ImplKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std9algorithm8mutation34__T4moveTS3std3net4curl4SMTP4ImplZ4moveFKS3std3net4curl4SMTP4ImplKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std9algorithm8mutation37__T4moveTS3std4file15DirIteratorImplZ4moveFKS3std4file15DirIteratorImplKS3std4file15DirIteratorImplZv@Base 6
+ _D3std9algorithm8mutation38__T4moveTS3std3uni17CodepointIntervalZ4moveFNaNbNiNfKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation40__T4swapTS3std5stdio17LockingTextReaderZ4swapFNaNbNiNeKS3std5stdio17LockingTextReaderKS3std5stdio17LockingTextReaderZv@Base 6
+ _D3std9algorithm8mutation46__T4moveTAS3std5regex8internal2ir10NamedGroupZ4moveFNaNbNiKAS3std5regex8internal2ir10NamedGroupZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std9algorithm8mutation51__T4swapTS3std8datetime13PosixTimeZone10LeapSecondZ4swapFNaNbNiNeKS3std8datetime13PosixTimeZone10LeapSecondKS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm8mutation52__T4moveTAS3std8datetime13PosixTimeZone10LeapSecondZ4moveFNaNbNiKAS3std8datetime13PosixTimeZone10LeapSecondZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std9algorithm8mutation52__T4swapTAS3std8datetime13PosixTimeZone10LeapSecondZ4swapFNaNbNiNeKAS3std8datetime13PosixTimeZone10LeapSecondKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm8mutation54__T6swapAtTAS3std8datetime13PosixTimeZone10LeapSecondZ6swapAtFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondmmZv@Base 6
+ _D3std9algorithm8mutation54__T7moveAllTAC4core6thread5FiberTAC4core6thread5FiberZ7moveAllFNaNfAC4core6thread5FiberAC4core6thread5FiberZAC4core6thread5Fiber@Base 6
+ _D3std9algorithm8mutation55__T4swapTS3std8datetime13PosixTimeZone14TempTransitionZ4swapFNaNbNiNeKS3std8datetime13PosixTimeZone14TempTransitionKS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm8mutation56__T4moveTAS3std8datetime13PosixTimeZone14TempTransitionZ4moveFNaNbNiKAS3std8datetime13PosixTimeZone14TempTransitionZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std9algorithm8mutation56__T4swapTAS3std8datetime13PosixTimeZone14TempTransitionZ4swapFNaNbNiNeKAS3std8datetime13PosixTimeZone14TempTransitionKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm8mutation58__T6swapAtTAS3std8datetime13PosixTimeZone14TempTransitionZ6swapAtFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionmmZv@Base 6
+ _D3std9algorithm8mutation59__T6removeVE3std9algorithm8mutation12SwapStrategyi0TAAyaTlZ6removeFNaNbNiNfAAyalZAAya@Base 6
+ _D3std9algorithm8mutation674__T4copyTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultTAkZ4copyFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZAk@Base 6
+ _D3std9algorithm8mutation674__T4copyTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultTAkZ4copyFS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZ11genericImplFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZAk@Base 6
+ _D3std9algorithm8mutation75__T6removeVE3std9algorithm8mutation12SwapStrategyi2TAC4core6thread5FiberTmZ6removeFNaNfAC4core6thread5FibermZAC4core6thread5Fiber@Base 6
+ _D3std9algorithm8mutation77__T4copyTAS3std5regex8internal2ir8BytecodeTAS3std5regex8internal2ir8BytecodeZ4copyFAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZ11genericImplFNaNbNiNfAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZAS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std9algorithm8mutation77__T4copyTAS3std5regex8internal2ir8BytecodeTAS3std5regex8internal2ir8BytecodeZ4copyFNaNbNiNfAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZAS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std9algorithm9iteration105__T6filterS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbZ88__T6filterTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ6filterFNaNfS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult4saveMFNaNbNdNiZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult5frontMFNaNbNdNiNfZm@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult6__ctorMFNaNbNcNiS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult7opSliceMFNaNbNiNfZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResult8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult4saveMFNaNdNfZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5emptyMFNaNdNfZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5frontMFNaNdNfZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__ctorMFNaNbNcNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZm@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult4saveMFNaNdNfZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5emptyMFNaNdNfZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5frontMFNaNdNfZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__ctorMFNaNbNcNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZm@Base 6
+ _D3std9algorithm9iteration11__T3sumTAkZ3sumFNaNbNiNfAkZk@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult11__fieldDtorMFZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult11__xopEqualsFKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZb@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult15__fieldPostblitMFNbZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult5emptyMFNdZb@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__ctorMFNcS3std4file11DirIteratorZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult7opSliceMFNbZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult8opAssignMFNcNjS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult8popFrontMFZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult9__xtoHashFNbNeKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZm@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult12__T7popBackZ7popBackMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult5frontMFNaNbNdNiNfZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__ctorMFNaNbNcNiNfAyS3std8internal14unicode_tables9CompEntryZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult7opIndexMFNaNbNiNfmZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult7opSliceMFNaNbNiNfmmZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult9__T4backZ4backMFNaNbNdNiNfZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZm@Base 6
+ _D3std9algorithm9iteration12__ModuleInfoZ@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult12__T7popBackZ7popBackMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__ctorMFNaNbNcNiNfAyS3std8internal14unicode_tables15UnicodePropertyZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6lengthMFNaNbNdNiNfZm@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult7opIndexMFNaNbNiNfmZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult7opSliceMFNaNbNiNfmmZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult9__T4backZ4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZm@Base 6
+ _D3std9algorithm9iteration13__T3sumTAkTkZ3sumFNaNbNiNfAkkZk@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult11__xopEqualsFKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZb@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult4saveMFNaNdNfZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult5frontMFNaNdNfZw@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__ctorMFNaNcNfS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult7opSliceMFNaNbNiNfZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult9__xtoHashFNbNeKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZm@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult4saveMFNaNbNdNiZS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult5frontMFNaNbNdNiZS3std8bitmanip14__T7BitsSetTmZ7BitsSet@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult6__ctorMFNaNbNcNiNfS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResult8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration23__T3mapVAyaa4_615b305dZ41__T3mapTS3std3uni21DecompressedIntervalsZ3mapFNaNbNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration23__T3mapVAyaa4_615b315dZ41__T3mapTS3std3uni21DecompressedIntervalsZ3mapFNaNbNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration25__T3mapVAyaa5_612e726873Z51__T3mapTAyS3std8internal14unicode_tables9CompEntryZ3mapFNaNbNiNfAyS3std8internal14unicode_tables9CompEntryZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFNaNbNiS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result4saveMFNaNbNdNiZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result5frontMFNaNbNdNiNfZm@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result6__ctorMFNaNbNcNiS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration27__T3mapVAyaa6_612e6e616d65Z58__T3mapTAyS3std8internal14unicode_tables15UnicodePropertyZ3mapFNaNbNiNfAyS3std8internal14unicode_tables15UnicodePropertyZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z16__T6reduceTkTAkZ6reduceFNaNbNiNfkAkZk@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z24__T13reducePreImplTAkTkZ13reducePreImplFNaNbNiNfAkKkZk@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z25__T10reduceImplVbi0TAkTkZ10reduceImplFNaNbNiNfAkKkZk@Base 6
+ _D3std9algorithm9iteration29__T3mapS183std5ascii7toLowerZ12__T3mapTAxaZ3mapFNaNbNiNfAxaZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result11__xopEqualsFKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultZb@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result11lastIndexOfFNaNfAyaaZm@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result4backMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result4saveMFNaNbNdNiNfZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result5frontMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__ctorMFNaNbNcNiNfAyaaZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result7popBackMFNaNfZv@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result9__xtoHashFNbNeKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultZm@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFNaNbNiNfAyaaZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult5frontMFNaNdNfZw@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__ctorMFNaNbNcNiNfAxaZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZm@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result11__xopEqualsFKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZb@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result15separatorLengthMFNaNbNdNiNfZm@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result16ensureBackLengthMFNaNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result17ensureFrontLengthMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result4backMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result4saveMFNaNbNdNiNfZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result5frontMFNaNbNdNiNfZAya@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__ctorMFNaNbNcNiNfAyaAyaZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result7popBackMFNaNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result9__xtoHashFNbNeKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZm@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFNaNbNiNfAyaAyaZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult5frontMFNdNfZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__ctorMFNaNbNcNiNfS3std5range13__T6RepeatTiZ6RepeatZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opIndexMFNfmZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfmS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarTokenZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfmmZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult5frontMFNdNfZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__ctorMFNaNbNcNiNfS3std5range13__T6RepeatTiZ6RepeatZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opIndexMFNfmZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfmS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarTokenZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfmmZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9searching12__ModuleInfoZ@Base 6
+ _D3std9algorithm9searching12__T7canFindZ20__T7canFindTAyhTAyaZ7canFindFNaNfAyhAyaZb@Base 6
+ _D3std9algorithm9searching12__T7canFindZ21__T7canFindTAyAaTAyaZ7canFindFNaNbNiNfAyAaAyaZb@Base 6
+ _D3std9algorithm9searching146__T4findVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ4findFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching159__T16simpleMindedFindVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ16simpleMindedFindFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching166__T10countUntilVAyaa6_61203d3d2062TAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10countUntilFNaNbNiNfAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZl@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxaTAywZ8skipOverFKAxaAywZ19__T9__lambda3TwTywZ9__lambda3FNaNbNiNfwywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxaTAywZ8skipOverFNaNfKAxaAywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxuTAywZ8skipOverFKAxuAywZ19__T9__lambda3TwTywZ9__lambda3FNaNbNiNfwywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxuTAywZ8skipOverFNaNfKAxuAywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxwTAywZ8skipOverFNaNbNiNfKAxwAywZb@Base 6
+ _D3std9algorithm9searching26__T14balancedParensTAxaTaZ14balancedParensFNaNfAxaaamZb@Base 6
+ _D3std9algorithm9searching29__T5countVAyaa4_74727565TAyaZ5countFNaNiNfAyaZm@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAhTAhZ4findFNaNbNiNfAhAhZAh@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAyaTaZ4findFAyaaZ13trustedMemchrFNaNbNiNeKAyaKaZAya@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAyaTaZ4findFNaNfAyaaZAya@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ16__T5forceTAhTAaZ5forceFNaNbNiNeAaZAh@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFNaNbNiNfAyaAaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAhTAxaZ5forceFNaNbNiNeAxaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAxaTAhZ5forceFNaNbNiNeAhZAxa@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFNaNbNiNfAxaAyaZAxa@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAhTAxaZ5forceFNaNbNiNeAxaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFNaNbNiNfAyaAxaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFAyaAyaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFAyaAyaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFNaNbNiNfAyaAyaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyhTAyaZ4findFNaNfAyhAyaZAyh@Base 6
+ _D3std9algorithm9searching37__T4findVAyaa6_61203d3d2062TAyAaTAyaZ4findFNaNbNiNfAyAaAyaZAyAa@Base 6
+ _D3std9algorithm9searching37__T5countVAyaa6_61203d3d2062TAyaTAyaZ5countFNaNbNiNfAyaAyaZm@Base 6
+ _D3std9algorithm9searching40__T10countUntilVAyaa6_61203d3d2062TAaTaZ10countUntilFNaNiNfAaaZl@Base 6
+ _D3std9algorithm9searching40__T10countUntilVAyaa6_61203d3d2062TAkTkZ10countUntilFNaNbNiNfAkkZl@Base 6
+ _D3std9algorithm9searching40__T8findSkipVAyaa6_61203d3d2062TAyaTAyaZ8findSkipFNaNbNiNfKAyaAyaZb@Base 6
+ _D3std9algorithm9searching41__T10startsWithVAyaa6_61203d3d2062TAhTAhZ10startsWithFNaNbNiNfAhAhZb@Base 6
+ _D3std9algorithm9searching41__T10startsWithVAyaa6_61203d3d2062TAxaTaZ10startsWithFNaNfAxaaZb@Base 6
+ _D3std9algorithm9searching41__T9findSplitVAyaa6_61203d3d2062TAyaTAyaZ9findSplitFNaNbNiNfAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAxaTAyaZ10startsWithFNaNbNiNfAxaAyaZb@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAyaTAyaZ10startsWithFNaNbNiNfAyaAyaZb@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAyhTAyaZ10startsWithFNaNfAyhAyaZb@Base 6
+ _D3std9algorithm9searching44__T10countUntilVAyaa6_61203d3d2062TAAyaTAyaZ10countUntilFNaNbNiNfAAyaAyaZl@Base 6
+ _D3std9algorithm9searching44__T10countUntilVAyaa6_61203d3d2062TAyAaTAyaZ10countUntilFNaNbNiNfAyAaAyaZl@Base 6
+ _D3std9algorithm9searching47__T10startsWithVAyaa6_61203d3d2062TAxaTAyaTAyaZ10startsWithFNaNfAxaAyaAyaZk@Base 6
+ _D3std9algorithm9searching50__T3anyS39_D3std4path14isDirSeparatorFNaNbNiNfwZbZ12__T3anyTAxaZ3anyFNaNfAxaZb@Base 6
+ _D3std9algorithm9searching51__T10startsWithVAyaa6_61203d3d2062TAxaTAyaTAyaTAyaZ10startsWithFNaNfAxaAyaAyaAyaZk@Base 6
+ _D3std9algorithm9searching55__T4findS39_D3std4path14isDirSeparatorFNaNbNiNfwZbTAxaZ4findFNaNfAxaZAxa@Base 6
+ _D3std9algorithm9searching76__T10countUntilVAyaa11_615b305d203e2030783830TAS3std3uni17CodepointIntervalZ10countUntilFNaNbNiNfAS3std3uni17CodepointIntervalZl@Base 6
+ _D3std9algorithm9searching89__T4findVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTaZ4findFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultaZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching92__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTlZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionlZl@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10LeapSecondTylZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10LeapSecondylZl@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTylZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionylZl@Base 6
+ _D3std9container10binaryheap12__ModuleInfoZ@Base 6
+ _D3std9container12__ModuleInfoZ@Base 6
+ _D3std9container4util12__ModuleInfoZ@Base 6
+ _D3std9container5array12__ModuleInfoZ@Base 6
+ _D3std9container5dlist12__ModuleInfoZ@Base 6
+ _D3std9container5dlist6DRange4backMFNaNbNdNfZPS3std9container5dlist8BaseNode@Base 6
+ _D3std9container5dlist6DRange4saveMFNaNbNdNfZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange5emptyMxFNaNbNdNfZb@Base 6
+ _D3std9container5dlist6DRange5frontMFNaNbNdNfZPS3std9container5dlist8BaseNode@Base 6
+ _D3std9container5dlist6DRange6__ctorMFNaNbNcNfPS3std9container5dlist8BaseNodePS3std9container5dlist8BaseNodeZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange6__ctorMFNaNbNcNfPS3std9container5dlist8BaseNodeZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange6__initZ@Base 6
+ _D3std9container5dlist6DRange7popBackMFNaNbNfZv@Base 6
+ _D3std9container5dlist6DRange8popFrontMFNaNbNfZv@Base 6
+ _D3std9container5dlist8BaseNode6__initZ@Base 6
+ _D3std9container5dlist8BaseNode7connectFNaNbNfPS3std9container5dlist8BaseNodePS3std9container5dlist8BaseNodeZv@Base 6
+ _D3std9container5slist12__ModuleInfoZ@Base 6
+ _D3std9container6rbtree12__ModuleInfoZ@Base 6
+ _D3std9exception104__T11doesPointToTPyS3std8datetime13PosixTimeZone6TTInfoTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPyS3std8datetime13PosixTimeZone6TTInfoKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception104__T11doesPointToTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception105__T11doesPointToTAS3std8datetime13PosixTimeZone10LeapSecondTAS3std8datetime13PosixTimeZone10LeapSecondTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone10LeapSecondKxAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std9exception111__T11doesPointToTPxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception111__T11doesPointToTS3std8datetime13PosixTimeZone14TempTransitionTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxS3std8datetime13PosixTimeZone14TempTransitionKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTAS3std8datetime13PosixTimeZone14TempTransitionTAS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone14TempTransitionKxAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTPxS3std8datetime13PosixTimeZone14TransitionTypeTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPS3std8datetime13PosixTimeZone14TransitionTypeKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception115__T11doesPointToTmTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxmKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi674Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi676Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi681Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi749Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi891Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi949Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi994Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T11doesPointToTAxkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxAkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1010Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1088Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1124Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1155Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi146Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi308Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi315Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi341Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi372Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi397Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi482Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T18isUnionAliasedImplTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception121__T12errnoEnforceTbVAyaa43_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f70726f636573732e64Vmi2907Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T11doesPointToTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception129__T11doesPointToTPxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception12__ModuleInfoZ@Base 6
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi385Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi455Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception144__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1588Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception14ErrnoException5errnoMFNdZk@Base 6
+ _D3std9exception14ErrnoException6__ctorMFNeAyaAyamZC3std9exception14ErrnoException@Base 6
+ _D3std9exception14ErrnoException6__initZ@Base 6
+ _D3std9exception14ErrnoException6__vtblZ@Base 6
+ _D3std9exception14ErrnoException7__ClassZ@Base 6
+ _D3std9exception14RangePrimitive6__initZ@Base 6
+ _D3std9exception14__T7enforceTbZ7enforceFNaNfbLC6object9ThrowableZb@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTbVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vmi557Z12errnoEnforceFNfbLAyaZb@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTiVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vmi557Z12errnoEnforceFNfiLAyaZi@Base 6
+ (optional)_D3std9exception203__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vmi557Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception207__T11doesPointToTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiKAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTkZ12assumeUniqueFNaNbNiKAkZAyk@Base 6
+ _D3std9exception25__T11doesPointToTAkTAkTvZ11doesPointToFNaNbNiNeKxAkKxAkZb@Base 6
+ _D3std9exception25__T7bailOutHTC9ExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTiZ7enforceFNaNfiLAxaAyamZi@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTkZ7enforceFNaNfkLAxaAyamZk@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTmZ7enforceFNaNfmLAxaAyamZm@Base 6
+ _D3std9exception289__T11doesPointToTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception28__T7enforceHTC9ExceptionTPvZ7enforceFNaNfPvLAxaAyamZPv@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception297__T11doesPointToTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception29__T11doesPointToTAAyaTAAyaTvZ11doesPointToFNaNbNiNeKxAAyaKxAAyaZb@Base 6
+ _D3std9exception37__T16collectExceptionHTC9ExceptionTmZ16collectExceptionFNaNbNfLmZC9Exception@Base 6
+ _D3std9exception39__T7bailOutHTC3std4json13JSONExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception40__T11doesPointToTAyaTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio4FileZb@Base 6
+ _D3std9exception40__T7bailOutHTC4core4time13TimeExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception41__T18isUnionAliasedImplTS3std5stdio4FileZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception41__T7enforceHTC3std4json13JSONExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception41__T9enforceExHTC3std4json13JSONExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyamZb@Base 6
+ _D3std9exception42__T7enforceHTC4core4time13TimeExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception43__T7bailOutHTC3std3net4curl13CurlExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std3net4curl4CurlZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std4file8DirEntryZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception44__T7enforceTPS4core3sys5posix5netdb7hostentZ7enforceFNaNfPS4core3sys5posix5netdb7hostentLC6object9ThrowableZPS4core3sys5posix5netdb7hostent@Base 6
+ _D3std9exception45__T11doesPointToTbTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception45__T7enforceHTC3std3net4curl13CurlExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyamZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTmZ9enforceExFNaNfmLAyaAyamZm@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTtTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxtKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T7enforceHTC3std3net4curl13CurlExceptionTPvZ7enforceFNaNfPvLAxaAyamZPv@Base 6
+ _D3std9exception47__T11doesPointToTAyaTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception47__T11doesPointToTPxvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception48__T18isUnionAliasedImplTS3std3net4curl3FTP4ImplZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception49__T11doesPointToTbTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxbKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToThTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxhKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTkTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxkKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTlTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxlKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTmTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxmKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4HTTP4ImplZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4SMTP4ImplZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAhZmTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZmKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAvZmTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZmKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T7bailOutHTC3std3net4curl20CurlTimeoutExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception51__T11doesPointToTAyaTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZmTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZmKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZmTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZmKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZmTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZmKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZmTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZmKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFxAaZvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTG3lTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxG3lKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFmmmmZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFmmmmZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTwTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxwKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception52__T18isUnionAliasedImplTS3std4file15DirIteratorImplZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception52__T7enforceHTC3std3net4curl20CurlTimeoutExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception53__T11doesPointToTDFmmmmZiTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFmmmmZiKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTDFmmmmZiTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFmmmmZiKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTHAyaxAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxHAyaAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTS3std5stdio4FileTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio4FileZb@Base 6
+ _D3std9exception53__T7bailOutHTC3std11concurrency19TidMissingExceptionZ7bailOutFAyamxAaZv@Base 6
+ _D3std9exception54__T11doesPointToTAyaTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception54__T7enforceHTC9ExceptionTPOS4core4stdc5stdio8_IO_FILEZ7enforceFNaNfPOS4core4stdc5stdio8_IO_FILELAxaAyamZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception55__T18isUnionAliasedImplTS3std5stdio17LockingTextReaderZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception55__T7enforceHTC3std11concurrency19TidMissingExceptionTbZ7enforceFbLAxaAyamZb@Base 6
+ _D3std9exception56__T18isUnionAliasedImplTS3std3net4curl4HTTP10StatusLineZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception57__T18isUnionAliasedImplTS4core3sys5posix3sys4stat6stat_tZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception60__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio4FileZb@Base 6
+ _D3std9exception63__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception63__T7enforceHTC3std4json13JSONExceptionTPNgS3std4json9JSONValueZ7enforceFNaNfPNgS3std4json9JSONValueLAxaAyamZPNgS3std4json9JSONValue@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTE3std4file8SpanModeTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxE3std4file8SpanModeKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std3net4curl3FTP4ImplTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl3FTP4ImplKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std4file8DirEntryTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std4file8DirEntryKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std5stdio4FileTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception67__T11doesPointToTlTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxlKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4HTTP4ImplTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP4ImplKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4SMTP4ImplTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4SMTP4ImplKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception70__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception70__T18isUnionAliasedImplTS3std8datetime13PosixTimeZone14TempTransitionZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception71__T11doesPointToTE3std3net4curl4HTTP6MethodTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxE3std3net4curl4HTTP6MethodKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception71__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception74__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception75__T11doesPointToTS3std4file15DirIteratorImplTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNeKxS3std4file15DirIteratorImplKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception76__T11doesPointToTS3std3net4curl4HTTP10StatusLineTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP10StatusLineKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTDFS3std3net4curl4HTTP10StatusLineZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFS3std3net4curl4HTTP10StatusLineZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTS4core3sys5posix3sys4stat6stat_tTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS4core3sys5posix3sys4stat6stat_tKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception81__T11doesPointToTS3std5stdio17LockingTextReaderTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio17LockingTextReaderKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception81__T18isUnionAliasedImplTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception93__T11doesPointToTAS3std5regex8internal2ir10NamedGroupTAS3std5regex8internal2ir10NamedGroupTvZ11doesPointToFNaNbNiNeKxAS3std5regex8internal2ir10NamedGroupKxAS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std9exception93__T7enforceHTC9ExceptionTPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZ7enforceFNaNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeLAxaAyamZPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std9exception94__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception96__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception96__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception99__T18isUnionAliasedImplTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9outbuffer12__ModuleInfoZ@Base 6
+ _D3std9outbuffer9OutBuffer11__invariantMxFZv@Base 6
+ _D3std9outbuffer9OutBuffer12__invariant1MxFZv@Base 6
+ _D3std9outbuffer9OutBuffer5fill0MFNaNbNfmZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeAxwZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNedZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeeZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNefZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNekZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNemZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNetZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeuZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNexAaZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNexAuZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfAxhZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfC3std9outbuffer9OutBufferZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfaZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfgZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfhZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfiZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNflZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfsZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfwZv@Base 6
+ _D3std9outbuffer9OutBuffer6__ctorMFNaNbNfZC3std9outbuffer9OutBuffer@Base 6
+ _D3std9outbuffer9OutBuffer6__initZ@Base 6
+ _D3std9outbuffer9OutBuffer6__vtblZ@Base 6
+ _D3std9outbuffer9OutBuffer6align2MFNaNbNfZv@Base 6
+ _D3std9outbuffer9OutBuffer6align4MFNaNbNfZv@Base 6
+ _D3std9outbuffer9OutBuffer6printfMFNeAyaYv@Base 6
+ _D3std9outbuffer9OutBuffer6spreadMFNaNbNfmmZv@Base 6
+ _D3std9outbuffer9OutBuffer7__ClassZ@Base 6
+ _D3std9outbuffer9OutBuffer7reserveMFNaNbNemZv@Base 6
+ _D3std9outbuffer9OutBuffer7toBytesMFNaNbNfZAh@Base 6
+ _D3std9outbuffer9OutBuffer7vprintfMFNbNeAyaG1S3gcc8builtins13__va_list_tagZv@Base 6
+ _D3std9outbuffer9OutBuffer8toStringMxFNaNbNfZAya@Base 6
+ _D3std9outbuffer9OutBuffer9alignSizeMFNaNbNfmZv@Base 6
+ _D3std9stdiobase12__ModuleInfoZ@Base 6
+ _D3std9stdiobase18_sharedStaticCtor1FZv@Base 6
+ _D3std9typetuple12__ModuleInfoZ@Base 6
+ _D401TypeInfo_S3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D403TypeInfo_S3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D403TypeInfo_S3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D404TypeInfo_S3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D407TypeInfo_S3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D40TypeInfo_C3std11concurrency11IsGenerator6__initZ@Base 6
+ _D40TypeInfo_E3std3uni20UnicodeDecomposition6__initZ@Base 6
+ _D40TypeInfo_E3std6socket17SocketOptionLevel6__initZ@Base 6
+ _D40TypeInfo_E3std6traits17FunctionAttribute6__initZ@Base 6
+ _D40TypeInfo_E3std7numeric16CustomFloatFlags6__initZ@Base 6
+ _D40TypeInfo_E3std8encoding15Windows1252Char6__initZ@Base 6
+ _D40TypeInfo_E3std9exception14RangePrimitive6__initZ@Base 6
+ _D40TypeInfo_S3etc1c7sqlite314sqlite3_module6__initZ@Base 6
+ _D40TypeInfo_S3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D40TypeInfo_xC3std11concurrency10MessageBox6__initZ@Base 6
+ _D41TypeInfo_AE3std8encoding15Windows1252Char6__initZ@Base 6
+ _D41TypeInfo_E3etc1c4curl18CurlFInfoFlagKnown6__initZ@Base 6
+ _D41TypeInfo_E3std8datetime16AllowDayOverflow6__initZ@Base 6
+ _D41TypeInfo_HAyaDFC3std3xml13ElementParserZv6__initZ@Base 6
+ _D41TypeInfo_S3std11parallelism12AbstractTask6__initZ@Base 6
+ _D41TypeInfo_S3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D41TypeInfo_S3std4math20FloatingPointControl6__initZ@Base 6
+ _D41TypeInfo_S3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D41TypeInfo_xS3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D426TypeInfo_S3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result6__initZ@Base 6
+ _D427TypeInfo_xS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6Result6__initZ@Base 6
+ _D42TypeInfo_AC3std3xml21ProcessingInstruction6__initZ@Base 6
+ _D42TypeInfo_AS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D42TypeInfo_E3std5regex8internal2ir9RegexInfo6__initZ@Base 6
+ _D42TypeInfo_HaE3std6traits17FunctionAttribute6__initZ@Base 6
+ _D42TypeInfo_S3std3net4curl12__T4PoolTAhZ4Pool6__initZ@Base 6
+ _D42TypeInfo_S3std5range13__T6RepeatTiZ6Repeat6__initZ@Base 6
+ _D42TypeInfo_xS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D42TypeInfo_xS3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D42TypeInfo_xS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D42TypeInfo_xS4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D43TypeInfo_AxS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D43TypeInfo_E3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D43TypeInfo_E3std9algorithm10comparison6EditOp6__initZ@Base 6
+ _D43TypeInfo_FS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D43TypeInfo_PxS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D43TypeInfo_S3std1c5linux5linux13struct_stat646__initZ@Base 6
+ _D43TypeInfo_S3std5range14__T6ChunksTAhZ6Chunks6__initZ@Base 6
+ _D43TypeInfo_xAS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D43TypeInfo_xPS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D44TypeInfo_DFS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D44TypeInfo_E3std6traits21ParameterStorageClass6__initZ@Base 6
+ _D44TypeInfo_E3std9algorithm7sorting10SortOutput6__initZ@Base 6
+ _D44TypeInfo_E3std9algorithm9searching9OpenRight6__initZ@Base 6
+ _D44TypeInfo_S3etc1c7sqlite318sqlite3_index_info6__initZ@Base 6
+ _D44TypeInfo_S3etc1c7sqlite318sqlite3_io_methods6__initZ@Base 6
+ _D44TypeInfo_S3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D44TypeInfo_S3std5stdio4File17LockingTextWriter6__initZ@Base 6
+ _D44TypeInfo_xC3std11concurrency14LinkTerminated6__initZ@Base 6
+ _D44TypeInfo_xE3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D45TypeInfo_AS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D45TypeInfo_E3std5regex8internal2ir11RegexOption6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_mem_methods6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_pcache_page6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_vtab_cursor6__initZ@Base 6
+ _D45TypeInfo_S3std3net4curl20AsyncChunkInputRange6__initZ@Base 6
+ _D45TypeInfo_S3std7numeric14__T6StrideTAfZ6Stride6__initZ@Base 6
+ _D45TypeInfo_S3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D45TypeInfo_S3std8typecons14__T5TupleTbTiZ5Tuple6__initZ@Base 6
+ _D45TypeInfo_S3std8typecons14__T5TupleTmTmZ5Tuple6__initZ@Base 6
+ _D45TypeInfo_xC3std11concurrency15OwnerTerminated6__initZ@Base 6
+ _D45TypeInfo_xDFS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D45TypeInfo_xS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_AxS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_E3std11parallelism8TaskPool9PoolState6__initZ@Base 6
+ _D46TypeInfo_S3std3uni7unicode18hangulSyllableType6__initZ@Base 6
+ _D46TypeInfo_S3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D46TypeInfo_S3std6traits23__InoutWorkaroundStruct6__initZ@Base 6
+ _D46TypeInfo_S3std7complex14__T7ComplexTeZ7Complex6__initZ@Base 6
+ _D46TypeInfo_S3std8internal14unicode_tables6blocks6__initZ@Base 6
+ _D46TypeInfo_S3std8internal14unicode_tables6hangul6__initZ@Base 6
+ _D46TypeInfo_xAS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_yS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D47TypeInfo_AC3std11parallelism17ParallelismThread6__initZ@Base 6
+ _D47TypeInfo_AS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D47TypeInfo_E3std8internal4test10dummyrange6Length6__initZ@Base 6
+ _D47TypeInfo_E3std9algorithm8mutation12SwapStrategy6__initZ@Base 6
+ _D47TypeInfo_PyS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D47TypeInfo_S3etc1c7sqlite321sqlite3_mutex_methods6__initZ@Base 6
+ _D47TypeInfo_S3std5array16__T8AppenderTAaZ8Appender6__initZ@Base 6
+ _D47TypeInfo_S3std5array16__T8AppenderTAhZ8Appender6__initZ@Base 6
+ _D47TypeInfo_S3std6traits15__T8DemangleTkZ8Demangle6__initZ@Base 6
+ _D47TypeInfo_S3std8bitmanip14__T7BitsSetTmZ7BitsSet6__initZ@Base 6
+ _D47TypeInfo_S3std8internal14unicode_tables7scripts6__initZ@Base 6
+ _D47TypeInfo_S3std8typecons16__T5TupleTiTAyaZ5Tuple6__initZ@Base 6
+ _D47TypeInfo_S3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D47TypeInfo_xS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_APyS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D48TypeInfo_AS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D48TypeInfo_AxS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_E3std4uuid20UUIDParsingException6Reason6__initZ@Base 6
+ _D48TypeInfo_S3etc1c7sqlite322sqlite3_pcache_methods6__initZ@Base 6
+ _D48TypeInfo_S3etc1c7sqlite322sqlite3_rtree_geometry6__initZ@Base 6
+ _D48TypeInfo_S3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAxaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAyaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAyuZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAywZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTyAaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std8internal14unicode_tables8uniProps6__initZ@Base 6
+ _D48TypeInfo_xAS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_xC3std12experimental6logger4core6Logger6__initZ@Base 6
+ _D48TypeInfo_xS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_AxS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_E3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D49TypeInfo_E3std8internal4test10dummyrange8ReturnBy6__initZ@Base 6
+ _D49TypeInfo_E3std8typecons24RefCountedAutoInitialize6__initZ@Base 6
+ _D49TypeInfo_S3etc1c7sqlite323sqlite3_pcache_methods26__initZ@Base 6
+ _D49TypeInfo_S3std12experimental6logger4core8MsgRange6__initZ@Base 6
+ _D49TypeInfo_S3std3uni18simpleCaseFoldingsFNewZ5Range6__initZ@Base 6
+ _D49TypeInfo_S3std5array18__T8AppenderTAAyaZ8Appender6__initZ@Base 6
+ _D49TypeInfo_S3std5regex18__T8CapturesTAaTmZ8Captures6__initZ@Base 6
+ _D49TypeInfo_S3std6stream6Stream6toHashMFNeZ8resUnion6__initZ@Base 6
+ _D49TypeInfo_S3std8datetime24ComparingBenchmarkResult6__initZ@Base 6
+ _D49TypeInfo_S3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D49TypeInfo_S3std8internal4math11biguintcore7BigUint6__initZ@Base 6
+ _D49TypeInfo_S3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_xAS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_xS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D4core4stdc6stdarg11__T6va_argZ6va_argFNbKG1S3gcc8builtins13__va_list_tagC8TypeInfoPvZv@Base 6
+ _D4core4time12TickDuration22__T8opBinaryVAyaa1_2bZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration25__T10opOpAssignVAyaa1_2bZ10opOpAssignMFNaNbNcNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_6d73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T18getUnitsFromHNSecsVAyaa6_686e73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7573656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa6_686e73656373VAyaa4_64617973Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time48__T7convertVAyaa4_64617973VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_686f757273VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7573656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_686f757273Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa5_686f757273VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_6d696e75746573Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time7FracSec28__T4fromVAyaa6_686e73656373Z4fromFNaNflZS4core4time7FracSec@Base 6
+ _D4core4time8Duration27__T5totalVAyaa5_6d73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration29__T5totalVAyaa6_686e73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration31__T5totalVAyaa7_7365636f6e6473Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration43__T8opBinaryVAyaa1_2bTS4core4time8DurationZ8opBinaryMxFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration44__T8opBinaryVAyaa1_2bTxS4core4time8DurationZ8opBinaryMxFNaNbNiNfxS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration44__T8opBinaryVAyaa1_2bTyS4core4time8DurationZ8opBinaryMxFNaNbNiNfyS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z14__T5splitTiTiZ5splitMxFNaNbNiNfJiJiZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration48__T8opBinaryVAyaa1_2dTS4core4time12TickDurationZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration51__T10opOpAssignVAyaa1_2dTS4core4time12TickDurationZ10opOpAssignMFNaNbNcNiNfxS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration54__T13opBinaryRightVAyaa1_2bTS4core4time12TickDurationZ13opBinaryRightMxFNaNbNiNfS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core6atomic122__T11atomicStoreVE4core6atomic11MemoryOrderi5TE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateZ11atomicStoreFNaNbNiKOE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZv@Base 6
+ _D4core6atomic122__T3casTE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateZ3casFNaNbNiPOE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D4core6atomic125__T11atomicStoreVE4core6atomic11MemoryOrderi3TC3std12experimental6logger4core6LoggerTOC3std12experimental6logger4core6LoggerZ11atomicStoreFNaNbNiKOC3std12experimental6logger4core6LoggerOC3std12experimental6logger4core6LoggerZv@Base 6
+ _D4core6atomic128__T11atomicStoreVE4core6atomic11MemoryOrderi3TE3std12experimental6logger4core8LogLevelTE3std12experimental6logger4core8LogLevelZ11atomicStoreFNaNbNiKOE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D4core6atomic128__T7casImplTE3std11parallelism8TaskPool9PoolStateTxE3std11parallelism8TaskPool9PoolStateTxE3std11parallelism8TaskPool9PoolStateZ7casImplFNaNbNiPOE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D4core6atomic14__T3casTbTbTbZ3casFNaNbNiPObxbxbZb@Base 6
+ _D4core6atomic20__T7casImplTbTxbTxbZ7casImplFNaNbNiPObxbxbZb@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi2TbZ10atomicLoadFNaNbNiKOxbZb@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5ThZ10atomicLoadFNaNbNiKOxhZh@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5TkZ10atomicLoadFNaNbNiKOxkZk@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi3TbTbZ11atomicStoreFNaNbNiKObbZv@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi5ThThZ11atomicStoreFNaNbNiKOhhZv@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi5TkTkZ11atomicStoreFNaNbNiKOkkZv@Base 6
+ _D4core6atomic58__T3casTC4core4sync5mutex5MutexTnTC4core4sync5mutex5MutexZ3casFNaNbNiPOC4core4sync5mutex5MutexOxnOC4core4sync5mutex5MutexZb@Base 6
+ _D4core6atomic65__T7casImplTC4core4sync5mutex5MutexTOxnTOC4core4sync5mutex5MutexZ7casImplFNaNbNiPOC4core4sync5mutex5MutexOxnOC4core4sync5mutex5MutexZb@Base 6
+ _D4core6atomic69__T10atomicLoadVE4core6atomic11MemoryOrderi2TC4core4sync5mutex5MutexZ10atomicLoadFNaNbNiKOxC4core4sync5mutex5MutexZC4core4sync5mutex5Mutex@Base 6
+ _D4core6atomic83__T10atomicLoadVE4core6atomic11MemoryOrderi5TE3std11parallelism8TaskPool9PoolStateZ10atomicLoadFNaNbNiKOxE3std11parallelism8TaskPool9PoolStateZE3std11parallelism8TaskPool9PoolState@Base 6
+ _D4core6atomic84__T10atomicLoadVE4core6atomic11MemoryOrderi2TC3std12experimental6logger4core6LoggerZ10atomicLoadFNaNbNiKOxC3std12experimental6logger4core6LoggerZC3std12experimental6logger4core6Logger@Base 6
+ _D4core6atomic86__T10atomicLoadVE4core6atomic11MemoryOrderi2TE3std12experimental6logger4core8LogLevelZ10atomicLoadFNaNbNiKOxE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D4core8internal4hash15__T6hashOfTAxaZ6hashOfFNaNbNfKAxamZm@Base 6
+ _D4core8internal4hash15__T6hashOfTAyaZ6hashOfFNaNbNfKAyamZm@Base 6
+ _D4core8internal7convert15__T7toUbyteTxaZ7toUbyteFNaNbNiNeAxaZAxh@Base 6
+ _D4core8internal7convert15__T7toUbyteTyaZ7toUbyteFNaNbNiNeAyaZAxh@Base 6
+ _D50TypeInfo_E3std8internal4test10dummyrange9RangeType6__initZ@Base 6
+ _D50TypeInfo_PxS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D50TypeInfo_S3etc1c7sqlite324sqlite3_rtree_query_info6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTbVmi1Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTkVmi7Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTkVmi8Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std5regex19__T8CapturesTAxaTmZ8Captures6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D50TypeInfo_xE3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D50TypeInfo_xPS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D50TypeInfo_xS3std5regex18__T8CapturesTAaTmZ8Captures6__initZ@Base 6
+ _D50TypeInfo_yS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D51TypeInfo_AyS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVmi11Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVmi12Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVmi13Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVmi14Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVmi15Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVmi16Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std5range13__T4iotaTmTmZ4iotaFmmZ6Result6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii160Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std7variant18__T8VariantNVmi32Z8VariantN6__initZ@Base 6
+ _D51TypeInfo_xS3std5regex19__T8CapturesTAxaTmZ8Captures6__initZ@Base 6
+ _D51TypeInfo_xS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_xS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D51TypeInfo_yS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_yS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_AxS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_AxS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_AyS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_AyS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVmi0Vmi5Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVmi0Vmi6Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVmi0Vmi7Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVmi0Vmi9Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std5array16__T8AppenderTAaZ8Appender4Data6__initZ@Base 6
+ _D52TypeInfo_S3std5array16__T8AppenderTAhZ8Appender4Data6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D52TypeInfo_xAS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_xAS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_xAyS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D52TypeInfo_xS3std7variant18__T8VariantNVmi32Z8VariantN6__initZ@Base 6
+ _D53TypeInfo_AS3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi5Vmi13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi6Vmi10Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi6Vmi13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi7Vmi13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi8Vmi21Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi9Vmi13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVmi9Vmi21Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAxaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAyaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAyuZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAywZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTyAaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5regex8internal12backtracking9CtContext6__initZ@Base 6
+ _D53TypeInfo_S3std6format18__T10FormatSpecTaZ10FormatSpec6__initZ@Base 6
+ _D53TypeInfo_S3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D54TypeInfo_AxS3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D54TypeInfo_G3S3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVmi10Vmi14Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVmi14Vmi21Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std5array18__T8AppenderTAAyaZ8Appender4Data6__initZ@Base 6
+ _D54TypeInfo_S3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D54TypeInfo_S3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D54TypeInfo_S3std8internal14unicode_tables13FullCaseEntry6__initZ@Base 6
+ _D54TypeInfo_xAS3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D55TypeInfo_AS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D55TypeInfo_PS3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D55TypeInfo_S3std5range13__T6RepeatTiZ6Repeat11DollarToken6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPmZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_xG3S3std5regex8internal2ir12__T5GroupTmZ5Group6__initZ@Base 6
+ _D55TypeInfo_xS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D56TypeInfo_APS3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D56TypeInfo_AxS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D56TypeInfo_E3std7variant18__T8VariantNVmi32Z8VariantN4OpID6__initZ@Base 6
+ _D56TypeInfo_S3std12experimental6logger4core6Logger8LogEntry6__initZ@Base 6
+ _D56TypeInfo_S3std5range14__T6ChunksTAhZ6Chunks11DollarToken6__initZ@Base 6
+ _D56TypeInfo_S3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D56TypeInfo_S3std8internal14unicode_tables15SimpleCaseEntry6__initZ@Base 6
+ _D56TypeInfo_S3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D56TypeInfo_xAS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D57TypeInfo_S3std3net4curl19__T11CurlMessageTbZ11CurlMessage6__initZ@Base 6
+ _D57TypeInfo_S3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult6__initZ@Base 6
+ _D57TypeInfo_xS3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D57TypeInfo_yS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D581TypeInfo_S3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTmTmZ4iotaFmmZ6ResultZ12FilterResultZ9MapResultZ6Result6__initZ@Base 6
+ _D58TypeInfo_AyS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D58TypeInfo_E3std8typecons28__T4FlagVAyaa6_756e73616665Z4Flag6__initZ@Base 6
+ _D58TypeInfo_xS3std5range23__T10OnlyResultTaHVmi1Z10OnlyResult6__initZ@Base 6
+ _D59TypeInfo_S3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage6__initZ@Base 6
+ _D59TypeInfo_xAyS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D60TypeInfo_E3std3net4curl20AsyncChunkInputRange8__mixin55State6__initZ@Base 6
+ _D60TypeInfo_S3std3uni25__T13PackedPtrImplThVmi8Z13PackedPtrImpl6__initZ@Base 6
+ _D60TypeInfo_S3std5regex8internal6parser15__T6ParserTAyaZ6Parser6__initZ@Base 6
+ _D60TypeInfo_S3std5regex8internal8thompson13__T6ThreadTmZ6Thread6__initZ@Base 6
+ _D61TypeInfo_S3std3uni26__T13PackedPtrImplTtVmi16Z13PackedPtrImpl6__initZ@Base 6
+ _D61TypeInfo_S3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D61TypeInfo_S3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTaZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTbZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperThZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTiZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTkZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTlZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTmZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTtZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_xE3std3net4curl20AsyncChunkInputRange8__mixin55State6__initZ@Base 6
+ _D61TypeInfo_xS3std5regex8internal8thompson13__T6ThreadTmZ6Thread6__initZ@Base 6
+ _D62TypeInfo_AS3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D62TypeInfo_PxS3std5regex8internal8thompson13__T6ThreadTmZ6Thread6__initZ@Base 6
+ _D62TypeInfo_S3std8bitmanip22__T13EndianSwapperTxkZ13EndianSwapper6__initZ@Base 6
+ _D62TypeInfo_xPS3std5regex8internal8thompson13__T6ThreadTmZ6Thread6__initZ@Base 6
+ _D62TypeInfo_xS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D63TypeInfo_S3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D64TypeInfo_E3std8typecons34__T4FlagVAyaa9_706970654f6e506f70Z4Flag6__initZ@Base 6
+ _D64TypeInfo_S3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D64TypeInfo_S3std7variant18__T8VariantNVmi32Z8VariantN11SizeChecker6__initZ@Base 6
+ _D64TypeInfo_S3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__initZ@Base 6
+ _D64TypeInfo_xS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D65TypeInfo_S3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D65TypeInfo_S3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG32hZ5Tuple6__initZ@Base 6
+ _D65TypeInfo_S3std8typecons34__T5TupleTC14TypeInfo_ClassTPG32hZ5Tuple6__initZ@Base 6
+ _D65TypeInfo_xS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D66TypeInfo_S3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D66TypeInfo_S3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__initZ@Base 6
+ _D66TypeInfo_S3std8typecons35__T5TupleTC15TypeInfo_StructTPG32hZ5Tuple6__initZ@Base 6
+ _D66TypeInfo_S3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__initZ@Base 6
+ _D66TypeInfo_xS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D670TypeInfo_S3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result6__initZ@Base 6
+ _D67TypeInfo_AS3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D67TypeInfo_S3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D67TypeInfo_S3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__initZ@Base 6
+ _D67TypeInfo_S3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6__initZ@Base 6
+ _D67TypeInfo_S3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result6__initZ@Base 6
+ _D68TypeInfo_xS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D69TypeInfo_E3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D69TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG32hZ5Tuple6__initZ@Base 6
+ _D69TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D6object102__T11_trustedDupTS3std8datetime13PosixTimeZone10LeapSecondTyS3std8datetime13PosixTimeZone10LeapSecondZ11_trustedDupFNaNbNeAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object102__T11_trustedDupTS3std8datetime13PosixTimeZone10TransitionTyS3std8datetime13PosixTimeZone10TransitionZ11_trustedDupFNaNbNeAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object10__T3dupTaZ3dupFNaNbNdNfAxaZAa@Base 6
+ _D6object10__T3dupThZ3dupFNaNbNdNfAxhZAh@Base 6
+ _D6object10__T3dupTkZ3dupFNaNbNdNfAxkZAk@Base 6
+ _D6object10__T3dupTmZ3dupFNaNbNdNfAxmZAm@Base 6
+ _D6object11__T4idupTaZ4idupFNaNbNdNfAaZAya@Base 6
+ _D6object12__T3dupTAyaZ3dupFNaNbNdNfAxAyaZAAya@Base 6
+ _D6object12__T3getTmTmZ3getFNaNfNgHmmmLNgmZNgm@Base 6
+ _D6object12__T4idupTxaZ4idupFNaNbNdNfAxaZAya@Base 6
+ _D6object12__T4idupTxhZ4idupFNaNbNdNfAxhZAyh@Base 6
+ _D6object12__T4idupTxuZ4idupFNaNbNdNfAxuZAyu@Base 6
+ _D6object12__T4idupTxwZ4idupFNaNbNdNfAxwZAyw@Base 6
+ _D6object14__T4_dupTaTyaZ4_dupFNaNbAaZAya@Base 6
+ _D6object14__T4_dupTxaTaZ4_dupFNaNbAxaZAa@Base 6
+ _D6object14__T4_dupTxhThZ4_dupFNaNbAxhZAh@Base 6
+ _D6object14__T4_dupTxkTkZ4_dupFNaNbAxkZAk@Base 6
+ _D6object14__T4_dupTxmTmZ4_dupFNaNbAxmZAm@Base 6
+ _D6object14__T7_rawDupTaZ7_rawDupFNaNbANgaZANga@Base 6
+ _D6object14__T7_rawDupThZ7_rawDupFNaNbANghZANgh@Base 6
+ _D6object14__T7_rawDupTkZ7_rawDupFNaNbANgkZANgk@Base 6
+ _D6object14__T7_rawDupTmZ7_rawDupFNaNbANgmZANgm@Base 6
+ _D6object14__T7_rawDupTuZ7_rawDupFNaNbANguZANgu@Base 6
+ _D6object14__T7_rawDupTwZ7_rawDupFNaNbANgwZANgw@Base 6
+ _D6object14__T7reserveTaZ7reserveFNaNbNeKAamZm@Base 6
+ _D6object15__T4_dupTxaTyaZ4_dupFNaNbAxaZAya@Base 6
+ _D6object15__T4_dupTxhTyhZ4_dupFNaNbAxhZAyh@Base 6
+ _D6object15__T4_dupTxuTyuZ4_dupFNaNbAxuZAyu@Base 6
+ _D6object15__T4_dupTxwTywZ4_dupFNaNbAxwZAyw@Base 6
+ _D6object15__T6hashOfTAxaZ6hashOfFNaNbNfKAxamZm@Base 6
+ _D6object15__T6hashOfTAyaZ6hashOfFNaNbNfKAyamZm@Base 6
+ _D6object15__T8capacityTaZ8capacityFNaNbNdAaZm@Base 6
+ _D6object15__T8capacityThZ8capacityFNaNbNdAhZm@Base 6
+ _D6object15__T8capacityTlZ8capacityFNaNbNdAlZm@Base 6
+ _D6object16__T7_rawDupTAyaZ7_rawDupFNaNbANgAyaZANgAya@Base 6
+ _D6object17__T8capacityTAyaZ8capacityFNaNbNdAAyaZm@Base 6
+ _D6object18__T4_dupTxAyaTAyaZ4_dupFNaNbAxAyaZAAya@Base 6
+ _D6object19__T11_doPostblitTaZ11_doPostblitFNaNbNiNfAaZv@Base 6
+ _D6object19__T11_doPostblitThZ11_doPostblitFNaNbNiNfAhZv@Base 6
+ _D6object19__T11_doPostblitTkZ11_doPostblitFNaNbNiNfAkZv@Base 6
+ _D6object19__T11_doPostblitTmZ11_doPostblitFNaNbNiNfAmZv@Base 6
+ _D6object20__T11_doPostblitTyaZ11_doPostblitFNaNbNiNfAyaZv@Base 6
+ _D6object20__T11_doPostblitTyhZ11_doPostblitFNaNbNiNfAyhZv@Base 6
+ _D6object20__T11_doPostblitTyuZ11_doPostblitFNaNbNiNfAyuZv@Base 6
+ _D6object20__T11_doPostblitTywZ11_doPostblitFNaNbNiNfAywZv@Base 6
+ _D6object20__T12_getPostblitTaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKaZv@Base 6
+ _D6object20__T12_getPostblitThZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKhZv@Base 6
+ _D6object20__T12_getPostblitTkZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKkZv@Base 6
+ _D6object20__T12_getPostblitTmZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKmZv@Base 6
+ _D6object21__T11_doPostblitTAyaZ11_doPostblitFNaNbNiNfAAyaZv@Base 6
+ _D6object21__T12_getPostblitTyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyaZv@Base 6
+ _D6object21__T12_getPostblitTyhZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyhZv@Base 6
+ _D6object21__T12_getPostblitTyuZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyuZv@Base 6
+ _D6object21__T12_getPostblitTywZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKywZv@Base 6
+ _D6object22__T11_trustedDupTaTyaZ11_trustedDupFNaNbNeAaZAya@Base 6
+ _D6object22__T11_trustedDupTxaTaZ11_trustedDupFNaNbNeAxaZAa@Base 6
+ _D6object22__T11_trustedDupTxhThZ11_trustedDupFNaNbNeAxhZAh@Base 6
+ _D6object22__T11_trustedDupTxkTkZ11_trustedDupFNaNbNeAxkZAk@Base 6
+ _D6object22__T11_trustedDupTxmTmZ11_trustedDupFNaNbNeAxmZAm@Base 6
+ _D6object22__T12_getPostblitTAyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKAyaZv@Base 6
+ _D6object23__T11_trustedDupTxaTyaZ11_trustedDupFNaNbNeAxaZAya@Base 6
+ _D6object23__T11_trustedDupTxhTyhZ11_trustedDupFNaNbNeAxhZAyh@Base 6
+ _D6object23__T11_trustedDupTxuTyuZ11_trustedDupFNaNbNeAxuZAyu@Base 6
+ _D6object23__T11_trustedDupTxwTywZ11_trustedDupFNaNbNeAxwZAyw@Base 6
+ _D6object24__T16assumeSafeAppendTkZ16assumeSafeAppendFNbNcKNgAkZNgAk@Base 6
+ _D6object26__T11_trustedDupTxAyaTAyaZ11_trustedDupFNaNbNeAxAyaZAAya@Base 6
+ _D6object29__T7destroyTS3std5stdio4FileZ7destroyFNfKS3std5stdio4FileZv@Base 6
+ _D6object33__T8capacityTS3std4file8DirEntryZ8capacityFNaNbNdAS3std4file8DirEntryZm@Base 6
+ _D6object36__T7destroyTS3std3net4curl3FTP4ImplZ7destroyFKS3std3net4curl3FTP4ImplZv@Base 6
+ _D6object37__T7destroyTS3std3net4curl4HTTP4ImplZ7destroyFKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D6object37__T7destroyTS3std3net4curl4SMTP4ImplZ7destroyFKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D6object39__T16_destructRecurseTS3std5stdio4FileZ16_destructRecurseFNfKS3std5stdio4FileZv@Base 6
+ _D6object39__T7destroyTS3std11concurrency7MessageZ7destroyFKS3std11concurrency7MessageZv@Base 6
+ _D6object39__T8capacityTS3std6socket11AddressInfoZ8capacityFNaNbNdAS3std6socket11AddressInfoZm@Base 6
+ _D6object40__T11_doPostblitTS3std11concurrency3TidZ11_doPostblitFNaNbNiNfAS3std11concurrency3TidZv@Base 6
+ _D6object40__T7destroyTS3std4file15DirIteratorImplZ7destroyFKS3std4file15DirIteratorImplZv@Base 6
+ _D6object41__T12_getPostblitTS3std11concurrency3TidZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKS3std11concurrency3TidZv@Base 6
+ _D6object45__T7reserveTS3std5regex8internal2ir8BytecodeZ7reserveFNaNbNeKAS3std5regex8internal2ir8BytecodemZm@Base 6
+ _D6object46__T16_destructRecurseTS3std3net4curl3FTP4ImplZ16_destructRecurseFKS3std3net4curl3FTP4ImplZv@Base 6
+ _D6object47__T16_destructRecurseTS3std3net4curl4HTTP4ImplZ16_destructRecurseFKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D6object47__T16_destructRecurseTS3std3net4curl4SMTP4ImplZ16_destructRecurseFKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D6object49__T16_destructRecurseTS3std11concurrency7MessageZ16_destructRecurseFKS3std11concurrency7MessageZv@Base 6
+ _D6object50__T16_destructRecurseTS3std4file15DirIteratorImplZ16_destructRecurseFKS3std4file15DirIteratorImplZv@Base 6
+ _D6object51__T4idupTS3std8datetime13PosixTimeZone10LeapSecondZ4idupFNaNbNdNfAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object51__T4idupTS3std8datetime13PosixTimeZone10TransitionZ4idupFNaNbNdNfAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object51__T8capacityTS3std4file15DirIteratorImpl9DirHandleZ8capacityFNaNbNdAS3std4file15DirIteratorImpl9DirHandleZm@Base 6
+ _D6object54__T7_rawDupTS3std8datetime13PosixTimeZone10LeapSecondZ7_rawDupFNaNbANgS3std8datetime13PosixTimeZone10LeapSecondZANgS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object54__T7_rawDupTS3std8datetime13PosixTimeZone10TransitionZ7_rawDupFNaNbANgS3std8datetime13PosixTimeZone10TransitionZANgS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object57__T8_ArrayEqTxS3std4json9JSONValueTxS3std4json9JSONValueZ8_ArrayEqFNaNbNiAxS3std4json9JSONValueAxS3std4json9JSONValueZb@Base 6
+ _D6object60__T11_doPostblitTyS3std8datetime13PosixTimeZone10LeapSecondZ11_doPostblitFNaNbNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D6object60__T11_doPostblitTyS3std8datetime13PosixTimeZone10TransitionZ11_doPostblitFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D6object60__T4keysHTHS3std11concurrency3TidbTbTS3std11concurrency3TidZ4keysFNaNbNdHS3std11concurrency3TidbZAS3std11concurrency3Tid@Base 6
+ _D6object61__T12_getPostblitTyS3std8datetime13PosixTimeZone10LeapSecondZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKyS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D6object61__T12_getPostblitTyS3std8datetime13PosixTimeZone10TransitionZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D6object61__T16assumeSafeAppendTS3std8typecons16__T5TupleTkTkTkZ5TupleZ16assumeSafeAppendFNbNcKNgAS3std8typecons16__T5TupleTkTkTkZ5TupleZNgAS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D6object62__T4keysHTxHAyaS3std4json9JSONValueTxS3std4json9JSONValueTAyaZ4keysFNaNbNdxHAyaS3std4json9JSONValueZAAya@Base 6
+ _D6object83__T16assumeSafeAppendTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ16assumeSafeAppendFNbNcKNgAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZNgAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D6object87__T16assumeSafeAppendTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16assumeSafeAppendFNbNcKNgAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZNgAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D6object90__T16assumeSafeAppendTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZ16assumeSafeAppendFNbNcKNgAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZNgAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D6object93__T8_ArrayEqTxS3std8typecons16__T5TupleTkTkTkZ5TupleTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ8_ArrayEqFNaNbNiNfAxS3std8typecons16__T5TupleTkTkTkZ5TupleAxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D6object94__T4_dupTS3std8datetime13PosixTimeZone10LeapSecondTyS3std8datetime13PosixTimeZone10LeapSecondZ4_dupFNaNbAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object94__T4_dupTS3std8datetime13PosixTimeZone10TransitionTyS3std8datetime13PosixTimeZone10TransitionZ4_dupFNaNbAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D70TypeInfo_AE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D70TypeInfo_S3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D70TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6__initZ@Base 6
+ _D70TypeInfo_S3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data6__initZ@Base 6
+ _D70TypeInfo_S3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__initZ@Base 6
+ _D70TypeInfo_S3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6__initZ@Base 6
+ _D70TypeInfo_S3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList6__initZ@Base 6
+ _D70TypeInfo_xE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_AxE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_E3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4Flag6__initZ@Base 6
+ _D71TypeInfo_S3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D71TypeInfo_S3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__initZ@Base 6
+ _D71TypeInfo_S3std8typecons40__T5TupleTmVAyaa3_706f73TmVAyaa3_6c656eZ5Tuple6__initZ@Base 6
+ _D71TypeInfo_xAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_xS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D71TypeInfo_xS3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList6__initZ@Base 6
+ _D72TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D72TypeInfo_S3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__initZ@Base 6
+ _D72TypeInfo_S3std3uni31__T19PackedArrayViewImplThVmi8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D72TypeInfo_S3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D72TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D72TypeInfo_xS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D73TypeInfo_E3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4Flag6__initZ@Base 6
+ _D73TypeInfo_S3std3uni32__T19PackedArrayViewImplTtVmi16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D73TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D73TypeInfo_S3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D73TypeInfo_S3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D74TypeInfo_AS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D74TypeInfo_S3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D74TypeInfo_S3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__initZ@Base 6
+ _D74TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D74TypeInfo_xS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D74TypeInfo_xS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D75TypeInfo_AxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D75TypeInfo_E3std8typecons45__T4FlagVAyaa14_6b6565705465726d696e61746f72Z4Flag6__initZ@Base 6
+ _D75TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D75TypeInfo_xAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D76TypeInfo_S3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D76TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__initZ@Base 6
+ _D76TypeInfo_S3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D76TypeInfo_S3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data6__initZ@Base 6
+ _D76TypeInfo_S3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D76TypeInfo_S3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink6__initZ@Base 6
+ _D76TypeInfo_S3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry6__initZ@Base 6
+ _D76TypeInfo_xS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_AS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D77TypeInfo_PxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_S3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__initZ@Base 6
+ _D77TypeInfo_xPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_xS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D77TypeInfo_xS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D78TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D78TypeInfo_S3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__initZ@Base 6
+ _D78TypeInfo_S3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__initZ@Base 6
+ _D78TypeInfo_S3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D78TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D79TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6__initZ@Base 6
+ _D79TypeInfo_S3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6__initZ@Base 6
+ _D79TypeInfo_S3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D79TypeInfo_S3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D79TypeInfo_xS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D80TypeInfo_S3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__initZ@Base 6
+ _D80TypeInfo_S3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D83TypeInfo_E3std8typecons53__T4FlagVAyaa18_707265736572766541747472696275746573Z4Flag6__initZ@Base 6
+ _D83TypeInfo_S3std3uni51__T10assumeSizeS28_D3std3uni5low_8FNaNbNiNfkZkVmi8Z10assumeSize6__initZ@Base 6
+ _D83TypeInfo_S3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D83TypeInfo_S3std5regex8internal8thompson18__T10ThreadListTmZ10ThreadList11ThreadRange6__initZ@Base 6
+ _D83TypeInfo_S3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry6__initZ@Base 6
+ _D84TypeInfo_E3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ5State6__initZ@Base 6
+ _D84TypeInfo_S3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__initZ@Base 6
+ _D84TypeInfo_xS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D85TypeInfo_E3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flag6__initZ@Base 6
+ _D85TypeInfo_S3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__initZ@Base 6
+ _D85TypeInfo_S3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D86TypeInfo_S3std3uni54__T10assumeSizeS31_D3std3uni8midlow_8FNaNbNiNfkZkVmi8Z10assumeSize6__initZ@Base 6
+ _D86TypeInfo_xS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D88TypeInfo_S3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data6__initZ@Base 6
+ _D890TypeInfo_S3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl6__initZ@Base 6
+ _D91TypeInfo_S3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__initZ@Base 6
+ _D92TypeInfo_S3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__initZ@Base 6
+ _D93TypeInfo_S3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D93TypeInfo_S3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6__initZ@Base 6
+ _D94TypeInfo_xS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D96TypeInfo_S3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__initZ@Base 6
+ _DT104_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT104_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT104_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT104_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT104_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT112_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT112_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT112_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT112_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT112_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT120_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT16_D3std11concurrency15ThreadScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _DT16_D3std11concurrency15ThreadScheduler5spawnMFDFZvZv@Base 6
+ _DT16_D3std11concurrency15ThreadScheduler5startMFDFZvZv@Base 6
+ _DT16_D3std11concurrency15ThreadScheduler5yieldMFNbZv@Base 6
+ _DT16_D3std11concurrency15ThreadScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT224_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT24_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT24_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT24_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT24_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT24_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
+ _DT40_D3std11concurrency14FiberScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _DT40_D3std11concurrency14FiberScheduler5spawnMFNbDFZvZv@Base 6
+ _DT40_D3std11concurrency14FiberScheduler5startMFDFZvZv@Base 6
+ _DT40_D3std11concurrency14FiberScheduler5yieldMFNbZv@Base 6
+ _DT40_D3std11concurrency14FiberScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _DT40_D3std6stream11SliceStream9availableMFNdZm@Base 6
+ _DT40_D3std6stream12EndianStream11readStringWMFmZAu@Base 6
+ _DT40_D3std6stream12EndianStream3eofMFNdZb@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJaZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJcZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJdZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJeZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJfZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJgZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJhZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJiZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJjZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJkZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJlZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJmZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJoZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJpZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJqZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJrZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJsZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJtZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJuZv@Base 6
+ _DT40_D3std6stream12EndianStream4readMFJwZv@Base 6
+ _DT40_D3std6stream12EndianStream5getcwMFZu@Base 6
+ _DT40_D3std6stream12FilterStream9availableMFNdZm@Base 6
+ _DT40_D3std6stream14BufferedStream3eofMFNdZb@Base 6
+ _DT40_D3std6stream14BufferedStream8readLineMFAaZAa@Base 6
+ _DT40_D3std6stream14BufferedStream9availableMFNdZm@Base 6
+ _DT40_D3std6stream14BufferedStream9readLineWMFAuZAu@Base 6
+ _DT40_D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9availableMFNdZm@Base 6
+ _DT40_D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9availableMFNdZm@Base 6
+ _DT40_D3std6stream4File9availableMFNdZm@Base 6
+ _DT40_D3std6stream6Stream10readStringMFmZAa@Base 6
+ _DT40_D3std6stream6Stream11readStringWMFmZAu@Base 6
+ _DT40_D3std6stream6Stream3eofMFNdZb@Base 6
+ _DT40_D3std6stream6Stream4getcMFZa@Base 6
+ _DT40_D3std6stream6Stream4readMFAhZm@Base 6
+ _DT40_D3std6stream6Stream4readMFJAaZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJAuZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJaZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJcZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJdZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJeZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJfZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJgZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJhZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJiZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJjZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJkZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJlZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJmZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJoZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJpZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJqZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJrZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJsZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJtZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJuZv@Base 6
+ _DT40_D3std6stream6Stream4readMFJwZv@Base 6
+ _DT40_D3std6stream6Stream5getcwMFZu@Base 6
+ _DT40_D3std6stream6Stream5readfMFYi@Base 6
+ _DT40_D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _DT40_D3std6stream6Stream6ungetcMFaZa@Base 6
+ _DT40_D3std6stream6Stream6vreadfMFAC8TypeInfoG1S3gcc8builtins13__va_list_tagZi@Base 6
+ _DT40_D3std6stream6Stream7opApplyMFMDFKAaZiZi@Base 6
+ _DT40_D3std6stream6Stream7opApplyMFMDFKAuZiZi@Base 6
+ _DT40_D3std6stream6Stream7opApplyMFMDFKmKAaZiZi@Base 6
+ _DT40_D3std6stream6Stream7opApplyMFMDFKmKAuZiZi@Base 6
+ _DT40_D3std6stream6Stream7ungetcwMFuZu@Base 6
+ _DT40_D3std6stream6Stream8readLineMFAaZAa@Base 6
+ _DT40_D3std6stream6Stream8readLineMFZAa@Base 6
+ _DT40_D3std6stream6Stream9availableMFNdZm@Base 6
+ _DT40_D3std6stream6Stream9readExactMFPvmZv@Base 6
+ _DT40_D3std6stream6Stream9readLineWMFAuZAu@Base 6
+ _DT40_D3std6stream6Stream9readLineWMFZAu@Base 6
+ _DT40_D3std7cstream5CFile3eofMFZb@Base 6
+ _DT40_D3std7cstream5CFile4getcMFZa@Base 6
+ _DT40_D3std7cstream5CFile6ungetcMFaZa@Base 6
+ _DT48_D3std12socketstream12SocketStream5closeMFZv@Base 6
+ _DT48_D3std6stream12EndianStream12writeStringWMFAxuZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFaZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFcZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFdZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFeZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFfZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFgZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFhZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFiZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFjZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFkZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFlZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFmZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFoZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFpZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFqZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFrZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFsZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFtZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFuZv@Base 6
+ _DT48_D3std6stream12EndianStream5writeMFwZv@Base 6
+ _DT48_D3std6stream12FilterStream5closeMFZv@Base 6
+ _DT48_D3std6stream12FilterStream5flushMFZv@Base 6
+ _DT48_D3std6stream12MmFileStream5closeMFZv@Base 6
+ _DT48_D3std6stream12MmFileStream5flushMFZv@Base 6
+ _DT48_D3std6stream14BufferedStream5flushMFZv@Base 6
+ _DT48_D3std6stream4File5closeMFZv@Base 6
+ _DT48_D3std6stream6Stream10writeExactMFxPvmZv@Base 6
+ _DT48_D3std6stream6Stream10writeLineWMFAxuZv@Base 6
+ _DT48_D3std6stream6Stream11writeStringMFAxaZv@Base 6
+ _DT48_D3std6stream6Stream12writeStringWMFAxuZv@Base 6
+ _DT48_D3std6stream6Stream5closeMFZv@Base 6
+ _DT48_D3std6stream6Stream5flushMFZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFAxaZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFAxhZm@Base 6
+ _DT48_D3std6stream6Stream5writeMFAxuZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFaZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFcZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFdZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFeZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFfZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFgZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFhZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFiZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFjZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFkZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFlZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFmZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFoZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFpZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFqZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFrZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFsZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFtZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFuZv@Base 6
+ _DT48_D3std6stream6Stream5writeMFwZv@Base 6
+ _DT48_D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _DT48_D3std6stream6Stream6printfMFAxaYm@Base 6
+ _DT48_D3std6stream6Stream6writefMFYC3std6stream12OutputStream@Base 6
+ _DT48_D3std6stream6Stream7vprintfMFAxaG1S3gcc8builtins13__va_list_tagZm@Base 6
+ _DT48_D3std6stream6Stream7writefxMFAC8TypeInfoG1S3gcc8builtins13__va_list_tagiZC3std6stream12OutputStream@Base 6
+ _DT48_D3std6stream6Stream8writeflnMFYC3std6stream12OutputStream@Base 6
+ _DT48_D3std6stream6Stream9writeLineMFAxaZv@Base 6
+ _DT48_D3std7cstream5CFile10writeLineWMFAxuZv@Base 6
+ _DT48_D3std7cstream5CFile5closeMFZv@Base 6
+ _DT48_D3std7cstream5CFile5flushMFZv@Base 6
+ _DT48_D3std7cstream5CFile9writeLineMFAxaZv@Base 6
+ __mod_ref__D3etc1c4curl12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc1c4zlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc1c7sqlite312__ModuleInfoZ@Base 6
+ __mod_ref__D3std10functional12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11concurrency12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11mathspecial12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11parallelism12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger10filelogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger10nulllogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger11multilogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger4core12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12socketstream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4fenv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4math12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4time12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux11linuxextern12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux4tipc12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux5linux12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux7pthread12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6locale12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stdarg12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stddef12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6string12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6wcharh12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c7process12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3csv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3net4curl12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3net7isemail12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3uni12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3uri12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3utf12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3xml12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3zip12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4conv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4file12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4json12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4math12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4meta12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4path12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4uuid12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4zlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5array12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5ascii12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range10interfaces12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range10primitives12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal12backtracking12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal2ir12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal5tests12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal6parser12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal8thompson12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal9generator12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal9kickstart12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6base6412__ModuleInfoZ@Base 6
+ __mod_ref__D3std6bigint12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest2md12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest3crc12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest3sha12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest6digest12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest6ripemd12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6format12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6getopt12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6mmfile12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6random12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6stdint12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6stream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6string12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6system12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6traits12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7complex12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7cstream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7numeric12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7process12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7signals12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7variant12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows7charset12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8iunknown12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8registry12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8syserror12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8bitmanip12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8compiler12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8datetime12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8demangle12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8encoding12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal11processinit12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal11scopebuffer12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal12unicode_comp12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal12unicode_norm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal14unicode_decomp12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal14unicode_tables12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal16unicode_grapheme12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math10biguintx8612__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math11biguintcore12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math12biguintnoasm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math13errorfunction12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math13gammafunction12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4test10dummyrange12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal6digest9sha_SSSE312__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal7cstring12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal7windows8advapi3212__ModuleInfoZ@Base 6
+ __mod_ref__D3std8syserror12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8typecons12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8typelist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm10comparison12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm6setops12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm7sorting12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm8internal12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm8mutation12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm9iteration12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm9searching12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container10binaryheap12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container4util12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5array12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5dlist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5slist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container6rbtree12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9outbuffer12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9stdiobase12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9typetuple12__ModuleInfoZ@Base 6
+ _arraySliceComSliceAssign_m@Base 6
+ deflateInit2@Base 6
+ deflateInit@Base 6
+ inflateBackInit@Base 6
+ inflateInit2@Base 6
+ inflateInit@Base 6
+ std_stdio_static_this@Base 6
--- gcc-6-6.3.0.orig/debian/libgphobos.symbols.arm32
+++ gcc-6-6.3.0/debian/libgphobos.symbols.arm32
@@ -0,0 +1,10380 @@
+ ZLIB_VERNUM@Base 6
+ ZLIB_VERSION@Base 6
+ Z_NULL@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__initZ@Base 6
+ _D101TypeInfo_S3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D102TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D102TypeInfo_S3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D103TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D106TypeInfo_S3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D106TypeInfo_S3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D109TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D112TypeInfo_S3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D113TypeInfo_S3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D114TypeInfo_PS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D114TypeInfo_S3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D115TypeInfo_S3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6__initZ@Base 6
+ _D115TypeInfo_S3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D116TypeInfo_PS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D116TypeInfo_xS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D119TypeInfo_S3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6__initZ@Base 6
+ _D11TypeInfo_Pa6__initZ@Base 6
+ _D11TypeInfo_Pb6__initZ@Base 6
+ _D11TypeInfo_Pd6__initZ@Base 6
+ _D11TypeInfo_Pe6__initZ@Base 6
+ _D11TypeInfo_Pf6__initZ@Base 6
+ _D11TypeInfo_Pg6__initZ@Base 6
+ _D11TypeInfo_Ph6__initZ@Base 6
+ _D11TypeInfo_Pi6__initZ@Base 6
+ _D11TypeInfo_Pk6__initZ@Base 6
+ _D11TypeInfo_Pl6__initZ@Base 6
+ _D11TypeInfo_Pm6__initZ@Base 6
+ _D11TypeInfo_Ps6__initZ@Base 6
+ _D11TypeInfo_Pt6__initZ@Base 6
+ _D11TypeInfo_Pv6__initZ@Base 6
+ _D11TypeInfo_xa6__initZ@Base 6
+ _D11TypeInfo_xb6__initZ@Base 6
+ _D11TypeInfo_xd6__initZ@Base 6
+ _D11TypeInfo_xe6__initZ@Base 6
+ _D11TypeInfo_xf6__initZ@Base 6
+ _D11TypeInfo_xh6__initZ@Base 6
+ _D11TypeInfo_xi6__initZ@Base 6
+ _D11TypeInfo_xk6__initZ@Base 6
+ _D11TypeInfo_xl6__initZ@Base 6
+ _D11TypeInfo_xm6__initZ@Base 6
+ _D11TypeInfo_xs6__initZ@Base 6
+ _D11TypeInfo_xt6__initZ@Base 6
+ _D11TypeInfo_xu6__initZ@Base 6
+ _D11TypeInfo_xv6__initZ@Base 6
+ _D11TypeInfo_xw6__initZ@Base 6
+ _D11TypeInfo_ya6__initZ@Base 6
+ _D11TypeInfo_yb6__initZ@Base 6
+ _D11TypeInfo_yd6__initZ@Base 6
+ _D11TypeInfo_ye6__initZ@Base 6
+ _D11TypeInfo_yf6__initZ@Base 6
+ _D11TypeInfo_yh6__initZ@Base 6
+ _D11TypeInfo_yi6__initZ@Base 6
+ _D11TypeInfo_yk6__initZ@Base 6
+ _D11TypeInfo_yl6__initZ@Base 6
+ _D11TypeInfo_ym6__initZ@Base 6
+ _D11TypeInfo_ys6__initZ@Base 6
+ _D11TypeInfo_yt6__initZ@Base 6
+ _D11TypeInfo_yu6__initZ@Base 6
+ _D11TypeInfo_yw6__initZ@Base 6
+ _D120TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D121TypeInfo_xS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D122TypeInfo_xS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D122TypeInfo_xS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D124TypeInfo_S3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D124TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D125TypeInfo_xS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D125TypeInfo_xS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D127TypeInfo_S3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__initZ@Base 6
+ _D12TypeInfo_AAf6__initZ@Base 6
+ _D12TypeInfo_Axf6__initZ@Base 6
+ _D12TypeInfo_Axh6__initZ@Base 6
+ _D12TypeInfo_Axk6__initZ@Base 6
+ _D12TypeInfo_Axu6__initZ@Base 6
+ _D12TypeInfo_Axv6__initZ@Base 6
+ _D12TypeInfo_Axw6__initZ@Base 6
+ _D12TypeInfo_Ayh6__initZ@Base 6
+ _D12TypeInfo_Ayk6__initZ@Base 6
+ _D12TypeInfo_Ayu6__initZ@Base 6
+ _D12TypeInfo_Ayw6__initZ@Base 6
+ _D12TypeInfo_FZv6__initZ@Base 6
+ _D12TypeInfo_G2k6__initZ@Base 6
+ _D12TypeInfo_G3k6__initZ@Base 6
+ _D12TypeInfo_G4a6__initZ@Base 6
+ _D12TypeInfo_G4k6__initZ@Base 6
+ _D12TypeInfo_Hkk6__initZ@Base 6
+ _D12TypeInfo_Hlh6__initZ@Base 6
+ _D12TypeInfo_Oxa6__initZ@Base 6
+ _D12TypeInfo_Oxd6__initZ@Base 6
+ _D12TypeInfo_Oxe6__initZ@Base 6
+ _D12TypeInfo_Oxf6__initZ@Base 6
+ _D12TypeInfo_Oxh6__initZ@Base 6
+ _D12TypeInfo_Oxi6__initZ@Base 6
+ _D12TypeInfo_Oxk6__initZ@Base 6
+ _D12TypeInfo_Oxl6__initZ@Base 6
+ _D12TypeInfo_Oxm6__initZ@Base 6
+ _D12TypeInfo_Oxs6__initZ@Base 6
+ _D12TypeInfo_Oxt6__initZ@Base 6
+ _D12TypeInfo_Oxu6__initZ@Base 6
+ _D12TypeInfo_Oxw6__initZ@Base 6
+ _D12TypeInfo_PAa6__initZ@Base 6
+ _D12TypeInfo_PAu6__initZ@Base 6
+ _D12TypeInfo_PAw6__initZ@Base 6
+ _D12TypeInfo_Pxa6__initZ@Base 6
+ _D12TypeInfo_Pxd6__initZ@Base 6
+ _D12TypeInfo_Pxk6__initZ@Base 6
+ _D12TypeInfo_Pxv6__initZ@Base 6
+ _D12TypeInfo_xAa6__initZ@Base 6
+ _D12TypeInfo_xAf6__initZ@Base 6
+ _D12TypeInfo_xAh6__initZ@Base 6
+ _D12TypeInfo_xAk6__initZ@Base 6
+ _D12TypeInfo_xAu6__initZ@Base 6
+ _D12TypeInfo_xAv6__initZ@Base 6
+ _D12TypeInfo_xAw6__initZ@Base 6
+ _D12TypeInfo_xPa6__initZ@Base 6
+ _D12TypeInfo_xPd6__initZ@Base 6
+ _D12TypeInfo_xPk6__initZ@Base 6
+ _D12TypeInfo_xPv6__initZ@Base 6
+ _D12TypeInfo_yAa6__initZ@Base 6
+ _D133TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D133TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D134TypeInfo_S3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D135TypeInfo_xS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D136TypeInfo_S3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6__initZ@Base 6
+ _D137TypeInfo_E3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11MatchResult6__initZ@Base 6
+ _D137TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D137TypeInfo_xS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D138TypeInfo_S3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D138TypeInfo_S3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D138TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D138TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D13TypeInfo_AAya6__initZ@Base 6
+ _D13TypeInfo_APxa6__initZ@Base 6
+ _D13TypeInfo_DFZv6__initZ@Base 6
+ _D13TypeInfo_G16h6__initZ@Base 6.2.1-1ubuntu2
+ _D13TypeInfo_Hkxk6__initZ@Base 6
+ _D13TypeInfo_PAyh6__initZ@Base 6
+ _D13TypeInfo_xAya6__initZ@Base 6
+ _D13TypeInfo_xAyh6__initZ@Base 6
+ _D13TypeInfo_xAyk6__initZ@Base 6
+ _D13TypeInfo_xG2k6__initZ@Base 6
+ _D13TypeInfo_xG3k6__initZ@Base 6
+ _D13TypeInfo_xG4a6__initZ@Base 6
+ _D13TypeInfo_xG4k6__initZ@Base 6
+ _D13TypeInfo_xHkk6__initZ@Base 6
+ _D141TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D142TypeInfo_S3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D142TypeInfo_S3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D143TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D143TypeInfo_S3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D145TypeInfo_S3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6__initZ@Base 6
+ _D146TypeInfo_S3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D146TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D146TypeInfo_S3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D149TypeInfo_E3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11MatchResult6__initZ@Base 6
+ _D14TypeInfo_AxAya6__initZ@Base 6
+ _D14TypeInfo_FPvZv6__initZ@Base 6
+ _D14TypeInfo_PG16h6__initZ@Base 6.2.1-1ubuntu2
+ _D14TypeInfo_UPvZv6__initZ@Base 6
+ _D14TypeInfo_xAAya6__initZ@Base 6
+ _D14TypeInfo_xDFZv6__initZ@Base 6
+ _D152TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D153TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D154TypeInfo_S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D154TypeInfo_S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D156TypeInfo_S3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine6__initZ@Base 6
+ _D15TypeInfo_PFPvZv6__initZ@Base 6
+ _D15TypeInfo_PUPvZv6__initZ@Base 6
+ _D160TypeInfo_S3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack6__initZ@Base 6
+ _D161TypeInfo_S3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D161TypeInfo_S3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D162TypeInfo_S3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D162TypeInfo_S3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D162TypeInfo_xS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D162TypeInfo_xS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D163TypeInfo_S3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult6__initZ@Base 6
+ _D165TypeInfo_S3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value6__initZ@Base 6
+ _D167TypeInfo_S3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D168TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__initZ@Base 6
+ _D168TypeInfo_S3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__initZ@Base 6
+ _D169TypeInfo_S3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D16TypeInfo_HAyaAya6__initZ@Base 6
+ _D16TypeInfo_xPFPvZv6__initZ@Base 6
+ _D16TypeInfo_xPUPvZv6__initZ@Base 6
+ _D170TypeInfo_S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D170TypeInfo_S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_G2S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_G2S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D172TypeInfo_S3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__initZ@Base 6
+ _D173TypeInfo_S3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D173TypeInfo_xG2S3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D173TypeInfo_xG2S3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D174TypeInfo_FNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D174TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D174TypeInfo_xS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D175TypeInfo_PFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_S3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D176TypeInfo_xPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D177TypeInfo_xS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D178TypeInfo_S3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D179TypeInfo_xS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D17TypeInfo_HAyaxAya6__initZ@Base 6
+ _D17TypeInfo_xHAyaAya6__initZ@Base 6
+ _D180TypeInfo_AxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D180TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__initZ@Base 6
+ _D180TypeInfo_xAS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D182TypeInfo_S3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D183TypeInfo_xS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D184TypeInfo_S3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D186TypeInfo_FNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D186TypeInfo_S3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D186TypeInfo_S3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D187TypeInfo_PFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D187TypeInfo_xS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D188TypeInfo_xPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb6__initZ@Base 6
+ _D18TypeInfo_xC6Object6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D199TypeInfo_S3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D200TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D215TypeInfo_S3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D216TypeInfo_S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D218TypeInfo_G3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_S3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D219TypeInfo_xG3S3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D21TypeInfo_xC9Exception6__initZ@Base 6
+ _D220TypeInfo_xS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D224TypeInfo_S3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D235TypeInfo_S3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D237TypeInfo_S3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__initZ@Base 6
+ _D23TypeInfo_E3std3uni4Mode6__initZ@Base 6
+ _D240TypeInfo_S3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__initZ@Base 6
+ _D242TypeInfo_S3std9algorithm7sorting201__T11TimSortImplS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ5Slice6__initZ@Base 6
+ _D243TypeInfo_HS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D246TypeInfo_S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D24TypeInfo_AC3std3xml4Item6__initZ@Base 6
+ _D24TypeInfo_AC3std3xml4Text6__initZ@Base 6
+ _D24TypeInfo_E3std6system2OS6__initZ@Base 6
+ _D24TypeInfo_S3std4uuid4UUID6__initZ@Base 6
+ _D25TypeInfo_AC3std3xml5CData6__initZ@Base 6
+ _D25TypeInfo_E3std6stream3BOM6__initZ@Base 6
+ _D25TypeInfo_S3etc1c4curl3_N26__initZ@Base 6
+ _D25TypeInfo_S3std5stdio4File6__initZ@Base 6
+ _D262TypeInfo_S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D264TypeInfo_G4S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D265TypeInfo_xG4S3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D267TypeInfo_S3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult6__initZ@Base 6
+ _D26TypeInfo_E3std3xml7TagType6__initZ@Base 6
+ _D26TypeInfo_HAyaC3std3xml3Tag6__initZ@Base 6
+ _D26TypeInfo_S3etc1c4curl4_N286__initZ@Base 6
+ _D26TypeInfo_S3etc1c4curl4_N316__initZ@Base 6
+ _D26TypeInfo_S3std3uni7unicode6__initZ@Base 6
+ _D26TypeInfo_S3std5stdio5lines6__initZ@Base 6
+ _D26TypeInfo_S3std8typecons2No6__initZ@Base 6
+ _D26TypeInfo_xS3std5stdio4File6__initZ@Base 6
+ _D270TypeInfo_S3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D27TypeInfo_AC3std3xml7Comment6__initZ@Base 6
+ _D27TypeInfo_AC3std3xml7Element6__initZ@Base 6
+ _D27TypeInfo_E3etc1c4curl5CurlM6__initZ@Base 6
+ _D27TypeInfo_S3std3net4curl3FTP6__initZ@Base 6
+ _D27TypeInfo_S3std3uni8GcPolicy6__initZ@Base 6
+ _D27TypeInfo_S3std3uni8Grapheme6__initZ@Base 6
+ _D27TypeInfo_S3std7process4Pipe6__initZ@Base 6
+ _D27TypeInfo_S3std8typecons3Yes6__initZ@Base 6
+ _D27TypeInfo_xC3std7process3Pid6__initZ@Base 6
+ _D28TypeInfo_E3std3csv9Malformed6__initZ@Base 6
+ _D28TypeInfo_E3std4file8SpanMode6__initZ@Base 6
+ _D28TypeInfo_E3std6format6Mangle6__initZ@Base 6
+ _D28TypeInfo_E3std6getopt6config6__initZ@Base 6
+ _D28TypeInfo_E3std6system6Endian6__initZ@Base 6
+ _D28TypeInfo_OC6object9Throwable6__initZ@Base 6
+ _D28TypeInfo_PC6object9Throwable6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4Curl6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4HTTP6__initZ@Base 6
+ _D28TypeInfo_S3std3net4curl4SMTP6__initZ@Base 6
+ _D28TypeInfo_S3std4file8DirEntry6__initZ@Base 6
+ _D28TypeInfo_S3std6bigint6BigInt6__initZ@Base 6
+ _D28TypeInfo_S3std6digest2md3MD56__initZ@Base 6
+ _D28TypeInfo_S3std6getopt6Option6__initZ@Base 6
+ _D28TypeInfo_S3std6socket6Linger6__initZ@Base 6
+ _D28TypeInfo_S3std8datetime4Date6__initZ@Base 6
+ _D28TypeInfo_xC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_AC4core6thread5Fiber6__initZ@Base 6
+ _D29TypeInfo_AS3std4file8DirEntry6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlFtp6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlMsg6__initZ@Base 6
+ _D29TypeInfo_E3etc1c4curl7CurlVer6__initZ@Base 6
+ _D29TypeInfo_E3std4json9JSON_TYPE6__initZ@Base 6
+ _D29TypeInfo_E3std5stdio8LockType6__initZ@Base 6
+ _D29TypeInfo_E3std6stream7SeekPos6__initZ@Base 6
+ _D29TypeInfo_E3std7process6Config6__initZ@Base 6
+ _D29TypeInfo_E3std8datetime5Month6__initZ@Base 6
+ _D29TypeInfo_POC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_S3etc1c4curl7CURLMsg6__initZ@Base 6
+ _D29TypeInfo_S3std4json9JSONValue6__initZ@Base 6
+ _D29TypeInfo_S3std4math9IeeeFlags6__initZ@Base 6
+ _D29TypeInfo_S3std5range8NullSink6__initZ@Base 6
+ _D29TypeInfo_S3std6socket7TimeVal6__initZ@Base 6
+ _D29TypeInfo_xE3std4file8SpanMode6__initZ@Base 6
+ _D29TypeInfo_xS3std3net4curl4Curl6__initZ@Base 6
+ _D29TypeInfo_xS3std4file8DirEntry6__initZ@Base 6
+ _D29TypeInfo_xS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_AC3std6socket7Address6__initZ@Base 6
+ _D30TypeInfo_AxS3std4file8DirEntry6__initZ@Base 6
+ _D30TypeInfo_AxS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlAuth6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlForm6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlInfo6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlPoll6__initZ@Base 6
+ _D30TypeInfo_E3etc1c4curl8CurlSeek6__initZ@Base 6
+ _D30TypeInfo_E3std3xml10DecodeMode6__initZ@Base 6
+ _D30TypeInfo_E3std6socket8socket_t6__initZ@Base 6
+ _D30TypeInfo_E3std6stream8FileMode6__initZ@Base 6
+ _D30TypeInfo_E3std6traits8Variadic6__initZ@Base 6
+ _D30TypeInfo_E3std8compiler6Vendor6__initZ@Base 6
+ _D30TypeInfo_S3etc1c4zlib8z_stream6__initZ@Base 6
+ _D30TypeInfo_S3std5stdio4File4Impl6__initZ@Base 6
+ _D30TypeInfo_xAS3std4file8DirEntry6__initZ@Base 6
+ _D30TypeInfo_xAS3std6getopt6Option6__initZ@Base 6
+ _D30TypeInfo_xC3std6socket7Address6__initZ@Base 6
+ _D30TypeInfo_xS3std4json9JSONValue6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlError6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlIoCmd6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlPause6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlProto6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlProxy6__initZ@Base 6
+ _D31TypeInfo_E3etc1c4curl9CurlRedir6__initZ@Base 6
+ _D31TypeInfo_E3std4math10RealFormat6__initZ@Base 6
+ _D31TypeInfo_E3std7process8Redirect6__initZ@Base 6
+ _D31TypeInfo_S3etc1c4zlib9gz_header6__initZ@Base 6
+ _D31TypeInfo_S3std11concurrency3Tid6__initZ@Base 6
+ _D31TypeInfo_S3std3net4curl7CurlAPI6__initZ@Base 6
+ _D31TypeInfo_S3std6digest3crc5CRC326__initZ@Base 6
+ _D31TypeInfo_S3std8datetime7SysTime6__initZ@Base 6
+ _D31TypeInfo_xS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_AS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_E3std4json11JSONOptions6__initZ@Base 6
+ _D32TypeInfo_E3std4uuid4UUID7Variant6__initZ@Base 6
+ _D32TypeInfo_E3std4uuid4UUID7Version6__initZ@Base 6
+ _D32TypeInfo_E3std5ascii10LetterCase6__initZ@Base 6
+ _D32TypeInfo_E3std8datetime8PopFirst6__initZ@Base 6
+ _D32TypeInfo_PS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_PxS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_S3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D32TypeInfo_S3std3net7isemail5Token6__initZ@Base 6
+ _D32TypeInfo_S3std3uni7unicode5block6__initZ@Base 6
+ _D32TypeInfo_S3std4file11DirIterator6__initZ@Base 6
+ _D32TypeInfo_S3std5stdio10ChunksImpl6__initZ@Base 6
+ _D32TypeInfo_S3std8bitmanip8BitArray6__initZ@Base 6
+ _D32TypeInfo_S3std8bitmanip8FloatRep6__initZ@Base 6
+ _D32TypeInfo_S3std8datetime8DateTime6__initZ@Base 6
+ _D32TypeInfo_xE3std7process8Redirect6__initZ@Base 6
+ _D32TypeInfo_xPS3std5stdio4File4Impl6__initZ@Base 6
+ _D32TypeInfo_xS3std11concurrency3Tid6__initZ@Base 6
+ _D32TypeInfo_xS3std8datetime7SysTime6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlFtpSSL6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlGlobal6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlKHStat6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlKHType6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlOption6__initZ@Base 6
+ _D33TypeInfo_E3etc1c4curl10CurlUseSSL6__initZ@Base 6
+ _D33TypeInfo_E3std4zlib12HeaderFormat6__initZ@Base 6
+ _D33TypeInfo_E3std6mmfile6MmFile4Mode6__initZ@Base 6
+ _D33TypeInfo_E3std6socket10SocketType6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9AutoStart6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9DayOfWeek6__initZ@Base 6
+ _D33TypeInfo_E3std8datetime9Direction6__initZ@Base 6
+ _D33TypeInfo_E3std8encoding9AsciiChar6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_forms6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_khkey6__initZ@Base 6
+ _D33TypeInfo_S3etc1c4curl10curl_slist6__initZ@Base 6
+ _D33TypeInfo_S3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D33TypeInfo_S3std3net4curl4SMTP4Impl6__initZ@Base 6
+ _D33TypeInfo_S3std3uni13ReallocPolicy6__initZ@Base 6
+ _D33TypeInfo_S3std3uni7unicode6script6__initZ@Base 6
+ _D33TypeInfo_S3std5stdio4File7ByChunk6__initZ@Base 6
+ _D33TypeInfo_S3std8bitmanip9DoubleRep6__initZ@Base 6
+ _D33TypeInfo_S3std8datetime9StopWatch6__initZ@Base 6
+ _D33TypeInfo_S3std8datetime9TimeOfDay6__initZ@Base 6
+ _D33TypeInfo_xC3std8datetime8TimeZone6__initZ@Base 6
+ _D33TypeInfo_xS3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D33TypeInfo_xS3std4file11DirIterator6__initZ@Base 6
+ _D33TypeInfo_yC3std8datetime8TimeZone6__initZ@Base 6
+ _D34TypeInfo_AE3std8encoding9AsciiChar6__initZ@Base 6
+ _D34TypeInfo_C3std6stream11InputStream6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlCSelect6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlFormAdd6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlFtpAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlIoError6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlKHMatch6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlMOption6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlRtspReq6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlSeekPos6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlShError6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlSshAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlTlsAuth6__initZ@Base 6
+ _D34TypeInfo_E3etc1c4curl11CurlVersion6__initZ@Base 6
+ _D34TypeInfo_E3std4path13CaseSensitive6__initZ@Base 6
+ _D34TypeInfo_E3std5range12SearchPolicy6__initZ@Base 6
+ _D34TypeInfo_E3std6digest6digest5Order6__initZ@Base 6
+ _D34TypeInfo_E3std6socket11SocketFlags6__initZ@Base 6
+ _D34TypeInfo_HAyaxS3std4json9JSONValue6__initZ@Base 6
+ _D34TypeInfo_HS3std11concurrency3Tidxb6__initZ@Base 6
+ _D34TypeInfo_S3std3uni14MatcherConcept6__initZ@Base 6
+ _D34TypeInfo_S3std6socket11AddressInfo6__initZ@Base 6
+ _D34TypeInfo_xE3std6socket10SocketType6__initZ@Base 6
+ _D34TypeInfo_xHAyaS3std4json9JSONValue6__initZ@Base 6
+ _D34TypeInfo_xHS3std11concurrency3Tidb6__initZ@Base 6
+ _D34TypeInfo_xS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D34TypeInfo_xS3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D35TypeInfo_AS3std6socket11AddressInfo6__initZ@Base 6
+ _D35TypeInfo_C3std6digest6digest6Digest6__initZ@Base 6
+ _D35TypeInfo_C3std6stream12OutputStream6__initZ@Base 6
+ _D35TypeInfo_C3std8typecons10Structural6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlFileType6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlLockData6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlReadFunc6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlShOption6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlSockType6__initZ@Base 6
+ _D35TypeInfo_E3etc1c4curl12CurlTimeCond6__initZ@Base 6
+ _D35TypeInfo_E3std11concurrency7MsgType6__initZ@Base 6
+ _D35TypeInfo_E3std3net4curl4HTTP6Method6__initZ@Base 6
+ _D35TypeInfo_E3std3net7isemail8CheckDns6__initZ@Base 6
+ _D35TypeInfo_E3std5regex8internal2ir2IR6__initZ@Base 6
+ _D35TypeInfo_E3std6socket12ProtocolType6__initZ@Base 6
+ _D35TypeInfo_E3std6socket12SocketOption6__initZ@Base 6
+ _D35TypeInfo_E3std8encoding10Latin1Char6__initZ@Base 6
+ _D35TypeInfo_HAyaS3std11concurrency3Tid6__initZ@Base 6
+ _D35TypeInfo_PxS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D35TypeInfo_S3std11concurrency7Message6__initZ@Base 6
+ _D35TypeInfo_S3std3net4curl7CurlAPI3API6__initZ@Base 6
+ _D35TypeInfo_S3std4json9JSONValue5Store6__initZ@Base 6
+ _D35TypeInfo_S3std6getopt12GetoptResult6__initZ@Base 6
+ _D35TypeInfo_xPS3etc1c4curl10curl_slist6__initZ@Base 6
+ _D35TypeInfo_xS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_AE3std8encoding10Latin1Char6__initZ@Base 6
+ _D36TypeInfo_AxS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_E3etc1c4curl13CurlFtpMethod6__initZ@Base 6
+ _D36TypeInfo_E3etc1c4curl13CurlIpResolve6__initZ@Base 6
+ _D36TypeInfo_E3std3net7isemail9EmailPart6__initZ@Base 6
+ _D36TypeInfo_E3std5range14StoppingPolicy6__initZ@Base 6
+ _D36TypeInfo_E3std6socket13AddressFamily6__initZ@Base 6
+ _D36TypeInfo_FC3std3xml13ElementParserZv6__initZ@Base 6
+ _D36TypeInfo_HS3std11concurrency3TidAAya6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_certinfo6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_fileinfo6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_httppost6__initZ@Base 6
+ _D36TypeInfo_S3etc1c4curl13curl_sockaddr6__initZ@Base 6
+ _D36TypeInfo_S3std4file15DirIteratorImpl6__initZ@Base 6
+ _D36TypeInfo_S3std6getopt13configuration6__initZ@Base 6
+ _D36TypeInfo_S3std7process12ProcessPipes6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D36TypeInfo_xAS3std6socket11AddressInfo6__initZ@Base 6
+ _D36TypeInfo_xE3std11concurrency7MsgType6__initZ@Base 6
+ _D36TypeInfo_xE3std3net4curl4HTTP6Method6__initZ@Base 6
+ _D36TypeInfo_xE3std6socket12ProtocolType6__initZ@Base 6
+ _D36TypeInfo_xS3std11concurrency7Message6__initZ@Base 6
+ _D37TypeInfo_C3std11concurrency9Scheduler6__initZ@Base 6
+ _D37TypeInfo_DFC3std3xml13ElementParserZv6__initZ@Base 6
+ _D37TypeInfo_E3etc1c4curl14CurlLockAccess6__initZ@Base 6
+ _D37TypeInfo_E3etc1c4curl14CurlSslVersion6__initZ@Base 6
+ _D37TypeInfo_E3std3uni17NormalizationForm6__initZ@Base 6
+ _D37TypeInfo_E3std3zip17CompressionMethod6__initZ@Base 6
+ _D37TypeInfo_E3std4json16JSONFloatLiteral6__initZ@Base 6
+ _D37TypeInfo_E3std6socket14SocketShutdown6__initZ@Base 6
+ _D37TypeInfo_E3std8typecons12TypeModifier6__initZ@Base 6
+ _D37TypeInfo_HAyaC3std3zip13ArchiveMember6__initZ@Base 6
+ _D37TypeInfo_S3etc1c7sqlite311sqlite3_vfs6__initZ@Base 6
+ _D37TypeInfo_S3std3net4curl12AutoProtocol6__initZ@Base 6
+ _D37TypeInfo_S3std3uni17CodepointInterval6__initZ@Base 6
+ _D37TypeInfo_S3std7numeric5bsr64FmZ5Ulong6__initZ@Base 6
+ _D37TypeInfo_S3std9container5dlist6DRange6__initZ@Base 6
+ _D37TypeInfo_xC3std11parallelism8TaskPool6__initZ@Base 6
+ _D37TypeInfo_xE3std6socket13AddressFamily6__initZ@Base 6
+ _D37TypeInfo_xS3std4file15DirIteratorImpl6__initZ@Base 6
+ _D37TypeInfo_xS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_AS3std3uni17CodepointInterval6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlClosePolicy6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlFnMAtchFunc6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlHttpVersion6__initZ@Base 6
+ _D38TypeInfo_E3etc1c4curl15CurlNetRcOption6__initZ@Base 6
+ _D38TypeInfo_E3std3net7isemail10AsciiToken6__initZ@Base 6
+ _D38TypeInfo_E3std5stdio4File11Orientation6__initZ@Base 6
+ _D38TypeInfo_PxS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_S3etc1c7sqlite312sqlite3_file6__initZ@Base 6
+ _D38TypeInfo_S3etc1c7sqlite312sqlite3_vtab6__initZ@Base 6
+ _D38TypeInfo_S3std6digest6ripemd9RIPEMD1606__initZ@Base 6
+ _D38TypeInfo_xPS4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D38TypeInfo_xS3std3uni17CodepointInterval6__initZ@Base 6
+ _D399TypeInfo_S3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlCallbackInfo6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlChunkBgnFunc6__initZ@Base 6
+ _D39TypeInfo_E3etc1c4curl16CurlChunkEndFunc6__initZ@Base 6
+ _D39TypeInfo_E3std11concurrency10OnCrowding6__initZ@Base 6
+ _D39TypeInfo_E3std11parallelism10TaskStatus6__initZ@Base 6
+ _D39TypeInfo_E3std5range17TransverseOptions6__initZ@Base 6
+ _D39TypeInfo_E3std6socket16AddressInfoFlags6__initZ@Base 6
+ _D39TypeInfo_HE3std6format6MangleC8TypeInfo6__initZ@Base 6
+ _D39TypeInfo_S3std11concurrency10ThreadInfo6__initZ@Base 6
+ _D39TypeInfo_S3std3net7isemail11EmailStatus6__initZ@Base 6
+ _D39TypeInfo_S3std5stdio17LockingTextReader6__initZ@Base 6
+ _D39TypeInfo_S3std9container5dlist8BaseNode6__initZ@Base 6
+ _D3etc1c4curl10CurlGlobal6__initZ@Base 6
+ _D3etc1c4curl10CurlOption6__initZ@Base 6
+ _D3etc1c4curl10curl_forms6__initZ@Base 6
+ _D3etc1c4curl10curl_khkey6__initZ@Base 6
+ _D3etc1c4curl10curl_slist6__initZ@Base 6
+ _D3etc1c4curl11CurlCSelect6__initZ@Base 6
+ _D3etc1c4curl11CurlMOption6__initZ@Base 6
+ _D3etc1c4curl11CurlSshAuth6__initZ@Base 6
+ _D3etc1c4curl11CurlVersion6__initZ@Base 6
+ _D3etc1c4curl12CurlReadFunc6__initZ@Base 6
+ _D3etc1c4curl12__ModuleInfoZ@Base 6
+ _D3etc1c4curl13curl_certinfo6__initZ@Base 6
+ _D3etc1c4curl13curl_fileinfo6__initZ@Base 6
+ _D3etc1c4curl13curl_httppost6__initZ@Base 6
+ _D3etc1c4curl13curl_sockaddr6__initZ@Base 6
+ _D3etc1c4curl18CurlFInfoFlagKnown6__initZ@Base 6
+ _D3etc1c4curl3_N26__initZ@Base 6
+ _D3etc1c4curl4_N286__initZ@Base 6
+ _D3etc1c4curl4_N316__initZ@Base 6
+ _D3etc1c4curl5CurlM6__initZ@Base 6
+ _D3etc1c4curl7CURLMsg6__initZ@Base 6
+ _D3etc1c4curl9CurlPause6__initZ@Base 6
+ _D3etc1c4curl9CurlProto6__initZ@Base 6
+ _D3etc1c4zlib12__ModuleInfoZ@Base 6
+ _D3etc1c4zlib8z_stream6__initZ@Base 6
+ _D3etc1c4zlib9gz_header6__initZ@Base 6
+ _D3etc1c7sqlite311sqlite3_vfs6__initZ@Base 6
+ _D3etc1c7sqlite312__ModuleInfoZ@Base 6
+ _D3etc1c7sqlite312sqlite3_file6__initZ@Base 6
+ _D3etc1c7sqlite312sqlite3_vtab6__initZ@Base 6
+ _D3etc1c7sqlite314sqlite3_module6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info11__xopEqualsFKxS3etc1c7sqlite318sqlite3_index_infoKxS3etc1c7sqlite318sqlite3_index_infoZb@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info6__initZ@Base 6
+ _D3etc1c7sqlite318sqlite3_index_info9__xtoHashFNbNeKxS3etc1c7sqlite318sqlite3_index_infoZk@Base 6
+ _D3etc1c7sqlite318sqlite3_io_methods6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_mem_methods6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_pcache_page6__initZ@Base 6
+ _D3etc1c7sqlite319sqlite3_vtab_cursor6__initZ@Base 6
+ _D3etc1c7sqlite321sqlite3_mutex_methods6__initZ@Base 6
+ _D3etc1c7sqlite322sqlite3_pcache_methods6__initZ@Base 6
+ _D3etc1c7sqlite322sqlite3_rtree_geometry6__initZ@Base 6
+ _D3etc1c7sqlite323sqlite3_pcache_methods26__initZ@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info11__xopEqualsFKxS3etc1c7sqlite324sqlite3_rtree_query_infoKxS3etc1c7sqlite324sqlite3_rtree_query_infoZb@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info6__initZ@Base 6
+ _D3etc1c7sqlite324sqlite3_rtree_query_info9__xtoHashFNbNeKxS3etc1c7sqlite324sqlite3_rtree_query_infoZk@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ11initializedAk@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ4memoAS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value11__xopEqualsFKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZb@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value6__initZ@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value9__xtoHashFNbNeKxS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZk@Base 6
+ _D3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std10functional11_ctfeSkipOpFKAyaZk@Base 6
+ _D3std10functional12__ModuleInfoZ@Base 6
+ _D3std10functional13_ctfeSkipNameFKAyaAyaZk@Base 6
+ _D3std10functional15_ctfeMatchUnaryFAyaAyaZk@Base 6
+ _D3std10functional16_ctfeMatchBinaryFAyaAyaAyaZk@Base 6
+ _D3std10functional16_ctfeSkipIntegerFKAyaZk@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTiTiZ6safeOpFNaNbNiNfKiKiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTkTiZ6safeOpFNaNbNiNfKkKiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTkTkZ6safeOpFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ15__T6safeOpTlTkZ6safeOpFNaNbNiNfKlKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTkTykZ6safeOpFNaNbNiNfKkKykZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTyiTkZ6safeOpFNaNbNiNfKyiKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ16__T6safeOpTykTkZ6safeOpFNaNbNiNfKykKkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T6safeOpTykTykZ6safeOpFNaNbNiNfKykKykZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T8unsafeOpTkTiZ8unsafeOpFNaNbNiNfkiZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ17__T8unsafeOpTlTkZ8unsafeOpFNaNbNiNflkZb@Base 6
+ _D3std10functional20__T6safeOpVAyaa1_3cZ18__T8unsafeOpTyiTkZ8unsafeOpFNaNbNiNfyikZb@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfS3std3uni17CodepointIntervalZk@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfS3std3uni17CodepointIntervalZk@Base 6
+ _D3std10functional37__T8unaryFunVAyaa4_74727565VAyaa1_61Z15__T8unaryFunTwZ8unaryFunFNaNbNiNfKwZb@Base 6
+ _D3std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z55__T8unaryFunTyS3std8internal14unicode_tables9CompEntryZ8unaryFunFNaNbNiNfKyS3std8internal14unicode_tables9CompEntryZyw@Base 6
+ _D3std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z62__T8unaryFunTyS3std8internal14unicode_tables15UnicodePropertyZ8unaryFunFNaNbNiNfKyS3std8internal14unicode_tables15UnicodePropertyZyAa@Base 6
+ _D3std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z19__T9binaryFunTxkTkZ9binaryFunFNaNbNiNfKxkKkZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61202b2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZk@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTiZ9binaryFunFNaNbNiNfKkKiZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTwZ9binaryFunFNaNbNiNfKwKwZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTywTwZ9binaryFunFNaNbNiNfKywKwZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z20__T9binaryFunTxhTxhZ9binaryFunFNaNbNiNfKxhKxhZb@Base 6
+ _D3std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTAyaTAyaZ9binaryFunFNaNbNiNfKAyaKAyaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203c3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTkTyiZ9binaryFunFNaNbNiNfKkKyiZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z144__T9binaryFunTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ9binaryFunFNaNbNiNfKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunThThZ9binaryFunFNaNbNiNfKhKhZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTkTkZ9binaryFunFNaNbNiNfKkKkZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTaZ9binaryFunFNaNbNiNfKwKaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTaZ9binaryFunFNaNbNiNfwKaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z18__T9binaryFunTwTwZ9binaryFunFNaNbNiNfwwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTyhTwZ9binaryFunFNaNbNiNfKyhKwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z19__T9binaryFunTyhTwZ9binaryFunFNaNbNiNfKyhwZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTAyaTAyaZ9binaryFunFNaNbNiNfKAyaKAyaZb@Base 6
+ _D3std10functional51__T9binaryFunVAyaa6_61203d3d2062VAyaa1_61VAyaa1_62Z22__T9binaryFunTyAaTAyaZ9binaryFunFNaNbNiNfKyAaKAyaZb@Base 6
+ _D3std10functional52__T8unaryFunVAyaa11_6120213d20612e4f70656eVAyaa1_61Z74__T8unaryFunTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ8unaryFunFNaNbNiNfKE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std10functional52__T8unaryFunVAyaa11_615b305d203e2030783830VAyaa1_61Z42__T8unaryFunTS3std3uni17CodepointIntervalZ8unaryFunFNaNbNiNfKS3std3uni17CodepointIntervalZb@Base 6
+ _D3std10functional54__T8unaryFunVAyaa12_61203d3d20612e556e696f6eVAyaa1_61Z74__T8unaryFunTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ8unaryFunFNaNbNiNfKE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z59__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTiZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKiZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10LeapSecondTyiZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10LeapSecondKyiZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTyiZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKyiZb@Base 6
+ _D3std10functional62__T9binaryFunVAyaa11_62203c20612e74696d6554VAyaa1_61VAyaa1_62Z60__T9binaryFunTyS3std8datetime13PosixTimeZone10TransitionTylZ9binaryFunFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionKylZb@Base 6
+ _D3std10functional70__T9binaryFunVAyaa15_612e6e616d65203c20622e6e616d65VAyaa1_61VAyaa1_62Z86__T9binaryFunTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ9binaryFunFNaNbNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z106__T9binaryFunTS3std8datetime13PosixTimeZone14TempTransitionTS3std8datetime13PosixTimeZone14TempTransitionZ9binaryFunFNaNbNiNfKS3std8datetime13PosixTimeZone14TempTransitionKS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z98__T9binaryFunTS3std8datetime13PosixTimeZone10LeapSecondTS3std8datetime13PosixTimeZone10LeapSecondZ9binaryFunFNaNbNiNfKS3std8datetime13PosixTimeZone10LeapSecondKS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std11concurrency10MessageBox10setMaxMsgsMFkPFS3std11concurrency3TidZbZv@Base 6
+ _D3std11concurrency10MessageBox12isControlMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox13isLinkDeadMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox13isPriorityMsgMFNaKS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency10MessageBox14updateMsgCountMFZv@Base 6
+ _D3std11concurrency10MessageBox160__T3getTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3getMFMDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbMDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency10MessageBox181__T3getTS4core4time8DurationTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3getMFMS4core4time8DurationMDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbMDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency10MessageBox36__T3getTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ3getMFMDFNaNbNiAyhZvMDFNaNbNiNfbZvZb@Base 6
+ _D3std11concurrency10MessageBox3putMFKS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency10MessageBox5closeMFZ13onLinkDeadMsgMFKS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency10MessageBox5closeMFZv@Base 6
+ _D3std11concurrency10MessageBox6__ctorMFNeZC3std11concurrency10MessageBox@Base 6
+ _D3std11concurrency10MessageBox6__initZ@Base 6
+ _D3std11concurrency10MessageBox6__vtblZ@Base 6
+ _D3std11concurrency10MessageBox7__ClassZ@Base 6
+ _D3std11concurrency10MessageBox8isClosedMFNdZb@Base 6
+ _D3std11concurrency10MessageBox8isClosedMxFNdZb@Base 6
+ _D3std11concurrency10MessageBox8mboxFullMFZb@Base 6
+ _D3std11concurrency10ThreadInfo11__xopEqualsFKxS3std11concurrency10ThreadInfoKxS3std11concurrency10ThreadInfoZb@Base 6
+ _D3std11concurrency10ThreadInfo6__initZ@Base 6
+ _D3std11concurrency10ThreadInfo7cleanupMFZv@Base 6
+ _D3std11concurrency10ThreadInfo8thisInfoFNbNcNdNiNfZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency10ThreadInfo8thisInfoFNbNcNdZ3valS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency10ThreadInfo9__xtoHashFNbNeKxS3std11concurrency10ThreadInfoZk@Base 6
+ _D3std11concurrency10namesByTidHS3std11concurrency3TidAAya@Base 6
+ _D3std11concurrency10unregisterFAyaZb@Base 6
+ _D3std11concurrency11IsGenerator11__InterfaceZ@Base 6
+ _D3std11concurrency11MailboxFull6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency11MailboxFull@Base 6
+ _D3std11concurrency11MailboxFull6__initZ@Base 6
+ _D3std11concurrency11MailboxFull6__vtblZ@Base 6
+ _D3std11concurrency11MailboxFull7__ClassZ@Base 6
+ _D3std11concurrency12__ModuleInfoZ@Base 6
+ _D3std11concurrency12_staticDtor1FZv@Base 6
+ _D3std11concurrency12initOnceLockFNdZ4lockC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12initOnceLockFNdZC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12registryLockC4core4sync5mutex5Mutex@Base 6
+ _D3std11concurrency12unregisterMeFZv@Base 6
+ _D3std11concurrency13__T4sendTAyhZ4sendFS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency14FiberScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition13switchContextMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition4waitMFNbS4core4time8DurationZb@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition4waitMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__ctorMFNbC4core4sync5mutex5MutexZC3std11concurrency14FiberScheduler14FiberCondition@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition6notifyMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition7__ClassZ@Base 6
+ _D3std11concurrency14FiberScheduler14FiberCondition9notifyAllMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler5spawnMFNbDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler5startMFDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler5yieldMFNbZv@Base 6
+ _D3std11concurrency14FiberScheduler6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler6createMFNbDFZvZv@Base 6
+ _D3std11concurrency14FiberScheduler7__ClassZ@Base 6
+ _D3std11concurrency14FiberScheduler8dispatchMFZv@Base 6
+ _D3std11concurrency14FiberScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__ctorMFNbDFZvZC3std11concurrency14FiberScheduler9InfoFiber@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__initZ@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber6__vtblZ@Base 6
+ _D3std11concurrency14FiberScheduler9InfoFiber7__ClassZ@Base 6
+ _D3std11concurrency14LinkTerminated6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency14LinkTerminated@Base 6
+ _D3std11concurrency14LinkTerminated6__initZ@Base 6
+ _D3std11concurrency14LinkTerminated6__vtblZ@Base 6
+ _D3std11concurrency14LinkTerminated7__ClassZ@Base 6
+ _D3std11concurrency14__T5_sendTAyhZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency14__T5_sendTAyhZ5_sendFS3std11concurrency3TidAyhZv@Base 6
+ _D3std11concurrency15MessageMismatch6__ctorMFAyaZC3std11concurrency15MessageMismatch@Base 6
+ _D3std11concurrency15MessageMismatch6__initZ@Base 6
+ _D3std11concurrency15MessageMismatch6__vtblZ@Base 6
+ _D3std11concurrency15MessageMismatch7__ClassZ@Base 6
+ _D3std11concurrency15OwnerTerminated6__ctorMFS3std11concurrency3TidAyaZC3std11concurrency15OwnerTerminated@Base 6
+ _D3std11concurrency15OwnerTerminated6__initZ@Base 6
+ _D3std11concurrency15OwnerTerminated6__vtblZ@Base 6
+ _D3std11concurrency15OwnerTerminated7__ClassZ@Base 6
+ _D3std11concurrency15ThreadScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D3std11concurrency15ThreadScheduler5spawnMFDFZvZv@Base 6
+ _D3std11concurrency15ThreadScheduler5startMFDFZvZv@Base 6
+ _D3std11concurrency15ThreadScheduler5yieldMFNbZv@Base 6
+ _D3std11concurrency15ThreadScheduler6__initZ@Base 6
+ _D3std11concurrency15ThreadScheduler6__vtblZ@Base 6
+ _D3std11concurrency15ThreadScheduler7__ClassZ@Base 6
+ _D3std11concurrency15ThreadScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency15onCrowdingBlockFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency15onCrowdingThrowFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency164__T7receiveTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ7receiveFDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZv@Base 6
+ _D3std11concurrency165__T8checkopsTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ8checkopsFNaNbNiNfDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZv@Base 6
+ _D3std11concurrency16onCrowdingIgnoreFS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency172__T14receiveTimeoutTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ14receiveTimeoutFS4core4time8DurationDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency17setMaxMailboxSizeFS3std11concurrency3TidkE3std11concurrency10OnCrowdingZv@Base 6
+ _D3std11concurrency17setMaxMailboxSizeFS3std11concurrency3TidkPFS3std11concurrency3TidZbZv@Base 6
+ _D3std11concurrency18_sharedStaticCtor8FZv@Base 6
+ _D3std11concurrency19TidMissingException6__ctorMFAyaAyakZC3std11concurrency19TidMissingException@Base 6
+ _D3std11concurrency19TidMissingException6__initZ@Base 6
+ _D3std11concurrency19TidMissingException6__vtblZ@Base 6
+ _D3std11concurrency19TidMissingException7__ClassZ@Base 6
+ _D3std11concurrency24PriorityMessageException11__fieldDtorMFZv@Base 6
+ _D3std11concurrency24PriorityMessageException6__ctorMFS3std7variant18__T8VariantNVki16Z8VariantNZC3std11concurrency24PriorityMessageException@Base 6.2.1-1ubuntu2
+ _D3std11concurrency24PriorityMessageException6__initZ@Base 6
+ _D3std11concurrency24PriorityMessageException6__vtblZ@Base 6
+ _D3std11concurrency24PriorityMessageException7__ClassZ@Base 6
+ _D3std11concurrency33__T5_sendTS3std11concurrency3TidZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidS3std11concurrency3TidZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFNaNbNiNfKS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4ListZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFNaNbNiNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List3putMFS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node11__fieldDtorMFZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node11__xopEqualsFKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node15__fieldPostblitMFZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__ctorMFNcS3std11concurrency7MessageZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node8opAssignMFNcNjS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node9__xtoHashFNbNeKxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZk@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5frontMFNaNcNdNfZS3std11concurrency7Message@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range5frontMFNdS3std11concurrency7MessageZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__ctorMFNaNbNcNiNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range8popFrontMFNaNfZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5clearMFNaNbNiNfZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7newNodeMFS3std11concurrency7MessageZPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7opSliceMFNaNbNiZS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7sm_headOPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List7sm_lockOS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock4lockMOFNbZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6__initZ@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6unlockMOFNaNbNiZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8freeNodeMFPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZv@Base 6
+ _D3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8removeAtMFS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5RangeZv@Base 6
+ _D3std11concurrency3Tid11__xopEqualsFKxS3std11concurrency3TidKxS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency3Tid6__ctorMFNcNfC3std11concurrency10MessageBoxZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency3Tid6__initZ@Base 6
+ _D3std11concurrency3Tid8toStringMFMDFAxaZvZv@Base 6
+ _D3std11concurrency3Tid9__xtoHashFNbNeKxS3std11concurrency3TidZk@Base 6
+ _D3std11concurrency40__T7receiveTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ7receiveFDFNaNbNiAyhZvDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency41__T8checkopsTDFNaNbNiAyhZvTDFNaNbNiNfbZvZ8checkopsFNaNbNiNfDFNaNbNiAyhZvDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvC4core4sync5mutex5MutexZ4flagOb@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvC4core4sync5mutex5MutexZPv@Base 6
+ _D3std11concurrency49__T8initOnceS33_D3std3net4curl7CurlAPI7_handlePvZ8initOnceFNcLPvZPv@Base 6
+ _D3std11concurrency5yieldFNbZv@Base 6
+ _D3std11concurrency6locateFAyaZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency7Message11__fieldDtorMFZv@Base 6
+ _D3std11concurrency7Message11__xopEqualsFKxS3std11concurrency7MessageKxS3std11concurrency7MessageZb@Base 6
+ _D3std11concurrency7Message15__T6__ctorTAyhZ6__ctorMFNcE3std11concurrency7MsgTypeAyhZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message15__fieldPostblitMFZv@Base 6
+ _D3std11concurrency7Message18__T10convertsToTbZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message20__T10convertsToTAyhZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message22__T3mapTDFNaNbNiAyhZvZ3mapMFDFNaNbNiAyhZvZv@Base 6
+ _D3std11concurrency7Message22__T3mapTDFNaNbNiNfbZvZ3mapMFDFNaNbNiNfbZvZv@Base 6
+ _D3std11concurrency7Message27__T3getTC6object9ThrowableZ3getMFNdZC6object9Throwable@Base 6
+ _D3std11concurrency7Message28__T3getTOC6object9ThrowableZ3getMFNdZOC6object9Throwable@Base 6
+ _D3std11concurrency7Message31__T3getTS3std11concurrency3TidZ3getMFNdZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency7Message34__T6__ctorTS3std11concurrency3TidZ6__ctorMFNcE3std11concurrency7MsgTypeS3std11concurrency3TidZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message35__T10convertsToTC6object9ThrowableZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message36__T10convertsToTOC6object9ThrowableZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message39__T10convertsToTS3std11concurrency3TidZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message46__T6__ctorTC3std11concurrency14LinkTerminatedZ6__ctorMFNcE3std11concurrency7MsgTypeC3std11concurrency14LinkTerminatedZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message47__T6__ctorTC3std11concurrency15OwnerTerminatedZ6__ctorMFNcE3std11concurrency7MsgTypeC3std11concurrency15OwnerTerminatedZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message6__initZ@Base 6
+ _D3std11concurrency7Message83__T3mapTDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZ3mapMFDFS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency7Message85__T3mapTDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbZ3mapMFDFS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZbZb@Base 6
+ _D3std11concurrency7Message85__T6__ctorTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ6__ctorMFNcE3std11concurrency7MsgTypeS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message88__T10convertsToTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message8opAssignMFNcNjS3std11concurrency7MessageZS3std11concurrency7Message@Base 6
+ _D3std11concurrency7Message90__T10convertsToTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ10convertsToMFNdZb@Base 6
+ _D3std11concurrency7Message9__xtoHashFNbNeKxS3std11concurrency7MessageZk@Base 6
+ _D3std11concurrency7thisTidFNdNfZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency83__T4sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ4sendFS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency84__T5_sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5_sendFE3std11concurrency7MsgTypeS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency84__T5_sendTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5_sendFS3std11concurrency3TidS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZv@Base 6
+ _D3std11concurrency8ownerTidFNdZS3std11concurrency3Tid@Base 6
+ _D3std11concurrency8registerFAyaS3std11concurrency3TidZb@Base 6
+ _D3std11concurrency8thisInfoFNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _D3std11concurrency9Scheduler11__InterfaceZ@Base 6
+ _D3std11concurrency9schedulerC3std11concurrency9Scheduler@Base 6
+ _D3std11concurrency9tidByNameHAyaS3std11concurrency3Tid@Base 6
+ _D3std11mathspecial11logmdigammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial12__ModuleInfoZ@Base 6
+ _D3std11mathspecial14betaIncompleteFNaNbNiNfeeeZe@Base 6
+ _D3std11mathspecial15gammaIncompleteFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial18logmdigammaInverseFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial18normalDistributionFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial20gammaIncompleteComplFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial21betaIncompleteInverseFNaNbNiNfeeeZe@Base 6
+ _D3std11mathspecial25normalDistributionInverseFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial27gammaIncompleteComplInverseFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial3erfFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial4betaFNaNbNiNfeeZe@Base 6
+ _D3std11mathspecial4erfcFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial5gammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial7digammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial8logGammaFNaNbNiNfeZe@Base 6
+ _D3std11mathspecial8sgnGammaFNaNbNiNfeZe@Base 6
+ _D3std11parallelism10addToChainFNaNbC6object9ThrowableKC6object9ThrowableKC6object9ThrowableZv@Base 6
+ _D3std11parallelism10foreachErrFZv@Base 6
+ _D3std11parallelism12AbstractTask11__xopEqualsFKxS3std11parallelism12AbstractTaskKxS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism12AbstractTask3jobMFZv@Base 6
+ _D3std11parallelism12AbstractTask4doneMFNdZb@Base 6
+ _D3std11parallelism12AbstractTask6__initZ@Base 6
+ _D3std11parallelism12AbstractTask9__xtoHashFNbNeKxS3std11parallelism12AbstractTaskZk@Base 6
+ _D3std11parallelism12__ModuleInfoZ@Base 6
+ _D3std11parallelism13__T3runTDFZvZ3runFDFZvZv@Base 6
+ _D3std11parallelism16submitAndExecuteFC3std11parallelism8TaskPoolMDFZvZv@Base 6
+ _D3std11parallelism17ParallelismThread6__ctorMFDFZvZC3std11parallelism17ParallelismThread@Base 6
+ _D3std11parallelism17ParallelismThread6__initZ@Base 6
+ _D3std11parallelism17ParallelismThread6__vtblZ@Base 6
+ _D3std11parallelism17ParallelismThread7__ClassZ@Base 6
+ _D3std11parallelism17findLastExceptionFNaNbC6object9ThrowableZC6object9Throwable@Base 6
+ _D3std11parallelism18_sharedStaticCtor2FZv@Base 6
+ _D3std11parallelism18_sharedStaticCtor9FZv@Base 6
+ _D3std11parallelism18_sharedStaticDtor7FZv@Base 6
+ _D3std11parallelism18defaultPoolThreadsFNdNeZk@Base 6
+ _D3std11parallelism18defaultPoolThreadsFNdNekZv@Base 6
+ _D3std11parallelism19_defaultPoolThreadsOk@Base 6
+ _D3std11parallelism20ParallelForeachError6__ctorMFZC3std11parallelism20ParallelForeachError@Base 6
+ _D3std11parallelism20ParallelForeachError6__initZ@Base 6
+ _D3std11parallelism20ParallelForeachError6__vtblZ@Base 6
+ _D3std11parallelism20ParallelForeachError7__ClassZ@Base 6
+ _D3std11parallelism21__T10scopedTaskTDFZvZ10scopedTaskFNfMDFZvZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism22__T14atomicSetUbyteThZ14atomicSetUbyteFNaNbNiKhhZv@Base 6
+ _D3std11parallelism23__T15atomicReadUbyteThZ15atomicReadUbyteFNaNbNiKhZh@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task10yieldForceMFNcNdNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task11__xopEqualsFKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZb@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task11enforcePoolMFNaNfZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task18executeInNewThreadMFNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task18executeInNewThreadMFNeiZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task4doneMFNdNeZb@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task4implFPvZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__ctorMFNaNbNcNiNfDFZvZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__dtorMFNfZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__initZ@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task7basePtrMFNaNbNdNiNfZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task8opAssignMFNfS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9__xtoHashFNbNeKxS3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4TaskZk@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9spinForceMFNcNdNeZv@Base 6
+ _D3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task9workForceMFNcNdNeZv@Base 6
+ _D3std11parallelism58__T14atomicCasUbyteTE3std11parallelism8TaskPool9PoolStateZ14atomicCasUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D3std11parallelism58__T14atomicSetUbyteTE3std11parallelism8TaskPool9PoolStateZ14atomicSetUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZv@Base 6
+ _D3std11parallelism59__T15atomicReadUbyteTE3std11parallelism8TaskPool9PoolStateZ15atomicReadUbyteFNaNbNiKE3std11parallelism8TaskPool9PoolStateZh@Base 6
+ _D3std11parallelism8TaskPool10deleteItemMFPS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism8TaskPool10waiterLockMFZv@Base 6
+ _D3std11parallelism8TaskPool11abstractPutMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool11queueUnlockMFZv@Base 6
+ _D3std11parallelism8TaskPool11threadIndexk@Base 6
+ _D3std11parallelism8TaskPool11workerIndexMxFNbNdNfZk@Base 6
+ _D3std11parallelism8TaskPool12doSingleTaskMFZv@Base 6
+ _D3std11parallelism8TaskPool12waiterUnlockMFZv@Base 6
+ _D3std11parallelism8TaskPool13notifyWaitersMFZv@Base 6
+ _D3std11parallelism8TaskPool13startWorkLoopMFZv@Base 6
+ _D3std11parallelism8TaskPool15executeWorkLoopMFZv@Base 6
+ _D3std11parallelism8TaskPool16deleteItemNoSyncMFPS3std11parallelism12AbstractTaskZb@Base 6
+ _D3std11parallelism8TaskPool16tryDeleteExecuteMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool17abstractPutNoSyncMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool17nextInstanceIndexk@Base 6
+ _D3std11parallelism8TaskPool19defaultWorkUnitSizeMxFNaNbNfkZk@Base 6
+ _D3std11parallelism8TaskPool19waitUntilCompletionMFZv@Base 6
+ _D3std11parallelism8TaskPool22abstractPutGroupNoSyncMFPS3std11parallelism12AbstractTaskPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool3popMFZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism8TaskPool4sizeMxFNaNbNdNfZk@Base 6
+ _D3std11parallelism8TaskPool4stopMFNeZv@Base 6
+ _D3std11parallelism8TaskPool4waitMFZv@Base 6
+ _D3std11parallelism8TaskPool5doJobMFPS3std11parallelism12AbstractTaskZv@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFNeZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFNekZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__ctorMFPS3std11parallelism12AbstractTaskiZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8TaskPool6__initZ@Base 6
+ _D3std11parallelism8TaskPool6__vtblZ@Base 6
+ _D3std11parallelism8TaskPool6finishMFNebZv@Base 6
+ _D3std11parallelism8TaskPool6notifyMFZv@Base 6
+ _D3std11parallelism8TaskPool7__ClassZ@Base 6
+ _D3std11parallelism8TaskPool8isDaemonMFNdNeZb@Base 6
+ _D3std11parallelism8TaskPool8isDaemonMFNdNebZv@Base 6
+ _D3std11parallelism8TaskPool8priorityMFNdNeZi@Base 6
+ _D3std11parallelism8TaskPool8priorityMFNdNeiZv@Base 6
+ _D3std11parallelism8TaskPool9notifyAllMFZv@Base 6
+ _D3std11parallelism8TaskPool9popNoSyncMFZPS3std11parallelism12AbstractTask@Base 6
+ _D3std11parallelism8TaskPool9queueLockMFZv@Base 6
+ _D3std11parallelism8taskPoolFNdNeZ11initializedb@Base 6
+ _D3std11parallelism8taskPoolFNdNeZ4poolC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism8taskPoolFNdNeZC3std11parallelism8TaskPool@Base 6
+ _D3std11parallelism9totalCPUsyk@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger10logMsgPartMFNfAxaZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11__fieldDtorMFNeZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11beginLogMsgMFNfAyaiAyaAyaAyaE3std12experimental6logger4core8LogLevelS3std11concurrency3TidS3std8datetime7SysTimeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11getFilenameMFZAya@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger12finishLogMsgMFNfZv@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger4fileMFNdNfZS3std5stdio4File@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__ctorMFNfS3std5stdio4FilexE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__ctorMFNfxAyaxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__initZ@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger6__vtblZ@Base 6
+ _D3std12experimental6logger10filelogger10FileLogger7__ClassZ@Base 6
+ _D3std12experimental6logger10filelogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger11writeLogMsgMFNiNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10nulllogger10NullLogger@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__initZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger6__vtblZ@Base 6
+ _D3std12experimental6logger10nulllogger10NullLogger7__ClassZ@Base 6
+ _D3std12experimental6logger10nulllogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger12insertLoggerMFNfAyaC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger12removeLoggerMFNfxAaZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger11multilogger11MultiLogger@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__initZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger6__vtblZ@Base 6
+ _D3std12experimental6logger11multilogger11MultiLogger7__ClassZ@Base 6
+ _D3std12experimental6logger11multilogger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry11__xopEqualsFKxS3std12experimental6logger11multilogger16MultiLoggerEntryKxS3std12experimental6logger11multilogger16MultiLoggerEntryZb@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D3std12experimental6logger11multilogger16MultiLoggerEntry9__xtoHashFNbNeKxS3std12experimental6logger11multilogger16MultiLoggerEntryZk@Base 6
+ _D3std12experimental6logger12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger4core10TestLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core10TestLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core10TestLogger@Base 6
+ _D3std12experimental6logger4core10TestLogger6__initZ@Base 6
+ _D3std12experimental6logger4core10TestLogger6__vtblZ@Base 6
+ _D3std12experimental6logger4core10TestLogger7__ClassZ@Base 6
+ _D3std12experimental6logger4core12__ModuleInfoZ@Base 6
+ _D3std12experimental6logger4core14globalLogLevelFNdNfE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core14globalLogLevelFNdNiNfZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core15stdSharedLoggerOC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger11writeLogMsgMFNfKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__ctorMFNfxE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core16StdForwardLogger@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__initZ@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger6__vtblZ@Base 6
+ _D3std12experimental6logger4core16StdForwardLogger7__ClassZ@Base 6
+ _D3std12experimental6logger4core17stdThreadLocalLogFNdNfC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core17stdThreadLocalLogFNdNfZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core18_sharedStaticCtor1FZv@Base 6
+ _D3std12experimental6logger4core20stdSharedLoggerMutexC4core4sync5mutex5Mutex@Base 6
+ _D3std12experimental6logger4core21stdLoggerThreadLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core21stdThreadLocalLogImplFNdNeZ7_bufferG112h@Base 6.2.1-1ubuntu2
+ _D3std12experimental6logger4core21stdThreadLocalLogImplFNdNeZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core22__T16isLoggingEnabledZ16isLoggingEnabledFNaNfE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelLbZb@Base 6
+ _D3std12experimental6logger4core22stdSharedDefaultLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core23defaultSharedLoggerImplFNdNeZ7_bufferG132h@Base 6.2.1-1ubuntu2
+ _D3std12experimental6logger4core23defaultSharedLoggerImplFNdNeZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core23stdLoggerGlobalLogLevelOE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core28stdLoggerDefaultThreadLoggerC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core58__T11trustedLoadTE3std12experimental6logger4core8LogLevelZ11trustedLoadFNaNbNiNeKOE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core59__T11trustedLoadTxE3std12experimental6logger4core8LogLevelZ11trustedLoadFNaNbNiNeKOxE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core59__T12trustedStoreTE3std12experimental6logger4core8LogLevelZ12trustedStoreFNaNbNiNeKOE3std12experimental6logger4core8LogLevelKE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core60__T18systimeToISOStringTS3std5stdio4File17LockingTextWriterZ18systimeToISOStringFNfS3std5stdio4File17LockingTextWriterKxS3std8datetime7SysTimeZv@Base 6
+ _D3std12experimental6logger4core6Logger10forwardMsgMFNeKS3std12experimental6logger4core6Logger8LogEntryZv@Base 6
+ _D3std12experimental6logger4core6Logger10logMsgPartMFNfAxaZv@Base 6
+ _D3std12experimental6logger4core6Logger11beginLogMsgMFNfAyaiAyaAyaAyaE3std12experimental6logger4core8LogLevelS3std11concurrency3TidS3std8datetime7SysTimeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core6Logger12fatalHandlerMFNdNiNfDFNfZvZv@Base 6
+ _D3std12experimental6logger4core6Logger12fatalHandlerMFNdNiNfZDFZv@Base 6
+ _D3std12experimental6logger4core6Logger12finishLogMsgMFNfZv@Base 6
+ _D3std12experimental6logger4core6Logger6__ctorMFNfE3std12experimental6logger4core8LogLevelZ9__lambda3FNbNeZC4core4sync5mutex5Mutex@Base 6
+ _D3std12experimental6logger4core6Logger6__ctorMFNfE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core6Logger6__initZ@Base 6
+ _D3std12experimental6logger4core6Logger6__vtblZ@Base 6
+ _D3std12experimental6logger4core6Logger7__ClassZ@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry11__xopEqualsFKxS3std12experimental6logger4core6Logger8LogEntryKxS3std12experimental6logger4core6Logger8LogEntryZb@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry6__initZ@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry8opAssignMFNaNbNcNjNfS3std12experimental6logger4core6Logger8LogEntryZS3std12experimental6logger4core6Logger8LogEntry@Base 6
+ _D3std12experimental6logger4core6Logger8LogEntry9__xtoHashFNbNeKxS3std12experimental6logger4core6Logger8LogEntryZk@Base 6
+ _D3std12experimental6logger4core6Logger8logLevelMFNdNiNfxE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D3std12experimental6logger4core6Logger8logLevelMxFNaNdNiNfZE3std12experimental6logger4core8LogLevel@Base 6
+ _D3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D3std12experimental6logger4core8MsgRange11__xopEqualsFKxS3std12experimental6logger4core8MsgRangeKxS3std12experimental6logger4core8MsgRangeZb@Base 6
+ _D3std12experimental6logger4core8MsgRange3putMFNfwZv@Base 6
+ _D3std12experimental6logger4core8MsgRange6__ctorMFNcNfC3std12experimental6logger4core6LoggerZS3std12experimental6logger4core8MsgRange@Base 6
+ _D3std12experimental6logger4core8MsgRange6__initZ@Base 6
+ _D3std12experimental6logger4core8MsgRange9__xtoHashFNbNeKxS3std12experimental6logger4core8MsgRangeZk@Base 6
+ _D3std12experimental6logger4core8parentOfFAyaZAya@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNeC3std12experimental6logger4core6LoggerZv@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNfZ11trustedLoadFNaNbNiNeKOC3std12experimental6logger4core6LoggerZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12experimental6logger4core9sharedLogFNdNfZC3std12experimental6logger4core6Logger@Base 6
+ _D3std12socketstream12SocketStream10writeBlockMFxPvkZk@Base 6
+ _D3std12socketstream12SocketStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std12socketstream12SocketStream5closeMFZv@Base 6
+ _D3std12socketstream12SocketStream6__ctorMFC3std6socket6SocketE3std6stream8FileModeZC3std12socketstream12SocketStream@Base 6
+ _D3std12socketstream12SocketStream6__ctorMFC3std6socket6SocketZC3std12socketstream12SocketStream@Base 6
+ _D3std12socketstream12SocketStream6__initZ@Base 6
+ _D3std12socketstream12SocketStream6__vtblZ@Base 6
+ _D3std12socketstream12SocketStream6socketMFZC3std6socket6Socket@Base 6
+ _D3std12socketstream12SocketStream7__ClassZ@Base 6
+ _D3std12socketstream12SocketStream8toStringMFZAya@Base 6
+ _D3std12socketstream12SocketStream9readBlockMFPvkZk@Base 6
+ _D3std12socketstream12__ModuleInfoZ@Base 6
+ _D3std1c4fenv12__ModuleInfoZ@Base 6
+ _D3std1c4math12__ModuleInfoZ@Base 6
+ _D3std1c4time12__ModuleInfoZ@Base 6
+ _D3std1c5linux11linuxextern12__ModuleInfoZ@Base 6
+ _D3std1c5linux4tipc12__ModuleInfoZ@Base 6
+ _D3std1c5linux5linux12__ModuleInfoZ@Base 6
+ _D3std1c5linux5linux13struct_stat646__initZ@Base 6
+ _D3std1c5linux6socket12__ModuleInfoZ@Base 6
+ _D3std1c5linux7pthread12__ModuleInfoZ@Base 6
+ _D3std1c5linux7termios12__ModuleInfoZ@Base 6
+ _D3std1c5stdio12__ModuleInfoZ@Base 6
+ _D3std1c6locale12__ModuleInfoZ@Base 6
+ _D3std1c6stdarg12__ModuleInfoZ@Base 6
+ _D3std1c6stddef12__ModuleInfoZ@Base 6
+ _D3std1c6stdlib12__ModuleInfoZ@Base 6
+ _D3std1c6string12__ModuleInfoZ@Base 6
+ _D3std1c6wcharh12__ModuleInfoZ@Base 6
+ _D3std1c7process12__ModuleInfoZ@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyaAyakC6object9ThrowableZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyaC6object9ThrowableAyakZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__ctorMFNaNfAyakkC6object9ThrowableAyakZC3std3csv12CSVException@Base 6
+ _D3std3csv12CSVException6__initZ@Base 6
+ _D3std3csv12CSVException6__vtblZ@Base 6
+ _D3std3csv12CSVException7__ClassZ@Base 6
+ _D3std3csv12CSVException8toStringMFNaNfZAya@Base 6
+ _D3std3csv12__ModuleInfoZ@Base 6
+ _D3std3csv23HeaderMismatchException6__ctorMFNaNfAyaAyakC6object9ThrowableZC3std3csv23HeaderMismatchException@Base 6
+ _D3std3csv23HeaderMismatchException6__ctorMFNaNfAyaC6object9ThrowableAyakZC3std3csv23HeaderMismatchException@Base 6
+ _D3std3csv23HeaderMismatchException6__initZ@Base 6
+ _D3std3csv23HeaderMismatchException6__vtblZ@Base 6
+ _D3std3csv23HeaderMismatchException7__ClassZ@Base 6
+ _D3std3csv23IncompleteCellException6__ctorMFNaNfAyaAyakC6object9ThrowableZC3std3csv23IncompleteCellException@Base 6
+ _D3std3csv23IncompleteCellException6__ctorMFNaNfAyaC6object9ThrowableAyakZC3std3csv23IncompleteCellException@Base 6
+ _D3std3csv23IncompleteCellException6__initZ@Base 6
+ _D3std3csv23IncompleteCellException6__vtblZ@Base 6
+ _D3std3csv23IncompleteCellException7__ClassZ@Base 6
+ _D3std3net4curl12AutoProtocol6__initZ@Base 6
+ _D3std3net4curl12__ModuleInfoZ@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool3popMFNaNfZAh@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool4pushMFNaNbNfAhZv@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry11__xopEqualsFKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryZb@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5Entry9__xtoHashFNbNeKxS3std3net4curl12__T4PoolTAhZ4Pool5EntryZk@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3net4curl12__T4PoolTAhZ4Pool6__initZ@Base 6
+ _D3std3net4curl13CurlException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3net4curl13CurlException@Base 6
+ _D3std3net4curl13CurlException6__initZ@Base 6
+ _D3std3net4curl13CurlException6__vtblZ@Base 6
+ _D3std3net4curl13CurlException7__ClassZ@Base 6
+ _D3std3net4curl19__T11CurlMessageTbZ11CurlMessage6__initZ@Base 6
+ _D3std3net4curl19_receiveAsyncChunksFAhKAhS3std3net4curl12__T4PoolTAhZ4PoolKAhS3std11concurrency3TidKbZk@Base 6
+ _D3std3net4curl20AsyncChunkInputRange11__xopEqualsFKxS3std3net4curl20AsyncChunkInputRangeKxS3std3net4curl20AsyncChunkInputRangeZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange6__ctorMFNcS3std11concurrency3TidkkZS3std3net4curl20AsyncChunkInputRange@Base 6
+ _D3std3net4curl20AsyncChunkInputRange6__initZ@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin514tryEnsureUnitsMFZv@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin54waitMFS4core4time8DurationZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin55emptyMFNdZb@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin55frontMFNdZAh@Base 6
+ _D3std3net4curl20AsyncChunkInputRange8__mixin58popFrontMFZv@Base 6
+ _D3std3net4curl20AsyncChunkInputRange9__xtoHashFNbNeKxS3std3net4curl20AsyncChunkInputRangeZk@Base 6
+ _D3std3net4curl20CurlTimeoutException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3net4curl20CurlTimeoutException@Base 6
+ _D3std3net4curl20CurlTimeoutException6__initZ@Base 6
+ _D3std3net4curl20CurlTimeoutException6__vtblZ@Base 6
+ _D3std3net4curl20CurlTimeoutException7__ClassZ@Base 6
+ _D3std3net4curl20_finalizeAsyncChunksFAhKAhS3std11concurrency3TidZv@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage11__xopEqualsFKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZb@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage6__initZ@Base 6
+ _D3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage9__xtoHashFNbNeKxS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZk@Base 6
+ _D3std3net4curl21__T11curlMessageTAyhZ11curlMessageFNaNbNiNfAyhZS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage@Base 6
+ _D3std3net4curl3FTP10addCommandMFAxaZv@Base 6
+ _D3std3net4curl3FTP10initializeMFZv@Base 6
+ _D3std3net4curl3FTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl3FTP11__xopEqualsFKxS3std3net4curl3FTPKxS3std3net4curl3FTPZb@Base 6
+ _D3std3net4curl3FTP13clearCommandsMFZv@Base 6
+ _D3std3net4curl3FTP13contentLengthMFNdkZv@Base 6
+ _D3std3net4curl3FTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl3FTP3dupMFZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP4Impl11__xopEqualsFKxS3std3net4curl3FTP4ImplKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std3net4curl3FTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl3FTP4Impl6__initZ@Base 6
+ _D3std3net4curl3FTP4Impl8opAssignMFNcNjS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std3net4curl3FTP4Impl9__xtoHashFNbNeKxS3std3net4curl3FTP4ImplZk@Base 6
+ _D3std3net4curl3FTP6__initZ@Base 6
+ _D3std3net4curl3FTP6opCallFAxaZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP6opCallFZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl3FTP8encodingMFNdAyaZv@Base 6
+ _D3std3net4curl3FTP8encodingMFNdZAya@Base 6
+ _D3std3net4curl3FTP8opAssignMFNcNjS3std3net4curl3FTPZS3std3net4curl3FTP@Base 6
+ _D3std3net4curl3FTP9__mixin1210dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210verifyHostMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1210verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin1211dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl3FTP9__mixin1212netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl3FTP9__mixin1214connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1214localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin1216operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl3FTP9__mixin1217setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1222setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin1228defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl3FTP9__mixin125proxyMFNdAxaZv@Base 6
+ _D3std3net4curl3FTP9__mixin126handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl3FTP9__mixin126onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl3FTP9__mixin127verboseMFNdbZv@Base 6
+ _D3std3net4curl3FTP9__mixin128shutdownMFZv@Base 6
+ _D3std3net4curl3FTP9__mixin129isStoppedMFNdZb@Base 6
+ _D3std3net4curl3FTP9__mixin129localPortMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin129onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl3FTP9__mixin129proxyPortMFNdtZv@Base 6
+ _D3std3net4curl3FTP9__mixin129proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl3FTP9__xtoHashFNbNeKxS3std3net4curl3FTPZk@Base 6
+ _D3std3net4curl4Curl10initializeMFZv@Base 6
+ _D3std3net4curl4Curl10onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl4Curl11errorStringMFiZAya@Base 6
+ _D3std3net4curl4Curl13_seekCallbackUPvliZi@Base 6
+ _D3std3net4curl4Curl13_sendCallbackUPakkPvZk@Base 6
+ _D3std3net4curl4Curl14onSocketOptionMFNdDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiZv@Base 6
+ _D3std3net4curl4Curl14throwOnStoppedMFAyaZv@Base 6
+ _D3std3net4curl4Curl15onReceiveHeaderMFNdDFxAaZvZv@Base 6
+ _D3std3net4curl4Curl16_receiveCallbackUxPakkPvZk@Base 6
+ _D3std3net4curl4Curl16clearIfSupportedMFE3etc1c4curl10CurlOptionZv@Base 6
+ _D3std3net4curl4Curl17_progressCallbackUPvddddZi@Base 6
+ _D3std3net4curl4Curl21_socketOptionCallbackUPvE3std6socket8socket_tiZi@Base 6
+ _D3std3net4curl4Curl22_receiveHeaderCallbackUxPakkPvZk@Base 6
+ _D3std3net4curl4Curl3dupMFZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionAxaZv@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionPvZv@Base 6
+ _D3std3net4curl4Curl3setMFE3etc1c4curl10CurlOptionlZv@Base 6
+ _D3std3net4curl4Curl4curlFNcNdZS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl4Curl5clearMFE3etc1c4curl10CurlOptionZv@Base 6
+ _D3std3net4curl4Curl5pauseMFbbZv@Base 6
+ _D3std3net4curl4Curl6__initZ@Base 6
+ _D3std3net4curl4Curl6_checkMFiZv@Base 6
+ _D3std3net4curl4Curl6onSeekMFNdDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekZv@Base 6
+ _D3std3net4curl4Curl6onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl4Curl7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4Curl7performMFbZi@Base 6
+ _D3std3net4curl4Curl8shutdownMFZv@Base 6
+ _D3std3net4curl4Curl9onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl4HTTP10StatusLine11__xopEqualsFKxS3std3net4curl4HTTP10StatusLineKxS3std3net4curl4HTTP10StatusLineZb@Base 6
+ _D3std3net4curl4HTTP10StatusLine5resetMFNfZv@Base 6
+ _D3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D3std3net4curl4HTTP10StatusLine8toStringMFZAya@Base 6
+ _D3std3net4curl4HTTP10StatusLine9__xtoHashFNbNeKxS3std3net4curl4HTTP10StatusLineZk@Base 6
+ _D3std3net4curl4HTTP10initializeMFZv@Base 6
+ _D3std3net4curl4HTTP10statusLineMFNdZS3std3net4curl4HTTP10StatusLine@Base 6
+ _D3std3net4curl4HTTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl4HTTP11__xopEqualsFKxS3std3net4curl4HTTPKxS3std3net4curl4HTTPZb@Base 6
+ _D3std3net4curl4HTTP11setPostDataMFAxvAyaZv@Base 6
+ _D3std3net4curl4HTTP12maxRedirectsMFNdkZv@Base 6
+ _D3std3net4curl4HTTP12setCookieJarMFAxaZv@Base 6
+ _D3std3net4curl4HTTP12setUserAgentMFAxaZv@Base 6
+ _D3std3net4curl4HTTP13contentLengthMFNdkZv@Base 6
+ _D3std3net4curl4HTTP14flushCookieJarMFZv@Base 6
+ _D3std3net4curl4HTTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl4HTTP15clearAllCookiesMFZv@Base 6
+ _D3std3net4curl4HTTP15onReceiveHeaderMFNdDFxAaxAaZvZv@Base 6
+ _D3std3net4curl4HTTP15responseHeadersMFNdZHAyaAya@Base 6
+ _D3std3net4curl4HTTP16addRequestHeaderMFAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZ3bufG63a@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZ9userAgentAya@Base 6
+ _D3std3net4curl4HTTP16defaultUserAgentFNdZAya@Base 6
+ _D3std3net4curl4HTTP16setTimeConditionMFE3etc1c4curl12CurlTimeCondS3std8datetime7SysTimeZv@Base 6
+ _D3std3net4curl4HTTP19clearRequestHeadersMFZv@Base 6
+ _D3std3net4curl4HTTP19clearSessionCookiesMFZv@Base 6
+ _D3std3net4curl4HTTP19defaultMaxRedirectsk@Base 6
+ _D3std3net4curl4HTTP19onReceiveStatusLineMFNdDFS3std3net4curl4HTTP10StatusLineZvZv@Base 6
+ _D3std3net4curl4HTTP20authenticationMethodMFNdE3etc1c4curl8CurlAuthZv@Base 6
+ _D3std3net4curl4HTTP3dupMFZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP4Impl11__xopEqualsFKxS3std3net4curl4HTTP4ImplKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std3net4curl4HTTP4Impl15onReceiveHeaderMFNdDFxAaxAaZvZv@Base 6
+ _D3std3net4curl4HTTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl4HTTP4Impl6__initZ@Base 6
+ _D3std3net4curl4HTTP4Impl8opAssignMFNcNjS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std3net4curl4HTTP4Impl9__xtoHashFNbNeKxS3std3net4curl4HTTP4ImplZk@Base 6
+ _D3std3net4curl4HTTP6__initZ@Base 6
+ _D3std3net4curl4HTTP6caInfoMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP6methodMFNdE3std3net4curl4HTTP6MethodZv@Base 6
+ _D3std3net4curl4HTTP6methodMFNdZE3std3net4curl4HTTP6Method@Base 6
+ _D3std3net4curl4HTTP6opCallFAxaZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP6opCallFZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4HTTP8opAssignMFNcNjS3std3net4curl4HTTPZS3std3net4curl4HTTP@Base 6
+ _D3std3net4curl4HTTP8postDataMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP8postDataMFNdAxvZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510verifyHostMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3510verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3511dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3512netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3514connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3514localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3516operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3517setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3522setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin3528defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl4HTTP9__mixin355proxyMFNdAxaZv@Base 6
+ _D3std3net4curl4HTTP9__mixin356handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4HTTP9__mixin356onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl4HTTP9__mixin357verboseMFNdbZv@Base 6
+ _D3std3net4curl4HTTP9__mixin358shutdownMFZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359isStoppedMFNdZb@Base 6
+ _D3std3net4curl4HTTP9__mixin359localPortMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359proxyPortMFNdtZv@Base 6
+ _D3std3net4curl4HTTP9__mixin359proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl4HTTP9__xtoHashFNbNeKxS3std3net4curl4HTTPZk@Base 6
+ _D3std3net4curl4HTTP9setCookieMFAxaZv@Base 6
+ _D3std3net4curl4SMTP10initializeMFZv@Base 6
+ _D3std3net4curl4SMTP11__fieldDtorMFZv@Base 6
+ _D3std3net4curl4SMTP11__xopEqualsFKxS3std3net4curl4SMTPKxS3std3net4curl4SMTPZb@Base 6
+ _D3std3net4curl4SMTP15__fieldPostblitMFNbZv@Base 6
+ _D3std3net4curl4SMTP3urlMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP4Impl6__dtorMFZv@Base 6
+ _D3std3net4curl4SMTP4Impl6__initZ@Base 6
+ _D3std3net4curl4SMTP4Impl7messageMFNdAyaZv@Base 6
+ _D3std3net4curl4SMTP4Impl8opAssignMFNcNjS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std3net4curl4SMTP6__initZ@Base 6
+ _D3std3net4curl4SMTP6opCallFAxaZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP6opCallFZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP7messageMFNdAyaZv@Base 6
+ _D3std3net4curl4SMTP7performMFE3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4FlagZi@Base 6
+ _D3std3net4curl4SMTP8opAssignMFNcNjS3std3net4curl4SMTPZS3std3net4curl4SMTP@Base 6
+ _D3std3net4curl4SMTP9__mixin1010dnsTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010onProgressMFNdDFkkkkZiZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010tcpNoDelayMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010verifyHostMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1010verifyPeerMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1011dataTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdC3std6socket15InternetAddressZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1012netInterfaceMFNdxG4hZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1014connectTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1014localPortRangeMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1016operationTimeoutMFNdS4core4time8DurationZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1017setAuthenticationMFAxaAxaAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1022setProxyAuthenticationMFAxaAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin1028defaultAsyncStringBufferSizek@Base 6
+ _D3std3net4curl4SMTP9__mixin105proxyMFNdAxaZv@Base 6
+ _D3std3net4curl4SMTP9__mixin106handleMFNcNdNjZS3std3net4curl4Curl@Base 6
+ _D3std3net4curl4SMTP9__mixin106onSendMFNdDFAvZkZv@Base 6
+ _D3std3net4curl4SMTP9__mixin107verboseMFNdbZv@Base 6
+ _D3std3net4curl4SMTP9__mixin108shutdownMFZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109isStoppedMFNdZb@Base 6
+ _D3std3net4curl4SMTP9__mixin109localPortMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109onReceiveMFNdDFAhZkZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109proxyPortMFNdtZv@Base 6
+ _D3std3net4curl4SMTP9__mixin109proxyTypeMFNdE3etc1c4curl9CurlProxyZv@Base 6
+ _D3std3net4curl4SMTP9__xtoHashFNbNeKxS3std3net4curl4SMTPZk@Base 6
+ _D3std3net4curl7CurlAPI19_sharedStaticDtor18FZv@Base 6
+ _D3std3net4curl7CurlAPI3API6__initZ@Base 6
+ _D3std3net4curl7CurlAPI4_apiS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl7CurlAPI6__initZ@Base 6
+ _D3std3net4curl7CurlAPI7_handlePv@Base 6
+ _D3std3net4curl7CurlAPI7loadAPIFZ5namesyAAa@Base 6
+ _D3std3net4curl7CurlAPI7loadAPIFZPv@Base 6
+ _D3std3net4curl7CurlAPI8instanceFNcNdZS3std3net4curl7CurlAPI3API@Base 6
+ _D3std3net4curl8isFTPUrlFAxaZb@Base 6
+ _D3std3net7isemail10AsciiToken6__initZ@Base 6
+ _D3std3net7isemail11EmailStatus10domainPartMxFNdZAya@Base 6
+ _D3std3net7isemail11EmailStatus10statusCodeMxFNdZE3std3net7isemail15EmailStatusCode@Base 6
+ _D3std3net7isemail11EmailStatus11__xopEqualsFKxS3std3net7isemail11EmailStatusKxS3std3net7isemail11EmailStatusZb@Base 6
+ _D3std3net7isemail11EmailStatus5validMxFNdZb@Base 6
+ _D3std3net7isemail11EmailStatus6__ctorMFNcbAyaAyaE3std3net7isemail15EmailStatusCodeZS3std3net7isemail11EmailStatus@Base 6
+ _D3std3net7isemail11EmailStatus6__initZ@Base 6
+ _D3std3net7isemail11EmailStatus6statusMxFNdZAya@Base 6
+ _D3std3net7isemail11EmailStatus8toStringMxFZAya@Base 6
+ _D3std3net7isemail11EmailStatus9__xtoHashFNbNeKxS3std3net7isemail11EmailStatusZk@Base 6
+ _D3std3net7isemail11EmailStatus9localPartMxFNdZAya@Base 6
+ _D3std3net7isemail12__ModuleInfoZ@Base 6
+ _D3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D3std3net7isemail21statusCodeDescriptionFE3std3net7isemail15EmailStatusCodeZAya@Base 6
+ _D3std3net7isemail5Token6__initZ@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ20__T12toCaseLengthTaZ12toCaseLengthFNaNfxAaZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ20__T12toCaseLengthTuZ12toCaseLengthFNaNfxAuZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ20__T12toCaseLengthTwZ12toCaseLengthFNaNfxAwZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ20__T12toCaseLengthTaZ12toCaseLengthFNaNfxAaZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ20__T12toCaseLengthTuZ12toCaseLengthFNaNfxAuZk@Base 6
+ _D3std3uni101__T12toCaseLengthS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ20__T12toCaseLengthTwZ12toCaseLengthFNaNfxAwZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZ6moveToFNaNbNiNfAakkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZ6moveToFNaNbNiNfAukkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZ6moveToFNaNbNiNfAwkkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZ6moveToFNaNbNiNfAakkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTaZ13toCaseInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZ6moveToFNaNbNiNfAukkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTuZ13toCaseInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZ6moveToFNaNbNiNfAwkkkZk@Base 6
+ _D3std3uni104__T13toCaseInPlaceS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTwZ13toCaseInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni107__T12mapTrieIndexTS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTaZ18toCaseInPlaceAllocFNaNeKAakkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTuZ18toCaseInPlaceAllocFNaNeKAukkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toLowerIndexFNaNbNiNewZtVki1043S34_D3std3uni10toLowerTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTwZ18toCaseInPlaceAllocFNaNeKAwkkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTaZ18toCaseInPlaceAllocFNaNeKAakkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTuZ18toCaseInPlaceAllocFNaNeKAukkZv@Base 6
+ _D3std3uni107__T18toCaseInPlaceAllocS36_D3std3uni12toUpperIndexFNaNbNiNewZtVki1051S34_D3std3uni10toUpperTabFNaNbNiNekZwZ26__T18toCaseInPlaceAllocTwZ18toCaseInPlaceAllocFNaNeKAwkkZv@Base 6
+ _D3std3uni10compressToFNaNbNfkKAhZv@Base 6
+ _D3std3uni10isPowerOf2FNaNbNiNfkZb@Base 6
+ _D3std3uni10nfkcQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkcQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10nfkdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10numberTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10numberTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10safeRead24FNaNbNiNexPhkZk@Base 6
+ _D3std3uni10symbolTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10symbolTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni10toLowerTabFNaNbNiNekZw@Base 6
+ _D3std3uni10toTitleTabFNaNbNiNekZw@Base 6
+ _D3std3uni10toUpperTabFNaNbNiNekZw@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayZS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieKxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZt@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni113__T23switchUniformLowerBoundS753std10functional47__T9binaryFunVAyaa4_613c3d62VAyaa1_61VAyaa1_62Z9binaryFunTAxkTkZ23switchUniformLowerBoundFNaNbNiNfAxkkZk@Base 6
+ _D3std3uni11composeJamoFNaNbNiNewwwZw@Base 6
+ _D3std3uni11isGraphicalFNaNbNiNfwZb@Base 6
+ _D3std3uni11isSurrogateFNaNbNiNfwZb@Base 6
+ _D3std3uni11safeWrite24FNaNbNiNePhkkZv@Base 6
+ _D3std3uni11toTitlecaseFNaNbNiNfwZw@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder109__T14deduceMaxIndexTS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki1TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki0TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki1TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder19__T8addValueVki1TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder60__T8addValueVki0TS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni120__T11TrieBuilderTbTwVii1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder109__T14deduceMaxIndexTS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekktZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki0TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder19__T8addValueVki1TtZ8addValueMFNaNbNetkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNektZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder60__T8addValueVki0TS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVki1TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVki1TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni120__T11TrieBuilderTtTwVii1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni121__T11findSetNameS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni124__T11findSetNameS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZi@Base 6
+ _D3std3uni127__T11findSetNameS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ11findSetNameFNaNfxAaZb@Base 6
+ _D3std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZi@Base 6
+ _D3std3uni12__ModuleInfoZ@Base 6
+ _D3std3uni12ceilPowerOf2FNaNbNiNfkZk@Base 6
+ _D3std3uni12fullCaseTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni12fullCaseTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni12isPrivateUseFNaNbNiNfwZb@Base 6
+ _D3std3uni12toLowerIndexFNaNbNiNewZt@Base 6
+ _D3std3uni12toTitleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni12toUpperIndexFNaNbNiNewZt@Base 6
+ _D3std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ22__T9__lambda2TAyaTAxaZ9__lambda2FNaNfAyaAxaZb@Base 6
+ _D3std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZi@Base 6
+ _D3std3uni13ReallocPolicy12__T5allocTkZ5allocFNekZAk@Base 6
+ _D3std3uni13ReallocPolicy14__T7destroyTkZ7destroyFNbNiNeKAkZv@Base 6
+ _D3std3uni13ReallocPolicy14__T7reallocTkZ7reallocFNeAkkZAk@Base 6
+ _D3std3uni13ReallocPolicy15__T6appendTkTiZ6appendFNeKAkiZv@Base 6
+ _D3std3uni13ReallocPolicy6__initZ@Base 6
+ _D3std3uni13floorPowerOf2FNaNbNiNfkZk@Base 6
+ _D3std3uni13graphicalTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13graphicalTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13isPunctuationFNaNbNiNfwZb@Base 6
+ _D3std3uni13isSurrogateHiFNaNbNiNfwZb@Base 6
+ _D3std3uni13isSurrogateLoFNaNbNiNfwZb@Base 6
+ _D3std3uni13lowerCaseTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13lowerCaseTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13upperCaseTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni13upperCaseTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni14MatcherConcept6__initZ@Base 6
+ _D3std3uni14__T5forceTkTiZ5forceFNaNbNiNfiZk@Base 6
+ _D3std3uni14combiningClassFNaNbNiNfwZh@Base 6
+ _D3std3uni14decompressFromFNaNfAxhKkZk@Base 6
+ _D3std3uni14isNonCharacterFNaNbNiNfwZb@Base 6
+ _D3std3uni14simpleCaseTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni14simpleCaseTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAaZv@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAuZv@Base 6
+ _D3std3uni14toLowerInPlaceFNaNfKAwZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAaZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAuZv@Base 6
+ _D3std3uni14toUpperInPlaceFNaNfKAwZv@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni101__T10MultiArrayTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni153__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedThZ10MultiArrayZS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZh@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTtZ10MultiArrayZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni103__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTtZ10MultiArrayZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZt@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni15__T7toLowerTAaZ7toLowerFNaNeAaZAa@Base 6
+ _D3std3uni15decomposeHangulFNewZS3std3uni8Grapheme@Base 6
+ _D3std3uni15hangulRecomposeFNaNbNiNeAwZv@Base 6
+ _D3std3uni15punctuationTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni15punctuationTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni15unalignedRead24FNaNbNiNexPhkZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki14Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki2TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder19__T8addValueVki2ThZ8addValueMFNaNbNehkZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNehZS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder89__T15spillToNextPageVki2TS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewhZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder93__T19spillToNextPageImplVki2TS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderThTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekktZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TtZ8addValueMFNaNbNetkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNektZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki16Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekktZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder155__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder19__T8addValueVki2TtZ8addValueMFNaNbNetkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNektZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNetZS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewtZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder90__T15spillToNextPageVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder94__T19spillToNextPageImplVki2TS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni166__T11TrieBuilderTtTwVii1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni16__T7toLowerTAxaZ7toLowerFNaNeAxaZAxa@Base 6
+ _D3std3uni16__T7toLowerTAyaZ7toLowerFNaNeAyaZAya@Base 6
+ _D3std3uni16__T7toLowerTAyuZ7toLowerFNaNeAyuZAyu@Base 6
+ _D3std3uni16__T7toLowerTAywZ7toLowerFNaNbNeAywZAyw@Base 6
+ _D3std3uni16__T7toUpperTAyaZ7toUpperFNaNeAyaZAya@Base 6
+ _D3std3uni16__T7toUpperTAyuZ7toUpperFNaNeAyuZAyu@Base 6
+ _D3std3uni16__T7toUpperTAywZ7toUpperFNaNbNeAywZAyw@Base 6
+ _D3std3uni16canonMappingTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16canonMappingTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16nonCharacterTrieFNaNbNdNiNfZ3resyS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16nonCharacterTrieFNaNbNdNiNfZyS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toLowerIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toLowerIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toTitleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toTitleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toUpperIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16toUpperIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni16unalignedWrite24FNaNbNiNePhkkZv@Base 6
+ _D3std3uni17CodepointInterval11__xopEqualsFKxS3std3uni17CodepointIntervalKxS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni17CodepointInterval1aMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std3uni17CodepointInterval1bMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std3uni17CodepointInterval43__T8opEqualsTxS3std3uni17CodepointIntervalZ8opEqualsMxFNaNbNiNfxS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni17CodepointInterval6__ctorMFNaNbNcNiNfkkZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni17CodepointInterval6__initZ@Base 6
+ _D3std3uni17__T4icmpTAxaTAxaZ4icmpFNaNeAxaAxaZi@Base 6
+ _D3std3uni17__T4icmpTAxuTAxuZ4icmpFNaNeAxuAxuZi@Base 6
+ _D3std3uni17__T4icmpTAxwTAxwZ4icmpFNaNbNiNeAxwAxwZi@Base 6
+ _D3std3uni17__T8spaceForVki1Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni17__T8spaceForVki7Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni17__T8spaceForVki8Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni17compatMappingTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni17compatMappingTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray11__xopEqualsFKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZb@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki2Z3ptrMNgFNaNbNdNiZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray12__T3ptrVki3Z3ptrMNgFNaNbNdNiZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki2Z5sliceMNgFNaNbNdNiZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray14__T5sliceVki3Z5sliceMNgFNaNbNdNiZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki2Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki3Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray15__T6lengthVki3Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki2Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray16__T7raw_ptrVki3Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray6__initZ@Base 6
+ _D3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArray9__xtoHashFNbNeKxS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZk@Base 6
+ _D3std3uni189__T14loadUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni18__T5sicmpTAxaTAxaZ5sicmpFNaNeAxaAxaZi@Base 6
+ _D3std3uni18__T5sicmpTAxuTAxuZ5sicmpFNaNeAxuAxuZi@Base 6
+ _D3std3uni18__T5sicmpTAxwTAxwZ5sicmpFNaNeAxwAxwZi@Base 6
+ _D3std3uni18__T8spaceForVki11Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki12Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki13Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki14Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki15Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18__T8spaceForVki16Z8spaceForFNaNbNiNfkZk@Base 6
+ _D3std3uni18combiningClassTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18combiningClassTrieFNaNbNdNiNfZyS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18graphemeExtendTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18graphemeExtendTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni18simpleCaseFoldingsFNaNbNewZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range5emptyMxFNaNbNdZb@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range5frontMxFNaNbNdZw@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__ctorMFNaNbNckkZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__ctorMFNaNbNcwZS3std3uni18simpleCaseFoldingsFNewZ5Range@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6__initZ@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range6lengthMxFNaNbNdZk@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range7isSmallMxFNaNbNdZb@Base 6
+ _D3std3uni18simpleCaseFoldingsFNewZ5Range8popFrontMFNaNbZv@Base 6
+ _D3std3uni18toLowerSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni18toTitleSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni18toUpperSimpleIndexFNaNbNiNewZt@Base 6
+ _D3std3uni192__T14loadUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni195__T14loadUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ14loadUnicodeSetFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni143__T10MultiArrayTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni199__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTiZ12mapTrieIndexFNaNbNiNfiZk@Base 6
+ _D3std3uni199__T12mapTrieIndexTS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ20__T12mapTrieIndexTwZ12mapTrieIndexFNaNbNiNfwZk@Base 6
+ _D3std3uni19compositionJumpTrieFNaNbNdNiNfZ3resyS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni19compositionJumpTrieFNaNbNdNiNfZyS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni19decompressIntervalsFNaNfAxhZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni19hangulSyllableIndexFNaNbNiNewZi@Base 6
+ _D3std3uni19isRegionalIndicatorFNfwZb@Base 6
+ _D3std3uni20__T9BitPackedTbVki1Z9BitPacked6__initZ@Base 6
+ _D3std3uni20__T9BitPackedTkVki7Z9BitPacked6__initZ@Base 6
+ _D3std3uni20__T9BitPackedTkVki8Z9BitPacked6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder10putRangeAtMFNaNbNekkbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder11__xopEqualsFKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZb@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki0TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder129__T15spillToNextPageVki3TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki0Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki1Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki2Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder12__T3idxVki3Z3idxMFNaNbNcNdNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder131__T15spillToNextPageVki2TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ15spillToNextPageMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder133__T19spillToNextPageImplVki3TS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki1TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder135__T19spillToNextPageImplVki2TS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ19spillToNextPageImplMFNaNbNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder14ConstructState6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder19__T8addValueVki3TbZ8addValueMFNaNbNebkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder201__T14deduceMaxIndexTS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ14deduceMaxIndexFNaNbNiNeZk@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder59__T8addValueVki0TS3std3uni20__T9BitPackedTkVki7Z9BitPackedZ8addValueMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5buildMFNaNbNeZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder5putAtMFNaNbNekbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki1TS3std3uni21__T9BitPackedTkVki11Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder60__T8addValueVki2TS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ8addValueMFNaNbNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__ctorMFNaNbNcNebZS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder6__initZ@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putRangeMFNaNewwbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder8putValueMFNaNewbZv@Base 6
+ _D3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilder9__xtoHashFNbNeKxS3std3uni212__T11TrieBuilderTbTwVii1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ11TrieBuilderZk@Base 6
+ _D3std3uni21DecompressedIntervals11__xopEqualsFKxS3std3uni21DecompressedIntervalsKxS3std3uni21DecompressedIntervalsZb@Base 6
+ _D3std3uni21DecompressedIntervals4saveMFNaNdNfZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni21DecompressedIntervals5emptyMxFNaNdNfZb@Base 6
+ _D3std3uni21DecompressedIntervals5frontMFNaNdNfZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni21DecompressedIntervals6__ctorMFNaNcNfAxhZS3std3uni21DecompressedIntervals@Base 6
+ _D3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D3std3uni21DecompressedIntervals8popFrontMFNaNfZv@Base 6
+ _D3std3uni21DecompressedIntervals9__xtoHashFNbNeKxS3std3uni21DecompressedIntervalsZk@Base 6
+ _D3std3uni21__T11copyForwardTiTkZ11copyForwardFNaNbNiNfAiAkZv@Base 6
+ _D3std3uni21__T11copyForwardTkTkZ11copyForwardFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni21__T9BitPackedTkVki11Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki12Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki13Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki14Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki15Z9BitPacked6__initZ@Base 6
+ _D3std3uni21__T9BitPackedTkVki16Z9BitPacked6__initZ@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxaZ12fullCasedCmpFNaNewwKAxaZi@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxuZ12fullCasedCmpFNaNewwKAxuZi@Base 6
+ _D3std3uni22__T12fullCasedCmpTAxwZ12fullCasedCmpFNaNbNiNewwKAxwZi@Base 6
+ _D3std3uni22__T14toLowerInPlaceTaZ14toLowerInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni22__T14toLowerInPlaceTuZ14toLowerInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni22__T14toLowerInPlaceTwZ14toLowerInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTaZ14toUpperInPlaceFNaNeKAaZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTuZ14toUpperInPlaceFNaNeKAuZv@Base 6
+ _D3std3uni22__T14toUpperInPlaceTwZ14toUpperInPlaceFNaNeKAwZv@Base 6
+ _D3std3uni22__T6asTrieTtVii12Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits6__initZ@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni23__T13copyBackwardsTkTkZ13copyBackwardsFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni23__T15packedArrayViewThZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T15packedArrayViewTtZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23genUnrolledSwitchSearchFkZAya@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii4Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii5Vii8Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii6Vii7Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieThVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii8Vii5Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNetkZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNetkZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T16propertyNameLessTaTaZ16propertyNameLessFNaNfAxaAxaZb@Base 6
+ _D3std3uni27__T13replicateBitsVki4Vki8Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki1Vki32Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki2Vki16Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki32Vki1Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T20isPrettyPropertyNameTaZ20isPrettyPropertyNameFNaNfxAaZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZi@Base 6
+ _D3std3uni29__T6asTrieTbVii7Vii4Vii4Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T16codepointSetTrieVii13Vii8Z87__T16codepointSetTrieTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16codepointSetTrieFNaNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNehkkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl77__T8opEqualsTS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl78__T8opEqualsTxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNetkZv@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNetkkZv@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl78__T8opEqualsTS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl79__T8opEqualsTxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray10__postblitMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray11__T6appendZ6appendMFNaNbNeAkXv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray11__xopEqualsFKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray12__T7opIndexZ7opIndexMxFNaNbNiNekZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray13__T8opEqualsZ8opEqualsMxFNaNbNiNeKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray13opIndexAssignMFNaNbNekkZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray14__T6__ctorTAkZ6__ctorMFNaNbNcNeAkZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray16dupThisReferenceMFNaNbNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray17freeThisReferenceMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray5reuseFNaNbNeAkZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray673__T6__ctorTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ6__ctorMFNaNcNeS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__dtorMFNaNbNiNeZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6lengthMFNaNbNdNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMFNaNbNeZAk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMFNaNbNekkZAk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMxFNaNbNiNeZAxk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray7opSliceMxFNaNbNiNekkZAxk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8opAssignMFNaNbNcNiNjNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8refCountMFNaNbNdNiNekZv@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray8refCountMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray9__xtoHashFNbNeKxS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList10byIntervalMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11addIntervalMFNaNbNeiikZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange5frontMxFNaNbNdNiNeZw@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__ctorMFNaNbNcNiNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRange9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList11byCodepointMFNdNeZ14CodepointRangeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12__T7scanForZ7scanForMxFNaNbNiNewZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ41__T6bisectTAS3std3uni17CodepointIntervalZ6bisectFAS3std3uni17CodepointIntervalkAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ47__T11binaryScopeTAS3std3uni17CodepointIntervalZ11binaryScopeFAS3std3uni17CodepointIntervalAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZ47__T11linearScopeTAS3std3uni17CodepointIntervalZ11linearScopeFNaNfAS3std3uni17CodepointIntervalAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList12toSourceCodeMFNeAyaZAya@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals13opIndexAssignMFNaNbNiNeS3std3uni17CodepointIntervalkZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4backMFNaNbNdNiNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4backMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals4saveMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5frontMFNaNbNdNiNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals5frontMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__ctorMFNaNbNcNiNeAkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__ctorMFNaNbNcNiNeAkkkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7opIndexMxFNaNbNiNekZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7opSliceMFNaNbNiNekkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals7popBackMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList19__T13fromIntervalsZ13fromIntervalsFNaNbNeAkXS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList27__T10opOpAssignVAyaa1_7cTkZ10opOpAssignMFNaNbNcNekZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList27__T10opOpAssignVAyaa1_7cTwZ10opOpAssignMFNaNbNcNewZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList52__T13fromIntervalsTS3std3uni21DecompressedIntervalsZ13fromIntervalsFNaNeS3std3uni21DecompressedIntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals11__xopEqualsFKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals13opIndexAssignMFNaNbNeS3std3uni17CodepointIntervalkZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4backMFNaNbNdNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4backMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals4saveMFNaNbNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5frontMFNaNbNdNeS3std3uni17CodepointIntervalZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals5frontMxFNaNbNdNiNeZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__ctorMFNaNbNcNiNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__ctorMFNaNbNcNiNeS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraykkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7opIndexMxFNaNbNiNekZS3std3uni17CodepointInterval@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7opSliceMFNaNbNiNekkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals7popBackMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals8popFrontMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9Intervals9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList73__T3addTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ3addMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList73__T3subTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ3subMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList76__T6__ctorTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ6__ctorMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList79__T9intersectTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ9intersectMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList7opIndexMxFNaNbNiNekZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList7subCharMFNaNbNcNewZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList87__T8opBinaryVAyaa1_26TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ8opBinaryMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList87__T8opBinaryVAyaa1_7cTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ8opBinaryMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8__T3addZ3addMFNaNbNcNekkZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8dropUpToMFNaNbNekkZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8invertedMFNaNbNdNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8opAssignMFNaNbNcNiNjNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ72__T9__lambda1TS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ9__lambda1FNaNbNiNfS3std3uni17CodepointIntervalS3std3uni17CodepointIntervalZb@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8skipUpToMFNaNbNekkZk@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8toStringMFNeMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_26TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_2dTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_7cTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList90__T10opOpAssignVAyaa1_7eTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10opOpAssignMFNaNbNcNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList9__xtoHashFNbNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray10__postblitMFNaNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray11__xopEqualsFKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray13__T8opEqualsZ8opEqualsMxFNaNbNiNeKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray13opIndexAssignMFNekkZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray16dupThisReferenceMFNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray17freeThisReferenceMFNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray5reuseFNeAkZS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__dtorMFNbNiNeZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__initZ@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6lengthMFNdNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMFNeZAk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMFNekkZAk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMxFNaNbNiNeZAxk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray7opSliceMxFNaNbNiNekkZAxk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8opAssignMFNbNcNiNjNeS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8refCountMFNaNbNdNiNekZv@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray8refCountMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray9__xtoHashFNbNeKxS3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArrayZk@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed11__xopEqualsFKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed13opIndexAssignMFNaNbNiNfwkZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4backMFNaNbNdNiNfwZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4backMxFNaNbNdNiNfZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed4saveMNgFNaNbNdNiNfZNgS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5frontMFNaNbNdNiNfwZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed5frontMxFNaNbNdNiNfZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6__initZ@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opIndexMxFNaNbNiNfkZw@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opSliceMFNaNbNiNfZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7opSliceMFNaNbNiNfkkZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed7popBackMFNaNbNiNfZv@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed85__T8opEqualsTxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZ8opEqualsMxFNaNbNiNfKxS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexedZb@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed8opDollarMxFNaNbNiNfZk@Base 6
+ _D3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3uni41__T16sliceOverIndexedTS3std3uni8GraphemeZ16sliceOverIndexedFNaNbNiNfkkPS3std3uni8GraphemeZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni4icmpFNaNfAxaAxaZi@Base 6
+ _D3std3uni4icmpFNaNfAxuAxuZi@Base 6
+ _D3std3uni4icmpFNaNfAxwAxwZi@Base 6
+ _D3std3uni51__T10assumeSizeS28_D3std3uni5low_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D3std3uni52__T10sharMethodS333std3uni23switchUniformLowerBoundZ37__T10sharMethodVAyaa4_613c3d62TAxkTkZ10sharMethodFNaNbNiNfAxkkZk@Base 6
+ _D3std3uni54__T10assumeSizeS31_D3std3uni8midlow_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D3std3uni54__T5forceTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni54__T5forceTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni55__T5forceTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTkZ5forceFNaNbNiNfkZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni5asSetFNaNfAxhZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni5low_8FNaNbNiNfkZk@Base 6
+ _D3std3uni5sicmpFNaNfAxaAxaZi@Base 6
+ _D3std3uni5sicmpFNaNfAxuAxuZi@Base 6
+ _D3std3uni5sicmpFNaNfAxwAxwZi@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray11__xopEqualsFKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayZb@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray12__T3ptrVki0Z3ptrMNgFNaNbNdNiNfZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray12__T3ptrVki1Z3ptrMNgFNaNbNdNiZNgS3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray14__T5sliceVki0Z5sliceMNgFNaNbNdNiNfZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray14__T5sliceVki1Z5sliceMNgFNaNbNdNiZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMFNaNbNdkZv@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki0Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMFNaNbNdNfkZv@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray15__T6lengthVki1Z6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki0Z7raw_ptrMNgFNaNbNdNiNfZPNgk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray16__T7raw_ptrVki1Z7raw_ptrMNgFNaNbNdNiZPNgk@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__ctorMFNaNbNcNfAkXS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__ctorMxFNaNbNcNiNfAxkAxkAxkZxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray9__xtoHashFNbNeKxS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArrayZk@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTkVki7Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni63__T15packedArrayViewTS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki11Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki14Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni64__T15packedArrayViewTS3std3uni21__T9BitPackedTkVki16Z9BitPackedZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl11simpleWriteMFNaNbNiNebkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl13opIndexAssignMFNaNbNiNebkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni6hangLVFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6hangLVFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6isMarkFNaNbNiNfwZb@Base 6
+ _D3std3uni6mcTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6mcTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni6read24FNaNbNiNfxPhkZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl117__T8opEqualsTS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNebkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNebkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl119__T8opEqualsTS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl120__T8opEqualsTxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni73__T19PackedArrayViewImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni78__T14genericReplaceTvTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayTAiZ14genericReplaceFNaNbNeKS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraykkAiZk@Base 6
+ _D3std3uni78__T14genericReplaceTvTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayTAkZ14genericReplaceFNaNbNeKS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArraykkAkZk@Base 6
+ _D3std3uni7composeFNaNbNewwZw@Base 6
+ _D3std3uni7hangLVTFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni7hangLVTFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni7isAlphaFNaNbNiNfwZb@Base 6
+ _D3std3uni7isJamoLFNaNbNiNewZb@Base 6
+ _D3std3uni7isJamoTFNaNbNiNewZb@Base 6
+ _D3std3uni7isJamoVFNaNbNiNewZb@Base 6
+ _D3std3uni7isLowerFNaNbNiNfwZb@Base 6
+ _D3std3uni7isSpaceFNaNbNiNfwZb@Base 6
+ _D3std3uni7isUpperFNaNbNiNfwZb@Base 6
+ _D3std3uni7isWhiteFNaNbNiNfwZb@Base 6
+ _D3std3uni7toLowerFNaNbNiNfwZw@Base 6
+ _D3std3uni7toLowerFNaNfAyaZAya@Base 6
+ _D3std3uni7toLowerFNaNfAyuZAyu@Base 6
+ _D3std3uni7toLowerFNaNfAywZAyw@Base 6
+ _D3std3uni7toUpperFNaNbNiNfwZw@Base 6
+ _D3std3uni7toUpperFNaNfAyaZAya@Base 6
+ _D3std3uni7toUpperFNaNfAyuZAyu@Base 6
+ _D3std3uni7toUpperFNaNfAywZAyw@Base 6
+ _D3std3uni7unicode13__T6opCallTaZ6opCallFNaNfxAaZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode18hangulSyllableType6__initZ@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4c43Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d63Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d65Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4d6eZ10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_4e64Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode27__T10opDispatchVAyaa2_5063Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode44__T10opDispatchVAyaa10_416c7068616265746963Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode46__T10opDispatchVAyaa11_57686974655f5370616365Z10opDispatchFNaNdNfZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode5block6__initZ@Base 6
+ _D3std3uni7unicode6__initZ@Base 6
+ _D3std3uni7unicode6script6__initZ@Base 6
+ _D3std3uni7unicode79__T7loadAnyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ7loadAnyFNaNfxAaZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std3uni7unicode7findAnyFNfAyaZb@Base 6
+ _D3std3uni7write24FNaNbNiNfPhkkZv@Base 6
+ _D3std3uni85__T12loadPropertyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTaZ12loadPropertyFNaNexAaKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std3uni8GcPolicy12__T5allocTkZ5allocFNaNbNekZAk@Base 6
+ _D3std3uni8GcPolicy14__T7reallocTkZ7reallocFNaNbNeAkkZAk@Base 6
+ _D3std3uni8GcPolicy15__T6appendTkTiZ6appendFNaNbNeKAkiZv@Base 6
+ _D3std3uni8GcPolicy15__T7destroyTAkZ7destroyFNaNbNiNeKAkZv@Base 6
+ _D3std3uni8GcPolicy6__initZ@Base 6
+ _D3std3uni8Grapheme10__postblitMFNeZv@Base 6
+ _D3std3uni8Grapheme11smallLengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni8Grapheme12convertToBigMFNeZv@Base 6
+ _D3std3uni8Grapheme13__T6__ctorTiZ6__ctorMFNcNexAiXS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme13__T6__ctorTwZ6__ctorMFNcNexAwXS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme13opIndexAssignMFNaNbNiNewkZv@Base 6
+ _D3std3uni8Grapheme25__T10opOpAssignVAyaa1_7eZ10opOpAssignMFNcNewZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxiZ10opOpAssignMFNcNeAxiZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxwZ10opOpAssignMFNcNeAxwZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme5isBigMxFNaNbNdNiNeZh@Base 6
+ _D3std3uni8Grapheme6__dtorMFNeZv@Base 6
+ _D3std3uni8Grapheme6__initZ@Base 6
+ _D3std3uni8Grapheme6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni8Grapheme6setBigMFNaNbNiNeZv@Base 6
+ _D3std3uni8Grapheme7opIndexMxFNaNbNiNekZw@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNiZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNikkZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme8opAssignMFNcNjNeS3std3uni8GraphemeZS3std3uni8Grapheme@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAakwZk@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAwkwZk@Base 6
+ _D3std3uni8encodeToFNaNeAukwZk@Base 6
+ _D3std3uni8isFormatFNaNbNiNfwZb@Base 6
+ _D3std3uni8isNumberFNaNbNiNfwZb@Base 6
+ _D3std3uni8isSymbolFNaNbNiNfwZb@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8midlow_8FNaNbNiNfkZk@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni20__T9BitPackedTkVki7Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVki7Z9BitPackedZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVki8Z9BitPackedTS3std3uni20__T9BitPackedTkVki8Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVki8Z9BitPackedZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki11Z9BitPackedZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTS3std3uni21__T9BitPackedTkVki12Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki12Z9BitPackedZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki13Z9BitPackedTS3std3uni21__T9BitPackedTkVki13Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki13Z9BitPackedZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki14Z9BitPackedTS3std3uni21__T9BitPackedTkVki14Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki14Z9BitPackedZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki15Z9BitPackedZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVki16Z9BitPackedTS3std3uni21__T9BitPackedTkVki16Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVki16Z9BitPackedZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni97__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAaZ6toCaseFNaNeAaZAa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAxaZ6toCaseFNaNeAxaZAxa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNekZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNekZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9isControlFNaNbNiNfwZb@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9recomposeFNaNbNekAwAhZk@Base 6
+ _D3std3uri10URI_EncodeFAywkZAya@Base 6
+ _D3std3uri12URIException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3uri12URIException@Base 6
+ _D3std3uri12URIException6__initZ@Base 6
+ _D3std3uri12URIException6__vtblZ@Base 6
+ _D3std3uri12URIException7__ClassZ@Base 6
+ _D3std3uri12__ModuleInfoZ@Base 6
+ _D3std3uri18_sharedStaticCtor1FZ6helperFyAakZv@Base 6
+ _D3std3uri18_sharedStaticCtor1FZv@Base 6
+ _D3std3uri9ascii2hexFwZk@Base 6
+ _D3std3uri9hex2asciiyG16a@Base 6
+ _D3std3uri9uri_flagsG128h@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNeKAyaJkZw@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNfKAyaZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFKAaKkZ17__T9exceptionTAaZ9exceptionFNaNfAaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFNaKAaKkZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ10decodeImplFNaKAuKkZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ10decodeImplFNaKAwKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFKAxaKkZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFNaKAxaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ10decodeImplFNaKAxuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ10decodeImplFNaKAxwKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFKAyaKkZ18__T9exceptionTAyaZ9exceptionFNaNfAyaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFNaKAyaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFKxAaKkZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFNaKxAaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ10decodeImplFNaKxAuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ10decodeImplFNaKxAwKkZw@Base 6
+ _D3std3utf10strideImplFNaNeakZk@Base 6
+ _D3std3utf12UTFException11setSequenceMFNaNbNiNfAkXC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNfAyakAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__initZ@Base 6
+ _D3std3utf12UTFException6__vtblZ@Base 6
+ _D3std3utf12UTFException7__ClassZ@Base 6
+ _D3std3utf12UTFException8toStringMFZAya@Base 6
+ _D3std3utf12__ModuleInfoZ@Base 6
+ _D3std3utf12isValidDcharFNaNbNiNfwZb@Base 6
+ _D3std3utf14__T6byCharTAaZ6byCharFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf14__T6strideTAaZ6strideFNaNfAaZk@Base 6
+ _D3std3utf14__T6toUTFzTPaZ15__T6toUTFzTAyaZ6toUTFzFNaNbNfAyaZPa@Base 6
+ _D3std3utf15__T6byCharTAxaZ6byCharFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6byCharTAyaZ6byCharFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfAxakZk@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfKAxakZk@Base 6
+ _D3std3utf15__T6strideTAyaZ6strideFNaNfKAyakZk@Base 6
+ _D3std3utf16__T7byDcharTAyaZ7byDcharFNaNbNiNfAyaZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf17__T8validateTAxaZ8validateFNaNfxAaZv@Base 6
+ _D3std3utf17__T8validateTAxuZ8validateFNaNfxAuZv@Base 6
+ _D3std3utf17__T8validateTAxwZ8validateFNaNfxAwZv@Base 6
+ _D3std3utf18__T10codeLengthTaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTuZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTwZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10toUCSindexTaZ10toUCSindexFNaNfAxakZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10codeLengthTyaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10strideBackTAxaZ10strideBackFNaNfKAxakZk@Base 6
+ _D3std3utf20__T10strideBackTAyaZ10strideBackFNaNfKAyakZk@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAxaZ10toUTFzImplFNaNbNfAxaZPa@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAyaZ10toUTFzImplFNaNbNfAyaZPa@Base 6
+ _D3std3utf28__T20canSearchInCodeUnitsTaZ20canSearchInCodeUnitsFNaNbNiNfwZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNaNbNiNfS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl11__xopEqualsFKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl4saveMFNaNbNdNiNfZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl5frontMFNaNbNdNiNfZa@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl6__ctorMFNaNbNcNiNfKS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl6__initZ@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl9__xtoHashFNbNeKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZk@Base 6
+ _D3std3utf6encodeFNaNfKAawZv@Base 6
+ _D3std3utf6encodeFNaNfKAuwZv@Base 6
+ _D3std3utf6encodeFNaNfKAwwZv@Base 6
+ _D3std3utf6encodeFNaNfKG2uwZk@Base 6
+ _D3std3utf6encodeFNaNfKG4awZk@Base 6
+ _D3std3utf6toUTF8FNaNbNiNfNkJG4awZAa@Base 6
+ _D3std3utf6toUTF8FNaNfxAaZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAuZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAwZAya@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl11__xopEqualsFKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl4saveMFNaNbNdNiNfZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5frontMFNaNbNdNiNfZw@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__ctorMFNaNbNcNiNfKS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl9__xtoHashFNbNeKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZk@Base 6
+ _D3std3utf7toUTF16FNaNbNiNfNkKG2uwZAu@Base 6
+ _D3std3utf7toUTF16FNaNfxAaZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAuZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAwZAyu@Base 6
+ _D3std3utf7toUTF32FNaNfxAaZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAuZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAwZAyw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ6decodeFNaNeKAaKkZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ6decodeFNaNeKAuKkZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ6decodeFNaNeKAwKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ6decodeFNaNeKAxaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ6decodeFNaNeKAxuKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ6decodeFNaNeKAxwKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ6decodeFNaNeKAyaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ6decodeFNaNeKxAaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ6decodeFNaNeKxAuKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ6decodeFNaNeKxAwKkZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNeKAaJkZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNfKAaZw@Base 6
+ _D3std3xml10DigitTableyAi@Base 6
+ _D3std3xml10checkCharsFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkCharsFKAyaZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZv@Base 6
+ _D3std3xml10isBaseCharFwZb@Base 6
+ _D3std3xml10isExtenderFwZb@Base 6
+ _D3std3xml111__T4starS99_D3std3xml76__T3seqS29_D3std3xml10checkSpaceFKAyaZvS33_D3std3xml14checkAttributeFKAyaZvZ3seqFKAyaZvZ4starFKAyaZv@Base 6
+ _D3std3xml112__T3seqS35_D3std3xml16checkDocTypeDeclFKAyaZvS63_D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZvZ3seqFKAyaZv@Base 6
+ _D3std3xml11PIException6__ctorMFAyaZC3std3xml11PIException@Base 6
+ _D3std3xml11PIException6__initZ@Base 6
+ _D3std3xml11PIException6__vtblZ@Base 6
+ _D3std3xml11PIException7__ClassZ@Base 6
+ _D3std3xml11XIException6__ctorMFAyaZC3std3xml11XIException@Base 6
+ _D3std3xml11XIException6__initZ@Base 6
+ _D3std3xml11XIException6__vtblZ@Base 6
+ _D3std3xml11XIException7__ClassZ@Base 6
+ _D3std3xml11checkCDSectFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkCDSectFKAyaZv@Base 6
+ _D3std3xml11checkPrologFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkPrologFKAyaZv@Base 6
+ _D3std3xml11checkSDDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml11checkSDDeclFKAyaZv@Base 6
+ _D3std3xml12TagException6__ctorMFAyaZC3std3xml12TagException@Base 6
+ _D3std3xml12TagException6__initZ@Base 6
+ _D3std3xml12TagException6__vtblZ@Base 6
+ _D3std3xml12TagException7__ClassZ@Base 6
+ _D3std3xml12XMLException6__ctorMFAyaZC3std3xml12XMLException@Base 6
+ _D3std3xml12XMLException6__initZ@Base 6
+ _D3std3xml12XMLException6__vtblZ@Base 6
+ _D3std3xml12XMLException7__ClassZ@Base 6
+ _D3std3xml12__ModuleInfoZ@Base 6
+ _D3std3xml12checkCharRefFKAyaJwZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkCharRefFKAyaJwZv@Base 6
+ _D3std3xml12checkCommentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkCommentFKAyaZv@Base 6
+ _D3std3xml12checkContentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkContentFKAyaZv@Base 6
+ _D3std3xml12checkElementFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkElementFKAyaZv@Base 6
+ _D3std3xml12checkEncNameFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkEncNameFKAyaZv@Base 6
+ _D3std3xml12checkLiteralFAyaKAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkLiteralFAyaKAyaZv@Base 6
+ _D3std3xml12checkXMLDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml12checkXMLDeclFKAyaZv@Base 6
+ _D3std3xml13BaseCharTableyAi@Base 6
+ _D3std3xml13ElementParser3tagMxFNdZxC3std3xml3Tag@Base 6
+ _D3std3xml13ElementParser4onPIMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser4onXIMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser5parseMFZv@Base 6
+ _D3std3xml13ElementParser6__ctorMFC3std3xml13ElementParserZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__ctorMFC3std3xml3TagPAyaZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__ctorMFZC3std3xml13ElementParser@Base 6
+ _D3std3xml13ElementParser6__initZ@Base 6
+ _D3std3xml13ElementParser6__vtblZ@Base 6
+ _D3std3xml13ElementParser6onTextMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser7__ClassZ@Base 6
+ _D3std3xml13ElementParser7onCDataMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser8toStringMxFZAya@Base 6
+ _D3std3xml13ElementParser9onCommentMFNdDFAyaZvZv@Base 6
+ _D3std3xml13ElementParser9onTextRawMFDFAyaZvZv@Base 6
+ _D3std3xml13ExtenderTableyAi@Base 6
+ _D3std3xml13TextException6__ctorMFAyaZC3std3xml13TextException@Base 6
+ _D3std3xml13TextException6__initZ@Base 6
+ _D3std3xml13TextException6__vtblZ@Base 6
+ _D3std3xml13TextException7__ClassZ@Base 6
+ _D3std3xml13checkAttValueFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkAttValueFKAyaZv@Base 6
+ _D3std3xml13checkCharDataFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkCharDataFKAyaZv@Base 6
+ _D3std3xml13checkDocumentFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml13checkDocumentFKAyaZv@Base 6
+ _D3std3xml13isIdeographicFwZb@Base 6
+ _D3std3xml148__T3optS136_D3std3xml112__T3seqS35_D3std3xml16checkDocTypeDeclFKAyaZvS63_D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZvZ3seqFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml14CDataException6__ctorMFAyaZC3std3xml14CDataException@Base 6
+ _D3std3xml14CDataException6__initZ@Base 6
+ _D3std3xml14CDataException6__vtblZ@Base 6
+ _D3std3xml14CDataException7__ClassZ@Base 6
+ _D3std3xml14CheckException6__ctorMFAyaAyaC3std3xml14CheckExceptionZC3std3xml14CheckException@Base 6
+ _D3std3xml14CheckException6__initZ@Base 6
+ _D3std3xml14CheckException6__vtblZ@Base 6
+ _D3std3xml14CheckException7__ClassZ@Base 6
+ _D3std3xml14CheckException8completeMFAyaZv@Base 6
+ _D3std3xml14CheckException8toStringMxFZAya@Base 6
+ _D3std3xml14DocumentParser6__ctorMFAyaZC3std3xml14DocumentParser@Base 6
+ _D3std3xml14DocumentParser6__initZ@Base 6
+ _D3std3xml14DocumentParser6__vtblZ@Base 6
+ _D3std3xml14DocumentParser7__ClassZ@Base 6
+ _D3std3xml14XMLInstruction10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml14XMLInstruction5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml14XMLInstruction6__ctorMFAyaZC3std3xml14XMLInstruction@Base 6
+ _D3std3xml14XMLInstruction6__initZ@Base 6
+ _D3std3xml14XMLInstruction6__vtblZ@Base 6
+ _D3std3xml14XMLInstruction6toHashMxFNbNfZk@Base 6
+ _D3std3xml14XMLInstruction7__ClassZ@Base 6
+ _D3std3xml14XMLInstruction8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml14XMLInstruction8toStringMxFZAya@Base 6
+ _D3std3xml14checkAttributeFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkAttributeFKAyaZv@Base 6
+ _D3std3xml14checkEntityRefFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkEntityRefFKAyaZv@Base 6
+ _D3std3xml14checkReferenceFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml14checkReferenceFKAyaZv@Base 6
+ _D3std3xml15DecodeException6__ctorMFAyaZC3std3xml15DecodeException@Base 6
+ _D3std3xml15DecodeException6__initZ@Base 6
+ _D3std3xml15DecodeException6__vtblZ@Base 6
+ _D3std3xml15DecodeException7__ClassZ@Base 6
+ _D3std3xml15__T6encodeTAyaZ6encodeFNaNbNfAyaZAya@Base 6
+ _D3std3xml15checkVersionNumFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml15checkVersionNumFKAyaZv@Base 6
+ _D3std3xml15isCombiningCharFwZb@Base 6
+ _D3std3xml16CommentException6__ctorMFAyaZC3std3xml16CommentException@Base 6
+ _D3std3xml16CommentException6__initZ@Base 6
+ _D3std3xml16CommentException6__vtblZ@Base 6
+ _D3std3xml16CommentException7__ClassZ@Base 6
+ _D3std3xml16IdeographicTableyAi@Base 6
+ _D3std3xml16checkDocTypeDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml16checkDocTypeDeclFKAyaZv@Base 6
+ _D3std3xml16checkVersionInfoFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml16checkVersionInfoFKAyaZv@Base 6
+ _D3std3xml17checkEncodingDeclFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml17checkEncodingDeclFKAyaZv@Base 6
+ _D3std3xml18CombiningCharTableyAi@Base 6
+ _D3std3xml20InvalidTypeException6__ctorMFAyaZC3std3xml20InvalidTypeException@Base 6
+ _D3std3xml20InvalidTypeException6__initZ@Base 6
+ _D3std3xml20InvalidTypeException6__vtblZ@Base 6
+ _D3std3xml20InvalidTypeException7__ClassZ@Base 6
+ _D3std3xml21ProcessingInstruction10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml21ProcessingInstruction5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml21ProcessingInstruction6__ctorMFAyaZC3std3xml21ProcessingInstruction@Base 6
+ _D3std3xml21ProcessingInstruction6__initZ@Base 6
+ _D3std3xml21ProcessingInstruction6__vtblZ@Base 6
+ _D3std3xml21ProcessingInstruction6toHashMxFNbNfZk@Base 6
+ _D3std3xml21ProcessingInstruction7__ClassZ@Base 6
+ _D3std3xml21ProcessingInstruction8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml21ProcessingInstruction8toStringMxFZAya@Base 6
+ _D3std3xml26__T6toTypeTxC3std3xml3TagZ6toTypeFC6ObjectZxC3std3xml3Tag@Base 6
+ _D3std3xml27__T6toTypeTxC3std3xml4ItemZ6toTypeFC6ObjectZxC3std3xml4Item@Base 6
+ _D3std3xml30__T6toTypeTxC3std3xml7ElementZ6toTypeFC6ObjectZxC3std3xml7Element@Base 6
+ _D3std3xml31__T6toTypeTxC3std3xml8DocumentZ6toTypeFC6ObjectZxC3std3xml8Document@Base 6
+ _D3std3xml39__T4starS27_D3std3xml9checkMiscFKAyaZvZ4starFKAyaZv@Base 6
+ _D3std3xml3Tag11__invariantMxFZv@Base 6
+ _D3std3xml3Tag11toEndStringMxFZAya@Base 6
+ _D3std3xml3Tag12__invariant6MxFZv@Base 6
+ _D3std3xml3Tag13toEmptyStringMxFZAya@Base 6
+ _D3std3xml3Tag13toStartStringMxFZAya@Base 6
+ _D3std3xml3Tag14toNonEndStringMxFZAya@Base 6
+ _D3std3xml3Tag5isEndMxFNdZb@Base 6
+ _D3std3xml3Tag5opCmpMxFC6ObjectZi@Base 6
+ _D3std3xml3Tag6__ctorMFAyaE3std3xml7TagTypeZC3std3xml3Tag@Base 6
+ _D3std3xml3Tag6__ctorMFKAyabZC3std3xml3Tag@Base 6
+ _D3std3xml3Tag6__initZ@Base 6
+ _D3std3xml3Tag6__vtblZ@Base 6
+ _D3std3xml3Tag6toHashMxFNbNfZk@Base 6
+ _D3std3xml3Tag7__ClassZ@Base 6
+ _D3std3xml3Tag7isEmptyMxFNdZb@Base 6
+ _D3std3xml3Tag7isStartMxFNdZb@Base 6
+ _D3std3xml3Tag8opEqualsMxFC6ObjectZb@Base 6
+ _D3std3xml3Tag8toStringMxFZAya@Base 6
+ _D3std3xml40__T3optS29_D3std3xml10checkSpaceFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml41__T3optS30_D3std3xml11checkSDDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml42__T3optS31_D3std3xml12checkXMLDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml45__T6quotedS31_D3std3xml12checkEncNameFKAyaZvZ6quotedFKAyaZv@Base 6
+ _D3std3xml47__T3optS36_D3std3xml17checkEncodingDeclFKAyaZvZ3optFKAyaZv@Base 6
+ _D3std3xml48__T6quotedS34_D3std3xml15checkVersionNumFKAyaZvZ6quotedFKAyaZv@Base 6
+ _D3std3xml4Item6__initZ@Base 6
+ _D3std3xml4Item6__vtblZ@Base 6
+ _D3std3xml4Item6prettyMxFkZAAya@Base 6
+ _D3std3xml4Item7__ClassZ@Base 6
+ _D3std3xml4Text10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml4Text5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml4Text6__ctorMFAyaZC3std3xml4Text@Base 6
+ _D3std3xml4Text6__initZ@Base 6
+ _D3std3xml4Text6__vtblZ@Base 6
+ _D3std3xml4Text6toHashMxFNbNfZk@Base 6
+ _D3std3xml4Text7__ClassZ@Base 6
+ _D3std3xml4Text8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml4Text8toStringMxFZAya@Base 6
+ _D3std3xml4chopFKAyakZAya@Base 6
+ _D3std3xml4exitFAyaZv@Base 6
+ _D3std3xml4hashFNbNeAyakZk@Base 6
+ _D3std3xml4optcFKAyaaZb@Base 6
+ _D3std3xml4reqcFKAyaaZv@Base 6
+ _D3std3xml5CData10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml5CData5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml5CData6__ctorMFAyaZC3std3xml5CData@Base 6
+ _D3std3xml5CData6__initZ@Base 6
+ _D3std3xml5CData6__vtblZ@Base 6
+ _D3std3xml5CData6toHashMxFNbNfZk@Base 6
+ _D3std3xml5CData7__ClassZ@Base 6
+ _D3std3xml5CData8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml5CData8toStringMxFZAya@Base 6
+ _D3std3xml5checkFAyaZv@Base 6
+ _D3std3xml6decodeFAyaE3std3xml10DecodeModeZAya@Base 6
+ _D3std3xml6isCharFwZb@Base 6
+ _D3std3xml6lookupFAxiiZb@Base 6
+ _D3std3xml76__T3seqS29_D3std3xml10checkSpaceFKAyaZvS33_D3std3xml14checkAttributeFKAyaZvZ3seqFKAyaZv@Base 6
+ _D3std3xml7Comment10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml7Comment5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml7Comment6__ctorMFAyaZC3std3xml7Comment@Base 6
+ _D3std3xml7Comment6__initZ@Base 6
+ _D3std3xml7Comment6__vtblZ@Base 6
+ _D3std3xml7Comment6toHashMxFNbNfZk@Base 6
+ _D3std3xml7Comment7__ClassZ@Base 6
+ _D3std3xml7Comment8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml7Comment8toStringMxFZAya@Base 6
+ _D3std3xml7Element10appendItemMFC3std3xml4ItemZv@Base 6
+ _D3std3xml7Element10isEmptyXMLMxFNdZb@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml21ProcessingInstructionZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml4TextZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml5CDataZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml7CommentZv@Base 6
+ _D3std3xml7Element11opCatAssignMFC3std3xml7ElementZv@Base 6
+ _D3std3xml7Element4textMxFE3std3xml10DecodeModeZAya@Base 6
+ _D3std3xml7Element5opCmpMFC6ObjectZi@Base 6
+ _D3std3xml7Element5parseMFC3std3xml13ElementParserZv@Base 6
+ _D3std3xml7Element6__ctorMFAyaAyaZC3std3xml7Element@Base 6
+ _D3std3xml7Element6__ctorMFxC3std3xml3TagZC3std3xml7Element@Base 6
+ _D3std3xml7Element6__initZ@Base 6
+ _D3std3xml7Element6__vtblZ@Base 6
+ _D3std3xml7Element6prettyMxFkZAAya@Base 6
+ _D3std3xml7Element6toHashMxFNbNfZk@Base 6
+ _D3std3xml7Element7__ClassZ@Base 6
+ _D3std3xml7Element8opEqualsMFC6ObjectZb@Base 6
+ _D3std3xml7Element8toStringMxFZAya@Base 6
+ _D3std3xml7checkEqFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml7checkEqFKAyaZv@Base 6
+ _D3std3xml7checkPIFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml7checkPIFKAyaZv@Base 6
+ _D3std3xml7isDigitFwZb@Base 6
+ _D3std3xml7isSpaceFwZb@Base 6
+ _D3std3xml7startOfFAyaZAya@Base 6
+ _D3std3xml8Document5opCmpMxFC6ObjectZi@Base 6
+ _D3std3xml8Document6__ctorMFAyaZC3std3xml8Document@Base 6
+ _D3std3xml8Document6__ctorMFxC3std3xml3TagZC3std3xml8Document@Base 6
+ _D3std3xml8Document6__initZ@Base 6
+ _D3std3xml8Document6__vtblZ@Base 6
+ _D3std3xml8Document6toHashMxFNbNeZk@Base 6
+ _D3std3xml8Document7__ClassZ@Base 6
+ _D3std3xml8Document8opEqualsMxFC6ObjectZb@Base 6
+ _D3std3xml8Document8toStringMxFZAya@Base 6
+ _D3std3xml8checkEndFAyaKAyaZv@Base 6
+ _D3std3xml8checkTagFKAyaJAyaJAyaZ8__mixin44failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml8checkTagFKAyaJAyaJAyaZv@Base 6
+ _D3std3xml8isLetterFwZb@Base 6
+ _D3std3xml9CharTableyAi@Base 6
+ _D3std3xml9checkETagFKAyaJAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkETagFKAyaJAyaZv@Base 6
+ _D3std3xml9checkMiscFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkMiscFKAyaZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZ8__mixin34failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZ8__mixin34failMFZv@Base 6
+ _D3std3xml9checkNameFKAyaJAyaZv@Base 6
+ _D3std3zip10ZipArchive10diskNumberMFNdZk@Base 6
+ _D3std3zip10ZipArchive10numEntriesMFNdZk@Base 6
+ _D3std3zip10ZipArchive12deleteMemberMFC3std3zip13ArchiveMemberZv@Base 6
+ _D3std3zip10ZipArchive12diskStartDirMFNdZk@Base 6
+ _D3std3zip10ZipArchive12eocd64Lengthxi@Base 6
+ _D3std3zip10ZipArchive12totalEntriesMFNdZk@Base 6
+ _D3std3zip10ZipArchive14digiSignLengthxi@Base 6
+ _D3std3zip10ZipArchive15eocd64LocLengthxi@Base 6
+ _D3std3zip10ZipArchive19zip64ExtractVersionxt@Base 6
+ _D3std3zip10ZipArchive4dataMFNdZAh@Base 6
+ _D3std3zip10ZipArchive5buildMFZAv@Base 6
+ _D3std3zip10ZipArchive6__ctorMFAvZC3std3zip10ZipArchive@Base 6
+ _D3std3zip10ZipArchive6__ctorMFZC3std3zip10ZipArchive@Base 6
+ _D3std3zip10ZipArchive6__initZ@Base 6
+ _D3std3zip10ZipArchive6__vtblZ@Base 6
+ _D3std3zip10ZipArchive6expandMFC3std3zip13ArchiveMemberZAh@Base 6
+ _D3std3zip10ZipArchive7__ClassZ@Base 6
+ _D3std3zip10ZipArchive7getUintMFiZk@Base 6
+ _D3std3zip10ZipArchive7isZip64MFNdZb@Base 6
+ _D3std3zip10ZipArchive7isZip64MFNdbZv@Base 6
+ _D3std3zip10ZipArchive7putUintMFikZv@Base 6
+ _D3std3zip10ZipArchive8getUlongMFiZm@Base 6
+ _D3std3zip10ZipArchive8putUlongMFimZv@Base 6
+ _D3std3zip10ZipArchive9addMemberMFC3std3zip13ArchiveMemberZv@Base 6
+ _D3std3zip10ZipArchive9directoryMFNdZHAyaC3std3zip13ArchiveMember@Base 6
+ _D3std3zip10ZipArchive9getUshortMFiZt@Base 6
+ _D3std3zip10ZipArchive9putUshortMFitZv@Base 6
+ _D3std3zip12ZipException6__ctorMFAyaZC3std3zip12ZipException@Base 6
+ _D3std3zip12ZipException6__initZ@Base 6
+ _D3std3zip12ZipException6__vtblZ@Base 6
+ _D3std3zip12ZipException7__ClassZ@Base 6
+ _D3std3zip12__ModuleInfoZ@Base 6
+ _D3std3zip13ArchiveMember10diskNumberMFNdZt@Base 6
+ _D3std3zip13ArchiveMember11madeVersionMNgFNaNbNcNdNfZNgt@Base 6
+ _D3std3zip13ArchiveMember12expandedDataMFNdAhZv@Base 6
+ _D3std3zip13ArchiveMember12expandedDataMFNdZAh@Base 6
+ _D3std3zip13ArchiveMember12expandedSizeMFNdZk@Base 6
+ _D3std3zip13ArchiveMember14compressedDataMFNdZAh@Base 6
+ _D3std3zip13ArchiveMember14compressedSizeMFNdZk@Base 6
+ _D3std3zip13ArchiveMember14extractVersionMFNdZt@Base 6
+ _D3std3zip13ArchiveMember14fileAttributesMFNdkZv@Base 6
+ _D3std3zip13ArchiveMember14fileAttributesMxFNdZk@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdE3std3zip17CompressionMethodZv@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdZE3std3zip17CompressionMethod@Base 6
+ _D3std3zip13ArchiveMember17compressionMethodMFNdtZv@Base 6
+ _D3std3zip13ArchiveMember18externalAttributesMNgFNaNbNcNdNfZNgk@Base 6
+ _D3std3zip13ArchiveMember4timeMFNdS3std8datetime7SysTimeZv@Base 6
+ _D3std3zip13ArchiveMember4timeMFNdkZv@Base 6
+ _D3std3zip13ArchiveMember4timeMxFNdZk@Base 6
+ _D3std3zip13ArchiveMember5crc32MFNdZk@Base 6
+ _D3std3zip13ArchiveMember6__initZ@Base 6
+ _D3std3zip13ArchiveMember6__vtblZ@Base 6
+ _D3std3zip13ArchiveMember7__ClassZ@Base 6
+ _D3std4conv103__T7emplaceTC3std12experimental6logger4core16StdForwardLoggerTE3std12experimental6logger4core8LogLevelZ7emplaceFAvE3std12experimental6logger4core8LogLevelZC3std12experimental6logger4core16StdForwardLogger@Base 6
+ _D3std4conv104__T8textImplTAyaTAyaTPvTAyaTiTAyaTiTAyaTaTAyaThTAyaThTAyaTbTAyaTbTAyaTbTAyaTbTAyaTbTAyaTAxaTAyaTAxaTAyaZ8textImplFNaNfAyaPvAyaiAyaiAyaaAyahAyahAyabAyabAyabAyabAyabAyaAxaAyaAxaAyaZAya@Base 6
+ _D3std4conv10parseErrorFNaNfLAyaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTAaZ2toFNaNbNfAaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTPaZ2toFNaNbPaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTPvZ2toFNaNfPvZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxaZ2toFNaNfxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxdZ2toFNfxdZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxlZ2toFNaNbNfxlZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTxmZ2toFNaNbNfxmZAya@Base 6
+ _D3std4conv11__T2toTAyaZ10__T2toTyhZ2toFNaNbNfyhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ114__T2toTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ2toFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAxaZ2toFNaNbNfAxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAyaZ2toFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTAyhZ2toFNaNfAyhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTPxaZ2toFNaNbPxaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ11__T2toTPxhZ2toFNaNfPxhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ30__T2toTS3std11concurrency3TidZ2toFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv11__T2toTAyaZ34__T2toTE3std5regex8internal2ir2IRZ2toFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv11__T2toTAyaZ34__T2toTE3std6socket12SocketOptionZ2toFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv11__T2toTAyaZ41__T2toTPS3std11parallelism12AbstractTaskZ2toFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv11__T2toTAyaZ42__T2toTC3std11concurrency14LinkTerminatedZ2toFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv11__T2toTAyaZ43__T2toTC3std11concurrency15OwnerTerminatedZ2toFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTaZ2toFNaNfaZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTbZ2toFNaNbNiNfbZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toThZ2toFNaNbNfhZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTiZ2toFNaNbNfiZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTkZ2toFNaNbNfkZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTtZ2toFNaNbNftZAya@Base 6
+ _D3std4conv11__T2toTAyaZ9__T2toTwZ2toFNaNfwZAya@Base 6
+ _D3std4conv121__T5toStrTAyaTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5toStrFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv121__T7emplaceTC3std12experimental6logger10filelogger10FileLoggerTS3std5stdio4FileTE3std12experimental6logger4core8LogLevelZ7emplaceFAvKS3std5stdio4FileE3std12experimental6logger4core8LogLevelZC3std12experimental6logger10filelogger10FileLogger@Base 6
+ _D3std4conv122__T6toImplTAyaTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ6toImplFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZAya@Base 6
+ _D3std4conv12__ModuleInfoZ@Base 6
+ _D3std4conv13ConvException6__ctorMFNaNbNfAyaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv13ConvException6__initZ@Base 6
+ _D3std4conv13ConvException6__vtblZ@Base 6
+ _D3std4conv13ConvException7__ClassZ@Base 6
+ _D3std4conv13__T4textTAyaZ4textFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv15__T4textTAyaTaZ4textFNaNfAyaaZAya@Base 6
+ _D3std4conv15__T6toImplTiThZ6toImplFNaNbNiNfhZi@Base 6
+ _D3std4conv15__T6toImplTiTiZ6toImplFNaNbNiNfiZi@Base 6
+ _D3std4conv15__T6toImplTiTkZ6toImplFNaNfkZi@Base 6
+ _D3std4conv15__T6toImplTiTlZ6toImplFNaNflZi@Base 6
+ _D3std4conv15__T6toImplTiTlZ6toImplFlZ16__T9__lambda2TlZ9__lambda2FNaNbNiNeKlZi@Base 6
+ _D3std4conv15__T6toImplTiTsZ6toImplFNaNbNiNfsZi@Base 6
+ _D3std4conv15__T6toImplTiTtZ6toImplFNaNbNiNftZi@Base 6
+ _D3std4conv15__T6toImplTkTkZ6toImplFNaNbNiNfkZk@Base 6
+ _D3std4conv15__T6toImplTkTlZ6toImplFNaNflZk@Base 6
+ _D3std4conv15__T6toImplTkTlZ6toImplFlZ16__T9__lambda2TlZ9__lambda2FNaNbNiNeKlZk@Base 6
+ _D3std4conv15__T6toImplTkTmZ6toImplFNaNfmZk@Base 6
+ _D3std4conv15__T6toImplTkTmZ6toImplFmZ16__T9__lambda2TmZ9__lambda2FNaNbNiNeKmZk@Base 6
+ _D3std4conv15__T6toImplTlTmZ6toImplFNaNfmZl@Base 6
+ _D3std4conv15__T6toImplTmTkZ6toImplFNaNbNiNfkZm@Base 6
+ _D3std4conv15__T8unsignedThZ8unsignedFNaNbNiNfhZh@Base 6
+ _D3std4conv15__T8unsignedTiZ8unsignedFNaNbNiNfiZk@Base 6
+ _D3std4conv15__T8unsignedTkZ8unsignedFNaNbNiNfkZk@Base 6
+ _D3std4conv15__T8unsignedTtZ8unsignedFNaNbNiNftZt@Base 6
+ _D3std4conv16__T4textTAyaTxaZ4textFNaNfAyaxaZAya@Base 6
+ _D3std4conv16__T5parseThTAxaZ5parseFNaNfKAxaZh@Base 6
+ _D3std4conv16__T5parseThTAxaZ5parseFNaNfKAxakZh@Base 6
+ _D3std4conv16__T5parseTiTAxaZ5parseFNaNfKAxaZi@Base 6
+ _D3std4conv16__T5parseTkTAxaZ5parseFNaNfKAxaZk@Base 6
+ _D3std4conv16__T5parseTtTAxaZ5parseFNaNfKAxaZt@Base 6
+ _D3std4conv16__T5toStrTAyaTaZ5toStrFNaNfaZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTbZ5toStrFNaNbNiNfbZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTwZ5toStrFNaNfwZAya@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFNaNfxkZh@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFxkZ17__T9__lambda2TxkZ9__lambda2FNaNbNiNeKxkZh@Base 6
+ _D3std4conv16__T6toImplTiTxhZ6toImplFNaNbNiNfxhZi@Base 6
+ _D3std4conv16__T6toImplTiTxkZ6toImplFNaNfxkZi@Base 6
+ _D3std4conv16__T6toImplTiTxsZ6toImplFNaNbNiNfxsZi@Base 6
+ _D3std4conv16__T6toImplTiTykZ6toImplFNaNfykZi@Base 6
+ _D3std4conv16__T8unsignedTxkZ8unsignedFNaNbNiNfxkZk@Base 6
+ _D3std4conv16__T8unsignedTxlZ8unsignedFNaNbNiNfxlZm@Base 6
+ _D3std4conv16__T8unsignedTxmZ8unsignedFNaNbNiNfxmZm@Base 6
+ _D3std4conv16__T8unsignedTyhZ8unsignedFNaNbNiNfyhZh@Base 6
+ _D3std4conv16testEmplaceChunkFNaNbNiAvkkAyaZv@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ69__T11emplaceImplTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv17__T4textTAyaTAxaZ4textFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv17__T4textTAyaTAyaZ4textFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTPvZ5toStrFNaNfPvZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxaZ5toStrFNaNfxaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxdZ5toStrFNfxdZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTaZ6toImplFNaNfaZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTbZ6toImplFNaNbNiNfbZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNehkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNfhZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNeikE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNfiZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNekkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNfkZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNetkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNftZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTwZ6toImplFNaNfwZAya@Base 6
+ _D3std4conv17__T6toImplTtTAxaZ6toImplFNaNfAxaZt@Base 6
+ _D3std4conv181__T18emplaceInitializerTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ18emplaceInitializerFNaNbNcNiNeKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv18__T5toStrTAyaTAyhZ5toStrFNaNfAyhZAya@Base 6
+ _D3std4conv18__T5toStrTAyaTPxhZ5toStrFNaNfPxhZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTAaZ6toImplFNaNbNfAaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPaZ6toImplFNaNbPaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPvZ6toImplFNaNfPvZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxaZ6toImplFNaNfxaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxdZ6toImplFNfxdZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNexlkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNfxlZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNexmkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNfxmZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNeyhkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNfyhZAya@Base 6
+ _D3std4conv19__T11emplaceImplTaZ19__T11emplaceImplTaZ11emplaceImplFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv19__T11emplaceImplThZ19__T11emplaceImplThZ11emplaceImplFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv19__T11emplaceImplTwZ19__T11emplaceImplTwZ11emplaceImplFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv19__T4textTAyaTAyaTkZ4textFNaNbNfAyaAyakZAya@Base 6
+ _D3std4conv19__T4textTAyaTkTAyaZ4textFNaNbNfAyakAyaZAya@Base 6
+ _D3std4conv19__T4textTAyaTwTAyaZ4textFNaNfAyawAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAxaZ6toImplFNaNbNfAxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyaZ6toImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyhZ6toImplFNaNfAyhZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxaZ6toImplFNaNbPxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxhZ6toImplFNaNfPxhZAya@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaaZa@Base 6
+ _D3std4conv20__T10emplaceRefThThZ10emplaceRefFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv20__T10emplaceRefTwTwZ10emplaceRefFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv20__T11emplaceImplTxaZ20__T11emplaceImplTxaZ11emplaceImplFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv20__T4textTAyaTxaTAyaZ4textFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv20__T9convErrorTAxaThZ9convErrorFNaNfAxaiAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTiZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTkZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTtZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20isOctalLiteralStringFAyaZb@Base 6
+ _D3std4conv20strippedOctalLiteralFAyaZAya@Base 6
+ _D3std4conv21ConvOverflowException6__ctorMFNaNbNfAyaAyakZC3std4conv21ConvOverflowException@Base 6
+ _D3std4conv21ConvOverflowException6__initZ@Base 6
+ _D3std4conv21ConvOverflowException6__vtblZ@Base 6
+ _D3std4conv21ConvOverflowException7__ClassZ@Base 6
+ _D3std4conv21__T11emplaceImplTAxaZ21__T11emplaceImplTAxaZ11emplaceImplFNaNbNcNiNfKAxaKAxaZAxa@Base 6
+ _D3std4conv21__T11emplaceImplTAyaZ21__T11emplaceImplTAyaZ11emplaceImplFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv21__T4textTAxaTAyaTAxaZ4textFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAxaTAyaZ4textFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAyaTAyaZ4textFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTkTAyaTkZ4textFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv21__T4textTPxhTAyaTPxhZ4textFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv21__T8textImplTAyaTAyaZ8textImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv221__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv23__T8textImplTAyaTAyaTaZ8textImplFNaNfAyaaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTAyaTAyaZ10emplaceRefFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTxaTaTxaZ10emplaceRefFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv24__T8textImplTAyaTAyaTxaZ8textImplFNaNfAyaxaZAya@Base 6
+ _D3std4conv25__T4textTAyaTkTAyaTkTAyaZ4textFNaNbNfAyakAyakAyaZAya@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363630Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363636Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_373737Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAxaZ8textImplFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv27__T4textTAyaTAyaTAyaTiTAyaZ4textFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTAyaTkZ8textImplFNaNbNfAyaAyakZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTkTAyaZ8textImplFNaNbNfAyakAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTwTAyaZ8textImplFNaNfAyawAyaZAya@Base 6
+ _D3std4conv28__T8textImplTAyaTAyaTxaTAyaZ8textImplFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTAyaTAxaTAyaZ4textFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTiTAyaTiTAyaZ4textFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAxaTAyaTAxaZ8textImplFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTkTAyaTkZ8textImplFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTPxhTAyaTPxhZ8textImplFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv30__T20convError_unexpectedTAxaZ20convError_unexpectedFNaNfAxaZAya@Base 6
+ _D3std4conv326__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv33__T8textImplTAyaTAyaTkTAyaTkTAyaZ8textImplFNaNbNfAyakAyakAyaZAya@Base 6
+ _D3std4conv34__T6toImplTiTE3std8datetime5MonthZ6toImplFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T6toImplTiTxE3std8datetime5MonthZ6toImplFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T8textImplTAyaTAyaTAyaTAyaTiTAyaZ8textImplFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv36__T4textTE3std5regex8internal2ir2IRZ4textFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv36__T7emplaceTS3std3net4curl3FTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl3FTP4ImplZPS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv37__T11emplaceImplTS3std4file8DirEntryZ37__T11emplaceImplTS3std4file8DirEntryZ11emplaceImplFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv37__T5toStrTAyaTS3std11concurrency3TidZ5toStrFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4HTTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4HTTP4ImplZPS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4SMTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4SMTP4ImplZPS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTiTAyaTiTAyaZ8textImplFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv38__T6toImplTAyaTS3std11concurrency3TidZ6toImplFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv40__T7emplaceTS3std4file15DirIteratorImplZ7emplaceFNaNbNiNfPS3std4file15DirIteratorImplZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv41__T11emplaceImplTS3std3net4curl3FTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std5regex8internal2ir2IRZ5toStrFNaNfE3std5regex8internal2ir2IRZyAa@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std6socket12SocketOptionZ5toStrFNaNfE3std6socket12SocketOptionZyAa@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4HTTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4SMTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std5regex8internal2ir2IRZ6toImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std6socket12SocketOptionZ6toImplFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv43__T11emplaceImplTS3std6socket11AddressInfoZ43__T11emplaceImplTS3std6socket11AddressInfoZ11emplaceImplFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv44__T8textImplTAyaTE3std5regex8internal2ir2IRZ8textImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ43__T11emplaceImplTAyaTE3std4file8SpanModeTbZ11emplaceImplFNcKS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv46__T11emplaceImplTS3std3uni17CodepointIntervalZ46__T11emplaceImplTS3std3uni17CodepointIntervalZ11emplaceImplFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl3FTP4ImplZ4inityS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T5toStrTAyaTPS3std11parallelism12AbstractTaskZ5toStrFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv48__T6toImplTiTE3std3net7isemail15EmailStatusCodeZ6toImplFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4HTTP4ImplZ4inityS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4SMTP4ImplZ4inityS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T5toStrTAyaTC3std11concurrency14LinkTerminatedZ5toStrFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv49__T6toImplTAyaTPS3std11parallelism12AbstractTaskZ6toImplFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv50__T5toStrTAyaTC3std11concurrency15OwnerTerminatedZ5toStrFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv50__T6toImplTAyaTC3std11concurrency14LinkTerminatedZ6toImplFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv51__T6toImplTAyaTC3std11concurrency15OwnerTerminatedZ6toImplFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNeKS3std4file15DirIteratorImplZ4inityS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNiNeKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv56__T10emplaceRefTS3std4file8DirEntryTS3std4file8DirEntryZ10emplaceRefFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir12__T5RegexTaZ5RegexKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std4conv65__T6toImplTiTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6toImplFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv66__T7emplaceTS3std4file15DirIteratorImplTAyaTE3std4file8SpanModeTbZ7emplaceFPS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv68__T10emplaceRefTS3std6socket11AddressInfoTS3std6socket11AddressInfoZ10emplaceRefFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni1Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni2Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni3Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni4Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni5Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni6Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni7Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni8Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni9Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni10Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni13Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni16Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni17Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni18Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni19Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni20Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni21Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni26Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni30Z7enumRepyAa@Base 6
+ _D3std4conv74__T10emplaceRefTS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ10emplaceRefFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi128Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi129Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi130Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi132Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi133Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi134Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi136Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi137Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi138Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi140Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi141Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi142Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi144Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi145Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi146Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi148Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi149Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi150Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi152Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi153Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi154Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi156Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi157Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi158Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi160Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi161Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi162Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi164Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi168Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi172Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi176Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi180Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi184Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi188Z7enumRepyAa@Base 6
+ _D3std4conv79__T4textTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ4textFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv82__T10emplaceRefTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv87__T8textImplTAyaTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ8textImplFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv88__T10emplaceRefTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv92__T10emplaceRefTS3std4file15DirIteratorImpl9DirHandleTS3std4file15DirIteratorImpl9DirHandleZ10emplaceRefFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv96__T4textTAyaTPvTAyaTiTAyaTiTAyaTaTAyaThTAyaThTAyaTbTAyaTbTAyaTbTAyaTbTAyaTbTAyaTAxaTAyaTAxaTAyaZ4textFNaNfAyaPvAyaiAyaiAyaaAyahAyahAyabAyabAyabAyabAyabAyaAxaAyaAxaAyaZAya@Base 6
+ _D3std4conv9__T2toThZ10__T2toTxkZ2toFNaNfxkZh@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxhZ2toFNaNbNiNfxhZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxkZ2toFNaNfxkZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxsZ2toFNaNbNiNfxsZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTykZ2toFNaNfykZi@Base 6
+ _D3std4conv9__T2toTiZ28__T2toTE3std8datetime5MonthZ2toFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ29__T2toTxE3std8datetime5MonthZ2toFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ42__T2toTE3std3net7isemail15EmailStatusCodeZ2toFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv9__T2toTiZ59__T2toTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ2toFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toThZ2toFNaNbNiNfhZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTiZ2toFNaNbNiNfiZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTkZ2toFNaNfkZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTlZ2toFNaNflZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTsZ2toFNaNbNiNfsZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTtZ2toFNaNbNiNftZi@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTkZ2toFNaNbNiNfkZk@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTlZ2toFNaNflZk@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTmZ2toFNaNfmZk@Base 6
+ _D3std4conv9__T2toTlZ9__T2toTmZ2toFNaNfmZl@Base 6
+ _D3std4conv9__T2toTmZ9__T2toTkZ2toFNaNbNiNfkZm@Base 6
+ _D3std4conv9__T2toTtZ11__T2toTAxaZ2toFNaNfAxaZt@Base 6
+ _D3std4file10attrIsFileFNaNbNiNfkZb@Base 6
+ _D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZb@Base 6
+ _D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std4file10dirEntriesFAyaE3std4file8SpanModebZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator11__fieldDtorMFZv@Base 6
+ _D3std4file11DirIterator11__xopEqualsFKxS3std4file11DirIteratorKxS3std4file11DirIteratorZb@Base 6
+ _D3std4file11DirIterator15__fieldPostblitMFNbZv@Base 6
+ _D3std4file11DirIterator5emptyMFNdZb@Base 6
+ _D3std4file11DirIterator5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std4file11DirIterator6__ctorMFNcAyaE3std4file8SpanModebZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator6__initZ@Base 6
+ _D3std4file11DirIterator8opAssignMFNcNjS3std4file11DirIteratorZS3std4file11DirIterator@Base 6
+ _D3std4file11DirIterator8popFrontMFZv@Base 6
+ _D3std4file11DirIterator9__xtoHashFNbNeKxS3std4file11DirIteratorZk@Base 6
+ _D3std4file11thisExePathFNeZAya@Base 6
+ _D3std4file12__ModuleInfoZ@Base 6
+ _D3std4file12mkdirRecurseFxAaZv@Base 6
+ _D3std4file12rmdirRecurseFKS3std4file8DirEntryZv@Base 6
+ _D3std4file12rmdirRecurseFS3std4file8DirEntryZv@Base 6
+ _D3std4file12rmdirRecurseFxAaZv@Base 6
+ _D3std4file13FileException6__ctorMFNaNfxAaxAaAyakZC3std4file13FileException@Base 6
+ _D3std4file13FileException6__ctorMFNexAakAyakZC3std4file13FileException@Base 6
+ _D3std4file13FileException6__initZ@Base 6
+ _D3std4file13FileException6__vtblZ@Base 6
+ _D3std4file13FileException7__ClassZ@Base 6
+ _D3std4file13attrIsSymlinkFNaNbNiNfkZb@Base 6
+ _D3std4file13getAttributesFNfxAaZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file13getAttributesFNfxAaZk@Base 6
+ _D3std4file13setAttributesFNfxAakZ12trustedChmodFNbNiNexAakZi@Base 6
+ _D3std4file13setAttributesFNfxAakZv@Base 6
+ _D3std4file15DirIteratorImpl11__xopEqualsFKxS3std4file15DirIteratorImplKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std4file15DirIteratorImpl11popDirStackMFZv@Base 6
+ _D3std4file15DirIteratorImpl15releaseDirStackMFZv@Base 6
+ _D3std4file15DirIteratorImpl4nextMFZb@Base 6
+ _D3std4file15DirIteratorImpl5emptyMFNdZb@Base 6
+ _D3std4file15DirIteratorImpl5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std4file15DirIteratorImpl6__ctorMFNcAyaE3std4file8SpanModebZS3std4file15DirIteratorImpl@Base 6
+ _D3std4file15DirIteratorImpl6__dtorMFZv@Base 6
+ _D3std4file15DirIteratorImpl6__initZ@Base 6
+ _D3std4file15DirIteratorImpl6stepInMFAyaZb@Base 6
+ _D3std4file15DirIteratorImpl8hasExtraMFZb@Base 6
+ _D3std4file15DirIteratorImpl8opAssignMFNcNjS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4file15DirIteratorImpl8popExtraMFZS3std4file8DirEntry@Base 6
+ _D3std4file15DirIteratorImpl8popFrontMFZv@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle11__xopEqualsFKxS3std4file15DirIteratorImpl9DirHandleKxS3std4file15DirIteratorImpl9DirHandleZb@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D3std4file15DirIteratorImpl9DirHandle9__xtoHashFNbNeKxS3std4file15DirIteratorImpl9DirHandleZk@Base 6
+ _D3std4file15DirIteratorImpl9__xtoHashFNbNeKxS3std4file15DirIteratorImplZk@Base 6
+ _D3std4file15DirIteratorImpl9mayStepInMFZb@Base 6
+ _D3std4file15DirIteratorImpl9pushExtraMFS3std4file8DirEntryZv@Base 6
+ _D3std4file15__T8cenforceTbZ8cenforceFNfbLAxaAyakZb@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZ15trustedReadlinkFNbNiNeAxaAaZi@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZ19trustedAssumeUniqueFNaNbNiNeKAaZAya@Base 6
+ _D3std4file15__T8readLinkTaZ8readLinkFNfAxaZAya@Base 6
+ _D3std4file15ensureDirExistsFxAaZb@Base 6
+ _D3std4file16__T8cenforceTPaZ8cenforceFNfPaLAxaAyakZPa@Base 6
+ _D3std4file16timeLastModifiedFNfxAaS3std8datetime7SysTimeZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file16timeLastModifiedFNfxAaS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std4file16timeLastModifiedFNfxAaZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file16timeLastModifiedFNfxAaZS3std8datetime7SysTime@Base 6
+ _D3std4file17getLinkAttributesFNfxAaZ12trustedLstatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file17getLinkAttributesFNfxAaZk@Base 6
+ _D3std4file42__T8cenforceTPS4core3sys5posix6dirent3DIRZ8cenforceFNfPS4core3sys5posix6dirent3DIRLAxaAyakZPS4core3sys5posix6dirent3DIR@Base 6
+ _D3std4file4copyFxAaxAaE3std8typecons53__T4FlagVAyaa18_707265736572766541747472696275746573Z4FlagZv@Base 6
+ _D3std4file4readFNexAakZAv@Base 6
+ _D3std4file5chdirFNfxAaZ12trustedChdirFNbNiNexAaZi@Base 6
+ _D3std4file5chdirFNfxAaZv@Base 6
+ _D3std4file5isDirFNdNfxAaZb@Base 6
+ _D3std4file5mkdirFNfxAaZ12trustedMkdirFNbNiNexAakZi@Base 6
+ _D3std4file5mkdirFNfxAaZv@Base 6
+ _D3std4file5rmdirFxAaZv@Base 6
+ _D3std4file5writeFNexAaxAvZv@Base 6
+ _D3std4file6appendFNexAaxAvZv@Base 6
+ _D3std4file6existsFNbNiNexAaZb@Base 6
+ _D3std4file6getcwdFZAya@Base 6
+ _D3std4file6isFileFNdNfxAaZb@Base 6
+ _D3std4file6removeFNexAaZv@Base 6
+ _D3std4file6renameFNexAaxAaZv@Base 6
+ _D3std4file7getSizeFNfxAaZ11trustedStatFNbNiNexAaPS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file7getSizeFNfxAaZ18ptrOfLocalVariableFNeNkKS4core3sys5posix3sys4stat6stat_tZPS4core3sys5posix3sys4stat6stat_t@Base 6
+ _D3std4file7getSizeFNfxAaZm@Base 6
+ _D3std4file7tempDirFNeZ45__T15findExistingDirTAyaTAyaTAyaTAyaTAyaTAyaZ15findExistingDirFNfLAyaLAyaLAyaLAyaLAyaLAyaZAya@Base 6
+ _D3std4file7tempDirFNeZ5cacheAya@Base 6
+ _D3std4file7tempDirFNeZAya@Base 6
+ _D3std4file8DirEntry10attributesMFNdZk@Base 6
+ _D3std4file8DirEntry11__xopEqualsFKxS3std4file8DirEntryKxS3std4file8DirEntryZb@Base 6
+ _D3std4file8DirEntry14linkAttributesMFNdZk@Base 6
+ _D3std4file8DirEntry15_ensureStatDoneMFNfZ11trustedStatFNbNiNexAaPS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file8DirEntry15_ensureStatDoneMFNfZv@Base 6
+ _D3std4file8DirEntry16_ensureLStatDoneMFZv@Base 6
+ _D3std4file8DirEntry16timeLastAccessedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry16timeLastModifiedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry17timeStatusChangedMFNdZS3std8datetime7SysTime@Base 6
+ _D3std4file8DirEntry22_ensureStatOrLStatDoneMFZv@Base 6
+ _D3std4file8DirEntry4nameMxFNaNbNdZAya@Base 6
+ _D3std4file8DirEntry4sizeMFNdZm@Base 6
+ _D3std4file8DirEntry5isDirMFNdZb@Base 6
+ _D3std4file8DirEntry6__ctorMFNcAyaPS4core3sys5posix6dirent6direntZS3std4file8DirEntry@Base 6
+ _D3std4file8DirEntry6__ctorMFNcAyaZS3std4file8DirEntry@Base 6
+ _D3std4file8DirEntry6__initZ@Base 6
+ _D3std4file8DirEntry6isFileMFNdZb@Base 6
+ _D3std4file8DirEntry7statBufMFNdZS4core3sys5posix3sys4stat6stat_t@Base 6
+ _D3std4file8DirEntry9__xtoHashFNbNeKxS3std4file8DirEntryZk@Base 6
+ _D3std4file8DirEntry9isSymlinkMFNdZb@Base 6
+ _D3std4file8deletemeFNdNfZ6_firstb@Base 6
+ _D3std4file8deletemeFNdNfZ9_deletemeAya@Base 6
+ _D3std4file8deletemeFNdNfZAya@Base 6
+ _D3std4file8dirEntryFxAaZS3std4file8DirEntry@Base 6
+ _D3std4file8getTimesFNfxAaJS3std8datetime7SysTimeJS3std8datetime7SysTimeZ11trustedStatFNbNiNexAaKS4core3sys5posix3sys4stat6stat_tZi@Base 6
+ _D3std4file8getTimesFNfxAaJS3std8datetime7SysTimeJS3std8datetime7SysTimeZv@Base 6
+ _D3std4file8setTimesFNfxAaS3std8datetime7SysTimeS3std8datetime7SysTimeZ13trustedUtimesFNbNiNexAaKxG2S4core3sys5posix3sys4time7timevalZi@Base 6
+ _D3std4file8setTimesFNfxAaS3std8datetime7SysTimeS3std8datetime7SysTimeZv@Base 6
+ _D3std4file9attrIsDirFNaNbNiNfkZb@Base 6
+ _D3std4file9isSymlinkFNdNfxAaZb@Base 6
+ _D3std4file9writeImplFNexAaxAvxkZv@Base 6
+ _D3std4json12__ModuleInfoZ@Base 6
+ _D3std4json13JSONException6__ctorMFNaNbNfAyaAyakZC3std4json13JSONException@Base 6
+ _D3std4json13JSONException6__ctorMFNaNbNfAyaiiZC3std4json13JSONException@Base 6
+ _D3std4json13JSONException6__initZ@Base 6
+ _D3std4json13JSONException6__vtblZ@Base 6
+ _D3std4json13JSONException7__ClassZ@Base 6
+ _D3std4json14appendJSONCharFPS3std5array17__T8AppenderTAyaZ8AppenderwMDFAyaZvZv@Base 6
+ _D3std4json16JSONFloatLiteral6__initZ@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ13putCharAndEOLMFaZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ6putEOLMFZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZ7putTabsMFmZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ7toValueMFxPS3std4json9JSONValuemZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZ8toStringMFAyaZv@Base 6
+ _D3std4json6toJSONFxPS3std4json9JSONValuexbxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue13__T6assignTdZ6assignMFNaNbNiNfdZv@Base 6
+ _D3std4json9JSONValue13__T6assignTlZ6assignMFNaNbNiNflZv@Base 6
+ _D3std4json9JSONValue13__T6assignTmZ6assignMFNaNbNiNfmZv@Base 6
+ _D3std4json9JSONValue14toPrettyStringMxFxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue15__T6assignTAyaZ6assignMFNaNbNiNfAyaZv@Base 6
+ _D3std4json9JSONValue33__T6assignTAS3std4json9JSONValueZ6assignMFNaNbNiNfAS3std4json9JSONValueZv@Base 6
+ _D3std4json9JSONValue36__T6assignTHAyaS3std4json9JSONValueZ6assignMFNaNbNiNfHAyaS3std4json9JSONValueZv@Base 6
+ _D3std4json9JSONValue3strMFNaNbNdNiAyaZAya@Base 6
+ _D3std4json9JSONValue3strMNgFNaNdZNgAya@Base 6
+ _D3std4json9JSONValue4typeMFNdE3std4json9JSON_TYPEZE3std4json9JSON_TYPE@Base 6
+ _D3std4json9JSONValue4typeMxFNaNbNdNiNfZE3std4json9JSON_TYPE@Base 6
+ _D3std4json9JSONValue5Store6__initZ@Base 6
+ _D3std4json9JSONValue5arrayMFNaNbNdNiAS3std4json9JSONValueZAS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue5arrayMNgFNaNcNdZNgAS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue6__initZ@Base 6
+ _D3std4json9JSONValue6isNullMxFNaNbNdNiNfZb@Base 6
+ _D3std4json9JSONValue6objectMFNaNbNdNiHAyaS3std4json9JSONValueZHAyaS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue6objectMNgFNaNcNdZNgHAyaS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue7integerMFNaNbNdNiNflZl@Base 6
+ _D3std4json9JSONValue7integerMNgFNaNdNfZNgl@Base 6
+ _D3std4json9JSONValue7opApplyMFDFAyaKS3std4json9JSONValueZiZi@Base 6
+ _D3std4json9JSONValue7opApplyMFDFkKS3std4json9JSONValueZiZi@Base 6
+ _D3std4json9JSONValue7opIndexMNgFNaNcAyaZNgS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue7opIndexMNgFNaNckZNgS3std4json9JSONValue@Base 6
+ _D3std4json9JSONValue8floatingMFNaNbNdNiNfdZd@Base 6
+ _D3std4json9JSONValue8floatingMNgFNaNdNfZNgd@Base 6
+ _D3std4json9JSONValue8opEqualsMxFNaNbNiKxS3std4json9JSONValueZb@Base 6
+ _D3std4json9JSONValue8opEqualsMxFNaNbNixS3std4json9JSONValueZb@Base 6
+ _D3std4json9JSONValue8toStringMxFxE3std4json11JSONOptionsZAya@Base 6
+ _D3std4json9JSONValue8uintegerMFNaNbNdNiNfmZm@Base 6
+ _D3std4json9JSONValue8uintegerMNgFNaNdNfZNgm@Base 6
+ _D3std4math10__T3absTeZ3absFNaNbNiNfeZe@Base 6
+ _D3std4math11isIdenticalFNaNbNiNeeeZb@Base 6
+ _D3std4math12__ModuleInfoZ@Base 6
+ _D3std4math12__T3powTeTeZ3powFNaNbNiNeeeZ4implFNaNbNiNfeeZe@Base 6
+ _D3std4math12__T3powTeTeZ3powFNaNbNiNeeeZe@Base 6
+ _D3std4math12__T3powTeTlZ3powFNaNbNiNeelZe@Base 6
+ _D3std4math12__T3powTiTiZ3powFNaNbNiNeiiZi@Base 6
+ _D3std4math12__T5frexpTeZ5frexpFNaNbNiNexeJiZe@Base 6
+ _D3std4math12__T5isNaNTdZ5isNaNFNaNbNiNedZb@Base 6
+ _D3std4math12__T5isNaNTeZ5isNaNFNaNbNiNeeZb@Base 6
+ _D3std4math12__T5isNaNTfZ5isNaNFNaNbNiNefZb@Base 6
+ _D3std4math13__T4polyTeTeZ4polyFNaNbNiNeexAeZe@Base 6
+ _D3std4math13__T5isNaNTxdZ5isNaNFNaNbNiNexdZb@Base 6
+ _D3std4math13__T5isNaNTxeZ5isNaNFNaNbNiNexeZb@Base 6
+ _D3std4math13getNaNPayloadFNaNbNiNeeZm@Base 6
+ _D3std4math14__T4polyTyeTeZ4polyFNaNbNiNeyexAeZe@Base 6
+ _D3std4math14__T7signbitTeZ7signbitFNaNbNiNeeZi@Base 6
+ _D3std4math14resetIeeeFlagsFZv@Base 6
+ _D3std4math15__T7signbitTxeZ7signbitFNaNbNiNexeZi@Base 6
+ _D3std4math15__T7signbitTyeZ7signbitFNaNbNiNeyeZi@Base 6
+ _D3std4math15__T8ieeeMeanTeZ8ieeeMeanFNaNbNiNexexeZe@Base 6
+ _D3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZd@Base 6
+ _D3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZe@Base 6
+ _D3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZ9floatBits6__initZ@Base 6
+ _D3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZf@Base 6
+ _D3std4math17__T8copysignTdTeZ8copysignFNaNbNiNedeZd@Base 6
+ _D3std4math17__T8copysignTeTeZ8copysignFNaNbNiNeeeZe@Base 6
+ _D3std4math17__T8copysignTeTiZ8copysignFNaNbNiNeieZe@Base 6
+ _D3std4math18__T10isInfinityTdZ10isInfinityFNaNbNiNedZb@Base 6
+ _D3std4math18__T10isInfinityTeZ10isInfinityFNaNbNiNeeZb@Base 6
+ _D3std4math18__T10isInfinityTfZ10isInfinityFNaNbNiNefZb@Base 6
+ _D3std4math19__T10isInfinityTxdZ10isInfinityFNaNbNiNexdZb@Base 6
+ _D3std4math20FloatingPointControl10initializeMFNiZv@Base 6
+ _D3std4math20FloatingPointControl15clearExceptionsFNiZv@Base 6
+ _D3std4math20FloatingPointControl15getControlStateFNbNiNeZk@Base 6.2.1-1ubuntu2
+ _D3std4math20FloatingPointControl15setControlStateFNbNiNekZv@Base 6.2.1-1ubuntu2
+ _D3std4math20FloatingPointControl16enableExceptionsMFNikZv@Base 6
+ _D3std4math20FloatingPointControl17disableExceptionsMFNikZv@Base 6
+ _D3std4math20FloatingPointControl17enabledExceptionsFNdNiZk@Base 6
+ _D3std4math20FloatingPointControl17hasExceptionTrapsFNbNdNiNfZb@Base 6
+ _D3std4math20FloatingPointControl6__dtorMFNiZv@Base 6
+ _D3std4math20FloatingPointControl6__initZ@Base 6
+ _D3std4math20FloatingPointControl8opAssignMFNcNiNjS3std4math20FloatingPointControlZS3std4math20FloatingPointControl@Base 6
+ _D3std4math20FloatingPointControl8roundingFNdNiZk@Base 6
+ _D3std4math20FloatingPointControl8roundingMFNdNikZv@Base 6
+ _D3std4math22__T12polyImplBaseTeTeZ12polyImplBaseFNaNbNiNeexAeZe@Base 6
+ _D3std4math3NaNFNaNbNiNemZe@Base 6
+ _D3std4math3cosFNaNbNiNfcZc@Base 6
+ _D3std4math3cosFNaNbNiNfdZd@Base 6
+ _D3std4math3cosFNaNbNiNffZf@Base 6
+ _D3std4math3cosFNaNbNiNfjZe@Base 6
+ _D3std4math3expFNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math3expFNaNbNiNeeZ1QyG4e@Base 6
+ _D3std4math3expFNaNbNiNeeZe@Base 6
+ _D3std4math3expFNaNbNiNfdZd@Base 6
+ _D3std4math3expFNaNbNiNffZf@Base 6
+ _D3std4math3fmaFNaNbNiNfeeeZe@Base 6
+ _D3std4math3logFNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math3logFNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math3logFNaNbNiNfeZe@Base 6
+ _D3std4math3sinFNaNbNiNfcZc@Base 6
+ _D3std4math3sinFNaNbNiNfdZd@Base 6
+ _D3std4math3sinFNaNbNiNffZf@Base 6
+ _D3std4math3sinFNaNbNiNfjZj@Base 6
+ _D3std4math3tanFNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math3tanFNaNbNiNeeZ1QyG5e@Base 6
+ _D3std4math3tanFNaNbNiNeeZe@Base 6
+ _D3std4math4acosFNaNbNiNfdZd@Base 6
+ _D3std4math4acosFNaNbNiNfeZe@Base 6
+ _D3std4math4acosFNaNbNiNffZf@Base 6
+ _D3std4math4asinFNaNbNiNfdZd@Base 6
+ _D3std4math4asinFNaNbNiNfeZe@Base 6
+ _D3std4math4asinFNaNbNiNffZf@Base 6
+ _D3std4math4atanFNaNbNiNfdZd@Base 6
+ _D3std4math4atanFNaNbNiNfeZ1PyG5e@Base 6
+ _D3std4math4atanFNaNbNiNfeZ1QyG6e@Base 6
+ _D3std4math4atanFNaNbNiNfeZe@Base 6
+ _D3std4math4atanFNaNbNiNffZf@Base 6
+ _D3std4math4cbrtFNbNiNeeZe@Base 6
+ _D3std4math4ceilFNaNbNiNedZd@Base 6
+ _D3std4math4ceilFNaNbNiNeeZe@Base 6
+ _D3std4math4ceilFNaNbNiNefZf@Base 6
+ _D3std4math4coshFNaNbNiNfdZd@Base 6
+ _D3std4math4coshFNaNbNiNfeZe@Base 6
+ _D3std4math4coshFNaNbNiNffZf@Base 6
+ _D3std4math4exp2FNaNbNiNeeZ1PyG3e@Base 6
+ _D3std4math4exp2FNaNbNiNeeZ1QyG4e@Base 6
+ _D3std4math4exp2FNaNbNiNeeZe@Base 6
+ _D3std4math4expiFNaNbNiNeeZc@Base 6
+ _D3std4math4fabsFNaNbNiNfdZd@Base 6
+ _D3std4math4fabsFNaNbNiNffZf@Base 6
+ _D3std4math4fdimFNaNbNiNfeeZe@Base 6
+ _D3std4math4fmaxFNaNbNiNfeeZe@Base 6
+ _D3std4math4fminFNaNbNiNfeeZe@Base 6
+ _D3std4math4fmodFNbNiNeeeZe@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math4log2FNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math4log2FNaNbNiNfeZe@Base 6
+ _D3std4math4logbFNbNiNeeZe@Base 6
+ _D3std4math4modfFNbNiNeeKeZe@Base 6
+ _D3std4math4rintFNaNbNiNfdZd@Base 6
+ _D3std4math4rintFNaNbNiNffZf@Base 6
+ _D3std4math4sinhFNaNbNiNfdZd@Base 6
+ _D3std4math4sinhFNaNbNiNfeZe@Base 6
+ _D3std4math4sinhFNaNbNiNffZf@Base 6
+ _D3std4math4sqrtFNaNbNiNfcZc@Base 6
+ _D3std4math4tanhFNaNbNiNfdZd@Base 6
+ _D3std4math4tanhFNaNbNiNfeZe@Base 6
+ _D3std4math4tanhFNaNbNiNffZf@Base 6
+ _D3std4math5acoshFNaNbNiNfdZd@Base 6
+ _D3std4math5acoshFNaNbNiNfeZe@Base 6
+ _D3std4math5acoshFNaNbNiNffZf@Base 6
+ _D3std4math5asinhFNaNbNiNfdZd@Base 6
+ _D3std4math5asinhFNaNbNiNfeZe@Base 6
+ _D3std4math5asinhFNaNbNiNffZf@Base 6
+ _D3std4math5atan2FNaNbNiNeeeZe@Base 6
+ _D3std4math5atan2FNaNbNiNfddZd@Base 6
+ _D3std4math5atan2FNaNbNiNfffZf@Base 6
+ _D3std4math5atanhFNaNbNiNfdZd@Base 6
+ _D3std4math5atanhFNaNbNiNfeZe@Base 6
+ _D3std4math5atanhFNaNbNiNffZf@Base 6
+ _D3std4math5expm1FNaNbNiNeeZ1PyG5e@Base 6
+ _D3std4math5expm1FNaNbNiNeeZ1QyG6e@Base 6
+ _D3std4math5expm1FNaNbNiNeeZe@Base 6
+ _D3std4math5floorFNaNbNiNedZd@Base 6
+ _D3std4math5floorFNaNbNiNeeZe@Base 6
+ _D3std4math5floorFNaNbNiNefZf@Base 6
+ _D3std4math5hypotFNaNbNiNfeeZe@Base 6
+ _D3std4math5ilogbFNbNiNeeZi@Base 6
+ _D3std4math5ldexpFNaNbNiNfdiZd@Base 6
+ _D3std4math5ldexpFNaNbNiNffiZf@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1PyG7e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1QyG7e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1RyG4e@Base 6
+ _D3std4math5log10FNaNbNiNfeZ1SyG4e@Base 6
+ _D3std4math5log10FNaNbNiNfeZe@Base 6
+ _D3std4math5log1pFNaNbNiNfeZe@Base 6
+ _D3std4math5lrintFNaNbNiNeeZl@Base 6
+ _D3std4math5roundFNbNiNeeZe@Base 6
+ _D3std4math5truncFNbNiNeeZe@Base 6
+ _D3std4math6lroundFNbNiNeeZl@Base 6
+ _D3std4math6nextUpFNaNbNiNedZd@Base 6
+ _D3std4math6nextUpFNaNbNiNeeZe@Base 6
+ _D3std4math6nextUpFNaNbNiNefZf@Base 6
+ _D3std4math6remquoFNbNiNeeeJiZe@Base 6
+ _D3std4math6rndtolFNaNbNiNfdZl@Base 6
+ _D3std4math6rndtolFNaNbNiNffZl@Base 6
+ _D3std4math6scalbnFNbNiNeeiZe@Base 6
+ _D3std4math8nextDownFNaNbNiNfdZd@Base 6
+ _D3std4math8nextDownFNaNbNiNfeZe@Base 6
+ _D3std4math8nextDownFNaNbNiNffZf@Base 6
+ _D3std4math8polyImplFNaNbNiNeexAeZe@Base 6
+ _D3std4math9IeeeFlags12getIeeeFlagsFZk@Base 6
+ _D3std4math9IeeeFlags14resetIeeeFlagsFZv@Base 6
+ _D3std4math9IeeeFlags6__initZ@Base 6
+ (optional)_D3std4math9IeeeFlags7inexactMFNdZb@Base 6
+ (optional)_D3std4math9IeeeFlags7invalidMFNdZb@Base 6
+ (optional)_D3std4math9IeeeFlags8overflowMFNdZb@Base 6
+ (optional)_D3std4math9IeeeFlags9divByZeroMFNdZb@Base 6
+ (optional)_D3std4math9IeeeFlags9underflowMFNdZb@Base 6
+ _D3std4math9coshisinhFNaNbNiNfeZc@Base 6
+ _D3std4math9ieeeFlagsFNdZS3std4math9IeeeFlags@Base 6
+ _D3std4math9nearbyintFNbNiNeeZe@Base 6
+ _D3std4math9remainderFNbNiNeeeZe@Base 6
+ _D3std4meta12__ModuleInfoZ@Base 6
+ _D3std4path109__T9globMatchVE3std4path13CaseSensitivei1TaTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ9globMatchFNaNbNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplAxaZb@Base 6
+ _D3std4path11expandTildeFNbAyaZ18expandFromDatabaseFNbAyaZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZ21combineCPathWithDPathFNbPaAyakZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZ21expandFromEnvironmentFNbAyaZAya@Base 6
+ _D3std4path11expandTildeFNbAyaZAya@Base 6
+ _D3std4path12__ModuleInfoZ@Base 6
+ _D3std4path12absolutePathFNaNfAyaLAyaZAya@Base 6
+ _D3std4path14isDirSeparatorFNaNbNiNfwZb@Base 6
+ _D3std4path16__T7dirNameTAxaZ7dirNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path16__T9buildPathTaZ9buildPathFNaNbNfAAxaXAya@Base 6
+ _D3std4path16isDriveSeparatorFNaNbNiNfwZb@Base 6
+ _D3std4path17__T8baseNameTAxaZ8baseNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path17__T8baseNameTAyaZ8baseNameFNaNbNiNfAyaZAya@Base 6
+ _D3std4path17__T8isRootedTAxaZ8isRootedFNaNbNiNfAxaZb@Base 6
+ _D3std4path17__T8isRootedTAyaZ8isRootedFNaNbNiNfAyaZb@Base 6
+ _D3std4path17__T8rootNameTAxaZ8rootNameFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path18__T9extensionTAyaZ9extensionFNaNbNiNfAyaZAya@Base 6
+ _D3std4path19__T9buildPathTAAxaZ9buildPathFAAxaZ24__T11trustedCastTAyaTAaZ11trustedCastFNaNbNiNeAaZAya@Base 6
+ _D3std4path19__T9buildPathTAAxaZ9buildPathFNaNbNfAAxaZAya@Base 6
+ _D3std4path20__T10stripDriveTAxaZ10stripDriveFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path20__T10stripDriveTAyaZ10stripDriveFNaNbNiNfAyaZAya@Base 6
+ _D3std4path21__T9chainPathTAaTAxaZ9chainPathFNaNbNiNfAaAxaZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter11__xopEqualsFKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterZb@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter4backMFNaNbNdNiNfZAxa@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter4saveMFNaNbNdNiNfZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5frontMFNaNbNdNiNfZAxa@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5ltrimMFNaNbNiNfkkZk@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter5rtrimMFNaNbNiNfkkZk@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__ctorMFNaNbNcNiNfAxaZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter7popBackMFNaNbNiNfZv@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter9__xtoHashFNbNeKxS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitterZk@Base 6
+ _D3std4path22__T12pathSplitterTAxaZ12pathSplitterFNaNbNiNfAxaZS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter@Base 6
+ _D3std4path22__T9chainPathTAxaTAxaZ9chainPathFNaNbNiNfAxaAxaZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path22__T9chainPathTAyaTAyaZ9chainPathFNaNbNiNfAyaAyaZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std4path23__T13lastSeparatorTAxaZ13lastSeparatorFNaNbNiNfAxaZi@Base 6
+ _D3std4path23__T13lastSeparatorTAyaZ13lastSeparatorFNaNbNiNfAyaZi@Base 6
+ _D3std4path25__T15extSeparatorPosTAyaZ15extSeparatorPosFNaNbNiNfxAyaZi@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result11__xopEqualsFKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result11getElement0MFNaNbNiNfZa@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result4saveMFNaNbNdNiNfZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5frontMFNaNbNdNiNfZa@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result5isDotFNaNbNiNfAxaZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__ctorMFNaNbNcNiNfAxaZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__initZ@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result8isDotDotFNaNbNiNfAxaZb@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result9__xtoHashFNbNeKxS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZk@Base 6
+ _D3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFNaNbNiNfAxaZS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result@Base 6
+ _D3std4path27__T19buildNormalizedPathTaZ19buildNormalizedPathFNaNbNeAxAaXAya@Base 6
+ _D3std4path28__T18rtrimDirSeparatorsTAxaZ18rtrimDirSeparatorsFNaNbNiNfAxaZAxa@Base 6
+ _D3std4path28__T18rtrimDirSeparatorsTAyaZ18rtrimDirSeparatorsFNaNbNiNfAyaZAya@Base 6
+ _D3std4path48__T9globMatchVE3std4path13CaseSensitivei1TaTAyaZ9globMatchFNaNbNfAyaAxaZb@Base 6
+ _D3std4path49__T15filenameCharCmpVE3std4path13CaseSensitivei1Z15filenameCharCmpFNaNbNiNfwwZi@Base 6
+ _D3std4uuid10randomUUIDFNfZS3std4uuid4UUID@Base 6
+ _D3std4uuid12__ModuleInfoZ@Base 6
+ _D3std4uuid164__T10randomUUIDTS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngineZ10randomUUIDFNaNbNfKS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngineZS3std4uuid4UUID@Base 6
+ _D3std4uuid20UUIDParsingException6__ctorMFNaNeAyakE3std4uuid20UUIDParsingException6ReasonAyaC6object9ThrowableAyakZC3std4uuid20UUIDParsingException@Base 6
+ _D3std4uuid20UUIDParsingException6__initZ@Base 6
+ _D3std4uuid20UUIDParsingException6__vtblZ@Base 6
+ _D3std4uuid20UUIDParsingException7__ClassZ@Base 6
+ _D3std4uuid4UUID11uuidVersionMxFNaNbNdNiNfZE3std4uuid4UUID7Version@Base 6
+ _D3std4uuid4UUID13__T6__ctorTaZ6__ctorMFNaNcNfxAaZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID16__T9asArrayOfTkZ9asArrayOfMFNaNbNcNiNjNeZG4k@Base 6
+ _D3std4uuid4UUID4swapMFNaNbNiNfKS3std4uuid4UUIDZv@Base 6
+ _D3std4uuid4UUID5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std4uuid4UUID5opCmpMxFNaNbNiNfKxS3std4uuid4UUIDZi@Base 6
+ _D3std4uuid4UUID5opCmpMxFNaNbNiNfxS3std4uuid4UUIDZi@Base 6
+ _D3std4uuid4UUID6__ctorMFNaNbNcNiNfKxG16hZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID6__ctorMFNaNbNcNiNfxG16hZS3std4uuid4UUID@Base 6
+ _D3std4uuid4UUID6__initZ@Base 6
+ _D3std4uuid4UUID6toCharMxFNaNbNfkZa@Base 6
+ _D3std4uuid4UUID6toHashMxFNaNbNiNfZk@Base 6
+ _D3std4uuid4UUID7Version6__initZ@Base 6
+ _D3std4uuid4UUID7variantMxFNaNbNdNiNfZE3std4uuid4UUID7Variant@Base 6
+ _D3std4uuid4UUID8opEqualsMxFNaNbNiNfKxS3std4uuid4UUIDZb@Base 6
+ _D3std4uuid4UUID8opEqualsMxFNaNbNiNfxS3std4uuid4UUIDZb@Base 6
+ _D3std4uuid4UUID8toStringMxFMDFAxaZvZv@Base 6
+ _D3std4uuid4UUID8toStringMxFNaNbNfZAya@Base 6
+ _D3std4uuid4UUID9_toStringMxFNaNbNfZG36a@Base 6
+ _D3std4uuid7md5UUIDFNaNbNiNfxAaxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid7md5UUIDFNaNbNiNfxAhxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid8sha1UUIDFNaNbNiNfxAaxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4uuid8sha1UUIDFNaNbNiNfxAhxS3std4uuid4UUIDZS3std4uuid4UUID@Base 6
+ _D3std4zlib10UnCompress10uncompressMFAxvZAxv@Base 6
+ _D3std4zlib10UnCompress5errorMFiZv@Base 6
+ _D3std4zlib10UnCompress5flushMFZAv@Base 6
+ _D3std4zlib10UnCompress6__ctorMFE3std4zlib12HeaderFormatZC3std4zlib10UnCompress@Base 6
+ _D3std4zlib10UnCompress6__ctorMFkZC3std4zlib10UnCompress@Base 6
+ _D3std4zlib10UnCompress6__dtorMFZv@Base 6
+ _D3std4zlib10UnCompress6__initZ@Base 6
+ _D3std4zlib10UnCompress6__vtblZ@Base 6
+ _D3std4zlib10UnCompress7__ClassZ@Base 6
+ _D3std4zlib10uncompressFAvkiZAv@Base 6
+ _D3std4zlib12__ModuleInfoZ@Base 6
+ _D3std4zlib13ZlibException6__ctorMFiZC3std4zlib13ZlibException@Base 6
+ _D3std4zlib13ZlibException6__initZ@Base 6
+ _D3std4zlib13ZlibException6__vtblZ@Base 6
+ _D3std4zlib13ZlibException7__ClassZ@Base 6
+ _D3std4zlib5crc32FkAxvZk@Base 6
+ _D3std4zlib7adler32FkAxvZk@Base 6
+ _D3std4zlib8Compress5errorMFiZv@Base 6
+ _D3std4zlib8Compress5flushMFiZAv@Base 6
+ _D3std4zlib8Compress6__ctorMFE3std4zlib12HeaderFormatZC3std4zlib8Compress@Base 6
+ _D3std4zlib8Compress6__ctorMFiE3std4zlib12HeaderFormatZC3std4zlib8Compress@Base 6
+ _D3std4zlib8Compress6__dtorMFZv@Base 6
+ _D3std4zlib8Compress6__initZ@Base 6
+ _D3std4zlib8Compress6__vtblZ@Base 6
+ _D3std4zlib8Compress7__ClassZ@Base 6
+ _D3std4zlib8Compress8compressMFAxvZAxv@Base 6
+ _D3std4zlib8compressFAxvZAxv@Base 6
+ _D3std4zlib8compressFAxviZAxv@Base 6
+ _D3std5array102__T5arrayTS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZ5arrayFNaNbNfS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZAAya@Base 6
+ _D3std5array118__T13insertInPlaceTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir8BytecodekS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array12__ModuleInfoZ@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNeANgvANgvZ3maxFNaNbNiNfPNgvPNgvZPNgv@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNeANgvANgvZ3minFNaNbNiNfPNgvPNgvZPNgv@Base 6
+ _D3std5array14__T7overlapTvZ7overlapFNaNbNiNeANgvANgvZANgv@Base 6
+ _D3std5array154__T5arrayTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZ5arrayFNaNbNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList67__T9IntervalsTS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArrayZ9IntervalsZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data11__xopEqualsFKxS3std5array16__T8AppenderTAaZ8Appender4DataKxS3std5array16__T8AppenderTAaZ8Appender4DataZb@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data6__initZ@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4Data9__xtoHashFNbNeKxS3std5array16__T8AppenderTAaZ8Appender4DataZk@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender4dataMNgFNaNbNdNiNeZANga@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender6__ctorMFNaNbNcNeAaZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender6__initZ@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array16__T8AppenderTAaZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender10__T3putThZ3putMFNaNbNfhZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender11__T3putTAhZ3putMFNaNbNfAhZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data11__xopEqualsFKxS3std5array16__T8AppenderTAhZ8Appender4DataKxS3std5array16__T8AppenderTAhZ8Appender4DataZb@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data6__initZ@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4Data9__xtoHashFNbNeKxS3std5array16__T8AppenderTAhZ8Appender4DataZk@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender4dataMNgFNaNbNdNiNeZANgh@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender6__ctorMFNaNbNcNeAhZS3std5array16__T8AppenderTAhZ8Appender@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender6__initZ@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array16__T8AppenderTAhZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array16__T8appenderTAaZ8appenderFNaNbNfZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array16__T8appenderTAhZ8appenderFNaNbNfZS3std5array16__T8AppenderTAhZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAxaZ8Appender4DataKxS3std5array17__T8AppenderTAxaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAxaZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender4dataMNgFNaNbNdNiNeZANgxa@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender6__ctorMFNaNbNcNeAxaZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAxaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTxaZ3putMFNaNbNfxaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTxwZ3putMFNaNfxwZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender11__T3putTyaZ3putMFNaNbNfyaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAyaZ8Appender4DataKxS3std5array17__T8AppenderTAyaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAyaZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender4dataMNgFNaNbNdNiNeZAya@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcAaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcNeAyaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAyaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender11__T3putTAuZ3putMFNaNbNfAuZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAyuZ8Appender4DataKxS3std5array17__T8AppenderTAyuZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAyuZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender4dataMNgFNaNbNdNiNeZAyu@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcAuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcNeAyuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAyuZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender10__T3putTwZ3putMFNaNbNfwZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTAywZ8Appender4DataKxS3std5array17__T8AppenderTAywZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTAywZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender4dataMNgFNaNbNdNiNeZAyw@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcAwZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcNeAywZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTAywZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender10__T3putTaZ3putMFNaNbNfaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender10__T3putTwZ3putMFNaNfwZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTAaZ3putMFNaNbNfAaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTxaZ3putMFNaNbNfxaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTxwZ3putMFNaNfxwZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender11__T3putTyaZ3putMFNaNbNfyaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender12__T3putTAxaZ3putMFNaNbNfAxaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data11__xopEqualsFKxS3std5array17__T8AppenderTyAaZ8Appender4DataKxS3std5array17__T8AppenderTyAaZ8Appender4DataZb@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data6__initZ@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4Data9__xtoHashFNbNeKxS3std5array17__T8AppenderTyAaZ8Appender4DataZk@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender4dataMNgFNaNbNdNiNeZAya@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcAaZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcNeAyaZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__ctorMFNaNbNcNfnZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender6__initZ@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array17__T8AppenderTyAaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array17__T8appenderTAxaZ8appenderFNaNbNfZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array17__T8appenderTAyaZ8appenderFNaNbNfZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array17__T8appenderTyAaZ8appenderFNaNbNfZS3std5array17__T8AppenderTyAaZ8Appender@Base 6
+ _D3std5array18__T5splitTAyaTAyaZ5splitFNaNbNfAyaAyaZAAya@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender12__T3putTAyaZ3putMFNaNbNfAyaZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data11__xopEqualsFKxS3std5array18__T8AppenderTAAyaZ8Appender4DataKxS3std5array18__T8AppenderTAAyaZ8Appender4DataZb@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data6__initZ@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4Data9__xtoHashFNbNeKxS3std5array18__T8AppenderTAAyaZ8Appender4DataZk@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender4dataMNgFNaNbNdNiNeZANgAya@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender6__ctorMFNaNbNcNeAAyaZS3std5array18__T8AppenderTAAyaZ8Appender@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender6__initZ@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array18__T8AppenderTAAyaZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array18__T8appenderTAAyaZ8appenderFNaNbNfZS3std5array18__T8AppenderTAAyaZ8Appender@Base 6
+ _D3std5array19__T8appenderHTAaTaZ8appenderFNaNbNfAaZS3std5array16__T8AppenderTAaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAxaTxaZ8appenderFNaNbNfAxaZS3std5array17__T8AppenderTAxaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAyaTyaZ8appenderFNaNbNfAyaZS3std5array17__T8AppenderTAyaZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAyuTyuZ8appenderFNaNbNfAyuZS3std5array17__T8AppenderTAyuZ8Appender@Base 6
+ _D3std5array21__T8appenderHTAywTywZ8appenderFNaNbNfAywZS3std5array17__T8AppenderTAywZ8Appender@Base 6
+ _D3std5array23__T7replaceTxaTAyaTAyaZ7replaceFNaNbNfAxaAyaAyaZAxa@Base 6
+ _D3std5array23__T7replaceTyaTAyaTAyaZ7replaceFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAaTkZ14arrayAllocImplFNaNbkZAa@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAfTkZ14arrayAllocImplFNaNbkZAf@Base 6
+ _D3std5array29__T14arrayAllocImplVbi0TAhTkZ14arrayAllocImplFNaNbkZAh@Base 6
+ _D3std5array29__T18uninitializedArrayTAaTkZ18uninitializedArrayFNaNbNekZAa@Base 6
+ _D3std5array29__T18uninitializedArrayTAfTkZ18uninitializedArrayFNaNbNekZAf@Base 6
+ _D3std5array29__T19appenderNewCapacityVki1Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array29__T19appenderNewCapacityVki2Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array29__T19appenderNewCapacityVki4Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array29__T19appenderNewCapacityVki8Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array30__T18uninitializedArrayTAhTykZ18uninitializedArrayFNaNbNeykZAh@Base 6
+ _D3std5array30__T19appenderNewCapacityVki12Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array30__T19appenderNewCapacityVki24Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6
+ _D3std5array31__T19appenderNewCapacityVki120Z19appenderNewCapacityFNaNbNiNfkkZk@Base 6.2.1-1ubuntu2
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender28__T3putTS3std4file8DirEntryZ3putMFNaNbNfS3std4file8DirEntryZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data11__xopEqualsFKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataZb@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data6__initZ@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data9__xtoHashFNbNeKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataZk@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4dataMNgFNaNbNdNiNeZANgS3std4file8DirEntry@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__ctorMFNaNbNcNeAS3std4file8DirEntryZS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array405__T5arrayTS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZ5arrayFNaNbNfS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZAxa@Base 6
+ _D3std5array405__T5arrayTS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZ5arrayFNaNbNfS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZAxa@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender34__T3putTS3std6socket11AddressInfoZ3putMFNaNbNfS3std6socket11AddressInfoZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data11__xopEqualsFKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataZb@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data6__initZ@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data9__xtoHashFNbNeKxS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4DataZk@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4dataMNgFNaNbNdNiNeZANgS3std6socket11AddressInfo@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender52__T10opOpAssignHVAyaa1_7eTS3std6socket11AddressInfoZ10opOpAssignMFNaNbNfS3std6socket11AddressInfoZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__ctorMFNaNbNcNeAS3std6socket11AddressInfoZS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__initZ@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array40__T8appenderTAS3std6socket11AddressInfoZ8appenderFNaNbNfZS3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender@Base 6
+ _D3std5array52__T13copyBackwardsTS3std5regex8internal2ir8BytecodeZ13copyBackwardsFNaNbNiAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender13ensureAddableMFNaNbNekZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender46__T3putTS3std4file15DirIteratorImpl9DirHandleZ3putMFNaNbNfS3std4file15DirIteratorImpl9DirHandleZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data11__xopEqualsFKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataZb@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data6__initZ@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data9__xtoHashFNbNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataZk@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4dataMNgFNaNbNdNiNeZANgS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender5clearMFNaNbNiNeZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__ctorMFNaNbNcNeAS3std4file15DirIteratorImpl9DirHandleZS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender7reserveMFNaNbNfkZv@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender8shrinkToMFNaNekZv@Base 6
+ _D3std5array55__T13copyBackwardsTS3std5regex8internal2ir10NamedGroupZ13copyBackwardsFNaNbNiAS3std5regex8internal2ir10NamedGroupAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5array55__T8appenderHTAS3std4file8DirEntryTS3std4file8DirEntryZ8appenderFNaNbNfAS3std4file8DirEntryZS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender@Base 6
+ _D3std5array56__T14arrayAllocImplVbi0TAS3std3uni17CodepointIntervalTkZ14arrayAllocImplFNaNbkZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array56__T18uninitializedArrayTAS3std3uni17CodepointIntervalTkZ18uninitializedArrayFNaNbNekZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array57__T18uninitializedArrayTAS3std3uni17CodepointIntervalTyiZ18uninitializedArrayFNaNbNeyiZAS3std3uni17CodepointInterval@Base 6
+ _D3std5array68__T11replaceIntoTxaTS3std5array17__T8AppenderTAxaZ8AppenderTAyaTAyaZ11replaceIntoFNaNbNfS3std5array17__T8AppenderTAxaZ8AppenderAxaAyaAyaZv@Base 6
+ _D3std5array68__T11replaceIntoTyaTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTAyaZ11replaceIntoFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderAyaAyaAyaZv@Base 6
+ _D3std5array79__T5arrayTS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZ5arrayFNaNbNfS3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6ResultZAa@Base 6
+ _D3std5array85__T13insertInPlaceTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir8BytecodekS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5array892__T5arrayTS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZ5arrayFNaNbNfS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZAa@Base 6
+ _D3std5array91__T13insertInPlaceTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ13insertInPlaceFNaNbNfKAS3std5regex8internal2ir10NamedGroupkS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5array91__T8appenderHTAS3std4file15DirIteratorImpl9DirHandleTS3std4file15DirIteratorImpl9DirHandleZ8appenderFNaNbNfAS3std4file15DirIteratorImpl9DirHandleZS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender@Base 6
+ _D3std5ascii10isAlphaNumFNaNbNiNfwZb@Base 6
+ _D3std5ascii10isHexDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii10whitespaceyAa@Base 6
+ _D3std5ascii11isGraphicalFNaNbNiNfwZb@Base 6
+ _D3std5ascii11isPrintableFNaNbNiNfwZb@Base 6
+ _D3std5ascii11octalDigitsyAa@Base 6
+ _D3std5ascii12__ModuleInfoZ@Base 6
+ _D3std5ascii12isOctalDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii13fullHexDigitsyAa@Base 6
+ _D3std5ascii13isPunctuationFNaNbNiNfwZb@Base 6
+ _D3std5ascii14__T7toLowerTwZ7toLowerFNaNbNiNfwZw@Base 6
+ _D3std5ascii14lowerHexDigitsyAa@Base 6
+ _D3std5ascii15__T7toLowerTxaZ7toLowerFNaNbNiNfxaZa@Base 6
+ _D3std5ascii15__T7toLowerTxwZ7toLowerFNaNbNiNfxwZw@Base 6
+ _D3std5ascii15__T7toLowerTyaZ7toLowerFNaNbNiNfyaZa@Base 6
+ _D3std5ascii6digitsyAa@Base 6
+ _D3std5ascii7isASCIIFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isAlphaFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isDigitFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isLowerFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isUpperFNaNbNiNfwZb@Base 6
+ _D3std5ascii7isWhiteFNaNbNiNfwZb@Base 6
+ _D3std5ascii7lettersyAa@Base 6
+ _D3std5ascii7newlineyAa@Base 6
+ _D3std5ascii9hexDigitsyAa@Base 6
+ _D3std5ascii9isControlFNaNbNiNfwZb@Base 6
+ _D3std5ascii9lowercaseyAa@Base 6
+ _D3std5ascii9uppercaseyAa@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange11__xopEqualsFKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZb@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4saveMFNaNbNdNiNfZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__ctorMFNaNbNcNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opIndexMFNaNbNcNiNfkZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7releaseMFNaNbNiZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange9__xtoHashFNbNeKxS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZk@Base 6
+ _D3std5range103__T12assumeSortedVAyaa17_612e74696d6554203c20622e74696d6554TAS3std8datetime13PosixTimeZone10LeapSecondZ12assumeSortedFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange11__xopEqualsFKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZb@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange4saveMFNaNbNdNiNfZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__ctorMFNaNbNcNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6__initZ@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opIndexMFNaNbNcNiNfkZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange7releaseMFNaNbNiZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange9__xtoHashFNbNeKxS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRangeZk@Base 6
+ _D3std5range107__T12assumeSortedVAyaa17_612e74696d6554203c20622e74696d6554TAS3std8datetime13PosixTimeZone14TempTransitionZ12assumeSortedFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std5range10interfaces12__ModuleInfoZ@Base 6
+ _D3std5range10primitives107__T6moveAtTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTkZ6moveAtFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalskZS3std3uni17CodepointInterval@Base 6
+ _D3std5range10primitives11__T4backThZ4backFNaNbNcNdNiNfAhZh@Base 6
+ _D3std5range10primitives11__T4backTkZ4backFNaNbNcNdNiNfAkZk@Base 6
+ _D3std5range10primitives11__T4saveTaZ4saveFNaNbNdNiNfAaZAa@Base 6
+ _D3std5range10primitives11__T4saveTfZ4saveFNaNbNdNiNfAfZAf@Base 6
+ _D3std5range10primitives11__T4saveThZ4saveFNaNbNdNiNfAhZAh@Base 6
+ _D3std5range10primitives11__T4saveTkZ4saveFNaNbNdNiNfAkZAk@Base 6
+ _D3std5range10primitives12__ModuleInfoZ@Base 6
+ _D3std5range10primitives12__T4backTxaZ4backFNaNdNfAxaZw@Base 6
+ _D3std5range10primitives12__T4backTxhZ4backFNaNbNcNdNiNfAxhZxh@Base 6
+ _D3std5range10primitives12__T4backTyaZ4backFNaNdNfAyaZw@Base 6
+ _D3std5range10primitives12__T4saveTxaZ4saveFNaNbNdNiNfAxaZAxa@Base 6
+ _D3std5range10primitives12__T4saveTxhZ4saveFNaNbNdNiNfAxhZAxh@Base 6
+ _D3std5range10primitives12__T4saveTxuZ4saveFNaNbNdNiNfAxuZAxu@Base 6
+ _D3std5range10primitives12__T4saveTyaZ4saveFNaNbNdNiNfAyaZAya@Base 6
+ _D3std5range10primitives12__T5emptyTaZ5emptyFNaNbNdNiNfxAaZb@Base 6
+ _D3std5range10primitives12__T5emptyTbZ5emptyFNaNbNdNiNfxAbZb@Base 6
+ _D3std5range10primitives12__T5emptyThZ5emptyFNaNbNdNiNfxAhZb@Base 6
+ _D3std5range10primitives12__T5emptyTkZ5emptyFNaNbNdNiNfxAkZb@Base 6
+ _D3std5range10primitives12__T5emptyTuZ5emptyFNaNbNdNiNfxAuZb@Base 6
+ _D3std5range10primitives12__T5emptyTwZ5emptyFNaNbNdNiNfxAwZb@Base 6
+ _D3std5range10primitives12__T5frontTaZ5frontFNaNdNfAaZw@Base 6
+ _D3std5range10primitives12__T5frontThZ5frontFNaNbNcNdNiNfAhZh@Base 6
+ _D3std5range10primitives12__T5frontTkZ5frontFNaNbNcNdNiNfAkZk@Base 6
+ _D3std5range10primitives138__T6moveAtTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultTkZ6moveAtFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZk@Base 6
+ _D3std5range10primitives138__T6moveAtTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultTkZ6moveAtFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZk@Base 6
+ _D3std5range10primitives139__T9moveFrontTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ9moveFrontFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZk@Base 6
+ _D3std5range10primitives139__T9moveFrontTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ9moveFrontFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZk@Base 6
+ _D3std5range10primitives13__T3putTAkTkZ3putFNaNbNiNfKAkkZv@Base 6
+ _D3std5range10primitives13__T4backTAyaZ4backFNaNbNcNdNiNfAAyaZAya@Base 6
+ _D3std5range10primitives13__T4saveTAxaZ4saveFNaNbNdNiNfAAxaZAAxa@Base 6
+ _D3std5range10primitives13__T4saveTAyaZ4saveFNaNbNdNiNfAAyaZAAya@Base 6
+ _D3std5range10primitives13__T5frontTxaZ5frontFNaNdNfAxaZw@Base 6
+ _D3std5range10primitives13__T5frontTxhZ5frontFNaNbNcNdNiNfAxhZxh@Base 6
+ _D3std5range10primitives13__T5frontTxuZ5frontFNaNdNfAxuZw@Base 6
+ _D3std5range10primitives13__T5frontTxwZ5frontFNaNbNcNdNiNfAxwZxw@Base 6
+ _D3std5range10primitives13__T5frontTyaZ5frontFNaNdNfAyaZw@Base 6
+ _D3std5range10primitives13__T5frontTyhZ5frontFNaNbNcNdNiNfAyhZyh@Base 6
+ _D3std5range10primitives13__T5frontTywZ5frontFNaNbNcNdNiNfAywZyw@Base 6
+ _D3std5range10primitives14__T5emptyTAxaZ5emptyFNaNbNdNiNfxAAaZb@Base 6
+ _D3std5range10primitives14__T5emptyTAyaZ5emptyFNaNbNdNiNfxAAyaZb@Base 6
+ _D3std5range10primitives14__T5frontTAyaZ5frontFNaNbNcNdNiNfAAyaZAya@Base 6
+ _D3std5range10primitives14__T5frontTyAaZ5frontFNaNbNcNdNiNfAyAaZyAa@Base 6
+ _D3std5range10primitives14__T7popBackThZ7popBackFNaNbNiNfKAhZv@Base 6
+ _D3std5range10primitives14__T7popBackTkZ7popBackFNaNbNiNfKAkZv@Base 6
+ _D3std5range10primitives15__T5doPutTAkTkZ5doPutFNaNbNiNfKAkKkZv@Base 6
+ _D3std5range10primitives15__T7popBackTxhZ7popBackFNaNbNiNfKAxhZv@Base 6
+ _D3std5range10primitives15__T7popBackTyaZ7popBackFNaNfKAyaZv@Base 6
+ _D3std5range10primitives15__T8popFrontTaZ8popFrontFNaNbNiNeKAaZv@Base 6
+ _D3std5range10primitives15__T8popFrontTkZ8popFrontFNaNbNiNfKAkZv@Base 6
+ _D3std5range10primitives16__T7popBackTAyaZ7popBackFNaNbNiNfKAAyaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxaZ8popFrontFNaNbNiNeKAxaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxhZ8popFrontFNaNbNiNfKAxhZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxuZ8popFrontFNaNbNiNeKAxuZv@Base 6
+ _D3std5range10primitives16__T8popFrontTxwZ8popFrontFNaNbNiNfKAxwZv@Base 6
+ _D3std5range10primitives16__T8popFrontTyaZ8popFrontFNaNbNiNeKAyaZv@Base 6
+ _D3std5range10primitives16__T8popFrontTyhZ8popFrontFNaNbNiNfKAyhZv@Base 6
+ _D3std5range10primitives16__T8popFrontTywZ8popFrontFNaNbNiNfKAywZv@Base 6
+ _D3std5range10primitives17__T6moveAtTAxhTkZ6moveAtFNaNbNiNfAxhkZxh@Base 6
+ _D3std5range10primitives17__T8moveBackTAxhZ8moveBackFNaNbNiNfAxhZxh@Base 6
+ _D3std5range10primitives17__T8moveBackTAyaZ8moveBackFNaNfAyaZw@Base 6
+ _D3std5range10primitives17__T8popFrontTAyaZ8popFrontFNaNbNiNfKAAyaZv@Base 6
+ _D3std5range10primitives17__T8popFrontTyAaZ8popFrontFNaNbNiNfKAyAaZv@Base 6
+ _D3std5range10primitives17__T9popFrontNTAhZ9popFrontNFNaNbNiNfKAhkZk@Base 6
+ _D3std5range10primitives18__T3putTDFAxaZvTaZ3putFKDFAxaZvaZ16__T9__lambda3TaZ9__lambda3FNaNbNiNeKaZAa@Base 6
+ _D3std5range10primitives18__T3putTDFAxaZvTaZ3putFKDFAxaZvaZv@Base 6
+ _D3std5range10primitives18__T9moveFrontTAxhZ9moveFrontFNaNbNiNfAxhZxh@Base 6
+ _D3std5range10primitives18__T9moveFrontTAyaZ9moveFrontFNaNfAyaZw@Base 6
+ _D3std5range10primitives192__T9moveFrontTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ9moveFrontFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZw@Base 6
+ _D3std5range10primitives19__T10walkLengthTAhZ10walkLengthFNaNbNiNfAhZk@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTAaZ3putFKDFAxaZvAaZv@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTxaZ3putFKDFAxaZvxaZ17__T9__lambda3TxaZ9__lambda3FNaNbNiNeKxaZAxa@Base 6
+ _D3std5range10primitives19__T3putTDFAxaZvTxaZ3putFKDFAxaZvxaZv@Base 6
+ _D3std5range10primitives20__T10walkLengthTAyaZ10walkLengthFNaNbNiNfAyaZk@Base 6
+ _D3std5range10primitives20__T3putTDFAxaZvTAxaZ3putFKDFAxaZvAxaZv@Base 6
+ _D3std5range10primitives20__T3putTDFAxaZvTAyaZ3putFKDFAxaZvAyaZv@Base 6
+ _D3std5range10primitives21__T5doPutTDFAxaZvTAaZ5doPutFKDFAxaZvAaZv@Base 6
+ _D3std5range10primitives21__T5doPutTDFAxaZvTAaZ5doPutFKDFAxaZvKAaZv@Base 6
+ _D3std5range10primitives223__T10walkLengthTS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZ10walkLengthFNaNbNiNfS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakexkZk@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAxaZ5doPutFKDFAxaZvAxaZv@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAxaZ5doPutFKDFAxaZvKAxaZv@Base 6
+ _D3std5range10primitives22__T5doPutTDFAxaZvTAyaZ5doPutFKDFAxaZvKAyaZv@Base 6
+ _D3std5range10primitives24__T3putTDFNaNbNfAxaZvTaZ3putFKDFNaNbNfAxaZvaZ16__T9__lambda3TaZ9__lambda3FNaNbNiNeKaZAa@Base 6
+ _D3std5range10primitives24__T3putTDFNaNbNfAxaZvTaZ3putFNaNbNfKDFNaNbNfAxaZvaZv@Base 6
+ _D3std5range10primitives25__T14popBackExactlyTAAyaZ14popBackExactlyFNaNbNiNfKAAyakZv@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTAaZ3putFNaNbNfKDFNaNbNfAxaZvAaZv@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTxaZ3putFKDFNaNbNfAxaZvxaZ17__T9__lambda3TxaZ9__lambda3FNaNbNiNeKxaZAxa@Base 6
+ _D3std5range10primitives25__T3putTDFNaNbNfAxaZvTxaZ3putFNaNbNfKDFNaNbNfAxaZvxaZv@Base 6
+ _D3std5range10primitives26__T15popFrontExactlyTAAyaZ15popFrontExactlyFNaNbNiNfKAAyakZv@Base 6
+ _D3std5range10primitives26__T3putTDFNaNbNfAxaZvTAxaZ3putFNaNbNfKDFNaNbNfAxaZvAxaZv@Base 6
+ _D3std5range10primitives26__T3putTDFNaNbNfAxaZvTAyaZ3putFNaNbNfKDFNaNbNfAxaZvAyaZv@Base 6
+ _D3std5range10primitives27__T5doPutTDFNaNbNfAxaZvTAaZ5doPutFNaNbNfKDFNaNbNfAxaZvAaZv@Base 6
+ _D3std5range10primitives27__T5doPutTDFNaNbNfAxaZvTAaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAxaZ5doPutFNaNbNfKDFNaNbNfAxaZvAxaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAxaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAxaZv@Base 6
+ _D3std5range10primitives28__T5doPutTDFNaNbNfAxaZvTAyaZ5doPutFNaNbNfKDFNaNbNfAxaZvKAyaZv@Base 6
+ _D3std5range10primitives30__T5emptyTS3std4file8DirEntryZ5emptyFNaNbNdNiNfxAS3std4file8DirEntryZb@Base 6
+ _D3std5range10primitives31__T5emptyTS3std4json9JSONValueZ5emptyFNaNbNdNiNfxAS3std4json9JSONValueZb@Base 6
+ _D3std5range10primitives41__T14popBackExactlyTAC4core6thread5FiberZ14popBackExactlyFNaNbNiNfKAC4core6thread5FiberkZv@Base 6
+ _D3std5range10primitives42__T15popFrontExactlyTAC4core6thread5FiberZ15popFrontExactlyFNaNbNiNfKAC4core6thread5FiberkZv@Base 6
+ _D3std5range10primitives43__T5emptyTS3std5regex8internal2ir8BytecodeZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir8BytecodeZb@Base 6
+ _D3std5range10primitives45__T4backTS3std5regex8internal2ir10NamedGroupZ4backFNaNbNcNdNiNfAS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives45__T4saveTS3std5regex8internal2ir10NamedGroupZ4saveFNaNbNdNiNfAS3std5regex8internal2ir10NamedGroupZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives46__T3putTS3std5stdio4File17LockingTextWriterTaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriteraZv@Base 6
+ _D3std5range10primitives46__T3putTS3std5stdio4File17LockingTextWriterTwZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterwZv@Base 6
+ _D3std5range10primitives46__T5emptyTS3std5regex8internal2ir10NamedGroupZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5range10primitives46__T5frontTS3std5regex8internal2ir10NamedGroupZ5frontFNaNbNcNdNiNfAS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTAaZ3putFNfKS3std5stdio4File17LockingTextWriterAaZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTxaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterxaZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTxwZ3putFNbNiNfKS3std5stdio4File17LockingTextWriterxwZv@Base 6
+ _D3std5range10primitives47__T3putTS3std5stdio4File17LockingTextWriterTyaZ3putFNbNiNfKS3std5stdio4File17LockingTextWriteryaZv@Base 6
+ _D3std5range10primitives47__T6moveAtTS3std5range13__T6RepeatTiZ6RepeatTkZ6moveAtFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatkZi@Base 6
+ _D3std5range10primitives48__T3putTS3std5stdio4File17LockingTextWriterTAxaZ3putFNfKS3std5stdio4File17LockingTextWriterAxaZv@Base 6
+ _D3std5range10primitives48__T3putTS3std5stdio4File17LockingTextWriterTAyaZ3putFNfKS3std5stdio4File17LockingTextWriterAyaZv@Base 6
+ _D3std5range10primitives48__T5doPutTS3std5stdio4File17LockingTextWriterTaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKaZv@Base 6
+ _D3std5range10primitives48__T5doPutTS3std5stdio4File17LockingTextWriterTwZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKwZv@Base 6
+ _D3std5range10primitives48__T5emptyTS3std4file15DirIteratorImpl9DirHandleZ5emptyFNaNbNdNiNfxAS3std4file15DirIteratorImpl9DirHandleZb@Base 6
+ _D3std5range10primitives48__T7popBackTS3std5regex8internal2ir10NamedGroupZ7popBackFNaNbNiNfKAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5range10primitives48__T9moveFrontTS3std5range13__T6RepeatTiZ6RepeatZ9moveFrontFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatZi@Base 6
+ _D3std5range10primitives48__T9popFrontNTAS3std5regex8internal2ir8BytecodeZ9popFrontNFNaNbNiNfKAS3std5regex8internal2ir8BytecodekZk@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTAaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAaZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTxaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKxaZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTxwZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKxwZv@Base 6
+ _D3std5range10primitives49__T5doPutTS3std5stdio4File17LockingTextWriterTyaZ5doPutFNbNiNfKS3std5stdio4File17LockingTextWriterKyaZv@Base 6
+ _D3std5range10primitives49__T5emptyTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5emptyFNaNbNdNiNfxAS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std5range10primitives49__T8popFrontTS3std5regex8internal2ir10NamedGroupZ8popFrontFNaNbNiNfKAS3std5regex8internal2ir10NamedGroupZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderaZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTwZ3putFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderwZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderaZv@Base 6
+ _D3std5range10primitives50__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTwZ3putFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderwZv@Base 6
+ _D3std5range10primitives50__T5doPutTS3std5stdio4File17LockingTextWriterTAxaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAxaZv@Base 6
+ _D3std5range10primitives50__T5doPutTS3std5stdio4File17LockingTextWriterTAyaZ5doPutFNfKS3std5stdio4File17LockingTextWriterKAyaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTxaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderxaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTxwZ3putFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderxwZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTyaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderyaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTxaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderxaZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTxwZ3putFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderxwZv@Base 6
+ _D3std5range10primitives51__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTyaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderyaZv@Base 6
+ _D3std5range10primitives51__T4backTS3std8datetime13PosixTimeZone10LeapSecondZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives51__T4backTS3std8datetime13PosixTimeZone10TransitionZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives51__T4backTyS3std8internal14unicode_tables9CompEntryZ4backFNaNbNcNdNiNfAyS3std8internal14unicode_tables9CompEntryZyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives51__T4saveTS3std8datetime13PosixTimeZone10LeapSecondZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives51__T4saveTS3std8datetime13PosixTimeZone10TransitionZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone10TransitionZAS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives51__T4saveTyS3std8internal14unicode_tables9CompEntryZ4saveFNaNbNdNiNfAyS3std8internal14unicode_tables9CompEntryZAyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives51__T5emptyTS3std8internal14unicode_tables9CompEntryZ5emptyFNaNbNdNiNfxAS3std8internal14unicode_tables9CompEntryZb@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAxaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAxaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTAyaZ8AppenderTAyaZ3putFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderAyaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAxaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAxaZv@Base 6
+ _D3std5range10primitives52__T3putTS3std5array17__T8AppenderTyAaZ8AppenderTAyaZ3putFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderAyaZv@Base 6
+ _D3std5range10primitives52__T4backTyS3std8datetime13PosixTimeZone10LeapSecondZ4backFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives52__T4backTyS3std8datetime13PosixTimeZone10TransitionZ4backFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10TransitionZyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKaZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTwZ5doPutFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKwZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKaZv@Base 6
+ _D3std5range10primitives52__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTwZ5doPutFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKwZv@Base 6
+ _D3std5range10primitives52__T5emptyTS3std8datetime13PosixTimeZone10LeapSecondZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std5range10primitives52__T5emptyTS3std8datetime13PosixTimeZone10TransitionZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone10TransitionZb@Base 6
+ _D3std5range10primitives52__T5frontTS3std8datetime13PosixTimeZone10LeapSecondZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives52__T5frontTS3std8datetime13PosixTimeZone10TransitionZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives52__T5frontTyS3std8internal14unicode_tables9CompEntryZ5frontFNaNbNcNdNiNfAyS3std8internal14unicode_tables9CompEntryZyS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKxaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTxwZ5doPutFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKxwZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKyaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKxaZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTxwZ5doPutFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKxwZv@Base 6
+ _D3std5range10primitives53__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKyaZv@Base 6
+ _D3std5range10primitives53__T5frontTyS3std8datetime13PosixTimeZone10LeapSecondZ5frontFNaNbNcNdNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTAyaZ8AppenderTAyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAxaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAxaZv@Base 6
+ _D3std5range10primitives54__T5doPutTS3std5array17__T8AppenderTyAaZ8AppenderTAyaZ5doPutFNaNbNfKS3std5array17__T8AppenderTyAaZ8AppenderKAyaZv@Base 6
+ _D3std5range10primitives54__T5emptyTS3std5regex8internal2ir12__T5GroupTkZ5GroupZ5emptyFNaNbNdNiNfxAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5range10primitives54__T7popBackTS3std8datetime13PosixTimeZone10LeapSecondZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std5range10primitives54__T7popBackTS3std8datetime13PosixTimeZone10TransitionZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range10primitives54__T7popBackTyS3std8internal14unicode_tables9CompEntryZ7popBackFNaNbNiNfKAyS3std8internal14unicode_tables9CompEntryZv@Base 6
+ _D3std5range10primitives55__T4backTS3std8datetime13PosixTimeZone14TempTransitionZ4backFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives55__T4saveTS3std8datetime13PosixTimeZone14TempTransitionZ4saveFNaNbNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives55__T8popFrontTS3std8datetime13PosixTimeZone10LeapSecondZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std5range10primitives55__T8popFrontTS3std8datetime13PosixTimeZone10TransitionZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range10primitives55__T8popFrontTyS3std8internal14unicode_tables9CompEntryZ8popFrontFNaNbNiNfKAyS3std8internal14unicode_tables9CompEntryZv@Base 6
+ _D3std5range10primitives56__T5emptyTS3std8datetime13PosixTimeZone14TempTransitionZ5emptyFNaNbNdNiNfxAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std5range10primitives56__T5frontTS3std8datetime13PosixTimeZone14TempTransitionZ5frontFNaNbNcNdNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std5range10primitives56__T6moveAtTAS3std8datetime13PosixTimeZone10TransitionTkZ6moveAtFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionkZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives56__T8moveBackTAS3std8datetime13PosixTimeZone10TransitionZ8moveBackFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives57__T9moveFrontTAS3std8datetime13PosixTimeZone10TransitionZ9moveFrontFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range10primitives58__T4backTyS3std8internal14unicode_tables15UnicodePropertyZ4backFNaNbNcNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives58__T4saveTyS3std8internal14unicode_tables15UnicodePropertyZ4saveFNaNbNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives58__T5emptyTS3std8internal14unicode_tables15UnicodePropertyZ5emptyFNaNbNdNiNfxAS3std8internal14unicode_tables15UnicodePropertyZb@Base 6
+ _D3std5range10primitives58__T7popBackTS3std8datetime13PosixTimeZone14TempTransitionZ7popBackFNaNbNiNfKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std5range10primitives59__T5frontTyS3std8internal14unicode_tables15UnicodePropertyZ5frontFNaNbNcNdNiNfAyS3std8internal14unicode_tables15UnicodePropertyZyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std5range10primitives59__T8popFrontTS3std8datetime13PosixTimeZone14TempTransitionZ8popFrontFNaNbNiNfKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std5range10primitives61__T7popBackTyS3std8internal14unicode_tables15UnicodePropertyZ7popBackFNaNbNiNfKAyS3std8internal14unicode_tables15UnicodePropertyZv@Base 6
+ _D3std5range10primitives62__T6moveAtTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTkZ6moveAtFNaNbNiNfS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultkZa@Base 6
+ _D3std5range10primitives62__T8moveBackTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZ8moveBackFNaNbNiNfS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZa@Base 6
+ _D3std5range10primitives62__T8popFrontTyS3std8internal14unicode_tables15UnicodePropertyZ8popFrontFNaNbNiNfKAyS3std8internal14unicode_tables15UnicodePropertyZv@Base 6
+ _D3std5range10primitives63__T9moveFrontTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZ9moveFrontFNaNbNiNfS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultZa@Base 6
+ _D3std5range10primitives673__T3putTAkTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ3putFNaNfKAkS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZv@Base 6
+ _D3std5range10primitives678__T10walkLengthTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZ10walkLengthFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZk@Base 6
+ _D3std5range10primitives67__T4backTS3std12experimental6logger11multilogger16MultiLoggerEntryZ4backFNaNbNcNdNiNfAS3std12experimental6logger11multilogger16MultiLoggerEntryZS3std12experimental6logger11multilogger16MultiLoggerEntry@Base 6
+ _D3std5range10primitives70__T7popBackTS3std12experimental6logger11multilogger16MultiLoggerEntryZ7popBackFNaNbNiNfKAS3std12experimental6logger11multilogger16MultiLoggerEntryZv@Base 6
+ _D3std5range10primitives71__T5emptyTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5emptyFNaNbNdNiNfxAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZb@Base 6
+ _D3std5range10primitives75__T5emptyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5emptyFNaNbNdNiNfxAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZb@Base 6
+ _D3std5range10primitives76__T6moveAtTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTkZ6moveAtFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplkZa@Base 6
+ _D3std5range10primitives76__T8moveBackTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZa@Base 6
+ _D3std5range10primitives77__T9moveFrontTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZa@Base 6
+ _D3std5range10primitives78__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaZ3putFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkaZv@Base 6
+ _D3std5range10primitives78__T5emptyTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZ5emptyFNaNbNdNiNfxAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZb@Base 6
+ _D3std5range10primitives78__T6moveAtTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTkZ6moveAtFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplkZxa@Base 6
+ _D3std5range10primitives78__T6moveAtTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTkZ6moveAtFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplkZya@Base 6
+ _D3std5range10primitives78__T8moveBackTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZxa@Base 6
+ _D3std5range10primitives78__T8moveBackTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ8moveBackFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZya@Base 6
+ _D3std5range10primitives79__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAaZ3putFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkAaZv@Base 6
+ _D3std5range10primitives79__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTxaZ3putFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxaZv@Base 6
+ _D3std5range10primitives79__T9moveFrontTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZxa@Base 6
+ _D3std5range10primitives79__T9moveFrontTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ9moveFrontFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZya@Base 6
+ _D3std5range10primitives80__T3putTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAxaZ3putFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkAxaZv@Base 6
+ _D3std5range10primitives80__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaZ5doPutFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKaZv@Base 6
+ _D3std5range10primitives81__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAaZ5doPutFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKAaZv@Base 6
+ _D3std5range10primitives81__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTxaZ5doPutFNaNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKxaZv@Base 6
+ _D3std5range10primitives82__T5doPutTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTAxaZ5doPutFNaNbNfKS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKAxaZv@Base 6
+ _D3std5range11__T4iotaTkZ4iotaFNaNbNiNfkZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range11__T4onlyTaZ4onlyFNaNbNiNfaZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range12__ModuleInfoZ@Base 6
+ _D3std5range12__T4takeTAhZ4takeFNaNbNiNfAhkZAh@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4backMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4saveMFNaNbNdNiNfZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5frontMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6moveAtMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7opIndexMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8moveBackMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9moveFrontMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4backMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take4saveMFNaNbNdNiNfZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take5frontMFNdNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6__initZ@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take6moveAtMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7opIndexMFNfkZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8moveBackMFNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take9moveFrontMFNfZk@Base 6
+ _D3std5range134__T4takeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4takeFNaNbNiNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range134__T4takeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4takeFNaNbNiNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFNaNbNiNfkkZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result4backMNgFNaNbNdNiNfZNgk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result4saveMFNaNbNdNiNfZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result5frontMNgFNaNbNdNiNfZNgk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6__ctorMFNaNbNcNiNfkkZS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6__initZ@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7opIndexMNgFNaNbNiNfmZNgk@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7opSliceMNgFNaNbNiNfZNgS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7opSliceMNgFNaNbNiNfmmZNgS3std5range13__T4iotaTkTkZ4iotaFkkZ6Result@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range13__T4iotaTkTkZ4iotaFkkZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat11DollarToken6__initZ@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat4backMNgFNaNbNdNiNfZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat4saveMNgFNaNbNdNiNfZNgS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat5frontMNgFNaNbNdNiNfZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat6__initZ@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opIndexMNgFNaNbNiNfkZNgi@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opSliceMFNaNbNfkkZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7opSliceMNgFNaNbNiNfkS3std5range13__T6RepeatTiZ6Repeat11DollarTokenZNgS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6RepeatTiZ6Repeat8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range13__T6repeatTiZ6repeatFNaNbNiNfiZS3std5range13__T6RepeatTiZ6Repeat@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result10retroIndexMFNaNbNiNfkZk@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result4backMFNaNbNcNdNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result5frontMFNaNbNcNdNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6moveAtMFNaNbNiNfkZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7opIndexMFNaNbNcNiNfkZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7opSliceMFNaNbNiNfkkZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result8moveBackMFNaNbNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6ResultZk@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result9moveFrontMFNaNbNiNfZxh@Base 6
+ _D3std5range14__T5retroTAxhZ5retroFNaNbNiNfAxhZS3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result4backMFNaNdNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result5frontMFNaNdNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result8moveBackMFNaNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZk@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result9moveFrontMFNaNfZw@Base 6
+ _D3std5range14__T5retroTAyaZ5retroFNaNbNiNfAyaZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11DollarToken6__initZ@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11DollarToken9momLengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks11__xopEqualsFKxS3std5range14__T6ChunksTAhZ6ChunksKxS3std5range14__T6ChunksTAhZ6ChunksZb@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks4backMFNaNbNdNiNfZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks4saveMFNaNbNdNiNfZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks5frontMFNaNbNdNiNfZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6__ctorMFNaNbNcNiNfAhkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6__initZ@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opIndexMFNaNbNiNfkZAh@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfkS3std5range14__T6ChunksTAhZ6Chunks11DollarTokenZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7opSliceMFNaNbNiNfkkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks8opDollarMFNaNbNiNfZS3std5range14__T6ChunksTAhZ6Chunks11DollarToken@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range14__T6ChunksTAhZ6Chunks9__xtoHashFNbNeKxS3std5range14__T6ChunksTAhZ6ChunksZk@Base 6
+ _D3std5range14__T6chunksTAhZ6chunksFNaNbNiNfAhkZS3std5range14__T6ChunksTAhZ6Chunks@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take11__xopEqualsFKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZb@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take4saveMFNaNbNdNiNfZS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take5frontMFNaNbNdNiNfZw@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take6__initZ@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9__xtoHashFNbNeKxS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4TakeZk@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take9moveFrontMFNaNbNiNfZw@Base 6
+ _D3std5range187__T4takeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4takeFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkZS3std5range187__T4TakeTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ4Take@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfkZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfkZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfkkZS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZk@Base 6
+ _D3std5range187__T5chainTS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfkkZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6ResultZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result11__xopEqualsFKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result4backMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result4saveMFNaNbNdNiNfZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result5frontMFNaNbNdNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__ctorMFNaNbNcNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6fixRefFNaNbNiNfxaZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6moveAtMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7opIndexMFNaNbNiNfkZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7opSliceMFNaNbNiNfkkZS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result8moveBackMFNaNbNiNfZxa@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result9__xtoHashFNbNeKxS3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6ResultZk@Base 6
+ _D3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result9moveFrontMFNaNbNiNfZxa@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange13__T3geqTywTwZ3geqMFNaNbNiNfywwZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange287__T18getTransitionIndexVE3std5range12SearchPolicyi3S2293std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange3geqTwZ18getTransitionIndexMFNaNbNiNfwZk@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi3TwZ10lowerBoundMFNaNbNiNfwZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange4backMFNaNbNdNiNfZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNdNiNfZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNiNfkZyw@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRangeZk@Base 6
+ _D3std5range200__T12assumeSortedVAyaa5_61203c2062TS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZ12assumeSortedFNaNbNiNfS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std5range199__T11SortedRangeTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange11__xopEqualsFKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeZb@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange4backMFNaNbNdNiNfZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange4saveMFNaNbNdNiNfZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange5frontMFNaNbNdNiNfZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__ctorMFNaNbNcNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6__initZ@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7opIndexMFNaNbNiNfkZS3std3uni17CodepointInterval@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange7releaseMFNaNbNiZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRange9__xtoHashFNbNeKxS3std5range201__T11SortedRangeTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1Z11SortedRangeZk@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult11__T6__ctorZ6__ctorMFNaNbNcNiNfKaZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult4backMFNaNbNdNiNfZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult4saveMFNaNbNdNiNfZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult5frontMFNaNbNdNiNfZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6__initZ@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7opIndexMFNaNbNiNfkZa@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7opSliceMFNaNbNiNfZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7opSliceMFNaNbNiNfkkZS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range23__T10OnlyResultTaHVki1Z10OnlyResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFNaNbNiNfS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result11__xopEqualsFKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZb@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result4saveMFNaNdNfZS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result5emptyMFNaNdNfZb@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result5frontMFNaNdNfZk@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result6__initZ@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result9__xtoHashFNbNeKxS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange11__xopEqualsFKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange121__T18getTransitionIndexVE3std5range12SearchPolicyi3S643std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange3geqTkZ18getTransitionIndexMFNaNbNiNfkZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange12__T3geqTkTkZ3geqMFNaNbNiNfkkZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi3TkZ10lowerBoundMFNaNbNiNfkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange4saveMFNaNbNdNiNfZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__initZ@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7opIndexMFNaNbNcNiNfkZk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange9__xtoHashFNbNeKxS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRangeZk@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange455__T18getTransitionIndexVE3std5range12SearchPolicyi3S3953std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZk@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZk@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange458__T18getTransitionIndexVE3std5range12SearchPolicyi3S3983std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZk@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZk@Base 6
+ _D3std5range36__T12assumeSortedVAyaa4_613c3d62TAkZ12assumeSortedFNaNbNiNfAkZS3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange11__xopEqualsFKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange16__T3geqTAyaTAxaZ3geqMFNaNfAyaAxaZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange461__T18getTransitionIndexVE3std5range12SearchPolicyi3S4013std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange3geqTAxaZ18getTransitionIndexMFNaNfAxaZk@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange48__T10lowerBoundVE3std5range12SearchPolicyi3TAxaZ10lowerBoundMFNaNfAxaZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange4saveMFNaNbNdNiNfZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__ctorMFNaNbNcNiNfS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange7releaseMFNaNbNiZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange9__xtoHashFNbNeKxS3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRangeZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange123__T18getTransitionIndexVE3std5range12SearchPolicyi2S663std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange3geqTiZ18getTransitionIndexMFNaNbNiNfiZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange123__T18getTransitionIndexVE3std5range12SearchPolicyi3S663std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange3geqTiZ18getTransitionIndexMFNaNbNiNfiZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange12__T3geqTkTiZ3geqMFNaNbNiNfkiZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange46__T10lowerBoundVE3std5range12SearchPolicyi2TiZ10lowerBoundMFNaNbNiNfiZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNcNiNfkZk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRangeZk@Base 6
+ _D3std5range38__T12assumeSortedVAyaa5_61203c2062TAkZ12assumeSortedFNaNbNiNfAkZS3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange11__xopEqualsFKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeZb@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange4backMFNaNbNcNdNiNfZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange5frontMFNaNbNcNdNiNfZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__ctorMFNaNbNcNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7opIndexMFNaNbNcNiNfkZAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange7releaseMFNaNbNiZAAya@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange9__xtoHashFNbNeKxS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRangeZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange11__xopEqualsFKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange126__T18getTransitionIndexVE3std5range12SearchPolicyi3S683std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange3geqTyiZ18getTransitionIndexMFNaNbNiNfyiZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange13__T3geqTkTyiZ3geqMFNaNbNiNfkyiZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange47__T10lowerBoundVE3std5range12SearchPolicyi3TyiZ10lowerBoundMFNaNbNiNfyiZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange4backMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange4saveMFNaNbNdNiNfZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange5frontMFNaNbNcNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__ctorMFNaNbNcNiNfAkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__initZ@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7opIndexMFNaNbNcNiNfkZk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange7releaseMFNaNbNiZAk@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange9__xtoHashFNbNeKxS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRangeZk@Base 6
+ _D3std5range40__T12assumeSortedVAyaa5_61203c2062TAAyaZ12assumeSortedFNaNbNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std5range40__T12assumeSortedVAyaa6_61203c3d2062TAkZ12assumeSortedFNaNbNiNfAkZS3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take4backMFNaNbNdNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take4saveMFNaNbNdNiNfZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take5frontMFNaNbNdNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6__initZ@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6moveAtMFNaNbNiNfkZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take7opIndexMFNaNbNiNfkZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take8moveBackMFNaNbNiNfZi@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take9maxLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take9moveFrontMFNaNbNiNfZi@Base 6
+ _D3std5range51__T11takeExactlyTS3std5range13__T6RepeatTiZ6RepeatZ11takeExactlyFNaNbNiNfS3std5range13__T6RepeatTiZ6RepeatkZS3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result10retroIndexMFNaNbNiNfkZk@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result11__xopEqualsFKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultZb@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result13opIndexAssignMFNaNbNiNfS3std8datetime13PosixTimeZone10TransitionkZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4backMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4backMFNaNbNdNiNfS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result4saveMFNaNbNdNiNfZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5frontMFNaNbNcNdNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result5frontMFNaNbNdNiNfS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6__initZ@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result6moveAtMFNaNbNiNfkZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7opIndexMFNaNbNcNiNfkZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7opSliceMFNaNbNiNfkkZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result8moveBackMFNaNbNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result9__xtoHashFNbNeKxS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6ResultZk@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result9moveFrontMFNaNbNiNfZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFNaNbNiNfAS3std8datetime13PosixTimeZone10TransitionZS3std5range53__T5retroTAS3std8datetime13PosixTimeZone10TransitionZ5retroFAS3std8datetime13PosixTimeZone10TransitionZ11__T6ResultZ6Result@Base 6
+ _D3std5range69__T5retroTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ5retroFNaNbNiNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZAya@Base 6
+ _D3std5range8NullSink6__initZ@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange11__xopEqualsFKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange15dbgVerifySortedMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange213__T18getTransitionIndexVE3std5range12SearchPolicyi3S1213std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange3geqTS3std5regex8internal2ir10NamedGroupZ18getTransitionIndexMFNaNbNiNfS3std5regex8internal2ir10NamedGroupZk@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange4backMFNaNbNcNdNiNfZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange4saveMFNaNbNdNiNfZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange5frontMFNaNbNcNdNiNfZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__ctorMFNaNbNcNiNfAS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6__initZ@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7opIndexMFNaNbNcNiNfkZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7opSliceMFNaNbNiNfkkZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange7releaseMFNaNbNiZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange80__T10lowerBoundVE3std5range12SearchPolicyi3TS3std5regex8internal2ir10NamedGroupZ10lowerBoundMFNaNbNiNfS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange80__T3geqTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ3geqMFNaNbNiNfS3std5regex8internal2ir10NamedGroupS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange9__xtoHashFNbNeKxS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRangeZk@Base 6
+ _D3std5range93__T12assumeSortedVAyaa15_612e6e616d65203c20622e6e616d65TAS3std5regex8internal2ir10NamedGroupZ12assumeSortedFNaNbNiNfAS3std5regex8internal2ir10NamedGroupZS3std5range92__T11SortedRangeTAS3std5regex8internal2ir10NamedGroupVAyaa15_612e6e616d65203c20622e6e616d65Z11SortedRange@Base 6
+ _D3std5regex12__ModuleInfoZ@Base 6
+ _D3std5regex14__T5regexTAyaZ5regexFNeAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures10newMatchesMFNaNbNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures11__xopEqualsFKxS3std5regex18__T8CapturesTAaTkZ8CapturesKxS3std5regex18__T8CapturesTAaTkZ8CapturesZb@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures12__T7opIndexZ7opIndexMFNaNbNekZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures3hitMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures3preMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures4backMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures4postMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures59__T6__ctorS453std5regex8internal8thompson15ThompsonMatcherZ6__ctorMFNaNbNcNeKS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures5frontMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures6__initZ@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures7matchesMFNaNbNdNiNeZAS3std5regex8internal2ir12__T5GroupTkZ5Group@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures7popBackMFNaNbNiNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures8capturesMFNaNbNcNdNiNeZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures8popFrontMFNaNbNiNeZv@Base 6
+ _D3std5regex18__T8CapturesTAaTkZ8Captures9__xtoHashFNbNeKxS3std5regex18__T8CapturesTAaTkZ8CapturesZk@Base 6
+ _D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures10newMatchesMFNaNbNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures11__xopEqualsFKxS3std5regex19__T8CapturesTAxaTkZ8CapturesKxS3std5regex19__T8CapturesTAxaTkZ8CapturesZb@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures12__T7opIndexZ7opIndexMFNaNbNekZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures3hitMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures3preMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures4backMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures4postMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures59__T6__ctorS453std5regex8internal8thompson15ThompsonMatcherZ6__ctorMFNaNbNcNeKS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures5emptyMxFNaNbNdNiNeZb@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures5frontMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures6__initZ@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures7matchesMFNaNbNdNiNeZAS3std5regex8internal2ir12__T5GroupTkZ5Group@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures7popBackMFNaNbNiNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures8capturesMFNaNbNcNdNiNeZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures8popFrontMFNaNbNiNeZv@Base 6
+ _D3std5regex19__T8CapturesTAxaTkZ8Captures9__xtoHashFNbNeKxS3std5regex19__T8CapturesTAxaTkZ8CapturesZk@Base 6
+ _D3std5regex57__T5matchTAaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ5matchFNfAaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex58__T5matchTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ5matchFNfAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch10__postblitMFNaNbNiNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch11__xopEqualsFKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZb@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3hitMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3preMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4postMFNaNbNdNiNeZAa@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4saveMFNaNbNiNeZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch55__T6__ctorTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ6__ctorMFNcNeAaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5frontMFNaNbNdNiNeZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__dtorMFNbNiNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch7counterMFNaNbNcNdNiNeZk@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8capturesMFNaNbNdNiNeZS3std5regex18__T8CapturesTAaTkZ8Captures@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8opAssignMFNbNcNiNjNeS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8popFrontMFNeZv@Base 6
+ _D3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch9__xtoHashFNbNeKxS3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZk@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch10__postblitMFNaNbNiNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch11__xopEqualsFKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZb@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3hitMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch3preMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4postMFNaNbNdNiNeZAxa@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch4saveMFNaNbNiNeZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch55__T6__ctorTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ6__ctorMFNcNeAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch5frontMFNaNbNdNiNeZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__dtorMFNbNiNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch7counterMFNaNbNcNdNiNeZk@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8capturesMFNaNbNdNiNeZS3std5regex19__T8CapturesTAxaTkZ8Captures@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8opAssignMFNbNcNiNjNeS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch8popFrontMFNeZv@Base 6
+ _D3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch9__xtoHashFNbNeKxS3std5regex68__T10RegexMatchTAxaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatchZk@Base 6
+ _D3std5regex8internal12backtracking10__T5ctSubZ5ctSubFNaNbNiNeAyaZAya@Base 6
+ _D3std5regex8internal12backtracking12__ModuleInfoZ@Base 6
+ _D3std5regex8internal12backtracking12__T5ctSubTiZ5ctSubFNaNbNeAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking12__T5ctSubTkZ5ctSubFNaNbNeAyakZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTAyaZ5ctSubFNaNbNeAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTiTiZ5ctSubFNaNbNeAyaiiZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTkTiZ5ctSubFNaNbNeAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking14__T5ctSubTkTkZ5ctSubFNaNbNeAyakkZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTAyaTiZ5ctSubFNaNbNeAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTiTAyaZ5ctSubFNaNbNeAyaiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTiTkTiZ5ctSubFNaNbNeAyaikiZAya@Base 6
+ _D3std5regex8internal12backtracking16__T5ctSubTkTAyaZ5ctSubFNaNbNeAyakAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTAyaTkTiZ5ctSubFNaNbNeAyaAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTiTAyaTiZ5ctSubFNaNbNeAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTiTiTAyaZ5ctSubFNaNbNeAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking18__T5ctSubTkTiTkTiZ5ctSubFNaNbNeAyakikiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTAyaTAyaTiZ5ctSubFNaNbNeAyaAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTiTiTAyaTiZ5ctSubFNaNbNeAyaiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTkTAyaTAyaZ5ctSubFNaNbNeAyakAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking20__T5ctSubTkTAyaTkTiZ5ctSubFNaNbNeAyakAyakiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTAyaTiTiTAyaZ5ctSubFNaNbNeAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTiTAyaTAyaTiZ5ctSubFNaNbNeAyaiAyaAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking22__T5ctSubTkTiTiTAyaTiZ5ctSubFNaNbNeAyakiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTAyaTiTiTAyaTiZ5ctSubFNaNbNeAyaAyaiiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking24__T5ctSubTkTAyaTAyaTAyaZ5ctSubFNaNbNeAyakAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTAyaTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking26__T5ctSubTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyakiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking28__T5ctSubTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10bwdMatcherMFNaNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10fwdMatcherMFNaNbNiNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10initializeMFNaNbNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher10stackAvailMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher11__xopEqualsFKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher13matchFinalizeMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher4nextMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5atEndMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__ctorMFNaNbNcNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvwkZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__ctorMFNaNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher6searchMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher8newStackMFNbNiNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9__xtoHashFNbNeKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9matchImplMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9prevStackMFNbNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher9stackSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10bwdMatcherMFNaNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10fwdMatcherMFNaNbNiNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10initializeMFNaNbNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher10stackAvailMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher11__xopEqualsFKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher13matchFinalizeMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher4nextMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5State6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5atEndMFNaNdNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__ctorMFNaNbNcNiNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvwkZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__ctorMFNaNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperAvZS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6__initZ@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher6searchMFNaNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher8newStackMFNbNiNeZv@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9__xtoHashFNbNeKxS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcherZk@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9matchImplMFNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9prevStackMFNbNiNeZb@Base 6
+ _D3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z83__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ19BacktrackingMatcher9stackSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal12backtracking30__T5ctSubTiTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking32__T5ctSubTiTiTiTAyaTAyaTiTiTAyaZ5ctSubFNaNbNeAyaiiiAyaAyaiiAyaZAya@Base 6
+ _D3std5regex8internal12backtracking34__T5ctSubTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking36__T5ctSubTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking36__T5ctSubTiTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking38__T5ctSubTiTiTiTAyaTAyaTiTAyaTiTAyaTiZ5ctSubFNaNbNeAyaiiiAyaAyaiAyaiAyaiZAya@Base 6
+ _D3std5regex8internal12backtracking40__T5ctSubTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking42__T5ctSubTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking46__T5ctSubTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking50__T5ctSubTAyaTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking52__T5ctSubTiTAyaTAyaTiTAyaTAyaTAyaTkTkTiTAyaTAyaTAyaZ5ctSubFNaNbNeAyaiAyaAyaiAyaAyaAyakkiAyaAyaAyaZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctAtomCodeMFAS3std5regex8internal2ir8BytecodeiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenBlockMFAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenGroupMFKAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext10ctGenRegExMFAS3std5regex8internal2ir8BytecodeZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext10lookaroundMFkkZS3std5regex8internal12backtracking9CtContext@Base 6
+ _D3std5regex8internal12backtracking9CtContext11ctQuickTestMFAS3std5regex8internal2ir8BytecodeiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext11restoreCodeMFZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext14ctGenFixupCodeMFAS3std5regex8internal2ir8BytecodeiiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext14ctGenFixupCodeMFKAS3std5regex8internal2ir8BytecodeiiZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext16ctGenAlternationMFAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal12backtracking9CtContext6__initZ@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState11__xopEqualsFKxS3std5regex8internal12backtracking9CtContext7CtStateKxS3std5regex8internal12backtracking9CtContext7CtStateZb@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D3std5regex8internal12backtracking9CtContext7CtState9__xtoHashFNbNeKxS3std5regex8internal12backtracking9CtContext7CtStateZk@Base 6
+ _D3std5regex8internal12backtracking9CtContext8saveCodeMFkAyaZAya@Base 6
+ _D3std5regex8internal12backtracking9CtContext9ctGenAtomMFKAS3std5regex8internal2ir8BytecodeiZS3std5regex8internal12backtracking9CtContext7CtState@Base 6
+ _D3std5regex8internal2ir10NamedGroup11__xopEqualsFKxS3std5regex8internal2ir10NamedGroupKxS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D3std5regex8internal2ir10NamedGroup9__xtoHashFNbNeKxS3std5regex8internal2ir10NamedGroupZk@Base 6
+ _D3std5regex8internal2ir10lengthOfIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir11RegexOption6__initZ@Base 6
+ _D3std5regex8internal2ir11disassembleFNexAS3std5regex8internal2ir8BytecodekxAS3std5regex8internal2ir10NamedGroupZAya@Base 6
+ _D3std5regex8internal2ir12__ModuleInfoZ@Base 6
+ _D3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper11__xopEqualsFKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper5atEndMFNaNdNfZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper5resetMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__ctorMFNaNbNcNiNfS3std5regex8internal2ir12__T5InputTaZ5InputkZS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper7opSliceMFNaNbNiNfkkZAxa@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper8loopBackMFNaNbNiNfkZS3std5regex8internal2ir12__T5InputTaZ5Input@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper8nextCharMFNaNeKwKkZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZk@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper9lastIndexMFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input11__xopEqualsFKxS3std5regex8internal2ir12__T5InputTaZ5InputKxS3std5regex8internal2ir12__T5InputTaZ5InputZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input5atEndMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input5resetMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input66__T6searchTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZ6searchMFNaNfKS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrKwKkZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input6__ctorMFNaNbNcNiNfAxakZS3std5regex8internal2ir12__T5InputTaZ5Input@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input7opSliceMFNaNbNiNfkkZAxa@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input8loopBackMFNaNbNiNfkZS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input8nextCharMFNaNfKwKkZb@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5InputTaZ5InputZk@Base 6
+ _D3std5regex8internal2ir12__T5InputTaZ5Input9lastIndexMFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex11__xopEqualsFKxS3std5regex8internal2ir12__T5RegexTaZ5RegexKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNaNbNdNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange11__xopEqualsFKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange4backMFNaNbNdNiNfZAya@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange4saveMFNaNbNdNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange5frontMFNaNbNdNiNfZAya@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__ctorMFNaNbNcNiNfAS3std5regex8internal2ir10NamedGroupkkZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7opSliceMFNaNbNiNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7opSliceMFNaNbNiNfkkZS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRangeZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex14checkIfOneShotMFZv@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex9__xtoHashFNbNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal2ir12__T5RegexTaZ5Regex9isBackrefMFNaNbNiNfkZk@Base 6
+ _D3std5regex8internal2ir13wordCharacterFNdZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir14RegexException6__ctorMFNeAyaAyakZC3std5regex8internal2ir14RegexException@Base 6
+ _D3std5regex8internal2ir14RegexException6__initZ@Base 6
+ _D3std5regex8internal2ir14RegexException6__vtblZ@Base 6
+ _D3std5regex8internal2ir14RegexException7__ClassZ@Base 6
+ _D3std5regex8internal2ir14__T9endOfLineZ9endOfLineFNaNbNiNfwbZb@Base 6
+ _D3std5regex8internal2ir16lengthOfPairedIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir17__T11startOfLineZ11startOfLineFNaNbNiNfwbZb@Base 6
+ _D3std5regex8internal2ir17immediateParamsIRFE3std5regex8internal2ir2IRZi@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex11__xopEqualsFKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexZb@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__ctorMFNaNbNcNiNfS3std5regex8internal2ir12__T5RegexTaZ5RegexPFNeKS3std5regex8internal12backtracking29__T19BacktrackingMatcherVbi1Z71__T19BacktrackingMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ19BacktrackingMatcherZbZS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__initZ@Base 6
+ _D3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex9__xtoHashFNbNeKxS3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegexZk@Base 6
+ _D3std5regex8internal2ir19__T11mallocArrayTkZ11mallocArrayFNbNikZAk@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZ11initializedb@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZ4slotS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir207__T11memoizeExprVAyaa91_756e69636f64652e416c7068616265746963207c20756e69636f64652e4d6e207c20756e69636f64652e4d630a20202020202020207c20756e69636f64652e4d65207c20756e69636f64652e4e64207c20756e69636f64652e5063Z11memoizeExprFNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal2ir20__T12arrayInChunkTkZ12arrayInChunkFNaNbNikKAvZAk@Base 6
+ _D3std5regex8internal2ir2IR6__initZ@Base 6
+ _D3std5regex8internal2ir62__T12quickTestFwdTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ12quickTestFwdFNaNbNiNfkwKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZi@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZ11initializedb@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZ4slotS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir71__T11memoizeExprVAyaa23_6d616b655472696528776f726443686172616374657229Z11memoizeExprFNeZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir7getTrieFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir7isEndIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8Bytecode11indexOfPairMxFkZk@Base 6
+ _D3std5regex8internal2ir8Bytecode11setLocalRefMFZv@Base 6
+ _D3std5regex8internal2ir8Bytecode12pairedLengthMxFNdZk@Base 6
+ _D3std5regex8internal2ir8Bytecode13__T8mnemonicZ8mnemonicMxFNaNdNeZAya@Base 6
+ _D3std5regex8internal2ir8Bytecode13__T8sequenceZ8sequenceMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir8Bytecode13backreferenceMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode14setBackrefenceMFZv@Base 6
+ _D3std5regex8internal2ir8Bytecode4argsMxFNdZi@Base 6
+ _D3std5regex8internal2ir8Bytecode5isEndMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode6__ctorMFNcE3std5regex8internal2ir2IRkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode6__ctorMFNcE3std5regex8internal2ir2IRkkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D3std5regex8internal2ir8Bytecode6isAtomMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode6lengthMxFNdZk@Base 6
+ _D3std5regex8internal2ir8Bytecode6pairedMxFNdZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode7fromRawFkZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std5regex8internal2ir8Bytecode7hotspotMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode7isStartMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode8localRefMxFNdZb@Base 6
+ _D3std5regex8internal2ir8Bytecode9__T4codeZ4codeMxFNaNbNdNiNfZE3std5regex8internal2ir2IR@Base 6
+ _D3std5regex8internal2ir8Bytecode9__T4dataZ4dataMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal2ir8hasMergeFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8isAtomIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir8pairedIRFE3std5regex8internal2ir2IRZE3std5regex8internal2ir2IR@Base 6
+ _D3std5regex8internal2ir8wordTrieFNdZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal2ir9RegexInfo6__initZ@Base 6
+ _D3std5regex8internal2ir9isStartIRFE3std5regex8internal2ir2IRZb@Base 6
+ _D3std5regex8internal2ir9trieCacheHS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal5tests12__ModuleInfoZ@Base 6
+ _D3std5regex8internal6parser11caseEncloseFNaS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser12__ModuleInfoZ@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack11__xopEqualsFKxS3std5regex8internal6parser12__T5StackTkZ5StackKxS3std5regex8internal6parser12__T5StackTkZ5StackZb@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack3popMFNbNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack3topMFNaNbNcNdNiNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack4pushMFNaNbNekZv@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser12__T5StackTkZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser12__T5StackTkZ5StackZk@Base 6
+ _D3std5regex8internal6parser13getUnicodeSetFNexAabbZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser10parseRegexMFNeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11__xopEqualsFKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11charsetToIrMFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11isOpenGroupMFNaNbNiNfkZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11markBackrefMFNaNbNfkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser11parseEscapeMFNeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ101__T11unrollWhileS813std10functional54__T8unaryFunVAyaa12_61203d3d20612e556e696f6eVAyaa1_61Z8unaryFunZ11unrollWhileFNfKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ5applyFNfE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZ99__T11unrollWhileS793std10functional52__T8unaryFunVAyaa11_6120213d20612e4f70656eVAyaa1_61Z8unaryFunZ11unrollWhileFNfKS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseCharsetMFZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser12parseDecimalMFNfZk@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13fixLookaroundMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13genLookaroundMFE3std5regex8internal2ir2IRZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ12addWithFlagsFNaNbKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListkkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ18twinSymbolOperatorFNaNbNiNfwZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser15__T6__ctorTAxaZ6__ctorMFNcNeAyaAxaZS3std5regex8internal6parser15__T6ParserTAyaZ6Parser@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser15parseQuantifierMFNekZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser16parseControlCodeMFNaNfZw@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser17finishAlternationMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser20__T10parseFlagsTAxaZ10parseFlagsMFNeAxaZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser24parseUnicodePropertySpecMFNfbZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser3putMFNaNfS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser4nextMFNaNfZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser5_nextMFNaNfZb@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser5errorMFNeAyaZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser6__initZ@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser6putRawMFkZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser7currentMFNaNbNdNiNfZw@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser7programMFNdNfZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9__xtoHashFNbNeKxS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZk@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9parseAtomMFZv@Base 6
+ _D3std5regex8internal6parser15__T6ParserTAyaZ6Parser9skipSpaceMFNaNfZv@Base 6
+ _D3std5regex8internal6parser18__T9makeRegexTAyaZ9makeRegexFNfS3std5regex8internal6parser15__T6ParserTAyaZ6ParserZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std5regex8internal6parser20__T11parseUniHexTyaZ11parseUniHexFNaNfKAyakZw@Base 6
+ _D3std5regex8internal6parser21__T15reverseBytecodeZ15reverseBytecodeFNeAS3std5regex8internal2ir8BytecodeZv@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack11__xopEqualsFKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackZb@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack3popMFNaNbNiNfZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack3topMFNaNbNcNdNiNfZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack4pushMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack6__initZ@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStack9__xtoHashFNbNeKxS3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZ18__T10FixedStackTkZ10FixedStackZk@Base 6
+ _D3std5regex8internal6parser24__T16lightPostprocessTaZ16lightPostprocessFNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexZv@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack11__xopEqualsFKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackZb@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack3popMFNbNeZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack3topMFNaNbNcNdNiNeZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack4pushMFNaNbNeS3std8typecons16__T5TupleTkTkTkZ5TupleZv@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5StackZk@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack11__xopEqualsFKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZb@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack3popMFNbNeZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack3topMFNaNbNcNdNiNeZE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack4pushMFNaNbNeE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZv@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser71__T5StackTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5StackZk@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack11__xopEqualsFKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZb@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack3popMFNbNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack3topMFNaNbNcNdNiNeZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack4pushMFNaNbNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZv@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack5emptyMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6__initZ@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack6lengthMFNaNbNdNiNeZk@Base 6
+ _D3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5Stack9__xtoHashFNbNeKxS3std5regex8internal6parser75__T5StackTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ5StackZk@Base 6
+ _D3std5regex8internal6parser7getTrieFNeS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal6parser9trieCacheHS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std5regex8internal8thompson12__ModuleInfoZ@Base 6
+ _D3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList10insertBackMFNaNbNiNfPS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange5frontMFNaNbNdNiNfZPxS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange6__ctorMFNaNbNcNiNfS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadListZS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange8popFrontMFNaNbNdNiNfZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11insertFrontMFNaNbNiNfPS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList5fetchMFNaNbNiNfZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList6__initZ@Base 6
+ _D3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList7opSliceMFNaNbNiNfZS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std5regex8internal2ir12__T5RegexTaZ5RegexS3std5regex8internal2ir12__T5InputTaZ5InputAvZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11__xopEqualsFKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11createStartMFNaNbNiNekkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher12matchOneShotMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupkZE3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher11MatchResult@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13__T4evalVbi0Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13__T4evalVbi1Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13getThreadSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher15prepareFreeListMFNaNbNiNekKAvZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher16__T10bwdMatcherZ10bwdMatcherMFNaNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher16__T10fwdMatcherZ10fwdMatcherMFNaNbNiNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18__T9matchImplVbi0Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18__T9matchImplVbi1Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher4forkMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadkkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher4nextMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher55__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5InputZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5InputZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5atEndMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher67__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5InputZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6__initZ@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6finishMFNaNbNiNePxS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher6searchMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7recycleMFNaNbNiNeKS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadListZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher7recycleMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher8allocateMFNaNbNiNeZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher9__xtoHashFNbNeKxS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherZk@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11__xopEqualsFKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11createStartMFNaNbNiNekkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher12matchOneShotMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupkZE3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher11MatchResult@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13__T4evalVbi0Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13__T4evalVbi1Z4evalMFNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13getThreadSizeFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher13initialMemoryFNaNbNiNeKxS3std5regex8internal2ir12__T5RegexTaZ5RegexZk@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher15prepareFreeListMFNaNbNiNekKAvZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher16__T10bwdMatcherZ10bwdMatcherMFNaNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher16__T10fwdMatcherZ10fwdMatcherMFNaNbNiNeAS3std5regex8internal2ir8BytecodekZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher18__T9matchImplVbi0Z9matchImplMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher18initExternalMemoryMFNaNbNiNeAvZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher4forkMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadkkZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher4nextMFNaNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher55__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5InputZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson67__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5InputZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5atEndMFNaNdNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5dupToMFNaNbNiNeAvZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher5matchMFNeAS3std5regex8internal2ir12__T5GroupTkZ5GroupZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher67__T6__ctorTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ6__ctorMFNaNbNcNiNeKS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherAS3std5regex8internal2ir8BytecodeS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6__initZ@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher6finishMFNaNbNiNePxS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadAS3std5regex8internal2ir12__T5GroupTkZ5GroupZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7atStartMFNaNbNdNiNeZb@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7recycleMFNaNbNiNeKS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadListZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher7recycleMFNaNbNiNePS3std5regex8internal8thompson13__T6ThreadTkZ6ThreadZv@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher8allocateMFNaNbNiNeZPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread@Base 6
+ _D3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcher9__xtoHashFNbNeKxS3std5regex8internal8thompson79__T15ThompsonMatcherTaTS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooperZ15ThompsonMatcherZk@Base 6
+ _D3std5regex8internal9generator12__ModuleInfoZ@Base 6
+ _D3std5regex8internal9kickstart12__ModuleInfoZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread105__T3setS94_D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread10setInvMaskMFNaNbNiNfkkZvZ3setMFNaNfwZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread10setInvMaskMFNaNbNiNfkkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread11__xopEqualsFKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread3addMFNaNfwZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread4fullMFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__ctorMFNaNbNcNiNfkkAkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread7advanceMFNaNbNiNfkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread7setMaskMFNaNbNiNfkkZv@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread9__xtoHashFNbNeKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11__xopEqualsFKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr4forkFNaNbNiNfS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadkkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr5fetchFNbNeKAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__ctorMFNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexAkZ10codeBoundsyAi@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__ctorMFNcNeKS3std5regex8internal2ir12__T5RegexTaZ5RegexAkZS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6searchMFNaNeAxakZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr7charLenFNaNbNiNfkZk@Base 6
+ _D3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr9__xtoHashFNbNeKxS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOrZk@Base 6
+ _D3std5regex8internal9kickstart21__T13effectiveSizeTaZ13effectiveSizeFNaNbNiNfZk@Base 6
+ _D3std5stdio10ChunksImpl11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio10ChunksImpl11__xopEqualsFKxS3std5stdio10ChunksImplKxS3std5stdio10ChunksImplZb@Base 6
+ _D3std5stdio10ChunksImpl15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio10ChunksImpl6__ctorMFNcS3std5stdio4FilekZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio10ChunksImpl6__initZ@Base 6
+ _D3std5stdio10ChunksImpl8opAssignMFNcNjNeS3std5stdio10ChunksImplZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio10ChunksImpl9__xtoHashFNbNeKxS3std5stdio10ChunksImplZk@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZ1nk@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZ7lineptrPa@Base 6
+ _D3std5stdio10readlnImplFPOS4core4stdc5stdio8_IO_FILEKAawE3std5stdio4File11OrientationZk@Base 6
+ _D3std5stdio11openNetworkFAyatZS3std5stdio4File@Base 6
+ _D3std5stdio12__ModuleInfoZ@Base 6
+ _D3std5stdio13trustedStdoutFNdNeZS3std5stdio4File@Base 6
+ _D3std5stdio14StdioException6__ctorMFAyakZC3std5stdio14StdioException@Base 6
+ _D3std5stdio14StdioException6__initZ@Base 6
+ _D3std5stdio14StdioException6__vtblZ@Base 6
+ _D3std5stdio14StdioException6opCallFAyaZv@Base 6
+ _D3std5stdio14StdioException6opCallFZv@Base 6
+ _D3std5stdio14StdioException7__ClassZ@Base 6
+ _D3std5stdio17LockingTextReader10__aggrDtorMFZv@Base 6
+ _D3std5stdio17LockingTextReader10__postblitMFZv@Base 6
+ _D3std5stdio17LockingTextReader11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio17LockingTextReader11__xopEqualsFKxS3std5stdio17LockingTextReaderKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std5stdio17LockingTextReader14__aggrPostblitMFZv@Base 6
+ _D3std5stdio17LockingTextReader15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio17LockingTextReader5emptyMFNdZb@Base 6
+ _D3std5stdio17LockingTextReader5frontMFNdZw@Base 6
+ _D3std5stdio17LockingTextReader6__ctorMFNcS3std5stdio4FileZS3std5stdio17LockingTextReader@Base 6
+ _D3std5stdio17LockingTextReader6__dtorMFZv@Base 6
+ _D3std5stdio17LockingTextReader6__initZ@Base 6
+ _D3std5stdio17LockingTextReader8opAssignMFS3std5stdio17LockingTextReaderZv@Base 6
+ _D3std5stdio17LockingTextReader8popFrontMFZv@Base 6
+ _D3std5stdio17LockingTextReader9__xtoHashFNbNeKxS3std5stdio17LockingTextReaderZk@Base 6
+ _D3std5stdio17LockingTextReader9readFrontMFZv@Base 6
+ _D3std5stdio17LockingTextReader9takeFrontMFNkKG4aZAa@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ10stderrImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ10stdoutImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio21std_stdio_static_thisUZ9stdinImplS3std5stdio4File4Impl@Base 6
+ _D3std5stdio4File10__postblitMFNbNfZv@Base 6
+ _D3std5stdio4File11__xopEqualsFKxS3std5stdio4FileKxS3std5stdio4FileZb@Base 6
+ _D3std5stdio4File13__T6readlnTaZ6readlnMFKAawZk@Base 6
+ _D3std5stdio4File14__T7rawReadTaZ7rawReadMFAaZAa@Base 6
+ _D3std5stdio4File14__T7rawReadTbZ7rawReadMFAbZAb@Base 6
+ _D3std5stdio4File14__T7rawReadThZ7rawReadMFAhZAh@Base 6
+ _D3std5stdio4File14__T7rawReadTiZ7rawReadMFAiZAi@Base 6
+ _D3std5stdio4File14__T7rawReadTlZ7rawReadMFAlZAl@Base 6
+ _D3std5stdio4File15__T6readlnTAyaZ6readlnMFwZAya@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNbNiNfaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNfaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTaZ3putMFNfaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNbNiNfwZv@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNfwZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__T3putTwZ3putMFNfwZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter10__postblitMFNeZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTAaZ3putMFAaZ13trustedFwriteFNbNiNexPvkkPOS4core4stdc5stdio8_IO_FILEZk@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTAaZ3putMFNfAaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNbNiNfxaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNfxaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxaZ3putMFNfxaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNbNiNfxwZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNfxwZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTxwZ3putMFNfxwZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNbNiNfyaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNfyaZ12trustedFPUTCFNbNiNeiPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter11__T3putTyaZ3putMFNfyaZ13trustedFPUTWCFNbNiNewPS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAxaZ3putMFAxaZ13trustedFwriteFNbNiNexPvkkPOS4core4stdc5stdio8_IO_FILEZk@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAxaZ3putMFNfAxaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAyaZ3putMFAyaZ13trustedFwriteFNbNiNexPvkkPOS4core4stdc5stdio8_IO_FILEZk@Base 6
+ _D3std5stdio4File17LockingTextWriter12__T3putTAyaZ3putMFNfAyaZv@Base 6
+ _D3std5stdio4File17LockingTextWriter6__ctorMFNcNeKS3std5stdio4FileZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File17LockingTextWriter6__dtorMFNeZv@Base 6
+ _D3std5stdio4File17LockingTextWriter6__initZ@Base 6
+ _D3std5stdio4File17LockingTextWriter8opAssignMFNcNjNeS3std5stdio4File17LockingTextWriterZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File17lockingTextWriterMFNfZS3std5stdio4File17LockingTextWriter@Base 6
+ _D3std5stdio4File3eofMxFNaNdNeZb@Base 6
+ _D3std5stdio4File4Impl6__initZ@Base 6
+ _D3std5stdio4File4lockMFE3std5stdio8LockTypemmZv@Base 6
+ _D3std5stdio4File4nameMxFNaNbNdNfZAya@Base 6
+ _D3std5stdio4File4openMFNfAyaxAaZv@Base 6
+ _D3std5stdio4File4seekMFNeliZv@Base 6
+ _D3std5stdio4File4sizeMFNdNfZm@Base 6
+ _D3std5stdio4File4syncMFNeZv@Base 6
+ _D3std5stdio4File4tellMxFNdNeZm@Base 6
+ _D3std5stdio4File5closeMFNeZv@Base 6
+ _D3std5stdio4File5errorMxFNaNbNdNeZb@Base 6
+ _D3std5stdio4File5flushMFNeZv@Base 6
+ _D3std5stdio4File5getFPMFNaNfZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio4File5popenMFNfAyaxAaZv@Base 6
+ _D3std5stdio4File6__ctorMFNcNePOS4core4stdc5stdio8_IO_FILEAyakbZS3std5stdio4File@Base 6
+ _D3std5stdio4File6__ctorMFNcNfAyaxAaZS3std5stdio4File@Base 6
+ _D3std5stdio4File6__dtorMFNfZv@Base 6
+ _D3std5stdio4File6__initZ@Base 6
+ _D3std5stdio4File6detachMFNfZv@Base 6
+ _D3std5stdio4File6fdopenMFNeixAaAyaZv@Base 6
+ _D3std5stdio4File6fdopenMFNfixAaZv@Base 6
+ _D3std5stdio4File6filenoMxFNdNeZi@Base 6
+ _D3std5stdio4File6isOpenMxFNaNbNdNfZb@Base 6
+ _D3std5stdio4File6rewindMFNfZv@Base 6
+ _D3std5stdio4File6unlockMFmmZv@Base 6
+ _D3std5stdio4File7ByChunk11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio4File7ByChunk11__xopEqualsFKxS3std5stdio4File7ByChunkKxS3std5stdio4File7ByChunkZb@Base 6
+ _D3std5stdio4File7ByChunk15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio4File7ByChunk5emptyMxFNbNdZb@Base 6
+ _D3std5stdio4File7ByChunk5frontMFNbNdZAh@Base 6
+ _D3std5stdio4File7ByChunk5primeMFZv@Base 6
+ _D3std5stdio4File7ByChunk6__ctorMFNcS3std5stdio4FileAhZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk6__ctorMFNcS3std5stdio4FilekZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk6__initZ@Base 6
+ _D3std5stdio4File7ByChunk8opAssignMFNcNjNeS3std5stdio4File7ByChunkZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7ByChunk8popFrontMFZv@Base 6
+ _D3std5stdio4File7ByChunk9__xtoHashFNbNeKxS3std5stdio4File7ByChunkZk@Base 6
+ _D3std5stdio4File7byChunkMFAhZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7byChunkMFkZS3std5stdio4File7ByChunk@Base 6
+ _D3std5stdio4File7setvbufMFNeAviZv@Base 6
+ _D3std5stdio4File7setvbufMFNekiZv@Base 6
+ _D3std5stdio4File7tmpfileFNfZS3std5stdio4File@Base 6
+ _D3std5stdio4File7tryLockMFE3std5stdio8LockTypemmZb@Base 6
+ _D3std5stdio4File8clearerrMFNaNbNfZv@Base 6
+ _D3std5stdio4File8lockImplMFismmZi@Base 6
+ _D3std5stdio4File8opAssignMFNfS3std5stdio4FileZv@Base 6
+ _D3std5stdio4File8wrapFileFNfPOS4core4stdc5stdio8_IO_FILEZS3std5stdio4File@Base 6
+ _D3std5stdio4File9__xtoHashFNbNeKxS3std5stdio4FileZk@Base 6
+ _D3std5stdio5fopenFNbNiNexAaxAaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio5lines11__fieldDtorMFNeZv@Base 6
+ _D3std5stdio5lines11__xopEqualsFKxS3std5stdio5linesKxS3std5stdio5linesZb@Base 6
+ _D3std5stdio5lines15__fieldPostblitMFNbNeZv@Base 6
+ _D3std5stdio5lines6__ctorMFNcS3std5stdio4FilewZS3std5stdio5lines@Base 6
+ _D3std5stdio5lines6__initZ@Base 6
+ _D3std5stdio5lines8opAssignMFNcNjNeS3std5stdio5linesZS3std5stdio5lines@Base 6
+ _D3std5stdio5lines9__xtoHashFNbNeKxS3std5stdio5linesZk@Base 6
+ _D3std5stdio5popenFNbNiNexAaxAaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std5stdio5stdinS3std5stdio4File@Base 6
+ _D3std5stdio6chunksFS3std5stdio4FilekZS3std5stdio10ChunksImpl@Base 6
+ _D3std5stdio6stderrS3std5stdio4File@Base 6
+ _D3std5stdio6stdoutS3std5stdio4File@Base 6
+ _D3std6base6412__ModuleInfoZ@Base 6
+ _D3std6base6415Base64Exception6__ctorMFNaNbNfAyaAyakZC3std6base6415Base64Exception@Base 6
+ _D3std6base6415Base64Exception6__initZ@Base 6
+ _D3std6base6415Base64Exception6__vtblZ@Base 6
+ _D3std6base6415Base64Exception7__ClassZ@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z12decodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z12encodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z9DecodeMapyG256i@Base 6
+ _D3std6base6431__T10Base64ImplVai43Vai47Vai61Z9EncodeMapyAa@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z12decodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z12encodeLengthFNaNbNfxkZk@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z9DecodeMapyG256i@Base 6
+ _D3std6base6431__T10Base64ImplVai45Vai95Vai61Z9EncodeMapyAa@Base 6
+ _D3std6bigint12__ModuleInfoZ@Base 6
+ _D3std6bigint15toDecimalStringFxS3std6bigint6BigIntZAya@Base 6
+ _D3std6bigint5toHexFxS3std6bigint6BigIntZAya@Base 6
+ _D3std6bigint6BigInt10isNegativeMxFNaNbNiNfZb@Base 6
+ _D3std6bigint6BigInt10uintLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std6bigint6BigInt11__xopEqualsFKxS3std6bigint6BigIntKxS3std6bigint6BigIntZb@Base 6
+ _D3std6bigint6BigInt11ulongLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std6bigint6BigInt13__T8opEqualsZ8opEqualsMxFNaNbNiNfKxS3std6bigint6BigIntZb@Base 6
+ _D3std6bigint6BigInt14checkDivByZeroMxFNaNbNfZv@Base 6
+ _D3std6bigint6BigInt31__T5opCmpHTS3std6bigint6BigIntZ5opCmpMxFNaNbNiNfxS3std6bigint6BigIntZi@Base 6
+ _D3std6bigint6BigInt5opCmpMxFNaNbNiKxS3std6bigint6BigIntZi@Base 6
+ _D3std6bigint6BigInt5toIntMxFNaNbNiNfZi@Base 6
+ _D3std6bigint6BigInt6__initZ@Base 6
+ _D3std6bigint6BigInt6isZeroMxFNaNbNiNfZb@Base 6
+ _D3std6bigint6BigInt6negateMFNaNbNiNfZv@Base 6
+ _D3std6bigint6BigInt6toHashMxFNbNfZk@Base 6
+ _D3std6bigint6BigInt6toLongMxFNaNbNiNfZl@Base 6
+ _D3std6bigint6BigInt8toStringMxFMDFAxaZvAyaZv@Base 6
+ _D3std6bigint6BigInt8toStringMxFMDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6digest2md10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest2md12__ModuleInfoZ@Base 6
+ _D3std6digest2md3MD51FFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD51IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest2md3MD52FFFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52GGFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52HHFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD52IIFNaNbNiNfKkkkkkkkZv@Base 6
+ _D3std6digest2md3MD53putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest2md3MD55startMFNaNbNiNfZv@Base 6
+ _D3std6digest2md3MD56__initZ@Base 6
+ _D3std6digest2md3MD56finishMFNaNbNiNeZG16h@Base 6
+ _D3std6digest2md3MD58_paddingyG64h@Base 6
+ _D3std6digest2md3MD59transformMFNaNbNiPxG64hZv@Base 6
+ _D3std6digest3crc11crc32_tableyG256k@Base 6
+ _D3std6digest3crc12__ModuleInfoZ@Base 6
+ _D3std6digest3crc5CRC323putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3crc5CRC324peekMxFNaNbNiNfZG4h@Base 6
+ _D3std6digest3crc5CRC325startMFNaNbNiNfZv@Base 6
+ _D3std6digest3crc5CRC326__initZ@Base 6
+ _D3std6digest3crc5CRC326finishMFNaNbNiNfZG4h@Base 6
+ _D3std6digest3sha10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest3sha11rotateRightFNaNbNiNfkkZk@Base 6
+ _D3std6digest3sha11rotateRightFNaNbNiNfmkZm@Base 6
+ _D3std6digest3sha12__ModuleInfoZ@Base 6
+ _D3std6digest3sha17bigEndianToNativeFNaNbNiNeG4hZk@Base 6
+ _D3std6digest3sha17bigEndianToNativeFNaNbNiNeG8hZm@Base 6
+ _D3std6digest3sha17nativeToBigEndianFNaNbNiNekZG4h@Base 6
+ _D3std6digest3sha17nativeToBigEndianFNaNbNiNemZG8h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA6finishMFNaNbNiNeZG20h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii160Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6finishMFNaNbNiNeZG48h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6finishMFNaNbNiNeZG64h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9constantsyG80m@Base 6
+ _D3std6digest6digest12__ModuleInfoZ@Base 6
+ _D3std6digest6digest18__T7asArrayVki4ThZ7asArrayFNaNbNcNiKAhAyaZG4h@Base 6
+ _D3std6digest6digest19__T7asArrayVki16ThZ7asArrayFNaNbNcNiKAhAyaZG16h@Base 6
+ _D3std6digest6digest19__T7asArrayVki20ThZ7asArrayFNaNbNcNiKAhAyaZG20h@Base 6
+ _D3std6digest6digest19__T7asArrayVki28ThZ7asArrayFNaNbNcNiKAhAyaZG28h@Base 6
+ _D3std6digest6digest19__T7asArrayVki32ThZ7asArrayFNaNbNcNiKAhAyaZG32h@Base 6
+ _D3std6digest6digest19__T7asArrayVki48ThZ7asArrayFNaNbNcNiKAhAyaZG48h@Base 6
+ _D3std6digest6digest19__T7asArrayVki64ThZ7asArrayFNaNbNcNiKAhAyaZG64h@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest6Digest11__InterfaceZ@Base 6
+ _D3std6digest6digest6Digest6digestMFNbNeMAxAvXAh@Base 6
+ _D3std6digest6digest71__T11toHexStringVE3std6digest6digest5Orderi1VE3std5ascii10LetterCasei0Z11toHexStringFNaNbxAhZAya@Base 6
+ _D3std6digest6digest76__T11toHexStringVE3std6digest6digest5Orderi1Vki16VE3std5ascii10LetterCasei0Z11toHexStringFNaNbNiNfxG16hZG32a@Base 6
+ _D3std6digest6ripemd10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest6ripemd12__ModuleInfoZ@Base 6
+ _D3std6digest6ripemd9RIPEMD1601FFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601JFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1602FFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602GGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602HHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602IIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602JJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603FFFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603GGGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603HHHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603IIIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603JJJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest6ripemd9RIPEMD1605startMFNaNbNiNfZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1606__initZ@Base 6
+ _D3std6digest6ripemd9RIPEMD1606finishMFNaNbNiNeZG20h@Base 6
+ _D3std6digest6ripemd9RIPEMD1608_paddingyG64h@Base 6
+ _D3std6digest6ripemd9RIPEMD1609transformMFNaNbNiPxG64hZv@Base 6
+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckbAyaAyaE3std3net7isemail15EmailStatusCodeZv@Base 6
+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckbAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZk@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda13FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda15FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda17FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda14TkZ10__lambda14FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda16TkZ10__lambda16FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ18__T10__lambda18TkZ10__lambda18FNaNbNiNeKkZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ19__T10__lambda10TykZ10__lambda10FNaNbNiNeKykZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ19__T10__lambda12TykZ10__lambda12FNaNbNiNeKykZxPv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZk@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T9__lambda9TbZ9__lambda9FNaNbNiNeKbZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ20__T10__lambda11TAyaZ10__lambda11FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ20__T10__lambda13TAyaZ10__lambda13FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ51__T10__lambda15TE3std3net7isemail15EmailStatusCodeZ10__lambda15FNaNbNiNeKE3std3net7isemail15EmailStatusCodeZxPv@Base 6
+ _D3std6format107__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAabAyaAyaE3std3net7isemail15EmailStatusCodeZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format111__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std3net4curl20AsyncChunkInputRange8__mixin55StateKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format113__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format117__T6formatTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6formatFNaNfxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZAya@Base 6
+ _D3std6format118__T9getNthIntTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9getNthIntFNaNfkE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std6format12__ModuleInfoZ@Base 6
+ _D3std6format137__T22enforceValidFormatSpecTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoS3gcc8builtins9__va_listZ6skipCIFNaNbNiNfC8TypeInfoZC8TypeInfo@Base 6.2.1-1ubuntu2
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoS3gcc8builtins9__va_listZ9formatArgMFaZ6getManFNaNbNiNfC8TypeInfoZE3std6format6Mangle@Base 6.2.1-1ubuntu2
+ _D3std6format13__T8doFormatZ8doFormatFMDFwZvAC8TypeInfoS3gcc8builtins9__va_listZv@Base 6.2.1-1ubuntu2
+ _D3std6format14__T9getNthIntZ9getNthIntFNaNfkZi@Base 6
+ _D3std6format15FormatException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6format15FormatException@Base 6
+ _D3std6format15FormatException6__ctorMFNaNbNfZC3std6format15FormatException@Base 6
+ _D3std6format15FormatException6__initZ@Base 6
+ _D3std6format15FormatException6__vtblZ@Base 6
+ _D3std6format15FormatException7__ClassZ@Base 6
+ _D3std6format15__T6formatTaTiZ6formatFNaNfxAaiZAya@Base 6
+ _D3std6format15__T6formatTaTkZ6formatFNaNfxAakZAya@Base 6
+ _D3std6format15__T6formatTaTwZ6formatFNaNfxAawZAya@Base 6
+ _D3std6format160__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZv@Base 6
+ _D3std6format160__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format166__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZk@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ66__T9__lambda7TE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda7FNaNbNiNeKE3std3net4curl20AsyncChunkInputRange8__mixin55StateZxPv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ66__T9__lambda9TE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda9FNaNbNiNeKE3std3net4curl20AsyncChunkInputRange8__mixin55StateZxPv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format166__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std3net4curl20AsyncChunkInputRange8__mixin55StateTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std3net4curl20AsyncChunkInputRange8__mixin55StateE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format167__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format16__T6formatTaTxsZ6formatFNaNfxAaxsZAya@Base 6
+ _D3std6format16__T9getNthIntTaZ9getNthIntFNaNfkaZi@Base 6
+ _D3std6format16__T9getNthIntTiZ9getNthIntFNaNfkiZi@Base 6
+ _D3std6format16__T9getNthIntTkZ9getNthIntFNaNfkkZi@Base 6
+ _D3std6format16__T9getNthIntTtZ9getNthIntFNaNfktZi@Base 6
+ _D3std6format16__T9getNthIntTwZ9getNthIntFNaNfkwZi@Base 6
+ _D3std6format17__T6formatTaTAyaZ6formatFNaNfxAaAyaZAya@Base 6
+ _D3std6format17__T6formatTaTiTiZ6formatFNaNfxAaiiZAya@Base 6
+ _D3std6format17__T6formatTaTkTkZ6formatFNaNfxAakkZAya@Base 6
+ _D3std6format17__T9getNthIntTPvZ9getNthIntFNaNfkPvZi@Base 6
+ _D3std6format17__T9getNthIntTxhZ9getNthIntFNaNfkxhZi@Base 6
+ _D3std6format17__T9getNthIntTxkZ9getNthIntFNaNfkxkZi@Base 6
+ _D3std6format17__T9getNthIntTxsZ9getNthIntFNaNfkxsZi@Base 6
+ _D3std6format17primitiveTypeInfoFE3std6format6MangleZ3dicHE3std6format6MangleC8TypeInfo@Base 6
+ _D3std6format17primitiveTypeInfoFE3std6format6MangleZC8TypeInfo@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec11__xopEqualsFKxS3std6format18__T10FormatSpecTaZ10FormatSpecKxS3std6format18__T10FormatSpecTaZ10FormatSpecZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec12getCurFmtStrMxFNaNfZAya@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec16headUpToNextSpecMFNaZAxa@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec31__T17writeUpToNextSpecTDFAxaZvZ17writeUpToNextSpecMFDFAxaZvZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec37__T17writeUpToNextSpecTDFNaNbNfAxaZvZ17writeUpToNextSpecMFNaNfDFNaNbNfAxaZvZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec59__T17writeUpToNextSpecTS3std5stdio4File17LockingTextWriterZ17writeUpToNextSpecMFNfS3std5stdio4File17LockingTextWriterZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec63__T17writeUpToNextSpecTS3std5array17__T8AppenderTAyaZ8AppenderZ17writeUpToNextSpecMFNaNfS3std5array17__T8AppenderTAyaZ8AppenderZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec63__T17writeUpToNextSpecTS3std5array17__T8AppenderTyAaZ8AppenderZ17writeUpToNextSpecMFNaNfS3std5array17__T8AppenderTyAaZ8AppenderZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6__ctorMFNaNbNcNiNfxAaZS3std6format18__T10FormatSpecTaZ10FormatSpec@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6__initZ@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6fillUpMFNaNfZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flDashMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flDashMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flHashMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flHashMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flPlusMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flPlusMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flZeroMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec6flZeroMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec7flSpaceMFNaNbNdNiNfbZv@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec7flSpaceMxFNaNbNdNiNfZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec8toStringMFNaNfZAya@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec91__T17writeUpToNextSpecTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkZ17writeUpToNextSpecMFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkZb@Base 6
+ _D3std6format18__T10FormatSpecTaZ10FormatSpec9__xtoHashFNbNeKxS3std6format18__T10FormatSpecTaZ10FormatSpecZk@Base 6
+ _D3std6format18__T6formatTaTAyAaZ6formatFNaNfxAaAyAaZAya@Base 6
+ _D3std6format18__T9getNthIntTAxaZ9getNthIntFNaNfkAxaZi@Base 6
+ _D3std6format18__T9getNthIntTAyaZ9getNthIntFNaNfkAyaZi@Base 6
+ _D3std6format18__T9getNthIntThTiZ9getNthIntFNaNfkhiZi@Base 6
+ _D3std6format18__T9getNthIntTiTiZ9getNthIntFNaNfkiiZi@Base 6
+ _D3std6format18__T9getNthIntTkTkZ9getNthIntFNaNfkkkZi@Base 6
+ _D3std6format18__T9getNthIntTtTtZ9getNthIntFNaNfkttZi@Base 6
+ _D3std6format18__T9getNthIntTwTkZ9getNthIntFNaNfkwkZi@Base 6
+ _D3std6format19__T6formatTaTAaTPvZ6formatFNaNfxAaAaPvZAya@Base 6
+ _D3std6format19__T6formatTaTAyaTkZ6formatFNaNfxAaAyakZAya@Base 6
+ _D3std6format19__T6formatTaTxkTxkZ6formatFNaNfxAaxkxkZAya@Base 6
+ _D3std6format19__T9getNthIntTAyAaZ9getNthIntFNaNfkAyAaZi@Base 6
+ _D3std6format20__T9getNthIntTAaTPvZ9getNthIntFNaNfkAaPvZi@Base 6
+ _D3std6format20__T9getNthIntTAxhTaZ9getNthIntFNaNfkAxhaZi@Base 6
+ _D3std6format20__T9getNthIntTAyaTiZ9getNthIntFNaNfkAyaiZi@Base 6
+ _D3std6format20__T9getNthIntTAyaTkZ9getNthIntFNaNfkAyakZi@Base 6
+ _D3std6format20__T9getNthIntThThTiZ9getNthIntFNaNfkhhiZi@Base 6
+ _D3std6format20__T9getNthIntTkTAyaZ9getNthIntFNaNfkkAyaZi@Base 6
+ _D3std6format20__T9getNthIntTkTkTkZ9getNthIntFNaNfkkkkZi@Base 6
+ _D3std6format20__T9getNthIntTwTkTkZ9getNthIntFNaNfkwkkZi@Base 6
+ _D3std6format20__T9getNthIntTxhTxhZ9getNthIntFNaNfkxhxhZi@Base 6
+ _D3std6format20__T9getNthIntTxkTxkZ9getNthIntFNaNfkxkxkZi@Base 6
+ _D3std6format21__T6formatTaTAxaTAxaZ6formatFNaNfxAaAxaAxaZAya@Base 6
+ _D3std6format21__T6formatTaTAyaTAyaZ6formatFNaNfxAaAyaAyaZAya@Base 6
+ _D3std6format21__T6formatTaTAyaTkTkZ6formatFNaNfxAaAyakkZAya@Base 6
+ _D3std6format21__T9getNthIntTAyaTxhZ9getNthIntFNaNfkAyaxhZi@Base 6
+ _D3std6format22__T6formatTaTxhTxhTxhZ6formatFNaNfxAaxhxhxhZAya@Base 6
+ _D3std6format22__T9getNthIntTAxaTAxaZ9getNthIntFNaNfkAxaAxaZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTAyaZ9getNthIntFNaNfkAyaAyaZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTkTkZ9getNthIntFNaNfkAyakkZi@Base 6
+ _D3std6format22__T9getNthIntTAyaTtTtZ9getNthIntFNaNfkAyattZi@Base 6
+ _D3std6format22__T9getNthIntThThThTiZ9getNthIntFNaNfkhhhiZi@Base 6
+ _D3std6format23__T6formatTaTAyaTAyaTkZ6formatFNaNfxAaAyaAyakZAya@Base 6
+ _D3std6format23__T6formatTaTAyaTkTAyaZ6formatFNaNfxAaAyakAyaZAya@Base 6
+ _D3std6format23__T6formatTaTtTAyaTtTtZ6formatFNaNfxAatAyattZAya@Base 6
+ _D3std6format23__T6formatTaTxsTAyaTxhZ6formatFNaNfxAaxsAyaxhZAya@Base 6
+ _D3std6format23__T9getNthIntTxhTxhTxhZ9getNthIntFNaNfkxhxhxhZi@Base 6
+ _D3std6format23__T9getNthIntTxkTxkTxkZ9getNthIntFNaNfkxkxkxkZi@Base 6
+ _D3std6format23__T9getNthIntTykTkTkTkZ9getNthIntFNaNfkykkkkZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTAyaTiZ9getNthIntFNaNfkAyaAyaiZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTAyaTkZ9getNthIntFNaNfkAyaAyakZi@Base 6
+ _D3std6format24__T9getNthIntTAyaTkTAyaZ9getNthIntFNaNfkAyakAyaZi@Base 6
+ _D3std6format24__T9getNthIntThThThThTiZ9getNthIntFNaNfkhhhhiZi@Base 6
+ _D3std6format24__T9getNthIntTkTAyaTAyaZ9getNthIntFNaNfkkAyaAyaZi@Base 6
+ _D3std6format24__T9getNthIntTtTAyaTtTtZ9getNthIntFNaNfktAyattZi@Base 6
+ _D3std6format24__T9getNthIntTxsTAyaTxhZ9getNthIntFNaNfkxsAyaxhZi@Base 6
+ _D3std6format25__T6formatTaTAyaTAyaTAyaZ6formatFNaNfxAaAyaAyaAyaZAya@Base 6
+ _D3std6format25__T6formatTaTxhTxhTxhTxhZ6formatFNaNfxAaxhxhxhxhZAya@Base 6
+ _D3std6format25__T9getNthIntTkTxkTxkTxkZ9getNthIntFNaNfkkxkxkxkZi@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNbNfAxaZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfAxuZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfAxwZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink3putMFNaNfwZv@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink6__initZ@Base 6
+ _D3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFNaNfAaxAaykykkkkZAa@Base 6
+ _D3std6format26__T9getNthIntTAyaTAyaTAyaZ9getNthIntFNaNfkAyaAyaAyaZi@Base 6
+ _D3std6format26__T9getNthIntTxhTxhTxhTxhZ9getNthIntFNaNfkxhxhxhxhZi@Base 6
+ _D3std6format26__T9getNthIntTykTykTkTkTkZ9getNthIntFNaNfkykykkkkZi@Base 6
+ _D3std6format28__T9getNthIntTAyaTkTAyaTAyaZ9getNthIntFNaNfkAyakAyaAyaZi@Base 6
+ _D3std6format29__T11formatValueTDFAxaZvTkTaZ11formatValueFDFAxaZvkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format29__T11formatValueTDFAxaZvTkTaZ11formatValueFDFAxaZvkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxeTaZ11formatValueFDFAxaZvxeKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxeZ9__lambda4FNaNbNiNeKxeZAxa@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxeTaZ11formatValueFDFAxaZvxeKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxmTaZ11formatValueFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxmZ9__lambda4FNaNbNiNeKxmZAxa@Base 6
+ _D3std6format30__T11formatValueTDFAxaZvTxmTaZ11formatValueFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format30__T9getNthIntTkTAyaTkTAyaTAyaZ9getNthIntFNaNfkkAyakAyaAyaZi@Base 6
+ _D3std6format32__T14formatIntegralTDFAxaZvTmTaZ14formatIntegralFDFAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format32__T14formatUnsignedTDFAxaZvTmTaZ14formatUnsignedFDFAxaZvmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format34__T6formatTaTE3std8datetime5MonthZ6formatFNaNfxAaE3std8datetime5MonthZAya@Base 6
+ _D3std6format34__T9getNthIntTAyaTkTAyaTkTAyaTAyaZ9getNthIntFNaNfkAyakAyakAyaAyaZi@Base 6
+ _D3std6format35__T9getNthIntTE3std8datetime5MonthZ9getNthIntFNaNfkE3std8datetime5MonthZi@Base 6
+ _D3std6format36__T11formatValueTDFNaNbNfAxaZvTyhTaZ11formatValueFDFNaNbNfAxaZvyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TyhZ9__lambda4FNaNbNiNeKyhZAxa@Base 6
+ _D3std6format36__T11formatValueTDFNaNbNfAxaZvTyhTaZ11formatValueFNaNfDFNaNbNfAxaZvyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format36__T9getNthIntTkTAyaTkTAyaTkTAyaTAyaZ9getNthIntFNaNfkkAyakAyakAyaAyaZi@Base 6
+ _D3std6format37__T11formatRangeTDFNaNbNfAxaZvTAyhTaZ11formatRangeFNaNfKDFNaNbNfAxaZvKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format37__T11formatValueTDFNaNbNfAxaZvTAyhTaZ11formatValueFNaNfDFNaNbNfAxaZvAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format37__T9getNthIntTE3std8datetime5MonthTiZ9getNthIntFNaNfkE3std8datetime5MonthiZi@Base 6
+ _D3std6format38__T13formatElementTDFNaNbNfAxaZvTyhTaZ13formatElementFNaNfDFNaNbNfAxaZvKyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format38__T14formatIntegralTDFNaNbNfAxaZvTmTaZ14formatIntegralFNaNbNfDFNaNbNfAxaZvxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format38__T14formatUnsignedTDFNaNbNfAxaZvTmTaZ14formatUnsignedFNaNbNfDFNaNbNfAxaZvmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format38__T6formatTaTiTE3std8datetime5MonthTiZ6formatFNaNfxAaiE3std8datetime5MonthiZAya@Base 6
+ _D3std6format39__T13formatElementTDFNaNbNfAxaZvTAyhTaZ13formatElementFNaNfDFNaNbNfAxaZvKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format39__T9getNthIntTiTE3std8datetime5MonthTiZ9getNthIntFNaNfkiE3std8datetime5MonthiZi@Base 6
+ _D3std6format39__T9getNthIntTxE3std8datetime5MonthTxhZ9getNthIntFNaNfkxE3std8datetime5MonthxhZi@Base 6
+ _D3std6format41__T6formatTaTxsTxE3std8datetime5MonthTxhZ6formatFNaNfxAaxsxE3std8datetime5MonthxhZAya@Base 6
+ _D3std6format42__T9getNthIntTxsTxE3std8datetime5MonthTxhZ9getNthIntFNaNfkxsxE3std8datetime5MonthxhZi@Base 6
+ _D3std6format45__T9getNthIntTE3std8datetime5MonthThThThThTiZ9getNthIntFNaNfkE3std8datetime5MonthhhhhiZi@Base 6
+ _D3std6format46__T9getNthIntTPC3std11concurrency10MessageBoxZ9getNthIntFNaNfkPC3std11concurrency10MessageBoxZi@Base 6
+ _D3std6format47__T9getNthIntTsTE3std8datetime5MonthThThThThTiZ9getNthIntFNaNfksE3std8datetime5MonthhhhhiZi@Base 6
+ _D3std6format49__T9getNthIntTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format52__T10formatCharTS3std5stdio4File17LockingTextWriterZ10formatCharFNfS3std5stdio4File17LockingTextWriterxwxaZv@Base 6
+ _D3std6format53__T22enforceValidFormatSpecTS3std11concurrency3TidTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format53__T9getNthIntTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format54__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZv@Base 6
+ _D3std6format54__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T10formatCharTS3std5array17__T8AppenderTAyaZ8AppenderZ10formatCharFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxwxaZv@Base 6
+ _D3std6format56__T10formatCharTS3std5array17__T8AppenderTyAaZ8AppenderZ10formatCharFNaNfS3std5array17__T8AppenderTyAaZ8AppenderxwxaZv@Base 6
+ _D3std6format56__T11formatValueTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ11formatValueFDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format56__T9formatNthTDFAxaZvTaTPC3std11concurrency10MessageBoxZ9formatNthFDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpeckPC3std11concurrency10MessageBoxZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T9formatNthTDFAxaZvTaTPC3std11concurrency10MessageBoxZ9formatNthFDFAxaZvKS3std6format18__T10FormatSpecTaZ10FormatSpeckPC3std11concurrency10MessageBoxZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAxaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAxaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZv@Base 6
+ _D3std6format56__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterThTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterThTaZ11formatValueFS3std5stdio4File17LockingTextWriterhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTiTaZ11formatValueFNfS3std5stdio4File17LockingTextWriteriKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTiTaZ11formatValueFS3std5stdio4File17LockingTextWriteriKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTkTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTkTaZ11formatValueFS3std5stdio4File17LockingTextWriterkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTsTaZ11formatValueFNfS3std5stdio4File17LockingTextWritersKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTsTaZ11formatValueFS3std5stdio4File17LockingTextWritersKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TsZ9__lambda4FNaNbNiNeKsZAxa@Base 6
+ _D3std6format57__T11formatValueTS3std5stdio4File17LockingTextWriterTwTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T12formatObjectTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ12formatObjectFKDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format57__T9getNthIntTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkAyaAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format58__T11formatValueTS3std5stdio4File17LockingTextWriterTxaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T11formatValueTS3std5stdio4File17LockingTextWriterTyaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriteryaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T13formatElementTDFNaNbNfAxaZvTS3std11concurrency3TidTaZ13formatElementFDFNaNbNfAxaZvKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format58__T6formatTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ6formatFNaNfxAabAyaAyaE3std3net7isemail15EmailStatusCodeZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ9formatNthFNaNfS3std5array17__T8AppenderTyAaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZv@Base 6
+ _D3std6format58__T9formatNthTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ9formatNthFS3std5array17__T8AppenderTyAaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T11formatRangeTS3std5stdio4File17LockingTextWriterTAxaTaZ11formatRangeFNfKS3std5stdio4File17LockingTextWriterKAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatRangeTS3std5stdio4File17LockingTextWriterTAyaTaZ11formatRangeFNfKS3std5stdio4File17LockingTextWriterKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTDFAxaZvTPC3std11concurrency10MessageBoxTaZ11formatValueFDFAxaZvPC3std11concurrency10MessageBoxKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTS3std5stdio4File17LockingTextWriterTAxaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T11formatValueTS3std5stdio4File17LockingTextWriterTAyaTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatElementTS3std5stdio4File17LockingTextWriterTwTaZ13formatElementFNfS3std5stdio4File17LockingTextWriterwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterThTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTiTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTkTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T13formatGenericTS3std5stdio4File17LockingTextWriterTsTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsZv@Base 6
+ _D3std6format59__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format59__T9getNthIntTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9getNthIntFNaNfkbAyaAyaE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std6format60__T14formatIntegralTS3std5stdio4File17LockingTextWriterTlTaZ14formatIntegralFNfS3std5stdio4File17LockingTextWriterxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format60__T14formatIntegralTS3std5stdio4File17LockingTextWriterTmTaZ14formatIntegralFNfS3std5stdio4File17LockingTextWriterxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format60__T14formatUnsignedTS3std5stdio4File17LockingTextWriterTmTaZ14formatUnsignedFNfS3std5stdio4File17LockingTextWritermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAakZk@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format60__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiiZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiiZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkZv@Base 6
+ _D3std6format60__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTbTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderbKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderThTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderThTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppendertKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppendertKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TtZ9__lambda4FNaNbNiNeKtZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderThTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderThTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4ThZ9__lambda4FNaNbNiNeKhZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTiTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTiTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TiZ9__lambda4FNaNbNiNeKiZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ11formatValueFS3std5array17__T8AppenderTyAaZ8AppenderkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format61__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTwTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTDFAxaZvTPC3std11concurrency10MessageBoxTaZ13formatGenericFDFAxaZvPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTS3std5stdio4File17LockingTextWriterTAxaTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T13formatGenericTS3std5stdio4File17LockingTextWriterTAyaTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format61__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyAaZv@Base 6
+ _D3std6format61__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyAaZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPvTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxdTaZ11formatValueFNfS3std5array17__T8AppenderTAyaZ8AppenderxdKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxdTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxdKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxdZ9__lambda4FNaNbNiNeKxdZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxhZ9__lambda4FNaNbNiNeKxhZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxiTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxiKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxiTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxiKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxiZ9__lambda4FNaNbNiNeKxiZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxkZ9__lambda4FNaNbNiNeKxkZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxmTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxmTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxmZ9__lambda4FNaNbNiNeKxmZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxsKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderxsKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TxsZ9__lambda4FNaNbNiNeKxsZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TyhZ9__lambda4FNaNbNiNeKyhZAxa@Base 6
+ _D3std6format62__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZ46__T9__lambda6TPC3std11concurrency10MessageBoxZ9__lambda6FNaNbNiNeKPC3std11concurrency10MessageBoxZxPv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZ9__lambda5FNaNbNiNeZPFNaNbNfDFAxaZvPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTDFAxaZvTaTPC3std11concurrency10MessageBoxZ14formattedWriteFDFAxaZvxAaPC3std11concurrency10MessageBoxZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAxaZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAxaZ18__T9__lambda6TAxaZ9__lambda6FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAxaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAxaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAyaZk@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaZ18__T9__lambda6TAyaZ9__lambda6FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format62__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAaPvZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAaPvZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxhaZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxhaZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkkkZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckwkkZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkxkZv@Base 6
+ _D3std6format62__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxkxkZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format62__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaiZv@Base 6
+ _D3std6format62__T9formatNthTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaiZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyhTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatRangeTS3std5array17__T8AppenderTyAaZ8AppenderTAyaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTyAaZ8AppenderKAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAxaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPxhTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTAyaTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatElementTS3std5array17__T8AppenderTyAaZ8AppenderTwTaZ13formatElementFNaNfS3std5array17__T8AppenderTyAaZ8AppenderwKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTbTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTiTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTkTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTtTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTwTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format63__T13formatGenericTS3std5array17__T8AppenderTyAaZ8AppenderTkTaZ13formatGenericFNaS3std5array17__T8AppenderTyAaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T11formatRangeTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ11formatRangeFNaNfKS3std5array17__T8AppenderTAyaZ8AppenderKAyAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyAaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKxhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTyhTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKyhKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTPvTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxhTaZ13formatGenericFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxkTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxsTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTAyaZ8AppenderTlTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTyAaZ8AppenderTlTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderxlKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatIntegralTS3std5array17__T8AppenderTyAaZ8AppenderTmTaZ14formatIntegralFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format64__T14formatUnsignedTS3std5array17__T8AppenderTAyaZ8AppenderTmTaZ14formatUnsignedFNaNbNfS3std5array17__T8AppenderTAyaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format64__T14formatUnsignedTS3std5array17__T8AppenderTyAaZ8AppenderTmTaZ14formatUnsignedFNaNbNfS3std5array17__T8AppenderTyAaZ8AppendermKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiZ16__T9__lambda6TiZ9__lambda6FNaNbNiNeKiZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawZ16__T9__lambda6TwZ9__lambda6FNaNbNiNeKwZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTyAaZ8AppenderxAakZk@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTyAaZ8AppenderxAakZ16__T9__lambda6TkZ9__lambda6FNaNbNiNeKkZxPv@Base 6
+ _D3std6format64__T14formattedWriteTS3std5array17__T8AppenderTyAaZ8AppenderTaTkZ14formattedWriteFS3std5array17__T8AppenderTyAaZ8AppenderxAakZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTyAaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaAxaZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAxaAxaZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaZ16__T7gencodeVki2Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakkZv@Base 6
+ _D3std6format64__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakkZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format65__T13formatElementTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ13formatElementFNaNfS3std5array17__T8AppenderTAyaZ8AppenderAyaKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAxaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAxhTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAyaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZk@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZ17__T9__lambda6TxkZ9__lambda6FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZk@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZ17__T9__lambda6TxsZ9__lambda6FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format65__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T22enforceValidFormatSpecTC3std11concurrency14LinkTerminatedTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format65__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhZv@Base 6
+ _D3std6format65__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTAyAaTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZ18__T9__lambda6TAyaZ9__lambda6FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ16__T9__lambda7TiZ9__lambda7FNaNbNiNeKiZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ16__T9__lambda9TiZ9__lambda9FNaNbNiNeKiZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiiZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakkZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ16__T9__lambda7TkZ9__lambda7FNaNbNiNeKkZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawkZk@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ16__T9__lambda7TwZ9__lambda7FNaNbNiNeKwZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T22enforceValidFormatSpecTC3std11concurrency15OwnerTerminatedTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyakZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyakZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakAyaZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyakAyaZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecktAyattZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecktAyattZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsAyaxhZv@Base 6
+ _D3std6format66__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsAyaxhZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format66__T9getNthIntTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ9getNthIntFNaNfkE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZk@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZ19__T9__lambda6TAyAaZ9__lambda6FNaNbNiNeKAyAaZxPv@Base 6
+ _D3std6format67__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyAaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyAaZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format67__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkxkxkxkZv@Base 6
+ _D3std6format67__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckkxkxkxkZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ17__T9__lambda7TAaZ9__lambda7FNaNbNiNeKAaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ17__T9__lambda9TPvZ9__lambda9FNaNbNiNeKPvZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAaTPvZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAaPvZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ16__T9__lambda9TaZ9__lambda9FNaNbNiNeKaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ18__T9__lambda7TAxhZ9__lambda7FNaNbNiNeKAxhZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxhTaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxhaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ18__T9__lambda7TAyaZ9__lambda7FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ16__T9__lambda8TkZ9__lambda8FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ16__T9__lambda8TwZ9__lambda8FNaNbNiNeKwZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTwTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAawkkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ17__T9__lambda7TxkZ9__lambda7FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ17__T9__lambda9TxkZ9__lambda9FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxkxkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAaAyaAyaiZk@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ18__T10__lambda12TiZ10__lambda12FNaNbNiNeKiZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTAyaTAyaTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAaAyaAyaiZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaAyaZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckAyaAyaAyaZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhxhZv@Base 6
+ _D3std6format68__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxhxhxhxhZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format6Mangle6__initZ@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ18__T9__lambda7TAxaZ9__lambda7FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ18__T9__lambda9TAxaZ9__lambda9FNaNbNiNeKAxaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAxaTAxaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAxaAxaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ18__T9__lambda7TAyaZ9__lambda7FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ18__T9__lambda9TAyaZ9__lambda9FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ9__lambda6FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZk@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format70__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakkZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZk@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ17__T9__lambda8TxhZ9__lambda8FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ19__T10__lambda10TxhZ10__lambda10FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format71__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyakZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ18__T10__lambda10TkZ10__lambda10FNaNbNiNeKkZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ20__T10__lambda12TAyaZ10__lambda12FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTkTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyakAyaZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ16__T9__lambda9TtZ9__lambda9FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ18__T10__lambda13TtZ10__lambda13FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ18__T10__lambda15TtZ10__lambda15FNaNbNiNeKtZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ20__T10__lambda11TAyaZ10__lambda11FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTtTAyaTtTtZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAatAyattZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZk@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ17__T9__lambda8TxsZ9__lambda8FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format72__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTAyaTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsAyaxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZk@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ16__T9__lambda9TkZ9__lambda9FNaNbNiNeKkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda11TxkZ10__lambda11FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda13TxkZ10__lambda13FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ19__T10__lambda15TxkZ10__lambda15FNaNbNiNeKxkZxPv@Base 6
+ _D3std6format73__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTkTxkTxkTxkZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAakxkxkxkZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZk@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ18__T9__lambda8TAyaZ9__lambda8FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ20__T10__lambda10TAyaZ10__lambda10FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ20__T10__lambda12TAyaZ10__lambda12FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTAyaTAyaTAyaZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaAyaAyaAyaZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZk@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda10FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda12FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ10__lambda14FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ17__T9__lambda9TxhZ9__lambda9FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda11TxhZ10__lambda11FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda13TxhZ10__lambda13FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ19__T10__lambda15TxhZ10__lambda15FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format74__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxhTxhTxhTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxhxhxhxhZ9__lambda8FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format74__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkAyakAyakAyaAyaZv@Base 6
+ _D3std6format74__T9formatNthTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpeckkAyakAyakAyaAyaZ16__T7gencodeVki7Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format76__T11formatValueTS3std5stdio4File17LockingTextWriterTE3std8datetime5MonthTaZ11formatValueFNfS3std5stdio4File17LockingTextWriterE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format77__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std8datetime5MonthZv@Base 6
+ _D3std6format77__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckE3std8datetime5MonthZ16__T7gencodeVki1Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format78__T13formatGenericTS3std5stdio4File17LockingTextWriterTE3std8datetime5MonthTaZ13formatGenericFS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std8datetime5MonthTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZk@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda13FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda15FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda17FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda19FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda21FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ10__lambda23FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ18__T10__lambda12TkZ10__lambda12FNaNbNiNeKkZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ18__T10__lambda16TkZ10__lambda16FNaNbNiNeKkZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ18__T10__lambda20TkZ10__lambda20FNaNbNiNeKkZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda14TAyaZ10__lambda14FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda18TAyaZ10__lambda18FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda22TAyaZ10__lambda22FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format80__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTkTAyaTkTAyaTkTAyaTAyaZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAakAyakAyakAyaAyaZ20__T10__lambda24TAyaZ10__lambda24FNaNbNiNeKAyaZxPv@Base 6
+ _D3std6format81__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTxE3std8datetime5MonthTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxE3std8datetime5MonthKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format81__T22enforceValidFormatSpecTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ22enforceValidFormatSpecFNaNfKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format81__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiE3std8datetime5MonthiZv@Base 6
+ _D3std6format81__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckiE3std8datetime5MonthiZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format82__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTS3std11concurrency3TidTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format82__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std8datetime5MonthTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTS3std11concurrency3TidTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKS3std11concurrency3TidKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTxE3std8datetime5MonthTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZk@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZ35__T9__lambda6TE3std8datetime5MonthZ9__lambda6FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format83__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTE3std8datetime5MonthZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaE3std8datetime5MonthZ9__lambda5FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format84__T11formatValueTDFNaNbNfAxaZvTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ11formatValueFNaNfDFNaNbNfAxaZvKS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format84__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ9formatNthFNaNfS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsxE3std8datetime5MonthxhZv@Base 6
+ _D3std6format84__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckxsxE3std8datetime5MonthxhZ16__T7gencodeVki3Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format85__T9formatNthTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ9formatNthFNfS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecksE3std8datetime5MonthhhhhiZv@Base 6
+ _D3std6format85__T9formatNthTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ9formatNthFS3std5stdio4File17LockingTextWriterKS3std6format18__T10FormatSpecTaZ10FormatSpecksE3std8datetime5MonthhhhhiZ16__T7gencodeVki7Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format86__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTE3std5regex8internal2ir2IRTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderE3std5regex8internal2ir2IRKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format86__T11formatValueTS3std5array17__T8AppenderTyAaZ8AppenderTE3std6socket12SocketOptionTaZ11formatValueFNaNfS3std5array17__T8AppenderTyAaZ8AppenderE3std6socket12SocketOptionKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format86__T13formatElementTDFNaNbNfAxaZvTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageTaZ13formatElementFNaNfDFNaNbNfAxaZvKS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZk@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ16__T9__lambda8TiZ9__lambda8FNaNbNiNeKiZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ18__T10__lambda12TiZ10__lambda12FNaNbNiNeKiZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ37__T10__lambda10TE3std8datetime5MonthZ10__lambda10FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format87__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTiTE3std8datetime5MonthTiZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaiE3std8datetime5MonthiZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format89__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ11formatValueFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkkKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format89__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ11formatValueFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkkKS3std6format18__T10FormatSpecTaZ10FormatSpecZ16__T9__lambda4TkZ9__lambda4FNaNbNiNeKkZAxa@Base 6
+ _D3std6format90__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ11formatValueFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkykKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T11formatValueTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ11formatValueFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkykKS3std6format18__T10FormatSpecTaZ10FormatSpecZ17__T9__lambda4TykZ9__lambda4FNaNbNiNeKykZAxa@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFNaNfS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZk@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ17__T9__lambda8TxsZ9__lambda8FNaNbNiNeKxsZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ19__T10__lambda12TxhZ10__lambda12FNaNbNiNeKxhZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ38__T10__lambda10TxE3std8datetime5MonthZ10__lambda10FNaNbNiNeKxE3std8datetime5MonthZxPv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ9__lambda7FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format90__T14formattedWriteTS3std5array17__T8AppenderTAyaZ8AppenderTaTxsTxE3std8datetime5MonthTxhZ14formattedWriteFS3std5array17__T8AppenderTAyaZ8AppenderxAaxsxE3std8datetime5MonthxhZ9__lambda9FNaNbNiNeZPFNaNbNfS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T13formatGenericTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTkTaZ13formatGenericFNaS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFNfS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZk@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda11FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda13FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda15FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda17FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda19FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda21FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ10__lambda23FNaNbNiNeZPFNaNbNfS3std5stdio4File17LockingTextWriterPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda12TsZ10__lambda12FNaNbNiNeKsZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda16ThZ10__lambda16FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda18ThZ10__lambda18FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda20ThZ10__lambda20FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda22ThZ10__lambda22FNaNbNiNeKhZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ18__T10__lambda24TiZ10__lambda24FNaNbNiNeKiZxPv@Base 6
+ _D3std6format91__T14formattedWriteTS3std5stdio4File17LockingTextWriterTaTsTE3std8datetime5MonthThThThThTiZ14formattedWriteFS3std5stdio4File17LockingTextWriterxAasE3std8datetime5MonthhhhhiZ37__T10__lambda14TE3std8datetime5MonthZ10__lambda14FNaNbNiNeKE3std8datetime5MonthZxPv@Base 6
+ _D3std6format92__T13formatGenericTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTykTaZ13formatGenericFNaS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format92__T14formatIntegralTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTmTaZ14formatIntegralFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxmKS3std6format18__T10FormatSpecTaZ10FormatSpeckmZv@Base 6
+ _D3std6format92__T14formatUnsignedTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTmTaZ14formatUnsignedFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkmKS3std6format18__T10FormatSpecTaZ10FormatSpeckbZv@Base 6
+ _D3std6format93__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTPS3std11parallelism12AbstractTaskTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderPS3std11parallelism12AbstractTaskKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format94__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency14LinkTerminatedTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderC3std11concurrency14LinkTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format94__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net7isemail15EmailStatusCodeTaZ11formatValueFNaNfS3std5array17__T8AppenderTAyaZ8AppenderE3std3net7isemail15EmailStatusCodeKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format95__T11formatValueTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency15OwnerTerminatedTaZ11formatValueFS3std5array17__T8AppenderTAyaZ8AppenderC3std11concurrency15OwnerTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format95__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency14LinkTerminatedTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKC3std11concurrency14LinkTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T12formatObjectTS3std5array17__T8AppenderTAyaZ8AppenderTC3std11concurrency15OwnerTerminatedTaZ12formatObjectFKS3std5array17__T8AppenderTAyaZ8AppenderKC3std11concurrency15OwnerTerminatedKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T13formatGenericTS3std5array17__T8AppenderTAyaZ8AppenderTE3std3net7isemail15EmailStatusCodeTaZ13formatGenericFNaS3std5array17__T8AppenderTAyaZ8AppenderPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format96__T9formatNthTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ9formatNthFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKS3std6format18__T10FormatSpecTaZ10FormatSpeckykykkkkZv@Base 6
+ _D3std6format96__T9formatNthTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ9formatNthFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkKS3std6format18__T10FormatSpecTaZ10FormatSpeckykykkkkZ16__T7gencodeVki5Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6getopt10assignCharw@Base 6
+ _D3std6getopt10optionCharw@Base 6
+ _D3std6getopt11splitAndGetFNaNbNeAyaZS3std6getopt6Option@Base 6
+ _D3std6getopt12GetoptResult11__xopEqualsFKxS3std6getopt12GetoptResultKxS3std6getopt12GetoptResultZb@Base 6
+ _D3std6getopt12GetoptResult6__initZ@Base 6
+ _D3std6getopt12GetoptResult9__xtoHashFNbNeKxS3std6getopt12GetoptResultZk@Base 6
+ _D3std6getopt12__ModuleInfoZ@Base 6
+ _D3std6getopt12endOfOptionsAya@Base 6
+ _D3std6getopt13configuration11passThroughMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration11passThroughMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration13caseSensitiveMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration13caseSensitiveMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration16keepEndOfOptionsMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration16keepEndOfOptionsMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration20stopOnFirstNonOptionMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration20stopOnFirstNonOptionMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration6__initZ@Base 6
+ _D3std6getopt13configuration8bundlingMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration8bundlingMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt13configuration8requiredMFNaNbNdNiNfbZv@Base 6
+ _D3std6getopt13configuration8requiredMxFNaNbNdNiNfZb@Base 6
+ _D3std6getopt15GetOptException6__ctorMFNaNbNfAyaAyakZC3std6getopt15GetOptException@Base 6
+ _D3std6getopt15GetOptException6__initZ@Base 6
+ _D3std6getopt15GetOptException6__vtblZ@Base 6
+ _D3std6getopt15GetOptException7__ClassZ@Base 6
+ _D3std6getopt20defaultGetoptPrinterFAyaAS3std6getopt6OptionZv@Base 6
+ _D3std6getopt64__T22defaultGetoptFormatterTS3std5stdio4File17LockingTextWriterZ22defaultGetoptFormatterFNfS3std5stdio4File17LockingTextWriterAyaAS3std6getopt6OptionZv@Base 6
+ _D3std6getopt6Option11__xopEqualsFKxS3std6getopt6OptionKxS3std6getopt6OptionZb@Base 6
+ _D3std6getopt6Option6__initZ@Base 6
+ _D3std6getopt6Option9__xtoHashFNbNeKxS3std6getopt6OptionZk@Base 6
+ _D3std6getopt8arraySepAya@Base 6
+ _D3std6getopt8optMatchFAyaAyaKAyaS3std6getopt13configurationZb@Base 6
+ _D3std6getopt9setConfigFKS3std6getopt13configurationE3std6getopt6configZv@Base 6
+ _D3std6mmfile12__ModuleInfoZ@Base 6
+ _D3std6mmfile6MmFile12ensureMappedMFmZv@Base 6
+ _D3std6mmfile6MmFile12ensureMappedMFmmZv@Base 6
+ _D3std6mmfile6MmFile13opIndexAssignMFhmZh@Base 6
+ _D3std6mmfile6MmFile3mapMFmkZv@Base 6
+ _D3std6mmfile6MmFile4modeMFZE3std6mmfile6MmFile4Mode@Base 6
+ _D3std6mmfile6MmFile5flushMFZv@Base 6
+ _D3std6mmfile6MmFile5unmapMFZv@Base 6
+ _D3std6mmfile6MmFile6__ctorMFAyaE3std6mmfile6MmFile4ModemPvkZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFAyaZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFS3std5stdio4FileE3std6mmfile6MmFile4ModemPvkZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__ctorMFiE3std6mmfile6MmFile4ModemPvkZC3std6mmfile6MmFile@Base 6
+ _D3std6mmfile6MmFile6__dtorMFZv@Base 6
+ _D3std6mmfile6MmFile6__initZ@Base 6
+ _D3std6mmfile6MmFile6__vtblZ@Base 6
+ _D3std6mmfile6MmFile6lengthMxFNdZm@Base 6
+ _D3std6mmfile6MmFile6mappedMFmZi@Base 6
+ _D3std6mmfile6MmFile7__ClassZ@Base 6
+ _D3std6mmfile6MmFile7opIndexMFmZh@Base 6
+ _D3std6mmfile6MmFile7opSliceMFZAv@Base 6
+ _D3std6mmfile6MmFile7opSliceMFmmZAv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine134__T4seedTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4seedMFNfS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine4saveMFNaNbNdNiNfZS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine5frontMFNaNbNdNfZk@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine6__ctorMFNaNbNcNfkZS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine6__initZ@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine8popFrontMFNaNbNfZ5mag01yG2k@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine8popFrontMFNaNbNfZv@Base 6
+ _D3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine9__T4seedZ4seedMFNaNbNfkZv@Base 6
+ _D3std6random12__ModuleInfoZ@Base 6
+ _D3std6random17unpredictableSeedFNdNeZ4randS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random17unpredictableSeedFNdNeZ6seededb@Base 6
+ _D3std6random17unpredictableSeedFNdNeZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG5kZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngineZb@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG6kZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngineZb@Base 6
+ _D3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG3kZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngineZb@Base 6
+ _D3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG4kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG1kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine13sanitizeSeedsFNaNbNiNfKG2kZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine4saveMFNaNbNdNiNfZS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine4seedMFNaNbNiNfkZv@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__ctorMFNaNbNcNiNfkZS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__initZ@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine8opEqualsMxFNaNbNiNfKxS3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngineZb@Base 6
+ _D3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine16primeFactorsOnlyFNaNbNiNfmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine34properLinearCongruentialParametersFNaNbNiNfmmmZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine3gcdFNaNbNiNfmmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine4saveMFNaNbNdNiNfZS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine4seedMFNaNfkZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__ctorMFNaNcNfkZS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine8opEqualsMxFNaNbNiNfKxS3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngineZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki16807Vki0Vki2147483647Z24LinearCongruentialEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine16primeFactorsOnlyFNaNbNiNfmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine34properLinearCongruentialParametersFNaNbNiNfmmmZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine3gcdFNaNbNiNfmmZm@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine4saveMFNaNbNdNiNfZS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine4seedMFNaNfkZv@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__ctorMFNaNcNfkZS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine6__initZ@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine8opEqualsMxFNaNbNiNfKxS3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngineZb@Base 6
+ _D3std6random57__T24LinearCongruentialEngineTkVki48271Vki0Vki2147483647Z24LinearCongruentialEngine8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6random6rndGenFNcNdNfZ11initializedb@Base 6
+ _D3std6random6rndGenFNcNdNfZ16__T9__lambda3TiZ9__lambda3FNfiZk@Base 6
+ _D3std6random6rndGenFNcNdNfZ16__T9__lambda4TiZ9__lambda4FNfiZk@Base 6
+ _D3std6random6rndGenFNcNdNfZ6resultS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6random6rndGenFNcNdNfZS3std6random109__T21MersenneTwisterEngineTkVki32Vki624Vki397Vki31Vki2567483615Vki11Vki7Vki2636928640Vki15Vki4022730752Vki18Z21MersenneTwisterEngine@Base 6
+ _D3std6socket10SocketType6__initZ@Base 6
+ _D3std6socket10getAddressFNfxAatZAC3std6socket7Address@Base 6
+ _D3std6socket10getAddressFNfxAaxAaZAC3std6socket7Address@Base 6
+ _D3std6socket10socketPairFNeZG2C3std6socket6Socket@Base 6
+ _D3std6socket11AddressInfo11__xopEqualsFKxS3std6socket11AddressInfoKxS3std6socket11AddressInfoZb@Base 6
+ _D3std6socket11AddressInfo6__initZ@Base 6
+ _D3std6socket11AddressInfo9__xtoHashFNbNeKxS3std6socket11AddressInfoZk@Base 6
+ _D3std6socket11UnixAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket11UnixAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket11UnixAddress4pathMxFNaNdNeZAya@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNbNiNfS4core3sys5posix3sys2un11sockaddr_unZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNbNiNfZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__ctorMFNaNexAaZC3std6socket11UnixAddress@Base 6
+ _D3std6socket11UnixAddress6__initZ@Base 6
+ _D3std6socket11UnixAddress6__vtblZ@Base 6
+ _D3std6socket11UnixAddress7__ClassZ@Base 6
+ _D3std6socket11UnixAddress7nameLenMxFNaNbNdNiNeZk@Base 6
+ _D3std6socket11UnixAddress8toStringMxFNaNfZAya@Base 6
+ _D3std6socket12InternetHost12validHostentMFNfxPS4core3sys5posix5netdb7hostentZv@Base 6
+ _D3std6socket12InternetHost13getHostByAddrMFNekZb@Base 6
+ _D3std6socket12InternetHost13getHostByAddrMFNexAaZb@Base 6
+ _D3std6socket12InternetHost13getHostByNameMFNexAaZb@Base 6
+ _D3std6socket12InternetHost174__T7getHostVAyaa75_0a202020202020202020202020202020206175746f206865203d20676574686f737462796e616d6528706172616d2e74656d7043537472696e672829293b0a202020202020202020202020TAxaZ7getHostMFAxaZb@Base 6
+ _D3std6socket12InternetHost181__T13getHostNoSyncVAyaa75_0a202020202020202020202020202020206175746f206865203d20676574686f737462796e616d6528706172616d2e74656d7043537472696e672829293b0a202020202020202020202020TAxaZ13getHostNoSyncMFAxaZb@Base 6
+ _D3std6socket12InternetHost257__T7getHostVAyaa117_0a2020202020202020202020206175746f2078203d2068746f6e6c28706172616d293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TkZ7getHostMFkZb@Base 6
+ _D3std6socket12InternetHost264__T13getHostNoSyncVAyaa117_0a2020202020202020202020206175746f2078203d2068746f6e6c28706172616d293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TkZ13getHostNoSyncMFkZb@Base 6
+ _D3std6socket12InternetHost513__T7getHostVAyaa244_0a2020202020202020202020206175746f2078203d20696e65745f6164647228706172616d2e74656d7043537472696e672829293b0a202020202020202020202020656e666f726365287820213d20494e414444525f4e4f4e452c0a202020202020202020202020202020206e657720536f636b6574506172616d65746572457863657074696f6e2822496e76616c6964204950763420616464726573732229293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TAxaZ7getHostMFAxaZb@Base 6
+ _D3std6socket12InternetHost520__T13getHostNoSyncVAyaa244_0a2020202020202020202020206175746f2078203d20696e65745f6164647228706172616d2e74656d7043537472696e672829293b0a202020202020202020202020656e666f726365287820213d20494e414444525f4e4f4e452c0a202020202020202020202020202020206e657720536f636b6574506172616d65746572457863657074696f6e2822496e76616c6964204950763420616464726573732229293b0a2020202020202020202020206175746f206865203d20676574686f73746279616464722826782c20342c206361737428696e74294164647265737346616d696c792e494e4554293b0a2020202020202020TAxaZ13getHostNoSyncMFAxaZb@Base 6
+ _D3std6socket12InternetHost6__initZ@Base 6
+ _D3std6socket12InternetHost6__vtblZ@Base 6
+ _D3std6socket12InternetHost7__ClassZ@Base 6
+ _D3std6socket12InternetHost8populateMFNaNbPS4core3sys5posix5netdb7hostentZv@Base 6
+ _D3std6socket12SocketOption6__initZ@Base 6
+ _D3std6socket12__ModuleInfoZ@Base 6
+ _D3std6socket12parseAddressFNfxAatZC3std6socket7Address@Base 6
+ _D3std6socket12parseAddressFNfxAaxAaZC3std6socket7Address@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaAyakC6object9ThrowableiZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaC6object9ThrowableAyakiZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__ctorMFNfAyaiAyakC6object9ThrowableZC3std6socket13HostException@Base 6
+ _D3std6socket13HostException6__initZ@Base 6
+ _D3std6socket13HostException6__vtblZ@Base 6
+ _D3std6socket13HostException7__ClassZ@Base 6
+ _D3std6socket13_SOCKET_ERRORxi@Base 6
+ _D3std6socket13serviceToPortFNfxAaZt@Base 6
+ _D3std6socket14UnknownAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket14UnknownAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket14UnknownAddress6__initZ@Base 6
+ _D3std6socket14UnknownAddress6__vtblZ@Base 6
+ _D3std6socket14UnknownAddress7__ClassZ@Base 6
+ _D3std6socket14UnknownAddress7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket14formatGaiErrorFNeiZ13__critsec1889G28g@Base 6
+ _D3std6socket14formatGaiErrorFNeiZAya@Base 6
+ _D3std6socket15InternetAddress12addrToStringFNbNekZAya@Base 6
+ _D3std6socket15InternetAddress12toAddrStringMxFNeZAya@Base 6
+ _D3std6socket15InternetAddress12toPortStringMxFNfZAya@Base 6
+ _D3std6socket15InternetAddress16toHostNameStringMxFNfZAya@Base 6
+ _D3std6socket15InternetAddress4addrMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket15InternetAddress4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket15InternetAddress4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket15InternetAddress4portMxFNaNbNdNiNfZt@Base 6
+ _D3std6socket15InternetAddress5parseFNbNexAaZk@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfS4core3sys5posix7netinet3in_11sockaddr_inZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNfktZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNaNbNiNftZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__ctorMFNfxAatZC3std6socket15InternetAddress@Base 6
+ _D3std6socket15InternetAddress6__initZ@Base 6
+ _D3std6socket15InternetAddress6__vtblZ@Base 6
+ _D3std6socket15InternetAddress7__ClassZ@Base 6
+ _D3std6socket15InternetAddress7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket15InternetAddress8opEqualsMxFNfC6ObjectZb@Base 6
+ _D3std6socket15SocketException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6socket15SocketException@Base 6
+ _D3std6socket15SocketException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC3std6socket15SocketException@Base 6
+ _D3std6socket15SocketException6__initZ@Base 6
+ _D3std6socket15SocketException6__vtblZ@Base 6
+ _D3std6socket15SocketException7__ClassZ@Base 6
+ _D3std6socket15lastSocketErrorFNdNfZAya@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaAyakC6object9ThrowableiZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaC6object9ThrowableAyakiZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__ctorMFNfAyaiAyakC6object9ThrowableZC3std6socket16AddressException@Base 6
+ _D3std6socket16AddressException6__initZ@Base 6
+ _D3std6socket16AddressException6__vtblZ@Base 6
+ _D3std6socket16AddressException7__ClassZ@Base 6
+ _D3std6socket16AddressInfoFlags6__initZ@Base 6
+ _D3std6socket16Internet6Address4addrMxFNaNbNdNiNfZG16h@Base 6
+ _D3std6socket16Internet6Address4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket16Internet6Address4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket16Internet6Address4portMxFNaNbNdNiNfZt@Base 6
+ _D3std6socket16Internet6Address5parseFNexAaZG16h@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfG16htZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfS4core3sys5posix7netinet3in_12sockaddr_in6ZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNfZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNaNbNiNftZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNexAaxAaZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__ctorMFNfxAatZC3std6socket16Internet6Address@Base 6
+ _D3std6socket16Internet6Address6__initZ@Base 6
+ _D3std6socket16Internet6Address6__vtblZ@Base 6
+ _D3std6socket16Internet6Address7__ClassZ@Base 6
+ _D3std6socket16Internet6Address7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket16Internet6Address8ADDR_ANYFNaNbNcNdNiNfZxG16h@Base 6
+ _D3std6socket16wouldHaveBlockedFNbNiNfZb@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaAyakC6object9ThrowableiPFNeiZAyaZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaC6object9ThrowableAyakiPFNeiZAyaZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__ctorMFNfAyaiPFNeiZAyaAyakC6object9ThrowableZC3std6socket17SocketOSException@Base 6
+ _D3std6socket17SocketOSException6__initZ@Base 6
+ _D3std6socket17SocketOSException6__vtblZ@Base 6
+ _D3std6socket17SocketOSException7__ClassZ@Base 6
+ _D3std6socket17SocketOptionLevel6__initZ@Base 6
+ _D3std6socket17formatSocketErrorFNeiZAya@Base 6
+ _D3std6socket18_sharedStaticCtor1FZv@Base 6
+ _D3std6socket18_sharedStaticDtor2FNbNiZv@Base 6
+ _D3std6socket18getAddressInfoImplFxAaxAaPS4core3sys5posix5netdb8addrinfoZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket18getaddrinfoPointeryPUNbNiPxaPxaPxS4core3sys5posix5netdb8addrinfoPPS4core3sys5posix5netdb8addrinfoZi@Base 6
+ _D3std6socket18getnameinfoPointeryPUNbNiPxS4core3sys5posix3sys6socket8sockaddrkPakPakiZi@Base 6
+ _D3std6socket19freeaddrinfoPointeryPUNbNiPS4core3sys5posix5netdb8addrinfoZv@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaAyakC6object9ThrowableiZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaC6object9ThrowableAyakiZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__ctorMFNfAyaiAyakC6object9ThrowableZC3std6socket21SocketAcceptException@Base 6
+ _D3std6socket21SocketAcceptException6__initZ@Base 6
+ _D3std6socket21SocketAcceptException6__vtblZ@Base 6
+ _D3std6socket21SocketAcceptException7__ClassZ@Base 6
+ _D3std6socket22SocketFeatureException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6socket22SocketFeatureException@Base 6
+ _D3std6socket22SocketFeatureException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC3std6socket22SocketFeatureException@Base 6
+ _D3std6socket22SocketFeatureException6__initZ@Base 6
+ _D3std6socket22SocketFeatureException6__vtblZ@Base 6
+ _D3std6socket22SocketFeatureException7__ClassZ@Base 6
+ _D3std6socket23UnknownAddressReference4nameMFNaNbNdNiNfZPS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket23UnknownAddressReference4nameMxFNaNbNdNiNfZPxS4core3sys5posix3sys6socket8sockaddr@Base 6
+ _D3std6socket23UnknownAddressReference6__ctorMFNaNbNiNfPS4core3sys5posix3sys6socket8sockaddrkZC3std6socket23UnknownAddressReference@Base 6
+ _D3std6socket23UnknownAddressReference6__ctorMFNaNbPxS4core3sys5posix3sys6socket8sockaddrkZC3std6socket23UnknownAddressReference@Base 6
+ _D3std6socket23UnknownAddressReference6__initZ@Base 6
+ _D3std6socket23UnknownAddressReference6__vtblZ@Base 6
+ _D3std6socket23UnknownAddressReference7__ClassZ@Base 6
+ _D3std6socket23UnknownAddressReference7nameLenMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket24SocketParameterException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6socket24SocketParameterException@Base 6
+ _D3std6socket24SocketParameterException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC3std6socket24SocketParameterException@Base 6
+ _D3std6socket24SocketParameterException6__initZ@Base 6
+ _D3std6socket24SocketParameterException6__vtblZ@Base 6
+ _D3std6socket24SocketParameterException7__ClassZ@Base 6
+ _D3std6socket24__T14getAddressInfoTAxaZ14getAddressInfoFNexAaAxaZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket51__T14getAddressInfoTE3std6socket16AddressInfoFlagsZ14getAddressInfoFNexAaE3std6socket16AddressInfoFlagsZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket52__T14getAddressInfoTAxaTE3std6socket13AddressFamilyZ14getAddressInfoFNexAaAxaE3std6socket13AddressFamilyZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket55__T14getAddressInfoTAxaTE3std6socket16AddressInfoFlagsZ14getAddressInfoFNexAaAxaE3std6socket16AddressInfoFlagsZAS3std6socket11AddressInfo@Base 6
+ _D3std6socket6Linger6__initZ@Base 6
+ _D3std6socket6Linger8__mixin22onMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket6Linger8__mixin22onMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket6Linger8__mixin34timeMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket6Linger8__mixin34timeMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNeAvE3std6socket11SocketFlagsKC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNeAvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNfAvKC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket11receiveFromMFNfAvZi@Base 6
+ _D3std6socket6Socket12getErrorTextMFNfZAya@Base 6
+ _D3std6socket6Socket12localAddressMFNdNeZC3std6socket7Address@Base 6
+ _D3std6socket6Socket12setKeepAliveMFNeiiZv@Base 6
+ _D3std6socket6Socket13addressFamilyMFNdNfZE3std6socket13AddressFamily@Base 6
+ _D3std6socket6Socket13createAddressMFNaNbNfZC3std6socket7Address@Base 6
+ _D3std6socket6Socket13remoteAddressMFNdNeZC3std6socket7Address@Base 6
+ _D3std6socket6Socket4bindMFNeC3std6socket7AddressZv@Base 6
+ _D3std6socket6Socket4sendMFNeAxvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket4sendMFNfAxvZi@Base 6
+ _D3std6socket6Socket5closeMFNbNiNeZv@Base 6
+ _D3std6socket6Socket6__ctorMFNaNbNiNfE3std6socket8socket_tE3std6socket13AddressFamilyZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNaNbNiNfZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNeE3std6socket13AddressFamilyE3std6socket10SocketTypeE3std6socket12ProtocolTypeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNeE3std6socket13AddressFamilyE3std6socket10SocketTypexAaZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNfE3std6socket13AddressFamilyE3std6socket10SocketTypeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__ctorMFNfxS3std6socket11AddressInfoZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6__dtorMFNbNiNfZv@Base 6
+ _D3std6socket6Socket6__initZ@Base 6
+ _D3std6socket6Socket6__vtblZ@Base 6
+ _D3std6socket6Socket6_closeFNbNiE3std6socket8socket_tZv@Base 6
+ _D3std6socket6Socket6acceptMFNeZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket6handleMxFNaNbNdNiNfZE3std6socket8socket_t@Base 6
+ _D3std6socket6Socket6listenMFNeiZv@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetPS3std6socket7TimeValZi@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetS4core4time8DurationZi@Base 6
+ _D3std6socket6Socket6selectFNeC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetlZi@Base 6
+ _D3std6socket6Socket6selectFNfC3std6socket9SocketSetC3std6socket9SocketSetC3std6socket9SocketSetZi@Base 6
+ _D3std6socket6Socket6sendToMFNeAxvE3std6socket11SocketFlagsC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket6sendToMFNeAxvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket6sendToMFNfAxvC3std6socket7AddressZi@Base 6
+ _D3std6socket6Socket6sendToMFNfAxvZi@Base 6
+ _D3std6socket6Socket7__ClassZ@Base 6
+ _D3std6socket6Socket7connectMFNeC3std6socket7AddressZv@Base 6
+ _D3std6socket6Socket7isAliveMxFNdNeZb@Base 6
+ _D3std6socket6Socket7receiveMFNeAvE3std6socket11SocketFlagsZi@Base 6
+ _D3std6socket6Socket7receiveMFNfAvZi@Base 6
+ _D3std6socket6Socket7setSockMFNfE3std6socket8socket_tZv@Base 6
+ _D3std6socket6Socket8blockingMFNdNebZv@Base 6
+ _D3std6socket6Socket8blockingMxFNbNdNiNeZb@Base 6
+ _D3std6socket6Socket8hostNameFNdNeZAya@Base 6
+ _D3std6socket6Socket8shutdownMFNbNiNeE3std6socket14SocketShutdownZv@Base 6
+ _D3std6socket6Socket9acceptingMFNaNbNfZC3std6socket6Socket@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionAvZi@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJS3std6socket6LingerZi@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJS4core4time8DurationZv@Base 6
+ _D3std6socket6Socket9getOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionJiZi@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionAvZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionS3std6socket6LingerZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptionS4core4time8DurationZv@Base 6
+ _D3std6socket6Socket9setOptionMFNeE3std6socket17SocketOptionLevelE3std6socket12SocketOptioniZv@Base 6
+ _D3std6socket7Address12toAddrStringMxFNfZAya@Base 6
+ _D3std6socket7Address12toHostStringMxFNebZAya@Base 6
+ _D3std6socket7Address12toPortStringMxFNfZAya@Base 6
+ _D3std6socket7Address13addressFamilyMxFNaNbNdNiNfZE3std6socket13AddressFamily@Base 6
+ _D3std6socket7Address15toServiceStringMxFNebZAya@Base 6
+ _D3std6socket7Address16toHostNameStringMxFNfZAya@Base 6
+ _D3std6socket7Address19toServiceNameStringMxFNfZAya@Base 6
+ _D3std6socket7Address6__initZ@Base 6
+ _D3std6socket7Address6__vtblZ@Base 6
+ _D3std6socket7Address7__ClassZ@Base 6
+ _D3std6socket7Address8toStringMxFNfZAya@Base 6
+ _D3std6socket7Service16getServiceByNameMFNbNexAaxAaZb@Base 6
+ _D3std6socket7Service16getServiceByPortMFNbNetxAaZb@Base 6
+ _D3std6socket7Service6__initZ@Base 6
+ _D3std6socket7Service6__vtblZ@Base 6
+ _D3std6socket7Service7__ClassZ@Base 6
+ _D3std6socket7Service8populateMFNaNbPS4core3sys5posix5netdb7serventZv@Base 6
+ _D3std6socket7TimeVal6__initZ@Base 6
+ _D3std6socket7TimeVal8__mixin47secondsMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket7TimeVal8__mixin47secondsMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket7TimeVal8__mixin512microsecondsMFNaNbNdNiNfiZi@Base 6
+ _D3std6socket7TimeVal8__mixin512microsecondsMxFNaNbNdNiNfZi@Base 6
+ _D3std6socket8Protocol17getProtocolByNameMFNbNexAaZb@Base 6
+ _D3std6socket8Protocol17getProtocolByTypeMFNbNeE3std6socket12ProtocolTypeZb@Base 6
+ _D3std6socket8Protocol6__initZ@Base 6
+ _D3std6socket8Protocol6__vtblZ@Base 6
+ _D3std6socket8Protocol7__ClassZ@Base 6
+ _D3std6socket8Protocol8populateMFNaNbPS4core3sys5posix5netdb8protoentZv@Base 6
+ _D3std6socket8_lasterrFNbNiNfZi@Base 6
+ _D3std6socket8socket_t6__initZ@Base 6
+ _D3std6socket9SocketSet14setMinCapacityMFNaNbNfkZv@Base 6
+ _D3std6socket9SocketSet3addMFNaNbNeE3std6socket8socket_tZv@Base 6
+ _D3std6socket9SocketSet3addMFNaNbNfC3std6socket6SocketZv@Base 6
+ _D3std6socket9SocketSet3maxMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket9SocketSet4maskFNaNbNiNfkZi@Base 6
+ _D3std6socket9SocketSet5isSetMxFNaNbNiNfC3std6socket6SocketZi@Base 6
+ _D3std6socket9SocketSet5isSetMxFNaNbNiNfE3std6socket8socket_tZi@Base 6
+ _D3std6socket9SocketSet5resetMFNaNbNiNfZv@Base 6
+ _D3std6socket9SocketSet6__ctorMFNaNbNfkZC3std6socket9SocketSet@Base 6
+ _D3std6socket9SocketSet6__initZ@Base 6
+ _D3std6socket9SocketSet6__vtblZ@Base 6
+ _D3std6socket9SocketSet6removeMFNaNbNfC3std6socket6SocketZv@Base 6
+ _D3std6socket9SocketSet6removeMFNaNbNfE3std6socket8socket_tZv@Base 6
+ _D3std6socket9SocketSet6resizeMFNaNbNfkZv@Base 6
+ _D3std6socket9SocketSet7__ClassZ@Base 6
+ _D3std6socket9SocketSet7selectnMxFNaNbNiNfZi@Base 6
+ _D3std6socket9SocketSet8capacityMxFNaNbNdNiNfZk@Base 6
+ _D3std6socket9SocketSet8toFd_setMFNaNbNiNeZPS4core3sys5posix3sys6select6fd_set@Base 6
+ _D3std6socket9SocketSet9lengthForFNaNbNiNfkZk@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfC3std6socket7AddressZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfE3std6socket13AddressFamilyZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__ctorMFNfZC3std6socket9TcpSocket@Base 6
+ _D3std6socket9TcpSocket6__initZ@Base 6
+ _D3std6socket9TcpSocket6__vtblZ@Base 6
+ _D3std6socket9TcpSocket7__ClassZ@Base 6
+ _D3std6socket9UdpSocket6__ctorMFNfE3std6socket13AddressFamilyZC3std6socket9UdpSocket@Base 6
+ _D3std6socket9UdpSocket6__ctorMFNfZC3std6socket9UdpSocket@Base 6
+ _D3std6socket9UdpSocket6__initZ@Base 6
+ _D3std6socket9UdpSocket6__vtblZ@Base 6
+ _D3std6socket9UdpSocket7__ClassZ@Base 6
+ _D3std6stdint12__ModuleInfoZ@Base 6
+ _D3std6stream11InputStream11__InterfaceZ@Base 6
+ _D3std6stream11SliceStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream11SliceStream11__invariantMxFZv@Base 6
+ _D3std6stream11SliceStream13__invariant11MxFZv@Base 6
+ _D3std6stream11SliceStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream11SliceStream6__ctorMFC3std6stream6StreammZC3std6stream11SliceStream@Base 6
+ _D3std6stream11SliceStream6__ctorMFC3std6stream6StreammmZC3std6stream11SliceStream@Base 6
+ _D3std6stream11SliceStream6__initZ@Base 6
+ _D3std6stream11SliceStream6__vtblZ@Base 6
+ _D3std6stream11SliceStream7__ClassZ@Base 6
+ _D3std6stream11SliceStream9availableMFNdZk@Base 6
+ _D3std6stream11SliceStream9readBlockMFPvkZk@Base 6
+ _D3std6stream12BufferedFile4openMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream12BufferedFile6__ctorMFAyaE3std6stream8FileModekZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFC3std6stream4FilekZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__ctorMFiE3std6stream8FileModekZC3std6stream12BufferedFile@Base 6
+ _D3std6stream12BufferedFile6__initZ@Base 6
+ _D3std6stream12BufferedFile6__vtblZ@Base 6
+ _D3std6stream12BufferedFile6createMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream12BufferedFile7__ClassZ@Base 6
+ _D3std6stream12EndianStream10fixBlockBOMFPvkkZv@Base 6
+ _D3std6stream12EndianStream11readStringWMFkZAu@Base 6
+ _D3std6stream12EndianStream12writeStringWMFAxuZv@Base 6
+ _D3std6stream12EndianStream3eofMFNdZb@Base 6
+ _D3std6stream12EndianStream4readMFJaZv@Base 6
+ _D3std6stream12EndianStream4readMFJcZv@Base 6
+ _D3std6stream12EndianStream4readMFJdZv@Base 6
+ _D3std6stream12EndianStream4readMFJeZv@Base 6
+ _D3std6stream12EndianStream4readMFJfZv@Base 6
+ _D3std6stream12EndianStream4readMFJgZv@Base 6
+ _D3std6stream12EndianStream4readMFJhZv@Base 6
+ _D3std6stream12EndianStream4readMFJiZv@Base 6
+ _D3std6stream12EndianStream4readMFJjZv@Base 6
+ _D3std6stream12EndianStream4readMFJkZv@Base 6
+ _D3std6stream12EndianStream4readMFJlZv@Base 6
+ _D3std6stream12EndianStream4readMFJmZv@Base 6
+ _D3std6stream12EndianStream4readMFJoZv@Base 6
+ _D3std6stream12EndianStream4readMFJpZv@Base 6
+ _D3std6stream12EndianStream4readMFJqZv@Base 6
+ _D3std6stream12EndianStream4readMFJrZv@Base 6
+ _D3std6stream12EndianStream4readMFJsZv@Base 6
+ _D3std6stream12EndianStream4readMFJtZv@Base 6
+ _D3std6stream12EndianStream4readMFJuZv@Base 6
+ _D3std6stream12EndianStream4readMFJwZv@Base 6
+ _D3std6stream12EndianStream4sizeMFNdZm@Base 6
+ _D3std6stream12EndianStream5fixBOMFPxvkZv@Base 6
+ _D3std6stream12EndianStream5getcwMFZu@Base 6
+ _D3std6stream12EndianStream5writeMFaZv@Base 6
+ _D3std6stream12EndianStream5writeMFcZv@Base 6
+ _D3std6stream12EndianStream5writeMFdZv@Base 6
+ _D3std6stream12EndianStream5writeMFeZv@Base 6
+ _D3std6stream12EndianStream5writeMFfZv@Base 6
+ _D3std6stream12EndianStream5writeMFgZv@Base 6
+ _D3std6stream12EndianStream5writeMFhZv@Base 6
+ _D3std6stream12EndianStream5writeMFiZv@Base 6
+ _D3std6stream12EndianStream5writeMFjZv@Base 6
+ _D3std6stream12EndianStream5writeMFkZv@Base 6
+ _D3std6stream12EndianStream5writeMFlZv@Base 6
+ _D3std6stream12EndianStream5writeMFmZv@Base 6
+ _D3std6stream12EndianStream5writeMFoZv@Base 6
+ _D3std6stream12EndianStream5writeMFpZv@Base 6
+ _D3std6stream12EndianStream5writeMFqZv@Base 6
+ _D3std6stream12EndianStream5writeMFrZv@Base 6
+ _D3std6stream12EndianStream5writeMFsZv@Base 6
+ _D3std6stream12EndianStream5writeMFtZv@Base 6
+ _D3std6stream12EndianStream5writeMFuZv@Base 6
+ _D3std6stream12EndianStream5writeMFwZv@Base 6
+ _D3std6stream12EndianStream6__ctorMFC3std6stream6StreamE3std6system6EndianZC3std6stream12EndianStream@Base 6
+ _D3std6stream12EndianStream6__initZ@Base 6
+ _D3std6stream12EndianStream6__vtblZ@Base 6
+ _D3std6stream12EndianStream7__ClassZ@Base 6
+ _D3std6stream12EndianStream7readBOMMFiZi@Base 6
+ _D3std6stream12EndianStream8writeBOMMFE3std6stream3BOMZv@Base 6
+ _D3std6stream12FilterStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream12FilterStream11resetSourceMFZv@Base 6
+ _D3std6stream12FilterStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream12FilterStream5closeMFZv@Base 6
+ _D3std6stream12FilterStream5flushMFZv@Base 6
+ _D3std6stream12FilterStream6__ctorMFC3std6stream6StreamZC3std6stream12FilterStream@Base 6
+ _D3std6stream12FilterStream6__initZ@Base 6
+ _D3std6stream12FilterStream6__vtblZ@Base 6
+ _D3std6stream12FilterStream6sourceMFC3std6stream6StreamZv@Base 6
+ _D3std6stream12FilterStream6sourceMFZC3std6stream6Stream@Base 6
+ _D3std6stream12FilterStream7__ClassZ@Base 6
+ _D3std6stream12FilterStream9availableMFNdZk@Base 6
+ _D3std6stream12FilterStream9readBlockMFPvkZk@Base 6
+ _D3std6stream12MemoryStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAaZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAgZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFAhZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__ctorMFZC3std6stream12MemoryStream@Base 6
+ _D3std6stream12MemoryStream6__initZ@Base 6
+ _D3std6stream12MemoryStream6__vtblZ@Base 6
+ _D3std6stream12MemoryStream7__ClassZ@Base 6
+ _D3std6stream12MemoryStream7reserveMFkZv@Base 6
+ _D3std6stream12MmFileStream5closeMFZv@Base 6
+ _D3std6stream12MmFileStream5flushMFZv@Base 6
+ _D3std6stream12MmFileStream6__ctorMFC3std6mmfile6MmFileZC3std6stream12MmFileStream@Base 6
+ _D3std6stream12MmFileStream6__initZ@Base 6
+ _D3std6stream12MmFileStream6__vtblZ@Base 6
+ _D3std6stream12MmFileStream7__ClassZ@Base 6
+ _D3std6stream12OutputStream11__InterfaceZ@Base 6
+ _D3std6stream12__ModuleInfoZ@Base 6
+ _D3std6stream13OpenException6__ctorMFAyaZC3std6stream13OpenException@Base 6
+ _D3std6stream13OpenException6__initZ@Base 6
+ _D3std6stream13OpenException6__vtblZ@Base 6
+ _D3std6stream13OpenException7__ClassZ@Base 6
+ _D3std6stream13ReadException6__ctorMFAyaZC3std6stream13ReadException@Base 6
+ _D3std6stream13ReadException6__initZ@Base 6
+ _D3std6stream13ReadException6__vtblZ@Base 6
+ _D3std6stream13ReadException7__ClassZ@Base 6
+ _D3std6stream13SeekException6__ctorMFAyaZC3std6stream13SeekException@Base 6
+ _D3std6stream13SeekException6__initZ@Base 6
+ _D3std6stream13SeekException6__vtblZ@Base 6
+ _D3std6stream13SeekException7__ClassZ@Base 6
+ _D3std6stream14BufferedStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream14BufferedStream11__invariantMxFZv@Base 6
+ _D3std6stream14BufferedStream11resetSourceMFZv@Base 6
+ _D3std6stream14BufferedStream12__invariant3MxFZv@Base 6
+ _D3std6stream14BufferedStream16__T9TreadLineTaZ8readLineMFAaZAa@Base 6
+ _D3std6stream14BufferedStream16__T9TreadLineTuZ8readLineMFAuZAu@Base 6
+ _D3std6stream14BufferedStream3eofMFNdZb@Base 6
+ _D3std6stream14BufferedStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream14BufferedStream4sizeMFNdZm@Base 6
+ _D3std6stream14BufferedStream5flushMFZv@Base 6
+ _D3std6stream14BufferedStream6__ctorMFC3std6stream6StreamkZC3std6stream14BufferedStream@Base 6
+ _D3std6stream14BufferedStream6__initZ@Base 6
+ _D3std6stream14BufferedStream6__vtblZ@Base 6
+ _D3std6stream14BufferedStream7__ClassZ@Base 6
+ _D3std6stream14BufferedStream8readLineMFAaZAa@Base 6
+ _D3std6stream14BufferedStream9availableMFNdZk@Base 6
+ _D3std6stream14BufferedStream9readBlockMFPvkZk@Base 6
+ _D3std6stream14BufferedStream9readLineWMFAuZAu@Base 6
+ _D3std6stream14ByteOrderMarksyG5Ah@Base 6
+ _D3std6stream14WriteException6__ctorMFAyaZC3std6stream14WriteException@Base 6
+ _D3std6stream14WriteException6__initZ@Base 6
+ _D3std6stream14WriteException6__vtblZ@Base 6
+ _D3std6stream14WriteException7__ClassZ@Base 6
+ _D3std6stream15StreamException6__ctorMFAyaZC3std6stream15StreamException@Base 6
+ _D3std6stream15StreamException6__initZ@Base 6
+ _D3std6stream15StreamException6__vtblZ@Base 6
+ _D3std6stream15StreamException7__ClassZ@Base 6
+ _D3std6stream19StreamFileException6__ctorMFAyaZC3std6stream19StreamFileException@Base 6
+ _D3std6stream19StreamFileException6__initZ@Base 6
+ _D3std6stream19StreamFileException6__vtblZ@Base 6
+ _D3std6stream19StreamFileException7__ClassZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream11__invariantMxFNaNbNiNfZv@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream15__invariant2473MxFNaNbNiNfZv@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream4dataMFNdZAh@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__ctorMFAhZC3std6stream21__T12TArrayStreamTAhZ12TArrayStream@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__initZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream6__vtblZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream7__ClassZ@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream8toStringMFZAya@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9availableMFNdZk@Base 6
+ _D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9readBlockMFPvkZk@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream10writeBlockMFxPvkZk@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream11__invariantMxFZv@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream15__invariant2474MxFZv@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream4dataMFNdZAh@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__ctorMFC3std6mmfile6MmFileZC3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__initZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream6__vtblZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream7__ClassZ@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream8toStringMFZAya@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9availableMFNdZk@Base 6
+ _D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9readBlockMFPvkZk@Base 6
+ _D3std6stream4File10writeBlockMFxPvkZk@Base 6
+ _D3std6stream4File4openMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream4File4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std6stream4File5closeMFZv@Base 6
+ _D3std6stream4File6__ctorMFAyaE3std6stream8FileModeZC3std6stream4File@Base 6
+ _D3std6stream4File6__ctorMFZC3std6stream4File@Base 6
+ _D3std6stream4File6__ctorMFiE3std6stream8FileModeZC3std6stream4File@Base 6
+ _D3std6stream4File6__dtorMFZv@Base 6
+ _D3std6stream4File6__initZ@Base 6
+ _D3std6stream4File6__vtblZ@Base 6
+ _D3std6stream4File6createMFAyaE3std6stream8FileModeZv@Base 6
+ _D3std6stream4File6createMFAyaZv@Base 6
+ _D3std6stream4File6handleMFZi@Base 6
+ _D3std6stream4File7__ClassZ@Base 6
+ _D3std6stream4File9availableMFNdZk@Base 6
+ _D3std6stream4File9parseModeMFiJiJiJiZv@Base 6
+ _D3std6stream4File9readBlockMFPvkZk@Base 6
+ _D3std6stream6Stream10readStringMFkZAa@Base 6
+ _D3std6stream6Stream10writeExactMFxPvkZv@Base 6
+ _D3std6stream6Stream10writeLineWMFAxuZv@Base 6
+ _D3std6stream6Stream11readStringWMFkZAu@Base 6
+ _D3std6stream6Stream11writeStringMFAxaZv@Base 6
+ _D3std6stream6Stream12writeStringWMFAxuZv@Base 6
+ _D3std6stream6Stream14assertReadableMFZv@Base 6
+ _D3std6stream6Stream14assertSeekableMFZv@Base 6
+ _D3std6stream6Stream14ungetAvailableMFZb@Base 6
+ _D3std6stream6Stream15assertWriteableMFZv@Base 6
+ _D3std6stream6Stream16doFormatCallbackMFwZv@Base 6
+ _D3std6stream6Stream3eofMFNdZb@Base 6
+ _D3std6stream6Stream4getcMFZa@Base 6
+ _D3std6stream6Stream4readMFAhZk@Base 6
+ _D3std6stream6Stream4readMFJAaZv@Base 6
+ _D3std6stream6Stream4readMFJAuZv@Base 6
+ _D3std6stream6Stream4readMFJaZv@Base 6
+ _D3std6stream6Stream4readMFJcZv@Base 6
+ _D3std6stream6Stream4readMFJdZv@Base 6
+ _D3std6stream6Stream4readMFJeZv@Base 6
+ _D3std6stream6Stream4readMFJfZv@Base 6
+ _D3std6stream6Stream4readMFJgZv@Base 6
+ _D3std6stream6Stream4readMFJhZv@Base 6
+ _D3std6stream6Stream4readMFJiZv@Base 6
+ _D3std6stream6Stream4readMFJjZv@Base 6
+ _D3std6stream6Stream4readMFJkZv@Base 6
+ _D3std6stream6Stream4readMFJlZv@Base 6
+ _D3std6stream6Stream4readMFJmZv@Base 6
+ _D3std6stream6Stream4readMFJoZv@Base 6
+ _D3std6stream6Stream4readMFJpZv@Base 6
+ _D3std6stream6Stream4readMFJqZv@Base 6
+ _D3std6stream6Stream4readMFJrZv@Base 6
+ _D3std6stream6Stream4readMFJsZv@Base 6
+ _D3std6stream6Stream4readMFJtZv@Base 6
+ _D3std6stream6Stream4readMFJuZv@Base 6
+ _D3std6stream6Stream4readMFJwZv@Base 6
+ _D3std6stream6Stream4sizeMFNdZm@Base 6
+ _D3std6stream6Stream5closeMFZv@Base 6
+ _D3std6stream6Stream5flushMFZv@Base 6
+ _D3std6stream6Stream5getcwMFZu@Base 6
+ _D3std6stream6Stream5readfMFYi@Base 6
+ _D3std6stream6Stream5writeMFAxaZv@Base 6
+ _D3std6stream6Stream5writeMFAxhZk@Base 6
+ _D3std6stream6Stream5writeMFAxuZv@Base 6
+ _D3std6stream6Stream5writeMFaZv@Base 6
+ _D3std6stream6Stream5writeMFcZv@Base 6
+ _D3std6stream6Stream5writeMFdZv@Base 6
+ _D3std6stream6Stream5writeMFeZv@Base 6
+ _D3std6stream6Stream5writeMFfZv@Base 6
+ _D3std6stream6Stream5writeMFgZv@Base 6
+ _D3std6stream6Stream5writeMFhZv@Base 6
+ _D3std6stream6Stream5writeMFiZv@Base 6
+ _D3std6stream6Stream5writeMFjZv@Base 6
+ _D3std6stream6Stream5writeMFkZv@Base 6
+ _D3std6stream6Stream5writeMFlZv@Base 6
+ _D3std6stream6Stream5writeMFmZv@Base 6
+ _D3std6stream6Stream5writeMFoZv@Base 6
+ _D3std6stream6Stream5writeMFpZv@Base 6
+ _D3std6stream6Stream5writeMFqZv@Base 6
+ _D3std6stream6Stream5writeMFrZv@Base 6
+ _D3std6stream6Stream5writeMFsZv@Base 6
+ _D3std6stream6Stream5writeMFtZv@Base 6
+ _D3std6stream6Stream5writeMFuZv@Base 6
+ _D3std6stream6Stream5writeMFwZv@Base 6
+ _D3std6stream6Stream6__ctorMFZC3std6stream6Stream@Base 6
+ _D3std6stream6Stream6__initZ@Base 6
+ _D3std6stream6Stream6__vtblZ@Base 6
+ _D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _D3std6stream6Stream6printfMFAxaYk@Base 6
+ _D3std6stream6Stream6toHashMFNbNeZk@Base 6
+ _D3std6stream6Stream6toHashMFNeZ8resUnion6__initZ@Base 6
+ _D3std6stream6Stream6ungetcMFaZa@Base 6
+ _D3std6stream6Stream6vreadfMFAC8TypeInfoS3gcc8builtins9__va_listZi@Base 6.2.1-1ubuntu2
+ _D3std6stream6Stream6writefMFYC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream7__ClassZ@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKAaZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKAuZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKmKAaZiZi@Base 6
+ _D3std6stream6Stream7opApplyMFMDFKmKAuZiZi@Base 6
+ _D3std6stream6Stream7seekCurMFlZm@Base 6
+ _D3std6stream6Stream7seekEndMFlZm@Base 6
+ _D3std6stream6Stream7seekSetMFlZm@Base 6
+ _D3std6stream6Stream7ungetcwMFuZu@Base 6
+ _D3std6stream6Stream7vprintfMFAxaS3gcc8builtins9__va_listZk@Base 6.2.1-1ubuntu2
+ _D3std6stream6Stream7writefxMFAC8TypeInfoS3gcc8builtins9__va_listiZC3std6stream12OutputStream@Base 6.2.1-1ubuntu2
+ _D3std6stream6Stream8copyFromMFC3std6stream6StreamZv@Base 6
+ _D3std6stream6Stream8copyFromMFC3std6stream6StreammZv@Base 6
+ _D3std6stream6Stream8positionMFNdZm@Base 6
+ _D3std6stream6Stream8positionMFNdmZv@Base 6
+ _D3std6stream6Stream8readLineMFAaZAa@Base 6
+ _D3std6stream6Stream8readLineMFZAa@Base 6
+ _D3std6stream6Stream8toStringMFZAya@Base 6
+ _D3std6stream6Stream8writeflnMFYC3std6stream12OutputStream@Base 6
+ _D3std6stream6Stream9availableMFNdZk@Base 6
+ _D3std6stream6Stream9readExactMFPvkZv@Base 6
+ _D3std6stream6Stream9readLineWMFAuZAu@Base 6
+ _D3std6stream6Stream9readLineWMFZAu@Base 6
+ _D3std6stream6Stream9writeLineMFAxaZv@Base 6
+ _D3std6stream8FileMode6__initZ@Base 6
+ _D3std6stream9BOMEndianyG5E3std6system6Endian@Base 6
+ _D3std6string11fromStringzFNaNbNiPNgaZANga@Base 6
+ _D3std6string12__ModuleInfoZ@Base 6
+ _D3std6string14__T5chompTAxaZ5chompFNaNbNiNfAxaZAxa@Base 6
+ _D3std6string14__T5stripTAyaZ5stripFNaNfAyaZAya@Base 6
+ _D3std6string14makeTransTableFNaNbNiNfxAaxAaZG256a@Base 6
+ _D3std6string15StringException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std6string15StringException@Base 6
+ _D3std6string15StringException6__initZ@Base 6
+ _D3std6string15StringException6__vtblZ@Base 6
+ _D3std6string15StringException7__ClassZ@Base 6
+ _D3std6string16__T7indexOfTAyaZ7indexOfFNaNbNiNfAyaxwxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZi@Base 6
+ _D3std6string18__T5munchTAyaTAyaZ5munchFNaNiNfKAyaAyaZAya@Base 6
+ _D3std6string18__T7indexOfTAyaTaZ7indexOfFAyaAxaxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZ18__T9__lambda4TwTwZ9__lambda4FNaNbNiNfwwZb@Base 6
+ _D3std6string18__T7indexOfTAyaTaZ7indexOfFNaNfAyaAxaxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZi@Base 6
+ _D3std6string18__T9inPatternTAyaZ9inPatternFNaNiNfwxAyaZb@Base 6
+ _D3std6string18__T9soundexerTAxaZ9soundexerFAxaZ3dexyAa@Base 6
+ _D3std6string18__T9soundexerTAxaZ9soundexerFNaNbNiNfAxaZG4a@Base 6
+ _D3std6string18__T9stripLeftTAyaZ9stripLeftFNaNfAyaZAya@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFNaNbNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result10initializeMFNaNbNiNfZv@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result11__xopEqualsFKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZb@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result4saveMFNaNbNdNiNfZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result5frontMFNaNbNdNiNfZw@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__ctorMFNaNbNcNiNfS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__initZ@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result9__xtoHashFNbNeKxS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZk@Base 6
+ _D3std6string19__T11lastIndexOfTaZ11lastIndexOfFNaNiNfAxaxwxE3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4FlagZi@Base 6
+ _D3std6string20__T10stripRightTAyaZ10stripRightFNaNiNfAyaZAya@Base 6
+ _D3std6string22__T12rightJustifyTAyaZ12rightJustifyFNaNbNfAyakwZAya@Base 6
+ _D3std6string23__T14representationTyaZ14representationFNaNbNiNfAyaZAyh@Base 6
+ _D3std6string24__T14rightJustifierTAyaZ14rightJustifierFNaNbNiNfAyakwZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std6string6abbrevFNaNfAAyaZHAyaAya@Base 6
+ _D3std6string7soundexFNaNbNfAxaAaZAa@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda3TAxaTAyaZ9__lambda3FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda4TAxaTAyaZ9__lambda4FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZ22__T9__lambda5TAxaTAyaZ9__lambda5FNaNfAxaAyaZb@Base 6
+ _D3std6string9isNumericFNaNfAxaxbZb@Base 6
+ _D3std6string9makeTransFNaNbNexAaxAaZAya@Base 6
+ _D3std6string9toStringzFNaNbNeAxaZPya@Base 6
+ _D3std6string9toStringzFNaNbNexAyaZPya@Base 6
+ _D3std6system12__ModuleInfoZ@Base 6
+ _D3std6system2OS6__initZ@Base 6
+ _D3std6system2osyE3std6system2OS@Base 6
+ _D3std6system6endianyE3std6system6Endian@Base 6
+ _D3std6traits12__ModuleInfoZ@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle11__xopEqualsFKxS3std6traits15__T8DemangleTkZ8DemangleKxS3std6traits15__T8DemangleTkZ8DemangleZb@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle6__initZ@Base 6
+ _D3std6traits15__T8DemangleTkZ8Demangle9__xtoHashFNbNeKxS3std6traits15__T8DemangleTkZ8DemangleZk@Base 6
+ _D3std6traits19removeDummyEnvelopeFAyaZAya@Base 6
+ _D3std6traits23__InoutWorkaroundStruct6__initZ@Base 6
+ _D3std6traits26demangleFunctionAttributesFAyaZS3std6traits15__T8DemangleTkZ8Demangle@Base 6
+ _D3std6traits29demangleParameterStorageClassFAyaZS3std6traits15__T8DemangleTkZ8Demangle@Base 6
+ _D3std7complex12__ModuleInfoZ@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex11__xopEqualsFKxS3std7complex14__T7ComplexTeZ7ComplexKxS3std7complex14__T7ComplexTeZ7ComplexZb@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex15__T8toStringTaZ8toStringMxFMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex16__T8opEqualsHTeZ8opEqualsMxFNaNbNiNfS3std7complex14__T7ComplexTeZ7ComplexZb@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex17__T6__ctorHTeHTeZ6__ctorMFNaNbNcNiNfeeZS3std7complex14__T7ComplexTeZ7Complex@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex6__initZ@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex8toStringMxFZAya@Base 6
+ _D3std7complex14__T7ComplexTeZ7Complex9__xtoHashFNbNeKxS3std7complex14__T7ComplexTeZ7ComplexZk@Base 6
+ _D3std7complex4expiFNaNbNiNeeZS3std7complex14__T7ComplexTeZ7Complex@Base 6
+ _D3std7cstream12__ModuleInfoZ@Base 6
+ _D3std7cstream18_sharedStaticCtor2FZv@Base 6
+ _D3std7cstream3dinC3std7cstream5CFile@Base 6
+ _D3std7cstream4derrC3std7cstream5CFile@Base 6
+ _D3std7cstream4doutC3std7cstream5CFile@Base 6
+ _D3std7cstream5CFile10writeBlockMFxPvkZk@Base 6
+ _D3std7cstream5CFile10writeLineWMFAxuZv@Base 6
+ _D3std7cstream5CFile3eofMFZb@Base 6
+ _D3std7cstream5CFile4fileMFNdPOS4core4stdc5stdio8_IO_FILEZv@Base 6
+ _D3std7cstream5CFile4fileMFNdZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std7cstream5CFile4getcMFZa@Base 6
+ _D3std7cstream5CFile4seekMFlE3std6stream7SeekPosZm@Base 6
+ _D3std7cstream5CFile5closeMFZv@Base 6
+ _D3std7cstream5CFile5flushMFZv@Base 6
+ _D3std7cstream5CFile6__ctorMFPOS4core4stdc5stdio8_IO_FILEE3std6stream8FileModebZC3std7cstream5CFile@Base 6
+ _D3std7cstream5CFile6__dtorMFZv@Base 6
+ _D3std7cstream5CFile6__initZ@Base 6
+ _D3std7cstream5CFile6__vtblZ@Base 6
+ _D3std7cstream5CFile6ungetcMFaZa@Base 6
+ _D3std7cstream5CFile7__ClassZ@Base 6
+ _D3std7cstream5CFile9readBlockMFPvkZk@Base 6
+ _D3std7cstream5CFile9writeLineMFAxaZv@Base 6
+ _D3std7numeric12__ModuleInfoZ@Base 6
+ _D3std7numeric12isPowerOfTwoFkZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride11__xopEqualsFKxS3std7numeric14__T6StrideTAfZ6StrideKxS3std7numeric14__T6StrideTAfZ6StrideZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride11doubleStepsMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride4saveMFNaNbNdNiNfZS3std7numeric14__T6StrideTAfZ6Stride@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride5frontMFNaNbNdNiNfZf@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6__ctorMFNaNbNcNiNfAfkZS3std7numeric14__T6StrideTAfZ6Stride@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6__initZ@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6nStepsMFNaNbNdNiNfkZk@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride6nStepsMxFNaNbNdNiNfZk@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride7opIndexMFNaNbNiNfkZf@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride7popHalfMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride8popFrontMFNaNbNiNfZv@Base 6
+ _D3std7numeric14__T6StrideTAfZ6Stride9__xtoHashFNbNeKxS3std7numeric14__T6StrideTAfZ6StrideZk@Base 6
+ _D3std7numeric16CustomFloatFlags6__initZ@Base 6
+ _D3std7numeric19roundDownToPowerOf2FkZk@Base 6
+ _D3std7numeric24__T13oppositeSignsTyeTeZ13oppositeSignsFNaNbNiNfyeeZb@Base 6
+ _D3std7numeric29__T8findRootTeTDFNaNbNiNfeZeZ8findRootFMDFNaNbNiNfeZexexeZ9__lambda4FNaNbNiNfeeZb@Base 6
+ _D3std7numeric29__T8findRootTeTDFNaNbNiNfeZeZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexeZe@Base 6
+ _D3std7numeric3Fft4sizeMxFNdZk@Base 6
+ _D3std7numeric3Fft6__ctorMFAfZC3std7numeric3Fft@Base 6
+ _D3std7numeric3Fft6__ctorMFkZC3std7numeric3Fft@Base 6
+ _D3std7numeric3Fft6__initZ@Base 6
+ _D3std7numeric3Fft6__vtblZ@Base 6
+ _D3std7numeric3Fft7__ClassZ@Base 6
+ _D3std7numeric44__T8findRootTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexeMPFNaNbNiNfeeZbZe@Base 6
+ _D3std7numeric46__T8findRootTeTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFMDFNaNbNiNfeZexexexexeMPFNaNbNiNfeeZbZ18secant_interpolateFNaNbNiNfeeeeZe@Base 6
+ _D3std7numeric46__T8findRootTeTeTDFNaNbNiNfeZeTPFNaNbNiNfeeZbZ8findRootFNaNbNiNfMDFNaNbNiNfeZexexexexeMPFNaNbNiNfeeZbZS3std8typecons18__T5TupleTeTeTeTeZ5Tuple@Base 6
+ _D3std7numeric5bsr64FmZ5Ulong6__initZ@Base 6
+ _D3std7numeric5bsr64FmZi@Base 6
+ _D3std7process10setCLOEXECFibZv@Base 6
+ _D3std7process10spawnShellFNexAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process10spawnShellFNexAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process10toAStringzFxAAyaPPxaZv@Base 6
+ _D3std7process11environment13opIndexAssignFNeNgAaxAaZANga@Base 6
+ _D3std7process11environment3getFNfxAaAyaZAya@Base 6
+ _D3std7process11environment4toAAFNeZHAyaAya@Base 6
+ _D3std7process11environment6__initZ@Base 6
+ _D3std7process11environment6__vtblZ@Base 6
+ _D3std7process11environment6removeFNbNiNexAaZv@Base 6
+ _D3std7process11environment7__ClassZ@Base 6
+ _D3std7process11environment7getImplFNexAaJAyaZ10lastResultAya@Base 6
+ _D3std7process11environment7getImplFNexAaJAyaZb@Base 6
+ _D3std7process11environment7opIndexFNfxAaZAya@Base 6
+ _D3std7process11pipeProcessFNfxAAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process11pipeProcessFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process11shellSwitchyAa@Base 6
+ _D3std7process12ProcessPipes11__fieldDtorMFNeZv@Base 6
+ _D3std7process12ProcessPipes11__xopEqualsFKxS3std7process12ProcessPipesKxS3std7process12ProcessPipesZb@Base 6
+ _D3std7process12ProcessPipes15__fieldPostblitMFNeZv@Base 6
+ _D3std7process12ProcessPipes3pidMFNbNdNfZC3std7process3Pid@Base 6
+ _D3std7process12ProcessPipes5stdinMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes6__initZ@Base 6
+ _D3std7process12ProcessPipes6stderrMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes6stdoutMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process12ProcessPipes8opAssignMFNcNjNeS3std7process12ProcessPipesZS3std7process12ProcessPipes@Base 6
+ _D3std7process12ProcessPipes9__xtoHashFNbNeKxS3std7process12ProcessPipesZk@Base 6
+ _D3std7process12__ModuleInfoZ@Base 6
+ _D3std7process12executeShellFNexAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process12isExecutableFNbNiNexAaZb@Base 6
+ _D3std7process12spawnProcessFNexAAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process12spawnProcessFNexAaxHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process136__T11executeImplS111_D3std7process9pipeShellFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipesTAxaZ11executeImplFAxaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process13charAllocatorFNaNbNfkZAa@Base 6
+ _D3std7process13searchPathForFNexAaZAya@Base 6
+ _D3std7process13thisProcessIDFNbNdNeZi@Base 6
+ _D3std7process16ProcessException12newFromErrnoFAyaAyakZC3std7process16ProcessException@Base 6
+ _D3std7process16ProcessException6__ctorMFAyaAyakZC3std7process16ProcessException@Base 6
+ _D3std7process16ProcessException6__initZ@Base 6
+ _D3std7process16ProcessException6__vtblZ@Base 6
+ _D3std7process16ProcessException7__ClassZ@Base 6
+ _D3std7process16spawnProcessImplFNexAAaS3std5stdio4FileS3std5stdio4FileS3std5stdio4FilexHAyaAyaE3std7process6ConfigxAaZC3std7process3Pid@Base 6
+ _D3std7process18escapeShellCommandFNaNfxAAaXAya@Base 6
+ _D3std7process19escapePosixArgumentFNaNbNexAaZAya@Base 6
+ _D3std7process19escapeShellFileNameFNaNbNexAaZAya@Base 6
+ _D3std7process20escapeShellArgumentsFNaNbNexAAaX9allocatorMFNaNbNfkZAa@Base 6
+ _D3std7process20escapeShellArgumentsFNaNbNexAAaXAya@Base 6
+ _D3std7process21escapeWindowsArgumentFNaNbNexAaZAya@Base 6
+ _D3std7process24escapeShellCommandStringFNaNfAyaZAya@Base 6
+ _D3std7process25escapeWindowsShellCommandFNaNfxAaZAya@Base 6
+ _D3std7process3Pid11performWaitMFNebZi@Base 6
+ _D3std7process3Pid6__ctorMFNaNbNfiZC3std7process3Pid@Base 6
+ _D3std7process3Pid6__initZ@Base 6
+ _D3std7process3Pid6__vtblZ@Base 6
+ _D3std7process3Pid7__ClassZ@Base 6
+ _D3std7process3Pid8osHandleMFNaNbNdNfZi@Base 6
+ _D3std7process3Pid9processIDMxFNaNbNdNfZi@Base 6
+ _D3std7process49__T11executeImplS253std7process11pipeProcessTAxaZ11executeImplFAxaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process4Pipe11__fieldDtorMFNeZv@Base 6
+ _D3std7process4Pipe11__xopEqualsFKxS3std7process4PipeKxS3std7process4PipeZb@Base 6
+ _D3std7process4Pipe15__fieldPostblitMFNeZv@Base 6
+ _D3std7process4Pipe5closeMFNfZv@Base 6
+ _D3std7process4Pipe6__initZ@Base 6
+ _D3std7process4Pipe7readEndMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process4Pipe8opAssignMFNcNjNeS3std7process4PipeZS3std7process4Pipe@Base 6
+ _D3std7process4Pipe8writeEndMFNbNdNfZS3std5stdio4File@Base 6
+ _D3std7process4Pipe9__xtoHashFNbNeKxS3std7process4PipeZk@Base 6
+ _D3std7process4killFC3std7process3PidZv@Base 6
+ _D3std7process4killFC3std7process3PidiZv@Base 6
+ _D3std7process4pipeFNeZS3std7process4Pipe@Base 6
+ _D3std7process4waitFNfC3std7process3PidZi@Base 6
+ _D3std7process50__T11executeImplS253std7process11pipeProcessTAxAaZ11executeImplFAxAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process52__T15pipeProcessImplS243std7process10spawnShellTAxaZ15pipeProcessImplFNeAxaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process54__T15pipeProcessImplS263std7process12spawnProcessTAxaZ15pipeProcessImplFNeAxaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process55__T15pipeProcessImplS263std7process12spawnProcessTAxAaZ15pipeProcessImplFNeAxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process5execvFxAyaxAAyaZi@Base 6
+ _D3std7process5shellFAyaZAya@Base 6
+ _D3std7process6browseFAyaZv@Base 6
+ _D3std7process6execv_FxAyaxAAyaZi@Base 6
+ _D3std7process6execveFxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process6execvpFxAyaxAAyaZi@Base 6
+ _D3std7process6getenvFNbxAaZ10lastResultAya@Base 6
+ _D3std7process6getenvFNbxAaZAya@Base 6
+ _D3std7process6setenvFxAaxAabZv@Base 6
+ _D3std7process6systemFAyaZi@Base 6
+ _D3std7process72__T23escapePosixArgumentImplS40_D3std7process13charAllocatorFNaNbNfkZAaZ23escapePosixArgumentImplFNaNbNfxAaZAa@Base 6
+ _D3std7process74__T25escapeWindowsArgumentImplS40_D3std7process13charAllocatorFNaNbNfkZAaZ25escapeWindowsArgumentImplFNaNbNfxAaZAa@Base 6
+ _D3std7process7executeFNexAAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process7executeFNexAaxHAyaAyaE3std7process6ConfigkxAaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std7process7execve_FxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process7execvp_FxAyaxAAyaZi@Base 6
+ _D3std7process7execvpeFxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process7spawnvpFiAyaAAyaZi@Base 6
+ _D3std7process7tryWaitFNfC3std7process3PidZS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple@Base 6
+ _D3std7process8Redirect6__initZ@Base 6
+ _D3std7process8_spawnvpFixPaxPPaZi@Base 6
+ _D3std7process8execvpe_FxAyaxAAyaxAAyaZi@Base 6
+ _D3std7process8unsetenvFxAaZv@Base 6
+ _D3std7process9createEnvFxHAyaAyabZPxPa@Base 6
+ _D3std7process9pipeShellFNfxAaE3std7process8RedirectxHAyaAyaE3std7process6ConfigxAaZS3std7process12ProcessPipes@Base 6
+ _D3std7process9userShellFNdNfZAya@Base 6
+ _D3std7signals12__ModuleInfoZ@Base 6
+ _D3std7signals6linkinFZv@Base 6
+ _D3std7variant12__ModuleInfoZ@Base 6
+ _D3std7variant16VariantException6__ctorMFAyaZC3std7variant16VariantException@Base 6
+ _D3std7variant16VariantException6__ctorMFC8TypeInfoC8TypeInfoZC3std7variant16VariantException@Base 6
+ _D3std7variant16VariantException6__initZ@Base 6
+ _D3std7variant16VariantException6__vtblZ@Base 6
+ _D3std7variant16VariantException7__ClassZ@Base 6
+ _D3std7variant18__T8VariantNVki16Z8VariantN10__T3getTbZ3getMNgFNdZNgb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN10__T3getTiZ3getMNgFNdZNgi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN10__T3getTkZ3getMNgFNdZNgk@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN10__postblitMFZv@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN113__T3getTS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ3getMNgFNdZNgS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN115__T3getTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ3getMNgFNdZNgS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN118__T6__ctorTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ6__ctorMFNcS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ10tryPuttingFPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleC8TypeInfoPvZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ6getPtrFNaNbNiPvZPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ7compareFPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TuplePS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleE3std7variant18__T8VariantNVki16Z8VariantN4OpIDZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN119__T7handlerTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN11SizeChecker6__initZ@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN11__T3getTyhZ3getMNgFNdZyh@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN11__T4peekTvZ4peekMNgFNdZPNgv@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN11__xopEqualsFKxS3std7variant18__T8VariantNVki16Z8VariantNKxS3std7variant18__T8VariantNVki16Z8VariantNZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN120__T8opAssignTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opAssignMFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN121__T10convertsToTS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN123__T10convertsToTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN12__T3getTAyhZ3getMNgFNdZNgAyh@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN15__T6__ctorTAyhZ6__ctorMFNcAyhZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN15__T7handlerHTvZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ10tryPuttingFPyhC8TypeInfoPvZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ6getPtrFNaNbNiPvZPyh@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ7compareFNaNbNiNfPyhPyhE3std7variant18__T8VariantNVki16Z8VariantN4OpIDZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN15__T7handlerTyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ10tryPuttingFPAyhC8TypeInfoPvZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ6getPtrFNaNbNiPvZPAyh@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ7compareFNaNbNiNfPAyhPAyhE3std7variant18__T8VariantNVki16Z8VariantN4OpIDZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN16__T7handlerTAyhZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN16__T8opAssignTyhZ8opAssignMFyhZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN17__T8opAssignTAyhZ8opAssignMFAyhZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN18__T10convertsToTbZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN18__T10convertsToTiZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN19__T10convertsToTyhZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN20__T10convertsToTAyhZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN27__T3getTC6object9ThrowableZ3getMNgFNdZNgC6object9Throwable@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN28__T3getTOC6object9ThrowableZ3getMNgFNdZONgC6object9Throwable@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN31__T3getTS3std11concurrency3TidZ3getMNgFNdZNgS3std11concurrency3Tid@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN34__T6__ctorTS3std11concurrency3TidZ6__ctorMFNcS3std11concurrency3TidZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN35__T10convertsToTC6object9ThrowableZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ10tryPuttingFPS3std11concurrency3TidC8TypeInfoPvZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ6getPtrFNaNbNiPvZPS3std11concurrency3Tid@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ7compareFPS3std11concurrency3TidPS3std11concurrency3TidE3std7variant18__T8VariantNVki16Z8VariantN4OpIDZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN35__T7handlerTS3std11concurrency3TidZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN36__T10convertsToTOC6object9ThrowableZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN36__T8opAssignTS3std11concurrency3TidZ8opAssignMFS3std11concurrency3TidZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN39__T10convertsToTS3std11concurrency3TidZ10convertsToMxFNdZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN46__T6__ctorTC3std11concurrency14LinkTerminatedZ6__ctorMFNcC3std11concurrency14LinkTerminatedZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN47__T6__ctorTC3std11concurrency15OwnerTerminatedZ6__ctorMFNcC3std11concurrency15OwnerTerminatedZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ10tryPuttingFPC3std11concurrency14LinkTerminatedC8TypeInfoPvZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ6getPtrFNaNbNiPvZPC3std11concurrency14LinkTerminated@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ7compareFPC3std11concurrency14LinkTerminatedPC3std11concurrency14LinkTerminatedE3std7variant18__T8VariantNVki16Z8VariantN4OpIDZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN47__T7handlerTC3std11concurrency14LinkTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ10tryPuttingFPC3std11concurrency15OwnerTerminatedC8TypeInfoPvZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ6getPtrFNaNbNiPvZPC3std11concurrency15OwnerTerminated@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZ7compareFPC3std11concurrency15OwnerTerminatedPC3std11concurrency15OwnerTerminatedE3std7variant18__T8VariantNVki16Z8VariantN4OpIDZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN48__T7handlerTC3std11concurrency15OwnerTerminatedZ7handlerFE3std7variant18__T8VariantNVki16Z8VariantN4OpIDPG16hPvZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN48__T8opAssignTC3std11concurrency14LinkTerminatedZ8opAssignMFC3std11concurrency14LinkTerminatedZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN49__T8opAssignTC3std11concurrency15OwnerTerminatedZ8opAssignMFC3std11concurrency15OwnerTerminatedZS3std7variant18__T8VariantNVki16Z8VariantN@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN4typeMxFNbNdNeZC8TypeInfo@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN53__T5opCmpTS3std7variant18__T8VariantNVki16Z8VariantNZ5opCmpMFS3std7variant18__T8VariantNVki16Z8VariantNZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN56__T8opEqualsTS3std7variant18__T8VariantNVki16Z8VariantNZ8opEqualsMxFKS3std7variant18__T8VariantNVki16Z8VariantNZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN57__T8opEqualsTxS3std7variant18__T8VariantNVki16Z8VariantNZ8opEqualsMxFKxS3std7variant18__T8VariantNVki16Z8VariantNZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN5opCmpMxFKxS3std7variant18__T8VariantNVki16Z8VariantNZi@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN6__dtorMFZv@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN6__initZ@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN6lengthMFNdZk@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN6toHashMxFNbNfZk@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN8hasValueMxFNaNbNdNiNfZb@Base 6.2.1-1ubuntu2
+ _D3std7variant18__T8VariantNVki16Z8VariantN8toStringMFZAya@Base 6.2.1-1ubuntu2
+ _D3std7windows7charset12__ModuleInfoZ@Base 6
+ _D3std7windows8iunknown12__ModuleInfoZ@Base 6
+ _D3std7windows8registry12__ModuleInfoZ@Base 6
+ _D3std7windows8syserror12__ModuleInfoZ@Base 6
+ _D3std8bitmanip10myToStringFmZAya@Base 6
+ _D3std8bitmanip11myToStringxFmZAya@Base 6
+ _D3std8bitmanip12__ModuleInfoZ@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet4saveMFNaNbNdNiNfZS3std8bitmanip14__T7BitsSetTkZ7BitsSet@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet5frontMFNaNbNdNiNfZk@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet6__ctorMFNaNbNcNiNfkkZS3std8bitmanip14__T7BitsSetTkZ7BitsSet@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet6__initZ@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std8bitmanip14__T7BitsSetTkZ7BitsSet8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNekZk@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNemZm@Base 6
+ _D3std8bitmanip14swapEndianImplFNaNbNiNftZt@Base 6
+ _D3std8bitmanip15getBitsForAlignFmZm@Base 6
+ _D3std8bitmanip18__T10swapEndianTaZ10swapEndianFNaNbNiNfaZa@Base 6
+ _D3std8bitmanip18__T10swapEndianTbZ10swapEndianFNaNbNiNfbZb@Base 6
+ _D3std8bitmanip18__T10swapEndianThZ10swapEndianFNaNbNiNfhZh@Base 6
+ _D3std8bitmanip18__T10swapEndianTiZ10swapEndianFNaNbNiNfiZi@Base 6
+ _D3std8bitmanip18__T10swapEndianTlZ10swapEndianFNaNbNiNflZl@Base 6
+ _D3std8bitmanip18__T10swapEndianTmZ10swapEndianFNaNbNiNfmZm@Base 6
+ _D3std8bitmanip20__T12countBitsSetTkZ12countBitsSetFNaNbNiNfkZk@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTaZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTbZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperThZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTiZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTkZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTlZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTmZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip21__T13EndianSwapperTtZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip22__T13EndianSwapperTxkZ13EndianSwapper6__initZ@Base 6
+ _D3std8bitmanip26__T18countTrailingZerosTkZ18countTrailingZerosFNaNbNiNfkZk@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTkZ20nativeToLittleEndianFNaNbNiNfkZG4h@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTmZ20nativeToLittleEndianFNaNbNiNfmZG8h@Base 6
+ _D3std8bitmanip28__T20nativeToLittleEndianTtZ20nativeToLittleEndianFNaNbNiNftZG2h@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTaVki1Z17bigEndianToNativeFNaNbNiNfG1hZa@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTbVki1Z17bigEndianToNativeFNaNbNiNfG1hZb@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeThVki1Z17bigEndianToNativeFNaNbNiNfG1hZh@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTiVki4Z17bigEndianToNativeFNaNbNiNfG4hZi@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTlVki8Z17bigEndianToNativeFNaNbNiNfG8hZl@Base 6
+ _D3std8bitmanip29__T17bigEndianToNativeTmVki8Z17bigEndianToNativeFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip29__T20nativeToLittleEndianTxkZ20nativeToLittleEndianFNaNbNiNfxkZG4h@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTkVki4Z20littleEndianToNativeFNaNbNiNfG4hZk@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTmVki8Z20littleEndianToNativeFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip32__T20littleEndianToNativeTtVki2Z20littleEndianToNativeFNaNbNiNfG2hZt@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTkZ24nativeToLittleEndianImplFNaNbNiNfkZG4h@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTmZ24nativeToLittleEndianImplFNaNbNiNfmZG8h@Base 6
+ _D3std8bitmanip32__T24nativeToLittleEndianImplTtZ24nativeToLittleEndianImplFNaNbNiNftZG2h@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTaVki1Z21bigEndianToNativeImplFNaNbNiNfG1hZa@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTbVki1Z21bigEndianToNativeImplFNaNbNiNfG1hZb@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplThVki1Z21bigEndianToNativeImplFNaNbNiNfG1hZh@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTiVki4Z21bigEndianToNativeImplFNaNbNiNfG4hZi@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTlVki8Z21bigEndianToNativeImplFNaNbNiNfG8hZl@Base 6
+ _D3std8bitmanip33__T21bigEndianToNativeImplTmVki8Z21bigEndianToNativeImplFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip33__T24nativeToLittleEndianImplTxkZ24nativeToLittleEndianImplFNaNbNiNfxkZG4h@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTkVki4Z24littleEndianToNativeImplFNaNbNiNfG4hZk@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTmVki8Z24littleEndianToNativeImplFNaNbNiNfG8hZm@Base 6
+ _D3std8bitmanip36__T24littleEndianToNativeImplTtVki2Z24littleEndianToNativeImplFNaNbNiNfG2hZt@Base 6
+ _D3std8bitmanip8BitArray11opCatAssignMFNaNbS3std8bitmanip8BitArrayZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray11opCatAssignMFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray13opIndexAssignMFNaNbNibkZb@Base 6
+ _D3std8bitmanip8BitArray14formatBitArrayMxFMDFAxaZvZv@Base 6
+ _D3std8bitmanip8BitArray15formatBitStringMxFMDFAxaZvZv@Base 6
+ _D3std8bitmanip8BitArray3dimMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray3dupMxFNaNbNdZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray4initMFNaNbAbZv@Base 6
+ _D3std8bitmanip8BitArray4initMFNaNbAvkZv@Base 6
+ _D3std8bitmanip8BitArray4sortMFNaNbNdNiZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCatMxFNaNbS3std8bitmanip8BitArrayZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCatMxFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray5opCmpMxFNaNbNiS3std8bitmanip8BitArrayZi@Base 6
+ _D3std8bitmanip8BitArray5opComMxFNaNbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNaNbNcAbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNaNbNcAvkZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__ctorMFNckPkZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray6__initZ@Base 6
+ _D3std8bitmanip8BitArray6lengthMFNaNbNdkZk@Base 6
+ _D3std8bitmanip8BitArray6lengthMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray6toHashMxFNaNbNiZk@Base 6
+ _D3std8bitmanip8BitArray7bitsSetMxFNaNbNdZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std8bitmanip8BitArray7endBitsMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray7endMaskMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8BitArray7opApplyMFMDFKbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMFMDFkKbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMxFMDFbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opApplyMxFMDFkbZiZi@Base 6
+ _D3std8bitmanip8BitArray7opCat_rMxFNaNbbZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray7opIndexMxFNaNbNikZb@Base 6
+ _D3std8bitmanip8BitArray7reverseMFNaNbNdNiZS3std8bitmanip8BitArray@Base 6
+ _D3std8bitmanip8BitArray8lenToDimFNaNbNikZk@Base 6
+ _D3std8bitmanip8BitArray8opEqualsMxFNaNbNiKxS3std8bitmanip8BitArrayZb@Base 6
+ _D3std8bitmanip8BitArray8toStringMxFMDFAxaZvS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std8bitmanip8BitArray9fullWordsMxFNaNbNdNiZk@Base 6
+ _D3std8bitmanip8FloatRep11__xopEqualsFKxS3std8bitmanip8FloatRepKxS3std8bitmanip8FloatRepZb@Base 6
+ _D3std8bitmanip8FloatRep4signMFNaNbNdNiNfbZv@Base 6
+ _D3std8bitmanip8FloatRep4signMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip8FloatRep6__initZ@Base 6
+ _D3std8bitmanip8FloatRep8exponentMFNaNbNdNiNfhZv@Base 6
+ _D3std8bitmanip8FloatRep8exponentMxFNaNbNdNiNfZh@Base 6
+ _D3std8bitmanip8FloatRep8fractionMFNaNbNdNiNfkZv@Base 6
+ _D3std8bitmanip8FloatRep8fractionMxFNaNbNdNiNfZk@Base 6
+ _D3std8bitmanip8FloatRep9__xtoHashFNbNeKxS3std8bitmanip8FloatRepZk@Base 6
+ _D3std8bitmanip9DoubleRep11__xopEqualsFKxS3std8bitmanip9DoubleRepKxS3std8bitmanip9DoubleRepZb@Base 6
+ _D3std8bitmanip9DoubleRep4signMFNaNbNdNiNfbZv@Base 6
+ _D3std8bitmanip9DoubleRep4signMxFNaNbNdNiNfZb@Base 6
+ _D3std8bitmanip9DoubleRep6__initZ@Base 6
+ _D3std8bitmanip9DoubleRep8exponentMFNaNbNdNiNftZv@Base 6
+ _D3std8bitmanip9DoubleRep8exponentMxFNaNbNdNiNfZt@Base 6
+ _D3std8bitmanip9DoubleRep8fractionMFNaNbNdNiNfmZv@Base 6
+ _D3std8bitmanip9DoubleRep8fractionMxFNaNbNdNiNfZm@Base 6
+ _D3std8bitmanip9DoubleRep9__xtoHashFNbNeKxS3std8bitmanip9DoubleRepZk@Base 6
+ _D3std8compiler12__ModuleInfoZ@Base 6
+ _D3std8compiler13version_majoryk@Base 6
+ _D3std8compiler13version_minoryk@Base 6
+ _D3std8compiler4nameyAa@Base 6
+ _D3std8compiler6vendoryE3std8compiler6Vendor@Base 6
+ _D3std8compiler7D_majoryk@Base 6
+ _D3std8compiler7D_minoryk@Base 6
+ _D3std8datetime11_monthNamesyG12Aa@Base 6
+ _D3std8datetime11lastDayLeapyG13i@Base 6
+ _D3std8datetime11setTZEnvVarFNbNeAyaZv@Base 6
+ _D3std8datetime11timeStringsyAAa@Base 6
+ _D3std8datetime12__ModuleInfoZ@Base 6
+ _D3std8datetime12cmpTimeUnitsFNaNfAyaAyaZi@Base 6
+ _D3std8datetime12getDayOfWeekFNaNbNfiZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime13PosixTimeZone10LeapSecond6__ctorMFNaNcNfliZS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone10TempTTInfo6__ctorMFNaNcNfibhZS3std8datetime13PosixTimeZone10TempTTInfo@Base 6
+ _D3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone10Transition6__ctorMFNaNcNflPyS3std8datetime13PosixTimeZone6TTInfoZS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime13PosixTimeZone11getTimeZoneFNeAyaAyaZyC3std8datetime13PosixTimeZone@Base 6
+ _D3std8datetime13PosixTimeZone14TempTransition6__ctorMFNaNcNflPyS3std8datetime13PosixTimeZone6TTInfoPS3std8datetime13PosixTimeZone14TransitionTypeZS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone14TransitionType6__ctorMFNaNcNfbbZS3std8datetime13PosixTimeZone14TransitionType@Base 6
+ _D3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTaZ7readValFNeKS3std5stdio4FileZa@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTbZ7readValFNeKS3std5stdio4FileZb@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValThZ7readValFNeKS3std5stdio4FileZh@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTiZ7readValFNeKS3std5stdio4FileZi@Base 6
+ _D3std8datetime13PosixTimeZone14__T7readValTlZ7readValFNeKS3std5stdio4FileZl@Base 6
+ _D3std8datetime13PosixTimeZone15__T7readValTAaZ7readValFNeKS3std5stdio4FilekZAa@Base 6
+ _D3std8datetime13PosixTimeZone15__T7readValTAhZ7readValFNeKS3std5stdio4FilekZAh@Base 6
+ _D3std8datetime13PosixTimeZone19_enforceValidTZFileFNaNfbkZv@Base 6
+ _D3std8datetime13PosixTimeZone19getInstalledTZNamesFNeAyaAyaZAAya@Base 6
+ _D3std8datetime13PosixTimeZone20calculateLeapSecondsMxFNaNbNflZi@Base 6
+ _D3std8datetime13PosixTimeZone54__T7readValTS3std8datetime13PosixTimeZone10TempTTInfoZ7readValFNfKS3std5stdio4FileZS3std8datetime13PosixTimeZone10TempTTInfo@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo11__xopEqualsFKxS3std8datetime13PosixTimeZone6TTInfoKxS3std8datetime13PosixTimeZone6TTInfoZb@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo6__ctorMyFNaNcNfxS3std8datetime13PosixTimeZone10TempTTInfoAyaZyS3std8datetime13PosixTimeZone6TTInfo@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone6TTInfo9__xtoHashFNbNeKxS3std8datetime13PosixTimeZone6TTInfoZk@Base 6
+ _D3std8datetime13PosixTimeZone6__ctorMyFNaNfyAS3std8datetime13PosixTimeZone10TransitionyAS3std8datetime13PosixTimeZone10LeapSecondAyaAyaAyabZyC3std8datetime13PosixTimeZone@Base 6
+ _D3std8datetime13PosixTimeZone6__initZ@Base 6
+ _D3std8datetime13PosixTimeZone6__vtblZ@Base 6
+ _D3std8datetime13PosixTimeZone6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime13PosixTimeZone7__ClassZ@Base 6
+ _D3std8datetime13PosixTimeZone7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime13PosixTimeZone7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime13clearTZEnvVarFNbNeZv@Base 6
+ _D3std8datetime13monthToStringFNaNfE3std8datetime5MonthZAya@Base 6
+ _D3std8datetime13monthsToMonthFNaNfiiZi@Base 6
+ _D3std8datetime14SimpleTimeZone11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime14SimpleTimeZone11toISOStringFNaNfS4core4time8DurationZAya@Base 6
+ _D3std8datetime14SimpleTimeZone11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime14SimpleTimeZone6__ctorMyFNaNfS4core4time8DurationAyaZyC3std8datetime14SimpleTimeZone@Base 6
+ _D3std8datetime14SimpleTimeZone6__ctorMyFNaNfiAyaZyC3std8datetime14SimpleTimeZone@Base 6
+ _D3std8datetime14SimpleTimeZone6__initZ@Base 6
+ _D3std8datetime14SimpleTimeZone6__vtblZ@Base 6
+ _D3std8datetime14SimpleTimeZone6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime14SimpleTimeZone7__ClassZ@Base 6
+ _D3std8datetime14SimpleTimeZone7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime14SimpleTimeZone7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime14SimpleTimeZone9utcOffsetMxFNaNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime14lastDayNonLeapyG13i@Base 6
+ _D3std8datetime14validTimeUnitsFNaNbNfAAyaXb@Base 6
+ _D3std8datetime14yearIsLeapYearFNaNbNfiZb@Base 6
+ _D3std8datetime15daysToDayOfWeekFNaNbNfE3std8datetime9DayOfWeekE3std8datetime9DayOfWeekZi@Base 6
+ _D3std8datetime15monthFromStringFNaNfAyaZE3std8datetime5Month@Base 6
+ _D3std8datetime16cmpTimeUnitsCTFEFNaNbNfAyaAyaZi@Base 6
+ _D3std8datetime17stdTimeToUnixTimeFNaNbNflZi@Base 6
+ _D3std8datetime17unixTimeToStdTimeFNaNbNfiZl@Base 6
+ _D3std8datetime19fracSecsToISOStringFNaNbNfiZAya@Base 6
+ _D3std8datetime20DosFileTimeToSysTimeFNfkyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime20SysTimeToDosFileTimeFNfS3std8datetime7SysTimeZk@Base 6
+ _D3std8datetime24ComparingBenchmarkResult10targetTimeMxFNaNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime24ComparingBenchmarkResult5pointMxFNaNbNdNfZe@Base 6
+ _D3std8datetime24ComparingBenchmarkResult6__ctorMFNaNbNcNfS4core4time12TickDurationS4core4time12TickDurationZS3std8datetime24ComparingBenchmarkResult@Base 6
+ _D3std8datetime24ComparingBenchmarkResult6__initZ@Base 6
+ _D3std8datetime24ComparingBenchmarkResult8baseTimeMxFNaNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime25__T5validVAyaa4_64617973Z5validFNaNbNfiiiZb@Base 6
+ _D3std8datetime27__T5validVAyaa5_686f757273Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime29__T5validVAyaa6_6d6f6e746873Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime29tzDatabaseNameToWindowsTZNameFNaNbNiNfAyaZAya@Base 6
+ _D3std8datetime29windowsTZNameToTZDatabaseNameFNaNbNiNfAyaZAya@Base 6
+ _D3std8datetime31__T5validVAyaa7_6d696e75746573Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime31__T5validVAyaa7_7365636f6e6473Z5validFNaNbNiNfiZb@Base 6
+ _D3std8datetime33__T12enforceValidVAyaa4_64617973Z12enforceValidFNaNfiE3std8datetime5MonthiAyakZv@Base 6
+ _D3std8datetime35__T12enforceValidVAyaa5_686f757273Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime37__T12enforceValidVAyaa6_6d6f6e746873Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime39__T12enforceValidVAyaa7_6d696e75746573Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime39__T12enforceValidVAyaa7_7365636f6e6473Z12enforceValidFNaNfiAyakZv@Base 6
+ _D3std8datetime39__T18getUnitsFromHNSecsVAyaa4_64617973Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime3UTC11dstInEffectMxFNbNflZb@Base 6
+ _D3std8datetime3UTC11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime3UTC4_utcyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC6__ctorMyFNaNfZyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC6__initZ@Base 6
+ _D3std8datetime3UTC6__vtblZ@Base 6
+ _D3std8datetime3UTC6hasDSTMxFNbNdNfZb@Base 6
+ _D3std8datetime3UTC6opCallFNaNbNfZyC3std8datetime3UTC@Base 6
+ _D3std8datetime3UTC7__ClassZ@Base 6
+ _D3std8datetime3UTC7tzToUTCMxFNbNflZl@Base 6
+ _D3std8datetime3UTC7utcToTZMxFNbNflZl@Base 6
+ _D3std8datetime41__T18getUnitsFromHNSecsVAyaa5_686f757273Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime41__T20splitUnitsFromHNSecsVAyaa4_64617973Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime42__T21removeUnitsFromHNSecsVAyaa4_64617973Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime44__T21removeUnitsFromHNSecsVAyaa5_686f757273Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime45__T18getUnitsFromHNSecsVAyaa7_6d696e75746573Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D3std8datetime48__T21removeUnitsFromHNSecsVAyaa7_6d696e75746573Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime48__T21removeUnitsFromHNSecsVAyaa7_7365636f6e6473Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D3std8datetime4Date10diffMonthsMxFNaNbNfxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date10endOfMonthMxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date10isLeapYearMxFNaNbNdNfZb@Base 6
+ _D3std8datetime4Date11__invariantMxFNaNfZv@Base 6
+ _D3std8datetime4Date11daysInMonthMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date12modJulianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime4Date14__invariant173MxFNaNfZv@Base 6
+ _D3std8datetime4Date14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date14toSimpleStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date17dayOfGregorianCalMFNaNbNdNfiZv@Base 6
+ _D3std8datetime4Date17dayOfGregorianCalMxFNaNbNdNfZi@Base 6
+ _D3std8datetime4Date22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNfxS3std8datetime4DateZS4core4time8Duration@Base 6
+ _D3std8datetime4Date3dayMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date3dayMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date3maxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date3minFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date4isADMxFNaNbNdNfZb@Base 6
+ _D3std8datetime4Date4yearMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date4yearMxFNaNbNdNfZs@Base 6
+ _D3std8datetime4Date5monthMFNaNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime4Date5monthMxFNaNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime4Date5opCmpMxFNaNbNfxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date6__ctorMFNaNbNcNfiZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date6__ctorMFNaNcNfiiiZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date6__initZ@Base 6
+ _D3std8datetime4Date6_validFNaNbNfiiiZb@Base 6
+ _D3std8datetime4Date6yearBCMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date6yearBCMxFNaNdNfZt@Base 6
+ _D3std8datetime4Date7isoWeekMxFNaNbNdNfZh@Base 6
+ _D3std8datetime4Date8__xopCmpFKxS3std8datetime4DateKxS3std8datetime4DateZi@Base 6
+ _D3std8datetime4Date8_addDaysMFNaNbNcNjNflZS3std8datetime4Date@Base 6
+ _D3std8datetime4Date8toStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime4Date9dayOfWeekMxFNaNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime4Date9dayOfYearMFNaNdNfiZv@Base 6
+ _D3std8datetime4Date9dayOfYearMxFNaNbNdNfZt@Base 6
+ _D3std8datetime4Date9julianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime5Clock11currAppTickFNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime5Clock11currStdTimeFNdNeZl@Base 6
+ _D3std8datetime5Clock14currSystemTickFNbNdNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime5Clock6__ctorMFZC3std8datetime5Clock@Base 6
+ _D3std8datetime5Clock6__initZ@Base 6
+ _D3std8datetime5Clock6__vtblZ@Base 6
+ _D3std8datetime5Clock7__ClassZ@Base 6
+ _D3std8datetime5Clock8currTimeFNfyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime5Month6__initZ@Base 6
+ _D3std8datetime6maxDayFNaNbNfiiZh@Base 6
+ _D3std8datetime7SysTime10diffMonthsMxFNbNfxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime10endOfMonthMxFNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime10isLeapYearMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime10toUnixTimeMxFNaNbNfZi@Base 6
+ _D3std8datetime7SysTime11daysInMonthMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime11dstInEffectMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime11toISOStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime11toLocalTimeMxFNaNbNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime12modJulianDayMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime14toISOExtStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime14toSimpleStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime17dayOfGregorianCalMFNbNdNfiZv@Base 6
+ _D3std8datetime7SysTime17dayOfGregorianCalMxFNbNdNfZi@Base 6
+ _D3std8datetime7SysTime31__T6opCastTS3std8datetime4DateZ6opCastMxFNbNfZS3std8datetime4Date@Base 6
+ _D3std8datetime7SysTime35__T6opCastTS3std8datetime8DateTimeZ6opCastMxFNbNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime7SysTime3dayMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime3dayMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime3maxFNaNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime3minFNaNbNdNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime4hourMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime4hourMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime4isADMxFNbNdNfZb@Base 6
+ _D3std8datetime7SysTime4toTMMxFNbNfZS4core4stdc4time2tm@Base 6
+ _D3std8datetime7SysTime4yearMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime4yearMxFNbNdNfZs@Base 6
+ _D3std8datetime7SysTime5monthMFNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime7SysTime5monthMxFNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime7SysTime5opCmpMxFNaNbNfxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime5toUTCMxFNaNbNfZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNaNbNcNflyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNbNcNfxS3std8datetime4DateyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNbNcNfxS3std8datetime8DateTimeyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNcNfxS3std8datetime8DateTimexS4core4time7FracSecyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__ctorMFNcNfxS3std8datetime8DateTimexS4core4time8DurationyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime6__initZ@Base 6
+ _D3std8datetime7SysTime6minuteMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6minuteMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime6secondMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6secondMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime6yearBCMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime6yearBCMxFNdNfZt@Base 6
+ _D3std8datetime7SysTime7adjTimeMFNbNdNflZv@Base 6
+ _D3std8datetime7SysTime7adjTimeMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime7fracSecMFNdNfS4core4time7FracSecZv@Base 6
+ _D3std8datetime7SysTime7fracSecMxFNbNdNfZS4core4time7FracSec@Base 6
+ _D3std8datetime7SysTime7isoWeekMxFNbNdNfZh@Base 6
+ _D3std8datetime7SysTime7stdTimeMFNaNbNdNflZv@Base 6
+ _D3std8datetime7SysTime7stdTimeMxFNaNbNdNfZl@Base 6
+ _D3std8datetime7SysTime8__xopCmpFKxS3std8datetime7SysTimeKxS3std8datetime7SysTimeZi@Base 6
+ _D3std8datetime7SysTime8fracSecsMFNdNfS4core4time8DurationZv@Base 6
+ _D3std8datetime7SysTime8fracSecsMxFNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime7SysTime8opAssignMFNaNbNcNjNfKxS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime8opAssignMFNaNbNcNjNfS3std8datetime7SysTimeZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime8opEqualsMxFNaNbNfKxS3std8datetime7SysTimeZb@Base 6
+ _D3std8datetime7SysTime8opEqualsMxFNaNbNfxS3std8datetime7SysTimeZb@Base 6
+ _D3std8datetime7SysTime8timezoneMFNaNbNdNfyC3std8datetime8TimeZoneZv@Base 6
+ _D3std8datetime7SysTime8timezoneMxFNaNbNdNfZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime7SysTime8toStringMxFNbNfZAya@Base 6
+ _D3std8datetime7SysTime9__xtoHashFNbNeKxS3std8datetime7SysTimeZk@Base 6
+ _D3std8datetime7SysTime9dayOfWeekMxFNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime7SysTime9dayOfYearMFNdNfiZv@Base 6
+ _D3std8datetime7SysTime9dayOfYearMxFNbNdNfZt@Base 6
+ _D3std8datetime7SysTime9julianDayMxFNbNdNfZl@Base 6
+ _D3std8datetime7SysTime9toOtherTZMxFNaNbNfyC3std8datetime8TimeZoneZS3std8datetime7SysTime@Base 6
+ _D3std8datetime7SysTime9toTimeValMxFNaNbNfZS4core3sys5posix3sys4time7timeval@Base 6
+ _D3std8datetime7SysTime9utcOffsetMxFNbNdNfZS4core4time8Duration@Base 6
+ _D3std8datetime8DateTime10diffMonthsMxFNaNbNfxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime10endOfMonthMxFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime10isLeapYearMxFNaNbNdNfZb@Base 6
+ _D3std8datetime8DateTime11_addSecondsMFNaNbNcNjNflZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime11daysInMonthMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime12modJulianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime8DateTime14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime14toSimpleStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime17dayOfGregorianCalMFNaNbNdNfiZv@Base 6
+ _D3std8datetime8DateTime17dayOfGregorianCalMxFNaNbNdNfZi@Base 6
+ _D3std8datetime8DateTime3dayMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime3dayMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime3maxFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime3minFNaNbNdNfZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime4dateMFNaNbNdNfxS3std8datetime4DateZv@Base 6
+ _D3std8datetime8DateTime4dateMxFNaNbNdNfZS3std8datetime4Date@Base 6
+ _D3std8datetime8DateTime4hourMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime4hourMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime4isADMxFNaNbNdNfZb@Base 6
+ _D3std8datetime8DateTime4yearMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime4yearMxFNaNbNdNfZs@Base 6
+ _D3std8datetime8DateTime5monthMFNaNdNfE3std8datetime5MonthZv@Base 6
+ _D3std8datetime8DateTime5monthMxFNaNbNdNfZE3std8datetime5Month@Base 6
+ _D3std8datetime8DateTime5opCmpMxFNaNbNfxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime6__ctorMFNaNbNcNfxS3std8datetime4DatexS3std8datetime9TimeOfDayZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime6__ctorMFNaNcNfiiiiiiZS3std8datetime8DateTime@Base 6
+ _D3std8datetime8DateTime6__initZ@Base 6
+ _D3std8datetime8DateTime6minuteMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6minuteMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime6secondMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6secondMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime6yearBCMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime6yearBCMxFNaNdNfZs@Base 6
+ _D3std8datetime8DateTime7isoWeekMxFNaNbNdNfZh@Base 6
+ _D3std8datetime8DateTime8__xopCmpFKxS3std8datetime8DateTimeKxS3std8datetime8DateTimeZi@Base 6
+ _D3std8datetime8DateTime8toStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime8DateTime9dayOfWeekMxFNaNbNdNfZE3std8datetime9DayOfWeek@Base 6
+ _D3std8datetime8DateTime9dayOfYearMFNaNdNfiZv@Base 6
+ _D3std8datetime8DateTime9dayOfYearMxFNaNbNdNfZt@Base 6
+ _D3std8datetime8DateTime9julianDayMxFNaNbNdNfZl@Base 6
+ _D3std8datetime8DateTime9timeOfDayMFNaNbNdNfxS3std8datetime9TimeOfDayZv@Base 6
+ _D3std8datetime8DateTime9timeOfDayMxFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime8TimeZone11_getOldNameFNaNbNfAyaZAya@Base 6
+ _D3std8datetime8TimeZone11getTimeZoneFNfAyaZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime8TimeZone11utcOffsetAtMxFNbNflZS4core4time8Duration@Base 6
+ _D3std8datetime8TimeZone19getInstalledTZNamesFNfAyaZAAya@Base 6
+ _D3std8datetime8TimeZone4nameMxFNbNdNfZAya@Base 6
+ _D3std8datetime8TimeZone6__ctorMyFNaNfAyaAyaAyaZyC3std8datetime8TimeZone@Base 6
+ _D3std8datetime8TimeZone6__initZ@Base 6
+ _D3std8datetime8TimeZone6__vtblZ@Base 6
+ _D3std8datetime8TimeZone7__ClassZ@Base 6
+ _D3std8datetime8TimeZone7dstNameMxFNbNdNfZAya@Base 6
+ _D3std8datetime8TimeZone7stdNameMxFNbNdNfZAya@Base 6
+ _D3std8datetime9LocalTime10_localTimeyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime11dstInEffectMxFNbNelZb@Base 6
+ _D3std8datetime9LocalTime15_tzsetWasCalledOb@Base 6
+ _D3std8datetime9LocalTime6__ctorMyFNaNfZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime6__initZ@Base 6
+ _D3std8datetime9LocalTime6__vtblZ@Base 6
+ _D3std8datetime9LocalTime6hasDSTMxFNbNdNeZb@Base 6
+ _D3std8datetime9LocalTime6opCallFNaNbNeZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9LocalTime7__ClassZ@Base 6
+ _D3std8datetime9LocalTime7dstNameMxFNbNdNeZAya@Base 6
+ _D3std8datetime9LocalTime7stdNameMxFNbNdNeZAya@Base 6
+ _D3std8datetime9LocalTime7tzToUTCMxFNbNelZl@Base 6
+ _D3std8datetime9LocalTime7utcToTZMxFNbNelZl@Base 6
+ _D3std8datetime9LocalTime8_lowLockb@Base 6
+ _D3std8datetime9LocalTime9singletonFNeZ13__critsec2792G28g@Base 6
+ _D3std8datetime9LocalTime9singletonFNeZyC3std8datetime9LocalTime@Base 6
+ _D3std8datetime9StopWatch11setMeasuredMFNfS4core4time12TickDurationZv@Base 6
+ _D3std8datetime9StopWatch4peekMxFNfZS4core4time12TickDuration@Base 6
+ _D3std8datetime9StopWatch4stopMFNfZv@Base 6
+ _D3std8datetime9StopWatch5resetMFNfZv@Base 6
+ _D3std8datetime9StopWatch5startMFNfZv@Base 6
+ _D3std8datetime9StopWatch6__ctorMFNcNfE3std8datetime9AutoStartZS3std8datetime9StopWatch@Base 6
+ _D3std8datetime9StopWatch6__initZ@Base 6
+ _D3std8datetime9StopWatch7runningMxFNaNbNdNfZb@Base 6
+ _D3std8datetime9StopWatch8opEqualsMxFNaNbNfKxS3std8datetime9StopWatchZb@Base 6
+ _D3std8datetime9StopWatch8opEqualsMxFNaNbNfxS3std8datetime9StopWatchZb@Base 6
+ _D3std8datetime9TimeOfDay11__invariantMxFNaNfZv@Base 6
+ _D3std8datetime9TimeOfDay11_addSecondsMFNaNbNcNjNflZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay11toISOStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime9TimeOfDay14__invariant201MxFNaNfZv@Base 6
+ _D3std8datetime9TimeOfDay14toISOExtStringMxFNaNbNfZAya@Base 6
+ _D3std8datetime9TimeOfDay22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfxS3std8datetime9TimeOfDayZS4core4time8Duration@Base 6
+ _D3std8datetime9TimeOfDay3maxFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay3minFNaNbNdNfZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay4hourMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay4hourMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay5opCmpMxFNaNbNfxS3std8datetime9TimeOfDayZi@Base 6
+ _D3std8datetime9TimeOfDay6__ctorMFNaNcNfiiiZS3std8datetime9TimeOfDay@Base 6
+ _D3std8datetime9TimeOfDay6__initZ@Base 6
+ _D3std8datetime9TimeOfDay6_validFNaNbNfiiiZb@Base 6
+ _D3std8datetime9TimeOfDay6minuteMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay6minuteMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay6secondMFNaNdNfiZv@Base 6
+ _D3std8datetime9TimeOfDay6secondMxFNaNbNdNfZh@Base 6
+ _D3std8datetime9TimeOfDay8__xopCmpFKxS3std8datetime9TimeOfDayKxS3std8datetime9TimeOfDayZi@Base 6
+ _D3std8datetime9TimeOfDay8toStringMxFNaNbNfZAya@Base 6
+ _D3std8demangle12__ModuleInfoZ@Base 6
+ _D3std8demangle8demangleFAyaZAya@Base 6
+ _D3std8encoding12__ModuleInfoZ@Base 6
+ _D3std8encoding13__T6encodeTaZ6encodeFwAaZk@Base 6
+ _D3std8encoding13__T6encodeTuZ6encodeFwAuZk@Base 6
+ _D3std8encoding13__T6encodeTwZ6encodeFwAwZk@Base 6
+ _D3std8encoding14EncodingScheme11validLengthMFAxhZk@Base 6
+ _D3std8encoding14EncodingScheme13firstSequenceMFAxhZk@Base 6
+ _D3std8encoding14EncodingScheme5countMFAxhZk@Base 6
+ _D3std8encoding14EncodingScheme5indexMFAxhkZi@Base 6
+ _D3std8encoding14EncodingScheme6__initZ@Base 6
+ _D3std8encoding14EncodingScheme6__vtblZ@Base 6
+ _D3std8encoding14EncodingScheme6createFAyaZC3std8encoding14EncodingScheme@Base 6
+ _D3std8encoding14EncodingScheme7__ClassZ@Base 6
+ _D3std8encoding14EncodingScheme7isValidMFAxhZb@Base 6
+ _D3std8encoding14EncodingScheme8registerFAyaZv@Base 6
+ _D3std8encoding14EncodingScheme8sanitizeMFAyhZAyh@Base 6
+ _D3std8encoding14EncodingScheme9supportedHAyaAya@Base 6
+ _D3std8encoding14__T7isValidTaZ7isValidFAxaZb@Base 6
+ _D3std8encoding15__T6decodeTAxaZ6decodeFKAxaZw@Base 6
+ _D3std8encoding15__T6decodeTAxuZ6decodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding15__T6decodeTAxwZ6decodeFNbKAxwZw@Base 6
+ _D3std8encoding16__T9canEncodeTaZ9canEncodeFwZb@Base 6
+ _D3std8encoding16__T9canEncodeTuZ9canEncodeFwZb@Base 6
+ _D3std8encoding16__T9canEncodeTwZ9canEncodeFwZb@Base 6
+ _D3std8encoding16isValidCodePointFwZb@Base 6
+ _D3std8encoding17EncodingException6__ctorMFAyaZC3std8encoding17EncodingException@Base 6
+ _D3std8encoding17EncodingException6__initZ@Base 6
+ _D3std8encoding17EncodingException6__vtblZ@Base 6
+ _D3std8encoding17EncodingException7__ClassZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf810safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding18EncodingSchemeUtf813encodedLengthMxFwZk@Base 6
+ _D3std8encoding18EncodingSchemeUtf819_sharedStaticCtor18FZv@Base 6
+ _D3std8encoding18EncodingSchemeUtf819replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding18EncodingSchemeUtf85namesMxFZAAya@Base 6
+ _D3std8encoding18EncodingSchemeUtf86__initZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf86__vtblZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf86decodeMxFKAxhZw@Base 6
+ _D3std8encoding18EncodingSchemeUtf86encodeMxFwAhZk@Base 6
+ _D3std8encoding18EncodingSchemeUtf87__ClassZ@Base 6
+ _D3std8encoding18EncodingSchemeUtf88toStringMxFZAya@Base 6
+ _D3std8encoding18EncodingSchemeUtf89canEncodeMxFwZb@Base 6
+ _D3std8encoding18__T9transcodeTaTwZ9transcodeFAyaJAywZv@Base 6
+ _D3std8encoding19EncodingSchemeASCII10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding19EncodingSchemeASCII13encodedLengthMxFwZk@Base 6
+ _D3std8encoding19EncodingSchemeASCII19_sharedStaticCtor15FZv@Base 6
+ _D3std8encoding19EncodingSchemeASCII19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding19EncodingSchemeASCII5namesMxFZAAya@Base 6
+ _D3std8encoding19EncodingSchemeASCII6__initZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII6__vtblZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII6decodeMxFKAxhZw@Base 6
+ _D3std8encoding19EncodingSchemeASCII6encodeMxFwAhZk@Base 6
+ _D3std8encoding19EncodingSchemeASCII7__ClassZ@Base 6
+ _D3std8encoding19EncodingSchemeASCII8toStringMxFZAya@Base 6
+ _D3std8encoding19EncodingSchemeASCII9canEncodeMxFwZb@Base 6
+ _D3std8encoding19__T11validLengthTaZ11validLengthFAxaZk@Base 6
+ _D3std8encoding20EncodingSchemeLatin110safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding20EncodingSchemeLatin113encodedLengthMxFwZk@Base 6
+ _D3std8encoding20EncodingSchemeLatin119_sharedStaticCtor16FZv@Base 6
+ _D3std8encoding20EncodingSchemeLatin119replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding20EncodingSchemeLatin15namesMxFZAAya@Base 6
+ _D3std8encoding20EncodingSchemeLatin16__initZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin16__vtblZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin16decodeMxFKAxhZw@Base 6
+ _D3std8encoding20EncodingSchemeLatin16encodeMxFwAhZk@Base 6
+ _D3std8encoding20EncodingSchemeLatin17__ClassZ@Base 6
+ _D3std8encoding20EncodingSchemeLatin18toStringMxFZAya@Base 6
+ _D3std8encoding20EncodingSchemeLatin19canEncodeMxFwZb@Base 6
+ _D3std8encoding20__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding20__T10safeDecodeTAxuZ10safeDecodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding20__T10safeDecodeTAxwZ10safeDecodeFKAxwZw@Base 6
+ _D3std8encoding21__T13encodedLengthTaZ13encodedLengthFwZk@Base 6
+ _D3std8encoding21__T13encodedLengthTuZ13encodedLengthFwZk@Base 6
+ _D3std8encoding21__T13encodedLengthTwZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ15isValidCodeUnitFaZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ19replacementSequenceFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ5tailsFaZi@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin1513decodeReverseFKAxaZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin1520__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin154skipFKAxaZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwDFaZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwKAaZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9__mixin156encodeFwZAa@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9canEncodeFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTaZ9tailTableyG128h@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ15isValidCodeUnitFuZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ19replacementSequenceFNdZAyu@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin1313decodeReverseFKAxuZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin134skipFKAxuZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwDFuZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwKAuZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9__mixin136encodeFwZAu@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTuZ9canEncodeFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ13encodedLengthFwZk@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ15isValidCodeUnitFwZb@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ19replacementSequenceFNdZAyw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin1313decodeReverseFKAxwZw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin134skipFKAxwZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwDFwZvZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwKAwZv@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9__mixin136encodeFwZAw@Base 6
+ _D3std8encoding24__T15EncoderInstanceHTwZ9canEncodeFwZb@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native13encodedLengthMxFwZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native19_sharedStaticCtor19FZv@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native5namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6__initZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native6encodeMxFwAhZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native7__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native8toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf16Native9canEncodeMxFwZb@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native10safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native13encodedLengthMxFwZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native19_sharedStaticCtor21FZv@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native19replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native5namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6__initZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native6encodeMxFwAhZk@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native7__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native8toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeUtf32Native9canEncodeMxFwZb@Base 6
+ _D3std8encoding25EncodingSchemeWindows125210safeDecodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeWindows125213encodedLengthMxFwZk@Base 6
+ _D3std8encoding25EncodingSchemeWindows125219_sharedStaticCtor17FZv@Base 6
+ _D3std8encoding25EncodingSchemeWindows125219replacementSequenceMxFNdZAyh@Base 6
+ _D3std8encoding25EncodingSchemeWindows12525namesMxFZAAya@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526__initZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526__vtblZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526decodeMxFKAxhZw@Base 6
+ _D3std8encoding25EncodingSchemeWindows12526encodeMxFwAhZk@Base 6
+ _D3std8encoding25EncodingSchemeWindows12527__ClassZ@Base 6
+ _D3std8encoding25EncodingSchemeWindows12528toStringMxFZAya@Base 6
+ _D3std8encoding25EncodingSchemeWindows12529canEncodeMxFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ13encodedLengthFwZk@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ15isValidCodeUnitFaZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ19replacementSequenceFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ5tailsFaZi@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1513decodeReverseFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1515__T6decodeTAxaZ6decodeFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin1520__T10safeDecodeTAxaZ10safeDecodeFKAxaZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin154skipFKAxaZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwDFaZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwKAaZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9__mixin156encodeFwZAa@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9canEncodeFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxaZ9tailTableyG128h@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ13encodedLengthFwZk@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ15isValidCodeUnitFuZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ19replacementSequenceFNdZAyu@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1313decodeReverseFKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1315__T6decodeTAxuZ6decodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin1320__T10safeDecodeTAxuZ10safeDecodeFNaNbNiNfKAxuZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin134skipFKAxuZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwDFuZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwKAuZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9__mixin136encodeFwZAu@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxuZ9canEncodeFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ13encodedLengthFwZk@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ15isValidCodeUnitFwZb@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ19replacementSequenceFNdZAyw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1313decodeReverseFKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1315__T6decodeTAxwZ6decodeFNaNbNiNfKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin1320__T10safeDecodeTAxwZ10safeDecodeFKAxwZw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin134skipFKAxwZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwDFwZvZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwKAwZv@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9__mixin136encodeFwZAw@Base 6
+ _D3std8encoding25__T15EncoderInstanceHTxwZ9canEncodeFwZb@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__ctorMFAyaZC3std8encoding29UnrecognizedEncodingException@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__initZ@Base 6
+ _D3std8encoding29UnrecognizedEncodingException6__vtblZ@Base 6
+ _D3std8encoding29UnrecognizedEncodingException7__ClassZ@Base 6
+ _D3std8encoding36__T6encodeTE3std8encoding9AsciiCharZ6encodeFwAE3std8encoding9AsciiCharZk@Base 6
+ _D3std8encoding38__T6decodeTAxE3std8encoding9AsciiCharZ6decodeFNbKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding38__T6encodeTE3std8encoding10Latin1CharZ6encodeFwAE3std8encoding10Latin1CharZk@Base 6
+ _D3std8encoding39__T9canEncodeTE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding40__T6decodeTAxE3std8encoding10Latin1CharZ6decodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding41__T9canEncodeTE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding43__T10safeDecodeTAxE3std8encoding9AsciiCharZ10safeDecodeFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding43__T6encodeTE3std8encoding15Windows1252CharZ6encodeFwAE3std8encoding15Windows1252CharZk@Base 6
+ _D3std8encoding44__T13encodedLengthTE3std8encoding9AsciiCharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding45__T10safeDecodeTAxE3std8encoding10Latin1CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding45__T6decodeTAxE3std8encoding15Windows1252CharZ6decodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding46__T13encodedLengthTE3std8encoding10Latin1CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding46__T9canEncodeTE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ15isValidCodeUnitFE3std8encoding9AsciiCharZb@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ19replacementSequenceFNdZAyE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin1413decodeReverseFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin144skipFKAxE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwDFE3std8encoding9AsciiCharZvZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwKAE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9__mixin146encodeFwZAE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding47__T15EncoderInstanceHTE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ15isValidCodeUnitFE3std8encoding9AsciiCharZb@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ19replacementSequenceFNdZAyE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1413decodeReverseFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1438__T6decodeTAxE3std8encoding9AsciiCharZ6decodeFNaNbNiNfKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin1443__T10safeDecodeTAxE3std8encoding9AsciiCharZ10safeDecodeFKAxE3std8encoding9AsciiCharZw@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin144skipFKAxE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwDFE3std8encoding9AsciiCharZvZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwKAE3std8encoding9AsciiCharZv@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9__mixin146encodeFwZAE3std8encoding9AsciiChar@Base 6
+ _D3std8encoding48__T15EncoderInstanceHTxE3std8encoding9AsciiCharZ9canEncodeFwZb@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ15isValidCodeUnitFE3std8encoding10Latin1CharZb@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ19replacementSequenceFNdZAyE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin1313decodeReverseFKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin134skipFKAxE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwDFE3std8encoding10Latin1CharZvZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwKAE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9__mixin136encodeFwZAE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding49__T15EncoderInstanceHTE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding50__T10safeDecodeTAxE3std8encoding15Windows1252CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ15isValidCodeUnitFE3std8encoding10Latin1CharZb@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ19replacementSequenceFNdZAyE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1313decodeReverseFKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1340__T6decodeTAxE3std8encoding10Latin1CharZ6decodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin1345__T10safeDecodeTAxE3std8encoding10Latin1CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding10Latin1CharZw@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin134skipFKAxE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwDFE3std8encoding10Latin1CharZvZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwKAE3std8encoding10Latin1CharZv@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9__mixin136encodeFwZAE3std8encoding10Latin1Char@Base 6
+ _D3std8encoding50__T15EncoderInstanceHTxE3std8encoding10Latin1CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding51__T13encodedLengthTE3std8encoding15Windows1252CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ15isValidCodeUnitFE3std8encoding15Windows1252CharZb@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ19replacementSequenceFNdZAyE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ7charMapyAu@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin1413decodeReverseFKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin144skipFKAxE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwDFE3std8encoding15Windows1252CharZvZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwKAE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9__mixin146encodeFwZAE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding54__T15EncoderInstanceHTE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ12encodingNameFNdZAya@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ13encodedLengthFwZk@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ15isValidCodeUnitFE3std8encoding15Windows1252CharZb@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ19replacementSequenceFNdZAyE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ7charMapyAu@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1413decodeReverseFKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1445__T6decodeTAxE3std8encoding15Windows1252CharZ6decodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin144skipFKAxE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin1450__T10safeDecodeTAxE3std8encoding15Windows1252CharZ10safeDecodeFNaNbNiNfKAxE3std8encoding15Windows1252CharZw@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwDFE3std8encoding15Windows1252CharZvZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwKAE3std8encoding15Windows1252CharZv@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9__mixin146encodeFwZAE3std8encoding15Windows1252Char@Base 6
+ _D3std8encoding55__T15EncoderInstanceHTxE3std8encoding15Windows1252CharZ9canEncodeFwZb@Base 6
+ _D3std8internal11processinit12__ModuleInfoZ@Base 6
+ _D3std8internal11scopebuffer12__ModuleInfoZ@Base 6
+ _D3std8internal12unicode_comp12__ModuleInfoZ@Base 6
+ _D3std8internal12unicode_comp16compositionTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std8internal12unicode_comp16compositionTableFNaNbNdNiNfZyAS3std8internal14unicode_tables9CompEntry@Base 6
+ _D3std8internal12unicode_norm12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_decomp12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_decomp16decompCanonTableFNaNbNdNiNfZ1tyAw@Base 6
+ _D3std8internal14unicode_decomp16decompCanonTableFNaNbNdNiNfZyAw@Base 6
+ _D3std8internal14unicode_decomp17decompCompatTableFNaNbNdNiNfZ1tyAw@Base 6
+ _D3std8internal14unicode_decomp17decompCompatTableFNaNbNdNiNfZyAw@Base 6
+ _D3std8internal14unicode_tables10isSpaceGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables10isWhiteGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables11isFormatGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables12__ModuleInfoZ@Base 6
+ _D3std8internal14unicode_tables12isControlGenFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables12toLowerTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toLowerTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables12toTitleTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toTitleTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables12toUpperTableFNaNbNdNiNfZ1tyAk@Base 6
+ _D3std8internal14unicode_tables12toUpperTableFNaNbNdNiNfZyAk@Base 6
+ _D3std8internal14unicode_tables13FullCaseEntry5valueMxFNaNbNdNiNjNeZAxw@Base 6
+ _D3std8internal14unicode_tables13FullCaseEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables13fullCaseTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables13FullCaseEntry@Base 6
+ _D3std8internal14unicode_tables13fullCaseTableFNaNbNdNiNfZyAS3std8internal14unicode_tables13FullCaseEntry@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry4sizeMxFNaNbNdNiNfZh@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry7isLowerMxFNaNbNdNiNfZi@Base 6
+ _D3std8internal14unicode_tables15SimpleCaseEntry7isUpperMxFNaNbNdNiNfZi@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty11__xopEqualsFKxS3std8internal14unicode_tables15UnicodePropertyKxS3std8internal14unicode_tables15UnicodePropertyZb@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D3std8internal14unicode_tables15UnicodeProperty9__xtoHashFNbNeKxS3std8internal14unicode_tables15UnicodePropertyZk@Base 6
+ _D3std8internal14unicode_tables15simpleCaseTableFNaNbNdNiNfZ1tyAS3std8internal14unicode_tables15SimpleCaseEntry@Base 6
+ _D3std8internal14unicode_tables15simpleCaseTableFNaNbNdNiNfZyAS3std8internal14unicode_tables15SimpleCaseEntry@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry11__xopEqualsFKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZb@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry6__initZ@Base 6
+ _D3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry9__xtoHashFNbNeKxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZk@Base 6
+ _D3std8internal14unicode_tables6blocks10DevanagariyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10GlagoliticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10KharoshthiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10Old_ItalicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10Old_TurkicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10PhoenicianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks10SaurashtrayAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Basic_LatinyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Box_DrawingyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11CJK_StrokesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Hangul_JamoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11New_Tai_LueyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Old_PersianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks11Yi_RadicalsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Domino_TilesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Meetei_MayekyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Number_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Sora_SompengyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Syloti_NagriyAh@Base 6
+ _D3std8internal14unicode_tables6blocks12Yi_SyllablesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Khmer_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Mahjong_TilesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Phaistos_DiscyAh@Base 6
+ _D3std8internal14unicode_tables6blocks13Playing_CardsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Aegean_NumbersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Block_ElementsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Greek_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14IPA_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Low_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks14Vertical_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Ancient_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15High_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Kana_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Kangxi_RadicalsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks15Musical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Bamum_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Braille_PatternsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Control_PicturesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Currency_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Geometric_ShapesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Greek_and_CopticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Hangul_SyllablesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Imperial_AramaicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_CyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Latin_Extended_DyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Meroitic_CursiveyAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Private_Use_AreayAh@Base 6
+ _D3std8internal14unicode_tables6blocks16Vedic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Arabic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Arabic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Bopomofo_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17CJK_CompatibilityyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Cypriot_SyllabaryyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Ethiopic_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks17Old_South_ArabianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Alchemical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Latin_1_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Letterlike_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Linear_B_IdeogramsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Linear_B_SyllabaryyAh@Base 6
+ _D3std8internal14unicode_tables6blocks18Myanmar_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Cyrillic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Devanagari_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Ethiopic_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Ethiopic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19General_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Georgian_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Phonetic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Small_Form_VariantsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks19Variation_SelectorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Combining_Half_MarksyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Egyptian_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Meroitic_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Rumi_Numeral_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks20Sundanese_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Ancient_Greek_NumbersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Counting_Rod_NumeralsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Inscriptional_PahlaviyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Miscellaneous_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Modifier_Tone_LettersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Supplemental_Arrows_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Supplemental_Arrows_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks21Tai_Xuan_Jing_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22CJK_Unified_IdeographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Enclosed_AlphanumericsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Hangul_Jamo_Extended_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Hangul_Jamo_Extended_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Inscriptional_ParthianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks22Mathematical_OperatorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23CJK_Compatibility_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23CJK_Radicals_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Meetei_Mayek_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Miscellaneous_TechnicalyAh@Base 6
+ _D3std8internal14unicode_tables6blocks23Yijing_Hexagram_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks24Spacing_Modifier_LettersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks24Supplemental_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Byzantine_Musical_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Common_Indic_Number_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Hangul_Compatibility_JamoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Latin_Extended_AdditionalyAh@Base 6
+ _D3std8internal14unicode_tables6blocks25Transport_And_Map_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Arabic_Presentation_Forms_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Arabic_Presentation_Forms_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks27CJK_Symbols_and_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Combining_Diacritical_MarksyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27High_Private_Use_SurrogatesyAh@Base 6
+ _D3std8internal14unicode_tables6blocks27Superscripts_and_SubscriptsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks28CJK_Compatibility_IdeographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks28Katakana_Phonetic_ExtensionsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Alphabetic_Presentation_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Halfwidth_and_Fullwidth_FormsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks29Optical_Character_RecognitionyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Ancient_Greek_Musical_NotationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Phonetic_Extensions_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks30Variation_Selectors_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks31Enclosed_CJK_Letters_and_MonthsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks31Enclosed_Ideographic_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Enclosed_Alphanumeric_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Miscellaneous_Symbols_and_ArrowsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Supplementary_Private_Use_Area_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks32Supplementary_Private_Use_Area_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks33Cuneiform_Numbers_and_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables6blocks33Mathematical_Alphanumeric_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_CyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34CJK_Unified_Ideographs_Extension_DyAh@Base 6
+ _D3std8internal14unicode_tables6blocks34Ideographic_Description_CharactersyAh@Base 6
+ _D3std8internal14unicode_tables6blocks35Supplemental_Mathematical_OperatorsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks36Miscellaneous_Mathematical_Symbols_AyAh@Base 6
+ _D3std8internal14unicode_tables6blocks36Miscellaneous_Mathematical_Symbols_ByAh@Base 6
+ _D3std8internal14unicode_tables6blocks37Miscellaneous_Symbols_And_PictographsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks37Unified_Canadian_Aboriginal_SyllabicsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks38Arabic_Mathematical_Alphabetic_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks38Combining_Diacritical_Marks_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks39CJK_Compatibility_Ideographs_SupplementyAh@Base 6
+ _D3std8internal14unicode_tables6blocks39Combining_Diacritical_Marks_for_SymbolsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3LaoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3NKoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3VaiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6blocks46Unified_Canadian_Aboriginal_Syllabics_ExtendedyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4ChamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4LisuyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4MiaoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4TagsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4ThaiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6blocks5BamumyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5BatakyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5BuhidyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5KhmeryAh@Base 6
+ _D3std8internal14unicode_tables6blocks5LimbuyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5OghamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5OriyayAh@Base 6
+ _D3std8internal14unicode_tables6blocks5RunicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5TakriyAh@Base 6
+ _D3std8internal14unicode_tables6blocks5TamilyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ArabicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ArrowsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6BrahmiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6CarianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ChakmayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6CopticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6GothicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6HebrewyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6KaithiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6KanbunyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LepchayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LycianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6LydianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6RejangyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6SyriacyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6Tai_LeyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6TeluguyAh@Base 6
+ _D3std8internal14unicode_tables6blocks6ThaanayAh@Base 6
+ _D3std8internal14unicode_tables6blocks6__initZ@Base 6
+ _D3std8internal14unicode_tables6blocks7AvestanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7BengaliyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7DeseretyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7HanunooyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7KannadayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7MandaicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7MyanmaryAh@Base 6
+ _D3std8internal14unicode_tables6blocks7OsmanyayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7SharadayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7ShavianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7SinhalayAh@Base 6
+ _D3std8internal14unicode_tables6blocks7TagalogyAh@Base 6
+ _D3std8internal14unicode_tables6blocks7TibetanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8ArmenianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BalineseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BopomofoyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8BugineseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8CherokeeyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8CyrillicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8DingbatsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8EthiopicyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GeorgianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GujaratiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8GurmukhiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8HiraganayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8JavaneseyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8KatakanayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Kayah_LiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Ol_ChikiyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Phags_payAh@Base 6
+ _D3std8internal14unicode_tables6blocks8SpecialsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8TagbanwayAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Tai_ThamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8Tai_VietyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8TifinaghyAh@Base 6
+ _D3std8internal14unicode_tables6blocks8UgariticyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9CuneiformyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9EmoticonsyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9MalayalamyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9MongolianyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9SamaritanyAh@Base 6
+ _D3std8internal14unicode_tables6blocks9SundaneseyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1LyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1TyAh@Base 6
+ _D3std8internal14unicode_tables6hangul1VyAh@Base 6
+ _D3std8internal14unicode_tables6hangul2LVyAh@Base 6
+ _D3std8internal14unicode_tables6hangul3LVTyAh@Base 6
+ _D3std8internal14unicode_tables6hangul3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6hangul4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables6hangul6__initZ@Base 6
+ _D3std8internal14unicode_tables7isHangLFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7isHangTFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7isHangVFNaNbNiNfwZb@Base 6
+ _D3std8internal14unicode_tables7scripts10DevanagariyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10GlagoliticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10KharoshthiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10Old_ItalicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10Old_TurkicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10PhoenicianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts10SaurashtrayAh@Base 6
+ _D3std8internal14unicode_tables7scripts11New_Tai_LueyAh@Base 6
+ _D3std8internal14unicode_tables7scripts11Old_PersianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Meetei_MayekyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Sora_SompengyAh@Base 6
+ _D3std8internal14unicode_tables7scripts12Syloti_NagriyAh@Base 6
+ _D3std8internal14unicode_tables7scripts16Imperial_AramaicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts16Meroitic_CursiveyAh@Base 6
+ _D3std8internal14unicode_tables7scripts17Old_South_ArabianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts19Canadian_AboriginalyAh@Base 6
+ _D3std8internal14unicode_tables7scripts20Egyptian_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables7scripts20Meroitic_HieroglyphsyAh@Base 6
+ _D3std8internal14unicode_tables7scripts21Inscriptional_PahlaviyAh@Base 6
+ _D3std8internal14unicode_tables7scripts22Inscriptional_ParthianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts2YiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3HanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3LaoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3NkoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3VaiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables7scripts4ChamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4LisuyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4MiaoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4ThaiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables7scripts5BamumyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5BatakyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5BuhidyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5GreekyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5KhmeryAh@Base 6
+ _D3std8internal14unicode_tables7scripts5LatinyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5LimbuyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5OghamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5OriyayAh@Base 6
+ _D3std8internal14unicode_tables7scripts5RunicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5TakriyAh@Base 6
+ _D3std8internal14unicode_tables7scripts5TamilyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ArabicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6BrahmiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CarianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ChakmayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CommonyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6CopticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6GothicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6HangulyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6HebrewyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6KaithiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LepchayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LycianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6LydianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6RejangyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6SyriacyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6Tai_LeyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6TeluguyAh@Base 6
+ _D3std8internal14unicode_tables7scripts6ThaanayAh@Base 6
+ _D3std8internal14unicode_tables7scripts6__initZ@Base 6
+ _D3std8internal14unicode_tables7scripts7AvestanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7BengaliyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7BrailleyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7CypriotyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7DeseretyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7HanunooyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7KannadayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7MandaicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7MyanmaryAh@Base 6
+ _D3std8internal14unicode_tables7scripts7OsmanyayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7SharadayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7ShavianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7SinhalayAh@Base 6
+ _D3std8internal14unicode_tables7scripts7TagalogyAh@Base 6
+ _D3std8internal14unicode_tables7scripts7TibetanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8ArmenianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BalineseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BopomofoyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8BugineseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8CherokeeyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8CyrillicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8EthiopicyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GeorgianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GujaratiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8GurmukhiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8HiraganayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8JavaneseyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8KatakanayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Kayah_LiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Linear_ByAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Ol_ChikiyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Phags_PayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8TagbanwayAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Tai_ThamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8Tai_VietyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8TifinaghyAh@Base 6
+ _D3std8internal14unicode_tables7scripts8UgariticyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9CuneiformyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9InheritedyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9MalayalamyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9MongolianyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9SamaritanyAh@Base 6
+ _D3std8internal14unicode_tables7scripts9SundaneseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10AlphabeticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10DeprecatedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps10Other_MathyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11ID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11IdeographicyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11Soft_DottedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps11White_SpaceyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12Bidi_ControlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12Join_ControlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps12XID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps13Grapheme_BaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps13Grapheme_LinkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Case_IgnorableyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Other_ID_StartyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Pattern_SyntaxyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps14Quotation_MarkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15ASCII_Hex_DigityAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Grapheme_ExtendyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Other_LowercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps15Other_UppercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps16Other_AlphabeticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps17Other_ID_ContinueyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps17Unified_IdeographyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps18Variation_SelectoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps19IDS_Binary_OperatoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps19Pattern_White_SpaceyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps20IDS_Trinary_OperatoryAh@Base 6
+ _D3std8internal14unicode_tables8uniProps20Terminal_PunctuationyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps21Other_Grapheme_ExtendyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps23Logical_Order_ExceptionyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps23Noncharacter_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps28Default_Ignorable_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CcyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CfyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CnyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2CsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LmyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LtyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2LuyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2McyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2MeyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2MnyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NdyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2NoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PcyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PdyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PeyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PfyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PiyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2PsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ScyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SkyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SmyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2SoyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZlyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZpyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps2ZsyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps34Other_Default_Ignorable_Code_PointyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables8uniProps4DashyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps4MathyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps4_tabyAS3std8internal14unicode_tables15UnicodeProperty@Base 6
+ _D3std8internal14unicode_tables8uniProps5CasedyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps5STermyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps6HyphenyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps6__initZ@Base 6
+ _D3std8internal14unicode_tables8uniProps7RadicalyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps8ExtenderyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps8ID_StartyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9DiacriticyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9Hex_DigityAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9LowercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9UppercaseyAh@Base 6
+ _D3std8internal14unicode_tables8uniProps9XID_StartyAh@Base 6
+ _D3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D3std8internal16unicode_grapheme12__ModuleInfoZ@Base 6
+ _D3std8internal4math10biguintx8612__ModuleInfoZ@Base 6
+ _D3std8internal4math11biguintcore10CACHELIMITyk@Base 6
+ _D3std8internal4math11biguintcore10inplaceSubFNaNbAkAxkAxkZb@Base 6
+ _D3std8internal4math11biguintcore11blockDivModFNaNbAkAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore11includeSignFNaNbNfAxkkbZAk@Base 6
+ _D3std8internal4math11biguintcore11mulInternalFNaNbAkAxkAxkZv@Base 6
+ _D3std8internal4math11biguintcore12FASTDIVLIMITyk@Base 6
+ _D3std8internal4math11biguintcore12__ModuleInfoZ@Base 6
+ _D3std8internal4math11biguintcore12biguintToHexFNaNbNfAaxAkaZAa@Base 6
+ _D3std8internal4math11biguintcore12mulKaratsubaFNaNbAkAxkAxkAkZv@Base 6
+ _D3std8internal4math11biguintcore12squareSimpleFNaNbAkAxkZv@Base 6
+ _D3std8internal4math11biguintcore13__T6intpowTkZ6intpowFNaNbNiNfkmZk@Base 6
+ _D3std8internal4math11biguintcore14divModInternalFNaNbAkAkxAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore14itoaZeroPaddedFNaNbNfAakiZv@Base 6
+ _D3std8internal4math11biguintcore14squareInternalFNaNbAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore14twosComplementFNaNbNfAxkAkZv@Base 6
+ _D3std8internal4math11biguintcore15addAssignSimpleFNaNbAkAxkZk@Base 6
+ _D3std8internal4math11biguintcore15adjustRemainderFNaNbAkAkAxkiAkbZv@Base 6
+ _D3std8internal4math11biguintcore15recursiveDivModFNaNbAkAkAxkAkbZv@Base 6
+ _D3std8internal4math11biguintcore15squareKaratsubaFNaNbAkxAkAkZv@Base 6
+ _D3std8internal4math11biguintcore15subAssignSimpleFNaNbAkAxkZk@Base 6
+ _D3std8internal4math11biguintcore15toHexZeroPaddedFNaNbNfAakZ9hexDigitsyAa@Base 6
+ _D3std8internal4math11biguintcore15toHexZeroPaddedFNaNbNfAakZv@Base 6
+ _D3std8internal4math11biguintcore16biguintToDecimalFNaNbAaAkZk@Base 6
+ _D3std8internal4math11biguintcore16schoolbookDivModFNaNbAkAkxAkZv@Base 6
+ _D3std8internal4math11biguintcore17firstNonZeroDigitFNaNbNiNfxAkZi@Base 6
+ _D3std8internal4math11biguintcore18_sharedStaticCtor1FZv@Base 6
+ _D3std8internal4math11biguintcore18biguintFromDecimalFNaAkAxaZi@Base 6
+ _D3std8internal4math11biguintcore18removeLeadingZerosFNaNbNfANgkZANgk@Base 6
+ _D3std8internal4math11biguintcore20addOrSubAssignSimpleFNaNbAkAxkbZk@Base 6
+ _D3std8internal4math11biguintcore21highestDifferentDigitFNaNbNiNfxAkxAkZk@Base 6
+ _D3std8internal4math11biguintcore24highestPowerBelowUintMaxFNaNbNfkZ6maxpwryG22h@Base 6
+ _D3std8internal4math11biguintcore24highestPowerBelowUintMaxFNaNbNfkZi@Base 6
+ _D3std8internal4math11biguintcore25highestPowerBelowUlongMaxFNaNbNfkZ6maxpwryG39h@Base 6
+ _D3std8internal4math11biguintcore25highestPowerBelowUlongMaxFNaNbNfkZi@Base 6
+ _D3std8internal4math11biguintcore25karatsubaRequiredBuffSizeFNaNbNfkZk@Base 6
+ _D3std8internal4math11biguintcore3ONEyAk@Base 6
+ _D3std8internal4math11biguintcore3TENyAk@Base 6
+ _D3std8internal4math11biguintcore3TWOyAk@Base 6
+ _D3std8internal4math11biguintcore3addFNaNbxAkxAkZAk@Base 6
+ _D3std8internal4math11biguintcore3subFNaNbxAkxAkPbZAk@Base 6
+ _D3std8internal4math11biguintcore4ZEROyAk@Base 6
+ _D3std8internal4math11biguintcore4lessFNaNbAxkAxkZb@Base 6
+ _D3std8internal4math11biguintcore6addIntFNaNbxAkmZAk@Base 6
+ _D3std8internal4math11biguintcore6subIntFNaNbxAkmZAk@Base 6
+ _D3std8internal4math11biguintcore7BigUint10uintLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint11__invariantMxFNaZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint11__xopEqualsFKxS3std8internal4math11biguintcore7BigUintKxS3std8internal4math11biguintcore7BigUintZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint11toHexStringMxFNaNbNfiaiaZAa@Base 6
+ _D3std8internal4math11biguintcore7BigUint11ulongLengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__T5opCmpTvZ5opCmpMxFNaNbNiNfxS3std8internal4math11biguintcore7BigUintZi@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__T5opShlTmZ5opShlMxFNaNbNfmZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint12__invariant2MxFNaZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint13fromHexStringMFNaNbNfAxaZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint14__T6divIntTykZ6divIntFNaNbNfS3std8internal4math11biguintcore7BigUintykZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint14__T6modIntTykZ6modIntFNaNbNfS3std8internal4math11biguintcore7BigUintykZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opAssignTmZ8opAssignMFNaNbNfmZv@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opEqualsTvZ8opEqualsMxFNaNbNiNfKxS3std8internal4math11biguintcore7BigUintZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__T8opEqualsTvZ8opEqualsMxFNaNbNiNfmZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint15__funcliteral31FNaNbNiNeAkZAyk@Base 6
+ _D3std8internal4math11biguintcore7BigUint15toDecimalStringMxFNaNbiZAa@Base 6
+ _D3std8internal4math11biguintcore7BigUint17fromDecimalStringMFNaNeAxaZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint3divFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3modFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3mulFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint3powFNaNbS3std8internal4math11biguintcore7BigUintmZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint6__ctorMFNaNbNcNiNfAykZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint6__initZ@Base 6
+ _D3std8internal4math11biguintcore7BigUint6isZeroMxFNaNbNiNfZb@Base 6
+ _D3std8internal4math11biguintcore7BigUint6toHashMxFNbNeZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint8__xopCmpFKxS3std8internal4math11biguintcore7BigUintKxS3std8internal4math11biguintcore7BigUintZi@Base 6
+ _D3std8internal4math11biguintcore7BigUint8addOrSubFNaNbS3std8internal4math11biguintcore7BigUintS3std8internal4math11biguintcore7BigUintbPbZS3std8internal4math11biguintcore7BigUint@Base 6
+ _D3std8internal4math11biguintcore7BigUint8numBytesMxFNaNbNiNfZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint8peekUintMxFNaNbNiNfiZk@Base 6
+ _D3std8internal4math11biguintcore7BigUint9peekUlongMxFNaNbNiNfiZm@Base 6
+ _D3std8internal4math11biguintcore9addSimpleFNaNbAkxAkxAkZk@Base 6
+ _D3std8internal4math11biguintcore9mulSimpleFNaNbAkAxkAxkZv@Base 6
+ _D3std8internal4math11biguintcore9subSimpleFNaNbAkAxkAxkZk@Base 6
+ _D3std8internal4math12biguintnoasm12__ModuleInfoZ@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteMulFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteShlFNaNbNiNfAkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm12multibyteShrFNaNbNiNfAkAxkkZv@Base 6
+ _D3std8internal4math12biguintnoasm15multibyteSquareFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm18multibyteDivAssignFNaNbNiNfAkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai43Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai45Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai43Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai45Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteAddDiagonalSquaresFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteMultiplyAccumulateFNaNbNiNfAkAxkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteTriangleAccumulateFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai43Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai45Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math13errorfunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13errorfunction1PyG10e@Base 6
+ _D3std8internal4math13errorfunction1QyG11e@Base 6
+ _D3std8internal4math13errorfunction1RyG5e@Base 6
+ _D3std8internal4math13errorfunction1SyG6e@Base 6
+ _D3std8internal4math13errorfunction1TyG7e@Base 6
+ _D3std8internal4math13errorfunction1UyG7e@Base 6
+ _D3std8internal4math13errorfunction20__T12rationalPolyTeZ12rationalPolyFNaNbNiNfeAxeAxeZe@Base 6
+ _D3std8internal4math13errorfunction22normalDistributionImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction3erfFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction4erfcFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5EXP_2ye@Base 6
+ _D3std8internal4math13errorfunction5erfceFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5expx2FNaNbNiNfeiZe@Base 6
+ _D3std8internal4math13gammafunction10EULERGAMMAye@Base 6
+ _D3std8internal4math13gammafunction11logmdigammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19LargeStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19SmallStirlingCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction14betaIncompleteFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction15gammaIncompleteFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction16GammaSmallCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZ4coefyG13Ae@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction17betaIncompleteInvFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction17logGammaNumeratoryG7e@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion1FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion2FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18logmdigammaInverseFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction19GammaSmallNegCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction19betaDistPowerSeriesFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction19logGammaDenominatoryG8e@Base 6
+ _D3std8internal4math13gammafunction20GammaNumeratorCoeffsyG8e@Base 6
+ _D3std8internal4math13gammafunction20gammaIncompleteComplFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction22GammaDenominatorCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction22logGammaStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction23gammaIncompleteComplInvFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction4Bn_nyG7e@Base 6
+ _D3std8internal4math13gammafunction5gammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction7digammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction8logGammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4test10dummyrange12__ModuleInfoZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange13opIndexAssignMFNaNbNiNfkkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMNgFNaNbNcNiNfkZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfkkZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMxFNaNbNiNfkZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfkkZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal6digest9sha_SSSE312__ModuleInfoZ@Base 6
+ _D3std8internal7cstring12__ModuleInfoZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3ResZS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFNbNiAxaZS3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3ResZS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res@Base 6
+ _D3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFNbNiAyaZS3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res3ptrMxFNaNbNdNiNfZPxa@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__dtorMFNbNiZv@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__initZ@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res7buffPtrMNgFNaNbNdNiNfZPNga@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res8opAssignMFNbNcNiNjS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3ResZS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res@Base 6
+ _D3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFNbNiANgaZS3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res@Base 6
+ _D3std8internal7windows8advapi3212__ModuleInfoZ@Base 6
+ _D3std8syserror12__ModuleInfoZ@Base 6
+ _D3std8syserror8SysError3msgFkZAya@Base 6
+ _D3std8syserror8SysError6__initZ@Base 6
+ _D3std8syserror8SysError6__vtblZ@Base 6
+ _D3std8syserror8SysError7__ClassZ@Base 6
+ _D3std8typecons10Structural11__InterfaceZ@Base 6
+ _D3std8typecons10__T5tupleZ135__T5tupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZS3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ136__T5tupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5tupleFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ137__T5tupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ16__T5tupleTkTkTkZ5tupleFNaNbNiNfkkkZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ22__T5tupleTAyaTAyaTAyaZ5tupleFNaNbNiNfAyaAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPbZ5tupleFNaNbNiNfC8TypeInfoPbZS3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPiZ5tupleFNaNbNiNfC8TypeInfoPiZS3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ24__T5tupleTC8TypeInfoTPkZ5tupleFNaNbNiNfC8TypeInfoPkZS3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ33__T5tupleTC14TypeInfo_ArrayTPAyhZ5tupleFNaNbNiNfC14TypeInfo_ArrayPAyhZS3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ34__T5tupleTC14TypeInfo_ArrayTPG16hZ5tupleFNaNbNiNfC14TypeInfo_ArrayPG16hZS3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons10__T5tupleZ34__T5tupleTC14TypeInfo_ClassTPG16hZ5tupleFNaNbNiNfC14TypeInfo_ClassPG16hZS3std8typecons34__T5TupleTC14TypeInfo_ClassTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons10__T5tupleZ35__T5tupleTC15TypeInfo_StructTPG16hZ5tupleFNaNbNiNfC15TypeInfo_StructPG16hZS3std8typecons35__T5TupleTC15TypeInfo_StructTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons10__T5tupleZ35__T5tupleTC18TypeInfo_InvariantTPhZ5tupleFNaNbNiNfC18TypeInfo_InvariantPhZS3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ38__T5tupleTC18TypeInfo_InvariantTPG16hZ5tupleFNaNbNiNfC18TypeInfo_InvariantPG16hZS3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons10__T5tupleZ48__T5tupleTC14TypeInfo_ClassTPC6object9ThrowableZ5tupleFNaNbNiNfC14TypeInfo_ClassPC6object9ThrowableZS3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ50__T5tupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5tupleFNaNbNiNfC15TypeInfo_SharedPOC6object9ThrowableZS3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons10__T5tupleZ53__T5tupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5tupleFNaNbNiNfC15TypeInfo_StructPS3std11concurrency3TidZS3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple@Base 6
+ _D3std8typecons12__ModuleInfoZ@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZS3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D3std8typecons135__T5TupleTC15TypeInfo_StructTPS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple11__fieldDtorMFNaNbNiNeZv@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple11__xopEqualsFKxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleKxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZb@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple15__fieldPostblitMFNaNbNiNeZv@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple174__T8opEqualsTxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5TupleZb@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__ctorMFNaNbNcNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZS3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6__initZ@Base 6
+ _D3std8typecons136__T5TupleTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZS3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6__initZ@Base 6
+ _D3std8typecons137__T5TupleTC15TypeInfo_StructTPS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons14__T5TupleTbTiZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple11__xopEqualsFKxS3std8typecons14__T5TupleTbTiZ5TupleKxS3std8typecons14__T5TupleTbTiZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple48__T5opCmpTxS3std8typecons14__T5TupleTbTiZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons14__T5TupleTbTiZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple51__T8opEqualsTxS3std8typecons14__T5TupleTbTiZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons14__T5TupleTbTiZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6__ctorMFNaNbNcNiNfbiZS3std8typecons14__T5TupleTbTiZ5Tuple@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6__initZ@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons14__T5TupleTbTiZ5Tuple8__xopCmpFKxS3std8typecons14__T5TupleTbTiZ5TupleKxS3std8typecons14__T5TupleTbTiZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTkTkZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple11__xopEqualsFKxS3std8typecons14__T5TupleTkTkZ5TupleKxS3std8typecons14__T5TupleTkTkZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple48__T5opCmpTxS3std8typecons14__T5TupleTkTkZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons14__T5TupleTkTkZ5TupleZi@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple51__T8opEqualsTxS3std8typecons14__T5TupleTkTkZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons14__T5TupleTkTkZ5TupleZb@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple6__ctorMFNaNbNcNiNfkkZS3std8typecons14__T5TupleTkTkZ5Tuple@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple6__initZ@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons14__T5TupleTkTkZ5Tuple8__xopCmpFKxS3std8typecons14__T5TupleTkTkZ5TupleKxS3std8typecons14__T5TupleTkTkZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple11__xopEqualsFKxS3std8typecons16__T5TupleTiTAyaZ5TupleKxS3std8typecons16__T5TupleTiTAyaZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple50__T5opCmpTxS3std8typecons16__T5TupleTiTAyaZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons16__T5TupleTiTAyaZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple53__T8opEqualsTxS3std8typecons16__T5TupleTiTAyaZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons16__T5TupleTiTAyaZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6__ctorMFNaNbNcNiNfiAyaZS3std8typecons16__T5TupleTiTAyaZ5Tuple@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6__initZ@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons16__T5TupleTiTAyaZ5Tuple8__xopCmpFKxS3std8typecons16__T5TupleTiTAyaZ5TupleKxS3std8typecons16__T5TupleTiTAyaZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple11__xopEqualsFKxS3std8typecons16__T5TupleTkTkTkZ5TupleKxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple50__T5opCmpTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons16__T5TupleTkTkTkZ5TupleZi@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple53__T8opEqualsTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6__ctorMFNaNbNcNiNfkkkZS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons16__T5TupleTkTkTkZ5Tuple8__xopCmpFKxS3std8typecons16__T5TupleTkTkTkZ5TupleKxS3std8typecons16__T5TupleTkTkTkZ5TupleZi@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple11__xopEqualsFKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZb@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple52__T5opCmpTxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZi@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple55__T8opEqualsTxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZb@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__ctorMFNaNbNcNiNfeeeeZS3std8typecons18__T5TupleTeTeTeTeZ5Tuple@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__initZ@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons18__T5TupleTeTeTeTeZ5Tuple8__xopCmpFKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleKxS3std8typecons18__T5TupleTeTeTeTeZ5TupleZi@Base 6
+ _D3std8typecons19NotImplementedError6__ctorMFAyaZC3std8typecons19NotImplementedError@Base 6
+ _D3std8typecons19NotImplementedError6__initZ@Base 6
+ _D3std8typecons19NotImplementedError6__vtblZ@Base 6
+ _D3std8typecons19NotImplementedError7__ClassZ@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple11__xopEqualsFKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZb@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple56__T5opCmpTxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZi@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple59__T8opEqualsTxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZb@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__ctorMFNaNbNcNiNfAyaAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__initZ@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple8__xopCmpFKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleKxS3std8typecons22__T5TupleTAyaTAyaTAyaZ5TupleZi@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPbZS3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPiZS3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPkZS3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__ctorMFNaNbNcNiNfC8TypeInfoPvZS3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__initZ@Base 6
+ _D3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons2No6__initZ@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ArrayPAyhZS3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__initZ@Base 6
+ _D3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG16hZ17injectNamedFieldsFZAya@Base 6.2.1-1ubuntu2
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG16hZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ArrayPG16hZS3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG16hZ5Tuple6toHashMxFNbNeZk@Base 6.2.1-1ubuntu2
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG16hZ17injectNamedFieldsFZAya@Base 6.2.1-1ubuntu2
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG16hZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ClassPG16hZS3std8typecons34__T5TupleTC14TypeInfo_ClassTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D3std8typecons34__T5TupleTC14TypeInfo_ClassTPG16hZ5Tuple6toHashMxFNbNeZk@Base 6.2.1-1ubuntu2
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG16hZ17injectNamedFieldsFZAya@Base 6.2.1-1ubuntu2
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG16hZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPG16hZS3std8typecons35__T5TupleTC15TypeInfo_StructTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D3std8typecons35__T5TupleTC15TypeInfo_StructTPG16hZ5Tuple6toHashMxFNbNeZk@Base 6.2.1-1ubuntu2
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__ctorMFNaNbNcNiNfC18TypeInfo_InvariantPhZS3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__initZ@Base 6
+ _D3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG16hZ17injectNamedFieldsFZAya@Base 6.2.1-1ubuntu2
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG16hZ5Tuple6__ctorMFNaNbNcNiNfC18TypeInfo_InvariantPG16hZS3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG16hZ5Tuple@Base 6.2.1-1ubuntu2
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG16hZ5Tuple6toHashMxFNbNeZk@Base 6.2.1-1ubuntu2
+ _D3std8typecons3Yes6__initZ@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple11__xopEqualsFKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZb@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons14__T5TupleTkTkZ5Tuple@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6__ctorMFNaNbNcNiNfkkZS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6__initZ@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple74__T5opCmpTxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZi@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple77__T8opEqualsTxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZb@Base 6
+ _D3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple8__xopCmpFKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleKxS3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5TupleZi@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable11__xopEqualsFKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZb@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin13getMNgFNaNbNcNdNiNeZyC3std8datetime8TimeZone@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin16__ctorMFNaNbNcNiNeyC3std8datetime8TimeZoneZS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin18opAssignMFNaNbNiNeS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZv@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable8__mixin18opAssignMFNaNbNiNeyC3std8datetime8TimeZoneZv@Base 6
+ _D3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable9__xtoHashFNbNeKxS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10RebindableZk@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__ctorMFNaNbNcNiNfC14TypeInfo_ClassPC6object9ThrowableZS3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_SharedPOC6object9ThrowableZS3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__ctorMFNaNbNcNiNfC15TypeInfo_StructPS3std11concurrency3TidZS3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__initZ@Base 6
+ _D3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple11__xopEqualsFKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZb@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons16__T5TupleTiTAyaZ5Tuple@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__ctorMFNaNbNcNiNfiAyaZS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__initZ@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple88__T5opCmpTxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZi@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple8__xopCmpFKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleKxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZi@Base 6
+ _D3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple91__T8opEqualsTxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5TupleZb@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple11__xopEqualsFKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZb@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple12_Tuple_superMNgFNaNbNcNdNiNeZNgS3std8typecons14__T5TupleTbTiZ5Tuple@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__ctorMFNaNbNcNiNfbiZS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__initZ@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6toHashMxFNbNeZk@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple8__xopCmpFKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleKxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZi@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple95__T5opCmpTxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZ5opCmpMxFNaNbNiNfxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZi@Base 6
+ _D3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple98__T8opEqualsTxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZ8opEqualsMxFNaNbNiNfxS3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple119__T8opEqualsTxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZ8opEqualsMxFxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple11__xopEqualsFKxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleKxS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__ctorMFNaNbNcNiNfS3std11concurrency3TidS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZS3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D3std8typecons82__T5TupleTS3std11concurrency3TidTS3std3net4curl19__T11CurlMessageTbZ11CurlMessageZ5Tuple6toHashMxFNaNbNeZk@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZk@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl3FTP4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl3FTP4Impl@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl3FTP4ImplZS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZk@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl4HTTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl4HTTP4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4moveMFNbNiKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMFNbNcNdNiNjZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std3net4curl4SMTP4Impl@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__ctorMFNcS3std3net4curl4SMTP4ImplZS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted6__initZ@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted8opAssignMFS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCountedZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ17injectNamedFieldsFZAya@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple11__xopEqualsFKxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleKxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple120__T8opAssignTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opAssignMFNaNbNiNfKS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple120__T8opEqualsTS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opEqualsMFS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple121__T8opEqualsTxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZ8opEqualsMxFxS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5TupleZb@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple27__T8toStringTDFNaNbNfAxaZvZ8toStringMFMDFNaNbNfAxaZvZv@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__ctorMFNaNbNcNiNfS3std11concurrency3TidS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZS3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6__initZ@Base 6
+ _D3std8typecons84__T5TupleTS3std11concurrency3TidTS3std3net4curl21__T11CurlMessageTAyhZ11CurlMessageZ5Tuple6toHashMxFNaNbNeZk@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted10__postblitMFNaNbNiNfZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore13isInitializedMxFNaNbNdNiNfZb@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore16__T10initializeZ10initializeMFNbNiZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore17ensureInitializedMFNbNiZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore42__T10initializeTAyaTE3std4file8SpanModeTbZ10initializeMFKAyaKE3std4file8SpanModeKbZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl11__fieldDtorMFZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl11__xopEqualsFKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl8opAssignMFNcNjS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4Impl9__xtoHashFNbNeKxS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZk@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4moveMFNbNiKS3std4file15DirIteratorImplZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore8refCountMxFNaNbNdNiNfZk@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15refCountedStoreMNgFNaNbNcNdNiNfZNgS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted17refCountedPayloadMNgFNaNbNcNdNiNjNfZNgS3std4file15DirIteratorImpl@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted37__T6__ctorTAyaTE3std4file8SpanModeTbZ6__ctorMFNcKAyaKE3std4file8SpanModeKbZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__ctorMFNcS3std4file15DirIteratorImplZS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__dtorMFZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted6__initZ@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted8opAssignMFS3std4file15DirIteratorImplZv@Base 6
+ _D3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted8opAssignMFS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCountedZv@Base 6
+ _D3std8typelist12__ModuleInfoZ@Base 6
+ _D3std9algorithm10comparison12__ModuleInfoZ@Base 6
+ _D3std9algorithm10comparison12__T3maxTiTiZ3maxFNaNbNiNfiiZi@Base 6
+ _D3std9algorithm10comparison12__T3maxTkTiZ3maxFNaNbNiNfkiZk@Base 6
+ _D3std9algorithm10comparison12__T3maxTkTkZ3maxFNaNbNiNfkkZk@Base 6
+ _D3std9algorithm10comparison12__T3minTkTiZ3minFNaNbNiNfkiZi@Base 6
+ _D3std9algorithm10comparison12__T3minTkTkZ3minFNaNbNiNfkkZk@Base 6
+ _D3std9algorithm10comparison12__T3minTlTkZ3minFNaNbNiNflkZl@Base 6
+ _D3std9algorithm10comparison13__T3minTkTykZ3minFNaNbNiNfkykZk@Base 6
+ _D3std9algorithm10comparison13__T3minTyiTkZ3minFNaNbNiNfyikZyi@Base 6
+ _D3std9algorithm10comparison13__T3minTykTkZ3minFNaNbNiNfykkZyk@Base 6
+ _D3std9algorithm10comparison14__T3maxTkTkTkZ3maxFNaNbNiNfkkkZk@Base 6
+ _D3std9algorithm10comparison14__T3minTykTykZ3minFNaNbNiNfykykZyk@Base 6
+ _D3std9algorithm10comparison20__T5amongVai45Vai43Z13__T5amongTxaZ5amongFNaNbNiNfxaZk@Base 6
+ _D3std9algorithm10comparison20__T5amongVai95Vai44Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison21__T5amongVai101Vai69Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison21__T5amongVai105Vai73Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison32__T5amongVai117Vai108Vai85Vai76Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison33__T3cmpVAyaa5_61203c2062TAxhTAxhZ3cmpFNaNbNiNfAxhAxhZi@Base 6
+ _D3std9algorithm10comparison43__T5amongVai108Vai76Vai102Vai70Vai105Vai73Z13__T5amongTyaZ5amongFNaNbNiNfyaZk@Base 6
+ _D3std9algorithm10comparison489__T3cmpVAyaa5_61203c2062TS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultTS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZ3cmpFNaNfS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZi@Base 6
+ _D3std9algorithm10comparison6EditOp6__initZ@Base 6
+ _D3std9algorithm12__ModuleInfoZ@Base 6
+ _D3std9algorithm6setops12__ModuleInfoZ@Base 6
+ _D3std9algorithm7sorting103__T12HeapSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ13__T8heapSortZ8heapSortFNaNbNiNfAAyaZv@Base 6
+ _D3std9algorithm7sorting103__T12HeapSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ9__T4siftZ4siftFNaNbNiNfAAyakykZv@Base 6
+ _D3std9algorithm7sorting104__T13quickSortImplS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ13quickSortImplFNaNbNiNfAAyakZv@Base 6
+ _D3std9algorithm7sorting114__T23optimisticInsertionSortS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ23optimisticInsertionSortFNaNbNiNfAAyaZv@Base 6
+ _D3std9algorithm7sorting12__ModuleInfoZ@Base 6
+ _D3std9algorithm7sorting135__T4sortVAyaa17_612e74696d6554203c20622e74696d6554VE3std9algorithm8mutation12SwapStrategyi0TAS3std8datetime13PosixTimeZone10LeapSecondZ4sortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZS3std5range102__T11SortedRangeTAS3std8datetime13PosixTimeZone10LeapSecondVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std9algorithm7sorting139__T4sortVAyaa17_612e74696d6554203c20622e74696d6554VE3std9algorithm8mutation12SwapStrategyi0TAS3std8datetime13PosixTimeZone14TempTransitionZ4sortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZS3std5range106__T11SortedRangeTAS3std8datetime13PosixTimeZone14TempTransitionVAyaa17_612e74696d6554203c20622e74696d6554Z11SortedRange@Base 6
+ _D3std9algorithm7sorting162__T8getPivotS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ8getPivotFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZk@Base 6
+ _D3std9algorithm7sorting162__T8isSortedS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ8isSortedFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std9algorithm7sorting166__T8getPivotS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ8getPivotFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZk@Base 6
+ _D3std9algorithm7sorting166__T8isSortedS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ8isSortedFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9algorithm7sorting167__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ13__T8heapSortZ8heapSortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm7sorting167__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ9__T4siftZ4siftFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondkykZv@Base 6
+ _D3std9algorithm7sorting168__T13quickSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ13quickSortImplFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondkZv@Base 6
+ _D3std9algorithm7sorting171__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ13__T8heapSortZ8heapSortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm7sorting171__T12HeapSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ9__T4siftZ4siftFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionkykZv@Base 6
+ _D3std9algorithm7sorting172__T13quickSortImplS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ13quickSortImplFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionkZv@Base 6
+ _D3std9algorithm7sorting178__T23optimisticInsertionSortS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone10LeapSecondZ23optimisticInsertionSortFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm7sorting182__T23optimisticInsertionSortS1023std10functional74__T9binaryFunVAyaa17_612e74696d6554203c20622e74696d6554VAyaa1_61VAyaa1_62Z9binaryFunTAS3std8datetime13PosixTimeZone14TempTransitionZ23optimisticInsertionSortFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm7sorting201__T11TimSortImplS873std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList8sanitizeMFNeZ9__lambda1TS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ5Slice6__initZ@Base 6
+ _D3std9algorithm7sorting72__T4sortVAyaa5_61203c2062VE3std9algorithm8mutation12SwapStrategyi0TAAyaZ4sortFNaNbNiNfAAyaZS3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange@Base 6
+ _D3std9algorithm7sorting98__T8getPivotS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ8getPivotFNaNbNiNfAAyaZk@Base 6
+ _D3std9algorithm7sorting98__T8isSortedS773std10functional49__T9binaryFunVAyaa5_61203c2062VAyaa1_61VAyaa1_62Z9binaryFunTAAyaZ8isSortedFNaNbNiNfAAyaZb@Base 6
+ _D3std9algorithm8internal12__ModuleInfoZ@Base 6
+ _D3std9algorithm8mutation103__T4moveTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ4moveFNaNbNiKS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals@Base 6
+ _D3std9algorithm8mutation105__T6swapAtTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ6swapAtFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalskkZv@Base 6
+ _D3std9algorithm8mutation106__T7reverseTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ7reverseFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZv@Base 6
+ _D3std9algorithm8mutation12__ModuleInfoZ@Base 6
+ _D3std9algorithm8mutation12__T4moveTAkZ4moveFNaNbNiKAkZAk@Base 6
+ _D3std9algorithm8mutation133__T4copyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTAS3std3uni17CodepointIntervalZ4copyFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZAS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation133__T4copyTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTAS3std3uni17CodepointIntervalZ4copyFS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZ11genericImplFNaNbNiNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsAS3std3uni17CodepointIntervalZAS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation13__T4moveTAyaZ4moveFNaNbNiNfKAyaKAyaZv@Base 6
+ _D3std9algorithm8mutation13__T4swapTAyaZ4swapFNaNbNiNeKAyaKAyaZv@Base 6
+ _D3std9algorithm8mutation144__T4swapTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation145__T4swapTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation145__T4swapTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation148__T4swapTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZ4swapFNaNbNiNeKPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZv@Base 6
+ _D3std9algorithm8mutation14__T4moveTAAyaZ4moveFNaNbNiKAAyaZAAya@Base 6
+ _D3std9algorithm8mutation14__T4swapTAAyaZ4swapFNaNbNiNeKAAyaKAAyaZv@Base 6
+ _D3std9algorithm8mutation15__T4copyTAiTAkZ4copyFAiAkZ11genericImplFNaNbNiNfAiAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAiTAkZ4copyFNaNbNiNfAiAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAkTAkZ4copyFAkAkZ11genericImplFNaNbNiNfAkAkZAk@Base 6
+ _D3std9algorithm8mutation15__T4copyTAkTAkZ4copyFNaNbNiNfAkAkZAk@Base 6
+ _D3std9algorithm8mutation16__T6swapAtTAAyaZ6swapAtFNaNbNiNfAAyakkZv@Base 6
+ _D3std9algorithm8mutation174__T4moveTS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZ4moveFNaNbNiKS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm8mutation183__T4moveTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZ4moveFNaNbNiKS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm8mutation26__T4swapTS3std5stdio4FileZ4swapFNaNbNiNeKS3std5stdio4FileKS3std5stdio4FileZv@Base 6
+ _D3std9algorithm8mutation29__T4moveTC4core6thread5FiberZ4moveFNaNbNiNfKC4core6thread5FiberKC4core6thread5FiberZv@Base 6
+ _D3std9algorithm8mutation33__T4moveTS3std3net4curl3FTP4ImplZ4moveFKS3std3net4curl3FTP4ImplKS3std3net4curl3FTP4ImplZv@Base 6
+ _D3std9algorithm8mutation34__T4moveTS3std3net4curl4HTTP4ImplZ4moveFKS3std3net4curl4HTTP4ImplKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D3std9algorithm8mutation34__T4moveTS3std3net4curl4SMTP4ImplZ4moveFKS3std3net4curl4SMTP4ImplKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D3std9algorithm8mutation37__T4moveTS3std4file15DirIteratorImplZ4moveFKS3std4file15DirIteratorImplKS3std4file15DirIteratorImplZv@Base 6
+ _D3std9algorithm8mutation38__T4moveTS3std3uni17CodepointIntervalZ4moveFNaNbNiNfKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std9algorithm8mutation40__T4swapTS3std5stdio17LockingTextReaderZ4swapFNaNbNiNeKS3std5stdio17LockingTextReaderKS3std5stdio17LockingTextReaderZv@Base 6
+ _D3std9algorithm8mutation46__T4moveTAS3std5regex8internal2ir10NamedGroupZ4moveFNaNbNiKAS3std5regex8internal2ir10NamedGroupZAS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std9algorithm8mutation51__T4swapTS3std8datetime13PosixTimeZone10LeapSecondZ4swapFNaNbNiNeKS3std8datetime13PosixTimeZone10LeapSecondKS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm8mutation52__T4moveTAS3std8datetime13PosixTimeZone10LeapSecondZ4moveFNaNbNiKAS3std8datetime13PosixTimeZone10LeapSecondZAS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D3std9algorithm8mutation52__T4swapTAS3std8datetime13PosixTimeZone10LeapSecondZ4swapFNaNbNiNeKAS3std8datetime13PosixTimeZone10LeapSecondKAS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D3std9algorithm8mutation54__T6swapAtTAS3std8datetime13PosixTimeZone10LeapSecondZ6swapAtFNaNbNiNfAS3std8datetime13PosixTimeZone10LeapSecondkkZv@Base 6
+ _D3std9algorithm8mutation54__T7moveAllTAC4core6thread5FiberTAC4core6thread5FiberZ7moveAllFNaNfAC4core6thread5FiberAC4core6thread5FiberZAC4core6thread5Fiber@Base 6
+ _D3std9algorithm8mutation55__T4swapTS3std8datetime13PosixTimeZone14TempTransitionZ4swapFNaNbNiNeKS3std8datetime13PosixTimeZone14TempTransitionKS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm8mutation56__T4moveTAS3std8datetime13PosixTimeZone14TempTransitionZ4moveFNaNbNiKAS3std8datetime13PosixTimeZone14TempTransitionZAS3std8datetime13PosixTimeZone14TempTransition@Base 6
+ _D3std9algorithm8mutation56__T4swapTAS3std8datetime13PosixTimeZone14TempTransitionZ4swapFNaNbNiNeKAS3std8datetime13PosixTimeZone14TempTransitionKAS3std8datetime13PosixTimeZone14TempTransitionZv@Base 6
+ _D3std9algorithm8mutation58__T6swapAtTAS3std8datetime13PosixTimeZone14TempTransitionZ6swapAtFNaNbNiNfAS3std8datetime13PosixTimeZone14TempTransitionkkZv@Base 6
+ _D3std9algorithm8mutation59__T6removeVE3std9algorithm8mutation12SwapStrategyi0TAAyaTiZ6removeFNaNbNiNfAAyaiZAAya@Base 6
+ _D3std9algorithm8mutation674__T4copyTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultTAkZ4copyFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZAk@Base 6
+ _D3std9algorithm8mutation674__T4copyTS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultTAkZ4copyFS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZ11genericImplFNaNfS3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6ResultAkZAk@Base 6
+ _D3std9algorithm8mutation75__T6removeVE3std9algorithm8mutation12SwapStrategyi2TAC4core6thread5FiberTkZ6removeFNaNfAC4core6thread5FiberkZAC4core6thread5Fiber@Base 6
+ _D3std9algorithm8mutation77__T4copyTAS3std5regex8internal2ir8BytecodeTAS3std5regex8internal2ir8BytecodeZ4copyFAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZ11genericImplFNaNbNiNfAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZAS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std9algorithm8mutation77__T4copyTAS3std5regex8internal2ir8BytecodeTAS3std5regex8internal2ir8BytecodeZ4copyFNaNbNiNfAS3std5regex8internal2ir8BytecodeAS3std5regex8internal2ir8BytecodeZAS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std9algorithm9iteration105__T6filterS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbZ88__T6filterTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ6filterFNaNfS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult4saveMFNaNbNdNiZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult5frontMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult6__ctorMFNaNbNcNiS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult7opSliceMFNaNbNiNfZS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResult8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult4saveMFNaNdNfZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5emptyMFNaNdNfZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5frontMFNaNdNfZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__ctorMFNaNbNcNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult4saveMFNaNdNfZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5emptyMFNaNdNfZb@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult5frontMFNaNdNfZk@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__ctorMFNaNbNcNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration11__T3sumTAkZ3sumFNaNbNiNfAkZk@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult11__fieldDtorMFZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult11__xopEqualsFKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZb@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult15__fieldPostblitMFNbZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult5emptyMFNdZb@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult5frontMFNdZS3std4file8DirEntry@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__ctorMFNcS3std4file11DirIteratorZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult7opSliceMFNbZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult8opAssignMFNcNjS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult8popFrontMFZv@Base 6
+ _D3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResult9__xtoHashFNbNeKxS3std9algorithm9iteration121__T12FilterResultS76_D3std4file10dirEntriesFAyaAyaE3std4file8SpanModebZ1fMFS3std4file8DirEntryZbTS3std4file11DirIteratorZ12FilterResultZk@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult12__T7popBackZ7popBackMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult5frontMFNaNbNdNiNfZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__ctorMFNaNbNcNiNfAyS3std8internal14unicode_tables9CompEntryZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult7opIndexMFNaNbNiNfkZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult7opSliceMFNaNbNiNfkkZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult9__T4backZ4backMFNaNbNdNiNfZyw@Base 6
+ _D3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration12__ModuleInfoZ@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult12__T7popBackZ7popBackMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult5frontMFNaNbNdNiNfZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__ctorMFNaNbNcNiNfAyS3std8internal14unicode_tables15UnicodePropertyZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult6lengthMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult7opIndexMFNaNbNiNfkZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult7opSliceMFNaNbNiNfkkZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult9__T4backZ4backMFNaNbNdNiNfZyAa@Base 6
+ _D3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration13__T3sumTAkTkZ3sumFNaNbNiNfAkkZk@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult11__xopEqualsFKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZb@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult4saveMFNaNdNfZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult5frontMFNaNdNfZw@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__ctorMFNaNcNfS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult6__initZ@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult7opSliceMFNaNbNiNfZS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResult9__xtoHashFNbNeKxS3std9algorithm9iteration189__T12FilterResultS91_D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZbTS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZ12FilterResultZk@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult4saveMFNaNbNdNiZS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult5frontMFNaNbNdNiZS3std8bitmanip14__T7BitsSetTkZ7BitsSet@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult6__ctorMFNaNbNcNiNfS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResult8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration23__T3mapVAyaa4_615b305dZ41__T3mapTS3std3uni21DecompressedIntervalsZ3mapFNaNbNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration23__T3mapVAyaa4_615b315dZ41__T3mapTS3std3uni21DecompressedIntervalsZ3mapFNaNbNiNfS3std3uni21DecompressedIntervalsZS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResult@Base 6
+ _D3std9algorithm9iteration25__T3mapVAyaa5_612e726873Z51__T3mapTAyS3std8internal14unicode_tables9CompEntryZ3mapFNaNbNiNfAyS3std8internal14unicode_tables9CompEntryZS3std9algorithm9iteration126__T9MapResultS663std10functional39__T8unaryFunVAyaa5_612e726873VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables9CompEntryZ9MapResult@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFNaNbNiS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result4saveMFNaNbNdNiZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result5frontMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result6__ctorMFNaNbNcNiS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZS3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result8popFrontMFNaNbNiZv@Base 6
+ _D3std9algorithm9iteration27__T3mapVAyaa6_612e6e616d65Z58__T3mapTAyS3std8internal14unicode_tables15UnicodePropertyZ3mapFNaNbNiNfAyS3std8internal14unicode_tables15UnicodePropertyZS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResult@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z16__T6reduceTkTAkZ6reduceFNaNbNiNfkAkZk@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z24__T13reducePreImplTAkTkZ13reducePreImplFNaNbNiNfAkKkZk@Base 6
+ _D3std9algorithm9iteration28__T6reduceVAyaa5_61202b2062Z25__T10reduceImplVbi0TAkTkZ10reduceImplFNaNbNiNfAkKkZk@Base 6
+ _D3std9algorithm9iteration29__T3mapS183std5ascii7toLowerZ12__T3mapTAxaZ3mapFNaNbNiNfAxaZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result11__xopEqualsFKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultZb@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result11lastIndexOfFNaNfAyaaZk@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result4backMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result4saveMFNaNbNdNiNfZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result5frontMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__ctorMFNaNbNcNiNfAyaaZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result7popBackMFNaNfZv@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result8popFrontMFNaNfZv@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result9__xtoHashFNbNeKxS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6ResultZk@Base 6
+ _D3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFNaNbNiNfAyaaZS3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult11__xopEqualsFKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZb@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult5frontMFNaNdNfZw@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__ctorMFNaNbNcNiNfAxaZS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult9__xtoHashFNbNeKxS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResultZk@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result11__xopEqualsFKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZb@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result15separatorLengthMFNaNbNdNiNfZk@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result16ensureBackLengthMFNaNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result17ensureFrontLengthMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result4backMFNaNdNfZAya@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result4saveMFNaNbNdNiNfZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result5frontMFNaNbNdNiNfZAya@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__ctorMFNaNbNcNiNfAyaAyaZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__initZ@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result7popBackMFNaNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result9__xtoHashFNbNeKxS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6ResultZk@Base 6
+ _D3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFNaNbNiNfAyaAyaZS3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult5frontMFNdNfZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__ctorMFNaNbNcNiNfS3std5range13__T6RepeatTiZ6RepeatZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opIndexMFNfkZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarTokenZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda3TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarToken6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult4saveMFNaNbNdNiNfZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult5frontMFNdNfZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__ctorMFNaNbNcNiNfS3std5range13__T6RepeatTiZ6RepeatZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult6__initZ@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opIndexMFNfkZk@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult11DollarTokenZS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult7opSliceMFNaNbNiNfkkZS3std5range134__T4TakeTS3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResultZ4Take@Base 6
+ _D3std9algorithm9iteration87__T9MapResultS363std6random6rndGenFNcNdNfZ9__lambda4TS3std5range13__T6RepeatTiZ6RepeatZ9MapResult8popFrontMFNaNbNiNfZv@Base 6
+ _D3std9algorithm9searching12__ModuleInfoZ@Base 6
+ _D3std9algorithm9searching12__T7canFindZ20__T7canFindTAyhTAyaZ7canFindFNaNfAyhAyaZb@Base 6
+ _D3std9algorithm9searching12__T7canFindZ21__T7canFindTAyAaTAyaZ7canFindFNaNbNiNfAyAaAyaZb@Base 6
+ _D3std9algorithm9searching146__T4findVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ4findFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching159__T16simpleMindedFindVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZ16simpleMindedFindFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching166__T10countUntilVAyaa6_61203d3d2062TAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ10countUntilFNaNbNiNfAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZi@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxaTAywZ8skipOverFKAxaAywZ19__T9__lambda3TwTywZ9__lambda3FNaNbNiNfwywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxaTAywZ8skipOverFNaNfKAxaAywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxuTAywZ8skipOverFKAxuAywZ19__T9__lambda3TwTywZ9__lambda3FNaNbNiNfwywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxuTAywZ8skipOverFNaNfKAxuAywZb@Base 6
+ _D3std9algorithm9searching21__T8skipOverTAxwTAywZ8skipOverFNaNbNiNfKAxwAywZb@Base 6
+ _D3std9algorithm9searching26__T14balancedParensTAxaTaZ14balancedParensFNaNfAxaaakZb@Base 6
+ _D3std9algorithm9searching29__T5countVAyaa4_74727565TAyaZ5countFNaNiNfAyaZk@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAhTAhZ4findFNaNbNiNfAhAhZAh@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAyaTaZ4findFAyaaZ13trustedMemchrFNaNbNiNeKAyaKaZAya@Base 6
+ _D3std9algorithm9searching34__T4findVAyaa6_61203d3d2062TAyaTaZ4findFNaNfAyaaZAya@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ16__T5forceTAhTAaZ5forceFNaNbNiNeAaZAh@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFAyaAaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching35__T4findVAyaa6_61203d3d2062TAyaTAaZ4findFNaNbNiNfAyaAaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAhTAxaZ5forceFNaNbNiNeAxaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFAxaAyaZ17__T5forceTAxaTAhZ5forceFNaNbNiNeAhZAxa@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAxaTAyaZ4findFNaNbNiNfAxaAyaZAxa@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAhTAxaZ5forceFNaNbNiNeAxaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFAyaAxaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAxaZ4findFNaNbNiNfAyaAxaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFAyaAyaZ17__T5forceTAhTAyaZ5forceFNaNbNiNeAyaZAh@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFAyaAyaZ17__T5forceTAyaTAhZ5forceFNaNbNiNeAhZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyaTAyaZ4findFNaNbNiNfAyaAyaZAya@Base 6
+ _D3std9algorithm9searching36__T4findVAyaa6_61203d3d2062TAyhTAyaZ4findFNaNfAyhAyaZAyh@Base 6
+ _D3std9algorithm9searching37__T4findVAyaa6_61203d3d2062TAyAaTAyaZ4findFNaNbNiNfAyAaAyaZAyAa@Base 6
+ _D3std9algorithm9searching37__T5countVAyaa6_61203d3d2062TAyaTAyaZ5countFNaNbNiNfAyaAyaZk@Base 6
+ _D3std9algorithm9searching40__T10countUntilVAyaa6_61203d3d2062TAaTaZ10countUntilFNaNiNfAaaZi@Base 6
+ _D3std9algorithm9searching40__T10countUntilVAyaa6_61203d3d2062TAkTkZ10countUntilFNaNbNiNfAkkZi@Base 6
+ _D3std9algorithm9searching40__T8findSkipVAyaa6_61203d3d2062TAyaTAyaZ8findSkipFNaNbNiNfKAyaAyaZb@Base 6
+ _D3std9algorithm9searching41__T10startsWithVAyaa6_61203d3d2062TAhTAhZ10startsWithFNaNbNiNfAhAhZb@Base 6
+ _D3std9algorithm9searching41__T10startsWithVAyaa6_61203d3d2062TAxaTaZ10startsWithFNaNfAxaaZb@Base 6
+ _D3std9algorithm9searching41__T9findSplitVAyaa6_61203d3d2062TAyaTAyaZ9findSplitFNaNbNiNfAyaAyaZS3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAxaTAyaZ10startsWithFNaNbNiNfAxaAyaZb@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAyaTAyaZ10startsWithFNaNbNiNfAyaAyaZb@Base 6
+ _D3std9algorithm9searching43__T10startsWithVAyaa6_61203d3d2062TAyhTAyaZ10startsWithFNaNfAyhAyaZb@Base 6
+ _D3std9algorithm9searching44__T10countUntilVAyaa6_61203d3d2062TAAyaTAyaZ10countUntilFNaNbNiNfAAyaAyaZi@Base 6
+ _D3std9algorithm9searching44__T10countUntilVAyaa6_61203d3d2062TAyAaTAyaZ10countUntilFNaNbNiNfAyAaAyaZi@Base 6
+ _D3std9algorithm9searching47__T10startsWithVAyaa6_61203d3d2062TAxaTAyaTAyaZ10startsWithFNaNfAxaAyaAyaZk@Base 6
+ _D3std9algorithm9searching50__T3anyS39_D3std4path14isDirSeparatorFNaNbNiNfwZbZ12__T3anyTAxaZ3anyFNaNfAxaZb@Base 6
+ _D3std9algorithm9searching51__T10startsWithVAyaa6_61203d3d2062TAxaTAyaTAyaTAyaZ10startsWithFNaNfAxaAyaAyaAyaZk@Base 6
+ _D3std9algorithm9searching55__T4findS39_D3std4path14isDirSeparatorFNaNbNiNfwZbTAxaZ4findFNaNfAxaZAxa@Base 6
+ _D3std9algorithm9searching76__T10countUntilVAyaa11_615b305d203e2030783830TAS3std3uni17CodepointIntervalZ10countUntilFNaNbNiNfAS3std3uni17CodepointIntervalZi@Base 6
+ _D3std9algorithm9searching89__T4findVAyaa6_61203d3d2062TS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultTaZ4findFNaNfS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6ResultaZS3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result@Base 6
+ _D3std9algorithm9searching92__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTiZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitioniZi@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10LeapSecondTyiZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10LeapSecondyiZi@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTyiZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionyiZi@Base 6
+ _D3std9algorithm9searching93__T10countUntilVAyaa11_62203c20612e74696d6554TAyS3std8datetime13PosixTimeZone10TransitionTylZ10countUntilFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionylZi@Base 6
+ _D3std9container10binaryheap12__ModuleInfoZ@Base 6
+ _D3std9container12__ModuleInfoZ@Base 6
+ _D3std9container4util12__ModuleInfoZ@Base 6
+ _D3std9container5array12__ModuleInfoZ@Base 6
+ _D3std9container5dlist12__ModuleInfoZ@Base 6
+ _D3std9container5dlist6DRange4backMFNaNbNdNfZPS3std9container5dlist8BaseNode@Base 6
+ _D3std9container5dlist6DRange4saveMFNaNbNdNfZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange5emptyMxFNaNbNdNfZb@Base 6
+ _D3std9container5dlist6DRange5frontMFNaNbNdNfZPS3std9container5dlist8BaseNode@Base 6
+ _D3std9container5dlist6DRange6__ctorMFNaNbNcNfPS3std9container5dlist8BaseNodePS3std9container5dlist8BaseNodeZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange6__ctorMFNaNbNcNfPS3std9container5dlist8BaseNodeZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange6__initZ@Base 6
+ _D3std9container5dlist6DRange7popBackMFNaNbNfZv@Base 6
+ _D3std9container5dlist6DRange8popFrontMFNaNbNfZv@Base 6
+ _D3std9container5dlist8BaseNode6__initZ@Base 6
+ _D3std9container5dlist8BaseNode7connectFNaNbNfPS3std9container5dlist8BaseNodePS3std9container5dlist8BaseNodeZv@Base 6
+ _D3std9container5slist12__ModuleInfoZ@Base 6
+ _D3std9container6rbtree12__ModuleInfoZ@Base 6
+ _D3std9exception104__T11doesPointToTPyS3std8datetime13PosixTimeZone6TTInfoTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPyS3std8datetime13PosixTimeZone6TTInfoKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception104__T11doesPointToTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception105__T11doesPointToTAS3std8datetime13PosixTimeZone10LeapSecondTAS3std8datetime13PosixTimeZone10LeapSecondTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone10LeapSecondKxAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std9exception111__T11doesPointToTPxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception111__T11doesPointToTS3std8datetime13PosixTimeZone14TempTransitionTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxS3std8datetime13PosixTimeZone14TempTransitionKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTAS3std8datetime13PosixTimeZone14TempTransitionTAS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone14TempTransitionKxAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTPxS3std8datetime13PosixTimeZone14TransitionTypeTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPS3std8datetime13PosixTimeZone14TransitionTypeKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception115__T11doesPointToTkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki674Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki676Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki681Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki749Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki891Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki949Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki994Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T11doesPointToTAxkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxAkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1010Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1088Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1124Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1155Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki146Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki308Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki315Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki341Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki372Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki397Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki482Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T18isUnionAliasedImplTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception121__T12errnoEnforceTbVAyaa43_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f70726f636573732e64Vki2907Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception122__T11doesPointToTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception129__T11doesPointToTPxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception12__ModuleInfoZ@Base 6
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki385Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki455Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception144__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1588Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception14ErrnoException5errnoMFNdZk@Base 6
+ _D3std9exception14ErrnoException6__ctorMFNeAyaAyakZC3std9exception14ErrnoException@Base 6
+ _D3std9exception14ErrnoException6__initZ@Base 6
+ _D3std9exception14ErrnoException6__vtblZ@Base 6
+ _D3std9exception14ErrnoException7__ClassZ@Base 6
+ _D3std9exception14RangePrimitive6__initZ@Base 6
+ _D3std9exception14__T7enforceTbZ7enforceFNaNfbLC6object9ThrowableZb@Base 6
+ (optional)_D3std9exception158__T12errnoEnforceTbVAyaa62_2f686f6d652f7562756e74752f6763632f6763632d362d362e322e312f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ (optional)_D3std9exception158__T12errnoEnforceTiVAyaa62_2f686f6d652f7562756e74752f6763632f6763632d362d362e322e312f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfiLAyaZi@Base 6.2.1-1ubuntu2
+ (optional)_D3std9exception185__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa62_2f686f6d652f7562756e74752f6763632f6763632d362d362e322e312f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception207__T11doesPointToTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiKAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTkZ12assumeUniqueFNaNbNiKAkZAyk@Base 6
+ _D3std9exception25__T11doesPointToTAkTAkTvZ11doesPointToFNaNbNiNeKxAkKxAkZb@Base 6
+ _D3std9exception25__T7bailOutHTC9ExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTiZ7enforceFNaNfiLAxaAyakZi@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTkZ7enforceFNaNfkLAxaAyakZk@Base 6
+ _D3std9exception289__T11doesPointToTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception28__T7enforceHTC9ExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception297__T11doesPointToTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception29__T11doesPointToTAAyaTAAyaTvZ11doesPointToFNaNbNiNeKxAAyaKxAAyaZb@Base 6
+ _D3std9exception37__T16collectExceptionHTC9ExceptionTmZ16collectExceptionFNaNbNfLmZC9Exception@Base 6
+ _D3std9exception39__T7bailOutHTC3std4json13JSONExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception40__T11doesPointToTAyaTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio4FileZb@Base 6
+ _D3std9exception40__T7bailOutHTC4core4time13TimeExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception41__T18isUnionAliasedImplTS3std5stdio4FileZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception41__T7enforceHTC3std4json13JSONExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception41__T9enforceExHTC3std4json13JSONExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception42__T7enforceHTC4core4time13TimeExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception43__T7bailOutHTC3std3net4curl13CurlExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std3net4curl4CurlZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std4file8DirEntryZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T7enforceTPS4core3sys5posix5netdb7hostentZ7enforceFNaNfPS4core3sys5posix5netdb7hostentLC6object9ThrowableZPS4core3sys5posix5netdb7hostent@Base 6
+ _D3std9exception45__T11doesPointToTbTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception45__T7enforceHTC3std3net4curl13CurlExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTkZ9enforceExFNaNfkLAyaAyakZk@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTtTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxtKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T7enforceHTC3std3net4curl13CurlExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception47__T11doesPointToTAyaTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception47__T11doesPointToTPxvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception48__T18isUnionAliasedImplTS3std3net4curl3FTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T11doesPointToTbTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxbKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToThTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxhKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTiTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxiKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTkTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxkKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTlTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxlKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTmTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxmKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTtTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxtKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4HTTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4SMTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAhZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAvZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T7bailOutHTC3std3net4curl20CurlTimeoutExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception51__T11doesPointToTAyaTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFxAaZvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFkkkkZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTwTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxwKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception52__T18isUnionAliasedImplTS3std4file15DirIteratorImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception52__T7enforceHTC3std3net4curl20CurlTimeoutExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception53__T11doesPointToTDFkkkkZiTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTDFkkkkZiTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTHAyaxAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxHAyaAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTS3std5stdio4FileTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio4FileZb@Base 6
+ _D3std9exception53__T7bailOutHTC3std11concurrency19TidMissingExceptionZ7bailOutFAyakxAaZv@Base 6
+ _D3std9exception54__T11doesPointToTAyaTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception54__T7enforceHTC9ExceptionTPOS4core4stdc5stdio8_IO_FILEZ7enforceFNaNfPOS4core4stdc5stdio8_IO_FILELAxaAyakZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception55__T18isUnionAliasedImplTS3std5stdio17LockingTextReaderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception55__T7enforceHTC3std11concurrency19TidMissingExceptionTbZ7enforceFbLAxaAyakZb@Base 6
+ _D3std9exception56__T18isUnionAliasedImplTS3std3net4curl4HTTP10StatusLineZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception57__T18isUnionAliasedImplTS4core3sys5posix3sys4stat6stat_tZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception60__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio4FileZb@Base 6
+ _D3std9exception63__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception63__T7enforceHTC3std4json13JSONExceptionTPNgS3std4json9JSONValueZ7enforceFNaNfPNgS3std4json9JSONValueLAxaAyakZPNgS3std4json9JSONValue@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTE3std4file8SpanModeTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxE3std4file8SpanModeKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std3net4curl3FTP4ImplTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl3FTP4ImplKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std4file8DirEntryTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std4file8DirEntryKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std5stdio4FileTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception67__T11doesPointToTlTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxlKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4HTTP4ImplTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP4ImplKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4SMTP4ImplTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4SMTP4ImplKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception70__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception70__T18isUnionAliasedImplTS3std8datetime13PosixTimeZone14TempTransitionZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception71__T11doesPointToTE3std3net4curl4HTTP6MethodTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxE3std3net4curl4HTTP6MethodKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception71__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception74__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception75__T11doesPointToTS3std4file15DirIteratorImplTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNeKxS3std4file15DirIteratorImplKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception76__T11doesPointToTS3std3net4curl4HTTP10StatusLineTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP10StatusLineKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTDFS3std3net4curl4HTTP10StatusLineZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFS3std3net4curl4HTTP10StatusLineZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTS4core3sys5posix3sys4stat6stat_tTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS4core3sys5posix3sys4stat6stat_tKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception81__T11doesPointToTS3std5stdio17LockingTextReaderTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio17LockingTextReaderKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception81__T18isUnionAliasedImplTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception93__T11doesPointToTAS3std5regex8internal2ir10NamedGroupTAS3std5regex8internal2ir10NamedGroupTvZ11doesPointToFNaNbNiNeKxAS3std5regex8internal2ir10NamedGroupKxAS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std9exception93__T7enforceHTC9ExceptionTPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZ7enforceFNaNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeLAxaAyakZPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std9exception94__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception96__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception96__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception99__T18isUnionAliasedImplTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9outbuffer12__ModuleInfoZ@Base 6
+ _D3std9outbuffer9OutBuffer11__invariantMxFZv@Base 6
+ _D3std9outbuffer9OutBuffer12__invariant1MxFZv@Base 6
+ _D3std9outbuffer9OutBuffer5fill0MFNaNbNfkZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeAxwZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNedZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeeZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNefZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNekZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNemZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNetZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNeuZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNexAaZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNexAuZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfAxhZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfC3std9outbuffer9OutBufferZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfaZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfgZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfhZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfiZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNflZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfsZv@Base 6
+ _D3std9outbuffer9OutBuffer5writeMFNaNbNfwZv@Base 6
+ _D3std9outbuffer9OutBuffer6__ctorMFNaNbNfZC3std9outbuffer9OutBuffer@Base 6
+ _D3std9outbuffer9OutBuffer6__initZ@Base 6
+ _D3std9outbuffer9OutBuffer6__vtblZ@Base 6
+ _D3std9outbuffer9OutBuffer6align2MFNaNbNfZv@Base 6
+ _D3std9outbuffer9OutBuffer6align4MFNaNbNfZv@Base 6
+ _D3std9outbuffer9OutBuffer6printfMFNeAyaYv@Base 6
+ _D3std9outbuffer9OutBuffer6spreadMFNaNbNfkkZv@Base 6
+ _D3std9outbuffer9OutBuffer7__ClassZ@Base 6
+ _D3std9outbuffer9OutBuffer7reserveMFNaNbNekZv@Base 6
+ _D3std9outbuffer9OutBuffer7toBytesMFNaNbNfZAh@Base 6
+ _D3std9outbuffer9OutBuffer7vprintfMFNbNeAyaS3gcc8builtins9__va_listZv@Base 6.2.1-1ubuntu2
+ _D3std9outbuffer9OutBuffer8toStringMxFNaNbNfZAya@Base 6
+ _D3std9outbuffer9OutBuffer9alignSizeMFNaNbNfkZv@Base 6
+ _D3std9stdiobase12__ModuleInfoZ@Base 6
+ _D3std9stdiobase18_sharedStaticCtor1FZv@Base 6
+ _D3std9typetuple12__ModuleInfoZ@Base 6
+ _D401TypeInfo_S3std5range365__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1703std3uni124__T14findUnicodeSetS99_D3std8internal14unicode_tables6blocks3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D403TypeInfo_S3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D403TypeInfo_S3std5range189__T5chainTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplTS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ5chainFS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplS3std5range23__T10OnlyResultTaHVki1Z10OnlyResultS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ6Result6__initZ@Base 6
+ _D404TypeInfo_S3std5range368__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1733std3uni127__T14findUnicodeSetS101_D3std8internal14unicode_tables8uniProps3tabFNaNdNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D407TypeInfo_S3std5range371__T11SortedRangeTS3std9algorithm9iteration135__T9MapResultS683std10functional41__T8unaryFunVAyaa6_612e6e616d65VAyaa1_61Z8unaryFunTAyS3std8internal14unicode_tables15UnicodePropertyZ9MapResultS1763std3uni130__T14findUnicodeSetS104_D3std8internal14unicode_tables7scripts3tabFNaNbNdNiNfZAyS3std8internal14unicode_tables15UnicodePropertyTaZ14findUnicodeSetFNaNexAaZ9__lambda2Z11SortedRange6__initZ@Base 6
+ _D40TypeInfo_C3std11concurrency11IsGenerator6__initZ@Base 6
+ _D40TypeInfo_E3std3uni20UnicodeDecomposition6__initZ@Base 6
+ _D40TypeInfo_E3std6socket17SocketOptionLevel6__initZ@Base 6
+ _D40TypeInfo_E3std6traits17FunctionAttribute6__initZ@Base 6
+ _D40TypeInfo_E3std7numeric16CustomFloatFlags6__initZ@Base 6
+ _D40TypeInfo_E3std8encoding15Windows1252Char6__initZ@Base 6
+ _D40TypeInfo_E3std9exception14RangePrimitive6__initZ@Base 6
+ _D40TypeInfo_S3etc1c7sqlite314sqlite3_module6__initZ@Base 6
+ _D40TypeInfo_S3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D40TypeInfo_xC3std11concurrency10MessageBox6__initZ@Base 6
+ _D41TypeInfo_AE3std8encoding15Windows1252Char6__initZ@Base 6
+ _D41TypeInfo_E3etc1c4curl18CurlFInfoFlagKnown6__initZ@Base 6
+ _D41TypeInfo_E3std8datetime16AllowDayOverflow6__initZ@Base 6
+ _D41TypeInfo_HAyaDFC3std3xml13ElementParserZv6__initZ@Base 6
+ _D41TypeInfo_S3std11parallelism12AbstractTask6__initZ@Base 6
+ _D41TypeInfo_S3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D41TypeInfo_S3std4math20FloatingPointControl6__initZ@Base 6
+ _D41TypeInfo_S3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D41TypeInfo_xS3std3net4curl4HTTP10StatusLine6__initZ@Base 6
+ _D426TypeInfo_S3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__initZ@Base 6
+ _D427TypeInfo_xS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6Result6__initZ@Base 6
+ _D42TypeInfo_AC3std3xml21ProcessingInstruction6__initZ@Base 6
+ _D42TypeInfo_AS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D42TypeInfo_E3std5regex8internal2ir9RegexInfo6__initZ@Base 6
+ _D42TypeInfo_HaE3std6traits17FunctionAttribute6__initZ@Base 6
+ _D42TypeInfo_S3std3net4curl12__T4PoolTAhZ4Pool6__initZ@Base 6
+ _D42TypeInfo_S3std5range13__T6RepeatTiZ6Repeat6__initZ@Base 6
+ _D42TypeInfo_xS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D42TypeInfo_xS3std3uni21DecompressedIntervals6__initZ@Base 6
+ _D42TypeInfo_xS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D42TypeInfo_xS4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D43TypeInfo_AxS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D43TypeInfo_E3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D43TypeInfo_E3std9algorithm10comparison6EditOp6__initZ@Base 6
+ _D43TypeInfo_FS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D43TypeInfo_PxS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D43TypeInfo_S3std1c5linux5linux13struct_stat646__initZ@Base 6
+ _D43TypeInfo_S3std5range14__T6ChunksTAhZ6Chunks6__initZ@Base 6
+ _D43TypeInfo_xAS3std5regex8internal2ir8Bytecode6__initZ@Base 6
+ _D43TypeInfo_xPS3std11parallelism12AbstractTask6__initZ@Base 6
+ _D44TypeInfo_DFS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D44TypeInfo_E3std6traits21ParameterStorageClass6__initZ@Base 6
+ _D44TypeInfo_E3std9algorithm7sorting10SortOutput6__initZ@Base 6
+ _D44TypeInfo_E3std9algorithm9searching9OpenRight6__initZ@Base 6
+ _D44TypeInfo_S3etc1c7sqlite318sqlite3_index_info6__initZ@Base 6
+ _D44TypeInfo_S3etc1c7sqlite318sqlite3_io_methods6__initZ@Base 6
+ _D44TypeInfo_S3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D44TypeInfo_S3std5stdio4File17LockingTextWriter6__initZ@Base 6
+ _D44TypeInfo_xC3std11concurrency14LinkTerminated6__initZ@Base 6
+ _D44TypeInfo_xE3std3net7isemail15EmailStatusCode6__initZ@Base 6
+ _D45TypeInfo_AS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D45TypeInfo_E3std5regex8internal2ir11RegexOption6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_mem_methods6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_pcache_page6__initZ@Base 6
+ _D45TypeInfo_S3etc1c7sqlite319sqlite3_vtab_cursor6__initZ@Base 6
+ _D45TypeInfo_S3std3net4curl20AsyncChunkInputRange6__initZ@Base 6
+ _D45TypeInfo_S3std7numeric14__T6StrideTAfZ6Stride6__initZ@Base 6
+ _D45TypeInfo_S3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D45TypeInfo_S3std8typecons14__T5TupleTbTiZ5Tuple6__initZ@Base 6
+ _D45TypeInfo_S3std8typecons14__T5TupleTkTkZ5Tuple6__initZ@Base 6
+ _D45TypeInfo_xC3std11concurrency15OwnerTerminated6__initZ@Base 6
+ _D45TypeInfo_xDFS3std3net4curl4HTTP10StatusLineZv6__initZ@Base 6
+ _D45TypeInfo_xS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_AxS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_E3std11parallelism8TaskPool9PoolState6__initZ@Base 6
+ _D46TypeInfo_S3std3uni7unicode18hangulSyllableType6__initZ@Base 6
+ _D46TypeInfo_S3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D46TypeInfo_S3std6traits23__InoutWorkaroundStruct6__initZ@Base 6
+ _D46TypeInfo_S3std7complex14__T7ComplexTeZ7Complex6__initZ@Base 6
+ _D46TypeInfo_S3std8internal14unicode_tables6blocks6__initZ@Base 6
+ _D46TypeInfo_S3std8internal14unicode_tables6hangul6__initZ@Base 6
+ _D46TypeInfo_xAS3std5regex8internal2ir10NamedGroup6__initZ@Base 6
+ _D46TypeInfo_yS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D47TypeInfo_AC3std11parallelism17ParallelismThread6__initZ@Base 6
+ _D47TypeInfo_AS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D47TypeInfo_E3std8internal4test10dummyrange6Length6__initZ@Base 6
+ _D47TypeInfo_E3std9algorithm8mutation12SwapStrategy6__initZ@Base 6
+ _D47TypeInfo_PyS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D47TypeInfo_S3etc1c7sqlite321sqlite3_mutex_methods6__initZ@Base 6
+ _D47TypeInfo_S3std5array16__T8AppenderTAaZ8Appender6__initZ@Base 6
+ _D47TypeInfo_S3std5array16__T8AppenderTAhZ8Appender6__initZ@Base 6
+ _D47TypeInfo_S3std6traits15__T8DemangleTkZ8Demangle6__initZ@Base 6
+ _D47TypeInfo_S3std8bitmanip14__T7BitsSetTkZ7BitsSet6__initZ@Base 6
+ _D47TypeInfo_S3std8internal14unicode_tables7scripts6__initZ@Base 6
+ _D47TypeInfo_S3std8typecons16__T5TupleTiTAyaZ5Tuple6__initZ@Base 6
+ _D47TypeInfo_S3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D47TypeInfo_xS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_APyS3std8datetime13PosixTimeZone6TTInfo6__initZ@Base 6
+ _D48TypeInfo_AS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D48TypeInfo_AxS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_E3std4uuid20UUIDParsingException6Reason6__initZ@Base 6
+ _D48TypeInfo_S3etc1c7sqlite322sqlite3_pcache_methods6__initZ@Base 6
+ _D48TypeInfo_S3etc1c7sqlite322sqlite3_rtree_geometry6__initZ@Base 6
+ _D48TypeInfo_S3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAxaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAyaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAyuZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTAywZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std5array17__T8AppenderTyAaZ8Appender6__initZ@Base 6
+ _D48TypeInfo_S3std8internal14unicode_tables8uniProps6__initZ@Base 6
+ _D48TypeInfo_xAS3std4file15DirIteratorImpl9DirHandle6__initZ@Base 6
+ _D48TypeInfo_xC3std12experimental6logger4core6Logger6__initZ@Base 6
+ _D48TypeInfo_xS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_AxS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_E3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D49TypeInfo_E3std8internal4test10dummyrange8ReturnBy6__initZ@Base 6
+ _D49TypeInfo_E3std8typecons24RefCountedAutoInitialize6__initZ@Base 6
+ _D49TypeInfo_S3etc1c7sqlite323sqlite3_pcache_methods26__initZ@Base 6
+ _D49TypeInfo_S3std12experimental6logger4core8MsgRange6__initZ@Base 6
+ _D49TypeInfo_S3std3uni18simpleCaseFoldingsFNewZ5Range6__initZ@Base 6
+ _D49TypeInfo_S3std5array18__T8AppenderTAAyaZ8Appender6__initZ@Base 6
+ _D49TypeInfo_S3std5regex18__T8CapturesTAaTkZ8Captures6__initZ@Base 6
+ _D49TypeInfo_S3std6stream6Stream6toHashMFNeZ8resUnion6__initZ@Base 6
+ _D49TypeInfo_S3std8datetime24ComparingBenchmarkResult6__initZ@Base 6
+ _D49TypeInfo_S3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D49TypeInfo_S3std8internal4math11biguintcore7BigUint6__initZ@Base 6
+ _D49TypeInfo_S3std8typecons18__T5TupleTeTeTeTeZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_xAS3std8typecons16__T5TupleTkTkTkZ5Tuple6__initZ@Base 6
+ _D49TypeInfo_xS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D4core4stdc6stdarg11__T6va_argZ6va_argFNaNbNiKS3gcc8builtins9__va_listC8TypeInfoPvZv@Base 6.2.1-1ubuntu2
+ _D4core4time12TickDuration22__T8opBinaryVAyaa1_2bZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration25__T10opOpAssignVAyaa1_2bZ10opOpAssignMFNaNbNcNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_6d73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T18getUnitsFromHNSecsVAyaa6_686e73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7573656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa6_686e73656373VAyaa4_64617973Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time48__T7convertVAyaa4_64617973VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_686f757273VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7573656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_686f757273Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa5_686f757273VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_6d696e75746573Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time7FracSec28__T4fromVAyaa6_686e73656373Z4fromFNaNflZS4core4time7FracSec@Base 6
+ _D4core4time8Duration27__T5totalVAyaa5_6d73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration29__T5totalVAyaa6_686e73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration31__T5totalVAyaa7_7365636f6e6473Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration43__T8opBinaryVAyaa1_2bTS4core4time8DurationZ8opBinaryMxFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration44__T8opBinaryVAyaa1_2bTxS4core4time8DurationZ8opBinaryMxFNaNbNiNfxS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration44__T8opBinaryVAyaa1_2bTyS4core4time8DurationZ8opBinaryMxFNaNbNiNfyS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z14__T5splitTiTiZ5splitMxFNaNbNiNfJiJiZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa5_686f757273VAyaa7_6d696e75746573Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z14__T5splitTiTiZ5splitMxFNaNbNiNfJiJiZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_7573656373Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration48__T8opBinaryVAyaa1_2dTS4core4time12TickDurationZ8opBinaryMxFNaNbNiNfS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration51__T10opOpAssignVAyaa1_2dTS4core4time12TickDurationZ10opOpAssignMFNaNbNcNiNfxS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration54__T13opBinaryRightVAyaa1_2bTS4core4time12TickDurationZ13opBinaryRightMxFNaNbNiNfS4core4time12TickDurationZS4core4time8Duration@Base 6
+ _D4core6atomic122__T11atomicStoreVE4core6atomic11MemoryOrderi5TE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateZ11atomicStoreFNaNbNiKOE3std11parallelism8TaskPool9PoolStateE3std11parallelism8TaskPool9PoolStateZv@Base 6
+ _D4core6atomic122__T3casTE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateTE3std11parallelism8TaskPool9PoolStateZ3casFNaNbNiPOE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D4core6atomic125__T11atomicStoreVE4core6atomic11MemoryOrderi3TC3std12experimental6logger4core6LoggerTOC3std12experimental6logger4core6LoggerZ11atomicStoreFNaNbNiKOC3std12experimental6logger4core6LoggerOC3std12experimental6logger4core6LoggerZv@Base 6
+ _D4core6atomic128__T11atomicStoreVE4core6atomic11MemoryOrderi3TE3std12experimental6logger4core8LogLevelTE3std12experimental6logger4core8LogLevelZ11atomicStoreFNaNbNiKOE3std12experimental6logger4core8LogLevelE3std12experimental6logger4core8LogLevelZv@Base 6
+ _D4core6atomic128__T7casImplTE3std11parallelism8TaskPool9PoolStateTxE3std11parallelism8TaskPool9PoolStateTxE3std11parallelism8TaskPool9PoolStateZ7casImplFNaNbNiPOE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStatexE3std11parallelism8TaskPool9PoolStateZb@Base 6
+ _D4core6atomic14__T3casTbTbTbZ3casFNaNbNiPObxbxbZb@Base 6
+ _D4core6atomic20__T7casImplTbTxbTxbZ7casImplFNaNbNiPObxbxbZb@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi2TbZ10atomicLoadFNaNbNiKOxbZb@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5ThZ10atomicLoadFNaNbNiKOxhZh@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5TkZ10atomicLoadFNaNbNiKOxkZk@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi3TbTbZ11atomicStoreFNaNbNiKObbZv@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi5ThThZ11atomicStoreFNaNbNiKOhhZv@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi5TkTkZ11atomicStoreFNaNbNiKOkkZv@Base 6
+ _D4core6atomic58__T3casTC4core4sync5mutex5MutexTnTC4core4sync5mutex5MutexZ3casFNaNbNiPOC4core4sync5mutex5MutexOxnOC4core4sync5mutex5MutexZb@Base 6
+ _D4core6atomic65__T7casImplTC4core4sync5mutex5MutexTOxnTOC4core4sync5mutex5MutexZ7casImplFNaNbNiPOC4core4sync5mutex5MutexOxnOC4core4sync5mutex5MutexZb@Base 6
+ _D4core6atomic69__T10atomicLoadVE4core6atomic11MemoryOrderi2TC4core4sync5mutex5MutexZ10atomicLoadFNaNbNiKOxC4core4sync5mutex5MutexZC4core4sync5mutex5Mutex@Base 6
+ _D4core6atomic83__T10atomicLoadVE4core6atomic11MemoryOrderi5TE3std11parallelism8TaskPool9PoolStateZ10atomicLoadFNaNbNiKOxE3std11parallelism8TaskPool9PoolStateZE3std11parallelism8TaskPool9PoolState@Base 6
+ _D4core6atomic84__T10atomicLoadVE4core6atomic11MemoryOrderi2TC3std12experimental6logger4core6LoggerZ10atomicLoadFNaNbNiKOxC3std12experimental6logger4core6LoggerZC3std12experimental6logger4core6Logger@Base 6
+ _D4core6atomic86__T10atomicLoadVE4core6atomic11MemoryOrderi2TE3std12experimental6logger4core8LogLevelZ10atomicLoadFNaNbNiKOxE3std12experimental6logger4core8LogLevelZE3std12experimental6logger4core8LogLevel@Base 6
+ _D4core8internal4hash15__T6hashOfTAxaZ6hashOfFNaNbNfKAxakZk@Base 6
+ _D4core8internal4hash15__T6hashOfTAyaZ6hashOfFNaNbNfKAyakZk@Base 6
+ _D4core8internal7convert15__T7toUbyteTxaZ7toUbyteFNaNbNiNeAxaZAxh@Base 6
+ _D4core8internal7convert15__T7toUbyteTyaZ7toUbyteFNaNbNiNeAyaZAxh@Base 6
+ _D50TypeInfo_E3std8internal4test10dummyrange9RangeType6__initZ@Base 6
+ _D50TypeInfo_PxS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D50TypeInfo_S3etc1c7sqlite324sqlite3_rtree_query_info6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTbVki1Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTkVki7Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std3uni20__T9BitPackedTkVki8Z9BitPacked6__initZ@Base 6
+ _D50TypeInfo_S3std5regex19__T8CapturesTAxaTkZ8Captures6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D50TypeInfo_S3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D50TypeInfo_xE3std12experimental6logger4core8LogLevel6__initZ@Base 6
+ _D50TypeInfo_xPS3std3net4curl12__T4PoolTAhZ4Pool5Entry6__initZ@Base 6
+ _D50TypeInfo_xS3std5regex18__T8CapturesTAaTkZ8Captures6__initZ@Base 6
+ _D50TypeInfo_yS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10TempTTInfo6__initZ@Base 6
+ _D51TypeInfo_AS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D51TypeInfo_AyS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki11Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki12Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki13Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki14Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki15Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std3uni21__T9BitPackedTkVki16Z9BitPacked6__initZ@Base 6
+ _D51TypeInfo_S3std5range13__T4iotaTkTkZ4iotaFkkZ6Result6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii160Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D51TypeInfo_S3std7variant18__T8VariantNVki16Z8VariantN6__initZ@Base 6.2.1-1ubuntu2
+ _D51TypeInfo_xS3std5regex19__T8CapturesTAxaTkZ8Captures6__initZ@Base 6
+ _D51TypeInfo_xS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_xS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D51TypeInfo_yS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D51TypeInfo_yS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_AxS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_AxS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_AyS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_AyS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits6__initZ@Base 6
+ _D52TypeInfo_S3std5array16__T8AppenderTAaZ8Appender4Data6__initZ@Base 6
+ _D52TypeInfo_S3std5array16__T8AppenderTAhZ8Appender4Data6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D52TypeInfo_S3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D52TypeInfo_S3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D52TypeInfo_xAS3std8datetime13PosixTimeZone10LeapSecond6__initZ@Base 6
+ _D52TypeInfo_xAS3std8datetime13PosixTimeZone10Transition6__initZ@Base 6
+ _D52TypeInfo_xAyS3std8internal14unicode_tables9CompEntry6__initZ@Base 6
+ _D52TypeInfo_xS3std7variant18__T8VariantNVki16Z8VariantN6__initZ@Base 6.2.1-1ubuntu2
+ _D53TypeInfo_AS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAxaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAyaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAyuZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTAywZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5array17__T8AppenderTyAaZ8Appender4Data6__initZ@Base 6
+ _D53TypeInfo_S3std5regex8internal12backtracking9CtContext6__initZ@Base 6
+ _D53TypeInfo_S3std6format18__T10FormatSpecTaZ10FormatSpec6__initZ@Base 6
+ _D53TypeInfo_S3std8typecons22__T5TupleTAyaTAyaTAyaZ5Tuple6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5InputTaZ5Input6__initZ@Base 6
+ _D53TypeInfo_xS3std5regex8internal2ir12__T5RegexTaZ5Regex6__initZ@Base 6
+ _D54TypeInfo_AxS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D54TypeInfo_G3S3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits6__initZ@Base 6
+ _D54TypeInfo_S3std5array18__T8AppenderTAAyaZ8Appender4Data6__initZ@Base 6
+ _D54TypeInfo_S3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D54TypeInfo_S3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D54TypeInfo_S3std8internal14unicode_tables13FullCaseEntry6__initZ@Base 6
+ _D54TypeInfo_xAS3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D55TypeInfo_AS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D55TypeInfo_PS3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D55TypeInfo_S3std5range13__T6RepeatTiZ6Repeat11DollarToken6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPbZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPiZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPkZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_S3std8typecons24__T5TupleTC8TypeInfoTPvZ5Tuple6__initZ@Base 6
+ _D55TypeInfo_xG3S3std5regex8internal2ir12__T5GroupTkZ5Group6__initZ@Base 6
+ _D55TypeInfo_xS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D56TypeInfo_APS3std8datetime13PosixTimeZone14TransitionType6__initZ@Base 6
+ _D56TypeInfo_AxS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D56TypeInfo_E3std7variant18__T8VariantNVki16Z8VariantN4OpID6__initZ@Base 6.2.1-1ubuntu2
+ _D56TypeInfo_S3std12experimental6logger4core6Logger8LogEntry6__initZ@Base 6
+ _D56TypeInfo_S3std5range14__T6ChunksTAhZ6Chunks11DollarToken6__initZ@Base 6
+ _D56TypeInfo_S3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D56TypeInfo_S3std8internal14unicode_tables15SimpleCaseEntry6__initZ@Base 6
+ _D56TypeInfo_S3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D56TypeInfo_xAS3std8datetime13PosixTimeZone14TempTransition6__initZ@Base 6
+ _D57TypeInfo_S3std3net4curl19__T11CurlMessageTbZ11CurlMessage6__initZ@Base 6
+ _D57TypeInfo_S3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6__initZ@Base 6
+ _D57TypeInfo_xS3std5regex8internal6parser12__T5StackTkZ5Stack6__initZ@Base 6
+ _D57TypeInfo_yS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D581TypeInfo_S3std9algorithm9iteration270__T6joinerTS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6joinerFS3std9algorithm9iteration220__T9MapResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda2TS3std9algorithm9iteration112__T12FilterResultS483std8bitmanip8BitArray7bitsSetMxFNbNdZ9__lambda1TS3std5range13__T4iotaTkTkZ4iotaFkkZ6ResultZ12FilterResultZ9MapResultZ6Result6__initZ@Base 6
+ _D58TypeInfo_AyS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D58TypeInfo_E3std8typecons28__T4FlagVAyaa6_756e73616665Z4Flag6__initZ@Base 6
+ _D58TypeInfo_xS3std5range23__T10OnlyResultTaHVki1Z10OnlyResult6__initZ@Base 6
+ _D59TypeInfo_S3std3net4curl21__T11CurlMessageTAyhZ11CurlMessage6__initZ@Base 6
+ _D59TypeInfo_xAyS3std8internal14unicode_tables15UnicodeProperty6__initZ@Base 6
+ _D60TypeInfo_E3std3net4curl20AsyncChunkInputRange8__mixin55State6__initZ@Base 6
+ _D60TypeInfo_S3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D60TypeInfo_S3std5regex8internal6parser15__T6ParserTAyaZ6Parser6__initZ@Base 6
+ _D60TypeInfo_S3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D61TypeInfo_S3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D61TypeInfo_S3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D61TypeInfo_S3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTaZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTbZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperThZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTiZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTkZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTlZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTmZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_S3std8bitmanip21__T13EndianSwapperTtZ13EndianSwapper6__initZ@Base 6
+ _D61TypeInfo_xE3std3net4curl20AsyncChunkInputRange8__mixin55State6__initZ@Base 6
+ _D61TypeInfo_xS3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D62TypeInfo_AS3std5regex8internal12backtracking9CtContext7CtState6__initZ@Base 6
+ _D62TypeInfo_PxS3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D62TypeInfo_S3std8bitmanip22__T13EndianSwapperTxkZ13EndianSwapper6__initZ@Base 6
+ _D62TypeInfo_xPS3std5regex8internal8thompson13__T6ThreadTkZ6Thread6__initZ@Base 6
+ _D62TypeInfo_xS3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray6__initZ@Base 6
+ _D63TypeInfo_S3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D64TypeInfo_E3std8typecons34__T4FlagVAyaa9_706970654f6e506f70Z4Flag6__initZ@Base 6
+ _D64TypeInfo_S3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D64TypeInfo_S3std7variant18__T8VariantNVki16Z8VariantN11SizeChecker6__initZ@Base 6.2.1-1ubuntu2
+ _D64TypeInfo_S3std8typecons33__T5TupleTC14TypeInfo_ArrayTPAyhZ5Tuple6__initZ@Base 6
+ _D64TypeInfo_xS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr6__initZ@Base 6
+ _D65TypeInfo_S3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D65TypeInfo_S3std8typecons34__T5TupleTC14TypeInfo_ArrayTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D65TypeInfo_S3std8typecons34__T5TupleTC14TypeInfo_ClassTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D65TypeInfo_xS3std5regex8internal2ir12__T5InputTaZ5Input10BackLooper6__initZ@Base 6
+ _D66TypeInfo_S3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D66TypeInfo_S3std5regex8internal2ir19__T11StaticRegexTaZ11StaticRegex6__initZ@Base 6
+ _D66TypeInfo_S3std8typecons35__T5TupleTC15TypeInfo_StructTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D66TypeInfo_S3std8typecons35__T5TupleTC18TypeInfo_InvariantTPhZ5Tuple6__initZ@Base 6
+ _D66TypeInfo_xS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender6__initZ@Base 6
+ _D670TypeInfo_S3std5range322__T10roundRobinTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultTS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ10roundRobinFS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b305dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultS3std9algorithm9iteration114__T9MapResultS643std10functional37__T8unaryFunVAyaa4_615b315dVAyaa1_61Z8unaryFunTS3std3uni21DecompressedIntervalsZ9MapResultZ6Result6__initZ@Base 6
+ _D67TypeInfo_AS3std12experimental6logger11multilogger16MultiLoggerEntry6__initZ@Base 6
+ _D67TypeInfo_S3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D67TypeInfo_S3std3uni38__T8CowArrayTS3std3uni13ReallocPolicyZ8CowArray6__initZ@Base 6
+ _D67TypeInfo_S3std5range14__T5retroTAxhZ5retroFAxhZ11__T6ResultZ6Result6__initZ@Base 6
+ _D67TypeInfo_S3std5range14__T5retroTAyaZ5retroFAyaZ11__T6ResultZ6Result6__initZ@Base 6
+ _D68TypeInfo_xS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D69TypeInfo_E3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D69TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTdZ9floorImplFNaNbNiNexdZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTeZ9floorImplFNaNbNiNexeZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std4math16__T9floorImplTfZ9floorImplFNaNbNiNexfZ9floatBits6__initZ@Base 6
+ _D69TypeInfo_S3std8typecons38__T5TupleTC18TypeInfo_InvariantTPG16hZ5Tuple6__initZ@Base 6.2.1-1ubuntu2
+ _D69TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info21sqlite3_index_orderby6__initZ@Base 6
+ _D6object102__T11_trustedDupTS3std8datetime13PosixTimeZone10LeapSecondTyS3std8datetime13PosixTimeZone10LeapSecondZ11_trustedDupFNaNbNeAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object102__T11_trustedDupTS3std8datetime13PosixTimeZone10TransitionTyS3std8datetime13PosixTimeZone10TransitionZ11_trustedDupFNaNbNeAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object10__T3dupTaZ3dupFNaNbNdNfAxaZAa@Base 6
+ _D6object10__T3dupThZ3dupFNaNbNdNfAxhZAh@Base 6
+ _D6object10__T3dupTkZ3dupFNaNbNdNfAxkZAk@Base 6
+ _D6object11__T4idupTaZ4idupFNaNbNdNfAaZAya@Base 6
+ _D6object12__T3dupTAyaZ3dupFNaNbNdNfAxAyaZAAya@Base 6
+ _D6object12__T3getTkTkZ3getFNaNfNgHkkkLNgkZNgk@Base 6
+ _D6object12__T4idupTxaZ4idupFNaNbNdNfAxaZAya@Base 6
+ _D6object12__T4idupTxhZ4idupFNaNbNdNfAxhZAyh@Base 6
+ _D6object12__T4idupTxuZ4idupFNaNbNdNfAxuZAyu@Base 6
+ _D6object12__T4idupTxwZ4idupFNaNbNdNfAxwZAyw@Base 6
+ _D6object14__T4_dupTaTyaZ4_dupFNaNbAaZAya@Base 6
+ _D6object14__T4_dupTxaTaZ4_dupFNaNbAxaZAa@Base 6
+ _D6object14__T4_dupTxhThZ4_dupFNaNbAxhZAh@Base 6
+ _D6object14__T4_dupTxkTkZ4_dupFNaNbAxkZAk@Base 6
+ _D6object14__T7_rawDupTaZ7_rawDupFNaNbANgaZANga@Base 6
+ _D6object14__T7_rawDupThZ7_rawDupFNaNbANghZANgh@Base 6
+ _D6object14__T7_rawDupTkZ7_rawDupFNaNbANgkZANgk@Base 6
+ _D6object14__T7_rawDupTuZ7_rawDupFNaNbANguZANgu@Base 6
+ _D6object14__T7_rawDupTwZ7_rawDupFNaNbANgwZANgw@Base 6
+ _D6object14__T7reserveTaZ7reserveFNaNbNeKAakZk@Base 6
+ _D6object15__T4_dupTxaTyaZ4_dupFNaNbAxaZAya@Base 6
+ _D6object15__T4_dupTxhTyhZ4_dupFNaNbAxhZAyh@Base 6
+ _D6object15__T4_dupTxuTyuZ4_dupFNaNbAxuZAyu@Base 6
+ _D6object15__T4_dupTxwTywZ4_dupFNaNbAxwZAyw@Base 6
+ _D6object15__T6hashOfTAxaZ6hashOfFNaNbNfKAxakZk@Base 6
+ _D6object15__T6hashOfTAyaZ6hashOfFNaNbNfKAyakZk@Base 6
+ _D6object15__T8capacityTaZ8capacityFNaNbNdAaZk@Base 6
+ _D6object15__T8capacityThZ8capacityFNaNbNdAhZk@Base 6
+ _D6object15__T8capacityTiZ8capacityFNaNbNdAiZk@Base 6
+ _D6object16__T7_rawDupTAyaZ7_rawDupFNaNbANgAyaZANgAya@Base 6
+ _D6object17__T8capacityTAyaZ8capacityFNaNbNdAAyaZk@Base 6
+ _D6object18__T4_dupTxAyaTAyaZ4_dupFNaNbAxAyaZAAya@Base 6
+ _D6object19__T11_doPostblitTaZ11_doPostblitFNaNbNiNfAaZv@Base 6
+ _D6object19__T11_doPostblitThZ11_doPostblitFNaNbNiNfAhZv@Base 6
+ _D6object19__T11_doPostblitTkZ11_doPostblitFNaNbNiNfAkZv@Base 6
+ _D6object20__T11_doPostblitTyaZ11_doPostblitFNaNbNiNfAyaZv@Base 6
+ _D6object20__T11_doPostblitTyhZ11_doPostblitFNaNbNiNfAyhZv@Base 6
+ _D6object20__T11_doPostblitTyuZ11_doPostblitFNaNbNiNfAyuZv@Base 6
+ _D6object20__T11_doPostblitTywZ11_doPostblitFNaNbNiNfAywZv@Base 6
+ _D6object20__T12_getPostblitTaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKaZv@Base 6
+ _D6object20__T12_getPostblitThZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKhZv@Base 6
+ _D6object20__T12_getPostblitTkZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKkZv@Base 6
+ _D6object21__T11_doPostblitTAyaZ11_doPostblitFNaNbNiNfAAyaZv@Base 6
+ _D6object21__T12_getPostblitTyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyaZv@Base 6
+ _D6object21__T12_getPostblitTyhZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyhZv@Base 6
+ _D6object21__T12_getPostblitTyuZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyuZv@Base 6
+ _D6object21__T12_getPostblitTywZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKywZv@Base 6
+ _D6object22__T11_trustedDupTaTyaZ11_trustedDupFNaNbNeAaZAya@Base 6
+ _D6object22__T11_trustedDupTxaTaZ11_trustedDupFNaNbNeAxaZAa@Base 6
+ _D6object22__T11_trustedDupTxhThZ11_trustedDupFNaNbNeAxhZAh@Base 6
+ _D6object22__T11_trustedDupTxkTkZ11_trustedDupFNaNbNeAxkZAk@Base 6
+ _D6object22__T12_getPostblitTAyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKAyaZv@Base 6
+ _D6object23__T11_trustedDupTxaTyaZ11_trustedDupFNaNbNeAxaZAya@Base 6
+ _D6object23__T11_trustedDupTxhTyhZ11_trustedDupFNaNbNeAxhZAyh@Base 6
+ _D6object23__T11_trustedDupTxuTyuZ11_trustedDupFNaNbNeAxuZAyu@Base 6
+ _D6object23__T11_trustedDupTxwTywZ11_trustedDupFNaNbNeAxwZAyw@Base 6
+ _D6object24__T16assumeSafeAppendTkZ16assumeSafeAppendFNbNcKNgAkZNgAk@Base 6
+ _D6object26__T11_trustedDupTxAyaTAyaZ11_trustedDupFNaNbNeAxAyaZAAya@Base 6
+ _D6object29__T7destroyTS3std5stdio4FileZ7destroyFNfKS3std5stdio4FileZv@Base 6
+ _D6object33__T8capacityTS3std4file8DirEntryZ8capacityFNaNbNdAS3std4file8DirEntryZk@Base 6
+ _D6object36__T7destroyTS3std3net4curl3FTP4ImplZ7destroyFKS3std3net4curl3FTP4ImplZv@Base 6
+ _D6object37__T7destroyTS3std3net4curl4HTTP4ImplZ7destroyFKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D6object37__T7destroyTS3std3net4curl4SMTP4ImplZ7destroyFKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D6object39__T16_destructRecurseTS3std5stdio4FileZ16_destructRecurseFNfKS3std5stdio4FileZv@Base 6
+ _D6object39__T7destroyTS3std11concurrency7MessageZ7destroyFKS3std11concurrency7MessageZv@Base 6
+ _D6object39__T8capacityTS3std6socket11AddressInfoZ8capacityFNaNbNdAS3std6socket11AddressInfoZk@Base 6
+ _D6object40__T11_doPostblitTS3std11concurrency3TidZ11_doPostblitFNaNbNiNfAS3std11concurrency3TidZv@Base 6
+ _D6object40__T7destroyTS3std4file15DirIteratorImplZ7destroyFKS3std4file15DirIteratorImplZv@Base 6
+ _D6object41__T12_getPostblitTS3std11concurrency3TidZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKS3std11concurrency3TidZv@Base 6
+ _D6object45__T7reserveTS3std5regex8internal2ir8BytecodeZ7reserveFNaNbNeKAS3std5regex8internal2ir8BytecodekZk@Base 6
+ _D6object46__T16_destructRecurseTS3std3net4curl3FTP4ImplZ16_destructRecurseFKS3std3net4curl3FTP4ImplZv@Base 6
+ _D6object47__T16_destructRecurseTS3std3net4curl4HTTP4ImplZ16_destructRecurseFKS3std3net4curl4HTTP4ImplZv@Base 6
+ _D6object47__T16_destructRecurseTS3std3net4curl4SMTP4ImplZ16_destructRecurseFKS3std3net4curl4SMTP4ImplZv@Base 6
+ _D6object49__T16_destructRecurseTS3std11concurrency7MessageZ16_destructRecurseFKS3std11concurrency7MessageZv@Base 6
+ _D6object50__T16_destructRecurseTS3std4file15DirIteratorImplZ16_destructRecurseFKS3std4file15DirIteratorImplZv@Base 6
+ _D6object51__T4idupTS3std8datetime13PosixTimeZone10LeapSecondZ4idupFNaNbNdNfAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object51__T4idupTS3std8datetime13PosixTimeZone10TransitionZ4idupFNaNbNdNfAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object51__T8capacityTS3std4file15DirIteratorImpl9DirHandleZ8capacityFNaNbNdAS3std4file15DirIteratorImpl9DirHandleZk@Base 6
+ _D6object54__T7_rawDupTS3std8datetime13PosixTimeZone10LeapSecondZ7_rawDupFNaNbANgS3std8datetime13PosixTimeZone10LeapSecondZANgS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object54__T7_rawDupTS3std8datetime13PosixTimeZone10TransitionZ7_rawDupFNaNbANgS3std8datetime13PosixTimeZone10TransitionZANgS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D6object57__T8_ArrayEqTxS3std4json9JSONValueTxS3std4json9JSONValueZ8_ArrayEqFNaNbNiAxS3std4json9JSONValueAxS3std4json9JSONValueZb@Base 6
+ _D6object60__T11_doPostblitTyS3std8datetime13PosixTimeZone10LeapSecondZ11_doPostblitFNaNbNiNfAyS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D6object60__T11_doPostblitTyS3std8datetime13PosixTimeZone10TransitionZ11_doPostblitFNaNbNiNfAyS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D6object60__T4keysHTHS3std11concurrency3TidbTbTS3std11concurrency3TidZ4keysFNaNbNdHS3std11concurrency3TidbZAS3std11concurrency3Tid@Base 6
+ _D6object61__T12_getPostblitTyS3std8datetime13PosixTimeZone10LeapSecondZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKyS3std8datetime13PosixTimeZone10LeapSecondZv@Base 6
+ _D6object61__T12_getPostblitTyS3std8datetime13PosixTimeZone10TransitionZ12_getPostblitFNaNbNiNeZPFNaNbNiNfKyS3std8datetime13PosixTimeZone10TransitionZv@Base 6
+ _D6object61__T16assumeSafeAppendTS3std8typecons16__T5TupleTkTkTkZ5TupleZ16assumeSafeAppendFNbNcKNgAS3std8typecons16__T5TupleTkTkTkZ5TupleZNgAS3std8typecons16__T5TupleTkTkTkZ5Tuple@Base 6
+ _D6object62__T4keysHTxHAyaS3std4json9JSONValueTxS3std4json9JSONValueTAyaZ4keysFNaNbNdxHAyaS3std4json9JSONValueZAAya@Base 6
+ _D6object83__T16assumeSafeAppendTE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZ16assumeSafeAppendFNbNcKNgAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8OperatorZNgAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator@Base 6
+ _D6object87__T16assumeSafeAppendTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16assumeSafeAppendFNbNcKNgAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZNgAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList@Base 6
+ _D6object90__T16assumeSafeAppendTS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZ16assumeSafeAppendFNbNcKNgAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThreadZNgAS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread@Base 6
+ _D6object93__T8_ArrayEqTxS3std8typecons16__T5TupleTkTkTkZ5TupleTxS3std8typecons16__T5TupleTkTkTkZ5TupleZ8_ArrayEqFNaNbNiNfAxS3std8typecons16__T5TupleTkTkTkZ5TupleAxS3std8typecons16__T5TupleTkTkTkZ5TupleZb@Base 6
+ _D6object94__T4_dupTS3std8datetime13PosixTimeZone10LeapSecondTyS3std8datetime13PosixTimeZone10LeapSecondZ4_dupFNaNbAS3std8datetime13PosixTimeZone10LeapSecondZAyS3std8datetime13PosixTimeZone10LeapSecond@Base 6
+ _D6object94__T4_dupTS3std8datetime13PosixTimeZone10TransitionTyS3std8datetime13PosixTimeZone10TransitionZ4_dupFNaNbAS3std8datetime13PosixTimeZone10TransitionZAyS3std8datetime13PosixTimeZone10Transition@Base 6
+ _D70TypeInfo_AE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D70TypeInfo_S3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D70TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List6__initZ@Base 6
+ _D70TypeInfo_S3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4Data6__initZ@Base 6
+ _D70TypeInfo_S3std5range35__T11SortedRangeTAkVAyaa4_613c3d62Z11SortedRange6__initZ@Base 6
+ _D70TypeInfo_S3std5range43__T4TakeTS3std5range13__T6RepeatTiZ6RepeatZ4Take6__initZ@Base 6
+ _D70TypeInfo_S3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList6__initZ@Base 6
+ _D70TypeInfo_xE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_AxE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_E3std8typecons41__T4FlagVAyaa12_7468726f774f6e4572726f72Z4Flag6__initZ@Base 6
+ _D71TypeInfo_S3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D71TypeInfo_S3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender6__initZ@Base 6
+ _D71TypeInfo_S3std8typecons40__T5TupleTkVAyaa3_706f73TkVAyaa3_6c656eZ5Tuple6__initZ@Base 6
+ _D71TypeInfo_xAE3std5regex8internal6parser15__T6ParserTAyaZ6Parser8Operator6__initZ@Base 6
+ _D71TypeInfo_xS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D71TypeInfo_xS3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList6__initZ@Base 6
+ _D72TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D72TypeInfo_S3std11parallelism38__T4TaskS213std11parallelism3runTDFZvZ4Task6__initZ@Base 6
+ _D72TypeInfo_S3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D72TypeInfo_S3std5range37__T11SortedRangeTAkVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D72TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info24sqlite3_index_constraint6__initZ@Base 6
+ _D72TypeInfo_xS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D73TypeInfo_E3std8typecons43__T4FlagVAyaa13_6361736553656e736974697665Z4Flag6__initZ@Base 6
+ _D73TypeInfo_S3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6__initZ@Base 6
+ _D73TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D73TypeInfo_S3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D73TypeInfo_S3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D74TypeInfo_AS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D74TypeInfo_S3std5range39__T11SortedRangeTAAyaVAyaa5_61203c2062Z11SortedRange6__initZ@Base 6
+ _D74TypeInfo_S3std5range39__T11SortedRangeTAkVAyaa6_61203c3d2062Z11SortedRange6__initZ@Base 6
+ _D74TypeInfo_xS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D74TypeInfo_xS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D74TypeInfo_xS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D75TypeInfo_AxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D75TypeInfo_E3std8typecons45__T4FlagVAyaa14_6b6565705465726d696e61746f72Z4Flag6__initZ@Base 6
+ _D75TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D75TypeInfo_xAS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList6__initZ@Base 6
+ _D76TypeInfo_S3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D76TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List5Range6__initZ@Base 6
+ _D76TypeInfo_S3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D76TypeInfo_S3std5array40__T8AppenderTAS3std6socket11AddressInfoZ8Appender4Data6__initZ@Base 6
+ _D76TypeInfo_S3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D76TypeInfo_S3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4Sink6__initZ@Base 6
+ _D76TypeInfo_S3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntry6__initZ@Base 6
+ _D76TypeInfo_xS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_AS3std5regex8internal9kickstart14__T7ShiftOrTaZ7ShiftOr11ShiftThread6__initZ@Base 6
+ _D77TypeInfo_PxS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_S3std4path26__T16asNormalizedPathTAxaZ16asNormalizedPathFAxaZ6Result6__initZ@Base 6
+ _D77TypeInfo_xPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node6__initZ@Base 6
+ _D77TypeInfo_xS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D77TypeInfo_xS3std4path22__T12pathSplitterTAxaZ12pathSplitterFAxaZ12PathSplitter6__initZ@Base 6
+ _D78TypeInfo_PxS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D78TypeInfo_S3std8internal7cstring23__T11tempCStringTaTAxaZ11tempCStringFAxaZ3Res6__initZ@Base 6
+ _D78TypeInfo_S3std8internal7cstring23__T11tempCStringTaTAyaZ11tempCStringFAyaZ3Res6__initZ@Base 6
+ _D78TypeInfo_S3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D78TypeInfo_xPS3etc1c7sqlite318sqlite3_index_info30sqlite3_index_constraint_usage6__initZ@Base 6
+ _D79TypeInfo_S3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List8SpinLock6__initZ@Base 6
+ _D79TypeInfo_S3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed6__initZ@Base 6
+ _D79TypeInfo_S3std6random40__T14XorshiftEngineTkVki160Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D79TypeInfo_S3std6random40__T14XorshiftEngineTkVki192Vki2Vki1Vki4Z14XorshiftEngine6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntry6__initZ@Base 6
+ _D79TypeInfo_S3std8typecons48__T5TupleTC14TypeInfo_ClassTPC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D79TypeInfo_xS3std8typecons41__T10RebindableTyC3std8datetime8TimeZoneZ10Rebindable6__initZ@Base 6
+ _D80TypeInfo_S3std6random41__T14XorshiftEngineTkVki96Vki10Vki5Vki26Z14XorshiftEngine6__initZ@Base 6
+ _D80TypeInfo_S3std8internal7cstring24__T11tempCStringTaTANgaZ11tempCStringFANgaZ3Res6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki128Vki11Vki8Vki19Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki32Vki13Vki17Vki15Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std6random42__T14XorshiftEngineTkVki64Vki10Vki13Vki10Z14XorshiftEngine6__initZ@Base 6
+ _D81TypeInfo_S3std8typecons50__T5TupleTC15TypeInfo_SharedTPOC6object9ThrowableZ5Tuple6__initZ@Base 6
+ _D83TypeInfo_E3std8typecons53__T4FlagVAyaa18_707265736572766541747472696275746573Z4Flag6__initZ@Base 6
+ _D83TypeInfo_S3std3uni51__T10assumeSizeS28_D3std3uni5low_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D83TypeInfo_S3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D83TypeInfo_S3std5regex8internal8thompson18__T10ThreadListTkZ10ThreadList11ThreadRange6__initZ@Base 6
+ _D83TypeInfo_S3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntry6__initZ@Base 6
+ _D84TypeInfo_E3std5regex8internal6parser15__T6ParserTAyaZ6Parser13parseCharTermMFZ5State6__initZ@Base 6
+ _D84TypeInfo_S3std8typecons53__T5TupleTC15TypeInfo_StructTPS3std11concurrency3TidZ5Tuple6__initZ@Base 6
+ _D84TypeInfo_xS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender6__initZ@Base 6
+ _D85TypeInfo_E3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flag6__initZ@Base 6
+ _D85TypeInfo_S3std8typecons54__T5TupleTiVAyaa6_737461747573TAyaVAyaa6_6f7574707574Z5Tuple6__initZ@Base 6
+ _D85TypeInfo_S3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D86TypeInfo_S3std3uni54__T10assumeSizeS31_D3std3uni8midlow_8FNaNbNiNfkZkVki8Z10assumeSize6__initZ@Base 6
+ _D86TypeInfo_xS3std9algorithm9iteration39__T9MapResultS183std5ascii7toLowerTAxaZ9MapResult6__initZ@Base 6
+ _D88TypeInfo_S3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4Data6__initZ@Base 6
+ _D890TypeInfo_S3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl6__initZ@Base 6
+ _D91TypeInfo_S3std5regex8internal2ir12__T5RegexTaZ5Regex13namedCapturesMFNdNfZ15NamedGroupRange6__initZ@Base 6
+ _D92TypeInfo_S3std8typecons61__T5TupleTbVAyaa10_7465726d696e61746564TiVAyaa6_737461747573Z5Tuple6__initZ@Base 6
+ _D93TypeInfo_S3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D93TypeInfo_S3std5regex8internal6parser49__T5StackTS3std8typecons16__T5TupleTkTkTkZ5TupleZ5Stack6__initZ@Base 6
+ _D94TypeInfo_xS3std3uni61__T10MultiArrayTS3std3uni21__T9BitPackedTkVki12Z9BitPackedTtZ10MultiArray6__initZ@Base 6
+ _D96TypeInfo_S3std9algorithm9iteration38__T8splitterVAyaa6_61203d3d2062TAyaTaZ8splitterFAyaaZ6Result6__initZ@Base 6
+ _DT104_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest3putMFNbNeMAxhXv@Base 6.2.1-1ubuntu2
+ _DT104_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest5resetMFNbNeZv@Base 6.2.1-1ubuntu2
+ _DT104_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbMAhZAh@Base 6.2.1-1ubuntu2
+ _DT104_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbNeZAh@Base 6.2.1-1ubuntu2
+ _DT104_D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6.2.1-1ubuntu2
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT104_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT112_D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT12_D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT20_D3std11concurrency14FiberScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _DT20_D3std11concurrency14FiberScheduler5spawnMFNbDFZvZv@Base 6
+ _DT20_D3std11concurrency14FiberScheduler5startMFDFZvZv@Base 6
+ _DT20_D3std11concurrency14FiberScheduler5yieldMFNbZv@Base 6
+ _DT20_D3std11concurrency14FiberScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii256Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii384Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT216_D3std6digest6digest63__T13WrapperDigestTS3std6digest3sha21__T3SHAVii1024Vii512Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _DT24_D3std6stream11SliceStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream12EndianStream11readStringWMFkZAu@Base 6
+ _DT24_D3std6stream12EndianStream3eofMFNdZb@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJaZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJcZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJdZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJeZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJfZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJgZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJhZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJiZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJjZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJkZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJlZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJmZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJoZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJpZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJqZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJrZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJsZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJtZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJuZv@Base 6
+ _DT24_D3std6stream12EndianStream4readMFJwZv@Base 6
+ _DT24_D3std6stream12EndianStream5getcwMFZu@Base 6
+ _DT24_D3std6stream12FilterStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream14BufferedStream3eofMFNdZb@Base 6
+ _DT24_D3std6stream14BufferedStream8readLineMFAaZAa@Base 6
+ _DT24_D3std6stream14BufferedStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream14BufferedStream9readLineWMFAuZAu@Base 6
+ _DT24_D3std6stream21__T12TArrayStreamTAhZ12TArrayStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream38__T12TArrayStreamTC3std6mmfile6MmFileZ12TArrayStream9availableMFNdZk@Base 6
+ _DT24_D3std6stream4File9availableMFNdZk@Base 6
+ _DT24_D3std6stream6Stream10readStringMFkZAa@Base 6
+ _DT24_D3std6stream6Stream11readStringWMFkZAu@Base 6
+ _DT24_D3std6stream6Stream3eofMFNdZb@Base 6
+ _DT24_D3std6stream6Stream4getcMFZa@Base 6
+ _DT24_D3std6stream6Stream4readMFAhZk@Base 6
+ _DT24_D3std6stream6Stream4readMFJAaZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJAuZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJaZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJcZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJdZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJeZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJfZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJgZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJhZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJiZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJjZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJkZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJlZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJmZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJoZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJpZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJqZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJrZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJsZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJtZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJuZv@Base 6
+ _DT24_D3std6stream6Stream4readMFJwZv@Base 6
+ _DT24_D3std6stream6Stream5getcwMFZu@Base 6
+ _DT24_D3std6stream6Stream5readfMFYi@Base 6
+ _DT24_D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _DT24_D3std6stream6Stream6ungetcMFaZa@Base 6
+ _DT24_D3std6stream6Stream6vreadfMFAC8TypeInfoS3gcc8builtins9__va_listZi@Base 6.2.1-1ubuntu2
+ _DT24_D3std6stream6Stream7opApplyMFMDFKAaZiZi@Base 6
+ _DT24_D3std6stream6Stream7opApplyMFMDFKAuZiZi@Base 6
+ _DT24_D3std6stream6Stream7opApplyMFMDFKmKAaZiZi@Base 6
+ _DT24_D3std6stream6Stream7opApplyMFMDFKmKAuZiZi@Base 6
+ _DT24_D3std6stream6Stream7ungetcwMFuZu@Base 6
+ _DT24_D3std6stream6Stream8readLineMFAaZAa@Base 6
+ _DT24_D3std6stream6Stream8readLineMFZAa@Base 6
+ _DT24_D3std6stream6Stream9availableMFNdZk@Base 6
+ _DT24_D3std6stream6Stream9readExactMFPvkZv@Base 6
+ _DT24_D3std6stream6Stream9readLineWMFAuZAu@Base 6
+ _DT24_D3std6stream6Stream9readLineWMFZAu@Base 6
+ _DT24_D3std7cstream5CFile3eofMFZb@Base 6
+ _DT24_D3std7cstream5CFile4getcMFZa@Base 6
+ _DT24_D3std7cstream5CFile6ungetcMFaZa@Base 6
+ _DT28_D3std12socketstream12SocketStream5closeMFZv@Base 6
+ _DT28_D3std6stream12EndianStream12writeStringWMFAxuZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFaZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFcZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFdZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFeZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFfZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFgZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFhZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFiZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFjZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFkZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFlZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFmZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFoZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFpZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFqZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFrZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFsZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFtZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFuZv@Base 6
+ _DT28_D3std6stream12EndianStream5writeMFwZv@Base 6
+ _DT28_D3std6stream12FilterStream5closeMFZv@Base 6
+ _DT28_D3std6stream12FilterStream5flushMFZv@Base 6
+ _DT28_D3std6stream12MmFileStream5closeMFZv@Base 6
+ _DT28_D3std6stream12MmFileStream5flushMFZv@Base 6
+ _DT28_D3std6stream14BufferedStream5flushMFZv@Base 6
+ _DT28_D3std6stream4File5closeMFZv@Base 6
+ _DT28_D3std6stream6Stream10writeExactMFxPvkZv@Base 6
+ _DT28_D3std6stream6Stream10writeLineWMFAxuZv@Base 6
+ _DT28_D3std6stream6Stream11writeStringMFAxaZv@Base 6
+ _DT28_D3std6stream6Stream12writeStringWMFAxuZv@Base 6
+ _DT28_D3std6stream6Stream5closeMFZv@Base 6
+ _DT28_D3std6stream6Stream5flushMFZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFAxaZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFAxhZk@Base 6
+ _DT28_D3std6stream6Stream5writeMFAxuZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFaZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFcZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFdZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFeZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFfZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFgZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFhZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFiZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFjZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFkZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFlZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFmZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFoZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFpZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFqZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFrZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFsZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFtZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFuZv@Base 6
+ _DT28_D3std6stream6Stream5writeMFwZv@Base 6
+ _DT28_D3std6stream6Stream6isOpenMFNdZb@Base 6
+ _DT28_D3std6stream6Stream6printfMFAxaYk@Base 6
+ _DT28_D3std6stream6Stream6writefMFYC3std6stream12OutputStream@Base 6
+ _DT28_D3std6stream6Stream7vprintfMFAxaS3gcc8builtins9__va_listZk@Base 6.2.1-1ubuntu2
+ _DT28_D3std6stream6Stream7writefxMFAC8TypeInfoS3gcc8builtins9__va_listiZC3std6stream12OutputStream@Base 6.2.1-1ubuntu2
+ _DT28_D3std6stream6Stream8writeflnMFYC3std6stream12OutputStream@Base 6
+ _DT28_D3std6stream6Stream9writeLineMFAxaZv@Base 6
+ _DT28_D3std7cstream5CFile10writeLineWMFAxuZv@Base 6
+ _DT28_D3std7cstream5CFile5closeMFZv@Base 6
+ _DT28_D3std7cstream5CFile5flushMFZv@Base 6
+ _DT28_D3std7cstream5CFile9writeLineMFAxaZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler12newConditionMFNbC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler5spawnMFDFZvZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler5startMFDFZvZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler5yieldMFNbZv@Base 6
+ _DT8_D3std11concurrency15ThreadScheduler8thisInfoMFNbNcNdZS3std11concurrency10ThreadInfo@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _DT96_D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ __mod_ref__D3etc1c4curl12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc1c4zlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc1c7sqlite312__ModuleInfoZ@Base 6
+ __mod_ref__D3std10functional12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11concurrency12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11mathspecial12__ModuleInfoZ@Base 6
+ __mod_ref__D3std11parallelism12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger10filelogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger10nulllogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger11multilogger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12experimental6logger4core12__ModuleInfoZ@Base 6
+ __mod_ref__D3std12socketstream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4fenv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4math12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c4time12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux11linuxextern12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux4tipc12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux5linux12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux7pthread12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5linux7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6locale12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stdarg12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stddef12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6string12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c6wcharh12__ModuleInfoZ@Base 6
+ __mod_ref__D3std1c7process12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3csv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3net4curl12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3net7isemail12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3uni12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3uri12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3utf12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3xml12__ModuleInfoZ@Base 6
+ __mod_ref__D3std3zip12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4conv12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4file12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4json12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4math12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4meta12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4path12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4uuid12__ModuleInfoZ@Base 6
+ __mod_ref__D3std4zlib12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5array12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5ascii12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range10interfaces12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range10primitives12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5range12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal12backtracking12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal2ir12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal5tests12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal6parser12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal8thompson12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal9generator12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5regex8internal9kickstart12__ModuleInfoZ@Base 6
+ __mod_ref__D3std5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6base6412__ModuleInfoZ@Base 6
+ __mod_ref__D3std6bigint12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest2md12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest3crc12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest3sha12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest6digest12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6digest6ripemd12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6format12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6getopt12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6mmfile12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6random12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6stdint12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6stream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6string12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6system12__ModuleInfoZ@Base 6
+ __mod_ref__D3std6traits12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7complex12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7cstream12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7numeric12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7process12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7signals12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7variant12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows7charset12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8iunknown12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8registry12__ModuleInfoZ@Base 6
+ __mod_ref__D3std7windows8syserror12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8bitmanip12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8compiler12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8datetime12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8demangle12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8encoding12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal11processinit12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal11scopebuffer12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal12unicode_comp12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal12unicode_norm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal14unicode_decomp12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal14unicode_tables12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal16unicode_grapheme12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math10biguintx8612__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math11biguintcore12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math12biguintnoasm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math13errorfunction12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4math13gammafunction12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal4test10dummyrange12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal6digest9sha_SSSE312__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal7cstring12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8internal7windows8advapi3212__ModuleInfoZ@Base 6
+ __mod_ref__D3std8syserror12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8typecons12__ModuleInfoZ@Base 6
+ __mod_ref__D3std8typelist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm10comparison12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm6setops12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm7sorting12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm8internal12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm8mutation12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm9iteration12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9algorithm9searching12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container10binaryheap12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container4util12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5array12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5dlist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container5slist12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9container6rbtree12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9outbuffer12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9stdiobase12__ModuleInfoZ@Base 6
+ __mod_ref__D3std9typetuple12__ModuleInfoZ@Base 6
+ _arraySliceComSliceAssign_k@Base 6
+ deflateInit2@Base 6
+ deflateInit@Base 6
+ inflateBackInit@Base 6
+ inflateInit2@Base 6
+ inflateInit@Base 6
+ std_stdio_static_this@Base 6
--- gcc-6-6.3.0.orig/debian/libgphobos.symbols.rt32
+++ gcc-6-6.3.0/debian/libgphobos.symbols.rt32
@@ -0,0 +1,3326 @@
+ LOG_MASK@Base 6
+ LOG_UPTO@Base 6
+ S_TYPEISMQ@Base 6
+ S_TYPEISSEM@Base 6
+ S_TYPEISSHM@Base 6
+ _D102TypeInfo_S2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ2DG6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D10TypeInfo_C6__initZ@Base 6
+ _D10TypeInfo_C6__vtblZ@Base 6
+ _D10TypeInfo_C7__ClassZ@Base 6
+ _D10TypeInfo_D6__initZ@Base 6
+ _D10TypeInfo_D6__vtblZ@Base 6
+ _D10TypeInfo_D7__ClassZ@Base 6
+ _D10TypeInfo_P6__initZ@Base 6
+ _D10TypeInfo_P6__vtblZ@Base 6
+ _D10TypeInfo_P7__ClassZ@Base 6
+ _D10TypeInfo_a6__initZ@Base 6
+ _D10TypeInfo_a6__vtblZ@Base 6
+ _D10TypeInfo_a7__ClassZ@Base 6
+ _D10TypeInfo_b6__initZ@Base 6
+ _D10TypeInfo_b6__vtblZ@Base 6
+ _D10TypeInfo_b7__ClassZ@Base 6
+ _D10TypeInfo_c6__initZ@Base 6
+ _D10TypeInfo_c6__vtblZ@Base 6
+ _D10TypeInfo_c7__ClassZ@Base 6
+ _D10TypeInfo_d6__initZ@Base 6
+ _D10TypeInfo_d6__vtblZ@Base 6
+ _D10TypeInfo_d7__ClassZ@Base 6
+ _D10TypeInfo_e6__initZ@Base 6
+ _D10TypeInfo_e6__vtblZ@Base 6
+ _D10TypeInfo_e7__ClassZ@Base 6
+ _D10TypeInfo_f6__initZ@Base 6
+ _D10TypeInfo_f6__vtblZ@Base 6
+ _D10TypeInfo_f7__ClassZ@Base 6
+ _D10TypeInfo_g6__initZ@Base 6
+ _D10TypeInfo_g6__vtblZ@Base 6
+ _D10TypeInfo_g7__ClassZ@Base 6
+ _D10TypeInfo_h6__initZ@Base 6
+ _D10TypeInfo_h6__vtblZ@Base 6
+ _D10TypeInfo_h7__ClassZ@Base 6
+ _D10TypeInfo_i6__initZ@Base 6
+ _D10TypeInfo_i6__vtblZ@Base 6
+ _D10TypeInfo_i7__ClassZ@Base 6
+ _D10TypeInfo_j6__initZ@Base 6
+ _D10TypeInfo_j6__vtblZ@Base 6
+ _D10TypeInfo_j7__ClassZ@Base 6
+ _D10TypeInfo_k6__initZ@Base 6
+ _D10TypeInfo_k6__vtblZ@Base 6
+ _D10TypeInfo_k7__ClassZ@Base 6
+ _D10TypeInfo_l6__initZ@Base 6
+ _D10TypeInfo_l6__vtblZ@Base 6
+ _D10TypeInfo_l7__ClassZ@Base 6
+ _D10TypeInfo_m6__initZ@Base 6
+ _D10TypeInfo_m6__vtblZ@Base 6
+ _D10TypeInfo_m7__ClassZ@Base 6
+ _D10TypeInfo_o6__initZ@Base 6
+ _D10TypeInfo_o6__vtblZ@Base 6
+ _D10TypeInfo_o7__ClassZ@Base 6
+ _D10TypeInfo_p6__initZ@Base 6
+ _D10TypeInfo_p6__vtblZ@Base 6
+ _D10TypeInfo_p7__ClassZ@Base 6
+ _D10TypeInfo_q6__initZ@Base 6
+ _D10TypeInfo_q6__vtblZ@Base 6
+ _D10TypeInfo_q7__ClassZ@Base 6
+ _D10TypeInfo_r6__initZ@Base 6
+ _D10TypeInfo_r6__vtblZ@Base 6
+ _D10TypeInfo_r7__ClassZ@Base 6
+ _D10TypeInfo_s6__initZ@Base 6
+ _D10TypeInfo_s6__vtblZ@Base 6
+ _D10TypeInfo_s7__ClassZ@Base 6
+ _D10TypeInfo_t6__initZ@Base 6
+ _D10TypeInfo_t6__vtblZ@Base 6
+ _D10TypeInfo_t7__ClassZ@Base 6
+ _D10TypeInfo_u6__initZ@Base 6
+ _D10TypeInfo_u6__vtblZ@Base 6
+ _D10TypeInfo_u7__ClassZ@Base 6
+ _D10TypeInfo_v6__initZ@Base 6
+ _D10TypeInfo_v6__vtblZ@Base 6
+ _D10TypeInfo_v7__ClassZ@Base 6
+ _D10TypeInfo_w6__initZ@Base 6
+ _D10TypeInfo_w6__vtblZ@Base 6
+ _D10TypeInfo_w7__ClassZ@Base 6
+ _D11TypeInfo_AC6__initZ@Base 6
+ _D11TypeInfo_AC6__vtblZ@Base 6
+ _D11TypeInfo_AC7__ClassZ@Base 6
+ _D11TypeInfo_Aa6__initZ@Base 6
+ _D11TypeInfo_Aa6__vtblZ@Base 6
+ _D11TypeInfo_Aa7__ClassZ@Base 6
+ _D11TypeInfo_Ab6__initZ@Base 6
+ _D11TypeInfo_Ab6__vtblZ@Base 6
+ _D11TypeInfo_Ab7__ClassZ@Base 6
+ _D11TypeInfo_Ac6__initZ@Base 6
+ _D11TypeInfo_Ac6__vtblZ@Base 6
+ _D11TypeInfo_Ac7__ClassZ@Base 6
+ _D11TypeInfo_Ad6__initZ@Base 6
+ _D11TypeInfo_Ad6__vtblZ@Base 6
+ _D11TypeInfo_Ad7__ClassZ@Base 6
+ _D11TypeInfo_Ae6__initZ@Base 6
+ _D11TypeInfo_Ae6__vtblZ@Base 6
+ _D11TypeInfo_Ae7__ClassZ@Base 6
+ _D11TypeInfo_Af6__initZ@Base 6
+ _D11TypeInfo_Af6__vtblZ@Base 6
+ _D11TypeInfo_Af7__ClassZ@Base 6
+ _D11TypeInfo_Ag6__initZ@Base 6
+ _D11TypeInfo_Ag6__vtblZ@Base 6
+ _D11TypeInfo_Ag7__ClassZ@Base 6
+ _D11TypeInfo_Ah6__initZ@Base 6
+ _D11TypeInfo_Ah6__vtblZ@Base 6
+ _D11TypeInfo_Ah7__ClassZ@Base 6
+ _D11TypeInfo_Ai6__initZ@Base 6
+ _D11TypeInfo_Ai6__vtblZ@Base 6
+ _D11TypeInfo_Ai7__ClassZ@Base 6
+ _D11TypeInfo_Aj6__initZ@Base 6
+ _D11TypeInfo_Aj6__vtblZ@Base 6
+ _D11TypeInfo_Aj7__ClassZ@Base 6
+ _D11TypeInfo_Ak6__initZ@Base 6
+ _D11TypeInfo_Ak6__vtblZ@Base 6
+ _D11TypeInfo_Ak7__ClassZ@Base 6
+ _D11TypeInfo_Al6__initZ@Base 6
+ _D11TypeInfo_Al6__vtblZ@Base 6
+ _D11TypeInfo_Al7__ClassZ@Base 6
+ _D11TypeInfo_Am6__initZ@Base 6
+ _D11TypeInfo_Am6__vtblZ@Base 6
+ _D11TypeInfo_Am7__ClassZ@Base 6
+ _D11TypeInfo_Ao6__initZ@Base 6
+ _D11TypeInfo_Ao6__vtblZ@Base 6
+ _D11TypeInfo_Ao7__ClassZ@Base 6
+ _D11TypeInfo_Ap6__initZ@Base 6
+ _D11TypeInfo_Ap6__vtblZ@Base 6
+ _D11TypeInfo_Ap7__ClassZ@Base 6
+ _D11TypeInfo_Aq6__initZ@Base 6
+ _D11TypeInfo_Aq6__vtblZ@Base 6
+ _D11TypeInfo_Aq7__ClassZ@Base 6
+ _D11TypeInfo_Ar6__initZ@Base 6
+ _D11TypeInfo_Ar6__vtblZ@Base 6
+ _D11TypeInfo_Ar7__ClassZ@Base 6
+ _D11TypeInfo_As6__initZ@Base 6
+ _D11TypeInfo_As6__vtblZ@Base 6
+ _D11TypeInfo_As7__ClassZ@Base 6
+ _D11TypeInfo_At6__initZ@Base 6
+ _D11TypeInfo_At6__vtblZ@Base 6
+ _D11TypeInfo_At7__ClassZ@Base 6
+ _D11TypeInfo_Au6__initZ@Base 6
+ _D11TypeInfo_Au6__vtblZ@Base 6
+ _D11TypeInfo_Au7__ClassZ@Base 6
+ _D11TypeInfo_Av6__initZ@Base 6
+ _D11TypeInfo_Av6__vtblZ@Base 6
+ _D11TypeInfo_Av7__ClassZ@Base 6
+ _D11TypeInfo_Aw6__initZ@Base 6
+ _D11TypeInfo_Aw6__vtblZ@Base 6
+ _D11TypeInfo_Aw7__ClassZ@Base 6
+ _D11TypeInfo_Oa6__initZ@Base 6
+ _D11TypeInfo_Ou6__initZ@Base 6
+ _D11TypeInfo_xa6__initZ@Base 6
+ _D11TypeInfo_xb6__initZ@Base 6
+ _D11TypeInfo_xf6__initZ@Base 6
+ _D11TypeInfo_xh6__initZ@Base 6
+ _D11TypeInfo_xi6__initZ@Base 6
+ _D11TypeInfo_xk6__initZ@Base 6
+ _D11TypeInfo_xt6__initZ@Base 6
+ _D11TypeInfo_xv6__initZ@Base 6
+ _D11TypeInfo_ya6__initZ@Base 6
+ _D11TypeInfo_yk6__initZ@Base 6
+ _D12TypeInfo_AOa6__initZ@Base 6
+ _D12TypeInfo_AOu6__initZ@Base 6
+ _D12TypeInfo_Axa6__initZ@Base 6
+ _D12TypeInfo_Axa6__vtblZ@Base 6
+ _D12TypeInfo_Axa7__ClassZ@Base 6
+ _D12TypeInfo_Axv6__initZ@Base 6
+ _D12TypeInfo_Aya6__initZ@Base 6
+ _D12TypeInfo_Aya6__vtblZ@Base 6
+ _D12TypeInfo_Aya7__ClassZ@Base 6
+ _D12TypeInfo_G0h6__initZ@Base 6
+ _D12TypeInfo_OAa6__initZ@Base 6
+ _D12TypeInfo_OAu6__initZ@Base 6
+ _D12TypeInfo_Pxh6__initZ@Base 6
+ _D12TypeInfo_Pxv6__initZ@Base 6
+ _D12TypeInfo_xAa6__initZ@Base 6
+ _D12TypeInfo_xAv6__initZ@Base 6
+ _D12TypeInfo_xPh6__initZ@Base 6
+ _D12TypeInfo_xPv6__initZ@Base 6
+ _D12TypeInfo_yAa6__initZ@Base 6
+ _D131TypeInfo_E3gcc3deh22__gdc_personality_implFiibPS3gcc6unwind7generic17_Unwind_ExceptionPS3gcc6unwind7generic15_Unwind_ContextZ5Found6__initZ@Base 6
+ _D13TypeInfo_AxPv6__initZ@Base 6
+ _D13TypeInfo_AyAa6__initZ@Base 6
+ _D13TypeInfo_Enum6__initZ@Base 6
+ _D13TypeInfo_Enum6__vtblZ@Base 6
+ _D13TypeInfo_Enum7__ClassZ@Base 6
+ _D13TypeInfo_xAPv6__initZ@Base 6
+ _D13TypeInfo_xG0h6__initZ@Base 6
+ _D143TypeInfo_S2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__initZ@Base 6
+ _D14TypeInfo_Array6__initZ@Base 6
+ _D14TypeInfo_Array6__vtblZ@Base 6
+ _D14TypeInfo_Array7__ClassZ@Base 6
+ _D14TypeInfo_Class6__initZ@Base 6
+ _D14TypeInfo_Class6__vtblZ@Base 6
+ _D14TypeInfo_Class7__ClassZ@Base 6
+ _D14TypeInfo_Const6__initZ@Base 6
+ _D14TypeInfo_Const6__vtblZ@Base 6
+ _D14TypeInfo_Const7__ClassZ@Base 6
+ _D14TypeInfo_Inout6__initZ@Base 6
+ _D14TypeInfo_Inout6__vtblZ@Base 6
+ _D14TypeInfo_Inout7__ClassZ@Base 6
+ _D14TypeInfo_Tuple6__initZ@Base 6
+ _D14TypeInfo_Tuple6__vtblZ@Base 6
+ _D14TypeInfo_Tuple7__ClassZ@Base 6
+ _D15TypeInfo_Shared6__initZ@Base 6
+ _D15TypeInfo_Shared6__vtblZ@Base 6
+ _D15TypeInfo_Shared7__ClassZ@Base 6
+ _D15TypeInfo_Struct6__initZ@Base 6
+ _D15TypeInfo_Struct6__vtblZ@Base 6
+ _D15TypeInfo_Struct7__ClassZ@Base 6
+ _D15TypeInfo_Vector6__initZ@Base 6
+ _D15TypeInfo_Vector6__vtblZ@Base 6
+ _D15TypeInfo_Vector7__ClassZ@Base 6
+ _D16TypeInfo_Pointer6__initZ@Base 6
+ _D16TypeInfo_Pointer6__vtblZ@Base 6
+ _D16TypeInfo_Pointer7__ClassZ@Base 6
+ _D16TypeInfo_Typedef6__initZ@Base 6
+ _D16TypeInfo_Typedef6__vtblZ@Base 6
+ _D16TypeInfo_Typedef7__ClassZ@Base 6
+ _D17TypeInfo_Delegate6__initZ@Base 6
+ _D17TypeInfo_Delegate6__vtblZ@Base 6
+ _D17TypeInfo_Delegate7__ClassZ@Base 6
+ _D17TypeInfo_Function6__initZ@Base 6
+ _D17TypeInfo_Function6__vtblZ@Base 6
+ _D17TypeInfo_Function7__ClassZ@Base 6
+ _D18TypeInfo_Interface6__initZ@Base 6
+ _D18TypeInfo_Interface6__vtblZ@Base 6
+ _D18TypeInfo_Interface7__ClassZ@Base 6
+ _D18TypeInfo_Invariant6__initZ@Base 6
+ _D18TypeInfo_Invariant6__vtblZ@Base 6
+ _D18TypeInfo_Invariant7__ClassZ@Base 6
+ _D19TypeInfo_S2gc2gc2GC6__initZ@Base 6
+ _D20TypeInfo_S2gc2gc3Gcx6__initZ@Base 6
+ _D20TypeInfo_S2rt3aaA2AA6__initZ@Base 6
+ _D20TypeInfo_StaticArray6__initZ@Base 6
+ _D20TypeInfo_StaticArray6__vtblZ@Base 6
+ _D20TypeInfo_StaticArray7__ClassZ@Base 6
+ _D20TypeInfo_xC8TypeInfo6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4List6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4Pool6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4Root6__initZ@Base 6
+ _D22TypeInfo_FNbC6ObjectZv6__initZ@Base 6
+ _D22TypeInfo_S2gc2gc5Range6__initZ@Base 6
+ _D22TypeInfo_S2rt3aaA4Impl6__initZ@Base 6
+ _D22TypeInfo_xS2gc2gc4List6__initZ@Base 6
+ _D22TypeInfo_xS2gc2gc4Root6__initZ@Base 6
+ _D23TypeInfo_DFNbC6ObjectZv6__initZ@Base 6
+ _D23TypeInfo_PxS2gc2gc4List6__initZ@Base 6
+ _D23TypeInfo_S2rt3aaA5Range6__initZ@Base 6
+ _D23TypeInfo_xPS2gc2gc4List6__initZ@Base 6
+ _D23TypeInfo_xS2gc2gc5Range6__initZ@Base 6
+ _D24TypeInfo_AxPS2gc2gc4List6__initZ@Base 6
+ _D24TypeInfo_S2rt3aaA6Bucket6__initZ@Base 6
+ _D24TypeInfo_S2rt5tlsgc4Data6__initZ@Base 6
+ _D24TypeInfo_xDFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_AssociativeArray6__initZ@Base 6
+ _D25TypeInfo_AssociativeArray6__vtblZ@Base 6
+ _D25TypeInfo_AssociativeArray7__ClassZ@Base 6
+ _D25TypeInfo_AxDFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_G8PxS2gc2gc4List6__initZ@Base 6
+ _D25TypeInfo_S2gc4bits6GCBits6__initZ@Base 6
+ _D25TypeInfo_S2gc5proxy5Proxy6__initZ@Base 6
+ _D25TypeInfo_S4core6memory2GC6__initZ@Base 6
+ _D25TypeInfo_S6object7AARange6__initZ@Base 6
+ _D25TypeInfo_xADFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_xG8PS2gc2gc4List6__initZ@Base 6
+ _D25TypeInfo_xS2rt3aaA6Bucket6__initZ@Base 6
+ _D26TypeInfo_AxS2rt3aaA6Bucket6__initZ@Base 6
+ _D26TypeInfo_S2rt6dmain25CArgs6__initZ@Base 6
+ _D26TypeInfo_xAS2rt3aaA6Bucket6__initZ@Base 6
+ _D27TypeInfo_S2gc5stats7GCStats6__initZ@Base 6
+ _D27TypeInfo_S2gc6config6Config6__initZ@Base 6
+ _D27TypeInfo_S6object9Interface6__initZ@Base 6
+ _D27TypeInfo_xC14TypeInfo_Class6__initZ@Base 6
+ _D28TypeInfo_E2rt3aaA4Impl5Flags6__initZ@Base 6
+ _D28TypeInfo_S2rt8lifetime5Array6__initZ@Base 6
+ _D28TypeInfo_S3gcc3deh9FuncTable6__initZ@Base 6
+ _D28TypeInfo_S4core4stdc4time2tm6__initZ@Base 6
+ _D28TypeInfo_S4core4time7FracSec6__initZ@Base 6
+ _D28TypeInfo_xC15TypeInfo_Struct6__initZ@Base 6
+ _D28TypeInfo_xC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_S4core4time8Duration6__initZ@Base 6
+ _D29TypeInfo_S4core7runtime5CArgs6__initZ@Base 6
+ _D29TypeInfo_S6object10ModuleInfo6__initZ@Base 6
+ _D29TypeInfo_xE2rt3aaA4Impl5Flags6__initZ@Base 6
+ _D29TypeInfo_yS3gcc3deh9FuncTable6__initZ@Base 6
+ _D2gc2gc10extendTimel@Base 6
+ _D2gc2gc10mallocTimel@Base 6
+ _D2gc2gc10notbinsizeyG11k@Base 6
+ _D2gc2gc10numExtendsl@Base 6
+ _D2gc2gc10numMallocsl@Base 6
+ _D2gc2gc11numReallocsl@Base 6
+ _D2gc2gc11reallocTimel@Base 6
+ _D2gc2gc11recoverTimeS4core4time8Duration@Base 6
+ _D2gc2gc12__ModuleInfoZ@Base 6
+ _D2gc2gc12maxPauseTimeS4core4time8Duration@Base 6
+ _D2gc2gc12sentinel_addFNbPvZPv@Base 6
+ _D2gc2gc12sentinel_subFNbPvZPv@Base 6
+ _D2gc2gc13maxPoolMemoryk@Base 6
+ _D2gc2gc13sentinel_initFNbPvkZv@Base 6
+ _D2gc2gc14SENTINEL_EXTRAxk@Base 6
+ _D2gc2gc14numCollectionsk@Base 6
+ _D2gc2gc15LargeObjectPool10allocPagesMFNbkZk@Base 6
+ _D2gc2gc15LargeObjectPool13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc15LargeObjectPool13updateOffsetsMFNbkZv@Base 6
+ _D2gc2gc15LargeObjectPool6__initZ@Base 6
+ _D2gc2gc15LargeObjectPool7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc15LargeObjectPool7getSizeMxFNbPvZk@Base 6
+ _D2gc2gc15LargeObjectPool9freePagesMFNbkkZv@Base 6
+ _D2gc2gc15SmallObjectPool13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc15SmallObjectPool6__initZ@Base 6
+ _D2gc2gc15SmallObjectPool7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc15SmallObjectPool7getSizeMxFNbPvZk@Base 6
+ _D2gc2gc15SmallObjectPool9allocPageMFNbhZPS2gc2gc4List@Base 6
+ _D2gc2gc18sentinel_InvariantFNbxPvZv@Base 6
+ _D2gc2gc2GC10freeNoSyncMFNbPvZv@Base 6
+ _D2gc2gc2GC10initializeMFZv@Base 6
+ _D2gc2gc2GC10removeRootMFNbPvZv@Base 6
+ _D2gc2gc2GC11checkNoSyncMFNbPvZv@Base 6
+ _D2gc2gc2GC11fullCollectMFNbZk@Base 6
+ _D2gc2gc2GC11queryNoSyncMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc2GC11removeRangeMFNbNiPvZv@Base 6
+ _D2gc2gc2GC12addrOfNoSyncMFNbPvZPv@Base 6
+ _D2gc2gc2GC12extendNoSyncMFNbPvkkxC8TypeInfoZk@Base 6
+ _D2gc2gc2GC12mallocNoSyncMFNbkkKkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC12mutexStorageG40v@Base 6
+ _D2gc2gc2GC12rootIterImplMFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2gc2gc2GC12sizeOfNoSyncMFNbPvZk@Base 6
+ _D2gc2gc2GC13rangeIterImplMFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2gc2gc2GC13reallocNoSyncMFNbPvkKkKkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC13reserveNoSyncMFNbkZk@Base 6
+ _D2gc2gc2GC13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc2GC14getStatsNoSyncMFNbJS2gc5stats7GCStatsZv@Base 6
+ _D2gc2gc2GC18fullCollectNoStackMFNbZv@Base 6
+ _D2gc2gc2GC4DtorMFZv@Base 6
+ _D2gc2gc2GC4filePa@Base 6
+ _D2gc2gc2GC4freeMFNbPvZv@Base 6
+ _D2gc2gc2GC4linek@Base 6
+ _D2gc2gc2GC5checkMFNbPvZv@Base 6
+ _D2gc2gc2GC5queryMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc2GC6__initZ@Base 6
+ _D2gc2gc2GC6addrOfMFNbPvZPv@Base 6
+ _D2gc2gc2GC6callocMFNbkkPkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC6configS2gc6config6Config@Base 6
+ _D2gc2gc2GC6enableMFZv@Base 6
+ _D2gc2gc2GC6extendMFNbPvkkxC8TypeInfoZk@Base 6
+ _D2gc2gc2GC6gcLockC2gc2gc7GCMutex@Base 6
+ _D2gc2gc2GC6mallocMFNbkkPkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC6sizeOfMFNbPvZk@Base 6
+ _D2gc2gc2GC7addRootMFNbPvZv@Base 6
+ _D2gc2gc2GC7clrAttrMFNbPvkZk@Base 6
+ _D2gc2gc2GC7disableMFZv@Base 6
+ _D2gc2gc2GC7getAttrMFNbPvZk@Base 6
+ _D2gc2gc2GC7reallocMFNbPvkkPkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC7reserveMFNbkZk@Base 6
+ _D2gc2gc2GC7setAttrMFNbPvkZk@Base 6
+ _D2gc2gc2GC8addRangeMFNbNiPvkxC8TypeInfoZv@Base 6
+ _D2gc2gc2GC8getStatsMFNbJS2gc5stats7GCStatsZv@Base 6
+ _D2gc2gc2GC8minimizeMFNbZv@Base 6
+ _D2gc2gc2GC8rootIterMFNaNbNdNiNfZDFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2gc2gc2GC9rangeIterMFNaNbNdNiNfZDFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2gc2gc3Gcx10initializeMFZv@Base 6
+ _D2gc2gc3Gcx10log_mallocMFNbPvkZv@Base 6
+ _D2gc2gc3Gcx10log_parentMFNbPvPvZv@Base 6
+ _D2gc2gc3Gcx10removeRootMFNbPvZv@Base 6
+ _D2gc2gc3Gcx10smallAllocMFNbhKkkZPv@Base 6
+ _D2gc2gc3Gcx11ToScanStack14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack3popMFNbZS2gc2gc5Range@Base 6
+ _D2gc2gc3Gcx11ToScanStack4growMFNbZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack4pushMFNbS2gc2gc5RangeZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack5emptyMxFNbNdZb@Base 6
+ _D2gc2gc3Gcx11ToScanStack5resetMFNbZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D2gc2gc3Gcx11ToScanStack6lengthMxFNbNdZk@Base 6
+ _D2gc2gc3Gcx11ToScanStack7opIndexMNgFNbNckZNgS2gc2gc5Range@Base 6
+ _D2gc2gc3Gcx11ToScanStack8opAssignMFNaNbNcNiNjNeS2gc2gc3Gcx11ToScanStackZS2gc2gc3Gcx11ToScanStack@Base 6
+ _D2gc2gc3Gcx11__fieldDtorMFNbNiZv@Base 6
+ _D2gc2gc3Gcx11__xopEqualsFKxS2gc2gc3GcxKxS2gc2gc3GcxZb@Base 6
+ _D2gc2gc3Gcx11fullcollectMFNbbZk@Base 6
+ _D2gc2gc3Gcx11log_collectMFNbZv@Base 6
+ _D2gc2gc3Gcx11removeRangeMFNbNiPvZv@Base 6
+ _D2gc2gc3Gcx13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZ11smoothDecayFNbffZf@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZ3maxFNbffZf@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZv@Base 6
+ _D2gc2gc3Gcx4DtorMFZv@Base 6
+ _D2gc2gc3Gcx4markMFNbPvPvZv@Base 6
+ _D2gc2gc3Gcx5allocMFNbkKkkZPv@Base 6
+ _D2gc2gc3Gcx5sweepMFNbZk@Base 6
+ _D2gc2gc3Gcx6__initZ@Base 6
+ _D2gc2gc3Gcx6lowMemMxFNbNdZb@Base 6
+ _D2gc2gc3Gcx6npoolsMxFNaNbNdZk@Base 6
+ _D2gc2gc3Gcx7addRootMFNbPvZv@Base 6
+ _D2gc2gc3Gcx7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc3Gcx7markAllMFNbbZv@Base 6
+ _D2gc2gc3Gcx7newPoolMFNbkbZPS2gc2gc4Pool@Base 6
+ _D2gc2gc3Gcx7prepareMFNbZv@Base 6
+ _D2gc2gc3Gcx7recoverMFNbZk@Base 6
+ _D2gc2gc3Gcx7reserveMFNbkZk@Base 6
+ _D2gc2gc3Gcx8addRangeMFNbNiPvPvxC8TypeInfoZv@Base 6
+ _D2gc2gc3Gcx8bigAllocMFNbkKkkxC8TypeInfoZPv@Base 6
+ _D2gc2gc3Gcx8binTablexG2049g@Base 6
+ _D2gc2gc3Gcx8ctfeBinsFNbZG2049g@Base 6
+ _D2gc2gc3Gcx8findBaseMFNbPvZPv@Base 6
+ _D2gc2gc3Gcx8findPoolMFNaNbPvZPS2gc2gc4Pool@Base 6
+ _D2gc2gc3Gcx8findSizeMFNbPvZk@Base 6
+ _D2gc2gc3Gcx8isMarkedMFNbPvZi@Base 6
+ _D2gc2gc3Gcx8log_freeMFNbPvZv@Base 6
+ _D2gc2gc3Gcx8log_initMFNbZv@Base 6
+ _D2gc2gc3Gcx8minimizeMFNbZv@Base 6
+ _D2gc2gc3Gcx8opAssignMFNbNcNiNjS2gc2gc3GcxZS2gc2gc3Gcx@Base 6
+ _D2gc2gc3Gcx9InvariantMxFZv@Base 6
+ _D2gc2gc3Gcx9__xtoHashFNbNeKxS2gc2gc3GcxZk@Base 6
+ _D2gc2gc3Gcx9allocPageMFNbhZPS2gc2gc4List@Base 6
+ _D2gc2gc3setFNaNbNiKG8kkZv@Base 6
+ _D2gc2gc4List6__initZ@Base 6
+ _D2gc2gc4Pool10initializeMFNbkbZv@Base 6
+ _D2gc2gc4Pool12freePageBitsMFNbkKxG8kZv@Base 6
+ _D2gc2gc4Pool4DtorMFNbZv@Base 6
+ _D2gc2gc4Pool6__initZ@Base 6
+ _D2gc2gc4Pool6isFreeMxFNaNbNdZb@Base 6
+ _D2gc2gc4Pool7clrBitsMFNbkkZv@Base 6
+ _D2gc2gc4Pool7getBitsMFNbkZk@Base 6
+ _D2gc2gc4Pool7setBitsMFNbkkZv@Base 6
+ _D2gc2gc4Pool9InvariantMxFZv@Base 6
+ _D2gc2gc4Pool9pagenumOfMxFNbPvZk@Base 6
+ _D2gc2gc4Pool9slGetInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc4Pool9slGetSizeMFNbPvZk@Base 6
+ _D2gc2gc4Root6__initZ@Base 6
+ _D2gc2gc5Range6__initZ@Base 6
+ _D2gc2gc7GCMutex4lockMFNbNiNeZv@Base 6
+ _D2gc2gc7GCMutex6__ctorMFNbNeZC2gc2gc7GCMutex@Base 6
+ _D2gc2gc7GCMutex6__initZ@Base 6
+ _D2gc2gc7GCMutex6__vtblZ@Base 6
+ _D2gc2gc7GCMutex6unlockMFNbNiNeZv@Base 6
+ _D2gc2gc7GCMutex7__ClassZ@Base 6
+ _D2gc2gc7binsizeyG11k@Base 6
+ _D2gc2gc8freeTimel@Base 6
+ _D2gc2gc8lockTimel@Base 6
+ _D2gc2gc8markTimeS4core4time8Duration@Base 6
+ _D2gc2gc8numFreesl@Base 6
+ _D2gc2gc8prepTimeS4core4time8Duration@Base 6
+ _D2gc2gc9GCVERSIONxk@Base 6
+ _D2gc2gc9numOthersl@Base 6
+ _D2gc2gc9otherTimel@Base 6
+ _D2gc2gc9sweepTimeS4core4time8Duration@Base 6
+ _D2gc2os10isLowOnMemFNbNikZb@Base 6
+ _D2gc2os10os_mem_mapFNbkZPv@Base 6
+ _D2gc2os12__ModuleInfoZ@Base 6
+ _D2gc2os12os_mem_unmapFNbPvkZi@Base 6
+ _D2gc4bits12__ModuleInfoZ@Base 6
+ _D2gc4bits6GCBits3setMFNbkZi@Base 6
+ _D2gc4bits6GCBits4DtorMFNbZv@Base 6
+ _D2gc4bits6GCBits4copyMFNbPS2gc4bits6GCBitsZv@Base 6
+ _D2gc4bits6GCBits4testMxFNbkZk@Base 6
+ _D2gc4bits6GCBits4zeroMFNbZv@Base 6
+ _D2gc4bits6GCBits5allocMFNbkZv@Base 6
+ _D2gc4bits6GCBits5clearMFNbkZi@Base 6
+ _D2gc4bits6GCBits6__initZ@Base 6
+ _D2gc4bits6GCBits6nwordsMxFNaNbNdZk@Base 6
+ _D2gc5proxy12__ModuleInfoZ@Base 6
+ _D2gc5proxy3_gcS2gc2gc2GC@Base 6
+ _D2gc5proxy5Proxy6__initZ@Base 6
+ _D2gc5proxy5proxyPS2gc5proxy5Proxy@Base 6
+ _D2gc5proxy5pthisS2gc5proxy5Proxy@Base 6
+ _D2gc5proxy9initProxyFZv@Base 6
+ _D2gc5stats12__ModuleInfoZ@Base 6
+ _D2gc5stats7GCStats6__initZ@Base 6
+ _D2gc6config10parseErrorFNbNixAaxAaxAaZb@Base 6
+ _D2gc6config12__ModuleInfoZ@Base 6
+ _D2gc6config13__T5parseHTbZ5parseFNbNiAxaKAxaKbZb@Base 6
+ _D2gc6config13__T5parseHTfZ5parseFNbNiAxaKAxaKfZb@Base 6
+ _D2gc6config13__T5parseHThZ5parseFNbNiAxaKAxaKhZb@Base 6
+ _D2gc6config13__T5parseHTkZ5parseFNbNiAxaKAxaKkZb@Base 6
+ _D2gc6config18__T4skipS7isspaceZ4skipFNaNbNiNfANgaZANga@Base 6
+ _D2gc6config18__T4skipS7isspaceZ4skipFNbNiANgaZ18__T9__lambda2TNgaZ9__lambda2FNaNbNiNfNgaZb@Base 6
+ _D2gc6config3minFNbNikkZk@Base 6
+ _D2gc6config6Config10initializeMFNbNiZb@Base 6
+ _D2gc6config6Config11__xopEqualsFKxS2gc6config6ConfigKxS2gc6config6ConfigZb@Base 6
+ _D2gc6config6Config12parseOptionsMFNbNiAxaZ18__T9__lambda2TNgaZ9__lambda2FNaNbNiNfNgaZb@Base 6
+ _D2gc6config6Config12parseOptionsMFNbNiAxaZb@Base 6
+ _D2gc6config6Config4helpMFNbNiZv@Base 6
+ _D2gc6config6Config6__initZ@Base 6
+ _D2gc6config6Config9__xtoHashFNbNeKxS2gc6config6ConfigZk@Base 6
+ _D2gc6config8optErrorFNbNixAaxAaZb@Base 6
+ _D2gc9pooltable12__ModuleInfoZ@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable4DtorMFNbNiZv@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6insertMFNbNiPS2gc2gc4PoolZb@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7maxAddrMxFNaNbNdNiNfZPxg@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7minAddrMxFNaNbNdNiNfZPxg@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7opIndexMNgFNaNbNcNikZNgPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7opSliceMNgFNaNbNikkZANgPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8findPoolMFNaNbNiPvZPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8minimizeMFNaNbZ4swapFNaNbNiNfKPS2gc2gc4PoolKPS2gc2gc4PoolZv@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8minimizeMFNaNbZAPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable9InvariantMxFNaNbNiZv@Base 6
+ _D2rt11arrayassign12__ModuleInfoZ@Base 6
+ _D2rt12sections_osx12__ModuleInfoZ@Base 6
+ _D2rt14sections_win3212__ModuleInfoZ@Base 6
+ _D2rt14sections_win6412__ModuleInfoZ@Base 6
+ _D2rt16sections_android12__ModuleInfoZ@Base 6
+ _D2rt16sections_solaris12__ModuleInfoZ@Base 6
+ _D2rt19sections_elf_shared10_rtLoadingb@Base 6
+ _D2rt19sections_elf_shared11_loadedDSOsS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt19sections_elf_shared11getTLSRangeFkkZAv@Base 6
+ _D2rt19sections_elf_shared12__ModuleInfoZ@Base 6
+ _D2rt19sections_elf_shared12_handleToDSOS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab@Base 6
+ _D2rt19sections_elf_shared12decThreadRefFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared12dsoForHandleFNbPvZPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt19sections_elf_shared12finiSectionsFZv@Base 6
+ _D2rt19sections_elf_shared12incThreadRefFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared12initSectionsFZv@Base 6
+ _D2rt19sections_elf_shared12scanSegmentsFKxS4core3sys5linux4link12dl_phdr_infoPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared13findThreadDSOFPS2rt19sections_elf_shared3DSOZPS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt19sections_elf_shared13finiTLSRangesFPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZv@Base 6
+ _D2rt19sections_elf_shared13handleForAddrFPvZPv@Base 6
+ _D2rt19sections_elf_shared13handleForNameFNbxPaZPv@Base 6
+ _D2rt19sections_elf_shared13initTLSRangesFZPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt19sections_elf_shared13runFinalizersFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared13scanTLSRangesFNbPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayMDFNbPvPvZvZv@Base 6
+ _D2rt19sections_elf_shared15CompilerDSOData6__initZ@Base 6
+ _D2rt19sections_elf_shared15getDependenciesFNbKxS4core3sys5linux4link12dl_phdr_infoKS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZv@Base 6
+ _D2rt19sections_elf_shared15setDSOForHandleFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt19sections_elf_shared16linkMapForHandleFNbPvZPS4core3sys5linux4link8link_map@Base 6
+ _D2rt19sections_elf_shared16registerGCRangesFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared17_handleToDSOMutexS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D2rt19sections_elf_shared17unsetDSOForHandleFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ2DG6__initZ@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ8callbackUNbNiPS4core3sys5linux4link12dl_phdr_infokPvZi@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZb@Base 6
+ _D2rt19sections_elf_shared18findSegmentForAddrFNbNiKxS4core3sys5linux4link12dl_phdr_infoxPvPS4core3sys5linux3elf10Elf32_PhdrZb@Base 6
+ _D2rt19sections_elf_shared18pinLoadedLibrariesFNbZPv@Base 6
+ _D2rt19sections_elf_shared18unregisterGCRangesFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared20runModuleDestructorsFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared20unpinLoadedLibrariesFNbPvZv@Base 6
+ _D2rt19sections_elf_shared21_isRuntimeInitializedb@Base 6
+ _D2rt19sections_elf_shared21checkModuleCollisionsFNbKxS4core3sys5linux4link12dl_phdr_infoxAPyS6object10ModuleInfoZv@Base 6
+ _D2rt19sections_elf_shared21runModuleConstructorsFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared22cleanupLoadedLibrariesFZv@Base 6
+ _D2rt19sections_elf_shared22inheritLoadedLibrariesFPvZv@Base 6
+ _D2rt19sections_elf_shared33__T7toRangeTyS3gcc3deh9FuncTableZ7toRangeFNaNbNiPyS3gcc3deh9FuncTablePyS3gcc3deh9FuncTableZAyS3gcc3deh9FuncTable@Base 6
+ _D2rt19sections_elf_shared35__T7toRangeTyPS6object10ModuleInfoZ7toRangeFNaNbNiPyPS6object10ModuleInfoPyPS6object10ModuleInfoZAyPS6object10ModuleInfo@Base 6
+ _D2rt19sections_elf_shared3DSO11__fieldDtorMFNbZv@Base 6
+ _D2rt19sections_elf_shared3DSO11__invariantMxFZv@Base 6
+ _D2rt19sections_elf_shared3DSO11__xopEqualsFKxS2rt19sections_elf_shared3DSOKxS2rt19sections_elf_shared3DSOZb@Base 6
+ _D2rt19sections_elf_shared3DSO11moduleGroupMNgFNcNdZNgS2rt5minfo11ModuleGroup@Base 6
+ _D2rt19sections_elf_shared3DSO12__invariant1MxFZv@Base 6
+ _D2rt19sections_elf_shared3DSO14opApplyReverseFMDFKS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D2rt19sections_elf_shared3DSO7modulesMxFNdZAyPS6object10ModuleInfo@Base 6
+ _D2rt19sections_elf_shared3DSO7opApplyFMDFKS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt19sections_elf_shared3DSO8ehTablesMxFNdZAyS3gcc3deh9FuncTable@Base 6
+ _D2rt19sections_elf_shared3DSO8gcRangesMNgFNdZANgAv@Base 6
+ _D2rt19sections_elf_shared3DSO8opAssignMFNbNcNjS2rt19sections_elf_shared3DSOZS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt19sections_elf_shared3DSO9__xtoHashFNbNeKxS2rt19sections_elf_shared3DSOZk@Base 6
+ _D2rt19sections_elf_shared7dsoNameFNbxPaZAxa@Base 6
+ _D2rt19sections_elf_shared7freeDSOFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared8prognameFNbNdNiZPxa@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO11__xopEqualsFKxS2rt19sections_elf_shared9ThreadDSOKxS2rt19sections_elf_shared9ThreadDSOZb@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO6__initZ@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO9__xtoHashFNbNeKxS2rt19sections_elf_shared9ThreadDSOZk@Base 6
+ _D2rt19sections_elf_shared9finiLocksFZv@Base 6
+ _D2rt19sections_elf_shared9initLocksFZv@Base 6
+ _D2rt19sections_elf_shared9tls_index6__initZ@Base 6
+ _D2rt3aaA10__T3maxTkZ3maxFNaNbNiNfkkZk@Base 6
+ _D2rt3aaA10__T3minTkZ3minFNaNbNiNfkkZk@Base 6
+ _D2rt3aaA10allocEntryFxPS2rt3aaA4ImplxPvZPv@Base 6
+ _D2rt3aaA11fakeEntryTIFxC8TypeInfoxC8TypeInfoZ6tiNameyAa@Base 6
+ _D2rt3aaA11fakeEntryTIFxC8TypeInfoxC8TypeInfoZC15TypeInfo_Struct@Base 6
+ _D2rt3aaA12__ModuleInfoZ@Base 6
+ _D2rt3aaA12allocBucketsFNaNbNekZAS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA2AA5emptyMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA2AA6__initZ@Base 6
+ _D2rt3aaA3mixFNaNbNiNfkZk@Base 6
+ _D2rt3aaA4Impl11__xopEqualsFKxS2rt3aaA4ImplKxS2rt3aaA4ImplZb@Base 6
+ _D2rt3aaA4Impl14findSlotInsertMNgFNaNbNikZPNgS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA4Impl14findSlotLookupMNgFkxPvxC8TypeInfoZPNgS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA4Impl3dimMxFNaNbNdNiZk@Base 6
+ _D2rt3aaA4Impl4growMFxC8TypeInfoZv@Base 6
+ _D2rt3aaA4Impl4maskMxFNaNbNdNiZk@Base 6
+ _D2rt3aaA4Impl6__ctorMFNcxC25TypeInfo_AssociativeArraykZS2rt3aaA4Impl@Base 6
+ _D2rt3aaA4Impl6__initZ@Base 6
+ _D2rt3aaA4Impl6lengthMxFNaNbNdNiZk@Base 6
+ _D2rt3aaA4Impl6resizeMFNaNbkZv@Base 6
+ _D2rt3aaA4Impl6shrinkMFxC8TypeInfoZv@Base 6
+ _D2rt3aaA4Impl9__xtoHashFNbNeKxS2rt3aaA4ImplZk@Base 6
+ _D2rt3aaA5Range6__initZ@Base 6
+ _D2rt3aaA6Bucket5emptyMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6Bucket6__initZ@Base 6
+ _D2rt3aaA6Bucket6filledMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6Bucket7deletedMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6talignFNaNbNiNfkkZk@Base 6
+ _D2rt3aaA7hasDtorFxC8TypeInfoZb@Base 6
+ _D2rt3aaA8calcHashFxPvxC8TypeInfoZk@Base 6
+ _D2rt3aaA8nextpow2FNaNbNixkZk@Base 6
+ _D2rt3aaA9entryDtorFPvxC15TypeInfo_StructZv@Base 6
+ _D2rt3adi12__ModuleInfoZ@Base 6
+ _D2rt3adi19__T11mallocUTF32TaZ11mallocUTF32FNixAaZAw@Base 6
+ _D2rt3adi19__T11mallocUTF32TuZ11mallocUTF32FNixAuZAw@Base 6
+ _D2rt3deh12__ModuleInfoZ@Base 6
+ _D2rt3obj12__ModuleInfoZ@Base 6
+ _D2rt4util3utf10UTF8strideyAi@Base 6
+ _D2rt4util3utf10toUCSindexFxAakZk@Base 6
+ _D2rt4util3utf10toUCSindexFxAukZk@Base 6
+ _D2rt4util3utf10toUCSindexFxAwkZk@Base 6
+ _D2rt4util3utf10toUTFindexFxAakZk@Base 6
+ _D2rt4util3utf10toUTFindexFxAukZk@Base 6
+ _D2rt4util3utf10toUTFindexFxAwkZk@Base 6
+ _D2rt4util3utf12__ModuleInfoZ@Base 6
+ _D2rt4util3utf12isValidDcharFwZb@Base 6
+ _D2rt4util3utf17__T8validateTAyaZ8validateFxAyaZv@Base 6
+ _D2rt4util3utf17__T8validateTAyuZ8validateFxAyuZv@Base 6
+ _D2rt4util3utf17__T8validateTAywZ8validateFxAywZv@Base 6
+ _D2rt4util3utf6decodeFxAaKkZw@Base 6
+ _D2rt4util3utf6decodeFxAuKkZw@Base 6
+ _D2rt4util3utf6decodeFxAwKkZw@Base 6
+ _D2rt4util3utf6encodeFKAawZv@Base 6
+ _D2rt4util3utf6encodeFKAuwZv@Base 6
+ _D2rt4util3utf6encodeFKAwwZv@Base 6
+ _D2rt4util3utf6strideFxAakZk@Base 6
+ _D2rt4util3utf6strideFxAukZk@Base 6
+ _D2rt4util3utf6strideFxAwkZk@Base 6
+ _D2rt4util3utf6toUTF8FAyaZAya@Base 6
+ _D2rt4util3utf6toUTF8FNkJG4awZAa@Base 6
+ _D2rt4util3utf6toUTF8FxAuZAya@Base 6
+ _D2rt4util3utf6toUTF8FxAwZAya@Base 6
+ _D2rt4util3utf7toUTF16FAyuZAyu@Base 6
+ _D2rt4util3utf7toUTF16FNkJG2uwZAu@Base 6
+ _D2rt4util3utf7toUTF16FxAaZAyu@Base 6
+ _D2rt4util3utf7toUTF16FxAwZAyu@Base 6
+ _D2rt4util3utf7toUTF32FAywZAyw@Base 6
+ _D2rt4util3utf7toUTF32FxAaZAyw@Base 6
+ _D2rt4util3utf7toUTF32FxAuZAyw@Base 6
+ _D2rt4util3utf8toUTF16zFxAaZPxu@Base 6
+ _D2rt4util4hash12__ModuleInfoZ@Base 6
+ _D2rt4util4hash6hashOfFNaNbNePxvkkZ9get16bitsFNaNbPxhZk@Base 6
+ _D2rt4util4hash6hashOfFNaNbNePxvkkZk@Base 6
+ _D2rt4util5array12__ModuleInfoZ@Base 6
+ _D2rt4util5array17_enforceNoOverlapFNbNfxAaxPvxPvxkZv@Base 6
+ _D2rt4util5array18_enforceSameLengthFNbNfxAaxkxkZv@Base 6
+ _D2rt4util5array27enforceRawArraysConformableFNbNfxAaxkxAvxAvxbZv@Base 6
+ _D2rt4util6random12__ModuleInfoZ@Base 6
+ _D2rt4util6random6Rand4811defaultSeedMFNbZv@Base 6
+ _D2rt4util6random6Rand484seedMFNbkZv@Base 6
+ _D2rt4util6random6Rand485frontMFNbNdNiZk@Base 6
+ _D2rt4util6random6Rand486__initZ@Base 6
+ _D2rt4util6random6Rand486opCallMFNbNiZk@Base 6
+ _D2rt4util6random6Rand488popFrontMFNbNiZv@Base 6
+ _D2rt4util6string12__ModuleInfoZ@Base 6
+ _D2rt4util6string16sizeToTempStringFNaNbNexkAaZAa@Base 6
+ _D2rt4util6string16uintToTempStringFNaNbNexkAaZAa@Base 6
+ _D2rt4util6string17ulongToTempStringFNaNbNexmAaZAa@Base 6
+ _D2rt4util6string29__T21_unsignedToTempStringTkZ21_unsignedToTempStringFNaNbNiNexkAaZAa@Base 6
+ _D2rt4util6string29__T21_unsignedToTempStringTmZ21_unsignedToTempStringFNaNbNiNexmAaZAa@Base 6
+ _D2rt4util6string7dstrcmpFNaNbNexAaxAaZi@Base 6
+ _D2rt4util8typeinfo12__ModuleInfoZ@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ6equalsFNaNbNfAcAcZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ6hashOfFNaNbNfAcZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ7compareFNaNbNfAcAcZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ6equalsFNaNbNfAdAdZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ6hashOfFNaNbNfAdZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ7compareFNaNbNfAdAdZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ6equalsFNaNbNfAeAeZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ6hashOfFNaNbNfAeZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ7compareFNaNbNfAeAeZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ6equalsFNaNbNfAfAfZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ6hashOfFNaNbNfAfZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ7compareFNaNbNfAfAfZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ6equalsFNaNbNfAqAqZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ6hashOfFNaNbNfAqZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ7compareFNaNbNfAqAqZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ6equalsFNaNbNfArArZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ6hashOfFNaNbNfArZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ7compareFNaNbNfArArZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ6equalsFNaNbNfccZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ6hashOfFNaNbNecZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ7compareFNaNbNfccZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ6equalsFNaNbNfddZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ6hashOfFNaNbNedZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ7compareFNaNbNfddZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ6equalsFNaNbNfeeZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ6hashOfFNaNbNeeZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ7compareFNaNbNfeeZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ6equalsFNaNbNfffZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ6hashOfFNaNbNefZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ7compareFNaNbNfffZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ6equalsFNaNbNfqqZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ6hashOfFNaNbNeqZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ7compareFNaNbNfqqZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ6equalsFNaNbNfrrZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ6hashOfFNaNbNerZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ7compareFNaNbNfrrZi@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array4backMNgFNaNbNcNdNiZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array4swapMFNaNbNiNfKS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5ArrayZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5frontMNgFNaNbNcNdNiNfZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__initZ@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opIndexMNgFNaNbNcNikZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opSliceMNgFNaNbNiZANgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opSliceMNgFNaNbNikkZANgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array8opAssignMFNbNcNjS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5ArrayZS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array@Base 6
+ _D2rt4util9container5array12__ModuleInfoZ@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array16__T10insertBackZ10insertBackMFNbAvZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array4backMNgFNaNbNcNdNiZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array4swapMFNaNbNiNfKS2rt4util9container5array13__T5ArrayTAvZ5ArrayZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5frontMNgFNaNbNcNdNiNfZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opIndexMNgFNaNbNcNikZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opSliceMNgFNaNbNiZANgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opSliceMNgFNaNbNikkZANgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array8opAssignMFNbNcNjS2rt4util9container5array13__T5ArrayTAvZ5ArrayZS2rt4util9container5array13__T5ArrayTAvZ5Array@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array16__T10insertBackZ10insertBackMFNbKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array4backMNgFNaNbNcNdNiZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array4swapMFNaNbNiNfKS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5frontMNgFNaNbNcNdNiNfZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opIndexMNgFNaNbNcNikZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opSliceMNgFNaNbNiZANgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opSliceMNgFNaNbNikkZANgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array8opAssignMFNbNcNjS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array16__T10insertBackZ10insertBackMFNbS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array4backMNgFNaNbNcNdNiZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array4swapMFNaNbNiNfKS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5frontMNgFNaNbNcNdNiNfZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__initZ@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opIndexMNgFNaNbNcNikZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opSliceMNgFNaNbNiZANgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opSliceMNgFNaNbNikkZANgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array8opAssignMFNbNcNjS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt4util9container5treap12__ModuleInfoZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap10initializeMFNbZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap13opApplyHelperFNbxPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeMDFNbKxS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node11__xopEqualsFKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZb@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node9__xtoHashFNbNeKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZk@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__dtorMFNbNiZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6insertMFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeS2gc2gc4RootZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6insertMFNbNiS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6removeFNbNiPPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6removeMFNbNiS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7opApplyMFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7opApplyMxFNbMDFNbKxS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7rotateLFNaNbNiNfPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7rotateRFNaNbNiNfPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap8freeNodeFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap8opAssignMFNbNcNiNjS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5TreapZS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9allocNodeMFNbNiS2gc2gc4RootZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9removeAllFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9removeAllMFNbNiZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap10initializeMFNbZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap13opApplyHelperFNbxPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeMDFNbKxS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node11__xopEqualsFKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZb@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node9__xtoHashFNbNeKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZk@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__dtorMFNbNiZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6insertMFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeS2gc2gc5RangeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6insertMFNbNiS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6removeFNbNiPPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6removeMFNbNiS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7opApplyMFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7opApplyMxFNbMDFNbKxS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7rotateLFNaNbNiNfPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7rotateRFNaNbNiNfPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap8freeNodeFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap8opAssignMFNbNcNiNjS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5TreapZS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9allocNodeMFNbNiS2gc2gc5RangeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9removeAllFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9removeAllMFNbNiZv@Base 6
+ _D2rt4util9container6common101__T7destroyTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common102__T7destroyTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common105__T10initializeTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ10initializeFNaNbNiKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common106__T10initializeTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ10initializeFNaNbNiNfKPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common12__ModuleInfoZ@Base 6
+ _D2rt4util9container6common15__T7destroyTAvZ7destroyFNaNbNiNfKAvZv@Base 6
+ _D2rt4util9container6common19__T10initializeTAvZ10initializeFNaNbNiNfKAvZv@Base 6
+ _D2rt4util9container6common43__T7destroyTPS2rt19sections_elf_shared3DSOZ7destroyFNaNbNiNfKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container6common47__T10initializeTPS2rt19sections_elf_shared3DSOZ10initializeFNaNbNiNfKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container6common48__T7destroyTS2rt19sections_elf_shared9ThreadDSOZ7destroyFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container6common52__T10initializeTS2rt19sections_elf_shared9ThreadDSOZ10initializeFNaNbNiKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container6common7xmallocFNbNikZPv@Base 6
+ _D2rt4util9container6common8xreallocFNbPvkZPv@Base 6
+ _D2rt4util9container7hashtab12__ModuleInfoZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab10__aggrDtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab11__fieldDtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab13opIndexAssignMFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab18ensureNotInOpApplyMFNaNbNiNfZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab3getMFNbPvZPPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node6__initZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4growMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4maskMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab5resetMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__dtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__initZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6hashOfFNaNbKxPvZk@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6opIn_rMNgFNaNbxPvZPNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6removeMFNbxPvZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6shrinkMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab7opApplyMFMDFKPvKPS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab7opIndexMNgFNaNbNcPvZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab8opAssignMFNbNcNjS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTabZS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab@Base 6
+ _D2rt5cast_12__ModuleInfoZ@Base 6
+ _D2rt5minfo11ModuleGroup11__xopEqualsFKxS2rt5minfo11ModuleGroupKxS2rt5minfo11ModuleGroupZb@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsCtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsCtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsDtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsDtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup4freeMFZv@Base 6
+ _D2rt5minfo11ModuleGroup6__ctorMFNcAyPS6object10ModuleInfoZS2rt5minfo11ModuleGroup@Base 6
+ _D2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D2rt5minfo11ModuleGroup7modulesMxFNdZAyPS6object10ModuleInfo@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZ37__T9__lambda2TPyS6object10ModuleInfoZ9__lambda2FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runDtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runDtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup9__xtoHashFNbNeKxS2rt5minfo11ModuleGroupZk@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ10findModuleMFxPS6object10ModuleInfoZi@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec11__xopEqualsFKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecZb@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec3modMFNdZPyS6object10ModuleInfo@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec6__initZ@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec9__xtoHashFNbNeKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecZk@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZv@Base 6
+ _D2rt5minfo12__ModuleInfoZ@Base 6
+ _D2rt5minfo17moduleinfos_applyFMDFyPS6object10ModuleInfoZiZi@Base 6
+ _D2rt5qsort12__ModuleInfoZ@Base 6
+ _D2rt5qsort7_adSortUAvC8TypeInfoZ3cmpUxPvxPvPvZi@Base 6
+ _D2rt5tlsgc12__ModuleInfoZ@Base 6
+ _D2rt5tlsgc14processGCMarksFNbPvMDFNbPvZiZv@Base 6
+ _D2rt5tlsgc4Data6__initZ@Base 6
+ _D2rt5tlsgc4initFZPv@Base 6
+ _D2rt5tlsgc4scanFNbPvMDFNbPvPvZvZv@Base 6
+ _D2rt5tlsgc7destroyFPvZv@Base 6
+ _D2rt6aApply12__ModuleInfoZ@Base 6
+ _D2rt6config12__ModuleInfoZ@Base 6
+ _D2rt6config13rt_linkOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6config15rt_configOptionFNbNiAyaMDFNbNiAyaZAyabZAya@Base 6
+ _D2rt6config16rt_cmdlineOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6config16rt_envvarsOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6dmain210_initCountOk@Base 6
+ _D2rt6dmain211_d_run_mainUiPPaPUAAaZiZ7tryExecMFMDFZvZv@Base 6
+ _D2rt6dmain212__ModuleInfoZ@Base 6
+ _D2rt6dmain212traceHandlerPFPvZC6object9Throwable9TraceInfo@Base 6
+ _D2rt6dmain215formatThrowableFC6object9ThrowableDFNbxAaZvZv@Base 6
+ _D2rt6dmain25CArgs6__initZ@Base 6
+ _D2rt6dmain26_cArgsS2rt6dmain25CArgs@Base 6
+ _D2rt6dmain27_d_argsAAya@Base 6
+ _D2rt6memory12__ModuleInfoZ@Base 6
+ _D2rt6memory16initStaticDataGCFZv@Base 6
+ _D2rt7aApplyR12__ModuleInfoZ@Base 6
+ _D2rt7switch_12__ModuleInfoZ@Base 6
+ _D2rt8arraycat12__ModuleInfoZ@Base 6
+ _D2rt8lifetime10__arrayPadFNaNbNekxC8TypeInfoZk@Base 6
+ _D2rt8lifetime10__blkcacheFNbNdZPS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime11hasPostblitFxC8TypeInfoZb@Base 6
+ _D2rt8lifetime11newCapacityFkkZk@Base 6
+ _D2rt8lifetime12__ModuleInfoZ@Base 6
+ _D2rt8lifetime12__arrayAllocFNaNbkxC8TypeInfoxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__arrayAllocFkKS4core6memory8BlkInfo_xC8TypeInfoxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__arrayStartFNaNbS4core6memory8BlkInfo_ZPv@Base 6
+ _D2rt8lifetime12__doPostblitFPvkxC8TypeInfoZv@Base 6
+ _D2rt8lifetime12__getBlkInfoFNbPvZPS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__nextBlkIdxi@Base 6
+ _D2rt8lifetime12_staticDtor1FZv@Base 6
+ _D2rt8lifetime14collectHandlerPFC6ObjectZb@Base 6
+ _D2rt8lifetime14finalize_arrayFPvkxC15TypeInfo_StructZv@Base 6
+ _D2rt8lifetime14processGCMarksFNbPS4core6memory8BlkInfo_MDFNbPvZiZv@Base 6
+ _D2rt8lifetime15finalize_array2FNbPvkZv@Base 6
+ _D2rt8lifetime15finalize_structFNbPvkZv@Base 6
+ _D2rt8lifetime18__arrayAllocLengthFNaNbKS4core6memory8BlkInfo_xC8TypeInfoZk@Base 6
+ _D2rt8lifetime18__blkcache_storagePS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime18structTypeInfoSizeFNaNbNixC8TypeInfoZk@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock6__initZ@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock6__vtblZ@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock7__ClassZ@Base 6
+ _D2rt8lifetime20__insertBlkInfoCacheFNbS4core6memory8BlkInfo_PS4core6memory8BlkInfo_Zv@Base 6
+ _D2rt8lifetime21__setArrayAllocLengthFNaNbKS4core6memory8BlkInfo_kbxC8TypeInfokZb@Base 6
+ _D2rt8lifetime23callStructDtorsDuringGCyb@Base 6
+ _D2rt8lifetime26hasArrayFinalizerInSegmentFNbPvkxAvZi@Base 6
+ _D2rt8lifetime27hasStructFinalizerInSegmentFNbPvkxAvZi@Base 6
+ _D2rt8lifetime35__T14_d_newarrayOpTS12_d_newarrayTZ14_d_newarrayOpTFNaNbxC8TypeInfoAkZAv@Base 6
+ _D2rt8lifetime36__T14_d_newarrayOpTS13_d_newarrayiTZ14_d_newarrayOpTFNaNbxC8TypeInfoAkZAv@Base 6
+ _D2rt8lifetime5Array6__initZ@Base 6
+ _D2rt8lifetime9unqualifyFNaNbNiNgC8TypeInfoZNgC8TypeInfo@Base 6
+ _D2rt8monitor_10getMonitorFNaNbC6ObjectZPOS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_10setMonitorFNaNbC6ObjectPOS2rt8monitor_7MonitorZv@Base 6
+ _D2rt8monitor_11unlockMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_12__ModuleInfoZ@Base 6
+ _D2rt8monitor_12destroyMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_12disposeEventFNbPS2rt8monitor_7MonitorC6ObjectZv@Base 6
+ _D2rt8monitor_13deleteMonitorFNbPS2rt8monitor_7MonitorZv@Base 6
+ _D2rt8monitor_13ensureMonitorFNbC6ObjectZPOS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_4gmtxS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D2rt8monitor_5gattrS4core3sys5posix3sys5types19pthread_mutexattr_t@Base 6
+ _D2rt8monitor_7Monitor11__xopEqualsFKxS2rt8monitor_7MonitorKxS2rt8monitor_7MonitorZb@Base 6
+ _D2rt8monitor_7Monitor6__initZ@Base 6
+ _D2rt8monitor_7Monitor9__xtoHashFNbNeKxS2rt8monitor_7MonitorZk@Base 6
+ _D2rt8monitor_7monitorFNaNbNcNdC6ObjectZOPS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_9initMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_9lockMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8sections12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Acfloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ap4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ap8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Adouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4initMxFNaNbNeZ1ryr@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_cdouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_idouble10TypeInfo_p8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_idouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo11ti_Acdouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo11ti_delegate12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C6equalsMxFNexPvxPvZb@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C7compareMxFNexPvxPvZi@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo4ti_C12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_AC12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ab4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ab8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Av4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Av8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Axa4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Axa8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Aya4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Aya8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo6ti_int12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo6ti_ptr12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Aw4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Aw8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_byte12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_cent12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4initMxFNaNbNeZ1cya@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_char12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l6talignMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_long12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4initMxFNaNbNeZ1rye@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_real12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_uint12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_void12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Along12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Aj4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Aj8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Areal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4initMxFNaNbNeZ1ryc@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_creal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4initMxFNaNbNeZ1cyw@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_dchar12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4initMxFNaNbNeZ1ryf@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_float12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ireal10TypeInfo_j8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ireal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_short12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_b8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ubyte12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ucent12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m6talignMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ulong12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4initMxFNaNbNeZ1cyu@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u8toStringMxFNaNbNeZAya@Base 6
+ _D2rt8typeinfo8ti_wchar12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Acreal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Ao4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Ao8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Afloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_Au4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_Au8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4initMxFNaNbNeZ1ryq@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_cfloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4initMxFNaNbNeZ1ryd@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_double12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_ifloat10TypeInfo_o8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_ifloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_ushort12__ModuleInfoZ@Base 6
+ _D2rt9arraycast12__ModuleInfoZ@Base 6
+ _D2rt9critical_11ensureMutexFNbPOS2rt9critical_18D_CRITICAL_SECTIONZv@Base 6
+ _D2rt9critical_12__ModuleInfoZ@Base 6
+ _D2rt9critical_18D_CRITICAL_SECTION6__initZ@Base 6
+ _D2rt9critical_3gcsOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D2rt9critical_4headOPS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D30TypeInfo_AC4core6thread6Thread6__initZ@Base 6
+ _D30TypeInfo_AyS3gcc3deh9FuncTable6__initZ@Base 6
+ _D30TypeInfo_E4core4time9ClockType6__initZ@Base 6
+ _D30TypeInfo_S2rt8monitor_7Monitor6__initZ@Base 6
+ _D30TypeInfo_yS6object10ModuleInfo6__initZ@Base 6
+ _D31TypeInfo_E4core6thread8IsMarked6__initZ@Base 6
+ _D31TypeInfo_E4core6thread8ScanType6__initZ@Base 6
+ _D31TypeInfo_PyS6object10ModuleInfo6__initZ@Base 6
+ _D31TypeInfo_S4core5cpuid9CacheInfo6__initZ@Base 6
+ _D31TypeInfo_S4core6memory8BlkInfo_6__initZ@Base 6
+ _D31TypeInfo_S4core7runtime7Runtime6__initZ@Base 6
+ _D31TypeInfo_xAyS3gcc3deh9FuncTable6__initZ@Base 6
+ _D31TypeInfo_yPS6object10ModuleInfo6__initZ@Base 6
+ _D32TypeInfo_AyPS6object10ModuleInfo6__initZ@Base 6
+ _D32TypeInfo_C6object6Object7Monitor6__initZ@Base 6
+ _D32TypeInfo_S2rt4util6random6Rand486__initZ@Base 6
+ _D32TypeInfo_S2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D32TypeInfo_S4core4stdc4fenv6fenv_t6__initZ@Base 6
+ _D32TypeInfo_xPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_AxPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_E4core6memory2GC7BlkAttr6__initZ@Base 6
+ _D33TypeInfo_E4core6thread5Fiber4Call6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc15LargeObjectPool6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc15SmallObjectPool6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc5stdio6fpos_t6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc6locale5lconv6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc6stdlib5div_t6__initZ@Base 6
+ _D33TypeInfo_S4core8demangle8Demangle6__initZ@Base 6
+ _D33TypeInfo_S6object14OffsetTypeInfo6__initZ@Base 6
+ _D33TypeInfo_xAPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_xAyPS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_xC6object6Object7Monitor6__initZ@Base 6
+ _D33TypeInfo_xS2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D34TypeInfo_E3gcc6config11ThreadModel6__initZ@Base 6
+ _D34TypeInfo_E4core6thread5Fiber5State6__initZ@Base 6
+ _D34TypeInfo_E4core6thread6Thread4Call6__initZ@Base 6
+ _D34TypeInfo_S4core4stdc6stdlib6ldiv_t6__initZ@Base 6
+ _D34TypeInfo_S4core4time12TickDuration6__initZ@Base 6
+ _D34TypeInfo_xS2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D35TypeInfo_E4core6atomic11MemoryOrder6__initZ@Base 6
+ _D35TypeInfo_S4core3sys5posix3grp5group6__initZ@Base 6
+ _D35TypeInfo_S4core4stdc5stdio8_IO_FILE6__initZ@Base 6
+ _D35TypeInfo_S4core4stdc6stdlib7lldiv_t6__initZ@Base 6
+ _D36TypeInfo_E4core6thread5Fiber7Rethrow6__initZ@Base 6
+ _D36TypeInfo_S3gcc3deh16globalExceptions6__initZ@Base 6
+ _D36TypeInfo_S3gcc3deh16lsda_header_info6__initZ@Base 6
+ _D36TypeInfo_S3gcc9backtrace10SymbolInfo6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix3pwd6passwd6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D37TypeInfo_C6object9Throwable9TraceInfo6__initZ@Base 6
+ _D37TypeInfo_S4core3sys5posix4poll6pollfd6__initZ@Base 6
+ _D37TypeInfo_S4core3sys5posix5fcntl5flock6__initZ@Base 6
+ _D37TypeInfo_S4core4stdc6wchar_9mbstate_t6__initZ@Base 6
+ _D37TypeInfo_S4core6thread6Thread7Context6__initZ@Base 6
+ _D38TypeInfo_S2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D38TypeInfo_S3gcc3deh18d_exception_header6__initZ@Base 6
+ _D38TypeInfo_S4core3sys5linux4link7r_debug6__initZ@Base 6
+ _D38TypeInfo_S4core3sys5posix5netdb6netent6__initZ@Base 6
+ _D38TypeInfo_S4core8internal7convert5Float6__initZ@Base 6
+ _D39TypeInfo_S3gcc9backtrace13SymbolOrError6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Dyn6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Lib6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Rel6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Sym6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Dyn6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Lib6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Rel6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Sym6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux4link8link_map6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux5dlfcn7Dl_info6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix3sys3uio5iovec6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5dlfcn7Dl_info6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5netdb7hostent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5netdb7servent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5utime7utimbuf6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix6dirent6dirent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix6signal6sigval6__initZ@Base 6
+ _D39TypeInfo_S4core4stdc8inttypes9imaxdiv_t6__initZ@Base 6
+ _D39TypeInfo_xS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D39TypeInfo_xS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D3etc5linux11memoryerror12__ModuleInfoZ@Base 6
+ _D3gcc12libbacktrace12__ModuleInfoZ@Base 6
+ _D3gcc12libbacktrace15backtrace_state6__initZ@Base 6
+ _D3gcc3deh12__ModuleInfoZ@Base 6
+ _D3gcc3deh15__gdc_terminateFZv@Base 6
+ _D3gcc3deh16globalExceptions6__initZ@Base 6
+ _D3gcc3deh16lsda_header_info6__initZ@Base 6
+ _D3gcc3deh17parse_lsda_headerFPS3gcc6unwind7generic15_Unwind_ContextPhPS3gcc3deh16lsda_header_infoZPh@Base 6
+ _D3gcc3deh18__globalExceptionsS3gcc3deh16globalExceptions@Base 6
+ _D3gcc3deh18d_exception_header11__xopEqualsFKxS3gcc3deh18d_exception_headerKxS3gcc3deh18d_exception_headerZb@Base 6
+ _D3gcc3deh18d_exception_header6__initZ@Base 6
+ _D3gcc3deh18d_exception_header9__xtoHashFNbNeKxS3gcc3deh18d_exception_headerZk@Base 6
+ _D3gcc3deh19get_classinfo_entryFPS3gcc3deh16lsda_header_infokZC14TypeInfo_Class@Base 6
+ _D3gcc3deh21__gdc_exception_classxm@Base 6
+ _D3gcc3deh21save_caught_exceptionFPS3gcc6unwind7generic17_Unwind_ExceptionPS3gcc6unwind7generic15_Unwind_ContextiPhkPhZv@Base 6
+ _D3gcc3deh22__gdc_personality_implFiibPS3gcc6unwind7generic17_Unwind_ExceptionPS3gcc6unwind7generic15_Unwind_ContextZk@Base 6
+ _D3gcc3deh24restore_caught_exceptionFPS3gcc6unwind7generic17_Unwind_ExceptionKiKPhKkZv@Base 6
+ _D3gcc3deh28get_exception_header_from_ueFPS3gcc6unwind7generic17_Unwind_ExceptionZPS3gcc3deh18d_exception_header@Base 6
+ _D3gcc3deh9FuncTable6__initZ@Base 6
+ _D3gcc6config12__ModuleInfoZ@Base 6
+ _D3gcc6unwind12__ModuleInfoZ@Base 6
+ _D3gcc6unwind2pe12__ModuleInfoZ@Base 6
+ _D3gcc6unwind2pe12read_sleb128FPhPiZPh@Base 6
+ _D3gcc6unwind2pe12read_uleb128FPhPkZPh@Base 6
+ _D3gcc6unwind2pe18read_encoded_valueFPS3gcc6unwind7generic15_Unwind_ContexthPhPkZPh@Base 6
+ _D3gcc6unwind2pe21base_of_encoded_valueFhPS3gcc6unwind7generic15_Unwind_ContextZk@Base 6
+ _D3gcc6unwind2pe21size_of_encoded_valueFhZk@Base 6
+ _D3gcc6unwind2pe28read_encoded_value_with_baseFhkPhPkZ9unaligned6__initZ@Base 6
+ _D3gcc6unwind2pe28read_encoded_value_with_baseFhkPhPkZPh@Base 6
+ _D3gcc6unwind3arm12__ModuleInfoZ@Base 6
+ _D3gcc6unwind7generic12__ModuleInfoZ@Base 6
+ _D3gcc6unwind7generic17_Unwind_Exception6__initZ@Base 6
+ _D3gcc7atomics12__ModuleInfoZ@Base 6
+ _D3gcc8builtins12__ModuleInfoZ@Base 6
+ _D3gcc9attribute12__ModuleInfoZ@Base 6
+ _D3gcc9backtrace10SymbolInfo6__initZ@Base 6
+ _D3gcc9backtrace10formatLineFxS3gcc9backtrace10SymbolInfoKG512aZAa@Base 6
+ _D3gcc9backtrace12LibBacktrace11initializedb@Base 6
+ _D3gcc9backtrace12LibBacktrace16initLibBacktraceFZv@Base 6
+ _D3gcc9backtrace12LibBacktrace5statePS3gcc12libbacktrace15backtrace_state@Base 6
+ _D3gcc9backtrace12LibBacktrace6__ctorMFiZC3gcc9backtrace12LibBacktrace@Base 6
+ _D3gcc9backtrace12LibBacktrace6__initZ@Base 6
+ _D3gcc9backtrace12LibBacktrace6__vtblZ@Base 6
+ _D3gcc9backtrace12LibBacktrace7__ClassZ@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFDFKkKS3gcc9backtrace13SymbolOrErrorZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKkKxAaZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKxAaZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace8toStringMxFZAya@Base 6
+ _D3gcc9backtrace12__ModuleInfoZ@Base 6
+ _D3gcc9backtrace13SymbolOrError6__initZ@Base 6
+ _D3gcc9backtrace18SymbolCallbackInfo5resetMFZv@Base 6
+ _D3gcc9backtrace18SymbolCallbackInfo6__initZ@Base 6
+ _D3gcc9backtrace19SymbolCallbackInfo26__initZ@Base 6
+ _D40TypeInfo_PxS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D40TypeInfo_PxS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5linux4tipc9tipc_name6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix3sys3msg6msgbuf6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix5netdb8addrinfo6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix5netdb8protoent6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix6signal7stack_t6__initZ@Base 6
+ _D40TypeInfo_xPS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D40TypeInfo_xPS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D41TypeInfo_E4core8demangle8Demangle7AddType6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Ehdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Move6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Nhdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Phdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Rela6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Shdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Ehdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Move6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Nhdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Phdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Rela6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Shdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys3msg7msginfo6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigevent6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigset_t6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigstack6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8timespec6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix7termios7termios6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix9semaphore5sem_t6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux3elf11Elf32_gptab6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux3elf11Elf_Options6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux4tipc10tipc_event6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3ipc8ipc_perm6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3msg8msqid_ds6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3shm8shmid_ds6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys4time7timeval6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys5ioctl6termio6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix4time10itimerspec6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix6signal9siginfo_t6__initZ@Base 6
+ _D42TypeInfo_xE4core8demangle8Demangle7AddType6__initZ@Base 6
+ _D43TypeInfo_E4core3sys5posix3sys4wait8idtype_t6__initZ@Base 6
+ _D43TypeInfo_E4core3sys5posix3sys7statvfs5FFlag6__initZ@Base 6
+ _D43TypeInfo_S2rt9critical_18D_CRITICAL_SECTION6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf32_Verdef6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf32_auxv_t6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf64_Verdef6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf64_auxv_t6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux4tipc11tipc_portid6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux4tipc11tipc_subscr6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux5dlfcn10Dl_serinfo6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux5dlfcn10Dl_serpath6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys5ioctl7winsize6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6select6fd_set6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6socket6linger6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6socket6msghdr6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix4arpa4inet7in_addr6__initZ@Base 6
+ _D44TypeInfo_S2rt19sections_elf_shared9ThreadDSO6__initZ@Base 6
+ _D44TypeInfo_S2rt19sections_elf_shared9tls_index6__initZ@Base 6
+ _D44TypeInfo_S3gcc9backtrace18SymbolCallbackInfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_RegInfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Syminfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Verdaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Vernaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Verneed6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Syminfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Verdaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Vernaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Verneed6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux4link12dl_phdr_info6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux5epoll11epoll_event6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys4time9itimerval6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys5ioctl8termios26__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys6socket7cmsghdr6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix5sched11sched_param6__initZ@Base 6
+ _D45TypeInfo_E4core8demangle8Demangle10IsDelegate6__initZ@Base 6
+ _D45TypeInfo_E4core8internal7convert11FloatFormat6__initZ@Base 6
+ _D45TypeInfo_E6object14TypeInfo_Class10ClassFlags6__initZ@Base 6
+ _D45TypeInfo_S3gcc12libbacktrace15backtrace_state6__initZ@Base 6
+ _D45TypeInfo_S3gcc9backtrace19SymbolCallbackInfo26__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf14Elf_Options_Hw6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf9Elf32_Dyn5_d_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf9Elf64_Dyn5_d_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux4tipc13tipc_name_seq6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux5epoll12epoll_data_t6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys2un11sockaddr_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys6socket8sockaddr6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys7utsname7utsname6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys8resource6rlimit6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys8resource6rusage6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix6signal11sigaction_t6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5linux3sys7sysinfo8sysinfo_6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix7netinet3in_8in6_addr6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix8ucontext10mcontext_t6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix8ucontext10ucontext_t6__initZ@Base 6
+ _D46TypeInfo_S4core4stdc6wchar_9mbstate_t8___value6__initZ@Base 6
+ _D46TypeInfo_S4core4sync5mutex5Mutex12MonitorProxy6__initZ@Base 6
+ _D47TypeInfo_E6object15TypeInfo_Struct11StructFlags6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix3sys7statvfs9statvfs_t6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix6setjmp13__jmp_buf_tag6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix7netinet3in_9ipv6_mreq6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix8ucontext11_libc_fpreg6__initZ@Base 6
+ _D48TypeInfo_S3gcc6unwind7generic17_Unwind_Exception6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5linux3elf12Elf32_auxv_t5_a_un6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5linux3elf12Elf64_auxv_t5_a_un6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5posix3net3if_14if_nameindex_t6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5posix8ucontext13_libc_fpstate6__initZ@Base 6
+ _D49TypeInfo_xS3gcc6unwind7generic17_Unwind_Exception6__initZ@Base 6
+ _D4core10checkedint12__ModuleInfoZ@Base 6
+ _D4core10checkedint4addsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4addsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4adduFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4adduFNaNbNiNfmmKbZm@Base 6
+ _D4core10checkedint4mulsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4mulsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4muluFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4muluFNaNbNiNfmmKbZm@Base 6
+ _D4core10checkedint4negsFNaNbNiNfiKbZi@Base 6
+ _D4core10checkedint4negsFNaNbNiNflKbZl@Base 6
+ _D4core10checkedint4subsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4subsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4subuFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4subuFNaNbNiNfmmKbZm@Base 6
+ _D4core3sys5linux3elf10Elf32_Ehdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Move6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Nhdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Phdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Rela6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Shdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Ehdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Move6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Nhdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Phdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Rela6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Shdr6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab10_gt_header6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab9_gt_entry6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf_Options6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_Verdef6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_auxv_t5_a_un6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_auxv_t6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_Verdef6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_auxv_t5_a_un6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_auxv_t6__initZ@Base 6
+ _D4core3sys5linux3elf12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3elf13Elf32_RegInfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Syminfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Verdaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Vernaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Verneed6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Syminfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Verdaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Vernaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Verneed6__initZ@Base 6
+ _D4core3sys5linux3elf14Elf_Options_Hw6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Dyn5_d_un6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Dyn6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Lib6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Rel6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Sym6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Dyn5_d_un6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Dyn6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Lib6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Rel6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Sym6__initZ@Base 6
+ _D4core3sys5linux3sys4mman12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys5xattr12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7inotify12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7inotify13inotify_event6__initZ@Base 6
+ _D4core3sys5linux3sys7sysinfo12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7sysinfo8sysinfo_6__initZ@Base 6
+ _D4core3sys5linux3sys8signalfd12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys8signalfd16signalfd_siginfo6__initZ@Base 6
+ _D4core3sys5linux4link12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4link12dl_phdr_info6__initZ@Base 6
+ _D4core3sys5linux4link7r_debug6__initZ@Base 6
+ _D4core3sys5linux4link8link_map6__initZ@Base 6
+ _D4core3sys5linux4time12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4tipc10tipc_event6__initZ@Base 6
+ _D4core3sys5linux4tipc11tipc_portid6__initZ@Base 6
+ _D4core3sys5linux4tipc11tipc_subscr6__initZ@Base 6
+ _D4core3sys5linux4tipc12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc4Addr4Name6__initZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc4Addr6__initZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc6__initZ@Base 6
+ _D4core3sys5linux4tipc13tipc_name_seq6__initZ@Base 6
+ _D4core3sys5linux4tipc9tipc_name6__initZ@Base 6
+ _D4core3sys5linux5dlfcn10Dl_serinfo6__initZ@Base 6
+ _D4core3sys5linux5dlfcn10Dl_serpath6__initZ@Base 6
+ _D4core3sys5linux5dlfcn12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5dlfcn7Dl_info6__initZ@Base 6
+ _D4core3sys5linux5epoll11epoll_event6__initZ@Base 6
+ _D4core3sys5linux5epoll12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5epoll12epoll_data_t6__initZ@Base 6
+ _D4core3sys5linux5errno12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5stdio12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5stdio21cookie_io_functions_t6__initZ@Base 6
+ _D4core3sys5linux6config12__ModuleInfoZ@Base 6
+ _D4core3sys5linux7termios12__ModuleInfoZ@Base 6
+ _D4core3sys5linux8execinfo12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3grp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3grp5group6__initZ@Base 6
+ _D4core3sys5posix3net3if_12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3net3if_14if_nameindex_t6__initZ@Base 6
+ _D4core3sys5posix3pwd12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3pwd6passwd6__initZ@Base 6
+ _D4core3sys5posix3sys2un11sockaddr_un6__initZ@Base 6
+ _D4core3sys5posix3sys2un12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3ipc12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3ipc8ipc_perm6__initZ@Base 6
+ _D4core3sys5posix3sys3msg12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3msg6msgbuf6__initZ@Base 6
+ _D4core3sys5posix3sys3msg7msginfo6__initZ@Base 6
+ _D4core3sys5posix3sys3msg8msqid_ds6__initZ@Base 6
+ _D4core3sys5posix3sys3shm12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3shm8shmid_ds6__initZ@Base 6
+ _D4core3sys5posix3sys3uio12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3uio5iovec6__initZ@Base 6
+ _D4core3sys5posix3sys4mman12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4stat12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D4core3sys5posix3sys4stat7S_ISBLKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISCHRFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISDIRFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISLNKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISREGFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISFIFOFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISSOCKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISTYPEFNbNikkZb@Base 6
+ _D4core3sys5posix3sys4time12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4time7timeval6__initZ@Base 6
+ _D4core3sys5posix3sys4time9itimerval6__initZ@Base 6
+ _D4core3sys5posix3sys4wait10WIFSTOPPEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys4wait10__WTERMSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait11WEXITSTATUSFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait11WIFSIGNALEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys4wait12WIFCONTINUEDFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4wait8WSTOPSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait8WTERMSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait9WIFEXITEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTiZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTkZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTnZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IORTkZ4_IORFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOWTiZ4_IOWFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys5ioctl3_IOFNbNiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IOCTS4core3sys5posix3sys5ioctl8termios2Z4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IORTS4core3sys5posix3sys5ioctl8termios2Z4_IORFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IOWTS4core3sys5posix3sys5ioctl8termios2Z4_IOWFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl6termio6__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl7_IOC_NRFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl7winsize6__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl8_IOC_DIRFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl8termios26__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl9_IOC_SIZEFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl9_IOC_TYPEFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5types12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys5types14pthread_attr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types14pthread_cond_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types16pthread_rwlock_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types17_pthread_fastlock6__initZ@Base 6
+ _D4core3sys5posix3sys5types17pthread_barrier_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types18pthread_condattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types19pthread_mutexattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types20pthread_rwlockattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types21pthread_barrierattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys6select12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys6select6FD_CLRFNbNiiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select6FD_SETFNbNiiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select6fd_set6__initZ@Base 6
+ _D4core3sys5posix3sys6select7FD_ZEROFNbNiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select7__FDELTFNaNbNiNfiZk@Base 6
+ _D4core3sys5posix3sys6select8FD_ISSETFNbNiiPxS4core3sys5posix3sys6select6fd_setZb@Base 6
+ _D4core3sys5posix3sys6select8__FDMASKFNaNbNiNfiZi@Base 6
+ _D4core3sys5posix3sys6socket10CMSG_ALIGNFNaNbNikZk@Base 6
+ _D4core3sys5posix3sys6socket10CMSG_SPACEFNaNbNikZk@Base 6
+ _D4core3sys5posix3sys6socket11CMSG_NXTHDRFNaNbNiPNgS4core3sys5posix3sys6socket6msghdrPNgS4core3sys5posix3sys6socket7cmsghdrZPNgS4core3sys5posix3sys6socket7cmsghdr@Base 6
+ _D4core3sys5posix3sys6socket12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys6socket13CMSG_FIRSTHDRFNaNbNiPNgS4core3sys5posix3sys6socket6msghdrZPNgS4core3sys5posix3sys6socket7cmsghdr@Base 6
+ _D4core3sys5posix3sys6socket16sockaddr_storage6__initZ@Base 6
+ _D4core3sys5posix3sys6socket6linger6__initZ@Base 6
+ _D4core3sys5posix3sys6socket6msghdr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket7cmsghdr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket8CMSG_LENFNaNbNikZk@Base 6
+ _D4core3sys5posix3sys6socket8sockaddr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket9CMSG_DATAFNaNbNiPNgS4core3sys5posix3sys6socket7cmsghdrZPNgh@Base 6
+ _D4core3sys5posix3sys7statvfs12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys7statvfs5FFlag6__initZ@Base 6
+ _D4core3sys5posix3sys7statvfs9statvfs_t6__initZ@Base 6
+ _D4core3sys5posix3sys7utsname12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys7utsname7utsname6__initZ@Base 6
+ _D4core3sys5posix3sys8resource12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys8resource6rlimit6__initZ@Base 6
+ _D4core3sys5posix3sys8resource6rusage6__initZ@Base 6
+ _D4core3sys5posix4arpa4inet12__ModuleInfoZ@Base 6
+ _D4core3sys5posix4arpa4inet7in_addr6__initZ@Base 6
+ _D4core3sys5posix4poll12__ModuleInfoZ@Base 6
+ _D4core3sys5posix4poll6pollfd6__initZ@Base 6
+ _D4core3sys5posix4time10itimerspec6__initZ@Base 6
+ _D4core3sys5posix4time12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5dlfcn12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5dlfcn7Dl_info6__initZ@Base 6
+ _D4core3sys5posix5fcntl12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5fcntl5flock6__initZ@Base 6
+ _D4core3sys5posix5netdb12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5netdb6netent6__initZ@Base 6
+ _D4core3sys5posix5netdb7hostent6__initZ@Base 6
+ _D4core3sys5posix5netdb7hostent6h_addrMUNdZPa@Base 6
+ _D4core3sys5posix5netdb7servent6__initZ@Base 6
+ _D4core3sys5posix5netdb8addrinfo6__initZ@Base 6
+ _D4core3sys5posix5netdb8protoent6__initZ@Base 6
+ _D4core3sys5posix5sched11sched_param6__initZ@Base 6
+ _D4core3sys5posix5sched12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5stdio12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5utime12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5utime7utimbuf6__initZ@Base 6
+ _D4core3sys5posix6config12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6dirent12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D4core3sys5posix6dirent6dirent6__initZ@Base 6
+ _D4core3sys5posix6setjmp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6setjmp13__jmp_buf_tag6__initZ@Base 6
+ _D4core3sys5posix6signal11sigaction_t6__initZ@Base 6
+ _D4core3sys5posix6signal12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6signal6sigval6__initZ@Base 6
+ _D4core3sys5posix6signal7stack_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent11_sigev_un_t15_sigev_thread_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent11_sigev_un_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent6__initZ@Base 6
+ _D4core3sys5posix6signal8sigset_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigstack6__initZ@Base 6
+ _D4core3sys5posix6signal8timespec6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t10_sigpoll_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t11_sigchild_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t11_sigfault_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t5_rt_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t7_kill_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t8_timer_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t6si_pidMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6signal9siginfo_t6si_uidMUNbNcNdNiNjZk@Base 6
+ _D4core3sys5posix6signal9siginfo_t7si_addrMUNbNcNdNiNjZPv@Base 6
+ _D4core3sys5posix6signal9siginfo_t7si_bandMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6signal9siginfo_t8si_valueMUNbNcNdNiNjZS4core3sys5posix6signal6sigval@Base 6
+ _D4core3sys5posix6signal9siginfo_t9si_statusMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6stdlib12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6syslog12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6unistd12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7netinet3in_11sockaddr_in6__initZ@Base 6
+ _D4core3sys5posix7netinet3in_12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7netinet3in_12sockaddr_in66__initZ@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_LOOPBACKFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_V4COMPATFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_V4MAPPEDFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_LINKLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_MC_GLOBALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_MULTICASTFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_SITELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_23IN6_IS_ADDR_MC_ORGLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_23IN6_IS_ADDR_UNSPECIFIEDFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_LINKLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_NODELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_SITELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_8in6_addr6__initZ@Base 6
+ _D4core3sys5posix7netinet3in_9ipv6_mreq6__initZ@Base 6
+ _D4core3sys5posix7netinet3tcp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7pthread12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup6__initZ@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup8__T3popZ3popMFNbiZv@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup9__T4pushZ4pushMFNbPUNbPvZvPvZv@Base 6
+ _D4core3sys5posix7pthread23_pthread_cleanup_buffer6__initZ@Base 6
+ _D4core3sys5posix7termios12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7termios7termios6__initZ@Base 6
+ _D4core3sys5posix8inttypes12__ModuleInfoZ@Base 6
+ _D4core3sys5posix8ucontext10mcontext_t6__initZ@Base 6
+ _D4core3sys5posix8ucontext10ucontext_t6__initZ@Base 6
+ _D4core3sys5posix8ucontext11_libc_fpreg6__initZ@Base 6
+ _D4core3sys5posix8ucontext12__ModuleInfoZ@Base 6
+ _D4core3sys5posix8ucontext13_libc_fpstate6__initZ@Base 6
+ _D4core3sys5posix9semaphore12__ModuleInfoZ@Base 6
+ _D4core3sys5posix9semaphore17_pthread_fastlock6__initZ@Base 6
+ _D4core3sys5posix9semaphore5sem_t6__initZ@Base 6
+ _D4core4math12__ModuleInfoZ@Base 6
+ _D4core4simd12__ModuleInfoZ@Base 6
+ _D4core4stdc4fenv12__ModuleInfoZ@Base 6
+ _D4core4stdc4fenv6fenv_t6__initZ@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNedZi@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNeeZi@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNefZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeddZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeeeZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeffZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeddZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeeeZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeffZi@Base 6
+ _D4core4stdc4math12__ModuleInfoZ@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeddZi@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeeeZi@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeffZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeddZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeeeZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeffZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNedZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNeeZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNefZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNedZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNeeZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNefZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeddZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeeeZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeffZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNedZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNeeZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNefZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNedZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNeeZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNefZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNedZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNeeZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNefZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeddZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeeeZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeffZi@Base 6
+ _D4core4stdc4time12__ModuleInfoZ@Base 6
+ _D4core4stdc4time2tm6__initZ@Base 6
+ _D4core4stdc5ctype12__ModuleInfoZ@Base 6
+ _D4core4stdc5errno12__ModuleInfoZ@Base 6
+ _D4core4stdc5errno5errnoFNbNdNiNeZi@Base 6
+ _D4core4stdc5errno5errnoFNbNdNiNeiZi@Base 6
+ _D4core4stdc5stdio12__ModuleInfoZ@Base 6
+ _D4core4stdc5stdio4getcFNbNiNePOS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D4core4stdc5stdio4putcFNbNiNeiPOS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D4core4stdc5stdio6fpos_t6__initZ@Base 6
+ _D4core4stdc5stdio7getcharFNbNiNeZi@Base 6
+ _D4core4stdc5stdio7putcharFNbNiNeiZi@Base 6
+ _D4core4stdc5stdio8_IO_FILE6__initZ@Base 6
+ _D4core4stdc6config12__ModuleInfoZ@Base 6
+ _D4core4stdc6float_12__ModuleInfoZ@Base 6
+ _D4core4stdc6limits12__ModuleInfoZ@Base 6
+ _D4core4stdc6locale12__ModuleInfoZ@Base 6
+ _D4core4stdc6locale5lconv6__initZ@Base 6
+ _D4core4stdc6signal12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdarg12__ModuleInfoZ@Base 6
+ _D4core4stdc6stddef12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdint12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdint14__T7_typifyTgZ7_typifyFNaNbNiNfgZg@Base 6
+ _D4core4stdc6stdint14__T7_typifyThZ7_typifyFNaNbNiNfhZh@Base 6
+ _D4core4stdc6stdint14__T7_typifyTiZ7_typifyFNaNbNiNfiZi@Base 6
+ _D4core4stdc6stdint14__T7_typifyTkZ7_typifyFNaNbNiNfkZk@Base 6
+ _D4core4stdc6stdint14__T7_typifyTlZ7_typifyFNaNbNiNflZl@Base 6
+ _D4core4stdc6stdint14__T7_typifyTmZ7_typifyFNaNbNiNfmZm@Base 6
+ _D4core4stdc6stdint14__T7_typifyTsZ7_typifyFNaNbNiNfsZs@Base 6
+ _D4core4stdc6stdint14__T7_typifyTtZ7_typifyFNaNbNiNftZt@Base 6
+ _D4core4stdc6stdlib12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdlib5div_t6__initZ@Base 6
+ _D4core4stdc6stdlib6ldiv_t6__initZ@Base 6
+ _D4core4stdc6stdlib7lldiv_t6__initZ@Base 6
+ _D4core4stdc6string12__ModuleInfoZ@Base 6
+ _D4core4stdc6tgmath12__ModuleInfoZ@Base 6
+ _D4core4stdc6wchar_12__ModuleInfoZ@Base 6
+ _D4core4stdc6wchar_5getwcFNbNiNePOS4core4stdc5stdio8_IO_FILEZw@Base 6
+ _D4core4stdc6wchar_5putwcFNbNiNewPOS4core4stdc5stdio8_IO_FILEZw@Base 6
+ _D4core4stdc6wchar_8getwcharFNbNiNeZw@Base 6
+ _D4core4stdc6wchar_8putwcharFNbNiNewZw@Base 6
+ _D4core4stdc6wchar_9mbstate_t6__initZ@Base 6
+ _D4core4stdc6wchar_9mbstate_t8___value6__initZ@Base 6
+ _D4core4stdc6wctype12__ModuleInfoZ@Base 6
+ _D4core4stdc7complex12__ModuleInfoZ@Base 6
+ _D4core4stdc8inttypes12__ModuleInfoZ@Base 6
+ _D4core4stdc8inttypes9imaxdiv_t6__initZ@Base 6
+ _D4core4sync5mutex12__ModuleInfoZ@Base 6
+ _D4core4sync5mutex5Mutex10handleAddrMFZPS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy11__xopEqualsFKxS4core4sync5mutex5Mutex12MonitorProxyKxS4core4sync5mutex5Mutex12MonitorProxyZb@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy6__initZ@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy9__xtoHashFNbNeKxS4core4sync5mutex5Mutex12MonitorProxyZk@Base 6
+ _D4core4sync5mutex5Mutex12lock_nothrowMFNbNiNeZv@Base 6
+ _D4core4sync5mutex5Mutex14unlock_nothrowMFNbNiNeZv@Base 6
+ _D4core4sync5mutex5Mutex4lockMFNeZv@Base 6
+ _D4core4sync5mutex5Mutex6__ctorMFNbNeC6ObjectZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync5mutex5Mutex6__ctorMFNbNeZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync5mutex5Mutex6__dtorMFZv@Base 6
+ _D4core4sync5mutex5Mutex6__initZ@Base 6
+ _D4core4sync5mutex5Mutex6__vtblZ@Base 6
+ _D4core4sync5mutex5Mutex6unlockMFNeZv@Base 6
+ _D4core4sync5mutex5Mutex7__ClassZ@Base 6
+ _D4core4sync5mutex5Mutex7tryLockMFZb@Base 6
+ _D4core4sync6config12__ModuleInfoZ@Base 6
+ _D4core4sync6config7mktspecFNbKS4core3sys5posix6signal8timespecS4core4time8DurationZv@Base 6
+ _D4core4sync6config7mktspecFNbKS4core3sys5posix6signal8timespecZv@Base 6
+ _D4core4sync6config7mvtspecFNbKS4core3sys5posix6signal8timespecS4core4time8DurationZv@Base 6
+ _D4core4sync7barrier12__ModuleInfoZ@Base 6
+ _D4core4sync7barrier7Barrier4waitMFZv@Base 6
+ _D4core4sync7barrier7Barrier6__ctorMFkZC4core4sync7barrier7Barrier@Base 6
+ _D4core4sync7barrier7Barrier6__initZ@Base 6
+ _D4core4sync7barrier7Barrier6__vtblZ@Base 6
+ _D4core4sync7barrier7Barrier7__ClassZ@Base 6
+ _D4core4sync7rwmutex12__ModuleInfoZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy11__xopEqualsFKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy9__xtoHashFNbNeKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyZk@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader17shouldQueueReaderMFNdZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader4lockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__ctorMFZC4core4sync7rwmutex14ReadWriteMutex6Reader@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6unlockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader7__ClassZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader7tryLockMFZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy11__xopEqualsFKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy9__xtoHashFNbNeKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyZk@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer17shouldQueueWriterMFNdZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer4lockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__ctorMFZC4core4sync7rwmutex14ReadWriteMutex6Writer@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6unlockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer7__ClassZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer7tryLockMFZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__ctorMFE4core4sync7rwmutex14ReadWriteMutex6PolicyZC4core4sync7rwmutex14ReadWriteMutex@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6policyMFNdZE4core4sync7rwmutex14ReadWriteMutex6Policy@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6readerMFNdZC4core4sync7rwmutex14ReadWriteMutex6Reader@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6writerMFNdZC4core4sync7rwmutex14ReadWriteMutex6Writer@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex7__ClassZ@Base 6
+ _D4core4sync9condition12__ModuleInfoZ@Base 6
+ _D4core4sync9condition9Condition13mutex_nothrowMFNaNbNdNiNfZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync9condition9Condition4waitMFS4core4time8DurationZb@Base 6
+ _D4core4sync9condition9Condition4waitMFZv@Base 6
+ _D4core4sync9condition9Condition5mutexMFNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync9condition9Condition6__ctorMFNbNfC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D4core4sync9condition9Condition6__dtorMFZv@Base 6
+ _D4core4sync9condition9Condition6__initZ@Base 6
+ _D4core4sync9condition9Condition6__vtblZ@Base 6
+ _D4core4sync9condition9Condition6notifyMFZv@Base 6
+ _D4core4sync9condition9Condition7__ClassZ@Base 6
+ _D4core4sync9condition9Condition9notifyAllMFZv@Base 6
+ _D4core4sync9exception12__ModuleInfoZ@Base 6
+ _D4core4sync9exception9SyncError6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core4sync9exception9SyncError@Base 6
+ _D4core4sync9exception9SyncError6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core4sync9exception9SyncError@Base 6
+ _D4core4sync9exception9SyncError6__initZ@Base 6
+ _D4core4sync9exception9SyncError6__vtblZ@Base 6
+ _D4core4sync9exception9SyncError7__ClassZ@Base 6
+ _D4core4sync9semaphore12__ModuleInfoZ@Base 6
+ _D4core4sync9semaphore9Semaphore4waitMFS4core4time8DurationZb@Base 6
+ _D4core4sync9semaphore9Semaphore4waitMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore6__ctorMFkZC4core4sync9semaphore9Semaphore@Base 6
+ _D4core4sync9semaphore9Semaphore6__dtorMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore6__initZ@Base 6
+ _D4core4sync9semaphore9Semaphore6__vtblZ@Base 6
+ _D4core4sync9semaphore9Semaphore6notifyMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore7__ClassZ@Base 6
+ _D4core4sync9semaphore9Semaphore7tryWaitMFZb@Base 6
+ _D4core4time11_posixClockFNaNbNiNfE4core4time9ClockTypeZi@Base 6
+ _D4core4time11numToStringFNaNbNflZAya@Base 6
+ _D4core4time12TickDuration11ticksPerSecyl@Base 6
+ _D4core4time12TickDuration14currSystemTickFNbNdNiNeZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration19_sharedStaticCtor55FNeZv@Base 6
+ _D4core4time12TickDuration3maxFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration3minFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration4zeroFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration5msecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration5nsecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration5opCmpMxFNaNbNiNfS4core4time12TickDurationZi@Base 6
+ _D4core4time12TickDuration5usecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration6__ctorMFNaNbNcNiNflZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration6__initZ@Base 6
+ _D4core4time12TickDuration6hnsecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration7secondsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration8__xopCmpFKxS4core4time12TickDurationKxS4core4time12TickDurationZi@Base 6
+ _D4core4time12TickDuration9appOriginyS4core4time12TickDuration@Base 6
+ _D4core4time12__ModuleInfoZ@Base 6
+ _D4core4time12nsecsToTicksFNaNbNiNflZl@Base 6
+ _D4core4time12ticksToNSecsFNaNbNiNflZl@Base 6
+ _D4core4time13TimeException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core4time13TimeException@Base 6
+ _D4core4time13TimeException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core4time13TimeException@Base 6
+ _D4core4time13TimeException6__initZ@Base 6
+ _D4core4time13TimeException6__vtblZ@Base 6
+ _D4core4time13TimeException7__ClassZ@Base 6
+ _D4core4time13_clockTypeIdxFE4core4time9ClockTypeZk@Base 6
+ _D4core4time13convClockFreqFNaNbNiNflllZl@Base 6
+ _D4core4time14_clockTypeNameFE4core4time9ClockTypeZAya@Base 6
+ _D4core4time15_ticksPerSecondyG8l@Base 6
+ _D4core4time23__T3durVAyaa4_64617973Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_686f757273Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_6d73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_6e73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_7573656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_7765656b73Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25unitsAreInDescendingOrderFAAyaXb@Base 6
+ _D4core4time27__T3durVAyaa6_686e73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time29__T3durVAyaa7_6d696e75746573Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time29__T3durVAyaa7_7365636f6e6473Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time39__T18getUnitsFromHNSecsVAyaa4_64617973Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time3absFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time3absFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_686f757273Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_6d73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_7573656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_7765656b73Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T20splitUnitsFromHNSecsVAyaa4_64617973Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl14ticksPerSecondFNaNbNdNiNfZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZS4core4time8Duration@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl3maxFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl3minFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl4zeroFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl5opCmpMxFNaNbNiNfS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZi@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl5ticksMxFNaNbNdNiNfZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl6__initZ@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8__xopCmpFKxS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplKxS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZi@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8currTimeFNbNdNiNeZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8toStringMxFNaNbNfZAya@Base 6
+ _D4core4time42__T21removeUnitsFromHNSecsVAyaa4_64617973Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_6d73656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7573656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7765656b73Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time44__T21removeUnitsFromHNSecsVAyaa5_686f757273Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time44__T21removeUnitsFromHNSecsVAyaa5_7765656b73Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_6d696e75746573Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa4_64617973VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa6_686e73656373VAyaa4_64617973Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time48__T21removeUnitsFromHNSecsVAyaa7_6d696e75746573Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time48__T21removeUnitsFromHNSecsVAyaa7_7365636f6e6473Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_686f757273VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_6d73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_6e73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7573656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7765656b73VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_686f757273Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7765656b73Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time4_absFNaNbNiNfdZd@Base 6
+ _D4core4time4_absFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa6_686e73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_6e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_6d696e75746573Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa7_6d696e75746573VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa7_7365636f6e6473VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time53__T2toVAyaa5_6d73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time53__T2toVAyaa5_6e73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time53__T2toVAyaa5_7573656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time54__T7convertVAyaa7_7365636f6e6473VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time55__T2toVAyaa6_686e73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time57__T2toVAyaa7_7365636f6e6473TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time7FracSec11__invariantMxFNaNfZv@Base 6
+ _D4core4time7FracSec13__invariant85MxFNaNfZv@Base 6
+ _D4core4time7FracSec13_enforceValidFNaNfiZv@Base 6
+ _D4core4time7FracSec13_toStringImplMxFNaNbNfZAya@Base 6
+ _D4core4time7FracSec28__T4fromVAyaa6_686e73656373Z4fromFNaNflZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec4zeroFNaNbNdNiNfZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec5msecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec5msecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec5nsecsMFNaNdNflZv@Base 6
+ _D4core4time7FracSec5nsecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec5usecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec5usecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec6__ctorMFNaNbNcNiNfiZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec6__initZ@Base 6
+ _D4core4time7FracSec6_validFNaNbNiNfiZb@Base 6
+ _D4core4time7FracSec6hnsecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec6hnsecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec8toStringMFNaNfZAya@Base 6
+ _D4core4time7FracSec8toStringMxFNaNbNfZAya@Base 6
+ _D4core4time8Duration10isNegativeMxFNaNbNdNiNfZb@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ10appListSepFNbNfKAyakbZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ31__T10appUnitValVAyaa4_64617973Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_686f757273Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_6d73656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_7573656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_7765656b73Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ35__T10appUnitValVAyaa6_686e73656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ37__T10appUnitValVAyaa7_6d696e75746573Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ37__T10appUnitValVAyaa7_7365636f6e6473Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZAya@Base 6
+ _D4core4time8Duration23__T3getVAyaa4_64617973Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration25__T10opOpAssignVAyaa1_2aZ10opOpAssignMFNaNbNcNiNflZS4core4time8Duration@Base 6
+ _D4core4time8Duration25__T3getVAyaa5_686f757273Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration25__T3getVAyaa5_7765656b73Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration27__T5totalVAyaa5_6d73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration29__T3getVAyaa7_6d696e75746573Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration29__T3getVAyaa7_7365636f6e6473Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration31__T5totalVAyaa7_7365636f6e6473Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration3maxFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration3minFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration43__T8opBinaryVAyaa1_2bTS4core4time8DurationZ8opBinaryMxFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration46__T10opOpAssignVAyaa1_2bTS4core4time8DurationZ10opOpAssignMFNaNbNcNiNfxS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z14__T5splitTiTiZ5splitMxFNaNbNiNfJiJiZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration4daysMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration4zeroFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration5hoursMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration5opCmpMxFNaNbNiNfS4core4time8DurationZi@Base 6
+ _D4core4time8Duration5weeksMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration6__ctorMFNaNbNcNiNflZS4core4time8Duration@Base 6
+ _D4core4time8Duration6__initZ@Base 6
+ _D4core4time8Duration7fracSecMxFNaNbNdNfZS4core4time7FracSec@Base 6
+ _D4core4time8Duration7minutesMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration7secondsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration8__xopCmpFKxS4core4time8DurationKxS4core4time8DurationZi@Base 6
+ _D4core4time8Duration8toStringMFNaNfZAya@Base 6
+ _D4core4time8Duration8toStringMxFNaNbNfZAya@Base 6
+ _D4core5bitop12__ModuleInfoZ@Base 6
+ _D4core5bitop2btFNaNbNixPkkZi@Base 6
+ _D4core5bitop6popcntFNaNbNiNfkZi@Base 6
+ _D4core5bitop7bitswapFNaNbNiNekZk@Base 6
+ _D4core5cpuid10dataCachesFNbNdNiNeZxG5S4core5cpuid9CacheInfo@Base 6
+ _D4core5cpuid10maxThreadsk@Base 6
+ _D4core5cpuid11amd3dnowExtFNbNdNiNeZb@Base 6
+ _D4core5cpuid11amdfeaturesk@Base 6
+ _D4core5cpuid11cacheLevelsFNbNdNiNeZk@Base 6
+ _D4core5cpuid11coresPerCPUFNbNdNiNeZk@Base 6
+ _D4core5cpuid11extfeaturesk@Base 6
+ _D4core5cpuid11hasLahfSahfFNbNdNiNeZb@Base 6
+ _D4core5cpuid11probablyAMDb@Base 6
+ _D4core5cpuid12__ModuleInfoZ@Base 6
+ _D4core5cpuid12getCpuInfo0BFNbNiNeZv@Base 6
+ _D4core5cpuid12hasCmpxchg8bFNbNdNiNeZb@Base 6
+ _D4core5cpuid12hasPclmulqdqFNbNdNiNeZb@Base 6
+ _D4core5cpuid12miscfeaturesk@Base 6
+ _D4core5cpuid12preferAthlonFNbNdNiNeZb@Base 6
+ _D4core5cpuid13hasCmpxchg16bFNbNdNiNeZb@Base 6
+ _D4core5cpuid13hasVpclmulqdqFNbNdNiNeZb@Base 6
+ _D4core5cpuid13probablyIntelb@Base 6
+ _D4core5cpuid13processorNameAya@Base 6
+ _D4core5cpuid13threadsPerCPUFNbNdNiNeZk@Base 6
+ _D4core5cpuid14hyperThreadingFNbNdNiNeZb@Base 6
+ _D4core5cpuid14numCacheLevelsk@Base 6
+ _D4core5cpuid14preferPentium1FNbNdNiNeZb@Base 6
+ _D4core5cpuid14preferPentium4FNbNdNiNeZb@Base 6
+ _D4core5cpuid15amdmiscfeaturesk@Base 6
+ _D4core5cpuid15getAMDcacheinfoFNbNiNeZ8assocmapyAh@Base 6
+ _D4core5cpuid15getAMDcacheinfoFNbNiNeZv@Base 6
+ _D4core5cpuid16has3dnowPrefetchFNbNdNiNeZb@Base 6
+ _D4core5cpuid17hyperThreadingBitFNbNdNiNeZb@Base 6
+ _D4core5cpuid18_sharedStaticCtor1FNbNiNeZv@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZ14decipherCpuid2MFNbNihZ3idsyG63h@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZ14decipherCpuid2MFNbNihZ4waysyG63h@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZ14decipherCpuid2MFNbNihZ5sizesyG63k@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZv@Base 6
+ _D4core5cpuid18getcacheinfoCPUID4FNbNiNeZv@Base 6
+ _D4core5cpuid18hasSysEnterSysExitFNbNdNiNeZb@Base 6
+ _D4core5cpuid18max_extended_cpuidk@Base 6
+ _D4core5cpuid19processorNameBufferG48a@Base 6
+ _D4core5cpuid3aesFNbNdNiNeZb@Base 6
+ _D4core5cpuid3avxFNbNdNiNeZb@Base 6
+ _D4core5cpuid3fmaFNbNdNiNeZb@Base 6
+ _D4core5cpuid3hleFNbNdNiNeZb@Base 6
+ _D4core5cpuid3mmxFNbNdNiNeZb@Base 6
+ _D4core5cpuid3rtmFNbNdNiNeZb@Base 6
+ _D4core5cpuid3sseFNbNdNiNeZb@Base 6
+ _D4core5cpuid4avx2FNbNdNiNeZb@Base 6
+ _D4core5cpuid4sse2FNbNdNiNeZb@Base 6
+ _D4core5cpuid4sse3FNbNdNiNeZb@Base 6
+ _D4core5cpuid4vaesFNbNdNiNeZb@Base 6
+ _D4core5cpuid5fp16cFNbNdNiNeZb@Base 6
+ _D4core5cpuid5modelk@Base 6
+ _D4core5cpuid5sse41FNbNdNiNeZb@Base 6
+ _D4core5cpuid5sse42FNbNdNiNeZb@Base 6
+ _D4core5cpuid5sse4aFNbNdNiNeZb@Base 6
+ _D4core5cpuid5ssse3FNbNdNiNeZb@Base 6
+ _D4core5cpuid6amdMmxFNbNdNiNeZb@Base 6
+ _D4core5cpuid6familyk@Base 6
+ _D4core5cpuid6hasShaFNbNdNiNeZb@Base 6
+ _D4core5cpuid6vendorFNbNdNiNeZAya@Base 6
+ _D4core5cpuid7hasCmovFNbNdNiNeZb@Base 6
+ _D4core5cpuid7hasFxsrFNbNdNiNeZb@Base 6
+ _D4core5cpuid8amd3dnowFNbNdNiNeZb@Base 6
+ _D4core5cpuid8cpuidX86FNbNiNeZv@Base 6
+ _D4core5cpuid8featuresk@Base 6
+ _D4core5cpuid8hasCPUIDFNbNiNeZb@Base 6
+ _D4core5cpuid8hasLzcntFNbNdNiNeZb@Base 6
+ _D4core5cpuid8hasRdtscFNbNdNiNeZb@Base 6
+ _D4core5cpuid8isX86_64FNbNdNiNeZb@Base 6
+ _D4core5cpuid8maxCoresk@Base 6
+ _D4core5cpuid8steppingk@Base 6
+ _D4core5cpuid8vendorIDG12a@Base 6
+ _D4core5cpuid9CacheInfo6__initZ@Base 6
+ _D4core5cpuid9datacacheG5S4core5cpuid9CacheInfo@Base 6
+ _D4core5cpuid9hasPopcntFNbNdNiNeZb@Base 6
+ _D4core5cpuid9hasRdrandFNbNdNiNeZb@Base 6
+ _D4core5cpuid9hasRdseedFNbNdNiNeZb@Base 6
+ _D4core5cpuid9isItaniumFNbNdNiNeZb@Base 6
+ _D4core5cpuid9max_cpuidk@Base 6
+ _D4core5cpuid9processorFNbNdNiNeZAya@Base 6
+ _D4core5cpuid9x87onChipFNbNdNiNeZb@Base 6
+ _D4core5cpuid9xfeaturesm@Base 6
+ _D4core6atomic11atomicFenceFNbNiZv@Base 6
+ _D4core6atomic120__T11atomicStoreVE4core6atomic11MemoryOrderi3TPOS2rt9critical_18D_CRITICAL_SECTIONTPOS2rt9critical_18D_CRITICAL_SECTIONZ11atomicStoreFNaNbNiKOPS2rt9critical_18D_CRITICAL_SECTIONPOS2rt9critical_18D_CRITICAL_SECTIONZv@Base 6
+ _D4core6atomic12__ModuleInfoZ@Base 6
+ _D4core6atomic14__T3casThThThZ3casFNaNbNiPOhxhxhZb@Base 6
+ _D4core6atomic14__T3casTkTkTkZ3casFNaNbNiPOkxkxkZb@Base 6
+ _D4core6atomic14__T3casTtTtTtZ3casFNaNbNiPOtxtxtZb@Base 6
+ _D4core6atomic20__T7casImplThTxhTxhZ7casImplFNaNbNiPOhxhxhZb@Base 6
+ _D4core6atomic20__T7casImplTkTxkTxkZ7casImplFNaNbNiPOkxkxkZb@Base 6
+ _D4core6atomic20__T7casImplTtTxtTxtZ7casImplFNaNbNiPOtxtxtZb@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2b3dTkTiZ8atomicOpFNaNbNiKOkiZk@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2b3dTkTkZ8atomicOpFNaNbNiKOkkZk@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2d3dTkTiZ8atomicOpFNaNbNiKOkiZk@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2d3dTkTkZ8atomicOpFNaNbNiKOkkZk@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi0TkZ10atomicLoadFNaNbNiKOxkZk@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5TbZ10atomicLoadFNaNbNiKOxbZb@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi0TbTbZ11atomicStoreFNaNbNiKObbZv@Base 6
+ _D4core6atomic69__T10atomicLoadVE4core6atomic11MemoryOrderi2TPOS2rt8monitor_7MonitorZ10atomicLoadFNaNbNiKOxPS2rt8monitor_7MonitorZPOS2rt8monitor_7Monitor@Base 6
+ _D4core6atomic82__T10atomicLoadVE4core6atomic11MemoryOrderi0TPOS2rt9critical_18D_CRITICAL_SECTIONZ10atomicLoadFNaNbNiKOxPS2rt9critical_18D_CRITICAL_SECTIONZPOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D4core6atomic82__T10atomicLoadVE4core6atomic11MemoryOrderi2TPOS2rt9critical_18D_CRITICAL_SECTIONZ10atomicLoadFNaNbNiKOxPS2rt9critical_18D_CRITICAL_SECTIONZPOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D4core6atomic94__T11atomicStoreVE4core6atomic11MemoryOrderi3TPOS2rt8monitor_7MonitorTPOS2rt8monitor_7MonitorZ11atomicStoreFNaNbNiKOPS2rt8monitor_7MonitorPOS2rt8monitor_7MonitorZv@Base 6
+ _D4core6memory12__ModuleInfoZ@Base 6
+ _D4core6memory2GC10removeRootFNbxPvZv@Base 6
+ _D4core6memory2GC11removeRangeFNbNixPvZv@Base 6
+ _D4core6memory2GC13runFinalizersFxAvZv@Base 6
+ _D4core6memory2GC4freeFNaNbPvZv@Base 6
+ _D4core6memory2GC5queryFNaNbPvZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC5queryFNbxPvZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC6__initZ@Base 6
+ _D4core6memory2GC6addrOfFNaNbPvZPv@Base 6
+ _D4core6memory2GC6addrOfFNbPNgvZPNgv@Base 6
+ _D4core6memory2GC6callocFNaNbkkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC6enableFNbZv@Base 6
+ _D4core6memory2GC6extendFNaNbPvkkxC8TypeInfoZk@Base 6
+ _D4core6memory2GC6mallocFNaNbkkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC6qallocFNaNbkkxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC6sizeOfFNaNbPvZk@Base 6
+ _D4core6memory2GC6sizeOfFNbxPvZk@Base 6
+ _D4core6memory2GC7addRootFNbxPvZv@Base 6
+ _D4core6memory2GC7clrAttrFNaNbPvkZk@Base 6
+ _D4core6memory2GC7clrAttrFNbxPvkZk@Base 6
+ _D4core6memory2GC7collectFNbZv@Base 6
+ _D4core6memory2GC7disableFNbZv@Base 6
+ _D4core6memory2GC7getAttrFNaNbPvZk@Base 6
+ _D4core6memory2GC7getAttrFNbxPvZk@Base 6
+ _D4core6memory2GC7reallocFNaNbPvkkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC7reserveFNbkZk@Base 6
+ _D4core6memory2GC7setAttrFNaNbPvkZk@Base 6
+ _D4core6memory2GC7setAttrFNbxPvkZk@Base 6
+ _D4core6memory2GC8addRangeFNbNixPvkxC8TypeInfoZv@Base 6
+ _D4core6memory2GC8minimizeFNbZv@Base 6
+ _D4core6memory8BlkInfo_6__initZ@Base 6
+ _D4core6thread11ThreadError6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core6thread11ThreadError@Base 6
+ _D4core6thread11ThreadError6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core6thread11ThreadError@Base 6
+ _D4core6thread11ThreadError6__initZ@Base 6
+ _D4core6thread11ThreadError6__vtblZ@Base 6
+ _D4core6thread11ThreadError7__ClassZ@Base 6
+ _D4core6thread11ThreadGroup3addMFC4core6thread6ThreadZv@Base 6
+ _D4core6thread11ThreadGroup6__initZ@Base 6
+ _D4core6thread11ThreadGroup6__vtblZ@Base 6
+ _D4core6thread11ThreadGroup6createMFDFZvZC4core6thread6Thread@Base 6
+ _D4core6thread11ThreadGroup6createMFPFZvZC4core6thread6Thread@Base 6
+ _D4core6thread11ThreadGroup6removeMFC4core6thread6ThreadZv@Base 6
+ _D4core6thread11ThreadGroup7__ClassZ@Base 6
+ _D4core6thread11ThreadGroup7joinAllMFbZv@Base 6
+ _D4core6thread11ThreadGroup7opApplyMFMDFKC4core6thread6ThreadZiZi@Base 6
+ _D4core6thread11getStackTopFNbZPv@Base 6
+ _D4core6thread12__ModuleInfoZ@Base 6
+ _D4core6thread12suspendCountS4core3sys5posix9semaphore5sem_t@Base 6
+ _D4core6thread12suspendDepthk@Base 6
+ _D4core6thread13onThreadErrorFNbAyaC6object9ThrowableZ5errorC4core6thread11ThreadError@Base 6
+ _D4core6thread13onThreadErrorFNbAyaC6object9ThrowableZv@Base 6
+ _D4core6thread14getStackBottomFNbZPv@Base 6
+ _D4core6thread15ThreadException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core6thread15ThreadException@Base 6
+ _D4core6thread15ThreadException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core6thread15ThreadException@Base 6
+ _D4core6thread15ThreadException6__initZ@Base 6
+ _D4core6thread15ThreadException6__vtblZ@Base 6
+ _D4core6thread15ThreadException7__ClassZ@Base 6
+ _D4core6thread15scanAllTypeImplFNbMDFNbE4core6thread8ScanTypePvPvZvPvZv@Base 6
+ _D4core6thread17PTHREAD_STACK_MINyk@Base 6
+ _D4core6thread17multiThreadedFlagb@Base 6
+ _D4core6thread17thread_entryPointUPvZ21thread_cleanupHandlerUNbPvZv@Base 6
+ _D4core6thread17thread_findByAddrFkZC4core6thread6Thread@Base 6
+ _D4core6thread18_sharedStaticDtor8FZv@Base 6
+ _D4core6thread18callWithStackShellFNbMDFNbPvZvZv@Base 6
+ _D4core6thread18resumeSignalNumberi@Base 6
+ _D4core6thread19_sharedStaticCtor18FZv@Base 6
+ _D4core6thread19suspendSignalNumberi@Base 6
+ _D4core6thread5Fiber10allocStackMFNbkZv@Base 6
+ _D4core6thread5Fiber13_staticCtor19FZv@Base 6
+ _D4core6thread5Fiber13yieldAndThrowFNbC6object9ThrowableZv@Base 6
+ _D4core6thread5Fiber39__T4callVE4core6thread5Fiber7Rethrowi0Z4callMFNbZC6object9Throwable@Base 6
+ _D4core6thread5Fiber39__T4callVE4core6thread5Fiber7Rethrowi1Z4callMFZC6object9Throwable@Base 6
+ _D4core6thread5Fiber3runMFZv@Base 6
+ _D4core6thread5Fiber4callMFE4core6thread5Fiber7RethrowZC6object9Throwable@Base 6
+ _D4core6thread5Fiber4callMFbZC6object9Throwable@Base 6
+ _D4core6thread5Fiber5resetMFNbDFZvZv@Base 6
+ _D4core6thread5Fiber5resetMFNbPFZvZv@Base 6
+ _D4core6thread5Fiber5resetMFNbZv@Base 6
+ _D4core6thread5Fiber5stateMxFNbNdZE4core6thread5Fiber5State@Base 6
+ _D4core6thread5Fiber5yieldFNbZv@Base 6
+ _D4core6thread5Fiber6__ctorMFNbDFZvkZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__ctorMFNbPFZvkZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__ctorMFNbZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__dtorMFNbZv@Base 6
+ _D4core6thread5Fiber6__initZ@Base 6
+ _D4core6thread5Fiber6__vtblZ@Base 6
+ _D4core6thread5Fiber7__ClassZ@Base 6
+ _D4core6thread5Fiber7getThisFNbZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber7setThisFNbC4core6thread5FiberZv@Base 6
+ _D4core6thread5Fiber7sm_thisC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber8callImplMFNbZv@Base 6
+ _D4core6thread5Fiber8switchInMFNbZv@Base 6
+ _D4core6thread5Fiber9freeStackMFNbZv@Base 6
+ _D4core6thread5Fiber9initStackMFNbZv@Base 6
+ _D4core6thread5Fiber9switchOutMFNbZv@Base 6
+ _D4core6thread6Thread10popContextMFNbZv@Base 6
+ _D4core6thread6Thread10topContextMFNbZPS4core6thread6Thread7Context@Base 6
+ _D4core6thread6Thread11pushContextMFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread12PRIORITY_MAXxi@Base 6
+ _D4core6thread6Thread12PRIORITY_MINxi@Base 6
+ _D4core6thread6Thread16PRIORITY_DEFAULTxi@Base 6
+ _D4core6thread6Thread18_sharedStaticCtor3FZv@Base 6
+ _D4core6thread6Thread18criticalRegionLockFNbNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core6thread6Thread3addFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread3addFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread3runMFZv@Base 6
+ _D4core6thread6Thread4joinMFbZC6object9Throwable@Base 6
+ _D4core6thread6Thread4nameMFNdAyaZv@Base 6
+ _D4core6thread6Thread4nameMFNdZAya@Base 6
+ _D4core6thread6Thread5sleepFNbS4core4time8DurationZv@Base 6
+ _D4core6thread6Thread5slockFNbNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core6thread6Thread5startMFNbZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread5yieldFNbZv@Base 6
+ _D4core6thread6Thread6__ctorMFDFZvkZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__ctorMFPFZvkZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__ctorMFkZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__dtorMFZv@Base 6
+ _D4core6thread6Thread6__initZ@Base 6
+ _D4core6thread6Thread6__vtblZ@Base 6
+ _D4core6thread6Thread6_locksG2G40v@Base 6
+ _D4core6thread6Thread6getAllFZAC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6removeFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread6removeFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread7Context6__initZ@Base 6
+ _D4core6thread6Thread7__ClassZ@Base 6
+ _D4core6thread6Thread7getThisFNbZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7opApplyFMDFKC4core6thread6ThreadZiZi@Base 6
+ _D4core6thread6Thread7setThisFC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread7sm_cbegPS4core6thread6Thread7Context@Base 6
+ _D4core6thread6Thread7sm_mainC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7sm_tbegC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7sm_thisk@Base 6
+ _D4core6thread6Thread7sm_tlenk@Base 6
+ _D4core6thread6Thread8isDaemonMFNdZb@Base 6
+ _D4core6thread6Thread8isDaemonMFNdbZv@Base 6
+ _D4core6thread6Thread8priorityMFNdZi@Base 6
+ _D4core6thread6Thread8priorityMFNdiZv@Base 6
+ _D4core6thread6Thread9initLocksFZv@Base 6
+ _D4core6thread6Thread9isRunningMFNbNdZb@Base 6
+ _D4core6thread6Thread9termLocksFZv@Base 6
+ _D4core6thread6resumeFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread7suspendFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread8PAGESIZEyk@Base 6
+ _D4core6vararg12__ModuleInfoZ@Base 6
+ _D4core7runtime12__ModuleInfoZ@Base 6
+ _D4core7runtime12_staticCtor1FZv@Base 6
+ _D4core7runtime18runModuleUnitTestsUZ19unittestSegvHandlerUiPS4core3sys5posix6signal9siginfo_tPvZv@Base 6
+ _D4core7runtime19defaultTraceHandlerFPvZC6object9Throwable9TraceInfo@Base 6
+ _D4core7runtime5CArgs6__initZ@Base 6
+ _D4core7runtime7Runtime10initializeFDFC6object9ThrowableZvZb@Base 6
+ _D4core7runtime7Runtime10initializeFZb@Base 6
+ _D4core7runtime7Runtime12traceHandlerFNdPFPvZC6object9Throwable9TraceInfoZv@Base 6
+ _D4core7runtime7Runtime12traceHandlerFNdZPFPvZC6object9Throwable9TraceInfo@Base 6
+ _D4core7runtime7Runtime14collectHandlerFNdPFC6ObjectZbZv@Base 6
+ _D4core7runtime7Runtime14collectHandlerFNdZPFC6ObjectZb@Base 6
+ _D4core7runtime7Runtime16moduleUnitTesterFNdPFZbZv@Base 6
+ _D4core7runtime7Runtime16moduleUnitTesterFNdZPFZb@Base 6
+ _D4core7runtime7Runtime19sm_moduleUnitTesterPFZb@Base 6
+ _D4core7runtime7Runtime4argsFNdZAAya@Base 6
+ _D4core7runtime7Runtime5cArgsFNdZS4core7runtime5CArgs@Base 6
+ _D4core7runtime7Runtime6__initZ@Base 6
+ _D4core7runtime7Runtime9terminateFDFC6object9ThrowableZvZb@Base 6
+ _D4core7runtime7Runtime9terminateFZb@Base 6
+ _D4core8demangle12__ModuleInfoZ@Base 6
+ _D4core8demangle12demangleTypeFAxaAaZAa@Base 6
+ _D4core8demangle15decodeDmdStringFAxaKkZAya@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle28__T10mangleFuncHTPFZPvTFZPvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle30__T10mangleFuncHTPFPvZvTFPvZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle48__T10mangleFuncHTPFNaNbNePxvkkZkTFNaNbNePxvkkZkZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle48__T10mangleFuncHTPFNaNbNexkAaZAaTFNaNbNexkAaZAaZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle50__T10mangleFuncHTPFNaNbNexAaxAaZiTFNaNbNexAaxAaZiZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle52__T10mangleFuncHTPFNbPvMDFNbPvZiZvTFNbPvMDFNbPvZiZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle56__T10mangleFuncHTPFNbPvMDFNbPvPvZvZvTFNbPvMDFNbPvPvZvZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle74__T10mangleFuncHTPFNbNiAyaMDFNbNiAyaZAyabZAyaTFNbNiAyaMDFNbNiAyaZAyabZAyaZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle7mangleCFAxaAaZAa@Base 6
+ _D4core8demangle8Demangle10isHexDigitFaZb@Base 6
+ _D4core8demangle8Demangle10parseLNameMFZv@Base 6
+ _D4core8demangle8Demangle10parseValueMFAaaZv@Base 6
+ _D4core8demangle8Demangle11__xopEqualsFKxS4core8demangle8DemangleKxS4core8demangle8DemangleZb@Base 6
+ _D4core8demangle8Demangle11sliceNumberMFZAxa@Base 6
+ _D4core8demangle8Demangle12decodeNumberMFAxaZk@Base 6
+ _D4core8demangle8Demangle12decodeNumberMFZk@Base 6
+ _D4core8demangle8Demangle12demangleNameMFZAa@Base 6
+ _D4core8demangle8Demangle12demangleTypeMFZAa@Base 6
+ _D4core8demangle8Demangle12val2HexDigitFhZa@Base 6
+ _D4core8demangle8Demangle13parseFuncAttrMFZv@Base 6
+ _D4core8demangle8Demangle14ParseException6__ctorMFNaNbNfAyaZC4core8demangle8Demangle14ParseException@Base 6
+ _D4core8demangle8Demangle14ParseException6__initZ@Base 6
+ _D4core8demangle8Demangle14ParseException6__vtblZ@Base 6
+ _D4core8demangle8Demangle14ParseException7__ClassZ@Base 6
+ _D4core8demangle8Demangle15parseSymbolNameMFZv@Base 6
+ _D4core8demangle8Demangle16isCallConventionFaZb@Base 6
+ _D4core8demangle8Demangle16parseMangledNameMFkZv@Base 6
+ _D4core8demangle8Demangle17OverflowException6__ctorMFNaNbNfAyaZC4core8demangle8Demangle17OverflowException@Base 6
+ _D4core8demangle8Demangle17OverflowException6__initZ@Base 6
+ _D4core8demangle8Demangle17OverflowException6__vtblZ@Base 6
+ _D4core8demangle8Demangle17OverflowException7__ClassZ@Base 6
+ _D4core8demangle8Demangle17parseIntegerValueMFAaaZv@Base 6
+ _D4core8demangle8Demangle17parseTemplateArgsMFZv@Base 6
+ _D4core8demangle8Demangle17parseTypeFunctionMFAaE4core8demangle8Demangle10IsDelegateZAa@Base 6
+ _D4core8demangle8Demangle18parseFuncArgumentsMFZv@Base 6
+ _D4core8demangle8Demangle18parseQualifiedNameMFZAa@Base 6
+ _D4core8demangle8Demangle19mayBeMangledNameArgMFZb@Base 6
+ _D4core8demangle8Demangle19parseCallConventionMFZv@Base 6
+ _D4core8demangle8Demangle19parseMangledNameArgMFZv@Base 6
+ _D4core8demangle8Demangle25mayBeTemplateInstanceNameMFZb@Base 6
+ _D4core8demangle8Demangle25parseTemplateInstanceNameMFZv@Base 6
+ _D4core8demangle8Demangle3eatMFaZv@Base 6
+ _D4core8demangle8Demangle3padMFAxaZv@Base 6
+ _D4core8demangle8Demangle3putMFAxaZAa@Base 6
+ _D4core8demangle8Demangle3tokMFZa@Base 6
+ _D4core8demangle8Demangle4nextMFZv@Base 6
+ _D4core8demangle8Demangle4testMFaZv@Base 6
+ _D4core8demangle8Demangle5errorFAyaZv@Base 6
+ _D4core8demangle8Demangle5matchMFAxaZv@Base 6
+ _D4core8demangle8Demangle5matchMFaZv@Base 6
+ _D4core8demangle8Demangle5shiftMFAxaZAa@Base 6
+ _D4core8demangle8Demangle61__T10doDemangleS42_D4core8demangle8Demangle9parseTypeMFAaZAaZ10doDemangleMFZAa@Base 6
+ _D4core8demangle8Demangle67__T10doDemangleS48_D4core8demangle8Demangle16parseMangledNameMFkZvZ10doDemangleMFZAa@Base 6
+ _D4core8demangle8Demangle6__ctorMFNcAxaAaZS4core8demangle8Demangle@Base 6
+ _D4core8demangle8Demangle6__ctorMFNcAxaE4core8demangle8Demangle7AddTypeAaZS4core8demangle8Demangle@Base 6
+ _D4core8demangle8Demangle6__initZ@Base 6
+ _D4core8demangle8Demangle6appendMFAxaZAa@Base 6
+ _D4core8demangle8Demangle6silentMFLvZv@Base 6
+ _D4core8demangle8Demangle7isAlphaFaZb@Base 6
+ _D4core8demangle8Demangle7isDigitFaZb@Base 6
+ _D4core8demangle8Demangle8containsFAxaAxaZb@Base 6
+ _D4core8demangle8Demangle8overflowFAyaZv@Base 6
+ _D4core8demangle8Demangle8putAsHexMFkiZAa@Base 6
+ _D4core8demangle8Demangle9__xtoHashFNbNeKxS4core8demangle8DemangleZk@Base 6
+ _D4core8demangle8Demangle9ascii2hexFaZh@Base 6
+ _D4core8demangle8Demangle9parseRealMFZv@Base 6
+ _D4core8demangle8Demangle9parseTypeMFAaZ10primitivesyG23Aa@Base 6
+ _D4core8demangle8Demangle9parseTypeMFAaZAa@Base 6
+ _D4core8demangle8demangleFAxaAaZAa@Base 6
+ _D4core8internal4hash12__ModuleInfoZ@Base 6
+ _D4core8internal4hash13__T6hashOfTkZ6hashOfFNaNbNekkZk@Base 6
+ _D4core8internal4hash14__T6hashOfTPkZ6hashOfFNaNbNeKPkkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ16__T6rotl32Vki13Z6rotl32FNaNbNiNfxkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ16__T6rotl32Vki15Z6rotl32FNaNbNiNfxkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ6fmix32FNaNbNfkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ9get32bitsFNaNbPxhZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZk@Base 6
+ _D4core8internal6traits12__ModuleInfoZ@Base 6
+ _D4core8internal7convert11shiftrRoundFNaNbNfmZm@Base 6
+ _D4core8internal7convert12__ModuleInfoZ@Base 6
+ _D4core8internal7convert14__T7toUbyteTkZ7toUbyteFNaNbNeKkZAxh@Base 6
+ _D4core8internal7convert5Float6__initZ@Base 6
+ _D4core8internal7convert7binPow2FNaNbNfiZ10binPosPow2FNaNbNfiZe@Base 6
+ _D4core8internal7convert7binPow2FNaNbNfiZe@Base 6
+ _D4core9exception10RangeError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception10RangeError@Base 6
+ _D4core9exception10RangeError6__initZ@Base 6
+ _D4core9exception10RangeError6__vtblZ@Base 6
+ _D4core9exception10RangeError7__ClassZ@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfAyakZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfC6object9ThrowableAyakZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__initZ@Base 6
+ _D4core9exception11AssertError6__vtblZ@Base 6
+ _D4core9exception11AssertError7__ClassZ@Base 6
+ _D4core9exception11SwitchError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception11SwitchError@Base 6
+ _D4core9exception11SwitchError6__initZ@Base 6
+ _D4core9exception11SwitchError6__vtblZ@Base 6
+ _D4core9exception11SwitchError7__ClassZ@Base 6
+ _D4core9exception12__ModuleInfoZ@Base 6
+ _D4core9exception13FinalizeError6__ctorMFNaNbNfC8TypeInfoAyakC6object9ThrowableZC4core9exception13FinalizeError@Base 6
+ _D4core9exception13FinalizeError6__ctorMFNaNbNfC8TypeInfoC6object9ThrowableAyakZC4core9exception13FinalizeError@Base 6
+ _D4core9exception13FinalizeError6__initZ@Base 6
+ _D4core9exception13FinalizeError6__vtblZ@Base 6
+ _D4core9exception13FinalizeError7__ClassZ@Base 6
+ _D4core9exception13FinalizeError8toStringMxFNfZAya@Base 6
+ _D4core9exception13assertHandlerFNbNdNiNePFNbAyakAyaZvZv@Base 6
+ _D4core9exception13assertHandlerFNbNdNiNeZPFNbAyakAyaZv@Base 6
+ _D4core9exception14_assertHandlerPFNbAyakAyaZv@Base 6
+ _D4core9exception15HiddenFuncError6__ctorMFNaNbNfC14TypeInfo_ClassZC4core9exception15HiddenFuncError@Base 6
+ _D4core9exception15HiddenFuncError6__initZ@Base 6
+ _D4core9exception15HiddenFuncError6__vtblZ@Base 6
+ _D4core9exception15HiddenFuncError7__ClassZ@Base 6
+ _D4core9exception15onFinalizeErrorUNbNeC8TypeInfoC6object9ThrowableAyakZ3errC4core9exception13FinalizeError@Base 6
+ _D4core9exception16OutOfMemoryError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception16OutOfMemoryError@Base 6
+ _D4core9exception16OutOfMemoryError6__initZ@Base 6
+ _D4core9exception16OutOfMemoryError6__vtblZ@Base 6
+ _D4core9exception16OutOfMemoryError7__ClassZ@Base 6
+ _D4core9exception16OutOfMemoryError8toStringMxFNeZAya@Base 6
+ _D4core9exception16UnicodeException6__ctorMFNaNbNfAyakAyakC6object9ThrowableZC4core9exception16UnicodeException@Base 6
+ _D4core9exception16UnicodeException6__initZ@Base 6
+ _D4core9exception16UnicodeException6__vtblZ@Base 6
+ _D4core9exception16UnicodeException7__ClassZ@Base 6
+ _D4core9exception16setAssertHandlerFNbNiNePFNbAyakAyaZvZv@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception27InvalidMemoryOperationError@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__initZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__vtblZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError7__ClassZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError8toStringMxFNeZAya@Base 6
+ _D50TypeInfo_HC4core6thread6ThreadC4core6thread6Thread6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc4Addr6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5posix7netinet3in_11sockaddr_in6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5posix7pthread15pthread_cleanup6__initZ@Base 6
+ _D51TypeInfo_E4core4sync7rwmutex14ReadWriteMutex6Policy6__initZ@Base 6
+ _D51TypeInfo_S2rt19sections_elf_shared15CompilerDSOData6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix3sys5types14pthread_attr_t6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix3sys5types14pthread_cond_t6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix7netinet3in_12sockaddr_in66__initZ@Base 6
+ _D52TypeInfo_S4core3sys5linux3elf11Elf32_gptab9_gt_entry6__initZ@Base 6
+ _D52TypeInfo_S4core3sys5linux3sys7inotify13inotify_event6__initZ@Base 6
+ _D52TypeInfo_S4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D53TypeInfo_S4core3sys5posix3sys5types16pthread_rwlock_t6__initZ@Base 6
+ _D53TypeInfo_xS4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D54TypeInfo_S2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5linux3elf11Elf32_gptab10_gt_header6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5linux5stdio21cookie_io_functions_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys5types17_pthread_fastlock6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys5types17pthread_barrier_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys6socket16sockaddr_storage6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix6signal8sigevent11_sigev_un_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix9semaphore17_pthread_fastlock6__initZ@Base 6
+ _D55TypeInfo_S2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc4Addr4Name6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5posix3sys5types18pthread_condattr_t6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t6__initZ@Base 6
+ _D56TypeInfo_S4core3sys5linux3sys8signalfd16signalfd_siginfo6__initZ@Base 6
+ _D56TypeInfo_S4core3sys5posix3sys5types19pthread_mutexattr_t6__initZ@Base 6
+ _D56TypeInfo_xS2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D57TypeInfo_S4core3sys5posix3sys5types20pthread_rwlockattr_t6__initZ@Base 6
+ _D58TypeInfo_S4core3sys5posix3sys5types21pthread_barrierattr_t6__initZ@Base 6
+ _D58TypeInfo_S4core3sys5posix7pthread23_pthread_cleanup_buffer6__initZ@Base 6
+ _D61TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t5_rt_t6__initZ@Base 6
+ _D62TypeInfo_S2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D63TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t7_kill_t6__initZ@Base 6
+ _D63TypeInfo_xS2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D64TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t8_timer_t6__initZ@Base 6
+ _D65TypeInfo_S2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D65TypeInfo_S4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy6__initZ@Base 6
+ _D65TypeInfo_S4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy6__initZ@Base 6
+ _D66TypeInfo_S2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D66TypeInfo_xS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D67TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t10_sigpoll_t6__initZ@Base 6
+ _D67TypeInfo_xS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D68TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t11_sigchild_t6__initZ@Base 6
+ _D68TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t11_sigfault_t6__initZ@Base 6
+ _D6Object6__initZ@Base 6
+ _D6Object6__vtblZ@Base 6
+ _D6Object7__ClassZ@Base 6
+ _D6object101__T7destroyTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D6object10ModuleInfo11xgetMembersMxFNaNbNdZPv@Base 6
+ _D6object10ModuleInfo12localClassesMxFNaNbNdZAC14TypeInfo_Class@Base 6
+ _D6object10ModuleInfo15importedModulesMxFNaNbNdZAyPS6object10ModuleInfo@Base 6
+ _D6object10ModuleInfo4ctorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo4dtorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo4nameMxFNaNbNdZAya@Base 6
+ _D6object10ModuleInfo5flagsMxFNaNbNdZk@Base 6
+ _D6object10ModuleInfo5ictorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo5indexMxFNaNbNdZk@Base 6
+ _D6object10ModuleInfo6__initZ@Base 6
+ _D6object10ModuleInfo6addrOfMxFNaNbiZPv@Base 6
+ _D6object10ModuleInfo7opApplyFMDFPS6object10ModuleInfoZiZi@Base 6
+ _D6object10ModuleInfo7tlsctorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo7tlsdtorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo8opAssignMFxS6object10ModuleInfoZv@Base 6
+ _D6object10ModuleInfo8unitTestMxFNaNbNdZPFZv@Base 6
+ _D6object10__T3dupThZ3dupFNaNbNdNfAxhZAh@Base 6
+ _D6object10_xopEqualsFxPvxPvZb@Base 6
+ _D6object10getElementFNaNbNeNgC8TypeInfoZNgC8TypeInfo@Base 6
+ _D6object111__T16_destructRecurseTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ16_destructRecurseFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D6object11__T4idupTaZ4idupFNaNbNdNfAaZAya@Base 6
+ _D6object12__ModuleInfoZ@Base 6
+ _D6object12getArrayHashFNbNexC8TypeInfoxPvxkZ15hasCustomToHashFNaNbNexC8TypeInfoZb@Base 6
+ _D6object12getArrayHashFNbNexC8TypeInfoxPvxkZk@Base 6
+ _D6object12setSameMutexFOC6ObjectOC6ObjectZv@Base 6
+ _D6object14OffsetTypeInfo11__xopEqualsFKxS6object14OffsetTypeInfoKxS6object14OffsetTypeInfoZb@Base 6
+ _D6object14OffsetTypeInfo6__initZ@Base 6
+ _D6object14OffsetTypeInfo9__xtoHashFNbNeKxS6object14OffsetTypeInfoZk@Base 6
+ _D6object14TypeInfo_Array4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object14TypeInfo_Array4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Array5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Array5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Array6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Array6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Array7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Array7getHashMxFNbNexPvZk@Base 6
+ _D6object14TypeInfo_Array8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Array8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Class10ClassFlags6__initZ@Base 6
+ _D6object14TypeInfo_Class4findFxAaZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Class4infoMxFNaNbNdNiNfZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Class4initMxFNaNbNiNfZAxv@Base 6
+ _D6object14TypeInfo_Class5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Class5offTiMxFNaNbNdZAxS6object14OffsetTypeInfo@Base 6
+ _D6object14TypeInfo_Class5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Class6createMxFZC6Object@Base 6
+ _D6object14TypeInfo_Class6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Class6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object14TypeInfo_Class7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Class7getHashMxFNbNexPvZk@Base 6
+ _D6object14TypeInfo_Class8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Class8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Class8typeinfoMxFNaNbNdNiNfZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Const4initMxFNaNbNiNfZAxv@Base 6
+ _D6object14TypeInfo_Const4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object14TypeInfo_Const4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Const5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Const5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Const6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Const6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Const7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Const7getHashMxFNbNfxPvZk@Base 6
+ _D6object14TypeInfo_Const8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Const8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Inout8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Tuple4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Tuple5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Tuple6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Tuple6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Tuple7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Tuple7destroyMxFPvZv@Base 6
+ _D6object14TypeInfo_Tuple7getHashMxFNbNfxPvZk@Base 6
+ _D6object14TypeInfo_Tuple8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Tuple8postblitMxFPvZv@Base 6
+ _D6object14TypeInfo_Tuple8toStringMxFNaNbNfZAya@Base 6
+ _D6object14__T4_dupTaTyaZ4_dupFNaNbAaZAya@Base 6
+ _D6object14__T4_dupTxhThZ4_dupFNaNbAxhZAh@Base 6
+ _D6object14__T6hashOfTPkZ6hashOfFNaNbNfPkkZk@Base 6
+ _D6object14__T7_rawDupTaZ7_rawDupFNaNbANgaZANga@Base 6
+ _D6object14__T7_rawDupThZ7_rawDupFNaNbANghZANgh@Base 6
+ _D6object15TypeInfo_Shared8toStringMxFNaNbNfZAya@Base 6
+ _D6object15TypeInfo_Struct11StructFlags6__initZ@Base 6
+ _D6object15TypeInfo_Struct4initMxFNaNbNiNfZAxv@Base 6
+ _D6object15TypeInfo_Struct5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Struct5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Struct6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D6object15TypeInfo_Struct6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object15TypeInfo_Struct6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Struct7compareMxFNaNbNexPvxPvZi@Base 6
+ _D6object15TypeInfo_Struct7destroyMxFPvZv@Base 6
+ _D6object15TypeInfo_Struct7getHashMxFNaNbNfxPvZk@Base 6
+ _D6object15TypeInfo_Struct8opEqualsMFC6ObjectZb@Base 6
+ _D6object15TypeInfo_Struct8postblitMxFPvZv@Base 6
+ _D6object15TypeInfo_Struct8toStringMxFNaNbNfZAya@Base 6
+ _D6object15TypeInfo_Vector4initMxFNaNbNiNfZAxv@Base 6
+ _D6object15TypeInfo_Vector4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object15TypeInfo_Vector4swapMxFPvPvZv@Base 6
+ _D6object15TypeInfo_Vector5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Vector5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Vector6equalsMxFxPvxPvZb@Base 6
+ _D6object15TypeInfo_Vector6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Vector7compareMxFxPvxPvZi@Base 6
+ _D6object15TypeInfo_Vector7getHashMxFNbNfxPvZk@Base 6
+ _D6object15TypeInfo_Vector8opEqualsMFC6ObjectZb@Base 6
+ _D6object15TypeInfo_Vector8toStringMxFNaNbNfZAya@Base 6
+ _D6object16TypeInfo_Pointer4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object16TypeInfo_Pointer4swapMxFPvPvZv@Base 6
+ _D6object16TypeInfo_Pointer5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Pointer5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Pointer6equalsMxFxPvxPvZb@Base 6
+ _D6object16TypeInfo_Pointer7compareMxFxPvxPvZi@Base 6
+ _D6object16TypeInfo_Pointer7getHashMxFNbNexPvZk@Base 6
+ _D6object16TypeInfo_Pointer8opEqualsMFC6ObjectZb@Base 6
+ _D6object16TypeInfo_Pointer8toStringMxFNaNbNfZAya@Base 6
+ _D6object16TypeInfo_Typedef4initMxFNaNbNiNfZAxv@Base 6
+ _D6object16TypeInfo_Typedef4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object16TypeInfo_Typedef4swapMxFPvPvZv@Base 6
+ _D6object16TypeInfo_Typedef5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Typedef5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Typedef6equalsMxFxPvxPvZb@Base 6
+ _D6object16TypeInfo_Typedef6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object16TypeInfo_Typedef6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Typedef7compareMxFxPvxPvZi@Base 6
+ _D6object16TypeInfo_Typedef7getHashMxFNbNfxPvZk@Base 6
+ _D6object16TypeInfo_Typedef8opEqualsMFC6ObjectZb@Base 6
+ _D6object16TypeInfo_Typedef8toStringMxFNaNbNfZAya@Base 6
+ _D6object17TypeInfo_Delegate5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Delegate5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Delegate6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Delegate8opEqualsMFC6ObjectZb@Base 6
+ _D6object17TypeInfo_Delegate8toStringMxFNaNbNfZAya@Base 6
+ _D6object17TypeInfo_Function5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Function8opEqualsMFC6ObjectZb@Base 6
+ _D6object17TypeInfo_Function8toStringMxFNaNbNfZAya@Base 6
+ _D6object18TypeInfo_Interface5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object18TypeInfo_Interface5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object18TypeInfo_Interface6equalsMxFxPvxPvZb@Base 6
+ _D6object18TypeInfo_Interface7compareMxFxPvxPvZi@Base 6
+ _D6object18TypeInfo_Interface7getHashMxFNbNexPvZk@Base 6
+ _D6object18TypeInfo_Interface8opEqualsMFC6ObjectZb@Base 6
+ _D6object18TypeInfo_Interface8toStringMxFNaNbNfZAya@Base 6
+ _D6object18TypeInfo_Invariant8toStringMxFNaNbNfZAya@Base 6
+ _D6object19__T11_doPostblitThZ11_doPostblitFNaNbNiNfAhZv@Base 6
+ _D6object20TypeInfo_StaticArray4initMxFNaNbNiNfZAxv@Base 6
+ _D6object20TypeInfo_StaticArray4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object20TypeInfo_StaticArray4swapMxFPvPvZv@Base 6
+ _D6object20TypeInfo_StaticArray5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object20TypeInfo_StaticArray5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object20TypeInfo_StaticArray6equalsMxFxPvxPvZb@Base 6
+ _D6object20TypeInfo_StaticArray6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object20TypeInfo_StaticArray7compareMxFxPvxPvZi@Base 6
+ _D6object20TypeInfo_StaticArray7destroyMxFPvZv@Base 6
+ _D6object20TypeInfo_StaticArray7getHashMxFNbNexPvZk@Base 6
+ _D6object20TypeInfo_StaticArray8opEqualsMFC6ObjectZb@Base 6
+ _D6object20TypeInfo_StaticArray8postblitMxFPvZv@Base 6
+ _D6object20TypeInfo_StaticArray8toStringMxFNaNbNfZAya@Base 6
+ _D6object20__T11_doPostblitTyaZ11_doPostblitFNaNbNiNfAyaZv@Base 6
+ _D6object20__T12_getPostblitThZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKhZv@Base 6
+ _D6object21__T12_getPostblitTyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyaZv@Base 6
+ _D6object22__T11_trustedDupTaTyaZ11_trustedDupFNaNbNeAaZAya@Base 6
+ _D6object22__T11_trustedDupTxhThZ11_trustedDupFNaNbNeAxhZAh@Base 6
+ _D6object25TypeInfo_AssociativeArray4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object25TypeInfo_AssociativeArray5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object25TypeInfo_AssociativeArray5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object25TypeInfo_AssociativeArray6equalsMxFNexPvxPvZb@Base 6
+ _D6object25TypeInfo_AssociativeArray6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object25TypeInfo_AssociativeArray7getHashMxFNbNexPvZk@Base 6
+ _D6object25TypeInfo_AssociativeArray8opEqualsMFC6ObjectZb@Base 6
+ _D6object25TypeInfo_AssociativeArray8toStringMxFNaNbNfZAya@Base 6
+ _D6object38__T11_doPostblitTC4core6thread6ThreadZ11_doPostblitFNaNbNiNfAC4core6thread6ThreadZv@Base 6
+ _D6object39__T12_getPostblitTC4core6thread6ThreadZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKC4core6thread6ThreadZv@Base 6
+ _D6object43__T7destroyTPS3gcc3deh18d_exception_headerZ7destroyFNaNbNiNfKPS3gcc3deh18d_exception_headerZv@Base 6
+ _D6object48__T7destroyTS2rt19sections_elf_shared9ThreadDSOZ7destroyFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D6object58__T16_destructRecurseTS2rt19sections_elf_shared9ThreadDSOZ16_destructRecurseFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D6object5Error6__ctorMFNaNbNiNfAyaAyakC6object9ThrowableZC6object5Error@Base 6
+ _D6object5Error6__ctorMFNaNbNiNfAyaC6object9ThrowableZC6object5Error@Base 6
+ _D6object5Error6__initZ@Base 6
+ _D6object5Error6__vtblZ@Base 6
+ _D6object5Error7__ClassZ@Base 6
+ _D6object6Object5opCmpMFC6ObjectZi@Base 6
+ _D6object6Object6toHashMFNbNeZk@Base 6
+ _D6object6Object7Monitor11__InterfaceZ@Base 6
+ _D6object6Object7factoryFAyaZC6Object@Base 6
+ _D6object6Object8opEqualsMFC6ObjectZb@Base 6
+ _D6object6Object8toStringMFZAya@Base 6
+ _D6object7AARange6__initZ@Base 6
+ _D6object7_xopCmpFxPvxPvZb@Base 6
+ _D6object8TypeInfo4initMxFNaNbNiNfZAxv@Base 6
+ _D6object8TypeInfo4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object8TypeInfo4swapMxFPvPvZv@Base 6
+ _D6object8TypeInfo5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object8TypeInfo5offTiMxFZAxS6object14OffsetTypeInfo@Base 6
+ _D6object8TypeInfo5opCmpMFC6ObjectZi@Base 6
+ _D6object8TypeInfo5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object8TypeInfo6equalsMxFxPvxPvZb@Base 6
+ _D6object8TypeInfo6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object8TypeInfo6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object8TypeInfo6toHashMxFNbNeZk@Base 6
+ _D6object8TypeInfo7compareMxFxPvxPvZi@Base 6
+ _D6object8TypeInfo7destroyMxFPvZv@Base 6
+ _D6object8TypeInfo7getHashMxFNbNexPvZk@Base 6
+ _D6object8TypeInfo8opEqualsMFC6ObjectZb@Base 6
+ _D6object8TypeInfo8postblitMxFPvZv@Base 6
+ _D6object8TypeInfo8toStringMxFNaNbNfZAya@Base 6
+ _D6object8opEqualsFC6ObjectC6ObjectZb@Base 6
+ _D6object8opEqualsFxC6ObjectxC6ObjectZb@Base 6
+ _D6object94__T4keysHTHC4core6thread6ThreadC4core6thread6ThreadTC4core6thread6ThreadTC4core6thread6ThreadZ4keysFNaNbNdHC4core6thread6ThreadC4core6thread6ThreadZAC4core6thread6Thread@Base 6
+ _D6object9Exception6__ctorMFNaNbNiNfAyaAyakC6object9ThrowableZC9Exception@Base 6
+ _D6object9Exception6__ctorMFNaNbNiNfAyaC6object9ThrowableAyakZC9Exception@Base 6
+ _D6object9Interface11__xopEqualsFKxS6object9InterfaceKxS6object9InterfaceZb@Base 6
+ _D6object9Interface6__initZ@Base 6
+ _D6object9Interface9__xtoHashFNbNeKxS6object9InterfaceZk@Base 6
+ _D6object9Throwable6__ctorMFNaNbNiNfAyaAyakC6object9ThrowableZC6object9Throwable@Base 6
+ _D6object9Throwable6__ctorMFNaNbNiNfAyaC6object9ThrowableZC6object9Throwable@Base 6
+ _D6object9Throwable6__initZ@Base 6
+ _D6object9Throwable6__vtblZ@Base 6
+ _D6object9Throwable7__ClassZ@Base 6
+ _D6object9Throwable8toStringMFZAya@Base 6
+ _D6object9Throwable8toStringMxFMDFxAaZvZv@Base 6
+ _D6object9Throwable9TraceInfo11__InterfaceZ@Base 6
+ _D70TypeInfo_S2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D71TypeInfo_S2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D71TypeInfo_S4core3sys5posix6signal8sigevent11_sigev_un_t15_sigev_thread_t6__initZ@Base 6
+ _D71TypeInfo_xS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_PxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_S3gcc6unwind2pe28read_encoded_value_with_baseFhkPhPkZ9unaligned6__initZ@Base 6
+ _D72TypeInfo_xPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_xS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D73TypeInfo_PxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D73TypeInfo_xPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D75TypeInfo_S4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D76TypeInfo_S4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D78TypeInfo_S4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl6__initZ@Base 6
+ _D83TypeInfo_S2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D84TypeInfo_xS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D85TypeInfo_S4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D85TypeInfo_S4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D86TypeInfo_S4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D87TypeInfo_S4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D88TypeInfo_S2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__initZ@Base 6
+ _D89TypeInfo_S4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D8TypeInfo6__initZ@Base 6
+ _D8TypeInfo6__vtblZ@Base 6
+ _D8TypeInfo7__ClassZ@Base 6
+ _D92TypeInfo_S2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__initZ@Base 6
+ _D97TypeInfo_S2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node6__initZ@Base 6
+ _D98TypeInfo_S4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D9Exception6__initZ@Base 6
+ _D9Exception6__vtblZ@Base 6
+ _D9Exception7__ClassZ@Base 6
+ _D9invariant12__ModuleInfoZ@Base 6
+ _D9invariant12_d_invariantFC6ObjectZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Reader4lockMFNeZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Reader6unlockMFNeZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Writer4lockMFNeZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Writer6unlockMFNeZv@Base 6
+ _DT36_D2gc2gc7GCMutex4lockMFNbNiNeZv@Base 6
+ _DT36_D2gc2gc7GCMutex6unlockMFNbNiNeZv@Base 6
+ _DT36_D4core4sync5mutex5Mutex4lockMFNeZv@Base 6
+ _DT36_D4core4sync5mutex5Mutex6unlockMFNeZv@Base 6
+ _DT660_D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKkKxAaZiZi@Base 6
+ _DT660_D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKxAaZiZi@Base 6
+ _DT660_D3gcc9backtrace12LibBacktrace8toStringMxFZAya@Base 6
+ __gdc_begin_catch@Base 6
+ __gdc_exception_cleanup@Base 6
+ __gdc_personality_v0@Base 6
+ __mod_ref__D2gc2gc12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc2os12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc4bits12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc5proxy12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc5stats12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc9pooltable12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt11arrayassign12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt12sections_osx12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt14sections_win3212__ModuleInfoZ@Base 6
+ __mod_ref__D2rt14sections_win6412__ModuleInfoZ@Base 6
+ __mod_ref__D2rt16sections_android12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt16sections_solaris12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt19sections_elf_shared12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3aaA12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3adi12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3deh12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3obj12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util3utf12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util4hash12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util5array12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util6random12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util6string12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util8typeinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container5array12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container5treap12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container6common12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container7hashtab12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5cast_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5minfo12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5qsort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5tlsgc12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6aApply12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6config12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6dmain212__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6memory12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt7aApplyR12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt7switch_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8arraycat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8lifetime12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8monitor_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8sections12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_Acfloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_Adouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_cdouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_idouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo11ti_Acdouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo11ti_delegate12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo4ti_C12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo5ti_AC12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo5ti_Ag12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo6ti_int12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo6ti_ptr12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_Aint12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_byte12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_cent12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_char12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_long12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_real12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_uint12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_void12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_Along12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_Areal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_creal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_dchar12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_float12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ireal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_short12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ubyte12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ucent12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ulong12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_wchar12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Acreal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Afloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Ashort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_cfloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_double12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_ifloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_ushort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt9arraycast12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt9critical_12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc5linux11memoryerror12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc12libbacktrace12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc3deh12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind2pe12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind3arm12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind7generic12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc7atomics12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc8builtins12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc9attribute12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc9backtrace12__ModuleInfoZ@Base 6
+ __mod_ref__D4core10checkedint12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3elf12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys4mman12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys5xattr12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys7inotify12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys7sysinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys8signalfd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4link12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4tipc12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5dlfcn12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5epoll12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5errno12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux8execinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3grp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3net3if_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3pwd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys2un12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3ipc12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3msg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3shm12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3uio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4mman12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4stat12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4wait12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys5ioctl12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys5types12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys6select12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys7statvfs12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys7utsname12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys8resource12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4arpa4inet12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4poll12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5dlfcn12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5fcntl12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5netdb12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5sched12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5utime12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6dirent12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6setjmp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6signal12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6syslog12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6unistd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7netinet3in_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7netinet3tcp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7pthread12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix8inttypes12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix8ucontext12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix9semaphore12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4math12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4simd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4fenv12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4math12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5ctype12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5errno12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6float_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6limits12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6locale12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6signal12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdarg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stddef12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdint12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6string12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6tgmath12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6wchar_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6wctype12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc7complex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc8inttypes12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync5mutex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync7barrier12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync7rwmutex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9condition12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9semaphore12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core5bitop12__ModuleInfoZ@Base 6
+ __mod_ref__D4core5cpuid12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6atomic12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6memory12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6thread12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6vararg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core7runtime12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8demangle12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal4hash12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal6traits12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal7convert12__ModuleInfoZ@Base 6
+ __mod_ref__D4core9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D6object12__ModuleInfoZ@Base 6
+ __mod_ref__D9invariant12__ModuleInfoZ@Base 6
+ _aApplyRcd1@Base 6
+ _aApplyRcd2@Base 6
+ _aApplyRcw1@Base 6
+ _aApplyRcw2@Base 6
+ _aApplyRdc1@Base 6
+ _aApplyRdc2@Base 6
+ _aApplyRdw1@Base 6
+ _aApplyRdw2@Base 6
+ _aApplyRwc1@Base 6
+ _aApplyRwc2@Base 6
+ _aApplyRwd1@Base 6
+ _aApplyRwd2@Base 6
+ _aApplycd1@Base 6
+ _aApplycd2@Base 6
+ _aApplycw1@Base 6
+ _aApplycw2@Base 6
+ _aApplydc1@Base 6
+ _aApplydc2@Base 6
+ _aApplydw1@Base 6
+ _aApplydw2@Base 6
+ _aApplywc1@Base 6
+ _aApplywc2@Base 6
+ _aApplywd1@Base 6
+ _aApplywd2@Base 6
+ _aaApply2@Base 6
+ _aaApply@Base 6
+ _aaDelX@Base 6
+ _aaEqual@Base 6
+ _aaGetHash@Base 6
+ _aaGetRvalueX@Base 6
+ _aaGetY@Base 6
+ _aaInX@Base 6
+ _aaKeys@Base 6
+ _aaLen@Base 6
+ _aaRange@Base 6
+ _aaRangeEmpty@Base 6
+ _aaRangeFrontKey@Base 6
+ _aaRangeFrontValue@Base 6
+ _aaRangePopFront@Base 6
+ _aaRehash@Base 6
+ _aaValues@Base 6
+ _aaVersion@Base 6
+ _adCmp2@Base 6
+ _adCmp@Base 6
+ _adCmpChar@Base 6
+ _adEq2@Base 6
+ _adEq@Base 6
+ _adReverse@Base 6
+ _adReverseChar@Base 6
+ _adReverseWchar@Base 6
+ _adSort@Base 6
+ _adSortChar@Base 6
+ _adSortWchar@Base 6
+ _d_allocmemory@Base 6
+ _d_array_bounds@Base 6
+ _d_arrayappendT@Base 6
+ _d_arrayappendcTX@Base 6
+ _d_arrayappendcd@Base 6
+ _d_arrayappendwd@Base 6
+ _d_arrayassign@Base 6
+ _d_arrayassign_l@Base 6
+ _d_arrayassign_r@Base 6
+ _d_arraybounds@Base 6
+ _d_arraycast@Base 6
+ _d_arraycatT@Base 6
+ _d_arraycatnTX@Base 6
+ _d_arraycopy@Base 6
+ _d_arrayctor@Base 6
+ _d_arrayliteralTX@Base 6
+ _d_arraysetassign@Base 6
+ _d_arraysetcapacity@Base 6
+ _d_arraysetctor@Base 6
+ _d_arraysetlengthT@Base 6
+ _d_arraysetlengthiT@Base 6
+ _d_arrayshrinkfit@Base 6
+ _d_assert@Base 6
+ _d_assert_msg@Base 6
+ _d_assertm@Base 6
+ _d_assocarrayliteralTX@Base 6
+ _d_callfinalizer@Base 6
+ _d_callinterfacefinalizer@Base 6
+ _d_createTrace@Base 6
+ _d_critical_init@Base 6
+ _d_critical_term@Base 6
+ _d_criticalenter@Base 6
+ _d_criticalexit@Base 6
+ _d_delarray@Base 6
+ _d_delarray_t@Base 6
+ _d_delclass@Base 6
+ _d_delinterface@Base 6
+ _d_delmemory@Base 6
+ _d_delstruct@Base 6
+ _d_dso_registry@Base 6
+ _d_dynamic_cast@Base 6
+ _d_initMonoTime@Base 6
+ _d_interface_cast@Base 6
+ _d_interface_vtbl@Base 6
+ _d_isbaseof2@Base 6
+ _d_isbaseof@Base 6
+ _d_main_args@Base 6
+ _d_monitor_staticctor@Base 6
+ _d_monitor_staticdtor@Base 6
+ _d_monitordelete@Base 6
+ _d_monitorenter@Base 6
+ _d_monitorexit@Base 6
+ _d_newarrayT@Base 6
+ _d_newarrayU@Base 6
+ _d_newarrayiT@Base 6
+ _d_newarraymTX@Base 6
+ _d_newarraymiTX@Base 6
+ _d_newclass@Base 6
+ _d_newitemT@Base 6
+ _d_newitemU@Base 6
+ _d_newitemiT@Base 6
+ _d_obj_cmp@Base 6
+ _d_obj_eq@Base 6
+ _d_print_throwable@Base 6
+ _d_run_main@Base 6
+ _d_setSameMutex@Base 6
+ _d_switch_dstring@Base 6
+ _d_switch_error@Base 6
+ _d_switch_errorm@Base 6
+ _d_switch_string@Base 6
+ _d_switch_ustring@Base 6
+ _d_throw@Base 6
+ _d_toObject@Base 6
+ _d_traceContext@Base 6
+ _d_unittest@Base 6
+ _d_unittest_msg@Base 6
+ _d_unittestm@Base 6
+ backtrace_alloc@Base 6
+ backtrace_close@Base 6
+ backtrace_create_state@Base 6
+ backtrace_dwarf_add@Base 6
+ backtrace_free@Base 6
+ backtrace_full@Base 6
+ backtrace_get_view@Base 6
+ backtrace_initialize@Base 6
+ backtrace_open@Base 6
+ backtrace_pcinfo@Base 6
+ backtrace_print@Base 6
+ backtrace_qsort@Base 6
+ backtrace_release_view@Base 6
+ backtrace_simple@Base 6
+ backtrace_syminfo@Base 6
+ backtrace_vector_finish@Base 6
+ backtrace_vector_grow@Base 6
+ backtrace_vector_release@Base 6
+ fiber_entryPoint@Base 6
+ fiber_switchContext@Base 6
+ gc_addRange@Base 6
+ gc_addRoot@Base 6
+ gc_addrOf@Base 6
+ gc_calloc@Base 6
+ gc_clrAttr@Base 6
+ gc_clrProxy@Base 6
+ gc_collect@Base 6
+ gc_disable@Base 6
+ gc_enable@Base 6
+ gc_extend@Base 6
+ gc_free@Base 6
+ gc_getAttr@Base 6
+ gc_getProxy@Base 6
+ gc_init@Base 6
+ gc_malloc@Base 6
+ gc_minimize@Base 6
+ gc_qalloc@Base 6
+ gc_query@Base 6
+ gc_realloc@Base 6
+ gc_removeRange@Base 6
+ gc_removeRoot@Base 6
+ gc_reserve@Base 6
+ gc_runFinalizers@Base 6
+ gc_setAttr@Base 6
+ gc_setProxy@Base 6
+ gc_sizeOf@Base 6
+ gc_stats@Base 6
+ gc_term@Base 6
+ getErrno@Base 6
+ lifetime_init@Base 6
+ onAssertError@Base 6
+ onAssertErrorMsg@Base 6
+ onFinalizeError@Base 6
+ onHiddenFuncError@Base 6
+ onInvalidMemoryOperationError@Base 6
+ onOutOfMemoryError@Base 6
+ onRangeError@Base 6
+ onSwitchError@Base 6
+ onUnicodeError@Base 6
+ onUnittestErrorMsg@Base 6
+ pcinfoCallback@Base 6
+ pcinfoErrorCallback@Base 6
+ rt_args@Base 6
+ rt_attachDisposeEvent@Base 6
+ rt_cArgs@Base 6
+ rt_cmdline_enabled@Base 6
+ rt_detachDisposeEvent@Base 6
+ rt_envvars_enabled@Base 6
+ rt_finalize2@Base 6
+ rt_finalize@Base 6
+ rt_finalizeFromGC@Base 6
+ rt_getCollectHandler@Base 6
+ rt_getTraceHandler@Base 6
+ rt_hasFinalizerInSegment@Base 6
+ rt_init@Base 6
+ rt_loadLibrary@Base 6
+ rt_moduleCtor@Base 6
+ rt_moduleDtor@Base 6
+ rt_moduleTlsCtor@Base 6
+ rt_moduleTlsDtor@Base 6
+ rt_options@Base 6
+ rt_setCollectHandler@Base 6
+ rt_setTraceHandler@Base 6
+ rt_term@Base 6
+ rt_trapExceptions@Base 6
+ rt_unloadLibrary@Base 6
+ runModuleUnitTests@Base 6
+ setErrno@Base 6
+ simpleCallback@Base 6
+ simpleErrorCallback@Base 6
+ syminfoCallback2@Base 6
+ syminfoCallback@Base 6
+ thread_attachThis@Base 6
+ thread_detachByAddr@Base 6
+ thread_detachInstance@Base 6
+ thread_detachThis@Base 6
+ thread_enterCriticalRegion@Base 6
+ thread_entryPoint@Base 6
+ thread_exitCriticalRegion@Base 6
+ thread_inCriticalRegion@Base 6
+ thread_init@Base 6
+ thread_isMainThread@Base 6
+ thread_joinAll@Base 6
+ thread_processGCMarks@Base 6
+ thread_resumeAll@Base 6
+ thread_resumeHandler@Base 6
+ thread_scanAll@Base 6
+ thread_scanAllType@Base 6
+ thread_setGCSignals@Base 6
+ thread_setThis@Base 6
+ thread_stackBottom@Base 6
+ thread_stackTop@Base 6
+ thread_suspendAll@Base 6
+ thread_suspendHandler@Base 6
+ thread_term@Base 6
+ tipc_addr@Base 6
+ tipc_cluster@Base 6
+ tipc_node@Base 6
+ tipc_zone@Base 6
--- gcc-6-6.3.0.orig/debian/libgphobos.symbols.rt64
+++ gcc-6-6.3.0/debian/libgphobos.symbols.rt64
@@ -0,0 +1,3347 @@
+ LOG_MASK@Base 6
+ LOG_UPTO@Base 6
+ S_TYPEISMQ@Base 6
+ S_TYPEISSEM@Base 6
+ S_TYPEISSHM@Base 6
+ _D102TypeInfo_S2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ2DG6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D10TypeInfo_C6__initZ@Base 6
+ _D10TypeInfo_C6__vtblZ@Base 6
+ _D10TypeInfo_C7__ClassZ@Base 6
+ _D10TypeInfo_D6__initZ@Base 6
+ _D10TypeInfo_D6__vtblZ@Base 6
+ _D10TypeInfo_D7__ClassZ@Base 6
+ _D10TypeInfo_P6__initZ@Base 6
+ _D10TypeInfo_P6__vtblZ@Base 6
+ _D10TypeInfo_P7__ClassZ@Base 6
+ _D10TypeInfo_a6__initZ@Base 6
+ _D10TypeInfo_a6__vtblZ@Base 6
+ _D10TypeInfo_a7__ClassZ@Base 6
+ _D10TypeInfo_b6__initZ@Base 6
+ _D10TypeInfo_b6__vtblZ@Base 6
+ _D10TypeInfo_b7__ClassZ@Base 6
+ _D10TypeInfo_c6__initZ@Base 6
+ _D10TypeInfo_c6__vtblZ@Base 6
+ _D10TypeInfo_c7__ClassZ@Base 6
+ _D10TypeInfo_d6__initZ@Base 6
+ _D10TypeInfo_d6__vtblZ@Base 6
+ _D10TypeInfo_d7__ClassZ@Base 6
+ _D10TypeInfo_e6__initZ@Base 6
+ _D10TypeInfo_e6__vtblZ@Base 6
+ _D10TypeInfo_e7__ClassZ@Base 6
+ _D10TypeInfo_f6__initZ@Base 6
+ _D10TypeInfo_f6__vtblZ@Base 6
+ _D10TypeInfo_f7__ClassZ@Base 6
+ _D10TypeInfo_g6__initZ@Base 6
+ _D10TypeInfo_g6__vtblZ@Base 6
+ _D10TypeInfo_g7__ClassZ@Base 6
+ _D10TypeInfo_h6__initZ@Base 6
+ _D10TypeInfo_h6__vtblZ@Base 6
+ _D10TypeInfo_h7__ClassZ@Base 6
+ _D10TypeInfo_i6__initZ@Base 6
+ _D10TypeInfo_i6__vtblZ@Base 6
+ _D10TypeInfo_i7__ClassZ@Base 6
+ _D10TypeInfo_j6__initZ@Base 6
+ _D10TypeInfo_j6__vtblZ@Base 6
+ _D10TypeInfo_j7__ClassZ@Base 6
+ _D10TypeInfo_k6__initZ@Base 6
+ _D10TypeInfo_k6__vtblZ@Base 6
+ _D10TypeInfo_k7__ClassZ@Base 6
+ _D10TypeInfo_l6__initZ@Base 6
+ _D10TypeInfo_l6__vtblZ@Base 6
+ _D10TypeInfo_l7__ClassZ@Base 6
+ _D10TypeInfo_m6__initZ@Base 6
+ _D10TypeInfo_m6__vtblZ@Base 6
+ _D10TypeInfo_m7__ClassZ@Base 6
+ _D10TypeInfo_o6__initZ@Base 6
+ _D10TypeInfo_o6__vtblZ@Base 6
+ _D10TypeInfo_o7__ClassZ@Base 6
+ _D10TypeInfo_p6__initZ@Base 6
+ _D10TypeInfo_p6__vtblZ@Base 6
+ _D10TypeInfo_p7__ClassZ@Base 6
+ _D10TypeInfo_q6__initZ@Base 6
+ _D10TypeInfo_q6__vtblZ@Base 6
+ _D10TypeInfo_q7__ClassZ@Base 6
+ _D10TypeInfo_r6__initZ@Base 6
+ _D10TypeInfo_r6__vtblZ@Base 6
+ _D10TypeInfo_r7__ClassZ@Base 6
+ _D10TypeInfo_s6__initZ@Base 6
+ _D10TypeInfo_s6__vtblZ@Base 6
+ _D10TypeInfo_s7__ClassZ@Base 6
+ _D10TypeInfo_t6__initZ@Base 6
+ _D10TypeInfo_t6__vtblZ@Base 6
+ _D10TypeInfo_t7__ClassZ@Base 6
+ _D10TypeInfo_u6__initZ@Base 6
+ _D10TypeInfo_u6__vtblZ@Base 6
+ _D10TypeInfo_u7__ClassZ@Base 6
+ _D10TypeInfo_v6__initZ@Base 6
+ _D10TypeInfo_v6__vtblZ@Base 6
+ _D10TypeInfo_v7__ClassZ@Base 6
+ _D10TypeInfo_w6__initZ@Base 6
+ _D10TypeInfo_w6__vtblZ@Base 6
+ _D10TypeInfo_w7__ClassZ@Base 6
+ _D11TypeInfo_AC6__initZ@Base 6
+ _D11TypeInfo_AC6__vtblZ@Base 6
+ _D11TypeInfo_AC7__ClassZ@Base 6
+ _D11TypeInfo_Aa6__initZ@Base 6
+ _D11TypeInfo_Aa6__vtblZ@Base 6
+ _D11TypeInfo_Aa7__ClassZ@Base 6
+ _D11TypeInfo_Ab6__initZ@Base 6
+ _D11TypeInfo_Ab6__vtblZ@Base 6
+ _D11TypeInfo_Ab7__ClassZ@Base 6
+ _D11TypeInfo_Ac6__initZ@Base 6
+ _D11TypeInfo_Ac6__vtblZ@Base 6
+ _D11TypeInfo_Ac7__ClassZ@Base 6
+ _D11TypeInfo_Ad6__initZ@Base 6
+ _D11TypeInfo_Ad6__vtblZ@Base 6
+ _D11TypeInfo_Ad7__ClassZ@Base 6
+ _D11TypeInfo_Ae6__initZ@Base 6
+ _D11TypeInfo_Ae6__vtblZ@Base 6
+ _D11TypeInfo_Ae7__ClassZ@Base 6
+ _D11TypeInfo_Af6__initZ@Base 6
+ _D11TypeInfo_Af6__vtblZ@Base 6
+ _D11TypeInfo_Af7__ClassZ@Base 6
+ _D11TypeInfo_Ag6__initZ@Base 6
+ _D11TypeInfo_Ag6__vtblZ@Base 6
+ _D11TypeInfo_Ag7__ClassZ@Base 6
+ _D11TypeInfo_Ah6__initZ@Base 6
+ _D11TypeInfo_Ah6__vtblZ@Base 6
+ _D11TypeInfo_Ah7__ClassZ@Base 6
+ _D11TypeInfo_Ai6__initZ@Base 6
+ _D11TypeInfo_Ai6__vtblZ@Base 6
+ _D11TypeInfo_Ai7__ClassZ@Base 6
+ _D11TypeInfo_Aj6__initZ@Base 6
+ _D11TypeInfo_Aj6__vtblZ@Base 6
+ _D11TypeInfo_Aj7__ClassZ@Base 6
+ _D11TypeInfo_Ak6__initZ@Base 6
+ _D11TypeInfo_Ak6__vtblZ@Base 6
+ _D11TypeInfo_Ak7__ClassZ@Base 6
+ _D11TypeInfo_Al6__initZ@Base 6
+ _D11TypeInfo_Al6__vtblZ@Base 6
+ _D11TypeInfo_Al7__ClassZ@Base 6
+ _D11TypeInfo_Am6__initZ@Base 6
+ _D11TypeInfo_Am6__vtblZ@Base 6
+ _D11TypeInfo_Am7__ClassZ@Base 6
+ _D11TypeInfo_Ao6__initZ@Base 6
+ _D11TypeInfo_Ao6__vtblZ@Base 6
+ _D11TypeInfo_Ao7__ClassZ@Base 6
+ _D11TypeInfo_Ap6__initZ@Base 6
+ _D11TypeInfo_Ap6__vtblZ@Base 6
+ _D11TypeInfo_Ap7__ClassZ@Base 6
+ _D11TypeInfo_Aq6__initZ@Base 6
+ _D11TypeInfo_Aq6__vtblZ@Base 6
+ _D11TypeInfo_Aq7__ClassZ@Base 6
+ _D11TypeInfo_Ar6__initZ@Base 6
+ _D11TypeInfo_Ar6__vtblZ@Base 6
+ _D11TypeInfo_Ar7__ClassZ@Base 6
+ _D11TypeInfo_As6__initZ@Base 6
+ _D11TypeInfo_As6__vtblZ@Base 6
+ _D11TypeInfo_As7__ClassZ@Base 6
+ _D11TypeInfo_At6__initZ@Base 6
+ _D11TypeInfo_At6__vtblZ@Base 6
+ _D11TypeInfo_At7__ClassZ@Base 6
+ _D11TypeInfo_Au6__initZ@Base 6
+ _D11TypeInfo_Au6__vtblZ@Base 6
+ _D11TypeInfo_Au7__ClassZ@Base 6
+ _D11TypeInfo_Av6__initZ@Base 6
+ _D11TypeInfo_Av6__vtblZ@Base 6
+ _D11TypeInfo_Av7__ClassZ@Base 6
+ _D11TypeInfo_Aw6__initZ@Base 6
+ _D11TypeInfo_Aw6__vtblZ@Base 6
+ _D11TypeInfo_Aw7__ClassZ@Base 6
+ _D11TypeInfo_Oa6__initZ@Base 6
+ _D11TypeInfo_Ou6__initZ@Base 6
+ _D11TypeInfo_Pv6__initZ@Base 6
+ _D11TypeInfo_xa6__initZ@Base 6
+ _D11TypeInfo_xb6__initZ@Base 6
+ _D11TypeInfo_xf6__initZ@Base 6
+ _D11TypeInfo_xh6__initZ@Base 6
+ _D11TypeInfo_xi6__initZ@Base 6
+ _D11TypeInfo_xk6__initZ@Base 6
+ _D11TypeInfo_xm6__initZ@Base 6
+ _D11TypeInfo_xv6__initZ@Base 6
+ _D11TypeInfo_ya6__initZ@Base 6
+ _D11TypeInfo_yk6__initZ@Base 6
+ _D12TypeInfo_AOa6__initZ@Base 6
+ _D12TypeInfo_AOu6__initZ@Base 6
+ _D12TypeInfo_Axa6__initZ@Base 6
+ _D12TypeInfo_Axa6__vtblZ@Base 6
+ _D12TypeInfo_Axa7__ClassZ@Base 6
+ _D12TypeInfo_Axv6__initZ@Base 6
+ _D12TypeInfo_Aya6__initZ@Base 6
+ _D12TypeInfo_Aya6__vtblZ@Base 6
+ _D12TypeInfo_Aya7__ClassZ@Base 6
+ _D12TypeInfo_G0h6__initZ@Base 6
+ _D12TypeInfo_OAa6__initZ@Base 6
+ _D12TypeInfo_OAu6__initZ@Base 6
+ _D12TypeInfo_Pxh6__initZ@Base 6
+ _D12TypeInfo_Pxv6__initZ@Base 6
+ _D12TypeInfo_xAa6__initZ@Base 6
+ _D12TypeInfo_xAv6__initZ@Base 6
+ _D12TypeInfo_xPh6__initZ@Base 6
+ _D12TypeInfo_xPv6__initZ@Base 6
+ _D12TypeInfo_yAa6__initZ@Base 6
+ _D131TypeInfo_E3gcc3deh22__gdc_personality_implFiibPS3gcc6unwind7generic17_Unwind_ExceptionPS3gcc6unwind7generic15_Unwind_ContextZ5Found6__initZ@Base 6
+ _D13TypeInfo_AxPv6__initZ@Base 6
+ _D13TypeInfo_AyAa6__initZ@Base 6
+ _D13TypeInfo_Enum6__initZ@Base 6
+ _D13TypeInfo_Enum6__vtblZ@Base 6
+ _D13TypeInfo_Enum7__ClassZ@Base 6
+ _D13TypeInfo_xAPv6__initZ@Base 6
+ _D13TypeInfo_xG0h6__initZ@Base 6
+ _D143TypeInfo_S2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__initZ@Base 6
+ _D14TypeInfo_Array6__initZ@Base 6
+ _D14TypeInfo_Array6__vtblZ@Base 6
+ _D14TypeInfo_Array7__ClassZ@Base 6
+ _D14TypeInfo_Class6__initZ@Base 6
+ _D14TypeInfo_Class6__vtblZ@Base 6
+ _D14TypeInfo_Class7__ClassZ@Base 6
+ _D14TypeInfo_Const6__initZ@Base 6
+ _D14TypeInfo_Const6__vtblZ@Base 6
+ _D14TypeInfo_Const7__ClassZ@Base 6
+ _D14TypeInfo_Inout6__initZ@Base 6
+ _D14TypeInfo_Inout6__vtblZ@Base 6
+ _D14TypeInfo_Inout7__ClassZ@Base 6
+ _D14TypeInfo_Tuple6__initZ@Base 6
+ _D14TypeInfo_Tuple6__vtblZ@Base 6
+ _D14TypeInfo_Tuple7__ClassZ@Base 6
+ _D15TypeInfo_Shared6__initZ@Base 6
+ _D15TypeInfo_Shared6__vtblZ@Base 6
+ _D15TypeInfo_Shared7__ClassZ@Base 6
+ _D15TypeInfo_Struct6__initZ@Base 6
+ _D15TypeInfo_Struct6__vtblZ@Base 6
+ _D15TypeInfo_Struct7__ClassZ@Base 6
+ _D15TypeInfo_Vector6__initZ@Base 6
+ _D15TypeInfo_Vector6__vtblZ@Base 6
+ _D15TypeInfo_Vector7__ClassZ@Base 6
+ _D16TypeInfo_Pointer6__initZ@Base 6
+ _D16TypeInfo_Pointer6__vtblZ@Base 6
+ _D16TypeInfo_Pointer7__ClassZ@Base 6
+ _D16TypeInfo_Typedef6__initZ@Base 6
+ _D16TypeInfo_Typedef6__vtblZ@Base 6
+ _D16TypeInfo_Typedef7__ClassZ@Base 6
+ _D17TypeInfo_Delegate6__initZ@Base 6
+ _D17TypeInfo_Delegate6__vtblZ@Base 6
+ _D17TypeInfo_Delegate7__ClassZ@Base 6
+ _D17TypeInfo_Function6__initZ@Base 6
+ _D17TypeInfo_Function6__vtblZ@Base 6
+ _D17TypeInfo_Function7__ClassZ@Base 6
+ _D18TypeInfo_Interface6__initZ@Base 6
+ _D18TypeInfo_Interface6__vtblZ@Base 6
+ _D18TypeInfo_Interface7__ClassZ@Base 6
+ _D18TypeInfo_Invariant6__initZ@Base 6
+ _D18TypeInfo_Invariant6__vtblZ@Base 6
+ _D18TypeInfo_Invariant7__ClassZ@Base 6
+ _D19TypeInfo_S2gc2gc2GC6__initZ@Base 6
+ _D20TypeInfo_S2gc2gc3Gcx6__initZ@Base 6
+ _D20TypeInfo_S2rt3aaA2AA6__initZ@Base 6
+ _D20TypeInfo_StaticArray6__initZ@Base 6
+ _D20TypeInfo_StaticArray6__vtblZ@Base 6
+ _D20TypeInfo_StaticArray7__ClassZ@Base 6
+ _D20TypeInfo_xC8TypeInfo6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4List6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4Pool6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4Root6__initZ@Base 6
+ _D22TypeInfo_FNbC6ObjectZv6__initZ@Base 6
+ _D22TypeInfo_S2gc2gc5Range6__initZ@Base 6
+ _D22TypeInfo_S2rt3aaA4Impl6__initZ@Base 6
+ _D22TypeInfo_xS2gc2gc4List6__initZ@Base 6
+ _D22TypeInfo_xS2gc2gc4Root6__initZ@Base 6
+ _D23TypeInfo_DFNbC6ObjectZv6__initZ@Base 6
+ _D23TypeInfo_PxS2gc2gc4List6__initZ@Base 6
+ _D23TypeInfo_S2rt3aaA5Range6__initZ@Base 6
+ _D23TypeInfo_xPS2gc2gc4List6__initZ@Base 6
+ _D23TypeInfo_xS2gc2gc5Range6__initZ@Base 6
+ _D24TypeInfo_AxPS2gc2gc4List6__initZ@Base 6
+ _D24TypeInfo_S2rt3aaA6Bucket6__initZ@Base 6
+ _D24TypeInfo_S2rt5tlsgc4Data6__initZ@Base 6
+ _D24TypeInfo_xDFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_AssociativeArray6__initZ@Base 6
+ _D25TypeInfo_AssociativeArray6__vtblZ@Base 6
+ _D25TypeInfo_AssociativeArray7__ClassZ@Base 6
+ _D25TypeInfo_AxDFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_G8PxS2gc2gc4List6__initZ@Base 6
+ _D25TypeInfo_S2gc4bits6GCBits6__initZ@Base 6
+ _D25TypeInfo_S2gc5proxy5Proxy6__initZ@Base 6
+ _D25TypeInfo_S4core6memory2GC6__initZ@Base 6
+ _D25TypeInfo_S6object7AARange6__initZ@Base 6
+ _D25TypeInfo_xADFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_xG8PS2gc2gc4List6__initZ@Base 6
+ _D25TypeInfo_xS2rt3aaA6Bucket6__initZ@Base 6
+ _D26TypeInfo_AxS2rt3aaA6Bucket6__initZ@Base 6
+ _D26TypeInfo_S2rt6dmain25CArgs6__initZ@Base 6
+ _D26TypeInfo_xAS2rt3aaA6Bucket6__initZ@Base 6
+ _D27TypeInfo_S2gc5stats7GCStats6__initZ@Base 6
+ _D27TypeInfo_S2gc6config6Config6__initZ@Base 6
+ _D27TypeInfo_S6object9Interface6__initZ@Base 6
+ _D27TypeInfo_xC14TypeInfo_Class6__initZ@Base 6
+ _D28TypeInfo_E2rt3aaA4Impl5Flags6__initZ@Base 6
+ _D28TypeInfo_S2rt8lifetime5Array6__initZ@Base 6
+ _D28TypeInfo_S3gcc3deh9FuncTable6__initZ@Base 6
+ _D28TypeInfo_S4core4stdc4time2tm6__initZ@Base 6
+ _D28TypeInfo_S4core4time7FracSec6__initZ@Base 6
+ _D28TypeInfo_xC15TypeInfo_Struct6__initZ@Base 6
+ _D28TypeInfo_xC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_S4core4time8Duration6__initZ@Base 6
+ _D29TypeInfo_S4core7runtime5CArgs6__initZ@Base 6
+ _D29TypeInfo_S6object10ModuleInfo6__initZ@Base 6
+ _D29TypeInfo_xE2rt3aaA4Impl5Flags6__initZ@Base 6
+ _D29TypeInfo_yS3gcc3deh9FuncTable6__initZ@Base 6
+ _D2gc2gc10extendTimel@Base 6
+ _D2gc2gc10mallocTimel@Base 6
+ _D2gc2gc10notbinsizeyG11m@Base 6
+ _D2gc2gc10numExtendsl@Base 6
+ _D2gc2gc10numMallocsl@Base 6
+ _D2gc2gc11numReallocsl@Base 6
+ _D2gc2gc11reallocTimel@Base 6
+ _D2gc2gc11recoverTimeS4core4time8Duration@Base 6
+ _D2gc2gc12__ModuleInfoZ@Base 6
+ _D2gc2gc12maxPauseTimeS4core4time8Duration@Base 6
+ _D2gc2gc12sentinel_addFNbPvZPv@Base 6
+ _D2gc2gc12sentinel_subFNbPvZPv@Base 6
+ _D2gc2gc13maxPoolMemorym@Base 6
+ _D2gc2gc13sentinel_initFNbPvmZv@Base 6
+ _D2gc2gc14SENTINEL_EXTRAxk@Base 6
+ _D2gc2gc14numCollectionsm@Base 6
+ _D2gc2gc15LargeObjectPool10allocPagesMFNbmZm@Base 6
+ _D2gc2gc15LargeObjectPool13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc15LargeObjectPool13updateOffsetsMFNbmZv@Base 6
+ _D2gc2gc15LargeObjectPool6__initZ@Base 6
+ _D2gc2gc15LargeObjectPool7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc15LargeObjectPool7getSizeMxFNbPvZm@Base 6
+ _D2gc2gc15LargeObjectPool9freePagesMFNbmmZv@Base 6
+ _D2gc2gc15SmallObjectPool13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc15SmallObjectPool6__initZ@Base 6
+ _D2gc2gc15SmallObjectPool7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc15SmallObjectPool7getSizeMxFNbPvZm@Base 6
+ _D2gc2gc15SmallObjectPool9allocPageMFNbhZPS2gc2gc4List@Base 6
+ _D2gc2gc18sentinel_InvariantFNbxPvZv@Base 6
+ _D2gc2gc2GC10freeNoSyncMFNbPvZv@Base 6
+ _D2gc2gc2GC10initializeMFZv@Base 6
+ _D2gc2gc2GC10removeRootMFNbPvZv@Base 6
+ _D2gc2gc2GC11checkNoSyncMFNbPvZv@Base 6
+ _D2gc2gc2GC11fullCollectMFNbZm@Base 6
+ _D2gc2gc2GC11queryNoSyncMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc2GC11removeRangeMFNbNiPvZv@Base 6
+ _D2gc2gc2GC12addrOfNoSyncMFNbPvZPv@Base 6
+ _D2gc2gc2GC12extendNoSyncMFNbPvmmxC8TypeInfoZm@Base 6
+ _D2gc2gc2GC12mallocNoSyncMFNbmkKmxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC12mutexStorageG72v@Base 6
+ _D2gc2gc2GC12rootIterImplMFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2gc2gc2GC12sizeOfNoSyncMFNbPvZm@Base 6
+ _D2gc2gc2GC13rangeIterImplMFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2gc2gc2GC13reallocNoSyncMFNbPvmKkKmxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC13reserveNoSyncMFNbmZm@Base 6
+ _D2gc2gc2GC13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc2GC14getStatsNoSyncMFNbJS2gc5stats7GCStatsZv@Base 6
+ _D2gc2gc2GC18fullCollectNoStackMFNbZv@Base 6
+ _D2gc2gc2GC4DtorMFZv@Base 6
+ _D2gc2gc2GC4filePa@Base 6
+ _D2gc2gc2GC4freeMFNbPvZv@Base 6
+ _D2gc2gc2GC4linem@Base 6
+ _D2gc2gc2GC5checkMFNbPvZv@Base 6
+ _D2gc2gc2GC5queryMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc2GC6__initZ@Base 6
+ _D2gc2gc2GC6addrOfMFNbPvZPv@Base 6
+ _D2gc2gc2GC6callocMFNbmkPmxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC6configS2gc6config6Config@Base 6
+ _D2gc2gc2GC6enableMFZv@Base 6
+ _D2gc2gc2GC6extendMFNbPvmmxC8TypeInfoZm@Base 6
+ _D2gc2gc2GC6gcLockC2gc2gc7GCMutex@Base 6
+ _D2gc2gc2GC6mallocMFNbmkPmxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC6sizeOfMFNbPvZm@Base 6
+ _D2gc2gc2GC7addRootMFNbPvZv@Base 6
+ _D2gc2gc2GC7clrAttrMFNbPvkZk@Base 6
+ _D2gc2gc2GC7disableMFZv@Base 6
+ _D2gc2gc2GC7getAttrMFNbPvZk@Base 6
+ _D2gc2gc2GC7reallocMFNbPvmkPmxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC7reserveMFNbmZm@Base 6
+ _D2gc2gc2GC7setAttrMFNbPvkZk@Base 6
+ _D2gc2gc2GC8addRangeMFNbNiPvmxC8TypeInfoZv@Base 6
+ _D2gc2gc2GC8getStatsMFNbJS2gc5stats7GCStatsZv@Base 6
+ _D2gc2gc2GC8minimizeMFNbZv@Base 6
+ _D2gc2gc2GC8rootIterMFNaNbNdNiNfZDFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2gc2gc2GC9rangeIterMFNaNbNdNiNfZDFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2gc2gc3Gcx10initializeMFZv@Base 6
+ _D2gc2gc3Gcx10log_mallocMFNbPvmZv@Base 6
+ _D2gc2gc3Gcx10log_parentMFNbPvPvZv@Base 6
+ _D2gc2gc3Gcx10removeRootMFNbPvZv@Base 6
+ _D2gc2gc3Gcx10smallAllocMFNbhKmkZPv@Base 6
+ _D2gc2gc3Gcx11ToScanStack14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack3popMFNbZS2gc2gc5Range@Base 6
+ _D2gc2gc3Gcx11ToScanStack4growMFNbZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack4pushMFNbS2gc2gc5RangeZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack5emptyMxFNbNdZb@Base 6
+ _D2gc2gc3Gcx11ToScanStack5resetMFNbZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D2gc2gc3Gcx11ToScanStack6lengthMxFNbNdZm@Base 6
+ _D2gc2gc3Gcx11ToScanStack7opIndexMNgFNbNcmZNgS2gc2gc5Range@Base 6
+ _D2gc2gc3Gcx11ToScanStack8opAssignMFNaNbNcNiNjNeS2gc2gc3Gcx11ToScanStackZS2gc2gc3Gcx11ToScanStack@Base 6
+ _D2gc2gc3Gcx11__fieldDtorMFNbNiZv@Base 6
+ _D2gc2gc3Gcx11__xopEqualsFKxS2gc2gc3GcxKxS2gc2gc3GcxZb@Base 6
+ _D2gc2gc3Gcx11fullcollectMFNbbZm@Base 6
+ _D2gc2gc3Gcx11log_collectMFNbZv@Base 6
+ _D2gc2gc3Gcx11removeRangeMFNbNiPvZv@Base 6
+ _D2gc2gc3Gcx13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZ11smoothDecayFNbffZf@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZ3maxFNbffZf@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZv@Base 6
+ _D2gc2gc3Gcx4DtorMFZv@Base 6
+ _D2gc2gc3Gcx4markMFNbPvPvZv@Base 6
+ _D2gc2gc3Gcx5allocMFNbmKmkZPv@Base 6
+ _D2gc2gc3Gcx5sweepMFNbZm@Base 6
+ _D2gc2gc3Gcx6__initZ@Base 6
+ _D2gc2gc3Gcx6lowMemMxFNbNdZb@Base 6
+ _D2gc2gc3Gcx6npoolsMxFNaNbNdZm@Base 6
+ _D2gc2gc3Gcx7addRootMFNbPvZv@Base 6
+ _D2gc2gc3Gcx7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc3Gcx7markAllMFNbbZv@Base 6
+ _D2gc2gc3Gcx7newPoolMFNbmbZPS2gc2gc4Pool@Base 6
+ _D2gc2gc3Gcx7prepareMFNbZv@Base 6
+ _D2gc2gc3Gcx7recoverMFNbZm@Base 6
+ _D2gc2gc3Gcx7reserveMFNbmZm@Base 6
+ _D2gc2gc3Gcx8addRangeMFNbNiPvPvxC8TypeInfoZv@Base 6
+ _D2gc2gc3Gcx8bigAllocMFNbmKmkxC8TypeInfoZPv@Base 6
+ _D2gc2gc3Gcx8binTablexG2049g@Base 6
+ _D2gc2gc3Gcx8ctfeBinsFNbZG2049g@Base 6
+ _D2gc2gc3Gcx8findBaseMFNbPvZPv@Base 6
+ _D2gc2gc3Gcx8findPoolMFNaNbPvZPS2gc2gc4Pool@Base 6
+ _D2gc2gc3Gcx8findSizeMFNbPvZm@Base 6
+ _D2gc2gc3Gcx8isMarkedMFNbPvZi@Base 6
+ _D2gc2gc3Gcx8log_freeMFNbPvZv@Base 6
+ _D2gc2gc3Gcx8log_initMFNbZv@Base 6
+ _D2gc2gc3Gcx8minimizeMFNbZv@Base 6
+ _D2gc2gc3Gcx8opAssignMFNbNcNiNjS2gc2gc3GcxZS2gc2gc3Gcx@Base 6
+ _D2gc2gc3Gcx9InvariantMxFZv@Base 6
+ _D2gc2gc3Gcx9__xtoHashFNbNeKxS2gc2gc3GcxZm@Base 6
+ _D2gc2gc3Gcx9allocPageMFNbhZPS2gc2gc4List@Base 6
+ _D2gc2gc3setFNaNbNiKG4mmZv@Base 6
+ _D2gc2gc4List6__initZ@Base 6
+ _D2gc2gc4Pool10initializeMFNbmbZv@Base 6
+ _D2gc2gc4Pool12freePageBitsMFNbmKxG4mZv@Base 6
+ _D2gc2gc4Pool4DtorMFNbZv@Base 6
+ _D2gc2gc4Pool6__initZ@Base 6
+ _D2gc2gc4Pool6isFreeMxFNaNbNdZb@Base 6
+ _D2gc2gc4Pool7clrBitsMFNbmkZv@Base 6
+ _D2gc2gc4Pool7getBitsMFNbmZk@Base 6
+ _D2gc2gc4Pool7setBitsMFNbmkZv@Base 6
+ _D2gc2gc4Pool9InvariantMxFZv@Base 6
+ _D2gc2gc4Pool9pagenumOfMxFNbPvZm@Base 6
+ _D2gc2gc4Pool9slGetInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc4Pool9slGetSizeMFNbPvZm@Base 6
+ _D2gc2gc4Root6__initZ@Base 6
+ _D2gc2gc5Range6__initZ@Base 6
+ _D2gc2gc7GCMutex4lockMFNbNiNeZv@Base 6
+ _D2gc2gc7GCMutex6__ctorMFNbNeZC2gc2gc7GCMutex@Base 6
+ _D2gc2gc7GCMutex6__initZ@Base 6
+ _D2gc2gc7GCMutex6__vtblZ@Base 6
+ _D2gc2gc7GCMutex6unlockMFNbNiNeZv@Base 6
+ _D2gc2gc7GCMutex7__ClassZ@Base 6
+ _D2gc2gc7binsizeyG11k@Base 6
+ _D2gc2gc8freeTimel@Base 6
+ _D2gc2gc8lockTimel@Base 6
+ _D2gc2gc8markTimeS4core4time8Duration@Base 6
+ _D2gc2gc8numFreesl@Base 6
+ _D2gc2gc8prepTimeS4core4time8Duration@Base 6
+ _D2gc2gc9GCVERSIONxk@Base 6
+ _D2gc2gc9numOthersl@Base 6
+ _D2gc2gc9otherTimel@Base 6
+ _D2gc2gc9sweepTimeS4core4time8Duration@Base 6
+ _D2gc2os10isLowOnMemFNbNimZb@Base 6
+ _D2gc2os10os_mem_mapFNbmZPv@Base 6
+ _D2gc2os12__ModuleInfoZ@Base 6
+ _D2gc2os12os_mem_unmapFNbPvmZi@Base 6
+ _D2gc4bits12__ModuleInfoZ@Base 6
+ _D2gc4bits6GCBits3setMFNbmZi@Base 6
+ _D2gc4bits6GCBits4DtorMFNbZv@Base 6
+ _D2gc4bits6GCBits4copyMFNbPS2gc4bits6GCBitsZv@Base 6
+ _D2gc4bits6GCBits4testMxFNbmZm@Base 6
+ _D2gc4bits6GCBits4zeroMFNbZv@Base 6
+ _D2gc4bits6GCBits5allocMFNbmZv@Base 6
+ _D2gc4bits6GCBits5clearMFNbmZi@Base 6
+ _D2gc4bits6GCBits6__initZ@Base 6
+ _D2gc4bits6GCBits6nwordsMxFNaNbNdZm@Base 6
+ _D2gc5proxy12__ModuleInfoZ@Base 6
+ _D2gc5proxy3_gcS2gc2gc2GC@Base 6
+ _D2gc5proxy5Proxy6__initZ@Base 6
+ _D2gc5proxy5proxyPS2gc5proxy5Proxy@Base 6
+ _D2gc5proxy5pthisS2gc5proxy5Proxy@Base 6
+ _D2gc5proxy9initProxyFZv@Base 6
+ _D2gc5stats12__ModuleInfoZ@Base 6
+ _D2gc5stats7GCStats6__initZ@Base 6
+ _D2gc6config10parseErrorFNbNixAaxAaxAaZb@Base 6
+ _D2gc6config12__ModuleInfoZ@Base 6
+ _D2gc6config13__T5parseHTbZ5parseFNbNiAxaKAxaKbZb@Base 6
+ _D2gc6config13__T5parseHTfZ5parseFNbNiAxaKAxaKfZb@Base 6
+ _D2gc6config13__T5parseHThZ5parseFNbNiAxaKAxaKhZb@Base 6
+ _D2gc6config13__T5parseHTmZ5parseFNbNiAxaKAxaKmZb@Base 6
+ _D2gc6config18__T4skipS7isspaceZ4skipFNaNbNiNfANgaZANga@Base 6
+ _D2gc6config18__T4skipS7isspaceZ4skipFNbNiANgaZ18__T9__lambda2TNgaZ9__lambda2FNaNbNiNfNgaZb@Base 6
+ _D2gc6config3minFNbNimmZm@Base 6
+ _D2gc6config6Config10initializeMFNbNiZb@Base 6
+ _D2gc6config6Config11__xopEqualsFKxS2gc6config6ConfigKxS2gc6config6ConfigZb@Base 6
+ _D2gc6config6Config12parseOptionsMFNbNiAxaZ18__T9__lambda2TNgaZ9__lambda2FNaNbNiNfNgaZb@Base 6
+ _D2gc6config6Config12parseOptionsMFNbNiAxaZb@Base 6
+ _D2gc6config6Config4helpMFNbNiZv@Base 6
+ _D2gc6config6Config6__initZ@Base 6
+ _D2gc6config6Config9__xtoHashFNbNeKxS2gc6config6ConfigZm@Base 6
+ _D2gc6config8optErrorFNbNixAaxAaZb@Base 6
+ _D2gc9pooltable12__ModuleInfoZ@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable4DtorMFNbNiZv@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6insertMFNbNiPS2gc2gc4PoolZb@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6lengthMxFNaNbNdNiNfZm@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7maxAddrMxFNaNbNdNiNfZPxg@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7minAddrMxFNaNbNdNiNfZPxg@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7opIndexMNgFNaNbNcNimZNgPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7opSliceMNgFNaNbNimmZANgPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8findPoolMFNaNbNiPvZPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8minimizeMFNaNbZ4swapFNaNbNiNfKPS2gc2gc4PoolKPS2gc2gc4PoolZv@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8minimizeMFNaNbZAPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable9InvariantMxFNaNbNiZv@Base 6
+ _D2rt11arrayassign12__ModuleInfoZ@Base 6
+ _D2rt12sections_osx12__ModuleInfoZ@Base 6
+ _D2rt14sections_win3212__ModuleInfoZ@Base 6
+ _D2rt14sections_win6412__ModuleInfoZ@Base 6
+ _D2rt16sections_android12__ModuleInfoZ@Base 6
+ _D2rt16sections_solaris12__ModuleInfoZ@Base 6
+ _D2rt19sections_elf_shared10_rtLoadingb@Base 6
+ _D2rt19sections_elf_shared11_loadedDSOsS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt19sections_elf_shared11getTLSRangeFmmZAv@Base 6
+ _D2rt19sections_elf_shared12__ModuleInfoZ@Base 6
+ _D2rt19sections_elf_shared12_handleToDSOS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab@Base 6
+ _D2rt19sections_elf_shared12decThreadRefFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared12dsoForHandleFNbPvZPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt19sections_elf_shared12finiSectionsFZv@Base 6
+ _D2rt19sections_elf_shared12incThreadRefFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared12initSectionsFZv@Base 6
+ _D2rt19sections_elf_shared12scanSegmentsFKxS4core3sys5linux4link12dl_phdr_infoPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared13findThreadDSOFPS2rt19sections_elf_shared3DSOZPS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt19sections_elf_shared13finiTLSRangesFPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZv@Base 6
+ _D2rt19sections_elf_shared13handleForAddrFPvZPv@Base 6
+ _D2rt19sections_elf_shared13handleForNameFNbxPaZPv@Base 6
+ _D2rt19sections_elf_shared13initTLSRangesFZPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt19sections_elf_shared13runFinalizersFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared13scanTLSRangesFNbPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayMDFNbPvPvZvZv@Base 6
+ _D2rt19sections_elf_shared15CompilerDSOData6__initZ@Base 6
+ _D2rt19sections_elf_shared15getDependenciesFNbKxS4core3sys5linux4link12dl_phdr_infoKS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZv@Base 6
+ _D2rt19sections_elf_shared15setDSOForHandleFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt19sections_elf_shared16linkMapForHandleFNbPvZPS4core3sys5linux4link8link_map@Base 6
+ _D2rt19sections_elf_shared16registerGCRangesFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared17_handleToDSOMutexS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D2rt19sections_elf_shared17unsetDSOForHandleFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ2DG6__initZ@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ8callbackUNbNiPS4core3sys5linux4link12dl_phdr_infomPvZi@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZb@Base 6
+ _D2rt19sections_elf_shared18findSegmentForAddrFNbNiKxS4core3sys5linux4link12dl_phdr_infoxPvPS4core3sys5linux3elf10Elf64_PhdrZb@Base 6
+ _D2rt19sections_elf_shared18pinLoadedLibrariesFNbZPv@Base 6
+ _D2rt19sections_elf_shared18unregisterGCRangesFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared20runModuleDestructorsFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared20unpinLoadedLibrariesFNbPvZv@Base 6
+ _D2rt19sections_elf_shared21_isRuntimeInitializedb@Base 6
+ _D2rt19sections_elf_shared21checkModuleCollisionsFNbKxS4core3sys5linux4link12dl_phdr_infoxAPyS6object10ModuleInfoZv@Base 6
+ _D2rt19sections_elf_shared21runModuleConstructorsFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared22cleanupLoadedLibrariesFZv@Base 6
+ _D2rt19sections_elf_shared22inheritLoadedLibrariesFPvZv@Base 6
+ _D2rt19sections_elf_shared33__T7toRangeTyS3gcc3deh9FuncTableZ7toRangeFNaNbNiPyS3gcc3deh9FuncTablePyS3gcc3deh9FuncTableZAyS3gcc3deh9FuncTable@Base 6
+ _D2rt19sections_elf_shared35__T7toRangeTyPS6object10ModuleInfoZ7toRangeFNaNbNiPyPS6object10ModuleInfoPyPS6object10ModuleInfoZAyPS6object10ModuleInfo@Base 6
+ _D2rt19sections_elf_shared3DSO11__fieldDtorMFNbZv@Base 6
+ _D2rt19sections_elf_shared3DSO11__invariantMxFZv@Base 6
+ _D2rt19sections_elf_shared3DSO11__xopEqualsFKxS2rt19sections_elf_shared3DSOKxS2rt19sections_elf_shared3DSOZb@Base 6
+ _D2rt19sections_elf_shared3DSO11moduleGroupMNgFNcNdZNgS2rt5minfo11ModuleGroup@Base 6
+ _D2rt19sections_elf_shared3DSO12__invariant1MxFZv@Base 6
+ _D2rt19sections_elf_shared3DSO14opApplyReverseFMDFKS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D2rt19sections_elf_shared3DSO7modulesMxFNdZAyPS6object10ModuleInfo@Base 6
+ _D2rt19sections_elf_shared3DSO7opApplyFMDFKS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt19sections_elf_shared3DSO8ehTablesMxFNdZAyS3gcc3deh9FuncTable@Base 6
+ _D2rt19sections_elf_shared3DSO8gcRangesMNgFNdZANgAv@Base 6
+ _D2rt19sections_elf_shared3DSO8opAssignMFNbNcNjS2rt19sections_elf_shared3DSOZS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt19sections_elf_shared3DSO9__xtoHashFNbNeKxS2rt19sections_elf_shared3DSOZm@Base 6
+ _D2rt19sections_elf_shared7dsoNameFNbxPaZAxa@Base 6
+ _D2rt19sections_elf_shared7freeDSOFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared8prognameFNbNdNiZPxa@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO11__xopEqualsFKxS2rt19sections_elf_shared9ThreadDSOKxS2rt19sections_elf_shared9ThreadDSOZb@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO6__initZ@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO9__xtoHashFNbNeKxS2rt19sections_elf_shared9ThreadDSOZm@Base 6
+ _D2rt19sections_elf_shared9finiLocksFZv@Base 6
+ _D2rt19sections_elf_shared9initLocksFZv@Base 6
+ _D2rt19sections_elf_shared9tls_index6__initZ@Base 6
+ _D2rt3aaA10__T3maxTmZ3maxFNaNbNiNfmmZm@Base 6
+ _D2rt3aaA10__T3minTkZ3minFNaNbNiNfkkZk@Base 6
+ _D2rt3aaA10allocEntryFxPS2rt3aaA4ImplxPvZPv@Base 6
+ _D2rt3aaA11fakeEntryTIFxC8TypeInfoxC8TypeInfoZ6tiNameyAa@Base 6
+ _D2rt3aaA11fakeEntryTIFxC8TypeInfoxC8TypeInfoZC15TypeInfo_Struct@Base 6
+ _D2rt3aaA12__ModuleInfoZ@Base 6
+ _D2rt3aaA12allocBucketsFNaNbNemZAS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA2AA5emptyMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA2AA6__initZ@Base 6
+ _D2rt3aaA3mixFNaNbNiNfmZm@Base 6
+ _D2rt3aaA4Impl11__xopEqualsFKxS2rt3aaA4ImplKxS2rt3aaA4ImplZb@Base 6
+ _D2rt3aaA4Impl14findSlotInsertMNgFNaNbNimZPNgS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA4Impl14findSlotLookupMNgFmxPvxC8TypeInfoZPNgS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA4Impl3dimMxFNaNbNdNiZm@Base 6
+ _D2rt3aaA4Impl4growMFxC8TypeInfoZv@Base 6
+ _D2rt3aaA4Impl4maskMxFNaNbNdNiZm@Base 6
+ _D2rt3aaA4Impl6__ctorMFNcxC25TypeInfo_AssociativeArraymZS2rt3aaA4Impl@Base 6
+ _D2rt3aaA4Impl6__initZ@Base 6
+ _D2rt3aaA4Impl6lengthMxFNaNbNdNiZm@Base 6
+ _D2rt3aaA4Impl6resizeMFNaNbmZv@Base 6
+ _D2rt3aaA4Impl6shrinkMFxC8TypeInfoZv@Base 6
+ _D2rt3aaA4Impl9__xtoHashFNbNeKxS2rt3aaA4ImplZm@Base 6
+ _D2rt3aaA5Range6__initZ@Base 6
+ _D2rt3aaA6Bucket5emptyMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6Bucket6__initZ@Base 6
+ _D2rt3aaA6Bucket6filledMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6Bucket7deletedMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6talignFNaNbNiNfmmZm@Base 6
+ _D2rt3aaA7hasDtorFxC8TypeInfoZb@Base 6
+ _D2rt3aaA8calcHashFxPvxC8TypeInfoZm@Base 6
+ _D2rt3aaA8nextpow2FNaNbNixmZm@Base 6
+ _D2rt3aaA9entryDtorFPvxC15TypeInfo_StructZv@Base 6
+ _D2rt3adi12__ModuleInfoZ@Base 6
+ _D2rt3adi19__T11mallocUTF32TaZ11mallocUTF32FNixAaZAw@Base 6
+ _D2rt3adi19__T11mallocUTF32TuZ11mallocUTF32FNixAuZAw@Base 6
+ _D2rt3deh12__ModuleInfoZ@Base 6
+ _D2rt3obj12__ModuleInfoZ@Base 6
+ _D2rt4util3utf10UTF8strideyAi@Base 6
+ _D2rt4util3utf10toUCSindexFxAamZm@Base 6
+ _D2rt4util3utf10toUCSindexFxAumZm@Base 6
+ _D2rt4util3utf10toUCSindexFxAwmZm@Base 6
+ _D2rt4util3utf10toUTFindexFxAamZm@Base 6
+ _D2rt4util3utf10toUTFindexFxAumZm@Base 6
+ _D2rt4util3utf10toUTFindexFxAwmZm@Base 6
+ _D2rt4util3utf12__ModuleInfoZ@Base 6
+ _D2rt4util3utf12isValidDcharFwZb@Base 6
+ _D2rt4util3utf17__T8validateTAyaZ8validateFxAyaZv@Base 6
+ _D2rt4util3utf17__T8validateTAyuZ8validateFxAyuZv@Base 6
+ _D2rt4util3utf17__T8validateTAywZ8validateFxAywZv@Base 6
+ _D2rt4util3utf6decodeFxAaKmZw@Base 6
+ _D2rt4util3utf6decodeFxAuKmZw@Base 6
+ _D2rt4util3utf6decodeFxAwKmZw@Base 6
+ _D2rt4util3utf6encodeFKAawZv@Base 6
+ _D2rt4util3utf6encodeFKAuwZv@Base 6
+ _D2rt4util3utf6encodeFKAwwZv@Base 6
+ _D2rt4util3utf6strideFxAamZk@Base 6
+ _D2rt4util3utf6strideFxAumZk@Base 6
+ _D2rt4util3utf6strideFxAwmZk@Base 6
+ _D2rt4util3utf6toUTF8FAyaZAya@Base 6
+ _D2rt4util3utf6toUTF8FNkJG4awZAa@Base 6
+ _D2rt4util3utf6toUTF8FxAuZAya@Base 6
+ _D2rt4util3utf6toUTF8FxAwZAya@Base 6
+ _D2rt4util3utf7toUTF16FAyuZAyu@Base 6
+ _D2rt4util3utf7toUTF16FNkJG2uwZAu@Base 6
+ _D2rt4util3utf7toUTF16FxAaZAyu@Base 6
+ _D2rt4util3utf7toUTF16FxAwZAyu@Base 6
+ _D2rt4util3utf7toUTF32FAywZAyw@Base 6
+ _D2rt4util3utf7toUTF32FxAaZAyw@Base 6
+ _D2rt4util3utf7toUTF32FxAuZAyw@Base 6
+ _D2rt4util3utf8toUTF16zFxAaZPxu@Base 6
+ _D2rt4util4hash12__ModuleInfoZ@Base 6
+ _D2rt4util4hash6hashOfFNaNbNePxvmmZ9get16bitsFNaNbPxhZk@Base 6
+ _D2rt4util4hash6hashOfFNaNbNePxvmmZm@Base 6
+ _D2rt4util5array12__ModuleInfoZ@Base 6
+ _D2rt4util5array17_enforceNoOverlapFNbNfxAaxPvxPvxmZv@Base 6
+ _D2rt4util5array18_enforceSameLengthFNbNfxAaxmxmZv@Base 6
+ _D2rt4util5array27enforceRawArraysConformableFNbNfxAaxmxAvxAvxbZv@Base 6
+ _D2rt4util6random12__ModuleInfoZ@Base 6
+ _D2rt4util6random6Rand4811defaultSeedMFNbZv@Base 6
+ _D2rt4util6random6Rand484seedMFNbkZv@Base 6
+ _D2rt4util6random6Rand485frontMFNbNdNiZk@Base 6
+ _D2rt4util6random6Rand486__initZ@Base 6
+ _D2rt4util6random6Rand486opCallMFNbNiZk@Base 6
+ _D2rt4util6random6Rand488popFrontMFNbNiZv@Base 6
+ _D2rt4util6string12__ModuleInfoZ@Base 6
+ _D2rt4util6string16sizeToTempStringFNaNbNexmAaZAa@Base 6
+ _D2rt4util6string16uintToTempStringFNaNbNexkAaZAa@Base 6
+ _D2rt4util6string17ulongToTempStringFNaNbNexmAaZAa@Base 6
+ _D2rt4util6string29__T21_unsignedToTempStringTkZ21_unsignedToTempStringFNaNbNiNexkAaZAa@Base 6
+ _D2rt4util6string29__T21_unsignedToTempStringTmZ21_unsignedToTempStringFNaNbNiNexmAaZAa@Base 6
+ _D2rt4util6string7dstrcmpFNaNbNexAaxAaZi@Base 6
+ _D2rt4util8typeinfo12__ModuleInfoZ@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ6equalsFNaNbNfAcAcZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ6hashOfFNaNbNfAcZm@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ7compareFNaNbNfAcAcZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ6equalsFNaNbNfAdAdZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ6hashOfFNaNbNfAdZm@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ7compareFNaNbNfAdAdZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ6equalsFNaNbNfAeAeZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ6hashOfFNaNbNfAeZm@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ7compareFNaNbNfAeAeZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ6equalsFNaNbNfAfAfZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ6hashOfFNaNbNfAfZm@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ7compareFNaNbNfAfAfZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ6equalsFNaNbNfAqAqZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ6hashOfFNaNbNfAqZm@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ7compareFNaNbNfAqAqZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ6equalsFNaNbNfArArZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ6hashOfFNaNbNfArZm@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ7compareFNaNbNfArArZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ6equalsFNaNbNfccZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ6hashOfFNaNbNecZm@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ7compareFNaNbNfccZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ6equalsFNaNbNfddZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ6hashOfFNaNbNedZm@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ7compareFNaNbNfddZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ6equalsFNaNbNfeeZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ6hashOfFNaNbNeeZm@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ7compareFNaNbNfeeZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ6equalsFNaNbNfffZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ6hashOfFNaNbNefZm@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ7compareFNaNbNfffZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ6equalsFNaNbNfqqZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ6hashOfFNaNbNeqZm@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ7compareFNaNbNfqqZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ6equalsFNaNbNfrrZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ6hashOfFNaNbNerZm@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ7compareFNaNbNfrrZi@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array4backMNgFNaNbNcNdNiZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array4swapMFNaNbNiNfKS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5ArrayZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5frontMNgFNaNbNcNdNiNfZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__initZ@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6lengthMFNbNdmZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6lengthMxFNaNbNdNiNfZm@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6removeMFNbmZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opIndexMNgFNaNbNcNimZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opSliceMNgFNaNbNiZANgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opSliceMNgFNaNbNimmZANgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array8opAssignMFNbNcNjS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5ArrayZS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array@Base 6
+ _D2rt4util9container5array12__ModuleInfoZ@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array16__T10insertBackZ10insertBackMFNbAvZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array4backMNgFNaNbNcNdNiZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array4swapMFNaNbNiNfKS2rt4util9container5array13__T5ArrayTAvZ5ArrayZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5frontMNgFNaNbNcNdNiNfZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6lengthMFNbNdmZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6lengthMxFNaNbNdNiNfZm@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6removeMFNbmZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opIndexMNgFNaNbNcNimZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opSliceMNgFNaNbNiZANgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opSliceMNgFNaNbNimmZANgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array8opAssignMFNbNcNjS2rt4util9container5array13__T5ArrayTAvZ5ArrayZS2rt4util9container5array13__T5ArrayTAvZ5Array@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array16__T10insertBackZ10insertBackMFNbKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array4backMNgFNaNbNcNdNiZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array4swapMFNaNbNiNfKS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5frontMNgFNaNbNcNdNiNfZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6lengthMFNbNdmZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6lengthMxFNaNbNdNiNfZm@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6removeMFNbmZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opIndexMNgFNaNbNcNimZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opSliceMNgFNaNbNiZANgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opSliceMNgFNaNbNimmZANgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array8opAssignMFNbNcNjS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array16__T10insertBackZ10insertBackMFNbS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array4backMNgFNaNbNcNdNiZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array4swapMFNaNbNiNfKS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5frontMNgFNaNbNcNdNiNfZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__initZ@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6lengthMFNbNdmZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6lengthMxFNaNbNdNiNfZm@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6removeMFNbmZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opIndexMNgFNaNbNcNimZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opSliceMNgFNaNbNiZANgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opSliceMNgFNaNbNimmZANgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array8opAssignMFNbNcNjS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt4util9container5treap12__ModuleInfoZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap10initializeMFNbZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap13opApplyHelperFNbxPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeMDFNbKxS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node11__xopEqualsFKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZb@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node9__xtoHashFNbNeKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZm@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__dtorMFNbNiZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6insertMFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeS2gc2gc4RootZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6insertMFNbNiS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6removeFNbNiPPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6removeMFNbNiS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7opApplyMFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7opApplyMxFNbMDFNbKxS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7rotateLFNaNbNiNfPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7rotateRFNaNbNiNfPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap8freeNodeFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap8opAssignMFNbNcNiNjS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5TreapZS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9allocNodeMFNbNiS2gc2gc4RootZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9removeAllFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9removeAllMFNbNiZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap10initializeMFNbZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap13opApplyHelperFNbxPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeMDFNbKxS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node11__xopEqualsFKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZb@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node9__xtoHashFNbNeKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZm@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__dtorMFNbNiZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6insertMFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeS2gc2gc5RangeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6insertMFNbNiS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6removeFNbNiPPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6removeMFNbNiS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7opApplyMFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7opApplyMxFNbMDFNbKxS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7rotateLFNaNbNiNfPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7rotateRFNaNbNiNfPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap8freeNodeFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap8opAssignMFNbNcNiNjS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5TreapZS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9allocNodeMFNbNiS2gc2gc5RangeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9removeAllFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9removeAllMFNbNiZv@Base 6
+ _D2rt4util9container6common101__T7destroyTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common102__T7destroyTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common105__T10initializeTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ10initializeFNaNbNiKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common106__T10initializeTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ10initializeFNaNbNiNfKPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common12__ModuleInfoZ@Base 6
+ _D2rt4util9container6common15__T7destroyTAvZ7destroyFNaNbNiNfKAvZv@Base 6
+ _D2rt4util9container6common19__T10initializeTAvZ10initializeFNaNbNiNfKAvZv@Base 6
+ _D2rt4util9container6common43__T7destroyTPS2rt19sections_elf_shared3DSOZ7destroyFNaNbNiNfKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container6common47__T10initializeTPS2rt19sections_elf_shared3DSOZ10initializeFNaNbNiNfKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container6common48__T7destroyTS2rt19sections_elf_shared9ThreadDSOZ7destroyFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container6common52__T10initializeTS2rt19sections_elf_shared9ThreadDSOZ10initializeFNaNbNiKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container6common7xmallocFNbNimZPv@Base 6
+ _D2rt4util9container6common8xreallocFNbPvmZPv@Base 6
+ _D2rt4util9container7hashtab12__ModuleInfoZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab10__aggrDtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab11__fieldDtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab13opIndexAssignMFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab18ensureNotInOpApplyMFNaNbNiNfZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab3getMFNbPvZPPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node6__initZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4growMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4maskMxFNaNbNdNiNfZm@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab5resetMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__dtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__initZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6hashOfFNaNbKxPvZm@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6lengthMxFNaNbNdNiNfZm@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6opIn_rMNgFNaNbxPvZPNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6removeMFNbxPvZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6shrinkMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab7opApplyMFMDFKPvKPS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab7opIndexMNgFNaNbNcPvZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab8opAssignMFNbNcNjS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTabZS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab@Base 6
+ _D2rt5cast_12__ModuleInfoZ@Base 6
+ _D2rt5minfo11ModuleGroup11__xopEqualsFKxS2rt5minfo11ModuleGroupKxS2rt5minfo11ModuleGroupZb@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsCtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsCtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsDtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsDtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup4freeMFZv@Base 6
+ _D2rt5minfo11ModuleGroup6__ctorMFNcAyPS6object10ModuleInfoZS2rt5minfo11ModuleGroup@Base 6
+ _D2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D2rt5minfo11ModuleGroup7modulesMxFNdZAyPS6object10ModuleInfo@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZ37__T9__lambda2TPyS6object10ModuleInfoZ9__lambda2FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runDtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runDtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup9__xtoHashFNbNeKxS2rt5minfo11ModuleGroupZm@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ10findModuleMFxPS6object10ModuleInfoZi@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec11__xopEqualsFKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecZb@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec3modMFNdZPyS6object10ModuleInfo@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec6__initZ@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec9__xtoHashFNbNeKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecZm@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZv@Base 6
+ _D2rt5minfo12__ModuleInfoZ@Base 6
+ _D2rt5minfo17moduleinfos_applyFMDFyPS6object10ModuleInfoZiZi@Base 6
+ _D2rt5qsort12__ModuleInfoZ@Base 6
+ _D2rt5qsort7_adSortUAvC8TypeInfoZ3cmpUxPvxPvPvZi@Base 6
+ _D2rt5tlsgc12__ModuleInfoZ@Base 6
+ _D2rt5tlsgc14processGCMarksFNbPvMDFNbPvZiZv@Base 6
+ _D2rt5tlsgc4Data6__initZ@Base 6
+ _D2rt5tlsgc4initFZPv@Base 6
+ _D2rt5tlsgc4scanFNbPvMDFNbPvPvZvZv@Base 6
+ _D2rt5tlsgc7destroyFPvZv@Base 6
+ _D2rt6aApply12__ModuleInfoZ@Base 6
+ _D2rt6config12__ModuleInfoZ@Base 6
+ _D2rt6config13rt_linkOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6config15rt_configOptionFNbNiAyaMDFNbNiAyaZAyabZAya@Base 6
+ _D2rt6config16rt_cmdlineOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6config16rt_envvarsOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6dmain210_initCountOm@Base 6
+ _D2rt6dmain211_d_run_mainUiPPaPUAAaZiZ7tryExecMFMDFZvZv@Base 6
+ _D2rt6dmain212__ModuleInfoZ@Base 6
+ _D2rt6dmain212traceHandlerPFPvZC6object9Throwable9TraceInfo@Base 6
+ _D2rt6dmain215formatThrowableFC6object9ThrowableDFNbxAaZvZv@Base 6
+ _D2rt6dmain25CArgs6__initZ@Base 6
+ _D2rt6dmain26_cArgsS2rt6dmain25CArgs@Base 6
+ _D2rt6dmain27_d_argsAAya@Base 6
+ _D2rt6memory12__ModuleInfoZ@Base 6
+ _D2rt6memory16initStaticDataGCFZv@Base 6
+ _D2rt7aApplyR12__ModuleInfoZ@Base 6
+ _D2rt7switch_12__ModuleInfoZ@Base 6
+ _D2rt8arraycat12__ModuleInfoZ@Base 6
+ _D2rt8lifetime10__arrayPadFNaNbNemxC8TypeInfoZm@Base 6
+ _D2rt8lifetime10__blkcacheFNbNdZPS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime11hasPostblitFxC8TypeInfoZb@Base 6
+ _D2rt8lifetime11newCapacityFmmZm@Base 6
+ _D2rt8lifetime12__ModuleInfoZ@Base 6
+ _D2rt8lifetime12__arrayAllocFNaNbmxC8TypeInfoxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__arrayAllocFmKS4core6memory8BlkInfo_xC8TypeInfoxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__arrayStartFNaNbS4core6memory8BlkInfo_ZPv@Base 6
+ _D2rt8lifetime12__doPostblitFPvmxC8TypeInfoZv@Base 6
+ _D2rt8lifetime12__getBlkInfoFNbPvZPS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__nextBlkIdxi@Base 6
+ _D2rt8lifetime12_staticDtor1FZv@Base 6
+ _D2rt8lifetime14collectHandlerPFC6ObjectZb@Base 6
+ _D2rt8lifetime14finalize_arrayFPvmxC15TypeInfo_StructZv@Base 6
+ _D2rt8lifetime14processGCMarksFNbPS4core6memory8BlkInfo_MDFNbPvZiZv@Base 6
+ _D2rt8lifetime15finalize_array2FNbPvmZv@Base 6
+ _D2rt8lifetime15finalize_structFNbPvmZv@Base 6
+ _D2rt8lifetime18__arrayAllocLengthFNaNbKS4core6memory8BlkInfo_xC8TypeInfoZm@Base 6
+ _D2rt8lifetime18__blkcache_storagePS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime18structTypeInfoSizeFNaNbNixC8TypeInfoZm@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock6__initZ@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock6__vtblZ@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock7__ClassZ@Base 6
+ _D2rt8lifetime20__insertBlkInfoCacheFNbS4core6memory8BlkInfo_PS4core6memory8BlkInfo_Zv@Base 6
+ _D2rt8lifetime21__setArrayAllocLengthFNaNbKS4core6memory8BlkInfo_mbxC8TypeInfomZb@Base 6
+ _D2rt8lifetime23callStructDtorsDuringGCyb@Base 6
+ _D2rt8lifetime26hasArrayFinalizerInSegmentFNbPvmxAvZi@Base 6
+ _D2rt8lifetime27hasStructFinalizerInSegmentFNbPvmxAvZi@Base 6
+ _D2rt8lifetime35__T14_d_newarrayOpTS12_d_newarrayTZ14_d_newarrayOpTFNaNbxC8TypeInfoAmZAv@Base 6
+ _D2rt8lifetime36__T14_d_newarrayOpTS13_d_newarrayiTZ14_d_newarrayOpTFNaNbxC8TypeInfoAmZAv@Base 6
+ _D2rt8lifetime5Array6__initZ@Base 6
+ _D2rt8lifetime9unqualifyFNaNbNiNgC8TypeInfoZNgC8TypeInfo@Base 6
+ _D2rt8monitor_10getMonitorFNaNbC6ObjectZPOS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_10setMonitorFNaNbC6ObjectPOS2rt8monitor_7MonitorZv@Base 6
+ _D2rt8monitor_11unlockMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_12__ModuleInfoZ@Base 6
+ _D2rt8monitor_12destroyMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_12disposeEventFNbPS2rt8monitor_7MonitorC6ObjectZv@Base 6
+ _D2rt8monitor_13deleteMonitorFNbPS2rt8monitor_7MonitorZv@Base 6
+ _D2rt8monitor_13ensureMonitorFNbC6ObjectZPOS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_4gmtxS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D2rt8monitor_5gattrS4core3sys5posix3sys5types19pthread_mutexattr_t@Base 6
+ _D2rt8monitor_7Monitor11__xopEqualsFKxS2rt8monitor_7MonitorKxS2rt8monitor_7MonitorZb@Base 6
+ _D2rt8monitor_7Monitor6__initZ@Base 6
+ _D2rt8monitor_7Monitor9__xtoHashFNbNeKxS2rt8monitor_7MonitorZm@Base 6
+ _D2rt8monitor_7monitorFNaNbNcNdC6ObjectZOPS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_9initMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_9lockMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8sections12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Acfloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ap4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ap8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Adouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4initMxFNaNbNeZ1ryr@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r6talignMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r8argTypesMFNaNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_cdouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_idouble10TypeInfo_p8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_idouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo11ti_Acdouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo11ti_delegate12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C6equalsMxFNexPvxPvZb@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C7compareMxFNexPvxPvZi@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo4ti_C12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_AC12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ab4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ab8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Av4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Av8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Axa4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Axa8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Aya4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Aya8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo6ti_int12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo6ti_ptr12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Aw4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Aw8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_byte12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_cent12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4initMxFNaNbNeZ1cya@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_char12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l6talignMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_long12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4initMxFNaNbNeZ1rye@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e6talignMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_real12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_uint12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_void12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Along12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Aj4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Aj8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Areal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4initMxFNaNbNeZ1ryc@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c6talignMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c8argTypesMFNaNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_creal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4initMxFNaNbNeZ1cyw@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_dchar12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4initMxFNaNbNeZ1ryf@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f5flagsMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_float12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ireal10TypeInfo_j8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ireal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_short12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_b8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ubyte12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ucent12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m6talignMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ulong12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4initMxFNaNbNeZ1cyu@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u8toStringMxFNaNbNeZAya@Base 6
+ _D2rt8typeinfo8ti_wchar12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Acreal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Ao4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Ao8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Afloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As7getHashMxFNbNexPvZm@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_Au4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_Au8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4initMxFNaNbNeZ1ryq@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q6talignMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q8argTypesMFNaNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_cfloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4initMxFNaNbNeZ1ryd@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d5flagsMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d6talignMxFNaNbNdNiNfZm@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_double12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_ifloat10TypeInfo_o8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_ifloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t5tsizeMxFNaNbNdNiNeZm@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t7getHashMxFNaNbNexPvZm@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_ushort12__ModuleInfoZ@Base 6
+ _D2rt9arraycast12__ModuleInfoZ@Base 6
+ _D2rt9critical_11ensureMutexFNbPOS2rt9critical_18D_CRITICAL_SECTIONZv@Base 6
+ _D2rt9critical_12__ModuleInfoZ@Base 6
+ _D2rt9critical_18D_CRITICAL_SECTION6__initZ@Base 6
+ _D2rt9critical_3gcsOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D2rt9critical_4headOPS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D30TypeInfo_AC4core6thread6Thread6__initZ@Base 6
+ _D30TypeInfo_AyS3gcc3deh9FuncTable6__initZ@Base 6
+ _D30TypeInfo_E4core4time9ClockType6__initZ@Base 6
+ _D30TypeInfo_S2rt8monitor_7Monitor6__initZ@Base 6
+ _D30TypeInfo_yS6object10ModuleInfo6__initZ@Base 6
+ _D31TypeInfo_E4core6thread8IsMarked6__initZ@Base 6
+ _D31TypeInfo_E4core6thread8ScanType6__initZ@Base 6
+ _D31TypeInfo_PyS6object10ModuleInfo6__initZ@Base 6
+ _D31TypeInfo_S4core5cpuid9CacheInfo6__initZ@Base 6
+ _D31TypeInfo_S4core6memory8BlkInfo_6__initZ@Base 6
+ _D31TypeInfo_S4core7runtime7Runtime6__initZ@Base 6
+ _D31TypeInfo_xAyS3gcc3deh9FuncTable6__initZ@Base 6
+ _D31TypeInfo_yPS6object10ModuleInfo6__initZ@Base 6
+ _D32TypeInfo_AyPS6object10ModuleInfo6__initZ@Base 6
+ _D32TypeInfo_C6object6Object7Monitor6__initZ@Base 6
+ _D32TypeInfo_S2rt4util6random6Rand486__initZ@Base 6
+ _D32TypeInfo_S2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D32TypeInfo_S4core4stdc4fenv6fenv_t6__initZ@Base 6
+ _D32TypeInfo_S6object13__va_list_tag6__initZ@Base 6
+ _D32TypeInfo_xPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_AxPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_E4core6memory2GC7BlkAttr6__initZ@Base 6
+ _D33TypeInfo_E4core6thread5Fiber4Call6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc15LargeObjectPool6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc15SmallObjectPool6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc5stdio6fpos_t6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc6locale5lconv6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc6stdlib5div_t6__initZ@Base 6
+ _D33TypeInfo_S4core8demangle8Demangle6__initZ@Base 6
+ _D33TypeInfo_S6object14OffsetTypeInfo6__initZ@Base 6
+ _D33TypeInfo_xAPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_xAyPS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_xC6object6Object7Monitor6__initZ@Base 6
+ _D33TypeInfo_xS2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D34TypeInfo_E3gcc6config11ThreadModel6__initZ@Base 6
+ _D34TypeInfo_E4core6thread5Fiber5State6__initZ@Base 6
+ _D34TypeInfo_E4core6thread6Thread4Call6__initZ@Base 6
+ _D34TypeInfo_S4core4stdc6stdlib6ldiv_t6__initZ@Base 6
+ _D34TypeInfo_S4core4time12TickDuration6__initZ@Base 6
+ _D34TypeInfo_xS2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D35TypeInfo_E4core6atomic11MemoryOrder6__initZ@Base 6
+ _D35TypeInfo_S4core3sys5posix3grp5group6__initZ@Base 6
+ _D35TypeInfo_S4core4stdc5stdio8_IO_FILE6__initZ@Base 6
+ _D35TypeInfo_S4core4stdc6stdlib7lldiv_t6__initZ@Base 6
+ _D36TypeInfo_E4core6thread5Fiber7Rethrow6__initZ@Base 6
+ _D36TypeInfo_S3gcc3deh16globalExceptions6__initZ@Base 6
+ _D36TypeInfo_S3gcc3deh16lsda_header_info6__initZ@Base 6
+ _D36TypeInfo_S3gcc9backtrace10SymbolInfo6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix3pwd6passwd6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D37TypeInfo_C6object9Throwable9TraceInfo6__initZ@Base 6
+ _D37TypeInfo_S4core3sys5posix4poll6pollfd6__initZ@Base 6
+ _D37TypeInfo_S4core3sys5posix5fcntl5flock6__initZ@Base 6
+ _D37TypeInfo_S4core4stdc6stdarg9__va_list6__initZ@Base 6
+ _D37TypeInfo_S4core4stdc6wchar_9mbstate_t6__initZ@Base 6
+ _D37TypeInfo_S4core6thread6Thread7Context6__initZ@Base 6
+ _D38TypeInfo_S2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D38TypeInfo_S3gcc3deh18d_exception_header6__initZ@Base 6
+ _D38TypeInfo_S4core3sys5linux4link7r_debug6__initZ@Base 6
+ _D38TypeInfo_S4core3sys5posix5netdb6netent6__initZ@Base 6
+ _D38TypeInfo_S4core8internal7convert5Float6__initZ@Base 6
+ _D39TypeInfo_S3gcc9backtrace13SymbolOrError6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Dyn6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Lib6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Rel6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Sym6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Dyn6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Lib6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Rel6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Sym6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux4link8link_map6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux5dlfcn7Dl_info6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix3sys3uio5iovec6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5dlfcn7Dl_info6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5netdb7hostent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5netdb7servent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5utime7utimbuf6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix6dirent6dirent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix6signal6sigval6__initZ@Base 6
+ _D39TypeInfo_S4core4stdc8inttypes9imaxdiv_t6__initZ@Base 6
+ _D39TypeInfo_xS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D39TypeInfo_xS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D3etc5linux11memoryerror12__ModuleInfoZ@Base 6
+ _D3gcc12libbacktrace12__ModuleInfoZ@Base 6
+ _D3gcc12libbacktrace15backtrace_state6__initZ@Base 6
+ _D3gcc3deh12__ModuleInfoZ@Base 6
+ _D3gcc3deh15__gdc_terminateFZv@Base 6
+ _D3gcc3deh16globalExceptions6__initZ@Base 6
+ _D3gcc3deh16lsda_header_info6__initZ@Base 6
+ _D3gcc3deh17parse_lsda_headerFPS3gcc6unwind7generic15_Unwind_ContextPhPS3gcc3deh16lsda_header_infoZPh@Base 6
+ _D3gcc3deh18__globalExceptionsS3gcc3deh16globalExceptions@Base 6
+ _D3gcc3deh18d_exception_header11__xopEqualsFKxS3gcc3deh18d_exception_headerKxS3gcc3deh18d_exception_headerZb@Base 6
+ _D3gcc3deh18d_exception_header6__initZ@Base 6
+ _D3gcc3deh18d_exception_header9__xtoHashFNbNeKxS3gcc3deh18d_exception_headerZm@Base 6
+ _D3gcc3deh19get_classinfo_entryFPS3gcc3deh16lsda_header_infomZC14TypeInfo_Class@Base 6
+ _D3gcc3deh21__gdc_exception_classxm@Base 6
+ _D3gcc3deh21save_caught_exceptionFPS3gcc6unwind7generic17_Unwind_ExceptionPS3gcc6unwind7generic15_Unwind_ContextiPhmPhZv@Base 6
+ _D3gcc3deh22__gdc_personality_implFiibPS3gcc6unwind7generic17_Unwind_ExceptionPS3gcc6unwind7generic15_Unwind_ContextZk@Base 6
+ _D3gcc3deh24restore_caught_exceptionFPS3gcc6unwind7generic17_Unwind_ExceptionKiKPhKmZv@Base 6
+ _D3gcc3deh28get_exception_header_from_ueFPS3gcc6unwind7generic17_Unwind_ExceptionZPS3gcc3deh18d_exception_header@Base 6
+ _D3gcc3deh9FuncTable6__initZ@Base 6
+ _D3gcc6config12__ModuleInfoZ@Base 6
+ _D3gcc6unwind12__ModuleInfoZ@Base 6
+ _D3gcc6unwind2pe12__ModuleInfoZ@Base 6
+ _D3gcc6unwind2pe12read_sleb128FPhPlZPh@Base 6
+ _D3gcc6unwind2pe12read_uleb128FPhPmZPh@Base 6
+ _D3gcc6unwind2pe18read_encoded_valueFPS3gcc6unwind7generic15_Unwind_ContexthPhPmZPh@Base 6
+ _D3gcc6unwind2pe21base_of_encoded_valueFhPS3gcc6unwind7generic15_Unwind_ContextZm@Base 6
+ _D3gcc6unwind2pe21size_of_encoded_valueFhZk@Base 6
+ _D3gcc6unwind2pe28read_encoded_value_with_baseFhmPhPmZ9unaligned6__initZ@Base 6
+ _D3gcc6unwind2pe28read_encoded_value_with_baseFhmPhPmZPh@Base 6
+ _D3gcc6unwind3arm12__ModuleInfoZ@Base 6
+ _D3gcc6unwind7generic12__ModuleInfoZ@Base 6
+ _D3gcc6unwind7generic17_Unwind_Exception6__initZ@Base 6
+ _D3gcc7atomics12__ModuleInfoZ@Base 6
+ _D3gcc8builtins12__ModuleInfoZ@Base 6
+ _D3gcc8builtins13__va_list_tag6__initZ@Base 6
+ _D3gcc9attribute12__ModuleInfoZ@Base 6
+ _D3gcc9backtrace10SymbolInfo6__initZ@Base 6
+ _D3gcc9backtrace10formatLineFxS3gcc9backtrace10SymbolInfoKG512aZAa@Base 6
+ _D3gcc9backtrace12LibBacktrace11initializedb@Base 6
+ _D3gcc9backtrace12LibBacktrace16initLibBacktraceFZv@Base 6
+ _D3gcc9backtrace12LibBacktrace5statePS3gcc12libbacktrace15backtrace_state@Base 6
+ _D3gcc9backtrace12LibBacktrace6__ctorMFiZC3gcc9backtrace12LibBacktrace@Base 6
+ _D3gcc9backtrace12LibBacktrace6__initZ@Base 6
+ _D3gcc9backtrace12LibBacktrace6__vtblZ@Base 6
+ _D3gcc9backtrace12LibBacktrace7__ClassZ@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFDFKmKS3gcc9backtrace13SymbolOrErrorZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKmKxAaZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKxAaZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace8toStringMxFZAya@Base 6
+ _D3gcc9backtrace12__ModuleInfoZ@Base 6
+ _D3gcc9backtrace13SymbolOrError6__initZ@Base 6
+ _D3gcc9backtrace18SymbolCallbackInfo5resetMFZv@Base 6
+ _D3gcc9backtrace18SymbolCallbackInfo6__initZ@Base 6
+ _D3gcc9backtrace19SymbolCallbackInfo26__initZ@Base 6
+ _D40TypeInfo_PxS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D40TypeInfo_PxS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5linux4tipc9tipc_name6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix3sys3msg6msgbuf6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix5netdb8addrinfo6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix5netdb8protoent6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix6signal7stack_t6__initZ@Base 6
+ _D40TypeInfo_xPS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D40TypeInfo_xPS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D41TypeInfo_E4core8demangle8Demangle7AddType6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Ehdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Move6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Nhdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Phdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Rela6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Shdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Ehdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Move6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Nhdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Phdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Rela6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Shdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys3msg7msginfo6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigevent6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigset_t6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigstack6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8timespec6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix7termios7termios6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix9semaphore5sem_t6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux3elf11Elf32_gptab6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux3elf11Elf_Options6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux4tipc10tipc_event6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3ipc8ipc_perm6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3msg8msqid_ds6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3shm8shmid_ds6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys4time7timeval6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys5ioctl6termio6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix4time10itimerspec6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix6signal9siginfo_t6__initZ@Base 6
+ _D42TypeInfo_xE4core8demangle8Demangle7AddType6__initZ@Base 6
+ _D43TypeInfo_E4core3sys5posix3sys4wait8idtype_t6__initZ@Base 6
+ _D43TypeInfo_E4core3sys5posix3sys7statvfs5FFlag6__initZ@Base 6
+ _D43TypeInfo_S2rt9critical_18D_CRITICAL_SECTION6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf32_Verdef6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf32_auxv_t6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf64_Verdef6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf64_auxv_t6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux4tipc11tipc_portid6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux4tipc11tipc_subscr6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux5dlfcn10Dl_serinfo6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux5dlfcn10Dl_serpath6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys5ioctl7winsize6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6select6fd_set6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6socket6linger6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6socket6msghdr6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix4arpa4inet7in_addr6__initZ@Base 6
+ _D44TypeInfo_S2rt19sections_elf_shared9ThreadDSO6__initZ@Base 6
+ _D44TypeInfo_S2rt19sections_elf_shared9tls_index6__initZ@Base 6
+ _D44TypeInfo_S3gcc9backtrace18SymbolCallbackInfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_RegInfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Syminfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Verdaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Vernaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Verneed6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Syminfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Verdaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Vernaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Verneed6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux4link12dl_phdr_info6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux5epoll11epoll_event6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys4time9itimerval6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys5ioctl8termios26__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys6socket7cmsghdr6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix5sched11sched_param6__initZ@Base 6
+ _D45TypeInfo_E4core8demangle8Demangle10IsDelegate6__initZ@Base 6
+ _D45TypeInfo_E4core8internal7convert11FloatFormat6__initZ@Base 6
+ _D45TypeInfo_E6object14TypeInfo_Class10ClassFlags6__initZ@Base 6
+ _D45TypeInfo_S3gcc12libbacktrace15backtrace_state6__initZ@Base 6
+ _D45TypeInfo_S3gcc9backtrace19SymbolCallbackInfo26__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf14Elf_Options_Hw6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf9Elf32_Dyn5_d_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf9Elf64_Dyn5_d_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux4tipc13tipc_name_seq6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux5epoll12epoll_data_t6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys2un11sockaddr_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys6socket8sockaddr6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys7utsname7utsname6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys8resource6rlimit6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys8resource6rusage6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix6signal11sigaction_t6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5linux3sys7sysinfo8sysinfo_6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix7netinet3in_8in6_addr6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix8ucontext10mcontext_t6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix8ucontext10ucontext_t6__initZ@Base 6
+ _D46TypeInfo_S4core4stdc6wchar_9mbstate_t8___value6__initZ@Base 6
+ _D46TypeInfo_S4core4sync5mutex5Mutex12MonitorProxy6__initZ@Base 6
+ _D47TypeInfo_E6object15TypeInfo_Struct11StructFlags6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix3sys7statvfs9statvfs_t6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix6setjmp13__jmp_buf_tag6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix7netinet3in_9ipv6_mreq6__initZ@Base 6
+ _D48TypeInfo_S3gcc6unwind7generic17_Unwind_Exception6__initZ@Base 6
+ _D48TypeInfo_S4core3sys5posix8ucontext12_libc_fpxreg6__initZ@Base 6
+ _D48TypeInfo_S4core3sys5posix8ucontext12_libc_xmmreg6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5linux3elf12Elf32_auxv_t5_a_un6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5linux3elf12Elf64_auxv_t5_a_un6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5posix3net3if_14if_nameindex_t6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5posix8ucontext13_libc_fpstate6__initZ@Base 6
+ _D49TypeInfo_xS3gcc6unwind7generic17_Unwind_Exception6__initZ@Base 6
+ _D4core10checkedint12__ModuleInfoZ@Base 6
+ _D4core10checkedint4addsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4addsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4adduFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4adduFNaNbNiNfmmKbZm@Base 6
+ _D4core10checkedint4mulsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4mulsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4muluFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4muluFNaNbNiNfmmKbZm@Base 6
+ _D4core10checkedint4negsFNaNbNiNfiKbZi@Base 6
+ _D4core10checkedint4negsFNaNbNiNflKbZl@Base 6
+ _D4core10checkedint4subsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4subsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4subuFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4subuFNaNbNiNfmmKbZm@Base 6
+ _D4core3sys5linux3elf10Elf32_Ehdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Move6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Nhdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Phdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Rela6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Shdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Ehdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Move6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Nhdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Phdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Rela6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Shdr6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab10_gt_header6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab9_gt_entry6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf_Options6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_Verdef6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_auxv_t5_a_un6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_auxv_t6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_Verdef6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_auxv_t5_a_un6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_auxv_t6__initZ@Base 6
+ _D4core3sys5linux3elf12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3elf13Elf32_RegInfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Syminfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Verdaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Vernaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Verneed6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Syminfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Verdaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Vernaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Verneed6__initZ@Base 6
+ _D4core3sys5linux3elf14Elf_Options_Hw6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Dyn5_d_un6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Dyn6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Lib6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Rel6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Sym6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Dyn5_d_un6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Dyn6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Lib6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Rel6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Sym6__initZ@Base 6
+ _D4core3sys5linux3sys4mman12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys5xattr12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7inotify12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7inotify13inotify_event6__initZ@Base 6
+ _D4core3sys5linux3sys7sysinfo12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7sysinfo8sysinfo_6__initZ@Base 6
+ _D4core3sys5linux3sys8signalfd12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys8signalfd16signalfd_siginfo6__initZ@Base 6
+ _D4core3sys5linux4link12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4link12dl_phdr_info6__initZ@Base 6
+ _D4core3sys5linux4link7r_debug6__initZ@Base 6
+ _D4core3sys5linux4link8link_map6__initZ@Base 6
+ _D4core3sys5linux4time12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4tipc10tipc_event6__initZ@Base 6
+ _D4core3sys5linux4tipc11tipc_portid6__initZ@Base 6
+ _D4core3sys5linux4tipc11tipc_subscr6__initZ@Base 6
+ _D4core3sys5linux4tipc12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc4Addr4Name6__initZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc4Addr6__initZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc6__initZ@Base 6
+ _D4core3sys5linux4tipc13tipc_name_seq6__initZ@Base 6
+ _D4core3sys5linux4tipc9tipc_name6__initZ@Base 6
+ _D4core3sys5linux5dlfcn10Dl_serinfo6__initZ@Base 6
+ _D4core3sys5linux5dlfcn10Dl_serpath6__initZ@Base 6
+ _D4core3sys5linux5dlfcn12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5dlfcn7Dl_info6__initZ@Base 6
+ _D4core3sys5linux5epoll11epoll_event6__initZ@Base 6
+ _D4core3sys5linux5epoll12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5epoll12epoll_data_t6__initZ@Base 6
+ _D4core3sys5linux5errno12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5stdio12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5stdio21cookie_io_functions_t6__initZ@Base 6
+ _D4core3sys5linux6config12__ModuleInfoZ@Base 6
+ _D4core3sys5linux7termios12__ModuleInfoZ@Base 6
+ _D4core3sys5linux8execinfo12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3grp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3grp5group6__initZ@Base 6
+ _D4core3sys5posix3net3if_12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3net3if_14if_nameindex_t6__initZ@Base 6
+ _D4core3sys5posix3pwd12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3pwd6passwd6__initZ@Base 6
+ _D4core3sys5posix3sys2un11sockaddr_un6__initZ@Base 6
+ _D4core3sys5posix3sys2un12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3ipc12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3ipc8ipc_perm6__initZ@Base 6
+ _D4core3sys5posix3sys3msg12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3msg6msgbuf6__initZ@Base 6
+ _D4core3sys5posix3sys3msg7msginfo6__initZ@Base 6
+ _D4core3sys5posix3sys3msg8msqid_ds6__initZ@Base 6
+ _D4core3sys5posix3sys3shm12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3shm8shmid_ds6__initZ@Base 6
+ _D4core3sys5posix3sys3uio12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3uio5iovec6__initZ@Base 6
+ _D4core3sys5posix3sys4mman12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4stat12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D4core3sys5posix3sys4stat7S_ISBLKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISCHRFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISDIRFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISLNKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISREGFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISFIFOFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISSOCKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISTYPEFNbNikkZb@Base 6
+ _D4core3sys5posix3sys4time12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4time7timeval6__initZ@Base 6
+ _D4core3sys5posix3sys4time9itimerval6__initZ@Base 6
+ _D4core3sys5posix3sys4wait10WIFSTOPPEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys4wait10__WTERMSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait11WEXITSTATUSFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait11WIFSIGNALEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys4wait12WIFCONTINUEDFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4wait8WSTOPSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait8WTERMSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait9WIFEXITEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTiZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTkZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTnZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IORTkZ4_IORFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOWTiZ4_IOWFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys5ioctl3_IOFNbNiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IOCTS4core3sys5posix3sys5ioctl8termios2Z4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IORTS4core3sys5posix3sys5ioctl8termios2Z4_IORFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IOWTS4core3sys5posix3sys5ioctl8termios2Z4_IOWFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl6termio6__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl7_IOC_NRFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl7winsize6__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl8_IOC_DIRFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl8termios26__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl9_IOC_SIZEFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl9_IOC_TYPEFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5types12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys5types14pthread_attr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types14pthread_cond_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types16pthread_rwlock_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types17_pthread_fastlock6__initZ@Base 6
+ _D4core3sys5posix3sys5types17pthread_barrier_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types18pthread_condattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types19pthread_mutexattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types20pthread_rwlockattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types21pthread_barrierattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys6select12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys6select6FD_CLRFNbNiiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select6FD_SETFNbNiiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select6fd_set6__initZ@Base 6
+ _D4core3sys5posix3sys6select7FD_ZEROFNbNiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select7__FDELTFNaNbNiNfiZk@Base 6
+ _D4core3sys5posix3sys6select8FD_ISSETFNbNiiPxS4core3sys5posix3sys6select6fd_setZb@Base 6
+ _D4core3sys5posix3sys6select8__FDMASKFNaNbNiNfiZl@Base 6
+ _D4core3sys5posix3sys6socket10CMSG_ALIGNFNaNbNimZm@Base 6
+ _D4core3sys5posix3sys6socket10CMSG_SPACEFNaNbNimZm@Base 6
+ _D4core3sys5posix3sys6socket11CMSG_NXTHDRFNaNbNiPNgS4core3sys5posix3sys6socket6msghdrPNgS4core3sys5posix3sys6socket7cmsghdrZPNgS4core3sys5posix3sys6socket7cmsghdr@Base 6
+ _D4core3sys5posix3sys6socket12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys6socket13CMSG_FIRSTHDRFNaNbNiPNgS4core3sys5posix3sys6socket6msghdrZPNgS4core3sys5posix3sys6socket7cmsghdr@Base 6
+ _D4core3sys5posix3sys6socket16sockaddr_storage6__initZ@Base 6
+ _D4core3sys5posix3sys6socket6linger6__initZ@Base 6
+ _D4core3sys5posix3sys6socket6msghdr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket7cmsghdr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket8CMSG_LENFNaNbNimZm@Base 6
+ _D4core3sys5posix3sys6socket8sockaddr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket9CMSG_DATAFNaNbNiPNgS4core3sys5posix3sys6socket7cmsghdrZPNgh@Base 6
+ _D4core3sys5posix3sys7statvfs12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys7statvfs5FFlag6__initZ@Base 6
+ _D4core3sys5posix3sys7statvfs9statvfs_t6__initZ@Base 6
+ _D4core3sys5posix3sys7utsname12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys7utsname7utsname6__initZ@Base 6
+ _D4core3sys5posix3sys8resource12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys8resource6rlimit6__initZ@Base 6
+ _D4core3sys5posix3sys8resource6rusage6__initZ@Base 6
+ _D4core3sys5posix4arpa4inet12__ModuleInfoZ@Base 6
+ _D4core3sys5posix4arpa4inet7in_addr6__initZ@Base 6
+ _D4core3sys5posix4poll12__ModuleInfoZ@Base 6
+ _D4core3sys5posix4poll6pollfd6__initZ@Base 6
+ _D4core3sys5posix4time10itimerspec6__initZ@Base 6
+ _D4core3sys5posix4time12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5dlfcn12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5dlfcn7Dl_info6__initZ@Base 6
+ _D4core3sys5posix5fcntl12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5fcntl5flock6__initZ@Base 6
+ _D4core3sys5posix5netdb12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5netdb6netent6__initZ@Base 6
+ _D4core3sys5posix5netdb7hostent6__initZ@Base 6
+ _D4core3sys5posix5netdb7hostent6h_addrMUNdZPa@Base 6
+ _D4core3sys5posix5netdb7servent6__initZ@Base 6
+ _D4core3sys5posix5netdb8addrinfo6__initZ@Base 6
+ _D4core3sys5posix5netdb8protoent6__initZ@Base 6
+ _D4core3sys5posix5sched11sched_param6__initZ@Base 6
+ _D4core3sys5posix5sched12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5stdio12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5utime12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5utime7utimbuf6__initZ@Base 6
+ _D4core3sys5posix6config12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6dirent12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D4core3sys5posix6dirent6dirent6__initZ@Base 6
+ _D4core3sys5posix6setjmp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6setjmp13__jmp_buf_tag6__initZ@Base 6
+ _D4core3sys5posix6signal11sigaction_t6__initZ@Base 6
+ _D4core3sys5posix6signal12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6signal6sigval6__initZ@Base 6
+ _D4core3sys5posix6signal7stack_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent11_sigev_un_t15_sigev_thread_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent11_sigev_un_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent6__initZ@Base 6
+ _D4core3sys5posix6signal8sigset_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigstack6__initZ@Base 6
+ _D4core3sys5posix6signal8timespec6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t10_sigpoll_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t11_sigchild_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t11_sigfault_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t5_rt_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t7_kill_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t8_timer_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t6si_pidMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6signal9siginfo_t6si_uidMUNbNcNdNiNjZk@Base 6
+ _D4core3sys5posix6signal9siginfo_t7si_addrMUNbNcNdNiNjZPv@Base 6
+ _D4core3sys5posix6signal9siginfo_t7si_bandMUNbNcNdNiNjZl@Base 6
+ _D4core3sys5posix6signal9siginfo_t8si_valueMUNbNcNdNiNjZS4core3sys5posix6signal6sigval@Base 6
+ _D4core3sys5posix6signal9siginfo_t9si_statusMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6stdlib12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6syslog12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6unistd12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7netinet3in_11sockaddr_in6__initZ@Base 6
+ _D4core3sys5posix7netinet3in_12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7netinet3in_12sockaddr_in66__initZ@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_LOOPBACKFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_V4COMPATFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_V4MAPPEDFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_LINKLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_MC_GLOBALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_MULTICASTFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_SITELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_23IN6_IS_ADDR_MC_ORGLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_23IN6_IS_ADDR_UNSPECIFIEDFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_LINKLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_NODELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_SITELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_8in6_addr6__initZ@Base 6
+ _D4core3sys5posix7netinet3in_9ipv6_mreq6__initZ@Base 6
+ _D4core3sys5posix7netinet3tcp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7pthread12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup6__initZ@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup8__T3popZ3popMFNbiZv@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup9__T4pushZ4pushMFNbPUNbPvZvPvZv@Base 6
+ _D4core3sys5posix7pthread23_pthread_cleanup_buffer6__initZ@Base 6
+ _D4core3sys5posix7termios12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7termios7termios6__initZ@Base 6
+ _D4core3sys5posix8inttypes12__ModuleInfoZ@Base 6
+ _D4core3sys5posix8ucontext10mcontext_t6__initZ@Base 6
+ _D4core3sys5posix8ucontext10ucontext_t6__initZ@Base 6
+ _D4core3sys5posix8ucontext12__ModuleInfoZ@Base 6
+ _D4core3sys5posix8ucontext12_libc_fpxreg6__initZ@Base 6
+ _D4core3sys5posix8ucontext12_libc_xmmreg6__initZ@Base 6
+ _D4core3sys5posix8ucontext13_libc_fpstate6__initZ@Base 6
+ _D4core3sys5posix9semaphore12__ModuleInfoZ@Base 6
+ _D4core3sys5posix9semaphore17_pthread_fastlock6__initZ@Base 6
+ _D4core3sys5posix9semaphore5sem_t6__initZ@Base 6
+ _D4core4math12__ModuleInfoZ@Base 6
+ _D4core4simd12__ModuleInfoZ@Base 6
+ _D4core4stdc4fenv12__ModuleInfoZ@Base 6
+ _D4core4stdc4fenv6fenv_t6__initZ@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNedZi@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNeeZi@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNefZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeddZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeeeZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeffZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeddZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeeeZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeffZi@Base 6
+ _D4core4stdc4math12__ModuleInfoZ@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeddZi@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeeeZi@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeffZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeddZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeeeZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeffZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNedZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNeeZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNefZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNedZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNeeZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNefZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeddZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeeeZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeffZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNedZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNeeZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNefZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNedZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNeeZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNefZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNedZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNeeZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNefZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeddZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeeeZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeffZi@Base 6
+ _D4core4stdc4time12__ModuleInfoZ@Base 6
+ _D4core4stdc4time2tm6__initZ@Base 6
+ _D4core4stdc5ctype12__ModuleInfoZ@Base 6
+ _D4core4stdc5errno12__ModuleInfoZ@Base 6
+ _D4core4stdc5errno5errnoFNbNdNiNeZi@Base 6
+ _D4core4stdc5errno5errnoFNbNdNiNeiZi@Base 6
+ _D4core4stdc5stdio12__ModuleInfoZ@Base 6
+ _D4core4stdc5stdio4getcFNbNiNePOS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D4core4stdc5stdio4putcFNbNiNeiPOS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D4core4stdc5stdio6fpos_t6__initZ@Base 6
+ _D4core4stdc5stdio7getcharFNbNiNeZi@Base 6
+ _D4core4stdc5stdio7putcharFNbNiNeiZi@Base 6
+ _D4core4stdc5stdio8_IO_FILE6__initZ@Base 6
+ _D4core4stdc6config12__ModuleInfoZ@Base 6
+ _D4core4stdc6float_12__ModuleInfoZ@Base 6
+ _D4core4stdc6limits12__ModuleInfoZ@Base 6
+ _D4core4stdc6locale12__ModuleInfoZ@Base 6
+ _D4core4stdc6locale5lconv6__initZ@Base 6
+ _D4core4stdc6signal12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdarg12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdarg9__va_list6__initZ@Base 6
+ _D4core4stdc6stddef12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdint12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdint14__T7_typifyTgZ7_typifyFNaNbNiNfgZg@Base 6
+ _D4core4stdc6stdint14__T7_typifyThZ7_typifyFNaNbNiNfhZh@Base 6
+ _D4core4stdc6stdint14__T7_typifyTiZ7_typifyFNaNbNiNfiZi@Base 6
+ _D4core4stdc6stdint14__T7_typifyTkZ7_typifyFNaNbNiNfkZk@Base 6
+ _D4core4stdc6stdint14__T7_typifyTlZ7_typifyFNaNbNiNflZl@Base 6
+ _D4core4stdc6stdint14__T7_typifyTmZ7_typifyFNaNbNiNfmZm@Base 6
+ _D4core4stdc6stdint14__T7_typifyTsZ7_typifyFNaNbNiNfsZs@Base 6
+ _D4core4stdc6stdint14__T7_typifyTtZ7_typifyFNaNbNiNftZt@Base 6
+ _D4core4stdc6stdlib12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdlib5div_t6__initZ@Base 6
+ _D4core4stdc6stdlib6ldiv_t6__initZ@Base 6
+ _D4core4stdc6stdlib7lldiv_t6__initZ@Base 6
+ _D4core4stdc6string12__ModuleInfoZ@Base 6
+ _D4core4stdc6tgmath12__ModuleInfoZ@Base 6
+ _D4core4stdc6wchar_12__ModuleInfoZ@Base 6
+ _D4core4stdc6wchar_5getwcFNbNiNePOS4core4stdc5stdio8_IO_FILEZw@Base 6
+ _D4core4stdc6wchar_5putwcFNbNiNewPOS4core4stdc5stdio8_IO_FILEZw@Base 6
+ _D4core4stdc6wchar_8getwcharFNbNiNeZw@Base 6
+ _D4core4stdc6wchar_8putwcharFNbNiNewZw@Base 6
+ _D4core4stdc6wchar_9mbstate_t6__initZ@Base 6
+ _D4core4stdc6wchar_9mbstate_t8___value6__initZ@Base 6
+ _D4core4stdc6wctype12__ModuleInfoZ@Base 6
+ _D4core4stdc7complex12__ModuleInfoZ@Base 6
+ _D4core4stdc8inttypes12__ModuleInfoZ@Base 6
+ _D4core4stdc8inttypes9imaxdiv_t6__initZ@Base 6
+ _D4core4sync5mutex12__ModuleInfoZ@Base 6
+ _D4core4sync5mutex5Mutex10handleAddrMFZPS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy11__xopEqualsFKxS4core4sync5mutex5Mutex12MonitorProxyKxS4core4sync5mutex5Mutex12MonitorProxyZb@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy6__initZ@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy9__xtoHashFNbNeKxS4core4sync5mutex5Mutex12MonitorProxyZm@Base 6
+ _D4core4sync5mutex5Mutex12lock_nothrowMFNbNiNeZv@Base 6
+ _D4core4sync5mutex5Mutex14unlock_nothrowMFNbNiNeZv@Base 6
+ _D4core4sync5mutex5Mutex4lockMFNeZv@Base 6
+ _D4core4sync5mutex5Mutex6__ctorMFNbNeC6ObjectZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync5mutex5Mutex6__ctorMFNbNeZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync5mutex5Mutex6__dtorMFZv@Base 6
+ _D4core4sync5mutex5Mutex6__initZ@Base 6
+ _D4core4sync5mutex5Mutex6__vtblZ@Base 6
+ _D4core4sync5mutex5Mutex6unlockMFNeZv@Base 6
+ _D4core4sync5mutex5Mutex7__ClassZ@Base 6
+ _D4core4sync5mutex5Mutex7tryLockMFZb@Base 6
+ _D4core4sync6config12__ModuleInfoZ@Base 6
+ _D4core4sync6config7mktspecFNbKS4core3sys5posix6signal8timespecS4core4time8DurationZv@Base 6
+ _D4core4sync6config7mktspecFNbKS4core3sys5posix6signal8timespecZv@Base 6
+ _D4core4sync6config7mvtspecFNbKS4core3sys5posix6signal8timespecS4core4time8DurationZv@Base 6
+ _D4core4sync7barrier12__ModuleInfoZ@Base 6
+ _D4core4sync7barrier7Barrier4waitMFZv@Base 6
+ _D4core4sync7barrier7Barrier6__ctorMFkZC4core4sync7barrier7Barrier@Base 6
+ _D4core4sync7barrier7Barrier6__initZ@Base 6
+ _D4core4sync7barrier7Barrier6__vtblZ@Base 6
+ _D4core4sync7barrier7Barrier7__ClassZ@Base 6
+ _D4core4sync7rwmutex12__ModuleInfoZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy11__xopEqualsFKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy9__xtoHashFNbNeKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyZm@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader17shouldQueueReaderMFNdZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader4lockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__ctorMFZC4core4sync7rwmutex14ReadWriteMutex6Reader@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6unlockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader7__ClassZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader7tryLockMFZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy11__xopEqualsFKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy9__xtoHashFNbNeKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyZm@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer17shouldQueueWriterMFNdZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer4lockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__ctorMFZC4core4sync7rwmutex14ReadWriteMutex6Writer@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6unlockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer7__ClassZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer7tryLockMFZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__ctorMFE4core4sync7rwmutex14ReadWriteMutex6PolicyZC4core4sync7rwmutex14ReadWriteMutex@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6policyMFNdZE4core4sync7rwmutex14ReadWriteMutex6Policy@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6readerMFNdZC4core4sync7rwmutex14ReadWriteMutex6Reader@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6writerMFNdZC4core4sync7rwmutex14ReadWriteMutex6Writer@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex7__ClassZ@Base 6
+ _D4core4sync9condition12__ModuleInfoZ@Base 6
+ _D4core4sync9condition9Condition13mutex_nothrowMFNaNbNdNiNfZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync9condition9Condition4waitMFS4core4time8DurationZb@Base 6
+ _D4core4sync9condition9Condition4waitMFZv@Base 6
+ _D4core4sync9condition9Condition5mutexMFNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync9condition9Condition6__ctorMFNbNfC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D4core4sync9condition9Condition6__dtorMFZv@Base 6
+ _D4core4sync9condition9Condition6__initZ@Base 6
+ _D4core4sync9condition9Condition6__vtblZ@Base 6
+ _D4core4sync9condition9Condition6notifyMFZv@Base 6
+ _D4core4sync9condition9Condition7__ClassZ@Base 6
+ _D4core4sync9condition9Condition9notifyAllMFZv@Base 6
+ _D4core4sync9exception12__ModuleInfoZ@Base 6
+ _D4core4sync9exception9SyncError6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC4core4sync9exception9SyncError@Base 6
+ _D4core4sync9exception9SyncError6__ctorMFNaNbNfAyaC6object9ThrowableAyamZC4core4sync9exception9SyncError@Base 6
+ _D4core4sync9exception9SyncError6__initZ@Base 6
+ _D4core4sync9exception9SyncError6__vtblZ@Base 6
+ _D4core4sync9exception9SyncError7__ClassZ@Base 6
+ _D4core4sync9semaphore12__ModuleInfoZ@Base 6
+ _D4core4sync9semaphore9Semaphore4waitMFS4core4time8DurationZb@Base 6
+ _D4core4sync9semaphore9Semaphore4waitMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore6__ctorMFkZC4core4sync9semaphore9Semaphore@Base 6
+ _D4core4sync9semaphore9Semaphore6__dtorMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore6__initZ@Base 6
+ _D4core4sync9semaphore9Semaphore6__vtblZ@Base 6
+ _D4core4sync9semaphore9Semaphore6notifyMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore7__ClassZ@Base 6
+ _D4core4sync9semaphore9Semaphore7tryWaitMFZb@Base 6
+ _D4core4time11_posixClockFNaNbNiNfE4core4time9ClockTypeZi@Base 6
+ _D4core4time11numToStringFNaNbNflZAya@Base 6
+ _D4core4time12TickDuration11ticksPerSecyl@Base 6
+ _D4core4time12TickDuration14currSystemTickFNbNdNiNeZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration19_sharedStaticCtor55FNeZv@Base 6
+ _D4core4time12TickDuration3maxFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration3minFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration4zeroFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration5msecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration5nsecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration5opCmpMxFNaNbNiNfS4core4time12TickDurationZi@Base 6
+ _D4core4time12TickDuration5usecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration6__ctorMFNaNbNcNiNflZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration6__initZ@Base 6
+ _D4core4time12TickDuration6hnsecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration7secondsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration8__xopCmpFKxS4core4time12TickDurationKxS4core4time12TickDurationZi@Base 6
+ _D4core4time12TickDuration9appOriginyS4core4time12TickDuration@Base 6
+ _D4core4time12__ModuleInfoZ@Base 6
+ _D4core4time12nsecsToTicksFNaNbNiNflZl@Base 6
+ _D4core4time12ticksToNSecsFNaNbNiNflZl@Base 6
+ _D4core4time13TimeException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC4core4time13TimeException@Base 6
+ _D4core4time13TimeException6__ctorMFNaNbNfAyaC6object9ThrowableAyamZC4core4time13TimeException@Base 6
+ _D4core4time13TimeException6__initZ@Base 6
+ _D4core4time13TimeException6__vtblZ@Base 6
+ _D4core4time13TimeException7__ClassZ@Base 6
+ _D4core4time13_clockTypeIdxFE4core4time9ClockTypeZm@Base 6
+ _D4core4time13convClockFreqFNaNbNiNflllZl@Base 6
+ _D4core4time14_clockTypeNameFE4core4time9ClockTypeZAya@Base 6
+ _D4core4time15_ticksPerSecondyG8l@Base 6
+ _D4core4time23__T3durVAyaa4_64617973Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_686f757273Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_6d73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_6e73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_7573656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_7765656b73Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25unitsAreInDescendingOrderFAAyaXb@Base 6
+ _D4core4time27__T3durVAyaa6_686e73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time29__T3durVAyaa7_6d696e75746573Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time29__T3durVAyaa7_7365636f6e6473Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time39__T18getUnitsFromHNSecsVAyaa4_64617973Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time3absFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time3absFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_686f757273Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_6d73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_7573656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_7765656b73Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T20splitUnitsFromHNSecsVAyaa4_64617973Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl14ticksPerSecondFNaNbNdNiNfZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZS4core4time8Duration@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl3maxFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl3minFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl4zeroFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl5opCmpMxFNaNbNiNfS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZi@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl5ticksMxFNaNbNdNiNfZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl6__initZ@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8__xopCmpFKxS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplKxS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZi@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8currTimeFNbNdNiNeZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8toStringMxFNaNbNfZAya@Base 6
+ _D4core4time42__T21removeUnitsFromHNSecsVAyaa4_64617973Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_6d73656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7573656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7765656b73Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time44__T21removeUnitsFromHNSecsVAyaa5_686f757273Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time44__T21removeUnitsFromHNSecsVAyaa5_7765656b73Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_6d696e75746573Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa4_64617973VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa6_686e73656373VAyaa4_64617973Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time48__T21removeUnitsFromHNSecsVAyaa7_6d696e75746573Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time48__T21removeUnitsFromHNSecsVAyaa7_7365636f6e6473Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_686f757273VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_6d73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_6e73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7573656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7765656b73VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_686f757273Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7765656b73Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time4_absFNaNbNiNfdZd@Base 6
+ _D4core4time4_absFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa6_686e73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_6e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_6d696e75746573Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa7_6d696e75746573VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa7_7365636f6e6473VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time53__T2toVAyaa5_6d73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time53__T2toVAyaa5_6e73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time53__T2toVAyaa5_7573656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time54__T7convertVAyaa7_7365636f6e6473VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time55__T2toVAyaa6_686e73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time57__T2toVAyaa7_7365636f6e6473TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time7FracSec11__invariantMxFNaNfZv@Base 6
+ _D4core4time7FracSec13__invariant85MxFNaNfZv@Base 6
+ _D4core4time7FracSec13_enforceValidFNaNfiZv@Base 6
+ _D4core4time7FracSec13_toStringImplMxFNaNbNfZAya@Base 6
+ _D4core4time7FracSec28__T4fromVAyaa6_686e73656373Z4fromFNaNflZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec4zeroFNaNbNdNiNfZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec5msecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec5msecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec5nsecsMFNaNdNflZv@Base 6
+ _D4core4time7FracSec5nsecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec5usecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec5usecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec6__ctorMFNaNbNcNiNfiZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec6__initZ@Base 6
+ _D4core4time7FracSec6_validFNaNbNiNfiZb@Base 6
+ _D4core4time7FracSec6hnsecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec6hnsecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec8toStringMFNaNfZAya@Base 6
+ _D4core4time7FracSec8toStringMxFNaNbNfZAya@Base 6
+ _D4core4time8Duration10isNegativeMxFNaNbNdNiNfZb@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ10appListSepFNbNfKAyakbZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ31__T10appUnitValVAyaa4_64617973Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_686f757273Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_6d73656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_7573656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_7765656b73Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ35__T10appUnitValVAyaa6_686e73656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ37__T10appUnitValVAyaa7_6d696e75746573Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ37__T10appUnitValVAyaa7_7365636f6e6473Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZAya@Base 6
+ _D4core4time8Duration23__T3getVAyaa4_64617973Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration25__T10opOpAssignVAyaa1_2aZ10opOpAssignMFNaNbNcNiNflZS4core4time8Duration@Base 6
+ _D4core4time8Duration25__T3getVAyaa5_686f757273Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration25__T3getVAyaa5_7765656b73Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration27__T5totalVAyaa5_6d73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration29__T3getVAyaa7_6d696e75746573Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration29__T3getVAyaa7_7365636f6e6473Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration31__T5totalVAyaa7_7365636f6e6473Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration3maxFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration3minFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration43__T8opBinaryVAyaa1_2bTS4core4time8DurationZ8opBinaryMxFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration46__T10opOpAssignVAyaa1_2bTS4core4time8DurationZ10opOpAssignMFNaNbNcNiNfxS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration4daysMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration4zeroFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration5hoursMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration5opCmpMxFNaNbNiNfS4core4time8DurationZi@Base 6
+ _D4core4time8Duration5weeksMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration6__ctorMFNaNbNcNiNflZS4core4time8Duration@Base 6
+ _D4core4time8Duration6__initZ@Base 6
+ _D4core4time8Duration7fracSecMxFNaNbNdNfZS4core4time7FracSec@Base 6
+ _D4core4time8Duration7minutesMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration7secondsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration8__xopCmpFKxS4core4time8DurationKxS4core4time8DurationZi@Base 6
+ _D4core4time8Duration8toStringMFNaNfZAya@Base 6
+ _D4core4time8Duration8toStringMxFNaNbNfZAya@Base 6
+ _D4core5bitop12__ModuleInfoZ@Base 6
+ _D4core5bitop2btFNaNbNixPmmZi@Base 6
+ _D4core5bitop6popcntFNaNbNiNfkZi@Base 6
+ _D4core5bitop7bitswapFNaNbNiNekZk@Base 6
+ _D4core5cpuid10dataCachesFNbNdNiNeZxG5S4core5cpuid9CacheInfo@Base 6
+ _D4core5cpuid10maxThreadsk@Base 6
+ _D4core5cpuid11amd3dnowExtFNbNdNiNeZb@Base 6
+ _D4core5cpuid11amdfeaturesk@Base 6
+ _D4core5cpuid11cacheLevelsFNbNdNiNeZk@Base 6
+ _D4core5cpuid11coresPerCPUFNbNdNiNeZk@Base 6
+ _D4core5cpuid11extfeaturesk@Base 6
+ _D4core5cpuid11hasLahfSahfFNbNdNiNeZb@Base 6
+ _D4core5cpuid11probablyAMDb@Base 6
+ _D4core5cpuid12__ModuleInfoZ@Base 6
+ _D4core5cpuid12getCpuInfo0BFNbNiNeZv@Base 6
+ _D4core5cpuid12hasCmpxchg8bFNbNdNiNeZb@Base 6
+ _D4core5cpuid12hasPclmulqdqFNbNdNiNeZb@Base 6
+ _D4core5cpuid12miscfeaturesk@Base 6
+ _D4core5cpuid12preferAthlonFNbNdNiNeZb@Base 6
+ _D4core5cpuid13hasCmpxchg16bFNbNdNiNeZb@Base 6
+ _D4core5cpuid13hasVpclmulqdqFNbNdNiNeZb@Base 6
+ _D4core5cpuid13probablyIntelb@Base 6
+ _D4core5cpuid13processorNameAya@Base 6
+ _D4core5cpuid13threadsPerCPUFNbNdNiNeZk@Base 6
+ _D4core5cpuid14hyperThreadingFNbNdNiNeZb@Base 6
+ _D4core5cpuid14numCacheLevelsk@Base 6
+ _D4core5cpuid14preferPentium1FNbNdNiNeZb@Base 6
+ _D4core5cpuid14preferPentium4FNbNdNiNeZb@Base 6
+ _D4core5cpuid15amdmiscfeaturesk@Base 6
+ _D4core5cpuid15getAMDcacheinfoFNbNiNeZ8assocmapyAh@Base 6
+ _D4core5cpuid15getAMDcacheinfoFNbNiNeZv@Base 6
+ _D4core5cpuid16has3dnowPrefetchFNbNdNiNeZb@Base 6
+ _D4core5cpuid17hyperThreadingBitFNbNdNiNeZb@Base 6
+ _D4core5cpuid18_sharedStaticCtor1FNbNiNeZv@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZ14decipherCpuid2MFNbNihZ3idsyG63h@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZ14decipherCpuid2MFNbNihZ4waysyG63h@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZ14decipherCpuid2MFNbNihZ5sizesyG63k@Base 6
+ _D4core5cpuid18getcacheinfoCPUID2FNbNiNeZv@Base 6
+ _D4core5cpuid18getcacheinfoCPUID4FNbNiNeZv@Base 6
+ _D4core5cpuid18hasSysEnterSysExitFNbNdNiNeZb@Base 6
+ _D4core5cpuid18max_extended_cpuidk@Base 6
+ _D4core5cpuid19processorNameBufferG48a@Base 6
+ _D4core5cpuid3aesFNbNdNiNeZb@Base 6
+ _D4core5cpuid3avxFNbNdNiNeZb@Base 6
+ _D4core5cpuid3fmaFNbNdNiNeZb@Base 6
+ _D4core5cpuid3hleFNbNdNiNeZb@Base 6
+ _D4core5cpuid3mmxFNbNdNiNeZb@Base 6
+ _D4core5cpuid3rtmFNbNdNiNeZb@Base 6
+ _D4core5cpuid3sseFNbNdNiNeZb@Base 6
+ _D4core5cpuid4avx2FNbNdNiNeZb@Base 6
+ _D4core5cpuid4sse2FNbNdNiNeZb@Base 6
+ _D4core5cpuid4sse3FNbNdNiNeZb@Base 6
+ _D4core5cpuid4vaesFNbNdNiNeZb@Base 6
+ _D4core5cpuid5fp16cFNbNdNiNeZb@Base 6
+ _D4core5cpuid5modelk@Base 6
+ _D4core5cpuid5sse41FNbNdNiNeZb@Base 6
+ _D4core5cpuid5sse42FNbNdNiNeZb@Base 6
+ _D4core5cpuid5sse4aFNbNdNiNeZb@Base 6
+ _D4core5cpuid5ssse3FNbNdNiNeZb@Base 6
+ _D4core5cpuid6amdMmxFNbNdNiNeZb@Base 6
+ _D4core5cpuid6familyk@Base 6
+ _D4core5cpuid6hasShaFNbNdNiNeZb@Base 6
+ _D4core5cpuid6vendorFNbNdNiNeZAya@Base 6
+ _D4core5cpuid7hasCmovFNbNdNiNeZb@Base 6
+ _D4core5cpuid7hasFxsrFNbNdNiNeZb@Base 6
+ _D4core5cpuid8amd3dnowFNbNdNiNeZb@Base 6
+ _D4core5cpuid8cpuidX86FNbNiNeZv@Base 6
+ _D4core5cpuid8featuresk@Base 6
+ _D4core5cpuid8hasCPUIDFNbNiNeZb@Base 6
+ _D4core5cpuid8hasLzcntFNbNdNiNeZb@Base 6
+ _D4core5cpuid8hasRdtscFNbNdNiNeZb@Base 6
+ _D4core5cpuid8isX86_64FNbNdNiNeZb@Base 6
+ _D4core5cpuid8maxCoresk@Base 6
+ _D4core5cpuid8steppingk@Base 6
+ _D4core5cpuid8vendorIDG12a@Base 6
+ _D4core5cpuid9CacheInfo6__initZ@Base 6
+ _D4core5cpuid9datacacheG5S4core5cpuid9CacheInfo@Base 6
+ _D4core5cpuid9hasPopcntFNbNdNiNeZb@Base 6
+ _D4core5cpuid9hasRdrandFNbNdNiNeZb@Base 6
+ _D4core5cpuid9hasRdseedFNbNdNiNeZb@Base 6
+ _D4core5cpuid9isItaniumFNbNdNiNeZb@Base 6
+ _D4core5cpuid9max_cpuidk@Base 6
+ _D4core5cpuid9processorFNbNdNiNeZAya@Base 6
+ _D4core5cpuid9x87onChipFNbNdNiNeZb@Base 6
+ _D4core5cpuid9xfeaturesm@Base 6
+ _D4core6atomic11atomicFenceFNbNiZv@Base 6
+ _D4core6atomic120__T11atomicStoreVE4core6atomic11MemoryOrderi3TPOS2rt9critical_18D_CRITICAL_SECTIONTPOS2rt9critical_18D_CRITICAL_SECTIONZ11atomicStoreFNaNbNiKOPS2rt9critical_18D_CRITICAL_SECTIONPOS2rt9critical_18D_CRITICAL_SECTIONZv@Base 6
+ _D4core6atomic12__ModuleInfoZ@Base 6
+ _D4core6atomic14__T3casThThThZ3casFNaNbNiPOhxhxhZb@Base 6
+ _D4core6atomic14__T3casTmTmTmZ3casFNaNbNiPOmxmxmZb@Base 6
+ _D4core6atomic14__T3casTtTtTtZ3casFNaNbNiPOtxtxtZb@Base 6
+ _D4core6atomic20__T7casImplThTxhTxhZ7casImplFNaNbNiPOhxhxhZb@Base 6
+ _D4core6atomic20__T7casImplTmTxmTxmZ7casImplFNaNbNiPOmxmxmZb@Base 6
+ _D4core6atomic20__T7casImplTtTxtTxtZ7casImplFNaNbNiPOtxtxtZb@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2b3dTmTiZ8atomicOpFNaNbNiKOmiZm@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2b3dTmTmZ8atomicOpFNaNbNiKOmmZm@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2d3dTmTiZ8atomicOpFNaNbNiKOmiZm@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2d3dTmTmZ8atomicOpFNaNbNiKOmmZm@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi0TmZ10atomicLoadFNaNbNiKOxmZm@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5TbZ10atomicLoadFNaNbNiKOxbZb@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi0TbTbZ11atomicStoreFNaNbNiKObbZv@Base 6
+ _D4core6atomic69__T10atomicLoadVE4core6atomic11MemoryOrderi2TPOS2rt8monitor_7MonitorZ10atomicLoadFNaNbNiKOxPS2rt8monitor_7MonitorZPOS2rt8monitor_7Monitor@Base 6
+ _D4core6atomic82__T10atomicLoadVE4core6atomic11MemoryOrderi0TPOS2rt9critical_18D_CRITICAL_SECTIONZ10atomicLoadFNaNbNiKOxPS2rt9critical_18D_CRITICAL_SECTIONZPOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D4core6atomic82__T10atomicLoadVE4core6atomic11MemoryOrderi2TPOS2rt9critical_18D_CRITICAL_SECTIONZ10atomicLoadFNaNbNiKOxPS2rt9critical_18D_CRITICAL_SECTIONZPOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D4core6atomic94__T11atomicStoreVE4core6atomic11MemoryOrderi3TPOS2rt8monitor_7MonitorTPOS2rt8monitor_7MonitorZ11atomicStoreFNaNbNiKOPS2rt8monitor_7MonitorPOS2rt8monitor_7MonitorZv@Base 6
+ _D4core6memory12__ModuleInfoZ@Base 6
+ _D4core6memory2GC10removeRootFNbxPvZv@Base 6
+ _D4core6memory2GC11removeRangeFNbNixPvZv@Base 6
+ _D4core6memory2GC13runFinalizersFxAvZv@Base 6
+ _D4core6memory2GC4freeFNaNbPvZv@Base 6
+ _D4core6memory2GC5queryFNaNbPvZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC5queryFNbxPvZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC6__initZ@Base 6
+ _D4core6memory2GC6addrOfFNaNbPvZPv@Base 6
+ _D4core6memory2GC6addrOfFNbPNgvZPNgv@Base 6
+ _D4core6memory2GC6callocFNaNbmkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC6enableFNbZv@Base 6
+ _D4core6memory2GC6extendFNaNbPvmmxC8TypeInfoZm@Base 6
+ _D4core6memory2GC6mallocFNaNbmkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC6qallocFNaNbmkxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC6sizeOfFNaNbPvZm@Base 6
+ _D4core6memory2GC6sizeOfFNbxPvZm@Base 6
+ _D4core6memory2GC7addRootFNbxPvZv@Base 6
+ _D4core6memory2GC7clrAttrFNaNbPvkZk@Base 6
+ _D4core6memory2GC7clrAttrFNbxPvkZk@Base 6
+ _D4core6memory2GC7collectFNbZv@Base 6
+ _D4core6memory2GC7disableFNbZv@Base 6
+ _D4core6memory2GC7getAttrFNaNbPvZk@Base 6
+ _D4core6memory2GC7getAttrFNbxPvZk@Base 6
+ _D4core6memory2GC7reallocFNaNbPvmkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC7reserveFNbmZm@Base 6
+ _D4core6memory2GC7setAttrFNaNbPvkZk@Base 6
+ _D4core6memory2GC7setAttrFNbxPvkZk@Base 6
+ _D4core6memory2GC8addRangeFNbNixPvmxC8TypeInfoZv@Base 6
+ _D4core6memory2GC8minimizeFNbZv@Base 6
+ _D4core6memory8BlkInfo_6__initZ@Base 6
+ _D4core6thread11ThreadError6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC4core6thread11ThreadError@Base 6
+ _D4core6thread11ThreadError6__ctorMFNaNbNfAyaC6object9ThrowableAyamZC4core6thread11ThreadError@Base 6
+ _D4core6thread11ThreadError6__initZ@Base 6
+ _D4core6thread11ThreadError6__vtblZ@Base 6
+ _D4core6thread11ThreadError7__ClassZ@Base 6
+ _D4core6thread11ThreadGroup3addMFC4core6thread6ThreadZv@Base 6
+ _D4core6thread11ThreadGroup6__initZ@Base 6
+ _D4core6thread11ThreadGroup6__vtblZ@Base 6
+ _D4core6thread11ThreadGroup6createMFDFZvZC4core6thread6Thread@Base 6
+ _D4core6thread11ThreadGroup6createMFPFZvZC4core6thread6Thread@Base 6
+ _D4core6thread11ThreadGroup6removeMFC4core6thread6ThreadZv@Base 6
+ _D4core6thread11ThreadGroup7__ClassZ@Base 6
+ _D4core6thread11ThreadGroup7joinAllMFbZv@Base 6
+ _D4core6thread11ThreadGroup7opApplyMFMDFKC4core6thread6ThreadZiZi@Base 6
+ _D4core6thread11getStackTopFNbZPv@Base 6
+ _D4core6thread12__ModuleInfoZ@Base 6
+ _D4core6thread12suspendCountS4core3sys5posix9semaphore5sem_t@Base 6
+ _D4core6thread12suspendDepthk@Base 6
+ _D4core6thread13onThreadErrorFNbAyaC6object9ThrowableZ5errorC4core6thread11ThreadError@Base 6
+ _D4core6thread13onThreadErrorFNbAyaC6object9ThrowableZv@Base 6
+ _D4core6thread14getStackBottomFNbZPv@Base 6
+ _D4core6thread15ThreadException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC4core6thread15ThreadException@Base 6
+ _D4core6thread15ThreadException6__ctorMFNaNbNfAyaC6object9ThrowableAyamZC4core6thread15ThreadException@Base 6
+ _D4core6thread15ThreadException6__initZ@Base 6
+ _D4core6thread15ThreadException6__vtblZ@Base 6
+ _D4core6thread15ThreadException7__ClassZ@Base 6
+ _D4core6thread15scanAllTypeImplFNbMDFNbE4core6thread8ScanTypePvPvZvPvZv@Base 6
+ _D4core6thread17PTHREAD_STACK_MINym@Base 6
+ _D4core6thread17multiThreadedFlagb@Base 6
+ _D4core6thread17thread_entryPointUPvZ21thread_cleanupHandlerUNbPvZv@Base 6
+ _D4core6thread17thread_findByAddrFmZC4core6thread6Thread@Base 6
+ _D4core6thread18_sharedStaticDtor8FZv@Base 6
+ _D4core6thread18callWithStackShellFNbMDFNbPvZvZv@Base 6
+ _D4core6thread18resumeSignalNumberi@Base 6
+ _D4core6thread19_sharedStaticCtor18FZv@Base 6
+ _D4core6thread19suspendSignalNumberi@Base 6
+ _D4core6thread5Fiber10allocStackMFNbmZv@Base 6
+ _D4core6thread5Fiber13_staticCtor19FZv@Base 6
+ _D4core6thread5Fiber13yieldAndThrowFNbC6object9ThrowableZv@Base 6
+ _D4core6thread5Fiber39__T4callVE4core6thread5Fiber7Rethrowi0Z4callMFNbZC6object9Throwable@Base 6
+ _D4core6thread5Fiber39__T4callVE4core6thread5Fiber7Rethrowi1Z4callMFZC6object9Throwable@Base 6
+ _D4core6thread5Fiber3runMFZv@Base 6
+ _D4core6thread5Fiber4callMFE4core6thread5Fiber7RethrowZC6object9Throwable@Base 6
+ _D4core6thread5Fiber4callMFbZC6object9Throwable@Base 6
+ _D4core6thread5Fiber5resetMFNbDFZvZv@Base 6
+ _D4core6thread5Fiber5resetMFNbPFZvZv@Base 6
+ _D4core6thread5Fiber5resetMFNbZv@Base 6
+ _D4core6thread5Fiber5stateMxFNbNdZE4core6thread5Fiber5State@Base 6
+ _D4core6thread5Fiber5yieldFNbZv@Base 6
+ _D4core6thread5Fiber6__ctorMFNbDFZvmZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__ctorMFNbPFZvmZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__ctorMFNbZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__dtorMFNbZv@Base 6
+ _D4core6thread5Fiber6__initZ@Base 6
+ _D4core6thread5Fiber6__vtblZ@Base 6
+ _D4core6thread5Fiber7__ClassZ@Base 6
+ _D4core6thread5Fiber7getThisFNbZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber7setThisFNbC4core6thread5FiberZv@Base 6
+ _D4core6thread5Fiber7sm_thisC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber8callImplMFNbZv@Base 6
+ _D4core6thread5Fiber8switchInMFNbZv@Base 6
+ _D4core6thread5Fiber9freeStackMFNbZv@Base 6
+ _D4core6thread5Fiber9initStackMFNbZv@Base 6
+ _D4core6thread5Fiber9switchOutMFNbZv@Base 6
+ _D4core6thread6Thread10popContextMFNbZv@Base 6
+ _D4core6thread6Thread10topContextMFNbZPS4core6thread6Thread7Context@Base 6
+ _D4core6thread6Thread11pushContextMFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread12PRIORITY_MAXxi@Base 6
+ _D4core6thread6Thread12PRIORITY_MINxi@Base 6
+ _D4core6thread6Thread16PRIORITY_DEFAULTxi@Base 6
+ _D4core6thread6Thread18_sharedStaticCtor3FZv@Base 6
+ _D4core6thread6Thread18criticalRegionLockFNbNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core6thread6Thread3addFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread3addFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread3runMFZv@Base 6
+ _D4core6thread6Thread4joinMFbZC6object9Throwable@Base 6
+ _D4core6thread6Thread4nameMFNdAyaZv@Base 6
+ _D4core6thread6Thread4nameMFNdZAya@Base 6
+ _D4core6thread6Thread5sleepFNbS4core4time8DurationZv@Base 6
+ _D4core6thread6Thread5slockFNbNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core6thread6Thread5startMFNbZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread5yieldFNbZv@Base 6
+ _D4core6thread6Thread6__ctorMFDFZvmZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__ctorMFPFZvmZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__ctorMFmZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__dtorMFZv@Base 6
+ _D4core6thread6Thread6__initZ@Base 6
+ _D4core6thread6Thread6__vtblZ@Base 6
+ _D4core6thread6Thread6_locksG2G72v@Base 6
+ _D4core6thread6Thread6getAllFZAC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6removeFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread6removeFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread7Context6__initZ@Base 6
+ _D4core6thread6Thread7__ClassZ@Base 6
+ _D4core6thread6Thread7getThisFNbZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7opApplyFMDFKC4core6thread6ThreadZiZi@Base 6
+ _D4core6thread6Thread7setThisFC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread7sm_cbegPS4core6thread6Thread7Context@Base 6
+ _D4core6thread6Thread7sm_mainC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7sm_tbegC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7sm_thisk@Base 6
+ _D4core6thread6Thread7sm_tlenm@Base 6
+ _D4core6thread6Thread8isDaemonMFNdZb@Base 6
+ _D4core6thread6Thread8isDaemonMFNdbZv@Base 6
+ _D4core6thread6Thread8priorityMFNdZi@Base 6
+ _D4core6thread6Thread8priorityMFNdiZv@Base 6
+ _D4core6thread6Thread9initLocksFZv@Base 6
+ _D4core6thread6Thread9isRunningMFNbNdZb@Base 6
+ _D4core6thread6Thread9termLocksFZv@Base 6
+ _D4core6thread6resumeFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread7suspendFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread8PAGESIZEym@Base 6
+ _D4core6vararg12__ModuleInfoZ@Base 6
+ _D4core7runtime12__ModuleInfoZ@Base 6
+ _D4core7runtime12_staticCtor1FZv@Base 6
+ _D4core7runtime18runModuleUnitTestsUZ19unittestSegvHandlerUiPS4core3sys5posix6signal9siginfo_tPvZv@Base 6
+ _D4core7runtime19defaultTraceHandlerFPvZC6object9Throwable9TraceInfo@Base 6
+ _D4core7runtime5CArgs6__initZ@Base 6
+ _D4core7runtime7Runtime10initializeFDFC6object9ThrowableZvZb@Base 6
+ _D4core7runtime7Runtime10initializeFZb@Base 6
+ _D4core7runtime7Runtime12traceHandlerFNdPFPvZC6object9Throwable9TraceInfoZv@Base 6
+ _D4core7runtime7Runtime12traceHandlerFNdZPFPvZC6object9Throwable9TraceInfo@Base 6
+ _D4core7runtime7Runtime14collectHandlerFNdPFC6ObjectZbZv@Base 6
+ _D4core7runtime7Runtime14collectHandlerFNdZPFC6ObjectZb@Base 6
+ _D4core7runtime7Runtime16moduleUnitTesterFNdPFZbZv@Base 6
+ _D4core7runtime7Runtime16moduleUnitTesterFNdZPFZb@Base 6
+ _D4core7runtime7Runtime19sm_moduleUnitTesterPFZb@Base 6
+ _D4core7runtime7Runtime4argsFNdZAAya@Base 6
+ _D4core7runtime7Runtime5cArgsFNdZS4core7runtime5CArgs@Base 6
+ _D4core7runtime7Runtime6__initZ@Base 6
+ _D4core7runtime7Runtime9terminateFDFC6object9ThrowableZvZb@Base 6
+ _D4core7runtime7Runtime9terminateFZb@Base 6
+ _D4core8demangle12__ModuleInfoZ@Base 6
+ _D4core8demangle12demangleTypeFAxaAaZAa@Base 6
+ _D4core8demangle15decodeDmdStringFAxaKmZAya@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle28__T10mangleFuncHTPFZPvTFZPvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle30__T10mangleFuncHTPFPvZvTFPvZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZl@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterZm@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAamZm@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle48__T10mangleFuncHTPFNaNbNePxvmmZmTFNaNbNePxvmmZmZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle48__T10mangleFuncHTPFNaNbNexmAaZAaTFNaNbNexmAaZAaZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle50__T10mangleFuncHTPFNaNbNexAaxAaZiTFNaNbNexAaxAaZiZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle52__T10mangleFuncHTPFNbPvMDFNbPvZiZvTFNbPvMDFNbPvZiZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle56__T10mangleFuncHTPFNbPvMDFNbPvPvZvZvTFNbPvMDFNbPvPvZvZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle74__T10mangleFuncHTPFNbNiAyaMDFNbNiAyaZAyabZAyaTFNbNiAyaMDFNbNiAyaZAyabZAyaZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle7mangleCFAxaAaZAa@Base 6
+ _D4core8demangle8Demangle10isHexDigitFaZb@Base 6
+ _D4core8demangle8Demangle10parseLNameMFZv@Base 6
+ _D4core8demangle8Demangle10parseValueMFAaaZv@Base 6
+ _D4core8demangle8Demangle11__xopEqualsFKxS4core8demangle8DemangleKxS4core8demangle8DemangleZb@Base 6
+ _D4core8demangle8Demangle11sliceNumberMFZAxa@Base 6
+ _D4core8demangle8Demangle12decodeNumberMFAxaZm@Base 6
+ _D4core8demangle8Demangle12decodeNumberMFZm@Base 6
+ _D4core8demangle8Demangle12demangleNameMFZAa@Base 6
+ _D4core8demangle8Demangle12demangleTypeMFZAa@Base 6
+ _D4core8demangle8Demangle12val2HexDigitFhZa@Base 6
+ _D4core8demangle8Demangle13parseFuncAttrMFZv@Base 6
+ _D4core8demangle8Demangle14ParseException6__ctorMFNaNbNfAyaZC4core8demangle8Demangle14ParseException@Base 6
+ _D4core8demangle8Demangle14ParseException6__initZ@Base 6
+ _D4core8demangle8Demangle14ParseException6__vtblZ@Base 6
+ _D4core8demangle8Demangle14ParseException7__ClassZ@Base 6
+ _D4core8demangle8Demangle15parseSymbolNameMFZv@Base 6
+ _D4core8demangle8Demangle16isCallConventionFaZb@Base 6
+ _D4core8demangle8Demangle16parseMangledNameMFmZv@Base 6
+ _D4core8demangle8Demangle17OverflowException6__ctorMFNaNbNfAyaZC4core8demangle8Demangle17OverflowException@Base 6
+ _D4core8demangle8Demangle17OverflowException6__initZ@Base 6
+ _D4core8demangle8Demangle17OverflowException6__vtblZ@Base 6
+ _D4core8demangle8Demangle17OverflowException7__ClassZ@Base 6
+ _D4core8demangle8Demangle17parseIntegerValueMFAaaZv@Base 6
+ _D4core8demangle8Demangle17parseTemplateArgsMFZv@Base 6
+ _D4core8demangle8Demangle17parseTypeFunctionMFAaE4core8demangle8Demangle10IsDelegateZAa@Base 6
+ _D4core8demangle8Demangle18parseFuncArgumentsMFZv@Base 6
+ _D4core8demangle8Demangle18parseQualifiedNameMFZAa@Base 6
+ _D4core8demangle8Demangle19mayBeMangledNameArgMFZb@Base 6
+ _D4core8demangle8Demangle19parseCallConventionMFZv@Base 6
+ _D4core8demangle8Demangle19parseMangledNameArgMFZv@Base 6
+ _D4core8demangle8Demangle25mayBeTemplateInstanceNameMFZb@Base 6
+ _D4core8demangle8Demangle25parseTemplateInstanceNameMFZv@Base 6
+ _D4core8demangle8Demangle3eatMFaZv@Base 6
+ _D4core8demangle8Demangle3padMFAxaZv@Base 6
+ _D4core8demangle8Demangle3putMFAxaZAa@Base 6
+ _D4core8demangle8Demangle3tokMFZa@Base 6
+ _D4core8demangle8Demangle4nextMFZv@Base 6
+ _D4core8demangle8Demangle4testMFaZv@Base 6
+ _D4core8demangle8Demangle5errorFAyaZv@Base 6
+ _D4core8demangle8Demangle5matchMFAxaZv@Base 6
+ _D4core8demangle8Demangle5matchMFaZv@Base 6
+ _D4core8demangle8Demangle5shiftMFAxaZAa@Base 6
+ _D4core8demangle8Demangle61__T10doDemangleS42_D4core8demangle8Demangle9parseTypeMFAaZAaZ10doDemangleMFZAa@Base 6
+ _D4core8demangle8Demangle67__T10doDemangleS48_D4core8demangle8Demangle16parseMangledNameMFmZvZ10doDemangleMFZAa@Base 6
+ _D4core8demangle8Demangle6__ctorMFNcAxaAaZS4core8demangle8Demangle@Base 6
+ _D4core8demangle8Demangle6__ctorMFNcAxaE4core8demangle8Demangle7AddTypeAaZS4core8demangle8Demangle@Base 6
+ _D4core8demangle8Demangle6__initZ@Base 6
+ _D4core8demangle8Demangle6appendMFAxaZAa@Base 6
+ _D4core8demangle8Demangle6silentMFLvZv@Base 6
+ _D4core8demangle8Demangle7isAlphaFaZb@Base 6
+ _D4core8demangle8Demangle7isDigitFaZb@Base 6
+ _D4core8demangle8Demangle8containsFAxaAxaZb@Base 6
+ _D4core8demangle8Demangle8overflowFAyaZv@Base 6
+ _D4core8demangle8Demangle8putAsHexMFmiZAa@Base 6
+ _D4core8demangle8Demangle9__xtoHashFNbNeKxS4core8demangle8DemangleZm@Base 6
+ _D4core8demangle8Demangle9ascii2hexFaZh@Base 6
+ _D4core8demangle8Demangle9parseRealMFZv@Base 6
+ _D4core8demangle8Demangle9parseTypeMFAaZ10primitivesyG23Aa@Base 6
+ _D4core8demangle8Demangle9parseTypeMFAaZAa@Base 6
+ _D4core8demangle8demangleFAxaAaZAa@Base 6
+ _D4core8internal4hash12__ModuleInfoZ@Base 6
+ _D4core8internal4hash13__T6hashOfTmZ6hashOfFNaNbNemmZm@Base 6
+ _D4core8internal4hash14__T6hashOfTPmZ6hashOfFNaNbNeKPmmZm@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvmmZ16__T6rotl32Vki13Z6rotl32FNaNbNiNfxkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvmmZ16__T6rotl32Vki15Z6rotl32FNaNbNiNfxkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvmmZ6fmix32FNaNbNfkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvmmZ9get32bitsFNaNbPxhZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvmmZm@Base 6
+ _D4core8internal6traits12__ModuleInfoZ@Base 6
+ _D4core8internal7convert11shiftrRoundFNaNbNfmZm@Base 6
+ _D4core8internal7convert12__ModuleInfoZ@Base 6
+ _D4core8internal7convert14__T7toUbyteTmZ7toUbyteFNaNbNeKmZAxh@Base 6
+ _D4core8internal7convert5Float6__initZ@Base 6
+ _D4core8internal7convert7binPow2FNaNbNfiZ10binPosPow2FNaNbNfiZe@Base 6
+ _D4core8internal7convert7binPow2FNaNbNfiZe@Base 6
+ _D4core9exception10RangeError6__ctorMFNaNbNfAyamC6object9ThrowableZC4core9exception10RangeError@Base 6
+ _D4core9exception10RangeError6__initZ@Base 6
+ _D4core9exception10RangeError6__vtblZ@Base 6
+ _D4core9exception10RangeError7__ClassZ@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfAyamZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfC6object9ThrowableAyamZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__initZ@Base 6
+ _D4core9exception11AssertError6__vtblZ@Base 6
+ _D4core9exception11AssertError7__ClassZ@Base 6
+ _D4core9exception11SwitchError6__ctorMFNaNbNfAyamC6object9ThrowableZC4core9exception11SwitchError@Base 6
+ _D4core9exception11SwitchError6__initZ@Base 6
+ _D4core9exception11SwitchError6__vtblZ@Base 6
+ _D4core9exception11SwitchError7__ClassZ@Base 6
+ _D4core9exception12__ModuleInfoZ@Base 6
+ _D4core9exception13FinalizeError6__ctorMFNaNbNfC8TypeInfoAyamC6object9ThrowableZC4core9exception13FinalizeError@Base 6
+ _D4core9exception13FinalizeError6__ctorMFNaNbNfC8TypeInfoC6object9ThrowableAyamZC4core9exception13FinalizeError@Base 6
+ _D4core9exception13FinalizeError6__initZ@Base 6
+ _D4core9exception13FinalizeError6__vtblZ@Base 6
+ _D4core9exception13FinalizeError7__ClassZ@Base 6
+ _D4core9exception13FinalizeError8toStringMxFNfZAya@Base 6
+ _D4core9exception13assertHandlerFNbNdNiNePFNbAyamAyaZvZv@Base 6
+ _D4core9exception13assertHandlerFNbNdNiNeZPFNbAyamAyaZv@Base 6
+ _D4core9exception14_assertHandlerPFNbAyamAyaZv@Base 6
+ _D4core9exception15HiddenFuncError6__ctorMFNaNbNfC14TypeInfo_ClassZC4core9exception15HiddenFuncError@Base 6
+ _D4core9exception15HiddenFuncError6__initZ@Base 6
+ _D4core9exception15HiddenFuncError6__vtblZ@Base 6
+ _D4core9exception15HiddenFuncError7__ClassZ@Base 6
+ _D4core9exception15onFinalizeErrorUNbNeC8TypeInfoC6object9ThrowableAyamZ3errC4core9exception13FinalizeError@Base 6
+ _D4core9exception16OutOfMemoryError6__ctorMFNaNbNfAyamC6object9ThrowableZC4core9exception16OutOfMemoryError@Base 6
+ _D4core9exception16OutOfMemoryError6__initZ@Base 6
+ _D4core9exception16OutOfMemoryError6__vtblZ@Base 6
+ _D4core9exception16OutOfMemoryError7__ClassZ@Base 6
+ _D4core9exception16OutOfMemoryError8toStringMxFNeZAya@Base 6
+ _D4core9exception16UnicodeException6__ctorMFNaNbNfAyamAyamC6object9ThrowableZC4core9exception16UnicodeException@Base 6
+ _D4core9exception16UnicodeException6__initZ@Base 6
+ _D4core9exception16UnicodeException6__vtblZ@Base 6
+ _D4core9exception16UnicodeException7__ClassZ@Base 6
+ _D4core9exception16setAssertHandlerFNbNiNePFNbAyamAyaZvZv@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__ctorMFNaNbNfAyamC6object9ThrowableZC4core9exception27InvalidMemoryOperationError@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__initZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__vtblZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError7__ClassZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError8toStringMxFNeZAya@Base 6
+ _D50TypeInfo_HC4core6thread6ThreadC4core6thread6Thread6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc4Addr6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5posix7netinet3in_11sockaddr_in6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5posix7pthread15pthread_cleanup6__initZ@Base 6
+ _D51TypeInfo_E4core4sync7rwmutex14ReadWriteMutex6Policy6__initZ@Base 6
+ _D51TypeInfo_S2rt19sections_elf_shared15CompilerDSOData6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix3sys5types14pthread_attr_t6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix3sys5types14pthread_cond_t6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix7netinet3in_12sockaddr_in66__initZ@Base 6
+ _D52TypeInfo_S4core3sys5linux3elf11Elf32_gptab9_gt_entry6__initZ@Base 6
+ _D52TypeInfo_S4core3sys5linux3sys7inotify13inotify_event6__initZ@Base 6
+ _D52TypeInfo_S4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D53TypeInfo_S4core3sys5posix3sys5types16pthread_rwlock_t6__initZ@Base 6
+ _D53TypeInfo_xS4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D54TypeInfo_S2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5linux3elf11Elf32_gptab10_gt_header6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5linux5stdio21cookie_io_functions_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys5types17_pthread_fastlock6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys5types17pthread_barrier_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys6socket16sockaddr_storage6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix6signal8sigevent11_sigev_un_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix9semaphore17_pthread_fastlock6__initZ@Base 6
+ _D55TypeInfo_S2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc4Addr4Name6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5posix3sys5types18pthread_condattr_t6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t6__initZ@Base 6
+ _D56TypeInfo_S4core3sys5linux3sys8signalfd16signalfd_siginfo6__initZ@Base 6
+ _D56TypeInfo_S4core3sys5posix3sys5types19pthread_mutexattr_t6__initZ@Base 6
+ _D56TypeInfo_xS2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D57TypeInfo_S4core3sys5posix3sys5types20pthread_rwlockattr_t6__initZ@Base 6
+ _D58TypeInfo_S4core3sys5posix3sys5types21pthread_barrierattr_t6__initZ@Base 6
+ _D58TypeInfo_S4core3sys5posix7pthread23_pthread_cleanup_buffer6__initZ@Base 6
+ _D61TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t5_rt_t6__initZ@Base 6
+ _D62TypeInfo_S2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D63TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t7_kill_t6__initZ@Base 6
+ _D63TypeInfo_xS2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D64TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t8_timer_t6__initZ@Base 6
+ _D65TypeInfo_S2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D65TypeInfo_S4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy6__initZ@Base 6
+ _D65TypeInfo_S4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy6__initZ@Base 6
+ _D66TypeInfo_S2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D66TypeInfo_xS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D67TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t10_sigpoll_t6__initZ@Base 6
+ _D67TypeInfo_xS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D68TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t11_sigchild_t6__initZ@Base 6
+ _D68TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t11_sigfault_t6__initZ@Base 6
+ _D6Object6__initZ@Base 6
+ _D6Object6__vtblZ@Base 6
+ _D6Object7__ClassZ@Base 6
+ _D6object101__T7destroyTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D6object10ModuleInfo11xgetMembersMxFNaNbNdZPv@Base 6
+ _D6object10ModuleInfo12localClassesMxFNaNbNdZAC14TypeInfo_Class@Base 6
+ _D6object10ModuleInfo15importedModulesMxFNaNbNdZAyPS6object10ModuleInfo@Base 6
+ _D6object10ModuleInfo4ctorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo4dtorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo4nameMxFNaNbNdZAya@Base 6
+ _D6object10ModuleInfo5flagsMxFNaNbNdZk@Base 6
+ _D6object10ModuleInfo5ictorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo5indexMxFNaNbNdZk@Base 6
+ _D6object10ModuleInfo6__initZ@Base 6
+ _D6object10ModuleInfo6addrOfMxFNaNbiZPv@Base 6
+ _D6object10ModuleInfo7opApplyFMDFPS6object10ModuleInfoZiZi@Base 6
+ _D6object10ModuleInfo7tlsctorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo7tlsdtorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo8opAssignMFxS6object10ModuleInfoZv@Base 6
+ _D6object10ModuleInfo8unitTestMxFNaNbNdZPFZv@Base 6
+ _D6object10__T3dupThZ3dupFNaNbNdNfAxhZAh@Base 6
+ _D6object10_xopEqualsFxPvxPvZb@Base 6
+ _D6object10getElementFNaNbNeNgC8TypeInfoZNgC8TypeInfo@Base 6
+ _D6object111__T16_destructRecurseTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ16_destructRecurseFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D6object11__T4idupTaZ4idupFNaNbNdNfAaZAya@Base 6
+ _D6object12__ModuleInfoZ@Base 6
+ _D6object12getArrayHashFNbNexC8TypeInfoxPvxmZ15hasCustomToHashFNaNbNexC8TypeInfoZb@Base 6
+ _D6object12getArrayHashFNbNexC8TypeInfoxPvxmZm@Base 6
+ _D6object12setSameMutexFOC6ObjectOC6ObjectZv@Base 6
+ _D6object14OffsetTypeInfo11__xopEqualsFKxS6object14OffsetTypeInfoKxS6object14OffsetTypeInfoZb@Base 6
+ _D6object14OffsetTypeInfo6__initZ@Base 6
+ _D6object14OffsetTypeInfo9__xtoHashFNbNeKxS6object14OffsetTypeInfoZm@Base 6
+ _D6object14TypeInfo_Array4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object14TypeInfo_Array4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Array5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Array5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object14TypeInfo_Array6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Array6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object14TypeInfo_Array7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Array7getHashMxFNbNexPvZm@Base 6
+ _D6object14TypeInfo_Array8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object14TypeInfo_Array8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Array8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Class10ClassFlags6__initZ@Base 6
+ _D6object14TypeInfo_Class4findFxAaZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Class4infoMxFNaNbNdNiNfZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Class4initMxFNaNbNiNfZAxv@Base 6
+ _D6object14TypeInfo_Class5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Class5offTiMxFNaNbNdZAxS6object14OffsetTypeInfo@Base 6
+ _D6object14TypeInfo_Class5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object14TypeInfo_Class6createMxFZC6Object@Base 6
+ _D6object14TypeInfo_Class6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Class6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object14TypeInfo_Class7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Class7getHashMxFNbNexPvZm@Base 6
+ _D6object14TypeInfo_Class8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Class8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Class8typeinfoMxFNaNbNdNiNfZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Const4initMxFNaNbNiNfZAxv@Base 6
+ _D6object14TypeInfo_Const4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object14TypeInfo_Const4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Const5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Const5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object14TypeInfo_Const6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Const6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object14TypeInfo_Const7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Const7getHashMxFNbNfxPvZm@Base 6
+ _D6object14TypeInfo_Const8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object14TypeInfo_Const8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Const8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Inout8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Tuple4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Tuple5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object14TypeInfo_Tuple6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Tuple6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object14TypeInfo_Tuple7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Tuple7destroyMxFPvZv@Base 6
+ _D6object14TypeInfo_Tuple7getHashMxFNbNfxPvZm@Base 6
+ _D6object14TypeInfo_Tuple8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object14TypeInfo_Tuple8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Tuple8postblitMxFPvZv@Base 6
+ _D6object14TypeInfo_Tuple8toStringMxFNaNbNfZAya@Base 6
+ _D6object14__T4_dupTaTyaZ4_dupFNaNbAaZAya@Base 6
+ _D6object14__T4_dupTxhThZ4_dupFNaNbAxhZAh@Base 6
+ _D6object14__T6hashOfTPmZ6hashOfFNaNbNfPmmZm@Base 6
+ _D6object14__T7_rawDupTaZ7_rawDupFNaNbANgaZANga@Base 6
+ _D6object14__T7_rawDupThZ7_rawDupFNaNbANghZANgh@Base 6
+ _D6object15TypeInfo_Shared8toStringMxFNaNbNfZAya@Base 6
+ _D6object15TypeInfo_Struct11StructFlags6__initZ@Base 6
+ _D6object15TypeInfo_Struct4initMxFNaNbNiNfZAxv@Base 6
+ _D6object15TypeInfo_Struct5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Struct5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object15TypeInfo_Struct6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D6object15TypeInfo_Struct6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object15TypeInfo_Struct6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object15TypeInfo_Struct7compareMxFNaNbNexPvxPvZi@Base 6
+ _D6object15TypeInfo_Struct7destroyMxFPvZv@Base 6
+ _D6object15TypeInfo_Struct7getHashMxFNaNbNfxPvZm@Base 6
+ _D6object15TypeInfo_Struct8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object15TypeInfo_Struct8opEqualsMFC6ObjectZb@Base 6
+ _D6object15TypeInfo_Struct8postblitMxFPvZv@Base 6
+ _D6object15TypeInfo_Struct8toStringMxFNaNbNfZAya@Base 6
+ _D6object15TypeInfo_Vector4initMxFNaNbNiNfZAxv@Base 6
+ _D6object15TypeInfo_Vector4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object15TypeInfo_Vector4swapMxFPvPvZv@Base 6
+ _D6object15TypeInfo_Vector5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Vector5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object15TypeInfo_Vector6equalsMxFxPvxPvZb@Base 6
+ _D6object15TypeInfo_Vector6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object15TypeInfo_Vector7compareMxFxPvxPvZi@Base 6
+ _D6object15TypeInfo_Vector7getHashMxFNbNfxPvZm@Base 6
+ _D6object15TypeInfo_Vector8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object15TypeInfo_Vector8opEqualsMFC6ObjectZb@Base 6
+ _D6object15TypeInfo_Vector8toStringMxFNaNbNfZAya@Base 6
+ _D6object16TypeInfo_Pointer4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object16TypeInfo_Pointer4swapMxFPvPvZv@Base 6
+ _D6object16TypeInfo_Pointer5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Pointer5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object16TypeInfo_Pointer6equalsMxFxPvxPvZb@Base 6
+ _D6object16TypeInfo_Pointer7compareMxFxPvxPvZi@Base 6
+ _D6object16TypeInfo_Pointer7getHashMxFNbNexPvZm@Base 6
+ _D6object16TypeInfo_Pointer8opEqualsMFC6ObjectZb@Base 6
+ _D6object16TypeInfo_Pointer8toStringMxFNaNbNfZAya@Base 6
+ _D6object16TypeInfo_Typedef4initMxFNaNbNiNfZAxv@Base 6
+ _D6object16TypeInfo_Typedef4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object16TypeInfo_Typedef4swapMxFPvPvZv@Base 6
+ _D6object16TypeInfo_Typedef5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Typedef5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object16TypeInfo_Typedef6equalsMxFxPvxPvZb@Base 6
+ _D6object16TypeInfo_Typedef6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object16TypeInfo_Typedef6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object16TypeInfo_Typedef7compareMxFxPvxPvZi@Base 6
+ _D6object16TypeInfo_Typedef7getHashMxFNbNfxPvZm@Base 6
+ _D6object16TypeInfo_Typedef8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object16TypeInfo_Typedef8opEqualsMFC6ObjectZb@Base 6
+ _D6object16TypeInfo_Typedef8toStringMxFNaNbNfZAya@Base 6
+ _D6object17TypeInfo_Delegate5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Delegate5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object17TypeInfo_Delegate6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object17TypeInfo_Delegate8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object17TypeInfo_Delegate8opEqualsMFC6ObjectZb@Base 6
+ _D6object17TypeInfo_Delegate8toStringMxFNaNbNfZAya@Base 6
+ _D6object17TypeInfo_Function5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object17TypeInfo_Function8opEqualsMFC6ObjectZb@Base 6
+ _D6object17TypeInfo_Function8toStringMxFNaNbNfZAya@Base 6
+ _D6object18TypeInfo_Interface5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object18TypeInfo_Interface5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object18TypeInfo_Interface6equalsMxFxPvxPvZb@Base 6
+ _D6object18TypeInfo_Interface7compareMxFxPvxPvZi@Base 6
+ _D6object18TypeInfo_Interface7getHashMxFNbNexPvZm@Base 6
+ _D6object18TypeInfo_Interface8opEqualsMFC6ObjectZb@Base 6
+ _D6object18TypeInfo_Interface8toStringMxFNaNbNfZAya@Base 6
+ _D6object18TypeInfo_Invariant8toStringMxFNaNbNfZAya@Base 6
+ _D6object19__T11_doPostblitThZ11_doPostblitFNaNbNiNfAhZv@Base 6
+ _D6object20TypeInfo_StaticArray4initMxFNaNbNiNfZAxv@Base 6
+ _D6object20TypeInfo_StaticArray4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object20TypeInfo_StaticArray4swapMxFPvPvZv@Base 6
+ _D6object20TypeInfo_StaticArray5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object20TypeInfo_StaticArray5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object20TypeInfo_StaticArray6equalsMxFxPvxPvZb@Base 6
+ _D6object20TypeInfo_StaticArray6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object20TypeInfo_StaticArray7compareMxFxPvxPvZi@Base 6
+ _D6object20TypeInfo_StaticArray7destroyMxFPvZv@Base 6
+ _D6object20TypeInfo_StaticArray7getHashMxFNbNexPvZm@Base 6
+ _D6object20TypeInfo_StaticArray8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object20TypeInfo_StaticArray8opEqualsMFC6ObjectZb@Base 6
+ _D6object20TypeInfo_StaticArray8postblitMxFPvZv@Base 6
+ _D6object20TypeInfo_StaticArray8toStringMxFNaNbNfZAya@Base 6
+ _D6object20__T11_doPostblitTyaZ11_doPostblitFNaNbNiNfAyaZv@Base 6
+ _D6object20__T12_getPostblitThZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKhZv@Base 6
+ _D6object21__T12_getPostblitTyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyaZv@Base 6
+ _D6object22__T11_trustedDupTaTyaZ11_trustedDupFNaNbNeAaZAya@Base 6
+ _D6object22__T11_trustedDupTxhThZ11_trustedDupFNaNbNeAxhZAh@Base 6
+ _D6object25TypeInfo_AssociativeArray4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object25TypeInfo_AssociativeArray5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object25TypeInfo_AssociativeArray5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object25TypeInfo_AssociativeArray6equalsMxFNexPvxPvZb@Base 6
+ _D6object25TypeInfo_AssociativeArray6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object25TypeInfo_AssociativeArray7getHashMxFNbNexPvZm@Base 6
+ _D6object25TypeInfo_AssociativeArray8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object25TypeInfo_AssociativeArray8opEqualsMFC6ObjectZb@Base 6
+ _D6object25TypeInfo_AssociativeArray8toStringMxFNaNbNfZAya@Base 6
+ _D6object38__T11_doPostblitTC4core6thread6ThreadZ11_doPostblitFNaNbNiNfAC4core6thread6ThreadZv@Base 6
+ _D6object39__T12_getPostblitTC4core6thread6ThreadZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKC4core6thread6ThreadZv@Base 6
+ _D6object43__T7destroyTPS3gcc3deh18d_exception_headerZ7destroyFNaNbNiNfKPS3gcc3deh18d_exception_headerZv@Base 6
+ _D6object48__T7destroyTS2rt19sections_elf_shared9ThreadDSOZ7destroyFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D6object58__T16_destructRecurseTS2rt19sections_elf_shared9ThreadDSOZ16_destructRecurseFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D6object5Error6__ctorMFNaNbNiNfAyaAyamC6object9ThrowableZC6object5Error@Base 6
+ _D6object5Error6__ctorMFNaNbNiNfAyaC6object9ThrowableZC6object5Error@Base 6
+ _D6object5Error6__initZ@Base 6
+ _D6object5Error6__vtblZ@Base 6
+ _D6object5Error7__ClassZ@Base 6
+ _D6object6Object5opCmpMFC6ObjectZi@Base 6
+ _D6object6Object6toHashMFNbNeZm@Base 6
+ _D6object6Object7Monitor11__InterfaceZ@Base 6
+ _D6object6Object7factoryFAyaZC6Object@Base 6
+ _D6object6Object8opEqualsMFC6ObjectZb@Base 6
+ _D6object6Object8toStringMFZAya@Base 6
+ _D6object7AARange6__initZ@Base 6
+ _D6object7_xopCmpFxPvxPvZb@Base 6
+ _D6object8TypeInfo4initMxFNaNbNiNfZAxv@Base 6
+ _D6object8TypeInfo4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object8TypeInfo4swapMxFPvPvZv@Base 6
+ _D6object8TypeInfo5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object8TypeInfo5offTiMxFZAxS6object14OffsetTypeInfo@Base 6
+ _D6object8TypeInfo5opCmpMFC6ObjectZi@Base 6
+ _D6object8TypeInfo5tsizeMxFNaNbNdNiNfZm@Base 6
+ _D6object8TypeInfo6equalsMxFxPvxPvZb@Base 6
+ _D6object8TypeInfo6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object8TypeInfo6talignMxFNaNbNdNiNfZm@Base 6
+ _D6object8TypeInfo6toHashMxFNbNeZm@Base 6
+ _D6object8TypeInfo7compareMxFxPvxPvZi@Base 6
+ _D6object8TypeInfo7destroyMxFPvZv@Base 6
+ _D6object8TypeInfo7getHashMxFNbNexPvZm@Base 6
+ _D6object8TypeInfo8argTypesMFNbNfJC8TypeInfoJC8TypeInfoZi@Base 6
+ _D6object8TypeInfo8opEqualsMFC6ObjectZb@Base 6
+ _D6object8TypeInfo8postblitMxFPvZv@Base 6
+ _D6object8TypeInfo8toStringMxFNaNbNfZAya@Base 6
+ _D6object8opEqualsFC6ObjectC6ObjectZb@Base 6
+ _D6object8opEqualsFxC6ObjectxC6ObjectZb@Base 6
+ _D6object94__T4keysHTHC4core6thread6ThreadC4core6thread6ThreadTC4core6thread6ThreadTC4core6thread6ThreadZ4keysFNaNbNdHC4core6thread6ThreadC4core6thread6ThreadZAC4core6thread6Thread@Base 6
+ _D6object9Exception6__ctorMFNaNbNiNfAyaAyamC6object9ThrowableZC9Exception@Base 6
+ _D6object9Exception6__ctorMFNaNbNiNfAyaC6object9ThrowableAyamZC9Exception@Base 6
+ _D6object9Interface11__xopEqualsFKxS6object9InterfaceKxS6object9InterfaceZb@Base 6
+ _D6object9Interface6__initZ@Base 6
+ _D6object9Interface9__xtoHashFNbNeKxS6object9InterfaceZm@Base 6
+ _D6object9Throwable6__ctorMFNaNbNiNfAyaAyamC6object9ThrowableZC6object9Throwable@Base 6
+ _D6object9Throwable6__ctorMFNaNbNiNfAyaC6object9ThrowableZC6object9Throwable@Base 6
+ _D6object9Throwable6__initZ@Base 6
+ _D6object9Throwable6__vtblZ@Base 6
+ _D6object9Throwable7__ClassZ@Base 6
+ _D6object9Throwable8toStringMFZAya@Base 6
+ _D6object9Throwable8toStringMxFMDFxAaZvZv@Base 6
+ _D6object9Throwable9TraceInfo11__InterfaceZ@Base 6
+ _D70TypeInfo_S2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D71TypeInfo_S2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D71TypeInfo_S4core3sys5posix6signal8sigevent11_sigev_un_t15_sigev_thread_t6__initZ@Base 6
+ _D71TypeInfo_xS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_PxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_S3gcc6unwind2pe28read_encoded_value_with_baseFhmPhPmZ9unaligned6__initZ@Base 6
+ _D72TypeInfo_xPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_xS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D73TypeInfo_PxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D73TypeInfo_xPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D75TypeInfo_S4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D76TypeInfo_S4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D78TypeInfo_S4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl6__initZ@Base 6
+ _D83TypeInfo_S2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D84TypeInfo_xS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D85TypeInfo_S4core8demangle26__T6mangleTFNaNbNePxvmmZmZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D85TypeInfo_S4core8demangle26__T6mangleTFNaNbNexmAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D86TypeInfo_S4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D87TypeInfo_S4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D88TypeInfo_S2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__initZ@Base 6
+ _D89TypeInfo_S4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D8TypeInfo6__initZ@Base 6
+ _D8TypeInfo6__vtblZ@Base 6
+ _D8TypeInfo7__ClassZ@Base 6
+ _D92TypeInfo_S2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__initZ@Base 6
+ _D97TypeInfo_S2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node6__initZ@Base 6
+ _D98TypeInfo_S4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D9Exception6__initZ@Base 6
+ _D9Exception6__vtblZ@Base 6
+ _D9Exception7__ClassZ@Base 6
+ _D9invariant12__ModuleInfoZ@Base 6
+ _D9invariant12_d_invariantFC6ObjectZv@Base 6
+ _DT1184_D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKmKxAaZiZi@Base 6
+ _DT1184_D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKxAaZiZi@Base 6
+ _DT1184_D3gcc9backtrace12LibBacktrace8toStringMxFZAya@Base 6
+ _DT32_D4core4sync7rwmutex14ReadWriteMutex6Reader4lockMFNeZv@Base 6
+ _DT32_D4core4sync7rwmutex14ReadWriteMutex6Reader6unlockMFNeZv@Base 6
+ _DT32_D4core4sync7rwmutex14ReadWriteMutex6Writer4lockMFNeZv@Base 6
+ _DT32_D4core4sync7rwmutex14ReadWriteMutex6Writer6unlockMFNeZv@Base 6
+ _DT64_D2gc2gc7GCMutex4lockMFNbNiNeZv@Base 6
+ _DT64_D2gc2gc7GCMutex6unlockMFNbNiNeZv@Base 6
+ _DT64_D4core4sync5mutex5Mutex4lockMFNeZv@Base 6
+ _DT64_D4core4sync5mutex5Mutex6unlockMFNeZv@Base 6
+ __gdc_begin_catch@Base 6
+ __gdc_exception_cleanup@Base 6
+ __gdc_personality_v0@Base 6
+ __mod_ref__D2gc2gc12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc2os12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc4bits12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc5proxy12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc5stats12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc9pooltable12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt11arrayassign12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt12sections_osx12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt14sections_win3212__ModuleInfoZ@Base 6
+ __mod_ref__D2rt14sections_win6412__ModuleInfoZ@Base 6
+ __mod_ref__D2rt16sections_android12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt16sections_solaris12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt19sections_elf_shared12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3aaA12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3adi12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3deh12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3obj12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util3utf12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util4hash12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util5array12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util6random12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util6string12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util8typeinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container5array12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container5treap12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container6common12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container7hashtab12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5cast_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5minfo12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5qsort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5tlsgc12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6aApply12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6config12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6dmain212__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6memory12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt7aApplyR12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt7switch_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8arraycat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8lifetime12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8monitor_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8sections12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_Acfloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_Adouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_cdouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_idouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo11ti_Acdouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo11ti_delegate12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo4ti_C12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo5ti_AC12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo5ti_Ag12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo6ti_int12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo6ti_ptr12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_Aint12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_byte12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_cent12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_char12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_long12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_real12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_uint12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_void12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_Along12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_Areal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_creal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_dchar12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_float12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ireal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_short12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ubyte12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ucent12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ulong12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_wchar12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Acreal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Afloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Ashort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_cfloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_double12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_ifloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_ushort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt9arraycast12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt9critical_12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc5linux11memoryerror12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc12libbacktrace12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc3deh12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind2pe12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind3arm12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind7generic12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc7atomics12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc8builtins12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc9attribute12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc9backtrace12__ModuleInfoZ@Base 6
+ __mod_ref__D4core10checkedint12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3elf12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys4mman12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys5xattr12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys7inotify12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys7sysinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys8signalfd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4link12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4tipc12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5dlfcn12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5epoll12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5errno12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux8execinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3grp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3net3if_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3pwd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys2un12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3ipc12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3msg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3shm12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3uio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4mman12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4stat12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4wait12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys5ioctl12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys5types12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys6select12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys7statvfs12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys7utsname12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys8resource12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4arpa4inet12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4poll12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5dlfcn12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5fcntl12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5netdb12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5sched12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5utime12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6dirent12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6setjmp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6signal12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6syslog12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6unistd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7netinet3in_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7netinet3tcp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7pthread12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix8inttypes12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix8ucontext12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix9semaphore12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4math12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4simd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4fenv12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4math12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5ctype12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5errno12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6float_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6limits12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6locale12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6signal12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdarg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stddef12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdint12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6string12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6tgmath12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6wchar_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6wctype12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc7complex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc8inttypes12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync5mutex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync7barrier12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync7rwmutex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9condition12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9semaphore12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core5bitop12__ModuleInfoZ@Base 6
+ __mod_ref__D4core5cpuid12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6atomic12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6memory12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6thread12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6vararg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core7runtime12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8demangle12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal4hash12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal6traits12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal7convert12__ModuleInfoZ@Base 6
+ __mod_ref__D4core9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D6object12__ModuleInfoZ@Base 6
+ __mod_ref__D9invariant12__ModuleInfoZ@Base 6
+ _aApplyRcd1@Base 6
+ _aApplyRcd2@Base 6
+ _aApplyRcw1@Base 6
+ _aApplyRcw2@Base 6
+ _aApplyRdc1@Base 6
+ _aApplyRdc2@Base 6
+ _aApplyRdw1@Base 6
+ _aApplyRdw2@Base 6
+ _aApplyRwc1@Base 6
+ _aApplyRwc2@Base 6
+ _aApplyRwd1@Base 6
+ _aApplyRwd2@Base 6
+ _aApplycd1@Base 6
+ _aApplycd2@Base 6
+ _aApplycw1@Base 6
+ _aApplycw2@Base 6
+ _aApplydc1@Base 6
+ _aApplydc2@Base 6
+ _aApplydw1@Base 6
+ _aApplydw2@Base 6
+ _aApplywc1@Base 6
+ _aApplywc2@Base 6
+ _aApplywd1@Base 6
+ _aApplywd2@Base 6
+ _aaApply2@Base 6
+ _aaApply@Base 6
+ _aaDelX@Base 6
+ _aaEqual@Base 6
+ _aaGetHash@Base 6
+ _aaGetRvalueX@Base 6
+ _aaGetY@Base 6
+ _aaInX@Base 6
+ _aaKeys@Base 6
+ _aaLen@Base 6
+ _aaRange@Base 6
+ _aaRangeEmpty@Base 6
+ _aaRangeFrontKey@Base 6
+ _aaRangeFrontValue@Base 6
+ _aaRangePopFront@Base 6
+ _aaRehash@Base 6
+ _aaValues@Base 6
+ _aaVersion@Base 6
+ _adCmp2@Base 6
+ _adCmp@Base 6
+ _adCmpChar@Base 6
+ _adEq2@Base 6
+ _adEq@Base 6
+ _adReverse@Base 6
+ _adReverseChar@Base 6
+ _adReverseWchar@Base 6
+ _adSort@Base 6
+ _adSortChar@Base 6
+ _adSortWchar@Base 6
+ _d_allocmemory@Base 6
+ _d_array_bounds@Base 6
+ _d_arrayappendT@Base 6
+ _d_arrayappendcTX@Base 6
+ _d_arrayappendcd@Base 6
+ _d_arrayappendwd@Base 6
+ _d_arrayassign@Base 6
+ _d_arrayassign_l@Base 6
+ _d_arrayassign_r@Base 6
+ _d_arraybounds@Base 6
+ _d_arraycast@Base 6
+ _d_arraycatT@Base 6
+ _d_arraycatnTX@Base 6
+ _d_arraycopy@Base 6
+ _d_arrayctor@Base 6
+ _d_arrayliteralTX@Base 6
+ _d_arraysetassign@Base 6
+ _d_arraysetcapacity@Base 6
+ _d_arraysetctor@Base 6
+ _d_arraysetlengthT@Base 6
+ _d_arraysetlengthiT@Base 6
+ _d_arrayshrinkfit@Base 6
+ _d_assert@Base 6
+ _d_assert_msg@Base 6
+ _d_assertm@Base 6
+ _d_assocarrayliteralTX@Base 6
+ _d_callfinalizer@Base 6
+ _d_callinterfacefinalizer@Base 6
+ _d_createTrace@Base 6
+ _d_critical_init@Base 6
+ _d_critical_term@Base 6
+ _d_criticalenter@Base 6
+ _d_criticalexit@Base 6
+ _d_delarray@Base 6
+ _d_delarray_t@Base 6
+ _d_delclass@Base 6
+ _d_delinterface@Base 6
+ _d_delmemory@Base 6
+ _d_delstruct@Base 6
+ _d_dso_registry@Base 6
+ _d_dynamic_cast@Base 6
+ _d_initMonoTime@Base 6
+ _d_interface_cast@Base 6
+ _d_interface_vtbl@Base 6
+ _d_isbaseof2@Base 6
+ _d_isbaseof@Base 6
+ _d_main_args@Base 6
+ _d_monitor_staticctor@Base 6
+ _d_monitor_staticdtor@Base 6
+ _d_monitordelete@Base 6
+ _d_monitorenter@Base 6
+ _d_monitorexit@Base 6
+ _d_newarrayT@Base 6
+ _d_newarrayU@Base 6
+ _d_newarrayiT@Base 6
+ _d_newarraymTX@Base 6
+ _d_newarraymiTX@Base 6
+ _d_newclass@Base 6
+ _d_newitemT@Base 6
+ _d_newitemU@Base 6
+ _d_newitemiT@Base 6
+ _d_obj_cmp@Base 6
+ _d_obj_eq@Base 6
+ _d_print_throwable@Base 6
+ _d_run_main@Base 6
+ _d_setSameMutex@Base 6
+ _d_switch_dstring@Base 6
+ _d_switch_error@Base 6
+ _d_switch_errorm@Base 6
+ _d_switch_string@Base 6
+ _d_switch_ustring@Base 6
+ _d_throw@Base 6
+ _d_toObject@Base 6
+ _d_traceContext@Base 6
+ _d_unittest@Base 6
+ _d_unittest_msg@Base 6
+ _d_unittestm@Base 6
+ backtrace_alloc@Base 6
+ backtrace_close@Base 6
+ backtrace_create_state@Base 6
+ backtrace_dwarf_add@Base 6
+ backtrace_free@Base 6
+ backtrace_full@Base 6
+ backtrace_get_view@Base 6
+ backtrace_initialize@Base 6
+ backtrace_open@Base 6
+ backtrace_pcinfo@Base 6
+ backtrace_print@Base 6
+ backtrace_qsort@Base 6
+ backtrace_release_view@Base 6
+ backtrace_simple@Base 6
+ backtrace_syminfo@Base 6
+ backtrace_vector_finish@Base 6
+ backtrace_vector_grow@Base 6
+ backtrace_vector_release@Base 6
+ fiber_entryPoint@Base 6
+ fiber_switchContext@Base 6
+ gc_addRange@Base 6
+ gc_addRoot@Base 6
+ gc_addrOf@Base 6
+ gc_calloc@Base 6
+ gc_clrAttr@Base 6
+ gc_clrProxy@Base 6
+ gc_collect@Base 6
+ gc_disable@Base 6
+ gc_enable@Base 6
+ gc_extend@Base 6
+ gc_free@Base 6
+ gc_getAttr@Base 6
+ gc_getProxy@Base 6
+ gc_init@Base 6
+ gc_malloc@Base 6
+ gc_minimize@Base 6
+ gc_qalloc@Base 6
+ gc_query@Base 6
+ gc_realloc@Base 6
+ gc_removeRange@Base 6
+ gc_removeRoot@Base 6
+ gc_reserve@Base 6
+ gc_runFinalizers@Base 6
+ gc_setAttr@Base 6
+ gc_setProxy@Base 6
+ gc_sizeOf@Base 6
+ gc_stats@Base 6
+ gc_term@Base 6
+ getErrno@Base 6
+ lifetime_init@Base 6
+ onAssertError@Base 6
+ onAssertErrorMsg@Base 6
+ onFinalizeError@Base 6
+ onHiddenFuncError@Base 6
+ onInvalidMemoryOperationError@Base 6
+ onOutOfMemoryError@Base 6
+ onRangeError@Base 6
+ onSwitchError@Base 6
+ onUnicodeError@Base 6
+ onUnittestErrorMsg@Base 6
+ pcinfoCallback@Base 6
+ pcinfoErrorCallback@Base 6
+ rt_args@Base 6
+ rt_attachDisposeEvent@Base 6
+ rt_cArgs@Base 6
+ rt_cmdline_enabled@Base 6
+ rt_detachDisposeEvent@Base 6
+ rt_envvars_enabled@Base 6
+ rt_finalize2@Base 6
+ rt_finalize@Base 6
+ rt_finalizeFromGC@Base 6
+ rt_getCollectHandler@Base 6
+ rt_getTraceHandler@Base 6
+ rt_hasFinalizerInSegment@Base 6
+ rt_init@Base 6
+ rt_loadLibrary@Base 6
+ rt_moduleCtor@Base 6
+ rt_moduleDtor@Base 6
+ rt_moduleTlsCtor@Base 6
+ rt_moduleTlsDtor@Base 6
+ rt_options@Base 6
+ rt_setCollectHandler@Base 6
+ rt_setTraceHandler@Base 6
+ rt_term@Base 6
+ rt_trapExceptions@Base 6
+ rt_unloadLibrary@Base 6
+ runModuleUnitTests@Base 6
+ setErrno@Base 6
+ simpleCallback@Base 6
+ simpleErrorCallback@Base 6
+ syminfoCallback2@Base 6
+ syminfoCallback@Base 6
+ thread_attachThis@Base 6
+ thread_detachByAddr@Base 6
+ thread_detachInstance@Base 6
+ thread_detachThis@Base 6
+ thread_enterCriticalRegion@Base 6
+ thread_entryPoint@Base 6
+ thread_exitCriticalRegion@Base 6
+ thread_inCriticalRegion@Base 6
+ thread_init@Base 6
+ thread_isMainThread@Base 6
+ thread_joinAll@Base 6
+ thread_processGCMarks@Base 6
+ thread_resumeAll@Base 6
+ thread_resumeHandler@Base 6
+ thread_scanAll@Base 6
+ thread_scanAllType@Base 6
+ thread_setGCSignals@Base 6
+ thread_setThis@Base 6
+ thread_stackBottom@Base 6
+ thread_stackTop@Base 6
+ thread_suspendAll@Base 6
+ thread_suspendHandler@Base 6
+ thread_term@Base 6
+ tipc_addr@Base 6
+ tipc_cluster@Base 6
+ tipc_node@Base 6
+ tipc_zone@Base 6
--- gcc-6-6.3.0.orig/debian/libgphobos.symbols.rtarm32
+++ gcc-6-6.3.0/debian/libgphobos.symbols.rtarm32
@@ -0,0 +1,3329 @@
+ LOG_MASK@Base 6
+ LOG_UPTO@Base 6
+ S_TYPEISMQ@Base 6
+ S_TYPEISSEM@Base 6
+ S_TYPEISSHM@Base 6
+ _D102TypeInfo_S2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ2DG6__initZ@Base 6
+ _D109TypeInfo_S4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D10TypeInfo_C6__initZ@Base 6
+ _D10TypeInfo_C6__vtblZ@Base 6
+ _D10TypeInfo_C7__ClassZ@Base 6
+ _D10TypeInfo_D6__initZ@Base 6
+ _D10TypeInfo_D6__vtblZ@Base 6
+ _D10TypeInfo_D7__ClassZ@Base 6
+ _D10TypeInfo_P6__initZ@Base 6
+ _D10TypeInfo_P6__vtblZ@Base 6
+ _D10TypeInfo_P7__ClassZ@Base 6
+ _D10TypeInfo_a6__initZ@Base 6
+ _D10TypeInfo_a6__vtblZ@Base 6
+ _D10TypeInfo_a7__ClassZ@Base 6
+ _D10TypeInfo_b6__initZ@Base 6
+ _D10TypeInfo_b6__vtblZ@Base 6
+ _D10TypeInfo_b7__ClassZ@Base 6
+ _D10TypeInfo_c6__initZ@Base 6
+ _D10TypeInfo_c6__vtblZ@Base 6
+ _D10TypeInfo_c7__ClassZ@Base 6
+ _D10TypeInfo_d6__initZ@Base 6
+ _D10TypeInfo_d6__vtblZ@Base 6
+ _D10TypeInfo_d7__ClassZ@Base 6
+ _D10TypeInfo_e6__initZ@Base 6
+ _D10TypeInfo_e6__vtblZ@Base 6
+ _D10TypeInfo_e7__ClassZ@Base 6
+ _D10TypeInfo_f6__initZ@Base 6
+ _D10TypeInfo_f6__vtblZ@Base 6
+ _D10TypeInfo_f7__ClassZ@Base 6
+ _D10TypeInfo_g6__initZ@Base 6
+ _D10TypeInfo_g6__vtblZ@Base 6
+ _D10TypeInfo_g7__ClassZ@Base 6
+ _D10TypeInfo_h6__initZ@Base 6
+ _D10TypeInfo_h6__vtblZ@Base 6
+ _D10TypeInfo_h7__ClassZ@Base 6
+ _D10TypeInfo_i6__initZ@Base 6
+ _D10TypeInfo_i6__vtblZ@Base 6
+ _D10TypeInfo_i7__ClassZ@Base 6
+ _D10TypeInfo_j6__initZ@Base 6
+ _D10TypeInfo_j6__vtblZ@Base 6
+ _D10TypeInfo_j7__ClassZ@Base 6
+ _D10TypeInfo_k6__initZ@Base 6
+ _D10TypeInfo_k6__vtblZ@Base 6
+ _D10TypeInfo_k7__ClassZ@Base 6
+ _D10TypeInfo_l6__initZ@Base 6
+ _D10TypeInfo_l6__vtblZ@Base 6
+ _D10TypeInfo_l7__ClassZ@Base 6
+ _D10TypeInfo_m6__initZ@Base 6
+ _D10TypeInfo_m6__vtblZ@Base 6
+ _D10TypeInfo_m7__ClassZ@Base 6
+ _D10TypeInfo_o6__initZ@Base 6
+ _D10TypeInfo_o6__vtblZ@Base 6
+ _D10TypeInfo_o7__ClassZ@Base 6
+ _D10TypeInfo_p6__initZ@Base 6
+ _D10TypeInfo_p6__vtblZ@Base 6
+ _D10TypeInfo_p7__ClassZ@Base 6
+ _D10TypeInfo_q6__initZ@Base 6
+ _D10TypeInfo_q6__vtblZ@Base 6
+ _D10TypeInfo_q7__ClassZ@Base 6
+ _D10TypeInfo_r6__initZ@Base 6
+ _D10TypeInfo_r6__vtblZ@Base 6
+ _D10TypeInfo_r7__ClassZ@Base 6
+ _D10TypeInfo_s6__initZ@Base 6
+ _D10TypeInfo_s6__vtblZ@Base 6
+ _D10TypeInfo_s7__ClassZ@Base 6
+ _D10TypeInfo_t6__initZ@Base 6
+ _D10TypeInfo_t6__vtblZ@Base 6
+ _D10TypeInfo_t7__ClassZ@Base 6
+ _D10TypeInfo_u6__initZ@Base 6
+ _D10TypeInfo_u6__vtblZ@Base 6
+ _D10TypeInfo_u7__ClassZ@Base 6
+ _D10TypeInfo_v6__initZ@Base 6
+ _D10TypeInfo_v6__vtblZ@Base 6
+ _D10TypeInfo_v7__ClassZ@Base 6
+ _D10TypeInfo_w6__initZ@Base 6
+ _D10TypeInfo_w6__vtblZ@Base 6
+ _D10TypeInfo_w7__ClassZ@Base 6
+ _D11TypeInfo_AC6__initZ@Base 6
+ _D11TypeInfo_AC6__vtblZ@Base 6
+ _D11TypeInfo_AC7__ClassZ@Base 6
+ _D11TypeInfo_Aa6__initZ@Base 6
+ _D11TypeInfo_Aa6__vtblZ@Base 6
+ _D11TypeInfo_Aa7__ClassZ@Base 6
+ _D11TypeInfo_Ab6__initZ@Base 6
+ _D11TypeInfo_Ab6__vtblZ@Base 6
+ _D11TypeInfo_Ab7__ClassZ@Base 6
+ _D11TypeInfo_Ac6__initZ@Base 6
+ _D11TypeInfo_Ac6__vtblZ@Base 6
+ _D11TypeInfo_Ac7__ClassZ@Base 6
+ _D11TypeInfo_Ad6__initZ@Base 6
+ _D11TypeInfo_Ad6__vtblZ@Base 6
+ _D11TypeInfo_Ad7__ClassZ@Base 6
+ _D11TypeInfo_Ae6__initZ@Base 6
+ _D11TypeInfo_Ae6__vtblZ@Base 6
+ _D11TypeInfo_Ae7__ClassZ@Base 6
+ _D11TypeInfo_Af6__initZ@Base 6
+ _D11TypeInfo_Af6__vtblZ@Base 6
+ _D11TypeInfo_Af7__ClassZ@Base 6
+ _D11TypeInfo_Ag6__initZ@Base 6
+ _D11TypeInfo_Ag6__vtblZ@Base 6
+ _D11TypeInfo_Ag7__ClassZ@Base 6
+ _D11TypeInfo_Ah6__initZ@Base 6
+ _D11TypeInfo_Ah6__vtblZ@Base 6
+ _D11TypeInfo_Ah7__ClassZ@Base 6
+ _D11TypeInfo_Ai6__initZ@Base 6
+ _D11TypeInfo_Ai6__vtblZ@Base 6
+ _D11TypeInfo_Ai7__ClassZ@Base 6
+ _D11TypeInfo_Aj6__initZ@Base 6
+ _D11TypeInfo_Aj6__vtblZ@Base 6
+ _D11TypeInfo_Aj7__ClassZ@Base 6
+ _D11TypeInfo_Ak6__initZ@Base 6
+ _D11TypeInfo_Ak6__vtblZ@Base 6
+ _D11TypeInfo_Ak7__ClassZ@Base 6
+ _D11TypeInfo_Al6__initZ@Base 6
+ _D11TypeInfo_Al6__vtblZ@Base 6
+ _D11TypeInfo_Al7__ClassZ@Base 6
+ _D11TypeInfo_Am6__initZ@Base 6
+ _D11TypeInfo_Am6__vtblZ@Base 6
+ _D11TypeInfo_Am7__ClassZ@Base 6
+ _D11TypeInfo_Ao6__initZ@Base 6
+ _D11TypeInfo_Ao6__vtblZ@Base 6
+ _D11TypeInfo_Ao7__ClassZ@Base 6
+ _D11TypeInfo_Ap6__initZ@Base 6
+ _D11TypeInfo_Ap6__vtblZ@Base 6
+ _D11TypeInfo_Ap7__ClassZ@Base 6
+ _D11TypeInfo_Aq6__initZ@Base 6
+ _D11TypeInfo_Aq6__vtblZ@Base 6
+ _D11TypeInfo_Aq7__ClassZ@Base 6
+ _D11TypeInfo_Ar6__initZ@Base 6
+ _D11TypeInfo_Ar6__vtblZ@Base 6
+ _D11TypeInfo_Ar7__ClassZ@Base 6
+ _D11TypeInfo_As6__initZ@Base 6
+ _D11TypeInfo_As6__vtblZ@Base 6
+ _D11TypeInfo_As7__ClassZ@Base 6
+ _D11TypeInfo_At6__initZ@Base 6
+ _D11TypeInfo_At6__vtblZ@Base 6
+ _D11TypeInfo_At7__ClassZ@Base 6
+ _D11TypeInfo_Au6__initZ@Base 6
+ _D11TypeInfo_Au6__vtblZ@Base 6
+ _D11TypeInfo_Au7__ClassZ@Base 6
+ _D11TypeInfo_Av6__initZ@Base 6
+ _D11TypeInfo_Av6__vtblZ@Base 6
+ _D11TypeInfo_Av7__ClassZ@Base 6
+ _D11TypeInfo_Aw6__initZ@Base 6
+ _D11TypeInfo_Aw6__vtblZ@Base 6
+ _D11TypeInfo_Aw7__ClassZ@Base 6
+ _D11TypeInfo_Oa6__initZ@Base 6
+ _D11TypeInfo_Ou6__initZ@Base 6
+ _D11TypeInfo_xa6__initZ@Base 6
+ _D11TypeInfo_xb6__initZ@Base 6
+ _D11TypeInfo_xf6__initZ@Base 6
+ _D11TypeInfo_xh6__initZ@Base 6
+ _D11TypeInfo_xk6__initZ@Base 6
+ _D11TypeInfo_xt6__initZ@Base 6
+ _D11TypeInfo_xv6__initZ@Base 6
+ _D11TypeInfo_ya6__initZ@Base 6
+ _D11TypeInfo_yk6__initZ@Base 6
+ _D127TypeInfo_E3gcc3deh22__gdc_personality_implFiibPS3gcc6unwind3arm21_Unwind_Control_BlockPS3gcc6unwind3arm15_Unwind_ContextZ5Found6__initZ@Base 6.2.1-1ubuntu2
+ _D12TypeInfo_AOa6__initZ@Base 6
+ _D12TypeInfo_AOu6__initZ@Base 6
+ _D12TypeInfo_Axa6__initZ@Base 6
+ _D12TypeInfo_Axa6__vtblZ@Base 6
+ _D12TypeInfo_Axa7__ClassZ@Base 6
+ _D12TypeInfo_Axv6__initZ@Base 6
+ _D12TypeInfo_Aya6__initZ@Base 6
+ _D12TypeInfo_Aya6__vtblZ@Base 6
+ _D12TypeInfo_Aya7__ClassZ@Base 6
+ _D12TypeInfo_G4h6__initZ@Base 6.2.1-1ubuntu2
+ _D12TypeInfo_OAa6__initZ@Base 6
+ _D12TypeInfo_OAu6__initZ@Base 6
+ _D12TypeInfo_Pxv6__initZ@Base 6
+ _D12TypeInfo_xAa6__initZ@Base 6
+ _D12TypeInfo_xAv6__initZ@Base 6
+ _D12TypeInfo_xPv6__initZ@Base 6
+ _D12TypeInfo_yAa6__initZ@Base 6
+ _D13TypeInfo_AxPv6__initZ@Base 6
+ _D13TypeInfo_AyAa6__initZ@Base 6
+ _D13TypeInfo_Enum6__initZ@Base 6
+ _D13TypeInfo_Enum6__vtblZ@Base 6
+ _D13TypeInfo_Enum7__ClassZ@Base 6
+ _D13TypeInfo_xAPv6__initZ@Base 6
+ _D13TypeInfo_xG4h6__initZ@Base 6.2.1-1ubuntu2
+ _D143TypeInfo_S2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__initZ@Base 6
+ _D14TypeInfo_Array6__initZ@Base 6
+ _D14TypeInfo_Array6__vtblZ@Base 6
+ _D14TypeInfo_Array7__ClassZ@Base 6
+ _D14TypeInfo_Class6__initZ@Base 6
+ _D14TypeInfo_Class6__vtblZ@Base 6
+ _D14TypeInfo_Class7__ClassZ@Base 6
+ _D14TypeInfo_Const6__initZ@Base 6
+ _D14TypeInfo_Const6__vtblZ@Base 6
+ _D14TypeInfo_Const7__ClassZ@Base 6
+ _D14TypeInfo_Inout6__initZ@Base 6
+ _D14TypeInfo_Inout6__vtblZ@Base 6
+ _D14TypeInfo_Inout7__ClassZ@Base 6
+ _D14TypeInfo_Tuple6__initZ@Base 6
+ _D14TypeInfo_Tuple6__vtblZ@Base 6
+ _D14TypeInfo_Tuple7__ClassZ@Base 6
+ _D15TypeInfo_Shared6__initZ@Base 6
+ _D15TypeInfo_Shared6__vtblZ@Base 6
+ _D15TypeInfo_Shared7__ClassZ@Base 6
+ _D15TypeInfo_Struct6__initZ@Base 6
+ _D15TypeInfo_Struct6__vtblZ@Base 6
+ _D15TypeInfo_Struct7__ClassZ@Base 6
+ _D15TypeInfo_Vector6__initZ@Base 6
+ _D15TypeInfo_Vector6__vtblZ@Base 6
+ _D15TypeInfo_Vector7__ClassZ@Base 6
+ _D16TypeInfo_Pointer6__initZ@Base 6
+ _D16TypeInfo_Pointer6__vtblZ@Base 6
+ _D16TypeInfo_Pointer7__ClassZ@Base 6
+ _D16TypeInfo_Typedef6__initZ@Base 6
+ _D16TypeInfo_Typedef6__vtblZ@Base 6
+ _D16TypeInfo_Typedef7__ClassZ@Base 6
+ _D17TypeInfo_Delegate6__initZ@Base 6
+ _D17TypeInfo_Delegate6__vtblZ@Base 6
+ _D17TypeInfo_Delegate7__ClassZ@Base 6
+ _D17TypeInfo_Function6__initZ@Base 6
+ _D17TypeInfo_Function6__vtblZ@Base 6
+ _D17TypeInfo_Function7__ClassZ@Base 6
+ _D18TypeInfo_Interface6__initZ@Base 6
+ _D18TypeInfo_Interface6__vtblZ@Base 6
+ _D18TypeInfo_Interface7__ClassZ@Base 6
+ _D18TypeInfo_Invariant6__initZ@Base 6
+ _D18TypeInfo_Invariant6__vtblZ@Base 6
+ _D18TypeInfo_Invariant7__ClassZ@Base 6
+ _D19TypeInfo_S2gc2gc2GC6__initZ@Base 6
+ _D20TypeInfo_S2gc2gc3Gcx6__initZ@Base 6
+ _D20TypeInfo_S2rt3aaA2AA6__initZ@Base 6
+ _D20TypeInfo_StaticArray6__initZ@Base 6
+ _D20TypeInfo_StaticArray6__vtblZ@Base 6
+ _D20TypeInfo_StaticArray7__ClassZ@Base 6
+ _D20TypeInfo_xC8TypeInfo6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4List6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4Pool6__initZ@Base 6
+ _D21TypeInfo_S2gc2gc4Root6__initZ@Base 6
+ _D22TypeInfo_FNbC6ObjectZv6__initZ@Base 6
+ _D22TypeInfo_S2gc2gc5Range6__initZ@Base 6
+ _D22TypeInfo_S2rt3aaA4Impl6__initZ@Base 6
+ _D22TypeInfo_xS2gc2gc4List6__initZ@Base 6
+ _D22TypeInfo_xS2gc2gc4Root6__initZ@Base 6
+ _D23TypeInfo_DFNbC6ObjectZv6__initZ@Base 6
+ _D23TypeInfo_PxS2gc2gc4List6__initZ@Base 6
+ _D23TypeInfo_S2rt3aaA5Range6__initZ@Base 6
+ _D23TypeInfo_xPS2gc2gc4List6__initZ@Base 6
+ _D23TypeInfo_xS2gc2gc5Range6__initZ@Base 6
+ _D24TypeInfo_AxPS2gc2gc4List6__initZ@Base 6
+ _D24TypeInfo_S2rt3aaA6Bucket6__initZ@Base 6
+ _D24TypeInfo_S2rt5tlsgc4Data6__initZ@Base 6
+ _D24TypeInfo_xDFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_AssociativeArray6__initZ@Base 6
+ _D25TypeInfo_AssociativeArray6__vtblZ@Base 6
+ _D25TypeInfo_AssociativeArray7__ClassZ@Base 6
+ _D25TypeInfo_AxDFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_G8PxS2gc2gc4List6__initZ@Base 6
+ _D25TypeInfo_S2gc4bits6GCBits6__initZ@Base 6
+ _D25TypeInfo_S2gc5proxy5Proxy6__initZ@Base 6
+ _D25TypeInfo_S4core6memory2GC6__initZ@Base 6
+ _D25TypeInfo_S6object7AARange6__initZ@Base 6
+ _D25TypeInfo_xADFNbC6ObjectZv6__initZ@Base 6
+ _D25TypeInfo_xG8PS2gc2gc4List6__initZ@Base 6
+ _D25TypeInfo_xS2rt3aaA6Bucket6__initZ@Base 6
+ _D26TypeInfo_AxS2rt3aaA6Bucket6__initZ@Base 6
+ _D26TypeInfo_S2rt6dmain25CArgs6__initZ@Base 6
+ _D26TypeInfo_xAS2rt3aaA6Bucket6__initZ@Base 6
+ _D27TypeInfo_S2gc5stats7GCStats6__initZ@Base 6
+ _D27TypeInfo_S2gc6config6Config6__initZ@Base 6
+ _D27TypeInfo_S6object9Interface6__initZ@Base 6
+ _D27TypeInfo_S6object9__va_list6__initZ@Base 6.2.1-1ubuntu2
+ _D27TypeInfo_xC14TypeInfo_Class6__initZ@Base 6
+ _D28TypeInfo_E2rt3aaA4Impl5Flags6__initZ@Base 6
+ _D28TypeInfo_S2rt8lifetime5Array6__initZ@Base 6
+ _D28TypeInfo_S3gcc3deh9FuncTable6__initZ@Base 6
+ _D28TypeInfo_S4core4stdc4time2tm6__initZ@Base 6
+ _D28TypeInfo_S4core4time7FracSec6__initZ@Base 6
+ _D28TypeInfo_xC15TypeInfo_Struct6__initZ@Base 6
+ _D28TypeInfo_xC6object9Throwable6__initZ@Base 6
+ _D29TypeInfo_S4core4time8Duration6__initZ@Base 6
+ _D29TypeInfo_S4core7runtime5CArgs6__initZ@Base 6
+ _D29TypeInfo_S6object10ModuleInfo6__initZ@Base 6
+ _D29TypeInfo_xE2rt3aaA4Impl5Flags6__initZ@Base 6
+ _D29TypeInfo_yS3gcc3deh9FuncTable6__initZ@Base 6
+ _D2gc2gc10extendTimel@Base 6
+ _D2gc2gc10mallocTimel@Base 6
+ _D2gc2gc10notbinsizeyG11k@Base 6
+ _D2gc2gc10numExtendsl@Base 6
+ _D2gc2gc10numMallocsl@Base 6
+ _D2gc2gc11numReallocsl@Base 6
+ _D2gc2gc11reallocTimel@Base 6
+ _D2gc2gc11recoverTimeS4core4time8Duration@Base 6
+ _D2gc2gc12__ModuleInfoZ@Base 6
+ _D2gc2gc12maxPauseTimeS4core4time8Duration@Base 6
+ _D2gc2gc12sentinel_addFNbPvZPv@Base 6
+ _D2gc2gc12sentinel_subFNbPvZPv@Base 6
+ _D2gc2gc13maxPoolMemoryk@Base 6
+ _D2gc2gc13sentinel_initFNbPvkZv@Base 6
+ _D2gc2gc14SENTINEL_EXTRAxk@Base 6
+ _D2gc2gc14numCollectionsk@Base 6
+ _D2gc2gc15LargeObjectPool10allocPagesMFNbkZk@Base 6
+ _D2gc2gc15LargeObjectPool13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc15LargeObjectPool13updateOffsetsMFNbkZv@Base 6
+ _D2gc2gc15LargeObjectPool6__initZ@Base 6
+ _D2gc2gc15LargeObjectPool7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc15LargeObjectPool7getSizeMxFNbPvZk@Base 6
+ _D2gc2gc15LargeObjectPool9freePagesMFNbkkZv@Base 6
+ _D2gc2gc15SmallObjectPool13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc15SmallObjectPool6__initZ@Base 6
+ _D2gc2gc15SmallObjectPool7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc15SmallObjectPool7getSizeMxFNbPvZk@Base 6
+ _D2gc2gc15SmallObjectPool9allocPageMFNbhZPS2gc2gc4List@Base 6
+ _D2gc2gc18sentinel_InvariantFNbxPvZv@Base 6
+ _D2gc2gc2GC10freeNoSyncMFNbPvZv@Base 6
+ _D2gc2gc2GC10initializeMFZv@Base 6
+ _D2gc2gc2GC10removeRootMFNbPvZv@Base 6
+ _D2gc2gc2GC11checkNoSyncMFNbPvZv@Base 6
+ _D2gc2gc2GC11fullCollectMFNbZk@Base 6
+ _D2gc2gc2GC11queryNoSyncMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc2GC11removeRangeMFNbNiPvZv@Base 6
+ _D2gc2gc2GC12addrOfNoSyncMFNbPvZPv@Base 6
+ _D2gc2gc2GC12extendNoSyncMFNbPvkkxC8TypeInfoZk@Base 6
+ _D2gc2gc2GC12mallocNoSyncMFNbkkKkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC12mutexStorageG40v@Base 6
+ _D2gc2gc2GC12rootIterImplMFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2gc2gc2GC12sizeOfNoSyncMFNbPvZk@Base 6
+ _D2gc2gc2GC13rangeIterImplMFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2gc2gc2GC13reallocNoSyncMFNbPvkKkKkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC13reserveNoSyncMFNbkZk@Base 6
+ _D2gc2gc2GC13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc2GC14getStatsNoSyncMFNbJS2gc5stats7GCStatsZv@Base 6
+ _D2gc2gc2GC18fullCollectNoStackMFNbZv@Base 6
+ _D2gc2gc2GC4DtorMFZv@Base 6
+ _D2gc2gc2GC4filePa@Base 6
+ _D2gc2gc2GC4freeMFNbPvZv@Base 6
+ _D2gc2gc2GC4linek@Base 6
+ _D2gc2gc2GC5checkMFNbPvZv@Base 6
+ _D2gc2gc2GC5queryMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc2GC6__initZ@Base 6
+ _D2gc2gc2GC6addrOfMFNbPvZPv@Base 6
+ _D2gc2gc2GC6callocMFNbkkPkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC6configS2gc6config6Config@Base 6
+ _D2gc2gc2GC6enableMFZv@Base 6
+ _D2gc2gc2GC6extendMFNbPvkkxC8TypeInfoZk@Base 6
+ _D2gc2gc2GC6gcLockC2gc2gc7GCMutex@Base 6
+ _D2gc2gc2GC6mallocMFNbkkPkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC6sizeOfMFNbPvZk@Base 6
+ _D2gc2gc2GC7addRootMFNbPvZv@Base 6
+ _D2gc2gc2GC7clrAttrMFNbPvkZk@Base 6
+ _D2gc2gc2GC7disableMFZv@Base 6
+ _D2gc2gc2GC7getAttrMFNbPvZk@Base 6
+ _D2gc2gc2GC7reallocMFNbPvkkPkxC8TypeInfoZPv@Base 6
+ _D2gc2gc2GC7reserveMFNbkZk@Base 6
+ _D2gc2gc2GC7setAttrMFNbPvkZk@Base 6
+ _D2gc2gc2GC8addRangeMFNbNiPvkxC8TypeInfoZv@Base 6
+ _D2gc2gc2GC8getStatsMFNbJS2gc5stats7GCStatsZv@Base 6
+ _D2gc2gc2GC8minimizeMFNbZv@Base 6
+ _D2gc2gc2GC8rootIterMFNaNbNdNiNfZDFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2gc2gc2GC9rangeIterMFNaNbNdNiNfZDFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2gc2gc3Gcx10initializeMFZv@Base 6
+ _D2gc2gc3Gcx10log_mallocMFNbPvkZv@Base 6
+ _D2gc2gc3Gcx10log_parentMFNbPvPvZv@Base 6
+ _D2gc2gc3Gcx10removeRootMFNbPvZv@Base 6
+ _D2gc2gc3Gcx10smallAllocMFNbhKkkZPv@Base 6
+ _D2gc2gc3Gcx11ToScanStack14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack3popMFNbZS2gc2gc5Range@Base 6
+ _D2gc2gc3Gcx11ToScanStack4growMFNbZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack4pushMFNbS2gc2gc5RangeZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack5emptyMxFNbNdZb@Base 6
+ _D2gc2gc3Gcx11ToScanStack5resetMFNbZv@Base 6
+ _D2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D2gc2gc3Gcx11ToScanStack6lengthMxFNbNdZk@Base 6
+ _D2gc2gc3Gcx11ToScanStack7opIndexMNgFNbNckZNgS2gc2gc5Range@Base 6
+ _D2gc2gc3Gcx11ToScanStack8opAssignMFNaNbNcNiNjNeS2gc2gc3Gcx11ToScanStackZS2gc2gc3Gcx11ToScanStack@Base 6
+ _D2gc2gc3Gcx11__fieldDtorMFNbNiZv@Base 6
+ _D2gc2gc3Gcx11__xopEqualsFKxS2gc2gc3GcxKxS2gc2gc3GcxZb@Base 6
+ _D2gc2gc3Gcx11fullcollectMFNbbZk@Base 6
+ _D2gc2gc3Gcx11log_collectMFNbZv@Base 6
+ _D2gc2gc3Gcx11removeRangeMFNbNiPvZv@Base 6
+ _D2gc2gc3Gcx13runFinalizersMFNbxAvZv@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZ11smoothDecayFNbffZf@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZ3maxFNbffZf@Base 6
+ _D2gc2gc3Gcx23updateCollectThresholdsMFNbZv@Base 6
+ _D2gc2gc3Gcx4DtorMFZv@Base 6
+ _D2gc2gc3Gcx4markMFNbPvPvZv@Base 6
+ _D2gc2gc3Gcx5allocMFNbkKkkZPv@Base 6
+ _D2gc2gc3Gcx5sweepMFNbZk@Base 6
+ _D2gc2gc3Gcx6__initZ@Base 6
+ _D2gc2gc3Gcx6lowMemMxFNbNdZb@Base 6
+ _D2gc2gc3Gcx6npoolsMxFNaNbNdZk@Base 6
+ _D2gc2gc3Gcx7addRootMFNbPvZv@Base 6
+ _D2gc2gc3Gcx7getInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc3Gcx7markAllMFNbbZv@Base 6
+ _D2gc2gc3Gcx7newPoolMFNbkbZPS2gc2gc4Pool@Base 6
+ _D2gc2gc3Gcx7prepareMFNbZv@Base 6
+ _D2gc2gc3Gcx7recoverMFNbZk@Base 6
+ _D2gc2gc3Gcx7reserveMFNbkZk@Base 6
+ _D2gc2gc3Gcx8addRangeMFNbNiPvPvxC8TypeInfoZv@Base 6
+ _D2gc2gc3Gcx8bigAllocMFNbkKkkxC8TypeInfoZPv@Base 6
+ _D2gc2gc3Gcx8binTablexG2049g@Base 6
+ _D2gc2gc3Gcx8ctfeBinsFNbZG2049g@Base 6
+ _D2gc2gc3Gcx8findBaseMFNbPvZPv@Base 6
+ _D2gc2gc3Gcx8findPoolMFNaNbPvZPS2gc2gc4Pool@Base 6
+ _D2gc2gc3Gcx8findSizeMFNbPvZk@Base 6
+ _D2gc2gc3Gcx8isMarkedMFNbPvZi@Base 6
+ _D2gc2gc3Gcx8log_freeMFNbPvZv@Base 6
+ _D2gc2gc3Gcx8log_initMFNbZv@Base 6
+ _D2gc2gc3Gcx8minimizeMFNbZv@Base 6
+ _D2gc2gc3Gcx8opAssignMFNbNcNiNjS2gc2gc3GcxZS2gc2gc3Gcx@Base 6
+ _D2gc2gc3Gcx9InvariantMxFZv@Base 6
+ _D2gc2gc3Gcx9__xtoHashFNbNeKxS2gc2gc3GcxZk@Base 6
+ _D2gc2gc3Gcx9allocPageMFNbhZPS2gc2gc4List@Base 6
+ _D2gc2gc3setFNaNbNiKG8kkZv@Base 6
+ _D2gc2gc4List6__initZ@Base 6
+ _D2gc2gc4Pool10initializeMFNbkbZv@Base 6
+ _D2gc2gc4Pool12freePageBitsMFNbkKxG8kZv@Base 6
+ _D2gc2gc4Pool4DtorMFNbZv@Base 6
+ _D2gc2gc4Pool6__initZ@Base 6
+ _D2gc2gc4Pool6isFreeMxFNaNbNdZb@Base 6
+ _D2gc2gc4Pool7clrBitsMFNbkkZv@Base 6
+ _D2gc2gc4Pool7getBitsMFNbkZk@Base 6
+ _D2gc2gc4Pool7setBitsMFNbkkZv@Base 6
+ _D2gc2gc4Pool9InvariantMxFZv@Base 6
+ _D2gc2gc4Pool9pagenumOfMxFNbPvZk@Base 6
+ _D2gc2gc4Pool9slGetInfoMFNbPvZS4core6memory8BlkInfo_@Base 6
+ _D2gc2gc4Pool9slGetSizeMFNbPvZk@Base 6
+ _D2gc2gc4Root6__initZ@Base 6
+ _D2gc2gc5Range6__initZ@Base 6
+ _D2gc2gc7GCMutex4lockMFNbNiNeZv@Base 6
+ _D2gc2gc7GCMutex6__ctorMFNbNeZC2gc2gc7GCMutex@Base 6
+ _D2gc2gc7GCMutex6__initZ@Base 6
+ _D2gc2gc7GCMutex6__vtblZ@Base 6
+ _D2gc2gc7GCMutex6unlockMFNbNiNeZv@Base 6
+ _D2gc2gc7GCMutex7__ClassZ@Base 6
+ _D2gc2gc7binsizeyG11k@Base 6
+ _D2gc2gc8freeTimel@Base 6
+ _D2gc2gc8lockTimel@Base 6
+ _D2gc2gc8markTimeS4core4time8Duration@Base 6
+ _D2gc2gc8numFreesl@Base 6
+ _D2gc2gc8prepTimeS4core4time8Duration@Base 6
+ _D2gc2gc9GCVERSIONxk@Base 6
+ _D2gc2gc9numOthersl@Base 6
+ _D2gc2gc9otherTimel@Base 6
+ _D2gc2gc9sweepTimeS4core4time8Duration@Base 6
+ _D2gc2os10isLowOnMemFNbNikZb@Base 6
+ _D2gc2os10os_mem_mapFNbkZPv@Base 6
+ _D2gc2os12__ModuleInfoZ@Base 6
+ _D2gc2os12os_mem_unmapFNbPvkZi@Base 6
+ _D2gc4bits12__ModuleInfoZ@Base 6
+ _D2gc4bits6GCBits3setMFNbkZi@Base 6
+ _D2gc4bits6GCBits4DtorMFNbZv@Base 6
+ _D2gc4bits6GCBits4copyMFNbPS2gc4bits6GCBitsZv@Base 6
+ _D2gc4bits6GCBits4testMxFNbkZk@Base 6
+ _D2gc4bits6GCBits4zeroMFNbZv@Base 6
+ _D2gc4bits6GCBits5allocMFNbkZv@Base 6
+ _D2gc4bits6GCBits5clearMFNbkZi@Base 6
+ _D2gc4bits6GCBits6__initZ@Base 6
+ _D2gc4bits6GCBits6nwordsMxFNaNbNdZk@Base 6
+ _D2gc5proxy12__ModuleInfoZ@Base 6
+ _D2gc5proxy3_gcS2gc2gc2GC@Base 6
+ _D2gc5proxy5Proxy6__initZ@Base 6
+ _D2gc5proxy5proxyPS2gc5proxy5Proxy@Base 6
+ _D2gc5proxy5pthisS2gc5proxy5Proxy@Base 6
+ _D2gc5proxy9initProxyFZv@Base 6
+ _D2gc5stats12__ModuleInfoZ@Base 6
+ _D2gc5stats7GCStats6__initZ@Base 6
+ _D2gc6config10parseErrorFNbNixAaxAaxAaZb@Base 6
+ _D2gc6config12__ModuleInfoZ@Base 6
+ _D2gc6config13__T5parseHTbZ5parseFNbNiAxaKAxaKbZb@Base 6
+ _D2gc6config13__T5parseHTfZ5parseFNbNiAxaKAxaKfZb@Base 6
+ _D2gc6config13__T5parseHThZ5parseFNbNiAxaKAxaKhZb@Base 6
+ _D2gc6config13__T5parseHTkZ5parseFNbNiAxaKAxaKkZb@Base 6
+ _D2gc6config18__T4skipS7isspaceZ4skipFNaNbNiNfANgaZANga@Base 6
+ _D2gc6config18__T4skipS7isspaceZ4skipFNbNiANgaZ18__T9__lambda2TNgaZ9__lambda2FNaNbNiNfNgaZb@Base 6
+ _D2gc6config3minFNbNikkZk@Base 6
+ _D2gc6config6Config10initializeMFNbNiZb@Base 6
+ _D2gc6config6Config11__xopEqualsFKxS2gc6config6ConfigKxS2gc6config6ConfigZb@Base 6
+ _D2gc6config6Config12parseOptionsMFNbNiAxaZ18__T9__lambda2TNgaZ9__lambda2FNaNbNiNfNgaZb@Base 6
+ _D2gc6config6Config12parseOptionsMFNbNiAxaZb@Base 6
+ _D2gc6config6Config4helpMFNbNiZv@Base 6
+ _D2gc6config6Config6__initZ@Base 6
+ _D2gc6config6Config9__xtoHashFNbNeKxS2gc6config6ConfigZk@Base 6
+ _D2gc6config8optErrorFNbNixAaxAaZb@Base 6
+ _D2gc9pooltable12__ModuleInfoZ@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable4DtorMFNbNiZv@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6insertMFNbNiPS2gc2gc4PoolZb@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7maxAddrMxFNaNbNdNiNfZPxg@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7minAddrMxFNaNbNdNiNfZPxg@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7opIndexMNgFNaNbNcNikZNgPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable7opSliceMNgFNaNbNikkZANgPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8findPoolMFNaNbNiPvZPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8minimizeMFNaNbZ4swapFNaNbNiNfKPS2gc2gc4PoolKPS2gc2gc4PoolZv@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable8minimizeMFNaNbZAPS2gc2gc4Pool@Base 6
+ _D2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable9InvariantMxFNaNbNiZv@Base 6
+ _D2rt11arrayassign12__ModuleInfoZ@Base 6
+ _D2rt12sections_osx12__ModuleInfoZ@Base 6
+ _D2rt14sections_win3212__ModuleInfoZ@Base 6
+ _D2rt14sections_win6412__ModuleInfoZ@Base 6
+ _D2rt16sections_android12__ModuleInfoZ@Base 6
+ _D2rt16sections_solaris12__ModuleInfoZ@Base 6
+ _D2rt19sections_elf_shared10_rtLoadingb@Base 6
+ _D2rt19sections_elf_shared11_loadedDSOsS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt19sections_elf_shared11getTLSRangeFkkZAv@Base 6
+ _D2rt19sections_elf_shared12__ModuleInfoZ@Base 6
+ _D2rt19sections_elf_shared12_handleToDSOS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab@Base 6
+ _D2rt19sections_elf_shared12decThreadRefFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared12dsoForHandleFNbPvZPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt19sections_elf_shared12finiSectionsFZv@Base 6
+ _D2rt19sections_elf_shared12incThreadRefFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared12initSectionsFZv@Base 6
+ _D2rt19sections_elf_shared12scanSegmentsFKxS4core3sys5linux4link12dl_phdr_infoPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared13findThreadDSOFPS2rt19sections_elf_shared3DSOZPS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt19sections_elf_shared13finiTLSRangesFPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZv@Base 6
+ _D2rt19sections_elf_shared13handleForAddrFPvZPv@Base 6
+ _D2rt19sections_elf_shared13handleForNameFNbxPaZPv@Base 6
+ _D2rt19sections_elf_shared13initTLSRangesFZPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt19sections_elf_shared13runFinalizersFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared13scanTLSRangesFNbPS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayMDFNbPvPvZvZv@Base 6
+ _D2rt19sections_elf_shared15CompilerDSOData6__initZ@Base 6
+ _D2rt19sections_elf_shared15getDependenciesFNbKxS4core3sys5linux4link12dl_phdr_infoKS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZv@Base 6
+ _D2rt19sections_elf_shared15setDSOForHandleFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt19sections_elf_shared16linkMapForHandleFNbPvZPS4core3sys5linux4link8link_map@Base 6
+ _D2rt19sections_elf_shared16registerGCRangesFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared17_handleToDSOMutexS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D2rt19sections_elf_shared17unsetDSOForHandleFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ2DG6__initZ@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZ8callbackUNbNiPS4core3sys5linux4link12dl_phdr_infokPvZi@Base 6
+ _D2rt19sections_elf_shared18findDSOInfoForAddrFNbNixPvPS4core3sys5linux4link12dl_phdr_infoZb@Base 6
+ _D2rt19sections_elf_shared18findSegmentForAddrFNbNiKxS4core3sys5linux4link12dl_phdr_infoxPvPS4core3sys5linux3elf10Elf32_PhdrZb@Base 6
+ _D2rt19sections_elf_shared18pinLoadedLibrariesFNbZPv@Base 6
+ _D2rt19sections_elf_shared18unregisterGCRangesFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared20runModuleDestructorsFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared20unpinLoadedLibrariesFNbPvZv@Base 6
+ _D2rt19sections_elf_shared21_isRuntimeInitializedb@Base 6
+ _D2rt19sections_elf_shared21checkModuleCollisionsFNbKxS4core3sys5linux4link12dl_phdr_infoxAPyS6object10ModuleInfoZv@Base 6
+ _D2rt19sections_elf_shared21runModuleConstructorsFPS2rt19sections_elf_shared3DSObZv@Base 6
+ _D2rt19sections_elf_shared22cleanupLoadedLibrariesFZv@Base 6
+ _D2rt19sections_elf_shared22inheritLoadedLibrariesFPvZv@Base 6
+ _D2rt19sections_elf_shared33__T7toRangeTyS3gcc3deh9FuncTableZ7toRangeFNaNbNiPyS3gcc3deh9FuncTablePyS3gcc3deh9FuncTableZAyS3gcc3deh9FuncTable@Base 6
+ _D2rt19sections_elf_shared35__T7toRangeTyPS6object10ModuleInfoZ7toRangeFNaNbNiPyPS6object10ModuleInfoPyPS6object10ModuleInfoZAyPS6object10ModuleInfo@Base 6
+ _D2rt19sections_elf_shared3DSO11__fieldDtorMFNbZv@Base 6
+ _D2rt19sections_elf_shared3DSO11__invariantMxFZv@Base 6
+ _D2rt19sections_elf_shared3DSO11__xopEqualsFKxS2rt19sections_elf_shared3DSOKxS2rt19sections_elf_shared3DSOZb@Base 6
+ _D2rt19sections_elf_shared3DSO11moduleGroupMNgFNcNdZNgS2rt5minfo11ModuleGroup@Base 6
+ _D2rt19sections_elf_shared3DSO12__invariant1MxFZv@Base 6
+ _D2rt19sections_elf_shared3DSO14opApplyReverseFMDFKS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D2rt19sections_elf_shared3DSO7modulesMxFNdZAyPS6object10ModuleInfo@Base 6
+ _D2rt19sections_elf_shared3DSO7opApplyFMDFKS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt19sections_elf_shared3DSO8ehTablesMxFNdZAyS3gcc3deh9FuncTable@Base 6
+ _D2rt19sections_elf_shared3DSO8gcRangesMNgFNdZANgAv@Base 6
+ _D2rt19sections_elf_shared3DSO8opAssignMFNbNcNjS2rt19sections_elf_shared3DSOZS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt19sections_elf_shared3DSO9__xtoHashFNbNeKxS2rt19sections_elf_shared3DSOZk@Base 6
+ _D2rt19sections_elf_shared7dsoNameFNbxPaZAxa@Base 6
+ _D2rt19sections_elf_shared7freeDSOFPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt19sections_elf_shared8prognameFNbNdNiZPxa@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO11__xopEqualsFKxS2rt19sections_elf_shared9ThreadDSOKxS2rt19sections_elf_shared9ThreadDSOZb@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO6__initZ@Base 6
+ _D2rt19sections_elf_shared9ThreadDSO9__xtoHashFNbNeKxS2rt19sections_elf_shared9ThreadDSOZk@Base 6
+ _D2rt19sections_elf_shared9finiLocksFZv@Base 6
+ _D2rt19sections_elf_shared9initLocksFZv@Base 6
+ _D2rt19sections_elf_shared9tls_index6__initZ@Base 6
+ _D2rt3aaA10__T3maxTkZ3maxFNaNbNiNfkkZk@Base 6
+ _D2rt3aaA10__T3minTkZ3minFNaNbNiNfkkZk@Base 6
+ _D2rt3aaA10allocEntryFxPS2rt3aaA4ImplxPvZPv@Base 6
+ _D2rt3aaA11fakeEntryTIFxC8TypeInfoxC8TypeInfoZ6tiNameyAa@Base 6
+ _D2rt3aaA11fakeEntryTIFxC8TypeInfoxC8TypeInfoZC15TypeInfo_Struct@Base 6
+ _D2rt3aaA12__ModuleInfoZ@Base 6
+ _D2rt3aaA12allocBucketsFNaNbNekZAS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA2AA5emptyMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA2AA6__initZ@Base 6
+ _D2rt3aaA3mixFNaNbNiNfkZk@Base 6
+ _D2rt3aaA4Impl11__xopEqualsFKxS2rt3aaA4ImplKxS2rt3aaA4ImplZb@Base 6
+ _D2rt3aaA4Impl14findSlotInsertMNgFNaNbNikZPNgS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA4Impl14findSlotLookupMNgFkxPvxC8TypeInfoZPNgS2rt3aaA6Bucket@Base 6
+ _D2rt3aaA4Impl3dimMxFNaNbNdNiZk@Base 6
+ _D2rt3aaA4Impl4growMFxC8TypeInfoZv@Base 6
+ _D2rt3aaA4Impl4maskMxFNaNbNdNiZk@Base 6
+ _D2rt3aaA4Impl6__ctorMFNcxC25TypeInfo_AssociativeArraykZS2rt3aaA4Impl@Base 6
+ _D2rt3aaA4Impl6__initZ@Base 6
+ _D2rt3aaA4Impl6lengthMxFNaNbNdNiZk@Base 6
+ _D2rt3aaA4Impl6resizeMFNaNbkZv@Base 6
+ _D2rt3aaA4Impl6shrinkMFxC8TypeInfoZv@Base 6
+ _D2rt3aaA4Impl9__xtoHashFNbNeKxS2rt3aaA4ImplZk@Base 6
+ _D2rt3aaA5Range6__initZ@Base 6
+ _D2rt3aaA6Bucket5emptyMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6Bucket6__initZ@Base 6
+ _D2rt3aaA6Bucket6filledMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6Bucket7deletedMxFNaNbNdNiZb@Base 6
+ _D2rt3aaA6talignFNaNbNiNfkkZk@Base 6
+ _D2rt3aaA7hasDtorFxC8TypeInfoZb@Base 6
+ _D2rt3aaA8calcHashFxPvxC8TypeInfoZk@Base 6
+ _D2rt3aaA8nextpow2FNaNbNixkZk@Base 6
+ _D2rt3aaA9entryDtorFPvxC15TypeInfo_StructZv@Base 6
+ _D2rt3adi12__ModuleInfoZ@Base 6
+ _D2rt3adi19__T11mallocUTF32TaZ11mallocUTF32FNixAaZAw@Base 6
+ _D2rt3adi19__T11mallocUTF32TuZ11mallocUTF32FNixAuZAw@Base 6
+ _D2rt3deh12__ModuleInfoZ@Base 6
+ _D2rt3obj12__ModuleInfoZ@Base 6
+ _D2rt4util3utf10UTF8strideyAi@Base 6
+ _D2rt4util3utf10toUCSindexFxAakZk@Base 6
+ _D2rt4util3utf10toUCSindexFxAukZk@Base 6
+ _D2rt4util3utf10toUCSindexFxAwkZk@Base 6
+ _D2rt4util3utf10toUTFindexFxAakZk@Base 6
+ _D2rt4util3utf10toUTFindexFxAukZk@Base 6
+ _D2rt4util3utf10toUTFindexFxAwkZk@Base 6
+ _D2rt4util3utf12__ModuleInfoZ@Base 6
+ _D2rt4util3utf12isValidDcharFwZb@Base 6
+ _D2rt4util3utf17__T8validateTAyaZ8validateFxAyaZv@Base 6
+ _D2rt4util3utf17__T8validateTAyuZ8validateFxAyuZv@Base 6
+ _D2rt4util3utf17__T8validateTAywZ8validateFxAywZv@Base 6
+ _D2rt4util3utf6decodeFxAaKkZw@Base 6
+ _D2rt4util3utf6decodeFxAuKkZw@Base 6
+ _D2rt4util3utf6decodeFxAwKkZw@Base 6
+ _D2rt4util3utf6encodeFKAawZv@Base 6
+ _D2rt4util3utf6encodeFKAuwZv@Base 6
+ _D2rt4util3utf6encodeFKAwwZv@Base 6
+ _D2rt4util3utf6strideFxAakZk@Base 6
+ _D2rt4util3utf6strideFxAukZk@Base 6
+ _D2rt4util3utf6strideFxAwkZk@Base 6
+ _D2rt4util3utf6toUTF8FAyaZAya@Base 6
+ _D2rt4util3utf6toUTF8FNkJG4awZAa@Base 6
+ _D2rt4util3utf6toUTF8FxAuZAya@Base 6
+ _D2rt4util3utf6toUTF8FxAwZAya@Base 6
+ _D2rt4util3utf7toUTF16FAyuZAyu@Base 6
+ _D2rt4util3utf7toUTF16FNkJG2uwZAu@Base 6
+ _D2rt4util3utf7toUTF16FxAaZAyu@Base 6
+ _D2rt4util3utf7toUTF16FxAwZAyu@Base 6
+ _D2rt4util3utf7toUTF32FAywZAyw@Base 6
+ _D2rt4util3utf7toUTF32FxAaZAyw@Base 6
+ _D2rt4util3utf7toUTF32FxAuZAyw@Base 6
+ _D2rt4util3utf8toUTF16zFxAaZPxu@Base 6
+ _D2rt4util4hash12__ModuleInfoZ@Base 6
+ _D2rt4util4hash6hashOfFNaNbNePxvkkZ9get16bitsFNaNbPxhZk@Base 6
+ _D2rt4util4hash6hashOfFNaNbNePxvkkZk@Base 6
+ _D2rt4util5array12__ModuleInfoZ@Base 6
+ _D2rt4util5array17_enforceNoOverlapFNbNfxAaxPvxPvxkZv@Base 6
+ _D2rt4util5array18_enforceSameLengthFNbNfxAaxkxkZv@Base 6
+ _D2rt4util5array27enforceRawArraysConformableFNbNfxAaxkxAvxAvxbZv@Base 6
+ _D2rt4util6random12__ModuleInfoZ@Base 6
+ _D2rt4util6random6Rand4811defaultSeedMFNbZv@Base 6
+ _D2rt4util6random6Rand484seedMFNbkZv@Base 6
+ _D2rt4util6random6Rand485frontMFNbNdNiZk@Base 6
+ _D2rt4util6random6Rand486__initZ@Base 6
+ _D2rt4util6random6Rand486opCallMFNbNiZk@Base 6
+ _D2rt4util6random6Rand488popFrontMFNbNiZv@Base 6
+ _D2rt4util6string12__ModuleInfoZ@Base 6
+ _D2rt4util6string16sizeToTempStringFNaNbNexkAaZAa@Base 6
+ _D2rt4util6string16uintToTempStringFNaNbNexkAaZAa@Base 6
+ _D2rt4util6string17ulongToTempStringFNaNbNexmAaZAa@Base 6
+ _D2rt4util6string29__T21_unsignedToTempStringTkZ21_unsignedToTempStringFNaNbNiNexkAaZAa@Base 6
+ _D2rt4util6string29__T21_unsignedToTempStringTmZ21_unsignedToTempStringFNaNbNiNexmAaZAa@Base 6
+ _D2rt4util6string7dstrcmpFNaNbNexAaxAaZi@Base 6
+ _D2rt4util8typeinfo12__ModuleInfoZ@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ6equalsFNaNbNfAcAcZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ6hashOfFNaNbNfAcZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTcZ7compareFNaNbNfAcAcZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ6equalsFNaNbNfAdAdZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ6hashOfFNaNbNfAdZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTdZ7compareFNaNbNfAdAdZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ6equalsFNaNbNfAeAeZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ6hashOfFNaNbNfAeZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTeZ7compareFNaNbNfAeAeZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ6equalsFNaNbNfAfAfZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ6hashOfFNaNbNfAfZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTfZ7compareFNaNbNfAfAfZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ6equalsFNaNbNfAqAqZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ6hashOfFNaNbNfAqZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTqZ7compareFNaNbNfAqAqZi@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ6equalsFNaNbNfArArZb@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ6hashOfFNaNbNfArZk@Base 6
+ _D2rt4util8typeinfo12__T5ArrayTrZ7compareFNaNbNfArArZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ6equalsFNaNbNfccZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ6hashOfFNaNbNecZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTcZ7compareFNaNbNfccZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ6equalsFNaNbNfddZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ6hashOfFNaNbNedZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTdZ7compareFNaNbNfddZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ6equalsFNaNbNfeeZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ6hashOfFNaNbNeeZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTeZ7compareFNaNbNfeeZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ6equalsFNaNbNfffZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ6hashOfFNaNbNefZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTfZ7compareFNaNbNfffZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ6equalsFNaNbNfqqZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ6hashOfFNaNbNeqZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTqZ7compareFNaNbNfqqZi@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ6equalsFNaNbNfrrZb@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ6hashOfFNaNbNerZk@Base 6
+ _D2rt4util8typeinfo15__T8FloatingTrZ7compareFNaNbNfrrZi@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array4backMNgFNaNbNcNdNiZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array4swapMFNaNbNiNfKS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5ArrayZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5frontMNgFNaNbNcNdNiNfZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6__initZ@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opIndexMNgFNaNbNcNikZNgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opSliceMNgFNaNbNiZANgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7opSliceMNgFNaNbNikkZANgPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array8opAssignMFNbNcNjS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5ArrayZS2rt4util9container5array100__T5ArrayTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ5Array@Base 6
+ _D2rt4util9container5array12__ModuleInfoZ@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array16__T10insertBackZ10insertBackMFNbAvZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array4backMNgFNaNbNcNdNiZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array4swapMFNaNbNiNfKS2rt4util9container5array13__T5ArrayTAvZ5ArrayZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5frontMNgFNaNbNcNdNiNfZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opIndexMNgFNaNbNcNikZNgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opSliceMNgFNaNbNiZANgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7opSliceMNgFNaNbNikkZANgAv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array13__T5ArrayTAvZ5Array8opAssignMFNbNcNjS2rt4util9container5array13__T5ArrayTAvZ5ArrayZS2rt4util9container5array13__T5ArrayTAvZ5Array@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array16__T10insertBackZ10insertBackMFNbKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array4backMNgFNaNbNcNdNiZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array4swapMFNaNbNiNfKS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5frontMNgFNaNbNcNdNiNfZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opIndexMNgFNaNbNcNikZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opSliceMNgFNaNbNiZANgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7opSliceMNgFNaNbNikkZANgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array8opAssignMFNbNcNjS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5ArrayZS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array16__T10insertBackZ10insertBackMFNbS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array4backMNgFNaNbNcNdNiZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array4swapMFNaNbNiNfKS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5frontMNgFNaNbNcNdNiNfZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array5resetMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__dtorMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__initZ@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6lengthMFNbNdkZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6removeMFNbkZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opIndexMNgFNaNbNcNikZNgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opSliceMNgFNaNbNiZANgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7opSliceMNgFNaNbNikkZANgS2rt19sections_elf_shared9ThreadDSO@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array7popBackMFNbZv@Base 6
+ _D2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array8opAssignMFNbNcNjS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5ArrayZS2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array@Base 6
+ _D2rt4util9container5treap12__ModuleInfoZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap10initializeMFNbZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap13opApplyHelperFNbxPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeMDFNbKxS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node11__xopEqualsFKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZb@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node9__xtoHashFNbNeKxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZk@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__dtorMFNbNiZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6insertMFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeS2gc2gc4RootZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6insertMFNbNiS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6removeFNbNiPPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6removeMFNbNiS2gc2gc4RootZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7opApplyMFNbMDFNbKS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7opApplyMxFNbMDFNbKxS2gc2gc4RootZiZi@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7rotateLFNaNbNiNfPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap7rotateRFNaNbNiNfPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap8freeNodeFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap8opAssignMFNbNcNiNjS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5TreapZS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9allocNodeMFNbNiS2gc2gc4RootZPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9removeAllFNbNiPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap9removeAllMFNbNiZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap10initializeMFNbZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap13opApplyHelperFNbxPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeMDFNbKxS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node11__xopEqualsFKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZb@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node9__xtoHashFNbNeKxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZk@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__dtorMFNbNiZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6insertMFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeS2gc2gc5RangeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6insertMFNbNiS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6removeFNbNiPPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6removeMFNbNiS2gc2gc5RangeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7opApplyMFNbMDFNbKS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7opApplyMxFNbMDFNbKxS2gc2gc5RangeZiZi@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7rotateLFNaNbNiNfPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap7rotateRFNaNbNiNfPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap8freeNodeFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap8opAssignMFNbNcNiNjS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5TreapZS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9allocNodeMFNbNiS2gc2gc5RangeZPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9removeAllFNbNiPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4NodeZv@Base 6
+ _D2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap9removeAllMFNbNiZv@Base 6
+ _D2rt4util9container6common101__T7destroyTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common102__T7destroyTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common105__T10initializeTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ10initializeFNaNbNiKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common106__T10initializeTPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ10initializeFNaNbNiNfKPS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D2rt4util9container6common12__ModuleInfoZ@Base 6
+ _D2rt4util9container6common15__T7destroyTAvZ7destroyFNaNbNiNfKAvZv@Base 6
+ _D2rt4util9container6common19__T10initializeTAvZ10initializeFNaNbNiNfKAvZv@Base 6
+ _D2rt4util9container6common43__T7destroyTPS2rt19sections_elf_shared3DSOZ7destroyFNaNbNiNfKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container6common47__T10initializeTPS2rt19sections_elf_shared3DSOZ10initializeFNaNbNiNfKPS2rt19sections_elf_shared3DSOZv@Base 6
+ _D2rt4util9container6common48__T7destroyTS2rt19sections_elf_shared9ThreadDSOZ7destroyFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container6common52__T10initializeTS2rt19sections_elf_shared9ThreadDSOZ10initializeFNaNbNiKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D2rt4util9container6common7xmallocFNbNikZPv@Base 6
+ _D2rt4util9container6common8xreallocFNbPvkZPv@Base 6
+ _D2rt4util9container7hashtab12__ModuleInfoZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab10__aggrDtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab11__fieldDtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab13opIndexAssignMFNbPS2rt19sections_elf_shared3DSOPvZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab14__aggrPostblitMFNaNbNiNfZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab18ensureNotInOpApplyMFNaNbNiNfZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab3getMFNbPvZPPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node6__initZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4growMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4maskMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab5emptyMxFNaNbNdNiNfZb@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab5resetMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__dtorMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__initZ@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6hashOfFNaNbKxPvZk@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6lengthMxFNaNbNdNiNfZk@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6opIn_rMNgFNaNbxPvZPNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6removeMFNbxPvZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6shrinkMFNbZv@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab7opApplyMFMDFKPvKPS2rt19sections_elf_shared3DSOZiZi@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab7opIndexMNgFNaNbNcPvZNgPS2rt19sections_elf_shared3DSO@Base 6
+ _D2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab8opAssignMFNbNcNjS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTabZS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab@Base 6
+ _D2rt5cast_12__ModuleInfoZ@Base 6
+ _D2rt5minfo11ModuleGroup11__xopEqualsFKxS2rt5minfo11ModuleGroupKxS2rt5minfo11ModuleGroupZb@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsCtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsCtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsDtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup11runTlsDtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup4freeMFZv@Base 6
+ _D2rt5minfo11ModuleGroup6__ctorMFNcAyPS6object10ModuleInfoZS2rt5minfo11ModuleGroup@Base 6
+ _D2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D2rt5minfo11ModuleGroup7modulesMxFNdZAyPS6object10ModuleInfo@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZ37__T9__lambda2TPyS6object10ModuleInfoZ9__lambda2FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runCtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runDtorsMFZ37__T9__lambda1TPyS6object10ModuleInfoZ9__lambda1FNaNbPyS6object10ModuleInfoZPFZv@Base 6
+ _D2rt5minfo11ModuleGroup8runDtorsMFZv@Base 6
+ _D2rt5minfo11ModuleGroup9__xtoHashFNbNeKxS2rt5minfo11ModuleGroupZk@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ10findModuleMFxPS6object10ModuleInfoZi@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec11__xopEqualsFKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecZb@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec3modMFNdZPyS6object10ModuleInfo@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec6__initZ@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec9__xtoHashFNbNeKxS2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRecZk@Base 6
+ _D2rt5minfo11ModuleGroup9sortCtorsMFZv@Base 6
+ _D2rt5minfo12__ModuleInfoZ@Base 6
+ _D2rt5minfo17moduleinfos_applyFMDFyPS6object10ModuleInfoZiZi@Base 6
+ _D2rt5qsort12__ModuleInfoZ@Base 6
+ _D2rt5qsort7_adSortUAvC8TypeInfoZ3cmpUxPvxPvPvZi@Base 6
+ _D2rt5tlsgc12__ModuleInfoZ@Base 6
+ _D2rt5tlsgc14processGCMarksFNbPvMDFNbPvZiZv@Base 6
+ _D2rt5tlsgc4Data6__initZ@Base 6
+ _D2rt5tlsgc4initFZPv@Base 6
+ _D2rt5tlsgc4scanFNbPvMDFNbPvPvZvZv@Base 6
+ _D2rt5tlsgc7destroyFPvZv@Base 6
+ _D2rt6aApply12__ModuleInfoZ@Base 6
+ _D2rt6config12__ModuleInfoZ@Base 6
+ _D2rt6config13rt_linkOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6config15rt_configOptionFNbNiAyaMDFNbNiAyaZAyabZAya@Base 6
+ _D2rt6config16rt_cmdlineOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6config16rt_envvarsOptionFNbNiAyaMDFNbNiAyaZAyaZAya@Base 6
+ _D2rt6dmain210_initCountOk@Base 6
+ _D2rt6dmain211_d_run_mainUiPPaPUAAaZiZ7tryExecMFMDFZvZv@Base 6
+ _D2rt6dmain212__ModuleInfoZ@Base 6
+ _D2rt6dmain212traceHandlerPFPvZC6object9Throwable9TraceInfo@Base 6
+ _D2rt6dmain215formatThrowableFC6object9ThrowableDFNbxAaZvZv@Base 6
+ _D2rt6dmain25CArgs6__initZ@Base 6
+ _D2rt6dmain26_cArgsS2rt6dmain25CArgs@Base 6
+ _D2rt6dmain27_d_argsAAya@Base 6
+ _D2rt6memory12__ModuleInfoZ@Base 6
+ _D2rt6memory16initStaticDataGCFZv@Base 6
+ _D2rt7aApplyR12__ModuleInfoZ@Base 6
+ _D2rt7switch_12__ModuleInfoZ@Base 6
+ _D2rt8arraycat12__ModuleInfoZ@Base 6
+ _D2rt8lifetime10__arrayPadFNaNbNekxC8TypeInfoZk@Base 6
+ _D2rt8lifetime10__blkcacheFNbNdZPS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime11hasPostblitFxC8TypeInfoZb@Base 6
+ _D2rt8lifetime11newCapacityFkkZk@Base 6
+ _D2rt8lifetime12__ModuleInfoZ@Base 6
+ _D2rt8lifetime12__arrayAllocFNaNbkxC8TypeInfoxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__arrayAllocFkKS4core6memory8BlkInfo_xC8TypeInfoxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__arrayStartFNaNbS4core6memory8BlkInfo_ZPv@Base 6
+ _D2rt8lifetime12__doPostblitFPvkxC8TypeInfoZv@Base 6
+ _D2rt8lifetime12__getBlkInfoFNbPvZPS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime12__nextBlkIdxi@Base 6
+ _D2rt8lifetime12_staticDtor1FZv@Base 6
+ _D2rt8lifetime14collectHandlerPFC6ObjectZb@Base 6
+ _D2rt8lifetime14finalize_arrayFPvkxC15TypeInfo_StructZv@Base 6
+ _D2rt8lifetime14processGCMarksFNbPS4core6memory8BlkInfo_MDFNbPvZiZv@Base 6
+ _D2rt8lifetime15finalize_array2FNbPvkZv@Base 6
+ _D2rt8lifetime15finalize_structFNbPvkZv@Base 6
+ _D2rt8lifetime18__arrayAllocLengthFNaNbKS4core6memory8BlkInfo_xC8TypeInfoZk@Base 6
+ _D2rt8lifetime18__blkcache_storagePS4core6memory8BlkInfo_@Base 6
+ _D2rt8lifetime18structTypeInfoSizeFNaNbNixC8TypeInfoZk@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock6__initZ@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock6__vtblZ@Base 6
+ _D2rt8lifetime20ArrayAllocLengthLock7__ClassZ@Base 6
+ _D2rt8lifetime20__insertBlkInfoCacheFNbS4core6memory8BlkInfo_PS4core6memory8BlkInfo_Zv@Base 6
+ _D2rt8lifetime21__setArrayAllocLengthFNaNbKS4core6memory8BlkInfo_kbxC8TypeInfokZb@Base 6
+ _D2rt8lifetime23callStructDtorsDuringGCyb@Base 6
+ _D2rt8lifetime26hasArrayFinalizerInSegmentFNbPvkxAvZi@Base 6
+ _D2rt8lifetime27hasStructFinalizerInSegmentFNbPvkxAvZi@Base 6
+ _D2rt8lifetime35__T14_d_newarrayOpTS12_d_newarrayTZ14_d_newarrayOpTFNaNbxC8TypeInfoAkZAv@Base 6
+ _D2rt8lifetime36__T14_d_newarrayOpTS13_d_newarrayiTZ14_d_newarrayOpTFNaNbxC8TypeInfoAkZAv@Base 6
+ _D2rt8lifetime5Array6__initZ@Base 6
+ _D2rt8lifetime9unqualifyFNaNbNiNgC8TypeInfoZNgC8TypeInfo@Base 6
+ _D2rt8monitor_10getMonitorFNaNbC6ObjectZPOS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_10setMonitorFNaNbC6ObjectPOS2rt8monitor_7MonitorZv@Base 6
+ _D2rt8monitor_11unlockMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_12__ModuleInfoZ@Base 6
+ _D2rt8monitor_12destroyMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_12disposeEventFNbPS2rt8monitor_7MonitorC6ObjectZv@Base 6
+ _D2rt8monitor_13deleteMonitorFNbPS2rt8monitor_7MonitorZv@Base 6
+ _D2rt8monitor_13ensureMonitorFNbC6ObjectZPOS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_4gmtxS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D2rt8monitor_5gattrS4core3sys5posix3sys5types19pthread_mutexattr_t@Base 6
+ _D2rt8monitor_7Monitor11__xopEqualsFKxS2rt8monitor_7MonitorKxS2rt8monitor_7MonitorZb@Base 6
+ _D2rt8monitor_7Monitor6__initZ@Base 6
+ _D2rt8monitor_7Monitor9__xtoHashFNbNeKxS2rt8monitor_7MonitorZk@Base 6
+ _D2rt8monitor_7monitorFNaNbNcNdC6ObjectZOPS2rt8monitor_7Monitor@Base 6
+ _D2rt8monitor_9initMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8monitor_9lockMutexFNbPS4core3sys5posix3sys5types15pthread_mutex_tZv@Base 6
+ _D2rt8sections12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo10ti_Acfloat11TypeInfo_Aq8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Acfloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ad8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ap4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo10ti_Adouble11TypeInfo_Ap8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_Adouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4initMxFNaNbNeZ1ryr@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo10ti_cdouble10TypeInfo_r8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_cdouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo10ti_idouble10TypeInfo_p8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo10ti_idouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo11ti_Acdouble11TypeInfo_Ar8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo11ti_Acdouble12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo11ti_delegate10TypeInfo_D7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo11ti_delegate12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C6equalsMxFNexPvxPvZb@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C7compareMxFNexPvxPvZi@Base 6
+ _D2rt8typeinfo4ti_C10TypeInfo_C7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo4ti_C12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo5ti_AC11TypeInfo_AC8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_AC12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Aa8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ab4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ab8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ag8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Ah8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Av4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag11TypeInfo_Av8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Axa4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Axa8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Aya4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo5ti_Ag12TypeInfo_Aya8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo5ti_Ag12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo6ti_int10TypeInfo_i8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo6ti_int12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo6ti_ptr10TypeInfo_P7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo6ti_ptr12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ai8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Ak8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Aw4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo7ti_Aint11TypeInfo_Aw8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_Aint12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_byte10TypeInfo_g8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_byte12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_cent12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4initMxFNaNbNeZ1cya@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_char10TypeInfo_a8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_char12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l6talignMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_long10TypeInfo_l8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_long12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4initMxFNaNbNeZ1rye@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_real10TypeInfo_e8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_real12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_uint10TypeInfo_k8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_uint12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v5flagsMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo7ti_void10TypeInfo_v8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo7ti_void12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Al8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Along11TypeInfo_Am8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Along12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Ae8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Aj4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo8ti_Areal11TypeInfo_Aj8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_Areal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4initMxFNaNbNeZ1ryc@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_creal10TypeInfo_c8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_creal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4initMxFNaNbNeZ1cyw@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_dchar10TypeInfo_w8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_dchar12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4initMxFNaNbNeZ1ryf@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_float10TypeInfo_f8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_float12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ireal10TypeInfo_j8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ireal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_short10TypeInfo_s8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_short12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_b8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_ubyte10TypeInfo_h8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ubyte12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ucent12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m6talignMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_ulong10TypeInfo_m8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo8ti_ulong12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4initMxFNaNbNeZ1cyu@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo8ti_wchar10TypeInfo_u8toStringMxFNaNbNeZAya@Base 6
+ _D2rt8typeinfo8ti_wchar12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Acreal11TypeInfo_Ac8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Acreal12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Af8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Ao4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Afloat11TypeInfo_Ao8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Afloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As6equalsMxFxPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As7getHashMxFNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As8opEqualsMFC6ObjectZb@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_As8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At7compareMxFxPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_At8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_Au4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D2rt8typeinfo9ti_Ashort11TypeInfo_Au8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_Ashort12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4initMxFNaNbNeZ1ryq@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_cfloat10TypeInfo_q8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_cfloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4initMxFNaNbNeZ1ryd@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4initMxFNaNbNiNeZAxv@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d6talignMxFNaNbNdNiNfZk@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_double10TypeInfo_d8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_double12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_ifloat10TypeInfo_o8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_ifloat12__ModuleInfoZ@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t4swapMxFNaNbNePvPvZv@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t5tsizeMxFNaNbNdNiNeZk@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t7compareMxFNaNbNexPvxPvZi@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t7getHashMxFNaNbNexPvZk@Base 6
+ _D2rt8typeinfo9ti_ushort10TypeInfo_t8toStringMxFNaNbNfZAya@Base 6
+ _D2rt8typeinfo9ti_ushort12__ModuleInfoZ@Base 6
+ _D2rt9arraycast12__ModuleInfoZ@Base 6
+ _D2rt9critical_11ensureMutexFNbPOS2rt9critical_18D_CRITICAL_SECTIONZv@Base 6
+ _D2rt9critical_12__ModuleInfoZ@Base 6
+ _D2rt9critical_18D_CRITICAL_SECTION6__initZ@Base 6
+ _D2rt9critical_3gcsOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D2rt9critical_4headOPS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D30TypeInfo_AC4core6thread6Thread6__initZ@Base 6
+ _D30TypeInfo_AyS3gcc3deh9FuncTable6__initZ@Base 6
+ _D30TypeInfo_E4core4time9ClockType6__initZ@Base 6
+ _D30TypeInfo_S2rt8monitor_7Monitor6__initZ@Base 6
+ _D30TypeInfo_yS6object10ModuleInfo6__initZ@Base 6
+ _D31TypeInfo_E4core6thread8IsMarked6__initZ@Base 6
+ _D31TypeInfo_E4core6thread8ScanType6__initZ@Base 6
+ _D31TypeInfo_PyS6object10ModuleInfo6__initZ@Base 6
+ _D31TypeInfo_S4core5cpuid9CacheInfo6__initZ@Base 6
+ _D31TypeInfo_S4core6memory8BlkInfo_6__initZ@Base 6
+ _D31TypeInfo_S4core7runtime7Runtime6__initZ@Base 6
+ _D31TypeInfo_xAyS3gcc3deh9FuncTable6__initZ@Base 6
+ _D31TypeInfo_yPS6object10ModuleInfo6__initZ@Base 6
+ _D32TypeInfo_AyPS6object10ModuleInfo6__initZ@Base 6
+ _D32TypeInfo_C6object6Object7Monitor6__initZ@Base 6
+ _D32TypeInfo_S2rt4util6random6Rand486__initZ@Base 6
+ _D32TypeInfo_S2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D32TypeInfo_S4core4stdc4fenv6fenv_t6__initZ@Base 6
+ _D32TypeInfo_xPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_AxPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_E4core6memory2GC7BlkAttr6__initZ@Base 6
+ _D33TypeInfo_E4core6thread5Fiber4Call6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc15LargeObjectPool6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc15SmallObjectPool6__initZ@Base 6
+ _D33TypeInfo_S2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc5stdio6fpos_t6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc6locale5lconv6__initZ@Base 6
+ _D33TypeInfo_S4core4stdc6stdlib5div_t6__initZ@Base 6
+ _D33TypeInfo_S4core8demangle8Demangle6__initZ@Base 6
+ _D33TypeInfo_S6object14OffsetTypeInfo6__initZ@Base 6
+ _D33TypeInfo_xAPyS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_xAyPS6object10ModuleInfo6__initZ@Base 6
+ _D33TypeInfo_xC6object6Object7Monitor6__initZ@Base 6
+ _D33TypeInfo_xS2rt5minfo11ModuleGroup6__initZ@Base 6
+ _D34TypeInfo_E3gcc6config11ThreadModel6__initZ@Base 6
+ _D34TypeInfo_E4core6thread5Fiber5State6__initZ@Base 6
+ _D34TypeInfo_E4core6thread6Thread4Call6__initZ@Base 6
+ _D34TypeInfo_S4core4stdc6stdlib6ldiv_t6__initZ@Base 6
+ _D34TypeInfo_S4core4time12TickDuration6__initZ@Base 6
+ _D34TypeInfo_xS2gc2gc3Gcx11ToScanStack6__initZ@Base 6
+ _D35TypeInfo_E4core6atomic11MemoryOrder6__initZ@Base 6
+ _D35TypeInfo_S4core3sys5posix3grp5group6__initZ@Base 6
+ _D35TypeInfo_S4core4stdc5stdio8_IO_FILE6__initZ@Base 6
+ _D35TypeInfo_S4core4stdc6stdlib7lldiv_t6__initZ@Base 6
+ _D36TypeInfo_E4core6thread5Fiber7Rethrow6__initZ@Base 6
+ _D36TypeInfo_S3gcc3deh16globalExceptions6__initZ@Base 6
+ _D36TypeInfo_S3gcc3deh16lsda_header_info6__initZ@Base 6
+ _D36TypeInfo_S3gcc9backtrace10SymbolInfo6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix3pwd6passwd6__initZ@Base 6
+ _D36TypeInfo_S4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D37TypeInfo_C6object9Throwable9TraceInfo6__initZ@Base 6
+ _D37TypeInfo_S4core3sys5posix4poll6pollfd6__initZ@Base 6
+ _D37TypeInfo_S4core3sys5posix5fcntl5flock6__initZ@Base 6
+ _D37TypeInfo_S4core4stdc6wchar_9mbstate_t6__initZ@Base 6
+ _D37TypeInfo_S4core6thread6Thread7Context6__initZ@Base 6
+ _D38TypeInfo_S2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D38TypeInfo_S3gcc3deh18d_exception_header6__initZ@Base 6
+ _D38TypeInfo_S4core3sys5linux4link7r_debug6__initZ@Base 6
+ _D38TypeInfo_S4core3sys5posix5netdb6netent6__initZ@Base 6
+ _D38TypeInfo_S4core8internal7convert5Float6__initZ@Base 6
+ _D39TypeInfo_S3gcc9backtrace13SymbolOrError6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Dyn6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Lib6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Rel6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf32_Sym6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Dyn6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Lib6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Rel6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux3elf9Elf64_Sym6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux4link8link_map6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5linux5dlfcn7Dl_info6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix3sys3uio5iovec6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5dlfcn7Dl_info6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5netdb7hostent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5netdb7servent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix5utime7utimbuf6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix6dirent6dirent6__initZ@Base 6
+ _D39TypeInfo_S4core3sys5posix6signal6sigval6__initZ@Base 6
+ _D39TypeInfo_S4core4stdc8inttypes9imaxdiv_t6__initZ@Base 6
+ _D39TypeInfo_xS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D39TypeInfo_xS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D3etc5linux11memoryerror12__ModuleInfoZ@Base 6
+ _D3gcc12libbacktrace12__ModuleInfoZ@Base 6
+ _D3gcc12libbacktrace15backtrace_state6__initZ@Base 6
+ _D3gcc3deh12__ModuleInfoZ@Base 6
+ _D3gcc3deh15__gdc_terminateFZv@Base 6
+ _D3gcc3deh16globalExceptions6__initZ@Base 6
+ _D3gcc3deh16lsda_header_info6__initZ@Base 6
+ _D3gcc3deh17parse_lsda_headerFPS3gcc6unwind3arm15_Unwind_ContextPhPS3gcc3deh16lsda_header_infoZPh@Base 6.2.1-1ubuntu2
+ _D3gcc3deh18__globalExceptionsS3gcc3deh16globalExceptions@Base 6
+ _D3gcc3deh18d_exception_header11__xopEqualsFKxS3gcc3deh18d_exception_headerKxS3gcc3deh18d_exception_headerZb@Base 6
+ _D3gcc3deh18d_exception_header6__initZ@Base 6
+ _D3gcc3deh18d_exception_header9__xtoHashFNbNeKxS3gcc3deh18d_exception_headerZk@Base 6
+ _D3gcc3deh19get_classinfo_entryFPS3gcc3deh16lsda_header_infokZC14TypeInfo_Class@Base 6
+ _D3gcc3deh21__gdc_exception_classxG8a@Base 6.2.1-1ubuntu2
+ _D3gcc3deh21save_caught_exceptionFPS3gcc6unwind3arm21_Unwind_Control_BlockPS3gcc6unwind3arm15_Unwind_ContextiPhkPhZv@Base 6.2.1-1ubuntu2
+ _D3gcc3deh22__gdc_personality_implFiibPS3gcc6unwind3arm21_Unwind_Control_BlockPS3gcc6unwind3arm15_Unwind_ContextZk@Base 6.2.1-1ubuntu2
+ _D3gcc3deh24restore_caught_exceptionFPS3gcc6unwind3arm21_Unwind_Control_BlockKiKPhKkZv@Base 6.2.1-1ubuntu2
+ _D3gcc3deh28get_exception_header_from_ueFPS3gcc6unwind3arm21_Unwind_Control_BlockZPS3gcc3deh18d_exception_header@Base 6.2.1-1ubuntu2
+ _D3gcc3deh9FuncTable6__initZ@Base 6
+ _D3gcc6config12__ModuleInfoZ@Base 6
+ _D3gcc6unwind12__ModuleInfoZ@Base 6
+ _D3gcc6unwind2pe12__ModuleInfoZ@Base 6
+ _D3gcc6unwind2pe12read_sleb128FPhPiZPh@Base 6
+ _D3gcc6unwind2pe12read_uleb128FPhPkZPh@Base 6
+ _D3gcc6unwind2pe18read_encoded_valueFPS3gcc6unwind3arm15_Unwind_ContexthPhPkZPh@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind2pe21base_of_encoded_valueFhPS3gcc6unwind3arm15_Unwind_ContextZk@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind2pe21size_of_encoded_valueFhZk@Base 6
+ _D3gcc6unwind2pe28read_encoded_value_with_baseFhkPhPkZ9unaligned6__initZ@Base 6
+ _D3gcc6unwind2pe28read_encoded_value_with_baseFhkPhPkZPh@Base 6
+ _D3gcc6unwind3arm12__ModuleInfoZ@Base 6
+ _D3gcc6unwind3arm18__gnu_unwind_state6__initZ@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind3arm21_Unwind_Control_Block14_barrier_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind3arm21_Unwind_Control_Block14_cleanup_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind3arm21_Unwind_Control_Block15_unwinder_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind3arm21_Unwind_Control_Block6__initZ@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind3arm21_Unwind_Control_Block9_pr_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D3gcc6unwind7generic12__ModuleInfoZ@Base 6
+ _D3gcc7atomics12__ModuleInfoZ@Base 6
+ _D3gcc8builtins12__ModuleInfoZ@Base 6
+ _D3gcc8builtins9__va_list6__initZ@Base 6.2.1-1ubuntu2
+ _D3gcc9attribute12__ModuleInfoZ@Base 6
+ _D3gcc9backtrace10SymbolInfo6__initZ@Base 6
+ _D3gcc9backtrace10formatLineFxS3gcc9backtrace10SymbolInfoKG512aZAa@Base 6
+ _D3gcc9backtrace12LibBacktrace11initializedb@Base 6
+ _D3gcc9backtrace12LibBacktrace16initLibBacktraceFZv@Base 6
+ _D3gcc9backtrace12LibBacktrace5statePS3gcc12libbacktrace15backtrace_state@Base 6
+ _D3gcc9backtrace12LibBacktrace6__ctorMFiZC3gcc9backtrace12LibBacktrace@Base 6
+ _D3gcc9backtrace12LibBacktrace6__initZ@Base 6
+ _D3gcc9backtrace12LibBacktrace6__vtblZ@Base 6
+ _D3gcc9backtrace12LibBacktrace7__ClassZ@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFDFKkKS3gcc9backtrace13SymbolOrErrorZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKkKxAaZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKxAaZiZi@Base 6
+ _D3gcc9backtrace12LibBacktrace8toStringMxFZAya@Base 6
+ _D3gcc9backtrace12__ModuleInfoZ@Base 6
+ _D3gcc9backtrace13SymbolOrError6__initZ@Base 6
+ _D3gcc9backtrace18SymbolCallbackInfo5resetMFZv@Base 6
+ _D3gcc9backtrace18SymbolCallbackInfo6__initZ@Base 6
+ _D3gcc9backtrace19SymbolCallbackInfo26__initZ@Base 6
+ _D40TypeInfo_PxS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D40TypeInfo_PxS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5linux4tipc9tipc_name6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix3sys3msg6msgbuf6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix5netdb8addrinfo6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix5netdb8protoent6__initZ@Base 6
+ _D40TypeInfo_S4core3sys5posix6signal7stack_t6__initZ@Base 6
+ _D40TypeInfo_xPS2rt19sections_elf_shared3DSO6__initZ@Base 6
+ _D40TypeInfo_xPS3gcc3deh18d_exception_header6__initZ@Base 6
+ _D41TypeInfo_E4core8demangle8Demangle7AddType6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Ehdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Move6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Nhdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Phdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Rela6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf32_Shdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Ehdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Move6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Nhdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Phdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Rela6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5linux3elf10Elf64_Shdr6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys3msg7msginfo6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigevent6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigset_t6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8sigstack6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix6signal8timespec6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix7termios7termios6__initZ@Base 6
+ _D41TypeInfo_S4core3sys5posix9semaphore5sem_t6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux3elf11Elf32_gptab6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux3elf11Elf_Options6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5linux4tipc10tipc_event6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3ipc8ipc_perm6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3msg8msqid_ds6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys3shm8shmid_ds6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys4time7timeval6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix3sys5ioctl6termio6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix4time10itimerspec6__initZ@Base 6
+ _D42TypeInfo_S4core3sys5posix6signal9siginfo_t6__initZ@Base 6
+ _D42TypeInfo_xE4core8demangle8Demangle7AddType6__initZ@Base 6
+ _D43TypeInfo_E4core3sys5posix3sys4wait8idtype_t6__initZ@Base 6
+ _D43TypeInfo_E4core3sys5posix3sys7statvfs5FFlag6__initZ@Base 6
+ _D43TypeInfo_S2rt9critical_18D_CRITICAL_SECTION6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf32_Verdef6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf32_auxv_t6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf64_Verdef6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux3elf12Elf64_auxv_t6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux4tipc11tipc_portid6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux4tipc11tipc_subscr6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux5dlfcn10Dl_serinfo6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5linux5dlfcn10Dl_serpath6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys5ioctl7winsize6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6select6fd_set6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6socket6linger6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix3sys6socket6msghdr6__initZ@Base 6
+ _D43TypeInfo_S4core3sys5posix4arpa4inet7in_addr6__initZ@Base 6
+ _D44TypeInfo_S2rt19sections_elf_shared9ThreadDSO6__initZ@Base 6
+ _D44TypeInfo_S2rt19sections_elf_shared9tls_index6__initZ@Base 6
+ _D44TypeInfo_S3gcc9backtrace18SymbolCallbackInfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_RegInfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Syminfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Verdaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Vernaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf32_Verneed6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Syminfo6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Verdaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Vernaux6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux3elf13Elf64_Verneed6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux4link12dl_phdr_info6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5linux5epoll11epoll_event6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys4time9itimerval6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys5ioctl8termios26__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix3sys6socket7cmsghdr6__initZ@Base 6
+ _D44TypeInfo_S4core3sys5posix5sched11sched_param6__initZ@Base 6
+ _D45TypeInfo_E4core8demangle8Demangle10IsDelegate6__initZ@Base 6
+ _D45TypeInfo_E4core8internal7convert11FloatFormat6__initZ@Base 6
+ _D45TypeInfo_E6object14TypeInfo_Class10ClassFlags6__initZ@Base 6
+ _D45TypeInfo_S3gcc12libbacktrace15backtrace_state6__initZ@Base 6
+ _D45TypeInfo_S3gcc6unwind3arm18__gnu_unwind_state6__initZ@Base 6.2.1-1ubuntu2
+ _D45TypeInfo_S3gcc9backtrace19SymbolCallbackInfo26__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf14Elf_Options_Hw6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf9Elf32_Dyn5_d_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux3elf9Elf64_Dyn5_d_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux4tipc13tipc_name_seq6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5linux5epoll12epoll_data_t6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys2un11sockaddr_un6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys6socket8sockaddr6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys7utsname7utsname6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys8resource6rlimit6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix3sys8resource6rusage6__initZ@Base 6
+ _D45TypeInfo_S4core3sys5posix6signal11sigaction_t6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5linux3sys7sysinfo8sysinfo_6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix7netinet3in_8in6_addr6__initZ@Base 6
+ _D46TypeInfo_S4core3sys5posix8ucontext10sigcontext6__initZ@Base 6.2.1-1ubuntu2
+ _D46TypeInfo_S4core3sys5posix8ucontext10ucontext_t6__initZ@Base 6
+ _D46TypeInfo_S4core4stdc6wchar_9mbstate_t8___value6__initZ@Base 6
+ _D46TypeInfo_S4core4sync5mutex5Mutex12MonitorProxy6__initZ@Base 6
+ _D47TypeInfo_E6object15TypeInfo_Struct11StructFlags6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix3sys7statvfs9statvfs_t6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix6setjmp13__jmp_buf_tag6__initZ@Base 6
+ _D47TypeInfo_S4core3sys5posix7netinet3in_9ipv6_mreq6__initZ@Base 6
+ _D48TypeInfo_S3gcc6unwind3arm21_Unwind_Control_Block6__initZ@Base 6.2.1-1ubuntu2
+ _D49TypeInfo_S4core3sys5linux3elf12Elf32_auxv_t5_a_un6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5linux3elf12Elf64_auxv_t5_a_un6__initZ@Base 6
+ _D49TypeInfo_S4core3sys5posix3net3if_14if_nameindex_t6__initZ@Base 6
+ _D49TypeInfo_xS3gcc6unwind3arm21_Unwind_Control_Block6__initZ@Base 6.2.1-1ubuntu2
+ _D4core10checkedint12__ModuleInfoZ@Base 6
+ _D4core10checkedint4addsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4addsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4adduFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4adduFNaNbNiNfmmKbZm@Base 6
+ _D4core10checkedint4mulsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4mulsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4muluFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4muluFNaNbNiNfmmKbZm@Base 6
+ _D4core10checkedint4negsFNaNbNiNfiKbZi@Base 6
+ _D4core10checkedint4negsFNaNbNiNflKbZl@Base 6
+ _D4core10checkedint4subsFNaNbNiNfiiKbZi@Base 6
+ _D4core10checkedint4subsFNaNbNiNfllKbZl@Base 6
+ _D4core10checkedint4subuFNaNbNiNfkkKbZk@Base 6
+ _D4core10checkedint4subuFNaNbNiNfmmKbZm@Base 6
+ _D4core3sys5linux3elf10Elf32_Ehdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Move6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Nhdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Phdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Rela6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf32_Shdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Ehdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Move6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Nhdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Phdr6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Rela6__initZ@Base 6
+ _D4core3sys5linux3elf10Elf64_Shdr6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab10_gt_header6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf32_gptab9_gt_entry6__initZ@Base 6
+ _D4core3sys5linux3elf11Elf_Options6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_Verdef6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_auxv_t5_a_un6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf32_auxv_t6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_Verdef6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_auxv_t5_a_un6__initZ@Base 6
+ _D4core3sys5linux3elf12Elf64_auxv_t6__initZ@Base 6
+ _D4core3sys5linux3elf12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3elf13Elf32_RegInfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Syminfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Verdaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Vernaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf32_Verneed6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Syminfo6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Verdaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Vernaux6__initZ@Base 6
+ _D4core3sys5linux3elf13Elf64_Verneed6__initZ@Base 6
+ _D4core3sys5linux3elf14Elf_Options_Hw6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Dyn5_d_un6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Dyn6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Lib6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Rel6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf32_Sym6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Dyn5_d_un6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Dyn6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Lib6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Rel6__initZ@Base 6
+ _D4core3sys5linux3elf9Elf64_Sym6__initZ@Base 6
+ _D4core3sys5linux3sys4mman12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys5xattr12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7inotify12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7inotify13inotify_event6__initZ@Base 6
+ _D4core3sys5linux3sys7sysinfo12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys7sysinfo8sysinfo_6__initZ@Base 6
+ _D4core3sys5linux3sys8signalfd12__ModuleInfoZ@Base 6
+ _D4core3sys5linux3sys8signalfd16signalfd_siginfo6__initZ@Base 6
+ _D4core3sys5linux4link12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4link12dl_phdr_info6__initZ@Base 6
+ _D4core3sys5linux4link7r_debug6__initZ@Base 6
+ _D4core3sys5linux4link8link_map6__initZ@Base 6
+ _D4core3sys5linux4time12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4tipc10tipc_event6__initZ@Base 6
+ _D4core3sys5linux4tipc11tipc_portid6__initZ@Base 6
+ _D4core3sys5linux4tipc11tipc_subscr6__initZ@Base 6
+ _D4core3sys5linux4tipc12__ModuleInfoZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc4Addr4Name6__initZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc4Addr6__initZ@Base 6
+ _D4core3sys5linux4tipc13sockaddr_tipc6__initZ@Base 6
+ _D4core3sys5linux4tipc13tipc_name_seq6__initZ@Base 6
+ _D4core3sys5linux4tipc9tipc_name6__initZ@Base 6
+ _D4core3sys5linux5dlfcn10Dl_serinfo6__initZ@Base 6
+ _D4core3sys5linux5dlfcn10Dl_serpath6__initZ@Base 6
+ _D4core3sys5linux5dlfcn12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5dlfcn7Dl_info6__initZ@Base 6
+ _D4core3sys5linux5epoll11epoll_event6__initZ@Base 6
+ _D4core3sys5linux5epoll12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5epoll12epoll_data_t6__initZ@Base 6
+ _D4core3sys5linux5errno12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5stdio12__ModuleInfoZ@Base 6
+ _D4core3sys5linux5stdio21cookie_io_functions_t6__initZ@Base 6
+ _D4core3sys5linux6config12__ModuleInfoZ@Base 6
+ _D4core3sys5linux7termios12__ModuleInfoZ@Base 6
+ _D4core3sys5linux8execinfo12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3grp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3grp5group6__initZ@Base 6
+ _D4core3sys5posix3net3if_12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3net3if_14if_nameindex_t6__initZ@Base 6
+ _D4core3sys5posix3pwd12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3pwd6passwd6__initZ@Base 6
+ _D4core3sys5posix3sys2un11sockaddr_un6__initZ@Base 6
+ _D4core3sys5posix3sys2un12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3ipc12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3ipc8ipc_perm6__initZ@Base 6
+ _D4core3sys5posix3sys3msg12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3msg6msgbuf6__initZ@Base 6
+ _D4core3sys5posix3sys3msg7msginfo6__initZ@Base 6
+ _D4core3sys5posix3sys3msg8msqid_ds6__initZ@Base 6
+ _D4core3sys5posix3sys3shm12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3shm8shmid_ds6__initZ@Base 6
+ _D4core3sys5posix3sys3uio12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys3uio5iovec6__initZ@Base 6
+ _D4core3sys5posix3sys4mman12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4stat12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4stat6stat_t6__initZ@Base 6
+ _D4core3sys5posix3sys4stat7S_ISBLKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISCHRFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISDIRFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISLNKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat7S_ISREGFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISFIFOFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISSOCKFNbNikZb@Base 6
+ _D4core3sys5posix3sys4stat8S_ISTYPEFNbNikkZb@Base 6
+ _D4core3sys5posix3sys4time12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4time7timeval6__initZ@Base 6
+ _D4core3sys5posix3sys4time9itimerval6__initZ@Base 6
+ _D4core3sys5posix3sys4wait10WIFSTOPPEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys4wait10__WTERMSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait11WEXITSTATUSFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait11WIFSIGNALEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys4wait12WIFCONTINUEDFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys4wait8WSTOPSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait8WTERMSIGFNbNiiZi@Base 6
+ _D4core3sys5posix3sys4wait9WIFEXITEDFNbNiiZb@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTiZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTkZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOCTnZ4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IORTkZ4_IORFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl11__T4_IOWTiZ4_IOWFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys5ioctl3_IOFNbNiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IOCTS4core3sys5posix3sys5ioctl8termios2Z4_IOCFNaNbNiNfiiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IORTS4core3sys5posix3sys5ioctl8termios2Z4_IORFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl45__T4_IOWTS4core3sys5posix3sys5ioctl8termios2Z4_IOWFNaNbNiNfiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl6termio6__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl7_IOC_NRFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl7winsize6__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl8_IOC_DIRFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl8termios26__initZ@Base 6
+ _D4core3sys5posix3sys5ioctl9_IOC_SIZEFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5ioctl9_IOC_TYPEFNbNiiZi@Base 6
+ _D4core3sys5posix3sys5types12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys5types14pthread_attr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types14pthread_cond_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types16pthread_rwlock_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types17_pthread_fastlock6__initZ@Base 6
+ _D4core3sys5posix3sys5types17pthread_barrier_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types18pthread_condattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types19pthread_mutexattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types20pthread_rwlockattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys5types21pthread_barrierattr_t6__initZ@Base 6
+ _D4core3sys5posix3sys6select12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys6select6FD_CLRFNbNiiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select6FD_SETFNbNiiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select6fd_set6__initZ@Base 6
+ _D4core3sys5posix3sys6select7FD_ZEROFNbNiPS4core3sys5posix3sys6select6fd_setZv@Base 6
+ _D4core3sys5posix3sys6select7__FDELTFNaNbNiNfiZk@Base 6
+ _D4core3sys5posix3sys6select8FD_ISSETFNbNiiPxS4core3sys5posix3sys6select6fd_setZb@Base 6
+ _D4core3sys5posix3sys6select8__FDMASKFNaNbNiNfiZi@Base 6
+ _D4core3sys5posix3sys6socket10CMSG_ALIGNFNaNbNikZk@Base 6
+ _D4core3sys5posix3sys6socket10CMSG_SPACEFNaNbNikZk@Base 6
+ _D4core3sys5posix3sys6socket11CMSG_NXTHDRFNaNbNiPNgS4core3sys5posix3sys6socket6msghdrPNgS4core3sys5posix3sys6socket7cmsghdrZPNgS4core3sys5posix3sys6socket7cmsghdr@Base 6
+ _D4core3sys5posix3sys6socket12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys6socket13CMSG_FIRSTHDRFNaNbNiPNgS4core3sys5posix3sys6socket6msghdrZPNgS4core3sys5posix3sys6socket7cmsghdr@Base 6
+ _D4core3sys5posix3sys6socket16sockaddr_storage6__initZ@Base 6
+ _D4core3sys5posix3sys6socket6linger6__initZ@Base 6
+ _D4core3sys5posix3sys6socket6msghdr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket7cmsghdr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket8CMSG_LENFNaNbNikZk@Base 6
+ _D4core3sys5posix3sys6socket8sockaddr6__initZ@Base 6
+ _D4core3sys5posix3sys6socket9CMSG_DATAFNaNbNiPNgS4core3sys5posix3sys6socket7cmsghdrZPNgh@Base 6
+ _D4core3sys5posix3sys7statvfs12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys7statvfs5FFlag6__initZ@Base 6
+ _D4core3sys5posix3sys7statvfs9statvfs_t6__initZ@Base 6
+ _D4core3sys5posix3sys7utsname12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys7utsname7utsname6__initZ@Base 6
+ _D4core3sys5posix3sys8resource12__ModuleInfoZ@Base 6
+ _D4core3sys5posix3sys8resource6rlimit6__initZ@Base 6
+ _D4core3sys5posix3sys8resource6rusage6__initZ@Base 6
+ _D4core3sys5posix4arpa4inet12__ModuleInfoZ@Base 6
+ _D4core3sys5posix4arpa4inet7in_addr6__initZ@Base 6
+ _D4core3sys5posix4poll12__ModuleInfoZ@Base 6
+ _D4core3sys5posix4poll6pollfd6__initZ@Base 6
+ _D4core3sys5posix4time10itimerspec6__initZ@Base 6
+ _D4core3sys5posix4time12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5dlfcn12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5dlfcn7Dl_info6__initZ@Base 6
+ _D4core3sys5posix5fcntl12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5fcntl5flock6__initZ@Base 6
+ _D4core3sys5posix5netdb12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5netdb6netent6__initZ@Base 6
+ _D4core3sys5posix5netdb7hostent6__initZ@Base 6
+ _D4core3sys5posix5netdb7hostent6h_addrMUNdZPa@Base 6
+ _D4core3sys5posix5netdb7servent6__initZ@Base 6
+ _D4core3sys5posix5netdb8addrinfo6__initZ@Base 6
+ _D4core3sys5posix5netdb8protoent6__initZ@Base 6
+ _D4core3sys5posix5sched11sched_param6__initZ@Base 6
+ _D4core3sys5posix5sched12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5stdio12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5utime12__ModuleInfoZ@Base 6
+ _D4core3sys5posix5utime7utimbuf6__initZ@Base 6
+ _D4core3sys5posix6config12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6dirent12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6dirent3DIR6__initZ@Base 6
+ _D4core3sys5posix6dirent6dirent6__initZ@Base 6
+ _D4core3sys5posix6setjmp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6setjmp13__jmp_buf_tag6__initZ@Base 6
+ _D4core3sys5posix6signal11sigaction_t6__initZ@Base 6
+ _D4core3sys5posix6signal12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6signal6sigval6__initZ@Base 6
+ _D4core3sys5posix6signal7stack_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent11_sigev_un_t15_sigev_thread_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent11_sigev_un_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigevent6__initZ@Base 6
+ _D4core3sys5posix6signal8sigset_t6__initZ@Base 6
+ _D4core3sys5posix6signal8sigstack6__initZ@Base 6
+ _D4core3sys5posix6signal8timespec6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t10_sigpoll_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t11_sigchild_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t11_sigfault_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t5_rt_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t7_kill_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t11_sifields_t8_timer_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t6__initZ@Base 6
+ _D4core3sys5posix6signal9siginfo_t6si_pidMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6signal9siginfo_t6si_uidMUNbNcNdNiNjZk@Base 6
+ _D4core3sys5posix6signal9siginfo_t7si_addrMUNbNcNdNiNjZPv@Base 6
+ _D4core3sys5posix6signal9siginfo_t7si_bandMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6signal9siginfo_t8si_valueMUNbNcNdNiNjZS4core3sys5posix6signal6sigval@Base 6
+ _D4core3sys5posix6signal9siginfo_t9si_statusMUNbNcNdNiNjZi@Base 6
+ _D4core3sys5posix6stdlib12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6syslog12__ModuleInfoZ@Base 6
+ _D4core3sys5posix6unistd12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7netinet3in_11sockaddr_in6__initZ@Base 6
+ _D4core3sys5posix7netinet3in_12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7netinet3in_12sockaddr_in66__initZ@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_LOOPBACKFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_V4COMPATFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_20IN6_IS_ADDR_V4MAPPEDFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_LINKLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_MC_GLOBALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_MULTICASTFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_21IN6_IS_ADDR_SITELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_23IN6_IS_ADDR_MC_ORGLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_23IN6_IS_ADDR_UNSPECIFIEDFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_LINKLOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_NODELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_24IN6_IS_ADDR_MC_SITELOCALFNaNbNiPS4core3sys5posix7netinet3in_8in6_addrZi@Base 6
+ _D4core3sys5posix7netinet3in_8in6_addr6__initZ@Base 6
+ _D4core3sys5posix7netinet3in_9ipv6_mreq6__initZ@Base 6
+ _D4core3sys5posix7netinet3tcp12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7pthread12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup6__initZ@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup8__T3popZ3popMFNbiZv@Base 6
+ _D4core3sys5posix7pthread15pthread_cleanup9__T4pushZ4pushMFNbPUNbPvZvPvZv@Base 6
+ _D4core3sys5posix7pthread23_pthread_cleanup_buffer6__initZ@Base 6
+ _D4core3sys5posix7termios12__ModuleInfoZ@Base 6
+ _D4core3sys5posix7termios7termios6__initZ@Base 6
+ _D4core3sys5posix8inttypes12__ModuleInfoZ@Base 6
+ _D4core3sys5posix8ucontext10sigcontext6__initZ@Base 6.2.1-1ubuntu2
+ _D4core3sys5posix8ucontext10ucontext_t6__initZ@Base 6
+ _D4core3sys5posix8ucontext12__ModuleInfoZ@Base 6
+ _D4core3sys5posix9semaphore12__ModuleInfoZ@Base 6
+ _D4core3sys5posix9semaphore17_pthread_fastlock6__initZ@Base 6
+ _D4core3sys5posix9semaphore5sem_t6__initZ@Base 6
+ _D4core4math12__ModuleInfoZ@Base 6
+ _D4core4simd12__ModuleInfoZ@Base 6
+ _D4core4stdc4fenv12__ModuleInfoZ@Base 6
+ _D4core4stdc4fenv6fenv_t6__initZ@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNedZi@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNeeZi@Base 6
+ _D4core4stdc4math10fpclassifyFNbNiNefZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeddZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeeeZi@Base 6
+ _D4core4stdc4math11islessequalFNbNiNeffZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeddZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeeeZi@Base 6
+ _D4core4stdc4math11isunorderedFNbNiNeffZi@Base 6
+ _D4core4stdc4math12__ModuleInfoZ@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeddZi@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeeeZi@Base 6
+ _D4core4stdc4math13islessgreaterFNbNiNeffZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeddZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeeeZi@Base 6
+ _D4core4stdc4math14isgreaterequalFNbNiNeffZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNedZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNeeZi@Base 6
+ _D4core4stdc4math5isinfFNbNiNefZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNedZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNeeZi@Base 6
+ _D4core4stdc4math5isnanFNbNiNefZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeddZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeeeZi@Base 6
+ _D4core4stdc4math6islessFNbNiNeffZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNedZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNeeZi@Base 6
+ _D4core4stdc4math7signbitFNbNiNefZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNedZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNeeZi@Base 6
+ _D4core4stdc4math8isfiniteFNbNiNefZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNedZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNeeZi@Base 6
+ _D4core4stdc4math8isnormalFNbNiNefZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeddZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeeeZi@Base 6
+ _D4core4stdc4math9isgreaterFNbNiNeffZi@Base 6
+ _D4core4stdc4time12__ModuleInfoZ@Base 6
+ _D4core4stdc4time2tm6__initZ@Base 6
+ _D4core4stdc5ctype12__ModuleInfoZ@Base 6
+ _D4core4stdc5errno12__ModuleInfoZ@Base 6
+ _D4core4stdc5errno5errnoFNbNdNiNeZi@Base 6
+ _D4core4stdc5errno5errnoFNbNdNiNeiZi@Base 6
+ _D4core4stdc5stdio12__ModuleInfoZ@Base 6
+ _D4core4stdc5stdio4getcFNbNiNePOS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D4core4stdc5stdio4putcFNbNiNeiPOS4core4stdc5stdio8_IO_FILEZi@Base 6
+ _D4core4stdc5stdio6fpos_t6__initZ@Base 6
+ _D4core4stdc5stdio7getcharFNbNiNeZi@Base 6
+ _D4core4stdc5stdio7putcharFNbNiNeiZi@Base 6
+ _D4core4stdc5stdio8_IO_FILE6__initZ@Base 6
+ _D4core4stdc6config12__ModuleInfoZ@Base 6
+ _D4core4stdc6float_12__ModuleInfoZ@Base 6
+ _D4core4stdc6limits12__ModuleInfoZ@Base 6
+ _D4core4stdc6locale12__ModuleInfoZ@Base 6
+ _D4core4stdc6locale5lconv6__initZ@Base 6
+ _D4core4stdc6signal12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdarg12__ModuleInfoZ@Base 6
+ _D4core4stdc6stddef12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdint12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdint14__T7_typifyTgZ7_typifyFNaNbNiNfgZg@Base 6
+ _D4core4stdc6stdint14__T7_typifyThZ7_typifyFNaNbNiNfhZh@Base 6
+ _D4core4stdc6stdint14__T7_typifyTiZ7_typifyFNaNbNiNfiZi@Base 6
+ _D4core4stdc6stdint14__T7_typifyTkZ7_typifyFNaNbNiNfkZk@Base 6
+ _D4core4stdc6stdint14__T7_typifyTlZ7_typifyFNaNbNiNflZl@Base 6
+ _D4core4stdc6stdint14__T7_typifyTmZ7_typifyFNaNbNiNfmZm@Base 6
+ _D4core4stdc6stdint14__T7_typifyTsZ7_typifyFNaNbNiNfsZs@Base 6
+ _D4core4stdc6stdint14__T7_typifyTtZ7_typifyFNaNbNiNftZt@Base 6
+ _D4core4stdc6stdlib12__ModuleInfoZ@Base 6
+ _D4core4stdc6stdlib5div_t6__initZ@Base 6
+ _D4core4stdc6stdlib6ldiv_t6__initZ@Base 6
+ _D4core4stdc6stdlib7lldiv_t6__initZ@Base 6
+ _D4core4stdc6string12__ModuleInfoZ@Base 6
+ _D4core4stdc6tgmath12__ModuleInfoZ@Base 6
+ _D4core4stdc6wchar_12__ModuleInfoZ@Base 6
+ _D4core4stdc6wchar_5getwcFNbNiNePOS4core4stdc5stdio8_IO_FILEZw@Base 6
+ _D4core4stdc6wchar_5putwcFNbNiNewPOS4core4stdc5stdio8_IO_FILEZw@Base 6
+ _D4core4stdc6wchar_8getwcharFNbNiNeZw@Base 6
+ _D4core4stdc6wchar_8putwcharFNbNiNewZw@Base 6
+ _D4core4stdc6wchar_9mbstate_t6__initZ@Base 6
+ _D4core4stdc6wchar_9mbstate_t8___value6__initZ@Base 6
+ _D4core4stdc6wctype12__ModuleInfoZ@Base 6
+ _D4core4stdc7complex12__ModuleInfoZ@Base 6
+ _D4core4stdc8inttypes12__ModuleInfoZ@Base 6
+ _D4core4stdc8inttypes9imaxdiv_t6__initZ@Base 6
+ _D4core4sync5mutex12__ModuleInfoZ@Base 6
+ _D4core4sync5mutex5Mutex10handleAddrMFZPS4core3sys5posix3sys5types15pthread_mutex_t@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy11__xopEqualsFKxS4core4sync5mutex5Mutex12MonitorProxyKxS4core4sync5mutex5Mutex12MonitorProxyZb@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy6__initZ@Base 6
+ _D4core4sync5mutex5Mutex12MonitorProxy9__xtoHashFNbNeKxS4core4sync5mutex5Mutex12MonitorProxyZk@Base 6
+ _D4core4sync5mutex5Mutex12lock_nothrowMFNbNiNeZv@Base 6
+ _D4core4sync5mutex5Mutex14unlock_nothrowMFNbNiNeZv@Base 6
+ _D4core4sync5mutex5Mutex4lockMFNeZv@Base 6
+ _D4core4sync5mutex5Mutex6__ctorMFNbNeC6ObjectZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync5mutex5Mutex6__ctorMFNbNeZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync5mutex5Mutex6__dtorMFZv@Base 6
+ _D4core4sync5mutex5Mutex6__initZ@Base 6
+ _D4core4sync5mutex5Mutex6__vtblZ@Base 6
+ _D4core4sync5mutex5Mutex6unlockMFNeZv@Base 6
+ _D4core4sync5mutex5Mutex7__ClassZ@Base 6
+ _D4core4sync5mutex5Mutex7tryLockMFZb@Base 6
+ _D4core4sync6config12__ModuleInfoZ@Base 6
+ _D4core4sync6config7mktspecFNbKS4core3sys5posix6signal8timespecS4core4time8DurationZv@Base 6
+ _D4core4sync6config7mktspecFNbKS4core3sys5posix6signal8timespecZv@Base 6
+ _D4core4sync6config7mvtspecFNbKS4core3sys5posix6signal8timespecS4core4time8DurationZv@Base 6
+ _D4core4sync7barrier12__ModuleInfoZ@Base 6
+ _D4core4sync7barrier7Barrier4waitMFZv@Base 6
+ _D4core4sync7barrier7Barrier6__ctorMFkZC4core4sync7barrier7Barrier@Base 6
+ _D4core4sync7barrier7Barrier6__initZ@Base 6
+ _D4core4sync7barrier7Barrier6__vtblZ@Base 6
+ _D4core4sync7barrier7Barrier7__ClassZ@Base 6
+ _D4core4sync7rwmutex12__ModuleInfoZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy11__xopEqualsFKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy9__xtoHashFNbNeKxS4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxyZk@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader17shouldQueueReaderMFNdZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader4lockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__ctorMFZC4core4sync7rwmutex14ReadWriteMutex6Reader@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader6unlockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader7__ClassZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Reader7tryLockMFZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy11__xopEqualsFKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy9__xtoHashFNbNeKxS4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxyZk@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer17shouldQueueWriterMFNdZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer4lockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__ctorMFZC4core4sync7rwmutex14ReadWriteMutex6Writer@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer6unlockMFNeZv@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer7__ClassZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6Writer7tryLockMFZb@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__ctorMFE4core4sync7rwmutex14ReadWriteMutex6PolicyZC4core4sync7rwmutex14ReadWriteMutex@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__initZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6__vtblZ@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6policyMFNdZE4core4sync7rwmutex14ReadWriteMutex6Policy@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6readerMFNdZC4core4sync7rwmutex14ReadWriteMutex6Reader@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex6writerMFNdZC4core4sync7rwmutex14ReadWriteMutex6Writer@Base 6
+ _D4core4sync7rwmutex14ReadWriteMutex7__ClassZ@Base 6
+ _D4core4sync9condition12__ModuleInfoZ@Base 6
+ _D4core4sync9condition9Condition13mutex_nothrowMFNaNbNdNiNfZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync9condition9Condition4waitMFS4core4time8DurationZb@Base 6
+ _D4core4sync9condition9Condition4waitMFZv@Base 6
+ _D4core4sync9condition9Condition5mutexMFNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core4sync9condition9Condition6__ctorMFNbNfC4core4sync5mutex5MutexZC4core4sync9condition9Condition@Base 6
+ _D4core4sync9condition9Condition6__dtorMFZv@Base 6
+ _D4core4sync9condition9Condition6__initZ@Base 6
+ _D4core4sync9condition9Condition6__vtblZ@Base 6
+ _D4core4sync9condition9Condition6notifyMFZv@Base 6
+ _D4core4sync9condition9Condition7__ClassZ@Base 6
+ _D4core4sync9condition9Condition9notifyAllMFZv@Base 6
+ _D4core4sync9exception12__ModuleInfoZ@Base 6
+ _D4core4sync9exception9SyncError6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core4sync9exception9SyncError@Base 6
+ _D4core4sync9exception9SyncError6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core4sync9exception9SyncError@Base 6
+ _D4core4sync9exception9SyncError6__initZ@Base 6
+ _D4core4sync9exception9SyncError6__vtblZ@Base 6
+ _D4core4sync9exception9SyncError7__ClassZ@Base 6
+ _D4core4sync9semaphore12__ModuleInfoZ@Base 6
+ _D4core4sync9semaphore9Semaphore4waitMFS4core4time8DurationZb@Base 6
+ _D4core4sync9semaphore9Semaphore4waitMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore6__ctorMFkZC4core4sync9semaphore9Semaphore@Base 6
+ _D4core4sync9semaphore9Semaphore6__dtorMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore6__initZ@Base 6
+ _D4core4sync9semaphore9Semaphore6__vtblZ@Base 6
+ _D4core4sync9semaphore9Semaphore6notifyMFZv@Base 6
+ _D4core4sync9semaphore9Semaphore7__ClassZ@Base 6
+ _D4core4sync9semaphore9Semaphore7tryWaitMFZb@Base 6
+ _D4core4time11_posixClockFNaNbNiNfE4core4time9ClockTypeZi@Base 6
+ _D4core4time11numToStringFNaNbNflZAya@Base 6
+ _D4core4time12TickDuration11ticksPerSecyl@Base 6
+ _D4core4time12TickDuration14currSystemTickFNbNdNiNeZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration19_sharedStaticCtor55FNeZv@Base 6
+ _D4core4time12TickDuration3maxFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration3minFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration4zeroFNaNbNdNiNfZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration5msecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration5nsecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration5opCmpMxFNaNbNiNfS4core4time12TickDurationZi@Base 6
+ _D4core4time12TickDuration5usecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration6__ctorMFNaNbNcNiNflZS4core4time12TickDuration@Base 6
+ _D4core4time12TickDuration6__initZ@Base 6
+ _D4core4time12TickDuration6hnsecsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration7secondsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time12TickDuration8__xopCmpFKxS4core4time12TickDurationKxS4core4time12TickDurationZi@Base 6
+ _D4core4time12TickDuration9appOriginyS4core4time12TickDuration@Base 6
+ _D4core4time12__ModuleInfoZ@Base 6
+ _D4core4time12nsecsToTicksFNaNbNiNflZl@Base 6
+ _D4core4time12ticksToNSecsFNaNbNiNflZl@Base 6
+ _D4core4time13TimeException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core4time13TimeException@Base 6
+ _D4core4time13TimeException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core4time13TimeException@Base 6
+ _D4core4time13TimeException6__initZ@Base 6
+ _D4core4time13TimeException6__vtblZ@Base 6
+ _D4core4time13TimeException7__ClassZ@Base 6
+ _D4core4time13_clockTypeIdxFE4core4time9ClockTypeZk@Base 6
+ _D4core4time13convClockFreqFNaNbNiNflllZl@Base 6
+ _D4core4time14_clockTypeNameFE4core4time9ClockTypeZAya@Base 6
+ _D4core4time15_ticksPerSecondyG8l@Base 6
+ _D4core4time23__T3durVAyaa4_64617973Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_686f757273Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_6d73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_6e73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_7573656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25__T3durVAyaa5_7765656b73Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time25unitsAreInDescendingOrderFAAyaXb@Base 6
+ _D4core4time27__T3durVAyaa6_686e73656373Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time29__T3durVAyaa7_6d696e75746573Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time29__T3durVAyaa7_7365636f6e6473Z3durFNaNbNiNflZS4core4time8Duration@Base 6
+ _D4core4time39__T18getUnitsFromHNSecsVAyaa4_64617973Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time3absFNaNbNiNfS4core4time12TickDurationZS4core4time12TickDuration@Base 6
+ _D4core4time3absFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_686f757273Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_6d73656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_7573656373Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T18getUnitsFromHNSecsVAyaa5_7765656b73Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time41__T20splitUnitsFromHNSecsVAyaa4_64617973Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl14ticksPerSecondFNaNbNdNiNfZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl22__T8opBinaryVAyaa1_2dZ8opBinaryMxFNaNbNiNfS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZS4core4time8Duration@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl3maxFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl3minFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl4zeroFNaNbNdNiNfZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl5opCmpMxFNaNbNiNfS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZi@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl5ticksMxFNaNbNdNiNfZl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl6__initZ@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8__xopCmpFKxS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplKxS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImplZi@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8currTimeFNbNdNiNeZS4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl@Base 6
+ _D4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl8toStringMxFNaNbNfZAya@Base 6
+ _D4core4time42__T21removeUnitsFromHNSecsVAyaa4_64617973Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_686f757273Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_6d73656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7573656373Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time43__T20splitUnitsFromHNSecsVAyaa5_7765656b73Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time44__T21removeUnitsFromHNSecsVAyaa5_686f757273Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time44__T21removeUnitsFromHNSecsVAyaa5_7765656b73Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_6d696e75746573Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time45__T18getUnitsFromHNSecsVAyaa7_7365636f6e6473Z18getUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa4_64617973VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time46__T7convertVAyaa6_686e73656373VAyaa4_64617973Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_6d696e75746573Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time47__T20splitUnitsFromHNSecsVAyaa7_7365636f6e6473Z20splitUnitsFromHNSecsFNaNbNiNfKlZl@Base 6
+ _D4core4time48__T21removeUnitsFromHNSecsVAyaa7_6d696e75746573Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time48__T21removeUnitsFromHNSecsVAyaa7_7365636f6e6473Z21removeUnitsFromHNSecsFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_686f757273VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_6d73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_6e73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7573656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa5_7765656b73VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_686f757273Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_6e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time48__T7convertVAyaa6_686e73656373VAyaa5_7765656b73Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time4_absFNaNbNiNfdZd@Base 6
+ _D4core4time4_absFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa6_686e73656373VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_6d73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_6e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time50__T7convertVAyaa7_7365636f6e6473VAyaa5_7573656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_6d696e75746573Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa6_686e73656373VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa7_6d696e75746573VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time52__T7convertVAyaa7_7365636f6e6473VAyaa6_686e73656373Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time53__T2toVAyaa5_6d73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time53__T2toVAyaa5_6e73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time53__T2toVAyaa5_7573656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time54__T7convertVAyaa7_7365636f6e6473VAyaa7_7365636f6e6473Z7convertFNaNbNiNflZl@Base 6
+ _D4core4time55__T2toVAyaa6_686e73656373TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time57__T2toVAyaa7_7365636f6e6473TlTxS4core4time12TickDurationZ2toFNaNbNiNfxS4core4time12TickDurationZl@Base 6
+ _D4core4time7FracSec11__invariantMxFNaNfZv@Base 6
+ _D4core4time7FracSec13__invariant85MxFNaNfZv@Base 6
+ _D4core4time7FracSec13_enforceValidFNaNfiZv@Base 6
+ _D4core4time7FracSec13_toStringImplMxFNaNbNfZAya@Base 6
+ _D4core4time7FracSec28__T4fromVAyaa6_686e73656373Z4fromFNaNflZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec4zeroFNaNbNdNiNfZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec5msecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec5msecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec5nsecsMFNaNdNflZv@Base 6
+ _D4core4time7FracSec5nsecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec5usecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec5usecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec6__ctorMFNaNbNcNiNfiZS4core4time7FracSec@Base 6
+ _D4core4time7FracSec6__initZ@Base 6
+ _D4core4time7FracSec6_validFNaNbNiNfiZb@Base 6
+ _D4core4time7FracSec6hnsecsMFNaNdNfiZv@Base 6
+ _D4core4time7FracSec6hnsecsMxFNaNbNdNiNfZi@Base 6
+ _D4core4time7FracSec8toStringMFNaNfZAya@Base 6
+ _D4core4time7FracSec8toStringMxFNaNbNfZAya@Base 6
+ _D4core4time8Duration10isNegativeMxFNaNbNdNiNfZb@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ10appListSepFNbNfKAyakbZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ31__T10appUnitValVAyaa4_64617973Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_686f757273Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_6d73656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_7573656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ33__T10appUnitValVAyaa5_7765656b73Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ35__T10appUnitValVAyaa6_686e73656373Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ37__T10appUnitValVAyaa7_6d696e75746573Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZ37__T10appUnitValVAyaa7_7365636f6e6473Z10appUnitValFNaNbNfKAyalZv@Base 6
+ _D4core4time8Duration13_toStringImplMxFNaNbNfZAya@Base 6
+ _D4core4time8Duration23__T3getVAyaa4_64617973Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration25__T10opOpAssignVAyaa1_2aZ10opOpAssignMFNaNbNcNiNflZS4core4time8Duration@Base 6
+ _D4core4time8Duration25__T3getVAyaa5_686f757273Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration25__T3getVAyaa5_7765656b73Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration27__T5totalVAyaa5_6d73656373Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration29__T3getVAyaa7_6d696e75746573Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration29__T3getVAyaa7_7365636f6e6473Z3getMxFNaNbNiNfZl@Base 6
+ _D4core4time8Duration31__T5totalVAyaa7_7365636f6e6473Z5totalMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration3maxFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration3minFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration43__T8opBinaryVAyaa1_2bTS4core4time8DurationZ8opBinaryMxFNaNbNiNfS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration46__T10opOpAssignVAyaa1_2bTS4core4time8DurationZ10opOpAssignMFNaNbNcNiNfxS4core4time8DurationZS4core4time8Duration@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z14__T5splitTiTiZ5splitMxFNaNbNiNfJiJiZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z14__T5splitTlTlZ5splitMxFNaNbNiNfJlJlZv@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits6__initZ@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ12genSplitCallFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ14genMemberDeclsFNaNbNfZAya@Base 6
+ _D4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZS4core4time8Duration48__T5splitVAyaa7_7365636f6e6473VAyaa5_6e73656373Z5splitMxFNaNbNiNfZ10SplitUnits@Base 6
+ _D4core4time8Duration4daysMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration4zeroFNaNbNdNiNfZS4core4time8Duration@Base 6
+ _D4core4time8Duration5hoursMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration5opCmpMxFNaNbNiNfS4core4time8DurationZi@Base 6
+ _D4core4time8Duration5weeksMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration6__ctorMFNaNbNcNiNflZS4core4time8Duration@Base 6
+ _D4core4time8Duration6__initZ@Base 6
+ _D4core4time8Duration7fracSecMxFNaNbNdNfZS4core4time7FracSec@Base 6
+ _D4core4time8Duration7minutesMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration7secondsMxFNaNbNdNiNfZl@Base 6
+ _D4core4time8Duration8__xopCmpFKxS4core4time8DurationKxS4core4time8DurationZi@Base 6
+ _D4core4time8Duration8toStringMFNaNfZAya@Base 6
+ _D4core4time8Duration8toStringMxFNaNbNfZAya@Base 6
+ _D4core5bitop12__ModuleInfoZ@Base 6
+ _D4core5bitop2btFNaNbNixPkkZi@Base 6
+ _D4core5bitop6popcntFNaNbNiNfkZi@Base 6
+ _D4core5bitop7bitswapFNaNbNiNekZk@Base 6
+ _D4core5cpuid10dataCachesFNbNdNiNeZxG5S4core5cpuid9CacheInfo@Base 6
+ _D4core5cpuid10maxThreadsk@Base 6
+ _D4core5cpuid11amd3dnowExtFNbNdNiNeZb@Base 6
+ _D4core5cpuid11amdfeaturesk@Base 6
+ _D4core5cpuid11cacheLevelsFNbNdNiNeZk@Base 6
+ _D4core5cpuid11coresPerCPUFNbNdNiNeZk@Base 6
+ _D4core5cpuid11extfeaturesk@Base 6
+ _D4core5cpuid11hasLahfSahfFNbNdNiNeZb@Base 6
+ _D4core5cpuid11probablyAMDb@Base 6
+ _D4core5cpuid12__ModuleInfoZ@Base 6
+ _D4core5cpuid12hasCmpxchg8bFNbNdNiNeZb@Base 6
+ _D4core5cpuid12hasPclmulqdqFNbNdNiNeZb@Base 6
+ _D4core5cpuid12miscfeaturesk@Base 6
+ _D4core5cpuid12preferAthlonFNbNdNiNeZb@Base 6
+ _D4core5cpuid13hasCmpxchg16bFNbNdNiNeZb@Base 6
+ _D4core5cpuid13hasVpclmulqdqFNbNdNiNeZb@Base 6
+ _D4core5cpuid13probablyIntelb@Base 6
+ _D4core5cpuid13processorNameAya@Base 6
+ _D4core5cpuid13threadsPerCPUFNbNdNiNeZk@Base 6
+ _D4core5cpuid14hyperThreadingFNbNdNiNeZb@Base 6
+ _D4core5cpuid14numCacheLevelsk@Base 6
+ _D4core5cpuid14preferPentium1FNbNdNiNeZb@Base 6
+ _D4core5cpuid14preferPentium4FNbNdNiNeZb@Base 6
+ _D4core5cpuid15amdmiscfeaturesk@Base 6
+ _D4core5cpuid16has3dnowPrefetchFNbNdNiNeZb@Base 6
+ _D4core5cpuid17hyperThreadingBitFNbNdNiNeZb@Base 6
+ _D4core5cpuid18_sharedStaticCtor1FNbNiNeZv@Base 6
+ _D4core5cpuid18hasSysEnterSysExitFNbNdNiNeZb@Base 6
+ _D4core5cpuid19processorNameBufferG48a@Base 6
+ _D4core5cpuid3aesFNbNdNiNeZb@Base 6
+ _D4core5cpuid3avxFNbNdNiNeZb@Base 6
+ _D4core5cpuid3fmaFNbNdNiNeZb@Base 6
+ _D4core5cpuid3hleFNbNdNiNeZb@Base 6
+ _D4core5cpuid3mmxFNbNdNiNeZb@Base 6
+ _D4core5cpuid3rtmFNbNdNiNeZb@Base 6
+ _D4core5cpuid3sseFNbNdNiNeZb@Base 6
+ _D4core5cpuid4avx2FNbNdNiNeZb@Base 6
+ _D4core5cpuid4sse2FNbNdNiNeZb@Base 6
+ _D4core5cpuid4sse3FNbNdNiNeZb@Base 6
+ _D4core5cpuid4vaesFNbNdNiNeZb@Base 6
+ _D4core5cpuid5fp16cFNbNdNiNeZb@Base 6
+ _D4core5cpuid5modelk@Base 6
+ _D4core5cpuid5sse41FNbNdNiNeZb@Base 6
+ _D4core5cpuid5sse42FNbNdNiNeZb@Base 6
+ _D4core5cpuid5sse4aFNbNdNiNeZb@Base 6
+ _D4core5cpuid5ssse3FNbNdNiNeZb@Base 6
+ _D4core5cpuid6amdMmxFNbNdNiNeZb@Base 6
+ _D4core5cpuid6familyk@Base 6
+ _D4core5cpuid6hasShaFNbNdNiNeZb@Base 6
+ _D4core5cpuid6vendorFNbNdNiNeZAya@Base 6
+ _D4core5cpuid7hasCmovFNbNdNiNeZb@Base 6
+ _D4core5cpuid7hasFxsrFNbNdNiNeZb@Base 6
+ _D4core5cpuid8amd3dnowFNbNdNiNeZb@Base 6
+ _D4core5cpuid8cpuidX86FNbNiNeZv@Base 6
+ _D4core5cpuid8featuresk@Base 6
+ _D4core5cpuid8hasCPUIDFNbNiNeZb@Base 6
+ _D4core5cpuid8hasLzcntFNbNdNiNeZb@Base 6
+ _D4core5cpuid8hasRdtscFNbNdNiNeZb@Base 6
+ _D4core5cpuid8isX86_64FNbNdNiNeZb@Base 6
+ _D4core5cpuid8maxCoresk@Base 6
+ _D4core5cpuid8steppingk@Base 6
+ _D4core5cpuid8vendorIDG12a@Base 6
+ _D4core5cpuid9CacheInfo6__initZ@Base 6
+ _D4core5cpuid9datacacheG5S4core5cpuid9CacheInfo@Base 6
+ _D4core5cpuid9hasPopcntFNbNdNiNeZb@Base 6
+ _D4core5cpuid9hasRdrandFNbNdNiNeZb@Base 6
+ _D4core5cpuid9hasRdseedFNbNdNiNeZb@Base 6
+ _D4core5cpuid9isItaniumFNbNdNiNeZb@Base 6
+ _D4core5cpuid9processorFNbNdNiNeZAya@Base 6
+ _D4core5cpuid9x87onChipFNbNdNiNeZb@Base 6
+ _D4core5cpuid9xfeaturesm@Base 6
+ _D4core6atomic11atomicFenceFNbNiZv@Base 6
+ _D4core6atomic120__T11atomicStoreVE4core6atomic11MemoryOrderi3TPOS2rt9critical_18D_CRITICAL_SECTIONTPOS2rt9critical_18D_CRITICAL_SECTIONZ11atomicStoreFNaNbNiKOPS2rt9critical_18D_CRITICAL_SECTIONPOS2rt9critical_18D_CRITICAL_SECTIONZv@Base 6
+ _D4core6atomic12__ModuleInfoZ@Base 6
+ _D4core6atomic14__T3casThThThZ3casFNaNbNiPOhxhxhZb@Base 6
+ _D4core6atomic14__T3casTkTkTkZ3casFNaNbNiPOkxkxkZb@Base 6
+ _D4core6atomic14__T3casTtTtTtZ3casFNaNbNiPOtxtxtZb@Base 6
+ _D4core6atomic20__T7casImplThTxhTxhZ7casImplFNaNbNiPOhxhxhZb@Base 6
+ _D4core6atomic20__T7casImplTkTxkTxkZ7casImplFNaNbNiPOkxkxkZb@Base 6
+ _D4core6atomic20__T7casImplTtTxtTxtZ7casImplFNaNbNiPOtxtxtZb@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2b3dTkTiZ8atomicOpFNaNbNiKOkiZk@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2b3dTkTkZ8atomicOpFNaNbNiKOkkZk@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2d3dTkTiZ8atomicOpFNaNbNiKOkiZk@Base 6
+ _D4core6atomic28__T8atomicOpVAyaa2_2d3dTkTkZ8atomicOpFNaNbNiKOkkZk@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi0TkZ10atomicLoadFNaNbNiKOxkZk@Base 6
+ _D4core6atomic47__T10atomicLoadVE4core6atomic11MemoryOrderi5TbZ10atomicLoadFNaNbNiKOxbZb@Base 6
+ _D4core6atomic50__T11atomicStoreVE4core6atomic11MemoryOrderi0TbTbZ11atomicStoreFNaNbNiKObbZv@Base 6
+ _D4core6atomic69__T10atomicLoadVE4core6atomic11MemoryOrderi2TPOS2rt8monitor_7MonitorZ10atomicLoadFNaNbNiKOxPS2rt8monitor_7MonitorZPOS2rt8monitor_7Monitor@Base 6
+ _D4core6atomic82__T10atomicLoadVE4core6atomic11MemoryOrderi0TPOS2rt9critical_18D_CRITICAL_SECTIONZ10atomicLoadFNaNbNiKOxPS2rt9critical_18D_CRITICAL_SECTIONZPOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D4core6atomic82__T10atomicLoadVE4core6atomic11MemoryOrderi2TPOS2rt9critical_18D_CRITICAL_SECTIONZ10atomicLoadFNaNbNiKOxPS2rt9critical_18D_CRITICAL_SECTIONZPOS2rt9critical_18D_CRITICAL_SECTION@Base 6
+ _D4core6atomic94__T11atomicStoreVE4core6atomic11MemoryOrderi3TPOS2rt8monitor_7MonitorTPOS2rt8monitor_7MonitorZ11atomicStoreFNaNbNiKOPS2rt8monitor_7MonitorPOS2rt8monitor_7MonitorZv@Base 6
+ _D4core6memory12__ModuleInfoZ@Base 6
+ _D4core6memory2GC10removeRootFNbxPvZv@Base 6
+ _D4core6memory2GC11removeRangeFNbNixPvZv@Base 6
+ _D4core6memory2GC13runFinalizersFxAvZv@Base 6
+ _D4core6memory2GC4freeFNaNbPvZv@Base 6
+ _D4core6memory2GC5queryFNaNbPvZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC5queryFNbxPvZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC6__initZ@Base 6
+ _D4core6memory2GC6addrOfFNaNbPvZPv@Base 6
+ _D4core6memory2GC6addrOfFNbPNgvZPNgv@Base 6
+ _D4core6memory2GC6callocFNaNbkkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC6enableFNbZv@Base 6
+ _D4core6memory2GC6extendFNaNbPvkkxC8TypeInfoZk@Base 6
+ _D4core6memory2GC6mallocFNaNbkkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC6qallocFNaNbkkxC8TypeInfoZS4core6memory8BlkInfo_@Base 6
+ _D4core6memory2GC6sizeOfFNaNbPvZk@Base 6
+ _D4core6memory2GC6sizeOfFNbxPvZk@Base 6
+ _D4core6memory2GC7addRootFNbxPvZv@Base 6
+ _D4core6memory2GC7clrAttrFNaNbPvkZk@Base 6
+ _D4core6memory2GC7clrAttrFNbxPvkZk@Base 6
+ _D4core6memory2GC7collectFNbZv@Base 6
+ _D4core6memory2GC7disableFNbZv@Base 6
+ _D4core6memory2GC7getAttrFNaNbPvZk@Base 6
+ _D4core6memory2GC7getAttrFNbxPvZk@Base 6
+ _D4core6memory2GC7reallocFNaNbPvkkxC8TypeInfoZPv@Base 6
+ _D4core6memory2GC7reserveFNbkZk@Base 6
+ _D4core6memory2GC7setAttrFNaNbPvkZk@Base 6
+ _D4core6memory2GC7setAttrFNbxPvkZk@Base 6
+ _D4core6memory2GC8addRangeFNbNixPvkxC8TypeInfoZv@Base 6
+ _D4core6memory2GC8minimizeFNbZv@Base 6
+ _D4core6memory8BlkInfo_6__initZ@Base 6
+ _D4core6thread11ThreadError6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core6thread11ThreadError@Base 6
+ _D4core6thread11ThreadError6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core6thread11ThreadError@Base 6
+ _D4core6thread11ThreadError6__initZ@Base 6
+ _D4core6thread11ThreadError6__vtblZ@Base 6
+ _D4core6thread11ThreadError7__ClassZ@Base 6
+ _D4core6thread11ThreadGroup3addMFC4core6thread6ThreadZv@Base 6
+ _D4core6thread11ThreadGroup6__initZ@Base 6
+ _D4core6thread11ThreadGroup6__vtblZ@Base 6
+ _D4core6thread11ThreadGroup6createMFDFZvZC4core6thread6Thread@Base 6
+ _D4core6thread11ThreadGroup6createMFPFZvZC4core6thread6Thread@Base 6
+ _D4core6thread11ThreadGroup6removeMFC4core6thread6ThreadZv@Base 6
+ _D4core6thread11ThreadGroup7__ClassZ@Base 6
+ _D4core6thread11ThreadGroup7joinAllMFbZv@Base 6
+ _D4core6thread11ThreadGroup7opApplyMFMDFKC4core6thread6ThreadZiZi@Base 6
+ _D4core6thread11getStackTopFNbZPv@Base 6
+ _D4core6thread12__ModuleInfoZ@Base 6
+ _D4core6thread12suspendCountS4core3sys5posix9semaphore5sem_t@Base 6
+ _D4core6thread12suspendDepthk@Base 6
+ _D4core6thread13onThreadErrorFNbAyaC6object9ThrowableZ5errorC4core6thread11ThreadError@Base 6
+ _D4core6thread13onThreadErrorFNbAyaC6object9ThrowableZv@Base 6
+ _D4core6thread14getStackBottomFNbZPv@Base 6
+ _D4core6thread15ThreadException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core6thread15ThreadException@Base 6
+ _D4core6thread15ThreadException6__ctorMFNaNbNfAyaC6object9ThrowableAyakZC4core6thread15ThreadException@Base 6
+ _D4core6thread15ThreadException6__initZ@Base 6
+ _D4core6thread15ThreadException6__vtblZ@Base 6
+ _D4core6thread15ThreadException7__ClassZ@Base 6
+ _D4core6thread15scanAllTypeImplFNbMDFNbE4core6thread8ScanTypePvPvZvPvZv@Base 6
+ _D4core6thread17PTHREAD_STACK_MINyk@Base 6
+ _D4core6thread17multiThreadedFlagb@Base 6
+ _D4core6thread17thread_entryPointUPvZ21thread_cleanupHandlerUNbPvZv@Base 6
+ _D4core6thread17thread_findByAddrFkZC4core6thread6Thread@Base 6
+ _D4core6thread18_sharedStaticDtor8FZv@Base 6
+ _D4core6thread18callWithStackShellFNbMDFNbPvZvZv@Base 6
+ _D4core6thread18resumeSignalNumberi@Base 6
+ _D4core6thread19_sharedStaticCtor18FZv@Base 6
+ _D4core6thread19suspendSignalNumberi@Base 6
+ _D4core6thread5Fiber10allocStackMFNbkZv@Base 6
+ _D4core6thread5Fiber13_staticCtor19FZv@Base 6
+ _D4core6thread5Fiber13yieldAndThrowFNbC6object9ThrowableZv@Base 6
+ _D4core6thread5Fiber39__T4callVE4core6thread5Fiber7Rethrowi0Z4callMFNbZC6object9Throwable@Base 6
+ _D4core6thread5Fiber39__T4callVE4core6thread5Fiber7Rethrowi1Z4callMFZC6object9Throwable@Base 6
+ _D4core6thread5Fiber3runMFZv@Base 6
+ _D4core6thread5Fiber4callMFE4core6thread5Fiber7RethrowZC6object9Throwable@Base 6
+ _D4core6thread5Fiber4callMFbZC6object9Throwable@Base 6
+ _D4core6thread5Fiber5resetMFNbDFZvZv@Base 6
+ _D4core6thread5Fiber5resetMFNbPFZvZv@Base 6
+ _D4core6thread5Fiber5resetMFNbZv@Base 6
+ _D4core6thread5Fiber5stateMxFNbNdZE4core6thread5Fiber5State@Base 6
+ _D4core6thread5Fiber5yieldFNbZv@Base 6
+ _D4core6thread5Fiber6__ctorMFNbDFZvkZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__ctorMFNbPFZvkZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__ctorMFNbZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber6__dtorMFNbZv@Base 6
+ _D4core6thread5Fiber6__initZ@Base 6
+ _D4core6thread5Fiber6__vtblZ@Base 6
+ _D4core6thread5Fiber7__ClassZ@Base 6
+ _D4core6thread5Fiber7getThisFNbZC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber7setThisFNbC4core6thread5FiberZv@Base 6
+ _D4core6thread5Fiber7sm_thisC4core6thread5Fiber@Base 6
+ _D4core6thread5Fiber8callImplMFNbZv@Base 6
+ _D4core6thread5Fiber8switchInMFNbZv@Base 6
+ _D4core6thread5Fiber9freeStackMFNbZv@Base 6
+ _D4core6thread5Fiber9initStackMFNbZv@Base 6
+ _D4core6thread5Fiber9switchOutMFNbZv@Base 6
+ _D4core6thread6Thread10popContextMFNbZv@Base 6
+ _D4core6thread6Thread10topContextMFNbZPS4core6thread6Thread7Context@Base 6
+ _D4core6thread6Thread11pushContextMFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread12PRIORITY_MAXxi@Base 6
+ _D4core6thread6Thread12PRIORITY_MINxi@Base 6
+ _D4core6thread6Thread16PRIORITY_DEFAULTxi@Base 6
+ _D4core6thread6Thread18_sharedStaticCtor3FZv@Base 6
+ _D4core6thread6Thread18criticalRegionLockFNbNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core6thread6Thread3addFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread3addFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread3runMFZv@Base 6
+ _D4core6thread6Thread4joinMFbZC6object9Throwable@Base 6
+ _D4core6thread6Thread4nameMFNdAyaZv@Base 6
+ _D4core6thread6Thread4nameMFNdZAya@Base 6
+ _D4core6thread6Thread5sleepFNbS4core4time8DurationZv@Base 6
+ _D4core6thread6Thread5slockFNbNdZC4core4sync5mutex5Mutex@Base 6
+ _D4core6thread6Thread5startMFNbZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread5yieldFNbZv@Base 6
+ _D4core6thread6Thread6__ctorMFDFZvkZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__ctorMFPFZvkZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__ctorMFkZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6__dtorMFZv@Base 6
+ _D4core6thread6Thread6__initZ@Base 6
+ _D4core6thread6Thread6__vtblZ@Base 6
+ _D4core6thread6Thread6_locksG2G40v@Base 6
+ _D4core6thread6Thread6getAllFZAC4core6thread6Thread@Base 6
+ _D4core6thread6Thread6removeFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread6removeFNbPS4core6thread6Thread7ContextZv@Base 6
+ _D4core6thread6Thread7Context6__initZ@Base 6
+ _D4core6thread6Thread7__ClassZ@Base 6
+ _D4core6thread6Thread7getThisFNbZC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7opApplyFMDFKC4core6thread6ThreadZiZi@Base 6
+ _D4core6thread6Thread7setThisFC4core6thread6ThreadZv@Base 6
+ _D4core6thread6Thread7sm_cbegPS4core6thread6Thread7Context@Base 6
+ _D4core6thread6Thread7sm_mainC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7sm_tbegC4core6thread6Thread@Base 6
+ _D4core6thread6Thread7sm_thisk@Base 6
+ _D4core6thread6Thread7sm_tlenk@Base 6
+ _D4core6thread6Thread8isDaemonMFNdZb@Base 6
+ _D4core6thread6Thread8isDaemonMFNdbZv@Base 6
+ _D4core6thread6Thread8priorityMFNdZi@Base 6
+ _D4core6thread6Thread8priorityMFNdiZv@Base 6
+ _D4core6thread6Thread9initLocksFZv@Base 6
+ _D4core6thread6Thread9isRunningMFNbNdZb@Base 6
+ _D4core6thread6Thread9termLocksFZv@Base 6
+ _D4core6thread6resumeFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread7suspendFNbC4core6thread6ThreadZv@Base 6
+ _D4core6thread8PAGESIZEyk@Base 6
+ _D4core6vararg12__ModuleInfoZ@Base 6
+ _D4core7runtime12__ModuleInfoZ@Base 6
+ _D4core7runtime12_staticCtor1FZv@Base 6
+ _D4core7runtime18runModuleUnitTestsUZ19unittestSegvHandlerUiPS4core3sys5posix6signal9siginfo_tPvZv@Base 6
+ _D4core7runtime19defaultTraceHandlerFPvZC6object9Throwable9TraceInfo@Base 6
+ _D4core7runtime5CArgs6__initZ@Base 6
+ _D4core7runtime7Runtime10initializeFDFC6object9ThrowableZvZb@Base 6
+ _D4core7runtime7Runtime10initializeFZb@Base 6
+ _D4core7runtime7Runtime12traceHandlerFNdPFPvZC6object9Throwable9TraceInfoZv@Base 6
+ _D4core7runtime7Runtime12traceHandlerFNdZPFPvZC6object9Throwable9TraceInfo@Base 6
+ _D4core7runtime7Runtime14collectHandlerFNdPFC6ObjectZbZv@Base 6
+ _D4core7runtime7Runtime14collectHandlerFNdZPFC6ObjectZb@Base 6
+ _D4core7runtime7Runtime16moduleUnitTesterFNdPFZbZv@Base 6
+ _D4core7runtime7Runtime16moduleUnitTesterFNdZPFZb@Base 6
+ _D4core7runtime7Runtime19sm_moduleUnitTesterPFZb@Base 6
+ _D4core7runtime7Runtime4argsFNdZAAya@Base 6
+ _D4core7runtime7Runtime5cArgsFNdZS4core7runtime5CArgs@Base 6
+ _D4core7runtime7Runtime6__initZ@Base 6
+ _D4core7runtime7Runtime9terminateFDFC6object9ThrowableZvZb@Base 6
+ _D4core7runtime7Runtime9terminateFZb@Base 6
+ _D4core8demangle12__ModuleInfoZ@Base 6
+ _D4core8demangle12demangleTypeFAxaAaZAa@Base 6
+ _D4core8demangle15decodeDmdStringFAxaKkZAya@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle28__T10mangleFuncHTPFZPvTFZPvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle30__T10mangleFuncHTPFPvZvTFPvZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter10indexOfDotMxFNaNbNiNfZi@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter11__xopEqualsFKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterZb@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter5emptyMxFNaNbNdNiNfZb@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter5frontMxFNaNbNdNiNfZAxa@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter8popFrontMFNaNbNiNfZv@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter9__xtoHashFNbNeKxS4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitterZk@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11numToStringFNaNbNiNfAakZk@Base 6
+ _D4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle48__T10mangleFuncHTPFNaNbNePxvkkZkTFNaNbNePxvkkZkZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle48__T10mangleFuncHTPFNaNbNexkAaZAaTFNaNbNexkAaZAaZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle50__T10mangleFuncHTPFNaNbNexAaxAaZiTFNaNbNexAaxAaZiZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle52__T10mangleFuncHTPFNbPvMDFNbPvZiZvTFNbPvMDFNbPvZiZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle56__T10mangleFuncHTPFNbPvMDFNbPvPvZvZvTFNbPvMDFNbPvPvZvZvZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle74__T10mangleFuncHTPFNbNiAyaMDFNbNiAyaZAyabZAyaTFNbNiAyaMDFNbNiAyaZAyabZAyaZ10mangleFuncFNaNbNfAxaAaZAa@Base 6
+ _D4core8demangle7mangleCFAxaAaZAa@Base 6
+ _D4core8demangle8Demangle10isHexDigitFaZb@Base 6
+ _D4core8demangle8Demangle10parseLNameMFZv@Base 6
+ _D4core8demangle8Demangle10parseValueMFAaaZv@Base 6
+ _D4core8demangle8Demangle11__xopEqualsFKxS4core8demangle8DemangleKxS4core8demangle8DemangleZb@Base 6
+ _D4core8demangle8Demangle11sliceNumberMFZAxa@Base 6
+ _D4core8demangle8Demangle12decodeNumberMFAxaZk@Base 6
+ _D4core8demangle8Demangle12decodeNumberMFZk@Base 6
+ _D4core8demangle8Demangle12demangleNameMFZAa@Base 6
+ _D4core8demangle8Demangle12demangleTypeMFZAa@Base 6
+ _D4core8demangle8Demangle12val2HexDigitFhZa@Base 6
+ _D4core8demangle8Demangle13parseFuncAttrMFZv@Base 6
+ _D4core8demangle8Demangle14ParseException6__ctorMFNaNbNfAyaZC4core8demangle8Demangle14ParseException@Base 6
+ _D4core8demangle8Demangle14ParseException6__initZ@Base 6
+ _D4core8demangle8Demangle14ParseException6__vtblZ@Base 6
+ _D4core8demangle8Demangle14ParseException7__ClassZ@Base 6
+ _D4core8demangle8Demangle15parseSymbolNameMFZv@Base 6
+ _D4core8demangle8Demangle16isCallConventionFaZb@Base 6
+ _D4core8demangle8Demangle16parseMangledNameMFkZv@Base 6
+ _D4core8demangle8Demangle17OverflowException6__ctorMFNaNbNfAyaZC4core8demangle8Demangle17OverflowException@Base 6
+ _D4core8demangle8Demangle17OverflowException6__initZ@Base 6
+ _D4core8demangle8Demangle17OverflowException6__vtblZ@Base 6
+ _D4core8demangle8Demangle17OverflowException7__ClassZ@Base 6
+ _D4core8demangle8Demangle17parseIntegerValueMFAaaZv@Base 6
+ _D4core8demangle8Demangle17parseTemplateArgsMFZv@Base 6
+ _D4core8demangle8Demangle17parseTypeFunctionMFAaE4core8demangle8Demangle10IsDelegateZAa@Base 6
+ _D4core8demangle8Demangle18parseFuncArgumentsMFZv@Base 6
+ _D4core8demangle8Demangle18parseQualifiedNameMFZAa@Base 6
+ _D4core8demangle8Demangle19mayBeMangledNameArgMFZb@Base 6
+ _D4core8demangle8Demangle19parseCallConventionMFZv@Base 6
+ _D4core8demangle8Demangle19parseMangledNameArgMFZv@Base 6
+ _D4core8demangle8Demangle25mayBeTemplateInstanceNameMFZb@Base 6
+ _D4core8demangle8Demangle25parseTemplateInstanceNameMFZv@Base 6
+ _D4core8demangle8Demangle3eatMFaZv@Base 6
+ _D4core8demangle8Demangle3padMFAxaZv@Base 6
+ _D4core8demangle8Demangle3putMFAxaZAa@Base 6
+ _D4core8demangle8Demangle3tokMFZa@Base 6
+ _D4core8demangle8Demangle4nextMFZv@Base 6
+ _D4core8demangle8Demangle4testMFaZv@Base 6
+ _D4core8demangle8Demangle5errorFAyaZv@Base 6
+ _D4core8demangle8Demangle5matchMFAxaZv@Base 6
+ _D4core8demangle8Demangle5matchMFaZv@Base 6
+ _D4core8demangle8Demangle5shiftMFAxaZAa@Base 6
+ _D4core8demangle8Demangle61__T10doDemangleS42_D4core8demangle8Demangle9parseTypeMFAaZAaZ10doDemangleMFZAa@Base 6
+ _D4core8demangle8Demangle67__T10doDemangleS48_D4core8demangle8Demangle16parseMangledNameMFkZvZ10doDemangleMFZAa@Base 6
+ _D4core8demangle8Demangle6__ctorMFNcAxaAaZS4core8demangle8Demangle@Base 6
+ _D4core8demangle8Demangle6__ctorMFNcAxaE4core8demangle8Demangle7AddTypeAaZS4core8demangle8Demangle@Base 6
+ _D4core8demangle8Demangle6__initZ@Base 6
+ _D4core8demangle8Demangle6appendMFAxaZAa@Base 6
+ _D4core8demangle8Demangle6silentMFLvZv@Base 6
+ _D4core8demangle8Demangle7isAlphaFaZb@Base 6
+ _D4core8demangle8Demangle7isDigitFaZb@Base 6
+ _D4core8demangle8Demangle8containsFAxaAxaZb@Base 6
+ _D4core8demangle8Demangle8overflowFAyaZv@Base 6
+ _D4core8demangle8Demangle8putAsHexMFkiZAa@Base 6
+ _D4core8demangle8Demangle9__xtoHashFNbNeKxS4core8demangle8DemangleZk@Base 6
+ _D4core8demangle8Demangle9ascii2hexFaZh@Base 6
+ _D4core8demangle8Demangle9parseRealMFZv@Base 6
+ _D4core8demangle8Demangle9parseTypeMFAaZ10primitivesyG23Aa@Base 6
+ _D4core8demangle8Demangle9parseTypeMFAaZAa@Base 6
+ _D4core8demangle8demangleFAxaAaZAa@Base 6
+ _D4core8internal4hash12__ModuleInfoZ@Base 6
+ _D4core8internal4hash13__T6hashOfTkZ6hashOfFNaNbNekkZk@Base 6
+ _D4core8internal4hash14__T6hashOfTPkZ6hashOfFNaNbNeKPkkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ16__T6rotl32Vki13Z6rotl32FNaNbNiNfxkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ16__T6rotl32Vki15Z6rotl32FNaNbNiNfxkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ6fmix32FNaNbNfkZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZ9get32bitsFNaNbPxhZk@Base 6
+ _D4core8internal4hash9bytesHashFNaNbNePxvkkZk@Base 6
+ _D4core8internal6traits12__ModuleInfoZ@Base 6
+ _D4core8internal7convert11shiftrRoundFNaNbNfmZm@Base 6
+ _D4core8internal7convert12__ModuleInfoZ@Base 6
+ _D4core8internal7convert14__T7toUbyteTkZ7toUbyteFNaNbNeKkZAxh@Base 6
+ _D4core8internal7convert5Float6__initZ@Base 6
+ _D4core8internal7convert7binPow2FNaNbNfiZ10binPosPow2FNaNbNfiZe@Base 6
+ _D4core8internal7convert7binPow2FNaNbNfiZe@Base 6
+ _D4core9exception10RangeError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception10RangeError@Base 6
+ _D4core9exception10RangeError6__initZ@Base 6
+ _D4core9exception10RangeError6__vtblZ@Base 6
+ _D4core9exception10RangeError7__ClassZ@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfAyakZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__ctorMFNaNbNfC6object9ThrowableAyakZC4core9exception11AssertError@Base 6
+ _D4core9exception11AssertError6__initZ@Base 6
+ _D4core9exception11AssertError6__vtblZ@Base 6
+ _D4core9exception11AssertError7__ClassZ@Base 6
+ _D4core9exception11SwitchError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception11SwitchError@Base 6
+ _D4core9exception11SwitchError6__initZ@Base 6
+ _D4core9exception11SwitchError6__vtblZ@Base 6
+ _D4core9exception11SwitchError7__ClassZ@Base 6
+ _D4core9exception12__ModuleInfoZ@Base 6
+ _D4core9exception13FinalizeError6__ctorMFNaNbNfC8TypeInfoAyakC6object9ThrowableZC4core9exception13FinalizeError@Base 6
+ _D4core9exception13FinalizeError6__ctorMFNaNbNfC8TypeInfoC6object9ThrowableAyakZC4core9exception13FinalizeError@Base 6
+ _D4core9exception13FinalizeError6__initZ@Base 6
+ _D4core9exception13FinalizeError6__vtblZ@Base 6
+ _D4core9exception13FinalizeError7__ClassZ@Base 6
+ _D4core9exception13FinalizeError8toStringMxFNfZAya@Base 6
+ _D4core9exception13assertHandlerFNbNdNiNePFNbAyakAyaZvZv@Base 6
+ _D4core9exception13assertHandlerFNbNdNiNeZPFNbAyakAyaZv@Base 6
+ _D4core9exception14_assertHandlerPFNbAyakAyaZv@Base 6
+ _D4core9exception15HiddenFuncError6__ctorMFNaNbNfC14TypeInfo_ClassZC4core9exception15HiddenFuncError@Base 6
+ _D4core9exception15HiddenFuncError6__initZ@Base 6
+ _D4core9exception15HiddenFuncError6__vtblZ@Base 6
+ _D4core9exception15HiddenFuncError7__ClassZ@Base 6
+ _D4core9exception15onFinalizeErrorUNbNeC8TypeInfoC6object9ThrowableAyakZ3errC4core9exception13FinalizeError@Base 6
+ _D4core9exception16OutOfMemoryError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception16OutOfMemoryError@Base 6
+ _D4core9exception16OutOfMemoryError6__initZ@Base 6
+ _D4core9exception16OutOfMemoryError6__vtblZ@Base 6
+ _D4core9exception16OutOfMemoryError7__ClassZ@Base 6
+ _D4core9exception16OutOfMemoryError8toStringMxFNeZAya@Base 6
+ _D4core9exception16UnicodeException6__ctorMFNaNbNfAyakAyakC6object9ThrowableZC4core9exception16UnicodeException@Base 6
+ _D4core9exception16UnicodeException6__initZ@Base 6
+ _D4core9exception16UnicodeException6__vtblZ@Base 6
+ _D4core9exception16UnicodeException7__ClassZ@Base 6
+ _D4core9exception16setAssertHandlerFNbNiNePFNbAyakAyaZvZv@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__ctorMFNaNbNfAyakC6object9ThrowableZC4core9exception27InvalidMemoryOperationError@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__initZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError6__vtblZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError7__ClassZ@Base 6
+ _D4core9exception27InvalidMemoryOperationError8toStringMxFNeZAya@Base 6
+ _D50TypeInfo_HC4core6thread6ThreadC4core6thread6Thread6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc4Addr6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5posix7netinet3in_11sockaddr_in6__initZ@Base 6
+ _D50TypeInfo_S4core3sys5posix7pthread15pthread_cleanup6__initZ@Base 6
+ _D51TypeInfo_E4core4sync7rwmutex14ReadWriteMutex6Policy6__initZ@Base 6
+ _D51TypeInfo_S2rt19sections_elf_shared15CompilerDSOData6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix3sys5types14pthread_attr_t6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix3sys5types14pthread_cond_t6__initZ@Base 6
+ _D51TypeInfo_S4core3sys5posix7netinet3in_12sockaddr_in66__initZ@Base 6
+ _D52TypeInfo_S4core3sys5linux3elf11Elf32_gptab9_gt_entry6__initZ@Base 6
+ _D52TypeInfo_S4core3sys5linux3sys7inotify13inotify_event6__initZ@Base 6
+ _D52TypeInfo_S4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D53TypeInfo_S4core3sys5posix3sys5types16pthread_rwlock_t6__initZ@Base 6
+ _D53TypeInfo_xS4core3sys5posix3sys5types15pthread_mutex_t6__initZ@Base 6
+ _D54TypeInfo_S2rt5minfo11ModuleGroup9sortCtorsMFZ8StackRec6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5linux3elf11Elf32_gptab10_gt_header6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5linux5stdio21cookie_io_functions_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys5types17_pthread_fastlock6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys5types17pthread_barrier_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix3sys6socket16sockaddr_storage6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix6signal8sigevent11_sigev_un_t6__initZ@Base 6
+ _D54TypeInfo_S4core3sys5posix9semaphore17_pthread_fastlock6__initZ@Base 6
+ _D55TypeInfo_S2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5linux4tipc13sockaddr_tipc4Addr4Name6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5posix3sys5types18pthread_condattr_t6__initZ@Base 6
+ _D55TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t6__initZ@Base 6
+ _D56TypeInfo_S4core3sys5linux3sys8signalfd16signalfd_siginfo6__initZ@Base 6
+ _D56TypeInfo_S4core3sys5posix3sys5types19pthread_mutexattr_t6__initZ@Base 6
+ _D56TypeInfo_xS2rt4util9container5array13__T5ArrayTAvZ5Array6__initZ@Base 6
+ _D57TypeInfo_S4core3sys5posix3sys5types20pthread_rwlockattr_t6__initZ@Base 6
+ _D58TypeInfo_S3gcc6unwind3arm21_Unwind_Control_Block9_pr_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D58TypeInfo_S4core3sys5posix3sys5types21pthread_barrierattr_t6__initZ@Base 6
+ _D58TypeInfo_S4core3sys5posix7pthread23_pthread_cleanup_buffer6__initZ@Base 6
+ _D61TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t5_rt_t6__initZ@Base 6
+ _D62TypeInfo_S2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D63TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t7_kill_t6__initZ@Base 6
+ _D63TypeInfo_xS2gc9pooltable27__T9PoolTableTS2gc2gc4PoolZ9PoolTable6__initZ@Base 6
+ _D64TypeInfo_S3gcc6unwind3arm21_Unwind_Control_Block14_barrier_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D64TypeInfo_S3gcc6unwind3arm21_Unwind_Control_Block14_cleanup_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D64TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t8_timer_t6__initZ@Base 6
+ _D65TypeInfo_S2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D65TypeInfo_S3gcc6unwind3arm21_Unwind_Control_Block15_unwinder_cache6__initZ@Base 6.2.1-1ubuntu2
+ _D65TypeInfo_S4core4sync7rwmutex14ReadWriteMutex6Reader12MonitorProxy6__initZ@Base 6
+ _D65TypeInfo_S4core4sync7rwmutex14ReadWriteMutex6Writer12MonitorProxy6__initZ@Base 6
+ _D66TypeInfo_S2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D66TypeInfo_xS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap6__initZ@Base 6
+ _D67TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t10_sigpoll_t6__initZ@Base 6
+ _D67TypeInfo_xS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap6__initZ@Base 6
+ _D68TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t11_sigchild_t6__initZ@Base 6
+ _D68TypeInfo_S4core3sys5posix6signal9siginfo_t11_sifields_t11_sigfault_t6__initZ@Base 6
+ _D6Object6__initZ@Base 6
+ _D6Object6__vtblZ@Base 6
+ _D6Object7__ClassZ@Base 6
+ _D6object101__T7destroyTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ7destroyFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D6object10ModuleInfo11xgetMembersMxFNaNbNdZPv@Base 6
+ _D6object10ModuleInfo12localClassesMxFNaNbNdZAC14TypeInfo_Class@Base 6
+ _D6object10ModuleInfo15importedModulesMxFNaNbNdZAyPS6object10ModuleInfo@Base 6
+ _D6object10ModuleInfo4ctorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo4dtorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo4nameMxFNaNbNdZAya@Base 6
+ _D6object10ModuleInfo5flagsMxFNaNbNdZk@Base 6
+ _D6object10ModuleInfo5ictorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo5indexMxFNaNbNdZk@Base 6
+ _D6object10ModuleInfo6__initZ@Base 6
+ _D6object10ModuleInfo6addrOfMxFNaNbiZPv@Base 6
+ _D6object10ModuleInfo7opApplyFMDFPS6object10ModuleInfoZiZi@Base 6
+ _D6object10ModuleInfo7tlsctorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo7tlsdtorMxFNaNbNdZPFZv@Base 6
+ _D6object10ModuleInfo8opAssignMFxS6object10ModuleInfoZv@Base 6
+ _D6object10ModuleInfo8unitTestMxFNaNbNdZPFZv@Base 6
+ _D6object10__T3dupThZ3dupFNaNbNdNfAxhZAh@Base 6
+ _D6object10_xopEqualsFxPvxPvZb@Base 6
+ _D6object10getElementFNaNbNeNgC8TypeInfoZNgC8TypeInfo@Base 6
+ _D6object111__T16_destructRecurseTS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZ16_destructRecurseFNaNbNiNfKS2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4NodeZv@Base 6
+ _D6object11__T4idupTaZ4idupFNaNbNdNfAaZAya@Base 6
+ _D6object12__ModuleInfoZ@Base 6
+ _D6object12getArrayHashFNbNexC8TypeInfoxPvxkZ15hasCustomToHashFNaNbNexC8TypeInfoZb@Base 6
+ _D6object12getArrayHashFNbNexC8TypeInfoxPvxkZk@Base 6
+ _D6object12setSameMutexFOC6ObjectOC6ObjectZv@Base 6
+ _D6object14OffsetTypeInfo11__xopEqualsFKxS6object14OffsetTypeInfoKxS6object14OffsetTypeInfoZb@Base 6
+ _D6object14OffsetTypeInfo6__initZ@Base 6
+ _D6object14OffsetTypeInfo9__xtoHashFNbNeKxS6object14OffsetTypeInfoZk@Base 6
+ _D6object14TypeInfo_Array4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object14TypeInfo_Array4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Array5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Array5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Array6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Array6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Array7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Array7getHashMxFNbNexPvZk@Base 6
+ _D6object14TypeInfo_Array8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Array8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Class10ClassFlags6__initZ@Base 6
+ _D6object14TypeInfo_Class4findFxAaZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Class4infoMxFNaNbNdNiNfZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Class4initMxFNaNbNiNfZAxv@Base 6
+ _D6object14TypeInfo_Class5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Class5offTiMxFNaNbNdZAxS6object14OffsetTypeInfo@Base 6
+ _D6object14TypeInfo_Class5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Class6createMxFZC6Object@Base 6
+ _D6object14TypeInfo_Class6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Class6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object14TypeInfo_Class7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Class7getHashMxFNbNexPvZk@Base 6
+ _D6object14TypeInfo_Class8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Class8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Class8typeinfoMxFNaNbNdNiNfZxC14TypeInfo_Class@Base 6
+ _D6object14TypeInfo_Const4initMxFNaNbNiNfZAxv@Base 6
+ _D6object14TypeInfo_Const4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object14TypeInfo_Const4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Const5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Const5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Const6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Const6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Const7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Const7getHashMxFNbNfxPvZk@Base 6
+ _D6object14TypeInfo_Const8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Const8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Inout8toStringMxFNaNbNfZAya@Base 6
+ _D6object14TypeInfo_Tuple4swapMxFPvPvZv@Base 6
+ _D6object14TypeInfo_Tuple5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Tuple6equalsMxFxPvxPvZb@Base 6
+ _D6object14TypeInfo_Tuple6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object14TypeInfo_Tuple7compareMxFxPvxPvZi@Base 6
+ _D6object14TypeInfo_Tuple7destroyMxFPvZv@Base 6
+ _D6object14TypeInfo_Tuple7getHashMxFNbNfxPvZk@Base 6
+ _D6object14TypeInfo_Tuple8opEqualsMFC6ObjectZb@Base 6
+ _D6object14TypeInfo_Tuple8postblitMxFPvZv@Base 6
+ _D6object14TypeInfo_Tuple8toStringMxFNaNbNfZAya@Base 6
+ _D6object14__T4_dupTaTyaZ4_dupFNaNbAaZAya@Base 6
+ _D6object14__T4_dupTxhThZ4_dupFNaNbAxhZAh@Base 6
+ _D6object14__T6hashOfTPkZ6hashOfFNaNbNfPkkZk@Base 6
+ _D6object14__T7_rawDupTaZ7_rawDupFNaNbANgaZANga@Base 6
+ _D6object14__T7_rawDupThZ7_rawDupFNaNbANghZANgh@Base 6
+ _D6object15TypeInfo_Shared8toStringMxFNaNbNfZAya@Base 6
+ _D6object15TypeInfo_Struct11StructFlags6__initZ@Base 6
+ _D6object15TypeInfo_Struct4initMxFNaNbNiNfZAxv@Base 6
+ _D6object15TypeInfo_Struct5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Struct5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Struct6equalsMxFNaNbNexPvxPvZb@Base 6
+ _D6object15TypeInfo_Struct6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object15TypeInfo_Struct6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Struct7compareMxFNaNbNexPvxPvZi@Base 6
+ _D6object15TypeInfo_Struct7destroyMxFPvZv@Base 6
+ _D6object15TypeInfo_Struct7getHashMxFNaNbNfxPvZk@Base 6
+ _D6object15TypeInfo_Struct8opEqualsMFC6ObjectZb@Base 6
+ _D6object15TypeInfo_Struct8postblitMxFPvZv@Base 6
+ _D6object15TypeInfo_Struct8toStringMxFNaNbNfZAya@Base 6
+ _D6object15TypeInfo_Vector4initMxFNaNbNiNfZAxv@Base 6
+ _D6object15TypeInfo_Vector4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object15TypeInfo_Vector4swapMxFPvPvZv@Base 6
+ _D6object15TypeInfo_Vector5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Vector5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Vector6equalsMxFxPvxPvZb@Base 6
+ _D6object15TypeInfo_Vector6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object15TypeInfo_Vector7compareMxFxPvxPvZi@Base 6
+ _D6object15TypeInfo_Vector7getHashMxFNbNfxPvZk@Base 6
+ _D6object15TypeInfo_Vector8opEqualsMFC6ObjectZb@Base 6
+ _D6object15TypeInfo_Vector8toStringMxFNaNbNfZAya@Base 6
+ _D6object16TypeInfo_Pointer4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object16TypeInfo_Pointer4swapMxFPvPvZv@Base 6
+ _D6object16TypeInfo_Pointer5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Pointer5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Pointer6equalsMxFxPvxPvZb@Base 6
+ _D6object16TypeInfo_Pointer7compareMxFxPvxPvZi@Base 6
+ _D6object16TypeInfo_Pointer7getHashMxFNbNexPvZk@Base 6
+ _D6object16TypeInfo_Pointer8opEqualsMFC6ObjectZb@Base 6
+ _D6object16TypeInfo_Pointer8toStringMxFNaNbNfZAya@Base 6
+ _D6object16TypeInfo_Typedef4initMxFNaNbNiNfZAxv@Base 6
+ _D6object16TypeInfo_Typedef4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object16TypeInfo_Typedef4swapMxFPvPvZv@Base 6
+ _D6object16TypeInfo_Typedef5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Typedef5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Typedef6equalsMxFxPvxPvZb@Base 6
+ _D6object16TypeInfo_Typedef6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object16TypeInfo_Typedef6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object16TypeInfo_Typedef7compareMxFxPvxPvZi@Base 6
+ _D6object16TypeInfo_Typedef7getHashMxFNbNfxPvZk@Base 6
+ _D6object16TypeInfo_Typedef8opEqualsMFC6ObjectZb@Base 6
+ _D6object16TypeInfo_Typedef8toStringMxFNaNbNfZAya@Base 6
+ _D6object17TypeInfo_Delegate5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Delegate5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Delegate6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Delegate8opEqualsMFC6ObjectZb@Base 6
+ _D6object17TypeInfo_Delegate8toStringMxFNaNbNfZAya@Base 6
+ _D6object17TypeInfo_Function5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object17TypeInfo_Function8opEqualsMFC6ObjectZb@Base 6
+ _D6object17TypeInfo_Function8toStringMxFNaNbNfZAya@Base 6
+ _D6object18TypeInfo_Interface5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object18TypeInfo_Interface5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object18TypeInfo_Interface6equalsMxFxPvxPvZb@Base 6
+ _D6object18TypeInfo_Interface7compareMxFxPvxPvZi@Base 6
+ _D6object18TypeInfo_Interface7getHashMxFNbNexPvZk@Base 6
+ _D6object18TypeInfo_Interface8opEqualsMFC6ObjectZb@Base 6
+ _D6object18TypeInfo_Interface8toStringMxFNaNbNfZAya@Base 6
+ _D6object18TypeInfo_Invariant8toStringMxFNaNbNfZAya@Base 6
+ _D6object19__T11_doPostblitThZ11_doPostblitFNaNbNiNfAhZv@Base 6
+ _D6object20TypeInfo_StaticArray4initMxFNaNbNiNfZAxv@Base 6
+ _D6object20TypeInfo_StaticArray4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object20TypeInfo_StaticArray4swapMxFPvPvZv@Base 6
+ _D6object20TypeInfo_StaticArray5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object20TypeInfo_StaticArray5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object20TypeInfo_StaticArray6equalsMxFxPvxPvZb@Base 6
+ _D6object20TypeInfo_StaticArray6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object20TypeInfo_StaticArray7compareMxFxPvxPvZi@Base 6
+ _D6object20TypeInfo_StaticArray7destroyMxFPvZv@Base 6
+ _D6object20TypeInfo_StaticArray7getHashMxFNbNexPvZk@Base 6
+ _D6object20TypeInfo_StaticArray8opEqualsMFC6ObjectZb@Base 6
+ _D6object20TypeInfo_StaticArray8postblitMxFPvZv@Base 6
+ _D6object20TypeInfo_StaticArray8toStringMxFNaNbNfZAya@Base 6
+ _D6object20__T11_doPostblitTyaZ11_doPostblitFNaNbNiNfAyaZv@Base 6
+ _D6object20__T12_getPostblitThZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKhZv@Base 6
+ _D6object21__T12_getPostblitTyaZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKyaZv@Base 6
+ _D6object22__T11_trustedDupTaTyaZ11_trustedDupFNaNbNeAaZAya@Base 6
+ _D6object22__T11_trustedDupTxhThZ11_trustedDupFNaNbNeAxhZAh@Base 6
+ _D6object25TypeInfo_AssociativeArray4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object25TypeInfo_AssociativeArray5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object25TypeInfo_AssociativeArray5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object25TypeInfo_AssociativeArray6equalsMxFNexPvxPvZb@Base 6
+ _D6object25TypeInfo_AssociativeArray6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object25TypeInfo_AssociativeArray7getHashMxFNbNexPvZk@Base 6
+ _D6object25TypeInfo_AssociativeArray8opEqualsMFC6ObjectZb@Base 6
+ _D6object25TypeInfo_AssociativeArray8toStringMxFNaNbNfZAya@Base 6
+ _D6object38__T11_doPostblitTC4core6thread6ThreadZ11_doPostblitFNaNbNiNfAC4core6thread6ThreadZv@Base 6
+ _D6object39__T12_getPostblitTC4core6thread6ThreadZ12_getPostblitFNaNbNiNeZDFNaNbNiNfKC4core6thread6ThreadZv@Base 6
+ _D6object43__T7destroyTPS3gcc3deh18d_exception_headerZ7destroyFNaNbNiNfKPS3gcc3deh18d_exception_headerZv@Base 6
+ _D6object48__T7destroyTS2rt19sections_elf_shared9ThreadDSOZ7destroyFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D6object58__T16_destructRecurseTS2rt19sections_elf_shared9ThreadDSOZ16_destructRecurseFNaNbNiNfKS2rt19sections_elf_shared9ThreadDSOZv@Base 6
+ _D6object5Error6__ctorMFNaNbNiNfAyaAyakC6object9ThrowableZC6object5Error@Base 6
+ _D6object5Error6__ctorMFNaNbNiNfAyaC6object9ThrowableZC6object5Error@Base 6
+ _D6object5Error6__initZ@Base 6
+ _D6object5Error6__vtblZ@Base 6
+ _D6object5Error7__ClassZ@Base 6
+ _D6object6Object5opCmpMFC6ObjectZi@Base 6
+ _D6object6Object6toHashMFNbNeZk@Base 6
+ _D6object6Object7Monitor11__InterfaceZ@Base 6
+ _D6object6Object7factoryFAyaZC6Object@Base 6
+ _D6object6Object8opEqualsMFC6ObjectZb@Base 6
+ _D6object6Object8toStringMFZAya@Base 6
+ _D6object7AARange6__initZ@Base 6
+ _D6object7_xopCmpFxPvxPvZb@Base 6
+ _D6object8TypeInfo4initMxFNaNbNiNfZAxv@Base 6
+ _D6object8TypeInfo4nextMNgFNaNbNdNiZNgC8TypeInfo@Base 6
+ _D6object8TypeInfo4swapMxFPvPvZv@Base 6
+ _D6object8TypeInfo5flagsMxFNaNbNdNiNfZk@Base 6
+ _D6object8TypeInfo5offTiMxFZAxS6object14OffsetTypeInfo@Base 6
+ _D6object8TypeInfo5opCmpMFC6ObjectZi@Base 6
+ _D6object8TypeInfo5tsizeMxFNaNbNdNiNfZk@Base 6
+ _D6object8TypeInfo6equalsMxFxPvxPvZb@Base 6
+ _D6object8TypeInfo6rtInfoMxFNaNbNdNiNfZPyv@Base 6
+ _D6object8TypeInfo6talignMxFNaNbNdNiNfZk@Base 6
+ _D6object8TypeInfo6toHashMxFNbNeZk@Base 6
+ _D6object8TypeInfo7compareMxFxPvxPvZi@Base 6
+ _D6object8TypeInfo7destroyMxFPvZv@Base 6
+ _D6object8TypeInfo7getHashMxFNbNexPvZk@Base 6
+ _D6object8TypeInfo8opEqualsMFC6ObjectZb@Base 6
+ _D6object8TypeInfo8postblitMxFPvZv@Base 6
+ _D6object8TypeInfo8toStringMxFNaNbNfZAya@Base 6
+ _D6object8opEqualsFC6ObjectC6ObjectZb@Base 6
+ _D6object8opEqualsFxC6ObjectxC6ObjectZb@Base 6
+ _D6object94__T4keysHTHC4core6thread6ThreadC4core6thread6ThreadTC4core6thread6ThreadTC4core6thread6ThreadZ4keysFNaNbNdHC4core6thread6ThreadC4core6thread6ThreadZAC4core6thread6Thread@Base 6
+ _D6object9Exception6__ctorMFNaNbNiNfAyaAyakC6object9ThrowableZC9Exception@Base 6
+ _D6object9Exception6__ctorMFNaNbNiNfAyaC6object9ThrowableAyakZC9Exception@Base 6
+ _D6object9Interface11__xopEqualsFKxS6object9InterfaceKxS6object9InterfaceZb@Base 6
+ _D6object9Interface6__initZ@Base 6
+ _D6object9Interface9__xtoHashFNbNeKxS6object9InterfaceZk@Base 6
+ _D6object9Throwable6__ctorMFNaNbNiNfAyaAyakC6object9ThrowableZC6object9Throwable@Base 6
+ _D6object9Throwable6__ctorMFNaNbNiNfAyaC6object9ThrowableZC6object9Throwable@Base 6
+ _D6object9Throwable6__initZ@Base 6
+ _D6object9Throwable6__vtblZ@Base 6
+ _D6object9Throwable7__ClassZ@Base 6
+ _D6object9Throwable8toStringMFZAya@Base 6
+ _D6object9Throwable8toStringMxFMDFxAaZvZv@Base 6
+ _D6object9Throwable9TraceInfo11__InterfaceZ@Base 6
+ _D70TypeInfo_S2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D71TypeInfo_S2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D71TypeInfo_S4core3sys5posix6signal8sigevent11_sigev_un_t15_sigev_thread_t6__initZ@Base 6
+ _D71TypeInfo_xS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_PxS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_S3gcc6unwind2pe28read_encoded_value_with_baseFhkPhPkZ9unaligned6__initZ@Base 6
+ _D72TypeInfo_xPS2rt4util9container5treap23__T5TreapTS2gc2gc4RootZ5Treap4Node6__initZ@Base 6
+ _D72TypeInfo_xS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D73TypeInfo_PxS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D73TypeInfo_xPS2rt4util9container5treap24__T5TreapTS2gc2gc5RangeZ5Treap4Node6__initZ@Base 6
+ _D75TypeInfo_S4core8demangle16__T6mangleTFZPvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D76TypeInfo_S4core8demangle17__T6mangleTFPvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D78TypeInfo_S4core4time42__T12MonoTimeImplVE4core4time9ClockTypei0Z12MonoTimeImpl6__initZ@Base 6
+ _D83TypeInfo_S2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D84TypeInfo_xS2rt4util9container5array41__T5ArrayTPS2rt19sections_elf_shared3DSOZ5Array6__initZ@Base 6
+ _D85TypeInfo_S4core8demangle26__T6mangleTFNaNbNePxvkkZkZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D85TypeInfo_S4core8demangle26__T6mangleTFNaNbNexkAaZAaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D86TypeInfo_S4core8demangle27__T6mangleTFNaNbNexAaxAaZiZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D87TypeInfo_S4core8demangle28__T6mangleTFNbPvMDFNbPvZiZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D88TypeInfo_S2rt4util9container5array46__T5ArrayTS2rt19sections_elf_shared9ThreadDSOZ5Array6__initZ@Base 6
+ _D89TypeInfo_S4core8demangle30__T6mangleTFNbPvMDFNbPvPvZvZvZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D8TypeInfo6__initZ@Base 6
+ _D8TypeInfo6__vtblZ@Base 6
+ _D8TypeInfo7__ClassZ@Base 6
+ _D92TypeInfo_S2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab6__initZ@Base 6
+ _D97TypeInfo_S2rt4util9container7hashtab46__T7HashTabTPvTPS2rt19sections_elf_shared3DSOZ7HashTab4Node6__initZ@Base 6
+ _D98TypeInfo_S4core8demangle39__T6mangleTFNbNiAyaMDFNbNiAyaZAyabZAyaZ6mangleFNaNbNfAxaAaZ11DotSplitter6__initZ@Base 6
+ _D9Exception6__initZ@Base 6
+ _D9Exception6__vtblZ@Base 6
+ _D9Exception7__ClassZ@Base 6
+ _D9invariant12__ModuleInfoZ@Base 6
+ _D9invariant12_d_invariantFC6ObjectZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Reader4lockMFNeZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Reader6unlockMFNeZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Writer4lockMFNeZv@Base 6
+ _DT16_D4core4sync7rwmutex14ReadWriteMutex6Writer6unlockMFNeZv@Base 6
+ _DT36_D2gc2gc7GCMutex4lockMFNbNiNeZv@Base 6
+ _DT36_D2gc2gc7GCMutex6unlockMFNbNiNeZv@Base 6
+ _DT36_D4core4sync5mutex5Mutex4lockMFNeZv@Base 6
+ _DT36_D4core4sync5mutex5Mutex6unlockMFNeZv@Base 6
+ _DT660_D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKkKxAaZiZi@Base 6
+ _DT660_D3gcc9backtrace12LibBacktrace7opApplyMxFMDFKxAaZiZi@Base 6
+ _DT660_D3gcc9backtrace12LibBacktrace8toStringMxFZAya@Base 6
+ _TTYPE_ENCODING@Base 6.2.1-1ubuntu2
+ _Unwind_GetGR@Base 6.2.1-1ubuntu2
+ _Unwind_GetIP@Base 6.2.1-1ubuntu2
+ _Unwind_GetIPInfo@Base 6.2.1-1ubuntu2
+ _Unwind_SetGR@Base 6.2.1-1ubuntu2
+ _Unwind_SetIP@Base 6.2.1-1ubuntu2
+ _Unwind_decode_typeinfo_ptr@Base 6.2.1-1ubuntu2
+ __gdc_begin_catch@Base 6
+ __gdc_exception_cleanup@Base 6
+ __gdc_personality_v0@Base 6
+ __gnu_unwind_24bit@Base 6.2.1-1ubuntu2
+ __mod_ref__D2gc2gc12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc2os12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc4bits12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc5proxy12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc5stats12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D2gc9pooltable12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt11arrayassign12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt12sections_osx12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt14sections_win3212__ModuleInfoZ@Base 6
+ __mod_ref__D2rt14sections_win6412__ModuleInfoZ@Base 6
+ __mod_ref__D2rt16sections_android12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt16sections_solaris12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt19sections_elf_shared12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3aaA12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3adi12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3deh12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt3obj12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util3utf12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util4hash12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util5array12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util6random12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util6string12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util8typeinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container5array12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container5treap12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container6common12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt4util9container7hashtab12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5cast_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5minfo12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5qsort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt5tlsgc12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6aApply12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6config12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6dmain212__ModuleInfoZ@Base 6
+ __mod_ref__D2rt6memory12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt7aApplyR12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt7switch_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8arraycat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8lifetime12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8monitor_12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8sections12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_Acfloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_Adouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_cdouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo10ti_idouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo11ti_Acdouble12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo11ti_delegate12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo4ti_C12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo5ti_AC12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo5ti_Ag12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo6ti_int12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo6ti_ptr12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_Aint12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_byte12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_cent12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_char12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_long12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_real12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_uint12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo7ti_void12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_Along12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_Areal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_creal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_dchar12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_float12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ireal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_short12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ubyte12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ucent12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_ulong12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo8ti_wchar12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Acreal12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Afloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_Ashort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_cfloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_double12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_ifloat12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt8typeinfo9ti_ushort12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt9arraycast12__ModuleInfoZ@Base 6
+ __mod_ref__D2rt9critical_12__ModuleInfoZ@Base 6
+ __mod_ref__D3etc5linux11memoryerror12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc12libbacktrace12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc3deh12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind2pe12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind3arm12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc6unwind7generic12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc7atomics12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc8builtins12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc9attribute12__ModuleInfoZ@Base 6
+ __mod_ref__D3gcc9backtrace12__ModuleInfoZ@Base 6
+ __mod_ref__D4core10checkedint12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3elf12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys4mman12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys5xattr12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys7inotify12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys7sysinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux3sys8signalfd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4link12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux4tipc12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5dlfcn12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5epoll12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5errno12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5linux8execinfo12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3grp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3net3if_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3pwd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys2un12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3ipc12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3msg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3shm12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys3uio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4mman12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4stat12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys4wait12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys5ioctl12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys5types12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys6select12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys6socket12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys7statvfs12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys7utsname12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix3sys8resource12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4arpa4inet12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4poll12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5dlfcn12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5fcntl12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5netdb12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5sched12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix5utime12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6dirent12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6setjmp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6signal12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6syslog12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix6unistd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7netinet3in_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7netinet3tcp12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7pthread12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix7termios12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix8inttypes12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix8ucontext12__ModuleInfoZ@Base 6
+ __mod_ref__D4core3sys5posix9semaphore12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4math12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4simd12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4fenv12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4math12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5ctype12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5errno12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc5stdio12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6float_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6limits12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6locale12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6signal12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdarg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stddef12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdint12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6stdlib12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6string12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6tgmath12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6wchar_12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc6wctype12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc7complex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4stdc8inttypes12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync5mutex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync6config12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync7barrier12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync7rwmutex12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9condition12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4sync9semaphore12__ModuleInfoZ@Base 6
+ __mod_ref__D4core4time12__ModuleInfoZ@Base 6
+ __mod_ref__D4core5bitop12__ModuleInfoZ@Base 6
+ __mod_ref__D4core5cpuid12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6atomic12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6memory12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6thread12__ModuleInfoZ@Base 6
+ __mod_ref__D4core6vararg12__ModuleInfoZ@Base 6
+ __mod_ref__D4core7runtime12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8demangle12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal4hash12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal6traits12__ModuleInfoZ@Base 6
+ __mod_ref__D4core8internal7convert12__ModuleInfoZ@Base 6
+ __mod_ref__D4core9exception12__ModuleInfoZ@Base 6
+ __mod_ref__D6object12__ModuleInfoZ@Base 6
+ __mod_ref__D9invariant12__ModuleInfoZ@Base 6
+ _aApplyRcd1@Base 6
+ _aApplyRcd2@Base 6
+ _aApplyRcw1@Base 6
+ _aApplyRcw2@Base 6
+ _aApplyRdc1@Base 6
+ _aApplyRdc2@Base 6
+ _aApplyRdw1@Base 6
+ _aApplyRdw2@Base 6
+ _aApplyRwc1@Base 6
+ _aApplyRwc2@Base 6
+ _aApplyRwd1@Base 6
+ _aApplyRwd2@Base 6
+ _aApplycd1@Base 6
+ _aApplycd2@Base 6
+ _aApplycw1@Base 6
+ _aApplycw2@Base 6
+ _aApplydc1@Base 6
+ _aApplydc2@Base 6
+ _aApplydw1@Base 6
+ _aApplydw2@Base 6
+ _aApplywc1@Base 6
+ _aApplywc2@Base 6
+ _aApplywd1@Base 6
+ _aApplywd2@Base 6
+ _aaApply2@Base 6
+ _aaApply@Base 6
+ _aaDelX@Base 6
+ _aaEqual@Base 6
+ _aaGetHash@Base 6
+ _aaGetRvalueX@Base 6
+ _aaGetY@Base 6
+ _aaInX@Base 6
+ _aaKeys@Base 6
+ _aaLen@Base 6
+ _aaRange@Base 6
+ _aaRangeEmpty@Base 6
+ _aaRangeFrontKey@Base 6
+ _aaRangeFrontValue@Base 6
+ _aaRangePopFront@Base 6
+ _aaRehash@Base 6
+ _aaValues@Base 6
+ _aaVersion@Base 6
+ _adCmp2@Base 6
+ _adCmp@Base 6
+ _adCmpChar@Base 6
+ _adEq2@Base 6
+ _adEq@Base 6
+ _adReverse@Base 6
+ _adReverseChar@Base 6
+ _adReverseWchar@Base 6
+ _adSort@Base 6
+ _adSortChar@Base 6
+ _adSortWchar@Base 6
+ _d_allocmemory@Base 6
+ _d_array_bounds@Base 6
+ _d_arrayappendT@Base 6
+ _d_arrayappendcTX@Base 6
+ _d_arrayappendcd@Base 6
+ _d_arrayappendwd@Base 6
+ _d_arrayassign@Base 6
+ _d_arrayassign_l@Base 6
+ _d_arrayassign_r@Base 6
+ _d_arraybounds@Base 6
+ _d_arraycast@Base 6
+ _d_arraycatT@Base 6
+ _d_arraycatnTX@Base 6
+ _d_arraycopy@Base 6
+ _d_arrayctor@Base 6
+ _d_arrayliteralTX@Base 6
+ _d_arraysetassign@Base 6
+ _d_arraysetcapacity@Base 6
+ _d_arraysetctor@Base 6
+ _d_arraysetlengthT@Base 6
+ _d_arraysetlengthiT@Base 6
+ _d_arrayshrinkfit@Base 6
+ _d_assert@Base 6
+ _d_assert_msg@Base 6
+ _d_assertm@Base 6
+ _d_assocarrayliteralTX@Base 6
+ _d_callfinalizer@Base 6
+ _d_callinterfacefinalizer@Base 6
+ _d_createTrace@Base 6
+ _d_critical_init@Base 6
+ _d_critical_term@Base 6
+ _d_criticalenter@Base 6
+ _d_criticalexit@Base 6
+ _d_delarray@Base 6
+ _d_delarray_t@Base 6
+ _d_delclass@Base 6
+ _d_delinterface@Base 6
+ _d_delmemory@Base 6
+ _d_delstruct@Base 6
+ _d_dso_registry@Base 6
+ _d_dynamic_cast@Base 6
+ _d_initMonoTime@Base 6
+ _d_interface_cast@Base 6
+ _d_interface_vtbl@Base 6
+ _d_isbaseof2@Base 6
+ _d_isbaseof@Base 6
+ _d_main_args@Base 6
+ _d_monitor_staticctor@Base 6
+ _d_monitor_staticdtor@Base 6
+ _d_monitordelete@Base 6
+ _d_monitorenter@Base 6
+ _d_monitorexit@Base 6
+ _d_newarrayT@Base 6
+ _d_newarrayU@Base 6
+ _d_newarrayiT@Base 6
+ _d_newarraymTX@Base 6
+ _d_newarraymiTX@Base 6
+ _d_newclass@Base 6
+ _d_newitemT@Base 6
+ _d_newitemU@Base 6
+ _d_newitemiT@Base 6
+ _d_obj_cmp@Base 6
+ _d_obj_eq@Base 6
+ _d_print_throwable@Base 6
+ _d_run_main@Base 6
+ _d_setSameMutex@Base 6
+ _d_switch_dstring@Base 6
+ _d_switch_error@Base 6
+ _d_switch_errorm@Base 6
+ _d_switch_string@Base 6
+ _d_switch_ustring@Base 6
+ _d_throw@Base 6
+ _d_toObject@Base 6
+ _d_traceContext@Base 6
+ _d_unittest@Base 6
+ _d_unittest_msg@Base 6
+ _d_unittestm@Base 6
+ backtrace_alloc@Base 6
+ backtrace_close@Base 6
+ backtrace_create_state@Base 6
+ backtrace_dwarf_add@Base 6
+ backtrace_free@Base 6
+ backtrace_full@Base 6
+ backtrace_get_view@Base 6
+ backtrace_initialize@Base 6
+ backtrace_open@Base 6
+ backtrace_pcinfo@Base 6
+ backtrace_print@Base 6
+ backtrace_qsort@Base 6
+ backtrace_release_view@Base 6
+ backtrace_simple@Base 6
+ backtrace_syminfo@Base 6
+ backtrace_vector_finish@Base 6
+ backtrace_vector_grow@Base 6
+ backtrace_vector_release@Base 6
+ fiber_entryPoint@Base 6
+ fiber_switchContext@Base 6
+ gc_addRange@Base 6
+ gc_addRoot@Base 6
+ gc_addrOf@Base 6
+ gc_calloc@Base 6
+ gc_clrAttr@Base 6
+ gc_clrProxy@Base 6
+ gc_collect@Base 6
+ gc_disable@Base 6
+ gc_enable@Base 6
+ gc_extend@Base 6
+ gc_free@Base 6
+ gc_getAttr@Base 6
+ gc_getProxy@Base 6
+ gc_init@Base 6
+ gc_malloc@Base 6
+ gc_minimize@Base 6
+ gc_qalloc@Base 6
+ gc_query@Base 6
+ gc_realloc@Base 6
+ gc_removeRange@Base 6
+ gc_removeRoot@Base 6
+ gc_reserve@Base 6
+ gc_runFinalizers@Base 6
+ gc_setAttr@Base 6
+ gc_setProxy@Base 6
+ gc_sizeOf@Base 6
+ gc_stats@Base 6
+ gc_term@Base 6
+ getErrno@Base 6
+ lifetime_init@Base 6
+ onAssertError@Base 6
+ onAssertErrorMsg@Base 6
+ onFinalizeError@Base 6
+ onHiddenFuncError@Base 6
+ onInvalidMemoryOperationError@Base 6
+ onOutOfMemoryError@Base 6
+ onRangeError@Base 6
+ onSwitchError@Base 6
+ onUnicodeError@Base 6
+ onUnittestErrorMsg@Base 6
+ pcinfoCallback@Base 6
+ pcinfoErrorCallback@Base 6
+ rt_args@Base 6
+ rt_attachDisposeEvent@Base 6
+ rt_cArgs@Base 6
+ rt_cmdline_enabled@Base 6
+ rt_detachDisposeEvent@Base 6
+ rt_envvars_enabled@Base 6
+ rt_finalize2@Base 6
+ rt_finalize@Base 6
+ rt_finalizeFromGC@Base 6
+ rt_getCollectHandler@Base 6
+ rt_getTraceHandler@Base 6
+ rt_hasFinalizerInSegment@Base 6
+ rt_init@Base 6
+ rt_loadLibrary@Base 6
+ rt_moduleCtor@Base 6
+ rt_moduleDtor@Base 6
+ rt_moduleTlsCtor@Base 6
+ rt_moduleTlsDtor@Base 6
+ rt_options@Base 6
+ rt_setCollectHandler@Base 6
+ rt_setTraceHandler@Base 6
+ rt_term@Base 6
+ rt_trapExceptions@Base 6
+ rt_unloadLibrary@Base 6
+ runModuleUnitTests@Base 6
+ setErrno@Base 6
+ simpleCallback@Base 6
+ simpleErrorCallback@Base 6
+ syminfoCallback2@Base 6
+ syminfoCallback@Base 6
+ thread_attachThis@Base 6
+ thread_detachByAddr@Base 6
+ thread_detachInstance@Base 6
+ thread_detachThis@Base 6
+ thread_enterCriticalRegion@Base 6
+ thread_entryPoint@Base 6
+ thread_exitCriticalRegion@Base 6
+ thread_inCriticalRegion@Base 6
+ thread_init@Base 6
+ thread_isMainThread@Base 6
+ thread_joinAll@Base 6
+ thread_processGCMarks@Base 6
+ thread_resumeAll@Base 6
+ thread_resumeHandler@Base 6
+ thread_scanAll@Base 6
+ thread_scanAllType@Base 6
+ thread_setGCSignals@Base 6
+ thread_setThis@Base 6
+ thread_stackBottom@Base 6
+ thread_stackTop@Base 6
+ thread_suspendAll@Base 6
+ thread_suspendHandler@Base 6
+ thread_term@Base 6
+ tipc_addr@Base 6
+ tipc_cluster@Base 6
+ tipc_node@Base 6
+ tipc_zone@Base 6
--- gcc-6-6.3.0.orig/debian/libitm.symbols
+++ gcc-6-6.3.0/debian/libitm.symbols
@@ -0,0 +1,3 @@
+libitm.so.1 #PACKAGE# #MINVER#
+ (symver)LIBITM_1.0 4.7
+ (symver)LIBITM_1.1 6
--- gcc-6-6.3.0.orig/debian/liblsan0.symbols
+++ gcc-6-6.3.0/debian/liblsan0.symbols
@@ -0,0 +1,118 @@
+liblsan.so.0 liblsan0 #MINVER#
+ _ZN11__sanitizer11CheckFailedEPKciS1_yy@Base 4.9
+ _ZN11__sanitizer7OnPrintEPKc@Base 4.9
+ _ZdaPv@Base 4.9
+ _ZdaPvRKSt9nothrow_t@Base 4.9
+ _ZdlPv@Base 4.9
+ _ZdlPvRKSt9nothrow_t@Base 4.9
+ _Znam@Base 4.9
+ _ZnamRKSt9nothrow_t@Base 4.9
+ _Znwm@Base 4.9
+ _ZnwmRKSt9nothrow_t@Base 4.9
+ __asan_backtrace_alloc@Base 4.9
+ __asan_backtrace_close@Base 4.9
+ __asan_backtrace_create_state@Base 4.9
+ __asan_backtrace_dwarf_add@Base 4.9
+ __asan_backtrace_free@Base 4.9
+ __asan_backtrace_get_view@Base 4.9
+ __asan_backtrace_initialize@Base 4.9
+ __asan_backtrace_open@Base 4.9
+ __asan_backtrace_pcinfo@Base 4.9
+ __asan_backtrace_qsort@Base 4.9
+ __asan_backtrace_release_view@Base 4.9
+ __asan_backtrace_syminfo@Base 4.9
+ __asan_backtrace_vector_finish@Base 4.9
+ __asan_backtrace_vector_grow@Base 4.9
+ __asan_backtrace_vector_release@Base 4.9
+ __asan_cplus_demangle_builtin_types@Base 4.9
+ __asan_cplus_demangle_fill_ctor@Base 4.9
+ __asan_cplus_demangle_fill_dtor@Base 4.9
+ __asan_cplus_demangle_fill_extended_operator@Base 4.9
+ __asan_cplus_demangle_fill_name@Base 4.9
+ __asan_cplus_demangle_init_info@Base 4.9
+ __asan_cplus_demangle_mangled_name@Base 4.9
+ __asan_cplus_demangle_operators@Base 4.9
+ __asan_cplus_demangle_print@Base 4.9
+ __asan_cplus_demangle_print_callback@Base 4.9
+ __asan_cplus_demangle_type@Base 4.9
+ __asan_cplus_demangle_v3@Base 4.9
+ __asan_cplus_demangle_v3_callback@Base 4.9
+ __asan_internal_memcmp@Base 4.9
+ __asan_internal_memcpy@Base 4.9
+ __asan_internal_memset@Base 4.9
+ __asan_internal_strcmp@Base 4.9
+ __asan_internal_strlen@Base 4.9
+ __asan_internal_strncmp@Base 4.9
+ __asan_internal_strnlen@Base 4.9
+ __asan_is_gnu_v3_mangled_ctor@Base 4.9
+ __asan_is_gnu_v3_mangled_dtor@Base 4.9
+ __asan_java_demangle_v3@Base 4.9
+ __asan_java_demangle_v3_callback@Base 4.9
+ __interceptor___libc_memalign@Base 4.9
+ __interceptor_aligned_alloc@Base 5
+ __interceptor_calloc@Base 4.9
+ __interceptor_cfree@Base 4.9
+ __interceptor_free@Base 4.9
+ __interceptor_mallinfo@Base 4.9
+ __interceptor_malloc@Base 4.9
+ __interceptor_malloc_usable_size@Base 4.9
+ __interceptor_mallopt@Base 4.9
+ __interceptor_memalign@Base 4.9
+ __interceptor_posix_memalign@Base 4.9
+ __interceptor_pthread_create@Base 4.9
+ __interceptor_pthread_join@Base 4.9
+ __interceptor_pvalloc@Base 4.9
+ __interceptor_realloc@Base 4.9
+ __interceptor_valloc@Base 4.9
+ __libc_memalign@Base 4.9
+ __lsan_disable@Base 4.9
+ __lsan_do_leak_check@Base 4.9
+ __lsan_do_recoverable_leak_check@Base 6
+ __lsan_enable@Base 4.9
+ __lsan_ignore_object@Base 4.9
+ __lsan_register_root_region@Base 5
+ __lsan_unregister_root_region@Base 5
+ __sanitizer_cov@Base 4.9
+ __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_cov_trace_basic_block@Base 6
+ __sanitizer_cov_trace_cmp@Base 6
+ __sanitizer_cov_trace_func_enter@Base 6
+ __sanitizer_cov_trace_switch@Base 6
+ __sanitizer_cov_with_check@Base 6
+ __sanitizer_get_allocated_size@Base 5
+ __sanitizer_get_coverage_guards@Base 6
+ __sanitizer_get_current_allocated_bytes@Base 5
+ __sanitizer_get_estimated_allocated_size@Base 5
+ __sanitizer_get_free_bytes@Base 5
+ __sanitizer_get_heap_size@Base 5
+ __sanitizer_get_number_of_counters@Base 6
+ __sanitizer_get_ownership@Base 5
+ __sanitizer_get_total_unique_caller_callee_pairs@Base 6
+ __sanitizer_get_total_unique_coverage@Base 6
+ __sanitizer_get_unmapped_bytes@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_print_stack_trace@Base 5
+ __sanitizer_report_error_summary@Base 4.9
+ __sanitizer_reset_coverage@Base 6
+ __sanitizer_sandbox_on_notify@Base 4.9
+ __sanitizer_set_death_callback@Base 6
+ __sanitizer_set_report_path@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6
+ aligned_alloc@Base 5
+ calloc@Base 4.9
+ cfree@Base 4.9
+ free@Base 4.9
+ mallinfo@Base 4.9
+ malloc@Base 4.9
+ malloc_usable_size@Base 4.9
+ mallopt@Base 4.9
+ memalign@Base 4.9
+ posix_memalign@Base 4.9
+ pthread_create@Base 4.9
+ pthread_join@Base 4.9
+ pvalloc@Base 4.9
+ realloc@Base 4.9
+ valloc@Base 4.9
--- gcc-6-6.3.0.orig/debian/libmpx.symbols
+++ gcc-6-6.3.0/debian/libmpx.symbols
@@ -0,0 +1,5 @@
+libmpx.so.2 #PACKAGE# #MINVER#
+ (symver)LIBMPX_1.0 5
+ (symver)LIBMPX_2.0 6
+libmpxwrappers.so.2 #PACKAGE# #MINVER#
+ (symver)LIBMPXWRAPPERS_1.0 5
--- gcc-6-6.3.0.orig/debian/libobjc.symbols
+++ gcc-6-6.3.0/debian/libobjc.symbols
@@ -0,0 +1,9 @@
+libobjc.so.4 #PACKAGE# #MINVER#
+#include "libobjc.symbols.common"
+ __gnu_objc_personality_v0@Base 4.2.1
+ (arch=armel armhf)__objc_exception_class@Base 4.3.0
+libobjc_gc.so.4 #PACKAGE# #MINVER#
+#include "libobjc.symbols.common"
+#include "libobjc.symbols.gc"
+ __gnu_objc_personality_v0@Base 4.2.1
+ (arch=armel armhf)__objc_exception_class@Base 4.3.0
--- gcc-6-6.3.0.orig/debian/libobjc.symbols.common
+++ gcc-6-6.3.0/debian/libobjc.symbols.common
@@ -0,0 +1,205 @@
+ __objc_accessors_init@Base 4.6
+ __objc_add_class_to_hash@Base 4.2.1
+ __objc_class_links_resolved@Base 4.2.1
+ __objc_class_name_NXConstantString@Base 4.2.1
+ __objc_class_name_Object@Base 4.2.1
+ __objc_class_name_Protocol@Base 4.2.1
+ __objc_dangling_categories@Base 4.2.1
+ __objc_exec_class@Base 4.2.1
+ __objc_force_linking@Base 4.2.1
+ __objc_generate_gc_type_description@Base 4.2.1
+ __objc_get_forward_imp@Base 4.2.1
+ __objc_init_class@Base 4.6
+ __objc_init_class_tables@Base 4.2.1
+ __objc_init_dispatch_tables@Base 4.2.1
+ __objc_init_selector_tables@Base 4.2.1
+ __objc_init_thread_system@Base 4.2.1
+ __objc_install_premature_dtable@Base 4.2.1
+ __objc_is_multi_threaded@Base 4.2.1
+ __objc_linking@Base 4.2.1
+ __objc_msg_forward@Base 4.2.1
+ __objc_msg_forward2@Base 4.3
+ __objc_print_dtable_stats@Base 4.2.1
+ __objc_protocols_add_protocol@Base 4.6
+ __objc_protocols_init@Base 4.6
+ __objc_register_instance_methods_to_class@Base 4.2.1
+ __objc_register_selectors_from_class@Base 4.2.1
+ __objc_register_selectors_from_description_list@Base 4.6
+ __objc_register_selectors_from_list@Base 4.2.1
+ __objc_register_selectors_from_module@Base 4.6
+ __objc_resolve_class_links@Base 4.2.1
+ __objc_responds_to@Base 4.2.1
+ __objc_runtime_mutex@Base 4.2.1
+ __objc_runtime_threads_alive@Base 4.2.1
+ __objc_selector_max_index@Base 4.2.1
+ __objc_sparse2_id@Base 4.2.1
+ __objc_sync_init@Base 4.6
+ __objc_thread_exit_status@Base 4.2.1
+ __objc_uninstalled_dtable@Base 4.2.1
+ __objc_update_classes_with_methods@Base 4.6
+ __objc_update_dispatch_table_for_class@Base 4.2.1
+ _objc_abort@Base 4.6
+ _objc_became_multi_threaded@Base 4.2.1
+ _objc_load_callback@Base 4.2.1
+ _objc_lookup_class@Base 4.6
+ class_addIvar@Base 4.6
+ class_addMethod@Base 4.6
+ class_addProtocol@Base 4.6
+ class_add_method_list@Base 4.2.1
+ class_conformsToProtocol@Base 4.6
+ class_copyIvarList@Base 4.6
+ class_copyMethodList@Base 4.6
+ class_copyPropertyList@Base 4.6
+ class_copyProtocolList@Base 4.6
+ class_createInstance@Base 4.6
+ class_getClassMethod@Base 4.6
+ class_getClassVariable@Base 4.6
+ class_getInstanceMethod@Base 4.6
+ class_getInstanceSize@Base 4.6
+ class_getInstanceVariable@Base 4.6
+ class_getIvarLayout@Base 4.6
+ class_getMethodImplementation@Base 4.6
+ class_getName@Base 4.6
+ class_getProperty@Base 4.6
+ class_getSuperclass@Base 4.6
+ class_getVersion@Base 4.6
+ class_getWeakIvarLayout@Base 4.6
+ class_isMetaClass@Base 4.6
+ class_ivar_set_gcinvisible@Base 4.2.1
+ class_replaceMethod@Base 4.6
+ class_respondsToSelector@Base 4.6
+ class_setIvarLayout@Base 4.6
+ class_setVersion@Base 4.6
+ class_setWeakIvarLayout@Base 4.6
+ get_imp@Base 4.2.1
+ idxsize@Base 4.2.1
+ ivar_getName@Base 4.6
+ ivar_getOffset@Base 4.6
+ ivar_getTypeEncoding@Base 4.6
+ method_copyArgumentType@Base 4.6
+ method_copyReturnType@Base 4.6
+ method_exchangeImplementations@Base 4.6
+ method_getArgumentType@Base 4.6
+ method_getDescription@Base 4.6
+ method_getImplementation@Base 4.6
+ method_getName@Base 4.6
+ method_getNumberOfArguments@Base 4.6
+ method_getReturnType@Base 4.6
+ method_getTypeEncoding@Base 4.6
+ method_get_imp@Base 4.6
+ method_setImplementation@Base 4.6
+ narrays@Base 4.2.1
+ nbuckets@Base 4.2.1
+ nil_method@Base 4.2.1
+ nindices@Base 4.2.1
+ objc_aligned_size@Base 4.2.1
+ objc_alignof_type@Base 4.2.1
+ objc_allocateClassPair@Base 4.6
+ objc_atomic_malloc@Base 4.2.1
+ objc_calloc@Base 4.2.1
+ objc_condition_allocate@Base 4.2.1
+ objc_condition_broadcast@Base 4.2.1
+ objc_condition_deallocate@Base 4.2.1
+ objc_condition_signal@Base 4.2.1
+ objc_condition_wait@Base 4.2.1
+ objc_copyProtocolList@Base 4.6
+ objc_copyStruct@Base 4.6
+ objc_disposeClassPair@Base 4.6
+ objc_enumerationMutation@Base 4.6
+ objc_exception_throw@Base 4.2.1
+ objc_free@Base 4.2.1
+ objc_getClass@Base 4.6
+ objc_getClassList@Base 4.6
+ objc_getMetaClass@Base 4.6
+ objc_getProperty@Base 4.6
+ objc_getPropertyStruct@Base 4.6
+ objc_getProtocol@Base 4.6
+ objc_getRequiredClass@Base 4.6
+ objc_get_class@Base 4.2.1
+ objc_get_meta_class@Base 4.2.1
+ objc_get_type_qualifiers@Base 4.2.1
+ objc_hash_add@Base 4.2.1
+ objc_hash_delete@Base 4.2.1
+ objc_hash_is_key_in_hash@Base 4.2.1
+ objc_hash_new@Base 4.2.1
+ objc_hash_next@Base 4.2.1
+ objc_hash_remove@Base 4.2.1
+ objc_hash_value_for_key@Base 4.2.1
+ objc_layout_finish_structure@Base 4.2.1
+ objc_layout_structure@Base 4.2.1
+ objc_layout_structure_get_info@Base 4.2.1
+ objc_layout_structure_next_member@Base 4.2.1
+ objc_lookUpClass@Base 4.6
+ objc_lookup_class@Base 4.2.1
+ objc_malloc@Base 4.2.1
+ objc_msg_lookup@Base 4.2.1
+ objc_msg_lookup_super@Base 4.2.1
+ objc_mutex_allocate@Base 4.2.1
+ objc_mutex_deallocate@Base 4.2.1
+ objc_mutex_lock@Base 4.2.1
+ objc_mutex_trylock@Base 4.2.1
+ objc_mutex_unlock@Base 4.2.1
+ objc_promoted_size@Base 4.2.1
+ objc_realloc@Base 4.2.1
+ objc_registerClassPair@Base 4.6
+ objc_setEnumerationMutationHandler@Base 4.6
+ objc_setExceptionMatcher@Base 4.6
+ objc_setGetUnknownClassHandler@Base 4.6
+ objc_setProperty@Base 4.6
+ objc_setPropertyStruct@Base 4.6
+ objc_setUncaughtExceptionHandler@Base 4.6
+ objc_set_thread_callback@Base 4.2.1
+ objc_sizeof_type@Base 4.2.1
+ objc_skip_argspec@Base 4.2.1
+ objc_skip_offset@Base 4.2.1
+ objc_skip_type_qualifiers@Base 4.2.1
+ objc_skip_typespec@Base 4.2.1
+ objc_sync_enter@Base 4.6
+ objc_sync_exit@Base 4.6
+ objc_thread_add@Base 4.2.1
+ objc_thread_detach@Base 4.2.1
+ objc_thread_exit@Base 4.2.1
+ objc_thread_get_data@Base 4.2.1
+ objc_thread_get_priority@Base 4.2.1
+ objc_thread_id@Base 4.2.1
+ objc_thread_remove@Base 4.2.1
+ objc_thread_set_data@Base 4.2.1
+ objc_thread_set_priority@Base 4.2.1
+ objc_thread_yield@Base 4.2.1
+ object_copy@Base 4.2.1
+ object_dispose@Base 4.2.1
+ object_getClassName@Base 4.6
+ object_getIndexedIvars@Base 4.6
+ object_getInstanceVariable@Base 4.6
+ object_getIvar@Base 4.6
+ object_setClass@Base 4.6
+ object_setInstanceVariable@Base 4.6
+ object_setIvar@Base 4.6
+ property_getAttributes@Base 4.6
+ property_getName@Base 4.6
+ protocol_conformsToProtocol@Base 4.6
+ protocol_copyMethodDescriptionList@Base 4.6
+ protocol_copyPropertyList@Base 4.6
+ protocol_copyProtocolList@Base 4.6
+ protocol_getMethodDescription@Base 4.6
+ protocol_getName@Base 4.6
+ protocol_getProperty@Base 4.6
+ protocol_isEqual@Base 4.6
+ sarray_at_put@Base 4.2.1
+ sarray_at_put_safe@Base 4.2.1
+ sarray_free@Base 4.2.1
+ sarray_lazy_copy@Base 4.2.1
+ sarray_new@Base 4.2.1
+ sarray_realloc@Base 4.2.1
+ sarray_remove_garbage@Base 4.2.1
+ search_for_method_in_list@Base 4.2.1
+ sel_copyTypedSelectorList@Base 4.6
+ sel_getName@Base 4.6
+ sel_getTypeEncoding@Base 4.6
+ sel_getTypedSelector@Base 4.6
+ sel_getUid@Base 4.6 
+ sel_get_any_uid@Base 4.2.1
+ sel_isEqual@Base 4.6
+ sel_is_mapped@Base 4.2.1
+ sel_registerName@Base 4.6
+ sel_registerTypedName@Base 4.6
--- gcc-6-6.3.0.orig/debian/libobjc.symbols.gc
+++ gcc-6-6.3.0/debian/libobjc.symbols.gc
@@ -0,0 +1,522 @@
+ async_set_pht_entry_from_index@Base 4.2.1
+ free_list_index_of@Base 4.2.1
+ suspend_self@Base 4.2.1
+ GC_abort@Base 6
+ GC_acquire_mark_lock@Base 6
+ GC_add_ext_descriptor@Base 6
+ GC_add_leaked@Base 6
+ GC_add_map_entry@Base 6
+ GC_add_roots@Base 6
+ GC_add_roots_inner@Base 6
+ GC_add_smashed@Base 6
+ GC_add_to_black_list_normal@Base 6
+ GC_add_to_black_list_stack@Base 6
+ GC_add_to_fl@Base 6
+ GC_add_to_heap@Base 6
+ GC_adj_words_allocd@Base 6
+ GC_all_bottom_indices@Base 6
+ GC_all_bottom_indices_end@Base 6
+ GC_all_interior_pointers@Base 6
+ GC_alloc_large@Base 6
+ GC_alloc_large_and_clear@Base 6
+ GC_alloc_reclaim_list@Base 6
+ GC_allocate_ml@Base 6
+ GC_allochblk@Base 6
+ GC_allochblk_nth@Base 6
+ GC_allocobj@Base 6
+ GC_aobjfreelist_ptr@Base 6
+ GC_apply_to_all_blocks@Base 6
+ GC_apply_to_maps@Base 6
+ GC_approx_sp@Base 6
+ GC_arobjfreelist@Base 6
+ GC_array_kind@Base 6
+ GC_array_mark_proc@Base 6
+ GC_array_mark_proc_index@Base 6
+ GC_arrays@Base 6
+ GC_auobjfreelist_ptr@Base 6
+ GC_avail_descr@Base 6
+ GC_base@Base 6
+ GC_begin_syscall@Base 6
+ GC_bl_init@Base 6
+ GC_black_list_spacing@Base 6
+ GC_block_count@Base 6
+ GC_block_empty@Base 6
+ GC_block_nearly_full1@Base 6
+ GC_block_nearly_full3@Base 6
+ GC_block_nearly_full@Base 6
+ GC_block_was_dirty@Base 6
+ GC_bm_table@Base 6
+ GC_brief_async_signal_safe_sleep@Base 6
+ GC_build_fl1@Base 6
+ GC_build_fl2@Base 6
+ GC_build_fl4@Base 6
+ GC_build_fl@Base 6
+ GC_build_fl_clear2@Base 6
+ GC_build_fl_clear3@Base 6
+ GC_build_fl_clear4@Base 6
+ GC_call_with_alloc_lock@Base 6
+ GC_calloc_explicitly_typed@Base 6
+ GC_change_stubborn@Base 6
+ GC_check_annotated_obj@Base 6
+ GC_check_heap@Base 6
+ GC_check_heap_block@Base 6
+ GC_check_heap_proc@Base 6
+ GC_clear_a_few_frames@Base 6
+ GC_clear_bl@Base 6
+ GC_clear_fl_links@Base 6
+ GC_clear_fl_marks@Base 6
+ GC_clear_hdr_marks@Base 6
+ GC_clear_mark_bit@Base 6
+ GC_clear_marks@Base 6
+ GC_clear_roots@Base 6
+ GC_clear_stack@Base 6
+ GC_clear_stack_inner@Base 6
+ GC_collect_a_little@Base 6
+ GC_collect_a_little_inner@Base 6
+ GC_collect_or_expand@Base 6
+ GC_collecting@Base 6
+ GC_collection_in_progress@Base 6
+ GC_cond_register_dynamic_libraries@Base 6
+ GC_continue_reclaim@Base 6
+ GC_copy_bl@Base 6
+ GC_copyright@Base 6
+ GC_current_warn_proc@Base 6
+ GC_data_start@Base 6
+ GC_debug_change_stubborn@Base 6
+ GC_debug_end_stubborn_change@Base 6
+ GC_debug_free@Base 6
+ GC_debug_free_inner@Base 6
+ GC_debug_gcj_fast_malloc@Base 6
+ GC_debug_gcj_malloc@Base 6
+ GC_debug_header_size@Base 6
+ GC_debug_invoke_finalizer@Base 6
+ GC_debug_malloc@Base 6
+ GC_debug_malloc_atomic@Base 6
+ GC_debug_malloc_atomic_ignore_off_page@Base 6
+ GC_debug_malloc_atomic_uncollectable@Base 6
+ GC_debug_malloc_ignore_off_page@Base 6
+ GC_debug_malloc_replacement@Base 6
+ GC_debug_malloc_stubborn@Base 6
+ GC_debug_malloc_uncollectable@Base 6
+ GC_debug_print_heap_obj_proc@Base 6
+ GC_debug_realloc@Base 6
+ GC_debug_realloc_replacement@Base 6
+ GC_debug_register_displacement@Base 6
+ GC_debug_register_finalizer@Base 6
+ GC_debug_register_finalizer_ignore_self@Base 6
+ GC_debug_register_finalizer_no_order@Base 6
+ GC_debug_register_finalizer_unreachable@Base 6
+ GC_debugging_started@Base 6
+ GC_default_is_valid_displacement_print_proc@Base 6
+ GC_default_is_visible_print_proc@Base 6
+ GC_default_oom_fn@Base 6
+ GC_default_print_heap_obj_proc@Base 6
+ GC_default_push_other_roots@Base 6
+ GC_default_same_obj_print_proc@Base 6
+ GC_default_warn_proc@Base 6
+ GC_deficit@Base 6
+ GC_delete_gc_thread@Base 6
+ GC_delete_thread@Base 6
+ GC_descr_obj_size@Base 6
+ GC_destroy_thread_local@Base 6
+ GC_dirty_init@Base 6
+ GC_dirty_maintained@Base 6
+ GC_disable@Base 6
+ GC_disable_signals@Base 6
+ GC_dl_entries@Base 6
+ GC_dlopen@Base 6
+ GC_do_nothing@Base 6
+ GC_dont_expand@Base 6
+ GC_dont_gc@Base 6
+ GC_dont_precollect@Base 6
+ GC_double_descr@Base 6
+ GC_dump@Base 6
+ GC_dump_finalization@Base 6
+ GC_dump_regions@Base 6
+ GC_dump_regularly@Base 6
+ GC_ed_size@Base 6
+ GC_enable@Base 6
+ GC_enable_incremental@Base 6
+ GC_enable_signals@Base 6
+ GC_end_blocking@Base 6
+ GC_end_stubborn_change@Base 6
+ GC_end_syscall@Base 6
+ GC_enqueue_all_finalizers@Base 6
+ GC_eobjfreelist@Base 6
+ GC_err_printf@Base 6
+ GC_err_puts@Base 6
+ GC_err_write@Base 6
+ GC_excl_table_entries@Base 6
+ GC_exclude_static_roots@Base 6
+ GC_exit_check@Base 6
+ GC_expand_hp@Base 6
+ GC_expand_hp_inner@Base 6
+ GC_explicit_kind@Base 6
+ GC_explicit_typing_initialized@Base 6
+ GC_ext_descriptors@Base 6
+ GC_extend_size_map@Base 6
+ GC_fail_count@Base 6
+ GC_fault_handler@Base 6
+ GC_finalization_failures@Base 6
+ GC_finalize@Base 6
+ GC_finalize_all@Base 6
+ GC_finalize_now@Base 6
+ GC_finalize_on_demand@Base 6
+ GC_finalizer_notifier@Base 6
+ GC_find_header@Base 6
+ GC_find_leak@Base 6
+ GC_find_limit@Base 6
+ GC_find_start@Base 6
+ GC_finish_collection@Base 6
+ GC_fl_builder_count@Base 6
+ GC_fo_entries@Base 6
+ GC_free@Base 6
+ GC_free_block_ending_at@Base 6
+ GC_free_bytes@Base 6
+ GC_free_inner@Base 6
+ GC_free_space_divisor@Base 6
+ GC_freehblk@Base 6
+ GC_freehblk_ptr@Base 6
+ GC_full_freq@Base 6
+ GC_gc_no@Base 6
+ GC_gcj_debug_kind@Base 6
+ GC_gcj_fast_malloc@Base 6
+ GC_gcj_kind@Base 6
+ GC_gcj_malloc@Base 6
+ GC_gcj_malloc_ignore_off_page@Base 6
+ GC_gcj_malloc_initialized@Base 6
+ GC_gcjdebugobjfreelist@Base 6
+ GC_gcjobjfreelist@Base 6
+ GC_gcollect@Base 6
+ GC_general_register_disappearing_link@Base 6
+ GC_generic_lock@Base 6
+ GC_generic_malloc@Base 6
+ GC_generic_malloc_ignore_off_page@Base 6
+ GC_generic_malloc_inner@Base 6
+ GC_generic_malloc_inner_ignore_off_page@Base 6
+ GC_generic_malloc_many@Base 6
+ GC_generic_malloc_words_small@Base 6
+ GC_generic_malloc_words_small_inner@Base 6
+ GC_generic_or_special_malloc@Base 6
+ GC_generic_push_regs@Base 6
+ GC_get_bytes_since_gc@Base 6
+ GC_get_first_part@Base 6
+ GC_get_free_bytes@Base 6
+ GC_get_heap_size@Base 6
+ GC_get_nprocs@Base 6
+ GC_get_stack_base@Base 6
+ GC_get_thread_stack_base@Base 6
+ GC_get_total_bytes@Base 6
+ GC_greatest_plausible_heap_addr@Base 6
+ GC_grow_table@Base 6
+ GC_has_other_debug_info@Base 6
+ GC_have_errors@Base 6
+ GC_hblk_fl_from_blocks@Base 6
+ GC_hblkfreelist@Base 6
+ GC_hdr_cache_hits@Base 6
+ GC_hdr_cache_misses@Base 6
+ GC_high_water@Base 6
+ GC_ignore_self_finalize_mark_proc@Base 6
+ GC_in_thread_creation@Base 6
+ GC_incomplete_normal_bl@Base 6
+ GC_incomplete_stack_bl@Base 6
+ GC_incr_mem_freed@Base 6
+ GC_incr_words_allocd@Base 6
+ GC_incremental@Base 6
+ GC_incremental_protection_needs@Base 6
+ GC_init@Base 6
+ GC_init_explicit_typing@Base 6
+ GC_init_gcj_malloc@Base 6
+ GC_init_headers@Base 6
+ GC_init_inner@Base 6
+ GC_init_linux_data_start@Base 6
+ GC_init_parallel@Base 6
+ GC_init_size_map@Base 6
+ GC_init_thread_local@Base 6
+ GC_initiate_gc@Base 6
+ GC_install_counts@Base 6
+ GC_install_header@Base 6
+ GC_invalid_header@Base 6
+ GC_invalid_map@Base 6
+ GC_invalidate_map@Base 6
+ GC_invalidate_mark_state@Base 6
+ GC_invoke_finalizers@Base 6
+ GC_is_black_listed@Base 6
+ GC_is_fresh@Base 6
+ GC_is_full_gc@Base 6
+ GC_is_initialized@Base 6
+ GC_is_marked@Base 6
+ GC_is_static_root@Base 6
+ GC_is_thread_suspended@Base 6
+ GC_is_valid_displacement@Base 6
+ GC_is_valid_displacement_print_proc@Base 6
+ GC_is_visible@Base 6
+ GC_is_visible_print_proc@Base 6
+ GC_java_finalization@Base 6
+ GC_jmp_buf@Base 6
+ GC_key_create@Base 6
+ GC_large_alloc_warn_interval@Base 6
+ GC_large_alloc_warn_suppressed@Base 6
+ GC_leaked@Base 6
+ GC_least_plausible_heap_addr@Base 6
+ GC_linux_stack_base@Base 6
+ GC_local_gcj_malloc@Base 6
+ GC_local_malloc@Base 6
+ GC_local_malloc_atomic@Base 6
+ GC_lock@Base 6
+ GC_lock_holder@Base 6
+ GC_lookup_thread@Base 6
+ GC_make_array_descriptor@Base 6
+ GC_make_closure@Base 6
+ GC_make_descriptor@Base 6
+ GC_make_sequence_descriptor@Base 6
+ GC_malloc@Base 6
+ GC_malloc_atomic@Base 6
+ GC_malloc_atomic_ignore_off_page@Base 6
+ GC_malloc_atomic_uncollectable@Base 6
+ GC_malloc_explicitly_typed@Base 6
+ GC_malloc_explicitly_typed_ignore_off_page@Base 6
+ GC_malloc_ignore_off_page@Base 6
+ GC_malloc_many@Base 6
+ GC_malloc_stubborn@Base 6
+ GC_malloc_uncollectable@Base 6
+ GC_mark_and_push@Base 6
+ GC_mark_and_push_stack@Base 6
+ GC_mark_from@Base 6
+ GC_mark_init@Base 6
+ GC_mark_some@Base 6
+ GC_mark_stack@Base 6
+ GC_mark_stack_empty@Base 6
+ GC_mark_stack_limit@Base 6
+ GC_mark_stack_size@Base 6
+ GC_mark_stack_too_small@Base 6
+ GC_mark_stack_top@Base 6
+ GC_mark_state@Base 6
+ GC_mark_thread_local_free_lists@Base 6
+ GC_max@Base 6
+ GC_max_retries@Base 6
+ GC_maybe_gc@Base 6
+ GC_mem_found@Base 6
+ GC_memalign@Base 6
+ GC_min@Base 6
+ GC_min_sp@Base 6
+ GC_n_attempts@Base 6
+ GC_n_heap_sects@Base 6
+ GC_n_kinds@Base 6
+ GC_n_leaked@Base 6
+ GC_n_mark_procs@Base 6
+ GC_n_rescuing_pages@Base 6
+ GC_n_set_marks@Base 6
+ GC_n_smashed@Base 6
+ GC_need_full_gc@Base 6
+ GC_never_stop_func@Base 6
+ GC_new_free_list@Base 6
+ GC_new_free_list_inner@Base 6
+ GC_new_hblk@Base 6
+ GC_new_kind@Base 6
+ GC_new_kind_inner@Base 6
+ GC_new_proc@Base 6
+ GC_new_proc_inner@Base 6
+ GC_new_thread@Base 6
+ GC_next_exclusion@Base 6
+ GC_next_used_block@Base 6
+ GC_no_dls@Base 6
+ GC_non_gc_bytes@Base 6
+ GC_noop1@Base 6
+ GC_noop@Base 6
+ GC_normal_finalize_mark_proc@Base 6
+ GC_notify_all_builder@Base 6
+ GC_notify_full_gc@Base 6
+ GC_notify_or_invoke_finalizers@Base 6
+ GC_nprocs@Base 6
+ GC_null_finalize_mark_proc@Base 6
+ GC_number_stack_black_listed@Base 6
+ GC_obj_kinds@Base 6
+ GC_objects_are_marked@Base 6
+ GC_objfreelist_ptr@Base 6
+ GC_old_bus_handler@Base 6
+ GC_old_normal_bl@Base 6
+ GC_old_segv_handler@Base 6
+ GC_old_stack_bl@Base 6
+ GC_on_stack@Base 6
+ GC_oom_fn@Base 6
+ GC_page_size@Base 6
+ GC_page_was_dirty@Base 6
+ GC_page_was_ever_dirty@Base 6
+ GC_parallel@Base 6
+ GC_pause@Base 6
+ GC_post_incr@Base 6
+ GC_pre_incr@Base 6
+ GC_prev_block@Base 6
+ GC_print_address_map@Base 6
+ GC_print_all_errors@Base 6
+ GC_print_all_smashed@Base 6
+ GC_print_all_smashed_proc@Base 6
+ GC_print_back_height@Base 6
+ GC_print_block_descr@Base 6
+ GC_print_block_list@Base 6
+ GC_print_finalization_stats@Base 6
+ GC_print_hblkfreelist@Base 6
+ GC_print_heap_obj@Base 6
+ GC_print_heap_sects@Base 6
+ GC_print_obj@Base 6
+ GC_print_smashed_obj@Base 6
+ GC_print_source_ptr@Base 6
+ GC_print_static_roots@Base 6
+ GC_print_stats@Base 6
+ GC_print_type@Base 6
+ GC_printf@Base 6
+ GC_project2@Base 6
+ GC_promote_black_lists@Base 6
+ GC_protect_heap@Base 6
+ GC_pthread_create@Base 6
+ GC_pthread_detach@Base 6
+ GC_pthread_join@Base 6
+ GC_pthread_sigmask@Base 6
+ GC_push_all@Base 6
+ GC_push_all_eager@Base 6
+ GC_push_all_stack@Base 6
+ GC_push_all_stacks@Base 6
+ GC_push_complex_descriptor@Base 6
+ GC_push_conditional@Base 6
+ GC_push_conditional_with_exclusions@Base 6
+ GC_push_current_stack@Base 6
+ GC_push_finalizer_structures@Base 6
+ GC_push_gc_structures@Base 6
+ GC_push_marked1@Base 6
+ GC_push_marked2@Base 6
+ GC_push_marked4@Base 6
+ GC_push_marked@Base 6
+ GC_push_next_marked@Base 6
+ GC_push_next_marked_dirty@Base 6
+ GC_push_next_marked_uncollectable@Base 6
+ GC_push_one@Base 6
+ GC_push_other_roots@Base 6
+ GC_push_roots@Base 6
+ GC_push_selected@Base 6
+ GC_push_stubborn_structures@Base 6
+ GC_push_thread_structures@Base 6
+ GC_quiet@Base 6
+ GC_read_dirty@Base 6
+ GC_realloc@Base 6
+ GC_reclaim1@Base 6
+ GC_reclaim_all@Base 6
+ GC_reclaim_block@Base 6
+ GC_reclaim_check@Base 6
+ GC_reclaim_clear2@Base 6
+ GC_reclaim_clear4@Base 6
+ GC_reclaim_clear@Base 6
+ GC_reclaim_generic@Base 6
+ GC_reclaim_small_nonempty_block@Base 6
+ GC_reclaim_uninit2@Base 6
+ GC_reclaim_uninit4@Base 6
+ GC_reclaim_uninit@Base 6
+ GC_register_data_segments@Base 6
+ GC_register_describe_type_fn@Base 6
+ GC_register_disappearing_link@Base 6
+ GC_register_displacement@Base 6
+ GC_register_displacement_inner@Base 6
+ GC_register_dynamic_libraries@Base 6
+ GC_register_dynamic_libraries_dl_iterate_phdr@Base 6
+ GC_register_finalizer@Base 6
+ GC_register_finalizer_ignore_self@Base 6
+ GC_register_finalizer_inner@Base 6
+ GC_register_finalizer_no_order@Base 6
+ GC_register_finalizer_unreachable@Base 6
+ GC_register_has_static_roots_callback@Base 6
+ GC_register_main_static_data@Base 6
+ GC_register_my_thread@Base 6
+ GC_release_mark_lock@Base 6
+ GC_remove_allowed_signals@Base 6
+ GC_remove_counts@Base 6
+ GC_remove_from_fl@Base 6
+ GC_remove_header@Base 6
+ GC_remove_protection@Base 6
+ GC_remove_roots@Base 6
+ GC_remove_roots_inner@Base 6
+ GC_remove_specific@Base 6
+ GC_remove_tmp_roots@Base 6
+ GC_repeat_read@Base 6
+ GC_reset_fault_handler@Base 6
+ GC_restart_handler@Base 6
+ GC_resume_thread@Base 6
+ GC_retry_signals@Base 6
+ GC_root_size@Base 6
+ GC_roots_present@Base 6
+ GC_same_obj@Base 6
+ GC_same_obj_print_proc@Base 6
+ GC_scratch_alloc@Base 6
+ GC_set_and_save_fault_handler@Base 6
+ GC_set_fl_marks@Base 6
+ GC_set_free_space_divisor@Base 6
+ GC_set_hdr_marks@Base 6
+ GC_set_mark_bit@Base 6
+ GC_set_max_heap_size@Base 6
+ GC_set_warn_proc@Base 6
+ GC_setpagesize@Base 6
+ GC_setspecific@Base 6
+ GC_setup_temporary_fault_handler@Base 6
+ GC_should_collect@Base 6
+ GC_should_invoke_finalizers@Base 6
+ GC_signal_mark_stack_overflow@Base 6
+ GC_size@Base 6
+ GC_sleep@Base 6
+ GC_slow_getspecific@Base 6
+ GC_smashed@Base 6
+ GC_spin_count@Base 6
+ GC_split_block@Base 6
+ GC_stack_last_cleared@Base 6
+ GC_stackbottom@Base 6
+ GC_start_blocking@Base 6
+ GC_start_call_back@Base 6
+ GC_start_debugging@Base 6
+ GC_start_reclaim@Base 6
+ GC_start_routine@Base 6
+ GC_start_time@Base 6
+ GC_start_world@Base 6
+ GC_stderr@Base 6
+ GC_stdout@Base 6
+ GC_stop_count@Base 6
+ GC_stop_init@Base 6
+ GC_stop_world@Base 6
+ GC_stopped_mark@Base 6
+ GC_stopping_pid@Base 6
+ GC_stopping_thread@Base 6
+ GC_store_debug_info@Base 6
+ GC_suspend_ack_sem@Base 6
+ GC_suspend_all@Base 6
+ GC_suspend_handler@Base 6
+ GC_suspend_handler_inner@Base 6
+ GC_suspend_thread@Base 6
+ GC_thr_init@Base 6
+ GC_thr_initialized@Base 6
+ GC_thread_exit_proc@Base 6
+ GC_thread_key@Base 6
+ GC_threads@Base 6
+ GC_time_limit@Base 6
+ GC_timeout_stop_func@Base 6
+ GC_total_stack_black_listed@Base 6
+ GC_try_to_collect@Base 6
+ GC_try_to_collect_inner@Base 6
+ GC_typed_mark_proc@Base 6
+ GC_typed_mark_proc_index@Base 6
+ GC_unix_get_mem@Base 6
+ GC_unlocked_count@Base 6
+ GC_unpromote_black_lists@Base 6
+ GC_unprotect_range@Base 6
+ GC_unreachable_finalize_mark_proc@Base 6
+ GC_unregister_disappearing_link@Base 6
+ GC_unregister_my_thread@Base 6
+ GC_uobjfreelist_ptr@Base 6
+ GC_use_entire_heap@Base 6
+ GC_used_heap_size_after_full@Base 6
+ GC_version@Base 6
+ GC_wait_builder@Base 6
+ GC_wait_for_gc_completion@Base 6
+ GC_wait_for_reclaim@Base 6
+ GC_with_callee_saves_pushed@Base 6
+ GC_words_allocd_at_reset@Base 6
+ GC_world_is_stopped@Base 6
+ GC_world_stopped@Base 6
+ GC_write@Base 6
+ GC_write_fault_handler@Base 6
--- gcc-6-6.3.0.orig/debian/libquadmath.symbols
+++ gcc-6-6.3.0/debian/libquadmath.symbols
@@ -0,0 +1,3 @@
+libquadmath.so.0 #PACKAGE# #MINVER#
+ (symver)QUADMATH_1.0 4.6
+ (symver)QUADMATH_1.1 6
--- gcc-6-6.3.0.orig/debian/libstdc++-BV-doc.doc-base
+++ gcc-6-6.3.0/debian/libstdc++-BV-doc.doc-base
@@ -0,0 +1,13 @@
+Document: libstdc++-@BV@-doc
+Title: The GNU Standard C++ Library v3 (gcc-@BV@)
+Author: Various
+Abstract: This package contains documentation files for the GNU stdc++ library.
+ One set is the distribution documentation, the other set is the
+ source documentation including a namespace list, class hierarchy,
+ alphabetical list, compound list, file list, namespace members,
+ compound members and file members.
+Section: Programming/C++
+
+Format: html
+Index: /usr/share/doc/libstdc++-@BV@-doc/libstdc++/index.html
+Files: /usr/share/doc/libstdc++-@BV@-doc/libstdc++/*
--- gcc-6-6.3.0.orig/debian/libstdc++-BV-doc.overrides
+++ gcc-6-6.3.0/debian/libstdc++-BV-doc.overrides
@@ -0,0 +1,11 @@
+libstdc++-@BV@-doc binary: hyphen-used-as-minus-sign
+libstdc++-@BV@-doc binary: manpage-has-bad-whatis-entry
+
+# 3xx used by intent to avoid conficts
+libstdc++-@BV@-doc binary: manpage-section-mismatch
+
+# some very long identifiers
+libstdc++-@BV@-doc binary: manpage-has-errors-from-man.*can't break line
+
+# doxygen accepts formulas in man pages ...
+libstdc++-@BV@-doc binary: manpage-has-errors-from-man.*a space character is not allowed in an escape name
--- gcc-6-6.3.0.orig/debian/libstdc++-breaks.Debian
+++ gcc-6-6.3.0/debian/libstdc++-breaks.Debian
@@ -0,0 +1,87 @@
+libantlr-dev (<= 2.7.7+dfsg-6),
+libaqsis1 (<= 1.8.2-1),
+libassimp3 (<= 3.0~dfsg-4),
+blockattack (<= 1.4.1+ds1-2.1+b2),
+boo (<= 0.9.5~git20110729.r1.202a430-2),
+libboost-date-time1.54.0,
+libboost-date-time1.55.0,
+libcpprest2.4 (<= 2.4.0-2),
+printer-driver-brlaser (<= 3-3),
+c++-annotations (<= 10.2.0-1),
+clustalx (<= 2.1+lgpl-3),
+libdavix0 (<= 0.4.0-1+b1),
+libdballe6 (<= 6.8-1),
+dff (<= 1.3.0+dfsg.1-4.1+b3),
+libdiet-sed2.8 (<= 2.8.0-1+b3),
+libdiet-client2.8 (<= 2.8.0-1+b3),
+libdiet-admin2.8 (<= 2.8.0-1+b3),
+digikam-private-libs (<= 4:4.4.0-1.1+b2),
+emscripten (<= 1.22.1-1),
+ergo (<= 3.4.0-1),
+fceux (<= 2.2.2+dfsg0-1),
+flush (<= 0.9.12-3.1),
+libfreefem++ (<= 3.37.1-1),
+freeorion (<= 0.4.4+git20150327-2),
+fslview (<= 4.0.1-4),
+fwbuilder (<= 5.1.0-4),
+libgazebo5 (<= 5.0.1+dfsg-2.1),
+libgetfem4++ (<= 4.2.1~beta1~svn4635~dfsg-3+b1),
+libgmsh2 (<= 2.9.3+dfsg1-1),
+gnote (<= 3.16.2-1),
+gnudatalanguage (<= 0.9.5-2+b2),
+python-healpy (<= 1.8.1-1+b1),
+innoextract (<= 1.4-1+b1),
+libinsighttoolkit4.7 (<= 4.7.2-2),
+libdap17 (<= 3.14.0-2),
+libdapclient6 (<= 3.14.0-2),
+libdapserver7 (<= 3.14.0-2),
+libkolabxml1 (<= 1.1.0-3),
+libpqxx-4.0 (<= 4.0.1+dfsg-3),
+libreoffice-core (<= 1:4.4.5-2),
+librime1 (<= 1.2+dfsg-2),
+libwibble-dev (<= 1.1-1),
+lightspark (<= 0.7.2+git20150512-2+b1),
+libmarisa0 (<= 0.2.4-8),
+mira-assembler (<= 4.9.5-1),
+mongodb (<= 1:2.4.14-2),
+mongodb-server (<= 1:2.4.14-2),
+ncbi-blast+ (<= 2.2.30-4),
+libogre-1.8.0 (<= 1.8.0+dfsg1-7+b1),
+libogre-1.9.0 (<= 1.9.0+dfsg1-4),
+openscad (<= 2014.03+dfsg-1+b1),
+libopenwalnut1 (<= 1.4.0~rc1+hg3a3147463ee2-1+b1),
+passepartout (<= 0.7.1-1.1),
+pdf2djvu (<= 0.7.21-2),
+photoprint (<= 0.4.2~pre2-2.3+b2),
+plastimatch (<= 1.6.2+dfsg-1),
+plee-the-bear (<= 0.6.0-3.1),
+povray (<= 1:3.7.0.0-8),
+powertop (<= 2.6.1-1),
+psi4 (<= 4.0~beta5+dfsg-2+b1),
+python3-taglib (<= 0.3.6+dfsg-2+b2),
+realtimebattle (<= 1.0.8-14),
+ruby-passenger (<= 5.0.7-1),
+libapache2-mod-passenger (<= 5.0.7-1),
+schroot (<= 1.6.10-1+b1),
+sqlitebrowser (<= 3.5.1-3),
+tecnoballz (<= 0.93.1-6),
+wesnoth-1.12-core (<= 1:1.12.4-1),
+widelands (<= 1:18-3+b1),
+libwreport2 (<= 2.14-1),
+xflr5 (<= 6.09.06-2),
+libxmltooling6 (<= 1.5.3-2.1),
+libchemps2-1 (<= 1.5-1),
+python-fiona (<= 1.5.1-2),
+python3-fiona (<= 1.5.1-2),
+fiona (<= 1.5.1-2),
+python-guiqwt (<= 2.3.1-1),
+python-htseq (<= 0.5.4p3-2),
+python-imposm (<= 2.5.0-3+b2),
+python-pysph (<= 0~20150606.gitfa26de9-5),
+python3-taglib (<= 0.3.6+dfsg-2+b2),
+python-scipy (<= 0.14.1-1),
+python3-scipy (<= 0.14.1-1),
+python-sfml (<= 2.2~git20150611.196c88+dfsg-1+b1),
+python3-sfml (<= 2.2~git20150611.196c88+dfsg-1+b1),
+python-rasterio (<= 0.24.0-1),
+libopenmpi1.6,
--- gcc-6-6.3.0.orig/debian/libstdc++-breaks.Ubuntu
+++ gcc-6-6.3.0/debian/libstdc++-breaks.Ubuntu
@@ -0,0 +1,73 @@
+libantlr-dev (<= 2.7.7+dfsg-6),
+libaqsis1 (<= 1.8.2-1),
+libassimp3 (<= 3.0~dfsg-4),
+blockattack (<= 1.4.1+ds1-2.1build2),
+boo (<= 0.9.5~git20110729.r1.202a430-2),
+libboost-date-time1.55.0,
+libcpprest2.2 (<= 2.2.0-1),
+printer-driver-brlaser (<= 3-3),
+c++-annotations (<= 10.2.0-1),
+chromium-browser (<= 43.0.2357.130-0ubuntu2),
+clustalx (<= 2.1+lgpl-2),
+libdavix0 (<= 0.4.0-1build1),
+libdballe6 (<= 6.8-1),
+dff (<= 1.3.0+dfsg.1-4.1build2),
+libdiet-sed2.8 (<= 2.8.0-1build3),
+libdiet-client2.8 (<= 2.8.0-1build3),
+libdiet-admin2.8 (<= 2.8.0-1build3),
+libkgeomap2 (<= 4:15.04.2-0ubuntu1),
+libmediawiki1 (<= 1.0~digikam4.10.0-0ubuntu2),
+libkvkontakte1 (<= 1.0~digikam4.10.0-0ubuntu2),
+emscripten (<= 1.22.1-1),
+ergo (<= 3.4.0-1),
+fceux (<= 2.2.2+dfsg0-1),
+flush (<= 0.9.12-3.1ubuntu1),
+libfreefem++ (<= 3.37.1-1),
+freeorion (<= 0.4.4+git20150327-2),
+fslview (<= 4.0.1-4),
+fwbuilder (<= 5.1.0-4),
+libgazebo5 (<= 5.0.1+dfsg-2.1),
+libgetfem4++ (<= 4.2.1~beta1~svn4482~dfsg-3ubuntu3),
+libgmsh2 (<= 2.8.5+dfsg-1.1ubuntu1),
+gnote (<= 3.16.2-1),
+gnudatalanguage (<= 0.9.5-2build1),
+python-healpy (<= 1.8.1-1),
+innoextract (<= 1.4-1build1),
+libinsighttoolkit4.6 (<= 4.6.0-3ubuntu3),
+libdap17 (<= 3.14.0-2),
+libdapclient6 (<= 3.14.0-2),
+libdapserver7 (<= 3.14.0-2),
+libkolabxml1 (<= 1.1.0-3),
+libpqxx-4.0 (<= 4.0.1+dfsg-3ubuntu1),
+libreoffice-core (<= 1:4.4.4~rc3-0ubuntu1),
+librime1 (<= 1.2+dfsg-2),
+libwibble-dev (<= 1.1-1),
+lightspark (<= 0.7.2+git20150512-2),
+libmarisa0 (<= 0.2.4-8build1),
+mira-assembler (<= 4.9.5-1),
+mongodb (<= 1:2.6.3-0ubuntu7),
+mongodb-server (<= 1:2.6.3-0ubuntu7),
+ncbi-blast+ (<= 2.2.30-4),
+libogre-1.8.0 (<= 1.8.1+dfsg-0ubuntu5),
+libogre-1.9.0 (<= 1.9.0+dfsg1-4),
+openscad (<= 2014.03+dfsg-1build1),
+libopenwalnut1 (<= 1.4.0~rc1+hg3a3147463ee2-1ubuntu2),
+passepartout (<= 0.7.1-1.1),
+pdf2djvu (<= 0.7.19-1ubuntu2),
+photoprint (<= 0.4.2~pre2-2.3),
+plastimatch (<= 1.6.2+dfsg-1),
+plee-the-bear (<= 0.6.0-3.1),
+povray (<= 1:3.7.0.0-8),
+powertop (<= 2.6.1-1),
+psi4 (<= 4.0~beta5+dfsg-2build1),
+python3-taglib (<= 0.3.6+dfsg-2build2),
+realtimebattle (<= 1.0.8-14),
+ruby-passenger (<= 4.0.53-1),
+libapache2-mod-passenger (<= 4.0.53-1),
+sqlitebrowser (<= 3.5.1-3),
+tecnoballz (<= 0.93.1-6),
+wesnoth-1.12-core (<= 1:1.12.4-1),
+widelands (<= 1:18-3build1),
+libwreport2 (<= 2.14-1),
+xflr5 (<= 6.09.06-2),
+libxmltooling6 (<= 1.5.3-2.1),
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.128bit
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.128bit
@@ -0,0 +1,46 @@
+ _ZNSt14numeric_limitsInE10has_denormE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE10is_boundedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE10is_integerE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE11round_styleE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12has_infinityE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12max_digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12max_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12min_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE13has_quiet_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE14is_specializedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE14max_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE14min_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE15has_denorm_lossE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE15tinyness_beforeE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE17has_signaling_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE5radixE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE5trapsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE6digitsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE8digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE8is_exactE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE9is_iec559E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE9is_moduloE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE9is_signedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE10has_denormE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE10is_boundedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE10is_integerE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE11round_styleE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12has_infinityE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12max_digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12max_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12min_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE13has_quiet_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE14is_specializedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE14max_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE14min_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE15has_denorm_lossE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE15tinyness_beforeE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE17has_signaling_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE5radixE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE5trapsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE6digitsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE8digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE8is_exactE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE9is_iec559E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE9is_moduloE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE9is_signedE@GLIBCXX_3.4.17 4.7
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.32bit
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.32bit
@@ -0,0 +1,601 @@
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.32bit.cxx11"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEj@GLIBCXX_3.4.4 4.1.1
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjRKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEj@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcjPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwjPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcjcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcjcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcjwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcjwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEj@GLIBCXX_3.4.18 4.8
+ _ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEjjj@GLIBCXX_3.4.18 4.8
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES3_S3_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES3_S3_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES3_S3_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES3_S3_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8valarrayIjE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE10_S_compareEjj@GLIBCXX_3.4.16 4.6.0
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructEjwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE14_M_replace_auxEjjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE18_S_construct_aux_2EjwRKS1_@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE15_M_replace_safeEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep8_M_cloneERKS1_j@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep9_S_createEjjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEjj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_jw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7reserveEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwjw@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_mutateEjjj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EPKwjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_jjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EjwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EPKwjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_jjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EjwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi4readEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSi6ignoreEii@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi8readsomeEPci@GLIBCXX_3.4 4.1.1
+ _ZNSo5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSo5writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSo8_M_writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSs10_S_compareEjj@GLIBCXX_3.4.16 4.6.0
+ _ZNSs12_S_constructEjcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs14_M_replace_auxEjjjc@GLIBCXX_3.4 4.1.1
+ _ZNSs15_M_replace_safeEjjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs18_S_construct_aux_2EjcRKSaIcE@GLIBCXX_3.4.14 4.5
+ _ZNSs2atEj@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4.5 4.1.1
+ _ZNSs4_Rep8_M_cloneERKSaIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep9_S_createEjjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs5eraseEjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjRKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEj@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcj@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7_M_moveEPcPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_moveEPcPKcj@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_jc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjRKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjjc@GLIBCXX_3.4 4.1.1
+ _ZNSs7reserveEj@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcjc@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcjc@GLIBCXX_3.4.5 4.1.1
+ _ZNSs9_M_mutateEjjj@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EPKcjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsjjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EjcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EPKcjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsjjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EjcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsixEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11this_thread11__sleep_forENSt6chrono8durationIxSt5ratioILx1ELx1EEEENS1_IxS2_ILx1ELx1000000000EEEE@GLIBCXX_3.4.18 4.8
+ _ZNSt11__timepunctIcEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EPSt17__timepunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EPSt17__timepunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EPSt17__timepunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EPSt17__timepunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE7seekoffExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE8xsputn_2EPKciS2_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt12strstreambuf6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_allocEj@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_setupEPcS0_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPFPvjEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPFPvjEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE22_M_convert_to_externalEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4readEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEij@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE8readsomeEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE8_M_writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt14collate_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ (arch=!powerpc !powerpcspe !ppc64 !sparc)_ZNSt14numeric_limitsIeE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_gbumpEi@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_pbumpEi@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9pubsetbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_gbumpEi@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_pbumpEi@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9pubsetbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcjj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE8_M_pbumpEPcS4_x@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwjj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS4_x@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15messages_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15messages_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15messages_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15messages_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt16__numpunct_cacheIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIcLb0EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIcLb1EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIcLb1EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb0EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb0EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb1EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC1ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb1EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC2ERKSsj@GLIBCXX_3.4.21 5
+ _ZNSt18__moneypunct_cacheIcLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ (arch=!armel !kfreebsd-amd64 !kfreebsd-i386)_ZNSt28__atomic_futex_unsigned_base19_M_futex_wait_untilEPjjbNSt6chrono8durationIxSt5ratioILx1ELx1EEEENS2_IxS3_ILx1ELx1000000000EEEE@GLIBCXX_3.4.21 5
+ _ZNSt5ctypeIcEC1EP15__locale_structPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EP15__locale_structPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl16_M_install_cacheEPKNS_5facetEj@GLIBCXX_3.4.7 4.1.1
+ _ZNSt6locale5_ImplC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1ERKS0_j@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2ERKS0_j@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC1ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC2ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEixEj@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZSt11_Hash_bytesPKvjj@CXXABI_1.3.5 4.6
+ _ZSt15_Fnv_hash_bytesPKvjj@CXXABI_1.3.5 4.6
+ _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt17__copy_streambufsIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__copy_streambufsIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__verify_groupingPKcjRKSs@GLIBCXX_3.4.10 4.3
+ _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZThn8_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZdaPvj@CXXABI_1.3.9 5
+ _ZdlPvj@CXXABI_1.3.9 5
+ _Znaj@GLIBCXX_3.4 4.1.1
+ _ZnajRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwj@GLIBCXX_3.4 4.1.1
+ _ZnwjRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.32bit.cxx11
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.32bit.cxx11
@@ -0,0 +1,329 @@
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4copyEPcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_checkEjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_limitEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4copyEPwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6substrEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_checkEjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_limitEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE12_M_transformEPcPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE12_M_transformEPwPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES4_S4_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES4_S4_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES4_S4_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES4_S4_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES4_S4_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES4_S4_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_destroyEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEjjPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_S_compareEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_capacityEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_set_lengthEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE14_M_replace_auxEjjjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE18_M_construct_aux_2Ejc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5eraseEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEN9__gnu_cxx17__normal_iteratorIPKcS4_EEjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEN9__gnu_cxx17__normal_iteratorIPcS4_EEjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEjPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEjjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6resizeEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6resizeEjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_S8_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_jc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_PKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_jc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEjjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEjjPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEjjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEjjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEjjjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_eraseEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_lengthEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEjjPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_S_assignEPcjc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_jjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EjcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EPKcjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_jjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EjcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE10_M_destroyEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE10_M_replaceEjjPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE10_S_compareEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE11_M_capacityEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_M_constructEjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_M_set_lengthEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE14_M_replace_auxEjjjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE18_M_construct_aux_2Ejw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5eraseEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendEjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignEjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPKwS4_EEjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS4_EEjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEjPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEjPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEjjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6resizeEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6resizeEjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7_S_copyEPwPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7_S_moveEPwPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_S8_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_jw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_PKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_jw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEjjPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEjjPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEjjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEjjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEjjjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7reserveEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_eraseEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_appendEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_createERjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_lengthEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_mutateEjjPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_S_assignEPwjw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1EPKwjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ERKS4_jjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1EjwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2EPKwjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ERKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ERKS4_jjRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2EjwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPci@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE8_M_pbumpEPcS5_x@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwi@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS5_x@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNS_12basic_stringIcS3_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNS_12basic_stringIcS3_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKNS_12basic_stringIcS2_IcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKNS_12basic_stringIcS2_IcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt17__verify_groupingPKcjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.32bit.hurd
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.32bit.hurd
@@ -0,0 +1,536 @@
+#include "libstdc++6.symbols.common"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEj@GLIBCXX_3.4.4 4.1.1
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjRKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEj@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcjPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwjPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcjcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcjcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcjwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcjwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES3_S3_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES3_S3_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8valarrayIjE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructEjwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE14_M_replace_auxEjjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE15_M_replace_safeEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep8_M_cloneERKS1_j@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep9_S_createEjjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEjj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_jw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEjjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7reserveEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwjw@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_mutateEjjj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EPKwjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_jjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EjwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EPKwjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_jjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EjwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi4readEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSi6ignoreEii@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi8readsomeEPci@GLIBCXX_3.4 4.1.1
+ _ZNSo5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSo5writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSo8_M_writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSs12_S_constructEjcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs14_M_replace_auxEjjjc@GLIBCXX_3.4 4.1.1
+ _ZNSs15_M_replace_safeEjjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs2atEj@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4.5 4.1.1
+ _ZNSs4_Rep8_M_cloneERKSaIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep9_S_createEjjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs5eraseEjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjRKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEjjc@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEj@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEjc@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcj@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7_M_moveEPcPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_moveEPcPKcj@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_jc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjRKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEjjjc@GLIBCXX_3.4 4.1.1
+ _ZNSs7reserveEj@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcjc@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcjc@GLIBCXX_3.4.5 4.1.1
+ _ZNSs9_M_mutateEjjj@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EPKcjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsjjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EjcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EPKcjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsjjRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EjcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsixEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EPSt17__timepunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EPSt17__timepunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EPSt17__timepunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EPSt17__timepunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE7seekoffExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE8xsputn_2EPKciS2_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_allocEj@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_setupEPcS0_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPFPvjEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPFPvjEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE22_M_convert_to_externalEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4readEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEij@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE8readsomeEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE8_M_writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9pubsetbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9pubsetbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcjj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwjj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EP15__locale_structPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EP15__locale_structPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EPKtbj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl16_M_install_cacheEPKNS_5facetEj@GLIBCXX_3.4.7 4.1.1
+ _ZNSt6locale5_ImplC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1ERKS0_j@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2ERKS0_j@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2EP15__locale_structPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC1ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC2ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayIjEixEj@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4 4.1.1
+ _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt17__copy_streambufsIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__copy_streambufsIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__verify_groupingPKcjRKSs@GLIBCXX_3.4.10 4.3
+ _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZThn8_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _Znaj@GLIBCXX_3.4 4.1.1
+ _ZnajRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwj@GLIBCXX_3.4 4.1.1
+ _ZnwjRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC1EP15__pthread_mutex@GLIBCXX_3.4 4.3.0
+ _ZNSt12__basic_fileIcEC2EP15__pthread_mutex@GLIBCXX_3.4 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.64bit
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.64bit
@@ -0,0 +1,614 @@
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.64bit.cxx11"
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPcl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKcl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEm@GLIBCXX_3.4.4 4.1.1
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcmPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwmPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEclRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwlRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEm@GLIBCXX_3.4.18 4.8
+ _ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEmmm@GLIBCXX_3.4.18 4.8
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8valarrayImE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE10_S_compareEmm@GLIBCXX_3.4.16 4.6.0
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructEmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE14_M_replace_auxEmmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE15_M_replace_safeEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE18_S_construct_aux_2EmwRKS1_@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep8_M_cloneERKS1_m@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep9_S_createEmmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEmm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_mw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7reserveEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwmw@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_mutateEmmm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EPKwmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_mmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EPKwmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_mmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPclc@GLIBCXX_3.4 4.1.1
+ _ZNSi4readEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSi5seekgElSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEl@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEl@GLIBCXX_3.4.5 4.1.1
+ _ZNSi6ignoreEli@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPclc@GLIBCXX_3.4 4.1.1
+ _ZNSi8readsomeEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSo5seekpElSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSo5writeEPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSo8_M_writeEPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSs10_S_compareEmm@GLIBCXX_3.4.16 4.6.0
+ _ZNSs12_S_constructEmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs14_M_replace_auxEmmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs15_M_replace_safeEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs18_S_construct_aux_2EmcRKSaIcE@GLIBCXX_3.4.14 4.5
+ _ZNSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs4_Rep8_M_cloneERKSaIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep9_S_createEmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs5eraseEmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEm@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7_M_moveEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_moveEPcPKcm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_mc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs7reserveEm@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcmc@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcmc@GLIBCXX_3.4.5 4.1.1
+ _ZNSs9_M_mutateEmmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EPKcmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EPKcmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11this_thread11__sleep_forENSt6chrono8durationIlSt5ratioILl1ELl1EEEENS1_IlS2_ILl1ELl1000000000EEEE@GLIBCXX_3.4.18 4.8
+ _ZNSt11__timepunctIcEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EPSt17__timepunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EPSt17__timepunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EPSt17__timepunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EPSt17__timepunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsgetnEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsputnEPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE7seekoffElSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE8xsputn_2EPKclS2_l@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt12strstreambuf6setbufEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_allocEm@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_setupEPcS0_l@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPFPvmEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKal@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKhl@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPalS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPclS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPhlS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1El@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPFPvmEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKal@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKhl@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPalS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPclS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPhlS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2El@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE13_M_set_bufferEl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6setbufEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsgetnEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsputnEPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7_M_seekElSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE13_M_set_bufferEl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE22_M_convert_to_externalEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6setbufEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsgetnEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsputnEPKwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7_M_seekElSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwlw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4readEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgElSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEl@GLIBCXX_3.4.5 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreElj@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwlw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE8readsomeEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5seekpElSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5writeEPKwl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE8_M_writeEPKwl@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt14collate_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ (arch=!alpha !powerpc !ppc64 !ppc64el !s390 !s390x)_ZNSt14numeric_limitsIeE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE10pubseekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_gbumpEl@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_pbumpEl@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sgetnEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sputnEPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6setbufEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsgetnEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsputnEPKcl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9pubsetbufEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPcl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE8_M_pbumpEPcS4_l@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE10pubseekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sgetnEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sputnEPKwl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6setbufEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsgetnEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsputnEPKwl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9pubsetbufEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_gbumpEl@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_pbumpEl@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwl@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS4_l@GLIBCXX_3.4.16 4.6.0
+ _ZNSt15messages_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15messages_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15messages_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15messages_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15numpunct_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC2ERKSsm@GLIBCXX_3.4.21 5
+
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt16__numpunct_cacheIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIcLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIcLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIcLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC1ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt17moneypunct_bynameIwLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC2ERKSsm@GLIBCXX_3.4.21 5
+ _ZNSt18__moneypunct_cacheIcLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ (arch=!kfreebsd-amd64)_ZNSt28__atomic_futex_unsigned_base19_M_futex_wait_untilEPjjbNSt6chrono8durationIlSt5ratioILl1ELl1EEEENS2_IlS3_ILl1ELl1000000000EEEE@GLIBCXX_3.4.21 5
+ _ZNSt5ctypeIcEC1EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC1EmRKSt8valarrayImES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC2EmRKSt8valarrayImES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl16_M_install_cacheEPKNS_5facetEm@GLIBCXX_3.4.7 4.1.1
+ _ZNSt6locale5_ImplC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1ERKS0_m@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2ERKS0_m@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2Em@GLIBCXX_3.4 4.1.1
+
+ _ZNSt7codecvtIcc11__mbstate_tEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC1ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC2ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEixEm@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZSt11_Hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt15_Fnv_hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@GLIBCXX_3.4.9 4.2.1
+ _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_l@GLIBCXX_3.4.9 4.2.1
+ _ZSt17__copy_streambufsIcSt11char_traitsIcEElPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.8 4.1.1
+ _ZSt17__copy_streambufsIwSt11char_traitsIwEElPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.8 4.1.1
+ _ZSt17__verify_groupingPKcmRKSs@GLIBCXX_3.4.10 4.3
+ _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEElPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEElPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZTIPKn@CXXABI_1.3.5 4.6
+ _ZTIPKo@CXXABI_1.3.5 4.6
+ _ZTIPn@CXXABI_1.3.5 4.6
+ _ZTIPo@CXXABI_1.3.5 4.6
+ _ZTIn@CXXABI_1.3.5 4.6
+ _ZTIo@CXXABI_1.3.5 4.6
+ _ZTSPKn@CXXABI_1.3.9 5
+ _ZTSPKo@CXXABI_1.3.9 5
+ _ZTSPn@CXXABI_1.3.9 5
+ _ZTSPo@CXXABI_1.3.9 5
+ _ZTSn@CXXABI_1.3.9 5
+ _ZTSo@CXXABI_1.3.9 5
+ _ZThn16_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZdaPvm@CXXABI_1.3.9 5
+ _ZdlPvm@CXXABI_1.3.9 5
+ _Znam@GLIBCXX_3.4 4.1.1
+ _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwm@GLIBCXX_3.4 4.1.1
+ _ZnwmRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.64bit.cxx11
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.64bit.cxx11
@@ -0,0 +1,329 @@
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4copyEPcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_checkEmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_limitEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES4_S4_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES4_S4_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES4_S4_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES4_S4_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES4_S4_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES4_S4_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_destroyEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_S_compareEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_capacityEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_set_lengthEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE14_M_replace_auxEmmmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE18_M_construct_aux_2Emc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5eraseEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEN9__gnu_cxx17__normal_iteratorIPKcS4_EEmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEN9__gnu_cxx17__normal_iteratorIPcS4_EEmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6resizeEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6resizeEmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_S8_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_mc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_PKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_mc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEmmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEmmPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEmmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEmmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEmmmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_eraseEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_lengthEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_S_assignEPcmc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_mmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EmcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EPKcmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_mmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EmcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE10_M_destroyEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE10_M_replaceEmmPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE10_S_compareEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE11_M_capacityEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_M_constructEmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_M_set_lengthEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE14_M_replace_auxEmmmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE18_M_construct_aux_2Emw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5eraseEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendEmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignEmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPKwS4_EEmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS4_EEmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEmPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEmPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEmmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6resizeEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6resizeEmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7_S_copyEPwPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7_S_moveEPwPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_S8_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_mw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_PKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_mw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEmmPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEmmPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEmmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEmmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEmmmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7reserveEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_eraseEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_appendEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_createERmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_lengthEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_mutateEmmPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_S_assignEPwmw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1EPKwmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ERKS4_mmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1EmwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2EPKwmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ERKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ERKS4_mmRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2EmwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPcl@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE8_M_pbumpEPcS5_l@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwl@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS5_l@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNS_12basic_stringIcS3_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNS_12basic_stringIcS3_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKNS_12basic_stringIcS2_IcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKNS_12basic_stringIcS2_IcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt17__verify_groupingPKcmRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.alpha
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.alpha
@@ -0,0 +1,56 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNSt14numeric_limitsInE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_signedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_signedE@GLIBCXX_3.4.17 4.8
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.amd64
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.amd64
@@ -0,0 +1,16 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvmS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvmS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.arm
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.arm
@@ -0,0 +1,6 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_sj0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.arm64
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.arm64
@@ -0,0 +1,10 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.armel
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.armel
@@ -0,0 +1,13 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+ CXXABI_ARM_1.3.3@CXXABI_ARM_1.3.3 4.4.0
+ _ZNKSt9type_info6beforeERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt9type_infoeqERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ __cxa_begin_cleanup@CXXABI_1.3 4.3.0
+ __cxa_end_cleanup@CXXABI_1.3 4.3.0
+ __cxa_type_match@CXXABI_1.3 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.armhf
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.armhf
@@ -0,0 +1,13 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+ CXXABI_ARM_1.3.3@CXXABI_ARM_1.3.3 4.4.0
+ _ZNKSt9type_info6beforeERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt9type_infoeqERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ __cxa_begin_cleanup@CXXABI_1.3 4.3.0
+ __cxa_end_cleanup@CXXABI_1.3 4.3.0
+ __cxa_type_match@CXXABI_1.3 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.common
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.common
@@ -0,0 +1,3462 @@
+ CXXABI_1.3.1@CXXABI_1.3.1 4.1.1
+ CXXABI_1.3.2@CXXABI_1.3.2 4.3
+ CXXABI_1.3.3@CXXABI_1.3.3 4.4.0
+ CXXABI_1.3.4@CXXABI_1.3.4 4.5
+ CXXABI_1.3.5@CXXABI_1.3.5 4.6
+ CXXABI_1.3.6@CXXABI_1.3.6 4.7
+ CXXABI_1.3.7@CXXABI_1.3.7 4.8
+ CXXABI_1.3.8@CXXABI_1.3.8 4.9
+ CXXABI_1.3.9@CXXABI_1.3.9 5
+ CXXABI_1.3.10@CXXABI_1.3.10 6
+ CXXABI_1.3@CXXABI_1.3 4.1.1
+ CXXABI_TM_1@CXXABI_TM_1 4.7
+ GLIBCXX_3.4.10@GLIBCXX_3.4.10 4.3
+ GLIBCXX_3.4.11@GLIBCXX_3.4.11 4.4.0
+ GLIBCXX_3.4.12@GLIBCXX_3.4.12 4.4.0
+ GLIBCXX_3.4.13@GLIBCXX_3.4.13 4.4.2
+ GLIBCXX_3.4.14@GLIBCXX_3.4.14 4.5
+ GLIBCXX_3.4.15@GLIBCXX_3.4.15 4.6
+ GLIBCXX_3.4.16@GLIBCXX_3.4.16 4.6.0
+ GLIBCXX_3.4.17@GLIBCXX_3.4.17 4.7
+ GLIBCXX_3.4.18@GLIBCXX_3.4.18 4.8
+ GLIBCXX_3.4.19@GLIBCXX_3.4.19 4.8
+ GLIBCXX_3.4.1@GLIBCXX_3.4.1 4.1.1
+ GLIBCXX_3.4.20@GLIBCXX_3.4.20 4.9
+ GLIBCXX_3.4.21@GLIBCXX_3.4.21 5
+ GLIBCXX_3.4.22@GLIBCXX_3.4.22 6
+ GLIBCXX_3.4.2@GLIBCXX_3.4.2 4.1.1
+ GLIBCXX_3.4.3@GLIBCXX_3.4.3 4.1.1
+ GLIBCXX_3.4.4@GLIBCXX_3.4.4 4.1.1
+ GLIBCXX_3.4.5@GLIBCXX_3.4.5 4.1.1
+ GLIBCXX_3.4.6@GLIBCXX_3.4.6 4.1.1
+ GLIBCXX_3.4.7@GLIBCXX_3.4.7 4.1.1
+ GLIBCXX_3.4.8@GLIBCXX_3.4.8 4.1.1
+ GLIBCXX_3.4.9@GLIBCXX_3.4.9 4.2.1
+ GLIBCXX_3.4@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.common.cxx11"
+(arch=amd64 i386 x32 kfreebsd-amd64 kfreebsd-i386)#include "libstdc++6.symbols.float128"
+(arch=!armel)#include "libstdc++6.symbols.not-armel"
+ (arch=!armel !hurd-i386 !kfreebsd-amd64 !kfreebsd-i386)_ZNSt28__atomic_futex_unsigned_base19_M_futex_notify_allEPj@GLIBCXX_3.4.21 5
+ _ZGTtNKSt11logic_error4whatEv@GLIBCXX_3.4.22 6
+ _ZGTtNKSt13bad_exception4whatEv@CXXABI_1.3.10 6
+ _ZGTtNKSt13bad_exceptionD1Ev@CXXABI_1.3.10 6
+ _ZGTtNKSt13runtime_error4whatEv@GLIBCXX_3.4.22 6
+ _ZGTtNKSt9exception4whatEv@CXXABI_1.3.10 6
+ _ZGTtNKSt9exceptionD1Ev@CXXABI_1.3.10 6
+ _ZGTtNSt11logic_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11logic_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11logic_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11range_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11range_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12domain_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12domain_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12length_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12length_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12out_of_rangeC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12out_of_rangeC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt13runtime_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt14overflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt14overflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt15underflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt15underflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt16invalid_argumentC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt16invalid_argumentC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentD2Ev@GLIBCXX_3.4.22 6
+ _ZGVNSt10moneypunctIcLb0EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt10moneypunctIcLb1EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt10moneypunctIwLb0EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt10moneypunctIwLb1EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt11__timepunctIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt11__timepunctIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7collateIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7collateIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8messagesIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8messagesIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8numpunctIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8numpunctIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZN10__cxxabiv116__enum_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv116__enum_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv116__enum_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__array_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__array_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__array_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__class_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__class_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__class_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__pbase_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__pbase_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__pbase_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv119__pointer_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv119__pointer_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv119__pointer_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__function_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__function_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__function_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__si_class_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__si_class_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__si_class_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv121__vmi_class_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv121__vmi_class_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv121__vmi_class_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv123__fundamental_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv123__fundamental_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv123__fundamental_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv129__pointer_to_member_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv129__pointer_to_member_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv129__pointer_to_member_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__gnu_norm15_List_node_base4hookEPS0_@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base4swapERS0_S1_@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base6unhookEv@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base7reverseEv@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base8transferEPS0_S1_@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_iterator_base12_M_get_mutexEv@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_iterator_base16_M_attach_singleEPNS_19_Safe_sequence_baseEb@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_iterator_base16_M_detach_singleEv@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_iterator_base9_M_attachEPNS_19_Safe_sequence_baseEb@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_iterator_base9_M_detachEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base12_M_get_mutexEv@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_sequence_base13_M_detach_allEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base18_M_detach_singularEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base22_M_revalidate_singularEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base7_M_swapERS0_@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug25_Safe_local_iterator_base9_M_attachEPNS_19_Safe_sequence_baseEb@GLIBCXX_3.4.17 4.7
+ _ZN11__gnu_debug25_Safe_local_iterator_base9_M_detachEv@GLIBCXX_3.4.17 4.7
+ _ZN11__gnu_debug30_Safe_unordered_container_base13_M_detach_allEv@GLIBCXX_3.4.17 4.7
+ _ZN11__gnu_debug30_Safe_unordered_container_base7_M_swapERS0_@GLIBCXX_3.4.17 4.7
+ _ZN14__gnu_parallel9_Settings3getEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN14__gnu_parallel9_Settings3setERS0_@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx17__pool_alloc_base12_M_get_mutexEv@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE4fileEv@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE4syncEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE4syncEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE5uflowEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE5uflowEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE8overflowEi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE9pbackfailEi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE9underflowEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC1EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC2EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE4fileEv@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE5uflowEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE8overflowEj@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE9pbackfailEj@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE9underflowEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC1EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC2EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZN9__gnu_cxx27__verbose_terminate_handlerEv@CXXABI_1.3 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE10_M_destroyEv@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE13_M_initializeEv@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE10_M_destroyEv@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE13_M_initializeEPFvPvE@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE13_M_initializeEv@GLIBCXX_3.4.6 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_get_thread_idEv@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE21_M_destroy_thread_keyEPv@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9__freeresEv@CXXABI_1.3.10 6
+ _ZN9__gnu_cxx9free_list8_M_clearEv@GLIBCXX_3.4.4 4.1.1
+ _ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PPv@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__pbase_type_info10__do_catchEPKSt9type_infoPPvj@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__pbase_type_info15__pointer_catchEPKS0_PPvj@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv119__pointer_type_info14__is_pointer_pEv@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv119__pointer_type_info15__pointer_catchEPKNS_17__pbase_type_infoEPPvj@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__function_type_info15__is_function_pEv@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv129__pointer_to_member_type_info15__pointer_catchEPKNS_17__pbase_type_infoEPPvj@CXXABI_1.3 4.1.1
+ _ZNK11__gnu_debug16_Error_formatter10_M_messageENS_13_Debug_msg_idE@GLIBCXX_3.4 4.1.1
+ _ZNK11__gnu_debug16_Error_formatter10_Parameter14_M_print_fieldEPKS0_PKc@GLIBCXX_3.4 4.1.1
+ _ZNK11__gnu_debug16_Error_formatter10_Parameter20_M_print_descriptionEPKS0_@GLIBCXX_3.4 4.1.1
+ _ZNK11__gnu_debug16_Error_formatter13_M_print_wordEPKc@GLIBCXX_3.4 4.1.1
+ _ZNK11__gnu_debug16_Error_formatter15_M_print_stringEPKc@GLIBCXX_3.4 4.1.1
+ _ZNK11__gnu_debug16_Error_formatter17_M_get_max_lengthEv@GLIBCXX_3.4.10 4.3
+ _ZNK11__gnu_debug16_Error_formatter8_M_errorEv@GLIBCXX_3.4 4.1.1
+ _ZNK11__gnu_debug19_Safe_iterator_base11_M_singularEv@GLIBCXX_3.4 4.1.1
+ _ZNK11__gnu_debug19_Safe_iterator_base14_M_can_compareERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE11_M_disjunctEPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE11_M_disjunctEPKw@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13get_allocatorEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE3endEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4_Rep12_M_is_leakedEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4_Rep12_M_is_sharedEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4backEv@GLIBCXX_3.4.15 4.6
+ _ZNKSbIwSt11char_traitsIwESaIwEE4cendEv@GLIBCXX_3.4.14 4.5
+ _ZNKSbIwSt11char_traitsIwESaIwEE4dataEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4rendEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5beginEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5crendEv@GLIBCXX_3.4.14 4.5
+ _ZNKSbIwSt11char_traitsIwESaIwEE5c_strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5emptyEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5frontEv@GLIBCXX_3.4.15 4.6
+ _ZNKSbIwSt11char_traitsIwESaIwEE6_M_repEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6cbeginEv@GLIBCXX_3.4.14 4.5
+ _ZNKSbIwSt11char_traitsIwESaIwEE6lengthEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6rbeginEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7_M_dataEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7_M_iendEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7crbeginEv@GLIBCXX_3.4.14 4.5
+ _ZNKSbIwSt11char_traitsIwESaIwEE8capacityEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8max_sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE9_M_ibeginEv@GLIBCXX_3.4 4.1.1
+ _ZNKSi6gcountEv@GLIBCXX_3.4 4.1.1
+ _ZNKSi6sentrycvbEv@GLIBCXX_3.4 4.1.1
+ _ZNKSo6sentrycvbEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs11_M_disjunctEPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs11_M_disjunctEPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs13get_allocatorEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs3endEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs4_Rep12_M_is_leakedEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs4_Rep12_M_is_sharedEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs4backEv@GLIBCXX_3.4.15 4.6
+ _ZNKSs4cendEv@GLIBCXX_3.4.14 4.5
+ _ZNKSs4dataEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs4rendEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs5beginEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs5c_strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs5crendEv@GLIBCXX_3.4.14 4.5
+ _ZNKSs5emptyEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs5frontEv@GLIBCXX_3.4.15 4.6
+ _ZNKSs6_M_repEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs6cbeginEv@GLIBCXX_3.4.14 4.5
+ _ZNKSs6lengthEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs6rbeginEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs7_M_dataEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs7_M_iendEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareERKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7crbeginEv@GLIBCXX_3.4.14 4.5
+ _ZNKSs8capacityEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs8max_sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNKSs9_M_ibeginEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10bad_typeid4whatEv@GLIBCXX_3.4.9 4.2.1
+ _ZNKSt10error_code23default_error_conditionEv@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt10istrstream5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10lock_error4whatEv@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt10moneypunctIcLb0EE10neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE10pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE11curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE11do_groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE11frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE13do_neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE13do_pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE13negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE13positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE14do_curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE14do_frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE16do_negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE16do_positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb0EE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE10neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE10pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE11curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE11do_groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE11frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE13do_neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE13do_pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE13negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE13positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE14do_curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE14do_frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE16do_negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE16do_positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIcLb1EE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE10neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE10pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE11curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE11do_groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE11frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE13do_neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE13do_pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE13negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE13positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE14do_curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE14do_frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE16do_negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE16do_positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb0EE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE10neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE10pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE11curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE11do_groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE11frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE13do_neg_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE13do_pos_formatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE13negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE13positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE14do_curr_symbolEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE14do_frac_digitsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE16do_negative_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE16do_positive_signEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10moneypunctIwLb1EE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10ostrstream5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt10ostrstream6pcountEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE15_M_am_pm_formatEPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE15_M_date_formatsEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE15_M_time_formatsEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE19_M_days_abbreviatedEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE20_M_date_time_formatsEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE21_M_months_abbreviatedEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE7_M_daysEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE8_M_am_pmEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE9_M_monthsEPPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE15_M_am_pm_formatEPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE15_M_date_formatsEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE15_M_time_formatsEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE19_M_days_abbreviatedEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE20_M_date_time_formatsEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE21_M_months_abbreviatedEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE7_M_daysEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE8_M_am_pmEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE9_M_monthsEPPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt11logic_error4whatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt12__basic_fileIcE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt12bad_weak_ptr4whatEv@GLIBCXX_3.4.15 4.6
+ _ZNKSt12future_error4whatEv@GLIBCXX_3.4.14 4.5
+ _ZNKSt12strstreambuf6pcountEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13bad_exception4whatEv@GLIBCXX_3.4.9 4.2.1
+ _ZNKSt13basic_filebufIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_filebufIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_fstreamIcSt11char_traitsIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_fstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_fstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt13basic_fstreamIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_fstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_fstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt13basic_istreamIwSt11char_traitsIwEE6gcountEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_istreamIwSt11char_traitsIwEE6sentrycvbEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_ostreamIwSt11char_traitsIwEE6sentrycvbEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13runtime_error4whatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIcSt11char_traitsIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt14basic_ifstreamIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt14basic_ofstreamIcSt11char_traitsIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt14basic_ofstreamIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt14error_category10equivalentERKSt10error_codei@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt14error_category10equivalentEiRKSt15error_condition@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt14error_category23default_error_conditionEi@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE4gptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE4pptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5ebackEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5egptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5epptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5pbaseEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE6getlocEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE4gptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE4pptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5ebackEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5egptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5epptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5pbaseEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt16bad_array_length4whatEv@CXXABI_1.3.8 4.9
+ _ZNKSt17bad_function_call4whatEv@GLIBCXX_3.4.18 4.8
+ _ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE5do_inER11__mbstate_tPKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE6do_outER11__mbstate_tPKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE5do_inER11__mbstate_tPKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE6do_outER11__mbstate_tPKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE5do_inER11__mbstate_tPKcS4_RS4_PwS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE6do_outER11__mbstate_tPKwS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19basic_istringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_istringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_istringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_istringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt20__codecvt_utf16_baseIDiE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE5do_inER11__mbstate_tPKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE6do_outER11__mbstate_tPKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE5do_inER11__mbstate_tPKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE6do_outER11__mbstate_tPKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE5do_inER11__mbstate_tPKcS4_RS4_PwS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE6do_outER11__mbstate_tPKwS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20bad_array_new_length4whatEv@CXXABI_1.3.8 4.9
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE5do_inER11__mbstate_tPKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE6do_outER11__mbstate_tPKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE5do_inER11__mbstate_tPKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE6do_outER11__mbstate_tPKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE5do_inER11__mbstate_tPKcS4_RS4_PwS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE6do_outER11__mbstate_tPKwS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category10_M_messageEi@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category10equivalentERKSt10error_codei@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category10equivalentEiRKSt15error_condition@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category23default_error_conditionEi@GLIBCXX_3.4.21 5
+ _ZNKSt3tr14hashIRKSbIwSt11char_traitsIwESaIwEEEclES6_@GLIBCXX_3.4.10 4.3
+ _ZNKSt3tr14hashIRKSsEclES2_@GLIBCXX_3.4.10 4.3
+ _ZNKSt3tr14hashISbIwSt11char_traitsIwESaIwEEEclES4_@GLIBCXX_3.4.10 4.3
+ _ZNKSt3tr14hashISsEclESs@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIRKSbIwSt11char_traitsIwESaIwEEEclES5_@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIRKSsEclES1_@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashISbIwSt11char_traitsIwESaIwEEEclES3_@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashISsEclESs@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashISt10error_codeEclES0_@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt5ctypeIcE10do_tolowerEPcPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE10do_tolowerEc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE10do_toupperEPcPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE10do_toupperEc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE13_M_widen_initEv@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt5ctypeIcE14_M_narrow_initEv@GLIBCXX_3.4.11 4.4.0
+ _ZNKSt5ctypeIcE8do_widenEPKcS2_Pc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE8do_widenEc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE9do_narrowEPKcS2_cPc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE9do_narrowEcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE10do_scan_isEtPKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE10do_tolowerEPwPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE10do_tolowerEw@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE10do_toupperEPwPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE10do_toupperEw@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE11do_scan_notEtPKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE19_M_convert_to_wmaskEt@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE5do_isEPKwS2_Pt@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE5do_isEtw@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE8do_widenEPKcS2_Pw@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE8do_widenEc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE9do_narrowEPKwS2_cPc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIwE9do_narrowEwc@GLIBCXX_3.4 4.1.1
+ _ZNKSt6locale2id5_M_idEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt6locale4nameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt6localeeqERKS_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIDic11__mbstate_tE10do_unshiftERS0_PcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE5do_inERS0_PKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE6do_outERS0_PKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE10do_unshiftERS0_PcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE5do_inERS0_PKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE6do_outERS0_PKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIcc11__mbstate_tE10do_unshiftERS0_PcS3_RS3_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIcc11__mbstate_tE11do_encodingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIcc11__mbstate_tE13do_max_lengthEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIcc11__mbstate_tE16do_always_noconvEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIcc11__mbstate_tE5do_inERS0_PKcS4_RS4_PcS6_RS6_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIcc11__mbstate_tE6do_outERS0_PKcS4_RS4_PcS6_RS6_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE10do_unshiftERS0_PcS3_RS3_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE11do_encodingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE13do_max_lengthEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE16do_always_noconvEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE5do_inERS0_PKcS4_RS4_PwS6_RS6_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE6do_outERS0_PKwS4_RS4_PcS6_RS6_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE10_M_compareEPKcS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE10do_compareEPKcS2_S2_S2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12do_transformEPKcS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE4hashEPKcS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE7compareEPKcS2_S2_S2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE7do_hashEPKcS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE9transformEPKcS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE10_M_compareEPKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE10do_compareEPKwS2_S2_S2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12do_transformEPKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE4hashEPKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE7compareEPKwS2_S2_S2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE7do_hashEPKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE9transformEPKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIjEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intItEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIxEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIyEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16_M_extract_floatES3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIjEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIlEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intImEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intItEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIxEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIyEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16_M_extract_floatES3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIlEES3_S3_RSt8ios_basecT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intImEES3_S3_RSt8ios_basecT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIxEES3_S3_RSt8ios_basecT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIyEES3_S3_RSt8ios_basecT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES3_S3_RSt8ios_baseccT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIeEES3_S3_RSt8ios_baseccT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecPKv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basece@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecy@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecPKv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basece@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecy@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIlEES3_S3_RSt8ios_basewT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intImEES3_S3_RSt8ios_basewT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIxEES3_S3_RSt8ios_basewT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIyEES3_S3_RSt8ios_basewT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIdEES3_S3_RSt8ios_basewcT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIeEES3_S3_RSt8ios_basewcT_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewPKv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewe@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewy@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewPKv@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewb@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewd@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewe@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewl@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewx@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@GLIBCXX_3.4 4.1.1
+ _ZNKSt8bad_cast4whatEv@GLIBCXX_3.4.9 4.2.1
+ _ZNKSt8ios_base7failure4whatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE18_M_convert_to_charERKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE20_M_convert_from_charEPc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE3getEiiiRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE4openERKSsRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE4openERKSsRKSt6localePKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE5closeEi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE6do_getEiiiRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE7do_openERKSsRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIcE8do_closeEi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE18_M_convert_to_charERKSbIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE20_M_convert_from_charEPc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE3getEiiiRKSbIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE4openERKSsRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE4openERKSsRKSt6localePKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE5closeEi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE6do_getEiiiRKSbIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE7do_openERKSsRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNKSt8messagesIwE8do_closeEi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE11do_groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE11do_truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE12do_falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE8truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE9falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE11do_groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE11do_truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE12do_falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE8truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE9falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10date_orderEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_yearES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13do_date_orderEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14do_get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16do_get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKcSC_@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE21_M_extract_via_formatES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_yearES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10date_orderEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_yearES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13do_date_orderEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14do_get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16do_get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE21_M_extract_via_formatES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKwSC_@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_yearES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecPK2tmPKcSB_@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecPK2tmcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_RSt8ios_basecPK2tmcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewPK2tmPKwSB_@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_RSt8ios_basewPK2tmcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewPK2tmcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9bad_alloc4whatEv@GLIBCXX_3.4.9 4.2.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE10exceptionsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE3badEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE3eofEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE3tieEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE4failEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE4fillEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE4goodEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE6narrowEcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE7rdstateEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEEcvbEv@GLIBCXX_3.4.21 5
+ _ZNKSt9basic_iosIcSt11char_traitsIcEEntEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE10exceptionsEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE3badEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE3eofEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE3tieEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE4failEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE4fillEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE4goodEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE5widenEc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE6narrowEwc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE7rdstateEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEEcvPvEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEEcvbEv@GLIBCXX_3.4.21 5
+ _ZNKSt9basic_iosIwSt11char_traitsIwEEntEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9exception4whatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb1EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb0EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb1EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_bRSt8ios_basecRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_bRSt8ios_basece@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_bRSt8ios_basecRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_bRSt8ios_basece@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb0EEES3_S3_RSt8ios_basecRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb1EEES3_S3_RSt8ios_basecRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_bRSt8ios_basewRKSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES3_bRSt8ios_basewe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_bRSt8ios_basewRKSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_bRSt8ios_basewe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb0EEES3_S3_RSt8ios_basewRKSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb1EEES3_S3_RSt8ios_basewRKSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt9strstream5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9strstream6pcountEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9type_info10__do_catchEPKS_PPvj@GLIBCXX_3.4 4.1.1
+ _ZNKSt9type_info11__do_upcastEPKN10__cxxabiv117__class_type_infoEPPv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9type_info14__is_pointer_pEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9type_info15__is_function_pEv@GLIBCXX_3.4 4.1.1
+ _ZNSaIcEC1ERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSaIcEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSaIcEC2ERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSaIcEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSaIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSaIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSaIwEC1ERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSaIwEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSaIwEC2ERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSaIwEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSaIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSaIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE12_Alloc_hiderC1EPwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE12_Alloc_hiderC2EPwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE12_M_leak_hardEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructIN9__gnu_cxx17__normal_iteratorIPwS2_EEEES6_T_S8_RKS1_St20forward_iterator_tag@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructIPKwEEPwT_S7_RKS1_St20forward_iterator_tag@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructIPwEES4_T_S5_RKS1_St20forward_iterator_tag@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_empty_repEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwN9__gnu_cxx17__normal_iteratorIPKwS2_EES8_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwN9__gnu_cxx17__normal_iteratorIS3_S2_EES6_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwPKwS5_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwS3_S3_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE13shrink_to_fitEv@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE3endEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_destroyERKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_disposeERKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_refcopyEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_refdataEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep11_S_max_sizeE@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep11_S_terminalE@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep12_S_empty_repEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep13_M_set_leakedEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep15_M_set_sharableEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep20_S_empty_rep_storageE@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep7_M_grabERKS1_S5_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4backEv@GLIBCXX_3.4.15 4.6
+ _ZNSbIwSt11char_traitsIwESaIwEE4nposE@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4rendEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4swapERS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5beginEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5clearEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEN9__gnu_cxx17__normal_iteratorIPwS2_EE@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5frontEv@GLIBCXX_3.4.15 4.6
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendESt16initializer_listIwE@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEOS2_@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignESt16initializer_listIwE@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EESt16initializer_listIwE@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EEw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6rbeginEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_dataEPw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_leakEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_NS4_IPKwS2_EES9_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKwS8_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_RKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_S5_S5_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_S6_S6_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_St16initializer_listIwE@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEE8pop_backEv@GLIBCXX_3.4.17 4.7
+ _ZNSbIwSt11char_traitsIwESaIwEE9push_backEw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EOS2_@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EPKwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1IN9__gnu_cxx17__normal_iteratorIPwS2_EEEET_S8_RKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1IPKwEET_S6_RKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1IPwEET_S5_RKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EOS2_@GLIBCXX_3.4.15 4.6
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EPKwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ESt16initializer_listIwERKS1_@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ESt16initializer_listIwERKS1_@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2IN9__gnu_cxx17__normal_iteratorIPwS2_EEEET_S8_RKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2IPKwEET_S6_RKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2IPwEET_S5_RKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEaSEOS2_@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEEaSEPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEaSERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEaSESt16initializer_listIwE@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEEaSEw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEpLEPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEpLERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEpLESt16initializer_listIwE@GLIBCXX_3.4.11 4.4.0
+ _ZNSbIwSt11char_traitsIwESaIwEEpLEw@GLIBCXX_3.4 4.1.1
+ _ZNSd4swapERSd@GLIBCXX_3.4.21 5
+ _ZNSdC1EOSd@GLIBCXX_3.4.21 5
+ _ZNSdC1EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSdC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSdC2EOSd@GLIBCXX_3.4.21 5
+ _ZNSdC2EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSdC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSdD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSdaSEOSd@GLIBCXX_3.4.21 5
+ _ZNSi10_M_extractIPvEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIbEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIdEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIeEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIfEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIjEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIlEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractImEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractItEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIxEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi10_M_extractIyEERSiRT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSi3getERSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSi3getERSt15basic_streambufIcSt11char_traitsIcEEc@GLIBCXX_3.4 4.1.1
+ _ZNSi3getERc@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEv@GLIBCXX_3.4 4.1.1
+ _ZNSi4peekEv@GLIBCXX_3.4 4.1.1
+ _ZNSi4swapERSi@GLIBCXX_3.4.21 5
+ _ZNSi4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSi5seekgESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZNSi5tellgEv@GLIBCXX_3.4 4.1.1
+ _ZNSi5ungetEv@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEv@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEv@GLIBCXX_3.4.5 4.1.1
+ _ZNSi6sentryC1ERSib@GLIBCXX_3.4 4.1.1
+ _ZNSi6sentryC2ERSib@GLIBCXX_3.4 4.1.1
+ _ZNSi7putbackEc@GLIBCXX_3.4 4.1.1
+ _ZNSiC1EOSi@GLIBCXX_3.4.21 5
+ _ZNSiC1EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSiC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSiC2EOSi@GLIBCXX_3.4.21 5
+ _ZNSiC2EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSiC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSiD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSiaSEOSi@GLIBCXX_3.4.21 5
+ _ZNSirsEPFRSiS_E@GLIBCXX_3.4 4.1.1
+ _ZNSirsEPFRSt8ios_baseS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSirsEPFRSt9basic_iosIcSt11char_traitsIcEES3_E@GLIBCXX_3.4 4.1.1
+ _ZNSirsEPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSirsERPv@GLIBCXX_3.4 4.1.1
+ _ZNSirsERb@GLIBCXX_3.4 4.1.1
+ _ZNSirsERd@GLIBCXX_3.4 4.1.1
+ _ZNSirsERe@GLIBCXX_3.4 4.1.1
+ _ZNSirsERf@GLIBCXX_3.4 4.1.1
+ _ZNSirsERi@GLIBCXX_3.4 4.1.1
+ _ZNSirsERj@GLIBCXX_3.4 4.1.1
+ _ZNSirsERl@GLIBCXX_3.4 4.1.1
+ _ZNSirsERm@GLIBCXX_3.4 4.1.1
+ _ZNSirsERs@GLIBCXX_3.4 4.1.1
+ _ZNSirsERt@GLIBCXX_3.4 4.1.1
+ _ZNSirsERx@GLIBCXX_3.4 4.1.1
+ _ZNSirsERy@GLIBCXX_3.4 4.1.1
+ _ZNSo3putEc@GLIBCXX_3.4 4.1.1
+ _ZNSo4swapERSo@GLIBCXX_3.4.21 5
+ _ZNSo5flushEv@GLIBCXX_3.4 4.1.1
+ _ZNSo5seekpESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZNSo5tellpEv@GLIBCXX_3.4 4.1.1
+ _ZNSo6sentryC1ERSo@GLIBCXX_3.4 4.1.1
+ _ZNSo6sentryC2ERSo@GLIBCXX_3.4 4.1.1
+ _ZNSo6sentryD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSo6sentryD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSo9_M_insertIPKvEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSo9_M_insertIbEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSo9_M_insertIdEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSo9_M_insertIeEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSo9_M_insertIlEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSo9_M_insertImEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSo9_M_insertIxEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSo9_M_insertIyEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSoC1EOSo@GLIBCXX_3.4.21 5
+ _ZNSoC1EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSoC1ERSd@GLIBCXX_3.4.21 5
+ _ZNSoC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSoC2EOSo@GLIBCXX_3.4.21 5
+ _ZNSoC2EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSoC2ERSd@GLIBCXX_3.4.21 5
+ _ZNSoC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSoD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSoaSEOSo@GLIBCXX_3.4.21 5
+ _ZNSolsEPFRSoS_E@GLIBCXX_3.4 4.1.1
+ _ZNSolsEPFRSt8ios_baseS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSolsEPFRSt9basic_iosIcSt11char_traitsIcEES3_E@GLIBCXX_3.4 4.1.1
+ _ZNSolsEPKv@GLIBCXX_3.4 4.1.1
+ _ZNSolsEPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSolsEb@GLIBCXX_3.4 4.1.1
+ _ZNSolsEd@GLIBCXX_3.4 4.1.1
+ _ZNSolsEe@GLIBCXX_3.4 4.1.1
+ _ZNSolsEf@GLIBCXX_3.4 4.1.1
+ _ZNSolsEi@GLIBCXX_3.4 4.1.1
+ _ZNSolsEj@GLIBCXX_3.4 4.1.1
+ _ZNSolsEl@GLIBCXX_3.4 4.1.1
+ _ZNSolsEm@GLIBCXX_3.4 4.1.1
+ _ZNSolsEs@GLIBCXX_3.4 4.1.1
+ _ZNSolsEt@GLIBCXX_3.4 4.1.1
+ _ZNSolsEx@GLIBCXX_3.4 4.1.1
+ _ZNSolsEy@GLIBCXX_3.4 4.1.1
+ _ZNSs12_Alloc_hiderC1EPcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs12_Alloc_hiderC2EPcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs12_M_leak_hardEv@GLIBCXX_3.4 4.1.1
+ _ZNSs12_S_constructIN9__gnu_cxx17__normal_iteratorIPcSsEEEES2_T_S4_RKSaIcESt20forward_iterator_tag@GLIBCXX_3.4.14 4.5
+ _ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag@GLIBCXX_3.4.14 4.5
+ _ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag@GLIBCXX_3.4.14 4.5
+ _ZNSs12_S_empty_repEv@GLIBCXX_3.4 4.1.1
+ _ZNSs13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIPKcSsEES4_@GLIBCXX_3.4 4.1.1
+ _ZNSs13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIS_SsEES2_@GLIBCXX_3.4 4.1.1
+ _ZNSs13_S_copy_charsEPcPKcS1_@GLIBCXX_3.4 4.1.1
+ _ZNSs13_S_copy_charsEPcS_S_@GLIBCXX_3.4 4.1.1
+ _ZNSs13shrink_to_fitEv@GLIBCXX_3.4.14 4.5
+ _ZNSs3endEv@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep10_M_destroyERKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep10_M_disposeERKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep10_M_refcopyEv@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep10_M_refdataEv@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep11_S_max_sizeE@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep11_S_terminalE@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep12_S_empty_repEv@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep13_M_set_leakedEv@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep15_M_set_sharableEv@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep20_S_empty_rep_storageE@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep7_M_grabERKSaIcES2_@GLIBCXX_3.4 4.1.1
+ _ZNSs4backEv@GLIBCXX_3.4.15 4.6
+ _ZNSs4nposE@GLIBCXX_3.4 4.1.1
+ _ZNSs4rendEv@GLIBCXX_3.4 4.1.1
+ _ZNSs4swapERSs@GLIBCXX_3.4 4.1.1
+ _ZNSs5beginEv@GLIBCXX_3.4 4.1.1
+ _ZNSs5clearEv@GLIBCXX_3.4 4.1.1
+ _ZNSs5eraseEN9__gnu_cxx17__normal_iteratorIPcSsEE@GLIBCXX_3.4 4.1.1
+ _ZNSs5eraseEN9__gnu_cxx17__normal_iteratorIPcSsEES2_@GLIBCXX_3.4 4.1.1
+ _ZNSs5frontEv@GLIBCXX_3.4.15 4.6
+ _ZNSs6appendEPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendESt16initializer_listIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSs6assignEOSs@GLIBCXX_3.4.14 4.5
+ _ZNSs6assignEPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignESt16initializer_listIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEESt16initializer_listIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEc@GLIBCXX_3.4 4.1.1
+ _ZNSs6rbeginEv@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_dataEPc@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_leakEv@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_NS0_IPKcSsEES5_@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcS4_@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_RKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_S1_S1_@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_S2_S2_@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_St16initializer_listIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSs8pop_backEv@GLIBCXX_3.4.17 4.7
+ _ZNSs9push_backEc@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EOSs@GLIBCXX_3.4.14 4.5
+ _ZNSsC1EPKcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ESt16initializer_listIcERKSaIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSsC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSsC1IN9__gnu_cxx17__normal_iteratorIPcSsEEEET_S4_RKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1IPKcEET_S2_RKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1IPcEET_S1_RKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EOSs@GLIBCXX_3.4.15 4.6
+ _ZNSsC2EPKcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ESt16initializer_listIcERKSaIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSsC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSsC2IN9__gnu_cxx17__normal_iteratorIPcSsEEEET_S4_RKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2IPKcEET_S2_RKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2IPcEET_S1_RKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSsD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSsaSEOSs@GLIBCXX_3.4.14 4.5
+ _ZNSsaSEPKc@GLIBCXX_3.4 4.1.1
+ _ZNSsaSERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSsaSESt16initializer_listIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSsaSEc@GLIBCXX_3.4 4.1.1
+ _ZNSspLEPKc@GLIBCXX_3.4 4.1.1
+ _ZNSspLERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSspLESt16initializer_listIcE@GLIBCXX_3.4.11 4.4.0
+ _ZNSspLEc@GLIBCXX_3.4 4.1.1
+ _ZNSt10_Sp_lockerC1EPKv@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerC1EPKvS1_@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerC2EPKv@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerC2EPKvS1_@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerD1Ev@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerD2Ev@GLIBCXX_3.4.21 5
+ _ZNSt10__num_base11_S_atoms_inE@GLIBCXX_3.4 4.1.1
+ _ZNSt10__num_base12_S_atoms_outE@GLIBCXX_3.4 4.1.1
+ _ZNSt10__num_base15_S_format_floatERKSt8ios_basePcc@GLIBCXX_3.4 4.1.1
+ _ZNSt10bad_typeidD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10bad_typeidD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10bad_typeidD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5alnumE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5alphaE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5blankE@GLIBCXX_3.4.21 5
+ _ZNSt10ctype_base5cntrlE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5digitE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5graphE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5lowerE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5printE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5punctE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5spaceE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5upperE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base6xdigitE@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstream3strEv@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPc@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPc@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10money_base18_S_default_patternE@GLIBCXX_3.4 4.1.1
+ _ZNSt10money_base20_S_construct_patternEccc@GLIBCXX_3.4 4.1.1
+ _ZNSt10money_base8_S_atomsE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstream3strEv@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstream6freezeEb@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstreamC1EPciSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstreamC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstreamC2EPciSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstreamC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt10ostrstreamD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcE23_M_initialize_timepunctEP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwE23_M_initialize_timepunctEP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11char_traitsIcE2eqERKcS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt11char_traitsIcE2eqERKcS2_@GLIBCXX_3.4.5 4.1.1
+ _ZNSt11char_traitsIwE2eqERKwS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt11char_traitsIwE2eqERKwS2_@GLIBCXX_3.4.5 4.1.1
+ _ZNSt11logic_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC1ERKS_@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt11logic_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC2ERKS_@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt11logic_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11logic_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11logic_errorD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11logic_erroraSERKS_@GLIBCXX_3.4.21 5
+ _ZNSt11range_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11range_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt11range_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11range_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt11range_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11range_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11range_errorD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt11regex_errorC1ENSt15regex_constants10error_typeE@GLIBCXX_3.4.20 4.9
+ _ZNSt11regex_errorC2ENSt15regex_constants10error_typeE@GLIBCXX_3.4.21 5
+ _ZNSt11regex_errorD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt11regex_errorD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt11regex_errorD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12__basic_fileIcE2fdEv@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE4fileEv@GLIBCXX_3.4.1 4.1.1
+ _ZNSt12__basic_fileIcE4openEPKcSt13_Ios_Openmodei@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE8sys_openEP8_IO_FILESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE8sys_openEiSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE9showmanycEv@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12bad_weak_ptrD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12bad_weak_ptrD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12bad_weak_ptrD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12ctype_bynameIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12domain_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12domain_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12domain_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12domain_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12domain_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12domain_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12domain_errorD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12future_errorD0Ev@GLIBCXX_3.4.14 4.5
+ _ZNSt12future_errorD1Ev@GLIBCXX_3.4.14 4.5
+ _ZNSt12future_errorD2Ev@GLIBCXX_3.4.14 4.5
+ _ZNSt12length_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12length_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12length_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12length_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12length_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12length_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12length_errorD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12out_of_rangeC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12out_of_rangeC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12out_of_rangeC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12out_of_rangeC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12out_of_rangeD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12out_of_rangeD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12out_of_rangeD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_1E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_2E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_3E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_4E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_5E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_6E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_7E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_8E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders2_9E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_10E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_11E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_12E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_13E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_14E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_15E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_16E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_17E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_18E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_19E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_20E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_21E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_22E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_23E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_24E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_25E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_26E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_27E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_28E@GLIBCXX_3.4.15 4.6
+ _ZNSt12placeholders3_29E@GLIBCXX_3.4.15 4.6
+ _ZNSt12strstreambuf3strEv@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf6freezeEb@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf7_M_freeEPc@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8overflowEi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf9pbackfailEi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12system_errorD0Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt12system_errorD1Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt12system_errorD2Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt13bad_exceptionD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13bad_exceptionD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13bad_exceptionD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE14_M_get_ext_posER11__mbstate_t@GLIBCXX_3.4.15 4.6
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE15_M_create_pbackEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE16_M_destroy_pbackEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE19_M_terminate_outputEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE26_M_destroy_internal_bufferEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE27_M_allocate_internal_bufferEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE8overflowEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE9pbackfailEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE9showmanycEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE14_M_get_ext_posER11__mbstate_t@GLIBCXX_3.4.15 4.6
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE15_M_create_pbackEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE16_M_destroy_pbackEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE19_M_terminate_outputEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE26_M_destroy_internal_bufferEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE27_M_allocate_internal_bufferEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE8overflowEj@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE9pbackfailEj@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE9showmanycEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIPvEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIbEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIdEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIeEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIfEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIjEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIlEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractImEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractItEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIxEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIyEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getERSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getERSt15basic_streambufIwS1_Ew@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getERw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4peekEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5tellgEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5ungetEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEv@GLIBCXX_3.4.5 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6sentryC1ERS2_b@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6sentryC2ERS2_b@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7putbackEw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPFRS2_S3_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPFRSt8ios_baseS4_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPFRSt9basic_iosIwS1_ES5_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERPv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERb@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERd@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERe@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERf@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERj@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERm@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERs@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERt@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERx@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERy@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5seekpESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5tellpEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE6sentryC1ERS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE6sentryC2ERS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE6sentryD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE6sentryD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIPKvEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIbEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIdEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIeEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIlEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIxEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIyEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1ERSt14basic_iostreamIwS1_E@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2ERSt14basic_iostreamIwS1_E@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRS2_S3_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRSt8ios_baseS4_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRSt9basic_iosIwS1_ES5_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPKv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEb@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEd@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEe@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEf@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEj@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEl@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEm@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEs@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEt@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEx@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@GLIBCXX_3.4 4.1.1
+ _ZNSt13random_device14_M_init_pretr1ERKSs@GLIBCXX_3.4.18 4.8
+ _ZNSt13random_device16_M_getval_pretr1Ev@GLIBCXX_3.4.18 4.8
+ _ZNSt13random_device7_M_finiEv@GLIBCXX_3.4.18 4.8
+ _ZNSt13random_device7_M_initERKSs@GLIBCXX_3.4.18 4.8
+ _ZNSt13random_device9_M_getvalEv@GLIBCXX_3.4.18 4.8
+ _ZNSt13runtime_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14error_categoryC1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt14error_categoryC2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt14error_categoryD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt14error_categoryD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt14error_categoryD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt14numeric_limitsIDiE10has_denormE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE10is_boundedE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE10is_integerE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE11round_styleE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE12has_infinityE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIDiE12max_exponentE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE12min_exponentE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE13has_quiet_NaNE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE14is_specializedE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE14max_exponent10E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE14min_exponent10E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE15has_denorm_lossE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE15tinyness_beforeE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE17has_signaling_NaNE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE5radixE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE5trapsE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE6digitsE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE8digits10E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE8is_exactE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE9is_iec559E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE9is_moduloE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDiE9is_signedE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE10has_denormE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE10is_boundedE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE10is_integerE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE11round_styleE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE12has_infinityE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIDsE12max_exponentE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE12min_exponentE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE13has_quiet_NaNE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE14is_specializedE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE14max_exponent10E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE14min_exponent10E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE15has_denorm_lossE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE15tinyness_beforeE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE17has_signaling_NaNE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE5radixE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE5trapsE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE6digitsE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE8digits10E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE8is_exactE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE9is_iec559E@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE9is_moduloE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIDsE9is_signedE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt14numeric_limitsIaE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIaE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIaE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIbE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIbE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIcE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIcE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIdE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIdE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIeE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIfE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIfE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIhE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIhE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIiE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIiE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIjE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIjE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIlE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIlE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsImE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsImE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIsE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIsE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsItE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsItE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIwE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIwE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIxE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIxE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt14numeric_limitsIyE12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt14numeric_limitsIyE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14overflow_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt14overflow_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt14overflow_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt14overflow_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt14overflow_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14overflow_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14overflow_errorD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt15_List_node_base10_M_reverseEv@GLIBCXX_3.4.14 4.5
+ _ZNSt15_List_node_base11_M_transferEPS_S0_@GLIBCXX_3.4.14 4.5
+ _ZNSt15_List_node_base4hookEPS_@GLIBCXX_3.4 4.1.1
+ _ZNSt15_List_node_base4swapERS_S0_@GLIBCXX_3.4 4.1.1
+ _ZNSt15_List_node_base6unhookEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15_List_node_base7_M_hookEPS_@GLIBCXX_3.4.14 4.5
+ _ZNSt15_List_node_base7reverseEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15_List_node_base8transferEPS_S0_@GLIBCXX_3.4 4.1.1
+ _ZNSt15_List_node_base9_M_unhookEv@GLIBCXX_3.4.14 4.5
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE10pubseekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE4setgEPcS3_S3_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE4setpEPcS3_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5gbumpEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5pbumpEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sgetcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sputcEc@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5uflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6snextcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6stosscEv@GLIBCXX_3.4.10 4.3
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7pubsyncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7sungetcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE8in_availEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE8overflowEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE8pubimbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9pbackfailEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9showmanycEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9sputbackcEc@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEEC1ERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEEC2ERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEEaSERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE10pubseekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE4setgEPwS3_S3_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE4setpEPwS3_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5gbumpEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5pbumpEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sgetcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sputcEw@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5uflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6sbumpcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6snextcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6stosscEv@GLIBCXX_3.4.10 4.3
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7pubsyncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7sungetcEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE8in_availEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE8overflowEj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE8pubimbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9pbackfailEj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9showmanycEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9sputbackcEw@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEEC1ERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEEC2ERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEEaSERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE15_M_update_egptrEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE17_M_stringbuf_initESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE8overflowEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE9pbackfailEi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE9showmanycEv@GLIBCXX_3.4.6 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE15_M_update_egptrEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE17_M_stringbuf_initESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strERKSbIwS1_S2_E@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8overflowEj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE9pbackfailEj@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE9showmanycEv@GLIBCXX_3.4.6 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC1ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC2ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15underflow_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt15underflow_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt15underflow_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt15underflow_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt15underflow_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15underflow_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15underflow_errorD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt16__numpunct_cacheIcE8_M_cacheERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwE8_M_cacheERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16bad_array_lengthD0Ev@CXXABI_1.3.8 4.9
+ _ZNSt16bad_array_lengthD1Ev@CXXABI_1.3.8 4.9
+ _ZNSt16bad_array_lengthD2Ev@CXXABI_1.3.8 4.9
+ _ZNSt16invalid_argumentC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt16invalid_argumentC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt16invalid_argumentC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt16invalid_argumentC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt16invalid_argumentD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16invalid_argumentD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt16invalid_argumentD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt17__timepunct_cacheIcE12_S_timezonesE@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwE12_S_timezonesE@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17bad_function_callD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt17bad_function_callD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt17bad_function_callD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt17moneypunct_bynameIcLb0EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EE4intlE@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EE8_M_cacheERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EE8_M_cacheERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EE8_M_cacheERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EE8_M_cacheERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strERKSbIwS1_S2_E@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC1ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC2ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt18condition_variable10notify_allEv@GLIBCXX_3.4.11 4.4.0
+ _ZNSt18condition_variable10notify_oneEv@GLIBCXX_3.4.11 4.4.0
+ _ZNSt18condition_variable4waitERSt11unique_lockISt5mutexE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt18condition_variableC1Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt18condition_variableC2Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt18condition_variableD1Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt18condition_variableD2Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt19__codecvt_utf8_baseIDiED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDiED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDiED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDsED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDsED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDsED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIwED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIwED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIwED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEE3strERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEE3strERKSbIwS1_S2_E@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC1ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC2ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE3strERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE3strERKSbIwS1_S2_E@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEEC1ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEEC2ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIwSt11char_traitsIwESaIwEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt19istreambuf_iteratorIcSt11char_traitsIcEEppEv@GLIBCXX_3.4 4.1.1
+ _ZNSt19istreambuf_iteratorIcSt11char_traitsIcEEppEv@GLIBCXX_3.4.5 4.1.1
+ _ZNSt19istreambuf_iteratorIwSt11char_traitsIwEEppEv@GLIBCXX_3.4 4.1.1
+ _ZNSt19istreambuf_iteratorIwSt11char_traitsIwEEppEv@GLIBCXX_3.4.5 4.1.1
+ _ZNSt20__codecvt_utf16_baseIDiED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIDiED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIDiED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIDsED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIDsED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIDsED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIwED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIwED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt20__codecvt_utf16_baseIwED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt20bad_array_new_lengthD0Ev@CXXABI_1.3.8 4.9
+ _ZNSt20bad_array_new_lengthD1Ev@CXXABI_1.3.8 4.9
+ _ZNSt20bad_array_new_lengthD2Ev@CXXABI_1.3.8 4.9
+ _ZNSt21__numeric_limits_base10has_denormE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base10is_boundedE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base10is_integerE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base11round_styleE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base12has_infinityE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base12max_digits10E@GLIBCXX_3.4.14 4.5.0
+ _ZNSt21__numeric_limits_base12max_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base12min_exponentE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base13has_quiet_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base14is_specializedE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base14max_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base14min_exponent10E@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base15has_denorm_lossE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base15tinyness_beforeE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base17has_signaling_NaNE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base5radixE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base5trapsE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base6digitsE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base8digits10E@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base8is_exactE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base9is_iec559E@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base9is_moduloE@GLIBCXX_3.4 4.1.1
+ _ZNSt21__numeric_limits_base9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt22condition_variable_anyC1Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt22condition_variable_anyC2Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt22condition_variable_anyD1Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt22condition_variable_anyD2Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt25__codecvt_utf8_utf16_baseIDiED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIDiED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIDiED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIDsED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIDsED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIDsED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIwED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIwED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt25__codecvt_utf8_utf16_baseIwED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt3_V214error_categoryD0Ev@GLIBCXX_3.4.21 5
+ _ZNSt3_V214error_categoryD1Ev@GLIBCXX_3.4.21 5
+ _ZNSt3_V214error_categoryD2Ev@GLIBCXX_3.4.21 5
+ _ZNSt3_V215system_categoryEv@GLIBCXX_3.4.21 5
+ _ZNSt3_V216generic_categoryEv@GLIBCXX_3.4.21 5
+ _ZNSt3tr18__detail12__prime_listE@GLIBCXX_3.4.10 4.3
+ _ZNSt5ctypeIcE10table_sizeE@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcE13classic_tableEv@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwE19_M_initialize_ctypeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6__norm15_List_node_base10_M_reverseEv@GLIBCXX_3.4.14 4.5
+ _ZNSt6__norm15_List_node_base11_M_transferEPS0_S1_@GLIBCXX_3.4.14 4.5
+ _ZNSt6__norm15_List_node_base4hookEPS0_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt6__norm15_List_node_base4swapERS0_S1_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt6__norm15_List_node_base6unhookEv@GLIBCXX_3.4.9 4.2.1
+ _ZNSt6__norm15_List_node_base7_M_hookEPS0_@GLIBCXX_3.4.14 4.5
+ _ZNSt6__norm15_List_node_base7reverseEv@GLIBCXX_3.4.9 4.2.1
+ _ZNSt6__norm15_List_node_base8transferEPS0_S1_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt6__norm15_List_node_base9_M_unhookEv@GLIBCXX_3.4.14 4.5
+ _ZNSt6chrono3_V212steady_clock3nowEv@GLIBCXX_3.4.19 4.8.1
+ _ZNSt6chrono3_V212steady_clock9is_steadyE@GLIBCXX_3.4.19 4.8.1
+ _ZNSt6chrono3_V212system_clock3nowEv@GLIBCXX_3.4.19 4.8.1
+ _ZNSt6chrono3_V212system_clock9is_steadyE@GLIBCXX_3.4.19 4.8.1
+ _ZNSt6chrono12system_clock12is_monotonicE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt6chrono12system_clock3nowEv@GLIBCXX_3.4.11 4.4.0
+ _ZNSt6locale11_M_coalesceERKS_S1_i@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale21_S_normalize_categoryEi@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale3allE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale4noneE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale4timeE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl16_M_install_facetEPKNS_2idEPKNS_5facetE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl16_M_replace_facetEPKS0_PKNS_2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl19_M_replace_categoryEPKS0_PKPKNS_2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl21_M_replace_categoriesEPKS0_i@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5ctypeE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5facet13_S_get_c_nameEv@GLIBCXX_3.4.6 4.1.1
+ _ZNSt6locale5facet15_S_get_c_localeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5facet17_S_clone_c_localeERP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5facet18_S_create_c_localeERP15__locale_structPKcS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5facet19_S_destroy_c_localeERP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5facetD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5facetD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5facetD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale6globalERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale7classicEv@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale7collateE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale7numericE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale8messagesE@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale8monetaryE@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC1EPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC1EPNS_5_ImplE@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC1ERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC1ERKS_PKci@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC1ERKS_S1_i@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC2EPKc@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC2EPNS_5_ImplE@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC2ERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC2ERKS_PKci@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC2ERKS_S1_i@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt6localeaSERKS_@GLIBCXX_3.4 4.1.1
+ _ZNSt6thread15_M_start_threadESt10shared_ptrINS_10_Impl_baseEE@GLIBCXX_3.4.11 4.4.0
+ _ZNSt6thread15_M_start_threadESt10shared_ptrINS_10_Impl_baseEEPFvvE@GLIBCXX_3.4.21 5
+ _ZNSt6thread15_M_start_threadESt10unique_ptrINS_6_StateESt14default_deleteIS1_EEPFvvE@GLIBCXX_3.4.22 6
+ _ZNSt6thread20hardware_concurrencyEv@GLIBCXX_3.4.17 4.7
+ _ZNSt6thread4joinEv@GLIBCXX_3.4.11 4.4.0
+ _ZNSt6thread6_StateD0Ev@GLIBCXX_3.4.22 6
+ _ZNSt6thread6_StateD1Ev@GLIBCXX_3.4.22 6
+ _ZNSt6thread6_StateD2Ev@GLIBCXX_3.4.22 6
+ _ZNSt6thread6detachEv@GLIBCXX_3.4.11 4.4.0
+ _ZNSt7codecvtIDic11__mbstate_tE2idE@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIDic11__mbstate_tED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIDic11__mbstate_tED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIDic11__mbstate_tED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIDsc11__mbstate_tE2idE@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIDsc11__mbstate_tED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIDsc11__mbstate_tED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIDsc11__mbstate_tED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt7codecvtIcc11__mbstate_tE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8__detail12__prime_listE@GLIBCXX_3.4.10 4.3
+ _ZNSt8__detail15_List_node_base10_M_reverseEv@GLIBCXX_3.4.15 4.6
+ _ZNSt8__detail15_List_node_base11_M_transferEPS0_S1_@GLIBCXX_3.4.15 4.6
+ _ZNSt8__detail15_List_node_base4swapERS0_S1_@GLIBCXX_3.4.15 4.6
+ _ZNSt8__detail15_List_node_base7_M_hookEPS0_@GLIBCXX_3.4.15 4.6
+ _ZNSt8__detail15_List_node_base9_M_unhookEv@GLIBCXX_3.4.15 4.6
+ _ZNSt8bad_castD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8bad_castD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8bad_castD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base10floatfieldE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base10scientificE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base11adjustfieldE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base13_M_grow_wordsEib@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base15sync_with_stdioEb@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base17_M_call_callbacksENS_5eventE@GLIBCXX_3.4.6 4.1.1
+ _ZNSt8ios_base17register_callbackEPFvNS_5eventERS_iEi@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base20_M_dispose_callbacksEv@GLIBCXX_3.4.6 4.1.1
+ _ZNSt8ios_base2inE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3appE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3ateE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3begE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3curE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3decE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3endE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3hexE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3octE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base3outE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base4InitC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base4InitC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base4InitD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base4InitD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base4leftE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base5fixedE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base5rightE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base5truncE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base6badbitE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base6binaryE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base6eofbitE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base6skipwsE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base6xallocEv@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7_M_initEv@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7_M_moveERS_@GLIBCXX_3.4.21 5
+ _ZNSt8ios_base7_M_swapERS_@GLIBCXX_3.4.21 5
+ _ZNSt8ios_base7failbitE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7failureC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7failureC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7failureD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7failureD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7failureD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7goodbitE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7showposE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base7unitbufE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base8internalE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base8showbaseE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base9basefieldE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base9boolalphaE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base9showpointE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_base9uppercaseE@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_baseC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_baseC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_baseD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_baseD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8ios_baseD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcE22_M_initialize_numpunctEP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwE22_M_initialize_numpunctEP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9__atomic011atomic_flag12test_and_setESt12memory_order@GLIBCXX_3.4.14 4.5
+ _ZNSt9__atomic011atomic_flag5clearESt12memory_order@GLIBCXX_3.4.14 4.5
+ _ZNSt9__cxx199815_List_node_base10_M_reverseEv@GLIBCXX_3.4.14 4.5
+ _ZNSt9__cxx199815_List_node_base11_M_transferEPS0_S1_@GLIBCXX_3.4.14 4.5
+ _ZNSt9__cxx199815_List_node_base4hookEPS0_@GLIBCXX_3.4.10 4.3
+ _ZNSt9__cxx199815_List_node_base4swapERS0_S1_@GLIBCXX_3.4.10 4.3
+ _ZNSt9__cxx199815_List_node_base7_M_hookEPS0_@GLIBCXX_3.4.14 4.5
+ _ZNSt9__cxx199815_List_node_base6unhookEv@GLIBCXX_3.4.10 4.3
+ _ZNSt9__cxx199815_List_node_base7reverseEv@GLIBCXX_3.4.10 4.3
+ _ZNSt9__cxx199815_List_node_base8transferEPS0_S1_@GLIBCXX_3.4.10 4.3
+ _ZNSt9__cxx199815_List_node_base9_M_unhookEv@GLIBCXX_3.4.14 4.5
+ _ZNSt9bad_allocD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9bad_allocD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9bad_allocD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE10exceptionsESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE11_M_setstateESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE15_M_cache_localeERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE3tieEPSo@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4fillEc@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4moveEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4moveERS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE5rdbufEPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE7copyfmtERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE8setstateESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE9set_rdbufEPSt15basic_streambufIcS1_E@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIcSt11char_traitsIcEEC1EPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEEC2EPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE10exceptionsESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE11_M_setstateESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE15_M_cache_localeERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE3tieEPSt13basic_ostreamIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4fillEw@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4initEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4moveEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4moveERS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIwSt11char_traitsIwEE5clearESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE5rdbufEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE7copyfmtERKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE8setstateESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE9set_rdbufEPSt15basic_streambufIwS1_E@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9exceptionD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9exceptionD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9exceptionD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstream3strEv@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstream6freezeEb@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstreamC1EPciSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstreamC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstreamC2EPciSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstreamC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9strstreamD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9type_infoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9type_infoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt9type_infoD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNVSt9__atomic011atomic_flag12test_and_setESt12memory_order@GLIBCXX_3.4.11 4.4.0
+ _ZNVSt9__atomic011atomic_flag5clearESt12memory_order@GLIBCXX_3.4.11 4.4.0
+ _ZSt10adopt_lock@GLIBCXX_3.4.11 4.4.0
+ _ZSt10defer_lock@GLIBCXX_3.4.11 4.4.0
+ _ZSt10unexpectedv@GLIBCXX_3.4 4.1.1
+ _ZSt11__once_call@GLIBCXX_3.4.11 4.4.0
+ _ZSt11try_to_lock@GLIBCXX_3.4.11 4.4.0
+ _ZSt13get_terminatev@GLIBCXX_3.4.20 4.9
+ _ZSt13set_terminatePFvvE@GLIBCXX_3.4 4.1.1
+ _ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZSt14__convert_to_vIfEvPKcRT_RSt12_Ios_IostateRKP15__locale_struct@GLIBCXX_3.4 4.1.1
+ _ZSt14get_unexpectedv@GLIBCXX_3.4.20 4.9
+ _ZSt14set_unexpectedPFvvE@GLIBCXX_3.4 4.1.1
+ _ZSt15__once_callable@GLIBCXX_3.4.11 4.4.0
+ _ZSt15future_category@GLIBCXX_3.4.14 4.5
+ _ZSt15future_categoryv@GLIBCXX_3.4.15 4.6
+ _ZSt15get_new_handlerv@GLIBCXX_3.4.20 4.9
+ _ZSt15set_new_handlerPFvvE@GLIBCXX_3.4 4.1.1
+ _ZSt15system_categoryv@GLIBCXX_3.4.11 4.4.0
+ _ZNSt13runtime_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC1ERKS_@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC2ERKS_@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_erroraSERKS_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZSt16__throw_bad_castv@GLIBCXX_3.4 4.1.1
+ _ZSt16generic_categoryv@GLIBCXX_3.4.11 4.4.0
+ _ZSt17__throw_bad_allocv@GLIBCXX_3.4 4.1.1
+ _ZSt18_Rb_tree_decrementPKSt18_Rb_tree_node_base@GLIBCXX_3.4 4.1.1
+ _ZSt18_Rb_tree_decrementPSt18_Rb_tree_node_base@GLIBCXX_3.4 4.1.1
+ _ZSt18_Rb_tree_incrementPKSt18_Rb_tree_node_base@GLIBCXX_3.4 4.1.1
+ _ZSt18_Rb_tree_incrementPSt18_Rb_tree_node_base@GLIBCXX_3.4 4.1.1
+ _ZSt18__throw_bad_typeidv@GLIBCXX_3.4 4.1.1
+ _ZSt18uncaught_exceptionv@GLIBCXX_3.4 4.1.1
+ _ZSt19__throw_ios_failurePKc@GLIBCXX_3.4 4.1.1
+ _ZSt19__throw_logic_errorPKc@GLIBCXX_3.4 4.1.1
+ _ZSt19__throw_range_errorPKc@GLIBCXX_3.4 4.1.1
+ _ZSt19__throw_regex_errorNSt15regex_constants10error_typeE@GLIBCXX_3.4.15 4.6
+ _ZSt19uncaught_exceptionsv@GLIBCXX_3.4.22 6
+ _ZSt20_Rb_tree_black_countPKSt18_Rb_tree_node_baseS1_@GLIBCXX_3.4 4.1.1
+ _ZSt20_Rb_tree_rotate_leftPSt18_Rb_tree_node_baseRS0_@GLIBCXX_3.4 4.1.1
+ _ZSt20__throw_domain_errorPKc@GLIBCXX_3.4 4.1.1
+ _ZSt20__throw_future_errori@GLIBCXX_3.4.14 4.5
+ _ZSt20__throw_length_errorPKc@GLIBCXX_3.4 4.1.1
+ _ZSt20__throw_out_of_rangePKc@GLIBCXX_3.4 4.1.1
+ _ZSt20__throw_system_errori@GLIBCXX_3.4.11 4.4.0
+ _ZSt21_Rb_tree_rotate_rightPSt18_Rb_tree_node_baseRS0_@GLIBCXX_3.4 4.1.1
+ _ZSt21__throw_bad_exceptionv@GLIBCXX_3.4 4.1.1
+ _ZSt21__throw_runtime_errorPKc@GLIBCXX_3.4 4.1.1
+ _ZSt22__throw_overflow_errorPKc@GLIBCXX_3.4 4.1.1
+ _ZSt23__throw_underflow_errorPKc@GLIBCXX_3.4 4.1.1
+ _ZSt24__throw_invalid_argumentPKc@GLIBCXX_3.4 4.1.1
+ _ZSt24__throw_out_of_range_fmtPKcz@GLIBCXX_3.4.20 4.9
+ _ZSt25__throw_bad_function_callv@GLIBCXX_3.4.14 4.5
+ _ZSt25notify_all_at_thread_exitRSt18condition_variableSt11unique_lockISt5mutexE@GLIBCXX_3.4.21 5
+ _ZSt28_Rb_tree_rebalance_for_erasePSt18_Rb_tree_node_baseRS_@GLIBCXX_3.4 4.1.1
+ _ZSt29_Rb_tree_insert_and_rebalancebPSt18_Rb_tree_node_baseS0_RS_@GLIBCXX_3.4 4.1.1
+ _ZSt2wsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt2wsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt3cin@GLIBCXX_3.4 4.1.1
+ _ZSt4cerr@GLIBCXX_3.4 4.1.1
+ _ZSt4clog@GLIBCXX_3.4 4.1.1
+ _ZSt4cout@GLIBCXX_3.4 4.1.1
+ _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt4endsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt4endsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt4wcin@GLIBCXX_3.4 4.1.1
+ _ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt5flushIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
+ _ZSt5wcerr@GLIBCXX_3.4 4.1.1
+ _ZSt5wclog@GLIBCXX_3.4 4.1.1
+ _ZSt5wcout@GLIBCXX_3.4 4.1.1
+ _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
+ _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_ES4_@GLIBCXX_3.4 4.1.1
+ _ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
+ _ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_ES4_@GLIBCXX_3.4 4.1.1
+ _ZSt7nothrow@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt10moneypunctIcLb0EEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt10moneypunctIwLb0EEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt11__timepunctIcEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt11__timepunctIwEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt5ctypeIcEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt5ctypeIwEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7codecvtIcc11__mbstate_tEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7codecvtIwc11__mbstate_tEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7collateIcEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7collateIwEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8messagesIcEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8messagesIwEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8numpunctIcEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8numpunctIwEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetISt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9terminatev@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt10moneypunctIcLb0EEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt10moneypunctIcLb1EEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt10moneypunctIwLb0EEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt10moneypunctIwLb1EEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt11__timepunctIcEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt11__timepunctIwEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt5ctypeIcEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt5ctypeIwEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7codecvtIcc11__mbstate_tEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7codecvtIwc11__mbstate_tEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7collateIcEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7collateIwEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8messagesIcEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8messagesIwEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8numpunctIcEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8numpunctIwEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetISt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
+ _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKa@GLIBCXX_3.4 4.1.1
+ _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@GLIBCXX_3.4 4.1.1
+ _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKh@GLIBCXX_3.4 4.1.1
+ _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_a@GLIBCXX_3.4 4.1.1
+ _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@GLIBCXX_3.4 4.1.1
+ _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_h@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St12_Setiosflags@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St13_Setprecision@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St14_Resetiosflags@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St5_Setw@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIdcSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIdwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIecSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIewSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIfcSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIfwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_S3_@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St12_Setiosflags@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St13_Setprecision@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St14_Resetiosflags@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St5_Setw@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_c@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwESaIwEERSt13basic_ostreamIT_T0_ES7_RKSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
+ _ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_@GLIBCXX_3.4 4.1.1
+ _ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_@GLIBCXX_3.4 4.1.1
+ _ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ES3_RKS6_@GLIBCXX_3.4 4.1.1
+ _ZStplIwSt11char_traitsIwESaIwEESbIT_T0_T1_EPKS3_RKS6_@GLIBCXX_3.4 4.1.1
+ _ZStplIwSt11char_traitsIwESaIwEESbIT_T0_T1_ERKS6_S8_@GLIBCXX_3.4 4.1.1
+ _ZStplIwSt11char_traitsIwESaIwEESbIT_T0_T1_ES3_RKS6_@GLIBCXX_3.4 4.1.1
+ _ZStrsISt11char_traitsIcEERSt13basic_istreamIcT_ES5_Pa@GLIBCXX_3.4 4.1.1
+ _ZStrsISt11char_traitsIcEERSt13basic_istreamIcT_ES5_Ph@GLIBCXX_3.4 4.1.1
+ _ZStrsISt11char_traitsIcEERSt13basic_istreamIcT_ES5_Ra@GLIBCXX_3.4 4.1.1
+ _ZStrsISt11char_traitsIcEERSt13basic_istreamIcT_ES5_Rh@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_RS3_@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St12_Setiosflags@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St13_Setprecision@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St14_Resetiosflags@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St5_Setw@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIdcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIdwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIecSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIewSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIfcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIfwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_PS3_@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_RS3_@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St12_Setiosflags@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St13_Setprecision@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St14_Resetiosflags@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St5_Setw@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
+ _ZTIDd@CXXABI_1.3.4 4.5
+ _ZTIDe@CXXABI_1.3.4 4.5
+ _ZTIDf@CXXABI_1.3.4 4.5
+ _ZTIDi@CXXABI_1.3.3 4.4.0
+ _ZTIDn@CXXABI_1.3.5 4.6
+ _ZTIDs@CXXABI_1.3.3 4.4.0
+ _ZTIN10__cxxabiv115__forced_unwindE@CXXABI_1.3.2 4.3
+ _ZTIN10__cxxabiv116__enum_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv117__array_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv117__class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv117__pbase_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv119__foreign_exceptionE@CXXABI_1.3.2 4.3
+ _ZTIN10__cxxabiv119__pointer_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv120__function_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv120__si_class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv121__vmi_class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv123__fundamental_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN10__cxxabiv129__pointer_to_member_type_infoE@CXXABI_1.3 4.1.1
+ _ZTIN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTIN9__gnu_cxx13stdio_filebufIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTIN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTIN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTINSt3_V214error_categoryE@GLIBCXX_3.4.21 5
+ _ZTINSt6locale5facetE@GLIBCXX_3.4 4.1.1
+ _ZTINSt6thread6_StateE@GLIBCXX_3.4.22 6
+ _ZTINSt8ios_base7failureE@GLIBCXX_3.4 4.1.1
+ _ZTIPDd@CXXABI_1.3.4 4.5
+ _ZTIPDe@CXXABI_1.3.4 4.5
+ _ZTIPDf@CXXABI_1.3.4 4.5
+ _ZTIPDi@CXXABI_1.3.3 4.4.0
+ _ZTIPDn@CXXABI_1.3.5 4.6
+ _ZTIPDs@CXXABI_1.3.3 4.4.0
+ _ZTIPKDd@CXXABI_1.3.4 4.5
+ _ZTIPKDe@CXXABI_1.3.4 4.5
+ _ZTIPKDf@CXXABI_1.3.4 4.5
+ _ZTIPKDi@CXXABI_1.3.3 4.4.0
+ _ZTIPKDn@CXXABI_1.3.5 4.6
+ _ZTIPKDs@CXXABI_1.3.3 4.4.0
+ _ZTIPKa@CXXABI_1.3 4.1.1
+ _ZTIPKb@CXXABI_1.3 4.1.1
+ _ZTIPKc@CXXABI_1.3 4.1.1
+ _ZTIPKd@CXXABI_1.3 4.1.1
+ _ZTIPKe@CXXABI_1.3 4.1.1
+ _ZTIPKf@CXXABI_1.3 4.1.1
+ _ZTIPKh@CXXABI_1.3 4.1.1
+ _ZTIPKi@CXXABI_1.3 4.1.1
+ _ZTIPKj@CXXABI_1.3 4.1.1
+ _ZTIPKl@CXXABI_1.3 4.1.1
+ _ZTIPKm@CXXABI_1.3 4.1.1
+ _ZTIPKs@CXXABI_1.3 4.1.1
+ _ZTIPKt@CXXABI_1.3 4.1.1
+ _ZTIPKv@CXXABI_1.3 4.1.1
+ _ZTIPKw@CXXABI_1.3 4.1.1
+ _ZTIPKx@CXXABI_1.3 4.1.1
+ _ZTIPKy@CXXABI_1.3 4.1.1
+ _ZTIPa@CXXABI_1.3 4.1.1
+ _ZTIPb@CXXABI_1.3 4.1.1
+ _ZTIPc@CXXABI_1.3 4.1.1
+ _ZTIPd@CXXABI_1.3 4.1.1
+ _ZTIPe@CXXABI_1.3 4.1.1
+ _ZTIPf@CXXABI_1.3 4.1.1
+ _ZTIPh@CXXABI_1.3 4.1.1
+ _ZTIPi@CXXABI_1.3 4.1.1
+ _ZTIPj@CXXABI_1.3 4.1.1
+ _ZTIPl@CXXABI_1.3 4.1.1
+ _ZTIPm@CXXABI_1.3 4.1.1
+ _ZTIPs@CXXABI_1.3 4.1.1
+ _ZTIPt@CXXABI_1.3 4.1.1
+ _ZTIPv@CXXABI_1.3 4.1.1
+ _ZTIPw@CXXABI_1.3 4.1.1
+ _ZTIPx@CXXABI_1.3 4.1.1
+ _ZTIPy@CXXABI_1.3 4.1.1
+ _ZTISd@GLIBCXX_3.4 4.1.1
+ _ZTISi@GLIBCXX_3.4 4.1.1
+ _ZTISo@GLIBCXX_3.4 4.1.1
+ _ZTISt10bad_typeid@GLIBCXX_3.4 4.1.1
+ _ZTISt10ctype_base@GLIBCXX_3.4 4.1.1
+ _ZTISt10istrstream@GLIBCXX_3.4 4.1.1
+ _ZTISt10lock_error@GLIBCXX_3.4.11 4.4.0
+ _ZTISt10money_base@GLIBCXX_3.4 4.1.1
+ _ZTISt10moneypunctIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTISt10moneypunctIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTISt10moneypunctIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTISt10moneypunctIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTISt10ostrstream@GLIBCXX_3.4 4.1.1
+ _ZTISt11__timepunctIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt11__timepunctIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt11logic_error@GLIBCXX_3.4 4.1.1
+ _ZTISt11range_error@GLIBCXX_3.4 4.1.1
+ _ZTISt11regex_error@GLIBCXX_3.4.15 4.6
+ _ZTISt12bad_weak_ptr@GLIBCXX_3.4.15 4.6
+ _ZTISt12codecvt_base@GLIBCXX_3.4 4.1.1
+ _ZTISt12ctype_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt12ctype_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt12domain_error@GLIBCXX_3.4 4.1.1
+ _ZTISt12future_error@GLIBCXX_3.4.14 4.5
+ _ZTISt12length_error@GLIBCXX_3.4 4.1.1
+ _ZTISt12out_of_range@GLIBCXX_3.4 4.1.1
+ _ZTISt12strstreambuf@GLIBCXX_3.4 4.1.1
+ _ZTISt12system_error@GLIBCXX_3.4.11 4.4.0
+ _ZTISt13bad_exception@GLIBCXX_3.4 4.1.1
+ _ZTISt13basic_filebufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt13basic_filebufIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt13basic_fstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt13basic_fstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt13basic_istreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt13basic_ostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt13messages_base@GLIBCXX_3.4 4.1.1
+ _ZTISt13runtime_error@GLIBCXX_3.4 4.1.1
+ _ZTISt14basic_ifstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt14basic_ifstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt14basic_iostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt14basic_ofstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt14basic_ofstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt14codecvt_bynameIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTISt14codecvt_bynameIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTISt14collate_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt14collate_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt14error_category@GLIBCXX_3.4.11 4.4.0
+ _ZTISt14overflow_error@GLIBCXX_3.4 4.1.1
+ _ZTISt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15basic_streambufIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15basic_stringbufIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15basic_stringbufIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15messages_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt15messages_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt15numpunct_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt15numpunct_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt15underflow_error@GLIBCXX_3.4 4.1.1
+ _ZTISt16bad_array_length@CXXABI_1.3.8 4.9
+ _ZTISt16invalid_argument@GLIBCXX_3.4 4.1.1
+ _ZTISt17bad_function_call@GLIBCXX_3.4.15 4.6
+ _ZTISt17moneypunct_bynameIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTISt17moneypunct_bynameIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTISt17moneypunct_bynameIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTISt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTISt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt19__codecvt_utf8_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTISt19__codecvt_utf8_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTISt19__codecvt_utf8_baseIwE@GLIBCXX_3.4.21 5
+ _ZTISt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt20__codecvt_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTISt20__codecvt_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTISt20__codecvt_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTISt20bad_array_new_length@CXXABI_1.3.8 4.9
+ _ZTISt21__ctype_abstract_baseIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt21__ctype_abstract_baseIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt23__codecvt_abstract_baseIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTISt23__codecvt_abstract_baseIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTISt25__codecvt_utf8_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTISt25__codecvt_utf8_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTISt25__codecvt_utf8_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTISt5ctypeIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt5ctypeIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt7codecvtIDic11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTISt7codecvtIDsc11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTISt7codecvtIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTISt7codecvtIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTISt7collateIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt7collateIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt8bad_cast@GLIBCXX_3.4 4.1.1
+ _ZTISt8ios_base@GLIBCXX_3.4 4.1.1
+ _ZTISt8messagesIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt8messagesIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt8numpunctIcE@GLIBCXX_3.4 4.1.1
+ _ZTISt8numpunctIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt9bad_alloc@GLIBCXX_3.4 4.1.1
+ _ZTISt9basic_iosIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTISt9basic_iosIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt9exception@GLIBCXX_3.4 4.1.1
+ _ZTISt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTISt9strstream@GLIBCXX_3.4 4.1.1
+ _ZTISt9time_base@GLIBCXX_3.4 4.1.1
+ _ZTISt9type_info@GLIBCXX_3.4 4.1.1
+ _ZTIa@CXXABI_1.3 4.1.1
+ _ZTIb@CXXABI_1.3 4.1.1
+ _ZTIc@CXXABI_1.3 4.1.1
+ _ZTId@CXXABI_1.3 4.1.1
+ _ZTIe@CXXABI_1.3 4.1.1
+ _ZTIf@CXXABI_1.3 4.1.1
+ _ZTIh@CXXABI_1.3 4.1.1
+ _ZTIi@CXXABI_1.3 4.1.1
+ _ZTIj@CXXABI_1.3 4.1.1
+ _ZTIl@CXXABI_1.3 4.1.1
+ _ZTIm@CXXABI_1.3 4.1.1
+ _ZTIs@CXXABI_1.3 4.1.1
+ _ZTIt@CXXABI_1.3 4.1.1
+ _ZTIv@CXXABI_1.3 4.1.1
+ _ZTIw@CXXABI_1.3 4.1.1
+ _ZTIx@CXXABI_1.3 4.1.1
+ _ZTIy@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv116__enum_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv117__array_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv117__class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv117__pbase_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv119__pointer_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv120__function_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv120__si_class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv121__vmi_class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv123__fundamental_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN10__cxxabiv129__pointer_to_member_type_infoE@CXXABI_1.3 4.1.1
+ _ZTSN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSN9__gnu_cxx13stdio_filebufIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSNSt6locale5facetE@GLIBCXX_3.4 4.1.1
+ _ZTSNSt6thread6_StateE@GLIBCXX_3.4.22 6
+ _ZTSNSt8ios_base7failureE@GLIBCXX_3.4 4.1.1
+ _ZTSPKa@CXXABI_1.3 4.1.1
+ _ZTSPKb@CXXABI_1.3 4.1.1
+ _ZTSPKc@CXXABI_1.3 4.1.1
+ _ZTSPKd@CXXABI_1.3 4.1.1
+ _ZTSPKe@CXXABI_1.3 4.1.1
+ _ZTSPKf@CXXABI_1.3 4.1.1
+ _ZTSPKh@CXXABI_1.3 4.1.1
+ _ZTSPKi@CXXABI_1.3 4.1.1
+ _ZTSPKj@CXXABI_1.3 4.1.1
+ _ZTSPKl@CXXABI_1.3 4.1.1
+ _ZTSPKm@CXXABI_1.3 4.1.1
+ _ZTSPKs@CXXABI_1.3 4.1.1
+ _ZTSPKt@CXXABI_1.3 4.1.1
+ _ZTSPKv@CXXABI_1.3 4.1.1
+ _ZTSPKw@CXXABI_1.3 4.1.1
+ _ZTSPKx@CXXABI_1.3 4.1.1
+ _ZTSPKy@CXXABI_1.3 4.1.1
+ _ZTSPa@CXXABI_1.3 4.1.1
+ _ZTSPb@CXXABI_1.3 4.1.1
+ _ZTSPc@CXXABI_1.3 4.1.1
+ _ZTSPd@CXXABI_1.3 4.1.1
+ _ZTSPe@CXXABI_1.3 4.1.1
+ _ZTSPf@CXXABI_1.3 4.1.1
+ _ZTSPh@CXXABI_1.3 4.1.1
+ _ZTSPi@CXXABI_1.3 4.1.1
+ _ZTSPj@CXXABI_1.3 4.1.1
+ _ZTSPl@CXXABI_1.3 4.1.1
+ _ZTSPm@CXXABI_1.3 4.1.1
+ _ZTSPs@CXXABI_1.3 4.1.1
+ _ZTSPt@CXXABI_1.3 4.1.1
+ _ZTSPv@CXXABI_1.3 4.1.1
+ _ZTSPw@CXXABI_1.3 4.1.1
+ _ZTSPx@CXXABI_1.3 4.1.1
+ _ZTSPy@CXXABI_1.3 4.1.1
+ _ZTSSd@GLIBCXX_3.4 4.1.1
+ _ZTSSi@GLIBCXX_3.4 4.1.1
+ _ZTSSo@GLIBCXX_3.4 4.1.1
+ _ZTSSt10bad_typeid@GLIBCXX_3.4 4.1.1
+ _ZTSSt10ctype_base@GLIBCXX_3.4 4.1.1
+ _ZTSSt10istrstream@GLIBCXX_3.4 4.1.1
+ _ZTSSt10lock_error@GLIBCXX_3.4.11 4.4.0
+ _ZTSSt10money_base@GLIBCXX_3.4 4.1.1
+ _ZTSSt10moneypunctIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt10moneypunctIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt10moneypunctIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt10moneypunctIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt10ostrstream@GLIBCXX_3.4 4.1.1
+ _ZTSSt11__timepunctIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt11__timepunctIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt11logic_error@GLIBCXX_3.4 4.1.1
+ _ZTSSt11range_error@GLIBCXX_3.4 4.1.1
+ _ZTSSt12codecvt_base@GLIBCXX_3.4 4.1.1
+ _ZTSSt12ctype_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt12ctype_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt12domain_error@GLIBCXX_3.4 4.1.1
+ _ZTSSt12future_error@GLIBCXX_3.4.14 4.5
+ _ZTSSt12length_error@GLIBCXX_3.4 4.1.1
+ _ZTSSt12out_of_range@GLIBCXX_3.4 4.1.1
+ _ZTSSt12strstreambuf@GLIBCXX_3.4 4.1.1
+ _ZTSSt12system_error@GLIBCXX_3.4.11 4.4.0
+ _ZTSSt13bad_exception@GLIBCXX_3.4 4.1.1
+ _ZTSSt13basic_filebufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt13basic_filebufIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt13basic_fstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt13basic_fstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt13basic_istreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt13basic_ostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt13messages_base@GLIBCXX_3.4 4.1.1
+ _ZTSSt13runtime_error@GLIBCXX_3.4 4.1.1
+ _ZTSSt14basic_ifstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14basic_ifstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14basic_iostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14basic_ofstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14basic_ofstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14codecvt_bynameIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14codecvt_bynameIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14collate_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14collate_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14error_category@GLIBCXX_3.4.11 4.4.0
+ _ZTSSt14overflow_error@GLIBCXX_3.4 4.1.1
+ _ZTSSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15basic_streambufIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15basic_stringbufIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15basic_stringbufIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15messages_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15messages_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15numpunct_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15numpunct_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15underflow_error@GLIBCXX_3.4 4.1.1
+ _ZTSSt16bad_array_length@CXXABI_1.3.8 4.9
+ _ZTSSt16invalid_argument@GLIBCXX_3.4 4.1.1
+ _ZTSSt17moneypunct_bynameIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt17moneypunct_bynameIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt17moneypunct_bynameIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt19__codecvt_utf8_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTSSt19__codecvt_utf8_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTSSt19__codecvt_utf8_baseIwE@GLIBCXX_3.4.21 5
+ _ZTSSt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt20__codecvt_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTSSt20__codecvt_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTSSt20__codecvt_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTSSt20bad_array_new_length@CXXABI_1.3.8 4.9
+ _ZTSSt21__ctype_abstract_baseIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt21__ctype_abstract_baseIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt23__codecvt_abstract_baseIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt23__codecvt_abstract_baseIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt25__codecvt_utf8_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTSSt25__codecvt_utf8_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTSSt25__codecvt_utf8_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTSSt5ctypeIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt5ctypeIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7codecvtIDic11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTSSt7codecvtIDsc11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTSSt7codecvtIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7codecvtIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7collateIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7collateIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8bad_cast@GLIBCXX_3.4 4.1.1
+ _ZTSSt8ios_base@GLIBCXX_3.4 4.1.1
+ _ZTSSt8messagesIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8messagesIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8numpunctIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8numpunctIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt9bad_alloc@GLIBCXX_3.4 4.1.1
+ _ZTSSt9basic_iosIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt9basic_iosIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt9exception@GLIBCXX_3.4 4.1.1
+ _ZTSSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt9strstream@GLIBCXX_3.4 4.1.1
+ _ZTSSt9time_base@GLIBCXX_3.4 4.1.1
+ _ZTSSt9type_info@GLIBCXX_3.4 4.1.1
+ _ZTSa@CXXABI_1.3 4.1.1
+ _ZTSb@CXXABI_1.3 4.1.1
+ _ZTSc@CXXABI_1.3 4.1.1
+ _ZTSd@CXXABI_1.3 4.1.1
+ _ZTSe@CXXABI_1.3 4.1.1
+ _ZTSf@CXXABI_1.3 4.1.1
+ _ZTSh@CXXABI_1.3 4.1.1
+ _ZTSi@CXXABI_1.3 4.1.1
+ _ZTSj@CXXABI_1.3 4.1.1
+ _ZTSl@CXXABI_1.3 4.1.1
+ _ZTSm@CXXABI_1.3 4.1.1
+ _ZTSs@CXXABI_1.3 4.1.1
+ _ZTSt@CXXABI_1.3 4.1.1
+ _ZTSv@CXXABI_1.3 4.1.1
+ _ZTSw@CXXABI_1.3 4.1.1
+ _ZTSx@CXXABI_1.3 4.1.1
+ _ZTSy@CXXABI_1.3 4.1.1
+ _ZTTSd@GLIBCXX_3.4 4.1.1
+ _ZTTSi@GLIBCXX_3.4 4.1.1
+ _ZTTSo@GLIBCXX_3.4 4.1.1
+ _ZTTSt10istrstream@GLIBCXX_3.4 4.1.1
+ _ZTTSt10ostrstream@GLIBCXX_3.4 4.1.1
+ _ZTTSt13basic_fstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt13basic_fstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt13basic_istreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt13basic_ostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt14basic_ifstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt14basic_ifstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt14basic_iostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt14basic_ofstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt14basic_ofstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTTSt9strstream@GLIBCXX_3.4 4.1.1
+ _ZTVN10__cxxabiv116__enum_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv117__array_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv117__class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv117__pbase_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv119__pointer_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv120__function_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv120__si_class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv121__vmi_class_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv123__fundamental_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN10__cxxabiv129__pointer_to_member_type_infoE@CXXABI_1.3 4.1.1
+ _ZTVN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVNSt3_V214error_categoryE@GLIBCXX_3.4.21 5
+ _ZTVNSt6locale5facetE@GLIBCXX_3.4 4.1.1
+ _ZTVNSt6thread6_StateE@GLIBCXX_3.4.22 6
+ _ZTVNSt8ios_base7failureE@GLIBCXX_3.4 4.1.1
+ _ZTVSd@GLIBCXX_3.4 4.1.1
+ _ZTVSi@GLIBCXX_3.4 4.1.1
+ _ZTVSo@GLIBCXX_3.4 4.1.1
+ _ZTVSt10bad_typeid@GLIBCXX_3.4 4.1.1
+ _ZTVSt10istrstream@GLIBCXX_3.4 4.1.1
+ _ZTVSt10lock_error@GLIBCXX_3.4.11 4.4.0
+ _ZTVSt10moneypunctIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt10moneypunctIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt10moneypunctIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt10moneypunctIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt10ostrstream@GLIBCXX_3.4 4.1.1
+ _ZTVSt11__timepunctIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt11__timepunctIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt11logic_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt11range_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt11regex_error@GLIBCXX_3.4.15 4.6
+ _ZTVSt12bad_weak_ptr@GLIBCXX_3.4.15 4.6
+ _ZTVSt12ctype_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt12ctype_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt12domain_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt12future_error@GLIBCXX_3.4.14 4.5
+ _ZTVSt12length_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt12out_of_range@GLIBCXX_3.4 4.1.1
+ _ZTVSt12strstreambuf@GLIBCXX_3.4 4.1.1
+ _ZTVSt12system_error@GLIBCXX_3.4.11 4.4.0
+ _ZTVSt13bad_exception@GLIBCXX_3.4 4.1.1
+ _ZTVSt13basic_filebufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt13basic_filebufIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt13basic_fstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt13basic_fstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt13basic_istreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt13basic_ostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt13runtime_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt14basic_ifstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14basic_ifstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14basic_iostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14basic_ofstreamIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14basic_ofstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14codecvt_bynameIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14codecvt_bynameIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14collate_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14collate_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt14error_category@GLIBCXX_3.4.11 4.4.0
+ _ZTVSt14overflow_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15basic_streambufIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15basic_stringbufIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15messages_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15messages_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15numpunct_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15numpunct_bynameIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15underflow_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt16bad_array_length@CXXABI_1.3.8 4.9
+ _ZTVSt16invalid_argument@GLIBCXX_3.4 4.1.1
+ _ZTVSt17bad_function_call@GLIBCXX_3.4.15 4.6
+ _ZTVSt17moneypunct_bynameIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt17moneypunct_bynameIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt17moneypunct_bynameIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19__codecvt_utf8_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt19__codecvt_utf8_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt19__codecvt_utf8_baseIwE@GLIBCXX_3.4.21 5
+ _ZTVSt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt20__codecvt_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt20__codecvt_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt20__codecvt_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTVSt20bad_array_new_length@CXXABI_1.3.8 4.9
+ _ZTVSt21__ctype_abstract_baseIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt21__ctype_abstract_baseIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt23__codecvt_abstract_baseIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt23__codecvt_abstract_baseIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt25__codecvt_utf8_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt25__codecvt_utf8_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt25__codecvt_utf8_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTVSt5ctypeIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt5ctypeIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7codecvtIDic11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTVSt7codecvtIDsc11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTVSt7codecvtIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7codecvtIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7collateIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7collateIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8bad_cast@GLIBCXX_3.4 4.1.1
+ _ZTVSt8ios_base@GLIBCXX_3.4 4.1.1
+ _ZTVSt8messagesIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8messagesIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8numpunctIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8numpunctIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9bad_alloc@GLIBCXX_3.4 4.1.1
+ _ZTVSt9basic_iosIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9basic_iosIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9exception@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9strstream@GLIBCXX_3.4 4.1.1
+ _ZTVSt9type_info@GLIBCXX_3.4 4.1.1
+ _ZdaPv@GLIBCXX_3.4 4.1.1
+ _ZdaPvRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _ZdlPv@GLIBCXX_3.4 4.1.1
+ _ZdlPvRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __atomic_flag_for_address@GLIBCXX_3.4.11 4.4.0
+ __atomic_flag_wait_explicit@GLIBCXX_3.4.11 4.4.0
+ __cxa_allocate_dependent_exception@CXXABI_1.3.6 4.7
+ __cxa_allocate_exception@CXXABI_1.3 4.1.1
+ __cxa_bad_cast@CXXABI_1.3 4.1.1
+ __cxa_bad_typeid@CXXABI_1.3 4.1.1
+ __cxa_begin_catch@CXXABI_1.3 4.1.1
+ __cxa_call_unexpected@CXXABI_1.3 4.1.1
+ __cxa_current_exception_type@CXXABI_1.3 4.1.1
+ __cxa_deleted_virtual@CXXABI_1.3.6 4.7
+ __cxa_demangle@CXXABI_1.3 4.1.1
+ __cxa_end_catch@CXXABI_1.3 4.1.1
+ __cxa_free_dependent_exception@CXXABI_1.3.6 4.7
+ __cxa_free_exception@CXXABI_1.3 4.1.1
+ __cxa_get_exception_ptr@CXXABI_1.3.1 4.1.1
+ __cxa_get_globals@CXXABI_1.3 4.1.1
+ __cxa_get_globals_fast@CXXABI_1.3 4.1.1
+ __cxa_guard_abort@CXXABI_1.3 4.1.1
+ __cxa_guard_acquire@CXXABI_1.3 4.1.1
+ __cxa_guard_release@CXXABI_1.3 4.1.1
+ __cxa_pure_virtual@CXXABI_1.3 4.1.1
+ __cxa_rethrow@CXXABI_1.3 4.1.1
+ __cxa_thread_atexit@CXXABI_1.3.7 4.8
+ __cxa_throw@CXXABI_1.3 4.1.1
+ __cxa_throw_bad_array_length@CXXABI_1.3.8 4.9
+ __cxa_throw_bad_array_new_length@CXXABI_1.3.8 4.9
+ __cxa_tm_cleanup@CXXABI_TM_1 4.7
+ __cxa_vec_cctor@CXXABI_1.3 4.1.1
+ __cxa_vec_cleanup@CXXABI_1.3 4.1.1
+ __cxa_vec_ctor@CXXABI_1.3 4.1.1
+ __cxa_vec_delete2@CXXABI_1.3 4.1.1
+ __cxa_vec_delete3@CXXABI_1.3 4.1.1
+ __cxa_vec_delete@CXXABI_1.3 4.1.1
+ __cxa_vec_dtor@CXXABI_1.3 4.1.1
+ __cxa_vec_new2@CXXABI_1.3 4.1.1
+ __cxa_vec_new3@CXXABI_1.3 4.1.1
+ __cxa_vec_new@CXXABI_1.3 4.1.1
+ __dynamic_cast@CXXABI_1.3 4.1.1
+ __once_proxy@GLIBCXX_3.4.11 4.4.0
+ atomic_flag_clear_explicit@GLIBCXX_3.4.11 4.4.0
+ atomic_flag_test_and_set_explicit@GLIBCXX_3.4.11 4.4.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.common.cxx11
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.common.cxx11
@@ -0,0 +1,880 @@
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIcLb0EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIcLb1EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIwLb0EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIwLb1EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx117collateIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx117collateIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118messagesIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118messagesIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118numpunctIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118numpunctIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt3_V214error_category10_M_messageB5cxx11Ei@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt3tr14hashINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEclES6_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt3tr14hashINSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEEEclES6_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt6locale4nameB5cxx11Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_disjunctEPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_local_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE3endEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4cendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4rendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4sizeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5beginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5c_strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5crendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5emptyEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5frontEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6cbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6lengthEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6rbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_M_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7crbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8max_sizeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE11_M_disjunctEPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE11_M_is_localEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_M_local_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE3endEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4cendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4rendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4sizeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5beginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5c_strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5crendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5emptyEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5frontEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6cbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6lengthEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6rbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7_M_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7crbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8capacityEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8max_sizeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE10_M_compareEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE10do_compareEPKcS3_S3_S3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE12do_transformEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE4hashEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE7compareEPKcS3_S3_S3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE7do_hashEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE9transformEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE10_M_compareEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE10do_compareEPKwS3_S3_S3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE12do_transformEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE4hashEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE7compareEPKwS3_S3_S3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE7do_hashEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE9transformEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE18_M_convert_to_charERKNS_12basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE20_M_convert_from_charEPc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE3getEiiiRKNS_12basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6localePKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE5closeEi@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE6do_getEiiiRKNS_12basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE7do_openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE8do_closeEi@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE18_M_convert_to_charERKNS_12basic_stringIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE20_M_convert_from_charEPc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE3getEiiiRKNS_12basic_stringIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6localePKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE5closeEi@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE6do_getEiiiRKNS_12basic_stringIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE7do_openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE8do_closeEi@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE11do_truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE12do_falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE8truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE9falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE11do_truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE12do_falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE8truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE9falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10date_orderEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13do_date_orderEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14do_get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16do_get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE21_M_extract_via_formatES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKcSD_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10date_orderEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13do_date_orderEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14do_get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16do_get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE21_M_extract_via_formatES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKwSD_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS2_IcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS2_IcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb0EEES4_S4_RSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb1EEES4_S4_RSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb0EEES4_S4_RSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb1EEES4_S4_RSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt8ios_base7failureB5cxx114whatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt11logic_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt11logic_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt11range_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt11range_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12domain_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12domain_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12length_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12length_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12out_of_rangeC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12out_of_rangeC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_filebufIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_filebufIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_fstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_fstreamIcSt11char_traitsIcEEC2ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_fstreamIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_fstreamIwSt11char_traitsIwEEC1ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13basic_fstreamIwSt11char_traitsIwEEC2ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC2ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ofstreamIwSt11char_traitsIwEEC2ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14overflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14overflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15underflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15underflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt16invalid_argumentC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt16invalid_argumentC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EE24_M_initialize_moneypunctEP15__locale_structPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC1EPcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC2EPcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIN9__gnu_cxx17__normal_iteratorIPKcS4_EEEEvT_SB_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIN9__gnu_cxx17__normal_iteratorIPcS4_EEEEvT_SA_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_local_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIPKcS4_EESA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIS5_S4_EES8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcPKcS7_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcS5_S5_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13shrink_to_fitEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE3endEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4nposE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4rendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5beginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5clearEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5eraseEN9__gnu_cxx17__normal_iteratorIPKcS4_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5eraseEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5eraseEN9__gnu_cxx17__normal_iteratorIPcS4_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5eraseEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5frontEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendESt16initializer_listIcE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignESt16initializer_listIcE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEN9__gnu_cxx17__normal_iteratorIPKcS4_EEc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEN9__gnu_cxx17__normal_iteratorIPcS4_EESt16initializer_listIcE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEN9__gnu_cxx17__normal_iteratorIPcS4_EEc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertIN9__gnu_cxx17__normal_iteratorIPcS4_EEEEvS9_T_SA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6rbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_M_dataEPc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_NS6_IPcS4_EESB_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_PcSA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_RKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_S8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_S8_S8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_S9_S9_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPKcS4_EES9_St16initializer_listIcE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_NS6_IPKcS4_EESB_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_PKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_PKcSA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_RKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_S7_S7_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7replaceEN9__gnu_cxx17__normal_iteratorIPcS4_EES8_S8_S8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8pop_backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_assignERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9push_backEc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EOS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ESt16initializer_listIcERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IN9__gnu_cxx17__normal_iteratorIPcS4_EEvEET_SA_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IPKcvEET_S8_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IPcvEET_S7_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EOS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EPKcRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ESt16initializer_listIcERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IN9__gnu_cxx17__normal_iteratorIPcS4_EEvEET_SA_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IPKcvEET_S8_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IPcvEET_S7_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSESt16initializer_listIcE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLESt16initializer_listIcE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE10_M_disposeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_Alloc_hiderC1EPwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_Alloc_hiderC2EPwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_M_constructIN9__gnu_cxx17__normal_iteratorIPKwS4_EEEEvT_SB_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_M_constructIN9__gnu_cxx17__normal_iteratorIPwS4_EEEEvT_SA_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_M_constructIPKwEEvT_S8_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12_M_constructIPwEEvT_S7_St20forward_iterator_tag@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_M_local_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwN9__gnu_cxx17__normal_iteratorIPKwS4_EESA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwN9__gnu_cxx17__normal_iteratorIS5_S4_EES8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwPKwS7_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwS5_S5_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13shrink_to_fitEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE3endEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4nposE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4rendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5beginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5clearEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5eraseEN9__gnu_cxx17__normal_iteratorIPKwS4_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5eraseEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5eraseEN9__gnu_cxx17__normal_iteratorIPwS4_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5eraseEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5frontEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendEPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6appendESt16initializer_listIwE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignEPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6assignESt16initializer_listIwE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPKwS4_EEw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS4_EESt16initializer_listIwE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS4_EEw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6insertIN9__gnu_cxx17__normal_iteratorIPwS4_EEEEvS9_T_SA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6rbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7_M_dataEPw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_NS6_IPwS4_EESB_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_PwSA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_RKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_S8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_S8_S8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_S9_S9_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPKwS4_EES9_St16initializer_listIwE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_NS6_IPKwS4_EESB_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_PKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_PKwSA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_RKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_S7_S7_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS4_EES8_S8_S8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8pop_backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9_M_assignERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE9push_backEw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1EOS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1EPKwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ERKS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ESt16initializer_listIwERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1IN9__gnu_cxx17__normal_iteratorIPwS4_EEvEET_SA_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1IPKwvEET_S8_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1IPwvEET_S7_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2EOS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2EPKwRKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ERKS4_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ESt16initializer_listIwERKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2IN9__gnu_cxx17__normal_iteratorIPwS4_EEvEET_SA_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2IPKwvEET_S8_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2IPwvEET_S7_RKS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEaSEPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEaSERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEaSESt16initializer_listIwE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEaSEw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEpLEPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEpLERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEpLESt16initializer_listIwE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEpLEw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIcED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1114collate_bynameIwED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE14__xfer_bufptrsC1ERKS4_PS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE14__xfer_bufptrsC2ERKS4_PS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE14__xfer_bufptrsD1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE14__xfer_bufptrsD2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE15_M_update_egptrEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE17_M_stringbuf_initESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE3strERKNS_12basic_stringIcS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE8overflowEi@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE9pbackfailEi@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE9showmanycEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE9underflowEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC1EOS4_ONS4_14__xfer_bufptrsE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC2EOS4_ONS4_14__xfer_bufptrsE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC2ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE14__xfer_bufptrsC1ERKS4_PS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE14__xfer_bufptrsC2ERKS4_PS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE14__xfer_bufptrsD1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE14__xfer_bufptrsD2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE15_M_update_egptrEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE17_M_stringbuf_initESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE3strERKNS_12basic_stringIwS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE7seekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE8overflowEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE9pbackfailEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE9showmanycEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE9underflowEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC1EOS4_ONS4_14__xfer_bufptrsE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC1ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC2EOS4_ONS4_14__xfer_bufptrsE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC2ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EE4intlE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE3strERKNS_12basic_stringIcS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC2ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEE3strERKNS_12basic_stringIwS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEC1ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEC2ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEE3strERKNS_12basic_stringIcS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC2ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEE3strERKNS_12basic_stringIwS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEC1ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEC2ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEE3strERKNS_12basic_stringIcS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEC2ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEE3strERKNS_12basic_stringIwS2_S3_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEE4swapERS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEC1EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEC1ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEC2EOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEC2ERKNS_12basic_stringIwS2_S3_EESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEaSEOS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcE22_M_initialize_numpunctEP15__locale_struct@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwE22_M_initialize_numpunctEP15__locale_struct@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11C1EPKcRKSt10error_code@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11C1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11C1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt10error_code@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11C2EPKcRKSt10error_code@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11C2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11C2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt10error_code@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11D0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11D1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt8ios_base7failureB5cxx11D2Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13random_device14_M_init_pretr1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt13runtime_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ifstreamIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ofstreamIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14basic_ofstreamIwSt11char_traitsIwEEC1ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt17iostream_categoryv@GLIBCXX_3.4.21 5.1.1
+ (optional=abi_c++11)_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx1110moneypunctIcLb0EEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx1110moneypunctIwLb0EEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx117collateIcEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx117collateIwEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx118messagesIcEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx118messagesIwEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx118numpunctIcEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx118numpunctIwEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9has_facetINSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx1110moneypunctIcLb0EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx1110moneypunctIcLb1EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx1110moneypunctIwLb0EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx1110moneypunctIwLb1EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx117collateIcEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx117collateIwEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx118messagesIcEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx118messagesIwEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx118numpunctIcEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx118numpunctIwEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt9use_facetINSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStlsIwSt11char_traitsIwESaIwEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_RKS8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_SA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EES5_RKS8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStplIwSt11char_traitsIwESaIwEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_RKS8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStplIwSt11char_traitsIwESaIwEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_SA_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStplIwSt11char_traitsIwESaIwEENSt7__cxx1112basic_stringIT_T0_T1_EES5_RKS8_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZStrsIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5.2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.excprop
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.excprop
@@ -0,0 +1,17 @@
+ _ZNKSt15__exception_ptr13exception_ptr20__cxa_exception_typeEv@CXXABI_1.3.3 4.4.0
+ _ZNKSt15__exception_ptr13exception_ptrcvMS0_FvvEEv@CXXABI_1.3.3 4.4.0
+ _ZNKSt15__exception_ptr13exception_ptrntEv@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptr4swapERS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC1ERKS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC1Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC2EMS0_FvvE@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC2ERKS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC2Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrD1Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrD2Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptraSERKS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptreqERKNS_13exception_ptrES2_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptrneERKNS_13exception_ptrES2_@CXXABI_1.3.3 4.4.0
+ _ZSt17current_exceptionv@CXXABI_1.3.3 4.4.0
+ _ZSt17rethrow_exceptionNSt15__exception_ptr13exception_ptrE@CXXABI_1.3.3 4.4.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.float128
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.float128
@@ -0,0 +1,7 @@
+ CXXABI_FLOAT128@CXXABI_FLOAT128 5
+ _ZTIPKg@CXXABI_FLOAT128 5
+ _ZTIPg@CXXABI_FLOAT128 5
+ _ZTIg@CXXABI_FLOAT128 5
+ _ZTSPKg@CXXABI_FLOAT128 5
+ _ZTSPg@CXXABI_FLOAT128 5
+ _ZTSg@CXXABI_FLOAT128 5
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.glibcxxmath
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.glibcxxmath
@@ -0,0 +1,22 @@
+ acosl@GLIBCXX_3.4.3 4.1.1
+ asinl@GLIBCXX_3.4.3 4.1.1
+ atan2l@GLIBCXX_3.4 4.1.1
+ atanl@GLIBCXX_3.4.3 4.1.1
+ ceill@GLIBCXX_3.4.3 4.1.1
+ coshl@GLIBCXX_3.4 4.1.1
+ cosl@GLIBCXX_3.4 4.1.1
+ expl@GLIBCXX_3.4 4.1.1
+ floorl@GLIBCXX_3.4.3 4.1.1
+ fmodl@GLIBCXX_3.4.3 4.1.1
+ frexpl@GLIBCXX_3.4.3 4.1.1
+ hypotl@GLIBCXX_3.4 4.1.1
+ ldexpl@GLIBCXX_3.4.3 4.1.1
+ log10l@GLIBCXX_3.4 4.1.1
+ logl@GLIBCXX_3.4 4.1.1
+ modfl@GLIBCXX_3.4.3 4.1.1
+ powl@GLIBCXX_3.4 4.1.1
+ sinhl@GLIBCXX_3.4 4.1.1
+ sinl@GLIBCXX_3.4 4.1.1
+ sqrtl@GLIBCXX_3.4 4.1.1
+ tanhl@GLIBCXX_3.4 4.1.1
+ tanl@GLIBCXX_3.4 4.1.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.hppa
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.hppa
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+# removed, see PR libstdc++/39491 __signbitl@GLIBCXX_3.4 4.2.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.hurd-i386
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.hurd-i386
@@ -0,0 +1,6 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit.hurd"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.i386
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.i386
@@ -0,0 +1,14 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.ia64
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.ia64
@@ -0,0 +1,53 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNSt14numeric_limitsInE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_signedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_signedE@GLIBCXX_3.4.17 4.8
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.kfreebsd-amd64
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.kfreebsd-amd64
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.kfreebsd-i386
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.kfreebsd-i386
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.ldbl.32bit
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.ldbl.32bit
@@ -0,0 +1,284 @@
+ CXXABI_LDBL_1.3@CXXABI_LDBL_1.3 4.2.1
+ GLIBCXX_LDBL_3.4.10@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ GLIBCXX_LDBL_3.4.7@GLIBCXX_LDBL_3.4.7 4.2.1
+ GLIBCXX_LDBL_3.4@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt3tr14hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcjcRSt8ios_basePcSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIlEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intImEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIxEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIyEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcjcS7_PcS8_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES4_S4_RSt8ios_baseccT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIgEES4_S4_RSt8ios_baseccT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE8__do_putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcjwRSt8ios_basePwSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIlEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intImEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIxEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIyEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcjwPKwPwSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIdEES4_S4_RSt8ios_basewcT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIgEES4_S4_RSt8ios_basewcT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE8__do_putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8__do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE8__do_putES4_bRSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb0EEES4_S4_RSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb1EEES4_S4_RSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE8__do_putES4_bRSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb0EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb1EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSi10_M_extractIgEERSiRT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSirsERg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSo9_M_insertIgEERSoT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSolsEg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIgEERS2_RT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIgEERS2_T_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10has_denormE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10is_boundedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10is_integerE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE11round_styleE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12has_infinityE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12max_digits10E@GLIBCXX_LDBL_3.4 4.5.0
+ _ZNSt14numeric_limitsIgE12max_exponentE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12min_exponentE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE13has_quiet_NaNE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14is_specializedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14max_exponent10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14min_exponent10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE15has_denorm_lossE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE15tinyness_beforeE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE17has_signaling_NaNE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE5radixE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE5trapsE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE6digitsE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE8digits10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE8is_exactE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_iec559E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_moduloE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_signedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt14__convert_to_vIgEvPKcRT_RSt12_Ios_IostateRKP15__locale_struct@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgcSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTIPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSg@CXXABI_LDBL_1.3 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.ldbl.32bit.s390
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.ldbl.32bit.s390
@@ -0,0 +1,284 @@
+ CXXABI_LDBL_1.3@CXXABI_LDBL_1.3 4.2.1
+ GLIBCXX_LDBL_3.4.10@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ GLIBCXX_LDBL_3.4.7@GLIBCXX_LDBL_3.4.7 4.2.1
+ GLIBCXX_LDBL_3.4@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt3tr14hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIlEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intImEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIxEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIyEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS7_PcS8_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES4_S4_RSt8ios_baseccT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIgEES4_S4_RSt8ios_baseccT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE8__do_putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIlEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intImEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIxEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIyEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIdEES4_S4_RSt8ios_basewcT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIgEES4_S4_RSt8ios_basewcT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE8__do_putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8__do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE8__do_putES4_bRSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb0EEES4_S4_RSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb1EEES4_S4_RSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE8__do_putES4_bRSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb0EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb1EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSi10_M_extractIgEERSiRT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSirsERg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSo9_M_insertIgEERSoT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSolsEg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIgEERS2_RT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIgEERS2_T_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10has_denormE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10is_boundedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10is_integerE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE11round_styleE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12has_infinityE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12max_digits10E@GLIBCXX_LDBL_3.4 4.5.0
+ _ZNSt14numeric_limitsIgE12max_exponentE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12min_exponentE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE13has_quiet_NaNE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14is_specializedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14max_exponent10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14min_exponent10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE15has_denorm_lossE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE15tinyness_beforeE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE17has_signaling_NaNE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE5radixE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE5trapsE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE6digitsE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE8digits10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE8is_exactE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_iec559E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_moduloE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_signedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt14__convert_to_vIgEvPKcRT_RSt12_Ios_IostateRKP15__locale_struct@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgcSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTIPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSg@CXXABI_LDBL_1.3 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.ldbl.64bit
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.ldbl.64bit
@@ -0,0 +1,284 @@
+ CXXABI_LDBL_1.3@CXXABI_LDBL_1.3 4.2.1
+ GLIBCXX_LDBL_3.4.10@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ GLIBCXX_LDBL_3.4.7@GLIBCXX_LDBL_3.4.7 4.2.1
+ GLIBCXX_LDBL_3.4@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt3tr14hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIlEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intImEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIxEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE13_M_insert_intIyEES4_S4_RSt8ios_basecT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS7_PcS8_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES4_S4_RSt8ios_baseccT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIgEES4_S4_RSt8ios_baseccT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_RSt8ios_basecy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEclRSt8ios_basePcPKcRi@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_RSt8ios_basecy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE8__do_putES4_RSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIlEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intImEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIxEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE13_M_insert_intIyEES4_S4_RSt8ios_basewT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwSA_Ri@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIdEES4_S4_RSt8ios_basewcT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE15_M_insert_floatIgEES4_S4_RSt8ios_basewcT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_RSt8ios_basewy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwlRSt8ios_basePwPKwRi@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewPKv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_RSt8ios_basewy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE8__do_putES4_RSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8__do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE8__do_putES4_bRSt8ios_basecd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb0EEES4_S4_RSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb1EEES4_S4_RSt8ios_basecRKSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE8__do_putES4_bRSt8ios_basewd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb0EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb1EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSi10_M_extractIgEERSiRT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSirsERg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSo9_M_insertIgEERSoT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSolsEg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIgEERS2_RT_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsERg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIgEERS2_T_@GLIBCXX_LDBL_3.4.7 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10has_denormE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10is_boundedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE10is_integerE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE11round_styleE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12has_infinityE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12max_digits10E@GLIBCXX_LDBL_3.4 4.5.0
+ _ZNSt14numeric_limitsIgE12max_exponentE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE12min_exponentE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE13has_quiet_NaNE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14is_specializedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14max_exponent10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE14min_exponent10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE15has_denorm_lossE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE15tinyness_beforeE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE17has_signaling_NaNE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE5radixE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE5trapsE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE6digitsE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE8digits10E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE8is_exactE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_iec559E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_moduloE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt14numeric_limitsIgE9is_signedE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt14__convert_to_vIgEvPKcRT_RSt12_Ios_IostateRKP15__locale_struct@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgcSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTIPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSg@CXXABI_LDBL_1.3 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.m68k
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.m68k
@@ -0,0 +1,6 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.mips
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.mips
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.mips64
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.mips64
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.mips64el
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.mips64el
@@ -0,0 +1,10 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.9.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.9.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.mipsel
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.mipsel
@@ -0,0 +1,8 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.money.f128
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.money.f128
@@ -0,0 +1,10 @@
+  GLIBCXX_LDBL_3.4.21@GLIBCXX_LDBL_3.4.21 5
+# cxx11 symbols only
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewg@GLIBCXX_3.4.21 5.2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.money.ldbl
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.money.ldbl
@@ -0,0 +1,9 @@
+# cxx11 symbols only
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basece@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basece@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewe@GLIBCXX_3.4.21 5.2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.not-armel
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.not-armel
@@ -0,0 +1,24 @@
+ _ZNSt13__future_base11_State_baseD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base11_State_baseD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base11_State_baseD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseC1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseC2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base13_State_baseV211_Make_ready6_M_setEv@GLIBCXX_3.4.21 5
+ _ZNSt13__future_base19_Async_state_commonD0Ev@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZNSt13__future_base19_Async_state_commonD1Ev@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZNSt13__future_base19_Async_state_commonD2Ev@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZNSt16nested_exceptionD0Ev@CXXABI_1.3.5 4.6
+ _ZNSt16nested_exceptionD1Ev@CXXABI_1.3.5 4.6
+ _ZNSt16nested_exceptionD2Ev@CXXABI_1.3.5 4.6
+ _ZTINSt13__future_base11_State_baseE@GLIBCXX_3.4.15 4.6
+ _ZTINSt13__future_base12_Result_baseE@GLIBCXX_3.4.15 4.6
+ _ZTINSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTISt16nested_exception@CXXABI_1.3.5 4.6
+ _ZTSNSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTVNSt13__future_base11_State_baseE@GLIBCXX_3.4.15 4.6
+ _ZTVNSt13__future_base12_Result_baseE@GLIBCXX_3.4.15 4.6
+ _ZTVNSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTVSt16nested_exception@CXXABI_1.3.5 4.6
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.powerpc
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.powerpc
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.powerpcspe
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.powerpcspe
@@ -0,0 +1,8 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.ppc64
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.ppc64
@@ -0,0 +1,11 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.ppc64el
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.ppc64el
@@ -0,0 +1,11 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.s390
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.s390
@@ -0,0 +1,558 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcmPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwmPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5.0
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5.0
+ _ZNKSt8valarrayImE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE10_S_compareEmm@GLIBCXX_3.4.16 4.7
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructEmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE14_M_replace_auxEmmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE15_M_replace_safeEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE18_S_construct_aux_2EmwRKS1_@GLIBCXX_3.4.14 4.5.0
+ _ZNSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep8_M_cloneERKS1_m@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep9_S_createEmmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEmm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwm@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_mw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEmmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7reserveEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_assignEPwmw@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE9_M_mutateEmmm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EPKwmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_mmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC1EmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EPKwmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2ERKS2_mmRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEC2EmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi3getEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi4readEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSi6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSi6ignoreEii@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPci@GLIBCXX_3.4 4.1.1
+ _ZNSi7getlineEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi8readsomeEPci@GLIBCXX_3.4 4.1.1
+ _ZNSo5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSo5writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSo8_M_writeEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSs10_S_compareEmm@GLIBCXX_3.4.16 4.7
+ _ZNSs12_S_constructEmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs14_M_replace_auxEmmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs15_M_replace_safeEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs18_S_construct_aux_2EmcRKSaIcE@GLIBCXX_3.4.14 4.5.0
+ _ZNSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs4_Rep8_M_cloneERKSaIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSs4_Rep9_S_createEmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSs5eraseEmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6appendEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6assignEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs6insertEmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEm@GLIBCXX_3.4 4.1.1
+ _ZNSs6resizeEmc@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_copyEPcPKcm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7_M_moveEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7_M_moveEPcPKcm@GLIBCXX_3.4.5 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_mc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSs7replaceEmmmc@GLIBCXX_3.4 4.1.1
+ _ZNSs7reserveEm@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcmc@GLIBCXX_3.4 4.1.1
+ _ZNSs9_M_assignEPcmc@GLIBCXX_3.4.5 4.1.1
+ _ZNSs9_M_mutateEmmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EPKcmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC1ERKSsmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC1EmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EPKcmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNSsC2ERKSsmmRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsC2EmcRKSaIcE@GLIBCXX_3.4 4.1.1
+ _ZNSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC1EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt10istrstreamC2EPci@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIcLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4 4.1.1
+ _ZNSt10moneypunctIwLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1EPSt17__timepunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2EPSt17__timepunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1EPSt17__timepunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2EPSt17__timepunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt11__timepunctIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt11this_thread11__sleep_forENSt6chrono8durationIxSt5ratioILx1ELx1EEEENS1_IxS2_ILx1ELx1000000000EEEE@GLIBCXX_3.4.18 4.8
+ _ZNSt12__basic_fileIcE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE7seekoffExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcE8xsputn_2EPKciS2_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_allocEm@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambuf8_M_setupEPcS0_i@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPFPvmEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC1Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPFPvmEPFvS0_E@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKai@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPKhi@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPaiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPciS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2EPhiS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt12strstreambufC2Ei@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE13_M_set_bufferEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE22_M_convert_to_externalEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7_M_seekExSt12_Ios_Seekdir11__mbstate_t@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4readEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEi@GLIBCXX_3.4.5 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEij@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7getlineEPwiw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE8readsomeEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5seekpExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE8_M_writeEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14collate_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_gbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE12__safe_pbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE5sputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE9pubsetbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE10pubseekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_gbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE12__safe_pbumpEi@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE5sputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE9pubsetbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPci@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE8_M_pbumpEPcS4_x@GLIBCXX_3.4.16 4.7
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwi@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS4_x@GLIBCXX_3.4.16 4.7
+ _ZNSt15messages_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt16__numpunct_cacheIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17__timepunct_cacheIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIcLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb0EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt18__moneypunct_cacheIwLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC1EPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIcEC2EPKtbm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt5ctypeIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC1EmRKSt8valarrayImES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6gslice8_IndexerC2EmRKSt8valarrayImES4_@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_Impl16_M_install_cacheEPKNS_5facetEm@GLIBCXX_3.4.7 4.1.1
+ _ZNSt6locale5_ImplC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1ERKS0_m@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2ERKS0_m@GLIBCXX_3.4 4.1.1
+ _ZNSt6locale5_ImplC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIcc11__mbstate_tEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7codecvtIwc11__mbstate_tEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt7collateIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2EP15__locale_structPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt8messagesIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIcEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4 4.1.1
+ _ZNSt8numpunctIwEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC1ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC2ERKS0_@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt8valarrayImEixEm@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZSt11_Hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt15_Fnv_hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt17__copy_streambufsIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__copy_streambufsIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__verify_groupingPKcmRKSs@GLIBCXX_3.4.10 4.3
+ _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZThn8_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _Znam@GLIBCXX_3.4 4.1.1
+ _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwm@GLIBCXX_3.4 4.1.1
+ _ZnwmRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit.s390"
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.s390x
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.s390x
@@ -0,0 +1,13 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.sh4
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.sh4
@@ -0,0 +1,8 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.sparc
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.sparc
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.sparc64
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.sparc64
@@ -0,0 +1,11 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1
+# FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc.
+# #include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.3.0.orig/debian/libstdc++6.symbols.x32
+++ gcc-6-6.3.0/debian/libstdc++6.symbols.x32
@@ -0,0 +1,27 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
+ _ZTIPKn@CXXABI_1.3.5 4.9.0
+ _ZTIPKo@CXXABI_1.3.5 4.9.0
+ _ZTIPn@CXXABI_1.3.5 4.9.0
+ _ZTIPo@CXXABI_1.3.5 4.9.0
+ _ZTIn@CXXABI_1.3.5 4.9.0
+ _ZTIo@CXXABI_1.3.5 4.9.0
+ _ZTSPKn@CXXABI_1.3.9 4.9.0
+ _ZTSPKo@CXXABI_1.3.9 4.9.0
+ _ZTSPn@CXXABI_1.3.9 4.9.0
+ _ZTSPo@CXXABI_1.3.9 4.9.0
+ _ZTSn@CXXABI_1.3.9 4.9.0
+ _ZTSo@CXXABI_1.3.9 4.9.0
--- gcc-6-6.3.0.orig/debian/libstdc++CXX.postinst
+++ gcc-6-6.3.0/debian/libstdc++CXX.postinst
@@ -0,0 +1,18 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libstdc++@CXX@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+
+	if [ -n "$2" ] && [ -d /usr/share/gcc-4.9 ] && dpkg --compare-versions "$2" lt 5.1.1-10; then
+	    find /usr/share/gcc-4.9/python -name __pycache__ -type d -print0 | xargs -r0 rm -rf
+	    find /usr/share/gcc-4.9/python -name '*.py[co]' -type f -print0 | xargs -r0 rm -f
+	    find /usr/share/gcc-4.9 -empty -delete 2>/dev/null || true
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libstdc++CXX.prerm
+++ gcc-6-6.3.0/debian/libstdc++CXX.prerm
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+set -e
+
+case "$1" in
+    remove|upgrade)
+	files=$(dpkg -L libstdc++@CXX@@TARGET_QUAL@ | awk -F/ 'BEGIN {OFS="/"} /\.py$/ {$NF=sprintf("__pycache__/%s.*.py[co]", substr($NF,1,length($NF)-3)); print}')
+	rm -f $files
+	dirs=$(dpkg -L libstdc++@CXX@@TARGET_QUAL@ | awk -F/ 'BEGIN {OFS="/"} /\.py$/ {NF--; print}' | sort -u)
+	find $dirs -mindepth 1 -maxdepth 1 -name __pycache__ -type d -empty | xargs -r rmdir
+esac
+
+#DEBHELPER#
--- gcc-6-6.3.0.orig/debian/libtsan0.symbols
+++ gcc-6-6.3.0/debian/libtsan0.symbols
@@ -0,0 +1,1758 @@
+libtsan.so.0 libtsan0 #MINVER#
+ AnnotateBenignRace@Base 4.9
+ AnnotateBenignRaceSized@Base 4.9
+ AnnotateCondVarSignal@Base 4.9
+ AnnotateCondVarSignalAll@Base 4.9
+ AnnotateCondVarWait@Base 4.9
+ AnnotateEnableRaceDetection@Base 4.9
+ AnnotateExpectRace@Base 4.9
+ AnnotateFlushExpectedRaces@Base 4.9
+ AnnotateFlushState@Base 4.9
+ AnnotateHappensAfter@Base 4.9
+ AnnotateHappensBefore@Base 4.9
+ AnnotateIgnoreReadsBegin@Base 4.9
+ AnnotateIgnoreReadsEnd@Base 4.9
+ AnnotateIgnoreSyncBegin@Base 4.9
+ AnnotateIgnoreSyncEnd@Base 4.9
+ AnnotateIgnoreWritesBegin@Base 4.9
+ AnnotateIgnoreWritesEnd@Base 4.9
+ AnnotateMemoryIsInitialized@Base 4.9
+ AnnotateMemoryIsUninitialized@Base 5
+ AnnotateMutexIsNotPHB@Base 4.9
+ AnnotateMutexIsUsedAsCondVar@Base 4.9
+ AnnotateNewMemory@Base 4.9
+ AnnotateNoOp@Base 4.9
+ AnnotatePCQCreate@Base 4.9
+ AnnotatePCQDestroy@Base 4.9
+ AnnotatePCQGet@Base 4.9
+ AnnotatePCQPut@Base 4.9
+ AnnotatePublishMemoryRange@Base 4.9
+ AnnotateRWLockAcquired@Base 4.9
+ AnnotateRWLockCreate@Base 4.9
+ AnnotateRWLockCreateStatic@Base 4.9
+ AnnotateRWLockDestroy@Base 4.9
+ AnnotateRWLockReleased@Base 4.9
+ AnnotateThreadName@Base 4.9
+ AnnotateTraceMemory@Base 4.9
+ AnnotateUnpublishMemoryRange@Base 4.9
+ RunningOnValgrind@Base 4.9
+ ThreadSanitizerQuery@Base 4.9
+ ValgrindSlowdown@Base 4.9
+ WTFAnnotateBenignRaceSized@Base 4.9
+ WTFAnnotateHappensAfter@Base 4.9
+ WTFAnnotateHappensBefore@Base 4.9
+ _ZN11__sanitizer11CheckFailedEPKciS1_yy@Base 4.9
+ _ZN11__sanitizer7OnPrintEPKc@Base 4.9
+ _ZN6__tsan10OnFinalizeEb@Base 4.9
+ _ZN6__tsan12OnInitializeEv@Base 5
+ _ZN6__tsan8OnReportEPKNS_10ReportDescEb@Base 4.9
+ _ZdaPv@Base 4.9
+ _ZdaPvRKSt9nothrow_t@Base 4.9
+ _ZdlPv@Base 4.9
+ _ZdlPvRKSt9nothrow_t@Base 4.9
+ _Znam@Base 4.9
+ _ZnamRKSt9nothrow_t@Base 4.9
+ _Znwm@Base 4.9
+ _ZnwmRKSt9nothrow_t@Base 4.9
+ __asan_backtrace_alloc@Base 4.9
+ __asan_backtrace_close@Base 4.9
+ __asan_backtrace_create_state@Base 4.9
+ __asan_backtrace_dwarf_add@Base 4.9
+ __asan_backtrace_free@Base 4.9
+ __asan_backtrace_get_view@Base 4.9
+ __asan_backtrace_initialize@Base 4.9
+ __asan_backtrace_open@Base 4.9
+ __asan_backtrace_pcinfo@Base 4.9
+ __asan_backtrace_qsort@Base 4.9
+ __asan_backtrace_release_view@Base 4.9
+ __asan_backtrace_syminfo@Base 4.9
+ __asan_backtrace_vector_finish@Base 4.9
+ __asan_backtrace_vector_grow@Base 4.9
+ __asan_backtrace_vector_release@Base 4.9
+ __asan_cplus_demangle_builtin_types@Base 4.9
+ __asan_cplus_demangle_fill_ctor@Base 4.9
+ __asan_cplus_demangle_fill_dtor@Base 4.9
+ __asan_cplus_demangle_fill_extended_operator@Base 4.9
+ __asan_cplus_demangle_fill_name@Base 4.9
+ __asan_cplus_demangle_init_info@Base 4.9
+ __asan_cplus_demangle_mangled_name@Base 4.9
+ __asan_cplus_demangle_operators@Base 4.9
+ __asan_cplus_demangle_print@Base 4.9
+ __asan_cplus_demangle_print_callback@Base 4.9
+ __asan_cplus_demangle_type@Base 4.9
+ __asan_cplus_demangle_v3@Base 4.9
+ __asan_cplus_demangle_v3_callback@Base 4.9
+ __asan_internal_memcmp@Base 4.9
+ __asan_internal_memcpy@Base 4.9
+ __asan_internal_memset@Base 4.9
+ __asan_internal_strcmp@Base 4.9
+ __asan_internal_strlen@Base 4.9
+ __asan_internal_strncmp@Base 4.9
+ __asan_internal_strnlen@Base 4.9
+ __asan_is_gnu_v3_mangled_ctor@Base 4.9
+ __asan_is_gnu_v3_mangled_dtor@Base 4.9
+ __asan_java_demangle_v3@Base 4.9
+ __asan_java_demangle_v3_callback@Base 4.9
+ __close@Base 4.9
+ __cxa_atexit@Base 4.9
+ __cxa_guard_abort@Base 4.9
+ __cxa_guard_acquire@Base 4.9
+ __cxa_guard_release@Base 4.9
+ __fxstat64@Base 4.9
+ __fxstat@Base 4.9
+ __getdelim@Base 5
+ __interceptor___close@Base 4.9
+ __interceptor___cxa_atexit@Base 4.9
+ __interceptor___fxstat64@Base 4.9
+ __interceptor___fxstat@Base 4.9
+ __interceptor___getdelim@Base 5
+ __interceptor___isoc99_fprintf@Base 5
+ __interceptor___isoc99_fscanf@Base 4.9
+ __interceptor___isoc99_printf@Base 5
+ __interceptor___isoc99_scanf@Base 4.9
+ __interceptor___isoc99_snprintf@Base 5
+ __interceptor___isoc99_sprintf@Base 5
+ __interceptor___isoc99_sscanf@Base 4.9
+ __interceptor___isoc99_vfprintf@Base 5
+ __interceptor___isoc99_vfscanf@Base 4.9
+ __interceptor___isoc99_vprintf@Base 5
+ __interceptor___isoc99_vscanf@Base 4.9
+ __interceptor___isoc99_vsnprintf@Base 5
+ __interceptor___isoc99_vsprintf@Base 5
+ __interceptor___isoc99_vsscanf@Base 4.9
+ __interceptor___libc_memalign@Base 4.9
+ __interceptor___lxstat64@Base 4.9
+ __interceptor___lxstat@Base 4.9
+ __interceptor___overflow@Base 5
+ __interceptor___res_iclose@Base 4.9
+ __interceptor___sigsetjmp@Base 4.9
+ __interceptor___tls_get_addr@Base 6
+ __interceptor___uflow@Base 5
+ __interceptor___underflow@Base 5
+ __interceptor___woverflow@Base 5
+ __interceptor___wuflow@Base 5
+ __interceptor___wunderflow@Base 5
+ __interceptor___xpg_strerror_r@Base 4.9
+ __interceptor___xstat64@Base 4.9
+ __interceptor___xstat@Base 4.9
+ __interceptor__exit@Base 4.9
+ __interceptor__obstack_begin@Base 5
+ __interceptor__obstack_begin_1@Base 5
+ __interceptor__obstack_newchunk@Base 5
+ __interceptor__setjmp@Base 4.9
+ __interceptor_abort@Base 4.9
+ __interceptor_accept4@Base 4.9
+ __interceptor_accept@Base 4.9
+ __interceptor_aligned_alloc@Base 5
+ __interceptor_asctime@Base 4.9
+ __interceptor_asctime_r@Base 4.9
+ __interceptor_asprintf@Base 5
+ __interceptor_atexit@Base 4.9
+ __interceptor_backtrace@Base 4.9
+ __interceptor_backtrace_symbols@Base 4.9
+ __interceptor_bind@Base 4.9
+ __interceptor_calloc@Base 4.9
+ __interceptor_canonicalize_file_name@Base 4.9
+ __interceptor_capget@Base 5
+ __interceptor_capset@Base 5
+ __interceptor_cfree@Base 4.9
+ __interceptor_clock_getres@Base 4.9
+ __interceptor_clock_gettime@Base 4.9
+ __interceptor_clock_settime@Base 4.9
+ __interceptor_close@Base 4.9
+ __interceptor_closedir@Base 6
+ __interceptor_confstr@Base 4.9
+ __interceptor_connect@Base 4.9
+ __interceptor_creat64@Base 4.9
+ __interceptor_creat@Base 4.9
+ __interceptor_ctime@Base 4.9
+ __interceptor_ctime_r@Base 4.9
+ __interceptor_dl_iterate_phdr@Base 6
+ __interceptor_dlclose@Base 4.9
+ __interceptor_dlopen@Base 4.9
+ __interceptor_drand48_r@Base 4.9
+ __interceptor_dup2@Base 4.9
+ __interceptor_dup3@Base 4.9
+ __interceptor_dup@Base 4.9
+ __interceptor_endgrent@Base 5
+ __interceptor_endpwent@Base 5
+ __interceptor_epoll_create1@Base 4.9
+ __interceptor_epoll_create@Base 4.9
+ __interceptor_epoll_ctl@Base 4.9
+ __interceptor_epoll_wait@Base 4.9
+ __interceptor_ether_aton@Base 4.9
+ __interceptor_ether_aton_r@Base 4.9
+ __interceptor_ether_hostton@Base 4.9
+ __interceptor_ether_line@Base 4.9
+ __interceptor_ether_ntoa@Base 4.9
+ __interceptor_ether_ntoa_r@Base 4.9
+ __interceptor_ether_ntohost@Base 4.9
+ __interceptor_eventfd@Base 4.9
+ __interceptor_fclose@Base 4.9
+ __interceptor_fdopen@Base 5
+ __interceptor_fflush@Base 4.9
+ __interceptor_fgetxattr@Base 5
+ __interceptor_flistxattr@Base 5
+ __interceptor_fmemopen@Base 5
+ __interceptor_fopen64@Base 5
+ __interceptor_fopen@Base 4.9
+ __interceptor_fopencookie@Base 6
+ __interceptor_fork@Base 4.9
+ __interceptor_fprintf@Base 5
+ __interceptor_fread@Base 4.9
+ __interceptor_free@Base 4.9
+ __interceptor_freopen64@Base 5
+ __interceptor_freopen@Base 4.9
+ __interceptor_frexp@Base 4.9
+ __interceptor_frexpf@Base 4.9
+ __interceptor_frexpl@Base 4.9
+ __interceptor_fscanf@Base 4.9
+ __interceptor_fstat64@Base 4.9
+ __interceptor_fstat@Base 4.9
+ __interceptor_fstatfs64@Base 4.9
+ __interceptor_fstatfs@Base 4.9
+ __interceptor_fstatvfs64@Base 4.9
+ __interceptor_fstatvfs@Base 4.9
+ __interceptor_ftime@Base 5
+ __interceptor_fwrite@Base 4.9
+ __interceptor_get_current_dir_name@Base 4.9
+ __interceptor_getaddrinfo@Base 4.9
+ __interceptor_getcwd@Base 4.9
+ __interceptor_getdelim@Base 4.9
+ __interceptor_getgroups@Base 4.9
+ __interceptor_gethostbyaddr@Base 4.9
+ __interceptor_gethostbyaddr_r@Base 4.9
+ __interceptor_gethostbyname2@Base 4.9
+ __interceptor_gethostbyname2_r@Base 4.9
+ __interceptor_gethostbyname@Base 4.9
+ __interceptor_gethostbyname_r@Base 4.9
+ __interceptor_gethostent@Base 4.9
+ __interceptor_gethostent_r@Base 4.9
+ __interceptor_getifaddrs@Base 5
+ __interceptor_getitimer@Base 4.9
+ __interceptor_getline@Base 4.9
+ __interceptor_getmntent@Base 4.9
+ __interceptor_getmntent_r@Base 4.9
+ __interceptor_getnameinfo@Base 5
+ __interceptor_getpass@Base 5
+ __interceptor_getpeername@Base 4.9
+ __interceptor_getresgid@Base 5
+ __interceptor_getresuid@Base 5
+ __interceptor_getsockname@Base 4.9
+ __interceptor_getsockopt@Base 4.9
+ __interceptor_gettimeofday@Base 4.9
+ __interceptor_getxattr@Base 5
+ __interceptor_glob64@Base 5
+ __interceptor_glob@Base 5
+ __interceptor_gmtime@Base 4.9
+ __interceptor_gmtime_r@Base 4.9
+ __interceptor_iconv@Base 4.9
+ __interceptor_if_indextoname@Base 5
+ __interceptor_if_nametoindex@Base 5
+ __interceptor_inet_aton@Base 4.9
+ __interceptor_inet_ntop@Base 4.9
+ __interceptor_inet_pton@Base 4.9
+ __interceptor_initgroups@Base 4.9
+ __interceptor_inotify_init1@Base 4.9
+ __interceptor_inotify_init@Base 4.9
+ __interceptor_ioctl@Base 4.9
+ __interceptor_kill@Base 4.9
+ __interceptor_lgamma@Base 4.9
+ __interceptor_lgamma_r@Base 4.9
+ __interceptor_lgammaf@Base 4.9
+ __interceptor_lgammaf_r@Base 4.9
+ __interceptor_lgammal@Base 4.9
+ __interceptor_lgammal_r@Base 4.9
+ __interceptor_lgetxattr@Base 5
+ __interceptor_listen@Base 4.9
+ __interceptor_listxattr@Base 5
+ __interceptor_llistxattr@Base 5
+ __interceptor_localtime@Base 4.9
+ __interceptor_localtime_r@Base 4.9
+ __interceptor_longjmp@Base 4.9
+ __interceptor_lrand48_r@Base 4.9
+ __interceptor_lstat64@Base 4.9
+ __interceptor_lstat@Base 4.9
+ __interceptor_malloc@Base 4.9
+ __interceptor_malloc_usable_size@Base 4.9
+ __interceptor_mbsnrtowcs@Base 4.9
+ __interceptor_mbsrtowcs@Base 4.9
+ __interceptor_mbstowcs@Base 4.9
+ __interceptor_memalign@Base 4.9
+ __interceptor_memchr@Base 4.9
+ __interceptor_memcmp@Base 4.9
+ __interceptor_memcpy@Base 4.9
+ __interceptor_memmove@Base 4.9
+ __interceptor_memrchr@Base 4.9
+ __interceptor_memset@Base 4.9
+ __interceptor_mincore@Base 6
+ __interceptor_mktime@Base 5
+ __interceptor_mlock@Base 4.9
+ __interceptor_mlockall@Base 4.9
+ __interceptor_mmap64@Base 4.9
+ __interceptor_mmap@Base 4.9
+ __interceptor_modf@Base 4.9
+ __interceptor_modff@Base 4.9
+ __interceptor_modfl@Base 4.9
+ __interceptor_munlock@Base 4.9
+ __interceptor_munlockall@Base 4.9
+ __interceptor_munmap@Base 4.9
+ __interceptor_nanosleep@Base 4.9
+ __interceptor_on_exit@Base 4.9
+ __interceptor_open64@Base 4.9
+ __interceptor_open@Base 4.9
+ __interceptor_open_memstream@Base 5
+ __interceptor_open_wmemstream@Base 5
+ __interceptor_opendir@Base 4.9
+ __interceptor_pipe2@Base 4.9
+ __interceptor_pipe@Base 4.9
+ __interceptor_poll@Base 4.9
+ __interceptor_posix_memalign@Base 4.9
+ __interceptor_ppoll@Base 4.9
+ __interceptor_prctl@Base 4.9
+ __interceptor_pread64@Base 4.9
+ __interceptor_pread@Base 4.9
+ __interceptor_preadv64@Base 4.9
+ __interceptor_preadv@Base 4.9
+ __interceptor_printf@Base 5
+ __interceptor_process_vm_readv@Base 6
+ __interceptor_process_vm_writev@Base 6
+ __interceptor_pthread_attr_getaffinity_np@Base 4.9
+ __interceptor_pthread_attr_getdetachstate@Base 4.9
+ __interceptor_pthread_attr_getguardsize@Base 4.9
+ __interceptor_pthread_attr_getinheritsched@Base 4.9
+ __interceptor_pthread_attr_getschedparam@Base 4.9
+ __interceptor_pthread_attr_getschedpolicy@Base 4.9
+ __interceptor_pthread_attr_getscope@Base 4.9
+ __interceptor_pthread_attr_getstack@Base 4.9
+ __interceptor_pthread_attr_getstacksize@Base 4.9
+ __interceptor_pthread_barrier_destroy@Base 4.9
+ __interceptor_pthread_barrier_init@Base 4.9
+ __interceptor_pthread_barrier_wait@Base 4.9
+ __interceptor_pthread_barrierattr_getpshared@Base 5
+ __interceptor_pthread_cond_broadcast@Base 4.9
+ __interceptor_pthread_cond_destroy@Base 4.9
+ __interceptor_pthread_cond_init@Base 4.9
+ __interceptor_pthread_cond_signal@Base 4.9
+ __interceptor_pthread_cond_timedwait@Base 4.9
+ __interceptor_pthread_cond_wait@Base 4.9
+ __interceptor_pthread_condattr_getclock@Base 5
+ __interceptor_pthread_condattr_getpshared@Base 5
+ __interceptor_pthread_create@Base 4.9
+ __interceptor_pthread_detach@Base 4.9
+ __interceptor_pthread_getschedparam@Base 4.9
+ __interceptor_pthread_join@Base 4.9
+ __interceptor_pthread_kill@Base 4.9
+ __interceptor_pthread_mutex_destroy@Base 4.9
+ __interceptor_pthread_mutex_init@Base 4.9
+ __interceptor_pthread_mutex_lock@Base 4.9
+ __interceptor_pthread_mutex_timedlock@Base 4.9
+ __interceptor_pthread_mutex_trylock@Base 4.9
+ __interceptor_pthread_mutex_unlock@Base 4.9
+ __interceptor_pthread_mutexattr_getprioceiling@Base 5
+ __interceptor_pthread_mutexattr_getprotocol@Base 5
+ __interceptor_pthread_mutexattr_getpshared@Base 5
+ __interceptor_pthread_mutexattr_getrobust@Base 5
+ __interceptor_pthread_mutexattr_getrobust_np@Base 5
+ __interceptor_pthread_mutexattr_gettype@Base 5
+ __interceptor_pthread_once@Base 4.9
+ __interceptor_pthread_rwlock_destroy@Base 4.9
+ __interceptor_pthread_rwlock_init@Base 4.9
+ __interceptor_pthread_rwlock_rdlock@Base 4.9
+ __interceptor_pthread_rwlock_timedrdlock@Base 4.9
+ __interceptor_pthread_rwlock_timedwrlock@Base 4.9
+ __interceptor_pthread_rwlock_tryrdlock@Base 4.9
+ __interceptor_pthread_rwlock_trywrlock@Base 4.9
+ __interceptor_pthread_rwlock_unlock@Base 4.9
+ __interceptor_pthread_rwlock_wrlock@Base 4.9
+ __interceptor_pthread_rwlockattr_getkind_np@Base 5
+ __interceptor_pthread_rwlockattr_getpshared@Base 5
+ __interceptor_pthread_setcancelstate@Base 6
+ __interceptor_pthread_setcanceltype@Base 6
+ __interceptor_pthread_setname_np@Base 4.9
+ __interceptor_pthread_spin_destroy@Base 4.9
+ __interceptor_pthread_spin_init@Base 4.9
+ __interceptor_pthread_spin_lock@Base 4.9
+ __interceptor_pthread_spin_trylock@Base 4.9
+ __interceptor_pthread_spin_unlock@Base 4.9
+ __interceptor_ptrace@Base 4.9
+ __interceptor_puts@Base 4.9
+ __interceptor_pvalloc@Base 4.9
+ __interceptor_pwrite64@Base 4.9
+ __interceptor_pwrite@Base 4.9
+ __interceptor_pwritev64@Base 4.9
+ __interceptor_pwritev@Base 4.9
+ __interceptor_raise@Base 4.9
+ __interceptor_rand_r@Base 5
+ __interceptor_random_r@Base 4.9
+ __interceptor_read@Base 4.9
+ __interceptor_readdir64@Base 4.9
+ __interceptor_readdir64_r@Base 4.9
+ __interceptor_readdir@Base 4.9
+ __interceptor_readdir_r@Base 4.9
+ __interceptor_readv@Base 4.9
+ __interceptor_realloc@Base 4.9
+ __interceptor_realpath@Base 4.9
+ __interceptor_recv@Base 4.9
+ __interceptor_recvmsg@Base 4.9
+ __interceptor_remquo@Base 4.9
+ __interceptor_remquof@Base 4.9
+ __interceptor_remquol@Base 4.9
+ __interceptor_rmdir@Base 4.9
+ __interceptor_scandir64@Base 4.9
+ __interceptor_scandir@Base 4.9
+ __interceptor_scanf@Base 4.9
+ __interceptor_sched_getaffinity@Base 4.9
+ __interceptor_sched_getparam@Base 6
+ __interceptor_sem_destroy@Base 4.9
+ __interceptor_sem_getvalue@Base 4.9
+ __interceptor_sem_init@Base 4.9
+ __interceptor_sem_post@Base 4.9
+ __interceptor_sem_timedwait@Base 4.9
+ __interceptor_sem_trywait@Base 4.9
+ __interceptor_sem_wait@Base 4.9
+ __interceptor_send@Base 4.9
+ __interceptor_sendmsg@Base 4.9
+ __interceptor_setgrent@Base 5
+ __interceptor_setitimer@Base 4.9
+ __interceptor_setjmp@Base 4.9
+ __interceptor_setlocale@Base 4.9
+ __interceptor_setpwent@Base 5
+ __interceptor_shmctl@Base 4.9
+ __interceptor_sigaction@Base 4.9
+ __interceptor_sigemptyset@Base 4.9
+ __interceptor_sigfillset@Base 4.9
+ __interceptor_siglongjmp@Base 4.9
+ __interceptor_signal@Base 4.9
+ __interceptor_signalfd@Base 4.9
+ __interceptor_sigpending@Base 4.9
+ __interceptor_sigprocmask@Base 4.9
+ __interceptor_sigsetjmp@Base 4.9
+ __interceptor_sigsuspend@Base 4.9
+ __interceptor_sigtimedwait@Base 4.9
+ __interceptor_sigwait@Base 4.9
+ __interceptor_sigwaitinfo@Base 4.9
+ __interceptor_sincos@Base 4.9
+ __interceptor_sincosf@Base 4.9
+ __interceptor_sincosl@Base 4.9
+ __interceptor_sleep@Base 4.9
+ __interceptor_snprintf@Base 5
+ __interceptor_socket@Base 4.9
+ __interceptor_socketpair@Base 4.9
+ __interceptor_sprintf@Base 5
+ __interceptor_sscanf@Base 4.9
+ __interceptor_stat64@Base 4.9
+ __interceptor_stat@Base 4.9
+ __interceptor_statfs64@Base 4.9
+ __interceptor_statfs@Base 4.9
+ __interceptor_statvfs64@Base 4.9
+ __interceptor_statvfs@Base 4.9
+ __interceptor_strcasecmp@Base 4.9
+ __interceptor_strcasestr@Base 6
+ __interceptor_strchr@Base 4.9
+ __interceptor_strchrnul@Base 4.9
+ __interceptor_strcmp@Base 4.9
+ __interceptor_strcpy@Base 4.9
+ __interceptor_strcspn@Base 6
+ __interceptor_strdup@Base 4.9
+ __interceptor_strerror@Base 4.9
+ __interceptor_strerror_r@Base 4.9
+ __interceptor_strlen@Base 4.9
+ __interceptor_strncasecmp@Base 4.9
+ __interceptor_strncmp@Base 4.9
+ __interceptor_strncpy@Base 4.9
+ __interceptor_strpbrk@Base 6
+ __interceptor_strptime@Base 4.9
+ __interceptor_strrchr@Base 4.9
+ __interceptor_strspn@Base 6
+ __interceptor_strstr@Base 4.9
+ __interceptor_strtoimax@Base 4.9
+ __interceptor_strtoumax@Base 4.9
+ __interceptor_sysinfo@Base 4.9
+ __interceptor_tcgetattr@Base 4.9
+ __interceptor_tempnam@Base 4.9
+ __interceptor_textdomain@Base 4.9
+ __interceptor_time@Base 4.9
+ __interceptor_timerfd_gettime@Base 5
+ __interceptor_timerfd_settime@Base 5
+ __interceptor_times@Base 4.9
+ __interceptor_tmpfile64@Base 5
+ __interceptor_tmpfile@Base 5
+ __interceptor_tmpnam@Base 4.9
+ __interceptor_tmpnam_r@Base 4.9
+ __interceptor_tsearch@Base 5
+ __interceptor_unlink@Base 4.9
+ __interceptor_usleep@Base 4.9
+ __interceptor_valloc@Base 4.9
+ __interceptor_vasprintf@Base 5
+ __interceptor_vfork@Base 5
+ __interceptor_vfprintf@Base 5
+ __interceptor_vfscanf@Base 4.9
+ __interceptor_vprintf@Base 5
+ __interceptor_vscanf@Base 4.9
+ __interceptor_vsnprintf@Base 5
+ __interceptor_vsprintf@Base 5
+ __interceptor_vsscanf@Base 4.9
+ __interceptor_wait3@Base 4.9
+ __interceptor_wait4@Base 4.9
+ __interceptor_wait@Base 4.9
+ __interceptor_waitid@Base 4.9
+ __interceptor_waitpid@Base 4.9
+ __interceptor_wcrtomb@Base 6
+ __interceptor_wcsnrtombs@Base 4.9
+ __interceptor_wcsrtombs@Base 4.9
+ __interceptor_wcstombs@Base 4.9
+ __interceptor_wordexp@Base 4.9
+ __interceptor_write@Base 4.9
+ __interceptor_writev@Base 4.9
+ __interceptor_xdr_bool@Base 5
+ __interceptor_xdr_bytes@Base 5
+ __interceptor_xdr_char@Base 5
+ __interceptor_xdr_double@Base 5
+ __interceptor_xdr_enum@Base 5
+ __interceptor_xdr_float@Base 5
+ __interceptor_xdr_hyper@Base 5
+ __interceptor_xdr_int16_t@Base 5
+ __interceptor_xdr_int32_t@Base 5
+ __interceptor_xdr_int64_t@Base 5
+ __interceptor_xdr_int8_t@Base 5
+ __interceptor_xdr_int@Base 5
+ __interceptor_xdr_long@Base 5
+ __interceptor_xdr_longlong_t@Base 5
+ __interceptor_xdr_quad_t@Base 5
+ __interceptor_xdr_short@Base 5
+ __interceptor_xdr_string@Base 5
+ __interceptor_xdr_u_char@Base 5
+ __interceptor_xdr_u_hyper@Base 5
+ __interceptor_xdr_u_int@Base 5
+ __interceptor_xdr_u_long@Base 5
+ __interceptor_xdr_u_longlong_t@Base 5
+ __interceptor_xdr_u_quad_t@Base 5
+ __interceptor_xdr_u_short@Base 5
+ __interceptor_xdr_uint16_t@Base 5
+ __interceptor_xdr_uint32_t@Base 5
+ __interceptor_xdr_uint64_t@Base 5
+ __interceptor_xdr_uint8_t@Base 5
+ __interceptor_xdrmem_create@Base 5
+ __interceptor_xdrstdio_create@Base 5
+ __isoc99_fprintf@Base 5
+ __isoc99_fscanf@Base 4.9
+ __isoc99_printf@Base 5
+ __isoc99_scanf@Base 4.9
+ __isoc99_snprintf@Base 5
+ __isoc99_sprintf@Base 5
+ __isoc99_sscanf@Base 4.9
+ __isoc99_vfprintf@Base 5
+ __isoc99_vfscanf@Base 4.9
+ __isoc99_vprintf@Base 5
+ __isoc99_vscanf@Base 4.9
+ __isoc99_vsnprintf@Base 5
+ __isoc99_vsprintf@Base 5
+ __isoc99_vsscanf@Base 4.9
+ __libc_memalign@Base 4.9
+ __lxstat64@Base 4.9
+ __lxstat@Base 4.9
+ __overflow@Base 5
+ __res_iclose@Base 4.9
+ __sanitizer_cov@Base 4.9
+ __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_cov_trace_basic_block@Base 6
+ __sanitizer_cov_trace_cmp@Base 6
+ __sanitizer_cov_trace_func_enter@Base 6
+ __sanitizer_cov_trace_switch@Base 6
+ __sanitizer_cov_with_check@Base 6
+ __sanitizer_free_hook@Base 5
+ __sanitizer_get_allocated_size@Base 5
+ __sanitizer_get_coverage_guards@Base 6
+ __sanitizer_get_current_allocated_bytes@Base 5
+ __sanitizer_get_estimated_allocated_size@Base 5
+ __sanitizer_get_free_bytes@Base 5
+ __sanitizer_get_heap_size@Base 5
+ __sanitizer_get_number_of_counters@Base 6
+ __sanitizer_get_ownership@Base 5
+ __sanitizer_get_total_unique_caller_callee_pairs@Base 6
+ __sanitizer_get_total_unique_coverage@Base 6
+ __sanitizer_get_unmapped_bytes@Base 5
+ __sanitizer_malloc_hook@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_print_stack_trace@Base 5
+ __sanitizer_report_error_summary@Base 4.9
+ __sanitizer_reset_coverage@Base 6
+ __sanitizer_sandbox_on_notify@Base 4.9
+ __sanitizer_set_death_callback@Base 6
+ __sanitizer_set_report_path@Base 4.9
+ __sanitizer_syscall_post_impl_accept4@Base 4.9
+ __sanitizer_syscall_post_impl_accept@Base 4.9
+ __sanitizer_syscall_post_impl_access@Base 4.9
+ __sanitizer_syscall_post_impl_acct@Base 4.9
+ __sanitizer_syscall_post_impl_add_key@Base 4.9
+ __sanitizer_syscall_post_impl_adjtimex@Base 4.9
+ __sanitizer_syscall_post_impl_alarm@Base 4.9
+ __sanitizer_syscall_post_impl_bdflush@Base 4.9
+ __sanitizer_syscall_post_impl_bind@Base 4.9
+ __sanitizer_syscall_post_impl_brk@Base 4.9
+ __sanitizer_syscall_post_impl_capget@Base 4.9
+ __sanitizer_syscall_post_impl_capset@Base 4.9
+ __sanitizer_syscall_post_impl_chdir@Base 4.9
+ __sanitizer_syscall_post_impl_chmod@Base 4.9
+ __sanitizer_syscall_post_impl_chown@Base 4.9
+ __sanitizer_syscall_post_impl_chroot@Base 4.9
+ __sanitizer_syscall_post_impl_clock_adjtime@Base 4.9
+ __sanitizer_syscall_post_impl_clock_getres@Base 4.9
+ __sanitizer_syscall_post_impl_clock_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_clock_nanosleep@Base 4.9
+ __sanitizer_syscall_post_impl_clock_settime@Base 4.9
+ __sanitizer_syscall_post_impl_close@Base 4.9
+ __sanitizer_syscall_post_impl_connect@Base 4.9
+ __sanitizer_syscall_post_impl_creat@Base 4.9
+ __sanitizer_syscall_post_impl_delete_module@Base 4.9
+ __sanitizer_syscall_post_impl_dup2@Base 4.9
+ __sanitizer_syscall_post_impl_dup3@Base 4.9
+ __sanitizer_syscall_post_impl_dup@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_create1@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_create@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_ctl@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_pwait@Base 4.9
+ __sanitizer_syscall_post_impl_epoll_wait@Base 4.9
+ __sanitizer_syscall_post_impl_eventfd2@Base 4.9
+ __sanitizer_syscall_post_impl_eventfd@Base 4.9
+ __sanitizer_syscall_post_impl_exit@Base 4.9
+ __sanitizer_syscall_post_impl_exit_group@Base 4.9
+ __sanitizer_syscall_post_impl_faccessat@Base 4.9
+ __sanitizer_syscall_post_impl_fchdir@Base 4.9
+ __sanitizer_syscall_post_impl_fchmod@Base 4.9
+ __sanitizer_syscall_post_impl_fchmodat@Base 4.9
+ __sanitizer_syscall_post_impl_fchown@Base 4.9
+ __sanitizer_syscall_post_impl_fchownat@Base 4.9
+ __sanitizer_syscall_post_impl_fcntl64@Base 4.9
+ __sanitizer_syscall_post_impl_fcntl@Base 4.9
+ __sanitizer_syscall_post_impl_fdatasync@Base 4.9
+ __sanitizer_syscall_post_impl_fgetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_flistxattr@Base 4.9
+ __sanitizer_syscall_post_impl_flock@Base 4.9
+ __sanitizer_syscall_post_impl_fork@Base 4.9
+ __sanitizer_syscall_post_impl_fremovexattr@Base 4.9
+ __sanitizer_syscall_post_impl_fsetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_fstat64@Base 4.9
+ __sanitizer_syscall_post_impl_fstat@Base 4.9
+ __sanitizer_syscall_post_impl_fstatat64@Base 4.9
+ __sanitizer_syscall_post_impl_fstatfs64@Base 4.9
+ __sanitizer_syscall_post_impl_fstatfs@Base 4.9
+ __sanitizer_syscall_post_impl_fsync@Base 4.9
+ __sanitizer_syscall_post_impl_ftruncate@Base 4.9
+ __sanitizer_syscall_post_impl_futimesat@Base 4.9
+ __sanitizer_syscall_post_impl_get_mempolicy@Base 4.9
+ __sanitizer_syscall_post_impl_get_robust_list@Base 4.9
+ __sanitizer_syscall_post_impl_getcpu@Base 4.9
+ __sanitizer_syscall_post_impl_getcwd@Base 4.9
+ __sanitizer_syscall_post_impl_getdents64@Base 4.9
+ __sanitizer_syscall_post_impl_getdents@Base 4.9
+ __sanitizer_syscall_post_impl_getegid@Base 4.9
+ __sanitizer_syscall_post_impl_geteuid@Base 4.9
+ __sanitizer_syscall_post_impl_getgid@Base 4.9
+ __sanitizer_syscall_post_impl_getgroups@Base 4.9
+ __sanitizer_syscall_post_impl_gethostname@Base 4.9
+ __sanitizer_syscall_post_impl_getitimer@Base 4.9
+ __sanitizer_syscall_post_impl_getpeername@Base 4.9
+ __sanitizer_syscall_post_impl_getpgid@Base 4.9
+ __sanitizer_syscall_post_impl_getpgrp@Base 4.9
+ __sanitizer_syscall_post_impl_getpid@Base 4.9
+ __sanitizer_syscall_post_impl_getppid@Base 4.9
+ __sanitizer_syscall_post_impl_getpriority@Base 4.9
+ __sanitizer_syscall_post_impl_getresgid@Base 4.9
+ __sanitizer_syscall_post_impl_getresuid@Base 4.9
+ __sanitizer_syscall_post_impl_getrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_getrusage@Base 4.9
+ __sanitizer_syscall_post_impl_getsid@Base 4.9
+ __sanitizer_syscall_post_impl_getsockname@Base 4.9
+ __sanitizer_syscall_post_impl_getsockopt@Base 4.9
+ __sanitizer_syscall_post_impl_gettid@Base 4.9
+ __sanitizer_syscall_post_impl_gettimeofday@Base 4.9
+ __sanitizer_syscall_post_impl_getuid@Base 4.9
+ __sanitizer_syscall_post_impl_getxattr@Base 4.9
+ __sanitizer_syscall_post_impl_init_module@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_add_watch@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_init1@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_init@Base 4.9
+ __sanitizer_syscall_post_impl_inotify_rm_watch@Base 4.9
+ __sanitizer_syscall_post_impl_io_cancel@Base 4.9
+ __sanitizer_syscall_post_impl_io_destroy@Base 4.9
+ __sanitizer_syscall_post_impl_io_getevents@Base 4.9
+ __sanitizer_syscall_post_impl_io_setup@Base 4.9
+ __sanitizer_syscall_post_impl_io_submit@Base 4.9
+ __sanitizer_syscall_post_impl_ioctl@Base 4.9
+ __sanitizer_syscall_post_impl_ioperm@Base 4.9
+ __sanitizer_syscall_post_impl_ioprio_get@Base 4.9
+ __sanitizer_syscall_post_impl_ioprio_set@Base 4.9
+ __sanitizer_syscall_post_impl_ipc@Base 4.9
+ __sanitizer_syscall_post_impl_kexec_load@Base 4.9
+ __sanitizer_syscall_post_impl_keyctl@Base 4.9
+ __sanitizer_syscall_post_impl_kill@Base 4.9
+ __sanitizer_syscall_post_impl_lchown@Base 4.9
+ __sanitizer_syscall_post_impl_lgetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_link@Base 4.9
+ __sanitizer_syscall_post_impl_linkat@Base 4.9
+ __sanitizer_syscall_post_impl_listen@Base 4.9
+ __sanitizer_syscall_post_impl_listxattr@Base 4.9
+ __sanitizer_syscall_post_impl_llistxattr@Base 4.9
+ __sanitizer_syscall_post_impl_llseek@Base 4.9
+ __sanitizer_syscall_post_impl_lookup_dcookie@Base 4.9
+ __sanitizer_syscall_post_impl_lremovexattr@Base 4.9
+ __sanitizer_syscall_post_impl_lseek@Base 4.9
+ __sanitizer_syscall_post_impl_lsetxattr@Base 4.9
+ __sanitizer_syscall_post_impl_lstat64@Base 4.9
+ __sanitizer_syscall_post_impl_lstat@Base 4.9
+ __sanitizer_syscall_post_impl_madvise@Base 4.9
+ __sanitizer_syscall_post_impl_mbind@Base 4.9
+ __sanitizer_syscall_post_impl_migrate_pages@Base 4.9
+ __sanitizer_syscall_post_impl_mincore@Base 4.9
+ __sanitizer_syscall_post_impl_mkdir@Base 4.9
+ __sanitizer_syscall_post_impl_mkdirat@Base 4.9
+ __sanitizer_syscall_post_impl_mknod@Base 4.9
+ __sanitizer_syscall_post_impl_mknodat@Base 4.9
+ __sanitizer_syscall_post_impl_mlock@Base 4.9
+ __sanitizer_syscall_post_impl_mlockall@Base 4.9
+ __sanitizer_syscall_post_impl_mmap_pgoff@Base 4.9
+ __sanitizer_syscall_post_impl_mount@Base 4.9
+ __sanitizer_syscall_post_impl_move_pages@Base 4.9
+ __sanitizer_syscall_post_impl_mprotect@Base 4.9
+ __sanitizer_syscall_post_impl_mq_getsetattr@Base 4.9
+ __sanitizer_syscall_post_impl_mq_notify@Base 4.9
+ __sanitizer_syscall_post_impl_mq_open@Base 4.9
+ __sanitizer_syscall_post_impl_mq_timedreceive@Base 4.9
+ __sanitizer_syscall_post_impl_mq_timedsend@Base 4.9
+ __sanitizer_syscall_post_impl_mq_unlink@Base 4.9
+ __sanitizer_syscall_post_impl_mremap@Base 4.9
+ __sanitizer_syscall_post_impl_msgctl@Base 4.9
+ __sanitizer_syscall_post_impl_msgget@Base 4.9
+ __sanitizer_syscall_post_impl_msgrcv@Base 4.9
+ __sanitizer_syscall_post_impl_msgsnd@Base 4.9
+ __sanitizer_syscall_post_impl_msync@Base 4.9
+ __sanitizer_syscall_post_impl_munlock@Base 4.9
+ __sanitizer_syscall_post_impl_munlockall@Base 4.9
+ __sanitizer_syscall_post_impl_munmap@Base 4.9
+ __sanitizer_syscall_post_impl_name_to_handle_at@Base 4.9
+ __sanitizer_syscall_post_impl_nanosleep@Base 4.9
+ __sanitizer_syscall_post_impl_newfstat@Base 4.9
+ __sanitizer_syscall_post_impl_newfstatat@Base 4.9
+ __sanitizer_syscall_post_impl_newlstat@Base 4.9
+ __sanitizer_syscall_post_impl_newstat@Base 4.9
+ __sanitizer_syscall_post_impl_newuname@Base 4.9
+ __sanitizer_syscall_post_impl_ni_syscall@Base 4.9
+ __sanitizer_syscall_post_impl_nice@Base 4.9
+ __sanitizer_syscall_post_impl_old_getrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_old_mmap@Base 4.9
+ __sanitizer_syscall_post_impl_old_readdir@Base 4.9
+ __sanitizer_syscall_post_impl_old_select@Base 4.9
+ __sanitizer_syscall_post_impl_oldumount@Base 4.9
+ __sanitizer_syscall_post_impl_olduname@Base 4.9
+ __sanitizer_syscall_post_impl_open@Base 4.9
+ __sanitizer_syscall_post_impl_open_by_handle_at@Base 4.9
+ __sanitizer_syscall_post_impl_openat@Base 4.9
+ __sanitizer_syscall_post_impl_pause@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_iobase@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_read@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_write@Base 4.9
+ __sanitizer_syscall_post_impl_perf_event_open@Base 4.9
+ __sanitizer_syscall_post_impl_personality@Base 4.9
+ __sanitizer_syscall_post_impl_pipe2@Base 4.9
+ __sanitizer_syscall_post_impl_pipe@Base 4.9
+ __sanitizer_syscall_post_impl_pivot_root@Base 4.9
+ __sanitizer_syscall_post_impl_poll@Base 4.9
+ __sanitizer_syscall_post_impl_ppoll@Base 4.9
+ __sanitizer_syscall_post_impl_pread64@Base 4.9
+ __sanitizer_syscall_post_impl_preadv@Base 4.9
+ __sanitizer_syscall_post_impl_prlimit64@Base 4.9
+ __sanitizer_syscall_post_impl_process_vm_readv@Base 4.9
+ __sanitizer_syscall_post_impl_process_vm_writev@Base 4.9
+ __sanitizer_syscall_post_impl_pselect6@Base 4.9
+ __sanitizer_syscall_post_impl_ptrace@Base 4.9
+ __sanitizer_syscall_post_impl_pwrite64@Base 4.9
+ __sanitizer_syscall_post_impl_pwritev@Base 4.9
+ __sanitizer_syscall_post_impl_quotactl@Base 4.9
+ __sanitizer_syscall_post_impl_read@Base 4.9
+ __sanitizer_syscall_post_impl_readlink@Base 4.9
+ __sanitizer_syscall_post_impl_readlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_readv@Base 4.9
+ __sanitizer_syscall_post_impl_reboot@Base 4.9
+ __sanitizer_syscall_post_impl_recv@Base 4.9
+ __sanitizer_syscall_post_impl_recvfrom@Base 4.9
+ __sanitizer_syscall_post_impl_recvmmsg@Base 4.9
+ __sanitizer_syscall_post_impl_recvmsg@Base 4.9
+ __sanitizer_syscall_post_impl_remap_file_pages@Base 4.9
+ __sanitizer_syscall_post_impl_removexattr@Base 4.9
+ __sanitizer_syscall_post_impl_rename@Base 4.9
+ __sanitizer_syscall_post_impl_renameat@Base 4.9
+ __sanitizer_syscall_post_impl_request_key@Base 4.9
+ __sanitizer_syscall_post_impl_restart_syscall@Base 4.9
+ __sanitizer_syscall_post_impl_rmdir@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigpending@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigprocmask@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigqueueinfo@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigtimedwait@Base 4.9
+ __sanitizer_syscall_post_impl_rt_tgsigqueueinfo@Base 4.9
+ __sanitizer_syscall_post_impl_sched_get_priority_max@Base 4.9
+ __sanitizer_syscall_post_impl_sched_get_priority_min@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getaffinity@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getparam@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getscheduler@Base 4.9
+ __sanitizer_syscall_post_impl_sched_rr_get_interval@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setaffinity@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setparam@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setscheduler@Base 4.9
+ __sanitizer_syscall_post_impl_sched_yield@Base 4.9
+ __sanitizer_syscall_post_impl_select@Base 4.9
+ __sanitizer_syscall_post_impl_semctl@Base 4.9
+ __sanitizer_syscall_post_impl_semget@Base 4.9
+ __sanitizer_syscall_post_impl_semop@Base 4.9
+ __sanitizer_syscall_post_impl_semtimedop@Base 4.9
+ __sanitizer_syscall_post_impl_send@Base 4.9
+ __sanitizer_syscall_post_impl_sendfile64@Base 4.9
+ __sanitizer_syscall_post_impl_sendfile@Base 4.9
+ __sanitizer_syscall_post_impl_sendmmsg@Base 4.9
+ __sanitizer_syscall_post_impl_sendmsg@Base 4.9
+ __sanitizer_syscall_post_impl_sendto@Base 4.9
+ __sanitizer_syscall_post_impl_set_mempolicy@Base 4.9
+ __sanitizer_syscall_post_impl_set_robust_list@Base 4.9
+ __sanitizer_syscall_post_impl_set_tid_address@Base 4.9
+ __sanitizer_syscall_post_impl_setdomainname@Base 4.9
+ __sanitizer_syscall_post_impl_setfsgid@Base 4.9
+ __sanitizer_syscall_post_impl_setfsuid@Base 4.9
+ __sanitizer_syscall_post_impl_setgid@Base 4.9
+ __sanitizer_syscall_post_impl_setgroups@Base 4.9
+ __sanitizer_syscall_post_impl_sethostname@Base 4.9
+ __sanitizer_syscall_post_impl_setitimer@Base 4.9
+ __sanitizer_syscall_post_impl_setns@Base 4.9
+ __sanitizer_syscall_post_impl_setpgid@Base 4.9
+ __sanitizer_syscall_post_impl_setpriority@Base 4.9
+ __sanitizer_syscall_post_impl_setregid@Base 4.9
+ __sanitizer_syscall_post_impl_setresgid@Base 4.9
+ __sanitizer_syscall_post_impl_setresuid@Base 4.9
+ __sanitizer_syscall_post_impl_setreuid@Base 4.9
+ __sanitizer_syscall_post_impl_setrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_setsid@Base 4.9
+ __sanitizer_syscall_post_impl_setsockopt@Base 4.9
+ __sanitizer_syscall_post_impl_settimeofday@Base 4.9
+ __sanitizer_syscall_post_impl_setuid@Base 4.9
+ __sanitizer_syscall_post_impl_setxattr@Base 4.9
+ __sanitizer_syscall_post_impl_sgetmask@Base 4.9
+ __sanitizer_syscall_post_impl_shmat@Base 4.9
+ __sanitizer_syscall_post_impl_shmctl@Base 4.9
+ __sanitizer_syscall_post_impl_shmdt@Base 4.9
+ __sanitizer_syscall_post_impl_shmget@Base 4.9
+ __sanitizer_syscall_post_impl_shutdown@Base 4.9
+ __sanitizer_syscall_post_impl_signal@Base 4.9
+ __sanitizer_syscall_post_impl_signalfd4@Base 4.9
+ __sanitizer_syscall_post_impl_signalfd@Base 4.9
+ __sanitizer_syscall_post_impl_sigpending@Base 4.9
+ __sanitizer_syscall_post_impl_sigprocmask@Base 4.9
+ __sanitizer_syscall_post_impl_socket@Base 4.9
+ __sanitizer_syscall_post_impl_socketcall@Base 4.9
+ __sanitizer_syscall_post_impl_socketpair@Base 4.9
+ __sanitizer_syscall_post_impl_splice@Base 4.9
+ __sanitizer_syscall_post_impl_spu_create@Base 4.9
+ __sanitizer_syscall_post_impl_spu_run@Base 4.9
+ __sanitizer_syscall_post_impl_ssetmask@Base 4.9
+ __sanitizer_syscall_post_impl_stat64@Base 4.9
+ __sanitizer_syscall_post_impl_stat@Base 4.9
+ __sanitizer_syscall_post_impl_statfs64@Base 4.9
+ __sanitizer_syscall_post_impl_statfs@Base 4.9
+ __sanitizer_syscall_post_impl_stime@Base 4.9
+ __sanitizer_syscall_post_impl_swapoff@Base 4.9
+ __sanitizer_syscall_post_impl_swapon@Base 4.9
+ __sanitizer_syscall_post_impl_symlink@Base 4.9
+ __sanitizer_syscall_post_impl_symlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_sync@Base 4.9
+ __sanitizer_syscall_post_impl_syncfs@Base 4.9
+ __sanitizer_syscall_post_impl_sysctl@Base 4.9
+ __sanitizer_syscall_post_impl_sysfs@Base 4.9
+ __sanitizer_syscall_post_impl_sysinfo@Base 4.9
+ __sanitizer_syscall_post_impl_syslog@Base 4.9
+ __sanitizer_syscall_post_impl_tee@Base 4.9
+ __sanitizer_syscall_post_impl_tgkill@Base 4.9
+ __sanitizer_syscall_post_impl_time@Base 4.9
+ __sanitizer_syscall_post_impl_timer_create@Base 4.9
+ __sanitizer_syscall_post_impl_timer_delete@Base 4.9
+ __sanitizer_syscall_post_impl_timer_getoverrun@Base 4.9
+ __sanitizer_syscall_post_impl_timer_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_timer_settime@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_create@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_settime@Base 4.9
+ __sanitizer_syscall_post_impl_times@Base 4.9
+ __sanitizer_syscall_post_impl_tkill@Base 4.9
+ __sanitizer_syscall_post_impl_truncate@Base 4.9
+ __sanitizer_syscall_post_impl_umask@Base 4.9
+ __sanitizer_syscall_post_impl_umount@Base 4.9
+ __sanitizer_syscall_post_impl_uname@Base 4.9
+ __sanitizer_syscall_post_impl_unlink@Base 4.9
+ __sanitizer_syscall_post_impl_unlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_unshare@Base 4.9
+ __sanitizer_syscall_post_impl_uselib@Base 4.9
+ __sanitizer_syscall_post_impl_ustat@Base 4.9
+ __sanitizer_syscall_post_impl_utime@Base 4.9
+ __sanitizer_syscall_post_impl_utimensat@Base 4.9
+ __sanitizer_syscall_post_impl_utimes@Base 4.9
+ __sanitizer_syscall_post_impl_vfork@Base 4.9
+ __sanitizer_syscall_post_impl_vhangup@Base 4.9
+ __sanitizer_syscall_post_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_post_impl_wait4@Base 4.9
+ __sanitizer_syscall_post_impl_waitid@Base 4.9
+ __sanitizer_syscall_post_impl_waitpid@Base 4.9
+ __sanitizer_syscall_post_impl_write@Base 4.9
+ __sanitizer_syscall_post_impl_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_accept4@Base 4.9
+ __sanitizer_syscall_pre_impl_accept@Base 4.9
+ __sanitizer_syscall_pre_impl_access@Base 4.9
+ __sanitizer_syscall_pre_impl_acct@Base 4.9
+ __sanitizer_syscall_pre_impl_add_key@Base 4.9
+ __sanitizer_syscall_pre_impl_adjtimex@Base 4.9
+ __sanitizer_syscall_pre_impl_alarm@Base 4.9
+ __sanitizer_syscall_pre_impl_bdflush@Base 4.9
+ __sanitizer_syscall_pre_impl_bind@Base 4.9
+ __sanitizer_syscall_pre_impl_brk@Base 4.9
+ __sanitizer_syscall_pre_impl_capget@Base 4.9
+ __sanitizer_syscall_pre_impl_capset@Base 4.9
+ __sanitizer_syscall_pre_impl_chdir@Base 4.9
+ __sanitizer_syscall_pre_impl_chmod@Base 4.9
+ __sanitizer_syscall_pre_impl_chown@Base 4.9
+ __sanitizer_syscall_pre_impl_chroot@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_adjtime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_getres@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_close@Base 4.9
+ __sanitizer_syscall_pre_impl_connect@Base 4.9
+ __sanitizer_syscall_pre_impl_creat@Base 4.9
+ __sanitizer_syscall_pre_impl_delete_module@Base 4.9
+ __sanitizer_syscall_pre_impl_dup2@Base 4.9
+ __sanitizer_syscall_pre_impl_dup3@Base 4.9
+ __sanitizer_syscall_pre_impl_dup@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create1@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_ctl@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_pwait@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_wait@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd2@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd@Base 4.9
+ __sanitizer_syscall_pre_impl_exit@Base 4.9
+ __sanitizer_syscall_pre_impl_exit_group@Base 4.9
+ __sanitizer_syscall_pre_impl_faccessat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchdir@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmod@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmodat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchown@Base 4.9
+ __sanitizer_syscall_pre_impl_fchownat@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl64@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl@Base 4.9
+ __sanitizer_syscall_pre_impl_fdatasync@Base 4.9
+ __sanitizer_syscall_pre_impl_fgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flock@Base 4.9
+ __sanitizer_syscall_pre_impl_fork@Base 4.9
+ __sanitizer_syscall_pre_impl_fremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs@Base 4.9
+ __sanitizer_syscall_pre_impl_fsync@Base 4.9
+ __sanitizer_syscall_pre_impl_ftruncate@Base 4.9
+ __sanitizer_syscall_pre_impl_futimesat@Base 4.9
+ __sanitizer_syscall_pre_impl_get_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_get_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_getcpu@Base 4.9
+ __sanitizer_syscall_pre_impl_getcwd@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents64@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents@Base 4.9
+ __sanitizer_syscall_pre_impl_getegid@Base 4.9
+ __sanitizer_syscall_pre_impl_geteuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_gethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_getitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_getpeername@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgrp@Base 4.9
+ __sanitizer_syscall_pre_impl_getpid@Base 4.9
+ __sanitizer_syscall_pre_impl_getppid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_getresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_getrusage@Base 4.9
+ __sanitizer_syscall_pre_impl_getsid@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockname@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_gettid@Base 4.9
+ __sanitizer_syscall_pre_impl_gettimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_getuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_init_module@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_add_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init1@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_rm_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_io_cancel@Base 4.9
+ __sanitizer_syscall_pre_impl_io_destroy@Base 4.9
+ __sanitizer_syscall_pre_impl_io_getevents@Base 4.9
+ __sanitizer_syscall_pre_impl_io_setup@Base 4.9
+ __sanitizer_syscall_pre_impl_io_submit@Base 4.9
+ __sanitizer_syscall_pre_impl_ioctl@Base 4.9
+ __sanitizer_syscall_pre_impl_ioperm@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_get@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_set@Base 4.9
+ __sanitizer_syscall_pre_impl_ipc@Base 4.9
+ __sanitizer_syscall_pre_impl_kexec_load@Base 4.9
+ __sanitizer_syscall_pre_impl_keyctl@Base 4.9
+ __sanitizer_syscall_pre_impl_kill@Base 4.9
+ __sanitizer_syscall_pre_impl_lchown@Base 4.9
+ __sanitizer_syscall_pre_impl_lgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_link@Base 4.9
+ __sanitizer_syscall_pre_impl_linkat@Base 4.9
+ __sanitizer_syscall_pre_impl_listen@Base 4.9
+ __sanitizer_syscall_pre_impl_listxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lookup_dcookie@Base 4.9
+ __sanitizer_syscall_pre_impl_lremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat@Base 4.9
+ __sanitizer_syscall_pre_impl_madvise@Base 4.9
+ __sanitizer_syscall_pre_impl_mbind@Base 4.9
+ __sanitizer_syscall_pre_impl_migrate_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mincore@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdir@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdirat@Base 4.9
+ __sanitizer_syscall_pre_impl_mknod@Base 4.9
+ __sanitizer_syscall_pre_impl_mknodat@Base 4.9
+ __sanitizer_syscall_pre_impl_mlock@Base 4.9
+ __sanitizer_syscall_pre_impl_mlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_mmap_pgoff@Base 4.9
+ __sanitizer_syscall_pre_impl_mount@Base 4.9
+ __sanitizer_syscall_pre_impl_move_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mprotect@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_getsetattr@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_notify@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_open@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedreceive@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedsend@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_mremap@Base 4.9
+ __sanitizer_syscall_pre_impl_msgctl@Base 4.9
+ __sanitizer_syscall_pre_impl_msgget@Base 4.9
+ __sanitizer_syscall_pre_impl_msgrcv@Base 4.9
+ __sanitizer_syscall_pre_impl_msgsnd@Base 4.9
+ __sanitizer_syscall_pre_impl_msync@Base 4.9
+ __sanitizer_syscall_pre_impl_munlock@Base 4.9
+ __sanitizer_syscall_pre_impl_munlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_munmap@Base 4.9
+ __sanitizer_syscall_pre_impl_name_to_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstatat@Base 4.9
+ __sanitizer_syscall_pre_impl_newlstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newuname@Base 4.9
+ __sanitizer_syscall_pre_impl_ni_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_nice@Base 4.9
+ __sanitizer_syscall_pre_impl_old_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_old_mmap@Base 4.9
+ __sanitizer_syscall_pre_impl_old_readdir@Base 4.9
+ __sanitizer_syscall_pre_impl_old_select@Base 4.9
+ __sanitizer_syscall_pre_impl_oldumount@Base 4.9
+ __sanitizer_syscall_pre_impl_olduname@Base 4.9
+ __sanitizer_syscall_pre_impl_open@Base 4.9
+ __sanitizer_syscall_pre_impl_open_by_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_openat@Base 4.9
+ __sanitizer_syscall_pre_impl_pause@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_iobase@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_read@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_write@Base 4.9
+ __sanitizer_syscall_pre_impl_perf_event_open@Base 4.9
+ __sanitizer_syscall_pre_impl_personality@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe2@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe@Base 4.9
+ __sanitizer_syscall_pre_impl_pivot_root@Base 4.9
+ __sanitizer_syscall_pre_impl_poll@Base 4.9
+ __sanitizer_syscall_pre_impl_ppoll@Base 4.9
+ __sanitizer_syscall_pre_impl_pread64@Base 4.9
+ __sanitizer_syscall_pre_impl_preadv@Base 4.9
+ __sanitizer_syscall_pre_impl_prlimit64@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_pselect6@Base 4.9
+ __sanitizer_syscall_pre_impl_ptrace@Base 4.9
+ __sanitizer_syscall_pre_impl_pwrite64@Base 4.9
+ __sanitizer_syscall_pre_impl_pwritev@Base 4.9
+ __sanitizer_syscall_pre_impl_quotactl@Base 4.9
+ __sanitizer_syscall_pre_impl_read@Base 4.9
+ __sanitizer_syscall_pre_impl_readlink@Base 4.9
+ __sanitizer_syscall_pre_impl_readlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_reboot@Base 4.9
+ __sanitizer_syscall_pre_impl_recv@Base 4.9
+ __sanitizer_syscall_pre_impl_recvfrom@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_remap_file_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_removexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_rename@Base 4.9
+ __sanitizer_syscall_pre_impl_renameat@Base 4.9
+ __sanitizer_syscall_pre_impl_request_key@Base 4.9
+ __sanitizer_syscall_pre_impl_restart_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_rmdir@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigtimedwait@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_tgsigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_max@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_min@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_rr_get_interval@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_yield@Base 4.9
+ __sanitizer_syscall_pre_impl_select@Base 4.9
+ __sanitizer_syscall_pre_impl_semctl@Base 4.9
+ __sanitizer_syscall_pre_impl_semget@Base 4.9
+ __sanitizer_syscall_pre_impl_semop@Base 4.9
+ __sanitizer_syscall_pre_impl_semtimedop@Base 4.9
+ __sanitizer_syscall_pre_impl_send@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile64@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendto@Base 4.9
+ __sanitizer_syscall_pre_impl_set_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_set_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_set_tid_address@Base 4.9
+ __sanitizer_syscall_pre_impl_setdomainname@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_sethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_setitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_setns@Base 4.9
+ __sanitizer_syscall_pre_impl_setpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_setregid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setreuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_setsid@Base 4.9
+ __sanitizer_syscall_pre_impl_setsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_settimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_setuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_sgetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_shmat@Base 4.9
+ __sanitizer_syscall_pre_impl_shmctl@Base 4.9
+ __sanitizer_syscall_pre_impl_shmdt@Base 4.9
+ __sanitizer_syscall_pre_impl_shmget@Base 4.9
+ __sanitizer_syscall_pre_impl_shutdown@Base 4.9
+ __sanitizer_syscall_pre_impl_signal@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd4@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd@Base 4.9
+ __sanitizer_syscall_pre_impl_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_socket@Base 4.9
+ __sanitizer_syscall_pre_impl_socketcall@Base 4.9
+ __sanitizer_syscall_pre_impl_socketpair@Base 4.9
+ __sanitizer_syscall_pre_impl_splice@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_create@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_run@Base 4.9
+ __sanitizer_syscall_pre_impl_ssetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_stat64@Base 4.9
+ __sanitizer_syscall_pre_impl_stat@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs@Base 4.9
+ __sanitizer_syscall_pre_impl_stime@Base 4.9
+ __sanitizer_syscall_pre_impl_swapoff@Base 4.9
+ __sanitizer_syscall_pre_impl_swapon@Base 4.9
+ __sanitizer_syscall_pre_impl_symlink@Base 4.9
+ __sanitizer_syscall_pre_impl_symlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_sync@Base 4.9
+ __sanitizer_syscall_pre_impl_syncfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysctl@Base 4.9
+ __sanitizer_syscall_pre_impl_sysfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_syslog@Base 4.9
+ __sanitizer_syscall_pre_impl_tee@Base 4.9
+ __sanitizer_syscall_pre_impl_tgkill@Base 4.9
+ __sanitizer_syscall_pre_impl_time@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_delete@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_getoverrun@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_times@Base 4.9
+ __sanitizer_syscall_pre_impl_tkill@Base 4.9
+ __sanitizer_syscall_pre_impl_truncate@Base 4.9
+ __sanitizer_syscall_pre_impl_umask@Base 4.9
+ __sanitizer_syscall_pre_impl_umount@Base 4.9
+ __sanitizer_syscall_pre_impl_uname@Base 4.9
+ __sanitizer_syscall_pre_impl_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_unlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_unshare@Base 4.9
+ __sanitizer_syscall_pre_impl_uselib@Base 4.9
+ __sanitizer_syscall_pre_impl_ustat@Base 4.9
+ __sanitizer_syscall_pre_impl_utime@Base 4.9
+ __sanitizer_syscall_pre_impl_utimensat@Base 4.9
+ __sanitizer_syscall_pre_impl_utimes@Base 4.9
+ __sanitizer_syscall_pre_impl_vfork@Base 4.9
+ __sanitizer_syscall_pre_impl_vhangup@Base 4.9
+ __sanitizer_syscall_pre_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_pre_impl_wait4@Base 4.9
+ __sanitizer_syscall_pre_impl_waitid@Base 4.9
+ __sanitizer_syscall_pre_impl_waitpid@Base 4.9
+ __sanitizer_syscall_pre_impl_write@Base 4.9
+ __sanitizer_syscall_pre_impl_writev@Base 4.9
+ __sanitizer_unaligned_load16@Base 4.9
+ __sanitizer_unaligned_load32@Base 4.9
+ __sanitizer_unaligned_load64@Base 4.9
+ __sanitizer_unaligned_store16@Base 4.9
+ __sanitizer_unaligned_store32@Base 4.9
+ __sanitizer_unaligned_store64@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6
+ __sigsetjmp@Base 4.9
+ __tls_get_addr@Base 6
+ __tsan_acquire@Base 4.9
+ __tsan_atomic128_compare_exchange_strong@Base 4.9
+ __tsan_atomic128_compare_exchange_val@Base 4.9
+ __tsan_atomic128_compare_exchange_weak@Base 4.9
+ __tsan_atomic128_exchange@Base 4.9
+ __tsan_atomic128_fetch_add@Base 4.9
+ __tsan_atomic128_fetch_and@Base 4.9
+ __tsan_atomic128_fetch_nand@Base 4.9
+ __tsan_atomic128_fetch_or@Base 4.9
+ __tsan_atomic128_fetch_sub@Base 4.9
+ __tsan_atomic128_fetch_xor@Base 4.9
+ __tsan_atomic128_load@Base 4.9
+ __tsan_atomic128_store@Base 4.9
+ __tsan_atomic16_compare_exchange_strong@Base 4.9
+ __tsan_atomic16_compare_exchange_val@Base 4.9
+ __tsan_atomic16_compare_exchange_weak@Base 4.9
+ __tsan_atomic16_exchange@Base 4.9
+ __tsan_atomic16_fetch_add@Base 4.9
+ __tsan_atomic16_fetch_and@Base 4.9
+ __tsan_atomic16_fetch_nand@Base 4.9
+ __tsan_atomic16_fetch_or@Base 4.9
+ __tsan_atomic16_fetch_sub@Base 4.9
+ __tsan_atomic16_fetch_xor@Base 4.9
+ __tsan_atomic16_load@Base 4.9
+ __tsan_atomic16_store@Base 4.9
+ __tsan_atomic32_compare_exchange_strong@Base 4.9
+ __tsan_atomic32_compare_exchange_val@Base 4.9
+ __tsan_atomic32_compare_exchange_weak@Base 4.9
+ __tsan_atomic32_exchange@Base 4.9
+ __tsan_atomic32_fetch_add@Base 4.9
+ __tsan_atomic32_fetch_and@Base 4.9
+ __tsan_atomic32_fetch_nand@Base 4.9
+ __tsan_atomic32_fetch_or@Base 4.9
+ __tsan_atomic32_fetch_sub@Base 4.9
+ __tsan_atomic32_fetch_xor@Base 4.9
+ __tsan_atomic32_load@Base 4.9
+ __tsan_atomic32_store@Base 4.9
+ __tsan_atomic64_compare_exchange_strong@Base 4.9
+ __tsan_atomic64_compare_exchange_val@Base 4.9
+ __tsan_atomic64_compare_exchange_weak@Base 4.9
+ __tsan_atomic64_exchange@Base 4.9
+ __tsan_atomic64_fetch_add@Base 4.9
+ __tsan_atomic64_fetch_and@Base 4.9
+ __tsan_atomic64_fetch_nand@Base 4.9
+ __tsan_atomic64_fetch_or@Base 4.9
+ __tsan_atomic64_fetch_sub@Base 4.9
+ __tsan_atomic64_fetch_xor@Base 4.9
+ __tsan_atomic64_load@Base 4.9
+ __tsan_atomic64_store@Base 4.9
+ __tsan_atomic8_compare_exchange_strong@Base 4.9
+ __tsan_atomic8_compare_exchange_val@Base 4.9
+ __tsan_atomic8_compare_exchange_weak@Base 4.9
+ __tsan_atomic8_exchange@Base 4.9
+ __tsan_atomic8_fetch_add@Base 4.9
+ __tsan_atomic8_fetch_and@Base 4.9
+ __tsan_atomic8_fetch_nand@Base 4.9
+ __tsan_atomic8_fetch_or@Base 4.9
+ __tsan_atomic8_fetch_sub@Base 4.9
+ __tsan_atomic8_fetch_xor@Base 4.9
+ __tsan_atomic8_load@Base 4.9
+ __tsan_atomic8_store@Base 4.9
+ __tsan_atomic_signal_fence@Base 4.9
+ __tsan_atomic_thread_fence@Base 4.9
+ __tsan_default_options@Base 4.9
+ __tsan_func_entry@Base 4.9
+ __tsan_func_exit@Base 4.9
+ __tsan_init@Base 4.9
+ __tsan_java_acquire@Base 6
+ __tsan_java_alloc@Base 4.9
+ __tsan_java_finalize@Base 5
+ __tsan_java_fini@Base 4.9
+ __tsan_java_free@Base 4.9
+ __tsan_java_init@Base 4.9
+ __tsan_java_move@Base 4.9
+ __tsan_java_mutex_lock@Base 4.9
+ __tsan_java_mutex_lock_rec@Base 4.9
+ __tsan_java_mutex_read_lock@Base 4.9
+ __tsan_java_mutex_read_unlock@Base 4.9
+ __tsan_java_mutex_unlock@Base 4.9
+ __tsan_java_mutex_unlock_rec@Base 4.9
+ __tsan_java_release@Base 6
+ __tsan_java_release_store@Base 6
+ __tsan_read16@Base 4.9
+ __tsan_read16_pc@Base 6
+ __tsan_read1@Base 4.9
+ __tsan_read1_pc@Base 6
+ __tsan_read2@Base 4.9
+ __tsan_read2_pc@Base 6
+ __tsan_read4@Base 4.9
+ __tsan_read4_pc@Base 6
+ __tsan_read8@Base 4.9
+ __tsan_read8_pc@Base 6
+ __tsan_read_range@Base 4.9
+ __tsan_release@Base 4.9
+ __tsan_unaligned_read16@Base 6
+ __tsan_unaligned_read2@Base 4.9
+ __tsan_unaligned_read4@Base 4.9
+ __tsan_unaligned_read8@Base 4.9
+ __tsan_unaligned_write16@Base 6
+ __tsan_unaligned_write2@Base 4.9
+ __tsan_unaligned_write4@Base 4.9
+ __tsan_unaligned_write8@Base 4.9
+ __tsan_vptr_read@Base 4.9
+ __tsan_vptr_update@Base 4.9
+ __tsan_write16@Base 4.9
+ __tsan_write16_pc@Base 6
+ __tsan_write1@Base 4.9
+ __tsan_write1_pc@Base 6
+ __tsan_write2@Base 4.9
+ __tsan_write2_pc@Base 6
+ __tsan_write4@Base 4.9
+ __tsan_write4_pc@Base 6
+ __tsan_write8@Base 4.9
+ __tsan_write8_pc@Base 6
+ __tsan_write_range@Base 4.9
+ __uflow@Base 5
+ __underflow@Base 5
+ __woverflow@Base 5
+ __wuflow@Base 5
+ __wunderflow@Base 5
+ __xpg_strerror_r@Base 4.9
+ __xstat64@Base 4.9
+ __xstat@Base 4.9
+ _exit@Base 4.9
+ _obstack_begin@Base 5
+ _obstack_begin_1@Base 5
+ _obstack_newchunk@Base 5
+ _setjmp@Base 4.9
+ abort@Base 4.9
+ accept4@Base 4.9
+ accept@Base 4.9
+ aligned_alloc@Base 5
+ asctime@Base 4.9
+ asctime_r@Base 4.9
+ asprintf@Base 5
+ atexit@Base 4.9
+ backtrace@Base 4.9
+ backtrace_symbols@Base 4.9
+ bind@Base 4.9
+ calloc@Base 4.9
+ canonicalize_file_name@Base 4.9
+ capget@Base 5
+ capset@Base 5
+ cfree@Base 4.9
+ clock_getres@Base 4.9
+ clock_gettime@Base 4.9
+ clock_settime@Base 4.9
+ close@Base 4.9
+ closedir@Base 6
+ confstr@Base 4.9
+ connect@Base 4.9
+ creat64@Base 4.9
+ creat@Base 4.9
+ ctime@Base 4.9
+ ctime_r@Base 4.9
+ dl_iterate_phdr@Base 6
+ dlclose@Base 4.9
+ dlopen@Base 4.9
+ drand48_r@Base 4.9
+ dup2@Base 4.9
+ dup3@Base 4.9
+ dup@Base 4.9
+ endgrent@Base 5
+ endpwent@Base 5
+ epoll_create1@Base 4.9
+ epoll_create@Base 4.9
+ epoll_ctl@Base 4.9
+ epoll_wait@Base 4.9
+ ether_aton@Base 4.9
+ ether_aton_r@Base 4.9
+ ether_hostton@Base 4.9
+ ether_line@Base 4.9
+ ether_ntoa@Base 4.9
+ ether_ntoa_r@Base 4.9
+ ether_ntohost@Base 4.9
+ eventfd@Base 4.9
+ fclose@Base 4.9
+ fdopen@Base 5
+ fflush@Base 4.9
+ fgetxattr@Base 5
+ flistxattr@Base 5
+ fmemopen@Base 5
+ fopen64@Base 5
+ fopen@Base 4.9
+ fopencookie@Base 6
+ fork@Base 4.9
+ fprintf@Base 5
+ fread@Base 4.9
+ free@Base 4.9
+ freopen64@Base 5
+ freopen@Base 4.9
+ frexp@Base 4.9
+ frexpf@Base 4.9
+ frexpl@Base 4.9
+ fscanf@Base 4.9
+ fstat64@Base 4.9
+ fstat@Base 4.9
+ fstatfs64@Base 4.9
+ fstatfs@Base 4.9
+ fstatvfs64@Base 4.9
+ fstatvfs@Base 4.9
+ ftime@Base 5
+ fwrite@Base 4.9
+ get_current_dir_name@Base 4.9
+ getaddrinfo@Base 4.9
+ getcwd@Base 4.9
+ getdelim@Base 4.9
+ getgroups@Base 4.9
+ gethostbyaddr@Base 4.9
+ gethostbyaddr_r@Base 4.9
+ gethostbyname2@Base 4.9
+ gethostbyname2_r@Base 4.9
+ gethostbyname@Base 4.9
+ gethostbyname_r@Base 4.9
+ gethostent@Base 4.9
+ gethostent_r@Base 4.9
+ getifaddrs@Base 5
+ getitimer@Base 4.9
+ getline@Base 4.9
+ getmntent@Base 4.9
+ getmntent_r@Base 4.9
+ getnameinfo@Base 5
+ getpass@Base 5
+ getpeername@Base 4.9
+ getresgid@Base 5
+ getresuid@Base 5
+ getsockname@Base 4.9
+ getsockopt@Base 4.9
+ gettimeofday@Base 4.9
+ getxattr@Base 5
+ glob64@Base 5
+ glob@Base 5
+ gmtime@Base 4.9
+ gmtime_r@Base 4.9
+ iconv@Base 4.9
+ if_indextoname@Base 5
+ if_nametoindex@Base 5
+ inet_aton@Base 4.9
+ inet_ntop@Base 4.9
+ inet_pton@Base 4.9
+ initgroups@Base 4.9
+ inotify_init1@Base 4.9
+ inotify_init@Base 4.9
+ ioctl@Base 4.9
+ kill@Base 4.9
+ lgamma@Base 4.9
+ lgamma_r@Base 4.9
+ lgammaf@Base 4.9
+ lgammaf_r@Base 4.9
+ lgammal@Base 4.9
+ lgammal_r@Base 4.9
+ lgetxattr@Base 5
+ listen@Base 4.9
+ listxattr@Base 5
+ llistxattr@Base 5
+ localtime@Base 4.9
+ localtime_r@Base 4.9
+ longjmp@Base 4.9
+ lrand48_r@Base 4.9
+ lstat64@Base 4.9
+ lstat@Base 4.9
+ malloc@Base 4.9
+ malloc_usable_size@Base 4.9
+ mbsnrtowcs@Base 4.9
+ mbsrtowcs@Base 4.9
+ mbstowcs@Base 4.9
+ memalign@Base 4.9
+ memchr@Base 4.9
+ memcmp@Base 4.9
+ memcpy@Base 4.9
+ memmove@Base 4.9
+ memrchr@Base 4.9
+ memset@Base 4.9
+ mincore@Base 6
+ mktime@Base 5
+ mlock@Base 4.9
+ mlockall@Base 4.9
+ mmap64@Base 4.9
+ mmap@Base 4.9
+ modf@Base 4.9
+ modff@Base 4.9
+ modfl@Base 4.9
+ munlock@Base 4.9
+ munlockall@Base 4.9
+ munmap@Base 4.9
+ nanosleep@Base 4.9
+ on_exit@Base 4.9
+ open64@Base 4.9
+ open@Base 4.9
+ open_memstream@Base 5
+ open_wmemstream@Base 5
+ opendir@Base 4.9
+ pipe2@Base 4.9
+ pipe@Base 4.9
+ poll@Base 4.9
+ posix_memalign@Base 4.9
+ ppoll@Base 4.9
+ prctl@Base 4.9
+ pread64@Base 4.9
+ pread@Base 4.9
+ preadv64@Base 4.9
+ preadv@Base 4.9
+ printf@Base 5
+ process_vm_readv@Base 6
+ process_vm_writev@Base 6
+ pthread_attr_getaffinity_np@Base 4.9
+ pthread_attr_getdetachstate@Base 4.9
+ pthread_attr_getguardsize@Base 4.9
+ pthread_attr_getinheritsched@Base 4.9
+ pthread_attr_getschedparam@Base 4.9
+ pthread_attr_getschedpolicy@Base 4.9
+ pthread_attr_getscope@Base 4.9
+ pthread_attr_getstack@Base 4.9
+ pthread_attr_getstacksize@Base 4.9
+ pthread_barrier_destroy@Base 4.9
+ pthread_barrier_init@Base 4.9
+ pthread_barrier_wait@Base 4.9
+ pthread_barrierattr_getpshared@Base 5
+ pthread_cond_broadcast@Base 4.9
+ pthread_cond_destroy@Base 4.9
+ pthread_cond_init@Base 4.9
+ pthread_cond_signal@Base 4.9
+ pthread_cond_timedwait@Base 4.9
+ pthread_cond_wait@Base 4.9
+ pthread_condattr_getclock@Base 5
+ pthread_condattr_getpshared@Base 5
+ pthread_create@Base 4.9
+ pthread_detach@Base 4.9
+ pthread_getschedparam@Base 4.9
+ pthread_join@Base 4.9
+ pthread_kill@Base 4.9
+ pthread_mutex_destroy@Base 4.9
+ pthread_mutex_init@Base 4.9
+ pthread_mutex_lock@Base 4.9
+ pthread_mutex_timedlock@Base 4.9
+ pthread_mutex_trylock@Base 4.9
+ pthread_mutex_unlock@Base 4.9
+ pthread_mutexattr_getprioceiling@Base 5
+ pthread_mutexattr_getprotocol@Base 5
+ pthread_mutexattr_getpshared@Base 5
+ pthread_mutexattr_getrobust@Base 5
+ pthread_mutexattr_getrobust_np@Base 5
+ pthread_mutexattr_gettype@Base 5
+ pthread_once@Base 4.9
+ pthread_rwlock_destroy@Base 4.9
+ pthread_rwlock_init@Base 4.9
+ pthread_rwlock_rdlock@Base 4.9
+ pthread_rwlock_timedrdlock@Base 4.9
+ pthread_rwlock_timedwrlock@Base 4.9
+ pthread_rwlock_tryrdlock@Base 4.9
+ pthread_rwlock_trywrlock@Base 4.9
+ pthread_rwlock_unlock@Base 4.9
+ pthread_rwlock_wrlock@Base 4.9
+ pthread_rwlockattr_getkind_np@Base 5
+ pthread_rwlockattr_getpshared@Base 5
+ pthread_setcancelstate@Base 6
+ pthread_setcanceltype@Base 6
+ pthread_setname_np@Base 4.9
+ pthread_spin_destroy@Base 4.9
+ pthread_spin_init@Base 4.9
+ pthread_spin_lock@Base 4.9
+ pthread_spin_trylock@Base 4.9
+ pthread_spin_unlock@Base 4.9
+ ptrace@Base 4.9
+ puts@Base 4.9
+ pvalloc@Base 4.9
+ pwrite64@Base 4.9
+ pwrite@Base 4.9
+ pwritev64@Base 4.9
+ pwritev@Base 4.9
+ raise@Base 4.9
+ rand_r@Base 5
+ random_r@Base 4.9
+ read@Base 4.9
+ readdir64@Base 4.9
+ readdir64_r@Base 4.9
+ readdir@Base 4.9
+ readdir_r@Base 4.9
+ readv@Base 4.9
+ realloc@Base 4.9
+ realpath@Base 4.9
+ recv@Base 4.9
+ recvmsg@Base 4.9
+ remquo@Base 4.9
+ remquof@Base 4.9
+ remquol@Base 4.9
+ rmdir@Base 4.9
+ scandir64@Base 4.9
+ scandir@Base 4.9
+ scanf@Base 4.9
+ sched_getaffinity@Base 4.9
+ sched_getparam@Base 6
+ sem_destroy@Base 4.9
+ sem_getvalue@Base 4.9
+ sem_init@Base 4.9
+ sem_post@Base 4.9
+ sem_timedwait@Base 4.9
+ sem_trywait@Base 4.9
+ sem_wait@Base 4.9
+ send@Base 4.9
+ sendmsg@Base 4.9
+ setgrent@Base 5
+ setitimer@Base 4.9
+ setjmp@Base 4.9
+ setlocale@Base 4.9
+ setpwent@Base 5
+ shmctl@Base 4.9
+ sigaction@Base 4.9
+ sigemptyset@Base 4.9
+ sigfillset@Base 4.9
+ siglongjmp@Base 4.9
+ signal@Base 4.9
+ signalfd@Base 4.9
+ sigpending@Base 4.9
+ sigprocmask@Base 4.9
+ sigsetjmp@Base 4.9
+ sigsuspend@Base 4.9
+ sigtimedwait@Base 4.9
+ sigwait@Base 4.9
+ sigwaitinfo@Base 4.9
+ sincos@Base 4.9
+ sincosf@Base 4.9
+ sincosl@Base 4.9
+ sleep@Base 4.9
+ snprintf@Base 5
+ socket@Base 4.9
+ socketpair@Base 4.9
+ sprintf@Base 5
+ sscanf@Base 4.9
+ stat64@Base 4.9
+ stat@Base 4.9
+ statfs64@Base 4.9
+ statfs@Base 4.9
+ statvfs64@Base 4.9
+ statvfs@Base 4.9
+ strcasecmp@Base 4.9
+ strcasestr@Base 6
+ strchr@Base 4.9
+ strchrnul@Base 4.9
+ strcmp@Base 4.9
+ strcpy@Base 4.9
+ strcspn@Base 6
+ strdup@Base 4.9
+ strerror@Base 4.9
+ strerror_r@Base 4.9
+ strlen@Base 4.9
+ strncasecmp@Base 4.9
+ strncmp@Base 4.9
+ strncpy@Base 4.9
+ strpbrk@Base 6
+ strptime@Base 4.9
+ strrchr@Base 4.9
+ strspn@Base 6
+ strstr@Base 4.9
+ strtoimax@Base 4.9
+ strtoumax@Base 4.9
+ sysinfo@Base 4.9
+ tcgetattr@Base 4.9
+ tempnam@Base 4.9
+ textdomain@Base 4.9
+ time@Base 4.9
+ timerfd_gettime@Base 5
+ timerfd_settime@Base 5
+ times@Base 4.9
+ tmpfile64@Base 5
+ tmpfile@Base 5
+ tmpnam@Base 4.9
+ tmpnam_r@Base 4.9
+ tsearch@Base 5
+ unlink@Base 4.9
+ usleep@Base 4.9
+ valloc@Base 4.9
+ vasprintf@Base 5
+ vfork@Base 5
+ vfprintf@Base 5
+ vfscanf@Base 4.9
+ vprintf@Base 5
+ vscanf@Base 4.9
+ vsnprintf@Base 5
+ vsprintf@Base 5
+ vsscanf@Base 4.9
+ wait3@Base 4.9
+ wait4@Base 4.9
+ wait@Base 4.9
+ waitid@Base 4.9
+ waitpid@Base 4.9
+ wcrtomb@Base 6
+ wcsnrtombs@Base 4.9
+ wcsrtombs@Base 4.9
+ wcstombs@Base 4.9
+ wordexp@Base 4.9
+ write@Base 4.9
+ writev@Base 4.9
+ xdr_bool@Base 5
+ xdr_bytes@Base 5
+ xdr_char@Base 5
+ xdr_double@Base 5
+ xdr_enum@Base 5
+ xdr_float@Base 5
+ xdr_hyper@Base 5
+ xdr_int16_t@Base 5
+ xdr_int32_t@Base 5
+ xdr_int64_t@Base 5
+ xdr_int8_t@Base 5
+ xdr_int@Base 5
+ xdr_long@Base 5
+ xdr_longlong_t@Base 5
+ xdr_quad_t@Base 5
+ xdr_short@Base 5
+ xdr_string@Base 5
+ xdr_u_char@Base 5
+ xdr_u_hyper@Base 5
+ xdr_u_int@Base 5
+ xdr_u_long@Base 5
+ xdr_u_longlong_t@Base 5
+ xdr_u_quad_t@Base 5
+ xdr_u_short@Base 5
+ xdr_uint16_t@Base 5
+ xdr_uint32_t@Base 5
+ xdr_uint64_t@Base 5
+ xdr_uint8_t@Base 5
+ xdrmem_create@Base 5
+ xdrstdio_create@Base 5
--- gcc-6-6.3.0.orig/debian/libubsan0.symbols
+++ gcc-6-6.3.0/debian/libubsan0.symbols
@@ -0,0 +1,100 @@
+libubsan.so.0 libubsan0 #MINVER#
+ _ZN11__sanitizer11CheckFailedEPKciS1_yy@Base 4.9
+ _ZN11__sanitizer7OnPrintEPKc@Base 4.9
+ __asan_backtrace_alloc@Base 4.9
+ __asan_backtrace_close@Base 4.9
+ __asan_backtrace_create_state@Base 4.9
+ __asan_backtrace_dwarf_add@Base 4.9
+ __asan_backtrace_free@Base 4.9
+ __asan_backtrace_get_view@Base 4.9
+ __asan_backtrace_initialize@Base 4.9
+ __asan_backtrace_open@Base 4.9
+ __asan_backtrace_pcinfo@Base 4.9
+ __asan_backtrace_qsort@Base 4.9
+ __asan_backtrace_release_view@Base 4.9
+ __asan_backtrace_syminfo@Base 4.9
+ __asan_backtrace_vector_finish@Base 4.9
+ __asan_backtrace_vector_grow@Base 4.9
+ __asan_backtrace_vector_release@Base 4.9
+ __asan_cplus_demangle_builtin_types@Base 4.9
+ __asan_cplus_demangle_fill_ctor@Base 4.9
+ __asan_cplus_demangle_fill_dtor@Base 4.9
+ __asan_cplus_demangle_fill_extended_operator@Base 4.9
+ __asan_cplus_demangle_fill_name@Base 4.9
+ __asan_cplus_demangle_init_info@Base 4.9
+ __asan_cplus_demangle_mangled_name@Base 4.9
+ __asan_cplus_demangle_operators@Base 4.9
+ __asan_cplus_demangle_print@Base 4.9
+ __asan_cplus_demangle_print_callback@Base 4.9
+ __asan_cplus_demangle_type@Base 4.9
+ __asan_cplus_demangle_v3@Base 4.9
+ __asan_cplus_demangle_v3_callback@Base 4.9
+ __asan_internal_memcmp@Base 4.9
+ __asan_internal_memcpy@Base 4.9
+ __asan_internal_memset@Base 4.9
+ __asan_internal_strcmp@Base 4.9
+ __asan_internal_strlen@Base 4.9
+ __asan_internal_strncmp@Base 4.9
+ __asan_internal_strnlen@Base 4.9
+ __asan_is_gnu_v3_mangled_ctor@Base 4.9
+ __asan_is_gnu_v3_mangled_dtor@Base 4.9
+ __asan_java_demangle_v3@Base 4.9
+ __asan_java_demangle_v3_callback@Base 4.9
+ __sanitizer_cov@Base 4.9
+ __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_cov_trace_basic_block@Base 6
+ __sanitizer_cov_trace_cmp@Base 6
+ __sanitizer_cov_trace_func_enter@Base 6
+ __sanitizer_cov_trace_switch@Base 6
+ __sanitizer_cov_with_check@Base 6
+ __sanitizer_get_coverage_guards@Base 6
+ __sanitizer_get_number_of_counters@Base 6
+ __sanitizer_get_total_unique_caller_callee_pairs@Base 6
+ __sanitizer_get_total_unique_coverage@Base 6
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_report_error_summary@Base 4.9
+ __sanitizer_reset_coverage@Base 6
+ __sanitizer_sandbox_on_notify@Base 4.9
+ __sanitizer_set_death_callback@Base 6
+ __sanitizer_set_report_path@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6
+ __ubsan_handle_add_overflow@Base 4.9
+ __ubsan_handle_add_overflow_abort@Base 4.9
+ __ubsan_handle_builtin_unreachable@Base 4.9
+ __ubsan_handle_cfi_bad_icall@Base 6
+ __ubsan_handle_cfi_bad_icall_abort@Base 6
+ __ubsan_handle_cfi_bad_type@Base 6
+ __ubsan_handle_cfi_bad_type_abort@Base 6
+ __ubsan_handle_divrem_overflow@Base 4.9
+ __ubsan_handle_divrem_overflow_abort@Base 4.9
+ __ubsan_handle_dynamic_type_cache_miss@Base 4.9
+ __ubsan_handle_dynamic_type_cache_miss_abort@Base 4.9
+ __ubsan_handle_float_cast_overflow@Base 4.9
+ __ubsan_handle_float_cast_overflow_abort@Base 4.9
+ __ubsan_handle_function_type_mismatch@Base 4.9
+ __ubsan_handle_function_type_mismatch_abort@Base 4.9
+ __ubsan_handle_load_invalid_value@Base 4.9
+ __ubsan_handle_load_invalid_value_abort@Base 4.9
+ __ubsan_handle_missing_return@Base 4.9
+ __ubsan_handle_mul_overflow@Base 4.9
+ __ubsan_handle_mul_overflow_abort@Base 4.9
+ __ubsan_handle_negate_overflow@Base 4.9
+ __ubsan_handle_negate_overflow_abort@Base 4.9
+ __ubsan_handle_nonnull_arg@Base 5
+ __ubsan_handle_nonnull_arg_abort@Base 5
+ __ubsan_handle_nonnull_return@Base 5
+ __ubsan_handle_nonnull_return_abort@Base 5
+ __ubsan_handle_out_of_bounds@Base 4.9
+ __ubsan_handle_out_of_bounds_abort@Base 4.9
+ __ubsan_handle_shift_out_of_bounds@Base 4.9
+ __ubsan_handle_shift_out_of_bounds_abort@Base 4.9
+ __ubsan_handle_sub_overflow@Base 4.9
+ __ubsan_handle_sub_overflow_abort@Base 4.9
+ __ubsan_handle_type_mismatch@Base 4.9
+ __ubsan_handle_type_mismatch_abort@Base 4.9
+ __ubsan_handle_vla_bound_not_positive@Base 4.9
+ __ubsan_handle_vla_bound_not_positive_abort@Base 4.9
+ __ubsan_vptr_type_cache@Base 4.9
--- gcc-6-6.3.0.orig/debian/libvtv0.symbols
+++ gcc-6-6.3.0/debian/libvtv0.symbols
@@ -0,0 +1,68 @@
+libvtv.so.0 libvtv0 #MINVER#
+ _Z10__vtv_freePv@Base 4.9.0
+ (arch=amd64)_Z12__vtv_mallocm@Base 4.9.0
+ (arch=i386)_Z12__vtv_mallocj@Base 4.9.0
+ _Z14__VLTDumpStatsv@Base 4.9.0
+ _Z14__vtv_open_logPKc@Base 4.9.0
+ (arch=amd64)_Z16__VLTRegisterSetPPvPKvmmS0_@Base 4.9.0
+ (arch=i386)_Z16__VLTRegisterSetPPvPKvjjS0_@Base 4.9.0
+ _Z16__vtv_add_to_logiPKcz@Base 4.9.0
+ (arch=amd64)_Z17__VLTRegisterPairPPvPKvmS2_@Base 4.9.0
+ (arch=i386)_Z17__VLTRegisterPairPPvPKvjS2_@Base 4.9.0
+ _Z17__vtv_malloc_initv@Base 4.9.0
+ _Z17__vtv_really_failPKc@Base 4.9.0
+ _Z17__vtv_verify_failPPvPKv@Base 4.9.0
+ _Z18__vtv_malloc_statsv@Base 4.9.0
+ _Z20__vtv_malloc_protectv@Base 4.9.0
+ (arch=amd64)_Z21__VLTRegisterSetDebugPPvPKvmmS0_@Base 4.9.0
+ (arch=i386)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@Base 4.9.0
+ (arch=amd64)_Z22__VLTRegisterPairDebugPPvPKvmS2_PKcS4_@Base 4.9.0
+ (arch=i386)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@Base 4.9.0
+ _Z22__vtv_malloc_unprotectv@Base 4.9.0
+ _Z23__vtv_malloc_dump_statsv@Base 4.9.0
+ _Z23__vtv_verify_fail_debugPPvPKvPKc@Base 4.9.0
+ (arch=amd64)_Z23search_cached_file_datam@Base 4.9.0
+ (arch=i386)_Z23search_cached_file_dataj@Base 4.9.0
+ _Z24__VLTVerifyVtablePointerPPvPKv@Base 4.9.0
+ _Z25__vtv_count_mmapped_pagesv@Base 4.9.0
+ _Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@Base 4.9.0
+ _Z30__vtv_log_verification_failurePKcb@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12put_internalEPKNS8_8key_typeERKS6_b@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE15find_or_add_keyEPKNS8_8key_typeEPPS6_@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE16destructive_copyEv@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3putEPKNS8_8key_typeERKS6_@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE6createEm@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE7destroyEPS8_@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE11is_too_fullEm@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12bucket_countEv@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3getEPKNS8_8key_typeE@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE4sizeEv@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE5emptyEv@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE8key_type6equalsEPKS9_@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12put_internalEPKNS8_8key_typeERKS6_b@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE15find_or_add_keyEPKNS8_8key_typeEPPS6_@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE16destructive_copyEv@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3putEPKNS8_8key_typeERKS6_@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE6createEj@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE7destroyEPS8_@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE11is_too_fullEj@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12bucket_countEv@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3getEPKNS8_8key_typeE@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE4sizeEv@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE5emptyEv@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE8key_type6equalsEPKS9_@Base 4.9.0
+ __VLTChangePermission@Base 4.9.0
+ __VLTprotect@Base 4.9.0
+ __VLTunprotect@Base 4.9.0
+ _vtable_map_vars_end@Base 4.9.0
+ _vtable_map_vars_start@Base 4.9.0
+ mprotect_cycles@Base 4.9.0
+ num_cache_entries@Base 4.9.0
+ num_calls_to_mprotect@Base 4.9.0
+ num_calls_to_regpair@Base 4.9.0
+ num_calls_to_regset@Base 4.9.0
+ num_calls_to_verify_vtable@Base 4.9.0
+ num_pages_protected@Base 4.9.0
+ regpair_cycles@Base 4.9.0
+ regset_cycles@Base 4.9.0
+ verify_vtable_cycles@Base 4.9.0
--- gcc-6-6.3.0.orig/debian/libx32asan3.overrides
+++ gcc-6-6.3.0/debian/libx32asan3.overrides
@@ -0,0 +1,2 @@
+# automake gets it wrong for the multilib build
+libx32asan3 binary: binary-or-shlib-defines-rpath
--- gcc-6-6.3.0.orig/debian/libx32asan3.symbols
+++ gcc-6-6.3.0/debian/libx32asan3.symbols
@@ -0,0 +1,4 @@
+libasan.so.3 libx32asan3 #MINVER#
+#include "libasan.symbols.common"
+#include "libasan.symbols.32"
+#include "libasan.symbols.16"
--- gcc-6-6.3.0.orig/debian/libx32gphobos68.lintian-overrides
+++ gcc-6-6.3.0/debian/libx32gphobos68.lintian-overrides
@@ -0,0 +1,2 @@
+# no multilib zlib for x32
+libx32gphobos68 binary: embedded-library
--- gcc-6-6.3.0.orig/debian/libx32stdc++6.symbols
+++ gcc-6-6.3.0/debian/libx32stdc++6.symbols
@@ -0,0 +1,27 @@
+libstdc++.so.6 libx32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
+ _ZTIPKn@CXXABI_1.3.5 4.9.0
+ _ZTIPKo@CXXABI_1.3.5 4.9.0
+ _ZTIPn@CXXABI_1.3.5 4.9.0
+ _ZTIPo@CXXABI_1.3.5 4.9.0
+ _ZTIn@CXXABI_1.3.5 4.9.0
+ _ZTIo@CXXABI_1.3.5 4.9.0
+ _ZTSPKn@CXXABI_1.3.9 4.9.0
+ _ZTSPKo@CXXABI_1.3.9 4.9.0
+ _ZTSPn@CXXABI_1.3.9 4.9.0
+ _ZTSPo@CXXABI_1.3.9 4.9.0
+ _ZTSn@CXXABI_1.3.9 4.9.0
+ _ZTSo@CXXABI_1.3.9 4.9.0
--- gcc-6-6.3.0.orig/debian/locale-gen
+++ gcc-6-6.3.0/debian/locale-gen
@@ -0,0 +1,50 @@
+#!/bin/sh
+
+# generate locales that the libstdc++ testsuite depends on
+
+LOCPATH=`pwd`/locales
+export LOCPATH
+
+[ -d $LOCPATH ] || mkdir -p $LOCPATH
+
+[ -n "$USE_CPUS" ] || USE_CPUS=1
+
+umask 022
+
+echo "Generating locales..."
+xargs -L 1 -P $USE_CPUS -I{} \
+    sh -c '
+	set {}; locale=$1; charset=$2
+	case $locale in \#*) exit;; esac
+	[ -n "$locale" -a -n "$charset" ] || exit
+	echo "  `echo $locale | sed \"s/\([^.\@]*\).*/\1/\"`.$charset`echo $locale | sed \"s/\([^\@]*\)\(\@.*\)*/\2/\"`..."
+        if [ -f $LOCPATH/$locale ]; then
+	    input=$locale
+	else
+            input=`echo $locale | sed "s/\([^.]*\)[^@]*\(.*\)/\1\2/"`
+	fi
+	localedef -i $input -c -f $charset $LOCPATH/$locale #-A /etc/locale.alias
+    ' <<EOF
+de_DE			ISO-8859-1
+de_DE@euro		ISO-8859-15
+en_HK			ISO-8859-1
+en_PH			ISO-8859-1
+en_US			ISO-8859-1
+en_US.ISO-8859-1	ISO-8859-1
+en_US.ISO-8859-15	ISO-8859-15
+en_US.UTF-8		UTF-8
+es_ES			ISO-8859-1
+es_MX			ISO-8859-1
+fr_FR			ISO-8859-1
+fr_FR@euro		ISO-8859-15
+is_IS			ISO-8859-1
+is_IS.UTF-8		UTF-8
+it_IT			ISO-8859-1
+ja_JP.eucjp		EUC-JP
+se_NO.UTF-8		UTF-8
+ta_IN			UTF-8
+zh_TW			BIG5
+zh_TW			UTF-8
+EOF
+
+echo "Generation complete."
--- gcc-6-6.3.0.orig/debian/logwatch.sh
+++ gcc-6-6.3.0/debian/logwatch.sh
@@ -0,0 +1,104 @@
+#! /bin/sh
+
+# script to trick the build daemons and output something, if there is
+# still test/build activity
+
+# $1: primary file to watch. if there is activity on this file, we do nothing
+# $2+: files to watch to look for activity despite no output in $1
+#      if the files are modified or are newly created, then the message
+#      is printed on stdout.
+#      if nothing is modified, don't output anything (so the buildd timeout
+#      hits).
+
+pidfile=logwatch.pid
+timeout=3600
+message='\nlogwatch still running\n'
+
+usage()
+{
+    echo >&2 "usage: `basename $0` [-p <pidfile>] [-t <timeout>] [-m <message>]"
+    echo >&2 "           <logfile> [<logfile> ...]"
+    exit 1
+}
+
+while [ $# -gt 0 ]; do
+    case $1 in
+    -p)
+	pidfile=$2
+	shift
+	shift
+	;;
+    -t)
+	timeout=$2
+	shift
+	shift
+	;;
+    -m)
+	message="$2"
+	shift
+	shift
+	;;
+    -*)
+	usage
+	;;
+    *)
+	break
+    esac
+done
+
+[ $# -gt 0 ] || usage
+
+logfile="$1"
+shift
+otherlogs="$@"
+
+cleanup()
+{
+    rm -f $pidfile
+    exit 0
+}
+
+#trap cleanup 0 1 3 15
+
+echo $$ > $pidfile
+
+update()
+{
+    _logvar=$1
+    _othervar=$2
+
+    # logfile may not exist yet
+    if [ -r $logfile ]; then
+	_logtail="`tail -10 $logfile | md5sum` $f"
+    else
+	_logtail="does not exist: $logfile"
+    fi
+    eval $_logvar="'$_logtail'"
+
+    _othertails=''
+    for f in $otherlogs; do
+	if [ -r $f ]; then
+	    _othertails="$_othertails `tail -10 $f | md5sum` $f"
+	else
+	    _othertails="$_othertails does not exist: $f"
+	fi
+    done
+    eval $_othervar="'$_othertails'"
+}
+
+update logtail othertails
+while true; do
+    sleep $timeout
+    update newlogtail newothertails
+    if [ "$logtail" != "$newlogtail" ]; then
+	# there is still action in the primary logfile. do nothing.
+	logtail="$newlogtail"
+    elif [ "$othertails" != "$newothertails" ]; then
+	# there is still action in the other log files, so print the message
+	/bin/echo -e $message
+	othertails="$newothertails"
+    else
+	# nothing changed in the other log files. maybe a timeout ...
+	:
+    fi
+done
--- gcc-6-6.3.0.orig/debian/patches/CVE-2016-9840.diff
+++ gcc-6-6.3.0/debian/patches/CVE-2016-9840.diff
@@ -0,0 +1,69 @@
+commit 6a043145ca6e9c55184013841a67b2fef87e44c0
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Wed Sep 21 23:35:50 2016 -0700
+
+    Remove offset pointer optimization in inftrees.c.
+    
+    inftrees.c was subtracting an offset from a pointer to an array,
+    in order to provide a pointer that allowed indexing starting at
+    the offset. This is not compliant with the C standard, for which
+    the behavior of a pointer decremented before its allocated memory
+    is undefined. Per the recommendation of a security audit of the
+    zlib code by Trail of Bits and TrustInSoft, in support of the
+    Mozilla Foundation, this tiny optimization was removed, in order
+    to avoid the possibility of undefined behavior.
+
+diff --git a/inftrees.c b/inftrees.c
+index 22fcd66..0d2670d 100644
+--- a/src/zlib/inftrees.c
++++ b/src/zlib/inftrees.c
+@@ -54,7 +54,7 @@ unsigned short FAR *work;
+     code FAR *next;             /* next available space in table */
+     const unsigned short FAR *base;     /* base value table to use */
+     const unsigned short FAR *extra;    /* extra bits table to use */
+-    int end;                    /* use base and extra for symbol > end */
++    unsigned match;             /* use base and extra for symbol >= match */
+     unsigned short count[MAXBITS+1];    /* number of codes of each length */
+     unsigned short offs[MAXBITS+1];     /* offsets in table for each length */
+     static const unsigned short lbase[31] = { /* Length codes 257..285 base */
+@@ -181,19 +181,17 @@ unsigned short FAR *work;
+     switch (type) {
+     case CODES:
+         base = extra = work;    /* dummy value--not used */
+-        end = 19;
++        match = 20;
+         break;
+     case LENS:
+         base = lbase;
+-        base -= 257;
+         extra = lext;
+-        extra -= 257;
+-        end = 256;
++        match = 257;
+         break;
+     default:            /* DISTS */
+         base = dbase;
+         extra = dext;
+-        end = -1;
++        match = 0;
+     }
+ 
+     /* initialize state for loop */
+@@ -216,13 +214,13 @@ unsigned short FAR *work;
+     for (;;) {
+         /* create table entry */
+         here.bits = (unsigned char)(len - drop);
+-        if ((int)(work[sym]) < end) {
++        if (work[sym] + 1 < match) {
+             here.op = (unsigned char)0;
+             here.val = work[sym];
+         }
+-        else if ((int)(work[sym]) > end) {
+-            here.op = (unsigned char)(extra[work[sym]]);
+-            here.val = base[work[sym]];
++        else if (work[sym] >= match) {
++            here.op = (unsigned char)(extra[work[sym] - match]);
++            here.val = base[work[sym] - match];
+         }
+         else {
+             here.op = (unsigned char)(32 + 64);         /* end of block */
--- gcc-6-6.3.0.orig/debian/patches/CVE-2016-9841.diff
+++ gcc-6-6.3.0/debian/patches/CVE-2016-9841.diff
@@ -0,0 +1,222 @@
+commit 9aaec95e82117c1cb0f9624264c3618fc380cecb
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Wed Sep 21 22:25:21 2016 -0700
+
+    Use post-increment only in inffast.c.
+    
+    An old inffast.c optimization turns out to not be optimal anymore
+    with modern compilers, and furthermore was not compliant with the
+    C standard, for which decrementing a pointer before its allocated
+    memory is undefined. Per the recommendation of a security audit of
+    the zlib code by Trail of Bits and TrustInSoft, in support of the
+    Mozilla Foundation, this "optimization" was removed, in order to
+    avoid the possibility of undefined behavior.
+
+diff --git a/inffast.c b/inffast.c
+index bda59ce..f0d163d 100644
+--- a/src/zlib/inffast.c
++++ b/src/zlib/inffast.c
+@@ -10,25 +10,6 @@
+ 
+ #ifndef ASMINF
+ 
+-/* Allow machine dependent optimization for post-increment or pre-increment.
+-   Based on testing to date,
+-   Pre-increment preferred for:
+-   - PowerPC G3 (Adler)
+-   - MIPS R5000 (Randers-Pehrson)
+-   Post-increment preferred for:
+-   - none
+-   No measurable difference:
+-   - Pentium III (Anderson)
+-   - M68060 (Nikl)
+- */
+-#ifdef POSTINC
+-#  define OFF 0
+-#  define PUP(a) *(a)++
+-#else
+-#  define OFF 1
+-#  define PUP(a) *++(a)
+-#endif
+-
+ /*
+    Decode literal, length, and distance codes and write out the resulting
+    literal and match bytes until either not enough input or output is
+@@ -96,9 +77,9 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+ 
+     /* copy state to local variables */
+     state = (struct inflate_state FAR *)strm->state;
+-    in = strm->next_in - OFF;
++    in = strm->next_in;
+     last = in + (strm->avail_in - 5);
+-    out = strm->next_out - OFF;
++    out = strm->next_out;
+     beg = out - (start - strm->avail_out);
+     end = out + (strm->avail_out - 257);
+ #ifdef INFLATE_STRICT
+@@ -119,9 +100,9 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+        input data or output space */
+     do {
+         if (bits < 15) {
+-            hold += (unsigned long)(PUP(in)) << bits;
++            hold += (unsigned long)(*in++) << bits;
+             bits += 8;
+-            hold += (unsigned long)(PUP(in)) << bits;
++            hold += (unsigned long)(*in++) << bits;
+             bits += 8;
+         }
+         here = lcode[hold & lmask];
+@@ -134,14 +115,14 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+             Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?
+                     "inflate:         literal '%c'\n" :
+                     "inflate:         literal 0x%02x\n", here.val));
+-            PUP(out) = (unsigned char)(here.val);
++            *out++ = (unsigned char)(here.val);
+         }
+         else if (op & 16) {                     /* length base */
+             len = (unsigned)(here.val);
+             op &= 15;                           /* number of extra bits */
+             if (op) {
+                 if (bits < op) {
+-                    hold += (unsigned long)(PUP(in)) << bits;
++                    hold += (unsigned long)(*in++) << bits;
+                     bits += 8;
+                 }
+                 len += (unsigned)hold & ((1U << op) - 1);
+@@ -150,9 +131,9 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+             }
+             Tracevv((stderr, "inflate:         length %u\n", len));
+             if (bits < 15) {
+-                hold += (unsigned long)(PUP(in)) << bits;
++                hold += (unsigned long)(*in++) << bits;
+                 bits += 8;
+-                hold += (unsigned long)(PUP(in)) << bits;
++                hold += (unsigned long)(*in++) << bits;
+                 bits += 8;
+             }
+             here = dcode[hold & dmask];
+@@ -165,10 +146,10 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+                 dist = (unsigned)(here.val);
+                 op &= 15;                       /* number of extra bits */
+                 if (bits < op) {
+-                    hold += (unsigned long)(PUP(in)) << bits;
++                    hold += (unsigned long)(*in++) << bits;
+                     bits += 8;
+                     if (bits < op) {
+-                        hold += (unsigned long)(PUP(in)) << bits;
++                        hold += (unsigned long)(*in++) << bits;
+                         bits += 8;
+                     }
+                 }
+@@ -196,30 +177,30 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+ #ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR
+                         if (len <= op - whave) {
+                             do {
+-                                PUP(out) = 0;
++                                *out++ = 0;
+                             } while (--len);
+                             continue;
+                         }
+                         len -= op - whave;
+                         do {
+-                            PUP(out) = 0;
++                            *out++ = 0;
+                         } while (--op > whave);
+                         if (op == 0) {
+                             from = out - dist;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--len);
+                             continue;
+                         }
+ #endif
+                     }
+-                    from = window - OFF;
++                    from = window;
+                     if (wnext == 0) {           /* very common case */
+                         from += wsize - op;
+                         if (op < len) {         /* some from window */
+                             len -= op;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--op);
+                             from = out - dist;  /* rest from output */
+                         }
+@@ -230,14 +211,14 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+                         if (op < len) {         /* some from end of window */
+                             len -= op;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--op);
+-                            from = window - OFF;
++                            from = window;
+                             if (wnext < len) {  /* some from start of window */
+                                 op = wnext;
+                                 len -= op;
+                                 do {
+-                                    PUP(out) = PUP(from);
++                                    *out++ = *from++;
+                                 } while (--op);
+                                 from = out - dist;      /* rest from output */
+                             }
+@@ -248,35 +229,35 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+                         if (op < len) {         /* some from window */
+                             len -= op;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--op);
+                             from = out - dist;  /* rest from output */
+                         }
+                     }
+                     while (len > 2) {
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
++                        *out++ = *from++;
++                        *out++ = *from++;
+                         len -= 3;
+                     }
+                     if (len) {
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
+                         if (len > 1)
+-                            PUP(out) = PUP(from);
++                            *out++ = *from++;
+                     }
+                 }
+                 else {
+                     from = out - dist;          /* copy direct from output */
+                     do {                        /* minimum length is three */
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
++                        *out++ = *from++;
++                        *out++ = *from++;
+                         len -= 3;
+                     } while (len > 2);
+                     if (len) {
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
+                         if (len > 1)
+-                            PUP(out) = PUP(from);
++                            *out++ = *from++;
+                     }
+                 }
+             }
+@@ -313,8 +294,8 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+     hold &= (1U << bits) - 1;
+ 
+     /* update state and return */
+-    strm->next_in = in + OFF;
+-    strm->next_out = out + OFF;
++    strm->next_in = in;
++    strm->next_out = out;
+     strm->avail_in = (unsigned)(in < last ? 5 + (last - in) : 5 - (in - last));
+     strm->avail_out = (unsigned)(out < end ?
+                                  257 + (end - out) : 257 - (out - end));
--- gcc-6-6.3.0.orig/debian/patches/CVE-2016-9842.diff
+++ gcc-6-6.3.0/debian/patches/CVE-2016-9842.diff
@@ -0,0 +1,27 @@
+commit e54e1299404101a5a9d0cf5e45512b543967f958
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Sat Sep 5 17:45:55 2015 -0700
+
+    Avoid shifts of negative values inflateMark().
+    
+    The C standard says that bit shifts of negative integers is
+    undefined.  This casts to unsigned values to assure a known
+    result.
+
+Index: b/src/zlib/inflate.c
+===================================================================
+--- a/src/zlib/inflate.c
++++ b/src/zlib/inflate.c
+@@ -1504,9 +1504,10 @@ z_streamp strm;
+ {
+     struct inflate_state FAR *state;
+ 
+-    if (strm == Z_NULL || strm->state == Z_NULL) return -1L << 16;
++    if (strm == Z_NULL || strm->state == Z_NULL)
++        return (long)(((unsigned long)0 - 1) << 16);
+     state = (struct inflate_state FAR *)strm->state;
+-    return ((long)(state->back) << 16) +
++    return (long)(((unsigned long)((long)state->back)) << 16) +
+         (state->mode == COPY ? state->length :
+             (state->mode == MATCH ? state->was - state->length : 0));
+ }
--- gcc-6-6.3.0.orig/debian/patches/CVE-2016-9843.diff
+++ gcc-6-6.3.0/debian/patches/CVE-2016-9843.diff
@@ -0,0 +1,47 @@
+commit d1d577490c15a0c6862473d7576352a9f18ef811
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Wed Sep 28 20:20:25 2016 -0700
+
+    Avoid pre-decrement of pointer in big-endian CRC calculation.
+    
+    There was a small optimization for PowerPCs to pre-increment a
+    pointer when accessing a word, instead of post-incrementing. This
+    required prefacing the loop with a decrement of the pointer,
+    possibly pointing before the object passed. This is not compliant
+    with the C standard, for which decrementing a pointer before its
+    allocated memory is undefined. When tested on a modern PowerPC
+    with a modern compiler, the optimization no longer has any effect.
+    Due to all that, and per the recommendation of a security audit of
+    the zlib code by Trail of Bits and TrustInSoft, in support of the
+    Mozilla Foundation, this "optimization" was removed, in order to
+    avoid the possibility of undefined behavior.
+
+diff --git a/crc32.c b/crc32.c
+index 979a719..05733f4 100644
+--- a/src/zlib/crc32.c
++++ b/src/zlib/crc32.c
+@@ -278,7 +278,7 @@ local unsigned long crc32_little(crc, buf, len)
+ }
+ 
+ /* ========================================================================= */
+-#define DOBIG4 c ^= *++buf4; \
++#define DOBIG4 c ^= *buf4++; \
+         c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
+             crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24]
+ #define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4
+@@ -300,7 +300,6 @@ local unsigned long crc32_big(crc, buf, len)
+     }
+ 
+     buf4 = (const z_crc_t FAR *)(const void FAR *)buf;
+-    buf4--;
+     while (len >= 32) {
+         DOBIG32;
+         len -= 32;
+@@ -309,7 +308,6 @@ local unsigned long crc32_big(crc, buf, len)
+         DOBIG4;
+         len -= 4;
+     }
+-    buf4++;
+     buf = (const unsigned char FAR *)buf4;
+ 
+     if (len) do {
--- gcc-6-6.3.0.orig/debian/patches/ada-749574.diff
+++ gcc-6-6.3.0/debian/patches/ada-749574.diff
@@ -0,0 +1,34 @@
+From: Ludovic Brenta <lbrenta@debian.org>
+Forwarded: no
+Bug-Debian: http://bugs.debian.org/749574
+Description: Constraint_Error, range check failed at gnatlink.adb:2195, when called from gnatmake with -D option
+ The procedure gnatlink assumes that the Linker_Options.Table contains access
+ values to strings whose 'First index is always 1.  This assumption is wrong
+ for the string returned by function Base_Name.
+.
+ Instead of fixing the assumption in many places, this patch changes the
+ function Base_Name always to return a string with 'First=1.
+.
+ This looks like an upstream bug but strangely the reporter of this bug
+ says it does not happen on GCC built from upstream sources.  Further
+ investigation is required to determine whether or not to forward this
+ bug and patch upstream.
+
+Index: b/src/gcc/ada/gnatlink.adb
+===================================================================
+--- a/src/gcc/ada/gnatlink.adb
++++ b/src/gcc/ada/gnatlink.adb
+@@ -266,7 +266,12 @@ procedure Gnatlink is
+          Findex2 := File_Name'Last + 1;
+       end if;
+ 
+-      return File_Name (Findex1 .. Findex2 - 1);
++      declare
++         Result : String (1 .. Findex2 - Findex1);
++      begin
++         Result (1 .. Findex2 - Findex1) := File_Name (Findex1 .. Findex2 - 1);
++         return Result;
++      end;
+    end Base_Name;
+ 
+    -------------------------------
--- gcc-6-6.3.0.orig/debian/patches/ada-acats.diff
+++ gcc-6-6.3.0/debian/patches/ada-acats.diff
@@ -0,0 +1,206 @@
+# DP: - When running the ACATS, look for the gnat tools in their new
+# DP:   directory (build/gnattools), and for the shared libraries in
+# DP:   build/gcc/ada/rts, build/libgnatvsn and build/libgnatprj.
+
+Index: b/src/gcc/testsuite/ada/acats/run_acats
+===================================================================
+--- a/src/gcc/testsuite/ada/acats/run_acats
++++ b/src/gcc/testsuite/ada/acats/run_acats
+@@ -20,52 +20,30 @@ which () {
+     return 1
+ }
+ 
++echo '#!/bin/sh' > host_gnatchop
++echo exec /usr/bin/gnatchop --GCC=gcc-6 '$*' >> host_gnatchop
++
++chmod +x host_gnatchop
++
++echo '#!/bin/sh' > host_gnatmake
++echo echo '$PATH' '$*' >> host_gnatmake
++echo exec /usr/bin/gnatmake '$*' >> host_gnatmake
++
++chmod +x host_gnatmake
++
+ # Set up environment to use the Ada compiler from the object tree
+ 
+-host_gnatchop=`which gnatchop`
+-host_gnatmake=`which gnatmake`
+ ROOT=`${PWDCMD-pwd}`
+ BASE=`cd $ROOT/../../..; ${PWDCMD-pwd}`
+-
+ PATH=$BASE:$ROOT:$PATH
+-ADA_INCLUDE_PATH=$BASE/ada/rts
+-LD_LIBRARY_PATH=$ADA_INCLUDE_PATH:$BASE:$LD_LIBRARY_PATH
+-ADA_OBJECTS_PATH=$ADA_INCLUDE_PATH
+-
+-if [ ! -d $ADA_INCLUDE_PATH ]; then
+-   echo gnatlib missing, exiting.
+-   exit 1
+-fi
+-
+-if [ ! -f $BASE/gnatchop ]; then
+-   echo gnattools missing, exiting.
+-   exit 1
+-fi
+-
+-if [ ! -f $BASE/gnatmake ]; then
+-   echo gnattools missing, exiting.
+-   exit 1
+-fi
+-
+ GCC_DRIVER="$BASE/xgcc"
++TARGET=`${GCC_DRIVER} -v  2>&1 |grep '^Target:' | cut -d' ' -f2`
++GNATTOOLS=`cd $BASE/../gnattools; ${PWDCMD-pwd}`
++LIBGNATVSN=`cd $BASE/../${TARGET}/libgnatvsn; ${PWDCMD-pwd}`
++LIBGNATPRJ=`cd $BASE/../${TARGET}/libgnatprj; ${PWDCMD-pwd}`
+ GCC="$BASE/xgcc -B$BASE/"
+ export PATH ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_DRIVER GCC LD_LIBRARY_PATH
+-
+-echo '#!/bin/sh' > host_gnatchop
+-echo PATH=`dirname $host_gnatchop`:'$PATH' >> host_gnatchop
+-echo unset ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_EXEC_PREFIX >> host_gnatchop
+-echo export PATH >> host_gnatchop
+-echo exec gnatchop '"$@"' >> host_gnatchop
+-
+-chmod +x host_gnatchop
+-
+-echo '#!/bin/sh' > host_gnatmake
+-echo PATH=`dirname $host_gnatmake`:'$PATH' >> host_gnatmake
+-echo unset ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_EXEC_PREFIX >> host_gnatmake
+-echo export PATH >> host_gnatmake
+-echo exec gnatmake '"$@"' >> host_gnatmake
+-
+-chmod +x host_gnatmake
++export GNATTOOLS LIBGNATVSN LIBGNATPRJ
+ 
+ # Limit the stack to 16MB for stack checking
+ ulimit -s 16384
+Index: b/src/gcc/testsuite/ada/acats/run_all.sh
+===================================================================
+--- a/src/gcc/testsuite/ada/acats/run_all.sh
++++ b/src/gcc/testsuite/ada/acats/run_all.sh
+@@ -1,4 +1,5 @@
+ #!/bin/sh
++
+ # Run ACATS with the GNU Ada compiler
+ 
+ # The following functions are to be customized if you run in cross
+@@ -12,6 +13,10 @@
+ gccflags="-O2"
+ gnatflags="-gnatws"
+ 
++RTS=`cd $GNATTOOLS/../gcc/ada/rts; ${PWDCMD-pwd}`
++LD_LIBRARY_PATH=$RTS:$LIBGNATVSN:$LIBGNATPRJ
++export LD_LIBRARY_PATH
++
+ target_run () {
+   eval $EXPECT -f $testdir/run_test.exp $*
+ }
+@@ -63,12 +68,15 @@ if [ "$dir" = "$testdir" ]; then
+ fi
+ 
+ target_gnatchop () {
+-  gnatchop --GCC="$GCC_DRIVER" $*
++  ADA_INCLUDE_PATH=$GNATTOOLS/../../src/gcc/ada $GNATTOOLS/gnatchop --GCC="$GCC_DRIVER" $*
+ }
+ 
+ target_gnatmake () {
+-  echo gnatmake --GCC=\"$GCC\" $gnatflags $gccflags $* -largs $EXTERNAL_OBJECTS --GCC=\"$GCC\"
+-  gnatmake --GCC="$GCC" $gnatflags $gccflags $* -largs $EXTERNAL_OBJECTS --GCC="$GCC"
++  EXTERNAL_OBJECTS="$EXTERNAL_OBJECTS $RTS/adaint.o $RTS/sysdep.o $RTS/init.o $RTS/raise-gcc.o"
++  $GNATTOOLS/gnatmake -I- -I$RTS -I. \
++      --GCC="$GCC" --GNATBIND="$GNATTOOLS/gnatbind" \
++      --GNATLINK="$GNATTOOLS/gnatlink" $gnatflags $gccflags $* \
++      -bargs -static -largs $EXTERNAL_OBJECTS --GCC="$GCC -I- -I$RTS -I."
+ }
+ 
+ target_gcc () {
+@@ -101,8 +109,8 @@ display target gcc is $GCC
+ display `$GCC -v 2>&1`
+ display host=`gcc -dumpmachine`
+ display target=$target
+-display `type gnatmake`
+-gnatls -v >> $dir/acats.log
++display `type $GNATTOOLS/gnatmake`
++$GNATTOOLS/gnatls -I- -I$RTS -v >> $dir/acats.log
+ display ""
+ 
+ if [ -n "$GCC_RUNTEST_PARALLELIZE_DIR" ]; then
+@@ -129,7 +137,7 @@ cp $testdir/support/*.ada $testdir/suppo
+ # Find out the size in bit of an address on the target
+ target_gnatmake $testdir/support/impbit.adb >> $dir/acats.log 2>&1
+ target_run $dir/support/impbit > $dir/support/impbit.out 2>&1
+-target_bit=`cat $dir/support/impbit.out`
++target_bit=`cat $dir/support/impbit.out | sed -e 's/ //g' -e 's/\r//g'`
+ echo target_bit="$target_bit" >> $dir/acats.log
+ 
+ # Find out a suitable asm statement
+Index: b/src/gcc/testsuite/lib/gnat.exp
+===================================================================
+--- a/src/gcc/testsuite/lib/gnat.exp
++++ b/src/gcc/testsuite/lib/gnat.exp
+@@ -88,18 +88,25 @@ proc gnat_init { args } {
+     global GNAT_UNDER_TEST
+     global TOOL_EXECUTABLE
+     global gnat_target_current
++    global ld_library_path
+ 
+     set gnat_target_current ""
+ 
+     if { $gnat_initialized == 1 } { return }
+ 
+-    if ![info exists GNAT_UNDER_TEST] then {
+-	if [info exists TOOL_EXECUTABLE] {
+-	    set GNAT_UNDER_TEST "$TOOL_EXECUTABLE"
+-	} else {
+-	    set GNAT_UNDER_TEST "[local_find_gnatmake]"
+-	}
+-    }
++    set target [target_info name]
++    set GNAT_UNDER_TEST "$rootme/../gnattools/gnatmake -I$rootme/ada/rts --GCC=$rootme/xgcc --GNATBIND=$rootme/../gnattools/gnatbind --GNATLINK=$rootme/../gnattools/gnatlink -cargs -B$rootme -largs --GCC=$rootme/xgcc -B$rootme -margs"
++    append ld_library_path ":$rootme/ada/rts"
++    append ld_library_path ":$rootme/../$target/libgnatvsn"
++    append ld_library_path ":$rootme/../$target/libgnatprj"
++    set_ld_library_path_env_vars
++
++    # gnatlink looks for system.ads itself and has no --RTS option, so
++    # specify via environment
++    verbose -log "ADA_INCLUDE_PATH=$rootme/ada/rts"
++    verbose -log "ADA_OBJECTS_PATH=$rootme/ada/rts"
++    setenv ADA_INCLUDE_PATH "$rootme/ada/rts"
++    setenv ADA_OBJECTS_PATH "$rootme/ada/rts"
+ 
+     if ![info exists tmpdir] then {
+ 	set tmpdir /tmp
+@@ -121,31 +128,6 @@ proc gnat_target_compile { source dest t
+ 	return [gcc_target_compile $source $dest $type $options]
+     }
+ 
+-    # If we detect a change of target, we need to recompute both
+-    # GNAT_UNDER_TEST and the appropriate RTS.
+-    if { $gnat_target_current!="[current_target_name]" } {
+-	set gnat_target_current "[current_target_name]"
+-	if [info exists TOOL_OPTIONS] {
+-	    set rtsdir "[get_multilibs ${TOOL_OPTIONS}]/libada"
+-	} else {
+-	    set rtsdir "[get_multilibs]/libada"
+-	}
+-	if [info exists TOOL_EXECUTABLE] {
+-	    set GNAT_UNDER_TEST "$TOOL_EXECUTABLE"
+-	} else {
+-	    set GNAT_UNDER_TEST "[local_find_gnatmake]"
+-	}
+-        set GNAT_UNDER_TEST "$GNAT_UNDER_TEST --RTS=$rtsdir"
+-
+-	# gnatlink looks for system.ads itself and has no --RTS option, so
+-	# specify via environment
+-	setenv ADA_INCLUDE_PATH "$rtsdir/adainclude"
+-	setenv ADA_OBJECTS_PATH "$rtsdir/adainclude"
+-	# Always log so compilations can be repeated manually.
+-	verbose -log "ADA_INCLUDE_PATH=$rtsdir/adainclude"
+-	verbose -log "ADA_OBJECTS_PATH=$rtsdir/adainclude"
+-    }
+-
+     lappend options "compiler=$GNAT_UNDER_TEST -q -f"
+     lappend options "timeout=[timeout_value]"
+ 
--- gcc-6-6.3.0.orig/debian/patches/ada-arm.diff
+++ gcc-6-6.3.0/debian/patches/ada-arm.diff
@@ -0,0 +1,18 @@
+DP: Improve support for ZCX on arm.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -1964,7 +1964,10 @@ ifeq ($(strip $(filter-out arm% linux-gn
+     LIBGNAT_TARGET_PAIRS += \
+     system.ads<system-linux-armeb.ads
+   else
+-    EH_MECHANISM=-arm
++    # Special case; the GCC exception mechanism is supported under
++    # another name and with different files than for other
++    # target_cpus.
++    override EH_MECHANISM=-arm
+     LIBGNAT_TARGET_PAIRS += \
+     system.ads<system-linux-armel.ads \
+     a-exexpr.adb<a-exexpr-gcc.adb \
--- gcc-6-6.3.0.orig/debian/patches/ada-default-project-path.diff
+++ gcc-6-6.3.0/debian/patches/ada-default-project-path.diff
@@ -0,0 +1,134 @@
+# DP: - Change the default search path for project files to the one specified
+# DP:   by the Debian Policy for Ada: /usr/share/ada/adainclude.
+
+Index: b/src/gcc/ada/Make-generated.in
+===================================================================
+--- a/src/gcc/ada/Make-generated.in
++++ b/src/gcc/ada/Make-generated.in
+@@ -76,6 +76,7 @@ $(ADA_GEN_SUBDIR)/stamp-sdefault : $(src
+ 	$(ECHO) "   S2 : constant String := \"$(ADA_RTL_OBJ_DIR)/\";" >>tmp-sdefault.adb
+ 	$(ECHO) "   S3 : constant String := \"$(target_noncanonical)/\";" >>tmp-sdefault.adb
+ 	$(ECHO) "   S4 : constant String := \"$(libsubdir)/\";" >>tmp-sdefault.adb
++	$(ECHO) "   S5 : constant String := \"/usr/share/ada/adainclude/\";" >>tmp-sdefault.adb
+ 	$(ECHO) "   function Include_Dir_Default_Name return String_Ptr is" >>tmp-sdefault.adb
+ 	$(ECHO) "   begin" >>tmp-sdefault.adb
+ 	$(ECHO) "      return Relocate_Path (S0, S1);" >>tmp-sdefault.adb
+@@ -92,6 +93,10 @@ $(ADA_GEN_SUBDIR)/stamp-sdefault : $(src
+ 	$(ECHO) "   begin" >>tmp-sdefault.adb
+ 	$(ECHO) "      return Relocate_Path (S0, S4);" >>tmp-sdefault.adb
+ 	$(ECHO) "   end Search_Dir_Prefix;" >>tmp-sdefault.adb
++	$(ECHO) "   function Project_Dir_Prefix return String_Ptr is" >>tmp-sdefault.adb
++	$(ECHO) "   begin" >>tmp-sdefault.adb
++	$(ECHO) "      return Relocate_Path (S0, S5);" >>tmp-sdefault.adb
++	$(ECHO) "   end Project_Dir_Prefix;" >>tmp-sdefault.adb
+ 	$(ECHO) "end Sdefault;" >> tmp-sdefault.adb
+ 	$(MOVE_IF_CHANGE) tmp-sdefault.adb $(ADA_GEN_SUBDIR)/sdefault.adb
+ 	touch $(ADA_GEN_SUBDIR)/stamp-sdefault
+Index: b/src/gcc/ada/prj-env.adb
+===================================================================
+--- a/src/gcc/ada/prj-env.adb
++++ b/src/gcc/ada/prj-env.adb
+@@ -1877,6 +1877,7 @@ package body Prj.Env is
+       Target_Name  : String;
+       Runtime_Name : String := "")
+    is
++      pragma Unreferenced (Target_Name);
+       Add_Default_Dir : Boolean := Target_Name /= "-";
+       First           : Positive;
+       Last            : Positive;
+@@ -2075,82 +2076,9 @@ package body Prj.Env is
+ 
+       --  Set the initial value of Current_Project_Path
+ 
+-      if Add_Default_Dir then
+-         if Sdefault.Search_Dir_Prefix = null then
+-
+-            --  gprbuild case
+-
+-            Prefix := new String'(Executable_Prefix_Path);
+-
+-         else
+-            Prefix := new String'(Sdefault.Search_Dir_Prefix.all
+-                                  & ".." & Dir_Separator
+-                                  & ".." & Dir_Separator
+-                                  & ".." & Dir_Separator
+-                                  & ".." & Dir_Separator);
+-         end if;
+-
+-         if Prefix.all /= "" then
+-            if Target_Name /= "" then
+-
+-               if Runtime_Name /= "" then
+-                  if Base_Name (Runtime_Name) = Runtime_Name then
+-
+-                     --  $prefix/$target/$runtime/lib/gnat
+-                     Add_Target;
+-                     Add_Str_To_Name_Buffer
+-                       (Runtime_Name & Directory_Separator &
+-                          "lib" & Directory_Separator & "gnat");
+-
+-                     --  $prefix/$target/$runtime/share/gpr
+-                     Add_Target;
+-                     Add_Str_To_Name_Buffer
+-                       (Runtime_Name & Directory_Separator &
+-                          "share" & Directory_Separator & "gpr");
+-
+-                  else
+-                     Runtime :=
+-                       new String'(Normalize_Pathname (Runtime_Name));
+-
+-                     --  $runtime_dir/lib/gnat
+-                     Add_Str_To_Name_Buffer
+-                       (Path_Separator & Runtime.all & Directory_Separator &
+-                        "lib" & Directory_Separator & "gnat");
+-
+-                     --  $runtime_dir/share/gpr
+-                     Add_Str_To_Name_Buffer
+-                       (Path_Separator & Runtime.all & Directory_Separator &
+-                        "share" & Directory_Separator & "gpr");
+-                  end if;
+-               end if;
+-
+-               --  $prefix/$target/lib/gnat
+-
+-               Add_Target;
+-               Add_Str_To_Name_Buffer
+-                 ("lib" & Directory_Separator & "gnat");
+-
+-               --  $prefix/$target/share/gpr
+-
+-               Add_Target;
+-               Add_Str_To_Name_Buffer
+-                 ("share" & Directory_Separator & "gpr");
+-            end if;
+-
+-            --  $prefix/share/gpr
+-
+-            Add_Str_To_Name_Buffer
+-              (Path_Separator & Prefix.all & "share"
+-               & Directory_Separator & "gpr");
+-
+-            --  $prefix/lib/gnat
+-
+-            Add_Str_To_Name_Buffer
+-              (Path_Separator & Prefix.all & "lib"
+-               & Directory_Separator & "gnat");
+-         end if;
+-
+-         Free (Prefix);
++      if Add_Default_Dir and Sdefault.Project_Dir_Prefix /= null then
++         Add_Str_To_Name_Buffer (Path_Separator
++                                 & Sdefault.Project_Dir_Prefix.all);
+       end if;
+ 
+       Self.Path := new String'(Name_Buffer (1 .. Name_Len));
+Index: b/src/gcc/ada/sdefault.ads
+===================================================================
+--- a/src/gcc/ada/sdefault.ads
++++ b/src/gcc/ada/sdefault.ads
+@@ -35,4 +35,5 @@ package Sdefault is
+    function Object_Dir_Default_Name  return String_Ptr;
+    function Target_Name              return String_Ptr;
+    function Search_Dir_Prefix        return String_Ptr;
++   function Project_Dir_Prefix       return String_Ptr;
+ end Sdefault;
--- gcc-6-6.3.0.orig/debian/patches/ada-driver-check.diff
+++ gcc-6-6.3.0/debian/patches/ada-driver-check.diff
@@ -0,0 +1,29 @@
+# DP: Simplify Ada driver check (we always build using the required
+# DP: Ada version. Needed for warnings on alpha.
+
+Index: b/src/config/acx.m4
+===================================================================
+--- a/src/config/acx.m4
++++ b/src/config/acx.m4
+@@ -381,7 +381,7 @@ acx_cv_cc_gcc_supports_ada=no
+ # Other compilers, like HP Tru64 UNIX cc, exit successfully when
+ # given a .adb file, but produce no object file.  So we must check
+ # if an object file was really produced to guard against this.
+-errors=`(${CC} $1[]m4_ifval([$1], [ ])-c conftest.adb) 2>&1 || echo failure`
++errors=`(${CC} $1[]m4_ifval([$1], [ ])-c conftest.adb) 2>/dev/null || echo failure`
+ if test x"$errors" = x && test -f conftest.$ac_objext; then
+   acx_cv_cc_gcc_supports_ada=yes
+ fi
+Index: b/src/configure
+===================================================================
+--- a/src/configure
++++ b/src/configure
+@@ -5355,7 +5355,7 @@ acx_cv_cc_gcc_supports_ada=no
+ # Other compilers, like HP Tru64 UNIX cc, exit successfully when
+ # given a .adb file, but produce no object file.  So we must check
+ # if an object file was really produced to guard against this.
+-errors=`(${CC} -c conftest.adb) 2>&1 || echo failure`
++errors=`(${CC} -c conftest.adb) 2>/dev/null || echo failure`
+ if test x"$errors" = x && test -f conftest.$ac_objext; then
+   acx_cv_cc_gcc_supports_ada=yes
+ fi
--- gcc-6-6.3.0.orig/debian/patches/ada-gnattools-cross.diff
+++ gcc-6-6.3.0/debian/patches/ada-gnattools-cross.diff
@@ -0,0 +1,761 @@
+# DP: - When building the native gnat, link the gnat tools against
+# DP:   the build tree (build/$(host_alias)/{libgnatvsn,libgnatprj}.)
+# DP: - When building a cross gnat, link against the libgnatvsn-6-dev
+# DP:   and libgnatprj-6-dev packages.
+# DP:   This link will be done by /usr/bin/$(host_alias)-gnat*, thus
+# DP:   the native gnat with the same major version will be required.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -102,7 +102,7 @@ INSTALL_DATA_DATE = cp -p
+ MAKEINFO = makeinfo
+ TEXI2DVI = texi2dvi
+ TEXI2PDF = texi2pdf
+-GNATBIND_FLAGS = -static -x
++GNATBIND_FLAGS = -shared -x
+ ADA_CFLAGS =
+ ADAFLAGS = -W -Wall -gnatpg -gnata
+ FORCE_DEBUG_ADAFLAGS = -g
+@@ -141,6 +141,8 @@ target=@target@
+ target_cpu=@target_cpu@
+ target_vendor=@target_vendor@
+ target_os=@target_os@
++host_alias=@host_alias@
++host=@host@
+ host_cpu=@host_cpu@
+ host_vendor=@host_vendor@
+ host_os=@host_os@
+@@ -235,7 +237,7 @@ ALL_CPPFLAGS = $(CPPFLAGS)
+ ALL_COMPILERFLAGS = $(ALL_CFLAGS)
+ 
+ # This is where we get libiberty.a from.
+-LIBIBERTY = ../../libiberty/libiberty.a
++LIBIBERTY = ../../libiberty/pic/libiberty.a
+ 
+ # We need to link against libbacktrace because diagnostic.c in
+ # libcommon.a uses it.
+@@ -247,9 +249,15 @@ LIBS = $(LIBINTL) $(LIBICONV) $(LIBBACKT
+ LIBDEPS = $(LIBINTL_DEP) $(LIBICONV_DEP) $(LIBBACKTRACE) $(LIBIBERTY)
+ # Default is no TGT_LIB; one might be passed down or something
+ TGT_LIB =
+-TOOLS_LIBS = ../link.o ../targext.o ../../ggc-none.o ../../libcommon-target.a \
+-  ../../libcommon.a ../../../libcpp/libcpp.a $(LIBGNAT) $(LIBINTL) $(LIBICONV) \
+-  ../$(LIBBACKTRACE) ../$(LIBIBERTY) $(SYSLIBS) $(TGT_LIB)
++
++TOOLS_LIBS = ../link.o ../targext.o ../../ggc-none.o ../../version.o ../../../libiberty/pic/lrealpath.o \
++      ../../libbackend.a ../../libcommon-target.a ../../libcommon.a ../../../libcpp/libcpp.a ../$(LIBBACKTRACE) ../$(LIBIBERTY) -lstdc++
++
++ifeq ($(host),$(target))
++  TOOLS_LIBS +=  -L../$(RTSDIR) -lgnat-6 \
++		-L../../../$(target_alias)/libgnatvsn -lgnatvsn \
++                -L../../../$(target_alias)/libgnatprj -lgnatprj
++endif
+ 
+ # Add -no-pie to TOOLS_LIBS since some of them are compiled with -fno-PIE.
+ TOOLS_LIBS += @NO_PIE_FLAG@
+@@ -261,7 +269,12 @@ TOOLS_LIBS += @NO_PIE_FLAG@
+ INCLUDES = -iquote . -iquote .. -iquote $(srcdir)/ada -iquote $(srcdir) \
+ 	   -I $(ftop_srcdir)/include $(GMPINC)
+ 
+-ADA_INCLUDES = -I- -I. -I$(srcdir)/ada
++ifeq ($(host),$(target))
++  ADA_INCLUDES = -I../rts \
++		-I../../../$(target_alias)/libgnatvsn \
++		-I../../../$(target_alias)/libgnatprj
++endif
++ADA_INCLUDES += -I- -I. -I$(srcdir)/ada
+ 
+ # Likewise, but valid for subdirectories of the current dir.
+ # FIXME: for VxWorks, we cannot add $(fsrcdir) because the regs.h file in
+@@ -309,30 +322,50 @@ Makefile: ../config.status $(srcdir)/ada
+ # defined in this file into the environment.
+ .NOEXPORT:
+ 
+-# Lists of files for various purposes.
+ 
+-GNATLINK_OBJS = gnatlink.o \
+- a-except.o ali.o alloc.o butil.o casing.o csets.o debug.o fmap.o fname.o \
+- gnatvsn.o hostparm.o indepsw.o interfac.o i-c.o i-cstrin.o namet.o opt.o \
+- osint.o output.o rident.o s-exctab.o s-secsta.o s-stalib.o s-stoele.o \
+- sdefault.o snames.o stylesw.o switch.o system.o table.o targparm.o tree_io.o \
+- types.o validsw.o widechar.o
+-
+-GNATMAKE_OBJS = a-except.o ali.o ali-util.o aspects.o s-casuti.o alloc.o \
+- atree.o binderr.o butil.o casing.o csets.o debug.o elists.o einfo.o errout.o \
+- erroutc.o errutil.o err_vars.o fmap.o fname.o fname-uf.o fname-sf.o \
+- gnatmake.o gnatvsn.o hostparm.o interfac.o i-c.o i-cstrin.o krunch.o lib.o \
+- make.o makeusg.o makeutl.o mlib.o mlib-fil.o mlib-prj.o mlib-tgt.o \
+- mlib-tgt-specific.o mlib-utl.o namet.o nlists.o opt.o osint.o osint-m.o \
+- output.o prj.o prj-attr.o prj-attr-pm.o prj-com.o prj-dect.o prj-env.o \
+- prj-conf.o prj-pp.o prj-err.o prj-ext.o prj-nmsc.o prj-pars.o prj-part.o \
+- prj-proc.o prj-strt.o prj-tree.o prj-util.o restrict.o rident.o s-exctab.o \
+- s-secsta.o s-stalib.o s-stoele.o scans.o scng.o sdefault.o sfn_scan.o \
+- s-purexc.o s-htable.o scil_ll.o sem_aux.o sinfo.o sinput.o sinput-c.o \
+- sinput-p.o snames.o stand.o stringt.o styleg.o stylesw.o system.o validsw.o \
+- switch.o switch-m.o table.o targparm.o tempdir.o tree_io.o types.o uintp.o \
+- uname.o urealp.o usage.o widechar.o \
+- $(EXTRA_GNATMAKE_OBJS)
++# Since we don't have gnatmake, we must specify the full list of
++# object files necessary to build gnatmake and gnatlink.
++GNATLINK_OBJS = \
++gnatlink.o \
++indepsw.o \
++validsw.o
++
++GNATMAKE_OBJS = \
++aspects.o \
++errout.o \
++fname-sf.o \
++gnatmake.o \
++make.o \
++makeusg.o \
++mlib-prj.o \
++osint-m.o \
++restrict.o \
++sem_aux.o \
++usage.o \
++validsw.o \
++$(EXTRA_GNATMAKE_OBJS)
++
++EXTRA_TOOLS_OBJS = \
++bcheck.o \
++binde.o \
++bindgen.o \
++bindusg.o \
++clean.o \
++gprep.o \
++makegpr.o \
++osint-b.o \
++osint-l.o \
++prep.o \
++prj-makr.o \
++prj-pp.o \
++switch-b.o \
++vms_cmds.o \
++vms_conv.o \
++vms_data.o \
++xr_tabls.o \
++xref_lib.o
++
++OBJECTS = $(GNATLINK_OBJS) $(GNATMAKE_OBJS) $(EXTRA_TOOLS_OBJS)
+ 
+ # Make arch match the current multilib so that the RTS selection code
+ # picks up the right files. For a given target this must be coherent
+@@ -1612,6 +1645,11 @@ ifeq ($(strip $(filter-out s390% linux%,
+   LIBRARY_VERSION := $(LIB_VERSION)
+ endif
+ 
++ifeq ($(strip $(filter-out hppa% unknown linux gnu,$(targ))),)
++  GNATLIB_SHARED = gnatlib-shared-dual
++  LIBRARY_VERSION := $(LIB_VERSION)
++endif
++
+ # HP/PA HP-UX 10
+ ifeq ($(strip $(filter-out hppa% hp hpux10%,$(target_cpu) $(target_vendor) $(target_os))),)
+   LIBGNAT_TARGET_PAIRS = \
+@@ -2500,153 +2538,6 @@ ADA_EXCLUDE_FILES=$(filter-out \
+   $(patsubst %$(objext),%.adb,$(GNATRTL_OBJS)), \
+   $(ADA_EXCLUDE_SRCS))
+ 
+-LIBGNAT=../$(RTSDIR)/libgnat.a
+-
+-TOOLS_FLAGS_TO_PASS=		\
+-	"CC=$(CC)" 		\
+-	"CFLAGS=$(CFLAGS)"	\
+-	"LDFLAGS=$(LDFLAGS)"	\
+-	"ADAFLAGS=$(ADAFLAGS)"	\
+-	"INCLUDES=$(INCLUDES_FOR_SUBDIR)"\
+-	"ADA_INCLUDES=$(ADA_INCLUDES) $(ADA_INCLUDES_FOR_SUBDIR)"\
+-	"libsubdir=$(libsubdir)"	\
+-	"exeext=$(exeext)"	\
+-	"fsrcdir=$(fsrcdir)"	\
+-	"srcdir=$(fsrcdir)"	\
+-	"TOOLS_LIBS=$(TOOLS_LIBS) $(TGT_LIB)"	\
+-	"GNATMAKE=$(GNATMAKE)"	\
+-	"GNATLINK=$(GNATLINK)"	\
+-	"GNATBIND=$(GNATBIND)"
+-
+-GCC_LINK=$(CXX) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS)
+-
+-# Build directory for the tools. Let's copy the target-dependent
+-# sources using the same mechanism as for gnatlib. The other sources are
+-# accessed using the vpath directive below
+-
+-../stamp-tools:
+-	-$(RM) tools/*
+-	-$(RMDIR) tools
+-	-$(MKDIR) tools
+-	-(cd tools; $(LN_S) ../sdefault.adb ../snames.ads ../snames.adb .)
+-	-$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
+-	          $(RM) tools/$(word 1,$(subst <, ,$(PAIR)));\
+-	          $(LN_S) $(fsrcpfx)ada/$(word 2,$(subst <, ,$(PAIR))) \
+-	                tools/$(word 1,$(subst <, ,$(PAIR)));)
+-	touch ../stamp-tools
+-
+-# when compiling the tools, the runtime has to be first on the path so that
+-# it hides the runtime files lying with the rest of the sources
+-ifeq ($(TOOLSCASE),native)
+-  vpath %.ads ../$(RTSDIR) ../
+-  vpath %.adb ../$(RTSDIR) ../
+-  vpath %.c   ../$(RTSDIR) ../
+-  vpath %.h   ../$(RTSDIR) ../
+-endif
+-
+-# in the cross tools case, everything is compiled with the native
+-# gnatmake/link. Therefore only -I needs to be modified in ADA_INCLUDES
+-ifeq ($(TOOLSCASE),cross)
+-  vpath %.ads ../
+-  vpath %.adb ../
+-  vpath %.c   ../
+-  vpath %.h   ../
+-endif
+-
+-# gnatmake/link tools cannot always be built with gnatmake/link for bootstrap
+-# reasons: gnatmake should be built with a recent compiler, a recent compiler
+-# may not generate ALI files compatible with an old gnatmake so it is important
+-# to be able to build gnatmake without a version of gnatmake around. Once
+-# everything has been compiled once, gnatmake can be recompiled with itself
+-# (see target gnattools1-re)
+-gnattools1: ../stamp-tools ../stamp-gnatlib-$(RTSDIR)
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=native \
+-	  ../../gnatmake$(exeext) ../../gnatlink$(exeext)
+-
+-# gnatmake/link can be built with recent gnatmake/link if they are available.
+-# This is especially convenient for building cross tools or for rebuilding
+-# the tools when the original bootstrap has already be done.
+-gnattools1-re: ../stamp-tools
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=cross INCLUDES="" gnatmake-re gnatlink-re
+-
+-# these tools are built with gnatmake & are common to native and cross
+-gnattools2: ../stamp-tools
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=native common-tools $(EXTRA_GNATTOOLS)
+-
+-# those tools are only built for the cross version
+-gnattools4: ../stamp-tools
+-ifeq ($(ENABLE_VXADDR2LINE),true)
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=cross top_buildir=../../.. \
+-	  ../../vxaddr2line$(exeext)
+-endif
+-
+-common-tools: ../stamp-tools
+-	$(GNATMAKE) -j0 -c -b $(ADA_INCLUDES) \
+-	  --GNATBIND="$(GNATBIND)" --GCC="$(CC) $(ALL_ADAFLAGS)" \
+-	  gnatchop gnatcmd gnatkr gnatls gnatprep gnatxref gnatfind gnatname \
+-	  gnatclean -bargs $(ADA_INCLUDES) $(GNATBIND_FLAGS)
+-	$(GNATLINK) -v gnatcmd -o ../../gnat$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatchop -o ../../gnatchop$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatkr -o ../../gnatkr$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatls -o ../../gnatls$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatprep -o ../../gnatprep$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatxref -o ../../gnatxref$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatfind -o ../../gnatfind$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatname -o ../../gnatname$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatclean -o ../../gnatclean$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-
+-../../gnatdll$(exeext): ../stamp-tools
+-	$(GNATMAKE) -c $(ADA_INCLUDES) gnatdll --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatdll
+-	$(GNATLINK) -v gnatdll -o $@ --GCC="$(GCC_LINK)" $(TOOLS_LIBS)
+-
+-../../vxaddr2line$(exeext): ../stamp-tools
+-	$(GNATMAKE) -c  $(ADA_INCLUDES) vxaddr2line --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) vxaddr2line
+-	$(GNATLINK) -v vxaddr2line -o $@ --GCC="$(GCC_LINK)" ../targext.o $(CLIB)
+-
+-gnatmake-re: ../stamp-tools
+-	$(GNATMAKE) -j0 $(ADA_INCLUDES) -u sdefault --GCC="$(CC) $(MOST_ADA_FLAGS)"
+-	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatmake --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatmake
+-	$(GNATLINK) -v gnatmake -o ../../gnatmake$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
+-
+-# Note the use of the "mv" command in order to allow gnatlink to be linked with
+-# with the former version of gnatlink itself which cannot override itself.
+-# gnatlink-re cannot be run at the same time as gnatmake-re, hence the
+-# dependency
+-gnatlink-re: ../stamp-tools gnatmake-re
+-	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatlink --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatlink
+-	$(GNATLINK) -v gnatlink -o ../../gnatlinknew$(exeext) \
+-		    --GCC="$(GCC_LINK)" $(TOOLS_LIBS)
+-	$(MV)  ../../gnatlinknew$(exeext)  ../../gnatlink$(exeext)
+-
+-# Needs to be built with CC=gcc
+-# Since the RTL should be built with the latest compiler, remove the
+-#  stamp target in the parent directory whenever gnat1 is rebuilt
+-
+-# Likewise for the tools
+-../../gnatmake$(exeext): $(P) b_gnatm.o $(GNATMAKE_OBJS)
+-	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS) $(TOOLS1_LIBS)
+-
+-../../gnatlink$(exeext): $(P) b_gnatl.o $(GNATLINK_OBJS)
+-	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS) $(TOOLS1_LIBS)
+-
+ ../stamp-gnatlib-$(RTSDIR):
+ 	@if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \
+ 	then \
+@@ -2685,14 +2576,10 @@ install-gnatlib: ../stamp-gnatlib-$(RTSD
+ #     Also install the .dSYM directories if they exist (these directories
+ #     contain the debug information for the shared libraries on darwin)
+ 	for file in gnat gnarl; do \
+-	   if [ -f $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext) ]; then \
+-	      $(INSTALL) $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext) \
++	   if [ -f $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).1 ]; then \
++	      $(INSTALL) $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 			 $(DESTDIR)$(ADA_RTL_OBJ_DIR); \
+ 	   fi; \
+-	   if [ -f $(RTSDIR)/lib$${file}$(soext) ]; then \
+-	      $(LN_S) lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-	      $(DESTDIR)$(ADA_RTL_OBJ_DIR)/lib$${file}$(soext); \
+-	   fi; \
+ 	   if [ -d $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).dSYM ]; then \
+ 	      $(CP) -r $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).dSYM \
+ 	        $(DESTDIR)$(ADA_RTL_OBJ_DIR); \
+@@ -2705,19 +2592,7 @@ install-gnatlib: ../stamp-gnatlib-$(RTSD
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.adb
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.ads
+ 
+-../stamp-gnatlib2-$(RTSDIR):
+-	$(RM) $(RTSDIR)/s-*.ali
+-	$(RM) $(RTSDIR)/s-*$(objext)
+-	$(RM) $(RTSDIR)/a-*.ali
+-	$(RM) $(RTSDIR)/a-*$(objext)
+-	$(RM) $(RTSDIR)/*.ali
+-	$(RM) $(RTSDIR)/*$(objext)
+-	$(RM) $(RTSDIR)/*$(arext)
+-	$(RM) $(RTSDIR)/*$(soext)
+-	touch ../stamp-gnatlib2-$(RTSDIR)
+-	$(RM) ../stamp-gnatlib-$(RTSDIR)
+-
+-../stamp-gnatlib1-$(RTSDIR): Makefile ../stamp-gnatlib2-$(RTSDIR)
++../stamp-gnatlib1-$(RTSDIR): Makefile
+ 	$(RMDIR) $(RTSDIR)
+ 	$(MKDIR) $(RTSDIR)
+ 	$(CHMOD) u+w $(RTSDIR)
+@@ -2782,7 +2657,7 @@ $(RTSDIR)/s-oscons.ads: ../stamp-gnatlib
+ 	    $(OSCONS_EXTRACT) ; \
+ 	    ../bldtools/oscons/xoscons s-oscons)
+ 
+-gnatlib: ../stamp-gnatlib1-$(RTSDIR) ../stamp-gnatlib2-$(RTSDIR) $(RTSDIR)/s-oscons.ads
++gnatlib: ../stamp-gnatlib1-$(RTSDIR) $(RTSDIR)/s-oscons.ads
+ 	test -f $(RTSDIR)/s-oscons.ads || exit 1
+ # C files
+ 	$(MAKE) -C $(RTSDIR) \
+@@ -2820,32 +2695,44 @@ gnatlib: ../stamp-gnatlib1-$(RTSDIR) ../
+ 
+ # Warning: this target assumes that LIBRARY_VERSION has been set correctly.
+ gnatlib-shared-default:
+-	$(MAKE) $(FLAGS_TO_PASS) \
+-             GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+-	     GNATLIBCFLAGS="$(GNATLIBCFLAGS) $(PICFLAG_FOR_TARGET)" \
+-	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C) $(PICFLAG_FOR_TARGET)" \
+-	     MULTISUBDIR="$(MULTISUBDIR)" \
+-	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib
+-	$(RM) $(RTSDIR)/libgna*$(soext)
++	$(MAKE) -C $(RTSDIR) \
++		CC="`echo \"$(GCC_FOR_TARGET)\" \
++		| sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'`" \
++	        INCLUDES="$(INCLUDES_FOR_SUBDIR) -I./../.." \
++                CFLAGS="$(GNATLIBCFLAGS_FOR_C) $(PICFLAG_FOR_TARGET)" \
++	        FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \
++		srcdir=$(fsrcdir) \
++	        -f ../Makefile $(LIBGNAT_OBJS)
++	$(MAKE) -C $(RTSDIR) \
++		CC="`echo \"$(GCC_FOR_TARGET)\" \
++		| sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'`" \
++	        ADA_INCLUDES="" \
++                CFLAGS="$(GNATLIBCFLAGS) $(PICFLAG_FOR_TARGET)" \
++	        ADAFLAGS="$(GNATLIBFLAGS) $(PICFLAG_FOR_TARGET)" \
++	        FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \
++		srcdir=$(fsrcdir) \
++	        -f ../Makefile \
++	        $(GNATRTL_OBJS)
++	$(RM) $(RTSDIR)/libgna*$(soext) $(RTSDIR)/libgna*$(soext).1
+ 	cd $(RTSDIR); `echo "$(GCC_FOR_TARGET)" \
+                 | sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'` -shared $(GNATLIBCFLAGS) \
+ 		$(PICFLAG_FOR_TARGET) \
+-		-o libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		-o libgnat$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(GNATRTL_NONTASKING_OBJS) $(LIBGNAT_OBJS) \
+-		$(SO_OPTS)libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		$(SO_OPTS)libgnat$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(MISCLIB) -lm $(GNATLIBLDFLAGS)
+ 	cd $(RTSDIR); `echo "$(GCC_FOR_TARGET)" \
+                 | sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'` -shared $(GNATLIBCFLAGS) \
+ 		$(PICFLAG_FOR_TARGET) \
+-		-o libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		-o libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(GNATRTL_TASKING_OBJS) \
+-		$(SO_OPTS)libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		$(SO_OPTS)libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(THREADSLIB) $(GNATLIBLDFLAGS)
+-	cd $(RTSDIR); $(LN_S) libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		libgnat$(soext)
+-	cd $(RTSDIR); $(LN_S) libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		libgnarl$(soext)
++	cd $(RTSDIR); for lib in gnat gnarl; do \
++		l=lib$${lib}$(hyphen)$(LIBRARY_VERSION)$(soext); \
++		$(LN_S) $$l.1 $$l; \
++	done
++	$(CHMOD) a-wx $(RTSDIR)/*.ali
+ 
+ gnatlib-shared-dual:
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+@@ -2855,9 +2742,8 @@ gnatlib-shared-dual:
+              GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib-shared-default
+-	$(MV) $(RTSDIR)/libgna*$(soext) .
+-	$(RM) ../stamp-gnatlib2-$(RTSDIR)
++	     gnatlib
++	$(RM) $(RTSDIR)/*.o $(RTSDIR)/*.ali
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+@@ -2865,8 +2751,7 @@ gnatlib-shared-dual:
+              GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib
+-	$(MV) libgna*$(soext) $(RTSDIR)
++	     gnatlib-shared-default
+ 
+ gnatlib-shared-dual-win32:
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+@@ -2876,17 +2761,15 @@ gnatlib-shared-dual-win32:
+ 	     PICFLAG_FOR_TARGET="$(PICFLAG_FOR_TARGET)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib-shared-win32
+-	$(MV) $(RTSDIR)/libgna*$(soext) .
+-	$(RM) ../stamp-gnatlib2-$(RTSDIR)
++             gnatlib
++	$(RM) $(RTSDIR)/*.o $(RTSDIR)/*.ali
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib
+-	$(MV) libgna*$(soext) $(RTSDIR)
++             gnatlib-shared-win32
+ 
+ # ??? we need to add the option to support auto-import of arrays/records to
+ # the GNATLIBFLAGS when this will be supported by GNAT. At this point we will
+@@ -3136,6 +3019,68 @@ targext.o : targext.c
+ 		$(ALL_CPPFLAGS) $(INCLUDES_FOR_SUBDIR) \
+ 		$< $(OUTPUT_OPTION)
+ 
++GCC_LINK=$(CXX) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS)
++
++../stamp-tools:
++	-$(RM) tools/*
++	-$(RMDIR) tools
++	-$(MKDIR) tools
++	-(cd tools; $(LN_S) ../sdefault.adb ../snames.ads ../snames.adb .)
++	-$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
++	          $(RM) tools/$(word 1,$(subst <, ,$(PAIR)));\
++	          $(LN_S) $(fsrcpfx)ada/$(word 2,$(subst <, ,$(PAIR))) \
++	                tools/$(word 1,$(subst <, ,$(PAIR)));)
++	touch ../stamp-tools
++
++gnatmake-re: ../stamp-tools
++	$(GNATMAKE) -j0 $(ADA_INCLUDES) -u sdefault --GCC="$(CC) $(MOST_ADA_FLAGS)"
++	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatmake --GCC="$(CC) $(ALL_ADAFLAGS)"
++	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatmake
++	$(GNATLINK) -v gnatmake -o ../../gnatmake$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++
++# Note the use of the "mv" command in order to allow gnatlink to be linked with
++# with the former version of gnatlink itself which cannot override itself.
++# gnatlink-re cannot be run at the same time as gnatmake-re, hence the
++# dependency
++gnatlink-re: ../stamp-tools gnatmake-re
++	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatlink --GCC="$(CC) $(ALL_ADAFLAGS)"
++	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatlink
++	$(GNATLINK) -v gnatlink -o ../../gnatlinknew$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(MV)  ../../gnatlinknew$(exeext)  ../../gnatlink$(exeext)
++
++# Likewise for the tools
++../../gnatmake$(exeext): $(P) b_gnatm.o $(GNATMAKE_OBJS)
++	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS)
++
++../../gnatlink$(exeext): $(P) b_gnatl.o $(GNATLINK_OBJS)
++	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS)
++
++common-tools: ../stamp-tools
++	$(GNATMAKE) -j0 -c -b $(ADA_INCLUDES) \
++	  --GNATBIND="$(GNATBIND)" --GCC="$(CC) $(ALL_ADAFLAGS)" \
++	  gnatchop gnatcmd gnatkr gnatls gnatprep gnatxref gnatfind gnatname \
++	  gnatclean -bargs $(ADA_INCLUDES) $(GNATBIND_FLAGS)
++	$(GNATLINK) -v gnatcmd -o ../../gnat$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatchop -o ../../gnatchop$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatkr -o ../../gnatkr$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatls -o ../../gnatls$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatprep -o ../../gnatprep$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatxref -o ../../gnatxref$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatfind -o ../../gnatfind$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatname -o ../../gnatname$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatclean -o ../../gnatclean$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++
+ # In GNU Make, ignore whether `stage*' exists.
+ .PHONY: stage1 stage2 stage3 stage4 clean realclean TAGS bootstrap
+ .PHONY: risky-stage1 risky-stage2 risky-stage3 risky-stage4
+Index: b/src/gnattools/Makefile.in
+===================================================================
+--- a/src/gnattools/Makefile.in
++++ b/src/gnattools/Makefile.in
+@@ -52,7 +52,7 @@ WARN_CFLAGS = @warn_cflags@
+ ADA_CFLAGS=@ADA_CFLAGS@
+ 
+ # Variables for gnattools.
+-ADAFLAGS= -gnatpg -gnata
++ADAFLAGS= -gnatn
+ 
+ # For finding the GCC build dir, which is used far too much
+ GCC_DIR=../gcc
+@@ -70,28 +70,168 @@ INCLUDES_FOR_SUBDIR = -iquote . -iquote
+ ADA_INCLUDES_FOR_SUBDIR = -I. -I$(fsrcdir)/ada
+ 
+ CXX_LFLAGS = \
+- -B../../../$(target_noncanonical)/libstdc++-v3/src/.libs \
+- -B../../../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs \
+- -L../../../$(target_noncanonical)/libstdc++-v3/src/.libs \
+- -L../../../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs
++ -B../$(target_noncanonical)/libstdc++-v3/src/.libs \
++ -B../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs \
++ -L../$(target_noncanonical)/libstdc++-v3/src/.libs \
++ -L../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs \
++ -L../$(target_noncanonical)/libatomic/.libs
++
++CFLAGS=-O2 -Wall
++ADA_CFLAGS=-O2 -gnatn
++ADA_INCLUDES=-nostdinc -I- -I. -I../gcc/ada/rts \
++     -I../$(target_noncanonical)/libgnatvsn -I../$(target_noncanonical)/libgnatprj
++LIB_VERSION=$(strip $(shell grep ' Library_Version :' \
++              ../$(target_noncanonical)/libgnatvsn/gnatvsn.ads | sed -e 's/.*"\(.*\)".*/\1/'))
++SHARED_ADA_LIBS := -L../gcc/ada/rts -lgnat-$(LIB_VERSION)
++SHARED_ADA_LIBS += -L../$(target_noncanonical)/libgnatvsn -lgnatvsn
++SHARED_ADA_LIBS += -L../$(target_noncanonical)/libgnatprj -lgnatprj
++STATIC_ADA_LIBS := ../gcc/ada/rts/libgnat.a
++STATIC_GCC_LIBS := ../gcc/libcommon-target.a ../gcc/libcommon.a ../libcpp/libcpp.a \
++../libbacktrace/.libs/libbacktrace.a ../libiberty/libiberty.a
++
++# We will use the just-built compiler to compile and link everything.
++GCC=../gcc/xgcc -B../gcc/ -no-pie
++GXX=../gcc/xg++ -B../gcc/ -no-pie
++
++# File lists
++# ----------
++
++# File associations set by configure
++EXTRA_GNATTOOLS = @EXTRA_GNATTOOLS@
++TOOLS_TARGET_PAIRS = @TOOLS_TARGET_PAIRS@
++
++# Stage 1 builds xgcc and gnatbind; we can use them to build
++# gnatmake-static and gnatlink-static, then use gnatmake-static and
++# gnatlink-static to build the other tools.  The reason we first build
++# statically-linked versions of gnatmake and gnatlink is so we can run
++# them with confidence on all build platforms, without LD_LIBRARY_PATH
++# or some such variable.
++
++# The tools we will build using gnatmake-static and gnatlink-static.
++TOOLS := gnat gnatbind gnatchop gnatclean gnatfind gnatkr gnatls gnatlink
++TOOLS += gnatmake gnatname gnatprep gnatxref
++
++# Since we don't have gnatmake, we must specify the full list of
++# object files necessary to build gnatmake and gnatlink.
++GNATLINK_OBJS = \
++gnatlink.o \
++indepsw.o \
++validsw.o \
++link.o
++
++GNATMAKE_OBJS = \
++aspects.o \
++errout.o \
++fname-sf.o \
++gnatmake.o \
++make.o \
++makeusg.o \
++mlib-prj.o \
++osint-m.o \
++restrict.o \
++sem_aux.o \
++usage.o \
++validsw.o \
++link.o \
++$(EXTRA_GNATMAKE_OBJS)
++
++EXTRA_TOOLS_OBJS = \
++bcheck.o \
++binde.o \
++bindgen.o \
++bindusg.o \
++clean.o \
++gprep.o \
++makegpr.o \
++osint-b.o \
++osint-l.o \
++prep.o \
++prj-makr.o \
++prj-pp.o \
++switch-b.o \
++vms_cmds.o \
++vms_conv.o \
++vms_data.o \
++xr_tabls.o \
++xref_lib.o
++
++OBJECTS = $(GNATLINK_OBJS) $(GNATMAKE_OBJS) $(EXTRA_TOOLS_OBJS)
++
++# Makefile targets
++# ----------------
++
++.PHONY: gnattools gnattools-native gnattools-cross regnattools
++gnattools: @default_gnattools_target@
++
++BODIES := $(foreach f,$(OBJECTS),$(wildcard $(patsubst %.o,@srcdir@/../gcc/ada/%.adb,$(f))))
++SPECS  := $(foreach f,$(OBJECTS),$(wildcard $(patsubst %.o,@srcdir@/../gcc/ada/%.ads,$(f))))
++
++$(notdir $(SPECS) $(BODIES)): stamp-gnattools-sources
++
++stamp-gnattools-sources:
++	for file in $(BODIES) $(SPECS); do \
++	   $(LN_S) -f $$file .; \
++	done
++	rm -f sdefault.adb; $(LN_S) ../gcc/ada/sdefault.adb .
++	$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
++	          rm -f $(word 1,$(subst <, ,$(PAIR)));\
++	          $(LN_S) @srcdir@/../gcc/ada/$(word 2,$(subst <, ,$(PAIR))) \
++	                  $(word 1,$(subst <, ,$(PAIR)));)
++	touch $@
++
++gnattools-native: ../gcc/ada/rts/libgnat-$(LIB_VERSION).so
++gnattools-native: ../$(target_noncanonical)/libgnatvsn/libgnatvsn.so
++gnattools-native: stamp-gnattools-sources
++gnattools-native: $(TOOLS)
++	cp -lpf $(TOOLS) ../gcc
++
++$(TOOLS) gnatcmd: | gnatmake-static gnatlink-static
++
++vpath %.c @srcdir@/../gcc/ada:@srcdir@/../gcc
++vpath %.h @srcdir@/../gcc/ada
++
++# gnatlink
++
++gnatlink-static: $(GNATLINK_OBJS) b_gnatl.o
++	$(GXX) -o $@ $^ \
++	  ../$(target_noncanonical)/libgnatprj/libgnatprj.a \
++	  ../$(target_noncanonical)/libgnatvsn/libgnatvsn.a \
++	  ../gcc/ada/rts/libgnat.a $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++gnatlink: $(GNATLINK_OBJS) b_gnatl.o
++	$(GXX) -o $@ $^ $(SHARED_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++b_gnatl.adb: $(GNATLINK_OBJS)
++	../gcc/gnatbind -o $@ $(ADA_INCLUDES) gnatlink.ali
++
++# gnatmake
++
++gnatmake-static: $(GNATMAKE_OBJS) b_gnatm.o
++	$(GXX) -o $@ $(ADA_CFLAGS) $^ \
++	  ../$(target_noncanonical)/libgnatprj/libgnatprj.a \
++	  ../$(target_noncanonical)/libgnatvsn/libgnatvsn.a \
++	  $(STATIC_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++gnatmake: $(GNATMAKE_OBJS) b_gnatm.o
++	$(GXX) -o $@ $(ADA_CFLAGS) $^ $(SHARED_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++b_gnatm.adb: $(GNATMAKE_OBJS)
++	../gcc/gnatbind -o $@ $(ADA_INCLUDES) gnatmake.ali
++
++# Other tools
++gnat: gnatcmd
++	cp -lp $< $@
++
++gnatbind gnatchop gnatclean gnatcmd gnatfind gnatkr gnatls gnatname gnatprep \
++gnatxref: link.o
++	if [ ! -f $@.adb ] ; then $(LN_S) ../../src/gcc/ada/$@.ad[bs] .; fi
++	./gnatmake-static -c -b $@ $(ADA_CFLAGS) $(ADA_INCLUDES) \
++	   --GCC="$(GCC)" \
++	   --GNATBIND=../gcc/gnatbind
++	./gnatlink-static -o $@ $@.ali $^ \
++	   $(ADA_INCLUDES) $(SHARED_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS) \
++	   --GCC="$(GXX) $(ADA_INCLUDES)"
+ 
+-# Variables for gnattools, native
+-TOOLS_FLAGS_TO_PASS_NATIVE= \
+-	"CC=../../xgcc -B../../" \
+-	"CXX=../../xg++ -B../../ $(CXX_LFLAGS)" \
+-	"CFLAGS=$(CFLAGS) $(WARN_CFLAGS)" \
+-	"LDFLAGS=$(LDFLAGS)" \
+-	"ADAFLAGS=$(ADAFLAGS)" \
+-	"ADA_CFLAGS=$(ADA_CFLAGS)" \
+-	"INCLUDES=$(INCLUDES_FOR_SUBDIR)" \
+-	"ADA_INCLUDES=-I- -I../rts $(ADA_INCLUDES_FOR_SUBDIR)"\
+-	"exeext=$(exeext)" \
+-	"fsrcdir=$(fsrcdir)" \
+-	"srcdir=$(fsrcdir)" \
+-	"GNATMAKE=../../gnatmake" \
+-	"GNATLINK=../../gnatlink" \
+-	"GNATBIND=../../gnatbind" \
+-	"TOOLSCASE=native"
+ 
+ # Variables for regnattools
+ TOOLS_FLAGS_TO_PASS_RE= \
+@@ -184,20 +324,12 @@ $(GCC_DIR)/stamp-tools:
+ 	                $(GCC_DIR)/ada/tools/$(word 1,$(subst <, ,$(PAIR)));)
+ 	touch $(GCC_DIR)/stamp-tools
+ 
+-# gnatmake/link tools cannot always be built with gnatmake/link for bootstrap 
+-# reasons: gnatmake should be built with a recent compiler, a recent compiler
+-# may not generate ALI files compatible with an old gnatmake so it is important
+-# to be able to build gnatmake without a version of gnatmake around. Once 
+-# everything has been compiled once, gnatmake can be recompiled with itself 
+-# (see target regnattools) 
+-gnattools-native: $(GCC_DIR)/stamp-tools $(GCC_DIR)/stamp-gnatlib-rts
+-	# gnattools1
+-	$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \
+-	  $(TOOLS_FLAGS_TO_PASS_NATIVE) \
+-	  ../../gnatmake$(exeext) ../../gnatlink$(exeext)
+-	# gnattools2
+-	$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \
+-	  $(TOOLS_FLAGS_TO_PASS_NATIVE) common-tools
++%.o: %.adb
++	$(GCC) -c -o $@ $< $(ADA_CFLAGS) $(ADA_INCLUDES)
++
++%.o: %.ads
++	$(GCC) -c -o $@ $< $(ADA_CFLAGS) $(ADA_INCLUDES)
++
+ 
+ # gnatmake/link can be built with recent gnatmake/link if they are available.
+ # This is especially convenient for building cross tools or for rebuilding
--- gcc-6-6.3.0.orig/debian/patches/ada-gnattools-ldflags.diff
+++ gcc-6-6.3.0/debian/patches/ada-gnattools-ldflags.diff
@@ -0,0 +1,96 @@
+# DP: Link gnat tools with the defaults LDFLAGS
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -111,6 +111,7 @@ NO_SIBLING_ADAFLAGS = -fno-optimize-sibl
+ NO_REORDER_ADAFLAGS = -fno-toplevel-reorder
+ GNATLIBFLAGS = -W -Wall -gnatpg -nostdinc
+ GNATLIBCFLAGS = -g -O2
++GNATLIBLDFLAGS = $(LDFLAGS)
+ # Pretend that _Unwind_GetIPInfo is available for the target by default.  This
+ # should be autodetected during the configuration of libada and passed down to
+ # here, but we need something for --disable-libada and hope for the best.
+@@ -2586,23 +2587,23 @@ common-tools: ../stamp-tools
+ 	  gnatchop gnatcmd gnatkr gnatls gnatprep gnatxref gnatfind gnatname \
+ 	  gnatclean -bargs $(ADA_INCLUDES) $(GNATBIND_FLAGS)
+ 	$(GNATLINK) -v gnatcmd -o ../../gnat$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatchop -o ../../gnatchop$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatkr -o ../../gnatkr$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatls -o ../../gnatls$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatprep -o ../../gnatprep$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatxref -o ../../gnatxref$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatfind -o ../../gnatfind$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatname -o ../../gnatname$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatclean -o ../../gnatclean$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 
+ ../../gnatdll$(exeext): ../stamp-tools
+ 	$(GNATMAKE) -c $(ADA_INCLUDES) gnatdll --GCC="$(CC) $(ALL_ADAFLAGS)"
+@@ -2830,14 +2831,14 @@ gnatlib-shared-default:
+ 		-o libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+ 		$(GNATRTL_NONTASKING_OBJS) $(LIBGNAT_OBJS) \
+ 		$(SO_OPTS)libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		$(MISCLIB) -lm
++		$(MISCLIB) -lm $(GNATLIBLDFLAGS)
+ 	cd $(RTSDIR); `echo "$(GCC_FOR_TARGET)" \
+                 | sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'` -shared $(GNATLIBCFLAGS) \
+ 		$(PICFLAG_FOR_TARGET) \
+ 		-o libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+ 		$(GNATRTL_TASKING_OBJS) \
+ 		$(SO_OPTS)libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		$(THREADSLIB)
++		$(THREADSLIB) $(GNATLIBLDFLAGS)
+ 	cd $(RTSDIR); $(LN_S) libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+ 		libgnat$(soext)
+ 	cd $(RTSDIR); $(LN_S) libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+@@ -2848,6 +2849,7 @@ gnatlib-shared-dual:
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+              gnatlib-shared-default
+@@ -2857,6 +2859,7 @@ gnatlib-shared-dual:
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+              gnatlib
+@@ -2944,6 +2947,7 @@ gnatlib-shared:
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+ 	     PICFLAG_FOR_TARGET="$(PICFLAG_FOR_TARGET)" \
+@@ -2989,6 +2993,7 @@ gnatlib-zcx:
+ 	     GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
--- gcc-6-6.3.0.orig/debian/patches/ada-kfreebsd.diff
+++ gcc-6-6.3.0/debian/patches/ada-kfreebsd.diff
@@ -0,0 +1,306 @@
+# DP: add support for GNU/kFreeBSD.
+
+Index: b/src/gcc/ada/terminals.c
+===================================================================
+--- a/src/gcc/ada/terminals.c
++++ b/src/gcc/ada/terminals.c
+@@ -1071,7 +1071,8 @@ __gnat_setup_winsize (void *desc, int ro
+ /* On some system termio is either absent or including it will disable termios
+    (HP-UX) */
+ #if !defined (__hpux__) && !defined (BSD) && !defined (__APPLE__) \
+-  && !defined (__rtems__)
++  && ! defined (__FreeBSD_kernel__) && ! defined (__GNU__) \
++  && ! defined (__rtems__)
+ #   include <termio.h>
+ #endif
+ 
+Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.adb
+===================================================================
+--- /dev/null
++++ b/src/gcc/ada/s-osinte-kfreebsd-gnu.adb
+@@ -0,0 +1,158 @@
++------------------------------------------------------------------------------
++--                                                                          --
++--                 GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS                 --
++--                                                                          --
++--                   S Y S T E M . O S _ I N T E R F A C E                  --
++--                                                                          --
++--                                   B o d y                                --
++--                                                                          --
++--             Copyright (C) 1991-1994, Florida State University            --
++--                     Copyright (C) 1995-2006, AdaCore                     --
++--                                                                          --
++-- GNARL is free software; you can  redistribute it  and/or modify it under --
++-- terms of the  GNU General Public License as published  by the Free Soft- --
++-- ware  Foundation;  either version 2,  or (at your option) any later ver- --
++-- sion. GNARL is distributed in the hope that it will be useful, but WITH- --
++-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
++-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License --
++-- for  more details.  You should have  received  a copy of the GNU General --
++-- Public License  distributed with GNARL; see file COPYING.  If not, write --
++-- to  the  Free Software Foundation,  51  Franklin  Street,  Fifth  Floor, --
++-- Boston, MA 02110-1301, USA.                                              --
++--                                                                          --
++-- As a special exception,  if other files  instantiate  generics from this --
++-- unit, or you link  this unit with other files  to produce an executable, --
++-- this  unit  does not  by itself cause  the resulting  executable  to  be --
++-- covered  by the  GNU  General  Public  License.  This exception does not --
++-- however invalidate  any other reasons why  the executable file  might be --
++-- covered by the  GNU Public License.                                      --
++--                                                                          --
++-- GNARL was developed by the GNARL team at Florida State University.       --
++-- Extensive contributions were provided by Ada Core Technologies, Inc.     --
++--                                                                          --
++------------------------------------------------------------------------------
++
++--  This is the GNU/kFreeBSD version of this package.
++
++pragma Polling (Off);
++--  Turn off polling, we do not want ATC polling to take place during
++--  tasking operations. It causes infinite loops and other problems.
++
++--  This package encapsulates all direct interfaces to OS services
++--  that are needed by children of System.
++
++package body System.OS_Interface is
++
++   --------------------
++   -- Get_Stack_Base --
++   --------------------
++
++   function Get_Stack_Base (thread : pthread_t) return Address is
++      pragma Warnings (Off, thread);
++
++   begin
++      return Null_Address;
++   end Get_Stack_Base;
++
++   ------------------
++   -- pthread_init --
++   ------------------
++
++   procedure pthread_init is
++   begin
++      null;
++   end pthread_init;
++
++   -----------------------------------
++   -- pthread_mutexattr_setprotocol --
++   -----------------------------------
++
++   function pthread_mutexattr_setprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : int) return int is
++      pragma Unreferenced (attr, protocol);
++   begin
++      return 0;
++   end pthread_mutexattr_setprotocol;
++
++   -----------------------------------
++   -- pthread_mutexattr_getprotocol --
++   -----------------------------------
++
++   function pthread_mutexattr_getprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : access int) return int is
++      pragma Unreferenced (attr, protocol);
++   begin
++      return 0;
++   end pthread_mutexattr_getprotocol;
++
++   --------------------------------------
++   -- pthread_mutexattr_setprioceiling --
++   --------------------------------------
++
++   function pthread_mutexattr_setprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : int) return int is
++      pragma Unreferenced (attr, prioceiling);
++   begin
++      return 0;
++   end pthread_mutexattr_setprioceiling;
++
++   --------------------------------------
++   -- pthread_mutexattr_getprioceiling --
++   --------------------------------------
++
++   function pthread_mutexattr_getprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : access int) return int is
++      pragma Unreferenced (attr, prioceiling);
++   begin
++      return 0;
++   end pthread_mutexattr_getprioceiling;
++
++   -----------------
++   -- To_Duration --
++   -----------------
++
++   function To_Duration (TS : timespec) return Duration is
++   begin
++      return Duration (TS.tv_sec) + Duration (TS.tv_nsec) / 10#1#E9;
++   end To_Duration;
++
++   ------------------------
++   -- To_Target_Priority --
++   ------------------------
++
++   function To_Target_Priority
++     (Prio : System.Any_Priority) return Interfaces.C.int
++   is
++   begin
++      return Interfaces.C.int (Prio);
++   end To_Target_Priority;
++
++   -----------------
++   -- To_Timespec --
++   -----------------
++
++   function To_Timespec (D : Duration) return timespec is
++      S : time_t;
++      F : Duration;
++
++   begin
++      S := time_t (Long_Long_Integer (D));
++      F := D - Duration (S);
++
++      --  If F has negative value due to a round-up, adjust for positive F
++      --  value.
++
++      if F < 0.0 then
++         S := S - 1;
++         F := F + 1.0;
++      end if;
++
++      return timespec'(tv_sec => S,
++                       tv_nsec => long (Long_Long_Integer (F * 10#1#E9)));
++   end To_Timespec;
++
++end System.OS_Interface;
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -1397,7 +1397,7 @@ ifeq ($(strip $(filter-out %86 kfreebsd%
+   a-intnam.ads<a-intnam-freebsd.ads \
+   s-inmaop.adb<s-inmaop-posix.adb \
+   s-intman.adb<s-intman-posix.adb \
+-  s-osinte.adb<s-osinte-posix.adb \
++  s-osinte.adb<s-osinte-kfreebsd-gnu.adb \
+   s-osinte.ads<s-osinte-kfreebsd-gnu.ads \
+   s-osprim.adb<s-osprim-posix.adb \
+   s-taprop.adb<s-taprop-posix.adb \
+@@ -1457,7 +1457,7 @@ ifeq ($(strip $(filter-out x86_64 kfreeb
+   a-numaux.ads<a-numaux-x86.ads \
+   s-inmaop.adb<s-inmaop-posix.adb \
+   s-intman.adb<s-intman-posix.adb \
+-  s-osinte.adb<s-osinte-posix.adb \
++  s-osinte.adb<s-osinte-kfreebsd-gnu.adb \
+   s-osinte.ads<s-osinte-kfreebsd-gnu.ads \
+   s-osprim.adb<s-osprim-posix.adb \
+   s-taprop.adb<s-taprop-posix.adb \
+Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
+===================================================================
+--- a/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
++++ b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
+@@ -45,6 +45,7 @@ package System.OS_Interface is
+    pragma Preelaborate;
+ 
+    pragma Linker_Options ("-lpthread");
++   pragma Linker_Options ("-lrt");
+ 
+    subtype int            is Interfaces.C.int;
+    subtype char           is Interfaces.C.char;
+@@ -206,9 +207,7 @@ package System.OS_Interface is
+    function nanosleep (rqtp, rmtp : access timespec) return int;
+    pragma Import (C, nanosleep, "nanosleep");
+ 
+-   type clockid_t is private;
+-
+-   CLOCK_REALTIME : constant clockid_t;
++   type clockid_t is new int;
+ 
+    function clock_gettime
+      (clock_id : clockid_t;
+@@ -441,31 +440,25 @@ package System.OS_Interface is
+    PTHREAD_PRIO_PROTECT : constant := 2;
+    PTHREAD_PRIO_INHERIT : constant := 1;
+ 
++   --  GNU/kFreeBSD does not support Thread Priority Protection or Thread
++   --  Priority Inheritance and lacks some pthread_mutexattr_* functions.
++   --  Replace them with dummy versions.
++
+    function pthread_mutexattr_setprotocol
+      (attr     : access pthread_mutexattr_t;
+       protocol : int) return int;
+-   pragma Import
+-      (C, pthread_mutexattr_setprotocol, "pthread_mutexattr_setprotocol");
+ 
+    function pthread_mutexattr_getprotocol
+      (attr     : access pthread_mutexattr_t;
+       protocol : access int) return int;
+-   pragma Import
+-     (C, pthread_mutexattr_getprotocol, "pthread_mutexattr_getprotocol");
+ 
+    function pthread_mutexattr_setprioceiling
+      (attr     : access pthread_mutexattr_t;
+       prioceiling : int) return int;
+-   pragma Import
+-     (C, pthread_mutexattr_setprioceiling,
+-      "pthread_mutexattr_setprioceiling");
+ 
+    function pthread_mutexattr_getprioceiling
+      (attr     : access pthread_mutexattr_t;
+       prioceiling : access int) return int;
+-   pragma Import
+-     (C, pthread_mutexattr_getprioceiling,
+-      "pthread_mutexattr_getprioceiling");
+ 
+    type struct_sched_param is record
+       sched_priority : int;  --  scheduling priority
+@@ -592,8 +585,8 @@ private
+    --  #define sa_handler __sigaction_u._handler
+    --  #define sa_sigaction __sigaction_u._sigaction
+ 
+-   --  Should we add a signal_context type here ?
+-   --  How could it be done independent of the CPU architecture ?
++   --  Should we add a signal_context type here ???
++   --  How could it be done independent of the CPU architecture ???
+    --  sigcontext type is opaque, so it is architecturally neutral.
+    --  It is always passed as an access type, so define it as an empty record
+    --  since the contents are not used anywhere.
+@@ -610,9 +603,6 @@ private
+    end record;
+    pragma Convention (C, timespec);
+ 
+-   type clockid_t is new int;
+-   CLOCK_REALTIME : constant clockid_t := 0;
+-
+    type pthread_attr_t is record
+       detachstate   : int;
+       schedpolicy   : int;
+Index: b/src/gcc/ada/gsocket.h
+===================================================================
+--- a/src/gcc/ada/gsocket.h
++++ b/src/gcc/ada/gsocket.h
+@@ -243,6 +243,7 @@
+ #endif
+ 
+ #if defined (__FreeBSD__) || defined (__vxworks) || defined(__rtems__) \
++ || defined (__FreeBSD_kernel__) || defined(__GNU__) \
+  || defined (__DragonFly__) || defined (__NetBSD__) || defined (__OpenBSD__)
+ # define Has_Sockaddr_Len 1
+ #else
+Index: b/src/gcc/ada/s-oscons-tmplt.c
+===================================================================
+--- a/src/gcc/ada/s-oscons-tmplt.c
++++ b/src/gcc/ada/s-oscons-tmplt.c
+@@ -1436,7 +1436,7 @@ CND(CLOCK_FASTEST, "Fastest clock")
+ CND(CLOCK_THREAD_CPUTIME_ID, "Thread CPU clock")
+ 
+ #if defined(__FreeBSD__) || (defined(_AIX) && defined(_AIXVERSION_530)) \
+- || defined(__DragonFly__)
++ || defined(__DragonFly__) || defined(__FreeBSD_kernel__)
+ /** On these platforms use system provided monotonic clock instead of
+  ** the default CLOCK_REALTIME. We then need to set up cond var attributes
+  ** appropriately (see thread.c).
--- gcc-6-6.3.0.orig/debian/patches/ada-libgnatprj.diff
+++ gcc-6-6.3.0/debian/patches/ada-libgnatprj.diff
@@ -0,0 +1,1991 @@
+t
+# DP: - Introduce a new shared library named libgnatprj, containing
+# DP:   the GNAT project file manager licensed under the pure GPL, for
+# DP:   use in GNAT tools, GLADE and GPS.  Link the GNAT tools against
+# DP:   this new library.
+
+# This patch seems large, but the hunks in Makefile.in are actually
+# generated from Makefile.def using autogen.
+
+# !!! Must be applied after ada-libgnatvsn.dpatch
+
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -34,8 +34,8 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ 
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+-target_libs="target-libada target-libgnatvsn"
+-lang_dirs="libada libgnatvsn gnattools"
++target_libs="target-libada target-libgnatvsn target-libgnatprj"
++lang_dirs="libada libgnatvsn libgnatprj gnattools"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/libgnatprj/Makefile.in
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/Makefile.in
+@@ -0,0 +1,180 @@
++# Makefile for libgnatprj.
++#   Copyright (c) 2006 Ludovic Brenta <ludovic@ludovic-brenta.org>
++#
++# This file is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++# 
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++# 
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++# Default target; must be first.
++all: libgnatprj
++
++.SUFFIXES:
++
++CPUS := $(shell getconf _NPROCESSORS_ONLN)
++LIB_VERSION := $(strip $(shell grep ' Library_Version :' \
++                 @srcdir@/../gcc/ada/gnatvsn.ads | \
++	         sed -e 's/.*"\(.*\)".*/\1/'))
++GCC=$(CC)
++GPP=$(CXX)
++LIBGNAT_JUST_BUILT := -nostdinc -I../../gcc/ada/rts
++LIBGNATVSN := -I../libgnatvsn
++CFLAGS := -g -O2
++ADAFLAGS := -g -O2 -gnatn
++BASEVER := $(shell cat @srcdir@/../gcc/BASE-VER)
++DEVPHASE := $(shell cat @srcdir@/../gcc/DEV-PHASE)
++DATESTAMP := $(shell cat @srcdir@/../gcc/DATESTAMP)
++TOOLS_TARGET_PAIRS := @TOOLS_TARGET_PAIRS@
++LN_S := @LN_S@
++
++ifneq (@build@,@host@)
++   CFLAGS += -b @host@
++endif
++
++.PHONY: libgnatprj install
++libgnatprj: libgnatprj.so.$(LIB_VERSION) libgnatprj.a
++
++# Here we list one file per Ada unit: the body file if the unit has a
++# body, the spec file otherwise.
++PRJ_SOURCES := ali.adb ali-util.adb butil.adb binderr.adb errout.adb \
++erroutc.adb errutil.adb err_vars.ads fname-uf.adb fmap.adb impunit.adb \
++lib-util.adb makeutl.adb mlib.adb mlib-fil.adb mlib-tgt.adb \
++mlib-tgt-specific.adb mlib-utl.adb osint.adb osint-c.adb prj.adb prj-attr.adb \
++prj-attr-pm.adb prj-com.ads prj-conf.adb prj-dect.adb prj-env.adb prj-err.adb \
++prj-ext.adb prj-makr.adb prj-nmsc.adb prj-pars.adb prj-part.adb prj-pp.adb \
++prj-proc.adb prj-strt.adb prj-tree.adb prj-util.adb restrict.adb rident.ads \
++scng.adb sfn_scan.adb sinfo-cn.adb sinput-c.adb sinput-p.adb style.adb \
++styleg.adb stylesw.adb switch.adb switch-m.adb targparm.adb tempdir.adb
++
++# Source files generated in build/gcc/ada, not src/gcc/ada.
++GENERATED_SOURCES := sdefault.adb
++
++SOURCES := $(PRJ_SOURCES) $(GENERATED_SOURCES)
++
++OBJECTS := $(patsubst %.ads,%.o,$(SOURCES:.adb=.o))
++
++# Add some object files compiled from C sources.  prefix.o requires
++# some objects from libiberty and from gcc.
++OBJECTS += link.o prefix.o
++
++# These object files have already been built, both PIC and non-PIC.
++# prefix.o depends on them.
++LIBIBERTY_OBJECTS := concat.o filename_cmp.o lrealpath.o safe-ctype.o xexit.o xmalloc.o xstrdup.o
++
++vpath %.c @srcdir@ @srcdir@/../gcc @srcdir@/../gcc/common @srcdir@/../gcc/ada
++
++libgnatprj.so.$(LIB_VERSION): $(addprefix obj-shared/,$(OBJECTS))
++	: # Make libgnatprj.so
++	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ -Wl,--no-allow-shlib-undefined \
++	   $^ $(addprefix ../libiberty/pic/,$(LIBIBERTY_OBJECTS)) \
++	   -L../../gcc/ada/rts -lgnat-$(LIB_VERSION) \
++	   -L../libgnatvsn -lgnatvsn $(LDFLAGS)
++	$(LN_S) -f libgnatprj.so.$(LIB_VERSION) libgnatprj.so
++	chmod a=r obj-shared/*.ali
++# Make the .ali files, but not the .o files, visible to the gnat tools.
++	cp -lp obj-shared/*.ali .
++
++$(addprefix obj-shared/,$(OBJECTS)): | stamp-libgnatprj-sources obj-shared
++
++obj-shared/%.o: %.adb
++	$(GCC) -c -fPIC $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-shared/%.o: %.ads
++	$(GCC) -c -fPIC $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-shared/%.o: %.c
++	$(GPP) -c -fPIC $(CFLAGS) -DHAVE_CONFIG_H -pedantic \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I@srcdir@/../libcpp/include -I../../gcc -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-shared/prefix.o: @srcdir@/../gcc/prefix.c
++	$(GPP) -c -fPIC $(CFLAGS) -DPREFIX=\"@prefix@\" -DBASEVER=\"$(BASEVER)\" \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I../../gcc -I@srcdir@/../libcpp/include -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-shared:
++	-mkdir $@
++
++libgnatprj.a: $(addprefix obj-static/,$(OBJECTS))
++	: # Make libgnatprj.a
++	ar rc $@ $^ $(addprefix ../libiberty/,$(LIBIBERTY_OBJECTS))
++	ranlib $@
++
++$(addprefix obj-static/,$(OBJECTS)): | stamp-libgnatprj-sources obj-static
++
++obj-static/%.o: %.adb
++	$(GCC) -c $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-static/%.o: %.ads
++	$(GCC) -c $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-static/%.o: %.c
++	$(GPP) -c $(CFLAGS) -DHAVE_CONFIG_H -pedantic \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I@srcdir@/../libcpp/include -I../../gcc -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-static/prefix.o: @srcdir@/../gcc/prefix.c
++	$(GPP) -c $(CFLAGS) -DPREFIX=\"@prefix@\" -DBASEVER=\"$(BASEVER)\" \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I../../gcc -I@srcdir@/../libcpp/include -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-static:
++	-mkdir $@
++
++$(SOURCES): stamp-libgnatprj-sources
++
++stamp-libgnatprj-sources:
++	for file in $(PRJ_SOURCES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f @srcdir@/../gcc/ada/$$file -a ! -L $$file ] ; then $(LN_S) @srcdir@/../gcc/ada/$$file .; fi; \
++	   if [ -f @srcdir@/../gcc/ada/$$ads -a ! -L $$ads ] ; then $(LN_S) @srcdir@/../gcc/ada/$$ads .; fi; \
++	done
++	for file in $(GENERATED_SOURCES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f ../../gcc/ada/$$file -a ! -L $$file ] ; then $(LN_S) ../../gcc/ada/$$file .; fi; \
++	   if [ -f ../../gcc/ada/$$ads -a ! -L $$ads ] ; then $(LN_S) ../../gcc/ada/$$ads .; \
++	   else \
++	      if [ -f @srcdir@/../gcc/ada/$$ads -a ! -L $$ads ] ; then $(LN_S) @srcdir@/../gcc/ada/$$ads .; fi; \
++	   fi; \
++	done
++	$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
++	          rm -f $(word 1,$(subst <, ,$(PAIR)));\
++	          $(LN_S) @srcdir@/../gcc/ada/$(word 2,$(subst <, ,$(PAIR))) \
++	                  $(word 1,$(subst <, ,$(PAIR)));)
++	touch $@
++
++# Generate a list of source files (.ads and .adb) to install.  Almost
++# all of them are in src/gcc/ada, but some are generated during build
++# and are in build/gcc/ada.
++BODIES := $(filter %.adb,$(PRJ_SOURCES))
++SPECS := $(filter %.ads,$(PRJ_SOURCES)) $(patsubst %.adb,%.ads,$(BODIES) $(GENERATED_SOURCES))
++SOURCES_TO_INSTALL := \
++$(addprefix  @srcdir@/../gcc/ada/,$(SPECS) $(BODIES)) \
++$(addprefix ../../gcc/ada/,$(GENERATED_SOURCES))
++
++libdir = @libdir@
++
++install: libgnatprj
++	$(INSTALL_DATA) libgnatprj.a $(DESTDIR)$(libdir)
++	$(INSTALL_DATA) libgnatprj.so.$(LIB_VERSION) $(DESTDIR)$(libdir)
++	cd $(DESTDIR)$(libdir); ln -sf libgnatprj.so.$(LIB_VERSION) libgnatprj.so
++	mkdir -p $(DESTDIR)$(prefix)/share/ada/adainclude/gnatprj
++	$(INSTALL_DATA) $(SOURCES_TO_INSTALL) \
++	   $(DESTDIR)$(prefix)/share/ada/adainclude/gnatprj
++	mkdir -p $(DESTDIR)$(prefix)/lib/ada/adalib/gnatprj
++	$(INSTALL) -m 0444 obj-shared/*.ali \
++	   $(DESTDIR)$(prefix)/lib/ada/adalib/gnatprj
++	chmod a=r $(DESTDIR)$(prefix)/lib/ada/adalib/gnatprj/*.ali
++
++.PHONY: clean
++clean:
++	rm -rf *.ali obj-static obj-shared libgnatprj* *.adb *.ads stamp*
+Index: b/src/libgnatprj/targetm.c
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/targetm.c
+@@ -0,0 +1,7 @@
++#include "config.h"
++#include "system.h"
++#include "coretypes.h"
++#include "common/common-target.h"
++#include "common/common-target-def.h"
++
++struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -190,6 +190,13 @@ target_modules = { module= libgnatvsn; n
+ 		   missing= TAGS;
+ 		   missing= install-info;
+ 		   missing= installcheck; };
++target_modules = { module= libgnatprj; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgomp; bootstrap= true; lib_path=.libs; };
+ target_modules = { module= libitm; lib_path=.libs; };
+ target_modules = { module= libatomic; lib_path=.libs; };
+@@ -389,8 +396,12 @@ dependencies = { module=all-fixincludes;
+ dependencies = { module=all-target-libada; on=all-gcc; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libgnatvsn; };
++dependencies = { module=all-gnattools; on=all-target-libgnatprj; };
+ dependencies = { module=all-target-libgnatvsn; on=all-target-libada; };
++dependencies = { module=all-target-libgnatprj; on=all-target-libgnatvsn; };
++dependencies = { module=all-target-libgnatprj; on=all-target-libiberty; };
+ dependencies = { module=all-gnattools; on=all-target-libstdc++-v3; };
++dependencies = { module=all-target-libgnatvsn; on=all-target-libstdc++-v3; };
+ 
+ // Depending on the specific configuration, the LTO plugin will either use the
+ // generic libiberty build or the specific build for linker plugins.
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -178,6 +178,7 @@ target_libraries="target-libgcc \
+ 		target-libada \
+ 		${target_libiberty} \
+ 		target-libgnatvsn \
++		target-libgnatprj \
+ 		target-libgo"
+ 
+ # these tools are built using the target libraries, and are intended to
+@@ -462,7 +463,7 @@ AC_ARG_ENABLE(libada,
+ ENABLE_LIBADA=$enableval,
+ ENABLE_LIBADA=yes)
+ if test "${ENABLE_LIBADA}" != "yes" ; then
+-  noconfigdirs="$noconfigdirs target-libgnatvsn gnattools"
++  noconfigdirs="$noconfigdirs target-libgnatvsn target-libgnatprj gnattools"
+ fi
+ 
+ AC_ARG_ENABLE(libssp,
+Index: b/src/libgnatprj/configure.ac
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/configure.ac
+@@ -0,0 +1,557 @@
++# Configure script for libada.
++#   Copyright 2003, 2004 Free Software Foundation, Inc.
++#
++# This file is free software; you can redistribute it and/or modify it
++# under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful, but
++# WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++# General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++
++AC_INIT
++AC_PREREQ([2.63])
++
++AC_CONFIG_SRCDIR([Makefile.in])
++
++# Start of actual configure tests
++
++AC_PROG_INSTALL
++
++AC_CANONICAL_BUILD
++AC_CANONICAL_HOST
++AC_CANONICAL_TARGET
++
++GCC_NO_EXECUTABLES
++AC_PROG_CC
++AC_GNU_SOURCE
++AC_PROG_CPP_WERROR
++
++AC_PROG_CC_C_O
++# autoconf is lame and doesn't give us any substitution variable for this.
++if eval "test \"`echo '$ac_cv_prog_cc_'${ac_cc}_c_o`\" = no"; then
++  NO_MINUS_C_MINUS_O=yes
++else
++  OUTPUT_OPTION='-o $@'
++fi
++AC_SUBST(NO_MINUS_C_MINUS_O)
++AC_SUBST(OUTPUT_OPTION)
++
++AC_C_CONST
++AC_C_INLINE
++AC_C_BIGENDIAN
++
++dnl When we start using libtool:
++dnl AM_PROG_LIBTOOL
++
++dnl When we start using automake:
++dnl AM_CONFIG_HEADER(config.h:config.in)
++AC_CONFIG_HEADER(config.h:config.in)
++
++sinclude(../config/acx.m4)
++ACX_NONCANONICAL_TARGET
++
++# Need to pass this down for now :-P
++AC_PROG_LN_S
++
++# It's OK to check for header files.  Although the compiler may not be
++# able to link anything, it had better be able to at least compile
++# something.
++AC_CHECK_HEADERS(sys/file.h sys/param.h limits.h stdlib.h malloc.h string.h unistd.h strings.h sys/time.h time.h sys/resource.h sys/stat.h sys/mman.h fcntl.h alloca.h sys/pstat.h sys/sysmp.h sys/sysinfo.h machine/hal_sysinfo.h sys/table.h sys/sysctl.h sys/systemcfg.h stdint.h stdio_ext.h process.h sys/prctl.h)
++AC_HEADER_SYS_WAIT
++AC_HEADER_TIME
++
++# Determine sizes of some types.
++AC_CHECK_SIZEOF([int])
++AC_CHECK_SIZEOF([long])
++AC_CHECK_SIZEOF([size_t])
++
++AC_TYPE_INTPTR_T
++AC_TYPE_UINTPTR_T
++AC_TYPE_SSIZE_T
++
++# Given the above check, we always have uintptr_t or a fallback
++# definition.  So define HAVE_UINTPTR_T in case any imported code
++# relies on it.
++AC_DEFINE(HAVE_UINTPTR_T, 1, [Define if you have the \`uintptr_t' type.])
++
++AC_TYPE_PID_T
++
++# This is the list of functions which libiberty will provide if they
++# are not available on the host.
++
++funcs="asprintf"
++funcs="$funcs atexit"
++funcs="$funcs basename"
++funcs="$funcs bcmp"
++funcs="$funcs bcopy"
++funcs="$funcs bsearch"
++funcs="$funcs bzero"
++funcs="$funcs calloc"
++funcs="$funcs clock"
++funcs="$funcs ffs"
++funcs="$funcs getcwd"
++funcs="$funcs getpagesize"
++funcs="$funcs gettimeofday"
++funcs="$funcs index"
++funcs="$funcs insque"
++funcs="$funcs memchr"
++funcs="$funcs memcmp"
++funcs="$funcs memcpy"
++funcs="$funcs memmem"
++funcs="$funcs memmove"
++funcs="$funcs mempcpy"
++funcs="$funcs memset"
++funcs="$funcs mkstemps"
++funcs="$funcs putenv"
++funcs="$funcs random"
++funcs="$funcs rename"
++funcs="$funcs rindex"
++funcs="$funcs setenv"
++funcs="$funcs snprintf"
++funcs="$funcs sigsetmask"
++funcs="$funcs stpcpy"
++funcs="$funcs stpncpy"
++funcs="$funcs strcasecmp"
++funcs="$funcs strchr"
++funcs="$funcs strdup"
++funcs="$funcs strncasecmp"
++funcs="$funcs strndup"
++funcs="$funcs strnlen"
++funcs="$funcs strrchr"
++funcs="$funcs strstr"
++funcs="$funcs strtod"
++funcs="$funcs strtol"
++funcs="$funcs strtoul"
++funcs="$funcs strtoll"
++funcs="$funcs strtoull"
++funcs="$funcs strverscmp"
++funcs="$funcs tmpnam"
++funcs="$funcs vasprintf"
++funcs="$funcs vfprintf"
++funcs="$funcs vprintf"
++funcs="$funcs vsnprintf"
++funcs="$funcs vsprintf"
++funcs="$funcs waitpid"
++funcs="$funcs setproctitle"
++
++# Also in the old function.def file: alloca, vfork, getopt.
++
++vars="sys_errlist sys_nerr sys_siglist"
++
++checkfuncs="__fsetlocking canonicalize_file_name dup3 getrlimit getrusage \
++ getsysinfo gettimeofday on_exit psignal pstat_getdynamic pstat_getstatic \
++ realpath setrlimit sbrk spawnve spawnvpe strerror strsignal sysconf sysctl \
++ sysmp table times wait3 wait4"
++
++# These are neither executed nor required, but they help keep
++# autoheader happy without adding a bunch of text to acconfig.h.
++if test "x" = "y"; then
++  AC_CHECK_FUNCS(asprintf atexit \
++    basename bcmp bcopy bsearch bzero \
++    calloc canonicalize_file_name clock \
++    dup3 \
++    ffs __fsetlocking \
++    getcwd getpagesize getrlimit getrusage getsysinfo gettimeofday \
++    index insque \
++    memchr memcmp memcpy memmem memmove memset mkstemps \
++    on_exit \
++    psignal pstat_getdynamic pstat_getstatic putenv \
++    random realpath rename rindex \
++    sbrk setenv setproctitle setrlimit sigsetmask snprintf spawnve spawnvpe \
++     stpcpy stpncpy strcasecmp strchr strdup \
++     strerror strncasecmp strndup strnlen strrchr strsignal strstr strtod \
++     strtol strtoul strtoll strtoull strverscmp sysconf sysctl sysmp \
++    table times tmpnam \
++    vasprintf vfprintf vprintf vsprintf \
++    wait3 wait4 waitpid)
++  AC_CHECK_DECLS([basename, ffs, asprintf, vasprintf, snprintf, vsnprintf, strtol, strtoul, strtoll, strtoull])
++  AC_DEFINE(HAVE_SYS_ERRLIST, 1, [Define if you have the sys_errlist variable.])
++  AC_DEFINE(HAVE_SYS_NERR,    1, [Define if you have the sys_nerr variable.])
++  AC_DEFINE(HAVE_SYS_SIGLIST, 1, [Define if you have the sys_siglist variable.])
++fi
++
++# For each of these functions, if the host does not provide the
++# function we want to put FN.o in LIBOBJS, and if the host does
++# provide the function, we want to define HAVE_FN in config.h.
++
++setobjs=
++CHECK=
++if test -n "${with_target_subdir}"; then
++
++  # We are being configured as a target library.  AC_REPLACE_FUNCS
++  # may not work correctly, because the compiler may not be able to
++  # link executables.  Note that we may still be being configured
++  # native.
++
++  # If we are being configured for newlib, we know which functions
++  # newlib provide and which ones we will be expected to provide.
++
++  if test "x${with_newlib}" = "xyes"; then
++    AC_LIBOBJ([asprintf])
++    AC_LIBOBJ([basename])
++    AC_LIBOBJ([insque])
++    AC_LIBOBJ([random])
++    AC_LIBOBJ([strdup])
++    AC_LIBOBJ([vasprintf])
++
++    for f in $funcs; do
++      case "$f" in
++	asprintf | basename | insque | random | strdup | vasprintf)
++	  ;;
++	*)
++	  n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++	  AC_DEFINE_UNQUOTED($n)
++	  ;;
++      esac
++    done
++
++    # newlib doesnt provide any of the variables in $vars, so we
++    # dont have to check them here.
++
++    # Of the functions in $checkfuncs, newlib only has strerror.
++    AC_DEFINE(HAVE_STRERROR)
++
++    setobjs=yes
++
++  fi
++
++  # If we are being configured for Mingw, we know which functions
++  # Mingw provides and which ones we will be expected to provide.
++
++  case "${host}" in
++  *-*-mingw*)
++    AC_LIBOBJ([asprintf])
++    AC_LIBOBJ([basename])
++    AC_LIBOBJ([bcmp])
++    AC_LIBOBJ([bcopy])
++    AC_LIBOBJ([bzero])
++    AC_LIBOBJ([clock])
++    AC_LIBOBJ([ffs])
++    AC_LIBOBJ([getpagesize])
++    AC_LIBOBJ([index])
++    AC_LIBOBJ([insque])
++    AC_LIBOBJ([mempcpy])
++    AC_LIBOBJ([mkstemps])
++    AC_LIBOBJ([random])
++    AC_LIBOBJ([rindex])
++    AC_LIBOBJ([sigsetmask])
++    AC_LIBOBJ([stpcpy])
++    AC_LIBOBJ([stpncpy])
++    AC_LIBOBJ([strndup])
++    AC_LIBOBJ([strnlen])
++    AC_LIBOBJ([strverscmp])
++    AC_LIBOBJ([vasprintf])
++    AC_LIBOBJ([waitpid])
++
++    for f in $funcs; do
++      case "$f" in
++	asprintf | basename | bcmp | bcopy | bzero | clock | ffs | getpagesize | index | insque | mempcpy | mkstemps | random | rindex | sigsetmask | stpcpy | stpncpy | strdup | strndup | strnlen | strverscmp | vasprintf | waitpid)
++	  ;;
++	*)
++	  n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++	  AC_DEFINE_UNQUOTED($n)
++	  ;;
++      esac
++    done
++
++    # Mingw doesnt provide any of the variables in $vars, so we
++    # dont have to check them here.
++
++    # Of the functions in $checkfuncs, Mingw only has strerror.
++    AC_DEFINE(HAVE_STRERROR)
++
++    setobjs=yes
++    ;;
++
++  *-*-msdosdjgpp)
++    AC_LIBOBJ([vasprintf])
++    AC_LIBOBJ([vsnprintf])
++    AC_LIBOBJ([snprintf])
++    AC_LIBOBJ([asprintf])
++
++    for f in atexit basename bcmp bcopy bsearch bzero calloc clock ffs \
++             getcwd getpagesize getrusage gettimeofday \
++             index insque memchr memcmp memcpy memmove memset psignal \
++             putenv random rename rindex sbrk setenv stpcpy strcasecmp \
++             strchr strdup strerror strncasecmp strrchr strstr strtod \
++             strtol strtoul sysconf times tmpnam vfprintf vprintf \
++             vsprintf waitpid
++    do
++      n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++      AC_DEFINE_UNQUOTED($n)
++    done
++
++
++    setobjs=yes
++    ;;
++
++  esac
++
++else
++
++   # Not a target library, so we set things up to run the test suite.
++   CHECK=really-check
++
++fi
++
++AC_SUBST(CHECK)
++AC_SUBST(target_header_dir)
++
++case "${host}" in
++  *-*-cygwin* | *-*-mingw*)
++    AC_DEFINE(HAVE_SYS_ERRLIST)
++    AC_DEFINE(HAVE_SYS_NERR)
++    ;;
++esac
++
++if test -z "${setobjs}"; then
++  case "${host}" in
++
++  *-*-vxworks*)
++    # Handle VxWorks configuration specially, since on VxWorks the
++    # libraries are actually on the target board, not in the file
++    # system.
++    AC_LIBOBJ([basename])
++    AC_LIBOBJ([getpagesize])
++    AC_LIBOBJ([insque])
++    AC_LIBOBJ([random])
++    AC_LIBOBJ([strcasecmp])
++    AC_LIBOBJ([strncasecmp])
++    AC_LIBOBJ([strdup])
++    AC_LIBOBJ([vfork])
++    AC_LIBOBJ([waitpid])
++    AC_LIBOBJ([vasprintf])
++    for f in $funcs; do
++      case "$f" in
++	basename | getpagesize | insque | random | strcasecmp)
++	  ;;
++	strncasecmp | strdup | vfork | waitpid | vasprintf)
++	  ;;
++	*)
++	  n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++	  AC_DEFINE_UNQUOTED($n)
++	  ;;
++      esac
++    done
++
++    # VxWorks doesn't provide any of the variables in $vars, so we
++    # don't have to check them here.
++
++    # Of the functions in $checkfuncs, VxWorks only has strerror.
++    AC_DEFINE(HAVE_STRERROR)
++
++    setobjs=yes
++    ;;
++
++  esac
++fi
++
++if test -z "${setobjs}"; then
++
++  case "${host}" in
++
++  *-*-android*)
++    # On android, getpagesize is defined in unistd.h as a static inline
++    # function, which AC_CHECK_FUNCS does not handle properly.
++    ac_cv_func_getpagesize=yes
++    ;;
++
++  *-*-mingw32*)
++    # Under mingw32, sys_nerr and sys_errlist exist, but they are
++    # macros, so the test below won't find them.
++    libgnatprj_cv_var_sys_nerr=yes
++    libgnatprj_cv_var_sys_errlist=yes
++    ;;
++
++  *-*-msdosdjgpp*)
++    # vfork and fork are stubs.
++    ac_cv_func_vfork_works=no
++    ;;
++
++  *-*-uwin*)
++    # Under some versions of uwin, vfork is notoriously buggy and the test 
++    # can hang configure; on other versions, vfork exists just as a stub.
++    # FIXME: This should be removed once vfork in uwin's runtime is fixed.
++    ac_cv_func_vfork_works=no
++    # Under uwin 2.0+, sys_nerr and sys_errlist exist, but they are
++    # macros (actually, these are imported from a DLL, but the end effect 
++    # is the same), so the test below won't find them.
++    libgnatprj_cv_var_sys_nerr=yes
++    libgnatprj_cv_var_sys_errlist=yes
++    ;;
++
++  *-*-*vms*)
++    # Under VMS, vfork works very different than on Unix. The standard test 
++    # won't work, and it isn't easily adaptable. It makes more sense to
++    # just force it.
++    ac_cv_func_vfork_works=yes
++    ;;
++
++  esac
++
++  # We haven't set the list of objects yet.  Use the standard autoconf
++  # tests.  This will only work if the compiler works.
++  AC_ISC_POSIX
++  AC_REPLACE_FUNCS($funcs)
++  AC_FUNC_FORK
++  if test $ac_cv_func_vfork_works = no; then
++    AC_LIBOBJ([vfork])
++  fi
++  # We only need _doprnt if we might use it to implement v*printf.
++  if test $ac_cv_func_vprintf != yes \
++     || test $ac_cv_func_vfprintf != yes \
++     || test $ac_cv_func_vsprintf != yes; then
++    AC_REPLACE_FUNCS(_doprnt)
++  else
++    AC_CHECK_FUNCS(_doprnt)
++  fi
++
++  for v in $vars; do
++    AC_MSG_CHECKING([for $v])
++    AC_CACHE_VAL(libgnatprj_cv_var_$v,
++      [AC_LINK_IFELSE([AC_LANG_PROGRAM([[int *p;]],[[extern int $v []; p = $v;]])],
++		      [eval "libgnatprj_cv_var_$v=yes"],
++		      [eval "libgnatprj_cv_var_$v=no"])])
++    if eval "test \"`echo '$libgnatprj_cv_var_'$v`\" = yes"; then
++      AC_MSG_RESULT(yes)
++      n=HAVE_`echo $v | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++      AC_DEFINE_UNQUOTED($n)
++    else
++      AC_MSG_RESULT(no)
++    fi
++  done
++
++  # special check for _system_configuration because AIX <4.3.2 do not
++  # contain the `physmem' member.
++  AC_MSG_CHECKING([for external symbol _system_configuration])
++  AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include <sys/systemcfg.h>]],
++			[[double x = _system_configuration.physmem;]])],
++    [AC_MSG_RESULT([yes])
++    AC_DEFINE(HAVE__SYSTEM_CONFIGURATION, 1,
++	      [Define if you have the _system_configuration variable.])],
++    [AC_MSG_RESULT([no])])
++
++  AC_CHECK_FUNCS($checkfuncs)
++  AC_CHECK_DECLS([basename, ffs, asprintf, vasprintf, snprintf, vsnprintf])
++  AC_CHECK_DECLS([calloc, getenv, getopt, malloc, realloc, sbrk])
++  AC_CHECK_DECLS([strtol, strtoul, strtoll, strtoull])
++  AC_CHECK_DECLS([strverscmp])
++fi
++
++# Determine x_ada_cflags
++case $host in
++  hppa*) x_ada_cflags=-mdisable-indexing ;;
++  *) x_ada_cflags= ;;
++esac
++AC_SUBST([x_ada_cflags])
++
++# Determine what to build for 'gnattools'
++if test $build = $target ; then
++  # Note that build=target is almost certainly the wrong test; FIXME
++  default_gnattools_target="gnattools-native"
++else
++  default_gnattools_target="gnattools-cross"
++fi
++AC_SUBST([default_gnattools_target])
++
++# Target-specific stuff (defaults)
++TOOLS_TARGET_PAIRS=
++AC_SUBST(TOOLS_TARGET_PAIRS)
++
++# Per-target case statement
++# ---/----------------------
++case "${target}" in
++  alpha*-dec-vx*) # Unlike all other Vxworks
++    ;;
++  m68k*-wrs-vx* \
++  | powerpc*-wrs-vxworks \
++  | sparc*-wrs-vx* \
++  | *86-wrs-vxworks \
++  | xscale*-wrs-vx* \
++  | xscale*-wrs-coff \
++  | mips*-wrs-vx*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"
++    ;;
++  sparc-sun-solaris*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
++    ;;
++  *86-*-solaris2*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
++    ;;
++  *86-*-linux* \
++  | aarch64*-*-linux* \
++  | arm*-*-linux* \
++  | powerpc*-*-linux* \
++  | *ia64-*-linux* \
++  | alpha*-*-linux* \
++  | sparc*-*-linux* \
++  | hppa*-*-linux* \
++  | mips*-*-linux* \
++  | m68k-*-linux \
++  | *x86_64-*-linux* \
++  | *86-*-kfreebsd*-gnu \
++  | *86-*-gnu \
++  | *x86_64-*-kfreebsd*-gnu )
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
++    ;;
++  s390*-*-linux*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
++    ;;
++  *86-*-freebsd*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
++    ;;
++  mips-sgi-irix*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-irix.adb"
++    ;;
++  hppa*-hp-hpux10*) # Unlike hpux11
++    ;;
++  hppa*-hp-hpux11*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"
++    ;;
++  *-ibm-aix*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb"
++    ;;
++  alpha*-dec-osf*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-tru64.adb"
++    ;;
++  alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \
++  | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \
++    symbols.adb<symbols-vms.adb \
++    symbols-processing.adb<symbols-processing-vms-alpha.adb"
++    ;;
++  ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \
++  | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-vms-ia64.adb \
++    symbols.adb<symbols-vms.adb \
++    symbols-processing.adb<symbols-processing-vms-ia64.adb"
++    ;;
++  *-*-cygwin32* | *-*-mingw32* | *-*-pe)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-mingw.adb"
++    ;;
++  powerpc-*-darwin*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"
++    ;;
++  *-*-lynxos)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb"
++    ;;
++esac
++
++# Output: create a Makefile.
++AC_CONFIG_FILES([Makefile])
++
++AC_OUTPUT
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -977,6 +977,7 @@ configure-target:  \
+     maybe-configure-target-rda \
+     maybe-configure-target-libada \
+     maybe-configure-target-libgnatvsn \
++    maybe-configure-target-libgnatprj \
+     maybe-configure-target-libgomp \
+     maybe-configure-target-libitm \
+     maybe-configure-target-libatomic
+@@ -1146,6 +1147,7 @@ all-target: maybe-all-target-boehm-gc
+ all-target: maybe-all-target-rda
+ all-target: maybe-all-target-libada
+ all-target: maybe-all-target-libgnatvsn
++all-target: maybe-all-target-libgnatprj
+ @if target-libgomp-no-bootstrap
+ all-target: maybe-all-target-libgomp
+ @endif target-libgomp-no-bootstrap
+@@ -1242,6 +1244,7 @@ info-target: maybe-info-target-boehm-gc
+ info-target: maybe-info-target-rda
+ info-target: maybe-info-target-libada
+ info-target: maybe-info-target-libgnatvsn
++info-target: maybe-info-target-libgnatprj
+ info-target: maybe-info-target-libgomp
+ info-target: maybe-info-target-libitm
+ info-target: maybe-info-target-libatomic
+@@ -1331,6 +1334,7 @@ dvi-target: maybe-dvi-target-boehm-gc
+ dvi-target: maybe-dvi-target-rda
+ dvi-target: maybe-dvi-target-libada
+ dvi-target: maybe-dvi-target-libgnatvsn
++dvi-target: maybe-dvi-target-libgnatprj
+ dvi-target: maybe-dvi-target-libgomp
+ dvi-target: maybe-dvi-target-libitm
+ dvi-target: maybe-dvi-target-libatomic
+@@ -1420,6 +1424,7 @@ pdf-target: maybe-pdf-target-boehm-gc
+ pdf-target: maybe-pdf-target-rda
+ pdf-target: maybe-pdf-target-libada
+ pdf-target: maybe-pdf-target-libgnatvsn
++pdf-target: maybe-pdf-target-libgnatprj
+ pdf-target: maybe-pdf-target-libgomp
+ pdf-target: maybe-pdf-target-libitm
+ pdf-target: maybe-pdf-target-libatomic
+@@ -1509,6 +1514,7 @@ html-target: maybe-html-target-boehm-gc
+ html-target: maybe-html-target-rda
+ html-target: maybe-html-target-libada
+ html-target: maybe-html-target-libgnatvsn
++html-target: maybe-html-target-libgnatprj
+ html-target: maybe-html-target-libgomp
+ html-target: maybe-html-target-libitm
+ html-target: maybe-html-target-libatomic
+@@ -1598,6 +1604,7 @@ TAGS-target: maybe-TAGS-target-boehm-gc
+ TAGS-target: maybe-TAGS-target-rda
+ TAGS-target: maybe-TAGS-target-libada
+ TAGS-target: maybe-TAGS-target-libgnatvsn
++TAGS-target: maybe-TAGS-target-libgnatprj
+ TAGS-target: maybe-TAGS-target-libgomp
+ TAGS-target: maybe-TAGS-target-libitm
+ TAGS-target: maybe-TAGS-target-libatomic
+@@ -1687,6 +1694,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-rda
+ install-info-target: maybe-install-info-target-libada
+ install-info-target: maybe-install-info-target-libgnatvsn
++install-info-target: maybe-install-info-target-libgnatprj
+ install-info-target: maybe-install-info-target-libgomp
+ install-info-target: maybe-install-info-target-libitm
+ install-info-target: maybe-install-info-target-libatomic
+@@ -1776,6 +1784,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-rda
+ install-pdf-target: maybe-install-pdf-target-libada
+ install-pdf-target: maybe-install-pdf-target-libgnatvsn
++install-pdf-target: maybe-install-pdf-target-libgnatprj
+ install-pdf-target: maybe-install-pdf-target-libgomp
+ install-pdf-target: maybe-install-pdf-target-libitm
+ install-pdf-target: maybe-install-pdf-target-libatomic
+@@ -1865,6 +1874,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-rda
+ install-html-target: maybe-install-html-target-libada
+ install-html-target: maybe-install-html-target-libgnatvsn
++install-html-target: maybe-install-html-target-libgnatprj
+ install-html-target: maybe-install-html-target-libgomp
+ install-html-target: maybe-install-html-target-libitm
+ install-html-target: maybe-install-html-target-libatomic
+@@ -1954,6 +1964,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-rda
+ installcheck-target: maybe-installcheck-target-libada
+ installcheck-target: maybe-installcheck-target-libgnatvsn
++installcheck-target: maybe-installcheck-target-libgnatprj
+ installcheck-target: maybe-installcheck-target-libgomp
+ installcheck-target: maybe-installcheck-target-libitm
+ installcheck-target: maybe-installcheck-target-libatomic
+@@ -2043,6 +2054,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-rda
+ mostlyclean-target: maybe-mostlyclean-target-libada
+ mostlyclean-target: maybe-mostlyclean-target-libgnatvsn
++mostlyclean-target: maybe-mostlyclean-target-libgnatprj
+ mostlyclean-target: maybe-mostlyclean-target-libgomp
+ mostlyclean-target: maybe-mostlyclean-target-libitm
+ mostlyclean-target: maybe-mostlyclean-target-libatomic
+@@ -2132,6 +2144,7 @@ clean-target: maybe-clean-target-boehm-g
+ clean-target: maybe-clean-target-rda
+ clean-target: maybe-clean-target-libada
+ clean-target: maybe-clean-target-libgnatvsn
++clean-target: maybe-clean-target-libgnatprj
+ clean-target: maybe-clean-target-libgomp
+ clean-target: maybe-clean-target-libitm
+ clean-target: maybe-clean-target-libatomic
+@@ -2221,6 +2234,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-rda
+ distclean-target: maybe-distclean-target-libada
+ distclean-target: maybe-distclean-target-libgnatvsn
++distclean-target: maybe-distclean-target-libgnatprj
+ distclean-target: maybe-distclean-target-libgomp
+ distclean-target: maybe-distclean-target-libitm
+ distclean-target: maybe-distclean-target-libatomic
+@@ -2310,6 +2324,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-rda
+ maintainer-clean-target: maybe-maintainer-clean-target-libada
+ maintainer-clean-target: maybe-maintainer-clean-target-libgnatvsn
++maintainer-clean-target: maybe-maintainer-clean-target-libgnatprj
+ maintainer-clean-target: maybe-maintainer-clean-target-libgomp
+ maintainer-clean-target: maybe-maintainer-clean-target-libitm
+ maintainer-clean-target: maybe-maintainer-clean-target-libatomic
+@@ -2455,6 +2470,7 @@ check-target:  \
+     maybe-check-target-rda \
+     maybe-check-target-libada \
+     maybe-check-target-libgnatvsn \
++    maybe-check-target-libgnatprj \
+     maybe-check-target-libgomp \
+     maybe-check-target-libitm \
+     maybe-check-target-libatomic
+@@ -2640,6 +2656,7 @@ install-target:  \
+     maybe-install-target-rda \
+     maybe-install-target-libada \
+     maybe-install-target-libgnatvsn \
++    maybe-install-target-libgnatprj \
+     maybe-install-target-libgomp \
+     maybe-install-target-libitm \
+     maybe-install-target-libatomic
+@@ -2749,6 +2766,7 @@ install-strip-target:  \
+     maybe-install-strip-target-rda \
+     maybe-install-strip-target-libada \
+     maybe-install-strip-target-libgnatvsn \
++    maybe-install-strip-target-libgnatprj \
+     maybe-install-strip-target-libgomp \
+     maybe-install-strip-target-libitm \
+     maybe-install-strip-target-libatomic
+@@ -46415,6 +46433,362 @@ maintainer-clean-target-libgnatvsn:
+ 
+ 
+ 
++.PHONY: configure-target-libgnatprj maybe-configure-target-libgnatprj
++maybe-configure-target-libgnatprj:
++@if gcc-bootstrap
++configure-target-libgnatprj: stage_current
++@endif gcc-bootstrap
++@if target-libgnatprj
++maybe-configure-target-libgnatprj: configure-target-libgnatprj
++configure-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libgnatprj..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatprj/multilib.tmp 2> /dev/null ; \
++	if test -r $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libgnatprj/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libgnatprj/Makefile; \
++	    mv $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libgnatprj/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libgnatprj; \
++	cd "$(TARGET_SUBDIR)/libgnatprj" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libgnatprj/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libgnatprj; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libgnatprj
++
++
++
++
++
++.PHONY: all-target-libgnatprj maybe-all-target-libgnatprj
++maybe-all-target-libgnatprj:
++@if gcc-bootstrap
++all-target-libgnatprj: stage_current
++@endif gcc-bootstrap
++@if target-libgnatprj
++TARGET-target-libgnatprj=all
++maybe-all-target-libgnatprj: all-target-libgnatprj
++all-target-libgnatprj: configure-target-libgnatprj
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libgnatprj))
++@endif target-libgnatprj
++
++
++
++
++
++.PHONY: check-target-libgnatprj maybe-check-target-libgnatprj
++maybe-check-target-libgnatprj:
++@if target-libgnatprj
++maybe-check-target-libgnatprj: check-target-libgnatprj
++
++# Dummy target for uncheckable module.
++check-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: install-target-libgnatprj maybe-install-target-libgnatprj
++maybe-install-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-target-libgnatprj: install-target-libgnatprj
++
++install-target-libgnatprj: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++
++@endif target-libgnatprj
++
++.PHONY: install-strip-target-libgnatprj maybe-install-strip-target-libgnatprj
++maybe-install-strip-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-strip-target-libgnatprj: install-strip-target-libgnatprj
++
++install-strip-target-libgnatprj: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++
++@endif target-libgnatprj
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libgnatprj info-target-libgnatprj
++maybe-info-target-libgnatprj:
++@if target-libgnatprj
++maybe-info-target-libgnatprj: info-target-libgnatprj
++
++# libgnatprj doesn't support info.
++info-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-dvi-target-libgnatprj dvi-target-libgnatprj
++maybe-dvi-target-libgnatprj:
++@if target-libgnatprj
++maybe-dvi-target-libgnatprj: dvi-target-libgnatprj
++
++# libgnatprj doesn't support dvi.
++dvi-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-pdf-target-libgnatprj pdf-target-libgnatprj
++maybe-pdf-target-libgnatprj:
++@if target-libgnatprj
++maybe-pdf-target-libgnatprj: pdf-target-libgnatprj
++
++pdf-target-libgnatprj: \
++    configure-target-libgnatprj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-html-target-libgnatprj html-target-libgnatprj
++maybe-html-target-libgnatprj:
++@if target-libgnatprj
++maybe-html-target-libgnatprj: html-target-libgnatprj
++
++# libgnatprj doesn't support html.
++html-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-TAGS-target-libgnatprj TAGS-target-libgnatprj
++maybe-TAGS-target-libgnatprj:
++@if target-libgnatprj
++maybe-TAGS-target-libgnatprj: TAGS-target-libgnatprj
++
++# libgnatprj doesn't support TAGS.
++TAGS-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-install-info-target-libgnatprj install-info-target-libgnatprj
++maybe-install-info-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-info-target-libgnatprj: install-info-target-libgnatprj
++
++# libgnatprj doesn't support install-info.
++install-info-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-install-pdf-target-libgnatprj install-pdf-target-libgnatprj
++maybe-install-pdf-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-pdf-target-libgnatprj: install-pdf-target-libgnatprj
++
++install-pdf-target-libgnatprj: \
++    configure-target-libgnatprj \
++    pdf-target-libgnatprj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-install-html-target-libgnatprj install-html-target-libgnatprj
++maybe-install-html-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-html-target-libgnatprj: install-html-target-libgnatprj
++
++install-html-target-libgnatprj: \
++    configure-target-libgnatprj \
++    html-target-libgnatprj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-installcheck-target-libgnatprj installcheck-target-libgnatprj
++maybe-installcheck-target-libgnatprj:
++@if target-libgnatprj
++maybe-installcheck-target-libgnatprj: installcheck-target-libgnatprj
++
++# libgnatprj doesn't support installcheck.
++installcheck-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-mostlyclean-target-libgnatprj mostlyclean-target-libgnatprj
++maybe-mostlyclean-target-libgnatprj:
++@if target-libgnatprj
++maybe-mostlyclean-target-libgnatprj: mostlyclean-target-libgnatprj
++
++mostlyclean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-clean-target-libgnatprj clean-target-libgnatprj
++maybe-clean-target-libgnatprj:
++@if target-libgnatprj
++maybe-clean-target-libgnatprj: clean-target-libgnatprj
++
++clean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-distclean-target-libgnatprj distclean-target-libgnatprj
++maybe-distclean-target-libgnatprj:
++@if target-libgnatprj
++maybe-distclean-target-libgnatprj: distclean-target-libgnatprj
++
++distclean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-maintainer-clean-target-libgnatprj maintainer-clean-target-libgnatprj
++maybe-maintainer-clean-target-libgnatprj:
++@if target-libgnatprj
++maybe-maintainer-clean-target-libgnatprj: maintainer-clean-target-libgnatprj
++
++maintainer-clean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++
++
++
++
+ .PHONY: configure-target-libgomp maybe-configure-target-libgomp
+ maybe-configure-target-libgomp:
+ @if gcc-bootstrap
+@@ -50620,6 +50994,7 @@ configure-target-boehm-gc: stage_last
+ configure-target-rda: stage_last
+ configure-target-libada: stage_last
+ configure-target-libgnatvsn: stage_last
++configure-target-libgnatprj: stage_last
+ configure-stage1-target-libgomp: maybe-all-stage1-gcc
+ configure-stage2-target-libgomp: maybe-all-stage2-gcc
+ configure-stage3-target-libgomp: maybe-all-stage3-gcc
+@@ -50656,6 +51031,7 @@ configure-target-boehm-gc: maybe-all-gcc
+ configure-target-rda: maybe-all-gcc
+ configure-target-libada: maybe-all-gcc
+ configure-target-libgnatvsn: maybe-all-gcc
++configure-target-libgnatprj: maybe-all-gcc
+ configure-target-libgomp: maybe-all-gcc
+ configure-target-libitm: maybe-all-gcc
+ configure-target-libatomic: maybe-all-gcc
+@@ -51030,8 +51406,12 @@ all-stagefeedback-fixincludes: maybe-all
+ all-target-libada: maybe-all-gcc
+ all-gnattools: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libgnatvsn
++all-gnattools: maybe-all-target-libgnatprj
+ all-target-libgnatvsn: maybe-all-target-libada
++all-target-libgnatprj: maybe-all-target-libgnatvsn
++all-target-libgnatprj: maybe-all-target-libiberty
+ all-gnattools: maybe-all-target-libstdc++-v3
++all-target-libgnatvsn: maybe-all-target-libstdc++-v3
+ all-lto-plugin: maybe-all-libiberty
+ 
+ all-stage1-lto-plugin: maybe-all-stage1-libiberty
+@@ -51628,6 +52008,7 @@ configure-target-boehm-gc: maybe-all-tar
+ configure-target-rda: maybe-all-target-libgcc
+ configure-target-libada: maybe-all-target-libgcc
+ configure-target-libgnatvsn: maybe-all-target-libgcc
++configure-target-libgnatprj: maybe-all-target-libgcc
+ configure-target-libgomp: maybe-all-target-libgcc
+ configure-target-libitm: maybe-all-target-libgcc
+ configure-target-libatomic: maybe-all-target-libgcc
+@@ -51684,6 +52065,8 @@ configure-target-libada: maybe-all-targe
+ 
+ configure-target-libgnatvsn: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libgnatprj: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libgomp: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-libitm: maybe-all-target-newlib maybe-all-target-libgloss
+Index: b/src/libgnatprj/config.in
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/config.in
+@@ -0,0 +1,565 @@
++/* config.in.  Generated from configure.ac by autoheader.  */
++
++/* Define if building universal (internal helper macro) */
++#undef AC_APPLE_UNIVERSAL_BUILD
++
++/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
++   This function is required for alloca.c support on those systems. */
++#undef CRAY_STACKSEG_END
++
++/* Define to 1 if you have the <alloca.h> header file. */
++#undef HAVE_ALLOCA_H
++
++/* Define to 1 if you have the `asprintf' function. */
++#undef HAVE_ASPRINTF
++
++/* Define to 1 if you have the `atexit' function. */
++#undef HAVE_ATEXIT
++
++/* Define to 1 if you have the `basename' function. */
++#undef HAVE_BASENAME
++
++/* Define to 1 if you have the `bcmp' function. */
++#undef HAVE_BCMP
++
++/* Define to 1 if you have the `bcopy' function. */
++#undef HAVE_BCOPY
++
++/* Define to 1 if you have the `bsearch' function. */
++#undef HAVE_BSEARCH
++
++/* Define to 1 if you have the `bzero' function. */
++#undef HAVE_BZERO
++
++/* Define to 1 if you have the `calloc' function. */
++#undef HAVE_CALLOC
++
++/* Define to 1 if you have the `canonicalize_file_name' function. */
++#undef HAVE_CANONICALIZE_FILE_NAME
++
++/* Define to 1 if you have the `clock' function. */
++#undef HAVE_CLOCK
++
++/* Define to 1 if you have the declaration of `asprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_ASPRINTF
++
++/* Define to 1 if you have the declaration of `basename(char *)', and to 0 if
++   you don't. */
++#undef HAVE_DECL_BASENAME
++
++/* Define to 1 if you have the declaration of `calloc', and to 0 if you don't.
++   */
++#undef HAVE_DECL_CALLOC
++
++/* Define to 1 if you have the declaration of `ffs', and to 0 if you don't. */
++#undef HAVE_DECL_FFS
++
++/* Define to 1 if you have the declaration of `getenv', and to 0 if you don't.
++   */
++#undef HAVE_DECL_GETENV
++
++/* Define to 1 if you have the declaration of `getopt', and to 0 if you don't.
++   */
++#undef HAVE_DECL_GETOPT
++
++/* Define to 1 if you have the declaration of `malloc', and to 0 if you don't.
++   */
++#undef HAVE_DECL_MALLOC
++
++/* Define to 1 if you have the declaration of `realloc', and to 0 if you
++   don't. */
++#undef HAVE_DECL_REALLOC
++
++/* Define to 1 if you have the declaration of `sbrk', and to 0 if you don't.
++   */
++#undef HAVE_DECL_SBRK
++
++/* Define to 1 if you have the declaration of `snprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_SNPRINTF
++
++/* Define to 1 if you have the declaration of `strtol', and to 0 if you don't.
++   */
++#undef HAVE_DECL_STRTOL
++
++/* Define to 1 if you have the declaration of `strtoll', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRTOLL
++
++/* Define to 1 if you have the declaration of `strtoul', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRTOUL
++
++/* Define to 1 if you have the declaration of `strtoull', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRTOULL
++
++/* Define to 1 if you have the declaration of `strverscmp', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRVERSCMP
++
++/* Define to 1 if you have the declaration of `vasprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_VASPRINTF
++
++/* Define to 1 if you have the declaration of `vsnprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_VSNPRINTF
++
++/* Define to 1 if you have the `dup3' function. */
++#undef HAVE_DUP3
++
++/* Define to 1 if you have the <fcntl.h> header file. */
++#undef HAVE_FCNTL_H
++
++/* Define to 1 if you have the `ffs' function. */
++#undef HAVE_FFS
++
++/* Define to 1 if you have the `fork' function. */
++#undef HAVE_FORK
++
++/* Define to 1 if you have the `getcwd' function. */
++#undef HAVE_GETCWD
++
++/* Define to 1 if you have the `getpagesize' function. */
++#undef HAVE_GETPAGESIZE
++
++/* Define to 1 if you have the `getrlimit' function. */
++#undef HAVE_GETRLIMIT
++
++/* Define to 1 if you have the `getrusage' function. */
++#undef HAVE_GETRUSAGE
++
++/* Define to 1 if you have the `getsysinfo' function. */
++#undef HAVE_GETSYSINFO
++
++/* Define to 1 if you have the `gettimeofday' function. */
++#undef HAVE_GETTIMEOFDAY
++
++/* Define to 1 if you have the `index' function. */
++#undef HAVE_INDEX
++
++/* Define to 1 if you have the `insque' function. */
++#undef HAVE_INSQUE
++
++/* Define to 1 if the system has the type `intptr_t'. */
++#undef HAVE_INTPTR_T
++
++/* Define to 1 if you have the <inttypes.h> header file. */
++#undef HAVE_INTTYPES_H
++
++/* Define to 1 if you have the <limits.h> header file. */
++#undef HAVE_LIMITS_H
++
++/* Define if you have the `long long' type. */
++#undef HAVE_LONG_LONG
++
++/* Define to 1 if you have the <machine/hal_sysinfo.h> header file. */
++#undef HAVE_MACHINE_HAL_SYSINFO_H
++
++/* Define to 1 if you have the <malloc.h> header file. */
++#undef HAVE_MALLOC_H
++
++/* Define to 1 if you have the `memchr' function. */
++#undef HAVE_MEMCHR
++
++/* Define to 1 if you have the `memcmp' function. */
++#undef HAVE_MEMCMP
++
++/* Define to 1 if you have the `memcpy' function. */
++#undef HAVE_MEMCPY
++
++/* Define to 1 if you have the `memmem' function. */
++#undef HAVE_MEMMEM
++
++/* Define to 1 if you have the `memmove' function. */
++#undef HAVE_MEMMOVE
++
++/* Define to 1 if you have the <memory.h> header file. */
++#undef HAVE_MEMORY_H
++
++/* Define to 1 if you have the `memset' function. */
++#undef HAVE_MEMSET
++
++/* Define to 1 if you have the `mkstemps' function. */
++#undef HAVE_MKSTEMPS
++
++/* Define to 1 if you have a working `mmap' system call. */
++#undef HAVE_MMAP
++
++/* Define to 1 if you have the `on_exit' function. */
++#undef HAVE_ON_EXIT
++
++/* Define to 1 if you have the <process.h> header file. */
++#undef HAVE_PROCESS_H
++
++/* Define to 1 if you have the `psignal' function. */
++#undef HAVE_PSIGNAL
++
++/* Define to 1 if you have the `pstat_getdynamic' function. */
++#undef HAVE_PSTAT_GETDYNAMIC
++
++/* Define to 1 if you have the `pstat_getstatic' function. */
++#undef HAVE_PSTAT_GETSTATIC
++
++/* Define to 1 if you have the `putenv' function. */
++#undef HAVE_PUTENV
++
++/* Define to 1 if you have the `random' function. */
++#undef HAVE_RANDOM
++
++/* Define to 1 if you have the `realpath' function. */
++#undef HAVE_REALPATH
++
++/* Define to 1 if you have the `rename' function. */
++#undef HAVE_RENAME
++
++/* Define to 1 if you have the `rindex' function. */
++#undef HAVE_RINDEX
++
++/* Define to 1 if you have the `sbrk' function. */
++#undef HAVE_SBRK
++
++/* Define to 1 if you have the `setenv' function. */
++#undef HAVE_SETENV
++
++/* Define to 1 if you have the `setproctitle' function. */
++#undef HAVE_SETPROCTITLE
++
++/* Define to 1 if you have the `setrlimit' function. */
++#undef HAVE_SETRLIMIT
++
++/* Define to 1 if you have the `sigsetmask' function. */
++#undef HAVE_SIGSETMASK
++
++/* Define to 1 if you have the `snprintf' function. */
++#undef HAVE_SNPRINTF
++
++/* Define to 1 if you have the `spawnve' function. */
++#undef HAVE_SPAWNVE
++
++/* Define to 1 if you have the `spawnvpe' function. */
++#undef HAVE_SPAWNVPE
++
++/* Define to 1 if you have the <stdint.h> header file. */
++#undef HAVE_STDINT_H
++
++/* Define to 1 if you have the <stdio_ext.h> header file. */
++#undef HAVE_STDIO_EXT_H
++
++/* Define to 1 if you have the <stdlib.h> header file. */
++#undef HAVE_STDLIB_H
++
++/* Define to 1 if you have the `stpcpy' function. */
++#undef HAVE_STPCPY
++
++/* Define to 1 if you have the `stpncpy' function. */
++#undef HAVE_STPNCPY
++
++/* Define to 1 if you have the `strcasecmp' function. */
++#undef HAVE_STRCASECMP
++
++/* Define to 1 if you have the `strchr' function. */
++#undef HAVE_STRCHR
++
++/* Define to 1 if you have the `strdup' function. */
++#undef HAVE_STRDUP
++
++/* Define to 1 if you have the `strerror' function. */
++#undef HAVE_STRERROR
++
++/* Define to 1 if you have the <strings.h> header file. */
++#undef HAVE_STRINGS_H
++
++/* Define to 1 if you have the <string.h> header file. */
++#undef HAVE_STRING_H
++
++/* Define to 1 if you have the `strncasecmp' function. */
++#undef HAVE_STRNCASECMP
++
++/* Define to 1 if you have the `strndup' function. */
++#undef HAVE_STRNDUP
++
++/* Define to 1 if you have the `strnlen' function. */
++#undef HAVE_STRNLEN
++
++/* Define to 1 if you have the `strrchr' function. */
++#undef HAVE_STRRCHR
++
++/* Define to 1 if you have the `strsignal' function. */
++#undef HAVE_STRSIGNAL
++
++/* Define to 1 if you have the `strstr' function. */
++#undef HAVE_STRSTR
++
++/* Define to 1 if you have the `strtod' function. */
++#undef HAVE_STRTOD
++
++/* Define to 1 if you have the `strtol' function. */
++#undef HAVE_STRTOL
++
++/* Define to 1 if you have the `strtoll' function. */
++#undef HAVE_STRTOLL
++
++/* Define to 1 if you have the `strtoul' function. */
++#undef HAVE_STRTOUL
++
++/* Define to 1 if you have the `strtoull' function. */
++#undef HAVE_STRTOULL
++
++/* Define to 1 if you have the `strverscmp' function. */
++#undef HAVE_STRVERSCMP
++
++/* Define to 1 if you have the `sysconf' function. */
++#undef HAVE_SYSCONF
++
++/* Define to 1 if you have the `sysctl' function. */
++#undef HAVE_SYSCTL
++
++/* Define to 1 if you have the `sysmp' function. */
++#undef HAVE_SYSMP
++
++/* Define if you have the sys_errlist variable. */
++#undef HAVE_SYS_ERRLIST
++
++/* Define to 1 if you have the <sys/file.h> header file. */
++#undef HAVE_SYS_FILE_H
++
++/* Define to 1 if you have the <sys/mman.h> header file. */
++#undef HAVE_SYS_MMAN_H
++
++/* Define if you have the sys_nerr variable. */
++#undef HAVE_SYS_NERR
++
++/* Define to 1 if you have the <sys/param.h> header file. */
++#undef HAVE_SYS_PARAM_H
++
++/* Define to 1 if you have the <sys/prctl.h> header file. */
++#undef HAVE_SYS_PRCTL_H
++
++/* Define to 1 if you have the <sys/pstat.h> header file. */
++#undef HAVE_SYS_PSTAT_H
++
++/* Define to 1 if you have the <sys/resource.h> header file. */
++#undef HAVE_SYS_RESOURCE_H
++
++/* Define if you have the sys_siglist variable. */
++#undef HAVE_SYS_SIGLIST
++
++/* Define to 1 if you have the <sys/stat.h> header file. */
++#undef HAVE_SYS_STAT_H
++
++/* Define to 1 if you have the <sys/sysctl.h> header file. */
++#undef HAVE_SYS_SYSCTL_H
++
++/* Define to 1 if you have the <sys/sysinfo.h> header file. */
++#undef HAVE_SYS_SYSINFO_H
++
++/* Define to 1 if you have the <sys/sysmp.h> header file. */
++#undef HAVE_SYS_SYSMP_H
++
++/* Define to 1 if you have the <sys/systemcfg.h> header file. */
++#undef HAVE_SYS_SYSTEMCFG_H
++
++/* Define to 1 if you have the <sys/table.h> header file. */
++#undef HAVE_SYS_TABLE_H
++
++/* Define to 1 if you have the <sys/time.h> header file. */
++#undef HAVE_SYS_TIME_H
++
++/* Define to 1 if you have the <sys/types.h> header file. */
++#undef HAVE_SYS_TYPES_H
++
++/* Define to 1 if you have <sys/wait.h> that is POSIX.1 compatible. */
++#undef HAVE_SYS_WAIT_H
++
++/* Define to 1 if you have the `table' function. */
++#undef HAVE_TABLE
++
++/* Define to 1 if you have the `times' function. */
++#undef HAVE_TIMES
++
++/* Define to 1 if you have the <time.h> header file. */
++#undef HAVE_TIME_H
++
++/* Define to 1 if you have the `tmpnam' function. */
++#undef HAVE_TMPNAM
++
++/* Define if you have the \`uintptr_t' type. */
++#undef HAVE_UINTPTR_T
++
++/* Define to 1 if you have the <unistd.h> header file. */
++#undef HAVE_UNISTD_H
++
++/* Define to 1 if you have the `vasprintf' function. */
++#undef HAVE_VASPRINTF
++
++/* Define to 1 if you have the `vfork' function. */
++#undef HAVE_VFORK
++
++/* Define to 1 if you have the <vfork.h> header file. */
++#undef HAVE_VFORK_H
++
++/* Define to 1 if you have the `vfprintf' function. */
++#undef HAVE_VFPRINTF
++
++/* Define to 1 if you have the `vprintf' function. */
++#undef HAVE_VPRINTF
++
++/* Define to 1 if you have the `vsprintf' function. */
++#undef HAVE_VSPRINTF
++
++/* Define to 1 if you have the `wait3' function. */
++#undef HAVE_WAIT3
++
++/* Define to 1 if you have the `wait4' function. */
++#undef HAVE_WAIT4
++
++/* Define to 1 if you have the `waitpid' function. */
++#undef HAVE_WAITPID
++
++/* Define to 1 if `fork' works. */
++#undef HAVE_WORKING_FORK
++
++/* Define to 1 if `vfork' works. */
++#undef HAVE_WORKING_VFORK
++
++/* Define to 1 if you have the `_doprnt' function. */
++#undef HAVE__DOPRNT
++
++/* Define if you have the _system_configuration variable. */
++#undef HAVE__SYSTEM_CONFIGURATION
++
++/* Define to 1 if you have the `__fsetlocking' function. */
++#undef HAVE___FSETLOCKING
++
++/* Define if canonicalize_file_name is not declared in system header files. */
++#undef NEED_DECLARATION_CANONICALIZE_FILE_NAME
++
++/* Define if errno must be declared even when <errno.h> is included. */
++#undef NEED_DECLARATION_ERRNO
++
++/* Define to 1 if your C compiler doesn't accept -c and -o together. */
++#undef NO_MINUS_C_MINUS_O
++
++/* Define to the address where bug reports for this package should be sent. */
++#undef PACKAGE_BUGREPORT
++
++/* Define to the full name of this package. */
++#undef PACKAGE_NAME
++
++/* Define to the full name and version of this package. */
++#undef PACKAGE_STRING
++
++/* Define to the one symbol short name of this package. */
++#undef PACKAGE_TARNAME
++
++/* Define to the home page for this package. */
++#undef PACKAGE_URL
++
++/* Define to the version of this package. */
++#undef PACKAGE_VERSION
++
++/* The size of `int', as computed by sizeof. */
++#undef SIZEOF_INT
++
++/* The size of `long', as computed by sizeof. */
++#undef SIZEOF_LONG
++
++/* The size of `long long', as computed by sizeof. */
++#undef SIZEOF_LONG_LONG
++
++/* The size of `size_t', as computed by sizeof. */
++#undef SIZEOF_SIZE_T
++
++/* Define if you know the direction of stack growth for your system; otherwise
++   it will be automatically deduced at run-time. STACK_DIRECTION > 0 => grows
++   toward higher addresses STACK_DIRECTION < 0 => grows toward lower addresses
++   STACK_DIRECTION = 0 => direction of growth unknown */
++#undef STACK_DIRECTION
++
++/* Define to 1 if you have the ANSI C header files. */
++#undef STDC_HEADERS
++
++/* Define to 1 if you can safely include both <sys/time.h> and <time.h>. */
++#undef TIME_WITH_SYS_TIME
++
++/* Define to an unsigned 64-bit type available in the compiler. */
++#undef UNSIGNED_64BIT_TYPE
++
++/* Enable extensions on AIX 3, Interix.  */
++#ifndef _ALL_SOURCE
++# undef _ALL_SOURCE
++#endif
++/* Enable GNU extensions on systems that have them.  */
++#ifndef _GNU_SOURCE
++# undef _GNU_SOURCE
++#endif
++/* Enable threading extensions on Solaris.  */
++#ifndef _POSIX_PTHREAD_SEMANTICS
++# undef _POSIX_PTHREAD_SEMANTICS
++#endif
++/* Enable extensions on HP NonStop.  */
++#ifndef _TANDEM_SOURCE
++# undef _TANDEM_SOURCE
++#endif
++/* Enable general extensions on Solaris.  */
++#ifndef __EXTENSIONS__
++# undef __EXTENSIONS__
++#endif
++
++
++/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
++   significant byte first (like Motorola and SPARC, unlike Intel). */
++#if defined AC_APPLE_UNIVERSAL_BUILD
++# if defined __BIG_ENDIAN__
++#  define WORDS_BIGENDIAN 1
++# endif
++#else
++# ifndef WORDS_BIGENDIAN
++#  undef WORDS_BIGENDIAN
++# endif
++#endif
++
++/* Number of bits in a file offset, on hosts where this is settable. */
++#undef _FILE_OFFSET_BITS
++
++/* Define for large files, on AIX-style hosts. */
++#undef _LARGE_FILES
++
++/* Define to 1 if on MINIX. */
++#undef _MINIX
++
++/* Define to 2 if the system does not provide POSIX.1 features except with
++   this defined. */
++#undef _POSIX_1_SOURCE
++
++/* Define to 1 if you need to in order for `stat' and other things to work. */
++#undef _POSIX_SOURCE
++
++/* Define to empty if `const' does not conform to ANSI C. */
++#undef const
++
++/* Define to `__inline__' or `__inline' if that's what the C compiler
++   calls it, or to nothing if 'inline' is not supported under any name.  */
++#ifndef __cplusplus
++#undef inline
++#endif
++
++/* Define to the type of a signed integer type wide enough to hold a pointer,
++   if such a type exists, and if the system does not define it. */
++#undef intptr_t
++
++/* Define to `int' if <sys/types.h> does not define. */
++#undef pid_t
++
++/* Define to `int' if <sys/types.h> does not define. */
++#undef ssize_t
++
++/* Define to the type of an unsigned integer type wide enough to hold a
++   pointer, if such a type exists, and if the system does not define it. */
++#undef uintptr_t
++
++/* Define as `fork' if `vfork' does not work. */
++#undef vfork
+Index: b/src/gcc/prefix.c
+===================================================================
+--- a/src/gcc/prefix.c
++++ b/src/gcc/prefix.c
+@@ -70,7 +70,10 @@ License along with GCC; see the file COP
+ #include <windows.h>
+ #endif
+ #include "prefix.h"
++
++#ifndef USED_FOR_TARGET
+ #include "common/common-target.h"
++#endif
+ 
+ static const char *std_prefix = PREFIX;
+ 
+@@ -284,7 +287,11 @@ update_path (const char *path, const cha
+ 	  && (p != result && IS_DIR_SEPARATOR (p[-1])))
+ 	{
+ 	  *p = 0;
++#ifndef USED_FOR_TARGET
+ 	  if (!targetm_common.always_strip_dotdot
++#else
++	  if (true
++#endif
+ 	      && access (result, X_OK) == 0)
+ 	    {
+ 	      *p = '.';
--- gcc-6-6.3.0.orig/debian/patches/ada-libgnatvsn.diff
+++ gcc-6-6.3.0/debian/patches/ada-libgnatvsn.diff
@@ -0,0 +1,836 @@
+# DP: - Introduce a new shared library named libgnatvsn, containing
+# DP:   common components of GNAT under the GNAT-Modified GPL, for
+# DP:   use in GNAT tools, ASIS, GLADE and GPS.   Link the gnat tools
+# DP:   against this new library.
+
+# This patch seems large, but the hunks in Makefile.in are actually
+# generated from Makefile.def using autogen.
+
+# !!! Must be applied after ada-link-lib.dpatch
+
+Index: b/src/libgnatvsn/configure
+===================================================================
+--- /dev/null
++++ b/src/libgnatvsn/configure
+@@ -0,0 +1,47 @@
++#!/bin/sh
++
++# Minimal configure script for libgnatvsn.  We're only interested in
++# a few parameters.
++
++for arg in $*; do
++    case ${arg} in
++	--build=*)
++	    build=`expr ${arg} : '--build=\(.\+\)'`;;
++	--host=*)
++	    host=`expr ${arg} : '--host=\(.\+\)'`;;
++	--target=*)
++	    target=`expr ${arg} : '--target=\(.\+\)'`;;
++	--prefix=*)
++	    prefix=`expr ${arg} : '--prefix=\(.\+\)'`;;
++	--srcdir=*)
++	    srcdir=`expr ${arg} : '--srcdir=\(.\+\)'`;;
++	--libdir=*)
++	    libdir=`expr ${arg} : '--libdir=\(.\+\)'`;;
++	--with-pkgversion=*)
++	    pkgversion=`expr ${arg} : '--with-pkgversion=\(.\+\)'`;;
++	--with-bugurl=*)
++	    bugurl=`expr ${arg} : '--with-bugurl=\(.\+\)'`;;
++	*)
++	    echo "Warning: ignoring option: ${arg}"
++    esac
++done
++
++echo "build: ${build}" | tee config.log
++echo "host: ${host}" | tee -a config.log
++echo "target: ${target}" | tee -a config.log
++echo "prefix: ${prefix}" | tee -a config.log
++echo "srcdir: ${srcdir}" | tee -a config.log
++echo "libdir: ${libdir}" | tee -a config.log
++echo "pkgversion: ${pkgversion}" | tee -a config.log
++echo "bugurl: ${bugurl}" | tee -a config.log
++
++echo "Creating Makefile..." | tee -a config.log
++sed -e "s,@build@,${build},g" \
++    -e "s,@host@,${host},g" \
++    -e "s,@target@,${target},g" \
++    -e "s,@prefix@,${prefix},g" \
++    -e "s,@srcdir@,${srcdir},g" \
++    -e "s,@libdir@,${libdir},g" \
++    -e "s,@PKGVERSION@,${pkgversion},g" \
++    -e "s,@REPORT_BUGS_TO@,${bugurl},g" \
++    < ${srcdir}/Makefile.in > Makefile
+Index: b/src/libgnatvsn/Makefile.in
+===================================================================
+--- /dev/null
++++ b/src/libgnatvsn/Makefile.in
+@@ -0,0 +1,153 @@
++# Makefile for libgnatvsn.
++#   Copyright (c) 2006 Ludovic Brenta <ludovic@ludovic-brenta.org>
++#
++# This file is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++# 
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++# 
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++# Default target; must be first.
++all: libgnatvsn
++
++.SUFFIXES:
++
++CPUS := $(shell getconf _NPROCESSORS_ONLN)
++LIB_VERSION := $(strip $(shell grep ' Library_Version :' \
++                 @srcdir@/../gcc/ada/gnatvsn.ads | \
++	         sed -e 's/.*"\(.*\)".*/\1/'))
++GCC:=$(CC)
++LIBGNAT_JUST_BUILT := -nostdinc -I../../gcc/ada/rts
++CFLAGS := -g -O2 -gnatn
++FULLVER := $(shell cat @srcdir@/../gcc/FULL-VER)
++DEVPHASE := $(shell cat @srcdir@/../gcc/DEV-PHASE)
++DATESTAMP := $(shell cat @srcdir@/../gcc/DATESTAMP)
++
++# For use in version.c - double quoted strings, with appropriate
++# surrounding punctuation and spaces, and with the datestamp and
++# development phase collapsed to the empty string in release mode
++# (i.e. if DEVPHASE_c is empty).  The space immediately after the
++# comma in the $(if ...) constructs is significant - do not remove it.
++FULLVER_s   := "\"$(FULLVER)\""
++DEVPHASE_s  := "\"$(if $(DEVPHASE), ($(DEVPHASE)))\""
++DATESTAMP_s := "\"$(if $(DEVPHASE), $(DATESTAMP))\""
++PKGVERSION_s:= "\"@PKGVERSION@\""
++BUGURL_s    := "\"@REPORT_BUGS_TO@\""
++
++.PHONY: libgnatvsn install
++libgnatvsn: libgnatvsn.so.$(LIB_VERSION) libgnatvsn.a
++
++VSN_SOURCES := alloc.ads aspects.adb atree.adb casing.adb csets.adb debug.adb einfo.adb \
++elists.adb fname.adb gnatvsn.adb hostparm.ads krunch.adb lib.adb namet.adb \
++nlists.adb opt.adb output.adb repinfo.adb scans.adb sinfo.adb sem_aux.adb \
++sinput.adb stand.adb stringt.adb table.adb tree_in.adb tree_io.adb types.adb \
++uintp.adb uname.adb urealp.adb widechar.adb
++
++VSN_SEPARATES := lib-list.adb lib-sort.adb
++
++VSN_GENERATED_SOURCES := snames.adb
++
++OBJECTS=$(patsubst %.ads,%.o,$(VSN_SOURCES:.adb=.o) $(VSN_GENERATED_SOURCES:.adb=.o)) version.o
++
++vpath %.c @srcdir@/../gcc
++
++libgnatvsn.so.$(LIB_VERSION): $(addprefix obj-shared/,$(OBJECTS))
++	: # Make libgnatvsn.so
++	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ $^ \
++	   -L../../gcc/ada/rts -lgnat-$(LIB_VERSION) $(LDFLAGS)
++	ln -s libgnatvsn.so.$(LIB_VERSION) libgnatvsn.so
++	chmod a=r obj-shared/*.ali
++# Make the .ali files, but not the .o files, visible to the gnat tools.
++	cp -lp obj-shared/*.ali .
++
++$(addprefix obj-shared/,$(OBJECTS)): | stamp-libgnatvsn-sources obj-shared
++
++obj-shared/%.o: %.adb
++	$(GCC) -c -fPIC $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-shared/%.o: %.ads
++	$(GCC) -c -fPIC $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-shared/version.o: version.c
++	$(GCC) -c -fPIC -g -O2 \
++	   -DBASEVER=$(FULLVER_s) \
++	   -DDATESTAMP=$(DATESTAMP_s) \
++	   -DDEVPHASE=$(DEVPHASE_s) \
++	   -DPKGVERSION=$(PKGVERSION_s) \
++	   -DBUGURL=$(BUGURL_s) \
++	   -DREVISION= \
++	   $(realpath $<) -o $@
++
++obj-shared:
++	-mkdir $@
++
++libgnatvsn.a: $(addprefix obj-static/,$(OBJECTS))
++	: # Make libgnatvsn.a
++	ar rc $@ $^
++	ranlib $@
++
++$(addprefix obj-static/,$(OBJECTS)): | stamp-libgnatvsn-sources obj-static
++
++obj-static/%.o: %.adb
++	$(GCC) -c $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-static/%.o: %.ads
++	$(GCC) -c $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-static/version.o: version.c
++	$(GCC) -c -g -O2 \
++	   -DBASEVER=$(FULLVER_s) \
++	   -DDATESTAMP=$(DATESTAMP_s) \
++	   -DDEVPHASE=$(DEVPHASE_s) \
++	   -DPKGVERSION=$(PKGVERSION_s) \
++	   -DBUGURL=$(BUGURL_s) \
++	   -DREVISION= \
++	   $< -o $@
++
++obj-static:
++	-mkdir $@
++
++$(VSN_SOURCES) $(VSN_SEPARATES) $(VSN_GENERATED_SOURCES): stamp-libgnatvsn-sources
++
++stamp-libgnatvsn-sources:
++	for file in $(VSN_SOURCES) $(VSN_SEPARATES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f @srcdir@/../gcc/ada/$$file -a ! -L $$file ] ; then ln -s @srcdir@/../gcc/ada/$$file .; fi; \
++	   if [ -f @srcdir@/../gcc/ada/$$ads -a ! -L $$ads ] ; then ln -s @srcdir@/../gcc/ada/$$ads .; fi; \
++	done
++	for file in $(VSN_GENERATED_SOURCES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f ../../gcc/ada/$$file -a ! -L $$file ] ; then ln -s ../../gcc/ada/$$file .; fi; \
++	   if [ -f ../../gcc/ada/$$ads -a ! -L $$ads ] ; then ln -s ../../gcc/ada/$$ads .; fi; \
++	done
++	touch $@
++
++libdir = @libdir@
++
++install: libgnatvsn
++	$(INSTALL_DATA) libgnatvsn.a $(DESTDIR)$(libdir)
++	$(INSTALL_DATA) libgnatvsn.so.$(LIB_VERSION) $(DESTDIR)$(libdir)
++	cd $(DESTDIR)$(libdir); ln -sf libgnatvsn.so.$(LIB_VERSION) libgnatvsn.so
++	mkdir -p $(DESTDIR)$(prefix)/share/ada/adainclude/gnatvsn
++	$(INSTALL_DATA) \
++	   $(addprefix @srcdir@/../gcc/ada/,$(VSN_SOURCES) $(VSN_SEPARATES)) \
++	   $(addprefix @srcdir@/../gcc/ada/,$(patsubst %.adb,%.ads,$(filter %.adb,$(VSN_SOURCES)))) \
++	   $(addprefix ../../gcc/ada/,$(VSN_GENERATED_SOURCES)) \
++	   $(addprefix ../../gcc/ada/,$(patsubst %.adb,%.ads,$(VSN_GENERATED_SOURCES))) \
++	   $(DESTDIR)$(prefix)/share/ada/adainclude/gnatvsn
++	mkdir -p $(DESTDIR)$(prefix)/lib/ada/adalib/gnatvsn
++	$(INSTALL) -m 0444 obj-shared/*.ali \
++	   $(DESTDIR)$(prefix)/lib/ada/adalib/gnatvsn
++	chmod a=r $(DESTDIR)$(prefix)/lib/ada/adalib/gnatvsn/*.ali
++
++.PHONY: clean
++clean:
++	rm -rf *.ali obj-static obj-shared libgnatvsn* *.adb *.ads stamp*
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -183,6 +183,13 @@ target_modules = { module= libada; no_in
+ 		   missing= TAGS;
+ 		   missing= install-info;
+ 		   missing= installcheck; };
++target_modules = { module= libgnatvsn; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgomp; bootstrap= true; lib_path=.libs; };
+ target_modules = { module= libitm; lib_path=.libs; };
+ target_modules = { module= libatomic; lib_path=.libs; };
+@@ -381,6 +388,8 @@ dependencies = { module=all-fixincludes;
+ 
+ dependencies = { module=all-target-libada; on=all-gcc; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
++dependencies = { module=all-gnattools; on=all-target-libgnatvsn; };
++dependencies = { module=all-target-libgnatvsn; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libstdc++-v3; };
+ 
+ // Depending on the specific configuration, the LTO plugin will either use the
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -177,6 +177,7 @@ target_libraries="target-libgcc \
+ 		target-libobjc \
+ 		target-libada \
+ 		${target_libiberty} \
++		target-libgnatvsn \
+ 		target-libgo"
+ 
+ # these tools are built using the target libraries, and are intended to
+@@ -461,7 +462,7 @@ AC_ARG_ENABLE(libada,
+ ENABLE_LIBADA=$enableval,
+ ENABLE_LIBADA=yes)
+ if test "${ENABLE_LIBADA}" != "yes" ; then
+-  noconfigdirs="$noconfigdirs gnattools"
++  noconfigdirs="$noconfigdirs target-libgnatvsn gnattools"
+ fi
+ 
+ AC_ARG_ENABLE(libssp,
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -34,8 +34,8 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ 
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+-target_libs="target-libada"
+-lang_dirs="libada gnattools"
++target_libs="target-libada target-libgnatvsn"
++lang_dirs="libada libgnatvsn gnattools"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -976,6 +976,7 @@ configure-target:  \
+     maybe-configure-target-boehm-gc \
+     maybe-configure-target-rda \
+     maybe-configure-target-libada \
++    maybe-configure-target-libgnatvsn \
+     maybe-configure-target-libgomp \
+     maybe-configure-target-libitm \
+     maybe-configure-target-libatomic
+@@ -1144,6 +1145,7 @@ all-target: maybe-all-target-zlib
+ all-target: maybe-all-target-boehm-gc
+ all-target: maybe-all-target-rda
+ all-target: maybe-all-target-libada
++all-target: maybe-all-target-libgnatvsn
+ @if target-libgomp-no-bootstrap
+ all-target: maybe-all-target-libgomp
+ @endif target-libgomp-no-bootstrap
+@@ -1239,6 +1241,7 @@ info-target: maybe-info-target-zlib
+ info-target: maybe-info-target-boehm-gc
+ info-target: maybe-info-target-rda
+ info-target: maybe-info-target-libada
++info-target: maybe-info-target-libgnatvsn
+ info-target: maybe-info-target-libgomp
+ info-target: maybe-info-target-libitm
+ info-target: maybe-info-target-libatomic
+@@ -1327,6 +1330,7 @@ dvi-target: maybe-dvi-target-zlib
+ dvi-target: maybe-dvi-target-boehm-gc
+ dvi-target: maybe-dvi-target-rda
+ dvi-target: maybe-dvi-target-libada
++dvi-target: maybe-dvi-target-libgnatvsn
+ dvi-target: maybe-dvi-target-libgomp
+ dvi-target: maybe-dvi-target-libitm
+ dvi-target: maybe-dvi-target-libatomic
+@@ -1415,6 +1419,7 @@ pdf-target: maybe-pdf-target-zlib
+ pdf-target: maybe-pdf-target-boehm-gc
+ pdf-target: maybe-pdf-target-rda
+ pdf-target: maybe-pdf-target-libada
++pdf-target: maybe-pdf-target-libgnatvsn
+ pdf-target: maybe-pdf-target-libgomp
+ pdf-target: maybe-pdf-target-libitm
+ pdf-target: maybe-pdf-target-libatomic
+@@ -1503,6 +1508,7 @@ html-target: maybe-html-target-zlib
+ html-target: maybe-html-target-boehm-gc
+ html-target: maybe-html-target-rda
+ html-target: maybe-html-target-libada
++html-target: maybe-html-target-libgnatvsn
+ html-target: maybe-html-target-libgomp
+ html-target: maybe-html-target-libitm
+ html-target: maybe-html-target-libatomic
+@@ -1591,6 +1597,7 @@ TAGS-target: maybe-TAGS-target-zlib
+ TAGS-target: maybe-TAGS-target-boehm-gc
+ TAGS-target: maybe-TAGS-target-rda
+ TAGS-target: maybe-TAGS-target-libada
++TAGS-target: maybe-TAGS-target-libgnatvsn
+ TAGS-target: maybe-TAGS-target-libgomp
+ TAGS-target: maybe-TAGS-target-libitm
+ TAGS-target: maybe-TAGS-target-libatomic
+@@ -1679,6 +1686,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-boehm-gc
+ install-info-target: maybe-install-info-target-rda
+ install-info-target: maybe-install-info-target-libada
++install-info-target: maybe-install-info-target-libgnatvsn
+ install-info-target: maybe-install-info-target-libgomp
+ install-info-target: maybe-install-info-target-libitm
+ install-info-target: maybe-install-info-target-libatomic
+@@ -1767,6 +1775,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-boehm-gc
+ install-pdf-target: maybe-install-pdf-target-rda
+ install-pdf-target: maybe-install-pdf-target-libada
++install-pdf-target: maybe-install-pdf-target-libgnatvsn
+ install-pdf-target: maybe-install-pdf-target-libgomp
+ install-pdf-target: maybe-install-pdf-target-libitm
+ install-pdf-target: maybe-install-pdf-target-libatomic
+@@ -1855,6 +1864,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-boehm-gc
+ install-html-target: maybe-install-html-target-rda
+ install-html-target: maybe-install-html-target-libada
++install-html-target: maybe-install-html-target-libgnatvsn
+ install-html-target: maybe-install-html-target-libgomp
+ install-html-target: maybe-install-html-target-libitm
+ install-html-target: maybe-install-html-target-libatomic
+@@ -1943,6 +1953,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-boehm-gc
+ installcheck-target: maybe-installcheck-target-rda
+ installcheck-target: maybe-installcheck-target-libada
++installcheck-target: maybe-installcheck-target-libgnatvsn
+ installcheck-target: maybe-installcheck-target-libgomp
+ installcheck-target: maybe-installcheck-target-libitm
+ installcheck-target: maybe-installcheck-target-libatomic
+@@ -2031,6 +2042,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-boehm-gc
+ mostlyclean-target: maybe-mostlyclean-target-rda
+ mostlyclean-target: maybe-mostlyclean-target-libada
++mostlyclean-target: maybe-mostlyclean-target-libgnatvsn
+ mostlyclean-target: maybe-mostlyclean-target-libgomp
+ mostlyclean-target: maybe-mostlyclean-target-libitm
+ mostlyclean-target: maybe-mostlyclean-target-libatomic
+@@ -2119,6 +2131,7 @@ clean-target: maybe-clean-target-zlib
+ clean-target: maybe-clean-target-boehm-gc
+ clean-target: maybe-clean-target-rda
+ clean-target: maybe-clean-target-libada
++clean-target: maybe-clean-target-libgnatvsn
+ clean-target: maybe-clean-target-libgomp
+ clean-target: maybe-clean-target-libitm
+ clean-target: maybe-clean-target-libatomic
+@@ -2207,6 +2220,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-boehm-gc
+ distclean-target: maybe-distclean-target-rda
+ distclean-target: maybe-distclean-target-libada
++distclean-target: maybe-distclean-target-libgnatvsn
+ distclean-target: maybe-distclean-target-libgomp
+ distclean-target: maybe-distclean-target-libitm
+ distclean-target: maybe-distclean-target-libatomic
+@@ -2295,6 +2309,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-boehm-gc
+ maintainer-clean-target: maybe-maintainer-clean-target-rda
+ maintainer-clean-target: maybe-maintainer-clean-target-libada
++maintainer-clean-target: maybe-maintainer-clean-target-libgnatvsn
+ maintainer-clean-target: maybe-maintainer-clean-target-libgomp
+ maintainer-clean-target: maybe-maintainer-clean-target-libitm
+ maintainer-clean-target: maybe-maintainer-clean-target-libatomic
+@@ -2439,6 +2454,7 @@ check-target:  \
+     maybe-check-target-boehm-gc \
+     maybe-check-target-rda \
+     maybe-check-target-libada \
++    maybe-check-target-libgnatvsn \
+     maybe-check-target-libgomp \
+     maybe-check-target-libitm \
+     maybe-check-target-libatomic
+@@ -2623,6 +2639,7 @@ install-target:  \
+     maybe-install-target-boehm-gc \
+     maybe-install-target-rda \
+     maybe-install-target-libada \
++    maybe-install-target-libgnatvsn \
+     maybe-install-target-libgomp \
+     maybe-install-target-libitm \
+     maybe-install-target-libatomic
+@@ -2731,6 +2748,7 @@ install-strip-target:  \
+     maybe-install-strip-target-boehm-gc \
+     maybe-install-strip-target-rda \
+     maybe-install-strip-target-libada \
++    maybe-install-strip-target-libgnatvsn \
+     maybe-install-strip-target-libgomp \
+     maybe-install-strip-target-libitm \
+     maybe-install-strip-target-libatomic
+@@ -46041,6 +46059,362 @@ maintainer-clean-target-libada:
+ 
+ 
+ 
++.PHONY: configure-target-libgnatvsn maybe-configure-target-libgnatvsn
++maybe-configure-target-libgnatvsn:
++@if gcc-bootstrap
++configure-target-libgnatvsn: stage_current
++@endif gcc-bootstrap
++@if target-libgnatvsn
++maybe-configure-target-libgnatvsn: configure-target-libgnatvsn
++configure-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libgnatvsn..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp 2> /dev/null ; \
++	if test -r $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libgnatvsn/Makefile; \
++	    mv $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libgnatvsn/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libgnatvsn; \
++	cd "$(TARGET_SUBDIR)/libgnatvsn" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libgnatvsn/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libgnatvsn; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libgnatvsn
++
++
++
++
++
++.PHONY: all-target-libgnatvsn maybe-all-target-libgnatvsn
++maybe-all-target-libgnatvsn:
++@if gcc-bootstrap
++all-target-libgnatvsn: stage_current
++@endif gcc-bootstrap
++@if target-libgnatvsn
++TARGET-target-libgnatvsn=all
++maybe-all-target-libgnatvsn: all-target-libgnatvsn
++all-target-libgnatvsn: configure-target-libgnatvsn
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libgnatvsn))
++@endif target-libgnatvsn
++
++
++
++
++
++.PHONY: check-target-libgnatvsn maybe-check-target-libgnatvsn
++maybe-check-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-check-target-libgnatvsn: check-target-libgnatvsn
++
++# Dummy target for uncheckable module.
++check-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: install-target-libgnatvsn maybe-install-target-libgnatvsn
++maybe-install-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-target-libgnatvsn: install-target-libgnatvsn
++
++install-target-libgnatvsn: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++
++@endif target-libgnatvsn
++
++.PHONY: install-strip-target-libgnatvsn maybe-install-strip-target-libgnatvsn
++maybe-install-strip-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-strip-target-libgnatvsn: install-strip-target-libgnatvsn
++
++install-strip-target-libgnatvsn: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++
++@endif target-libgnatvsn
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libgnatvsn info-target-libgnatvsn
++maybe-info-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-info-target-libgnatvsn: info-target-libgnatvsn
++
++# libgnatvsn doesn't support info.
++info-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-dvi-target-libgnatvsn dvi-target-libgnatvsn
++maybe-dvi-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-dvi-target-libgnatvsn: dvi-target-libgnatvsn
++
++# libgnatvsn doesn't support dvi.
++dvi-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-pdf-target-libgnatvsn pdf-target-libgnatvsn
++maybe-pdf-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-pdf-target-libgnatvsn: pdf-target-libgnatvsn
++
++pdf-target-libgnatvsn: \
++    configure-target-libgnatvsn 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-html-target-libgnatvsn html-target-libgnatvsn
++maybe-html-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-html-target-libgnatvsn: html-target-libgnatvsn
++
++# libgnatvsn doesn't support html.
++html-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-TAGS-target-libgnatvsn TAGS-target-libgnatvsn
++maybe-TAGS-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-TAGS-target-libgnatvsn: TAGS-target-libgnatvsn
++
++# libgnatvsn doesn't support TAGS.
++TAGS-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-install-info-target-libgnatvsn install-info-target-libgnatvsn
++maybe-install-info-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-info-target-libgnatvsn: install-info-target-libgnatvsn
++
++# libgnatvsn doesn't support install-info.
++install-info-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-install-pdf-target-libgnatvsn install-pdf-target-libgnatvsn
++maybe-install-pdf-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-pdf-target-libgnatvsn: install-pdf-target-libgnatvsn
++
++install-pdf-target-libgnatvsn: \
++    configure-target-libgnatvsn \
++    pdf-target-libgnatvsn 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-install-html-target-libgnatvsn install-html-target-libgnatvsn
++maybe-install-html-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-html-target-libgnatvsn: install-html-target-libgnatvsn
++
++install-html-target-libgnatvsn: \
++    configure-target-libgnatvsn \
++    html-target-libgnatvsn 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-installcheck-target-libgnatvsn installcheck-target-libgnatvsn
++maybe-installcheck-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-installcheck-target-libgnatvsn: installcheck-target-libgnatvsn
++
++# libgnatvsn doesn't support installcheck.
++installcheck-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-mostlyclean-target-libgnatvsn mostlyclean-target-libgnatvsn
++maybe-mostlyclean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-mostlyclean-target-libgnatvsn: mostlyclean-target-libgnatvsn
++
++mostlyclean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-clean-target-libgnatvsn clean-target-libgnatvsn
++maybe-clean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-clean-target-libgnatvsn: clean-target-libgnatvsn
++
++clean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-distclean-target-libgnatvsn distclean-target-libgnatvsn
++maybe-distclean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-distclean-target-libgnatvsn: distclean-target-libgnatvsn
++
++distclean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-maintainer-clean-target-libgnatvsn maintainer-clean-target-libgnatvsn
++maybe-maintainer-clean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-maintainer-clean-target-libgnatvsn: maintainer-clean-target-libgnatvsn
++
++maintainer-clean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++
++
++
++
+ .PHONY: configure-target-libgomp maybe-configure-target-libgomp
+ maybe-configure-target-libgomp:
+ @if gcc-bootstrap
+@@ -50245,6 +50619,7 @@ configure-target-zlib: stage_last
+ configure-target-boehm-gc: stage_last
+ configure-target-rda: stage_last
+ configure-target-libada: stage_last
++configure-target-libgnatvsn: stage_last
+ configure-stage1-target-libgomp: maybe-all-stage1-gcc
+ configure-stage2-target-libgomp: maybe-all-stage2-gcc
+ configure-stage3-target-libgomp: maybe-all-stage3-gcc
+@@ -50280,6 +50655,7 @@ configure-target-zlib: maybe-all-gcc
+ configure-target-boehm-gc: maybe-all-gcc
+ configure-target-rda: maybe-all-gcc
+ configure-target-libada: maybe-all-gcc
++configure-target-libgnatvsn: maybe-all-gcc
+ configure-target-libgomp: maybe-all-gcc
+ configure-target-libitm: maybe-all-gcc
+ configure-target-libatomic: maybe-all-gcc
+@@ -50653,6 +51029,8 @@ all-stageprofile-fixincludes: maybe-all-
+ all-stagefeedback-fixincludes: maybe-all-stagefeedback-libiberty
+ all-target-libada: maybe-all-gcc
+ all-gnattools: maybe-all-target-libada
++all-gnattools: maybe-all-target-libgnatvsn
++all-target-libgnatvsn: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libstdc++-v3
+ all-lto-plugin: maybe-all-libiberty
+ 
+@@ -51249,6 +51627,7 @@ configure-target-zlib: maybe-all-target-
+ configure-target-boehm-gc: maybe-all-target-libgcc
+ configure-target-rda: maybe-all-target-libgcc
+ configure-target-libada: maybe-all-target-libgcc
++configure-target-libgnatvsn: maybe-all-target-libgcc
+ configure-target-libgomp: maybe-all-target-libgcc
+ configure-target-libitm: maybe-all-target-libgcc
+ configure-target-libatomic: maybe-all-target-libgcc
+@@ -51303,6 +51682,8 @@ configure-target-rda: maybe-all-target-n
+ 
+ configure-target-libada: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libgnatvsn: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libgomp: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-libitm: maybe-all-target-newlib maybe-all-target-libgloss
--- gcc-6-6.3.0.orig/debian/patches/ada-library-project-files-soname.diff
+++ gcc-6-6.3.0/debian/patches/ada-library-project-files-soname.diff
@@ -0,0 +1,81 @@
+# DP: - in project files, use the exact Library_Version provided, if any, as
+# DP:   the soname of libraries; do not strip minor version numbers
+# DP:   (PR ada/40025).
+
+Index: b/src/gcc/ada/mlib-tgt-specific-linux.adb
+===================================================================
+--- a/src/gcc/ada/mlib-tgt-specific-linux.adb
++++ b/src/gcc/ada/mlib-tgt-specific-linux.adb
+@@ -50,6 +50,8 @@ package body MLib.Tgt.Specific is
+ 
+    function Is_Archive_Ext (Ext : String) return Boolean;
+ 
++   function Library_Major_Minor_Id_Supported return Boolean;
++
+    ---------------------------
+    -- Build_Dynamic_Library --
+    ---------------------------
+@@ -142,7 +144,18 @@ package body MLib.Tgt.Specific is
+       return Ext = ".a" or else Ext = ".so";
+    end Is_Archive_Ext;
+ 
++   --------------------------------------
++   -- Library_Major_Minor_Id_Supported --
++   --------------------------------------
++
++   function Library_Major_Minor_Id_Supported return Boolean is
++   begin
++      return False;
++   end Library_Major_Minor_Id_Supported;
++
+ begin
+    Build_Dynamic_Library_Ptr := Build_Dynamic_Library'Access;
+    Is_Archive_Ext_Ptr := Is_Archive_Ext'Access;
++   Library_Major_Minor_Id_Supported_Ptr :=
++                                Library_Major_Minor_Id_Supported'Access;
+ end MLib.Tgt.Specific;
+Index: b/src/gcc/ada/mlib.adb
+===================================================================
+--- a/src/gcc/ada/mlib.adb
++++ b/src/gcc/ada/mlib.adb
+@@ -30,6 +30,7 @@ with System;
+ with Opt;
+ with Output; use Output;
+ 
++with MLib.Tgt;
+ with MLib.Utl; use MLib.Utl;
+ 
+ with Prj.Com;
+@@ -393,7 +394,11 @@ package body MLib is
+    -- Major_Id_Name --
+    -------------------
+ 
+-   function Major_Id_Name
++   function Major_Id_Name_If_Supported
++     (Lib_Filename : String;
++      Lib_Version  : String)
++      return String;
++   function Major_Id_Name_If_Supported
+      (Lib_Filename : String;
+       Lib_Version  : String)
+       return String
+@@ -447,6 +452,19 @@ package body MLib is
+       else
+          return "";
+       end if;
++   end Major_Id_Name_If_Supported;
++
++   function Major_Id_Name
++     (Lib_Filename : String;
++      Lib_Version  : String)
++      return String
++   is
++   begin
++      if MLib.Tgt.Library_Major_Minor_Id_Supported then
++         return Major_Id_Name_If_Supported (Lib_Filename, Lib_Version);
++      else
++         return "";
++      end if;
+    end Major_Id_Name;
+ 
+    -------------------------------
--- gcc-6-6.3.0.orig/debian/patches/ada-link-lib.diff
+++ gcc-6-6.3.0/debian/patches/ada-link-lib.diff
@@ -0,0 +1,1195 @@
+# DP: - Install the shared Ada libraries as '.so.1', not '.so' to conform
+# DP:   to the Debian policy.
+# DP: - Don't include a runtime link path (-rpath), when linking binaries.
+# DP: - Build the shared libraries on hppa-linux.
+# DP: - Instead of building libada as a target library only, build it as
+# DP:   both a host and, if different, target library.
+# DP: - Build the GNAT tools in their top-level directory; do not use
+# DP:   recursive makefiles.
+# DP: - Link the GNAT tools dynamically.
+
+# This patch seems large, but the hunks in Makefile.in are actually
+# generated from Makefile.def using autogen.
+
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -35,7 +35,7 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+ target_libs="target-libada"
+-lang_dirs="gnattools"
++lang_dirs="libada gnattools"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/gcc/ada/link.c
+===================================================================
+--- a/src/gcc/ada/link.c
++++ b/src/gcc/ada/link.c
+@@ -106,9 +106,9 @@ const char *__gnat_default_libgcc_subdir
+ #elif defined (__FreeBSD__) || defined (__DragonFly__) \
+    || defined (__NetBSD__) || defined (__OpenBSD__)
+ const char *__gnat_object_file_option = "-Wl,@";
+-const char *__gnat_run_path_option = "-Wl,-rpath,";
+-char __gnat_shared_libgnat_default = STATIC;
+-char __gnat_shared_libgcc_default = STATIC;
++const char *__gnat_run_path_option = "";
++char __gnat_shared_libgnat_default = SHARED;
++char __gnat_shared_libgcc_default = SHARED;
+ int __gnat_link_max = 8192;
+ unsigned char __gnat_objlist_file_supported = 1;
+ const char *__gnat_object_library_extension = ".a";
+@@ -128,9 +128,9 @@ const char *__gnat_default_libgcc_subdir
+ 
+ #elif defined (__linux__) || defined (__GLIBC__)
+ const char *__gnat_object_file_option = "-Wl,@";
+-const char *__gnat_run_path_option = "-Wl,-rpath,";
+-char __gnat_shared_libgnat_default = STATIC;
+-char __gnat_shared_libgcc_default = STATIC;
++const char *__gnat_run_path_option = "";
++char __gnat_shared_libgnat_default = SHARED;
++char __gnat_shared_libgcc_default = SHARED;
+ int __gnat_link_max = 8192;
+ unsigned char __gnat_objlist_file_supported = 1;
+ const char *__gnat_object_library_extension = ".a";
+Index: b/src/libada/Makefile.in
+===================================================================
+--- a/src/libada/Makefile.in
++++ b/src/libada/Makefile.in
+@@ -60,7 +60,7 @@ CFLAGS=-g
+ PICFLAG = @PICFLAG@
+ GNATLIBFLAGS= -W -Wall -gnatpg -nostdinc
+ GNATLIBCFLAGS= -g -O2
+-GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) $(CFLAGS_FOR_TARGET) \
++GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) \
+ 	-fexceptions -DIN_RTS @have_getipinfo@
+ 
+ host_subdir = @host_subdir@
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -121,7 +121,13 @@ host_modules= { module= libtermcap; no_c
+                 missing=distclean;
+                 missing=maintainer-clean; };
+ host_modules= { module= utils; no_check=true; };
+-host_modules= { module= gnattools; };
++host_modules= { module= gnattools; no_check=true;
++		missing= info;
++		missing= dvi;
++		missing= html;
++		missing= TAGS;
++		missing= install-info;
++		missing= installcheck; };
+ host_modules= { module= lto-plugin; bootstrap=true;
+ 		extra_configure_flags='--enable-shared @extra_linker_plugin_flags@ @extra_linker_plugin_configure_flags@';
+ 		extra_make_flags='@extra_linker_plugin_flags@'; };
+@@ -164,12 +170,19 @@ target_modules = { module= libtermcap; n
+ target_modules = { module= winsup; };
+ target_modules = { module= libgloss; no_check=true; };
+ target_modules = { module= libffi; no_install=true; };
++target_modules = { module= libiberty; no_install=true; no_check=true; };
+ target_modules = { module= libjava; raw_cxx=true;
+                    extra_configure_flags="$(EXTRA_CONFIGARGS_LIBJAVA)"; };
+ target_modules = { module= zlib; };
+ target_modules = { module= boehm-gc; };
+ target_modules = { module= rda; };
+-target_modules = { module= libada; };
++target_modules = { module= libada; no_install=true; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgomp; bootstrap= true; lib_path=.libs; };
+ target_modules = { module= libitm; lib_path=.libs; };
+ target_modules = { module= libatomic; lib_path=.libs; };
+@@ -366,6 +379,7 @@ dependencies = { module=all-libcpp; on=a
+ 
+ dependencies = { module=all-fixincludes; on=all-libiberty; };
+ 
++dependencies = { module=all-target-libada; on=all-gcc; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libstdc++-v3; };
+ 
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -970,6 +970,7 @@ configure-target:  \
+     maybe-configure-target-winsup \
+     maybe-configure-target-libgloss \
+     maybe-configure-target-libffi \
++    maybe-configure-target-libiberty \
+     maybe-configure-target-libjava \
+     maybe-configure-target-zlib \
+     maybe-configure-target-boehm-gc \
+@@ -1137,6 +1138,7 @@ all-target: maybe-all-target-libtermcap
+ all-target: maybe-all-target-winsup
+ all-target: maybe-all-target-libgloss
+ all-target: maybe-all-target-libffi
++all-target: maybe-all-target-libiberty
+ all-target: maybe-all-target-libjava
+ all-target: maybe-all-target-zlib
+ all-target: maybe-all-target-boehm-gc
+@@ -1231,6 +1233,7 @@ info-target: maybe-info-target-libtermca
+ info-target: maybe-info-target-winsup
+ info-target: maybe-info-target-libgloss
+ info-target: maybe-info-target-libffi
++info-target: maybe-info-target-libiberty
+ info-target: maybe-info-target-libjava
+ info-target: maybe-info-target-zlib
+ info-target: maybe-info-target-boehm-gc
+@@ -1318,6 +1321,7 @@ dvi-target: maybe-dvi-target-libtermcap
+ dvi-target: maybe-dvi-target-winsup
+ dvi-target: maybe-dvi-target-libgloss
+ dvi-target: maybe-dvi-target-libffi
++dvi-target: maybe-dvi-target-libiberty
+ dvi-target: maybe-dvi-target-libjava
+ dvi-target: maybe-dvi-target-zlib
+ dvi-target: maybe-dvi-target-boehm-gc
+@@ -1405,6 +1409,7 @@ pdf-target: maybe-pdf-target-libtermcap
+ pdf-target: maybe-pdf-target-winsup
+ pdf-target: maybe-pdf-target-libgloss
+ pdf-target: maybe-pdf-target-libffi
++pdf-target: maybe-pdf-target-libiberty
+ pdf-target: maybe-pdf-target-libjava
+ pdf-target: maybe-pdf-target-zlib
+ pdf-target: maybe-pdf-target-boehm-gc
+@@ -1492,6 +1497,7 @@ html-target: maybe-html-target-libtermca
+ html-target: maybe-html-target-winsup
+ html-target: maybe-html-target-libgloss
+ html-target: maybe-html-target-libffi
++html-target: maybe-html-target-libiberty
+ html-target: maybe-html-target-libjava
+ html-target: maybe-html-target-zlib
+ html-target: maybe-html-target-boehm-gc
+@@ -1579,6 +1585,7 @@ TAGS-target: maybe-TAGS-target-libtermca
+ TAGS-target: maybe-TAGS-target-winsup
+ TAGS-target: maybe-TAGS-target-libgloss
+ TAGS-target: maybe-TAGS-target-libffi
++TAGS-target: maybe-TAGS-target-libiberty
+ TAGS-target: maybe-TAGS-target-libjava
+ TAGS-target: maybe-TAGS-target-zlib
+ TAGS-target: maybe-TAGS-target-boehm-gc
+@@ -1666,6 +1673,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-winsup
+ install-info-target: maybe-install-info-target-libgloss
+ install-info-target: maybe-install-info-target-libffi
++install-info-target: maybe-install-info-target-libiberty
+ install-info-target: maybe-install-info-target-libjava
+ install-info-target: maybe-install-info-target-zlib
+ install-info-target: maybe-install-info-target-boehm-gc
+@@ -1753,6 +1761,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-winsup
+ install-pdf-target: maybe-install-pdf-target-libgloss
+ install-pdf-target: maybe-install-pdf-target-libffi
++install-pdf-target: maybe-install-pdf-target-libiberty
+ install-pdf-target: maybe-install-pdf-target-libjava
+ install-pdf-target: maybe-install-pdf-target-zlib
+ install-pdf-target: maybe-install-pdf-target-boehm-gc
+@@ -1840,6 +1849,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-winsup
+ install-html-target: maybe-install-html-target-libgloss
+ install-html-target: maybe-install-html-target-libffi
++install-html-target: maybe-install-html-target-libiberty
+ install-html-target: maybe-install-html-target-libjava
+ install-html-target: maybe-install-html-target-zlib
+ install-html-target: maybe-install-html-target-boehm-gc
+@@ -1927,6 +1937,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-winsup
+ installcheck-target: maybe-installcheck-target-libgloss
+ installcheck-target: maybe-installcheck-target-libffi
++installcheck-target: maybe-installcheck-target-libiberty
+ installcheck-target: maybe-installcheck-target-libjava
+ installcheck-target: maybe-installcheck-target-zlib
+ installcheck-target: maybe-installcheck-target-boehm-gc
+@@ -2014,6 +2025,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-winsup
+ mostlyclean-target: maybe-mostlyclean-target-libgloss
+ mostlyclean-target: maybe-mostlyclean-target-libffi
++mostlyclean-target: maybe-mostlyclean-target-libiberty
+ mostlyclean-target: maybe-mostlyclean-target-libjava
+ mostlyclean-target: maybe-mostlyclean-target-zlib
+ mostlyclean-target: maybe-mostlyclean-target-boehm-gc
+@@ -2101,6 +2113,7 @@ clean-target: maybe-clean-target-libterm
+ clean-target: maybe-clean-target-winsup
+ clean-target: maybe-clean-target-libgloss
+ clean-target: maybe-clean-target-libffi
++clean-target: maybe-clean-target-libiberty
+ clean-target: maybe-clean-target-libjava
+ clean-target: maybe-clean-target-zlib
+ clean-target: maybe-clean-target-boehm-gc
+@@ -2188,6 +2201,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-winsup
+ distclean-target: maybe-distclean-target-libgloss
+ distclean-target: maybe-distclean-target-libffi
++distclean-target: maybe-distclean-target-libiberty
+ distclean-target: maybe-distclean-target-libjava
+ distclean-target: maybe-distclean-target-zlib
+ distclean-target: maybe-distclean-target-boehm-gc
+@@ -2275,6 +2289,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-winsup
+ maintainer-clean-target: maybe-maintainer-clean-target-libgloss
+ maintainer-clean-target: maybe-maintainer-clean-target-libffi
++maintainer-clean-target: maybe-maintainer-clean-target-libiberty
+ maintainer-clean-target: maybe-maintainer-clean-target-libjava
+ maintainer-clean-target: maybe-maintainer-clean-target-zlib
+ maintainer-clean-target: maybe-maintainer-clean-target-boehm-gc
+@@ -2418,6 +2433,7 @@ check-target:  \
+     maybe-check-target-winsup \
+     maybe-check-target-libgloss \
+     maybe-check-target-libffi \
++    maybe-check-target-libiberty \
+     maybe-check-target-libjava \
+     maybe-check-target-zlib \
+     maybe-check-target-boehm-gc \
+@@ -2601,6 +2617,7 @@ install-target:  \
+     maybe-install-target-winsup \
+     maybe-install-target-libgloss \
+     maybe-install-target-libffi \
++    maybe-install-target-libiberty \
+     maybe-install-target-libjava \
+     maybe-install-target-zlib \
+     maybe-install-target-boehm-gc \
+@@ -2708,6 +2725,7 @@ install-strip-target:  \
+     maybe-install-strip-target-winsup \
+     maybe-install-strip-target-libgloss \
+     maybe-install-strip-target-libffi \
++    maybe-install-strip-target-libiberty \
+     maybe-install-strip-target-libjava \
+     maybe-install-strip-target-zlib \
+     maybe-install-strip-target-boehm-gc \
+@@ -30607,12 +30625,6 @@ maybe-check-gnattools:
+ maybe-check-gnattools: check-gnattools
+ 
+ check-gnattools:
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS)  \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(FLAGS_TO_PASS)  check)
+ 
+ @endif gnattools
+ 
+@@ -30653,24 +30665,8 @@ maybe-info-gnattools:
+ @if gnattools
+ maybe-info-gnattools: info-gnattools
+ 
+-info-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing info in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          info) \
+-	  || exit 1
++# gnattools doesn't support info.
++info-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30679,24 +30675,8 @@ maybe-dvi-gnattools:
+ @if gnattools
+ maybe-dvi-gnattools: dvi-gnattools
+ 
+-dvi-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing dvi in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          dvi) \
+-	  || exit 1
++# gnattools doesn't support dvi.
++dvi-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30731,24 +30711,8 @@ maybe-html-gnattools:
+ @if gnattools
+ maybe-html-gnattools: html-gnattools
+ 
+-html-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing html in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          html) \
+-	  || exit 1
++# gnattools doesn't support html.
++html-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30757,24 +30721,8 @@ maybe-TAGS-gnattools:
+ @if gnattools
+ maybe-TAGS-gnattools: TAGS-gnattools
+ 
+-TAGS-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing TAGS in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          TAGS) \
+-	  || exit 1
++# gnattools doesn't support TAGS.
++TAGS-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30783,25 +30731,8 @@ maybe-install-info-gnattools:
+ @if gnattools
+ maybe-install-info-gnattools: install-info-gnattools
+ 
+-install-info-gnattools: \
+-    configure-gnattools \
+-    info-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing install-info in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          install-info) \
+-	  || exit 1
++# gnattools doesn't support install-info.
++install-info-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30864,24 +30795,8 @@ maybe-installcheck-gnattools:
+ @if gnattools
+ maybe-installcheck-gnattools: installcheck-gnattools
+ 
+-installcheck-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing installcheck in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          installcheck) \
+-	  || exit 1
++# gnattools doesn't support installcheck.
++installcheck-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -43505,6 +43420,449 @@ maintainer-clean-target-libffi:
+ 
+ 
+ 
++.PHONY: configure-target-libiberty maybe-configure-target-libiberty
++maybe-configure-target-libiberty:
++@if gcc-bootstrap
++configure-target-libiberty: stage_current
++@endif gcc-bootstrap
++@if target-libiberty
++maybe-configure-target-libiberty: configure-target-libiberty
++configure-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libiberty..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libiberty; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libiberty/multilib.tmp 2> /dev/null; \
++	if test -r $(TARGET_SUBDIR)/libiberty/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libiberty/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libiberty/Makefile; \
++	    mv $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libiberty/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libiberty; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libiberty; \
++	cd "$(TARGET_SUBDIR)/libiberty" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libiberty/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libiberty; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libiberty
++
++
++
++
++
++.PHONY: all-target-libiberty maybe-all-target-libiberty
++maybe-all-target-libiberty:
++@if gcc-bootstrap
++all-target-libiberty: stage_current
++@endif gcc-bootstrap
++@if target-libiberty
++TARGET-target-libiberty=all
++maybe-all-target-libiberty: all-target-libiberty
++all-target-libiberty: configure-target-libiberty
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libiberty))
++@endif target-libiberty
++
++
++
++
++
++.PHONY: check-target-libiberty maybe-check-target-libiberty
++maybe-check-target-libiberty:
++@if target-libiberty
++maybe-check-target-libiberty: check-target-libiberty
++
++# Dummy target for uncheckable module.
++check-target-libiberty:
++
++@endif target-libiberty
++
++.PHONY: install-target-libiberty maybe-install-target-libiberty
++maybe-install-target-libiberty:
++@if target-libiberty
++maybe-install-target-libiberty: install-target-libiberty
++
++# Dummy target for uninstallable.
++install-target-libiberty:
++
++@endif target-libiberty
++
++.PHONY: install-strip-target-libiberty maybe-install-strip-target-libiberty
++maybe-install-strip-target-libiberty:
++@if target-libiberty
++maybe-install-strip-target-libiberty: install-strip-target-libiberty
++
++# Dummy target for uninstallable.
++install-strip-target-libiberty:
++
++@endif target-libiberty
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libiberty info-target-libiberty
++maybe-info-target-libiberty:
++@if target-libiberty
++maybe-info-target-libiberty: info-target-libiberty
++
++info-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing info in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           info) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-dvi-target-libiberty dvi-target-libiberty
++maybe-dvi-target-libiberty:
++@if target-libiberty
++maybe-dvi-target-libiberty: dvi-target-libiberty
++
++dvi-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing dvi in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           dvi) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-pdf-target-libiberty pdf-target-libiberty
++maybe-pdf-target-libiberty:
++@if target-libiberty
++maybe-pdf-target-libiberty: pdf-target-libiberty
++
++pdf-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-html-target-libiberty html-target-libiberty
++maybe-html-target-libiberty:
++@if target-libiberty
++maybe-html-target-libiberty: html-target-libiberty
++
++html-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing html in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           html) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-TAGS-target-libiberty TAGS-target-libiberty
++maybe-TAGS-target-libiberty:
++@if target-libiberty
++maybe-TAGS-target-libiberty: TAGS-target-libiberty
++
++TAGS-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing TAGS in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           TAGS) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-install-info-target-libiberty install-info-target-libiberty
++maybe-install-info-target-libiberty:
++@if target-libiberty
++maybe-install-info-target-libiberty: install-info-target-libiberty
++
++install-info-target-libiberty: \
++    configure-target-libiberty \
++    info-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-info in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-info) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-install-pdf-target-libiberty install-pdf-target-libiberty
++maybe-install-pdf-target-libiberty:
++@if target-libiberty
++maybe-install-pdf-target-libiberty: install-pdf-target-libiberty
++
++install-pdf-target-libiberty: \
++    configure-target-libiberty \
++    pdf-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-install-html-target-libiberty install-html-target-libiberty
++maybe-install-html-target-libiberty:
++@if target-libiberty
++maybe-install-html-target-libiberty: install-html-target-libiberty
++
++install-html-target-libiberty: \
++    configure-target-libiberty \
++    html-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-installcheck-target-libiberty installcheck-target-libiberty
++maybe-installcheck-target-libiberty:
++@if target-libiberty
++maybe-installcheck-target-libiberty: installcheck-target-libiberty
++
++installcheck-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing installcheck in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           installcheck) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-mostlyclean-target-libiberty mostlyclean-target-libiberty
++maybe-mostlyclean-target-libiberty:
++@if target-libiberty
++maybe-mostlyclean-target-libiberty: mostlyclean-target-libiberty
++
++mostlyclean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-clean-target-libiberty clean-target-libiberty
++maybe-clean-target-libiberty:
++@if target-libiberty
++maybe-clean-target-libiberty: clean-target-libiberty
++
++clean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-distclean-target-libiberty distclean-target-libiberty
++maybe-distclean-target-libiberty:
++@if target-libiberty
++maybe-distclean-target-libiberty: distclean-target-libiberty
++
++distclean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-maintainer-clean-target-libiberty maintainer-clean-target-libiberty
++maybe-maintainer-clean-target-libiberty:
++@if target-libiberty
++maybe-maintainer-clean-target-libiberty: maintainer-clean-target-libiberty
++
++maintainer-clean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libiberty
++
++
++
++
++
+ .PHONY: configure-target-libjava maybe-configure-target-libjava
+ maybe-configure-target-libjava:
+ @if gcc-bootstrap
+@@ -45412,13 +45770,8 @@ maybe-check-target-libada:
+ @if target-libada
+ maybe-check-target-libada: check-target-libada
+ 
++# Dummy target for uncheckable module.
+ check-target-libada:
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(TARGET_FLAGS_TO_PASS)   check)
+ 
+ @endif target-libada
+ 
+@@ -45427,13 +45780,8 @@ maybe-install-target-libada:
+ @if target-libada
+ maybe-install-target-libada: install-target-libada
+ 
+-install-target-libada: installdirs
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++# Dummy target for uninstallable.
++install-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45442,13 +45790,8 @@ maybe-install-strip-target-libada:
+ @if target-libada
+ maybe-install-strip-target-libada: install-strip-target-libada
+ 
+-install-strip-target-libada: installdirs
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++# Dummy target for uninstallable.
++install-strip-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45459,24 +45802,8 @@ maybe-info-target-libada:
+ @if target-libada
+ maybe-info-target-libada: info-target-libada
+ 
+-info-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing info in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           info) \
+-	  || exit 1
++# libada doesn't support info.
++info-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45485,24 +45812,8 @@ maybe-dvi-target-libada:
+ @if target-libada
+ maybe-dvi-target-libada: dvi-target-libada
+ 
+-dvi-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing dvi in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           dvi) \
+-	  || exit 1
++# libada doesn't support dvi.
++dvi-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45537,24 +45848,8 @@ maybe-html-target-libada:
+ @if target-libada
+ maybe-html-target-libada: html-target-libada
+ 
+-html-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing html in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           html) \
+-	  || exit 1
++# libada doesn't support html.
++html-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45563,24 +45858,8 @@ maybe-TAGS-target-libada:
+ @if target-libada
+ maybe-TAGS-target-libada: TAGS-target-libada
+ 
+-TAGS-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing TAGS in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           TAGS) \
+-	  || exit 1
++# libada doesn't support TAGS.
++TAGS-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45589,25 +45868,8 @@ maybe-install-info-target-libada:
+ @if target-libada
+ maybe-install-info-target-libada: install-info-target-libada
+ 
+-install-info-target-libada: \
+-    configure-target-libada \
+-    info-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-info in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           install-info) \
+-	  || exit 1
++# libada doesn't support install-info.
++install-info-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45670,24 +45932,8 @@ maybe-installcheck-target-libada:
+ @if target-libada
+ maybe-installcheck-target-libada: installcheck-target-libada
+ 
+-installcheck-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing installcheck in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           installcheck) \
+-	  || exit 1
++# libada doesn't support installcheck.
++installcheck-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -49993,6 +50239,7 @@ configure-target-libtermcap: stage_last
+ configure-target-winsup: stage_last
+ configure-target-libgloss: stage_last
+ configure-target-libffi: stage_last
++configure-target-libiberty: stage_last
+ configure-target-libjava: stage_last
+ configure-target-zlib: stage_last
+ configure-target-boehm-gc: stage_last
+@@ -50027,6 +50274,7 @@ configure-target-libtermcap: maybe-all-g
+ configure-target-winsup: maybe-all-gcc
+ configure-target-libgloss: maybe-all-gcc
+ configure-target-libffi: maybe-all-gcc
++configure-target-libiberty: maybe-all-gcc
+ configure-target-libjava: maybe-all-gcc
+ configure-target-zlib: maybe-all-gcc
+ configure-target-boehm-gc: maybe-all-gcc
+@@ -50403,6 +50651,7 @@ all-stage3-fixincludes: maybe-all-stage3
+ all-stage4-fixincludes: maybe-all-stage4-libiberty
+ all-stageprofile-fixincludes: maybe-all-stageprofile-libiberty
+ all-stagefeedback-fixincludes: maybe-all-stagefeedback-libiberty
++all-target-libada: maybe-all-gcc
+ all-gnattools: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libstdc++-v3
+ all-lto-plugin: maybe-all-libiberty
+@@ -50994,6 +51243,7 @@ configure-target-libtermcap: maybe-all-t
+ configure-target-winsup: maybe-all-target-libgcc
+ configure-target-libgloss: maybe-all-target-libgcc
+ configure-target-libffi: maybe-all-target-libgcc
++configure-target-libiberty: maybe-all-target-libgcc
+ configure-target-libjava: maybe-all-target-libgcc
+ configure-target-zlib: maybe-all-target-libgcc
+ configure-target-boehm-gc: maybe-all-target-libgcc
+@@ -51041,6 +51291,7 @@ configure-target-winsup: maybe-all-targe
+ configure-target-libffi: maybe-all-target-newlib maybe-all-target-libgloss
+ configure-target-libffi: maybe-all-target-libstdc++-v3
+ 
++
+ configure-target-libjava: maybe-all-target-newlib maybe-all-target-libgloss
+ configure-target-libjava: maybe-all-target-libstdc++-v3
+ 
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -148,6 +148,11 @@ libgcj="target-libffi \
+ 	target-zlib \
+ 	target-libjava"
+ 
++case "${target}" in
++  hppa64-*linux*) ;;
++  *) target_libiberty="target-libiberty";;
++esac
++
+ # these libraries are built for the target environment, and are built after
+ # the host libraries and the host tools (which may be a cross compiler)
+ # Note that libiberty is not a target library.
+@@ -171,6 +176,7 @@ target_libraries="target-libgcc \
+ 		${libgcj} \
+ 		target-libobjc \
+ 		target-libada \
++		${target_libiberty} \
+ 		target-libgo"
+ 
+ # these tools are built using the target libraries, and are intended to
+Index: b/src/gcc/ada/gcc-interface/Make-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Make-lang.in
++++ b/src/gcc/ada/gcc-interface/Make-lang.in
+@@ -58,11 +58,7 @@ WARN_ADAFLAGS= -W -Wall
+ # need to be built by a recent/matching native so we might as well leave the
+ # checks fully active.
+ 
+-ifeq ($(CROSS),)
+ ADAFLAGS= $(COMMON_ADAFLAGS) -gnatwns
+-else
+-ADAFLAGS= $(COMMON_ADAFLAGS)
+-endif
+ 
+ ALL_ADAFLAGS = \
+   $(CFLAGS) $(ADA_CFLAGS) $(ADAFLAGS) $(CHECKING_ADAFLAGS) $(WARN_ADAFLAGS)
+Index: b/src/libada/configure.ac
+===================================================================
+--- a/src/libada/configure.ac
++++ b/src/libada/configure.ac
+@@ -127,8 +127,7 @@ AC_PROG_AWK
+ AC_PROG_LN_S
+ 
+ # Determine what to build for 'gnatlib'
+-if test $build = $target \
+-   && test ${enable_shared} = yes ; then
++if test ${enable_shared} = yes ; then
+   # Note that build=target is almost certainly the wrong test; FIXME
+   default_gnatlib_target="gnatlib-shared"
+ else
--- gcc-6-6.3.0.orig/debian/patches/ada-link-shlib.diff
+++ gcc-6-6.3.0/debian/patches/ada-link-shlib.diff
@@ -0,0 +1,89 @@
+# DP: In gnatlink, pass the options and libraries after objects to the
+# DP: linker to avoid link failures with --as-needed. Closes: #680292.
+
+Index: b/src/gcc/ada/mlib-tgt-specific-linux.adb
+===================================================================
+--- a/src/gcc/ada/mlib-tgt-specific-linux.adb
++++ b/src/gcc/ada/mlib-tgt-specific-linux.adb
+@@ -81,19 +81,54 @@ package body MLib.Tgt.Specific is
+       Version_Arg          : String_Access;
+       Symbolic_Link_Needed : Boolean := False;
+ 
++      N_Options    : Argument_List := Options;
++      Options_Last : Natural := N_Options'Last;
++      --  After moving -lxxx to Options_2, N_Options up to index Options_Last
++      --  will contain the Options to pass to MLib.Utl.Gcc.
++
++      Real_Options_2 : Argument_List (1 .. Options'Length);
++      Real_Options_2_Last : Natural := 0;
++      --  Real_Options_2 up to index Real_Options_2_Last will contain the
++      --  Options_2 to pass to MLib.Utl.Gcc.
++
+    begin
+       if Opt.Verbose_Mode then
+          Write_Str ("building relocatable shared library ");
+          Write_Line (Lib_Path);
+       end if;
+ 
++      --  Move all -lxxx to Options_2
++
++      declare
++         Index : Natural := N_Options'First;
++         Arg   : String_Access;
++
++      begin
++         while Index <= Options_Last loop
++            Arg := N_Options (Index);
++
++            if Arg'Length > 2
++              and then Arg (Arg'First .. Arg'First + 1) = "-l"
++            then
++               Real_Options_2_Last := Real_Options_2_Last + 1;
++               Real_Options_2 (Real_Options_2_Last) := Arg;
++               N_Options (Index .. Options_Last - 1) :=
++                 N_Options (Index + 1 .. Options_Last);
++               Options_Last := Options_Last - 1;
++
++            else
++               Index := Index + 1;
++            end if;
++         end loop;
++      end;
++
+       if Lib_Version = "" then
+          Utl.Gcc
+            (Output_File => Lib_Path,
+             Objects     => Ofiles,
+-            Options     => Options,
++            Options     => N_Options (N_Options'First .. Options_Last),
+             Driver_Name => Driver_Name,
+-            Options_2   => No_Argument_List);
++            Options_2   => Real_Options_2 (1 .. Real_Options_2_Last));
+ 
+       else
+          declare
+@@ -111,18 +146,20 @@ package body MLib.Tgt.Specific is
+                Utl.Gcc
+                  (Output_File => Lib_Version,
+                   Objects     => Ofiles,
+-                  Options     => Options & Version_Arg,
++                  Options     => N_Options (N_Options'First .. Options_Last)
++                                 & Version_Arg,
+                   Driver_Name => Driver_Name,
+-                  Options_2   => No_Argument_List);
++                  Options_2   => Real_Options_2 (1 .. Real_Options_2_Last));
+                Symbolic_Link_Needed := Lib_Version /= Lib_Path;
+ 
+             else
+                Utl.Gcc
+                  (Output_File => Lib_Dir & Directory_Separator & Lib_Version,
+                   Objects     => Ofiles,
+-                  Options     => Options & Version_Arg,
++                  Options     => N_Options (N_Options'First .. Options_Last)
++                                 & Version_Arg,
+                   Driver_Name => Driver_Name,
+-                  Options_2   => No_Argument_List);
++                  Options_2   => Real_Options_2 (1 .. Real_Options_2_Last));
+                Symbolic_Link_Needed :=
+                  Lib_Dir & Directory_Separator & Lib_Version /= Lib_Path;
+             end if;
--- gcc-6-6.3.0.orig/debian/patches/ada-m68k.diff
+++ gcc-6-6.3.0/debian/patches/ada-m68k.diff
@@ -0,0 +1,259 @@
+gcc/ada/
+
+2011-10-12  Mikael Pettersson  <mikpe@it.uu.se>
+
+	PR ada/48835
+	* gcc-interface/Makefile.in: Add support for m68k-linux.
+	* system-linux-m68k.ads: New file based on system-linux-ppc.ads
+	and system-vxworks-m68k.ads.
+	* s-memory.adb (Gnat_Malloc): New wrapper around Alloc, returning
+	the memory address as a pointer not an integer.
+	Add Gnat_Malloc -> __gnat_malloc export.
+	* s-memory.ads: Remove Alloc -> __gnat_malloc export.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -2084,6 +2084,35 @@ ifeq ($(strip $(filter-out hppa% linux%,
+   LIBRARY_VERSION := $(LIB_VERSION)
+ endif
+ 
++# M68K Linux
++ifeq ($(strip $(filter-out m68k% linux%,$(arch) $(osys))),)
++  LIBGNAT_TARGET_PAIRS = \
++  a-intnam.ads<a-intnam-linux.ads \
++  s-inmaop.adb<s-inmaop-posix.adb \
++  s-intman.adb<s-intman-posix.adb \
++  s-linux.ads<s-linux.ads \
++  s-osinte.adb<s-osinte-posix.adb \
++  s-osinte.ads<s-osinte-linux.ads \
++  s-osprim.adb<s-osprim-posix.adb \
++  s-taprop.adb<s-taprop-linux.adb \
++  s-tasinf.ads<s-tasinf-linux.ads \
++  s-tasinf.adb<s-tasinf-linux.adb \
++  s-taspri.ads<s-taspri-posix.ads \
++  s-tpopsp.adb<s-tpopsp-posix-foreign.adb \
++  system.ads<system-linux-m68k.ads
++
++  TOOLS_TARGET_PAIRS =  \
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
++    indepsw.adb<indepsw-gnu.adb
++
++  EXTRA_GNATRTL_TASKING_OBJS=s-linux.o
++  EH_MECHANISM=-gcc
++  THREADSLIB = -lpthread
++  GNATLIB_SHARED = gnatlib-shared-dual
++  GMEM_LIB = gmemlib
++  LIBRARY_VERSION := $(LIB_VERSION)
++endif
++
+ # SH4 Linux
+ ifeq ($(strip $(filter-out sh4% linux%,$(target_cpu) $(target_os))),)
+   LIBGNAT_TARGET_PAIRS = \
+Index: b/src/gcc/ada/s-memory.adb
+===================================================================
+--- a/src/gcc/ada/s-memory.adb
++++ b/src/gcc/ada/s-memory.adb
+@@ -47,6 +47,7 @@ with Ada.Exceptions;
+ with System.Soft_Links;
+ with System.Parameters;
+ with System.CRTL;
++with Ada.Unchecked_Conversion;
+ 
+ package body System.Memory is
+ 
+@@ -100,6 +101,22 @@ package body System.Memory is
+       return Result;
+    end Alloc;
+ 
++   type Char_Ptr is access all Character;
++   pragma Convention (C, Char_Ptr);
++   pragma No_Strict_Aliasing (Char_Ptr);
++
++   function To_Char_Ptr is
++      new Ada.Unchecked_Conversion (System.Address, Char_Ptr);
++
++   --  The function exported as __gnat_malloc MUST return a pointer type.
++   function Gnat_Malloc (Size : size_t) return Char_Ptr;
++   pragma Export (C, Gnat_Malloc, "__gnat_malloc");
++
++   function Gnat_Malloc (Size : size_t) return Char_Ptr is
++   begin
++      return To_Char_Ptr (Alloc (Size));
++   end Gnat_Malloc;
++
+    ----------
+    -- Free --
+    ----------
+Index: b/src/gcc/ada/s-memory.ads
+===================================================================
+--- a/src/gcc/ada/s-memory.ads
++++ b/src/gcc/ada/s-memory.ads
+@@ -100,7 +100,6 @@ private
+ 
+    --  The following names are used from the generated compiler code
+ 
+-   pragma Export (C, Alloc,   "__gnat_malloc");
+    pragma Export (C, Free,    "__gnat_free");
+    pragma Export (C, Realloc, "__gnat_realloc");
+ 
+Index: b/src/gcc/ada/system-linux-m68k.ads
+===================================================================
+--- /dev/null
++++ b/src/gcc/ada/system-linux-m68k.ads
+@@ -0,0 +1,154 @@
++------------------------------------------------------------------------------
++--                                                                          --
++--                        GNAT RUN-TIME COMPONENTS                          --
++--                                                                          --
++--                               S Y S T E M                                --
++--                                                                          --
++--                                 S p e c                                  --
++--                         (GNU/Linux/m68k Version)                         --
++--                                                                          --
++--          Copyright (C) 2014, Free Software Foundation, Inc.              --
++--                                                                          --
++-- This specification is derived from the Ada Reference Manual for use with --
++-- GNAT. The copyright notice above, and the license provisions that follow --
++-- apply solely to the  contents of the part following the private keyword. --
++--                                                                          --
++-- GNAT is free software;  you can  redistribute it  and/or modify it under --
++-- terms of the  GNU General Public License as published  by the Free Soft- --
++-- ware  Foundation;  either version 3,  or (at your option) any later ver- --
++-- sion.  GNAT is distributed in the hope that it will be useful, but WITH- --
++-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
++-- or FITNESS FOR A PARTICULAR PURPOSE.                                     --
++--                                                                          --
++-- As a special exception under Section 7 of GPL version 3, you are granted --
++-- additional permissions described in the GCC Runtime Library Exception,   --
++-- version 3.1, as published by the Free Software Foundation.               --
++--                                                                          --
++-- You should have received a copy of the GNU General Public License and    --
++-- a copy of the GCC Runtime Library Exception along with this program;     --
++-- see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see    --
++-- <http://www.gnu.org/licenses/>.                                          --
++--                                                                          --
++-- GNAT was originally developed  by the GNAT team at  New York University. --
++-- Extensive contributions were provided by Ada Core Technologies Inc.      --
++--                                                                          --
++------------------------------------------------------------------------------
++
++package System is
++   pragma Pure;
++   --  Note that we take advantage of the implementation permission to make
++   --  this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
++   --  2005, this is Pure in any case (AI-362).
++
++   type Name is (SYSTEM_NAME_GNAT);
++   System_Name : constant Name := SYSTEM_NAME_GNAT;
++
++   --  System-Dependent Named Numbers
++
++   Min_Int               : constant := Long_Long_Integer'First;
++   Max_Int               : constant := Long_Long_Integer'Last;
++
++   Max_Binary_Modulus    : constant := 2 ** Long_Long_Integer'Size;
++   Max_Nonbinary_Modulus : constant := 2 ** Integer'Size - 1;
++
++   Max_Base_Digits       : constant := Long_Long_Float'Digits;
++   Max_Digits            : constant := Long_Long_Float'Digits;
++
++   Max_Mantissa          : constant := 63;
++   Fine_Delta            : constant := 2.0 ** (-Max_Mantissa);
++
++   Tick                  : constant := 0.000_001;
++
++   --  Storage-related Declarations
++
++   type Address is private;
++   pragma Preelaborable_Initialization (Address);
++   Null_Address : constant Address;
++
++   Storage_Unit : constant := 8;
++   Word_Size    : constant := 32;
++   Memory_Size  : constant := 2 ** 32;
++
++   --  Address comparison
++
++   function "<"  (Left, Right : Address) return Boolean;
++   function "<=" (Left, Right : Address) return Boolean;
++   function ">"  (Left, Right : Address) return Boolean;
++   function ">=" (Left, Right : Address) return Boolean;
++   function "="  (Left, Right : Address) return Boolean;
++
++   pragma Import (Intrinsic, "<");
++   pragma Import (Intrinsic, "<=");
++   pragma Import (Intrinsic, ">");
++   pragma Import (Intrinsic, ">=");
++   pragma Import (Intrinsic, "=");
++
++   --  Other System-Dependent Declarations
++
++   type Bit_Order is (High_Order_First, Low_Order_First);
++   Default_Bit_Order : constant Bit_Order := High_Order_First;
++   pragma Warnings (Off, Default_Bit_Order); -- kill constant condition warning
++
++   --  Priority-related Declarations (RM D.1)
++
++   --  Is the following actually true for GNU/Linux/m68k?
++   --
++   --  0 .. 98 corresponds to the system priority range 1 .. 99.
++   --
++   --  If the scheduling policy is SCHED_FIFO or SCHED_RR the runtime makes use
++   --  of the entire range provided by the system.
++   --
++   --  If the scheduling policy is SCHED_OTHER the only valid system priority
++   --  is 1 and other values are simply ignored.
++
++   Max_Priority           : constant Positive := 97;
++   Max_Interrupt_Priority : constant Positive := 98;
++
++   subtype Any_Priority       is Integer      range  0 .. 98;
++   subtype Priority           is Any_Priority range  0 .. 97;
++   subtype Interrupt_Priority is Any_Priority range 98 .. 98;
++
++   Default_Priority : constant Priority := 48;
++
++private
++
++   type Address is mod Memory_Size;
++   Null_Address : constant Address := 0;
++
++   --------------------------------------
++   -- System Implementation Parameters --
++   --------------------------------------
++
++   --  These parameters provide information about the target that is used
++   --  by the compiler. They are in the private part of System, where they
++   --  can be accessed using the special circuitry in the Targparm unit
++   --  whose source should be consulted for more detailed descriptions
++   --  of the individual switch values.
++
++   Backend_Divide_Checks     : constant Boolean := False;
++   Backend_Overflow_Checks   : constant Boolean := False;
++   Command_Line_Args         : constant Boolean := True;
++   Configurable_Run_Time     : constant Boolean := False;
++   Denorm                    : constant Boolean := True;
++   Duration_32_Bits          : constant Boolean := False;
++   Exit_Status_Supported     : constant Boolean := True;
++   Fractional_Fixed_Ops      : constant Boolean := False;
++   Frontend_Layout           : constant Boolean := False;
++   Machine_Overflows         : constant Boolean := False;
++   Machine_Rounds            : constant Boolean := True;
++   Preallocated_Stacks       : constant Boolean := False;
++   Signed_Zeros              : constant Boolean := True;
++   Stack_Check_Default       : constant Boolean := False;
++   Stack_Check_Probes        : constant Boolean := False;
++   Stack_Check_Limits        : constant Boolean := False;
++   Support_Aggregates        : constant Boolean := True;
++   Support_Atomic_Primitives : constant Boolean := True;
++   Support_Composite_Assign  : constant Boolean := True;
++   Support_Composite_Compare : constant Boolean := True;
++   Support_Long_Shifts       : constant Boolean := True;
++   Always_Compatible_Rep     : constant Boolean := False;
++   Suppress_Standard_Library : constant Boolean := False;
++   Use_Ada_Main_Program_Name : constant Boolean := False;
++   ZCX_By_Default            : constant Boolean := True;
++
++end System;
--- gcc-6-6.3.0.orig/debian/patches/ada-mips.diff
+++ gcc-6-6.3.0/debian/patches/ada-mips.diff
@@ -0,0 +1,23 @@
+# DP: Improve support for mips.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -1878,10 +1878,15 @@ ifeq ($(strip $(filter-out mips linux%,$
+   s-taprop.adb<s-taprop-linux.adb \
+   s-tasinf.ads<s-tasinf-linux.ads \
+   s-tasinf.adb<s-tasinf-linux.adb \
+-  s-taspri.ads<s-taspri-posix.ads \
++  s-taspri.ads<s-taspri-posix-noaltstack.ads \
+   s-tpopsp.adb<s-tpopsp-posix-foreign.adb \
+   system.ads<system-linux-mips.ads
+ 
++  TOOLS_TARGET_PAIRS =  \
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
++    indepsw.adb<indepsw-gnu.adb
++
++  EXTRA_GNATRTL_TASKING_OBJS=s-linux.o
+   EH_MECHANISM=-gcc
+   THREADSLIB = -lpthread
+   GNATLIB_SHARED = gnatlib-shared-dual
--- gcc-6-6.3.0.orig/debian/patches/ada-nobiarch-check.diff
+++ gcc-6-6.3.0/debian/patches/ada-nobiarch-check.diff
@@ -0,0 +1,20 @@
+# DP: For biarch builds, disable the gnat testsuite for the non-default
+# architecture (no biarch support in gnat yet).
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -4510,7 +4510,11 @@
+ 	if [ -f $${rootme}/../expect/expect ] ; then  \
+ 	   TCL_LIBRARY=`cd .. ; cd $${srcdir}/../tcl/library ; ${PWD_COMMAND}` ; \
+ 	    export TCL_LIBRARY ; fi ; \
+-	$(RUNTEST) --tool $* $(RUNTESTFLAGS))
++	if [ "$*" = gnat ]; then \
++	  runtestflags="`echo '$(RUNTESTFLAGS)' | sed -r 's/,-m(32|64|x32)//g;s/,-mabi=(n32|64)//g'`"; \
++	  case "$$runtestflags" in *\\{\\}) runtestflags=; esac; \
++	fi; \
++	$(RUNTEST) --tool $* $$runtestflags)
+ 
+ $(patsubst %,%-subtargets,$(filter-out $(lang_checks_parallelized),$(lang_checks))): check-%-subtargets:
+ 	@echo check-$*
--- gcc-6-6.3.0.orig/debian/patches/ada-revert-pr63225.diff
+++ gcc-6-6.3.0/debian/patches/ada-revert-pr63225.diff
@@ -0,0 +1,97 @@
+# DP: Revert the changes made to allow bootstrapping with -fno-inline.
+# DP: We allow inlining during bootstrap and this change breaks aliversion compatibility
+# DP: with earlier uploads of libgnatvsn5.  This patch shall be removed in the next
+# DP: major version of GNAT.
+
+Index: b/src/gcc/ada/uintp.adb
+===================================================================
+--- a/src/gcc/ada/uintp.adb
++++ b/src/gcc/ada/uintp.adb
+@@ -171,6 +171,22 @@ package body Uintp is
+    --  If Discard_Quotient is True, Quotient is set to No_Uint
+    --  If Discard_Remainder is True, Remainder is set to No_Uint
+ 
++   function Vector_To_Uint
++     (In_Vec   : UI_Vector;
++      Negative : Boolean) return Uint;
++   --  Functions that calculate values in UI_Vectors, call this function to
++   --  create and return the Uint value. In_Vec contains the multiple precision
++   --  (Base) representation of a non-negative value. Leading zeroes are
++   --  permitted. Negative is set if the desired result is the negative of the
++   --  given value. The result will be either the appropriate directly
++   --  represented value, or a table entry in the proper canonical format is
++   --  created and returned.
++   --
++   --  Note that Init_Operand puts a signed value in the result vector, but
++   --  Vector_To_Uint is always presented with a non-negative value. The
++   --  processing of signs is something that is done by the caller before
++   --  calling Vector_To_Uint.
++
+    ------------
+    -- Direct --
+    ------------
+Index: b/src/gcc/ada/uintp.ads
+===================================================================
+--- a/src/gcc/ada/uintp.ads
++++ b/src/gcc/ada/uintp.ads
+@@ -90,18 +90,6 @@ package Uintp is
+    Uint_Minus_80  : constant Uint;
+    Uint_Minus_128 : constant Uint;
+ 
+-   type UI_Vector is array (Pos range <>) of Int;
+-   --  Vector containing the integer values of a Uint value
+-
+-   --  Note: An earlier version of this package used pointers of arrays of Ints
+-   --  (dynamically allocated) for the Uint type. The change leads to a few
+-   --  less natural idioms used throughout this code, but eliminates all uses
+-   --  of the heap except for the table package itself. For example, Uint
+-   --  parameters are often converted to UI_Vectors for internal manipulation.
+-   --  This is done by creating the local UI_Vector using the function N_Digits
+-   --  on the Uint to find the size needed for the vector, and then calling
+-   --  Init_Operand to copy the values out of the table into the vector.
+-
+    -----------------
+    -- Subprograms --
+    -----------------
+@@ -264,22 +252,6 @@ package Uintp is
+    --  function is used for capacity checks, and it can be one bit off
+    --  without affecting its usage.
+ 
+-   function Vector_To_Uint
+-     (In_Vec   : UI_Vector;
+-      Negative : Boolean) return Uint;
+-   --  Functions that calculate values in UI_Vectors, call this function to
+-   --  create and return the Uint value. In_Vec contains the multiple precision
+-   --  (Base) representation of a non-negative value. Leading zeroes are
+-   --  permitted. Negative is set if the desired result is the negative of the
+-   --  given value. The result will be either the appropriate directly
+-   --  represented value, or a table entry in the proper canonical format is
+-   --  created and returned.
+-   --
+-   --  Note that Init_Operand puts a signed value in the result vector, but
+-   --  Vector_To_Uint is always presented with a non-negative value. The
+-   --  processing of signs is something that is done by the caller before
+-   --  calling Vector_To_Uint.
+-
+    ---------------------
+    -- Output Routines --
+    ---------------------
+@@ -527,6 +499,18 @@ private
+    --  UI_Vector is defined for this purpose and some internal subprograms
+    --  used for converting from one to the other are defined.
+ 
++   type UI_Vector is array (Pos range <>) of Int;
++   --  Vector containing the integer values of a Uint value
++
++   --  Note: An earlier version of this package used pointers of arrays of Ints
++   --  (dynamically allocated) for the Uint type. The change leads to a few
++   --  less natural idioms used throughout this code, but eliminates all uses
++   --  of the heap except for the table package itself. For example, Uint
++   --  parameters are often converted to UI_Vectors for internal manipulation.
++   --  This is done by creating the local UI_Vector using the function N_Digits
++   --  on the Uint to find the size needed for the vector, and then calling
++   --  Init_Operand to copy the values out of the table into the vector.
++
+    type Uint_Entry is record
+       Length : Pos;
+       --  Length of entry in Udigits table in digits (i.e. in words)
--- gcc-6-6.3.0.orig/debian/patches/ada-s-osinte-gnu.ads.diff
+++ gcc-6-6.3.0/debian/patches/ada-s-osinte-gnu.ads.diff
@@ -0,0 +1,752 @@
+--- /dev/null	2012-01-30 20:41:15.189616186 +0100
++++ b/src/gcc/ada/s-osinte-gnu.ads	2012-04-11 19:34:45.000000000 +0200
+@@ -0,0 +1,749 @@
++------------------------------------------------------------------------------
++--                                                                          --
++--                GNU ADA RUN-TIME LIBRARY (GNARL) COMPONENTS               --
++--                                                                          --
++--                   S Y S T E M . O S _ I N T E R F A C E                  --
++--                                                                          --
++--                                  S p e c                                 --
++--                                                                          --
++--             Copyright (C) 1991-1994, Florida State University            --
++--          Copyright (C) 1995-2011, Free Software Foundation, Inc.         --
++--                                                                          --
++-- GNARL is free software; you can  redistribute it  and/or modify it under --
++-- terms of the  GNU General Public License as published  by the Free Soft- --
++-- ware  Foundation;  either version 2,  or (at your option) any later ver- --
++-- sion. GNARL is distributed in the hope that it will be useful, but WITH- --
++-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
++-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License --
++-- for  more details.  You should have  received  a copy of the GNU General --
++-- Public License  distributed with GNARL; see file COPYING.  If not, write --
++-- to  the  Free Software Foundation,  51  Franklin  Street,  Fifth  Floor, --
++-- Boston, MA 02110-1301, USA.                                              --
++--                                                                          --
++-- As a special exception,  if other files  instantiate  generics from this --
++-- unit, or you link  this unit with other files  to produce an executable, --
++-- this  unit  does not  by itself cause  the resulting  executable  to  be --
++-- covered  by the  GNU  General  Public  License.  This exception does not --
++-- however invalidate  any other reasons why  the executable file  might be --
++-- covered by the  GNU Public License.                                      --
++--                                                                          --
++-- GNARL was developed by the GNARL team at Florida State University.       --
++-- Extensive contributions were provided by Ada Core Technologies, Inc.     --
++--                                                                          --
++------------------------------------------------------------------------------
++
++--  This is the GNU/Hurd version of this package
++
++--  This package encapsulates all direct interfaces to OS services
++--  that are needed by children of System.
++
++--  PLEASE DO NOT add any with-clauses to this package or remove the pragma
++--  Preelaborate. This package is designed to be a bottom-level (leaf) package
++
++with Interfaces.C;
++with Unchecked_Conversion;
++
++package System.OS_Interface is
++   pragma Preelaborate;
++
++   pragma Linker_Options ("-lpthread");
++   pragma Linker_Options ("-lrt");
++
++   subtype int            is Interfaces.C.int;
++   subtype char           is Interfaces.C.char;
++   subtype short          is Interfaces.C.short;
++   subtype long           is Interfaces.C.long;
++   subtype unsigned       is Interfaces.C.unsigned;
++   subtype unsigned_short is Interfaces.C.unsigned_short;
++   subtype unsigned_long  is Interfaces.C.unsigned_long;
++   subtype unsigned_char  is Interfaces.C.unsigned_char;
++   subtype plain_char     is Interfaces.C.plain_char;
++   subtype size_t         is Interfaces.C.size_t;
++
++   -----------
++   -- Errno --
++   -----------
++   --  From /usr/include/i386-gnu/bits/errno.h
++
++   function errno return int;
++   pragma Import (C, errno, "__get_errno");
++
++   EAGAIN   : constant := 1073741859;
++   EINTR    : constant := 1073741828;
++   EINVAL   : constant := 1073741846;
++   ENOMEM   : constant := 1073741836;
++   EPERM    : constant := 1073741825;
++   ETIMEDOUT    : constant := 1073741884;
++
++   -------------
++   -- Signals --
++   -------------
++   --  From /usr/include/i386-gnu/bits/signum.h
++
++   Max_Interrupt : constant := 32;
++   type Signal is new int range 0 .. Max_Interrupt;
++   for Signal'Size use int'Size;
++
++   SIGHUP     : constant := 1; --  hangup
++   SIGINT     : constant := 2; --  interrupt (rubout)
++   SIGQUIT    : constant := 3; --  quit (ASCD FS)
++   SIGILL     : constant := 4; --  illegal instruction (not reset)
++   SIGTRAP    : constant := 5; --  trace trap (not reset)
++   SIGIOT     : constant := 6; --  IOT instruction
++   SIGABRT    : constant := 6; --  used by abort, replace SIGIOT in the  future
++   SIGEMT     : constant := 7; --  EMT instruction
++   SIGFPE     : constant := 8; --  floating point exception
++   SIGKILL    : constant := 9; --  kill (cannot be caught or ignored)
++   SIGBUS     : constant := 10; --  bus error
++   SIGSEGV    : constant := 11; --  segmentation violation
++   SIGSYS     : constant := 12; --  bad argument to system call
++   SIGPIPE    : constant := 13; --  write on a pipe with no one to read it
++   SIGALRM    : constant := 14; --  alarm clock
++   SIGTERM    : constant := 15; --  software termination signal from kill
++   SIGURG     : constant := 16; --  urgent condition on IO channel
++   SIGSTOP    : constant := 17; --  stop (cannot be caught or ignored)
++   SIGTSTP    : constant := 18; --  user stop requested from tty
++   SIGCONT    : constant := 19; --  stopped process has been continued
++   SIGCLD     : constant := 20; --  alias for SIGCHLD
++   SIGCHLD    : constant := 20; --  child status change
++   SIGTTIN    : constant := 21; --  background tty read attempted
++   SIGTTOU    : constant := 22; --  background tty write attempted
++   SIGIO      : constant := 23; --  I/O possible (Solaris SIGPOLL alias)
++   SIGPOLL    : constant := 23; --  I/O possible (same as SIGIO?)
++   SIGXCPU    : constant := 24; --  CPU time limit exceeded
++   SIGXFSZ    : constant := 25; --  filesize limit exceeded
++   SIGVTALRM  : constant := 26; --  virtual timer expired
++   SIGPROF    : constant := 27; --  profiling timer expired
++   SIGWINCH   : constant := 28; --  window size change
++   SIGINFO    : constant := 29; --  information request (NetBSD/FreeBSD)
++   SIGUSR1    : constant := 30; --  user defined signal 1
++   SIGUSR2    : constant := 31; --  user defined signal 2
++   SIGLOST    : constant := 32; --  Resource lost (Sun); server died (GNU)
++--   SIGLTHRRES : constant := 32; --  GNU/LinuxThreads restart signal
++--   SIGLTHRCAN : constant := 33; --  GNU/LinuxThreads cancel signal
++--   SIGLTHRDBG : constant := 34; --  GNU/LinuxThreads debugger signal
++
++   SIGADAABORT : constant := SIGABRT;
++   --  Change this if you want to use another signal for task abort.
++   --  SIGTERM might be a good one.
++
++   type Signal_Set is array (Natural range <>) of Signal;
++
++   Unmasked    : constant Signal_Set := (
++      SIGTRAP,
++      --  To enable debugging on multithreaded applications, mark SIGTRAP to
++      --  be kept unmasked.
++
++      SIGBUS,
++
++      SIGTTIN, SIGTTOU, SIGTSTP,
++      --  Keep these three signals unmasked so that background processes
++      --  and IO behaves as normal "C" applications
++
++      SIGPROF,
++      --  To avoid confusing the profiler
++
++      SIGKILL, SIGSTOP);
++      --  These two signals actually cannot be masked;
++      --  POSIX simply won't allow it.
++
++   Reserved    : constant Signal_Set :=
++   --  I am not sure why the following signal is reserved.
++   --  I guess they are not supported by this version of GNU/Hurd.
++     (0 .. 0 => SIGVTALRM);
++
++   type sigset_t is private;
++
++   --  From /usr/include/signal.h /usr/include/i386-gnu/bits/sigset.h
++   function sigaddset (set : access sigset_t; sig : Signal) return int;
++   pragma Import (C, sigaddset, "sigaddset");
++
++   function sigdelset (set : access sigset_t; sig : Signal) return int;
++   pragma Import (C, sigdelset, "sigdelset");
++
++   function sigfillset (set : access sigset_t) return int;
++   pragma Import (C, sigfillset, "sigfillset");
++
++   function sigismember (set : access sigset_t; sig : Signal) return int;
++   pragma Import (C, sigismember, "sigismember");
++
++   function sigemptyset (set : access sigset_t) return int;
++   pragma Import (C, sigemptyset, "sigemptyset");
++
++   --  sigcontext is architecture dependent, so define it private
++   type struct_sigcontext is private;
++
++   --  From /usr/include/i386-gnu/bits/sigaction.h: Note: arg. order differs
++   type struct_sigaction is record
++      sa_handler : System.Address;
++      sa_mask    : sigset_t;
++      sa_flags   : int;
++   end record;
++   pragma Convention (C, struct_sigaction);
++
++   type struct_sigaction_ptr is access all struct_sigaction;
++
++   --  From /usr/include/i386-gnu/bits/sigaction.h
++   SIG_BLOCK   : constant := 1;
++   SIG_UNBLOCK : constant := 2;
++   SIG_SETMASK : constant := 3;
++
++   --  From /usr/include/i386-gnu/bits/signum.h
++   SIG_ERR  : constant := 1;
++   SIG_DFL  : constant := 0;
++   SIG_IGN  : constant := 1;
++   SIG_HOLD : constant := 2;
++
++   --  From /usr/include/i386-gnu/bits/sigaction.h
++   SA_SIGINFO : constant := 16#0040#;
++   SA_ONSTACK : constant := 16#0001#;
++
++   function sigaction
++     (sig  : Signal;
++      act  : struct_sigaction_ptr;
++      oact : struct_sigaction_ptr) return int;
++   pragma Import (C, sigaction, "sigaction");
++
++   ----------
++   -- Time --
++   ----------
++
++   Time_Slice_Supported : constant Boolean := True;
++   --  Indicates whether time slicing is supported (i.e SCHED_RR is supported)
++
++   type timespec is private;
++
++   function nanosleep (rqtp, rmtp : access timespec) return int;
++   pragma Import (C, nanosleep, "nanosleep");
++
++   type clockid_t is private;
++
++   CLOCK_REALTIME : constant clockid_t;
++
++   --  From: /usr/include/time.h
++   function clock_gettime
++     (clock_id : clockid_t;
++      tp       : access timespec)
++      return int;
++   pragma Import (C, clock_gettime, "clock_gettime");
++
++   function To_Duration (TS : timespec) return Duration;
++   pragma Inline (To_Duration);
++
++   function To_Timespec (D : Duration) return timespec;
++   pragma Inline (To_Timespec);
++
++   --  From: /usr/include/unistd.h
++   function sysconf (name : int) return long;
++   pragma Import (C, sysconf);
++
++   --  From /usr/include/i386-gnu/bits/confname.h
++   SC_CLK_TCK          : constant := 2;
++   SC_NPROCESSORS_ONLN : constant := 84;
++
++   -------------------------
++   -- Priority Scheduling --
++   -------------------------
++   --  From /usr/include/i386-gnu/bits/sched.h
++
++   SCHED_OTHER : constant := 0;
++   SCHED_FIFO  : constant := 1;
++   SCHED_RR    : constant := 2;
++
++   function To_Target_Priority
++     (Prio : System.Any_Priority) return Interfaces.C.int;
++   --  Maps System.Any_Priority to a POSIX priority.
++
++   -------------
++   -- Process --
++   -------------
++
++   type pid_t is private;
++
++   --  From: /usr/include/signal.h
++   function kill (pid : pid_t; sig : Signal) return int;
++   pragma Import (C, kill, "kill");
++
++   --  From: /usr/include/unistd.h
++   function getpid return pid_t;
++   pragma Import (C, getpid, "getpid");
++
++   ---------
++   -- LWP --
++   ---------
++
++   --  From: /usr/include/pthread/pthread.h
++   function lwp_self return System.Address;
++   --  lwp_self does not exist on this thread library, revert to pthread_self
++   --  which is the closest approximation (with getpid). This function is
++   --  needed to share 7staprop.adb across POSIX-like targets.
++   pragma Import (C, lwp_self, "pthread_self");
++
++   -------------
++   -- Threads --
++   -------------
++
++   type Thread_Body is access
++     function (arg : System.Address) return System.Address;
++   pragma Convention (C, Thread_Body);
++
++   function Thread_Body_Access is new
++     Unchecked_Conversion (System.Address, Thread_Body);
++
++   --  From: /usr/include/bits/pthread.h:typedef int __pthread_t;
++   --  /usr/include/pthread/pthreadtypes.h:typedef __pthread_t pthread_t;
++   type pthread_t is new unsigned_long;
++   subtype Thread_Id        is pthread_t;
++
++   function To_pthread_t is new Unchecked_Conversion
++     (unsigned_long, pthread_t);
++
++   type pthread_mutex_t     is limited private;
++   type pthread_cond_t      is limited private;
++   type pthread_attr_t      is limited private;
++   type pthread_mutexattr_t is limited private;
++   type pthread_condattr_t  is limited private;
++   type pthread_key_t       is private;
++
++   --  From /usr/include/pthread/pthreadtypes.h
++   PTHREAD_CREATE_DETACHED : constant := 1;
++   PTHREAD_CREATE_JOINABLE : constant := 0;
++
++   PTHREAD_SCOPE_PROCESS : constant := 1;
++   PTHREAD_SCOPE_SYSTEM  : constant := 0;
++
++   -----------
++   -- Stack --
++   -----------
++
++   --  From: /usr/include/i386-gnu/bits/sigstack.h
++   type stack_t is record
++      ss_sp    : System.Address;
++      ss_size  : size_t;
++      ss_flags : int;
++   end record;
++   pragma Convention (C, stack_t);
++
++   function sigaltstack
++     (ss  : not null access stack_t;
++      oss : access stack_t) return int;
++   pragma Import (C, sigaltstack, "sigaltstack");
++
++   Alternate_Stack : aliased System.Address;
++   --  This is a dummy definition, never used (Alternate_Stack_Size is null)
++
++   Alternate_Stack_Size : constant := 0;
++   --  No alternate signal stack is used on this platform
++
++   Stack_Base_Available : constant Boolean := False;
++   --  Indicates whether the stack base is available on this target
++
++   function Get_Stack_Base (thread : pthread_t) return Address;
++   pragma Inline (Get_Stack_Base);
++   --  returns the stack base of the specified thread. Only call this function
++   --  when Stack_Base_Available is True.
++
++   --  From: /usr/include/unistd.h __getpagesize or getpagesize??
++   function Get_Page_Size return int;
++   pragma Import (C, Get_Page_Size, "__getpagesize");
++   --  Returns the size of a page
++
++   --  From /usr/include/i386-gnu/bits/mman.h
++   PROT_NONE  : constant := 0;
++   PROT_READ  : constant := 4;
++   PROT_WRITE : constant := 2;
++   PROT_EXEC  : constant := 1;
++   PROT_ALL   : constant := PROT_READ + PROT_WRITE + PROT_EXEC;
++   PROT_ON    : constant := PROT_NONE;
++   PROT_OFF   : constant := PROT_ALL;
++
++   --  From /usr/include/i386-gnu/bits/mman.h
++   function mprotect (addr : Address; len : size_t; prot : int) return int;
++   pragma Import (C, mprotect);
++
++   ---------------------------------------
++   -- Nonstandard Thread Initialization --
++   ---------------------------------------
++
++   procedure pthread_init;
++   pragma Inline (pthread_init);
++   --  This is a dummy procedure to share some GNULLI files
++
++   -------------------------
++   -- POSIX.1c  Section 3 --
++   -------------------------
++
++   --  From: /usr/include/signal.h:
++   --  sigwait (__const sigset_t *__restrict __set, int *__restrict __sig)
++   function sigwait (set : access sigset_t; sig : access Signal) return int;
++   pragma Import (C, sigwait, "sigwait");
++
++   --  From: /usr/include/pthread/pthread.h:
++   --  extern int pthread_kill (pthread_t thread, int signo);
++   function pthread_kill (thread : pthread_t; sig : Signal) return int;
++   pragma Import (C, pthread_kill, "pthread_kill");
++
++   --  From: /usr/include/i386-gnu/bits/sigthread.h
++   --  extern int pthread_sigmask (int __how, __const __sigset_t *__newmask,
++   --  __sigset_t *__oldmask) __THROW;
++   function pthread_sigmask
++     (how  : int;
++      set  : access sigset_t;
++      oset : access sigset_t) return int;
++   pragma Import (C, pthread_sigmask, "pthread_sigmask");
++
++   --------------------------
++   -- POSIX.1c  Section 11 --
++   --------------------------
++
++   --  From: /usr/include/pthread/pthread.h and
++   --  /usr/include/pthread/pthreadtypes.h
++   function pthread_mutexattr_init
++     (attr : access pthread_mutexattr_t) return int;
++   pragma Import (C, pthread_mutexattr_init, "pthread_mutexattr_init");
++
++   function pthread_mutexattr_destroy
++     (attr : access pthread_mutexattr_t) return int;
++   pragma Import (C, pthread_mutexattr_destroy, "pthread_mutexattr_destroy");
++
++   function pthread_mutex_init
++     (mutex : access pthread_mutex_t;
++      attr  : access pthread_mutexattr_t) return int;
++   pragma Import (C, pthread_mutex_init, "pthread_mutex_init");
++
++   function pthread_mutex_destroy (mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_mutex_destroy, "pthread_mutex_destroy");
++
++   function pthread_mutex_lock (mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_mutex_lock, "pthread_mutex_lock");
++
++   function pthread_mutex_unlock (mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_mutex_unlock, "pthread_mutex_unlock");
++
++   function pthread_condattr_init
++     (attr : access pthread_condattr_t) return int;
++   pragma Import (C, pthread_condattr_init, "pthread_condattr_init");
++
++   function pthread_condattr_destroy
++     (attr : access pthread_condattr_t) return int;
++   pragma Import (C, pthread_condattr_destroy, "pthread_condattr_destroy");
++
++   function pthread_cond_init
++     (cond : access pthread_cond_t;
++      attr : access pthread_condattr_t) return int;
++   pragma Import (C, pthread_cond_init, "pthread_cond_init");
++
++   function pthread_cond_destroy (cond : access pthread_cond_t) return int;
++   pragma Import (C, pthread_cond_destroy, "pthread_cond_destroy");
++
++   function pthread_cond_signal (cond : access pthread_cond_t) return int;
++   pragma Import (C, pthread_cond_signal, "pthread_cond_signal");
++
++   function pthread_cond_wait
++     (cond  : access pthread_cond_t;
++      mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_cond_wait, "pthread_cond_wait");
++
++   function pthread_cond_timedwait
++     (cond    : access pthread_cond_t;
++      mutex   : access pthread_mutex_t;
++      abstime : access timespec) return int;
++   pragma Import (C, pthread_cond_timedwait, "pthread_cond_timedwait");
++
++   Relative_Timed_Wait : constant Boolean := False;
++   --  pthread_cond_timedwait requires an absolute delay time
++
++   --------------------------
++   -- POSIX.1c  Section 13 --
++   --------------------------
++   --  From /usr/include/pthread/pthreadtypes.h
++
++   PTHREAD_PRIO_NONE    : constant := 0;
++   PTHREAD_PRIO_PROTECT : constant := 2;
++   PTHREAD_PRIO_INHERIT : constant := 1;
++
++   --  From: /usr/include/pthread/pthread.h
++   function pthread_mutexattr_setprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : int) return int;
++   pragma Import (C, pthread_mutexattr_setprotocol,
++     "pthread_mutexattr_setprotocol");
++
++   function pthread_mutexattr_getprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : access int) return int;
++   pragma Import (C, pthread_mutexattr_getprotocol,
++     "pthread_mutexattr_getprotocol");
++
++   function pthread_mutexattr_setprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : int) return int;
++   pragma Import (C, pthread_mutexattr_setprioceiling,
++     "pthread_mutexattr_setprioceiling");
++
++   function pthread_mutexattr_getprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : access int) return int;
++   pragma Import (C, pthread_mutexattr_getprioceiling,
++     "pthread_mutexattr_getprioceiling");
++
++   type struct_sched_param is record
++      sched_priority : int;  --  scheduling priority
++   end record;
++   pragma Convention (C, struct_sched_param);
++
++   function pthread_setschedparam
++     (thread : pthread_t;
++      policy : int;
++      param  : access struct_sched_param) return int;
++   pragma Import (C, pthread_setschedparam, "pthread_setschedparam");
++
++   function pthread_attr_setscope
++     (attr            : access pthread_attr_t;
++      contentionscope : int) return int;
++   pragma Import (C, pthread_attr_setscope, "pthread_attr_setscope");
++
++   function pthread_attr_getscope
++     (attr            : access pthread_attr_t;
++      contentionscope : access int) return int;
++   pragma Import (C, pthread_attr_getscope, "pthread_attr_getscope");
++
++   function pthread_attr_setinheritsched
++     (attr            : access pthread_attr_t;
++      inheritsched : int) return int;
++   pragma Import (C, pthread_attr_setinheritsched,
++     "pthread_attr_setinheritsched");
++
++   function pthread_attr_getinheritsched
++     (attr         : access pthread_attr_t;
++      inheritsched : access int) return int;
++   pragma Import (C, pthread_attr_getinheritsched,
++     "pthread_attr_getinheritsched");
++
++   function pthread_attr_setschedpolicy
++     (attr   : access pthread_attr_t;
++      policy : int) return int;
++   pragma Import (C, pthread_attr_setschedpolicy, "pthread_setschedpolicy");
++
++   function sched_yield return int;
++   pragma Import (C, sched_yield, "sched_yield");
++
++   ---------------------------
++   -- P1003.1c - Section 16 --
++   ---------------------------
++
++   function pthread_attr_init
++     (attributes : access pthread_attr_t) return int;
++   pragma Import (C, pthread_attr_init, "pthread_attr_init");
++
++   function pthread_attr_destroy
++     (attributes : access pthread_attr_t) return int;
++   pragma Import (C, pthread_attr_destroy, "pthread_attr_destroy");
++
++   function pthread_attr_setdetachstate
++     (attr        : access pthread_attr_t;
++      detachstate : int) return int;
++   pragma Import
++     (C, pthread_attr_setdetachstate, "pthread_attr_setdetachstate");
++
++   function pthread_attr_setstacksize
++     (attr      : access pthread_attr_t;
++      stacksize : size_t) return int;
++   pragma Import (C, pthread_attr_setstacksize, "pthread_attr_setstacksize");
++
++   --  From: /usr/include/pthread/pthread.h
++   function pthread_create
++     (thread        : access pthread_t;
++      attributes    : access pthread_attr_t;
++      start_routine : Thread_Body;
++      arg           : System.Address) return int;
++   pragma Import (C, pthread_create, "pthread_create");
++
++   procedure pthread_exit (status : System.Address);
++   pragma Import (C, pthread_exit, "pthread_exit");
++
++   function pthread_self return pthread_t;
++   pragma Import (C, pthread_self, "pthread_self");
++
++   --------------------------
++   -- POSIX.1c  Section 17 --
++   --------------------------
++
++   function pthread_setspecific
++     (key   : pthread_key_t;
++      value : System.Address) return int;
++   pragma Import (C, pthread_setspecific, "pthread_setspecific");
++
++   function pthread_getspecific (key : pthread_key_t) return System.Address;
++   pragma Import (C, pthread_getspecific, "pthread_getspecific");
++
++   type destructor_pointer is access procedure (arg : System.Address);
++   pragma Convention (C, destructor_pointer);
++
++   function pthread_key_create
++     (key        : access pthread_key_t;
++      destructor : destructor_pointer) return int;
++   pragma Import (C, pthread_key_create, "pthread_key_create");
++
++   --  From /usr/include/i386-gnu/bits/sched.h
++   --  1_024 == 1024??
++   CPU_SETSIZE : constant := 1_024;
++
++   type bit_field is array (1 .. CPU_SETSIZE) of Boolean;
++   for bit_field'Size use CPU_SETSIZE;
++   pragma Pack (bit_field);
++   pragma Convention (C, bit_field);
++
++   type cpu_set_t is record
++      bits : bit_field;
++   end record;
++   pragma Convention (C, cpu_set_t);
++
++   --  function pthread_setaffinity_np
++   --  (thread     : pthread_t;
++   --   cpusetsize : size_t;
++   --   cpuset     : access cpu_set_t) return int;
++   --   pragma Import (C, pthread_setaffinity_np,
++   --   "__gnat_pthread_setaffinity_np");
++
++private
++
++   type sigset_t is array (1 .. 4) of unsigned;
++
++   --  FIXME:
++   --  In GNU/Hurd the component sa_handler turns out to
++   --  be one a union type, and the selector is a macro:
++   --  #define sa_handler __sigaction_handler.sa_handler
++   --  #define sa_sigaction __sigaction_handler.sa_sigaction
++
++   --  In FreeBSD the component sa_handler turns out to
++   --  be one a union type, and the selector is a macro:
++   --  #define sa_handler __sigaction_u._handler
++   --  #define sa_sigaction __sigaction_u._sigaction
++
++   --  Should we add a signal_context type here ?
++   --  How could it be done independent of the CPU architecture ?
++   --  sigcontext type is opaque, so it is architecturally neutral.
++   --  It is always passed as an access type, so define it as an empty record
++   --  since the contents are not used anywhere.
++   type struct_sigcontext is null record;
++   pragma Convention (C, struct_sigcontext);
++
++   type pid_t is new int;
++
++   type time_t is new long;
++
++   type timespec is record
++      tv_sec  : time_t;
++      tv_nsec : long;
++   end record;
++   pragma Convention (C, timespec);
++
++   type clockid_t is new int;
++   CLOCK_REALTIME : constant clockid_t := 0;
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_attr pthread_attr_t;
++   --  /usr/include/bits/thread-attr.h: struct __pthread_attr...
++   --  /usr/include/pthread/pthreadtypes.h: enum __pthread_contentionscope
++   --   enum __pthread_detachstate detachstate;
++   --   enum __pthread_inheritsched inheritsched;
++   --   enum __pthread_contentionscope contentionscope;
++   --   Not used: schedpolicy   : int;
++   type pthread_attr_t is record
++      schedparam    : struct_sched_param;
++      stackaddr     : System.Address;
++      stacksize     : size_t;
++      guardsize     : size_t;
++      detachstate   : int;
++      inheritsched  : int;
++      contentionscope : int;
++      schedpolicy   : int;
++   end record;
++   pragma Convention (C, pthread_attr_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_condattr pthread_condattr_t;
++   --  From: /usr/include/bits/condition-attr.h:
++   --  struct __pthread_condattr {
++   --    enum __pthread_process_shared pshared;
++   --    __Clockid_T Clock;}
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  enum __pthread_process_shared
++   type pthread_condattr_t is record
++      pshared : int;
++      clock   : clockid_t;
++   end record;
++   pragma Convention (C, pthread_condattr_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_mutexattr pthread_mutexattr_t; and
++   --  /usr/include/bits/mutex-attr.h
++   --  struct __pthread_mutexattr {
++   --  Int Prioceiling;
++   --  Enum __Pthread_Mutex_Protocol Protocol;
++   --  Enum __Pthread_Process_Shared Pshared;
++   --  Enum __Pthread_Mutex_Type Mutex_Type;};
++   type pthread_mutexattr_t is record
++      prioceiling : int;
++      protocol    : int;
++      pshared     : int;
++      mutex_type  : int;
++   end record;
++   pragma Convention (C, pthread_mutexattr_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h
++   --  typedef struct __pthread_mutex pthread_mutex_t; and
++   --  /usr/include/bits/mutex.h:
++   --  struct __pthread_mutex {
++   --  __pthread_spinlock_t __held;
++   --  __pthread_spinlock_t __lock;
++   --  /* in cthreads, mutex_init does not initialized the third
++   --    pointer, as such, we cannot rely on its value for anything.  */
++   --    char *cthreadscompat1;
++   --  struct __pthread *__queue;
++   --  struct __pthread_mutexattr *attr;
++   --  void *data;
++   --  /*  up to this point, we are completely compatible with cthreads
++   --    and what libc expects.  */
++   --    void *owner;
++   --  unsigned locks;
++   --  /* if null then the default attributes apply.  */
++   --    };
++   type pthread_mutex_t is record
++      held          : int;
++      lock          : int;
++      cthreadcompat : System.Address;
++      queue         : System.Address;
++      attr          : System.Address;
++      data          : System.Address;
++      owner         : System.Address;
++      locks         : unsigned;
++   end record;
++   pragma Convention (C, pthread_mutex_t);
++   --  pointer needed?
++   --  type pthread_mutex_t_ptr is access pthread_mutex_t;
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_cond pthread_cond_t;
++   --  typedef struct __pthread_condattr pthread_condattr_t;
++   --  /usr/include/bits/condition.h:struct __pthread_cond{}
++   --  pthread_condattr_t: see above!
++   --  /usr/include/bits/condition.h:    struct __pthread_condimpl *__impl;
++
++   type pthread_cond_t is record
++      lock       : int;
++      queue      : System.Address;
++      condattr   : System.Address;
++      impl       : System.Address;
++      data       : System.Address;
++   end record;
++   pragma Convention (C, pthread_cond_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef __pthread_key pthread_key_t; and
++   --  /usr/include/bits/thread-specific.h:
++   --  typedef int __pthread_key;
++   type pthread_key_t is new int;
++
++end System.OS_Interface;
--- gcc-6-6.3.0.orig/debian/patches/ada-sjlj.diff
+++ gcc-6-6.3.0/debian/patches/ada-sjlj.diff
@@ -0,0 +1,1034 @@
+Index: b/src/libada-sjlj/Makefile.in
+===================================================================
+--- /dev/null
++++ b/src/libada-sjlj/Makefile.in
+@@ -0,0 +1,201 @@
++# Makefile for libada.
++#   Copyright (C) 2003-2015 Free Software Foundation, Inc.
++#
++# This file is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++# 
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++# 
++# You should have received a copy of the GNU General Public License
++# along with this program; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++# Default target; must be first.
++all: gnatlib
++	$(MULTIDO) $(AM_MAKEFLAGS) DO=all multi-do # $(MAKE)
++
++.PHONY: all
++
++## Multilib support variables.
++MULTISRCTOP =
++MULTIBUILDTOP =
++MULTIDIRS =
++MULTISUBDIR =
++MULTIDO = true
++MULTICLEAN = true
++
++# Standard autoconf-set variables.
++SHELL = @SHELL@
++srcdir = @srcdir@
++libdir = @libdir@
++build = @build@
++target = @target@
++prefix = @prefix@
++
++# Nonstandard autoconf-set variables.
++enable_shared = @enable_shared@
++
++LN_S=@LN_S@
++AWK=@AWK@
++
++ifeq (cp -p,$(LN_S))
++LN_S_RECURSIVE = cp -pR
++else
++LN_S_RECURSIVE = $(LN_S)
++endif
++
++# Variables for the user (or the top level) to override.
++objext=.o
++THREAD_KIND=native
++TRACE=no
++LDFLAGS=
++
++# The tedious process of getting CFLAGS right.
++CFLAGS=-g
++PICFLAG = @PICFLAG@
++GNATLIBFLAGS= -W -Wall -gnatpg -nostdinc
++GNATLIBCFLAGS= -g -O2
++GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) \
++	-fexceptions -DIN_RTS @have_getipinfo@
++
++host_subdir = @host_subdir@
++GCC_DIR=$(MULTIBUILDTOP)../../$(host_subdir)/gcc
++
++target_noncanonical:=@target_noncanonical@
++version := $(shell cat $(srcdir)/../gcc/BASE-VER)
++libsubdir := $(libdir)/gcc/$(target_noncanonical)/$(version)$(MULTISUBDIR)
++ADA_RTS_DIR=$(GCC_DIR)/ada/rts$(subst /,_,$(MULTISUBDIR))
++ADA_RTS_SUBDIR=./rts$(subst /,_,$(MULTISUBDIR))
++
++# exeext should not be used because it's the *host* exeext.  We're building
++# a *target* library, aren't we?!?  Likewise for CC.  Still, provide bogus
++# definitions just in case something slips through the safety net provided
++# by recursive make invocations in gcc/ada/Makefile.in
++LIBADA_FLAGS_TO_PASS = \
++        "MAKEOVERRIDES=" \
++        "LDFLAGS=$(LDFLAGS)" \
++        "LN_S=$(LN_S)" \
++        "SHELL=$(SHELL)" \
++        "GNATLIBFLAGS=$(GNATLIBFLAGS) $(MULTIFLAGS)" \
++        "GNATLIBCFLAGS=$(GNATLIBCFLAGS) $(MULTIFLAGS)" \
++        "GNATLIBCFLAGS_FOR_C=$(GNATLIBCFLAGS_FOR_C) $(MULTIFLAGS)" \
++        "PICFLAG_FOR_TARGET=$(PICFLAG)" \
++        "THREAD_KIND=$(THREAD_KIND)" \
++        "TRACE=$(TRACE)" \
++        "MULTISUBDIR=$(MULTISUBDIR)" \
++        "libsubdir=$(libsubdir)" \
++        "objext=$(objext)" \
++        "prefix=$(prefix)" \
++        "exeext=.exeext.should.not.be.used " \
++	'CC=the.host.compiler.should.not.be.needed' \
++	"GCC_FOR_TARGET=$(CC)" \
++        "CFLAGS=$(CFLAGS)" \
++	"RTSDIR=rts-sjlj"
++
++# Rules to build gnatlib.
++.PHONY: gnatlib gnatlib-plain gnatlib-sjlj gnatlib-zcx gnatlib-shared osconstool
++gnatlib: gnatlib-sjlj
++
++gnatlib-plain: osconstool $(GCC_DIR)/ada/Makefile
++	test -f stamp-libada || \
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) gnatlib \
++	&& touch stamp-libada
++	-rm -rf adainclude
++	-rm -rf adalib
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adainclude
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adalib
++
++gnatlib-sjlj gnatlib-zcx gnatlib-shared: osconstool $(GCC_DIR)/ada/Makefile
++	test -f stamp-libada || \
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) $@ \
++	&& touch stamp-libada-sjlj
++	-rm -rf adainclude
++	-rm -rf adalib
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adainclude
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adalib
++
++osconstool:
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) ./bldtools/oscons/xoscons
++
++install-gnatlib: $(GCC_DIR)/ada/Makefile
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) install-gnatlib-sjlj
++
++# Check uninstalled version.
++check:
++
++# Check installed version.
++installcheck:
++
++# Build info (none here).
++info:
++
++# Build DVI (none here).
++dvi:
++
++# Build PDF (none here).
++pdf:
++
++# Build html (none here).
++html:
++
++# Build TAGS (none here).
++TAGS:
++
++.PHONY: check installcheck info dvi pdf html
++
++# Installation rules.
++install: install-gnatlib
++	$(MULTIDO) $(AM_MAKEFLAGS) DO=install multi-do # $(MAKE)
++
++install-strip: install
++
++install-info:
++
++install-pdf:
++
++install-html:
++
++.PHONY: install install-strip install-info install-pdf install-html
++
++# Cleaning rules.
++mostlyclean:
++	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=mostlyclean multi-clean # $(MAKE)
++
++clean:
++	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=clean multi-clean # $(MAKE)
++
++distclean:
++	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=distclean multi-clean # $(MAKE)
++	$(RM) Makefile config.status config.log
++
++maintainer-clean:
++
++.PHONY: mostlyclean clean distclean maintainer-clean
++
++# Rules for rebuilding this Makefile.
++Makefile: $(srcdir)/Makefile.in config.status
++	CONFIG_FILES=$@ ; \
++	CONFIG_HEADERS= ; \
++	$(SHELL) ./config.status
++
++config.status: $(srcdir)/configure
++	$(SHELL) ./config.status --recheck
++
++AUTOCONF = autoconf
++configure_deps = \
++	$(srcdir)/configure.ac \
++	$(srcdir)/../config/acx.m4 \
++	$(srcdir)/../config/override.m4 \
++	$(srcdir)/../config/multi.m4
++
++$(srcdir)/configure: @MAINT@ $(configure_deps)
++	cd $(srcdir) && $(AUTOCONF)
++
++# Don't export variables to the environment, in order to not confuse
++# configure.
++.NOEXPORT:
+Index: b/src/libada-sjlj/configure.ac
+===================================================================
+--- /dev/null
++++ b/src/libada-sjlj/configure.ac
+@@ -0,0 +1,140 @@
++# Configure script for libada.
++#   Copyright (C) 2003-2015 Free Software Foundation, Inc.
++#
++# This file is free software; you can redistribute it and/or modify it
++# under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful, but
++# WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++# General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++sinclude(../config/acx.m4)
++sinclude(../config/multi.m4)
++sinclude(../config/override.m4)
++sinclude(../config/picflag.m4)
++sinclude(../config/unwind_ipinfo.m4)
++
++AC_INIT
++AC_PREREQ([2.64])
++
++AC_CONFIG_SRCDIR([Makefile.in])
++
++# Determine the host, build, and target systems
++AC_CANONICAL_BUILD
++AC_CANONICAL_HOST
++AC_CANONICAL_TARGET
++target_alias=${target_alias-$host_alias}
++
++# Determine the noncanonical target name, for directory use.
++ACX_NONCANONICAL_TARGET
++
++# Determine the target- and build-specific subdirectories
++GCC_TOPLEV_SUBDIRS
++
++# Command-line options.
++# Very limited version of AC_MAINTAINER_MODE.
++AC_ARG_ENABLE([maintainer-mode],
++  [AC_HELP_STRING([--enable-maintainer-mode],
++                 [enable make rules and dependencies not useful (and
++                  sometimes confusing) to the casual installer])],
++  [case ${enable_maintainer_mode} in
++     yes) MAINT='' ;;
++     no) MAINT='#' ;;
++     *) AC_MSG_ERROR([--enable-maintainer-mode must be yes or no]) ;;
++   esac
++   maintainer_mode=${enableval}],
++  [MAINT='#'])
++AC_SUBST([MAINT])dnl
++
++AM_ENABLE_MULTILIB(, ..)
++# Calculate toolexeclibdir
++# Also toolexecdir, though it's only used in toolexeclibdir
++case ${enable_version_specific_runtime_libs} in
++  yes)
++    # Need the gcc compiler version to know where to install libraries
++    # and header files if --enable-version-specific-runtime-libs option
++    # is selected.
++    toolexecdir='$(libdir)/gcc/$(target_alias)'
++    toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)'
++    ;;
++  no)
++    if test -n "$with_cross_host" &&
++       test x"$with_cross_host" != x"no"; then
++      # Install a library built with a cross compiler in tooldir, not libdir.
++      toolexecdir='$(exec_prefix)/$(target_alias)'
++      toolexeclibdir='$(toolexecdir)/lib'
++    else
++      toolexecdir='$(libdir)/gcc-lib/$(target_alias)'
++      toolexeclibdir='$(libdir)'
++    fi
++    multi_os_directory=`$CC -print-multi-os-directory`
++    case $multi_os_directory in
++      .) ;; # Avoid trailing /.
++      *) toolexeclibdir=$toolexeclibdir/$multi_os_directory ;;
++    esac
++    ;;
++esac
++AC_SUBST(toolexecdir)
++AC_SUBST(toolexeclibdir)
++#TODO: toolexeclibdir is currently disregarded
++
++# Check the compiler.
++# The same as in boehm-gc and libstdc++. Have to borrow it from there.
++# We must force CC to /not/ be precious variables; otherwise
++# the wrong, non-multilib-adjusted value will be used in multilibs.
++# As a side effect, we have to subst CFLAGS ourselves.
++
++m4_rename([_AC_ARG_VAR_PRECIOUS],[real_PRECIOUS])
++m4_define([_AC_ARG_VAR_PRECIOUS],[])
++AC_PROG_CC
++m4_rename_force([real_PRECIOUS],[_AC_ARG_VAR_PRECIOUS])
++
++AC_SUBST(CFLAGS)
++
++AC_ARG_ENABLE([shared],
++[AC_HELP_STRING([--disable-shared],
++                [don't provide a shared libgnat])],
++[
++case $enable_shared in
++  yes | no) ;;
++  *)
++    enable_shared=no
++    IFS="${IFS=         }"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
++    for pkg in $enableval; do
++      case $pkg in
++        ada | libada)
++          enable_shared=yes ;;
++      esac
++    done
++    IFS="$ac_save_ifs"
++    ;;
++esac
++], [enable_shared=yes])
++AC_SUBST([enable_shared])
++
++GCC_PICFLAG
++AC_SUBST([PICFLAG])
++
++# These must be passed down, or are needed by gcc/libgcc.mvars
++AC_PROG_AWK
++AC_PROG_LN_S
++
++# Check for _Unwind_GetIPInfo
++GCC_CHECK_UNWIND_GETIPINFO
++have_getipinfo=
++if test x$have_unwind_getipinfo = xyes; then
++  have_getipinfo=-DHAVE_GETIPINFO
++fi
++AC_SUBST(have_getipinfo)
++
++# Output: create a Makefile.
++AC_CONFIG_FILES([Makefile])
++
++AC_OUTPUT
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -183,6 +183,13 @@ target_modules = { module= libada; no_in
+ 		   missing= TAGS;
+ 		   missing= install-info;
+ 		   missing= installcheck; };
++target_modules = { module= libada-sjlj; no_install=true; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgnatvsn; no_check=true;
+ 		   missing= info;
+ 		   missing= dvi;
+@@ -394,6 +401,7 @@ dependencies = { module=all-libcpp; on=a
+ dependencies = { module=all-fixincludes; on=all-libiberty; };
+ 
+ dependencies = { module=all-target-libada; on=all-gcc; };
++dependencies = { module=all-target-libada-sjlj; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libgnatvsn; };
+ dependencies = { module=all-gnattools; on=all-target-libgnatprj; };
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -976,6 +976,7 @@ configure-target:  \
+     maybe-configure-target-boehm-gc \
+     maybe-configure-target-rda \
+     maybe-configure-target-libada \
++    maybe-configure-target-libada-sjlj \
+     maybe-configure-target-libgnatvsn \
+     maybe-configure-target-libgnatprj \
+     maybe-configure-target-libgomp \
+@@ -1146,6 +1147,7 @@ all-target: maybe-all-target-zlib
+ all-target: maybe-all-target-boehm-gc
+ all-target: maybe-all-target-rda
+ all-target: maybe-all-target-libada
++all-target: maybe-all-target-libada-sjlj
+ all-target: maybe-all-target-libgnatvsn
+ all-target: maybe-all-target-libgnatprj
+ @if target-libgomp-no-bootstrap
+@@ -1243,6 +1245,7 @@ info-target: maybe-info-target-zlib
+ info-target: maybe-info-target-boehm-gc
+ info-target: maybe-info-target-rda
+ info-target: maybe-info-target-libada
++info-target: maybe-info-target-libada-sjlj
+ info-target: maybe-info-target-libgnatvsn
+ info-target: maybe-info-target-libgnatprj
+ info-target: maybe-info-target-libgomp
+@@ -1333,6 +1336,7 @@ dvi-target: maybe-dvi-target-zlib
+ dvi-target: maybe-dvi-target-boehm-gc
+ dvi-target: maybe-dvi-target-rda
+ dvi-target: maybe-dvi-target-libada
++dvi-target: maybe-dvi-target-libada-sjlj
+ dvi-target: maybe-dvi-target-libgnatvsn
+ dvi-target: maybe-dvi-target-libgnatprj
+ dvi-target: maybe-dvi-target-libgomp
+@@ -1423,6 +1427,7 @@ pdf-target: maybe-pdf-target-zlib
+ pdf-target: maybe-pdf-target-boehm-gc
+ pdf-target: maybe-pdf-target-rda
+ pdf-target: maybe-pdf-target-libada
++pdf-target: maybe-pdf-target-libada-sjlj
+ pdf-target: maybe-pdf-target-libgnatvsn
+ pdf-target: maybe-pdf-target-libgnatprj
+ pdf-target: maybe-pdf-target-libgomp
+@@ -1513,6 +1518,7 @@ html-target: maybe-html-target-zlib
+ html-target: maybe-html-target-boehm-gc
+ html-target: maybe-html-target-rda
+ html-target: maybe-html-target-libada
++html-target: maybe-html-target-libada-sjlj
+ html-target: maybe-html-target-libgnatvsn
+ html-target: maybe-html-target-libgnatprj
+ html-target: maybe-html-target-libgomp
+@@ -1603,6 +1609,7 @@ TAGS-target: maybe-TAGS-target-zlib
+ TAGS-target: maybe-TAGS-target-boehm-gc
+ TAGS-target: maybe-TAGS-target-rda
+ TAGS-target: maybe-TAGS-target-libada
++TAGS-target: maybe-TAGS-target-libada-sjlj
+ TAGS-target: maybe-TAGS-target-libgnatvsn
+ TAGS-target: maybe-TAGS-target-libgnatprj
+ TAGS-target: maybe-TAGS-target-libgomp
+@@ -1693,6 +1700,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-boehm-gc
+ install-info-target: maybe-install-info-target-rda
+ install-info-target: maybe-install-info-target-libada
++install-info-target: maybe-install-info-target-libada-sjlj
+ install-info-target: maybe-install-info-target-libgnatvsn
+ install-info-target: maybe-install-info-target-libgnatprj
+ install-info-target: maybe-install-info-target-libgomp
+@@ -1783,6 +1791,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-boehm-gc
+ install-pdf-target: maybe-install-pdf-target-rda
+ install-pdf-target: maybe-install-pdf-target-libada
++install-pdf-target: maybe-install-pdf-target-libada-sjlj
+ install-pdf-target: maybe-install-pdf-target-libgnatvsn
+ install-pdf-target: maybe-install-pdf-target-libgnatprj
+ install-pdf-target: maybe-install-pdf-target-libgomp
+@@ -1873,6 +1882,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-boehm-gc
+ install-html-target: maybe-install-html-target-rda
+ install-html-target: maybe-install-html-target-libada
++install-html-target: maybe-install-html-target-libada-sjlj
+ install-html-target: maybe-install-html-target-libgnatvsn
+ install-html-target: maybe-install-html-target-libgnatprj
+ install-html-target: maybe-install-html-target-libgomp
+@@ -1963,6 +1973,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-boehm-gc
+ installcheck-target: maybe-installcheck-target-rda
+ installcheck-target: maybe-installcheck-target-libada
++installcheck-target: maybe-installcheck-target-libada-sjlj
+ installcheck-target: maybe-installcheck-target-libgnatvsn
+ installcheck-target: maybe-installcheck-target-libgnatprj
+ installcheck-target: maybe-installcheck-target-libgomp
+@@ -2053,6 +2064,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-boehm-gc
+ mostlyclean-target: maybe-mostlyclean-target-rda
+ mostlyclean-target: maybe-mostlyclean-target-libada
++mostlyclean-target: maybe-mostlyclean-target-libada-sjlj
+ mostlyclean-target: maybe-mostlyclean-target-libgnatvsn
+ mostlyclean-target: maybe-mostlyclean-target-libgnatprj
+ mostlyclean-target: maybe-mostlyclean-target-libgomp
+@@ -2143,6 +2155,7 @@ clean-target: maybe-clean-target-zlib
+ clean-target: maybe-clean-target-boehm-gc
+ clean-target: maybe-clean-target-rda
+ clean-target: maybe-clean-target-libada
++clean-target: maybe-clean-target-libada-sjlj
+ clean-target: maybe-clean-target-libgnatvsn
+ clean-target: maybe-clean-target-libgnatprj
+ clean-target: maybe-clean-target-libgomp
+@@ -2233,6 +2246,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-boehm-gc
+ distclean-target: maybe-distclean-target-rda
+ distclean-target: maybe-distclean-target-libada
++distclean-target: maybe-distclean-target-libada-sjlj
+ distclean-target: maybe-distclean-target-libgnatvsn
+ distclean-target: maybe-distclean-target-libgnatprj
+ distclean-target: maybe-distclean-target-libgomp
+@@ -2323,6 +2337,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-boehm-gc
+ maintainer-clean-target: maybe-maintainer-clean-target-rda
+ maintainer-clean-target: maybe-maintainer-clean-target-libada
++maintainer-clean-target: maybe-maintainer-clean-target-libada-sjlj
+ maintainer-clean-target: maybe-maintainer-clean-target-libgnatvsn
+ maintainer-clean-target: maybe-maintainer-clean-target-libgnatprj
+ maintainer-clean-target: maybe-maintainer-clean-target-libgomp
+@@ -2469,6 +2484,7 @@ check-target:  \
+     maybe-check-target-boehm-gc \
+     maybe-check-target-rda \
+     maybe-check-target-libada \
++    maybe-check-target-libada-sjlj \
+     maybe-check-target-libgnatvsn \
+     maybe-check-target-libgnatprj \
+     maybe-check-target-libgomp \
+@@ -2655,6 +2671,7 @@ install-target:  \
+     maybe-install-target-boehm-gc \
+     maybe-install-target-rda \
+     maybe-install-target-libada \
++    maybe-install-target-libada-sjlj \
+     maybe-install-target-libgnatvsn \
+     maybe-install-target-libgnatprj \
+     maybe-install-target-libgomp \
+@@ -2765,6 +2782,7 @@ install-strip-target:  \
+     maybe-install-strip-target-boehm-gc \
+     maybe-install-strip-target-rda \
+     maybe-install-strip-target-libada \
++    maybe-install-strip-target-libada-sjlj \
+     maybe-install-strip-target-libgnatvsn \
+     maybe-install-strip-target-libgnatprj \
+     maybe-install-strip-target-libgomp \
+@@ -46077,6 +46095,352 @@ maintainer-clean-target-libada:
+ 
+ 
+ 
++.PHONY: configure-target-libada-sjlj maybe-configure-target-libada-sjlj
++maybe-configure-target-libada-sjlj:
++@if gcc-bootstrap
++configure-target-libada-sjlj: stage_current
++@endif gcc-bootstrap
++@if target-libada-sjlj
++maybe-configure-target-libada-sjlj: configure-target-libada-sjlj
++configure-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libada-sjlj..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp 2> /dev/null ; \
++	if test -r $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libada-sjlj/Makefile; \
++	    mv $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libada-sjlj/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libada-sjlj; \
++	cd "$(TARGET_SUBDIR)/libada-sjlj" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libada-sjlj/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libada-sjlj; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libada-sjlj
++
++
++
++
++
++.PHONY: all-target-libada-sjlj maybe-all-target-libada-sjlj
++maybe-all-target-libada-sjlj:
++@if gcc-bootstrap
++all-target-libada-sjlj: stage_current
++@endif gcc-bootstrap
++@if target-libada-sjlj
++TARGET-target-libada-sjlj=all
++maybe-all-target-libada-sjlj: all-target-libada-sjlj
++all-target-libada-sjlj: configure-target-libada-sjlj
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libada-sjlj))
++@endif target-libada-sjlj
++
++
++
++
++
++.PHONY: check-target-libada-sjlj maybe-check-target-libada-sjlj
++maybe-check-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-check-target-libada-sjlj: check-target-libada-sjlj
++
++# Dummy target for uncheckable module.
++check-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: install-target-libada-sjlj maybe-install-target-libada-sjlj
++maybe-install-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-target-libada-sjlj: install-target-libada-sjlj
++
++# Dummy target for uninstallable.
++install-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: install-strip-target-libada-sjlj maybe-install-strip-target-libada-sjlj
++maybe-install-strip-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-strip-target-libada-sjlj: install-strip-target-libada-sjlj
++
++# Dummy target for uninstallable.
++install-strip-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libada-sjlj info-target-libada-sjlj
++maybe-info-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-info-target-libada-sjlj: info-target-libada-sjlj
++
++# libada-sjlj doesn't support info.
++info-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-dvi-target-libada-sjlj dvi-target-libada-sjlj
++maybe-dvi-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-dvi-target-libada-sjlj: dvi-target-libada-sjlj
++
++# libada-sjlj doesn't support dvi.
++dvi-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-pdf-target-libada-sjlj pdf-target-libada-sjlj
++maybe-pdf-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-pdf-target-libada-sjlj: pdf-target-libada-sjlj
++
++pdf-target-libada-sjlj: \
++    configure-target-libada-sjlj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-html-target-libada-sjlj html-target-libada-sjlj
++maybe-html-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-html-target-libada-sjlj: html-target-libada-sjlj
++
++# libada-sjlj doesn't support html.
++html-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-TAGS-target-libada-sjlj TAGS-target-libada-sjlj
++maybe-TAGS-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-TAGS-target-libada-sjlj: TAGS-target-libada-sjlj
++
++# libada-sjlj doesn't support TAGS.
++TAGS-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-install-info-target-libada-sjlj install-info-target-libada-sjlj
++maybe-install-info-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-info-target-libada-sjlj: install-info-target-libada-sjlj
++
++# libada-sjlj doesn't support install-info.
++install-info-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-install-pdf-target-libada-sjlj install-pdf-target-libada-sjlj
++maybe-install-pdf-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-pdf-target-libada-sjlj: install-pdf-target-libada-sjlj
++
++install-pdf-target-libada-sjlj: \
++    configure-target-libada-sjlj \
++    pdf-target-libada-sjlj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-install-html-target-libada-sjlj install-html-target-libada-sjlj
++maybe-install-html-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-html-target-libada-sjlj: install-html-target-libada-sjlj
++
++install-html-target-libada-sjlj: \
++    configure-target-libada-sjlj \
++    html-target-libada-sjlj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-installcheck-target-libada-sjlj installcheck-target-libada-sjlj
++maybe-installcheck-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-installcheck-target-libada-sjlj: installcheck-target-libada-sjlj
++
++# libada-sjlj doesn't support installcheck.
++installcheck-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-mostlyclean-target-libada-sjlj mostlyclean-target-libada-sjlj
++maybe-mostlyclean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-mostlyclean-target-libada-sjlj: mostlyclean-target-libada-sjlj
++
++mostlyclean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-clean-target-libada-sjlj clean-target-libada-sjlj
++maybe-clean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-clean-target-libada-sjlj: clean-target-libada-sjlj
++
++clean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-distclean-target-libada-sjlj distclean-target-libada-sjlj
++maybe-distclean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-distclean-target-libada-sjlj: distclean-target-libada-sjlj
++
++distclean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-maintainer-clean-target-libada-sjlj maintainer-clean-target-libada-sjlj
++maybe-maintainer-clean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-maintainer-clean-target-libada-sjlj: maintainer-clean-target-libada-sjlj
++
++maintainer-clean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++
++
++
++
+ .PHONY: configure-target-libgnatvsn maybe-configure-target-libgnatvsn
+ maybe-configure-target-libgnatvsn:
+ @if gcc-bootstrap
+@@ -50993,6 +51357,7 @@ configure-target-zlib: stage_last
+ configure-target-boehm-gc: stage_last
+ configure-target-rda: stage_last
+ configure-target-libada: stage_last
++configure-target-libada-sjlj: stage_last
+ configure-target-libgnatvsn: stage_last
+ configure-target-libgnatprj: stage_last
+ configure-stage1-target-libgomp: maybe-all-stage1-gcc
+@@ -51030,6 +51395,7 @@ configure-target-zlib: maybe-all-gcc
+ configure-target-boehm-gc: maybe-all-gcc
+ configure-target-rda: maybe-all-gcc
+ configure-target-libada: maybe-all-gcc
++configure-target-libada-sjlj: maybe-all-gcc
+ configure-target-libgnatvsn: maybe-all-gcc
+ configure-target-libgnatprj: maybe-all-gcc
+ configure-target-libgomp: maybe-all-gcc
+@@ -51404,6 +51770,7 @@ all-stage4-fixincludes: maybe-all-stage4
+ all-stageprofile-fixincludes: maybe-all-stageprofile-libiberty
+ all-stagefeedback-fixincludes: maybe-all-stagefeedback-libiberty
+ all-target-libada: maybe-all-gcc
++all-target-libada-sjlj: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libgnatvsn
+ all-gnattools: maybe-all-target-libgnatprj
+@@ -52007,6 +52374,7 @@ configure-target-zlib: maybe-all-target-
+ configure-target-boehm-gc: maybe-all-target-libgcc
+ configure-target-rda: maybe-all-target-libgcc
+ configure-target-libada: maybe-all-target-libgcc
++configure-target-libada-sjlj: maybe-all-target-libgcc
+ configure-target-libgnatvsn: maybe-all-target-libgcc
+ configure-target-libgnatprj: maybe-all-target-libgcc
+ configure-target-libgomp: maybe-all-target-libgcc
+@@ -52063,6 +52431,8 @@ configure-target-rda: maybe-all-target-n
+ 
+ configure-target-libada: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libada-sjlj: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libgnatvsn: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-libgnatprj: maybe-all-target-newlib maybe-all-target-libgloss
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -176,6 +176,7 @@ target_libraries="target-libgcc \
+ 		${libgcj} \
+ 		target-libobjc \
+ 		target-libada \
++		target-libada-sjlj \
+ 		${target_libiberty} \
+ 		target-libgnatvsn \
+ 		target-libgnatprj \
+@@ -463,7 +464,7 @@ AC_ARG_ENABLE(libada,
+ ENABLE_LIBADA=$enableval,
+ ENABLE_LIBADA=yes)
+ if test "${ENABLE_LIBADA}" != "yes" ; then
+-  noconfigdirs="$noconfigdirs target-libgnatvsn target-libgnatprj gnattools"
++  noconfigdirs="$noconfigdirs target-libgnatvsn target-libgnatprj gnattools target-libada-sjlj"
+ fi
+ 
+ AC_ARG_ENABLE(libssp,
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -192,7 +192,7 @@ TOOLSCASE =
+ 
+ # Multilib handling
+ MULTISUBDIR =
+-RTSDIR = rts$(subst /,_,$(MULTISUBDIR))
++RTSDIR := rts$(subst /,_,$(MULTISUBDIR))
+ 
+ # Link flags used to build gnat tools.  By default we prefer to statically
+ # link with libgcc to avoid a dependency on shared libgcc (which is tricky
+@@ -2592,6 +2592,27 @@ install-gnatlib: ../stamp-gnatlib-$(RTSD
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.adb
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.ads
+ 
++install-gnatlib-sjlj: ../stamp-gnatlib-$(RTSDIR)
++#	Create the directory before deleting it, in case the directory is
++#	a list of directories (as it may be on VMS). This ensures we are
++#	deleting the right one.
++	-$(MKDIR) $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ)
++	-$(MKDIR) $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ)
++	$(RMDIR) $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ)
++	$(RMDIR) $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ)
++	-$(MKDIR) $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ)
++	-$(MKDIR) $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ)
++	for file in $(RTSDIR)/*.ali; do \
++	    $(INSTALL_DATA_DATE) $$file $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ); \
++	done
++	# This copy must be done preserving the date on the original file.
++	for file in $(RTSDIR)/*.ad?; do \
++	    $(INSTALL_DATA_DATE) $$file $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ); \
++	done
++	cd $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ); $(CHMOD) a-wx *.adb
++	cd $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ); $(CHMOD) a-wx *.ads
++
++
+ ../stamp-gnatlib1-$(RTSDIR): Makefile
+ 	$(RMDIR) $(RTSDIR)
+ 	$(MKDIR) $(RTSDIR)
+@@ -2848,7 +2869,7 @@ gnatlib-shared:
+ # in getting multiple blank lines, hence a style check error, as a
+ # result.
+ gnatlib-sjlj:
+-	$(MAKE) $(FLAGS_TO_PASS) EH_MECHANISM="" \
++	$(MAKE) $(FLAGS_TO_PASS) EH_MECHANISM="" RTSDIR="$(RTSDIR)" \
+ 	THREAD_KIND="$(THREAD_KIND)" ../stamp-gnatlib1-$(RTSDIR)
+ 	sed \
+ 	  -e 's/Frontend_Exceptions.*/Frontend_Exceptions       : constant Boolean := True;/' \
+@@ -2857,6 +2878,7 @@ gnatlib-sjlj:
+ 	  $(RTSDIR)/system.ads > $(RTSDIR)/s.ads
+ 	$(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads
+ 	$(MAKE) $(FLAGS_TO_PASS) \
++	     RTSDIR="$(RTSDIR)" \
+ 	     EH_MECHANISM="" \
+ 	     GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+@@ -2909,6 +2931,8 @@ b_gnatm.o : b_gnatm.adb
+ 
+ ADA_INCLUDE_DIR = $(libsubdir)/adainclude
+ ADA_RTL_OBJ_DIR = $(libsubdir)/adalib
++ADA_INCLUDE_DIR_SJLJ = $(libsubdir)/rts-sjlj/adainclude
++ADA_RTL_OBJ_DIR_SJLJ = $(libsubdir)/rts-sjlj/adalib
+ 
+ # Special flags
+ 
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -34,8 +34,8 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ 
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+-target_libs="target-libada target-libgnatvsn target-libgnatprj"
+-lang_dirs="libada libgnatvsn libgnatprj gnattools"
++target_libs="target-libada target-libgnatvsn target-libgnatprj target-libada-sjlj"
++lang_dirs="libada libgnatvsn libgnatprj gnattools libada-sjlj"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/gcc/ada/gcc-interface/Make-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Make-lang.in
++++ b/src/gcc/ada/gcc-interface/Make-lang.in
+@@ -784,6 +784,7 @@ ada.install-common:
+ 
+ install-gnatlib:
+ 	$(MAKE) -C ada $(COMMON_FLAGS_TO_PASS) $(ADA_FLAGS_TO_PASS) install-gnatlib$(LIBGNAT_TARGET)
++	$(MAKE) -C ada $(COMMON_FLAGS_TO_PASS) $(ADA_FLAGS_TO_PASS) RTSDIR="rts-sjlj" install-gnatlib-sjlj$(LIBGNAT_TARGET)
+ 
+ install-gnatlib-obj:
+ 	$(MAKE) -C ada $(COMMON_FLAGS_TO_PASS) $(ADA_FLAGS_TO_PASS) install-gnatlib-obj
--- gcc-6-6.3.0.orig/debian/patches/ada-symbolic-tracebacks.diff
+++ gcc-6-6.3.0/debian/patches/ada-symbolic-tracebacks.diff
@@ -0,0 +1,401 @@
+# DP: - Enable support for symbolic tracebacks in exceptions (delete the dummy
+# DP:   convert_addresses from adaint.c, and provide a real one separately.)
+
+Ported Jürgen Pfeifer's patch to enable symbolic tracebacks on Debian
+GNU/Linux.
+
+The binary distribution of GNAT 3.15p comes with an old version of
+binutils that includes a library, libaddr2line.a.  This library does
+not exist in recent versions of binutils.  The patch works around this
+by calling /usr/bin/addr2line (still part of binutils) and parsing the
+output.  See debian/convert_addresses.c for the gory details.
+
+I have modified convert_addresses.c to not use a shell script anymore;
+Debian controls the version of binutils which is installed.  Also, I
+use execve instead of execle.
+
+-- 
+Ludovic Brenta.
+
+# ' make emacs highlighting happy
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -270,7 +270,8 @@
+ # Both . and srcdir are used, in that order,
+ # so that tm.h and config.h will be found in the compilation
+ # subdirectory rather than in the source directory.
+-INCLUDES = -I- -I. -I.. -I$(srcdir)/ada -I$(srcdir) -I$(ftop_srcdir)/include $(GMPINC)
++INCLUDES = -iquote . -iquote .. -iquote $(srcdir)/ada -iquote $(srcdir) \
++ -iquote $(ftop_srcdir)/include $(GMPINC)
+ 
+ ADA_INCLUDES = -I- -I. -I$(srcdir)/ada
+ 
+@@ -2426,7 +2427,7 @@
+ # library.  LIBGNAT_OBJS is the list of object files for libgnat.
+ # thread.c is special as put into GNATRTL_TASKING_OBJS by Makefile.rtl
+ LIBGNAT_OBJS = adadecode.o adaint.o argv.o aux-io.o 			\
+-  cal.o cio.o cstreams.o ctrl_c.o					\
++  cal.o cio.o convert_addresses.o cstreams.o ctrl_c.o			\
+   env.o errno.o exit.o expect.o final.o 				\
+   init.o initialize.o locales.o mkdir.o					\
+   raise.o seh_init.o socket.o sysdep.o					\
+@@ -3104,6 +3105,7 @@
+ socket.o  : socket.c gsocket.h
+ sysdep.o  : sysdep.c
+ raise.o   : raise.c raise.h
++convert_addresses.o : convert_addresses.c
+ sigtramp-armdroid.o : sigtramp-armdroid.c sigtramp.h
+ sigtramp-armvxw.o : sigtramp-armvxw.c sigtramp.h
+ sigtramp-ppcvxw.o : sigtramp-ppcvxw.c sigtramp.h
+Index: b/src/gcc/ada/adaint.c
+===================================================================
+--- a/src/gcc/ada/adaint.c
++++ b/src/gcc/ada/adaint.c
+@@ -3608,35 +3608,6 @@
+ }
+ #endif
+ 
+-#if defined (IS_CROSS)  \
+-  || (! ((defined (sparc) || defined (i386)) && defined (sun) \
+-      && defined (__SVR4)) \
+-      && ! (defined (linux) && (defined (i386) || defined (__x86_64__))) \
+-      && ! (defined (linux) && defined (__ia64__)) \
+-      && ! (defined (linux) && defined (powerpc)) \
+-      && ! defined (__FreeBSD__) \
+-      && ! defined (__Lynx__) \
+-      && ! defined (__hpux__) \
+-      && ! defined (__APPLE__) \
+-      && ! defined (_AIX) \
+-      && ! defined (VMS) \
+-      && ! defined (__MINGW32__))
+-
+-/* Dummy function to satisfy g-trasym.o. See the preprocessor conditional
+-   just above for a list of native platforms that provide a non-dummy
+-   version of this procedure in libaddr2line.a.  */
+-
+-void
+-convert_addresses (const char *file_name ATTRIBUTE_UNUSED,
+-		   void *addrs ATTRIBUTE_UNUSED,
+-		   int n_addr ATTRIBUTE_UNUSED,
+-		   void *buf ATTRIBUTE_UNUSED,
+-		   int *len ATTRIBUTE_UNUSED)
+-{
+-  *len = 0;
+-}
+-#endif
+-
+ #if defined (_WIN32)
+ int __gnat_argument_needs_quote = 1;
+ #else
+Index: b/src/gcc/ada/convert_addresses.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/ada/convert_addresses.c
+@@ -0,0 +1,159 @@
++/*
++  Copyright (C) 1999 by Juergen Pfeifer <juergen.pfeifer@gmx.net>
++  Ada for Linux Team (ALT)
++
++  Permission is hereby granted, free of charge, to any person obtaining a
++  copy of this software and associated documentation files (the
++  "Software"), to deal in the Software without restriction, including
++  without limitation the rights to use, copy, modify, merge, publish,
++  distribute, distribute with modifications, sublicense, and/or sell
++  copies of the Software, and to permit persons to whom the Software is
++  furnished to do so, subject to the following conditions:
++
++  The above copyright notice and this permission notice shall be included
++  in all copies or substantial portions of the Software.
++
++  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++  OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
++  IN NO EVENT SHALL THE ABOVE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
++  DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++  OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
++  THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++
++  Except as contained in this notice, the name(s) of the above copyright
++  holders shall not be used in advertising or otherwise to promote the
++  sale, use or other dealings in this Software without prior written
++  authorization.
++*/
++#include <sys/types.h>
++#include <stdlib.h>
++#include <stdio.h>
++#include <unistd.h>
++#include <string.h>
++#include <signal.h>
++
++#define STDIN_FILENO  0
++#define STDOUT_FILENO 1
++#define MAX_LINE      1024
++
++#define CLOSE1  close(fd1[0]); close(fd1[1])
++#define CLOSE2  close(fd2[0]); close(fd2[1])
++#define RESTSIG sigaction(SIGPIPE,&oact,NULL)
++
++void convert_addresses
++(const char const *file_name,
++  void* addrs[],
++  int   n_addr,
++  char* buf,
++  int*  len)
++{
++  int max_len = *len;
++  pid_t child;
++
++  struct sigaction act, oact;
++
++  int fd1[2], fd2[2];
++
++  if (!file_name) {
++    return;
++  }
++
++  *buf = 0; *len = 0;
++  act.sa_handler = SIG_IGN;
++  sigemptyset(&act.sa_mask);
++  act.sa_flags = 0;
++  if (sigaction(SIGPIPE,&act,&oact) < 0)
++    return;
++
++  if (pipe(fd1) >= 0) {
++    if (pipe(fd2)>=0) {
++      if ((child = fork()) < 0) {
++      CLOSE1; CLOSE2; RESTSIG;
++      return;
++      }
++      else {
++      if (0==child) {
++        close(fd1[1]);
++        close(fd2[0]);
++        if (fd1[0] != STDIN_FILENO) {
++          if (dup2(fd1[0],STDIN_FILENO) != STDIN_FILENO) {
++            CLOSE1; CLOSE2;
++          }
++          close(fd1[0]);
++        }
++        if (fd2[1] != STDOUT_FILENO) {
++          if (dup2(fd2[1],STDOUT_FILENO) != STDOUT_FILENO) {
++            CLOSE1; CLOSE2;
++          }
++          close(fd2[1]);
++        }
++        {
++          /* As pointed out by Florian Weimer to me, it is a
++             security threat to call the script with a user defined
++             environment and using the path. That would be Trojans
++             pleasure.  Therefore we use the absolute path to
++             addr2line and an empty environment. That should be
++             safe.
++          */
++          char *file_name_for_execve = strdup (file_name); /* non-const */
++          char *const argv[] = { "addr2line",
++                                 "-e",
++                                 file_name_for_execve,
++                                 "--demangle=gnat",
++                                 "--functions",
++                                 "--basenames",
++                                 NULL };
++          char *const envp[] = { NULL };
++          if (execve("/usr/bin/addr2line", argv, envp) < 0) {
++            CLOSE1; CLOSE2;
++          }
++	  if (file_name_for_execve) { free (file_name_for_execve); }
++        }
++      }
++      else {
++        int i, n;
++        char hex[16];
++        char line[MAX_LINE + 1];
++        char *p;
++        char *s = buf;
++
++        /* Parent context */
++        close(fd1[0]);
++        close(fd2[1]);
++
++        for(i=0; i < n_addr; i++) {
++          snprintf(hex,sizeof(hex),"%p\n",addrs[i]);
++          write(fd1[1],hex,strlen(hex));
++          n = read(fd2[0],line,MAX_LINE);
++          if (n<=0)
++            break;
++          line[n]=0;
++          /* We have approx. 16 additional chars for "%p in " clause.
++             We use this info to prevent a buffer overrun.
++          */
++          if (n + 16 + (*len) > max_len)
++            break;
++          p = strchr(line,'\n');
++          if (p) {
++            if (*(p+1)) {
++              *p = 0;
++              *len += snprintf(s, (max_len - (*len)), "%p in %s at %s",addrs[i], line, p+1);
++            }
++            else {
++              *len += snprintf(s, (max_len - (*len)), "%p at %s",addrs[i], line);
++            }
++            s = buf + (*len);
++          }
++        }
++        close(fd1[1]);
++        close(fd2[0]);
++      }
++      }
++    }
++    else {
++      CLOSE1;
++    }
++  }
++  RESTSIG;
++}
+Index: b/src/gcc/ada/g-trasym.adb
+===================================================================
+--- a/src/gcc/ada/g-trasym.adb
++++ b/src/gcc/ada/g-trasym.adb
+@@ -33,40 +33,110 @@
+ --  is not supported. It returns tracebacks as lists of LF separated strings of
+ --  the form "0x..." corresponding to the addresses.
+ 
++with System.Soft_Links;
+ with Ada.Exceptions.Traceback; use Ada.Exceptions.Traceback;
+-with System.Address_Image;
+ 
+ package body GNAT.Traceback.Symbolic is
+ 
++   package TSL renames System.Soft_Links;
++
++   --  To perform the raw addresses to symbolic form translation we rely on a
++   --  libaddr2line symbolizer which examines debug info from a provided
++   --  executable file name, and an absolute path is needed to ensure the file
++   --  is always found. This is "__gnat_locate_exec_on_path (gnat_argv [0])"
++   --  for our executable file, a fairly heavy operation so we cache the
++   --  result.
++
++   Exename : System.Address;
++   --  Pointer to the name of the executable file to be used on all
++   --  invocations of the libaddr2line symbolization service.
++
++   Exename_Resolved : Boolean := False;
++   --  Flag to indicate whether we have performed the executable file name
++   --  resolution already. Relying on a not null Exename for this purpose
++   --  would be potentially inefficient as this is what we will get if the
++   --  resolution attempt fails.
++
+    ------------------------
+    -- Symbolic_Traceback --
+    ------------------------
+ 
+    function Symbolic_Traceback (Traceback : Tracebacks_Array) return String is
++
++      procedure convert_addresses
++        (filename : System.Address;
++         addrs    : System.Address;
++         n_addrs  : Integer;
++         buf      : System.Address;
++         len      : System.Address);
++      pragma Import (C, convert_addresses, "convert_addresses");
++      --  This is the procedure version of the Ada-aware addr2line. It places
++      --  in BUF a string representing the symbolic translation of the N_ADDRS
++      --  raw addresses provided in ADDRS, looked up in debug information from
++      --  FILENAME. LEN points to an integer which contains the size of the
++      --  BUF buffer at input and the result length at output.
++      --
++      --  Note that this procedure is *not* thread-safe.
++
++      type Argv_Array is array (0 .. 0) of System.Address;
++      gnat_argv : access Argv_Array;
++      pragma Import (C, gnat_argv, "gnat_argv");
++
++      function locate_exec_on_path
++        (c_exename : System.Address) return System.Address;
++      pragma Import (C, locate_exec_on_path, "__gnat_locate_exec_on_path");
++
++      B_Size : constant Integer := 256 * Traceback'Length;
++      Len    : Integer := B_Size;
++      Res    : String (1 .. B_Size);
++
++      use type System.Address;
++
+    begin
++      --  The symbolic translation of an empty set of addresses is an empty
++      --  string.
++
+       if Traceback'Length = 0 then
+          return "";
++      end if;
+ 
+-      else
+-         declare
+-            Img : String := System.Address_Image (Traceback (Traceback'First));
++      --  If our input set of raw addresses is not empty, resort to the
++      --  libaddr2line service to symbolize it all.
+ 
+-            Result : String (1 .. (Img'Length + 3) * Traceback'Length);
+-            Last   : Natural := 0;
++      --  Compute, cache and provide the absolute path to our executable file
++      --  name as the binary file where the relevant debug information is to be
++      --  found. If the executable file name resolution fails, we have no
++      --  sensible basis to invoke the symbolizer at all.
++
++      --  Protect all this against concurrent accesses explicitly, as the
++      --  underlying services are potentially thread unsafe.
++
++      TSL.Lock_Task.all;
++
++      if not Exename_Resolved then
++         Exename := locate_exec_on_path (gnat_argv (0));
++         Exename_Resolved := True;
++      end if;
++
++      if Exename /= System.Null_Address then
++         Len := Res'Length;
++         convert_addresses
++           (Exename, Traceback'Address, Traceback'Length,
++            Res (1)'Address, Len'Address);
++      end if;
++
++      TSL.Unlock_Task.all;
+ 
+-         begin
+-            for J in Traceback'Range loop
+-               Img := System.Address_Image (Traceback (J));
+-               Result (Last + 1 .. Last + 2) := "0x";
+-               Last := Last + 2;
+-               Result (Last + 1 .. Last + Img'Length) := Img;
+-               Last := Last + Img'Length + 1;
+-               Result (Last) := ASCII.LF;
+-            end loop;
++      --  Return what the addr2line symbolizer has produced if we have called
++      --  it (the executable name resolution succeeded), or an empty string
++      --  otherwise.
+ 
+-            return Result (1 .. Last);
+-         end;
++      if Exename /= System.Null_Address then
++         return Res (1 .. Len);
++      else
++         return "";
+       end if;
++
+    end Symbolic_Traceback;
+ 
+    function Symbolic_Traceback (E : Exception_Occurrence) return String is
+Index: b/src/gcc/ada/tracebak.c
+===================================================================
+--- a/src/gcc/ada/tracebak.c
++++ b/src/gcc/ada/tracebak.c
+@@ -425,7 +425,7 @@
+ /* Starting with GCC 4.6, -fomit-frame-pointer is turned on by default for
+    32-bit x86/Linux as well and DWARF 2 unwind tables are emitted instead.
+    See the x86-64 case below for the drawbacks with this approach.  */
+-#if defined (linux) && (__GNUC__ * 10 + __GNUC_MINOR__ > 45)
++#if (defined (linux) || defined(__GNU__)) && (__GNUC__ * 10 + __GNUC_MINOR__ > 45)
+ #define USE_GCC_UNWINDER
+ #else
+ #define USE_GENERIC_UNWINDER
--- gcc-6-6.3.0.orig/debian/patches/add-gnu-to-libgo-headers.diff
+++ gcc-6-6.3.0/debian/patches/add-gnu-to-libgo-headers.diff
@@ -0,0 +1,793 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/archive/tar/stat_atim.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/archive/tar/stat_atim.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/archive/tar/stat_atim.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build linux dragonfly openbsd solaris
++// +build linux dragonfly openbsd solaris gnu
+ 
+ package tar
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_resnew.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_resnew.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_resnew.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build darwin linux,!android netbsd solaris
++// +build darwin linux,!android netbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_socknew.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_socknew.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_socknew.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build android linux solaris
++// +build android linux solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/hook_cloexec.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/hook_cloexec.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/hook_cloexec.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build freebsd linux
++// +build freebsd linux gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/main_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/main_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/main_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sock_cloexec.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sock_cloexec.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sock_cloexec.go
+@@ -5,7 +5,7 @@
+ // This file implements sysSocket and accept for platforms that
+ // provide a fast path for setting SetNonblock and CloseOnExec.
+ 
+-// +build freebsd linux
++// +build freebsd linux gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sockoptip_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd windows
++// +build darwin dragonfly freebsd linux netbsd openbsd windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/exec_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Fork, exec, wait, etc.
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll_select.c
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/runtime/netpoll_select.c
++++ gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll_select.c
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build solaris
++// +build solaris gnu
+ 
+ #include "config.h"
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/exec/lp_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package exec
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/exec/lp_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package exec
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/os_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/os_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/os_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package os_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/signal/signal_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package signal
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/signal/signal_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package signal
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/runtime/crash_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/runtime/crash_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/runtime/crash_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package runtime_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/exec_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package syscall_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/error_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/error_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/error_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/file_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/file_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/file_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/path_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/path_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/path_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/sys_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/sys_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/sys_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build dragonfly linux netbsd openbsd solaris
++// +build dragonfly linux netbsd openbsd solaris gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/user/decls_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/user/decls_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/user/decls_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd
++// +build darwin dragonfly freebsd linux netbsd openbsd gnu
+ // +build cgo
+ 
+ package user
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/user/lookup_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/user/lookup_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/user/lookup_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd !android,linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd !android,linux netbsd openbsd solaris gnu
+ // +build cgo
+ 
+ package user
+Index: gcc-6-6.2.1-4.1/src/libgo/go/runtime/runtime_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/runtime/runtime_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/runtime/runtime_unix_test.go
+@@ -6,7 +6,7 @@
+ // We need a fast system call to provoke the race,
+ // and Close(-1) is nearly universally fast.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd plan9
++// +build darwin dragonfly freebsd linux netbsd openbsd plan9 gnu
+ 
+ package runtime_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/env_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/env_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/env_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ // Unix environment variables.
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_bsd.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/exec_bsd.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_bsd.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd netbsd openbsd
++// +build darwin dragonfly freebsd netbsd openbsd gnu
+ 
+ package syscall
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/export_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/export_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/export_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd
++// +build darwin dragonfly freebsd linux netbsd openbsd gnu
+ 
+ package syscall
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/mmap_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/mmap_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/mmap_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd
++// +build darwin dragonfly freebsd linux netbsd openbsd gnu
+ 
+ package syscall_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/sockcmsg_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/sockcmsg_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/sockcmsg_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Socket control messages
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/syscall_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package syscall
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/time/sys_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/time/sys_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/time/sys_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package time
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/time/zoneinfo_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/time/zoneinfo_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/time/zoneinfo_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin,386 darwin,amd64 dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin,386 darwin,amd64 dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ // Parse "zoneinfo" time zone file.
+ // This is a fairly standard file format used on OS X, Linux, BSD, Sun, and others.
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/addrselect.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Minimal RFC 6724 address selection.
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/addrselect_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix_test.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/conf.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/conf.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/conf.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/conf_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/conf_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/conf_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/dnsclient_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/dnsclient_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/dnsclient_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // DNS client: see RFC 1035.
+ // Has to be linked into package net for Dial.
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/dnsconfig_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Read system DNS config from /etc/resolv.conf
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/dnsconfig_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/fd_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/fd_posix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/fd_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/fd_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/fd_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/file_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/file_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/file_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/hook_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/hook_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/hook_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/interface_stub.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/interface_stub.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/interface_stub.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build nacl plan9 solaris
++// +build nacl plan9 solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/iprawsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/iprawsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/iprawsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/ipsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/ipsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/ipsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ // Internet protocol family sockets for POSIX
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/lookup_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/lookup_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/lookup_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/nss.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/nss.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/nss.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/nss_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/nss_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/nss_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/port_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/port_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/port_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Read system port mappings from /etc/services
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sockopt_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/tcpsockopt_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/tcpsockopt_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build freebsd linux netbsd
++// +build freebsd linux netbsd gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/tcpsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/udpsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/udpsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/udpsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/unixsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/unixsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/unixsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/exec_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/exec_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/exec_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/file_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/file_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/file_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package os
+ 
--- gcc-6-6.3.0.orig/debian/patches/alpha-ieee-doc.diff
+++ gcc-6-6.3.0/debian/patches/alpha-ieee-doc.diff
@@ -0,0 +1,24 @@
+# DP: #212912
+# DP: on alpha-linux, make -mieee default and add -mieee-disable switch
+# DP: to turn default off (doc patch)
+
+---
+ gcc/doc/invoke.texi |    7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -9980,6 +9980,13 @@ able to correctly support denormalized numbers and exceptional IEEE
+ values such as not-a-number and plus/minus infinity.  Other Alpha
+ compilers call this option @option{-ieee_with_no_inexact}.
+ 
++DEBIAN SPECIFIC: This option is on by default for alpha-linux-gnu, unless
++@option{-ffinite-math-only} (which is part of the @option{-ffast-math}
++set) is specified, because the software functions in the GNU libc math
++libraries generate denormalized numbers, NaNs, and infs (all of which
++will cause a programs to SIGFPE when it attempts to use the results without
++@option{-mieee}).
++
+ @item -mieee-with-inexact
+ @opindex mieee-with-inexact
+ This is like @option{-mieee} except the generated code also maintains
--- gcc-6-6.3.0.orig/debian/patches/alpha-ieee.diff
+++ gcc-6-6.3.0/debian/patches/alpha-ieee.diff
@@ -0,0 +1,21 @@
+# DP: #212912
+# DP: on alpha-linux, make -mieee default and add -mieee-disable switch
+# DP: to turn default off
+
+---
+ gcc/config/alpha/alpha.c |    4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+--- a/src/gcc/config/alpha/alpha.c
++++ b/src/gcc/config/alpha/alpha.c
+@@ -259,6 +259,10 @@
+   int line_size = 0, l1_size = 0, l2_size = 0;
+   int i;
+ 
++  /* If not -ffinite-math-only, enable -mieee*/
++  if (!flag_finite_math_only)
++    target_flags |= MASK_IEEE|MASK_IEEE_CONFORMANT;
++
+ #ifdef SUBTARGET_OVERRIDE_OPTIONS
+   SUBTARGET_OVERRIDE_OPTIONS;
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/alpha-no-ev4-directive.diff
+++ gcc-6-6.3.0/debian/patches/alpha-no-ev4-directive.diff
@@ -0,0 +1,32 @@
+# DP: never emit .ev4 directive.
+
+---
+ gcc/config/alpha/alpha.c |    7 +++----
+ 1 files changed, 3 insertions(+), 4 deletions(-)
+
+Index: b/src/gcc/config/alpha/alpha.c
+===================================================================
+--- a/src/gcc/config/alpha/alpha.c
++++ b/src/gcc/config/alpha/alpha.c
+@@ -9460,7 +9460,7 @@ alpha_file_start (void)
+     fputs ("\t.set nomacro\n", asm_out_file);
+   if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
+     {
+-      const char *arch;
++      const char *arch = NULL;
+ 
+       if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX)
+ 	arch = "ev6";
+@@ -9470,10 +9470,9 @@ alpha_file_start (void)
+ 	arch = "ev56";
+       else if (alpha_cpu == PROCESSOR_EV5)
+ 	arch = "ev5";
+-      else
+-	arch = "ev4";
+ 
+-      fprintf (asm_out_file, "\t.arch %s\n", arch);
++      if (arch)
++        fprintf (asm_out_file, "\t.arch %s\n", arch);
+     }
+ }
+ 
--- gcc-6-6.3.0.orig/debian/patches/aotcompile.diff
+++ gcc-6-6.3.0/debian/patches/aotcompile.diff
@@ -0,0 +1,51 @@
+--- ./build/aot/aotcompile.py.orig	2010-04-08 13:38:27.621086079 +0000
++++ ./build/aot/aotcompile.py	2010-04-08 14:22:55.102335973 +0000
+@@ -31,12 +31,25 @@
+          "dbtool": "/usr/lib/gcc-snapshot/bin/gcj-dbtool"}
+ 
+ MAKEFLAGS = []
+-GCJFLAGS = ["-fPIC", "-findirect-dispatch", "-fjni"]
++GCJFLAGS = ["-O2 -fPIC", "-findirect-dispatch", "-fjni"]
+ LDFLAGS = ["-Wl,-Bsymbolic"]
+ 
+ MAX_CLASSES_PER_JAR = 1024
+ MAX_BYTES_PER_JAR = 1048576
+ 
++try:
++    for line in file('/proc/meminfo'):
++        if line.startswith('MemTotal:'):
++            memtotal = int(line.split()[1])
++        if memtotal < 270000:
++            MAX_CLASSES_PER_JAR = 512
++            MAX_BYTES_PER_JAR = 524288
++        if memtotal < 140000:
++            MAX_CLASSES_PER_JAR = 256
++            MAX_BYTES_PER_JAR = 262144
++except:
++    pass
++
+ MAKEFILE = "Makefile"
+ 
+ MAKEFILE_HEADER = '''\
+@@ -49,7 +62,7 @@
+ 	$(GCJ) -c $(GCJFLAGS) $< -o $@
+ 
+ TARGETS = \\
+-%(targets)s
++javac ecj1
+ 
+ all: $(TARGETS)'''
+ 
+@@ -63,6 +76,12 @@
+ %(dso)s: $(%(base)s_OBJECTS)
+ 	$(GCJ) -shared $(GCJFLAGS) $(LDFLAGS) $^ -o $@
+ 
++javac: $(%(base)s_OBJECTS) resources.o
++	$(GCJ) $(GCJFLAGS) $(RPATH) -Wl,-O1 --main=org.eclipse.jdt.internal.compiler.batch.Main $^ -o $@
++
++ecj1: $(%(base)s_OBJECTS) resources.o
++	$(GCJ) $(GCJFLAGS) $(RPATH) -Wl,-O1 --main=org.eclipse.jdt.internal.compiler.batch.GCCMain $^ -o $@
++
+ %(db)s: $(%(base)s_SOURCES)
+ 	$(DBTOOL) -n $@ 64
+ 	for jar in $^; do \\
--- gcc-6-6.3.0.orig/debian/patches/arm-multilib-defaults.diff
+++ gcc-6-6.3.0/debian/patches/arm-multilib-defaults.diff
@@ -0,0 +1,92 @@
+# DP: Set MULTILIB_DEFAULTS for ARM multilib builds
+
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -3738,10 +3738,18 @@ case "${target}" in
+ 		fi
+ 
+ 		case "$with_float" in
+-		"" \
+-		| soft | hard | softfp)
++		"")
+ 			# OK
+ 			;;
++		soft)
++			tm_defines="${tm_defines} TARGET_CONFIGURED_FLOAT_ABI=0"
++			;;
++		softfp)
++			tm_defines="${tm_defines} TARGET_CONFIGURED_FLOAT_ABI=1"
++			;;
++		hard)
++			tm_defines="${tm_defines} TARGET_CONFIGURED_FLOAT_ABI=2"
++			;;
+ 		*)
+ 			echo "Unknown floating point type used in --with-float=$with_float" 1>&2
+ 			exit 1
+@@ -3775,6 +3783,9 @@ case "${target}" in
+ 		"" \
+ 		| arm | thumb )
+ 			#OK
++			if test "$with_mode" = thumb; then
++				tm_defines="${tm_defines} TARGET_CONFIGURED_THUMB_MODE=1"
++			fi
+ 			;;
+ 		*)
+ 			echo "Unknown mode used in --with-mode=$with_mode"
+Index: b/src/gcc/config/arm/linux-eabi.h
+===================================================================
+--- a/src/gcc/config/arm/linux-eabi.h
++++ b/src/gcc/config/arm/linux-eabi.h
+@@ -43,7 +43,21 @@
+    target hardware.  If you override this to use the hard-float ABI then
+    change the setting of GLIBC_DYNAMIC_LINKER_DEFAULT as well.  */
+ #undef  TARGET_DEFAULT_FLOAT_ABI
++#ifdef TARGET_CONFIGURED_FLOAT_ABI
++#if TARGET_CONFIGURED_FLOAT_ABI == 2
++#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_HARD
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=hard"
++#elif TARGET_CONFIGURED_FLOAT_ABI == 1
++#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFTFP
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=softfp"
++#else
++#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=soft"
++#endif
++#else
+ #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=soft"
++#endif
+ 
+ /* We default to the "aapcs-linux" ABI so that enums are int-sized by
+    default.  */
+@@ -103,6 +117,28 @@
+ #define MUSL_DYNAMIC_LINKER \
+   "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1"
+ 
++/* Set the multilib defaults according the configuration, needed to
++   let gcc -print-multi-dir do the right thing.  */
++
++#if TARGET_BIG_ENDIAN_DEFAULT
++#define MULTILIB_DEFAULT_ENDIAN "mbig-endian"
++#else
++#define MULTILIB_DEFAULT_ENDIAN "mlittle-endian"
++#endif
++
++#ifndef TARGET_CONFIGURED_THUMB_MODE
++#define MULTILIB_DEFAULT_MODE "marm"
++#elif TARGET_CONFIGURED_THUMB_MODE == 1
++#define MULTILIB_DEFAULT_MODE "mthumb"
++#else
++#define MULTILIB_DEFAULT_MODE "marm"
++#endif
++
++#undef  MULTILIB_DEFAULTS
++#define MULTILIB_DEFAULTS \
++	{ MULTILIB_DEFAULT_MODE, MULTILIB_DEFAULT_ENDIAN, \
++	  MULTILIB_DEFAULT_FLOAT_ABI, "mno-thumb-interwork" }
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to
+    use the GNU/Linux version, not the generic BPABI version.  */
+ #undef  LINK_SPEC
--- gcc-6-6.3.0.orig/debian/patches/arm-multilib-soft-cross.diff
+++ gcc-6-6.3.0/debian/patches/arm-multilib-soft-cross.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/soft float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi
++++ b/src/gcc/config/arm/t-linux-eabi
+@@ -21,6 +21,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= ../libsf:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi ../libhf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.3.0.orig/debian/patches/arm-multilib-soft-float.diff
+++ gcc-6-6.3.0/debian/patches/arm-multilib-soft-float.diff
@@ -0,0 +1,26 @@
+--- a/src/gcc/config/arm/t-linux-eabi
++++ b/src/gcc/config/arm/t-linux-eabi
+@@ -24,6 +24,23 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifneq (,$(findstring MULTIARCH_DEFAULTS,$(tm_defines)))
++ifneq (,$(findstring __arm_linux_gnueabi__,$(tm_defines)))
++  MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard/mfloat-abi=soft
++  MULTILIB_DIRNAMES	= . hf soft-float
++  MULTILIB_EXCEPTIONS	=
++  MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float
++  MULTILIB_OSDIRNAMES	= ../../lib/arm-linux-gnueabi ../../lib/arm-linux-gnueabihf soft-float
++endif
++ifneq (,$(findstring __arm_linux_gnueabihf__,$(tm_defines)))
++  MULTILIB_OPTIONS	= mfloat-abi=hard/mfloat-abi=softfp/mfloat-abi=soft
++  MULTILIB_DIRNAMES	= . sf soft-float
++  MULTILIB_EXCEPTIONS	=
++  MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float
++  MULTILIB_OSDIRNAMES	= ../../lib/arm-linux-gnueabihf ../../lib/arm-linux-gnueabi soft-float
++endif
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.3.0.orig/debian/patches/arm-multilib-soft.diff
+++ gcc-6-6.3.0/debian/patches/arm-multilib-soft.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/soft float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi
++++ b/src/gcc/config/arm/t-linux-eabi
+@@ -23,6 +23,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= arm-linux-gnueabi:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi arm-linux-gnueabihf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.3.0.orig/debian/patches/arm-multilib-softfp-cross.diff
+++ gcc-6-6.3.0/debian/patches/arm-multilib-softfp-cross.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/softfp float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi	2011-01-03 20:52:22.000000000 +0000
++++ b/src/gcc/config/arm/t-linux-eabi	2011-08-21 21:08:47.583351817 +0000
+@@ -24,6 +24,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= ../libsf:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi ../libhf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.3.0.orig/debian/patches/arm-multilib-softfp.diff
+++ gcc-6-6.3.0/debian/patches/arm-multilib-softfp.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/softfp float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi	2011-01-03 20:52:22.000000000 +0000
++++ b/src/gcc/config/arm/t-linux-eabi	2011-08-21 21:08:47.583351817 +0000
+@@ -24,6 +24,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= arm-linux-gnueabi:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi arm-linux-gnueabihf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.3.0.orig/debian/patches/bind_now_when_pie.diff
+++ gcc-6-6.3.0/debian/patches/bind_now_when_pie.diff
@@ -0,0 +1,20 @@
+Author: Steve Beattie <steve.beattie@canonical.com>
+Description: enable bind now by default when linking with pie by default
+
+---
+ src/gcc/gcc.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -930,7 +930,7 @@ proper position among the other output f
+ #ifndef LINK_PIE_SPEC
+ #ifdef HAVE_LD_PIE
+ #ifndef LD_PIE_SPEC
+-#define LD_PIE_SPEC "-pie"
++#define LD_PIE_SPEC "-pie -z now"
+ #endif
+ #else
+ #define LD_PIE_SPEC ""
--- gcc-6-6.3.0.orig/debian/patches/boehm-gc-getnprocs.diff
+++ gcc-6-6.3.0/debian/patches/boehm-gc-getnprocs.diff
@@ -0,0 +1,20 @@
+# DP: boehm-gc/pthread_support.c (GC_get_nprocs): Use sysconf as fallback.
+
+---
+ boehm-gc/pthread_support.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+Index: b/src/boehm-gc/pthread_support.c
+===================================================================
+--- a/src/boehm-gc/pthread_support.c
++++ b/src/boehm-gc/pthread_support.c
+@@ -724,7 +724,8 @@ int GC_get_nprocs()
+     f = open("/proc/stat", O_RDONLY);
+     if (f < 0 || (len = STAT_READ(f, stat_buf, STAT_BUF_SIZE)) < 100) {
+ 	WARN("Couldn't read /proc/stat\n", 0);
+-	return -1;
++	/* Fallback to sysconf after the warning */
++	return sysconf(_SC_NPROCESSORS_ONLN);
+     }
+     for (i = 0; i < len - 100; ++i) {
+         if (stat_buf[i] == '\n' && stat_buf[i+1] == 'c'
--- gcc-6-6.3.0.orig/debian/patches/boehm-gc-nocheck.diff
+++ gcc-6-6.3.0/debian/patches/boehm-gc-nocheck.diff
@@ -0,0 +1,18 @@
+# DP: Disable running the boehm-gc testsuite. Hangs the buildd at least on hppa.
+
+---
+ boehm-gc/Makefile.in |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+--- a/src/boehm-gc/Makefile.in
++++ b/src/boehm-gc/Makefile.in
+@@ -684,7 +684,8 @@ check-TESTS: $(TESTS)
+ 	  test "$$failed" -eq 0; \
+ 	else :; fi
+ check-am: $(check_PROGRAMS)
+-	$(MAKE) $(AM_MAKEFLAGS) check-TESTS
++	: # $(MAKE) $(AM_MAKEFLAGS) check-TESTS
++	@echo target $@ disabled for Debian build.
+ check: check-recursive
+ all-am: Makefile $(LTLIBRARIES) all-multi
+ installdirs: installdirs-recursive
--- gcc-6-6.3.0.orig/debian/patches/bootstrap-no-unneeded-libs.diff
+++ gcc-6-6.3.0/debian/patches/bootstrap-no-unneeded-libs.diff
@@ -0,0 +1,1422 @@
+# DP: For bootstrap builds, don't build unneeded libstdc++ things
+# DP: (debug library, PCH headers).
+
+Index: b/src/Makefile.tpl
+===================================================================
+--- a/src/Makefile.tpl
++++ b/src/Makefile.tpl
+@@ -1060,7 +1060,9 @@
+ 	  --target=[+target_alias+] $${srcdiroption} [+ IF prev +]\
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) [+ ENDIF prev +]\
+ 	  $(STAGE[+id+]_CONFIGURE_FLAGS)[+ IF extra_configure_flags +] \
+-	  [+extra_configure_flags+][+ ENDIF extra_configure_flags +]
++	  [+extra_configure_flags+][+ ENDIF extra_configure_flags +] \
++	  [+ IF bootstrap_configure_flags +][+bootstrap_configure_flags+] \
++	  [+ ENDIF bootstrap_configure_flags +]
+ @endif [+prefix+][+module+]-bootstrap
+ [+ ENDFOR bootstrap_stage +]
+ [+ ENDIF bootstrap +]
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -117,7 +117,8 @@
+ target_modules = { module= libstdc++-v3;
+ 		   bootstrap=true;
+ 		   lib_path=src/.libs;
+-		   raw_cxx=true; };
++		   raw_cxx=true;
++		   bootstrap_configure_flags='--disable-libstdcxx-debug --disable-libstdcxx-pch'; };
+ target_modules = { module= libmudflap; lib_path=.libs; };
+ target_modules = { module= libsanitizer; lib_path=.libs; };
+ target_modules = { module= libssp; lib_path=.libs; };
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -3007,7 +3007,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stage2-bfd maybe-configure-stage2-bfd
+@@ -3040,7 +3041,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stage3-bfd maybe-configure-stage3-bfd
+@@ -3073,7 +3075,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stage4-bfd maybe-configure-stage4-bfd
+@@ -3106,7 +3109,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stageprofile-bfd maybe-configure-stageprofile-bfd
+@@ -3139,7 +3143,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stagefeedback-bfd maybe-configure-stagefeedback-bfd
+@@ -3172,7 +3177,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ 
+@@ -3879,7 +3885,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stage2-opcodes maybe-configure-stage2-opcodes
+@@ -3912,7 +3919,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stage3-opcodes maybe-configure-stage3-opcodes
+@@ -3945,7 +3953,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stage4-opcodes maybe-configure-stage4-opcodes
+@@ -3978,7 +3987,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stageprofile-opcodes maybe-configure-stageprofile-opcodes
+@@ -4011,7 +4021,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stagefeedback-opcodes maybe-configure-stagefeedback-opcodes
+@@ -4044,7 +4055,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ 
+@@ -4751,7 +4763,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stage2-binutils maybe-configure-stage2-binutils
+@@ -4784,7 +4797,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stage3-binutils maybe-configure-stage3-binutils
+@@ -4817,7 +4831,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stage4-binutils maybe-configure-stage4-binutils
+@@ -4850,7 +4865,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stageprofile-binutils maybe-configure-stageprofile-binutils
+@@ -4883,7 +4899,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stagefeedback-binutils maybe-configure-stagefeedback-binutils
+@@ -4916,7 +4933,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ 
+@@ -8696,7 +8714,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stage2-gas maybe-configure-stage2-gas
+@@ -8729,7 +8748,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stage3-gas maybe-configure-stage3-gas
+@@ -8762,7 +8782,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stage4-gas maybe-configure-stage4-gas
+@@ -8795,7 +8816,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stageprofile-gas maybe-configure-stageprofile-gas
+@@ -8828,7 +8850,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gas maybe-configure-stagefeedback-gas
+@@ -8861,7 +8884,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ 
+@@ -9568,7 +9592,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stage2-gcc maybe-configure-stage2-gcc
+@@ -9601,7 +9626,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stage3-gcc maybe-configure-stage3-gcc
+@@ -9634,7 +9660,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stage4-gcc maybe-configure-stage4-gcc
+@@ -9667,7 +9694,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stageprofile-gcc maybe-configure-stageprofile-gcc
+@@ -9700,7 +9728,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gcc maybe-configure-stagefeedback-gcc
+@@ -9733,7 +9762,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ 
+@@ -10441,7 +10471,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=none-${host_vendor}-${host_os} \
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stage2-gmp maybe-configure-stage2-gmp
+@@ -10475,7 +10506,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stage3-gmp maybe-configure-stage3-gmp
+@@ -10509,7 +10541,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stage4-gmp maybe-configure-stage4-gmp
+@@ -10543,7 +10576,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stageprofile-gmp maybe-configure-stageprofile-gmp
+@@ -10577,7 +10611,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gmp maybe-configure-stagefeedback-gmp
+@@ -10611,7 +10646,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ 
+@@ -11307,7 +11343,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stage2-mpfr maybe-configure-stage2-mpfr
+@@ -11341,7 +11378,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stage3-mpfr maybe-configure-stage3-mpfr
+@@ -11375,7 +11413,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stage4-mpfr maybe-configure-stage4-mpfr
+@@ -11409,7 +11448,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stageprofile-mpfr maybe-configure-stageprofile-mpfr
+@@ -11443,7 +11483,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stagefeedback-mpfr maybe-configure-stagefeedback-mpfr
+@@ -11477,7 +11518,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ 
+@@ -12173,7 +12215,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stage2-mpc maybe-configure-stage2-mpc
+@@ -12207,7 +12250,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stage3-mpc maybe-configure-stage3-mpc
+@@ -12241,7 +12285,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stage4-mpc maybe-configure-stage4-mpc
+@@ -12275,7 +12320,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stageprofile-mpc maybe-configure-stageprofile-mpc
+@@ -12309,7 +12355,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stagefeedback-mpc maybe-configure-stagefeedback-mpc
+@@ -12343,7 +12390,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ 
+@@ -13039,7 +13087,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stage2-isl maybe-configure-stage2-isl
+@@ -13073,7 +13122,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stage3-isl maybe-configure-stage3-isl
+@@ -13107,7 +13157,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stage4-isl maybe-configure-stage4-isl
+@@ -13141,7 +13192,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stageprofile-isl maybe-configure-stageprofile-isl
+@@ -13175,7 +13227,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stagefeedback-isl maybe-configure-stagefeedback-isl
+@@ -13209,7 +13262,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ 
+@@ -13905,7 +13959,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stage2-cloog maybe-configure-stage2-cloog
+@@ -13939,7 +13994,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stage3-cloog maybe-configure-stage3-cloog
+@@ -13973,7 +14029,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stage4-cloog maybe-configure-stage4-cloog
+@@ -14007,7 +14064,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stageprofile-cloog maybe-configure-stageprofile-cloog
+@@ -14041,7 +14099,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stagefeedback-cloog maybe-configure-stagefeedback-cloog
+@@ -14075,7 +14134,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ 
+@@ -14771,7 +14831,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stage2-libelf maybe-configure-stage2-libelf
+@@ -14805,7 +14866,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stage3-libelf maybe-configure-stage3-libelf
+@@ -14839,7 +14901,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stage4-libelf maybe-configure-stage4-libelf
+@@ -14873,7 +14936,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stageprofile-libelf maybe-configure-stageprofile-libelf
+@@ -14907,7 +14971,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libelf maybe-configure-stagefeedback-libelf
+@@ -14941,7 +15006,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ 
+@@ -15636,7 +15702,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stage2-gold maybe-configure-stage2-gold
+@@ -15669,7 +15736,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stage3-gold maybe-configure-stage3-gold
+@@ -15702,7 +15770,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stage4-gold maybe-configure-stage4-gold
+@@ -15735,7 +15804,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stageprofile-gold maybe-configure-stageprofile-gold
+@@ -15768,7 +15838,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gold maybe-configure-stagefeedback-gold
+@@ -15801,7 +15872,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ 
+@@ -16948,7 +17020,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stage2-intl maybe-configure-stage2-intl
+@@ -16981,7 +17054,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stage3-intl maybe-configure-stage3-intl
+@@ -17014,7 +17088,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stage4-intl maybe-configure-stage4-intl
+@@ -17047,7 +17122,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stageprofile-intl maybe-configure-stageprofile-intl
+@@ -17080,7 +17156,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stagefeedback-intl maybe-configure-stagefeedback-intl
+@@ -17113,7 +17190,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ 
+@@ -18685,7 +18763,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stage2-ld maybe-configure-stage2-ld
+@@ -18718,7 +18797,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stage3-ld maybe-configure-stage3-ld
+@@ -18751,7 +18831,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stage4-ld maybe-configure-stage4-ld
+@@ -18784,7 +18865,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stageprofile-ld maybe-configure-stageprofile-ld
+@@ -18817,7 +18899,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stagefeedback-ld maybe-configure-stagefeedback-ld
+@@ -18850,7 +18933,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ 
+@@ -19557,7 +19641,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stage2-libbacktrace maybe-configure-stage2-libbacktrace
+@@ -19590,7 +19675,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stage3-libbacktrace maybe-configure-stage3-libbacktrace
+@@ -19623,7 +19709,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stage4-libbacktrace maybe-configure-stage4-libbacktrace
+@@ -19656,7 +19743,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stageprofile-libbacktrace maybe-configure-stageprofile-libbacktrace
+@@ -19689,7 +19777,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libbacktrace maybe-configure-stagefeedback-libbacktrace
+@@ -19722,7 +19811,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ 
+@@ -20429,7 +20519,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stage2-libcpp maybe-configure-stage2-libcpp
+@@ -20462,7 +20553,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stage3-libcpp maybe-configure-stage3-libcpp
+@@ -20495,7 +20587,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stage4-libcpp maybe-configure-stage4-libcpp
+@@ -20528,7 +20621,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stageprofile-libcpp maybe-configure-stageprofile-libcpp
+@@ -20561,7 +20655,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libcpp maybe-configure-stagefeedback-libcpp
+@@ -20594,7 +20689,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ 
+@@ -21301,7 +21397,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stage2-libdecnumber maybe-configure-stage2-libdecnumber
+@@ -21334,7 +21431,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stage3-libdecnumber maybe-configure-stage3-libdecnumber
+@@ -21367,7 +21465,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stage4-libdecnumber maybe-configure-stage4-libdecnumber
+@@ -21400,7 +21499,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stageprofile-libdecnumber maybe-configure-stageprofile-libdecnumber
+@@ -21433,7 +21533,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libdecnumber maybe-configure-stagefeedback-libdecnumber
+@@ -21466,7 +21567,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ 
+@@ -22614,7 +22716,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stage2-libiberty maybe-configure-stage2-libiberty
+@@ -22648,7 +22751,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stage3-libiberty maybe-configure-stage3-libiberty
+@@ -22682,7 +22786,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stage4-libiberty maybe-configure-stage4-libiberty
+@@ -22716,7 +22821,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stageprofile-libiberty maybe-configure-stageprofile-libiberty
+@@ -22750,7 +22856,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libiberty maybe-configure-stagefeedback-libiberty
+@@ -22784,7 +22891,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ 
+@@ -26056,7 +26164,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stage2-zlib maybe-configure-stage2-zlib
+@@ -26089,7 +26198,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stage3-zlib maybe-configure-stage3-zlib
+@@ -26122,7 +26232,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stage4-zlib maybe-configure-stage4-zlib
+@@ -26155,7 +26266,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stageprofile-zlib maybe-configure-stageprofile-zlib
+@@ -26188,7 +26300,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stagefeedback-zlib maybe-configure-stagefeedback-zlib
+@@ -26221,7 +26334,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ 
+@@ -29919,7 +30033,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stage2-lto-plugin maybe-configure-stage2-lto-plugin
+@@ -29953,7 +30068,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stage3-lto-plugin maybe-configure-stage3-lto-plugin
+@@ -29987,7 +30103,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stage4-lto-plugin maybe-configure-stage4-lto-plugin
+@@ -30021,7 +30138,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stageprofile-lto-plugin maybe-configure-stageprofile-lto-plugin
+@@ -30055,7 +30173,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stagefeedback-lto-plugin maybe-configure-stagefeedback-lto-plugin
+@@ -30089,7 +30208,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ 
+@@ -30829,7 +30949,9 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stage2-target-libstdc++-v3 maybe-configure-stage2-target-libstdc++-v3
+@@ -30874,7 +30996,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stage3-target-libstdc++-v3 maybe-configure-stage3-target-libstdc++-v3
+@@ -30919,7 +31043,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stage4-target-libstdc++-v3 maybe-configure-stage4-target-libstdc++-v3
+@@ -30964,7 +31090,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stageprofile-target-libstdc++-v3 maybe-configure-stageprofile-target-libstdc++-v3
+@@ -31009,7 +31137,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stagefeedback-target-libstdc++-v3 maybe-configure-stagefeedback-target-libstdc++-v3
+@@ -31054,7 +31184,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ 
+@@ -33631,7 +33763,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stage2-target-libgcc maybe-configure-stage2-target-libgcc
+@@ -33676,7 +33809,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stage3-target-libgcc maybe-configure-stage3-target-libgcc
+@@ -33721,7 +33855,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stage4-target-libgcc maybe-configure-stage4-target-libgcc
+@@ -33766,7 +33901,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stageprofile-target-libgcc maybe-configure-stageprofile-target-libgcc
+@@ -33811,7 +33947,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stagefeedback-target-libgcc maybe-configure-stagefeedback-target-libgcc
+@@ -33856,7 +33993,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ 
+@@ -40928,7 +41066,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stage2-target-libgomp maybe-configure-stage2-target-libgomp
+@@ -40973,7 +41112,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stage3-target-libgomp maybe-configure-stage3-target-libgomp
+@@ -41018,7 +41158,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stage4-target-libgomp maybe-configure-stage4-target-libgomp
+@@ -41063,7 +41204,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stageprofile-target-libgomp maybe-configure-stageprofile-target-libgomp
+@@ -41108,7 +41250,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stagefeedback-target-libgomp maybe-configure-stagefeedback-target-libgomp
+@@ -41153,7 +41296,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ 
--- gcc-6-6.3.0.orig/debian/patches/canonical-cpppath.diff
+++ gcc-6-6.3.0/debian/patches/canonical-cpppath.diff
@@ -0,0 +1,36 @@
+# DP: Don't use any relative path names for the standard include paths.
+
+Index: b/src/gcc/incpath.c
+===================================================================
+--- a/src/gcc/incpath.c
++++ b/src/gcc/incpath.c
+@@ -171,6 +171,14 @@ add_standard_paths (const char *sysroot,
+ 			str = reconcat (str, str, dir_separator_str,
+ 					imultiarch, NULL);
+ 		    }
++		  {
++		    char *rp = lrealpath (str);
++		    if (rp)
++		      {
++			free (str);
++			str = rp;
++		      }
++		  }
+ 		  add_path (str, SYSTEM, p->cxx_aware, false);
+ 		}
+ 	    }
+@@ -245,6 +253,14 @@ add_standard_paths (const char *sysroot,
+ 	      else
+ 		str = reconcat (str, str, dir_separator_str, imultiarch, NULL);
+ 	    }
++	  {
++	    char *rp = lrealpath (str);
++	    if (rp)
++	      {
++		free (str);
++		str = rp;
++	      }
++	  }
+ 
+ 	  add_path (str, SYSTEM, p->cxx_aware, false);
+ 	}
--- gcc-6-6.3.0.orig/debian/patches/cmd-go-combine-gccgo-s-ld-and-ldShared-methods.diff
+++ gcc-6-6.3.0/debian/patches/cmd-go-combine-gccgo-s-ld-and-ldShared-methods.diff
@@ -0,0 +1,148 @@
+# DP: cmd/go: combine gccgo's ld() and ldShared() methods
+
+From 7fc382a2a201960826ed72413983685ac942c64c Mon Sep 17 00:00:00 2001
+From: Michael Hudson-Doyle <michael.hudson@canonical.com>
+Date: Tue, 31 May 2016 20:48:42 +1200
+Subject: [PATCH] cmd/go: combine gccgo's ld() and ldShared() methods
+
+This fixes handling of cgo flags and makes sure packages that are only
+implicitly included in the shared library are passed to the link.
+
+Fixes #15885
+
+Change-Id: I1e8a72b5314261973ca903c78834700fb113dde9
+---
+ src/cmd/go/build.go | 63 ++++++++++++++++++++++++-----------------------------
+ 1 file changed, 29 insertions(+), 34 deletions(-)
+
+Index: b/src/libgo/go/cmd/go/build.go
+===================================================================
+--- a/src/libgo/go/cmd/go/build.go
++++ b/src/libgo/go/cmd/go/build.go
+@@ -2629,7 +2629,7 @@ func (gccgoToolchain) pack(b *builder, p
+ 	return b.run(p.Dir, p.ImportPath, nil, "ar", "rc", mkAbs(objDir, afile), absOfiles)
+ }
+ 
+-func (tools gccgoToolchain) ld(b *builder, root *action, out string, allactions []*action, mainpkg string, ofiles []string) error {
++func (tools gccgoToolchain) link(b *builder, root *action, out string, allactions []*action, mainpkg string, ofiles []string, buildmode, desc string) error {
+ 	// gccgo needs explicit linking with all package dependencies,
+ 	// and all LDFLAGS from cgo dependencies.
+ 	apackagePathsSeen := make(map[string]bool)
+@@ -2638,8 +2638,12 @@ func (tools gccgoToolchain) ld(b *builde
+ 	ldflags := b.gccArchArgs()
+ 	cgoldflags := []string{}
+ 	usesCgo := false
+-	cxx := len(root.p.CXXFiles) > 0 || len(root.p.SwigCXXFiles) > 0
+-	objc := len(root.p.MFiles) > 0
++	cxx := false
++	objc := false
++	if root.p != nil {
++		cxx = len(root.p.CXXFiles) > 0 || len(root.p.SwigCXXFiles) > 0
++		objc = len(root.p.MFiles) > 0
++	}
+ 
+ 	readCgoFlags := func(flagsFile string) error {
+ 		flags, err := ioutil.ReadFile(flagsFile)
+@@ -2686,11 +2690,11 @@ func (tools gccgoToolchain) ld(b *builde
+ 		}
+ 
+ 		newarchive := newa.Name()
+-		err = b.run(b.work, root.p.ImportPath, nil, "ar", "x", newarchive, "_cgo_flags")
++		err = b.run(b.work, desc, nil, "ar", "x", newarchive, "_cgo_flags")
+ 		if err != nil {
+ 			return "", err
+ 		}
+-		err = b.run(".", root.p.ImportPath, nil, "ar", "d", newarchive, "_cgo_flags")
++		err = b.run(".", desc, nil, "ar", "d", newarchive, "_cgo_flags")
+ 		if err != nil {
+ 			return "", err
+ 		}
+@@ -2793,7 +2797,9 @@ func (tools gccgoToolchain) ld(b *builde
+ 
+ 	ldflags = append(ldflags, cgoldflags...)
+ 	ldflags = append(ldflags, envList("CGO_LDFLAGS", "")...)
+-	ldflags = append(ldflags, root.p.CgoLDFLAGS...)
++	if root.p != nil {
++		ldflags = append(ldflags, root.p.CgoLDFLAGS...)
++	}
+ 
+ 	ldflags = stringList("-Wl,-(", ldflags, "-Wl,-)")
+ 
+@@ -2808,7 +2814,7 @@ func (tools gccgoToolchain) ld(b *builde
+ 	}
+ 
+ 	var realOut string
+-	switch ldBuildmode {
++	switch buildmode {
+ 	case "exe":
+ 		if usesCgo && goos == "linux" {
+ 			ldflags = append(ldflags, "-Wl,-E")
+@@ -2843,12 +2849,14 @@ func (tools gccgoToolchain) ld(b *builde
+ 
+ 	case "c-shared":
+ 		ldflags = append(ldflags, "-shared", "-nostdlib", "-Wl,--whole-archive", "-lgolibbegin", "-Wl,--no-whole-archive", "-lgo", "-lgcc_s", "-lgcc", "-lc", "-lgcc")
++	case "shared":
++		ldflags = append(ldflags, "-zdefs", "-shared", "-nostdlib", "-lgo", "-lgcc_s", "-lgcc", "-lc")
+ 
+ 	default:
+-		fatalf("-buildmode=%s not supported for gccgo", ldBuildmode)
++		fatalf("-buildmode=%s not supported for gccgo", buildmode)
+ 	}
+ 
+-	switch ldBuildmode {
++	switch buildmode {
+ 	case "exe", "c-shared":
+ 		if cxx {
+ 			ldflags = append(ldflags, "-lstdc++")
+@@ -2858,41 +2866,27 @@ func (tools gccgoToolchain) ld(b *builde
+ 		}
+ 	}
+ 
+-	if err := b.run(".", root.p.ImportPath, nil, tools.linker(), "-o", out, ofiles, ldflags, buildGccgoflags); err != nil {
++	if err := b.run(".", desc, nil, tools.linker(), "-o", out, ofiles, ldflags, buildGccgoflags); err != nil {
+ 		return err
+ 	}
+ 
+-	switch ldBuildmode {
++	switch buildmode {
+ 	case "c-archive":
+-		if err := b.run(".", root.p.ImportPath, nil, "ar", "rc", realOut, out); err != nil {
++		if err := b.run(".", desc, nil, "ar", "rc", realOut, out); err != nil {
+ 			return err
+ 		}
+ 	}
+ 	return nil
+ }
+ 
++func (tools gccgoToolchain) ld(b *builder, root *action, out string, allactions []*action, mainpkg string, ofiles []string) error {
++	return tools.link(b, root, out, allactions, mainpkg, ofiles, ldBuildmode, root.p.ImportPath)
++}
++
+ func (tools gccgoToolchain) ldShared(b *builder, toplevelactions []*action, out string, allactions []*action) error {
+-	args := []string{"-o", out, "-shared", "-nostdlib", "-zdefs", "-Wl,--whole-archive"}
+-	for _, a := range toplevelactions {
+-		args = append(args, a.target)
+-	}
+-	args = append(args, "-Wl,--no-whole-archive", "-shared", "-nostdlib", "-lgo", "-lgcc_s", "-lgcc", "-lc")
+-	shlibs := []string{}
+-	for _, a := range allactions {
+-		if strings.HasSuffix(a.target, ".so") {
+-			shlibs = append(shlibs, a.target)
+-		}
+-	}
+-	for _, shlib := range shlibs {
+-		args = append(
+-			args,
+-			"-L"+filepath.Dir(shlib),
+-			"-Wl,-rpath="+filepath.Dir(shlib),
+-			"-l"+strings.TrimSuffix(
+-				strings.TrimPrefix(filepath.Base(shlib), "lib"),
+-				".so"))
+-	}
+-	return b.run(".", out, nil, tools.linker(), args, buildGccgoflags)
++	fakeRoot := &action{}
++	fakeRoot.deps = toplevelactions
++	return tools.link(b, fakeRoot, out, allactions, "", []string{}, "shared", out)
+ }
+ 
+ func (tools gccgoToolchain) cc(b *builder, p *Package, objdir, ofile, cfile string) error {
--- gcc-6-6.3.0.orig/debian/patches/compress-debug-check.diff
+++ gcc-6-6.3.0/debian/patches/compress-debug-check.diff
@@ -0,0 +1,88 @@
+gcc/
+
+2016-06-22  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* configure.ac (gcc_cv_as_compress_debug): Remove
+	--compress-debug-sections as extra as switch.
+	Handle gas --compress-debug-sections=type.
+	(gcc_cv_ld_compess_debug): Remove bogus ld_date check.
+	Handle gld --compress-debug-sections=type.
+	* configure: Regenerate.
+
+ 
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -4729,12 +4729,21 @@
+ fi
+ 
+ gcc_GAS_CHECK_FEATURE([compressed debug sections],
+-  gcc_cv_as_compress_debug,,[--compress-debug-sections],,
++  gcc_cv_as_compress_debug,,,,
+   [# gas compiled without zlib cannot compress debug sections and warns
+    # about it, but still exits successfully.  So check for this, too.
+    if $gcc_cv_as --compress-debug-sections -o conftest.o conftest.s 2>&1 | grep -i warning > /dev/null
+    then
+      gcc_cv_as_compress_debug=0
++   # Since binutils 2.26, gas supports --compress-debug-sections=type,
++   # defaulting to the ELF gABI format.
++   elif $gcc_cv_as --compress-debug-sections=zlib-gnu -o conftest.o conftest.s > /dev/null 2>&1
++   then
++     gcc_cv_as_compress_debug=2
++     gcc_cv_as_compress_debug_option="--compress-debug-sections"
++     gcc_cv_as_no_compress_debug_option="--nocompress-debug-sections"
++   # Before binutils 2.26, gas only supported --compress-debug-options and
++   # emitted the traditional GNU format.
+    elif $gcc_cv_as --compress-debug-sections -o conftest.o conftest.s > /dev/null 2>&1
+    then
+      gcc_cv_as_compress_debug=1
+@@ -4742,8 +4751,6 @@
+      gcc_cv_as_no_compress_debug_option="--nocompress-debug-sections"
+    else
+      gcc_cv_as_compress_debug=0
+-   # FIXME: Future gas versions will support ELF gABI style via
+-   # --compress-debug-sections[=type].
+    fi])
+ AC_DEFINE_UNQUOTED(HAVE_AS_COMPRESS_DEBUG, $gcc_cv_as_compress_debug,
+ [Define to the level of your assembler's compressed debug section support.])
+@@ -5118,6 +5125,7 @@
+ 
+ AC_MSG_CHECKING(linker for compressed debug sections)
+ # gold/gld support compressed debug sections since binutils 2.19/2.21
++# In binutils 2.26, gld gained support for the ELF gABI format.
+ if test $in_tree_ld = yes ; then
+   gcc_cv_ld_compress_debug=0
+   if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 19 -o "$gcc_cv_gld_major_version" -gt 2 \
+@@ -5124,21 +5132,23 @@
+      && test $in_tree_ld_is_elf = yes && test $ld_is_gold = yes; then
+     gcc_cv_ld_compress_debug=2
+     gcc_cv_ld_compress_debug_option="--compress-debug-sections"
++  elif test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 26 -o "$gcc_cv_gld_major_version" -gt 2 \
++     && test $in_tree_ld_is_elf = yes && test $ld_is_gold = no; then
++    gcc_cv_ld_compress_debug=3
++    gcc_cv_ld_compress_debug_option="--compress-debug-sections"
+   elif test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2 \
+      && test $in_tree_ld_is_elf = yes; then
+     gcc_cv_ld_compress_debug=1
+   fi
+ elif echo "$ld_ver" | grep GNU > /dev/null; then
+-  gcc_cv_ld_compress_debug=1
+-  if test 0"$ld_date" -lt 20050308; then
+-    if test -n "$ld_date"; then
+-      # If there was date string, but was earlier than 2005-03-08, fail
+-      gcc_cv_ld_compress_debug=0
+-    elif test "$ld_vers_major" -lt 2; then
+-      gcc_cv_ld_compress_debug=0
+-    elif test "$ld_vers_major" -eq 2 -a "$ld_vers_minor" -lt 21; then
+-      gcc_cv_ld_compress_debug=0
+-    fi
++  if test "$ld_vers_major" -lt 2 \
++     || test "$ld_vers_major" -eq 2 -a "$ld_vers_minor" -lt 21; then
++    gcc_cv_ld_compress_debug=0
++  elif test "$ld_vers_major" -eq 2 -a "$ld_vers_minor" -lt 26; then
++    gcc_cv_ld_compress_debug=1
++  else
++    gcc_cv_ld_compress_debug=3
++    gcc_cv_ld_compress_debug_option="--compress-debug-sections"
+   fi
+   if test $ld_is_gold = yes; then
+     gcc_cv_ld_compress_debug=2
--- gcc-6-6.3.0.orig/debian/patches/config-ml.diff
+++ gcc-6-6.3.0/debian/patches/config-ml.diff
@@ -0,0 +1,55 @@
+# DP: - Disable some biarch libraries for biarch builds.
+# DP: - Fix multilib builds on kernels which don't support all multilibs.
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -475,6 +475,25 @@ powerpc*-*-* | rs6000*-*-*)
+ 	;;
+ esac
+ 
++if [ -z "$biarch_multidir_names" ]; then
++  biarch_multidir_names="libiberty libstdc++-v3 libgfortran libmudflap libssp libffi libobjc libgomp"
++  echo "WARNING: biarch_multidir_names is unset. Use default value:"
++  echo "  $biarch_multidir_names"
++fi
++ml_srcbase=`basename $ml_realsrcdir`
++old_multidirs="${multidirs}"
++multidirs=""
++for x in ${old_multidirs}; do
++    case " $x " in
++	" 32 "|" n32 "|" x32 "|" 64 "|" hf "|" sf "|" m4-nofpu ")
++	case "$biarch_multidir_names" in
++	    *"$ml_srcbase"*) multidirs="${multidirs} ${x}" ;;
++	esac
++	;;
++	*) multidirs="${multidirs} ${x}" ;;
++    esac
++done
++
+ # Remove extraneous blanks from multidirs.
+ # Tests like `if [ -n "$multidirs" ]' require it.
+ multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'`
+@@ -891,9 +910,20 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	fi
+     fi
+ 
++    ml_configure_args=
++    for arg in ${ac_configure_args}
++    do
++      case $arg in
++      *CC=*)  ml_configure_args=${ml_config_env} ;;
++      *CXX=*) ml_configure_args=${ml_config_env} ;;
++      *GCJ=*) ml_configure_args=${ml_config_env} ;;
++      *) ;;
++      esac
++    done
++
+     if eval ${ml_config_env} ${ml_config_shell} ${ml_recprog} \
+ 	--with-multisubdir=${ml_dir} --with-multisrctop=${multisrctop} \
+-	"${ac_configure_args}" ${ml_config_env} ${ml_srcdiroption} ; then
++	"${ac_configure_args}" ${ml_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then
+       true
+     else
+       exit 1
--- gcc-6-6.3.0.orig/debian/patches/cross-biarch.diff
+++ gcc-6-6.3.0/debian/patches/cross-biarch.diff
@@ -0,0 +1,91 @@
+# DP: Fix the location of target's libs in cross-build for biarch
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -533,7 +533,13 @@ multi-do:
+ 	    else \
+ 	      if [ -d ../$${dir}/$${lib} ]; then \
+ 		flags=`echo $$i | sed -e 's/^[^;]*;//' -e 's/@/ -/g'`; \
+-		if (cd ../$${dir}/$${lib}; $(MAKE) $(FLAGS_TO_PASS) \
++		libsuffix_="$${dir}"; \
++		if [ "$${dir}" = "n32" ]; then libsuffix_=32; fi; \
++		if [ -n "$$($${compiler} -v 2>&1 |grep '^Target: mips')" ] && [ "$${dir}" = "32" ]; then libsuffix_=o32; fi; \
++		if (cd ../$${dir}/$${lib}; $(MAKE) $(subst \
++				-B$(build_tooldir)/lib/, \
++				-B$(build_tooldir)/lib$${libsuffix_}/, \
++				$(FLAGS_TO_PASS)) \
+ 				CFLAGS="$(CFLAGS) $${flags}" \
+ 				CCASFLAGS="$(CCASFLAGS) $${flags}" \
+ 				FCFLAGS="$(FCFLAGS) $${flags}" \
+@@ -786,6 +792,15 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	GFORTRAN_=$GFORTRAN' '
+ 	GOC_=$GOC' '
+     else
++	if [ "${ml_dir}" = "." ]; then
++		FILTER_="s!X\\(.*\\)!\\1!p"
++	elif [ "${ml_dir}" = "n32" ]; then # mips n32 -> lib32
++		FILTER_="s!X\\(.*\\)/!\\132/!p"
++	elif [ "${ml_dir}" = "32" ] && [ "$(echo ${host} |grep '^mips')" ]; then # mips o32 -> libo32
++		FILTER_="s!X\\(.*\\)/!\\1o32/!p"
++	else
++		FILTER_="s!X\\(.*\\)/!\\1${ml_dir}/!p"
++	fi
+ 	# Create a regular expression that matches any string as long
+ 	# as ML_POPDIR.
+ 	popdir_rx=`echo "${ML_POPDIR}" | sed 's,.,.,g'`
+@@ -794,6 +809,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    CC_="${CC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\1/p"`' ' ;;
++	  -B*/lib/)
++	    CC_="${CC_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    CC_="${CC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -806,6 +823,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    CXX_="${CXX_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    CXX_="${CXX_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    CXX_="${CXX_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -818,6 +837,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    F77_="${F77_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    F77_="${F77_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    F77_="${F77_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -830,6 +851,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GCJ_="${GCJ_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GCJ_="${GCJ_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GCJ_="${GCJ_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -842,6 +865,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GFORTRAN_="${GFORTRAN_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GFORTRAN_="${GFORTRAN_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GFORTRAN_="${GFORTRAN_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -854,6 +879,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GOC_="${GOC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GOC_="${GOC_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GOC_="${GOC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
--- gcc-6-6.3.0.orig/debian/patches/cross-fixes.diff
+++ gcc-6-6.3.0/debian/patches/cross-fixes.diff
@@ -0,0 +1,81 @@
+# DP: Fix the linker error when creating an xcc for ia64
+
+---
+ gcc/config/ia64/fde-glibc.c     |    3 +++
+ gcc/config/ia64/unwind-ia64.c   |    3 ++-
+ gcc/unwind-compat.c             |    2 ++
+ gcc/unwind-generic.h            |    2 ++
+ 6 files changed, 14 insertions(+), 1 deletions(-)
+
+Index: b/src/libgcc/config/ia64/fde-glibc.c
+===================================================================
+--- a/src/libgcc/config/ia64/fde-glibc.c
++++ b/src/libgcc/config/ia64/fde-glibc.c
+@@ -28,6 +28,7 @@
+ #ifndef _GNU_SOURCE
+ #define _GNU_SOURCE 1
+ #endif
++#ifndef inhibit_libc
+ #include "config.h"
+ #include <stddef.h>
+ #include <stdlib.h>
+@@ -159,3 +160,5 @@ _Unwind_FindTableEntry (void *pc, unw_wo
+ 
+   return data.ret;
+ }
++
++#endif
+Index: b/src/libgcc/config/ia64/unwind-ia64.c
+===================================================================
+--- a/src/libgcc/config/ia64/unwind-ia64.c
++++ b/src/libgcc/config/ia64/unwind-ia64.c
+@@ -26,6 +26,7 @@
+    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+    <http://www.gnu.org/licenses/>.  */
+ 
++#ifndef inhibit_libc
+ #include "tconfig.h"
+ #include "tsystem.h"
+ #include "coretypes.h"
+@@ -2466,3 +2467,4 @@ alias (_Unwind_SetIP);
+ #endif
+ 
+ #endif
++#endif
+Index: b/src/libgcc/unwind-compat.c
+===================================================================
+--- a/src/libgcc/unwind-compat.c
++++ b/src/libgcc/unwind-compat.c
+@@ -23,6 +23,7 @@
+    <http://www.gnu.org/licenses/>.  */
+ 
+ #if defined (USE_GAS_SYMVER) && defined (USE_LIBUNWIND_EXCEPTIONS)
++#ifndef inhibit_libc
+ #include "tconfig.h"
+ #include "tsystem.h"
+ #include "unwind.h"
+@@ -207,3 +208,4 @@ _Unwind_SetIP (struct _Unwind_Context *c
+ }
+ symver (_Unwind_SetIP, GCC_3.0);
+ #endif
++#endif
+Index: b/src/libgcc/unwind-generic.h
+===================================================================
+--- a/src/libgcc/unwind-generic.h
++++ b/src/libgcc/unwind-generic.h
+@@ -221,6 +221,7 @@ _Unwind_SjLj_Resume_or_Rethrow (struct _
+    compatible with the standard ABI for IA-64, we inline these.  */
+ 
+ #ifdef __ia64__
++#ifndef inhibit_libc
+ static inline _Unwind_Ptr
+ _Unwind_GetDataRelBase (struct _Unwind_Context *_C)
+ {
+@@ -237,6 +238,7 @@ _Unwind_GetTextRelBase (struct _Unwind_C
+ 
+ /* @@@ Retrieve the Backing Store Pointer of the given context.  */
+ extern _Unwind_Word _Unwind_GetBSP (struct _Unwind_Context *);
++#endif /* inhibit_libc */
+ #else
+ extern _Unwind_Ptr _Unwind_GetDataRelBase (struct _Unwind_Context *);
+ extern _Unwind_Ptr _Unwind_GetTextRelBase (struct _Unwind_Context *);
--- gcc-6-6.3.0.orig/debian/patches/cross-install-location.diff
+++ gcc-6-6.3.0/debian/patches/cross-install-location.diff
@@ -0,0 +1,409 @@
+Index: b/src/fixincludes/Makefile.in
+===================================================================
+--- a/src/fixincludes/Makefile.in
++++ b/src/fixincludes/Makefile.in
+@@ -52,9 +52,9 @@ target_noncanonical:=@target_noncanonica
+ gcc_version := $(shell cat $(srcdir)/../gcc/BASE-VER)
+ 
+ # Directory in which the compiler finds libraries etc.
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ # Directory in which the compiler finds executables
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ # Where our executable files go
+ itoolsdir = $(libexecsubdir)/install-tools
+ # Where our data files go
+Index: b/src/libgfortran/Makefile.in
+===================================================================
+--- a/src/libgfortran/Makefile.in
++++ b/src/libgfortran/Makefile.in
+@@ -604,12 +604,12 @@ libgfortran_la_LDFLAGS = -version-info `
+ 
+ libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP)
+ cafexeclib_LTLIBRARIES = libcaf_single.la
+-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+ libcaf_single_la_SOURCES = caf/single.c
+ libcaf_single_la_LDFLAGS = -static
+ libcaf_single_la_DEPENDENCIES = caf/libcaf.h
+ libcaf_single_la_LINK = $(LINK) $(libcaf_single_la_LDFLAGS)
+-@IEEE_SUPPORT_TRUE@fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
++@IEEE_SUPPORT_TRUE@fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
+ @IEEE_SUPPORT_TRUE@nodist_finclude_HEADERS = ieee_arithmetic.mod ieee_exceptions.mod ieee_features.mod
+ AM_CPPFLAGS = -iquote$(srcdir)/io -I$(srcdir)/$(MULTISRCTOP)../gcc \
+ 	      -I$(srcdir)/$(MULTISRCTOP)../gcc/config $(LIBQUADINCLUDE) \
+Index: b/src/libgfortran/Makefile.am
+===================================================================
+--- a/src/libgfortran/Makefile.am
++++ b/src/libgfortran/Makefile.am
+@@ -43,14 +43,14 @@ libgfortran_la_LDFLAGS = -version-info `
+ libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP)
+ 
+ cafexeclib_LTLIBRARIES = libcaf_single.la
+-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+ libcaf_single_la_SOURCES = caf/single.c
+ libcaf_single_la_LDFLAGS = -static
+ libcaf_single_la_DEPENDENCIES = caf/libcaf.h
+ libcaf_single_la_LINK = $(LINK) $(libcaf_single_la_LDFLAGS)
+ 
+ if IEEE_SUPPORT
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
+ nodist_finclude_HEADERS = ieee_arithmetic.mod ieee_exceptions.mod ieee_features.mod
+ endif
+ 
+Index: b/src/lto-plugin/Makefile.in
+===================================================================
+--- a/src/lto-plugin/Makefile.in
++++ b/src/lto-plugin/Makefile.in
+@@ -255,7 +255,7 @@ with_libiberty = @with_libiberty@
+ ACLOCAL_AMFLAGS = -I .. -I ../config
+ AUTOMAKE_OPTIONS = no-dependencies
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+-libexecsubdir := $(libexecdir)/gcc/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
++libexecsubdir := $(libexecdir)/gcc-cross/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
+ AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS)
+ AM_CFLAGS = @ac_lto_plugin_warn_cflags@
+ AM_LDFLAGS = @ac_lto_plugin_ldflags@
+Index: b/src/lto-plugin/Makefile.am
+===================================================================
+--- a/src/lto-plugin/Makefile.am
++++ b/src/lto-plugin/Makefile.am
+@@ -5,7 +5,7 @@ AUTOMAKE_OPTIONS = no-dependencies
+ 
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+ target_noncanonical := @target_noncanonical@
+-libexecsubdir := $(libexecdir)/gcc/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
++libexecsubdir := $(libexecdir)/gcc-cross/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
+ 
+ AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS)
+ AM_CFLAGS = @ac_lto_plugin_warn_cflags@
+Index: b/src/libitm/Makefile.in
+===================================================================
+--- a/src/libitm/Makefile.in
++++ b/src/libitm/Makefile.in
+@@ -334,8 +334,8 @@ SUBDIRS = testsuite
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+ abi_version = -fabi-version=4
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir)
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ AM_CPPFLAGS = $(addprefix -I, $(search_path))
+ AM_CFLAGS = $(XCFLAGS)
+ AM_CXXFLAGS = $(XCFLAGS) -std=gnu++0x -funwind-tables -fno-exceptions \
+Index: b/src/libitm/Makefile.am
+===================================================================
+--- a/src/libitm/Makefile.am
++++ b/src/libitm/Makefile.am
+@@ -11,8 +11,8 @@ abi_version = -fabi-version=4
+ config_path = @config_path@
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir)
+ 
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ vpath % $(strip $(search_path))
+ 
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -4179,7 +4179,7 @@ process_command (unsigned int decoded_op
+ 	 GCC_EXEC_PREFIX is typically a directory name with a trailing
+ 	 / (which is ignored by make_relative_prefix), so append a
+ 	 program name.  */
+-      char *tmp_prefix = concat (gcc_exec_prefix, "gcc", NULL);
++      char *tmp_prefix = concat (gcc_exec_prefix, "gcc-cross", NULL);
+       gcc_libexec_prefix = get_relative_prefix (tmp_prefix,
+ 						standard_exec_prefix,
+ 						standard_libexec_prefix);
+@@ -4205,15 +4205,15 @@ process_command (unsigned int decoded_op
+     {
+       int len = strlen (gcc_exec_prefix);
+ 
+-      if (len > (int) sizeof ("/lib/gcc/") - 1
++      if (len > (int) sizeof ("/lib/gcc-cross/") - 1
+ 	  && (IS_DIR_SEPARATOR (gcc_exec_prefix[len-1])))
+ 	{
+-	  temp = gcc_exec_prefix + len - sizeof ("/lib/gcc/") + 1;
++	  temp = gcc_exec_prefix + len - sizeof ("/lib/gcc-cross/") + 1;
+ 	  if (IS_DIR_SEPARATOR (*temp)
+ 	      && filename_ncmp (temp + 1, "lib", 3) == 0
+ 	      && IS_DIR_SEPARATOR (temp[4])
+-	      && filename_ncmp (temp + 5, "gcc", 3) == 0)
+-	    len -= sizeof ("/lib/gcc/") - 1;
++	      && filename_ncmp (temp + 5, "gcc-cross", 3) == 0)
++	    len -= sizeof ("/lib/gcc-cross/") - 1;
+ 	}
+ 
+       set_std_prefix (gcc_exec_prefix, len);
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -592,9 +592,9 @@ libexecdir = @libexecdir@
+ # --------
+ 
+ # Directory in which the compiler finds libraries etc.
+-libsubdir = $(libdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
++libsubdir = $(libdir)/gcc-cross/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
+ # Directory in which the compiler finds executables
+-libexecsubdir = $(libexecdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
++libexecsubdir = $(libexecdir)/gcc-cross/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
+ # Directory in which all plugin resources are installed
+ plugin_resourcesdir = $(libsubdir)/plugin
+  # Directory in which plugin headers are installed
+@@ -2017,8 +2017,8 @@ prefix.o: $(FULLVER)
+ 
+ DRIVER_DEFINES = \
+   -DSTANDARD_STARTFILE_PREFIX=\"$(unlibsubdir)/\" \
+-  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+-  -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc/\" \
++  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \
++  -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc-cross/\" \
+   -DDEFAULT_TARGET_VERSION=\"$(BASEVER_c)\" \
+   -DDEFAULT_TARGET_FULL_VERSION=\"$(FULLVER_c)\" \
+   -DDEFAULT_REAL_TARGET_MACHINE=\"$(real_target_noncanonical)\" \
+@@ -2671,7 +2671,7 @@ PREPROCESSOR_DEFINES = \
+   -DTOOL_INCLUDE_DIR=\"$(gcc_tooldir)/include\" \
+   -DNATIVE_SYSTEM_HEADER_DIR=\"$(NATIVE_SYSTEM_HEADER_DIR)\" \
+   -DPREFIX=\"$(prefix)/\" \
+-  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
++  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+ CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(FULLVER_s)
+Index: b/src/libssp/Makefile.in
+===================================================================
+--- a/src/libssp/Makefile.in
++++ b/src/libssp/Makefile.in
+@@ -287,7 +287,7 @@ gcc_version := $(shell cat $(top_srcdir)
+ @LIBSSP_USE_SYMVER_SUN_TRUE@@LIBSSP_USE_SYMVER_TRUE@version_dep = ssp.map-sun
+ AM_CFLAGS = -Wall
+ toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la
+-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include
++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include
+ nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h
+ libssp_la_SOURCES = \
+ 	ssp.c gets-chk.c memcpy-chk.c memmove-chk.c mempcpy-chk.c \
+Index: b/src/libssp/Makefile.am
+===================================================================
+--- a/src/libssp/Makefile.am
++++ b/src/libssp/Makefile.am
+@@ -39,7 +39,7 @@ AM_CFLAGS = -Wall
+ toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la
+ 
+ target_noncanonical = @target_noncanonical@
+-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include
++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include
+ nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h
+ 
+ libssp_la_SOURCES = \
+Index: b/src/libquadmath/Makefile.in
+===================================================================
+--- a/src/libquadmath/Makefile.in
++++ b/src/libquadmath/Makefile.in
+@@ -354,7 +354,7 @@ AUTOMAKE_OPTIONS = 1.8 foreign
+ 
+ @BUILD_LIBQUADMATH_TRUE@libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD)
+ @BUILD_LIBQUADMATH_TRUE@nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h
+-@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ @BUILD_LIBQUADMATH_TRUE@libquadmath_la_SOURCES = \
+ @BUILD_LIBQUADMATH_TRUE@  math/x2y2m1q.c math/isinf_nsq.c math/acoshq.c math/fmodq.c \
+ @BUILD_LIBQUADMATH_TRUE@  math/acosq.c math/frexpq.c \
+Index: b/src/libquadmath/Makefile.am
+===================================================================
+--- a/src/libquadmath/Makefile.am
++++ b/src/libquadmath/Makefile.am
+@@ -41,7 +41,7 @@ libquadmath_la_LDFLAGS = -version-info `
+ libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD)
+ 
+ nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ libquadmath_la_SOURCES = \
+   math/x2y2m1q.c math/isinf_nsq.c math/acoshq.c math/fmodq.c \
+Index: b/src/libobjc/Makefile.in
+===================================================================
+--- a/src/libobjc/Makefile.in
++++ b/src/libobjc/Makefile.in
+@@ -50,7 +50,7 @@ top_builddir = .
+ -include ../boehm-gc/threads.mk
+ 
+ libdir = $(exec_prefix)/lib
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ 
+ # Multilib support variables.
+ MULTISRCTOP =
+Index: b/src/libada/Makefile.in
+===================================================================
+--- a/src/libada/Makefile.in
++++ b/src/libada/Makefile.in
+@@ -68,7 +68,7 @@ GCC_DIR=$(MULTIBUILDTOP)../../$(host_sub
+ 
+ target_noncanonical:=@target_noncanonical@
+ version := $(shell cat $(srcdir)/../gcc/BASE-VER)
+-libsubdir := $(libdir)/gcc/$(target_noncanonical)/$(version)$(MULTISUBDIR)
++libsubdir := $(libdir)/gcc-cross/$(target_noncanonical)/$(version)$(MULTISUBDIR)
+ ADA_RTS_DIR=$(GCC_DIR)/ada/rts$(subst /,_,$(MULTISUBDIR))
+ ADA_RTS_SUBDIR=./rts$(subst /,_,$(MULTISUBDIR))
+ 
+Index: b/src/libgomp/Makefile.in
+===================================================================
+--- a/src/libgomp/Makefile.in
++++ b/src/libgomp/Makefile.in
+@@ -386,8 +386,8 @@ gcc_version := $(shell cat $(top_srcdir)
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) \
+ 	      $(top_srcdir)/../include
+ 
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ AM_CPPFLAGS = $(addprefix -I, $(search_path))
+ AM_CFLAGS = $(XCFLAGS)
+ AM_LDFLAGS = $(XLDFLAGS) $(SECTION_LDFLAGS) $(OPT_LDFLAGS)
+Index: b/src/libgomp/Makefile.am
+===================================================================
+--- a/src/libgomp/Makefile.am
++++ b/src/libgomp/Makefile.am
+@@ -10,8 +10,8 @@ config_path = @config_path@
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) \
+ 	      $(top_srcdir)/../include
+ 
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ vpath % $(strip $(search_path))
+ 
+Index: b/src/libgcc/Makefile.in
+===================================================================
+--- a/src/libgcc/Makefile.in
++++ b/src/libgcc/Makefile.in
+@@ -186,7 +186,7 @@ STRIP = @STRIP@
+ STRIP_FOR_TARGET = $(STRIP)
+ 
+ # Directory in which the compiler finds libraries etc.
+-libsubdir = $(libdir)/gcc/$(real_host_noncanonical)/$(version)@accel_dir_suffix@
++libsubdir = $(libdir)/gcc-cross/$(real_host_noncanonical)/$(version)@accel_dir_suffix@
+ # Used to install the shared libgcc.
+ slibdir = @slibdir@
+ # Maybe used for DLLs on Windows targets.
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -825,8 +825,8 @@ write_entries_to_file = $(shell rm -f $(
+ 
+ 
+ # This is required by TL_AC_GXX_INCLUDE_DIR.
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ toolexeclib_LTLIBRARIES = libgcj.la libgij.la libgcj-tools.la \
+ 	$(am__append_2) $(am__append_3) $(am__append_4)
+ toolexecmainlib_DATA = libgcj.spec
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -35,9 +35,9 @@ write_entries_to_file = $(shell rm -f $(
+ target_noncanonical = @target_noncanonical@
+ 
+ # This is required by TL_AC_GXX_INCLUDE_DIR.
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ 
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ 
+ ##
+ ## What gets installed, and where.
+Index: b/src/libffi/include/Makefile.am
+===================================================================
+--- a/src/libffi/include/Makefile.am
++++ b/src/libffi/include/Makefile.am
+@@ -8,6 +8,6 @@ EXTRA_DIST=ffi.h.in
+ 
+ # Where generated headers like ffitarget.h get installed.
+ gcc_version   := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ toollibffi_HEADERS = ffi.h ffitarget.h
+Index: b/src/libffi/include/Makefile.in
+===================================================================
+--- a/src/libffi/include/Makefile.in
++++ b/src/libffi/include/Makefile.in
+@@ -251,7 +251,7 @@ EXTRA_DIST = ffi.h.in
+ 
+ # Where generated headers like ffitarget.h get installed.
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ toollibffi_HEADERS = ffi.h ffitarget.h
+ all: all-am
+ 
+Index: b/src/libcc1/Makefile.am
+===================================================================
+--- a/src/libcc1/Makefile.am
++++ b/src/libcc1/Makefile.am
+@@ -35,7 +35,7 @@ libiberty = $(if $(wildcard $(libiberty_
+ 	    $(Wc)$(libiberty_normal)))
+ libiberty_dep = $(patsubst $(Wc)%,%,$(libiberty))
+ 
+-plugindir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/plugin
++plugindir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/plugin
+ cc1libdir = $(libdir)/$(libsuffix)
+ 
+ if ENABLE_PLUGIN
+Index: b/src/libcc1/Makefile.in
+===================================================================
+--- a/src/libcc1/Makefile.in
++++ b/src/libcc1/Makefile.in
+@@ -290,7 +290,7 @@ libiberty = $(if $(wildcard $(libiberty_
+ 	    $(Wc)$(libiberty_normal)))
+ 
+ libiberty_dep = $(patsubst $(Wc)%,%,$(libiberty))
+-plugindir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/plugin
++plugindir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/plugin
+ cc1libdir = $(libdir)/$(libsuffix)
+ @ENABLE_PLUGIN_TRUE@plugin_LTLIBRARIES = libcc1plugin.la
+ @ENABLE_PLUGIN_TRUE@cc1lib_LTLIBRARIES = libcc1.la
+Index: b/src/libsanitizer/Makefile.am
+===================================================================
+--- a/src/libsanitizer/Makefile.am
++++ b/src/libsanitizer/Makefile.am
+@@ -1,6 +1,6 @@
+ ACLOCAL_AMFLAGS = -I .. -I ../config
+ 
+-sanincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include/sanitizer
++sanincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include/sanitizer
+ 
+ nodist_saninclude_HEADERS =
+ 
+Index: b/src/libsanitizer/Makefile.in
+===================================================================
+--- a/src/libsanitizer/Makefile.in
++++ b/src/libsanitizer/Makefile.in
+@@ -285,7 +285,7 @@ top_build_prefix = @top_build_prefix@
+ top_builddir = @top_builddir@
+ top_srcdir = @top_srcdir@
+ ACLOCAL_AMFLAGS = -I .. -I ../config
+-sanincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include/sanitizer
++sanincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include/sanitizer
+ nodist_saninclude_HEADERS = $(am__append_1)
+ @SANITIZER_SUPPORTED_TRUE@SUBDIRS = sanitizer_common $(am__append_2) \
+ @SANITIZER_SUPPORTED_TRUE@	$(am__append_3) lsan asan ubsan \
--- gcc-6-6.3.0.orig/debian/patches/cross-no-locale-include.diff
+++ gcc-6-6.3.0/debian/patches/cross-no-locale-include.diff
@@ -0,0 +1,17 @@
+# DP: Don't add /usr/local/include for cross compilers. Assume that
+# DP: /usr/include is ready for multiarch, but not /usr/local/include.
+
+--- a/src/gcc/cppdefault.c
++++ b/src/gcc/cppdefault.c
+@@ -66,8 +66,11 @@
+ #ifdef LOCAL_INCLUDE_DIR
+     /* /usr/local/include comes before the fixincluded header files.  */
+     { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 },
++#if 0
++    /* Unsafe to assume that /usr/local/include is ready for multiarch.  */
+     { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
+ #endif
++#endif
+ #ifdef PREFIX_INCLUDE_DIR
+     { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0 },
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/disable-gdc-tests.diff
+++ gcc-6-6.3.0/debian/patches/disable-gdc-tests.diff
@@ -0,0 +1,16 @@
+# DP: Disable D tests, hang on many buildds
+
+Index: b/src/gcc/d/Make-lang.in
+===================================================================
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -284,6 +284,6 @@ d.stagefeedback: stagefeedback-start
+ # check targets.  However, our DejaGNU framework requires 'check-gdc' as its
+ # entry point.  We feed the former to the latter here.
+ check-d: check-gdc
+-lang_checks += check-gdc
+-lang_checks_parallelized += check-gdc
+-check_gdc_parallelize = 10
++#lang_checks += check-gdc
++#lang_checks_parallelized += check-gdc
++#check_gdc_parallelize = 10
--- gcc-6-6.3.0.orig/debian/patches/g++-multiarch-incdir.diff
+++ gcc-6-6.3.0/debian/patches/g++-multiarch-incdir.diff
@@ -0,0 +1,119 @@
+# DP: Use /usr/include/<multiarch>/c++/4.x as the include directory
+# DP: for host dependent c++ header files.
+
+Index: b/src/libstdc++-v3/include/Makefile.am
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.am
++++ b/src/libstdc++-v3/include/Makefile.am
+@@ -911,7 +911,7 @@ endif
+ 
+ host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
+ host_builddir = ./${host_alias}/bits
+-host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits
++host_installdir = $(if $(shell $(CC) -print-multiarch),/usr/include/$(shell $(filter-out -m%,$(CC)) -print-multiarch)/c++/$(notdir ${gxx_include_dir})$(MULTISUBDIR)/bits,${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits)
+ host_headers = \
+ 	${host_srcdir}/ctype_base.h \
+ 	${host_srcdir}/ctype_inline.h \
+Index: b/src/libstdc++-v3/include/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.in
++++ b/src/libstdc++-v3/include/Makefile.in
+@@ -1193,7 +1193,7 @@ profile_impl_headers = \
+ @GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE@c_compatibility_headers_extra = ${c_compatibility_headers}
+ host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
+ host_builddir = ./${host_alias}/bits
+-host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits
++host_installdir = $(if $(shell $(CC) -print-multiarch),/usr/include/$(shell $(filter-out -m%,$(CC)) -print-multiarch)/c++/$(notdir ${gxx_include_dir})$(MULTISUBDIR)/bits,${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits)
+ host_headers = \
+ 	${host_srcdir}/ctype_base.h \
+ 	${host_srcdir}/ctype_inline.h \
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -1139,6 +1139,7 @@ FLAGS_TO_PASS = \
+ 	"prefix=$(prefix)" \
+ 	"local_prefix=$(local_prefix)" \
+ 	"gxx_include_dir=$(gcc_gxx_include_dir)" \
++	"gxx_tool_include_dir=$(gcc_gxx_tool_include_dir)" \
+ 	"build_tooldir=$(build_tooldir)" \
+ 	"gcc_tooldir=$(gcc_tooldir)" \
+ 	"bindir=$(bindir)" \
+@@ -1636,6 +1637,14 @@ ifneq ($(xmake_file),)
+ include $(xmake_file)
+ endif
+ 
++# Directory in which the compiler finds target-dependent g++ includes.
++ifneq ($(call if_multiarch,non-empty),)
++  gcc_gxx_tool_include_dir = $(libsubdir)/$(libsubdir_to_prefix)include/$(MULTIARCH_DIRNAME)/c++/$(BASEVER_c)
++else
++  gcc_gxx_tool_include_dir = $(gcc_gxx_include_dir)/$(target_noncanonical)
++endif
++
++
+ # all-tree.def includes all the tree.def files.
+ all-tree.def: s-alltree; @true
+ s-alltree: Makefile
+@@ -2673,7 +2682,7 @@ PREPROCESSOR_DEFINES = \
+   -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
+   -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
+   -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
+-  -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/$(target_noncanonical)\" \
++  -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_tool_include_dir)\" \
+   -DGPLUSPLUS_BACKWARD_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/backward\" \
+   -DLOCAL_INCLUDE_DIR=\"$(local_includedir)\" \
+   -DCROSS_INCLUDE_DIR=\"$(CROSS_SYSTEM_HEADER_DIR)\" \
+Index: b/src/gcc/cppdefault.c
+===================================================================
+--- a/src/gcc/cppdefault.c
++++ b/src/gcc/cppdefault.c
+@@ -49,6 +49,8 @@ const struct default_include cpp_include
+     /* Pick up GNU C++ target-dependent include files.  */
+     { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1,
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 },
++    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1,
++      GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 2 },
+ #endif
+ #ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR
+     /* Pick up GNU C++ backward and deprecated include files.  */
+Index: b/src/gcc/incpath.c
+===================================================================
+--- a/src/gcc/incpath.c
++++ b/src/gcc/incpath.c
+@@ -158,6 +158,18 @@ add_standard_paths (const char *sysroot,
+ 			}
+ 		      str = reconcat (str, str, dir_separator_str,
+ 				      imultiarch, NULL);
++		      if (p->cplusplus && strstr (str, "/c++/"))
++			{
++			  char *suffix = strstr (str, "/c++/");
++			  *suffix++ = '\0';
++			  suffix = xstrdup (suffix);
++			  str = reconcat (str, str, dir_separator_str,
++					  imultiarch,
++					  dir_separator_str, suffix, NULL);
++			}
++		      else
++			str = reconcat (str, str, dir_separator_str,
++					imultiarch, NULL);
+ 		    }
+ 		  add_path (str, SYSTEM, p->cxx_aware, false);
+ 		}
+@@ -222,7 +234,16 @@ add_standard_paths (const char *sysroot,
+ 		  free (str);
+ 		  continue;
+ 		}
+-	      str = reconcat (str, str, dir_separator_str, imultiarch, NULL);
++	      if (p->cplusplus && strstr (str, "/c++/"))
++		{
++		  char *suffix = strstr (str, "/c++/");
++		  *suffix++ = '\0';
++		  suffix = xstrdup (suffix);
++		  str = reconcat (str, str, dir_separator_str, imultiarch,
++				  dir_separator_str, suffix, NULL);
++		}
++	      else
++		str = reconcat (str, str, dir_separator_str, imultiarch, NULL);
+ 	    }
+ 
+ 	  add_path (str, SYSTEM, p->cxx_aware, false);
--- gcc-6-6.3.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH-2-doc.diff
+++ gcc-6-6.3.0/debian/patches/gcc-SOURCE_DATE_EPOCH-2-doc.diff
@@ -0,0 +1,31 @@
+gcc/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* doc/cppenv.texi: Note that the `%s` in `date` is a non-standard
+	extension.
+
+diff --git a/gcc/doc/cppenv.texi b/gcc/doc/cppenv.texi
+index e958e93..8cefd52 100644
+--- a/src/gcc/doc/cppenv.texi
++++ b/src/gcc/doc/cppenv.texi
+@@ -81,7 +81,6 @@ main input file is omitted.
+ @end ifclear
+ 
+ @item SOURCE_DATE_EPOCH
+-
+ If this variable is set, its value specifies a UNIX timestamp to be
+ used in replacement of the current date and time in the @code{__DATE__}
+ and @code{__TIME__} macros, so that the embedded timestamps become
+@@ -89,8 +88,9 @@ reproducible.
+ 
+ The value of @env{SOURCE_DATE_EPOCH} must be a UNIX timestamp,
+ defined as the number of seconds (excluding leap seconds) since
+-01 Jan 1970 00:00:00 represented in ASCII, identical to the output of
+-@samp{@command{date +%s}}.
++01 Jan 1970 00:00:00 represented in ASCII; identical to the output of
++@samp{@command{date +%s}} on GNU/Linux and other systems that support the
++@code{%s} extension in the @code{date} command.
+ 
+ The value should be a known timestamp such as the last modification
+ time of the source or package and it should be set by the build
--- gcc-6-6.3.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH-2.diff
+++ gcc-6-6.3.0/debian/patches/gcc-SOURCE_DATE_EPOCH-2.diff
@@ -0,0 +1,378 @@
+gcc/c-family/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* c-common.c (get_source_date_epoch): Rename to
+	cb_get_source_date_epoch.
+	* c-common.c (cb_get_source_date_epoch): Use a single generic erorr
+	message when the parsing fails.  Use error_at instead of fatal_error.
+	* c-common.h (get_source_date_epoch): Rename to
+	cb_get_source_date_epoch.
+	* c-common.h (cb_get_source_date_epoch): Prototype.
+	* c-common.h (MAX_SOURCE_DATE_EPOCH): Define.
+	* c-common.h (c_omp_region_type): Remove trailing comma.
+	* c-lex.c (init_c_lex): Set cb->get_source_date_epoch callback.
+	* c-lex.c (c_lex_with_flags): Remove initialization of
+	pfile->source_date_epoch.
+
+gcc/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* doc/cppenv.texi: Note that the `%s` in `date` is a non-standard
+	extension.
+	* gcc.c (driver_handle_option): Call set_source_date_epoch_envvar.
+	* gcc.c (set_source_date_epoch_envvar): New function, sets
+	the SOURCE_DATE_EPOCH environment variable to the current time.
+
+gcc/testsuite/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* gcc.dg/cpp/source_date_epoch-1.c: New file, test the proper
+	behaviour of the macros __DATE__ and __TIME__ when SOURCE_DATE_EPOCH
+	env var is set.
+	* gcc.dg/cpp/source_date_epoch-2.c: New file, test the error output
+	when parsing the SOURCE_DATE_EPOCH env var, and make sure it is only
+	shown once.
+	* lib/gcc-dg.exp (dg-set-compiler-env-var): New function, set env vars
+	during compilation.
+	* lib/gcc-dg.exp (restore-compiler-env-var): New function, restore env
+	vars set by dg-set-compiler-env-var.
+
+libcpp/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* include/cpplib.h (cpp_callbacks): Add get_source_date_epoch
+	callback.
+	* include/cpplib.h (cpp_init_source_date_epoch): Remove prototype.
+	* init.c (cpp_init_source_date_epoch): Remove function.
+	* init.c (cpp_create_reader): Initialize pfile->source_date_epoch.
+	* internal.h (cpp_reader): Extend comment about source_date_epoch.
+	* macro.c (_cpp_builtin_macro_text): Use get_source_date_epoch
+	callback only once, read pfile->source_date_epoch on future passes.
+	Check that get_source_date_epoch callback is not NULL.
+
+Index: b/src/gcc/c-family/c-common.c
+===================================================================
+--- a/src/gcc/c-family/c-common.c
++++ b/src/gcc/c-family/c-common.c
+@@ -12746,8 +12746,9 @@ valid_array_size_p (location_t loc, tree
+ /* Read SOURCE_DATE_EPOCH from environment to have a deterministic
+    timestamp to replace embedded current dates to get reproducible
+    results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++
+ time_t
+-get_source_date_epoch ()
++cb_get_source_date_epoch (cpp_reader *pfile ATTRIBUTE_UNUSED)
+ {
+   char *source_date_epoch;
+   long long epoch;
+@@ -12759,19 +12760,14 @@ get_source_date_epoch ()
+ 
+   errno = 0;
+   epoch = strtoll (source_date_epoch, &endptr, 10);
+-  if ((errno == ERANGE && (epoch == LLONG_MAX || epoch == LLONG_MIN))
+-      || (errno != 0 && epoch == 0))
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "strtoll: %s\n", xstrerror(errno));
+-  if (endptr == source_date_epoch)
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "no digits were found: %s\n", endptr);
+-  if (*endptr != '\0')
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "trailing garbage: %s\n", endptr);
+-  if (epoch < 0)
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "value must be nonnegative: %lld \n", epoch);
++  if (errno != 0 || endptr == source_date_epoch || *endptr != '\0'
++      || epoch < 0 || epoch > MAX_SOURCE_DATE_EPOCH)
++    {
++      error_at (input_location, "environment variable SOURCE_DATE_EPOCH must "
++	        "expand to a non-negative integer less than or equal to %wd",
++		MAX_SOURCE_DATE_EPOCH);
++      return (time_t) -1;
++    }
+ 
+   return (time_t) epoch;
+ }
+Index: b/src/gcc/c-family/c-common.h
+===================================================================
+--- a/src/gcc/c-family/c-common.h
++++ b/src/gcc/c-family/c-common.h
+@@ -1084,6 +1084,16 @@ extern vec<tree, va_gc> *make_tree_vecto
+    c_register_builtin_type.  */
+ extern GTY(()) tree registered_builtin_types;
+ 
++/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
++   timestamp to replace embedded current dates to get reproducible
++   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++extern time_t cb_get_source_date_epoch (cpp_reader *pfile);
++
++/* The value (as a unix timestamp) corresponds to date
++   "Dec 31 9999 23:59:59 UTC", which is the latest date that __DATE__ and
++   __TIME__ can store.  */
++#define MAX_SOURCE_DATE_EPOCH HOST_WIDE_INT_C (253402300799)
++
+ /* In c-gimplify.c  */
+ extern void c_genericize (tree);
+ extern int c_gimplify_expr (tree *, gimple_seq *, gimple_seq *);
+@@ -1467,9 +1477,4 @@ extern bool reject_gcc_builtin (const_tr
+ extern void warn_duplicated_cond_add_or_warn (location_t, tree, vec<tree> **);
+ extern bool valid_array_size_p (location_t, tree, tree);
+ 
+-/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
+-   timestamp to replace embedded current dates to get reproducible
+-   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
+-extern time_t get_source_date_epoch (void);
+-
+ #endif /* ! GCC_C_COMMON_H */
+Index: b/src/gcc/c-family/c-lex.c
+===================================================================
+--- a/src/gcc/c-family/c-lex.c
++++ b/src/gcc/c-family/c-lex.c
+@@ -80,6 +80,7 @@ init_c_lex (void)
+   cb->valid_pch = c_common_valid_pch;
+   cb->read_pch = c_common_read_pch;
+   cb->has_attribute = c_common_has_attribute;
++  cb->get_source_date_epoch = cb_get_source_date_epoch;
+ 
+   /* Set the debug callbacks if we can use them.  */
+   if ((debug_info_level == DINFO_LEVEL_VERBOSE
+@@ -385,9 +386,6 @@ c_lex_with_flags (tree *value, location_
+   enum cpp_ttype type;
+   unsigned char add_flags = 0;
+   enum overflow_type overflow = OT_NONE;
+-  time_t source_date_epoch = get_source_date_epoch ();
+-
+-  cpp_init_source_date_epoch (parse_in, source_date_epoch);
+ 
+   timevar_push (TV_CPP);
+  retry:
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -3539,6 +3539,29 @@ save_switch (const char *opt, size_t n_a
+   n_switches++;
+ }
+ 
++/* Set the SOURCE_DATE_EPOCH environment variable to the current time if it is
++   not set already.  */
++
++static void
++set_source_date_epoch_envvar ()
++{
++  /* Array size is 21 = ceil(log_10(2^64)) + 1 to hold string representations
++     of 64 bit integers.  */
++  char source_date_epoch[21];
++  time_t tt;
++
++  errno = 0;
++  tt = time (NULL);
++  if (tt < (time_t) 0 || errno != 0)
++    tt = (time_t) 0;
++
++  snprintf (source_date_epoch, 21, "%llu", (unsigned long long) tt);
++  /* Using setenv instead of xputenv because we want the variable to remain
++     after finalizing so that it's still set in the second run when using
++     -fcompare-debug.  */
++  setenv ("SOURCE_DATE_EPOCH", source_date_epoch, 0);
++}
++
+ /* Handle an option DECODED that is unknown to the option-processing
+    machinery.  */
+ 
+@@ -3838,6 +3861,7 @@ driver_handle_option (struct gcc_options
+       else
+ 	compare_debug_opt = arg;
+       save_switch (compare_debug_replacement_opt, 0, NULL, validated, true);
++      set_source_date_epoch_envvar ();
+       return true;
+ 
+     case OPT_fdiagnostics_color_:
+Index: b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-1.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-1.c
+@@ -0,0 +1,11 @@
++/* { dg-do run } */
++/* { dg-set-compiler-env-var SOURCE_DATE_EPOCH "630333296" } */
++
++int
++main()
++{
++  if (__builtin_strcmp (__DATE__, "Dec 22 1989") != 0
++      || __builtin_strcmp (__TIME__, "12:34:56") != 0)
++    __builtin_abort ();
++  return 0;
++}
+Index: b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-2.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-2.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-set-compiler-env-var SOURCE_DATE_EPOCH "AAA" } */
++
++/* Make sure that SOURCE_DATE_EPOCH is only parsed once */
++
++int
++main(void)
++{
++  __builtin_printf ("%s %s\n", __DATE__, __TIME__); /* { dg-error "SOURCE_DATE_EPOCH must expand" } */
++  __builtin_printf ("%s %s\n", __DATE__, __TIME__);
++  return 0;
++}
+Index: b/src/gcc/testsuite/lib/gcc-dg.exp
+===================================================================
+--- a/src/gcc/testsuite/lib/gcc-dg.exp
++++ b/src/gcc/testsuite/lib/gcc-dg.exp
+@@ -450,6 +450,38 @@ proc restore-target-env-var { } {
+     }
+ }
+ 
++proc dg-set-compiler-env-var { args } {
++    global set_compiler_env_var
++    global saved_compiler_env_var
++    if { [llength $args] != 3 } {
++	error "dg-set-compiler-env-var: need two arguments"
++	return
++    }
++    set var [lindex $args 1]
++    set value [lindex $args 2]
++    if [info exists ::env($var)] {
++      lappend saved_compiler_env_var [list $var 1 $::env($var)]
++    } else {
++      lappend saved_compiler_env_var [list $var 0]
++    }
++    setenv $var $value
++    lappend set_compiler_env_var [list $var $value]
++}
++
++proc restore-compiler-env-var { } {
++    global saved_compiler_env_var
++    for { set env_vari [llength $saved_compiler_env_var] } {
++          [incr env_vari -1] >= 0 } {} {
++	set env_var [lindex $saved_compiler_env_var $env_vari]
++	set var [lindex $env_var 0]
++	if [lindex $env_var 1] {
++	    setenv $var [lindex $env_var 2]
++	} else {
++	    unsetenv $var
++	}
++    }
++}
++
+ # Utility routines.
+ 
+ #
+@@ -862,6 +894,8 @@ if { [info procs saved-dg-test] == [list
+ 	global shouldfail
+ 	global testname_with_flags
+ 	global set_target_env_var
++	global set_compiler_env_var
++	global saved_compiler_env_var
+ 	global keep_saved_temps_suffixes
+ 	global multiline_expected_outputs
+ 
+@@ -876,6 +910,11 @@ if { [info procs saved-dg-test] == [list
+ 	if [info exists keep_saved_temps_suffixes] {
+ 	    unset keep_saved_temps_suffixes
+ 	}
++	if [info exists set_compiler_env_var] {
++	    restore-compiler-env-var
++	    unset set_compiler_env_var
++	    unset saved_compiler_env_var
++	}
+ 	unset_timeout_vars
+ 	if [info exists compiler_conditional_xfail_data] {
+ 	    unset compiler_conditional_xfail_data
+Index: b/src/libcpp/include/cpplib.h
+===================================================================
+--- a/src/libcpp/include/cpplib.h
++++ b/src/libcpp/include/cpplib.h
+@@ -594,6 +594,9 @@ struct cpp_callbacks
+ 
+   /* Callback that can change a user builtin into normal macro.  */
+   bool (*user_builtin_macro) (cpp_reader *, cpp_hashnode *);
++
++  /* Callback to parse SOURCE_DATE_EPOCH from environment.  */
++  time_t (*get_source_date_epoch) (cpp_reader *);
+ };
+ 
+ #ifdef VMS
+@@ -784,9 +787,6 @@ extern void cpp_init_special_builtins (c
+ /* Set up built-ins like __FILE__.  */
+ extern void cpp_init_builtins (cpp_reader *, int);
+ 
+-/* Initialize the source_date_epoch value.  */
+-extern void cpp_init_source_date_epoch (cpp_reader *, time_t);
+-
+ /* This is called after options have been parsed, and partially
+    processed.  */
+ extern void cpp_post_options (cpp_reader *);
+Index: b/src/libcpp/init.c
+===================================================================
+--- a/src/libcpp/init.c
++++ b/src/libcpp/init.c
+@@ -257,6 +257,9 @@ cpp_create_reader (enum c_lang lang, cpp
+   /* Do not force token locations by default.  */
+   pfile->forced_token_location_p = NULL;
+ 
++  /* Initialize source_date_epoch to -2 (not yet set).  */
++  pfile->source_date_epoch = (time_t) -2;
++
+   /* The expression parser stack.  */
+   _cpp_expand_op_stack (pfile);
+ 
+@@ -533,13 +536,6 @@ cpp_init_builtins (cpp_reader *pfile, in
+     _cpp_define_builtin (pfile, "__OBJC__ 1");
+ }
+ 
+-/* Initialize the source_date_epoch value.  */
+-void
+-cpp_init_source_date_epoch (cpp_reader *pfile, time_t source_date_epoch)
+-{
+-  pfile->source_date_epoch = source_date_epoch; 
+-}
+-
+ /* Sanity-checks are dependent on command-line options, so it is
+    called as a subroutine of cpp_read_main_file.  */
+ #if CHECKING_P
+Index: b/src/libcpp/internal.h
+===================================================================
+--- a/src/libcpp/internal.h
++++ b/src/libcpp/internal.h
+@@ -503,7 +503,8 @@ struct cpp_reader
+   const unsigned char *time;
+ 
+   /* Externally set timestamp to replace current date and time useful for
+-     reproducibility.  */
++     reproducibility.  It should be initialized to -2 (not yet set) and
++     set to -1 to disable it or to a non-negative value to enable it.  */
+   time_t source_date_epoch;
+ 
+   /* EOF token, and a token forcing paste avoidance.  */
+Index: b/src/libcpp/macro.c
+===================================================================
+--- a/src/libcpp/macro.c
++++ b/src/libcpp/macro.c
+@@ -358,9 +358,13 @@ _cpp_builtin_macro_text (cpp_reader *pfi
+ 	  struct tm *tb = NULL;
+ 
+ 	  /* Set a reproducible timestamp for __DATE__ and __TIME__ macro
+-	     usage if SOURCE_DATE_EPOCH is defined.  */
+-	  if (pfile->source_date_epoch != (time_t) -1)
+-	     tb = gmtime (&pfile->source_date_epoch);
++	     if SOURCE_DATE_EPOCH is defined.  */
++	  if (pfile->source_date_epoch == (time_t) -2
++	      && pfile->cb.get_source_date_epoch != NULL)
++	    pfile->source_date_epoch = pfile->cb.get_source_date_epoch (pfile);
++
++	  if (pfile->source_date_epoch >= (time_t) 0)
++	    tb = gmtime (&pfile->source_date_epoch);
+ 	  else
+ 	    {
+ 	      /* (time_t) -1 is a legitimate value for "number of seconds
--- gcc-6-6.3.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH-doc.diff
+++ gcc-6-6.3.0/debian/patches/gcc-SOURCE_DATE_EPOCH-doc.diff
@@ -0,0 +1,33 @@
+# DP: Allow embedded timestamps by C/C++ macros to be set externally (docs)
+
+gcc/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* doc/cppenv.texi: Document SOURCE_DATE_EPOCH environment variable.
+
+--- a/src/gcc/doc/cppenv.texi
++++ b/src/gcc/doc/cppenv.texi
+@@ -79,4 +79,21 @@
+ @ifclear cppmanual
+ @xref{Preprocessor Options}.
+ @end ifclear
++
++@item SOURCE_DATE_EPOCH
++
++If this variable is set, its value specifies a UNIX timestamp to be
++used in replacement of the current date and time in the @code{__DATE__}
++and @code{__TIME__} macros, so that the embedded timestamps become
++reproducible.
++
++The value of @env{SOURCE_DATE_EPOCH} must be a UNIX timestamp,
++defined as the number of seconds (excluding leap seconds) since
++01 Jan 1970 00:00:00 represented in ASCII, identical to the output of
++@samp{@command{date +%s}}.
++
++The value should be a known timestamp such as the last modification
++time of the source or package and it should be set by the build
++process.
++
+ @end vtable
--- gcc-6-6.3.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH.diff
+++ gcc-6-6.3.0/debian/patches/gcc-SOURCE_DATE_EPOCH.diff
@@ -0,0 +1,186 @@
+# DP: Allow embedded timestamps by C/C++ macros to be set externally
+
+gcc/c-family/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* c-common.c (get_source_date_epoch): New function, gets the environment
+	variable SOURCE_DATE_EPOCH and parses it as long long with error 
+	handling.
+	* c-common.h (get_source_date_epoch): Prototype.
+	* c-lex.c (c_lex_with_flags): set parse_in->source_date_epoch.
+
+gcc/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* doc/cppenv.texi: Document SOURCE_DATE_EPOCH environment variable.
+
+libcpp/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* include/cpplib.h (cpp_init_source_date_epoch): Prototype.
+	* init.c (cpp_init_source_date_epoch): New function.
+	* internal.h: Added source_date_epoch variable to struct
+	cpp_reader to store a reproducible date.
+	* macro.c (_cpp_builtin_macro_text): Set pfile->date timestamp from 
+	pfile->source_date_epoch instead of localtime if source_date_epoch is 
+	set, to be used for __DATE__ and __TIME__ macros to help reproducible 
+	builds.
+
+Index: b/src/gcc/c-family/c-common.c
+===================================================================
+--- a/src/gcc/c-family/c-common.c
++++ b/src/gcc/c-family/c-common.c
+@@ -12743,4 +12743,37 @@ valid_array_size_p (location_t loc, tree
+   return true;
+ }
+ 
++/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
++   timestamp to replace embedded current dates to get reproducible
++   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++time_t
++get_source_date_epoch ()
++{
++  char *source_date_epoch;
++  long long epoch;
++  char *endptr;
++
++  source_date_epoch = getenv ("SOURCE_DATE_EPOCH");
++  if (!source_date_epoch)
++    return (time_t) -1;
++
++  errno = 0;
++  epoch = strtoll (source_date_epoch, &endptr, 10);
++  if ((errno == ERANGE && (epoch == LLONG_MAX || epoch == LLONG_MIN))
++      || (errno != 0 && epoch == 0))
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "strtoll: %s\n", xstrerror(errno));
++  if (endptr == source_date_epoch)
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "no digits were found: %s\n", endptr);
++  if (*endptr != '\0')
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "trailing garbage: %s\n", endptr);
++  if (epoch < 0)
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "value must be nonnegative: %lld \n", epoch);
++
++  return (time_t) epoch;
++}
++
+ #include "gt-c-family-c-common.h"
+Index: b/src/gcc/c-family/c-common.h
+===================================================================
+--- a/src/gcc/c-family/c-common.h
++++ b/src/gcc/c-family/c-common.h
+@@ -1467,4 +1467,9 @@ extern bool reject_gcc_builtin (const_tr
+ extern void warn_duplicated_cond_add_or_warn (location_t, tree, vec<tree> **);
+ extern bool valid_array_size_p (location_t, tree, tree);
+ 
++/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
++   timestamp to replace embedded current dates to get reproducible
++   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++extern time_t get_source_date_epoch (void);
++
+ #endif /* ! GCC_C_COMMON_H */
+Index: b/src/gcc/c-family/c-lex.c
+===================================================================
+--- a/src/gcc/c-family/c-lex.c
++++ b/src/gcc/c-family/c-lex.c
+@@ -385,6 +385,9 @@ c_lex_with_flags (tree *value, location_
+   enum cpp_ttype type;
+   unsigned char add_flags = 0;
+   enum overflow_type overflow = OT_NONE;
++  time_t source_date_epoch = get_source_date_epoch ();
++
++  cpp_init_source_date_epoch (parse_in, source_date_epoch);
+ 
+   timevar_push (TV_CPP);
+  retry:
+Index: b/src/libcpp/include/cpplib.h
+===================================================================
+--- a/src/libcpp/include/cpplib.h
++++ b/src/libcpp/include/cpplib.h
+@@ -784,6 +784,9 @@ extern void cpp_init_special_builtins (c
+ /* Set up built-ins like __FILE__.  */
+ extern void cpp_init_builtins (cpp_reader *, int);
+ 
++/* Initialize the source_date_epoch value.  */
++extern void cpp_init_source_date_epoch (cpp_reader *, time_t);
++
+ /* This is called after options have been parsed, and partially
+    processed.  */
+ extern void cpp_post_options (cpp_reader *);
+Index: b/src/libcpp/init.c
+===================================================================
+--- a/src/libcpp/init.c
++++ b/src/libcpp/init.c
+@@ -533,8 +533,15 @@ cpp_init_builtins (cpp_reader *pfile, in
+     _cpp_define_builtin (pfile, "__OBJC__ 1");
+ }
+ 
++/* Initialize the source_date_epoch value.  */
++void
++cpp_init_source_date_epoch (cpp_reader *pfile, time_t source_date_epoch)
++{
++  pfile->source_date_epoch = source_date_epoch; 
++}
++
+ /* Sanity-checks are dependent on command-line options, so it is
+-   called as a subroutine of cpp_read_main_file ().  */
++   called as a subroutine of cpp_read_main_file.  */
+ #if CHECKING_P
+ static void sanity_checks (cpp_reader *);
+ static void sanity_checks (cpp_reader *pfile)
+Index: b/src/libcpp/internal.h
+===================================================================
+--- a/src/libcpp/internal.h
++++ b/src/libcpp/internal.h
+@@ -502,6 +502,10 @@ struct cpp_reader
+   const unsigned char *date;
+   const unsigned char *time;
+ 
++  /* Externally set timestamp to replace current date and time useful for
++     reproducibility.  */
++  time_t source_date_epoch;
++
+   /* EOF token, and a token forcing paste avoidance.  */
+   cpp_token avoid_paste;
+   cpp_token eof;
+Index: b/src/libcpp/macro.c
+===================================================================
+--- a/src/libcpp/macro.c
++++ b/src/libcpp/macro.c
+@@ -357,13 +357,20 @@ _cpp_builtin_macro_text (cpp_reader *pfi
+ 	  time_t tt;
+ 	  struct tm *tb = NULL;
+ 
+-	  /* (time_t) -1 is a legitimate value for "number of seconds
+-	     since the Epoch", so we have to do a little dance to
+-	     distinguish that from a genuine error.  */
+-	  errno = 0;
+-	  tt = time(NULL);
+-	  if (tt != (time_t)-1 || errno == 0)
+-	    tb = localtime (&tt);
++	  /* Set a reproducible timestamp for __DATE__ and __TIME__ macro
++	     usage if SOURCE_DATE_EPOCH is defined.  */
++	  if (pfile->source_date_epoch != (time_t) -1)
++	     tb = gmtime (&pfile->source_date_epoch);
++	  else
++	    {
++	      /* (time_t) -1 is a legitimate value for "number of seconds
++		 since the Epoch", so we have to do a little dance to
++		 distinguish that from a genuine error.  */
++	      errno = 0;
++	      tt = time (NULL);
++	      if (tt != (time_t)-1 || errno == 0)
++		tb = localtime (&tt);
++	    }
+ 
+ 	  if (tb)
+ 	    {
--- gcc-6-6.3.0.orig/debian/patches/gcc-as-needed-gold.diff
+++ gcc-6-6.3.0/debian/patches/gcc-as-needed-gold.diff
@@ -0,0 +1,17 @@
+# DP: Use --push-state/--pop-state for gold as well when linking libtsan.
+
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -700,10 +700,10 @@
+ #define LIBTSAN_SPEC STATIC_LIBTSAN_LIBS
+ #elif defined(HAVE_LD_STATIC_DYNAMIC)
+ #define LIBTSAN_SPEC "%{static-libtsan:" LD_STATIC_OPTION "}" \
+-		     " %{!static-libtsan:%{!fuse-ld=gold:--push-state }--no-as-needed}" \
++		     " %{!static-libtsan:--push-state --no-as-needed}" \
+ 		     " -ltsan " \
+ 		     " %{static-libtsan:" LD_DYNAMIC_OPTION "}" \
+-		     " %{!static-libtsan:%{fuse-ld=gold:--as-needed;:--pop-state}}" \
++		     " %{!static-libtsan:--pop-state}" \
+ 		     STATIC_LIBTSAN_LIBS
+ #else
+ #define LIBTSAN_SPEC "-ltsan" STATIC_LIBTSAN_LIBS
--- gcc-6-6.3.0.orig/debian/patches/gcc-as-needed.diff
+++ gcc-6-6.3.0/debian/patches/gcc-as-needed.diff
@@ -0,0 +1,209 @@
+# DP: On linux targets pass --as-needed by default to the linker, but always
+# DP: link the sanitizer libraries with --no-as-needed.
+
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -568,8 +568,11 @@ proper position among the other output f
+ #ifdef LIBTSAN_EARLY_SPEC
+ #define LIBTSAN_SPEC STATIC_LIBTSAN_LIBS
+ #elif defined(HAVE_LD_STATIC_DYNAMIC)
+-#define LIBTSAN_SPEC "%{static-libtsan:" LD_STATIC_OPTION \
+-		     "} -ltsan %{static-libtsan:" LD_DYNAMIC_OPTION "}" \
++#define LIBTSAN_SPEC "%{static-libtsan:" LD_STATIC_OPTION "}" \
++		     " %{!static-libtsan:%{!fuse-ld=gold:--push-state }--no-as-needed}" \
++		     " -ltsan " \
++		     " %{static-libtsan:" LD_DYNAMIC_OPTION "}" \
++		     " %{!static-libtsan:%{fuse-ld=gold:--as-needed;:--pop-state}}" \
+ 		     STATIC_LIBTSAN_LIBS
+ #else
+ #define LIBTSAN_SPEC "-ltsan" STATIC_LIBTSAN_LIBS
+--- a/src/gcc/config/gnu-user.h
++++ b/src/gcc/config/gnu-user.h
+@@ -124,13 +124,13 @@
+ #define LIBASAN_EARLY_SPEC "%{!shared:libasan_preinit%O%s} " \
+   "%{static-libasan:%{!shared:" \
+   LD_STATIC_OPTION " --whole-archive -lasan --no-whole-archive " \
+-  LD_DYNAMIC_OPTION "}}%{!static-libasan:-lasan}"
++  LD_DYNAMIC_OPTION "}}%{!static-libasan:%{!fuse-ld=gold:--push-state} --no-as-needed -lasan %{fuse-ld=gold:--as-needed;:--pop-state}}"
+ #undef LIBTSAN_EARLY_SPEC
+ #define LIBTSAN_EARLY_SPEC "%{static-libtsan:%{!shared:" \
+   LD_STATIC_OPTION " --whole-archive -ltsan --no-whole-archive " \
+-  LD_DYNAMIC_OPTION "}}%{!static-libtsan:-ltsan}"
++  LD_DYNAMIC_OPTION "}}%{!static-libtsan:%{!fuse-ld=gold:--push-state} --no-as-needed -ltsan %{fuse-ld=gold:--as-needed;:--pop-state}}"
+ #undef LIBLSAN_EARLY_SPEC
+ #define LIBLSAN_EARLY_SPEC "%{static-liblsan:%{!shared:" \
+   LD_STATIC_OPTION " --whole-archive -llsan --no-whole-archive " \
+-  LD_DYNAMIC_OPTION "}}%{!static-liblsan:-llsan}"
++  LD_DYNAMIC_OPTION "}}%{!static-liblsan:%{!fuse-ld=gold:--push-state} --no-as-needed -llsan %{fuse-ld=gold:--as-needed;:--pop-state}}"
+ #endif
+Index: b/src/gcc/config/aarch64/aarch64-linux.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-linux.h
++++ b/src/gcc/config/aarch64/aarch64-linux.h
+@@ -36,6 +36,7 @@
+ 
+ #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
+    --hash-style=gnu				\
++   --as-needed					\
+    %{static:-Bstatic}				\
+    %{shared:-shared}				\
+    %{symbolic:-Bsymbolic}			\
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -58,7 +58,7 @@ do {						\
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+ 
+ #undef LINK_SPEC
+-#define LINK_SPEC " --hash-style=gnu \
++#define LINK_SPEC " --hash-style=gnu --as-needed \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/sparc/linux.h
+===================================================================
+--- a/src/gcc/config/sparc/linux.h
++++ b/src/gcc/config/sparc/linux.h
+@@ -86,7 +86,7 @@ extern const char *host_detect_local_cpu
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+ 
+ #undef  LINK_SPEC
+-#define LINK_SPEC "-m elf32_sparc --hash-style=gnu %{shared:-shared} \
++#define LINK_SPEC "-m elf32_sparc --hash-style=gnu --as-needed %{shared:-shared} \
+   %{!mno-relax:%{!r:-relax}} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/s390/linux.h
+===================================================================
+--- a/src/gcc/config/s390/linux.h
++++ b/src/gcc/config/s390/linux.h
+@@ -65,7 +65,7 @@ along with GCC; see the file COPYING3.
+ 
+ #undef  LINK_SPEC
+ #define LINK_SPEC \
+-  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu \
++  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu --as-needed \
+    %{shared:-shared} \
+    %{!shared: \
+       %{static:-static} \
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -466,12 +466,12 @@ extern int dot_symbols;
+ 					   " -m elf64ppc")
+ #endif
+ 
+-#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=gnu %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=gnu --as-needed %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
+   %(link_os_extra_spec32)"
+ 
+-#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=gnu %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=gnu --as-needed %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}} \
+   %(link_os_extra_spec64)"
+Index: b/src/gcc/config/rs6000/sysv4.h
+===================================================================
+--- a/src/gcc/config/rs6000/sysv4.h
++++ b/src/gcc/config/rs6000/sysv4.h
+@@ -784,7 +784,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \
+ 			 MUSL_DYNAMIC_LINKER)
+ 
+-#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu --as-needed %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
+ 
+Index: b/src/gcc/config/i386/gnu-user64.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user64.h
++++ b/src/gcc/config/i386/gnu-user64.h
+@@ -57,6 +57,7 @@ see the files COPYING3 and COPYING.RUNTI
+                    %{" SPEC_32 ":-m " GNU_USER_LINK_EMULATION32 "} \
+                    %{" SPEC_X32 ":-m " GNU_USER_LINK_EMULATIONX32 "} \
+   --hash-style=gnu \
++  --as-needed \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/i386/gnu-user.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user.h
++++ b/src/gcc/config/i386/gnu-user.h
+@@ -74,7 +74,7 @@ along with GCC; see the file COPYING3.
+   { "link_emulation", GNU_USER_LINK_EMULATION },\
+   { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+ 
+-#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=gnu %{shared:-shared} \
++#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=gnu --as-needed %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/gcc/config/alpha/linux-elf.h
+===================================================================
+--- a/src/gcc/config/alpha/linux-elf.h
++++ b/src/gcc/config/alpha/linux-elf.h
+@@ -37,7 +37,7 @@ along with GCC; see the file COPYING3.
+ 
+ #define ELF_DYNAMIC_LINKER	GNU_USER_DYNAMIC_LINKER
+ 
+-#define LINK_SPEC "-m elf64alpha --hash-style=gnu %{G*} %{relax:-relax}	\
++#define LINK_SPEC "-m elf64alpha --hash-style=gnu --as-needed %{G*} %{relax:-relax}	\
+   %{O*:-O3} %{!O*:-O1}						\
+   %{shared:-shared}						\
+   %{!shared:							\
+Index: b/src/gcc/config/arm/linux-elf.h
+===================================================================
+--- a/src/gcc/config/arm/linux-elf.h
++++ b/src/gcc/config/arm/linux-elf.h
+@@ -73,6 +73,7 @@
+      %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+    -X \
+    --hash-style=gnu \
++   --as-needed \
+    %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
+    SUBTARGET_EXTRA_LINK_SPEC
+ 
+Index: b/src/gcc/config/mips/gnu-user.h
+===================================================================
+--- a/src/gcc/config/mips/gnu-user.h
++++ b/src/gcc/config/mips/gnu-user.h
+@@ -55,6 +55,7 @@ along with GCC; see the file COPYING3.
+ #undef GNU_USER_TARGET_LINK_SPEC
+ #define GNU_USER_TARGET_LINK_SPEC "\
+   %{G*} %{EB} %{EL} %{mips*} %{shared} \
++ -as-needed \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -628,7 +628,7 @@ libgcj_bc.la: $(libgcj_bc_la_OBJECTS) $(
+ 	rm .libs/libgcj_bc.so; \
+ 	mv .libs/libgcj_bc.so.1.0.0 .libs/libgcj_bc.so; \
+ 	$(libgcj_bc_dummy_LINK) -xc /dev/null -Wl,-soname,libgcj_bc.so.1 \
+-	-o .libs/libgcj_bc.so.1.0.0 -lgcj || exit; \
++	-o .libs/libgcj_bc.so.1.0.0 -Wl,--no-as-needed -lgcj || exit; \
+ 	rm .libs/libgcj_bc.so.1; \
+ 	$(LN_S) libgcj_bc.so.1.0.0 .libs/libgcj_bc.so.1
+ 
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -10646,7 +10646,7 @@ libgcj_bc.la: $(libgcj_bc_la_OBJECTS) $(
+ 	rm .libs/libgcj_bc.so; \
+ 	mv .libs/libgcj_bc.so.1.0.0 .libs/libgcj_bc.so; \
+ 	$(libgcj_bc_dummy_LINK) -xc /dev/null -Wl,-soname,libgcj_bc.so.1 \
+-	-o .libs/libgcj_bc.so.1.0.0 -lgcj || exit; \
++	-o .libs/libgcj_bc.so.1.0.0 -Wl,--no-as-needed -lgcj || exit; \
+ 	rm .libs/libgcj_bc.so.1; \
+ 	$(LN_S) libgcj_bc.so.1.0.0 .libs/libgcj_bc.so.1
+ 
--- gcc-6-6.3.0.orig/debian/patches/gcc-auto-build.diff
+++ gcc-6-6.3.0/debian/patches/gcc-auto-build.diff
@@ -0,0 +1,15 @@
+# DP: Fix cross building a native compiler.
+
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -1686,7 +1686,7 @@ else
+ 	# Clearing GMPINC is necessary to prevent host headers being
+ 	# used by the build compiler.  Defining GENERATOR_FILE stops
+ 	# system.h from including gmp.h.
+-	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
++	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD} -DGENERATOR_FILE" \
+ 	CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \
+ 	LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \
+ 	GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \
--- gcc-6-6.3.0.orig/debian/patches/gcc-base-version.diff
+++ gcc-6-6.3.0/debian/patches/gcc-base-version.diff
@@ -0,0 +1,228 @@
+# DP: Set base version to 5, introduce full version 5.x.y.
+
+Index: b/src/gcc/BASE-VER
+===================================================================
+--- a/src/gcc/BASE-VER
++++ b/src/gcc/BASE-VER
+@@ -1 +1 @@
+-6.3.0
++6
+Index: b/src/gcc/FULL-VER
+===================================================================
+--- /dev/null
++++ b/src/gcc/FULL-VER
+@@ -0,0 +1 @@
++6.3.0
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -828,11 +828,13 @@ GTM_H     = tm.h      $(tm_file_list) in
+ TM_H      = $(GTM_H) insn-flags.h $(OPTIONS_H)
+ 
+ # Variables for version information.
+-BASEVER     := $(srcdir)/BASE-VER  # 4.x.y
++FULLVER     := $(srcdir)/FULL-VER  # 6.x.y
++BASEVER     := $(srcdir)/BASE-VER  # 6.x
+ DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
+ DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
+ REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
+ 
++FULLVER_c   := $(shell cat $(FULLVER))
+ BASEVER_c   := $(shell cat $(BASEVER))
+ DEVPHASE_c  := $(shell cat $(DEVPHASE))
+ DATESTAMP_c := $(shell cat $(DATESTAMP))
+@@ -857,6 +859,7 @@ PATCHLEVEL_c := \
+ # immediately after the comma in the $(if ...) constructs is
+ # significant - do not remove it.
+ BASEVER_s   := "\"$(BASEVER_c)\""
++FULLVER_s   := "\"$(FULLVER_c)\""
+ DEVPHASE_s  := "\"$(if $(DEVPHASE_c), ($(DEVPHASE_c)))\""
+ DATESTAMP_s := \
+   "\"$(if $(DEVPHASE_c)$(filter-out 0,$(PATCHLEVEL_c)), $(DATESTAMP_c))\""
+@@ -2015,8 +2018,8 @@ default-c.o: config/default-c.c
+ 
+ # Files used by all variants of C and some other languages.
+ 
+-CFLAGS-prefix.o += -DPREFIX=\"$(prefix)\" -DBASEVER=$(BASEVER_s)
+-prefix.o: $(BASEVER)
++CFLAGS-prefix.o += -DPREFIX=\"$(prefix)\" -DBASEVER=$(FULLVER_s)
++prefix.o: $(FULLVER)
+ 
+ # Language-independent files.
+ 
+@@ -2024,7 +2027,8 @@ DRIVER_DEFINES = \
+   -DSTANDARD_STARTFILE_PREFIX=\"$(unlibsubdir)/\" \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc/\" \
+-  -DDEFAULT_TARGET_VERSION=\"$(version)\" \
++  -DDEFAULT_TARGET_VERSION=\"$(BASEVER_c)\" \
++  -DDEFAULT_TARGET_FULL_VERSION=\"$(FULLVER_c)\" \
+   -DDEFAULT_REAL_TARGET_MACHINE=\"$(real_target_noncanonical)\" \
+   -DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\" \
+   -DSTANDARD_BINDIR_PREFIX=\"$(bindir)/\" \
+@@ -2074,20 +2078,20 @@ s-options-h: optionlist $(srcdir)/opt-fu
+ 
+ dumpvers: dumpvers.c
+ 
+-CFLAGS-version.o += -DBASEVER=$(BASEVER_s) -DDATESTAMP=$(DATESTAMP_s) \
++CFLAGS-version.o += -DBASEVER=$(FULLVER_s) -DDATESTAMP=$(DATESTAMP_s) \
+ 	-DREVISION=$(REVISION_s) \
+ 	-DDEVPHASE=$(DEVPHASE_s) -DPKGVERSION=$(PKGVERSION_s) \
+ 	-DBUGURL=$(BUGURL_s)
+-version.o: $(REVISION) $(DATESTAMP) $(BASEVER) $(DEVPHASE)
++version.o: $(REVISION) $(DATESTAMP) $(FULLVER) $(DEVPHASE)
+ 
+ # lto-compress.o needs $(ZLIBINC) added to the include flags.
+ CFLAGS-lto-compress.o += $(ZLIBINC)
+ 
+ bversion.h: s-bversion; @true
+-s-bversion: BASE-VER
+-	echo "#define BUILDING_GCC_MAJOR `echo $(BASEVER_c) | sed -e 's/^\([0-9]*\).*$$/\1/'`" > bversion.h
+-	echo "#define BUILDING_GCC_MINOR `echo $(BASEVER_c) | sed -e 's/^[0-9]*\.\([0-9]*\).*$$/\1/'`" >> bversion.h
+-	echo "#define BUILDING_GCC_PATCHLEVEL `echo $(BASEVER_c) | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$$/\1/'`" >> bversion.h
++s-bversion: FULL-VER
++	echo "#define BUILDING_GCC_MAJOR `echo $(FULLVER_c) | sed -e 's/^\([0-9]*\).*$$/\1/'`" > bversion.h
++	echo "#define BUILDING_GCC_MINOR `echo $(FULLVER_c) | sed -e 's/^[0-9]*\.\([0-9]*\).*$$/\1/'`" >> bversion.h
++	echo "#define BUILDING_GCC_PATCHLEVEL `echo $(FULLVER_c) | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$$/\1/'`" >> bversion.h
+ 	echo "#define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)" >> bversion.h
+ 	$(STAMP) s-bversion
+ 
+@@ -2454,9 +2458,9 @@ build/%.o :  # dependencies provided by
+ ## build/version.o is compiled by the $(COMPILER_FOR_BUILD) but needs
+ ## several C macro definitions, just like version.o
+ build/version.o:  version.c version.h \
+-                  $(REVISION) $(DATESTAMP) $(BASEVER) $(DEVPHASE)
++                  $(REVISION) $(DATESTAMP) $(FULLVER) $(DEVPHASE)
+ 	$(COMPILER_FOR_BUILD) -c $(BUILD_COMPILERFLAGS) $(BUILD_CPPFLAGS) \
+-	-DBASEVER=$(BASEVER_s) -DDATESTAMP=$(DATESTAMP_s) \
++	-DBASEVER=$(FULLVER_s) -DDATESTAMP=$(DATESTAMP_s) \
+ 	-DREVISION=$(REVISION_s) \
+ 	-DDEVPHASE=$(DEVPHASE_s) -DPKGVERSION=$(PKGVERSION_s) \
+ 	-DBUGURL=$(BUGURL_s) -o $@ $<
+@@ -2679,8 +2683,8 @@ PREPROCESSOR_DEFINES = \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+-CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s)
+-cppbuiltin.o: $(BASEVER)
++CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(FULLVER_s)
++cppbuiltin.o: $(FULLVER)
+ 
+ CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
+ 
+@@ -2696,8 +2700,8 @@ build/gcov-iov$(build_exeext): build/gco
+ 		build/gcov-iov.o -o $@
+ 
+ gcov-iov.h: s-iov; @true
+-s-iov: build/gcov-iov$(build_exeext) $(BASEVER) $(DEVPHASE)
+-	build/gcov-iov$(build_exeext) '$(BASEVER_c)' '$(DEVPHASE_c)' \
++s-iov: build/gcov-iov$(build_exeext) $(FULLVER) $(DEVPHASE)
++	build/gcov-iov$(build_exeext) '$(FULLVER_c)' '$(DEVPHASE_c)' \
+ 	    > tmp-gcov-iov.h
+ 	$(SHELL) $(srcdir)/../move-if-change tmp-gcov-iov.h gcov-iov.h
+ 	$(STAMP) s-iov
+@@ -2976,8 +2980,8 @@ TEXI_GCCINSTALL_FILES = install.texi ins
+ TEXI_CPPINT_FILES = cppinternals.texi gcc-common.texi gcc-vers.texi
+ 
+ # gcc-vers.texi is generated from the version files.
+-gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+-	(echo "@set version-GCC $(BASEVER_c)"; \
++gcc-vers.texi: $(FULLVER) $(DEVPHASE)
++	(echo "@set version-GCC $(FULLVER_c)"; \
+ 	 if [ "$(DEVPHASE_c)" = "experimental" ]; \
+ 	 then echo "@set DEVELOPMENT"; \
+ 	 else echo "@clear DEVELOPMENT"; \
+Index: b/src/libjava/testsuite/lib/libjava.exp
+===================================================================
+--- a/src/libjava/testsuite/lib/libjava.exp
++++ b/src/libjava/testsuite/lib/libjava.exp
+@@ -179,7 +179,8 @@ proc libjava_init { args } {
+ 
+     set text [eval exec "$GCJ_UNDER_TEST -B$specdir -v 2>@ stdout"]
+     regexp " version \[^\n\r\]*" $text version
+-    set libjava_version [lindex $version 1]
++    # FIXME: Still needed?
++    set libjava_version 6
+ 
+     verbose "version: $libjava_version"
+ 
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -278,7 +278,8 @@ static const char *compiler_version;
+ 
+ /* The target version.  */
+ 
+-static const char *const spec_version = DEFAULT_TARGET_VERSION;
++static const char *const base_version = DEFAULT_TARGET_VERSION;
++static const char *const spec_version = DEFAULT_TARGET_FULL_VERSION;
+ 
+ /* The target machine.  */
+ 
+@@ -4492,7 +4493,7 @@ process_command (unsigned int decoded_op
+      running, or, if that is not available, the configured prefix.  */
+   tooldir_prefix
+     = concat (gcc_exec_prefix ? gcc_exec_prefix : standard_exec_prefix,
+-	      spec_host_machine, dir_separator_str, spec_version,
++	      spec_host_machine, dir_separator_str, base_version,
+ 	      accel_dir_suffix, dir_separator_str, tooldir_prefix2, NULL);
+   free (tooldir_prefix2);
+ 
+@@ -7367,7 +7368,7 @@ driver::set_up_specs () const
+ 
+   /* Read specs from a file if there is one.  */
+ 
+-  machine_suffix = concat (spec_host_machine, dir_separator_str, spec_version,
++  machine_suffix = concat (spec_host_machine, dir_separator_str, base_version,
+ 			   accel_dir_suffix, dir_separator_str, NULL);
+   just_machine_suffix = concat (spec_machine, dir_separator_str, NULL);
+ 
+@@ -7572,7 +7573,7 @@ driver::set_up_specs () const
+   /* If we have a GCC_EXEC_PREFIX envvar, modify it for cpp's sake.  */
+   if (gcc_exec_prefix)
+     gcc_exec_prefix = concat (gcc_exec_prefix, spec_host_machine,
+-			      dir_separator_str, spec_version,
++			      dir_separator_str, base_version,
+ 			      accel_dir_suffix, dir_separator_str, NULL);
+ 
+   /* Now we have the specs.
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -207,7 +207,7 @@ if test x${gcc_gxx_include_dir} = x; the
+   if test x${enable_version_specific_runtime_libs} = xyes; then
+     gcc_gxx_include_dir='${libsubdir}/include/c++'
+   else
+-    libstdcxx_incdir='include/c++/$(version)'
++    libstdcxx_incdir='include/c++/$(BASEVER_c)'
+     if test x$host != x$target; then
+        libstdcxx_incdir="$target_alias/$libstdcxx_incdir"
+     fi
+@@ -1746,6 +1746,7 @@ changequote([,])dnl
+ 
+ changequote(,)dnl
+ gcc_BASEVER=`cat $srcdir/BASE-VER`
++gcc_FULLVER=`cat $srcdir/FULL-VER`
+ gcc_DEVPHASE=`cat $srcdir/DEV-PHASE`
+ gcc_DATESTAMP=`cat $srcdir/DATESTAMP`
+ if test -f $srcdir/REVISION ; then
+@@ -1756,12 +1757,12 @@ fi
+ cat > plugin-version.h <<EOF
+ #include "configargs.h"
+ 
+-#define GCCPLUGIN_VERSION_MAJOR   `echo $gcc_BASEVER | sed -e 's/^\([0-9]*\).*$/\1/'`
+-#define GCCPLUGIN_VERSION_MINOR   `echo $gcc_BASEVER | sed -e 's/^[0-9]*\.\([0-9]*\).*$/\1/'`
+-#define GCCPLUGIN_VERSION_PATCHLEVEL   `echo $gcc_BASEVER | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$/\1/'`
++#define GCCPLUGIN_VERSION_MAJOR   `echo $gcc_FULLVER | sed -e 's/^\([0-9]*\).*$/\1/'`
++#define GCCPLUGIN_VERSION_MINOR   `echo $gcc_FULLVER | sed -e 's/^[0-9]*\.\([0-9]*\).*$/\1/'`
++#define GCCPLUGIN_VERSION_PATCHLEVEL   `echo $gcc_FULLVER | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$/\1/'`
+ #define GCCPLUGIN_VERSION  (GCCPLUGIN_VERSION_MAJOR*1000 + GCCPLUGIN_VERSION_MINOR)
+ 
+-static char basever[] = "$gcc_BASEVER";
++static char basever[] = "$gcc_FULLVER";
+ static char datestamp[] = "$gcc_DATESTAMP";
+ static char devphase[] = "$gcc_DEVPHASE";
+ static char revision[] = "$gcc_REVISION";
--- gcc-6-6.3.0.orig/debian/patches/gcc-d-lang.diff
+++ gcc-6-6.3.0/debian/patches/gcc-d-lang.diff
@@ -0,0 +1,251 @@
+# DP: Add D options and specs for the gcc driver.
+
+Index: b/src/gcc/d/lang-specs.h
+===================================================================
+--- /dev/null
++++ b/src/gcc/d/lang-specs.h
+@@ -0,0 +1,31 @@
++/* lang-specs.h -- D frontend for GCC.
++   Copyright (C) 2011, 2012 Free Software Foundation, Inc.
++
++   GCC is free software; you can redistribute it and/or modify it under
++   the terms of the GNU General Public License as published by the Free
++   Software Foundation; either version 3, or (at your option) any later
++   version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or
++   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++   for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.
++*/
++
++/* %{!M} probably doesn't make sense because we would need
++   to do that -- -MD and -MMD doesn't sound like a plan for D.... */
++
++{".d", "@d", 0, 1, 0 },
++{".D", "@d", 0, 1, 0 },
++{".dd", "@d", 0, 1, 0 },
++{".DD", "@d", 0, 1, 0 },
++{".di", "@d", 0, 1, 0 },
++{".DI", "@d", 0, 1, 0 },
++{"@d",
++  "%{!E:cc1d %i %(cc1_options) %(cc1d) %I %{nostdinc*} %{+e*} %{I*} %{J*}\
++    %{M} %{MM} %{!fsyntax-only:%(invoke_as)}}", 0, 1, 0 },
++
+Index: b/src/gcc/d/lang.opt
+===================================================================
+--- /dev/null
++++ b/src/gcc/d/lang.opt
+@@ -0,0 +1,208 @@
++; GDC -- D front-end for GCC
++; Copyright (C) 2011, 2012 Free Software Foundation, Inc.
++;
++; This program is free software; you can redistribute it and/or modify
++; it under the terms of the GNU General Public License as published by
++; the Free Software Foundation; either version 2 of the License, or
++; (at your option) any later version.
++;
++; This program is distributed in the hope that it will be useful,
++; but WITHOUT ANY WARRANTY; without even the implied warranty of
++; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++; GNU General Public License for more details.
++;
++; You should have received a copy of the GNU General Public License
++; along with GCC; see the file COPYING3.  If not see
++; <http://www.gnu.org/licenses/>.
++
++Language
++D
++
++debuglib=
++Driver Joined
++Debug library to use instead of phobos
++
++defaultlib=
++Driver Joined
++Default library to use instead of phobos
++
++fassert
++D
++Permit the use of the assert keyword
++
++; For D: defaults to on
++fbounds-check
++D
++Generate code to check bounds before indexing arrays
++
++fbuiltin
++D Var(flag_no_builtin, 0)
++Recognize built-in functions
++
++fdebug
++D
++Compile in debug code
++
++fdebug=
++D Joined RejectNegative
++-fdebug,-fdebug=<level>,-fdebug=<ident> Compile in debug code, code <= level, or code identified by ident
++
++fdeps=
++D Joined RejectNegative
++-fdeps=<filename> Write module dependencies to filename
++
++fdoc
++D
++Generate documentation
++
++fdoc-dir=
++D Joined RejectNegative
++-fdoc-dir=<docdir> Write documentation file to docdir directory
++
++fdoc-file=
++D Joined RejectNegative
++-fdoc-file=<filename> Write documentation file to filename
++
++fdoc-inc=
++D Joined RejectNegative
++-fdoc-inc=<filename> Include a Ddoc macro file
++
++fdump-source
++D RejectNegative
++Dump decoded UTF-8 text and source from HTML
++
++fd-verbose
++D
++Print information about D language processing to stdout
++
++fd-vtls
++D
++List all variables going into thread local storage
++
++femit-templates
++D
++-femit-templates Emit templates code and data even if the linker cannot merge multiple copies
++
++fignore-unknown-pragmas
++D
++Ignore unsupported pragmas
++
++fin
++D
++Generate runtime code for in() contracts
++
++fintfc
++Generate D interface files
++
++fintfc-dir=
++D Joined RejectNegative
++-fintfc-dir=<dir> Write D interface files to directory <dir>
++
++fintfc-file=
++D Joined RejectNegative
++-fintfc-file=<filename> Write D interface file to <filename>
++
++finvariants
++D
++Generate runtime code for invariant()'s
++
++fmake-deps=
++D Joined RejectNegative
++-fmake-deps=<file> Write dependency output to the given file
++
++fmake-mdeps=
++D Joined RejectNegative
++Like -fmake-deps=<file> but ignore system modules
++
++femit-moduleinfo
++D
++Generate ModuleInfo struct for output module
++
++fonly=
++D Joined RejectNegative
++Process all modules specified on the command line, but only generate code for the module specified by the argument
++
++fout
++D
++Generate runtime code for out() contracts
++
++fproperty
++D
++Enforce property syntax
++
++frelease
++D
++Compile release version
++
++fsplit-dynamic-arrays
++D Var(flag_split_darrays)
++Split dynamic arrays into length and pointer when passing to functions
++
++funittest
++D
++Compile in unittest code
++
++fversion=
++D Joined RejectNegative
++-fversion=<level|ident> Compile in version code >= <level> or identified by <ident>
++
++fXf=
++D Joined RejectNegative
++-fXf=<filename> Write JSON file to <filename>
++
++imultilib
++D Joined Separate
++-imultilib <dir>	Set <dir> to be the multilib include subdirectory
++
++iprefix
++D Joined Separate
++-iprefix <path>	Specify <path> as a prefix for next two options
++
++isysroot
++D Joined Separate
++-isysroot <dir>	Set <dir> to be the system root directory
++
++isystem
++D Joined Separate
++-isystem <dir>	Add <dir> to the start of the system include path
++
++I
++D Joined Separate
++-I <dir>	Add <dir> to the end of the main include path
++
++J
++D Joined Separate
++-J<directory>	Put MODULE files in 'directory'
++
++nophoboslib
++Driver
++Do not link the standard D library in the compilation
++
++nostdinc
++D
++Do not search standard system include directories (those specified with -isystem will still be used)
++
++static-libphobos
++Driver
++Link the standard D library statically in the compilation
++
++Wall
++D
++; Documented in c.opt
++
++Wcast-result
++D Warning Var(warn_cast_result)
++Warn about casts that will produce a null or nil result
++
++Wdeprecated
++D
++; Documented in c.opt
++
++Werror
++D
++; Documented in common.opt
++
++Wunknown-pragmas
++D
++; Documented in c.opt
++
--- gcc-6-6.3.0.orig/debian/patches/gcc-default-format-security.diff
+++ gcc-6-6.3.0/debian/patches/gcc-default-format-security.diff
@@ -0,0 +1,39 @@
+# DP: Turn on -Wformat -Wformat-security by  default for C, C++, ObjC, ObjC++.
+
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -3799,6 +3799,11 @@ included in @option{-Wformat-nonliteral}
+ If @option{-Wformat} is specified, also warn if the format string
+ requires an unsigned argument and the argument is signed and vice versa.
+ 
++NOTE: In Ubuntu 8.10 and later versions this option is enabled by default
++for C, C++, ObjC, ObjC++.  To disable, use @option{-Wno-format-security},
++or disable all format warnings with @option{-Wformat=0}.  To make format
++security warnings fatal, specify @option{-Werror=format-security}.
++
+ @item -Wformat-y2k
+ @opindex Wformat-y2k
+ @opindex Wno-format-y2k
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -858,11 +858,14 @@ proper position among the other output f
+ #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G"
+ #endif
+ 
++/* no separate spec, just shove it into the ssp default spec */
++#define FORMAT_SECURITY_SPEC "%{!Wformat:%{!Wformat=2:%{!Wformat=0:%{!Wall:-Wformat} %{!Wno-format-security:-Wformat-security}}}}"
++
+ #ifndef SSP_DEFAULT_SPEC
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+-#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}}"
++#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}} " FORMAT_SECURITY_SPEC
+ #else
+-#define SSP_DEFAULT_SPEC ""
++#define SSP_DEFAULT_SPEC FORMAT_SECURITY_SPEC
+ #endif
+ #endif
+ 
--- gcc-6-6.3.0.orig/debian/patches/gcc-default-fortify-source.diff
+++ gcc-6-6.3.0/debian/patches/gcc-default-fortify-source.diff
@@ -0,0 +1,40 @@
+# DP: Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++,
+# DP: if the optimization level is > 0
+
+---
+ gcc/doc/invoke.texi          |    6 ++++++
+ gcc/c-family/c-cppbuiltin.c  |    3 +
+ 2 files changed, 9 insertions(+), 0 deletions(-)
+
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -7840,6 +7840,12 @@ also turns on the following optimization
+ Please note the warning under @option{-fgcse} about
+ invoking @option{-O2} on programs that use computed gotos.
+ 
++NOTE: In Ubuntu 8.10 and later versions, @option{-D_FORTIFY_SOURCE=2} is
++set by default, and is activated when @option{-O} is set to 2 or higher.
++This enables additional compile-time and run-time checks for several libc
++functions.  To disable, specify either @option{-U_FORTIFY_SOURCE} or
++@option{-D_FORTIFY_SOURCE=0}.
++
+ @item -O3
+ @opindex O3
+ Optimize yet more.  @option{-O3} turns on all optimizations specified
+Index: b/src/gcc/c-family/c-cppbuiltin.c
+===================================================================
+--- a/src/gcc/c-family/c-cppbuiltin.c
++++ b/src/gcc/c-family/c-cppbuiltin.c
+@@ -1176,6 +1176,10 @@ c_cpp_builtins (cpp_reader *pfile)
+   builtin_define_with_value ("__REGISTER_PREFIX__", REGISTER_PREFIX, 0);
+   builtin_define_with_value ("__USER_LABEL_PREFIX__", user_label_prefix, 0);
+ 
++  /* Fortify Source enabled by default for optimization levels > 0 */
++  if (optimize)
++    builtin_define_with_int_value ("_FORTIFY_SOURCE", 2);
++
+   /* Misc.  */
+   if (flag_gnu89_inline)
+     cpp_define (pfile, "__GNUC_GNU_INLINE__");
--- gcc-6-6.3.0.orig/debian/patches/gcc-default-relro.diff
+++ gcc-6-6.3.0/debian/patches/gcc-default-relro.diff
@@ -0,0 +1,33 @@
+# DP: Turn on -Wl,-z,relro by default.
+
+---
+ gcc/doc/invoke.texi |    3 +++
+ gcc/gcc.c           |    1 +
+ 2 files changed, 4 insertions(+), 0 deletions(-)
+
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -11638,6 +11638,9 @@ For example, @option{-Wl,-Map,output.map
+ linker.  When using the GNU linker, you can also get the same effect with
+ @option{-Wl,-Map=output.map}.
+ 
++NOTE: In Ubuntu 8.10 and later versions, for LDFLAGS, the option
++@option{-Wl,-z,relro} is used.  To disable, use @option{-Wl,-z,norelro}.
++
+ @item -u @var{symbol}
+ @opindex u
+ Pretend the symbol @var{symbol} is undefined, to force linking of
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -1027,6 +1027,7 @@ proper position among the other output f
+    "%{flto|flto=*:%<fcompare-debug*} \
+     %{flto} %{fno-lto} %{flto=*} %l " LINK_PIE_SPEC \
+    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
++   "-z relro " \
+    "%X %{o*} %{e*} %{N} %{n} %{r}\
+     %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}} \
+     %{static:} %{L*} %(mfwrap) %(link_libgcc) " \
--- gcc-6-6.3.0.orig/debian/patches/gcc-default-ssp-strong.diff
+++ gcc-6-6.3.0/debian/patches/gcc-default-ssp-strong.diff
@@ -0,0 +1,59 @@
+# DP: Default to -fstack-protector-strong starting with Ubuntu 14.10.
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -863,7 +863,7 @@ proper position among the other output f
+ 
+ #ifndef SSP_DEFAULT_SPEC
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+-#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}} " FORMAT_SECURITY_SPEC
++#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:%{!fstack-protector:-fstack-protector-strong}}}}} " FORMAT_SECURITY_SPEC
+ #else
+ #define SSP_DEFAULT_SPEC FORMAT_SECURITY_SPEC
+ #endif
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -9771,6 +9771,11 @@ branch target registers within any basic
+ Optimize the prologue of variadic argument functions with respect to usage of
+ those arguments.
+ 
++NOTE: In Ubuntu 14.10 and later versions,
++@option{-fstack-protector-strong} is enabled by default for C,
++C++, ObjC, ObjC++, if none of @option{-fno-stack-protector},
++@option{-nostdlib}, nor @option{-ffreestanding} are found.
++
+ @item -fsection-anchors
+ @opindex fsection-anchors
+ Try to reduce the number of symbolic address calculations by using
+@@ -10351,13 +10356,13 @@ value of a shared integer constant.  The
+ The minimum size of buffers (i.e.@: arrays) that receive stack smashing
+ protection when @option{-fstack-protection} is used.
+ 
++This default before Ubuntu 10.10 was "8". Currently it is "4", to increase
++the number of functions protected by the stack protector.
++
+ @item min-size-for-stack-sharing
+ The minimum size of variables taking part in stack slot sharing when not
+ optimizing. The default value is 32.
+ 
+-This default before Ubuntu 10.10 was "8". Currently it is "4", to increase
+-the number of functions protected by the stack protector.
+-
+ @item max-jump-thread-duplication-stmts
+ Maximum number of statements allowed in a block that needs to be
+ duplicated when threading jumps.
+@@ -11276,10 +11281,6 @@ functions with buffers larger than 8 byt
+ when a function is entered and then checked when the function exits.
+ If a guard check fails, an error message is printed and the program exits.
+ 
+-NOTE: In Ubuntu 6.10 and later versions this option is enabled by default
+-for C, C++, ObjC, ObjC++, if none of @option{-fno-stack-protector},
+-@option{-nostdlib}, nor @option{-ffreestanding} are found.
+-
+ @item -fstack-protector-all
+ @opindex fstack-protector-all
+ Like @option{-fstack-protector} except that all functions are protected.
--- gcc-6-6.3.0.orig/debian/patches/gcc-default-ssp.diff
+++ gcc-6-6.3.0/debian/patches/gcc-default-ssp.diff
@@ -0,0 +1,214 @@
+# DP: Turn on -fstack-protector by default for C, C++, ObjC, ObjC++.
+# DP: Build libgcc using -fno-stack-protector.
+
+---
+ gcc/Makefile.in        |    2 ++
+ gcc/cp/lang-specs.h    |    6 +++---
+ gcc/doc/invoke.texi    |    4 ++++
+ gcc/gcc.c              |   18 ++++++++++++++----
+ gcc/objc/lang-specs.h  |   10 +++++-----
+ gcc/objcp/lang-specs.h |    8 ++++----
+ 6 files changed, 32 insertions(+), 16 deletions(-)
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -858,6 +858,14 @@ proper position among the other output f
+ #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G"
+ #endif
+ 
++#ifndef SSP_DEFAULT_SPEC
++#ifdef TARGET_LIBC_PROVIDES_SSP
++#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}}"
++#else
++#define SSP_DEFAULT_SPEC ""
++#endif
++#endif
++
+ #ifndef LINK_SSP_SPEC
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+ #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
+@@ -1057,6 +1065,7 @@ static const char *cc1_spec = CC1_SPEC;
+ static const char *cc1plus_spec = CC1PLUS_SPEC;
+ static const char *link_gcc_c_sequence_spec = LINK_GCC_C_SEQUENCE_SPEC;
+ static const char *link_ssp_spec = LINK_SSP_SPEC;
++static const char *ssp_default_spec = SSP_DEFAULT_SPEC;
+ static const char *asm_spec = ASM_SPEC;
+ static const char *asm_final_spec = ASM_FINAL_SPEC;
+ static const char *link_spec = LINK_SPEC;
+@@ -1112,7 +1121,7 @@ static const char *cpp_unique_options =
+ static const char *cpp_options =
+ "%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w}\
+  %{f*} %{g*:%{!g0:%{g*} %{!fno-working-directory:-fworking-directory}}} %{O*}\
+- %{undef} %{save-temps*:-fpch-preprocess}";
++ %{undef} %{save-temps*:-fpch-preprocess} %(ssp_default)";
+ 
+ /* This contains cpp options which are not passed when the preprocessor
+    output will be used by another program.  */
+@@ -1301,9 +1310,9 @@ static const struct compiler default_com
+       %{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \
+ 	  %(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i} \n\
+ 	    cc1 -fpreprocessed %{save-temps*:%b.i} %{!save-temps*:%g.i} \
+-	  %(cc1_options)}\
++	  %(cc1_options) %(ssp_default)}\
+       %{!save-temps*:%{!traditional-cpp:%{!no-integrated-cpp:\
+-	  cc1 %(cpp_unique_options) %(cc1_options)}}}\
++	  cc1 %(cpp_unique_options) %(cc1_options) %(ssp_default)}}}\
+       %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 1},
+   {"-",
+    "%{!E:%e-E or -x required when input is from standard input}\
+@@ -1328,7 +1337,7 @@ static const struct compiler default_com
+ 					   %W{o*:--output-pch=%*}}%V}}}}}}}", 0, 0, 0},
+   {".i", "@cpp-output", 0, 0, 0},
+   {"@cpp-output",
+-   "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
++   "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %(ssp_default) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {".s", "@assembler", 0, 0, 0},
+   {"@assembler",
+    "%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 0, 0},
+@@ -1560,6 +1569,7 @@ static struct spec_list static_specs[] =
+   INIT_STATIC_SPEC ("cc1plus",			&cc1plus_spec),
+   INIT_STATIC_SPEC ("link_gcc_c_sequence",	&link_gcc_c_sequence_spec),
+   INIT_STATIC_SPEC ("link_ssp",			&link_ssp_spec),
++  INIT_STATIC_SPEC ("ssp_default",		&ssp_default_spec),
+   INIT_STATIC_SPEC ("endfile",			&endfile_spec),
+   INIT_STATIC_SPEC ("link",			&link_spec),
+   INIT_STATIC_SPEC ("lib",			&lib_spec),
+Index: b/src/gcc/cp/lang-specs.h
+===================================================================
+--- a/src/gcc/cp/lang-specs.h
++++ b/src/gcc/cp/lang-specs.h
+@@ -46,7 +46,7 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.ii} %{!save-temps*:%g.ii} \n}\
+       cc1plus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.ii} %{!save-temps*:%g.ii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+ 	%{!fsyntax-only:-o %g.s \
+ 	    %{!fdump-ada-spec*:%{!o*:--output-pch=%i.gch}\
+ 			       %W{o*:--output-pch=%*}}%V}}}}",
+@@ -58,11 +58,11 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.ii} %{!save-temps*:%g.ii} \n}\
+       cc1plus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.ii} %{!save-temps*:%g.ii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+        %{!fsyntax-only:%(invoke_as)}}}}",
+      CPLUSPLUS_CPP_SPEC, 0, 0},
+   {".ii", "@c++-cpp-output", 0, 0, 0},
+   {"@c++-cpp-output",
+    "%{!M:%{!MM:%{!E:\
+-    cc1plus -fpreprocessed %i %(cc1_options) %2\
++    cc1plus -fpreprocessed %i %(cc1_options) %(ssp_default) %2\
+     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+Index: b/src/gcc/params.def
+===================================================================
+--- a/src/gcc/params.def
++++ b/src/gcc/params.def
+@@ -673,7 +673,7 @@ DEFPARAM (PARAM_INTEGER_SHARE_LIMIT,
+ DEFPARAM (PARAM_SSP_BUFFER_SIZE,
+ 	  "ssp-buffer-size",
+ 	  "The lower bound for a buffer to be considered for stack smashing protection.",
+-	  8, 1, 0)
++	  4, 1, 0)
+ 
+ DEFPARAM (PARAM_MIN_SIZE_FOR_STACK_SHARING,
+ 	  "min-size-for-stack-sharing",
+Index: b/src/gcc/objc/lang-specs.h
+===================================================================
+--- a/src/gcc/objc/lang-specs.h
++++ b/src/gcc/objc/lang-specs.h
+@@ -29,9 +29,9 @@ along with GCC; see the file COPYING3.
+ 	%{traditional|traditional-cpp:\
+ %eGNU Objective C no longer supports traditional compilation}\
+ 	%{save-temps*|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps*:%b.mi} %{!save-temps*:%g.mi} \n\
+-	    cc1obj -fpreprocessed %{save-temps*:%b.mi} %{!save-temps*:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\
++	    cc1obj -fpreprocessed %{save-temps*:%b.mi} %{!save-temps*:%g.mi} %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}\
+ 	%{!save-temps*:%{!no-integrated-cpp:\
+-	    cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\
++	    cc1obj %(cpp_unique_options) %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}}\
+         %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {"@objective-c-header",
+      "%{E|M|MM:cc1obj -E %{traditional|traditional-cpp:-traditional-cpp}\
+@@ -40,18 +40,18 @@ along with GCC; see the file COPYING3.
+ 	%{traditional|traditional-cpp:\
+ %eGNU Objective C no longer supports traditional compilation}\
+ 	%{save-temps*|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps*:%b.mi} %{!save-temps*:%g.mi} \n\
+-	    cc1obj -fpreprocessed %b.mi %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++	    cc1obj -fpreprocessed %b.mi %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+                         -o %g.s %{!o*:--output-pch=%i.gch}\
+                         %W{o*:--output-pch=%*}%V}\
+ 	%{!save-temps*:%{!no-integrated-cpp:\
+-	    cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++	    cc1obj %(cpp_unique_options) %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+                         -o %g.s %{!o*:--output-pch=%i.gch}\
+                         %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0},
+   {".mi", "@objective-c-cpp-output", 0, 0, 0},
+   {"@objective-c-cpp-output",
+-     "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++     "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+ 			     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {"@objc-cpp-output",
+       "%nobjc-cpp-output is deprecated; please use objective-c-cpp-output instead\n\
+-       %{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++       %{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+ 			     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+Index: b/src/gcc/objcp/lang-specs.h
+===================================================================
+--- a/src/gcc/objcp/lang-specs.h
++++ b/src/gcc/objcp/lang-specs.h
+@@ -36,7 +36,7 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.mii} %{!save-temps*:%g.mii} \n}\
+       cc1objplus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.mii} %{!save-temps*:%g.mii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+         -o %g.s %{!o*:--output-pch=%i.gch} %W{o*:--output-pch=%*}%V}}}",
+      CPLUSPLUS_CPP_SPEC, 0, 0},
+   {"@objective-c++",
+@@ -46,16 +46,16 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.mii} %{!save-temps*:%g.mii} \n}\
+       cc1objplus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.mii} %{!save-temps*:%g.mii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+        %{!fsyntax-only:%(invoke_as)}}}}",
+      CPLUSPLUS_CPP_SPEC, 0, 0},
+   {".mii", "@objective-c++-cpp-output", 0, 0, 0},
+   {"@objective-c++-cpp-output",
+    "%{!M:%{!MM:%{!E:\
+-    cc1objplus -fpreprocessed %i %(cc1_options) %2\
++    cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2\
+     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {"@objc++-cpp-output",
+    "%nobjc++-cpp-output is deprecated; please use objective-c++-cpp-output instead\n\
+     %{!M:%{!MM:%{!E:\
+-    cc1objplus -fpreprocessed %i %(cc1_options) %2\
++    cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2\
+     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -10350,6 +10350,9 @@ protection when @option{-fstack-protecti
+ The minimum size of variables taking part in stack slot sharing when not
+ optimizing. The default value is 32.
+ 
++This default before Ubuntu 10.10 was "8". Currently it is "4", to increase
++the number of functions protected by the stack protector.
++
+ @item max-jump-thread-duplication-stmts
+ Maximum number of statements allowed in a block that needs to be
+ duplicated when threading jumps.
+@@ -11268,6 +11271,10 @@ functions with buffers larger than 8 byt
+ when a function is entered and then checked when the function exits.
+ If a guard check fails, an error message is printed and the program exits.
+ 
++NOTE: In Ubuntu 6.10 and later versions this option is enabled by default
++for C, C++, ObjC, ObjC++, if none of @option{-fno-stack-protector},
++@option{-nostdlib}, nor @option{-ffreestanding} are found.
++
+ @item -fstack-protector-all
+ @opindex fstack-protector-all
+ Like @option{-fstack-protector} except that all functions are protected.
--- gcc-6-6.3.0.orig/debian/patches/gcc-driver-extra-langs-linaro.diff
+++ gcc-6-6.3.0/debian/patches/gcc-driver-extra-langs-linaro.diff
@@ -0,0 +1,22 @@
+# DP: Add options and specs for languages that are not built from a source
+# DP: (but built from separate sources).
+
+---
+ gcc/Makefile.in |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -527,8 +527,8 @@ xm_include_list=@xm_include_list@
+ xm_defines=@xm_defines@
+ lang_checks=
+ lang_checks_parallelized=
+-lang_opt_files=@lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt
+-lang_specs_files=@lang_specs_files@
++lang_opt_files=$(sort @lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang.opt))
++lang_specs_files=$(sort @lang_specs_files@ $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang-specs.h))
+ lang_tree_files=@lang_tree_files@
+ target_cpu_default=@target_cpu_default@
+ OBJC_BOEHM_GC=@objc_boehm_gc@
--- gcc-6-6.3.0.orig/debian/patches/gcc-driver-extra-langs.diff
+++ gcc-6-6.3.0/debian/patches/gcc-driver-extra-langs.diff
@@ -0,0 +1,22 @@
+# DP: Add options and specs for languages that are not built from a source
+# DP: (but built from separate sources).
+
+---
+ gcc/Makefile.in |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -542,8 +542,8 @@ xm_include_list=@xm_include_list@
+ xm_defines=@xm_defines@
+ lang_checks=
+ lang_checks_parallelized=
+-lang_opt_files=@lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt
+-lang_specs_files=@lang_specs_files@
++lang_opt_files=$(sort @lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang.opt))
++lang_specs_files=$(sort @lang_specs_files@ $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang-specs.h))
+ lang_tree_files=@lang_tree_files@
+ target_cpu_default=@target_cpu_default@
+ OBJC_BOEHM_GC=@objc_boehm_gc@
--- gcc-6-6.3.0.orig/debian/patches/gcc-fuse-ld-lld-doc.diff
+++ gcc-6-6.3.0/debian/patches/gcc-fuse-ld-lld-doc.diff
@@ -0,0 +1,17 @@
+# DP: Allow to use lld with -fuse-ld=ld.lld (documentation)
+
+Index: gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi	(revision 246158)
++++ a/src/gcc/doc/invoke.texi	(working copy)
+@@ -10501,6 +10501,10 @@
+ @opindex fuse-ld=gold
+ Use the @command{gold} linker instead of the default linker.
+ 
++@item -fuse-ld=lld
++@opindex fuse-ld=lld
++Use the LLVM @command{lld} linker instead of the default linker.
++
+ @cindex Libraries
+ @item -l@var{library}
+ @itemx -l @var{library}
--- gcc-6-6.3.0.orig/debian/patches/gcc-fuse-ld-lld.diff
+++ gcc-6-6.3.0/debian/patches/gcc-fuse-ld-lld.diff
@@ -0,0 +1,83 @@
+# DP: Allow to use lld with -fuse-ld=ld.lld
+
+Index: gcc/collect2.c
+===================================================================
+--- a/src/gcc/collect2.c	(revision 246158)
++++ a/src/gcc/collect2.c	(working copy)
+@@ -831,6 +831,7 @@
+       USE_PLUGIN_LD,
+       USE_GOLD_LD,
+       USE_BFD_LD,
++      USE_LLD_LD,
+       USE_LD_MAX
+     } selected_linker = USE_DEFAULT_LD;
+   static const char *const ld_suffixes[USE_LD_MAX] =
+@@ -838,7 +839,8 @@
+       "ld",
+       PLUGIN_LD_SUFFIX,
+       "ld.gold",
+-      "ld.bfd"
++      "ld.bfd",
++      "ld.lld"
+     };
+   static const char *const real_ld_suffix = "real-ld";
+   static const char *const collect_ld_suffix = "collect-ld";
+@@ -1004,6 +1006,8 @@
+ 	  selected_linker = USE_BFD_LD;
+ 	else if (strcmp (argv[i], "-fuse-ld=gold") == 0)
+ 	  selected_linker = USE_GOLD_LD;
++  else if (strcmp (argv[i], "-fuse-ld=lld") == 0)
++    selected_linker = USE_LLD_LD;
+ 
+ #ifdef COLLECT_EXPORT_LIST
+ 	/* These flags are position independent, although their order
+@@ -1093,7 +1097,8 @@
+   /* Maybe we know the right file to use (if not cross).  */
+   ld_file_name = 0;
+ #ifdef DEFAULT_LINKER
+-  if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD)
++  if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD ||
++      selected_linker == USE_LLD_LD)
+     {
+       char *linker_name;
+ # ifdef HOST_EXECUTABLE_SUFFIX
+@@ -1307,7 +1312,7 @@
+ 	      else if (!use_collect_ld
+ 		       && strncmp (arg, "-fuse-ld=", 9) == 0)
+ 		{
+-		  /* Do not pass -fuse-ld={bfd|gold} to the linker. */
++		  /* Do not pass -fuse-ld={bfd|gold|lld} to the linker. */
+ 		  ld1--;
+ 		  ld2--;
+ 		}
+Index: gcc/common.opt
+===================================================================
+--- a/src/gcc/common.opt	(revision 246158)
++++ a/src/gcc/common.opt	(working copy)
+@@ -2512,9 +2512,13 @@
+ Use the bfd linker instead of the default linker.
+ 
+ fuse-ld=gold
+-Common Driver Negative(fuse-ld=bfd)
++Common Driver Negative(fuse-ld=lld)
+ Use the gold linker instead of the default linker.
+ 
++fuse-ld=lld
++Common Driver Negative(fuse-ld=bfd)
++Use the lld LLVM linker instead of the default linker.
++
+ fuse-linker-plugin
+ Common Undocumented Var(flag_use_linker_plugin)
+ 
+Index: gcc/opts.c
+===================================================================
+--- a/src/gcc/opts.c	(revision 246158)
++++ a/src/gcc/opts.c	(working copy)
+@@ -2168,6 +2168,7 @@
+ 
+     case OPT_fuse_ld_bfd:
+     case OPT_fuse_ld_gold:
++    case OPT_fuse_ld_lld:
+     case OPT_fuse_linker_plugin:
+       /* No-op. Used by the driver and passed to us because it starts with f.*/
+       break;
--- gcc-6-6.3.0.orig/debian/patches/gcc-gfdl-build.diff
+++ gcc-6-6.3.0/debian/patches/gcc-gfdl-build.diff
@@ -0,0 +1,39 @@
+# DP: Build a dummy s-tm-texi without access to the texinfo sources
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -2312,30 +2312,8 @@ s-tm-texi: $(srcdir)/doc/../doc/tm.texi
+ # \r is not portable to Solaris tr, therefore we have a special
+ # case for ASCII.  We use \r for other encodings like EBCDIC.
+ s-tm-texi: build/genhooks$(build_exeext) $(srcdir)/doc/tm.texi.in
+-	$(RUN_GEN) build/genhooks$(build_exeext) -d \
+-			$(srcdir)/doc/tm.texi.in > tmp-tm.texi
+-	case `echo X|tr X '\101'` in \
+-	  A) tr -d '\015' < tmp-tm.texi > tmp2-tm.texi ;; \
+-	  *) tr -d '\r' < tmp-tm.texi > tmp2-tm.texi ;; \
+-	esac
+-	mv tmp2-tm.texi tmp-tm.texi
+-	$(SHELL) $(srcdir)/../move-if-change tmp-tm.texi tm.texi
+-	@if cmp -s $(srcdir)/doc/tm.texi tm.texi; then \
+-	  $(STAMP) $@; \
+-	elif test $(srcdir)/doc/tm.texi -nt $(srcdir)/doc/tm.texi.in \
+-	  && ( test $(srcdir)/doc/tm.texi -nt $(srcdir)/target.def \
+-	    || test $(srcdir)/doc/tm.texi -nt $(srcdir)/c-family/c-target.def \
+-	    || test $(srcdir)/doc/tm.texi -nt $(srcdir)/common/common-target.def \
+-	  ); then \
+-	  echo >&2 ; \
+-	  echo You should edit $(srcdir)/doc/tm.texi.in rather than $(srcdir)/doc/tm.texi . >&2 ; \
+-	  false; \
+-	else \
+-	  echo >&2 ; \
+-	  echo Verify that you have permission to grant a GFDL license for all >&2 ; \
+-	  echo new text in tm.texi, then copy it to $(srcdir)/doc/tm.texi. >&2 ; \
+-	  false; \
+-	fi
++	cat $(srcdir)/doc/tm.texi.in > tmp-tm.texi
++	$(STAMP) $@
+ 
+ gimple-match.c: s-match gimple-match-head.c ; @true
+ generic-match.c: s-match generic-match-head.c ; @true
--- gcc-6-6.3.0.orig/debian/patches/gcc-hash-style-both.diff
+++ gcc-6-6.3.0/debian/patches/gcc-hash-style-both.diff
@@ -0,0 +1,167 @@
+# DP: Link using --hash-style=both (alpha, amd64, armel, armhf, ia64, i386, powerpc, ppc64, s390, sparc)
+
+2006-07-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/linux.h (LINK_SPEC): Add --hash-style=both.
+	* config/i386/linux64.h (LINK_SPEC): Likewise.
+	* config/rs6000/sysv4.h (LINK_OS_LINUX_SPEC): Likewise.
+	* config/rs6000/linux64.h (LINK_OS_LINUX_SPEC32,
+	LINK_OS_LINUX_SPEC64): Likewise.
+	* config/s390/linux.h (LINK_SPEC): Likewise.
+	* config/ia64/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux64.h (LINK_SPEC, LINK_ARCH32_SPEC,
+	LINK_ARCH64_SPEC): Likewise.
+	* config/alpha/linux-elf.h (LINK_SPEC): Likewise.
+
+2009-12-21  Matthias Klose  <doko@ubuntu.com>
+
+	* config/arm/linux-elf.h (LINK_SPEC): Add --hash-style=both.
+
+2012-11-17  Matthias Klose  <doko@ubuntu.com>
+
+	* config/aarch64/aarch64-linux.h (LINK_SPEC): Add --hash-style=both.
+	
+---
+ gcc/config/alpha/linux-elf.h |    2 +-
+ gcc/config/i386/linux.h      |    2 +-
+ gcc/config/i386/linux64.h    |    2 +-
+ gcc/config/ia64/linux.h      |    2 +-
+ gcc/config/rs6000/linux64.h  |    4 ++--
+ gcc/config/rs6000/sysv4.h    |    2 +-
+ gcc/config/s390/linux.h      |    2 +-
+ gcc/config/sparc/linux.h     |    2 +-
+ 8 files changed, 9 insertions(+), 9 deletions(-)
+
+Index: b/src/gcc/config/alpha/linux-elf.h
+===================================================================
+--- a/src/gcc/config/alpha/linux-elf.h
++++ b/src/gcc/config/alpha/linux-elf.h
+@@ -37,7 +37,7 @@
+ 
+ #define ELF_DYNAMIC_LINKER	GNU_USER_DYNAMIC_LINKER
+ 
+-#define LINK_SPEC "-m elf64alpha %{G*} %{relax:-relax}		\
++#define LINK_SPEC "-m elf64alpha --hash-style=both %{G*} %{relax:-relax}	\
+   %{O*:-O3} %{!O*:-O1}						\
+   %{shared:-shared}						\
+   %{!shared:							\
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -58,7 +58,7 @@
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+ 
+ #undef LINK_SPEC
+-#define LINK_SPEC "\
++#define LINK_SPEC " --hash-style=both \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -385,11 +385,11 @@
+ 					   " -m elf64ppc")
+ #endif
+ 
+-#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=both %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}}"
+ 
+-#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=both %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}}"
+ 
+Index: b/src/gcc/config/rs6000/sysv4.h
+===================================================================
+--- a/src/gcc/config/rs6000/sysv4.h
++++ b/src/gcc/config/rs6000/sysv4.h
+@@ -788,7 +788,7 @@
+ #define GNU_USER_DYNAMIC_LINKER \
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+ 
+-#define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=both %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
+ 
+Index: b/src/gcc/config/s390/linux.h
+===================================================================
+--- a/src/gcc/config/s390/linux.h
++++ b/src/gcc/config/s390/linux.h
+@@ -65,7 +65,7 @@
+ 
+ #undef  LINK_SPEC
+ #define LINK_SPEC \
+-  "%{m31:-m elf_s390}%{m64:-m elf64_s390} \
++  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=both \
+    %{shared:-shared} \
+    %{!shared: \
+       %{static:-static} \
+Index: b/src/gcc/config/sparc/linux.h
+===================================================================
+--- a/src/gcc/config/sparc/linux.h
++++ b/src/gcc/config/sparc/linux.h
+@@ -86,7 +86,7 @@
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+ 
+ #undef  LINK_SPEC
+-#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
++#define LINK_SPEC "-m elf32_sparc --hash-style=both %{shared:-shared} \
+   %{!mno-relax:%{!r:-relax}} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/arm/linux-elf.h
+===================================================================
+--- a/src/gcc/config/arm/linux-elf.h
++++ b/src/gcc/config/arm/linux-elf.h
+@@ -67,6 +67,7 @@
+      %{rdynamic:-export-dynamic} \
+      -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \
+    -X \
++   --hash-style=both \
+    %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
+    SUBTARGET_EXTRA_LINK_SPEC
+ 
+Index: b/src/gcc/config/i386/gnu-user.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user.h
++++ b/src/gcc/config/i386/gnu-user.h
+@@ -74,7 +74,7 @@
+   { "link_emulation", GNU_USER_LINK_EMULATION },\
+   { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+ 
+-#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) %{shared:-shared} \
++#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=both %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/gcc/config/i386/gnu-user64.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user64.h
++++ b/src/gcc/config/i386/gnu-user64.h
+@@ -56,6 +56,7 @@
+                   "%{" SPEC_64 ":-m " GNU_USER_LINK_EMULATION64 "} \
+                    %{" SPEC_32 ":-m " GNU_USER_LINK_EMULATION32 "} \
+                    %{" SPEC_X32 ":-m " GNU_USER_LINK_EMULATIONX32 "} \
++  --hash-style=both \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/aarch64/aarch64-linux.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-linux.h
++++ b/src/gcc/config/aarch64/aarch64-linux.h
+@@ -24,6 +24,7 @@
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1"
+ 
+ #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
++   --hash-style=both				\
+    %{static:-Bstatic}				\
+    %{shared:-shared}				\
+    %{symbolic:-Bsymbolic}			\
--- gcc-6-6.3.0.orig/debian/patches/gcc-hash-style-gnu.diff
+++ gcc-6-6.3.0/debian/patches/gcc-hash-style-gnu.diff
@@ -0,0 +1,169 @@
+# DP: Link using --hash-style=gnu (aarch64, alpha, amd64, armel, armhf, ia64,
+# DP: i386, powerpc, ppc64, s390, sparc)
+
+2006-07-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/linux.h (LINK_SPEC): Add --hash-style=gnu.
+	* config/i386/linux64.h (LINK_SPEC): Likewise.
+	* config/rs6000/sysv4.h (LINK_OS_LINUX_SPEC): Likewise.
+	* config/rs6000/linux64.h (LINK_OS_LINUX_SPEC32,
+	LINK_OS_LINUX_SPEC64): Likewise.
+	* config/s390/linux.h (LINK_SPEC): Likewise.
+	* config/ia64/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux64.h (LINK_SPEC, LINK_ARCH32_SPEC,
+	LINK_ARCH64_SPEC): Likewise.
+	* config/alpha/linux-elf.h (LINK_SPEC): Likewise.
+
+2009-12-21  Matthias Klose  <doko@ubuntu.com>
+
+	* config/arm/linux-elf.h (LINK_SPEC): Add --hash-style=gnu.
+
+2012-11-17  Matthias Klose  <doko@ubuntu.com>
+
+	* config/aarch64/aarch64-linux.h (LINK_SPEC): Add --hash-style=gnu.
+	
+---
+ gcc/config/alpha/linux-elf.h |    2 +-
+ gcc/config/i386/linux.h      |    2 +-
+ gcc/config/i386/linux64.h    |    2 +-
+ gcc/config/ia64/linux.h      |    2 +-
+ gcc/config/rs6000/linux64.h  |    4 ++--
+ gcc/config/rs6000/sysv4.h    |    2 +-
+ gcc/config/s390/linux.h      |    2 +-
+ gcc/config/sparc/linux.h     |    2 +-
+ 8 files changed, 9 insertions(+), 9 deletions(-)
+
+Index: b/src/gcc/config/alpha/linux-elf.h
+===================================================================
+--- a/src/gcc/config/alpha/linux-elf.h
++++ b/src/gcc/config/alpha/linux-elf.h
+@@ -37,7 +37,7 @@ along with GCC; see the file COPYING3.
+ 
+ #define ELF_DYNAMIC_LINKER	GNU_USER_DYNAMIC_LINKER
+ 
+-#define LINK_SPEC "-m elf64alpha %{G*} %{relax:-relax}		\
++#define LINK_SPEC "-m elf64alpha --hash-style=gnu %{G*} %{relax:-relax}	\
+   %{O*:-O3} %{!O*:-O1}						\
+   %{shared:-shared}						\
+   %{!shared:							\
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -58,7 +58,7 @@ do {						\
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+ 
+ #undef LINK_SPEC
+-#define LINK_SPEC "\
++#define LINK_SPEC " --hash-style=gnu \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -469,12 +469,12 @@ extern int dot_symbols;
+ 					   " -m elf64ppc")
+ #endif
+ 
+-#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=gnu %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
+   %(link_os_extra_spec32)"
+ 
+-#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=gnu %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}} \
+   %(link_os_extra_spec64)"
+Index: b/src/gcc/config/rs6000/sysv4.h
+===================================================================
+--- a/src/gcc/config/rs6000/sysv4.h
++++ b/src/gcc/config/rs6000/sysv4.h
+@@ -795,7 +795,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \
+ 			 MUSL_DYNAMIC_LINKER)
+ 
+-#define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
+ 
+Index: b/src/gcc/config/s390/linux.h
+===================================================================
+--- a/src/gcc/config/s390/linux.h
++++ b/src/gcc/config/s390/linux.h
+@@ -65,7 +65,7 @@ along with GCC; see the file COPYING3.
+ 
+ #undef  LINK_SPEC
+ #define LINK_SPEC \
+-  "%{m31:-m elf_s390}%{m64:-m elf64_s390} \
++  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu \
+    %{shared:-shared} \
+    %{!shared: \
+       %{static:-static} \
+Index: b/src/gcc/config/sparc/linux.h
+===================================================================
+--- a/src/gcc/config/sparc/linux.h
++++ b/src/gcc/config/sparc/linux.h
+@@ -86,7 +86,7 @@ extern const char *host_detect_local_cpu
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+ 
+ #undef  LINK_SPEC
+-#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
++#define LINK_SPEC "-m elf32_sparc --hash-style=gnu %{shared:-shared} \
+   %{!mno-relax:%{!r:-relax}} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/arm/linux-elf.h
+===================================================================
+--- a/src/gcc/config/arm/linux-elf.h
++++ b/src/gcc/config/arm/linux-elf.h
+@@ -72,6 +72,7 @@
+      %{rdynamic:-export-dynamic} \
+      %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+    -X \
++   --hash-style=gnu \
+    %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
+    SUBTARGET_EXTRA_LINK_SPEC
+ 
+Index: b/src/gcc/config/i386/gnu-user.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user.h
++++ b/src/gcc/config/i386/gnu-user.h
+@@ -74,7 +74,7 @@ along with GCC; see the file COPYING3.
+   { "link_emulation", GNU_USER_LINK_EMULATION },\
+   { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+ 
+-#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) %{shared:-shared} \
++#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=gnu %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/gcc/config/i386/gnu-user64.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user64.h
++++ b/src/gcc/config/i386/gnu-user64.h
+@@ -56,6 +56,7 @@ see the files COPYING3 and COPYING.RUNTI
+                   "%{" SPEC_64 ":-m " GNU_USER_LINK_EMULATION64 "} \
+                    %{" SPEC_32 ":-m " GNU_USER_LINK_EMULATION32 "} \
+                    %{" SPEC_X32 ":-m " GNU_USER_LINK_EMULATIONX32 "} \
++  --hash-style=gnu \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/aarch64/aarch64-linux.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-linux.h
++++ b/src/gcc/config/aarch64/aarch64-linux.h
+@@ -35,6 +35,7 @@
+ #define CPP_SPEC "%{pthread:-D_REENTRANT}"
+ 
+ #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
++   --hash-style=gnu				\
+    %{static:-Bstatic}				\
+    %{shared:-shared}				\
+    %{symbolic:-Bsymbolic}			\
--- gcc-6-6.3.0.orig/debian/patches/gcc-ia64-bootstrap-ignore.diff
+++ gcc-6-6.3.0/debian/patches/gcc-ia64-bootstrap-ignore.diff
@@ -0,0 +1,17 @@
+# DP: Ignore bootstrap comparison failure on ia64. Filed upstream as
+# DP: PR middle-end/65874.
+
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -3595,6 +3595,9 @@ fi
+ 
+ compare_exclusions="gcc/cc*-checksum\$(objext) | gcc/ada/*tools/*"
+ case "$target" in
++  ia64-*linux-gnu)
++    compare_exclusions="gcc/cc*-checksum\$(objext) | gcc/ada/*tools/* | gcc/ira.o"
++    ;;
+   hppa*64*-*-hpux*) ;;
+   hppa*-*-hpux*) compare_exclusions="gcc/cc*-checksum\$(objext) | */libgcc/lib2funcs* | gcc/ada/*tools/*" ;;
+   powerpc*-ibm-aix*) compare_exclusions="gcc/cc*-checksum\$(objext) | gcc/ada/*tools/* | *libgomp*\$(objext)" ;;
--- gcc-6-6.3.0.orig/debian/patches/gcc-ice-apport.diff
+++ gcc-6-6.3.0/debian/patches/gcc-ice-apport.diff
@@ -0,0 +1,24 @@
+# DP: Report an ICE to apport (if apport is available
+# DP: and the environment variable GCC_NOAPPORT is not set)
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -6860,6 +6860,16 @@ do_report_bug (const char **new_argv, co
+ 	  fflush(stderr);
+ 	  free(cmd);
+ 	}
++      if (!env.get ("GCC_NOAPPORT")
++	  && !access ("/usr/share/apport/gcc_ice_hook", R_OK | X_OK))
++	{
++	  char *cmd = XNEWVEC (char, 50 + strlen (*out_file)
++			       + strlen (new_argv[0]));
++	  sprintf (cmd, "/usr/share/apport/gcc_ice_hook %s %s",
++		   new_argv[0], *out_file);
++	  system (cmd);
++	  free (cmd);
++	}
+       /* Make sure it is not deleted.  */
+       free (*out_file);
+       *out_file = NULL;
--- gcc-6-6.3.0.orig/debian/patches/gcc-ice-dump.diff
+++ gcc-6-6.3.0/debian/patches/gcc-ice-dump.diff
@@ -0,0 +1,41 @@
+# DP: For ICEs, dump the preprocessed source file to stderr
+# DP: when in a distro build environment.
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -3140,7 +3140,8 @@ execute (void)
+ 	    /* For ICEs in cc1, cc1obj, cc1plus see if it is
+ 	       reproducible or not.  */
+ 	    const char *p;
+-	    if (flag_report_bug
++	    const char *deb_build_options = env.get("DEB_BUILD_OPTIONS");
++	    if ((flag_report_bug || deb_build_options)
+ 		&& WEXITSTATUS (status) == ICE_EXIT_CODE
+ 		&& i == 0
+ 		&& (p = strrchr (commands[0].argv[0], DIR_SEPARATOR))
+@@ -6842,8 +6843,23 @@ do_report_bug (const char **new_argv, co
+ 
+   if (status == ATTEMPT_STATUS_SUCCESS)
+     {
++      const char *deb_build_options = env.get("DEB_BUILD_OPTIONS");
++
+       fnotice (stderr, "Preprocessed source stored into %s file,"
+ 	       " please attach this to your bugreport.\n", *out_file);
++      if (deb_build_options)
++	{
++	  char *cmd = XNEWVEC (char, 50 + strlen (*out_file));
++
++	  sprintf(cmd, "/usr/bin/awk '{print \"%d:\", $0}' %s >&2", getpid(), *out_file);
++	  fprintf(stderr, "=== BEGIN GCC DUMP ===\n");
++	  fflush(stderr);
++	  system(cmd);
++	  fflush(stderr);
++	  fprintf(stderr, "=== END GCC DUMP ===\n");
++	  fflush(stderr);
++	  free(cmd);
++	}
+       /* Make sure it is not deleted.  */
+       free (*out_file);
+       *out_file = NULL;
--- gcc-6-6.3.0.orig/debian/patches/gcc-linaro-doc.diff
+++ gcc-6-6.3.0/debian/patches/gcc-linaro-doc.diff
@@ -0,0 +1,658 @@
+# DP: Changes for the Linaro 6-2017.02 release (documentation).
+
+--- a/src/gcc/doc/cpp.texi
++++ b/src/gcc/doc/cpp.texi
+@@ -1984,7 +1984,7 @@ by GCC, or a non-GCC compiler that claims to accept the GNU C dialects,
+ you can simply test @code{__GNUC__}.  If you need to write code
+ which depends on a specific version, you must be more careful.  Each
+ time the minor version is increased, the patch level is reset to zero;
+-each time the major version is increased (which happens rarely), the
++each time the major version is increased, the
+ minor version and patch level are reset.  If you wish to use the
+ predefined macros directly in the conditional, you will need to write it
+ like this:
+--- a/src/gcc/doc/extend.texi
++++ b/src/gcc/doc/extend.texi
+@@ -11416,6 +11416,7 @@ instructions, but allow the compiler to schedule those calls.
+ * ARM iWMMXt Built-in Functions::
+ * ARM C Language Extensions (ACLE)::
+ * ARM Floating Point Status and Control Intrinsics::
++* ARM ARMv8-M Security Extensions::
+ * AVR Built-in Functions::
+ * Blackfin Built-in Functions::
+ * FR-V Built-in Functions::
+@@ -12260,6 +12261,35 @@ unsigned int __builtin_arm_get_fpscr ()
+ void __builtin_arm_set_fpscr (unsigned int)
+ @end smallexample
+ 
++@node ARM ARMv8-M Security Extensions
++@subsection ARM ARMv8-M Security Extensions
++
++GCC implements the ARMv8-M Security Extensions as described in the ARMv8-M
++Security Extensions: Requiremenets on Development Tools Engineering
++Specification, which can be found at
++@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}.
++
++As part of the Security Extensions GCC implements two new function attributes:
++@code{cmse_nonsecure_entry} and @code{cmse_nonsecure_call}.
++
++As part of the Security Extensions GCC implements the intrinsics below.  FPTR
++is used here to mean any function pointer type.
++
++@smallexample
++cmse_address_info_t cmse_TT (void *)
++cmse_address_info_t cmse_TT_fptr (FPTR)
++cmse_address_info_t cmse_TTT (void *)
++cmse_address_info_t cmse_TTT_fptr (FPTR)
++cmse_address_info_t cmse_TTA (void *)
++cmse_address_info_t cmse_TTA_fptr (FPTR)
++cmse_address_info_t cmse_TTAT (void *)
++cmse_address_info_t cmse_TTAT_fptr (FPTR)
++void * cmse_check_address_range (void *, size_t, int)
++typeof(p) cmse_nsfptr_create (FPTR p)
++intptr_t cmse_is_nsfptr (FPTR)
++int cmse_nonsecure_caller (void)
++@end smallexample
++
+ @node AVR Built-in Functions
+ @subsection AVR Built-in Functions
+ 
+--- a/src/gcc/doc/fragments.texi
++++ b/src/gcc/doc/fragments.texi
+@@ -156,15 +156,16 @@ variants.  And for some targets it is better to reuse an existing multilib
+ than to fall back to default multilib when there is no corresponding multilib.
+ This can be done by adding reuse rules to @code{MULTILIB_REUSE}.
+ 
+-A reuse rule is comprised of two parts connected by equality sign.  The left part
+-is option set used to build multilib and the right part is option set that will
+-reuse this multilib.  The order of options in the left part matters and should be
+-same with those specified in @code{MULTILIB_REQUIRED} or aligned with order in
+-@code{MULTILIB_OPTIONS}.  There is no such limitation for options in right part
+-as we don't build multilib from them.  But the equality sign in both parts should
+-be replaced with period.
+-
+-The @code{MULTILIB_REUSE} is different from @code{MULTILIB_MATCHES} in that it
++A reuse rule is comprised of two parts connected by equality sign.  The left
++part is the option set used to build multilib and the right part is the option
++set that will reuse this multilib.  Both parts should only use options
++specified in @code{MULTILIB_OPTIONS} and the equality signs found in options
++name should be replaced with periods.  The order of options in the left part
++matters and should be same with those specified in @code{MULTILIB_REQUIRED} or
++aligned with the order in @code{MULTILIB_OPTIONS}.  There is no such limitation
++for options in the right part as we don't build multilib from them.
++
++@code{MULTILIB_REUSE} is different from @code{MULTILIB_MATCHES} in that it
+ sets up relations between two option sets rather than two options.  Here is an
+ example to demo how we reuse libraries built in Thumb mode for applications built
+ in ARM mode:
+--- a/src/gcc/doc/install.texi
++++ b/src/gcc/doc/install.texi
+@@ -1101,19 +1101,59 @@ sysv, aix.
+ 
+ @item --with-multilib-list=@var{list}
+ @itemx --without-multilib-list
+-Specify what multilibs to build.
+-Currently only implemented for arm*-*-*, sh*-*-* and x86-64-*-linux*.
++Specify what multilibs to build.  @var{list} is a comma separated list of
++values, possibly consisting of a single value.  Currently only implemented
++for arm*-*-*, sh*-*-* and x86-64-*-linux*.  The accepted values and meaning
++for each target is given below.
+ 
+ @table @code
+ @item arm*-*-*
+-@var{list} is either @code{default} or @code{aprofile}.  Specifying
+-@code{default} is equivalent to omitting this option while specifying
+-@code{aprofile} builds multilibs for each combination of ISA (@code{-marm} or
+-@code{-mthumb}), architecture (@code{-march=armv7-a}, @code{-march=armv7ve},
+-or @code{-march=armv8-a}), FPU available (none, @code{-mfpu=vfpv3-d16},
+-@code{-mfpu=neon}, @code{-mfpu=vfpv4-d16}, @code{-mfpu=neon-vfpv4} or
+-@code{-mfpu=neon-fp-armv8} depending on architecture) and floating-point ABI
+-(@code{-mfloat-abi=softfp} or @code{-mfloat-abi=hard}).
++@var{list} is one of@code{default}, @code{aprofile} or @code{rmprofile}.
++Specifying @code{default} is equivalent to omitting this option, ie. only the
++default runtime library will be enabled.  Specifying @code{aprofile} or
++@code{rmprofile} builds multilibs for a combination of ISA, architecture,
++FPU available and floating-point ABI.
++
++The table below gives the combination of ISAs, architectures, FPUs and
++floating-point ABIs for which multilibs are built for each accepted value.
++
++@multitable @columnfractions .15 .28 .30
++@item Option @tab aprofile @tab rmprofile
++@item ISAs
++@tab @code{-marm} and @code{-mthumb}
++@tab @code{-mthumb}
++@item Architectures@*@*@*@*@*@*
++@tab default architecture@*
++@code{-march=armv7-a}@*
++@code{-march=armv7ve}@*
++@code{-march=armv8-a}@*@*@*
++@tab default architecture@*
++@code{-march=armv6s-m}@*
++@code{-march=armv7-m}@*
++@code{-march=armv7e-m}@*
++@code{-march=armv8-m.base}@*
++@code{-march=armv8-m.main}@*
++@code{-march=armv7}
++@item FPUs@*@*@*@*@*
++@tab none@*
++@code{-mfpu=vfpv3-d16}@*
++@code{-mfpu=neon}@*
++@code{-mfpu=vfpv4-d16}@*
++@code{-mfpu=neon-vfpv4}@*
++@code{-mfpu=neon-fp-armv8}
++@tab none@*
++@code{-mfpu=vfpv3-d16}@*
++@code{-mfpu=fpv4-sp-d16}@*
++@code{-mfpu=fpv5-sp-d16}@*
++@code{-mfpu=fpv5-d16}@*
++@item floating-point@/ ABIs@*@*
++@tab @code{-mfloat-abi=soft}@*
++@code{-mfloat-abi=softfp}@*
++@code{-mfloat-abi=hard}
++@tab @code{-mfloat-abi=soft}@*
++@code{-mfloat-abi=softfp}@*
++@code{-mfloat-abi=hard}
++@end multitable
+ 
+ @item sh*-*-*
+ @var{list} is a comma separated list of CPU names.  These must be of the
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -573,6 +573,8 @@ Objective-C and Objective-C++ Dialects}.
+ -mfix-cortex-a53-835769  -mno-fix-cortex-a53-835769 @gol
+ -mfix-cortex-a53-843419  -mno-fix-cortex-a53-843419 @gol
+ -mlow-precision-recip-sqrt -mno-low-precision-recip-sqrt@gol
++-mlow-precision-sqrt -mno-low-precision-sqrt@gol
++-mlow-precision-div -mno-low-precision-div @gol
+ -march=@var{name}  -mcpu=@var{name}  -mtune=@var{name}}
+ 
+ @emph{Adapteva Epiphany Options}
+@@ -632,7 +634,8 @@ Objective-C and Objective-C++ Dialects}.
+ -mneon-for-64bits @gol
+ -mslow-flash-data @gol
+ -masm-syntax-unified @gol
+--mrestrict-it}
++-mrestrict-it @gol
++-mcmse}
+ 
+ @emph{AVR Options}
+ @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
+@@ -9477,6 +9480,11 @@ Size of minimal partition for WHOPR (in estimated instructions).
+ This prevents expenses of splitting very small programs into too many
+ partitions.
+ 
++@item lto-max-partition
++Size of max partition for WHOPR (in estimated instructions).
++to provide an upper bound for individual size of partition.
++Meant to be used only with balanced partitioning.
++
+ @item cxx-max-namespaces-for-diagnostic-help
+ The maximum number of namespaces to consult for suggestions when C++
+ name lookup fails for an identifier.  The default is 1000.
+@@ -12827,9 +12835,9 @@ These options are defined for AArch64 implementations:
+ @item -mabi=@var{name}
+ @opindex mabi
+ Generate code for the specified data model.  Permissible values
+-are @samp{ilp32} for SysV-like data model where int, long int and pointer
+-are 32-bit, and @samp{lp64} for SysV-like data model where int is 32-bit,
+-but long int and pointer are 64-bit.
++are @samp{ilp32} for SysV-like data model where int, long int and pointers
++are 32 bits, and @samp{lp64} for SysV-like data model where int is 32 bits,
++but long int and pointers are 64 bits.
+ 
+ The default depends on the specific target configuration.  Note that
+ the LP64 and ILP32 ABIs are not link-compatible; you must compile your
+@@ -12854,25 +12862,24 @@ Generate little-endian code.  This is the default when GCC is configured for an
+ @item -mcmodel=tiny
+ @opindex mcmodel=tiny
+ Generate code for the tiny code model.  The program and its statically defined
+-symbols must be within 1GB of each other.  Pointers are 64 bits.  Programs can
+-be statically or dynamically linked.  This model is not fully implemented and
+-mostly treated as @samp{small}.
++symbols must be within 1MB of each other.  Programs can be statically or
++dynamically linked.
+ 
+ @item -mcmodel=small
+ @opindex mcmodel=small
+ Generate code for the small code model.  The program and its statically defined
+-symbols must be within 4GB of each other.  Pointers are 64 bits.  Programs can
+-be statically or dynamically linked.  This is the default code model.
++symbols must be within 4GB of each other.  Programs can be statically or
++dynamically linked.  This is the default code model.
+ 
+ @item -mcmodel=large
+ @opindex mcmodel=large
+ Generate code for the large code model.  This makes no assumptions about
+-addresses and sizes of sections.  Pointers are 64 bits.  Programs can be
+-statically linked only.
++addresses and sizes of sections.  Programs can be statically linked only.
+ 
+ @item -mstrict-align
+ @opindex mstrict-align
+-Do not assume that unaligned memory references are handled by the system.
++Avoid generating memory accesses that may not be aligned on a natural object
++boundary as described in the architecture specification.
+ 
+ @item -momit-leaf-frame-pointer
+ @itemx -mno-omit-leaf-frame-pointer
+@@ -12894,7 +12901,7 @@ of TLS variables.
+ @item -mtls-size=@var{size}
+ @opindex mtls-size
+ Specify bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.
+-This option depends on binutils higher than 2.25.
++This option requires binutils 2.26 or newer.
+ 
+ @item -mfix-cortex-a53-835769
+ @itemx -mno-fix-cortex-a53-835769
+@@ -12914,12 +12921,34 @@ corresponding flag to the linker.
+ 
+ @item -mlow-precision-recip-sqrt
+ @item -mno-low-precision-recip-sqrt
+-@opindex -mlow-precision-recip-sqrt
+-@opindex -mno-low-precision-recip-sqrt
+-When calculating the reciprocal square root approximation,
+-uses one less step than otherwise, thus reducing latency and precision.
+-This is only relevant if @option{-ffast-math} enables the reciprocal square root
+-approximation, which in turn depends on the target processor.
++@opindex mlow-precision-recip-sqrt
++@opindex mno-low-precision-recip-sqrt
++Enable or disable the reciprocal square root approximation.
++This option only has an effect if @option{-ffast-math} or
++@option{-funsafe-math-optimizations} is used as well.  Enabling this reduces
++precision of reciprocal square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++
++@item -mlow-precision-sqrt
++@item -mno-low-precision-sqrt
++@opindex -mlow-precision-sqrt
++@opindex -mno-low-precision-sqrt
++Enable or disable the square root approximation.
++This option only has an effect if @option{-ffast-math} or
++@option{-funsafe-math-optimizations} is used as well.  Enabling this reduces
++precision of square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++If enabled, it implies @option{-mlow-precision-recip-sqrt}.
++
++@item -mlow-precision-div
++@item -mno-low-precision-div
++@opindex -mlow-precision-div
++@opindex -mno-low-precision-div
++Enable or disable the division approximation.
++This option only has an effect if @option{-ffast-math} or
++@option{-funsafe-math-optimizations} is used as well.  Enabling this reduces
++precision of division results to about 16 bits for
++single precision and to 32 bits for double precision.
+ 
+ @item -march=@var{name}
+ @opindex march
+@@ -12928,10 +12957,13 @@ more feature modifiers.  This option has the form
+ @option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
+ 
+ The permissible values for @var{arch} are @samp{armv8-a},
+-@samp{armv8.1-a} or @var{native}.
++@samp{armv8.1-a}, @samp{armv8.2-a} or @var{native}.
++
++The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler
++support for the ARMv8.2-A architecture extensions.
+ 
+ The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
+-support for the ARMv8.1 architecture extension.  In particular, it
++support for the ARMv8.1-A architecture extension.  In particular, it
+ enables the @samp{+crc} and @samp{+lse} features.
+ 
+ The value @samp{native} is available on native AArch64 GNU/Linux and
+@@ -12955,18 +12987,18 @@ processors implementing the target architecture.
+ Specify the name of the target processor for which GCC should tune the
+ performance of the code.  Permissible values for this option are:
+ @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+-@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx},
+-@samp{xgene1}.
++@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{qdf24xx},
++@samp{thunderx}, @samp{xgene1}, @samp{vulcan}, @samp{cortex-a57.cortex-a53},
++@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
++@samp{cortex-a73.cortex-a53}, @samp{native}.
+ 
+-Additionally, this option can specify that GCC should tune the performance
+-of the code for a big.LITTLE system.  Permissible values for this
+-option are: @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
++The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
++@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}
++specify that GCC should tune for a big.LITTLE system.
+ 
+ Additionally on native AArch64 GNU/Linux systems the value
+-@samp{native} is available.  This option causes the compiler to pick
+-the architecture of and tune the performance of the code for the
+-processor of the host system.  This option has no effect if the
+-compiler is unable to recognize the architecture of the host system.
++@samp{native} tunes performance to the host system.  This option has no effect
++if the compiler is unable to recognize the processor of the host system.
+ 
+ Where none of @option{-mtune=}, @option{-mcpu=} or @option{-march=}
+ are specified, the code is tuned to perform well across a range
+@@ -12986,12 +13018,6 @@ documented in the sub-section on
+ Feature Modifiers}.  Where conflicting feature modifiers are
+ specified, the right-most feature is used.
+ 
+-Additionally on native AArch64 GNU/Linux systems the value
+-@samp{native} is available.  This option causes the compiler to tune
+-the performance of the code for the processor of the host system.
+-This option has no effect if the compiler is unable to recognize the
+-architecture of the host system.
+-
+ GCC uses @var{name} to determine what kind of instructions it can emit when
+ generating assembly code (as if by @option{-march}) and to determine
+ the target processor for which to tune for performance (as if
+@@ -13009,11 +13035,11 @@ across releases.
+ This option is only intended to be useful when developing GCC.
+ 
+ @item -mpc-relative-literal-loads
+-@opindex mpcrelativeliteralloads
+-Enable PC relative literal loads. If this option is used, literal
+-pools are assumed to have a range of up to 1MiB and an appropriate
+-instruction sequence is used. This option has no impact when used
+-with @option{-mcmodel=tiny}.
++@opindex mpc-relative-literal-loads
++Enable PC-relative literal loads.  With this option literal pools are
++accessed using a single instruction and emitted after each function.  This
++limits the maximum size of functions to 1MB.  This is enabled by default for
++@option{-mcmodel=tiny}.
+ 
+ @end table
+ 
+@@ -13041,12 +13067,14 @@ instructions.  This is on by default for all possible values for options
+ @item lse
+ Enable Large System Extension instructions.  This is on by default for
+ @option{-march=armv8.1-a}.
++@item fp16
++Enable FP16 extension.  This also enables floating-point instructions.
+ 
+ @end table
+ 
+-That is, @option{crypto} implies @option{simd} implies @option{fp}.
+-Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only})
+-implies @option{nosimd} implies @option{nocrypto}.
++Feature @option{crypto} implies @option{simd}, which implies @option{fp}.
++Conversely, @option{nofp} implies @option{nosimd}, which implies
++@option{nocrypto}.
+ 
+ @node Adapteva Epiphany Options
+ @subsection Adapteva Epiphany Options
+@@ -13966,21 +13994,42 @@ name to determine what kind of instructions it can emit when generating
+ assembly code.  This option can be used in conjunction with or instead
+ of the @option{-mcpu=} option.  Permissible names are: @samp{armv2},
+ @samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
+-@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te},
+-@samp{armv6}, @samp{armv6j},
+-@samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
+-@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
++@samp{armv5}, @samp{armv5e}, @samp{armv5t}, @samp{armv5te},
++@samp{armv6}, @samp{armv6-m}, @samp{armv6j}, @samp{armv6k},
++@samp{armv6kz}, @samp{armv6s-m},
++@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk},
++@samp{armv7}, @samp{armv7-a}, @samp{armv7-m}, @samp{armv7-r}, @samp{armv7e-m},
+ @samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
+-@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
++@samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main},
++@samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}.
++
++Architecture revisions older than @samp{armv4t} are deprecated.
+ 
+-Architecture revisions older than @option{armv4t} are deprecated.
++@option{-march=armv6s-m} is the @samp{armv6-m} architecture with support for
++the (now mandatory) SVC instruction.
+ 
+-@option{-march=armv7ve} is the armv7-a architecture with virtualization
++@option{-march=armv6zk} is an alias for @samp{armv6kz}, existing for backwards
++compatibility.
++
++@option{-march=armv7ve} is the @samp{armv7-a} architecture with virtualization
+ extensions.
+ 
+ @option{-march=armv8-a+crc} enables code generation for the ARMv8-A
+ architecture together with the optional CRC32 extensions.
+ 
++@option{-march=armv8.1-a} enables compiler support for the ARMv8.1-A
++architecture.  This also enables the features provided by
++@option{-march=armv8-a+crc}.
++
++@option{-march=armv8.2-a} enables compiler support for the ARMv8.2-A
++architecture.  This also enables the features provided by
++@option{-march=armv8.1-a}.
++
++@option{-march=armv8.2-a+fp16} enables compiler support for the
++ARMv8.2-A architecture with the optional FP16 instructions extension.
++This also enables the features provided by @option{-march=armv8.1-a}
++and implies @option{-mfp16-format=ieee}.
++
+ @option{-march=native} causes the compiler to auto-detect the architecture
+ of the build computer.  At present, this feature is only supported on
+ GNU/Linux, and not all architectures are recognized.  If the auto-detect
+@@ -14012,8 +14061,10 @@ Permissible names are: @samp{arm2}, @samp{arm250},
+ @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
+ @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
+ @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+-@samp{cortex-a72}, @samp{cortex-r4},
++@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4},
+ @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
++@samp{cortex-m33},
++@samp{cortex-m23},
+ @samp{cortex-m7},
+ @samp{cortex-m4},
+ @samp{cortex-m3},
+@@ -14034,7 +14085,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
+ Additionally, this option can specify that GCC should tune the performance
+ of the code for a big.LITTLE system.  Permissible names are:
+ @samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
+-@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
++@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
++@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}.
+ 
+ @option{-mtune=generic-@var{arch}} specifies that GCC should tune the
+ performance for a blend of processors within architecture @var{arch}.
+@@ -14164,9 +14216,12 @@ otherwise the default is @samp{R10}.
+ 
+ @item -mpic-data-is-text-relative
+ @opindex mpic-data-is-text-relative
+-Assume that each data segments are relative to text segment at load time.
+-Therefore, it permits addressing data using PC-relative operations.
+-This option is on by default for targets other than VxWorks RTP.
++Assume that the displacement between the text and data segments is fixed
++at static link time.  This permits using PC-relative addressing
++operations to access data known to be in the data segment.  For
++non-VxWorks RTP targets, this option is enabled by default.  When
++disabled on such targets, it will enable @option{-msingle-pic-base} by
++default.
+ 
+ @item -mpoke-function-name
+ @opindex mpoke-function-name
+@@ -14276,10 +14331,10 @@ generating these instructions.  This option is enabled by default when
+ @opindex mno-unaligned-access
+ Enables (or disables) reading and writing of 16- and 32- bit values
+ from addresses that are not 16- or 32- bit aligned.  By default
+-unaligned access is disabled for all pre-ARMv6 and all ARMv6-M
+-architectures, and enabled for all other architectures.  If unaligned
+-access is not enabled then words in packed data structures are
+-accessed a byte at a time.
++unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for
++ARMv8-M Baseline architectures, and enabled for all other
++architectures.  If unaligned access is not enabled then words in packed
++data structures are accessed a byte at a time.
+ 
+ The ARM attribute @code{Tag_CPU_unaligned_access} is set in the
+ generated object file to either true or false, depending upon the
+@@ -14319,6 +14374,12 @@ Print CPU tuning information as comment in assembler file.  This is
+ an option used only for regression testing of the compiler and not
+ intended for ordinary use in compiling code.  This option is disabled
+ by default.
++
++@item -mcmse
++@opindex mcmse
++Generate secure code as per the "ARMv8-M Security Extensions: Requirements on
++Development Tools Engineering Specification", which can be found on
++@url{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}.
+ @end table
+ 
+ @node AVR Options
+@@ -18081,7 +18142,7 @@ IEEE 754 floating-point data.
+ 
+ The @option{-mnan=legacy} option selects the legacy encoding.  In this
+ case quiet NaNs (qNaNs) are denoted by the first bit of their trailing
+-significand field being 0, whereas signalling NaNs (sNaNs) are denoted
++significand field being 0, whereas signaling NaNs (sNaNs) are denoted
+ by the first bit of their trailing significand field being 1.
+ 
+ The @option{-mnan=2008} option selects the IEEE 754-2008 encoding.  In
+--- a/src/gcc/doc/md.texi
++++ b/src/gcc/doc/md.texi
+@@ -5027,7 +5027,7 @@ it is unspecified which of the two operands is returned as the result.
+ IEEE-conformant minimum and maximum operations.  If one operand is a quiet
+ @code{NaN}, then the other operand is returned.  If both operands are quiet
+ @code{NaN}, then a quiet @code{NaN} is returned.  In the case when gcc supports
+-signalling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
++signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
+ raised and a quiet @code{NaN} is returned.
+ 
+ All operands have mode @var{m}, which is a scalar or vector
+--- a/src/gcc/doc/sourcebuild.texi
++++ b/src/gcc/doc/sourcebuild.texi
+@@ -1555,6 +1555,16 @@ options.  Some multilibs may be incompatible with these options.
+ ARM Target supports @code{-mfpu=neon-vfpv4 -mfloat-abi=softfp} or compatible
+ options.  Some multilibs may be incompatible with these options.
+ 
++@item arm_fp16_ok
++@anchor{arm_fp16_ok}
++Target supports options to generate VFP half-precision floating-point
++instructions.  Some multilibs may be incompatible with these
++options.  This test is valid for ARM only.
++
++@item arm_fp16_hw
++Target supports executing VFP half-precision floating-point
++instructions.  This test is valid for ARM only.
++
+ @item arm_neon_fp16_ok
+ @anchor{arm_neon_fp16_ok}
+ ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible
+@@ -1565,6 +1575,13 @@ options, including @code{-mfp16-format=ieee} if necessary to obtain the
+ Test system supports executing Neon half-precision float instructions.
+ (Implies previous.)
+ 
++@item arm_fp16_alternative_ok
++ARM target supports the ARM FP16 alternative format.  Some multilibs
++may be incompatible with the options needed.
++
++@item arm_fp16_none_ok
++ARM target supports specifying none as the ARM FP16 format.
++
+ @item arm_thumb1_ok
+ ARM target generates Thumb-1 code for @code{-mthumb}.
+ 
+@@ -1589,6 +1606,7 @@ ARM target supports @code{-mfpu=neon-fp-armv8 -mfloat-abi=softfp}.
+ Some multilibs may be incompatible with these options.
+ 
+ @item arm_v8_1a_neon_ok
++@anchor{arm_v8_1a_neon_ok}
+ ARM target supports options to generate ARMv8.1 Adv.SIMD instructions.
+ Some multilibs may be incompatible with these options.
+ 
+@@ -1597,10 +1615,47 @@ ARM target supports executing ARMv8.1 Adv.SIMD instructions.  Some
+ multilibs may be incompatible with the options needed.  Implies
+ arm_v8_1a_neon_ok.
+ 
++@item arm_acq_rel
++ARM target supports acquire-release instructions.
++
++@item arm_v8_2a_fp16_scalar_ok
++@anchor{arm_v8_2a_fp16_scalar_ok}
++ARM target supports options to generate instructions for ARMv8.2 and
++scalar instructions from the FP16 extension.  Some multilibs may be
++incompatible with these options.
++
++@item arm_v8_2a_fp16_scalar_hw
++ARM target supports executing instructions for ARMv8.2 and scalar
++instructions from the FP16 extension.  Some multilibs may be
++incompatible with these options.  Implies arm_v8_2a_fp16_neon_ok.
++
++@item arm_v8_2a_fp16_neon_ok
++@anchor{arm_v8_2a_fp16_neon_ok}
++ARM target supports options to generate instructions from ARMv8.2 with
++the FP16 extension.  Some multilibs may be incompatible with these
++options.  Implies arm_v8_2a_fp16_scalar_ok.
++
++@item arm_v8_2a_fp16_neon_hw
++ARM target supports executing instructions from ARMv8.2 with the FP16
++extension.  Some multilibs may be incompatible with these options.
++Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw.
++
+ @item arm_prefer_ldrd_strd
+ ARM target prefers @code{LDRD} and @code{STRD} instructions over
+ @code{LDM} and @code{STM} instructions.
+ 
++@item arm_thumb1_movt_ok
++ARM target generates Thumb-1 code for @code{-mthumb} with @code{MOVW}
++and @code{MOVT} instructions available.
++
++@item arm_thumb1_cbz_ok
++ARM target generates Thumb-1 code for @code{-mthumb} with
++@code{CBZ} and @code{CBNZ} instructions available.
++
++@item arm_cmse_ok
++ARM target supports ARMv8-M Security Extensions, enabled by the @code{-mcmse}
++option.
++
+ @end table
+ 
+ @subsubsection AArch64-specific attributes
+@@ -2066,6 +2121,28 @@ NEON support.  Only ARM targets support this feature, and only then
+ in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target
+ keyword}.
+ 
++@item arm_fp16
++VFP half-precision floating point support.  This does not select the
++FP16 format; for that, use @ref{arm_fp16_ieee,,arm_fp16_ieee} or
++@ref{arm_fp16_alternative,,arm_fp16_alternative} instead.  This
++feature is only supported by ARM targets and then only in certain
++modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
++keyword}.
++
++@item arm_fp16_ieee
++@anchor{arm_fp16_ieee}
++ARM IEEE 754-2008 format VFP half-precision floating point support.
++This feature is only supported by ARM targets and then only in certain
++modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
++keyword}.
++
++@item arm_fp16_alternative
++@anchor{arm_fp16_alternative}
++ARM Alternative format VFP half-precision floating point support.
++This feature is only supported by ARM targets and then only in certain
++modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
++keyword}.
++
+ @item arm_neon_fp16
+ NEON and half-precision floating point support.  Only ARM targets
+ support this feature, and only then in certain modes; see
+@@ -2075,6 +2152,23 @@ the @ref{arm_neon_fp16_ok,,arm_neon_fp16_ok effective target keyword}.
+ arm vfp3 floating point support; see
+ the @ref{arm_vfp3_ok,,arm_vfp3_ok effective target keyword}.
+ 
++@item arm_v8_1a_neon
++Add options for ARMv8.1 with Adv.SIMD support, if this is supported
++by the target; see the @ref{arm_v8_1a_neon_ok,,arm_v8_1a_neon_ok}
++effective target keyword.
++
++@item arm_v8_2a_fp16_scalar
++Add options for ARMv8.2 with scalar FP16 support, if this is
++supported by the target; see the
++@ref{arm_v8_2a_fp16_scalar_ok,,arm_v8_2a_fp16_scalar_ok} effective
++target keyword.
++
++@item arm_v8_2a_fp16_neon
++Add options for ARMv8.2 with Adv.SIMD FP16 support, if this is
++supported by the target; see the
++@ref{arm_v8_2a_fp16_neon_ok,,arm_v8_2a_fp16_neon_ok} effective target
++keyword.
++
+ @item bind_pic_locally
+ Add the target-specific flags needed to enable functions to bind
+ locally when using pic/PIC passes in the testsuite.
--- gcc-6-6.3.0.orig/debian/patches/gcc-linaro-no-macros.diff
+++ gcc-6-6.3.0/debian/patches/gcc-linaro-no-macros.diff
@@ -0,0 +1,105 @@
+# DP : Don't add the __LINARO_RELEASE__ and __LINARO_SPIN__ macros for distro builds.
+
+Index: b/src/gcc/cppbuiltin.c
+===================================================================
+--- a/src/gcc/cppbuiltin.c
++++ b/src/gcc/cppbuiltin.c
+@@ -52,41 +52,18 @@ parse_basever (int *major, int *minor, i
+     *patchlevel = s_patchlevel;
+ }
+ 
+-/* Parse a LINAROVER version string of the format "M.m-year.month[-spin][~dev]"
+-   to create Linaro release number YYYYMM and spin version.  */
+-static void
+-parse_linarover (int *release, int *spin)
+-{
+-  static int s_year = -1, s_month, s_spin;
+-
+-  if (s_year == -1)
+-    if (sscanf (LINAROVER, "%*[^-]-%d.%d-%d", &s_year, &s_month, &s_spin) != 3)
+-      {
+-	sscanf (LINAROVER, "%*[^-]-%d.%d", &s_year, &s_month);
+-	s_spin = 0;
+-      }
+-
+-  if (release)
+-    *release = s_year * 100 + s_month;
+-
+-  if (spin)
+-    *spin = s_spin;
+-}
+ 
+ /* Define __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__ and __VERSION__.  */
+ static void
+ define__GNUC__ (cpp_reader *pfile)
+ {
+-  int major, minor, patchlevel, linaro_release, linaro_spin;
++  int major, minor, patchlevel;
+ 
+   parse_basever (&major, &minor, &patchlevel);
+-  parse_linarover (&linaro_release, &linaro_spin);
+   cpp_define_formatted (pfile, "__GNUC__=%d", major);
+   cpp_define_formatted (pfile, "__GNUC_MINOR__=%d", minor);
+   cpp_define_formatted (pfile, "__GNUC_PATCHLEVEL__=%d", patchlevel);
+   cpp_define_formatted (pfile, "__VERSION__=\"%s\"", version_string);
+-  cpp_define_formatted (pfile, "__LINARO_RELEASE__=%d", linaro_release);
+-  cpp_define_formatted (pfile, "__LINARO_SPIN__=%d", linaro_spin);
+   cpp_define_formatted (pfile, "__ATOMIC_RELAXED=%d", MEMMODEL_RELAXED);
+   cpp_define_formatted (pfile, "__ATOMIC_SEQ_CST=%d", MEMMODEL_SEQ_CST);
+   cpp_define_formatted (pfile, "__ATOMIC_ACQUIRE=%d", MEMMODEL_ACQUIRE);
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -832,12 +832,10 @@ BASEVER     := $(srcdir)/BASE-VER  # 4.x
+ DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
+ DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
+ REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
+-LINAROVER   := $(srcdir)/LINARO-VERSION # M.x-YYYY.MM[-S][~dev]
+ 
+ BASEVER_c   := $(shell cat $(BASEVER))
+ DEVPHASE_c  := $(shell cat $(DEVPHASE))
+ DATESTAMP_c := $(shell cat $(DATESTAMP))
+-LINAROVER_c := $(shell cat $(LINAROVER))
+ 
+ ifeq (,$(wildcard $(REVISION)))
+ REVISION_c  :=
+@@ -864,7 +862,6 @@ DATESTAMP_s := \
+   "\"$(if $(DEVPHASE_c)$(filter-out 0,$(PATCHLEVEL_c)), $(DATESTAMP_c))\""
+ PKGVERSION_s:= "\"@PKGVERSION@\""
+ BUGURL_s    := "\"@REPORT_BUGS_TO@\""
+-LINAROVER_s := "\"$(LINAROVER_c)\""
+ 
+ PKGVERSION  := @PKGVERSION@
+ BUGURL_TEXI := @REPORT_BUGS_TEXI@
+@@ -2704,9 +2701,8 @@ PREPROCESSOR_DEFINES = \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+-CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s) \
+-	-DLINAROVER=$(LINAROVER_s)
+-cppbuiltin.o: $(BASEVER) $(LINAROVER)
++CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s)
++cppbuiltin.o: $(BASEVER)
+ 
+ CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
+ 
+Index: b/src/gcc/LINARO-VERSION
+===================================================================
+--- a/src/gcc/LINARO-VERSION
++++ /dev/null
+@@ -1,1 +0,0 @@
+-6.3-2017.02~dev
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -903,7 +903,7 @@ AC_ARG_WITH(specs,
+ )
+ AC_SUBST(CONFIGURE_SPECS)
+ 
+-ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`])
++ACX_PKGVERSION([GCC])
+ ACX_BUGURL([http://gcc.gnu.org/bugs.html])
+ 
+ # Sanity check enable_languages in case someone does not run the toplevel
--- gcc-6-6.3.0.orig/debian/patches/gcc-linaro.diff
+++ gcc-6-6.3.0/debian/patches/gcc-linaro.diff
@@ -0,0 +1,161178 @@
+# DP: Changes for the Linaro 6-2017.02 release.
+
+MSG=$(git log origin/linaro/gcc-6-branch --format=format:"%s" -n 1 --grep "Merge branches"); SVN=${MSG##* }; git log origin/gcc-6-branch --format=format:"%H" -n 1 --grep "gcc-6-branch@${SVN%.}"
+
+LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02179d21167c43b18b31b3e8008dae1ed \
+ | egrep -v '^(diff|index) ' \
+ | filterdiff --strip=1 --addoldprefix=a/src/  --addnewprefix=b/src/ \
+ | sed 's,a/src//dev/null,/dev/null,'
+
+--- a/src/contrib/compare_tests
++++ b/src/contrib/compare_tests
+@@ -107,8 +107,8 @@ elif [ -d "$1" -o -d "$2" ] ; then
+ 	usage "Must specify either two directories or two files"
+ fi
+ 
+-sed 's/^XFAIL/FAIL/; s/^XPASS/PASS/' < "$1" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp1
+-sed 's/^XFAIL/FAIL/; s/^XPASS/PASS/' < "$2" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp2
++sed 's/^XFAIL/FAIL/; s/^ERROR/FAIL/; s/^XPASS/PASS/' < "$1" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp1
++sed 's/^XFAIL/FAIL/; s/^ERROR/FAIL/; s/^XPASS/PASS/' < "$2" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp2
+ 
+ before=$tmp1
+ now=$tmp2
+--- a/src/contrib/dg-extract-results.py
++++ b/src/contrib/dg-extract-results.py
+@@ -134,6 +134,7 @@ class Prog:
+         self.end_line = None
+         # Known summary types.
+         self.count_names = [
++            '# of DejaGnu errors\t\t',
+             '# of expected passes\t\t',
+             '# of unexpected failures\t',
+             '# of unexpected successes\t',
+@@ -245,6 +246,10 @@ class Prog:
+             segment = Segment (filename, file.tell())
+             variation.header = segment
+ 
++        # Parse the rest of the summary (the '# of ' lines).
++        if len (variation.counts) == 0:
++            variation.counts = self.zero_counts()
++
+         # Parse up until the first line of the summary.
+         if num_variations == 1:
+             end = '\t\t=== ' + tool.name + ' Summary ===\n'
+@@ -291,6 +296,11 @@ class Prog:
+                 harness.results.append ((key, line))
+                 if not first_key and sort_logs:
+                     first_key = key
++                if line.startswith ('ERROR: (DejaGnu)'):
++                    for i in range (len (self.count_names)):
++                        if 'DejaGnu errors' in self.count_names[i]:
++                            variation.counts[i] += 1
++                            break
+ 
+             # 'Using ...' lines are only interesting in a header.  Splitting
+             # the test up into parallel runs leads to more 'Using ...' lines
+@@ -309,9 +319,6 @@ class Prog:
+             segment.lines -= final_using
+             harness.add_segment (first_key, segment)
+ 
+-        # Parse the rest of the summary (the '# of ' lines).
+-        if len (variation.counts) == 0:
+-            variation.counts = self.zero_counts()
+         while True:
+             before = file.tell()
+             line = file.readline()
+--- a/src/contrib/dg-extract-results.sh
++++ b/src/contrib/dg-extract-results.sh
+@@ -369,10 +369,11 @@ EOF
+ BEGIN {
+   variant="$VAR"
+   tool="$TOOL"
+-  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kpasscnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0;
++  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kpasscnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0; dgerrorcnt=0;
+   curvar=""; insummary=0
+ }
+ /^Running target /		{ curvar = \$3; next }
++/^ERROR: \(DejaGnu\)/		{ if (variant == curvar) dgerrorcnt += 1 }
+ /^# of /			{ if (variant == curvar) insummary = 1 }
+ /^# of expected passes/		{ if (insummary == 1) passcnt += \$5; next; }
+ /^# of unexpected successes/	{ if (insummary == 1) xpasscnt += \$5; next; }
+@@ -390,6 +391,7 @@ BEGIN {
+ { next }
+ END {
+   printf ("\t\t=== %s Summary for %s ===\n\n", tool, variant)
++  if (dgerrorcnt != 0) printf ("# of DejaGnu errors\t\t%d\n", dgerrorcnt)
+   if (passcnt != 0) printf ("# of expected passes\t\t%d\n", passcnt)
+   if (failcnt != 0) printf ("# of unexpected failures\t%d\n", failcnt)
+   if (xpasscnt != 0) printf ("# of unexpected successes\t%d\n", xpasscnt)
+@@ -419,8 +421,9 @@ TOTAL_AWK=${TMP}/total.awk
+ cat << EOF > $TOTAL_AWK
+ BEGIN {
+   tool="$TOOL"
+-  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0
++  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0; dgerrorcnt=0
+ }
++/^# of DejaGnu errors/		{ dgerrorcnt += \$5 }
+ /^# of expected passes/		{ passcnt += \$5 }
+ /^# of unexpected failures/	{ failcnt += \$5 }
+ /^# of unexpected successes/	{ xpasscnt += \$5 }
+@@ -431,7 +434,8 @@ BEGIN {
+ /^# of unresolved testcases/	{ unrescnt += \$5 }
+ /^# of unsupported tests/	{ unsupcnt += \$5 }
+ END {
+-  printf ("\n\t\t=== %s Summary ===\n\n", tool)
++  printf ("\n\t\t=== %s MySummary ===\n\n", tool)
++  if (dgerrorcnt != 0) printf ("# of DejaGnu errors\t\t%d\n", dgerrorcnt)
+   if (passcnt != 0) printf ("# of expected passes\t\t%d\n", passcnt)
+   if (failcnt != 0) printf ("# of unexpected failures\t%d\n", failcnt)
+   if (xpasscnt != 0) printf ("# of unexpected successes\t%d\n", xpasscnt)
+--- /dev/null
++++ b/src/gcc/LINARO-VERSION
+@@ -0,0 +1 @@
++6.3-2017.02~dev
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -832,10 +832,12 @@ BASEVER     := $(srcdir)/BASE-VER  # 4.x.y
+ DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
+ DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
+ REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
++LINAROVER   := $(srcdir)/LINARO-VERSION # M.x-YYYY.MM[-S][~dev]
+ 
+ BASEVER_c   := $(shell cat $(BASEVER))
+ DEVPHASE_c  := $(shell cat $(DEVPHASE))
+ DATESTAMP_c := $(shell cat $(DATESTAMP))
++LINAROVER_c := $(shell cat $(LINAROVER))
+ 
+ ifeq (,$(wildcard $(REVISION)))
+ REVISION_c  :=
+@@ -862,6 +864,7 @@ DATESTAMP_s := \
+   "\"$(if $(DEVPHASE_c)$(filter-out 0,$(PATCHLEVEL_c)), $(DATESTAMP_c))\""
+ PKGVERSION_s:= "\"@PKGVERSION@\""
+ BUGURL_s    := "\"@REPORT_BUGS_TO@\""
++LINAROVER_s := "\"$(LINAROVER_c)\""
+ 
+ PKGVERSION  := @PKGVERSION@
+ BUGURL_TEXI := @REPORT_BUGS_TEXI@
+@@ -2701,8 +2704,9 @@ PREPROCESSOR_DEFINES = \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+-CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s)
+-cppbuiltin.o: $(BASEVER)
++CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s) \
++	-DLINAROVER=$(LINAROVER_s)
++cppbuiltin.o: $(BASEVER) $(LINAROVER)
+ 
+ CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
+ 
+--- a/src/gcc/ada/gcc-interface/misc.c
++++ b/src/gcc/ada/gcc-interface/misc.c
+@@ -255,8 +255,7 @@ static bool
+ gnat_post_options (const char **pfilename ATTRIBUTE_UNUSED)
+ {
+   /* Excess precision other than "fast" requires front-end support.  */
+-  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-      && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+     sorry ("-fexcess-precision=standard for Ada");
+   flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+ 
+--- a/src/gcc/builtins.c
++++ b/src/gcc/builtins.c
+@@ -28,6 +28,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "predict.h"
+ #include "tm_p.h"
+--- a/src/gcc/c-family/c-common.c
++++ b/src/gcc/c-family/c-common.c
+@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "function.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "c-common.h"
+ #include "gimple-expr.h"
+ #include "tm_p.h"
+--- a/src/gcc/c-family/c-opts.c
++++ b/src/gcc/c-family/c-opts.c
+@@ -772,8 +772,7 @@ c_common_post_options (const char **pfilename)
+      support.  */
+   if (c_dialect_cxx ())
+     {
+-      if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-	  && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++      if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+ 	sorry ("-fexcess-precision=standard for C++");
+       flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+     }
+--- a/src/gcc/calls.c
++++ b/src/gcc/calls.c
+@@ -194,10 +194,19 @@ prepare_call_address (tree fndecl_or_type, rtx funexp, rtx static_chain_value,
+ 	       && targetm.small_register_classes_for_mode_p (FUNCTION_MODE))
+ 	      ? force_not_mem (memory_address (FUNCTION_MODE, funexp))
+ 	      : memory_address (FUNCTION_MODE, funexp));
+-  else if (! sibcallp)
++  else
+     {
+-      if (!NO_FUNCTION_CSE && optimize && ! flag_no_function_cse)
+-	funexp = force_reg (Pmode, funexp);
++      /* funexp could be a SYMBOL_REF represents a function pointer which is
++	 of ptr_mode.  In this case, it should be converted into address mode
++	 to be a valid address for memory rtx pattern.  See PR 64971.  */
++      if (GET_MODE (funexp) != Pmode)
++	funexp = convert_memory_address (Pmode, funexp);
++
++      if (! sibcallp)
++	{
++	  if (!NO_FUNCTION_CSE && optimize && ! flag_no_function_cse)
++	    funexp = force_reg (Pmode, funexp);
++	}
+     }
+ 
+   if (static_chain_value != 0
+--- a/src/gcc/cfg.c
++++ b/src/gcc/cfg.c
+@@ -1064,7 +1064,7 @@ free_original_copy_tables (void)
+   delete bb_copy;
+   bb_copy = NULL;
+   delete bb_original;
+-  bb_copy = NULL;
++  bb_original = NULL;
+   delete loop_copy;
+   loop_copy = NULL;
+   delete original_copy_bb_pool;
+--- a/src/gcc/common/config/arm/arm-common.c
++++ b/src/gcc/common/config/arm/arm-common.c
+@@ -97,6 +97,29 @@ arm_rewrite_mcpu (int argc, const char **argv)
+   return arm_rewrite_selected_cpu (argv[argc - 1]);
+ }
+ 
++/* Called by the driver to check whether the target denoted by current
++   command line options is a Thumb-only target.  ARGV is an array of
++   -march and -mcpu values (ie. it contains the rhs after the equal
++   sign) and we use the last one of them to make a decision.  The
++   number of elements in ARGV is given in ARGC.  */
++const char *
++arm_target_thumb_only (int argc, const char **argv)
++{
++  unsigned int opt;
++
++  if (argc)
++    {
++      for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags)); opt++)
++	if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0)
++	    && !ARM_FSET_HAS_CPU1(arm_arch_core_flags[opt].flags, FL_NOTM))
++	  return "-mthumb";
++
++      return NULL;
++    }
++  else
++    return NULL;
++}
++
+ #undef ARM_CPU_NAME_LENGTH
+ 
+ 
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -307,7 +307,7 @@ m32c*-*-*)
+         ;;
+ aarch64*-*-*)
+ 	cpu_type=aarch64
+-	extra_headers="arm_neon.h arm_acle.h"
++	extra_headers="arm_fp16.h arm_neon.h arm_acle.h"
+ 	c_target_objs="aarch64-c.o"
+ 	cxx_target_objs="aarch64-c.o"
+ 	extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o"
+@@ -327,7 +327,7 @@ arc*-*-*)
+ arm*-*-*)
+ 	cpu_type=arm
+ 	extra_objs="arm-builtins.o aarch-common.o"
+-	extra_headers="mmintrin.h arm_neon.h arm_acle.h"
++	extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h"
+ 	target_type_format_char='%'
+ 	c_target_objs="arm-c.o"
+ 	cxx_target_objs="arm-c.o"
+@@ -1500,7 +1500,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
+ 		extra_options="${extra_options} linux-android.opt"
+ 		# Assume modern glibc if not targeting Android nor uclibc.
+ 		case ${target} in
+-		*-*-*android*|*-*-*uclibc*)
++		*-*-*android*|*-*-*uclibc*|*-*-*musl*)
+ 		  ;;
+ 		*)
+ 		  default_gnu_indirect_function=yes
+@@ -1569,7 +1569,7 @@ x86_64-*-linux* | x86_64-*-kfreebsd*-gnu | x86_64-*-knetbsd*-gnu)
+ 		extra_options="${extra_options} linux-android.opt"
+ 		# Assume modern glibc if not targeting Android nor uclibc.
+ 		case ${target} in
+-		*-*-*android*|*-*-*uclibc*)
++		*-*-*android*|*-*-*uclibc*|*-*-*musl*)
+ 		  ;;
+ 		*)
+ 		  default_gnu_indirect_function=yes
+@@ -3811,38 +3811,51 @@ case "${target}" in
+ 		# Add extra multilibs
+ 		if test "x$with_multilib_list" != x; then
+ 			arm_multilibs=`echo $with_multilib_list | sed -e 's/,/ /g'`
+-			for arm_multilib in ${arm_multilibs}; do
+-				case ${arm_multilib} in
+-				aprofile)
++			case ${arm_multilibs} in
++			aprofile)
+ 				# Note that arm/t-aprofile is a
+ 				# stand-alone make file fragment to be
+ 				# used only with itself.  We do not
+ 				# specifically use the
+ 				# TM_MULTILIB_OPTION framework because
+ 				# this shorthand is more
+-				# pragmatic. Additionally it is only
+-				# designed to work without any
+-				# with-cpu, with-arch with-mode
+-				# with-fpu or with-float options.
+-					if test "x$with_arch" != x \
+-					    || test "x$with_cpu" != x \
+-					    || test "x$with_float" != x \
+-					    || test "x$with_fpu" != x \
+-					    || test "x$with_mode" != x ; then
+-					    echo "Error: You cannot use any of --with-arch/cpu/fpu/float/mode with --with-multilib-list=aprofile" 1>&2
+-					    exit 1
+-					fi
+-					tmake_file="${tmake_file} arm/t-aprofile"
+-					break
+-					;;
+-				default)
+-					;;
+-				*)
+-					echo "Error: --with-multilib-list=${with_multilib_list} not supported." 1>&2
+-					exit 1
+-					;;
+-				esac
+-			done
++				# pragmatic.
++				tmake_profile_file="arm/t-aprofile"
++				;;
++			rmprofile)
++				# Note that arm/t-rmprofile is a
++				# stand-alone make file fragment to be
++				# used only with itself.  We do not
++				# specifically use the
++				# TM_MULTILIB_OPTION framework because
++				# this shorthand is more
++				# pragmatic.
++				tmake_profile_file="arm/t-rmprofile"
++				;;
++			default)
++				;;
++			*)
++				echo "Error: --with-multilib-list=${with_multilib_list} not supported." 1>&2
++				exit 1
++				;;
++			esac
++
++			if test "x${tmake_profile_file}" != x ; then
++				# arm/t-aprofile and arm/t-rmprofile are only
++				# designed to work without any with-cpu,
++				# with-arch, with-mode, with-fpu or with-float
++				# options.
++				if test "x$with_arch" != x \
++				    || test "x$with_cpu" != x \
++				    || test "x$with_float" != x \
++				    || test "x$with_fpu" != x \
++				    || test "x$with_mode" != x ; then
++				    echo "Error: You cannot use any of --with-arch/cpu/fpu/float/mode with --with-multilib-list=${with_multilib_list}" 1>&2
++				    exit 1
++				fi
++
++				tmake_file="${tmake_file} ${tmake_profile_file}"
++			fi
+ 		fi
+ 		;;
+ 
+--- a/src/gcc/config/aarch64/aarch64-arches.def
++++ b/src/gcc/config/aarch64/aarch64-arches.def
+@@ -32,4 +32,5 @@
+ 
+ AARCH64_ARCH("armv8-a",	      generic,	     8A,	8,  AARCH64_FL_FOR_ARCH8)
+ AARCH64_ARCH("armv8.1-a",     generic,	     8_1A,	8,  AARCH64_FL_FOR_ARCH8_1)
++AARCH64_ARCH("armv8.2-a",     generic,	     8_2A,	8,  AARCH64_FL_FOR_ARCH8_2)
+ 
+--- a/src/gcc/config/aarch64/aarch64-builtins.c
++++ b/src/gcc/config/aarch64/aarch64-builtins.c
+@@ -62,6 +62,7 @@
+ #define si_UP    SImode
+ #define sf_UP    SFmode
+ #define hi_UP    HImode
++#define hf_UP    HFmode
+ #define qi_UP    QImode
+ #define UP(X) X##_UP
+ 
+@@ -139,6 +140,10 @@ aarch64_types_binop_ssu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_none, qualifier_none, qualifier_unsigned };
+ #define TYPES_BINOP_SSU (aarch64_types_binop_ssu_qualifiers)
+ static enum aarch64_type_qualifiers
++aarch64_types_binop_uss_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_unsigned, qualifier_none, qualifier_none };
++#define TYPES_BINOP_USS (aarch64_types_binop_uss_qualifiers)
++static enum aarch64_type_qualifiers
+ aarch64_types_binopp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_poly, qualifier_poly, qualifier_poly };
+ #define TYPES_BINOPP (aarch64_types_binopp_qualifiers)
+@@ -164,6 +169,10 @@ aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ #define TYPES_QUADOP_LANE (aarch64_types_quadop_lane_qualifiers)
+ 
+ static enum aarch64_type_qualifiers
++aarch64_types_binop_imm_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_poly, qualifier_none, qualifier_immediate };
++#define TYPES_GETREGP (aarch64_types_binop_imm_p_qualifiers)
++static enum aarch64_type_qualifiers
+ aarch64_types_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_none, qualifier_none, qualifier_immediate };
+ #define TYPES_GETREG (aarch64_types_binop_imm_qualifiers)
+@@ -173,16 +182,29 @@ aarch64_types_shift_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_unsigned, qualifier_none, qualifier_immediate };
+ #define TYPES_SHIFTIMM_USS (aarch64_types_shift_to_unsigned_qualifiers)
+ static enum aarch64_type_qualifiers
++aarch64_types_fcvt_from_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_none, qualifier_unsigned, qualifier_immediate };
++#define TYPES_FCVTIMM_SUS (aarch64_types_fcvt_from_unsigned_qualifiers)
++static enum aarch64_type_qualifiers
+ aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate };
+ #define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
+ 
+ static enum aarch64_type_qualifiers
+-aarch64_types_ternop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+-  = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
+-#define TYPES_SETREG (aarch64_types_ternop_imm_qualifiers)
+-#define TYPES_SHIFTINSERT (aarch64_types_ternop_imm_qualifiers)
+-#define TYPES_SHIFTACC (aarch64_types_ternop_imm_qualifiers)
++aarch64_types_ternop_s_imm_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_none, qualifier_none, qualifier_poly, qualifier_immediate};
++#define TYPES_SETREGP (aarch64_types_ternop_s_imm_p_qualifiers)
++static enum aarch64_type_qualifiers
++aarch64_types_ternop_s_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate};
++#define TYPES_SETREG (aarch64_types_ternop_s_imm_qualifiers)
++#define TYPES_SHIFTINSERT (aarch64_types_ternop_s_imm_qualifiers)
++#define TYPES_SHIFTACC (aarch64_types_ternop_s_imm_qualifiers)
++
++static enum aarch64_type_qualifiers
++aarch64_types_ternop_p_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_poly, qualifier_poly, qualifier_poly, qualifier_immediate};
++#define TYPES_SHIFTINSERTP (aarch64_types_ternop_p_imm_qualifiers)
+ 
+ static enum aarch64_type_qualifiers
+ aarch64_types_unsigned_shiftacc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+@@ -197,6 +219,11 @@ aarch64_types_combine_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ #define TYPES_COMBINE (aarch64_types_combine_qualifiers)
+ 
+ static enum aarch64_type_qualifiers
++aarch64_types_combine_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_poly, qualifier_poly, qualifier_poly };
++#define TYPES_COMBINEP (aarch64_types_combine_p_qualifiers)
++
++static enum aarch64_type_qualifiers
+ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_none, qualifier_const_pointer_map_mode };
+ #define TYPES_LOAD1 (aarch64_types_load1_qualifiers)
+@@ -229,6 +256,10 @@ aarch64_types_bsl_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+    qualifier_map_mode | qualifier_pointer to build a pointer to the
+    element type of the vector.  */
+ static enum aarch64_type_qualifiers
++aarch64_types_store1_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_void, qualifier_pointer_map_mode, qualifier_poly };
++#define TYPES_STORE1P (aarch64_types_store1_p_qualifiers)
++static enum aarch64_type_qualifiers
+ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_void, qualifier_pointer_map_mode, qualifier_none };
+ #define TYPES_STORE1 (aarch64_types_store1_qualifiers)
+@@ -753,16 +784,16 @@ aarch64_init_simd_builtins (void)
+ 
+ 	  if (qualifiers & qualifier_unsigned)
+ 	    {
+-	      type_signature[arg_num] = 'u';
++	      type_signature[op_num] = 'u';
+ 	      print_type_signature_p = true;
+ 	    }
+ 	  else if (qualifiers & qualifier_poly)
+ 	    {
+-	      type_signature[arg_num] = 'p';
++	      type_signature[op_num] = 'p';
+ 	      print_type_signature_p = true;
+ 	    }
+ 	  else
+-	    type_signature[arg_num] = 's';
++	    type_signature[op_num] = 's';
+ 
+ 	  /* Skip an internal operand for vget_{low, high}.  */
+ 	  if (qualifiers & qualifier_internal)
+--- a/src/gcc/config/aarch64/aarch64-c.c
++++ b/src/gcc/config/aarch64/aarch64-c.c
+@@ -95,6 +95,11 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
+   else
+     cpp_undef (pfile, "__ARM_FP");
+ 
++  aarch64_def_or_undef (TARGET_FP_F16INST,
++			"__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", pfile);
++  aarch64_def_or_undef (TARGET_SIMD_F16INST,
++			"__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", pfile);
++
+   aarch64_def_or_undef (TARGET_SIMD, "__ARM_FEATURE_NUMERIC_MAXMIN", pfile);
+   aarch64_def_or_undef (TARGET_SIMD, "__ARM_NEON", pfile);
+ 
+--- a/src/gcc/config/aarch64/aarch64-cores.def
++++ b/src/gcc/config/aarch64/aarch64-cores.def
+@@ -40,17 +40,33 @@
+ 
+ /* V8 Architecture Processors.  */
+ 
++/* ARM ('A') cores. */
+ AARCH64_CORE("cortex-a35",  cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, "0x41", "0xd04")
+ AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03")
+ AARCH64_CORE("cortex-a57",  cortexa57, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07")
+ AARCH64_CORE("cortex-a72",  cortexa72, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")
++AARCH64_CORE("cortex-a73",  cortexa73, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09")
++
++/* Samsung ('S') cores. */
+ AARCH64_CORE("exynos-m1",   exynosm1,  exynosm1,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1,  "0x53", "0x001")
+-AARCH64_CORE("qdf24xx",     qdf24xx,   cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x51", "0x800")
++
++/* Qualcomm ('Q') cores. */
++AARCH64_CORE("qdf24xx",     qdf24xx,   cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx,   "0x51", "0x800")
++
++/* Cavium ('C') cores. */
+ AARCH64_CORE("thunderx",    thunderx,  thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  "0x43", "0x0a1")
++
++/* APM ('P') cores. */
+ AARCH64_CORE("xgene1",      xgene1,    xgene1,    8A,  AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
+ 
++/* V8.1 Architecture Processors.  */
++
++/* Broadcom ('B') cores. */
++AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, vulcan, "0x42", "0x516")
++
+ /* V8 big.LITTLE implementations.  */
+ 
+ AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07.0xd03")
+ AARCH64_CORE("cortex-a72.cortex-a53",  cortexa72cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08.0xd03")
+-
++AARCH64_CORE("cortex-a73.cortex-a35",  cortexa73cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09.0xd04")
++AARCH64_CORE("cortex-a73.cortex-a53",  cortexa73cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09.0xd03")
+--- a/src/gcc/config/aarch64/aarch64-cost-tables.h
++++ b/src/gcc/config/aarch64/aarch64-cost-tables.h
+@@ -127,6 +127,108 @@ const struct cpu_cost_table thunderx_extra_costs =
+   }
+ };
+ 
++const struct cpu_cost_table vulcan_extra_costs =
++{
++  /* ALU */
++  {
++    0,			/* Arith.  */
++    0,			/* Logical.  */
++    0,			/* Shift.  */
++    0,			/* Shift_reg.  */
++    COSTS_N_INSNS (1),	/* Arith_shift.  */
++    COSTS_N_INSNS (1),	/* Arith_shift_reg.  */
++    COSTS_N_INSNS (1),	/* Log_shift.  */
++    COSTS_N_INSNS (1),	/* Log_shift_reg.  */
++    0,			/* Extend.  */
++    COSTS_N_INSNS (1),	/* Extend_arith.  */
++    0,			/* Bfi.  */
++    0,			/* Bfx.  */
++    COSTS_N_INSNS (3),	/* Clz.  */
++    0,			/* Rev.  */
++    0,			/* Non_exec.  */
++    true		/* Non_exec_costs_exec.  */
++  },
++  {
++    /* MULT SImode */
++    {
++      COSTS_N_INSNS (4),	/* Simple.  */
++      COSTS_N_INSNS (4),	/* Flag_setting.  */
++      COSTS_N_INSNS (4),	/* Extend.  */
++      COSTS_N_INSNS (5),	/* Add.  */
++      COSTS_N_INSNS (5),	/* Extend_add.  */
++      COSTS_N_INSNS (18)	/* Idiv.  */
++    },
++    /* MULT DImode */
++    {
++      COSTS_N_INSNS (4),       /* Simple.  */
++      0,                       /* Flag_setting.  */
++      COSTS_N_INSNS (4),       /* Extend.  */
++      COSTS_N_INSNS (5),       /* Add.  */
++      COSTS_N_INSNS (5),       /* Extend_add.  */
++      COSTS_N_INSNS (26)       /* Idiv.  */
++    }
++  },
++  /* LD/ST */
++  {
++    COSTS_N_INSNS (4),	/* Load.  */
++    COSTS_N_INSNS (4),	/* Load_sign_extend.  */
++    COSTS_N_INSNS (5),	/* Ldrd.  */
++    COSTS_N_INSNS (4),	/* Ldm_1st.  */
++    1,			/* Ldm_regs_per_insn_1st.  */
++    1,			/* Ldm_regs_per_insn_subsequent.  */
++    COSTS_N_INSNS (4),	/* Loadf.  */
++    COSTS_N_INSNS (4),	/* Loadd.  */
++    COSTS_N_INSNS (4),	/* Load_unaligned.  */
++    0,			/* Store.  */
++    0,			/* Strd.  */
++    0,			/* Stm_1st.  */
++    1,			/* Stm_regs_per_insn_1st.  */
++    1,			/* Stm_regs_per_insn_subsequent.  */
++    0,			/* Storef.  */
++    0,			/* Stored.  */
++    0,			/* Store_unaligned.  */
++    COSTS_N_INSNS (1),	/* Loadv.  */
++    COSTS_N_INSNS (1)	/* Storev.  */
++  },
++  {
++    /* FP SFmode */
++    {
++      COSTS_N_INSNS (4),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub. */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst. */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    },
++    /* FP DFmode */
++    {
++      COSTS_N_INSNS (6),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub.  */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst.  */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    }
++  },
++  /* Vector */
++  {
++    COSTS_N_INSNS (1)	/* Alu.  */
++  }
++};
+ 
+ 
+ #endif
+--- a/src/gcc/config/aarch64/aarch64-elf.h
++++ b/src/gcc/config/aarch64/aarch64-elf.h
+@@ -25,15 +25,6 @@
+ #define ASM_OUTPUT_LABELREF(FILE, NAME) \
+   aarch64_asm_output_labelref (FILE, NAME)
+ 
+-#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2)	\
+-  do						\
+-    {						\
+-      assemble_name (FILE, NAME1);		\
+-      fputs (" = ", FILE);			\
+-      assemble_name (FILE, NAME2);		\
+-      fputc ('\n', FILE);			\
+-    } while (0)
+-
+ #define TEXT_SECTION_ASM_OP	"\t.text"
+ #define DATA_SECTION_ASM_OP	"\t.data"
+ #define BSS_SECTION_ASM_OP	"\t.bss"
+--- a/src/gcc/config/aarch64/aarch64-modes.def
++++ b/src/gcc/config/aarch64/aarch64-modes.def
+@@ -21,8 +21,6 @@
+ CC_MODE (CCFP);
+ CC_MODE (CCFPE);
+ CC_MODE (CC_SWP);
+-CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS).  */
+-CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS).  */
+ CC_MODE (CC_NZ);    /* Only N and Z bits of condition flags are valid.  */
+ CC_MODE (CC_Z);     /* Only Z bit of condition flags is valid.  */
+ CC_MODE (CC_C);     /* Only C bit of condition flags is valid.  */
+--- a/src/gcc/config/aarch64/aarch64-option-extensions.def
++++ b/src/gcc/config/aarch64/aarch64-option-extensions.def
+@@ -39,8 +39,8 @@
+    that are required.  Their order is not important.  */
+ 
+ /* Enabling "fp" just enables "fp".
+-   Disabling "fp" also disables "simd", "crypto".  */
+-AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO, "fp")
++   Disabling "fp" also disables "simd", "crypto" and "fp16".  */
++AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16, "fp")
+ 
+ /* Enabling "simd" also enables "fp".
+    Disabling "simd" also disables "crypto".  */
+@@ -55,3 +55,7 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, "crc32")
+ 
+ /* Enabling or disabling "lse" only changes "lse".  */
+ AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, "atomics")
++
++/* Enabling "fp16" also enables "fp".
++   Disabling "fp16" just disables "fp16".  */
++AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fp16")
+--- a/src/gcc/config/aarch64/aarch64-protos.h
++++ b/src/gcc/config/aarch64/aarch64-protos.h
+@@ -178,6 +178,25 @@ struct cpu_branch_cost
+   const int unpredictable;  /* Unpredictable branch or optimizing for speed.  */
+ };
+ 
++/* Control approximate alternatives to certain FP operators.  */
++#define AARCH64_APPROX_MODE(MODE) \
++  ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \
++   ? (1 << ((MODE) - MIN_MODE_FLOAT)) \
++   : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \
++     ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \
++	      + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \
++     : (0))
++#define AARCH64_APPROX_NONE (0)
++#define AARCH64_APPROX_ALL (-1)
++
++/* Allowed modes for approximations.  */
++struct cpu_approx_modes
++{
++  const unsigned int division;		/* Division.  */
++  const unsigned int sqrt;		/* Square root.  */
++  const unsigned int recip_sqrt;	/* Reciprocal square root.  */
++};
++
+ struct tune_params
+ {
+   const struct cpu_cost_table *insn_extra_cost;
+@@ -185,6 +204,7 @@ struct tune_params
+   const struct cpu_regmove_cost *regmove_cost;
+   const struct cpu_vector_cost *vec_costs;
+   const struct cpu_branch_cost *branch_costs;
++  const struct cpu_approx_modes *approx_modes;
+   int memmov_cost;
+   int issue_rate;
+   unsigned int fusible_ops;
+@@ -282,14 +302,14 @@ int aarch64_get_condition_code (rtx);
+ bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
+ int aarch64_branch_cost (bool, bool);
+ enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
+-bool aarch64_cannot_change_mode_class (machine_mode,
+-				       machine_mode,
+-				       enum reg_class);
+ bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
+ bool aarch64_constant_address_p (rtx);
++bool aarch64_emit_approx_div (rtx, rtx, rtx);
++bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
+ bool aarch64_expand_movmem (rtx *);
+ bool aarch64_float_const_zero_rtx_p (rtx);
+ bool aarch64_function_arg_regno_p (unsigned);
++bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs);
+ bool aarch64_gen_movmemqi (rtx *);
+ bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *);
+ bool aarch64_is_extend_from_extract (machine_mode, rtx, rtx);
+@@ -298,6 +318,7 @@ bool aarch64_is_noplt_call_p (rtx);
+ bool aarch64_label_mentioned_p (rtx);
+ void aarch64_declare_function_name (FILE *, const char*, tree);
+ bool aarch64_legitimate_pic_operand_p (rtx);
++bool aarch64_mask_and_shift_for_ubfiz_p (machine_mode, rtx, rtx);
+ bool aarch64_modes_tieable_p (machine_mode mode1,
+ 			      machine_mode mode2);
+ bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
+@@ -335,11 +356,9 @@ machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
+ 						       machine_mode);
+ int aarch64_hard_regno_mode_ok (unsigned, machine_mode);
+ int aarch64_hard_regno_nregs (unsigned, machine_mode);
+-int aarch64_simd_attr_length_move (rtx_insn *);
+ int aarch64_uxt_size (int, HOST_WIDE_INT);
+ int aarch64_vec_fpconst_pow_of_2 (rtx);
+ rtx aarch64_eh_return_handler_rtx (void);
+-rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int);
+ rtx aarch64_mask_from_zextract_ops (rtx, rtx);
+ const char *aarch64_output_move_struct (rtx *operands);
+ rtx aarch64_return_addr (int, rtx);
+@@ -352,7 +371,6 @@ unsigned aarch64_dbx_register_number (unsigned);
+ unsigned aarch64_trampoline_size (void);
+ void aarch64_asm_output_labelref (FILE *, const char *);
+ void aarch64_cpu_cpp_builtins (cpp_reader *);
+-void aarch64_elf_asm_named_section (const char *, unsigned, tree);
+ const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
+ const char * aarch64_output_probe_stack_range (rtx, rtx);
+ void aarch64_err_no_fpadvsimd (machine_mode, const char *);
+@@ -369,7 +387,6 @@ void aarch64_register_pragmas (void);
+ void aarch64_relayout_simd_types (void);
+ void aarch64_reset_previous_fndecl (void);
+ void aarch64_save_restore_target_globals (tree);
+-void aarch64_emit_approx_rsqrt (rtx, rtx);
+ 
+ /* Initialize builtins for SIMD intrinsics.  */
+ void init_aarch64_simd_builtins (void);
+@@ -436,7 +453,6 @@ int aarch64_ccmp_mode_to_code (enum machine_mode mode);
+ bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
+ bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode);
+ bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode);
+-extern bool aarch64_nopcrelative_literal_loads;
+ 
+ extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
+ 					      tree, HOST_WIDE_INT);
+--- a/src/gcc/config/aarch64/aarch64-simd-builtins.def
++++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def
+@@ -40,9 +40,10 @@
+    10 - CODE_FOR_<name><mode>.  */
+ 
+   BUILTIN_VDC (COMBINE, combine, 0)
++  VAR1 (COMBINEP, combine, 0, di)
+   BUILTIN_VB (BINOP, pmul, 0)
+-  BUILTIN_VALLF (BINOP, fmulx, 0)
+-  BUILTIN_VDQF_DF (UNOP, sqrt, 2)
++  BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0)
++  BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
+   BUILTIN_VD_BHSI (BINOP, addp, 0)
+   VAR1 (UNOP, addp, 0, di)
+   BUILTIN_VDQ_BHSI (UNOP, clrsb, 2)
+@@ -68,14 +69,23 @@
+   BUILTIN_VDC (GETREG, get_dregoi, 0)
+   BUILTIN_VDC (GETREG, get_dregci, 0)
+   BUILTIN_VDC (GETREG, get_dregxi, 0)
++  VAR1 (GETREGP, get_dregoi, 0, di)
++  VAR1 (GETREGP, get_dregci, 0, di)
++  VAR1 (GETREGP, get_dregxi, 0, di)
+   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
+   BUILTIN_VQ (GETREG, get_qregoi, 0)
+   BUILTIN_VQ (GETREG, get_qregci, 0)
+   BUILTIN_VQ (GETREG, get_qregxi, 0)
++  VAR1 (GETREGP, get_qregoi, 0, v2di)
++  VAR1 (GETREGP, get_qregci, 0, v2di)
++  VAR1 (GETREGP, get_qregxi, 0, v2di)
+   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
+   BUILTIN_VQ (SETREG, set_qregoi, 0)
+   BUILTIN_VQ (SETREG, set_qregci, 0)
+   BUILTIN_VQ (SETREG, set_qregxi, 0)
++  VAR1 (SETREGP, set_qregoi, 0, v2di)
++  VAR1 (SETREGP, set_qregci, 0, v2di)
++  VAR1 (SETREGP, set_qregxi, 0, v2di)
+   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
+   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
+   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
+@@ -224,6 +234,7 @@
+   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
+   BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
+   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
++  VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di)
+   BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
+   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
+   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
+@@ -234,105 +245,145 @@
+   BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
+ 
+   /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar).  */
+-  BUILTIN_VDQIF (UNOP, reduc_smax_scal_, 10)
+-  BUILTIN_VDQIF (UNOP, reduc_smin_scal_, 10)
++  BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10)
++  BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10)
+   BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10)
+   BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10)
+-  BUILTIN_VDQF (UNOP, reduc_smax_nan_scal_, 10)
+-  BUILTIN_VDQF (UNOP, reduc_smin_nan_scal_, 10)
++  BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10)
++  BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10)
+ 
+-  /* Implemented by <maxmin><mode>3.
++  /* Implemented by <maxmin_uns><mode>3.
+      smax variants map to fmaxnm,
+      smax_nan variants map to fmax.  */
+   BUILTIN_VDQ_BHSI (BINOP, smax, 3)
+   BUILTIN_VDQ_BHSI (BINOP, smin, 3)
+   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
+   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
+-  BUILTIN_VDQF (BINOP, smax_nan, 3)
+-  BUILTIN_VDQF (BINOP, smin_nan, 3)
++  BUILTIN_VHSDF_DF (BINOP, smax_nan, 3)
++  BUILTIN_VHSDF_DF (BINOP, smin_nan, 3)
+ 
+-  /* Implemented by <fmaxmin><mode>3.  */
+-  BUILTIN_VDQF (BINOP, fmax, 3)
+-  BUILTIN_VDQF (BINOP, fmin, 3)
++  /* Implemented by <maxmin_uns><mode>3.  */
++  BUILTIN_VHSDF_HSDF (BINOP, fmax, 3)
++  BUILTIN_VHSDF_HSDF (BINOP, fmin, 3)
+ 
+   /* Implemented by aarch64_<maxmin_uns>p<mode>.  */
+   BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
+   BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
+   BUILTIN_VDQ_BHSI (BINOP, umaxp, 0)
+   BUILTIN_VDQ_BHSI (BINOP, uminp, 0)
+-  BUILTIN_VDQF (BINOP, smaxp, 0)
+-  BUILTIN_VDQF (BINOP, sminp, 0)
+-  BUILTIN_VDQF (BINOP, smax_nanp, 0)
+-  BUILTIN_VDQF (BINOP, smin_nanp, 0)
++  BUILTIN_VHSDF (BINOP, smaxp, 0)
++  BUILTIN_VHSDF (BINOP, sminp, 0)
++  BUILTIN_VHSDF (BINOP, smax_nanp, 0)
++  BUILTIN_VHSDF (BINOP, smin_nanp, 0)
+ 
+   /* Implemented by <frint_pattern><mode>2.  */
+-  BUILTIN_VDQF (UNOP, btrunc, 2)
+-  BUILTIN_VDQF (UNOP, ceil, 2)
+-  BUILTIN_VDQF (UNOP, floor, 2)
+-  BUILTIN_VDQF (UNOP, nearbyint, 2)
+-  BUILTIN_VDQF (UNOP, rint, 2)
+-  BUILTIN_VDQF (UNOP, round, 2)
+-  BUILTIN_VDQF_DF (UNOP, frintn, 2)
++  BUILTIN_VHSDF (UNOP, btrunc, 2)
++  BUILTIN_VHSDF (UNOP, ceil, 2)
++  BUILTIN_VHSDF (UNOP, floor, 2)
++  BUILTIN_VHSDF (UNOP, nearbyint, 2)
++  BUILTIN_VHSDF (UNOP, rint, 2)
++  BUILTIN_VHSDF (UNOP, round, 2)
++  BUILTIN_VHSDF_DF (UNOP, frintn, 2)
++
++  VAR1 (UNOP, btrunc, 2, hf)
++  VAR1 (UNOP, ceil, 2, hf)
++  VAR1 (UNOP, floor, 2, hf)
++  VAR1 (UNOP, frintn, 2, hf)
++  VAR1 (UNOP, nearbyint, 2, hf)
++  VAR1 (UNOP, rint, 2, hf)
++  VAR1 (UNOP, round, 2, hf)
+ 
+   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
++  VAR1 (UNOP, lbtruncv4hf, 2, v4hi)
++  VAR1 (UNOP, lbtruncv8hf, 2, v8hi)
+   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
+   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
+   VAR1 (UNOP, lbtruncv2df, 2, v2di)
+ 
++  VAR1 (UNOPUS, lbtruncuv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lbtruncuv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si)
+   VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si)
+   VAR1 (UNOPUS, lbtruncuv2df, 2, v2di)
+ 
++  VAR1 (UNOP, lroundv4hf, 2, v4hi)
++  VAR1 (UNOP, lroundv8hf, 2, v8hi)
+   VAR1 (UNOP, lroundv2sf, 2, v2si)
+   VAR1 (UNOP, lroundv4sf, 2, v4si)
+   VAR1 (UNOP, lroundv2df, 2, v2di)
+-  /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
++  /* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2.  */
++  BUILTIN_GPI_I16 (UNOP, lroundhf, 2)
+   VAR1 (UNOP, lroundsf, 2, si)
+   VAR1 (UNOP, lrounddf, 2, di)
+ 
++  VAR1 (UNOPUS, lrounduv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lrounduv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lrounduv2sf, 2, v2si)
+   VAR1 (UNOPUS, lrounduv4sf, 2, v4si)
+   VAR1 (UNOPUS, lrounduv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2)
+   VAR1 (UNOPUS, lroundusf, 2, si)
+   VAR1 (UNOPUS, lroundudf, 2, di)
+ 
++  VAR1 (UNOP, lceilv4hf, 2, v4hi)
++  VAR1 (UNOP, lceilv8hf, 2, v8hi)
+   VAR1 (UNOP, lceilv2sf, 2, v2si)
+   VAR1 (UNOP, lceilv4sf, 2, v4si)
+   VAR1 (UNOP, lceilv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOP, lceilhf, 2)
+ 
++  VAR1 (UNOPUS, lceiluv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lceiluv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lceiluv2sf, 2, v2si)
+   VAR1 (UNOPUS, lceiluv4sf, 2, v4si)
+   VAR1 (UNOPUS, lceiluv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2)
+   VAR1 (UNOPUS, lceilusf, 2, si)
+   VAR1 (UNOPUS, lceiludf, 2, di)
+ 
++  VAR1 (UNOP, lfloorv4hf, 2, v4hi)
++  VAR1 (UNOP, lfloorv8hf, 2, v8hi)
+   VAR1 (UNOP, lfloorv2sf, 2, v2si)
+   VAR1 (UNOP, lfloorv4sf, 2, v4si)
+   VAR1 (UNOP, lfloorv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOP, lfloorhf, 2)
+ 
++  VAR1 (UNOPUS, lflooruv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lflooruv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lflooruv2sf, 2, v2si)
+   VAR1 (UNOPUS, lflooruv4sf, 2, v4si)
+   VAR1 (UNOPUS, lflooruv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2)
+   VAR1 (UNOPUS, lfloorusf, 2, si)
+   VAR1 (UNOPUS, lfloorudf, 2, di)
+ 
++  VAR1 (UNOP, lfrintnv4hf, 2, v4hi)
++  VAR1 (UNOP, lfrintnv8hf, 2, v8hi)
+   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
+   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
+   VAR1 (UNOP, lfrintnv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2)
+   VAR1 (UNOP, lfrintnsf, 2, si)
+   VAR1 (UNOP, lfrintndf, 2, di)
+ 
++  VAR1 (UNOPUS, lfrintnuv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lfrintnuv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si)
+   VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si)
+   VAR1 (UNOPUS, lfrintnuv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2)
+   VAR1 (UNOPUS, lfrintnusf, 2, si)
+   VAR1 (UNOPUS, lfrintnudf, 2, di)
+ 
+   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
++  VAR1 (UNOP, floatv4hi, 2, v4hf)
++  VAR1 (UNOP, floatv8hi, 2, v8hf)
+   VAR1 (UNOP, floatv2si, 2, v2sf)
+   VAR1 (UNOP, floatv4si, 2, v4sf)
+   VAR1 (UNOP, floatv2di, 2, v2df)
+ 
++  VAR1 (UNOP, floatunsv4hi, 2, v4hf)
++  VAR1 (UNOP, floatunsv8hi, 2, v8hf)
+   VAR1 (UNOP, floatunsv2si, 2, v2sf)
+   VAR1 (UNOP, floatunsv4si, 2, v4sf)
+   VAR1 (UNOP, floatunsv2di, 2, v2df)
+@@ -352,19 +403,19 @@
+ 
+   /* Implemented by
+      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
+-  BUILTIN_GPF (UNOP, frecpe, 0)
+-  BUILTIN_GPF (BINOP, frecps, 0)
+-  BUILTIN_GPF (UNOP, frecpx, 0)
++  BUILTIN_GPF_F16 (UNOP, frecpe, 0)
++  BUILTIN_GPF_F16 (UNOP, frecpx, 0)
+ 
+   BUILTIN_VDQ_SI (UNOP, urecpe, 0)
+ 
+-  BUILTIN_VDQF (UNOP, frecpe, 0)
+-  BUILTIN_VDQF (BINOP, frecps, 0)
++  BUILTIN_VHSDF (UNOP, frecpe, 0)
++  BUILTIN_VHSDF_HSDF (BINOP, frecps, 0)
+ 
+   /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
+      only ever used for the int64x1_t intrinsic, there is no scalar version.  */
+   BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
+-  BUILTIN_VDQF (UNOP, abs, 2)
++  BUILTIN_VHSDF (UNOP, abs, 2)
++  VAR1 (UNOP, abs, 2, hf)
+ 
+   BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
+   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
+@@ -376,15 +427,22 @@
+ 
+   /* Implemented by aarch64_ld1<VALL_F16:mode>.  */
+   BUILTIN_VALL_F16 (LOAD1, ld1, 0)
++  VAR1(STORE1P, ld1, 0, v2di)
+ 
+   /* Implemented by aarch64_st1<VALL_F16:mode>.  */
+   BUILTIN_VALL_F16 (STORE1, st1, 0)
++  VAR1(STORE1P, st1, 0, v2di)
+ 
+   /* Implemented by fma<mode>4.  */
+-  BUILTIN_VDQF (TERNOP, fma, 4)
++  BUILTIN_VHSDF (TERNOP, fma, 4)
++  VAR1 (TERNOP, fma, 4, hf)
++  /* Implemented by fnma<mode>4.  */
++  BUILTIN_VHSDF (TERNOP, fnma, 4)
++  VAR1 (TERNOP, fnma, 4, hf)
+ 
+   /* Implemented by aarch64_simd_bsl<mode>.  */
+   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
++  VAR2 (BSL_P, simd_bsl,0, di, v2di)
+   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
+   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
+ 
+@@ -436,7 +494,7 @@
+   VAR1 (TERNOP, qtbx4, 0, v8qi)
+   VAR1 (TERNOP, qtbx4, 0, v16qi)
+ 
+-  /* Builtins for ARMv8.1 Adv.SIMD instructions.  */
++  /* Builtins for ARMv8.1-A Adv.SIMD instructions.  */
+ 
+   /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>.  */
+   BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
+@@ -449,3 +507,60 @@
+   /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>.  */
+   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
+   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
++
++  /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3.  */
++  BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3)
++  BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3)
++  BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3)
++  BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3)
++  VAR1 (SHIFTIMM, scvtfsi, 3, hf)
++  VAR1 (SHIFTIMM, scvtfdi, 3, hf)
++  VAR1 (FCVTIMM_SUS, ucvtfsi, 3, hf)
++  VAR1 (FCVTIMM_SUS, ucvtfdi, 3, hf)
++  BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3)
++  BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3)
++
++  /* Implemented by aarch64_rsqrte<mode>.  */
++  BUILTIN_VHSDF_HSDF (UNOP, rsqrte, 0)
++
++  /* Implemented by aarch64_rsqrts<mode>.  */
++  BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0)
++
++  /* Implemented by fabd<mode>3.  */
++  BUILTIN_VHSDF_HSDF (BINOP, fabd, 3)
++
++  /* Implemented by aarch64_faddp<mode>.  */
++  BUILTIN_VHSDF (BINOP, faddp, 0)
++
++  /* Implemented by aarch64_cm<optab><mode>.  */
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmeq, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmge, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmgt, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmle, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmlt, 0)
++
++  /* Implemented by neg<mode>2.  */
++  BUILTIN_VHSDF_HSDF (UNOP, neg, 2)
++
++  /* Implemented by aarch64_fac<optab><mode>.  */
++  BUILTIN_VHSDF_HSDF (BINOP_USS, faclt, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, facle, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, facgt, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, facge, 0)
++
++  /* Implemented by sqrt<mode>2.  */
++  VAR1 (UNOP, sqrt, 2, hf)
++
++  /* Implemented by <optab><mode>hf2.  */
++  VAR1 (UNOP, floatdi, 2, hf)
++  VAR1 (UNOP, floatsi, 2, hf)
++  VAR1 (UNOP, floathi, 2, hf)
++  VAR1 (UNOPUS, floatunsdi, 2, hf)
++  VAR1 (UNOPUS, floatunssi, 2, hf)
++  VAR1 (UNOPUS, floatunshi, 2, hf)
++  BUILTIN_GPI_I16 (UNOP, fix_trunchf, 2)
++  BUILTIN_GPI (UNOP, fix_truncsf, 2)
++  BUILTIN_GPI (UNOP, fix_truncdf, 2)
++  BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
++  BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
++  BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
+\ No newline at end of file
+--- a/src/gcc/config/aarch64/aarch64-simd.md
++++ b/src/gcc/config/aarch64/aarch64-simd.md
+@@ -351,7 +351,7 @@
+     operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+     return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
+   }
+-  [(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
++  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
+ )
+ 
+ (define_insn "*aarch64_mul3_elt_<vswap_width_name><mode>"
+@@ -371,33 +371,33 @@
+   [(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "*aarch64_mul3_elt_to_128df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-     (mult:V2DF
+-       (vec_duplicate:V2DF
+-	 (match_operand:DF 2 "register_operand" "w"))
+-      (match_operand:V2DF 1 "register_operand" "w")))]
++(define_insn "*aarch64_mul3_elt_from_dup<mode>"
++ [(set (match_operand:VMUL 0 "register_operand" "=w")
++    (mult:VMUL
++      (vec_duplicate:VMUL
++	    (match_operand:<VEL> 1 "register_operand" "<h_con>"))
++      (match_operand:VMUL 2 "register_operand" "w")))]
+   "TARGET_SIMD"
+-  "fmul\\t%0.2d, %1.2d, %2.d[0]"
+-  [(set_attr "type" "neon_fp_mul_d_scalar_q")]
++  "<f>mul\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]";
++  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
+ )
+ 
+-(define_insn "aarch64_rsqrte_<mode>2"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")]
++(define_insn "aarch64_rsqrte<mode>"
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF [(match_operand:VHSDF_HSDF 1 "register_operand" "w")]
+ 		     UNSPEC_RSQRTE))]
+   "TARGET_SIMD"
+   "frsqrte\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
+-  [(set_attr "type" "neon_fp_rsqrte_<Vetype><q>")])
++  [(set_attr "type" "neon_fp_rsqrte_<stype><q>")])
+ 
+-(define_insn "aarch64_rsqrts_<mode>3"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
+-	       (match_operand:VALLF 2 "register_operand" "w")]
+-		     UNSPEC_RSQRTS))]
++(define_insn "aarch64_rsqrts<mode>"
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF [(match_operand:VHSDF_HSDF 1 "register_operand" "w")
++			    (match_operand:VHSDF_HSDF 2 "register_operand" "w")]
++	 UNSPEC_RSQRTS))]
+   "TARGET_SIMD"
+   "frsqrts\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
+-  [(set_attr "type" "neon_fp_rsqrts_<Vetype><q>")])
++  [(set_attr "type" "neon_fp_rsqrts_<stype><q>")])
+ 
+ (define_expand "rsqrt<mode>2"
+   [(set (match_operand:VALLF 0 "register_operand" "=w")
+@@ -405,7 +405,7 @@
+ 		     UNSPEC_RSQRT))]
+   "TARGET_SIMD"
+ {
+-  aarch64_emit_approx_rsqrt (operands[0], operands[1]);
++  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
+   DONE;
+ })
+ 
+@@ -474,24 +474,15 @@
+   [(set_attr "type" "neon_arith_acc<q>")]
+ )
+ 
+-(define_insn "fabd<mode>_3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(abs:VDQF (minus:VDQF
+-		   (match_operand:VDQF 1 "register_operand" "w")
+-		   (match_operand:VDQF 2 "register_operand" "w"))))]
+-  "TARGET_SIMD"
+-  "fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_abd_<Vetype><q>")]
+-)
+-
+-(define_insn "*fabd_scalar<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (abs:GPF (minus:GPF
+-                 (match_operand:GPF 1 "register_operand" "w")
+-                 (match_operand:GPF 2 "register_operand" "w"))))]
++(define_insn "fabd<mode>3"
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(abs:VHSDF_HSDF
++	  (minus:VHSDF_HSDF
++	    (match_operand:VHSDF_HSDF 1 "register_operand" "w")
++	    (match_operand:VHSDF_HSDF 2 "register_operand" "w"))))]
+   "TARGET_SIMD"
+-  "fabd\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "neon_fp_abd_<Vetype><q>")]
++  "fabd\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
++  [(set_attr "type" "neon_fp_abd_<stype><q>")]
+ )
+ 
+ (define_insn "and<mode>3"
+@@ -555,6 +546,49 @@
+   [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_1reg<q>")]
+ )
+ 
++(define_insn "*aarch64_simd_vec_copy_lane<mode>"
++  [(set (match_operand:VALL 0 "register_operand" "=w")
++	(vec_merge:VALL
++	    (vec_duplicate:VALL
++	      (vec_select:<VEL>
++		(match_operand:VALL 3 "register_operand" "w")
++		(parallel
++		  [(match_operand:SI 4 "immediate_operand" "i")])))
++	    (match_operand:VALL 1 "register_operand" "0")
++	    (match_operand:SI 2 "immediate_operand" "i")))]
++  "TARGET_SIMD"
++  {
++    int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
++    operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
++    operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
++
++    return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
++  }
++  [(set_attr "type" "neon_ins<q>")]
++)
++
++(define_insn "*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>"
++  [(set (match_operand:VALL 0 "register_operand" "=w")
++	(vec_merge:VALL
++	    (vec_duplicate:VALL
++	      (vec_select:<VEL>
++		(match_operand:<VSWAP_WIDTH> 3 "register_operand" "w")
++		(parallel
++		  [(match_operand:SI 4 "immediate_operand" "i")])))
++	    (match_operand:VALL 1 "register_operand" "0")
++	    (match_operand:SI 2 "immediate_operand" "i")))]
++  "TARGET_SIMD"
++  {
++    int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
++    operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
++    operands[4] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
++			   INTVAL (operands[4])));
++
++    return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
++  }
++  [(set_attr "type" "neon_ins<q>")]
++)
++
+ (define_insn "aarch64_simd_lshr<mode>"
+  [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+        (lshiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+@@ -1071,10 +1105,10 @@
+ 
+ ;; Pairwise FP Max/Min operations.
+ (define_insn "aarch64_<maxmin_uns>p<mode>"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")
+-		     (match_operand:VDQF 2 "register_operand" "w")]
+-		    FMAXMINV))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")
++		      (match_operand:VHSDF 2 "register_operand" "w")]
++		      FMAXMINV))]
+  "TARGET_SIMD"
+  "<maxmin_uns_op>p\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+   [(set_attr "type" "neon_minmax<q>")]
+@@ -1483,65 +1517,77 @@
+ ;; FP arithmetic operations.
+ 
+ (define_insn "add<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (plus:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		  (match_operand:VDQF 2 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (plus:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		   (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fadd\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_addsub_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_addsub_<stype><q>")]
+ )
+ 
+ (define_insn "sub<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (minus:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		   (match_operand:VDQF 2 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (minus:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		    (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fsub\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_addsub_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_addsub_<stype><q>")]
+ )
+ 
+ (define_insn "mul<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (mult:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		  (match_operand:VDQF 2 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (mult:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		   (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fmul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_mul_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_mul_<stype><q>")]
+ )
+ 
+-(define_insn "div<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (div:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		 (match_operand:VDQF 2 "register_operand" "w")))]
++(define_expand "div<mode>3"
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (div:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		  (match_operand:VHSDF 2 "register_operand" "w")))]
++ "TARGET_SIMD"
++{
++  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
++    DONE;
++
++  operands[1] = force_reg (<MODE>mode, operands[1]);
++})
++
++(define_insn "*div<mode>3"
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (div:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		 (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fdiv\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_div_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_div_<stype><q>")]
+ )
+ 
+ (define_insn "neg<mode>2"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (neg:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (neg:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fneg\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_neg_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_neg_<stype><q>")]
+ )
+ 
+ (define_insn "abs<mode>2"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (abs:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (abs:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fabs\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_abs_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_abs_<stype><q>")]
+ )
+ 
+ (define_insn "fma<mode>4"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (fma:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-                (match_operand:VDQF 2 "register_operand" "w")
+-                (match_operand:VDQF 3 "register_operand" "0")))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (fma:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		  (match_operand:VHSDF 2 "register_operand" "w")
++		  (match_operand:VHSDF 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+  "fmla\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_mla_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_mla_<stype><q>")]
+ )
+ 
+ (define_insn "*aarch64_fma4_elt<mode>"
+@@ -1579,16 +1625,16 @@
+   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "*aarch64_fma4_elt_to_128df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-    (fma:V2DF
+-      (vec_duplicate:V2DF
+-	  (match_operand:DF 1 "register_operand" "w"))
+-      (match_operand:V2DF 2 "register_operand" "w")
+-      (match_operand:V2DF 3 "register_operand" "0")))]
++(define_insn "*aarch64_fma4_elt_from_dup<mode>"
++  [(set (match_operand:VMUL 0 "register_operand" "=w")
++    (fma:VMUL
++      (vec_duplicate:VMUL
++	  (match_operand:<VEL> 1 "register_operand" "w"))
++      (match_operand:VMUL 2 "register_operand" "w")
++      (match_operand:VMUL 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+-  "fmla\\t%0.2d, %2.2d, %1.2d[0]"
+-  [(set_attr "type" "neon_fp_mla_d_scalar_q")]
++  "fmla\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
++  [(set_attr "type" "neon<fp>_mla_<stype>_scalar<q>")]
+ )
+ 
+ (define_insn "*aarch64_fma4_elt_to_64v2df"
+@@ -1608,15 +1654,15 @@
+ )
+ 
+ (define_insn "fnma<mode>4"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(fma:VDQF
+-	  (match_operand:VDQF 1 "register_operand" "w")
+-          (neg:VDQF
+-	    (match_operand:VDQF 2 "register_operand" "w"))
+-	  (match_operand:VDQF 3 "register_operand" "0")))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(fma:VHSDF
++	  (match_operand:VHSDF 1 "register_operand" "w")
++          (neg:VHSDF
++	    (match_operand:VHSDF 2 "register_operand" "w"))
++	  (match_operand:VHSDF 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+- "fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_mla_<Vetype><q>")]
++  "fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
++  [(set_attr "type" "neon_fp_mla_<stype><q>")]
+ )
+ 
+ (define_insn "*aarch64_fnma4_elt<mode>"
+@@ -1656,17 +1702,17 @@
+   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "*aarch64_fnma4_elt_to_128df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-    (fma:V2DF
+-      (neg:V2DF
+-        (match_operand:V2DF 2 "register_operand" "w"))
+-      (vec_duplicate:V2DF
+-	(match_operand:DF 1 "register_operand" "w"))
+-      (match_operand:V2DF 3 "register_operand" "0")))]
++(define_insn "*aarch64_fnma4_elt_from_dup<mode>"
++  [(set (match_operand:VMUL 0 "register_operand" "=w")
++    (fma:VMUL
++      (neg:VMUL
++        (match_operand:VMUL 2 "register_operand" "w"))
++      (vec_duplicate:VMUL
++	(match_operand:<VEL> 1 "register_operand" "w"))
++      (match_operand:VMUL 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+-  "fmls\\t%0.2d, %2.2d, %1.2d[0]"
+-  [(set_attr "type" "neon_fp_mla_d_scalar_q")]
++  "fmls\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
++  [(set_attr "type" "neon<fp>_mla_<stype>_scalar<q>")]
+ )
+ 
+ (define_insn "*aarch64_fnma4_elt_to_64v2df"
+@@ -1689,24 +1735,50 @@
+ ;; Vector versions of the floating-point frint patterns.
+ ;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
+ (define_insn "<frint_pattern><mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
+-		      FRINT))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
++		       FRINT))]
+   "TARGET_SIMD"
+   "frint<frint_suffix>\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_round_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_round_<stype><q>")]
+ )
+ 
+ ;; Vector versions of the fcvt standard patterns.
+ ;; Expands to lbtrunc, lround, lceil, lfloor
+-(define_insn "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2"
++(define_insn "l<fcvt_pattern><su_optab><VHSDF:mode><fcvt_target>2"
+   [(set (match_operand:<FCVT_TARGET> 0 "register_operand" "=w")
+ 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+-			       [(match_operand:VDQF 1 "register_operand" "w")]
++			       [(match_operand:VHSDF 1 "register_operand" "w")]
+ 			       FCVT)))]
+   "TARGET_SIMD"
+   "fcvt<frint_suffix><su>\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_to_int_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_to_int_<stype><q>")]
++)
++
++;; HF Scalar variants of related SIMD instructions.
++(define_insn "l<fcvt_pattern><su_optab>hfhi2"
++  [(set (match_operand:HI 0 "register_operand" "=w")
++	(FIXUORS:HI (unspec:HF [(match_operand:HF 1 "register_operand" "w")]
++		      FCVT)))]
++  "TARGET_SIMD_F16INST"
++  "fcvt<frint_suffix><su>\t%h0, %h1"
++  [(set_attr "type" "neon_fp_to_int_s")]
++)
++
++(define_insn "<optab>_trunchfhi2"
++  [(set (match_operand:HI 0 "register_operand" "=w")
++	(FIXUORS:HI (match_operand:HF 1 "register_operand" "w")))]
++  "TARGET_SIMD_F16INST"
++  "fcvtz<su>\t%h0, %h1"
++  [(set_attr "type" "neon_fp_to_int_s")]
++)
++
++(define_insn "<optab>hihf2"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(FLOATUORS:HF (match_operand:HI 1 "register_operand" "w")))]
++  "TARGET_SIMD_F16INST"
++  "<su_optab>cvtf\t%h0, %h1"
++  [(set_attr "type" "neon_int_to_fp_s")]
+ )
+ 
+ (define_insn "*aarch64_fcvt<su_optab><VDQF:mode><fcvt_target>2_mult"
+@@ -1729,36 +1801,36 @@
+   [(set_attr "type" "neon_fp_to_int_<Vetype><q>")]
+ )
+ 
+-(define_expand "<optab><VDQF:mode><fcvt_target>2"
++(define_expand "<optab><VHSDF:mode><fcvt_target>2"
+   [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+ 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+-			       [(match_operand:VDQF 1 "register_operand")]
+-			       UNSPEC_FRINTZ)))]
++			       [(match_operand:VHSDF 1 "register_operand")]
++				UNSPEC_FRINTZ)))]
+   "TARGET_SIMD"
+   {})
+ 
+-(define_expand "<fix_trunc_optab><VDQF:mode><fcvt_target>2"
++(define_expand "<fix_trunc_optab><VHSDF:mode><fcvt_target>2"
+   [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+ 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+-			       [(match_operand:VDQF 1 "register_operand")]
+-			       UNSPEC_FRINTZ)))]
++			       [(match_operand:VHSDF 1 "register_operand")]
++				UNSPEC_FRINTZ)))]
+   "TARGET_SIMD"
+   {})
+ 
+-(define_expand "ftrunc<VDQF:mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand")]
+-		      UNSPEC_FRINTZ))]
++(define_expand "ftrunc<VHSDF:mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand")
++	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")]
++		       UNSPEC_FRINTZ))]
+   "TARGET_SIMD"
+   {})
+ 
+-(define_insn "<optab><fcvt_target><VDQF:mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(FLOATUORS:VDQF
++(define_insn "<optab><fcvt_target><VHSDF:mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(FLOATUORS:VHSDF
+ 	  (match_operand:<FCVT_TARGET> 1 "register_operand" "w")))]
+   "TARGET_SIMD"
+   "<su_optab>cvtf\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_int_to_fp_<Vetype><q>")]
++  [(set_attr "type" "neon_int_to_fp_<stype><q>")]
+ )
+ 
+ ;; Conversions between vectors of floats and doubles.
+@@ -1778,6 +1850,30 @@
+   [(set_attr "type" "neon_fp_cvt_widen_s")]
+ )
+ 
++;; Convert between fixed-point and floating-point (vector modes)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn><VHSDF:mode>3"
++  [(set (match_operand:<VHSDF:FCVT_TARGET> 0 "register_operand" "=w")
++	(unspec:<VHSDF:FCVT_TARGET>
++	  [(match_operand:VHSDF 1 "register_operand" "w")
++	   (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_F2FIXED))]
++  "TARGET_SIMD"
++  "<FCVT_F2FIXED:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
++  [(set_attr "type" "neon_fp_to_int_<VHSDF:stype><q>")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_HSDI:mode>3"
++  [(set (match_operand:<VDQ_HSDI:FCVT_TARGET> 0 "register_operand" "=w")
++	(unspec:<VDQ_HSDI:FCVT_TARGET>
++	  [(match_operand:VDQ_HSDI 1 "register_operand" "w")
++	   (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_FIXED2F))]
++  "TARGET_SIMD"
++  "<FCVT_FIXED2F:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
++  [(set_attr "type" "neon_int_to_fp_<VDQ_HSDI:stype><q>")]
++)
++
+ ;; ??? Note that the vectorizer usage of the vec_unpacks_[lo/hi] patterns
+ ;; is inconsistent with vector ordering elsewhere in the compiler, in that
+ ;; the meaning of HI and LO changes depending on the target endianness.
+@@ -1934,33 +2030,25 @@
+ ;; NaNs.
+ 
+ (define_insn "<su><maxmin><mode>3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-        (FMAXMIN:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		   (match_operand:VDQF 2 "register_operand" "w")))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(FMAXMIN:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		       (match_operand:VHSDF 2 "register_operand" "w")))]
+   "TARGET_SIMD"
+   "f<maxmin>nm\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_minmax_<stype><q>")]
+ )
+ 
++;; Vector forms for fmax, fmin, fmaxnm, fminnm.
++;; fmaxnm and fminnm are used for the fmax<mode>3 standard pattern names,
++;; which implement the IEEE fmax ()/fmin () functions.
+ (define_insn "<maxmin_uns><mode>3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")
+-		     (match_operand:VDQF 2 "register_operand" "w")]
+-		    FMAXMIN_UNS))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")
++		      (match_operand:VHSDF 2 "register_operand" "w")]
++		      FMAXMIN_UNS))]
+   "TARGET_SIMD"
+   "<maxmin_uns_op>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
+-)
+-
+-;; Auto-vectorized forms for the IEEE-754 fmax()/fmin() functions
+-(define_insn "<fmaxmin><mode>3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")
+-		      (match_operand:VDQF 2 "register_operand" "w")]
+-		      FMAXMIN))]
+-  "TARGET_SIMD"
+-  "<fmaxmin_op>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_minmax_<stype><q>")]
+ )
+ 
+ ;; 'across lanes' add.
+@@ -1979,17 +2067,14 @@
+   }
+ )
+ 
+-(define_expand "reduc_plus_scal_<mode>"
+-  [(match_operand:<VEL> 0 "register_operand" "=w")
+-   (match_operand:V2F 1 "register_operand" "w")]
+-  "TARGET_SIMD"
+-  {
+-    rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
+-    rtx scratch = gen_reg_rtx (<MODE>mode);
+-    emit_insn (gen_aarch64_reduc_plus_internal<mode> (scratch, operands[1]));
+-    emit_insn (gen_aarch64_get_lane<mode> (operands[0], scratch, elt));
+-    DONE;
+-  }
++(define_insn "aarch64_faddp<mode>"
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")
++		      (match_operand:VHSDF 2 "register_operand" "w")]
++	UNSPEC_FADDV))]
++ "TARGET_SIMD"
++ "faddp\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
++  [(set_attr "type" "neon_fp_reduc_add_<stype><q>")]
+ )
+ 
+ (define_insn "aarch64_reduc_plus_internal<mode>"
+@@ -2010,24 +2095,15 @@
+   [(set_attr "type" "neon_reduc_add")]
+ )
+ 
+-(define_insn "aarch64_reduc_plus_internal<mode>"
+- [(set (match_operand:V2F 0 "register_operand" "=w")
+-       (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
++(define_insn "reduc_plus_scal_<mode>"
++ [(set (match_operand:<VEL> 0 "register_operand" "=w")
++       (unspec:<VEL> [(match_operand:V2F 1 "register_operand" "w")]
+ 		   UNSPEC_FADDV))]
+  "TARGET_SIMD"
+  "faddp\\t%<Vetype>0, %1.<Vtype>"
+   [(set_attr "type" "neon_fp_reduc_add_<Vetype><q>")]
+ )
+ 
+-(define_insn "aarch64_addpv4sf"
+- [(set (match_operand:V4SF 0 "register_operand" "=w")
+-       (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")]
+-		    UNSPEC_FADDV))]
+- "TARGET_SIMD"
+- "faddp\\t%0.4s, %1.4s, %1.4s"
+-  [(set_attr "type" "neon_fp_reduc_add_s_q")]
+-)
+-
+ (define_expand "reduc_plus_scal_v4sf"
+  [(set (match_operand:SF 0 "register_operand")
+        (unspec:V4SF [(match_operand:V4SF 1 "register_operand")]
+@@ -2036,8 +2112,8 @@
+ {
+   rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
+   rtx scratch = gen_reg_rtx (V4SFmode);
+-  emit_insn (gen_aarch64_addpv4sf (scratch, operands[1]));
+-  emit_insn (gen_aarch64_addpv4sf (scratch, scratch));
++  emit_insn (gen_aarch64_faddpv4sf (scratch, operands[1], operands[1]));
++  emit_insn (gen_aarch64_faddpv4sf (scratch, scratch, scratch));
+   emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
+   DONE;
+ })
+@@ -2072,8 +2148,8 @@
+ ;; gimple_fold'd to the REDUC_(MAX|MIN)_EXPR tree code.  (This is FP smax/smin).
+ (define_expand "reduc_<maxmin_uns>_scal_<mode>"
+   [(match_operand:<VEL> 0 "register_operand")
+-   (unspec:VDQF [(match_operand:VDQF 1 "register_operand")]
+-		FMAXMINV)]
++   (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")]
++		  FMAXMINV)]
+   "TARGET_SIMD"
+   {
+     rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
+@@ -2120,12 +2196,12 @@
+ )
+ 
+ (define_insn "aarch64_reduc_<maxmin_uns>_internal<mode>"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
+-		    FMAXMINV))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
++		      FMAXMINV))]
+  "TARGET_SIMD"
+  "<maxmin_uns_op><vp>\\t%<Vetype>0, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_reduc_minmax_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_reduc_minmax_<stype><q>")]
+ )
+ 
+ ;; aarch64_simd_bsl may compile to any of bsl/bif/bit depending on register
+@@ -2635,7 +2711,7 @@
+ (define_insn "*aarch64_combinez<mode>"
+   [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
+         (vec_concat:<VDBL>
+-	   (match_operand:VD_BHSI 1 "general_operand" "w,r,m")
++	   (match_operand:VD_BHSI 1 "general_operand" "w,?r,m")
+ 	   (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")))]
+   "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "@
+@@ -2651,7 +2727,7 @@
+   [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
+         (vec_concat:<VDBL>
+ 	   (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")
+-	   (match_operand:VD_BHSI 1 "general_operand" "w,r,m")))]
++	   (match_operand:VD_BHSI 1 "general_operand" "w,?r,m")))]
+   "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "@
+    mov\\t%0.8b, %1.8b
+@@ -2994,13 +3070,14 @@
+ ;; fmulx.
+ 
+ (define_insn "aarch64_fmulx<mode>"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
+-		       (match_operand:VALLF 2 "register_operand" "w")]
+-		      UNSPEC_FMULX))]
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF
++	  [(match_operand:VHSDF_HSDF 1 "register_operand" "w")
++	   (match_operand:VHSDF_HSDF 2 "register_operand" "w")]
++	   UNSPEC_FMULX))]
+  "TARGET_SIMD"
+  "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
+- [(set_attr "type" "neon_fp_mul_<Vetype>")]
++ [(set_attr "type" "neon_fp_mul_<stype>")]
+ )
+ 
+ ;; vmulxq_lane_f32, and vmulx_laneq_f32
+@@ -3042,20 +3119,18 @@
+   [(set_attr "type" "neon_fp_mul_<Vetype><q>")]
+ )
+ 
+-;; vmulxq_lane_f64
++;; vmulxq_lane
+ 
+-(define_insn "*aarch64_mulx_elt_to_64v2df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-	(unspec:V2DF
+-	 [(match_operand:V2DF 1 "register_operand" "w")
+-	  (vec_duplicate:V2DF
+-	    (match_operand:DF 2 "register_operand" "w"))]
++(define_insn "*aarch64_mulx_elt_from_dup<mode>"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(unspec:VHSDF
++	 [(match_operand:VHSDF 1 "register_operand" "w")
++	  (vec_duplicate:VHSDF
++	    (match_operand:<VEL> 2 "register_operand" "w"))]
+ 	 UNSPEC_FMULX))]
+   "TARGET_SIMD"
+-  {
+-    return "fmulx\t%0.2d, %1.2d, %2.d[0]";
+-  }
+-  [(set_attr "type" "neon_fp_mul_d_scalar_q")]
++  "fmulx\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]";
++  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
+ )
+ 
+ ;; vmulxs_lane_f32, vmulxs_laneq_f32
+@@ -3937,15 +4012,12 @@
+ 			   "aarch64_simd_shift_imm_bitsize_<ve_mode>" "i")]
+                          VSHLL))]
+   "TARGET_SIMD"
+-  "*
+-  int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
+-  if (INTVAL (operands[2]) == bit_width)
+   {
+-    return \"shll\\t%0.<Vwtype>, %1.<Vtype>, %2\";
++    if (INTVAL (operands[2]) == GET_MODE_UNIT_BITSIZE (<MODE>mode))
++      return "shll\\t%0.<Vwtype>, %1.<Vtype>, %2";
++    else
++      return "<sur>shll\\t%0.<Vwtype>, %1.<Vtype>, %2";
+   }
+-  else {
+-    return \"<sur>shll\\t%0.<Vwtype>, %1.<Vtype>, %2\";
+-  }"
+   [(set_attr "type" "neon_shift_imm_long")]
+ )
+ 
+@@ -3957,15 +4029,12 @@
+ 			 (match_operand:SI 2 "immediate_operand" "i")]
+                          VSHLL))]
+   "TARGET_SIMD"
+-  "*
+-  int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
+-  if (INTVAL (operands[2]) == bit_width)
+   {
+-    return \"shll2\\t%0.<Vwtype>, %1.<Vtype>, %2\";
++    if (INTVAL (operands[2]) == GET_MODE_UNIT_BITSIZE (<MODE>mode))
++      return "shll2\\t%0.<Vwtype>, %1.<Vtype>, %2";
++    else
++      return "<sur>shll2\\t%0.<Vwtype>, %1.<Vtype>, %2";
+   }
+-  else {
+-    return \"<sur>shll2\\t%0.<Vwtype>, %1.<Vtype>, %2\";
+-  }"
+   [(set_attr "type" "neon_shift_imm_long")]
+ )
+ 
+@@ -4246,30 +4315,32 @@
+   [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
+ 	(neg:<V_cmp_result>
+ 	  (COMPARISONS:<V_cmp_result>
+-	    (match_operand:VALLF 1 "register_operand" "w,w")
+-	    (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")
++	    (match_operand:VHSDF_HSDF 1 "register_operand" "w,w")
++	    (match_operand:VHSDF_HSDF 2 "aarch64_simd_reg_or_zero" "w,YDz")
+ 	  )))]
+   "TARGET_SIMD"
+   "@
+   fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
+   fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
+-  [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_compare_<stype><q>")]
+ )
+ 
+ ;; fac(ge|gt)
+ ;; Note we can also handle what would be fac(le|lt) by
+ ;; generating fac(ge|gt).
+ 
+-(define_insn "*aarch64_fac<optab><mode>"
++(define_insn "aarch64_fac<optab><mode>"
+   [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
+ 	(neg:<V_cmp_result>
+ 	  (FAC_COMPARISONS:<V_cmp_result>
+-	    (abs:VALLF (match_operand:VALLF 1 "register_operand" "w"))
+-	    (abs:VALLF (match_operand:VALLF 2 "register_operand" "w"))
++	    (abs:VHSDF_HSDF
++	      (match_operand:VHSDF_HSDF 1 "register_operand" "w"))
++	    (abs:VHSDF_HSDF
++	      (match_operand:VHSDF_HSDF 2 "register_operand" "w"))
+   )))]
+   "TARGET_SIMD"
+   "fac<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
+-  [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_compare_<stype><q>")]
+ )
+ 
+ ;; addp
+@@ -4297,12 +4368,21 @@
+ 
+ ;; sqrt
+ 
+-(define_insn "sqrt<mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-        (sqrt:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
++(define_expand "sqrt<mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(sqrt:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
++  "TARGET_SIMD"
++{
++  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
++    DONE;
++})
++
++(define_insn "*sqrt<mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(sqrt:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
+   "TARGET_SIMD"
+   "fsqrt\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_sqrt_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_sqrt_<stype><q>")]
+ )
+ 
+ ;; Patterns for vector struct loads and stores.
+@@ -4652,7 +4732,7 @@
+    ld1\\t{%S0.16b - %<Vendreg>0.16b}, %1"
+   [(set_attr "type" "multiple,neon_store<nregs>_<nregs>reg_q,\
+ 		     neon_load<nregs>_<nregs>reg_q")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "<insn_count>,4,4")]
+ )
+ 
+ (define_insn "aarch64_be_ld1<mode>"
+@@ -4685,7 +4765,7 @@
+    stp\\t%q1, %R1, %0
+    ldp\\t%q0, %R0, %1"
+   [(set_attr "type" "multiple,neon_stp_q,neon_ldp_q")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "8,4,4")]
+ )
+ 
+ (define_insn "*aarch64_be_movci"
+@@ -4696,7 +4776,7 @@
+        || register_operand (operands[1], CImode))"
+   "#"
+   [(set_attr "type" "multiple")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "12,4,4")]
+ )
+ 
+ (define_insn "*aarch64_be_movxi"
+@@ -4707,7 +4787,7 @@
+        || register_operand (operands[1], XImode))"
+   "#"
+   [(set_attr "type" "multiple")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "16,4,4")]
+ )
+ 
+ (define_split
+@@ -4787,7 +4867,7 @@
+   DONE;
+ })
+ 
+-(define_insn "aarch64_ld2<mode>_dreg"
++(define_insn "aarch64_ld2<mode>_dreg_le"
+   [(set (match_operand:OI 0 "register_operand" "=w")
+ 	(subreg:OI
+ 	  (vec_concat:<VRL2>
+@@ -4800,12 +4880,30 @@
+ 	     (unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD2)
+ 	     (vec_duplicate:VD (const_int 0)))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
+   [(set_attr "type" "neon_load2_2reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld2<mode>_dreg"
++(define_insn "aarch64_ld2<mode>_dreg_be"
++  [(set (match_operand:OI 0 "register_operand" "=w")
++	(subreg:OI
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD2))
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD [(match_dup 1)]
++			UNSPEC_LD2))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
++  "ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
++  [(set_attr "type" "neon_load2_2reg<q>")]
++)
++
++(define_insn "aarch64_ld2<mode>_dreg_le"
+   [(set (match_operand:OI 0 "register_operand" "=w")
+ 	(subreg:OI
+ 	  (vec_concat:<VRL2>
+@@ -4818,12 +4916,30 @@
+ 	     (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD2)
+ 	     (const_int 0))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "ld1\\t{%S0.1d - %T0.1d}, %1"
+   [(set_attr "type" "neon_load1_2reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld3<mode>_dreg"
++(define_insn "aarch64_ld2<mode>_dreg_be"
++  [(set (match_operand:OI 0 "register_operand" "=w")
++	(subreg:OI
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD2))
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX [(match_dup 1)]
++			UNSPEC_LD2))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
++  "ld1\\t{%S0.1d - %T0.1d}, %1"
++  [(set_attr "type" "neon_load1_2reg<q>")]
++)
++
++(define_insn "aarch64_ld3<mode>_dreg_le"
+   [(set (match_operand:CI 0 "register_operand" "=w")
+ 	(subreg:CI
+ 	 (vec_concat:<VRL3>
+@@ -4841,12 +4957,35 @@
+ 	     (unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD3)
+ 	     (vec_duplicate:VD (const_int 0)))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
++  "ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
++  [(set_attr "type" "neon_load3_3reg<q>")]
++)
++
++(define_insn "aarch64_ld3<mode>_dreg_be"
++  [(set (match_operand:CI 0 "register_operand" "=w")
++	(subreg:CI
++	 (vec_concat:<VRL3>
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD3))
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD [(match_dup 1)]
++			UNSPEC_LD3)))
++	  (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD [(match_dup 1)]
++			UNSPEC_LD3))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
+   [(set_attr "type" "neon_load3_3reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld3<mode>_dreg"
++(define_insn "aarch64_ld3<mode>_dreg_le"
+   [(set (match_operand:CI 0 "register_operand" "=w")
+ 	(subreg:CI
+ 	 (vec_concat:<VRL3>
+@@ -4864,12 +5003,35 @@
+ 	     (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD3)
+ 	     (const_int 0))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "ld1\\t{%S0.1d - %U0.1d}, %1"
+   [(set_attr "type" "neon_load1_3reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld4<mode>_dreg"
++(define_insn "aarch64_ld3<mode>_dreg_be"
++  [(set (match_operand:CI 0 "register_operand" "=w")
++	(subreg:CI
++	 (vec_concat:<VRL3>
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD3))
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX [(match_dup 1)]
++			UNSPEC_LD3)))
++	  (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX [(match_dup 1)]
++			UNSPEC_LD3))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
++  "ld1\\t{%S0.1d - %U0.1d}, %1"
++  [(set_attr "type" "neon_load1_3reg<q>")]
++)
++
++(define_insn "aarch64_ld4<mode>_dreg_le"
+   [(set (match_operand:XI 0 "register_operand" "=w")
+ 	(subreg:XI
+ 	 (vec_concat:<VRL4>
+@@ -4880,9 +5042,9 @@
+ 		UNSPEC_LD4)
+ 	       (vec_duplicate:VD (const_int 0)))
+ 	      (vec_concat:<VDBL>
+-	        (unspec:VD [(match_dup 1)]
++		(unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD4)
+-	        (vec_duplicate:VD (const_int 0))))
++		(vec_duplicate:VD (const_int 0))))
+ 	   (vec_concat:<VRL2>
+ 	     (vec_concat:<VDBL>
+ 	       (unspec:VD [(match_dup 1)]
+@@ -4892,12 +5054,40 @@
+ 	       (unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD4)
+ 	       (vec_duplicate:VD (const_int 0))))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
++  "ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
++  [(set_attr "type" "neon_load4_4reg<q>")]
++)
++
++(define_insn "aarch64_ld4<mode>_dreg_be"
++  [(set (match_operand:XI 0 "register_operand" "=w")
++	(subreg:XI
++	 (vec_concat:<VRL4>
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (vec_duplicate:VD (const_int 0))
++	       (unspec:VD
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD4))
++	      (vec_concat:<VDBL>
++		(vec_duplicate:VD (const_int 0))
++		(unspec:VD [(match_dup 1)]
++			UNSPEC_LD4)))
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (vec_duplicate:VD (const_int 0))
++	       (unspec:VD [(match_dup 1)]
++			UNSPEC_LD4))
++	     (vec_concat:<VDBL>
++	       (vec_duplicate:VD (const_int 0))
++	       (unspec:VD [(match_dup 1)]
++			UNSPEC_LD4)))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
+   [(set_attr "type" "neon_load4_4reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld4<mode>_dreg"
++(define_insn "aarch64_ld4<mode>_dreg_le"
+   [(set (match_operand:XI 0 "register_operand" "=w")
+ 	(subreg:XI
+ 	 (vec_concat:<VRL4>
+@@ -4910,7 +5100,7 @@
+ 	      (vec_concat:<VDBL>
+ 	        (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD4)
+-	        (const_int 0)))
++		(const_int 0)))
+ 	   (vec_concat:<VRL2>
+ 	     (vec_concat:<VDBL>
+ 	       (unspec:DX [(match_dup 1)]
+@@ -4920,7 +5110,35 @@
+ 	       (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD4)
+ 	       (const_int 0)))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
++  "ld1\\t{%S0.1d - %V0.1d}, %1"
++  [(set_attr "type" "neon_load1_4reg<q>")]
++)
++
++(define_insn "aarch64_ld4<mode>_dreg_be"
++  [(set (match_operand:XI 0 "register_operand" "=w")
++	(subreg:XI
++	 (vec_concat:<VRL4>
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (const_int 0)
++	       (unspec:DX
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD4))
++	      (vec_concat:<VDBL>
++		(const_int 0)
++		(unspec:DX [(match_dup 1)]
++			UNSPEC_LD4)))
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (const_int 0)
++	       (unspec:DX [(match_dup 1)]
++			UNSPEC_LD4))
++	     (vec_concat:<VDBL>
++	       (const_int 0)
++	       (unspec:DX [(match_dup 1)]
++			UNSPEC_LD4)))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "ld1\\t{%S0.1d - %V0.1d}, %1"
+   [(set_attr "type" "neon_load1_4reg<q>")]
+ )
+@@ -4934,7 +5152,12 @@
+   rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+   set_mem_size (mem, <VSTRUCT:nregs> * 8);
+ 
+-  emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg (operands[0], mem));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg_be (operands[0],
++								mem));
++  else
++    emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg_le (operands[0],
++								mem));
+   DONE;
+ })
+ 
+@@ -5160,10 +5383,10 @@
+ )
+ 
+ (define_insn "aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>"
+-  [(set (match_operand:VALL 0 "register_operand" "=w")
+-	(unspec:VALL [(match_operand:VALL 1 "register_operand" "w")
+-		      (match_operand:VALL 2 "register_operand" "w")]
+-		       PERMUTE))]
++  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
++	(unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")
++			  (match_operand:VALL_F16 2 "register_operand" "w")]
++	 PERMUTE))]
+   "TARGET_SIMD"
+   "<PERMUTE:perm_insn><PERMUTE:perm_hilo>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+   [(set_attr "type" "neon_permute<q>")]
+@@ -5171,11 +5394,11 @@
+ 
+ ;; Note immediate (third) operand is lane index not byte index.
+ (define_insn "aarch64_ext<mode>"
+-  [(set (match_operand:VALL 0 "register_operand" "=w")
+-        (unspec:VALL [(match_operand:VALL 1 "register_operand" "w")
+-                      (match_operand:VALL 2 "register_operand" "w")
+-                      (match_operand:SI 3 "immediate_operand" "i")]
+-                     UNSPEC_EXT))]
++  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
++        (unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")
++			  (match_operand:VALL_F16 2 "register_operand" "w")
++			  (match_operand:SI 3 "immediate_operand" "i")]
++	 UNSPEC_EXT))]
+   "TARGET_SIMD"
+ {
+   operands[3] = GEN_INT (INTVAL (operands[3])
+@@ -5186,8 +5409,8 @@
+ )
+ 
+ (define_insn "aarch64_rev<REVERSE:rev_op><mode>"
+-  [(set (match_operand:VALL 0 "register_operand" "=w")
+-	(unspec:VALL [(match_operand:VALL 1 "register_operand" "w")]
++  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
++	(unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")]
+                     REVERSE))]
+   "TARGET_SIMD"
+   "rev<REVERSE:rev_op>\\t%0.<Vtype>, %1.<Vtype>"
+@@ -5354,31 +5577,32 @@
+ )
+ 
+ (define_insn "aarch64_frecpe<mode>"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
+-		    UNSPEC_FRECPE))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
++	 UNSPEC_FRECPE))]
+   "TARGET_SIMD"
+   "frecpe\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_recpe_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_recpe_<stype><q>")]
+ )
+ 
+ (define_insn "aarch64_frecp<FRECP:frecp_suffix><mode>"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
+-		    FRECP))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")]
++	 FRECP))]
+   "TARGET_SIMD"
+   "frecp<FRECP:frecp_suffix>\\t%<s>0, %<s>1"
+-  [(set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF:Vetype><GPF:q>")]
++  [(set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF_F16:stype>")]
+ )
+ 
+ (define_insn "aarch64_frecps<mode>"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
+-		     (match_operand:VALLF 2 "register_operand" "w")]
+-		    UNSPEC_FRECPS))]
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF
++	  [(match_operand:VHSDF_HSDF 1 "register_operand" "w")
++	  (match_operand:VHSDF_HSDF 2 "register_operand" "w")]
++	  UNSPEC_FRECPS))]
+   "TARGET_SIMD"
+   "frecps\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
+-  [(set_attr "type" "neon_fp_recps_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_recps_<stype><q>")]
+ )
+ 
+ (define_insn "aarch64_urecpe<mode>"
+@@ -5414,13 +5638,25 @@
+   [(set_attr "type" "crypto_aese")]
+ )
+ 
++;; When AES/AESMC fusion is enabled we want the register allocation to
++;; look like:
++;;    AESE Vn, _
++;;    AESMC Vn, Vn
++;; So prefer to tie operand 1 to operand 0 when fusing.
++
+ (define_insn "aarch64_crypto_aes<aesmc_op>v16qi"
+-  [(set (match_operand:V16QI 0 "register_operand" "=w")
+-	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "w")]
++  [(set (match_operand:V16QI 0 "register_operand" "=w,w")
++	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0,w")]
+ 	 CRYPTO_AESMC))]
+   "TARGET_SIMD && TARGET_CRYPTO"
+   "aes<aesmc_op>\\t%0.16b, %1.16b"
+-  [(set_attr "type" "crypto_aesmc")]
++  [(set_attr "type" "crypto_aesmc")
++   (set_attr_alternative "enabled"
++     [(if_then_else (match_test
++		       "aarch64_fusion_enabled_p (AARCH64_FUSE_AES_AESMC)")
++		     (const_string "yes" )
++		     (const_string "no"))
++      (const_string "yes")])]
+ )
+ 
+ ;; sha1
+@@ -5435,6 +5671,26 @@
+   [(set_attr "type" "crypto_sha1_fast")]
+ )
+ 
++(define_insn "aarch64_crypto_sha1hv4si"
++  [(set (match_operand:SI 0 "register_operand" "=w")
++	(unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w")
++		     (parallel [(const_int 0)]))]
++	 UNSPEC_SHA1H))]
++  "TARGET_SIMD && TARGET_CRYPTO && !BYTES_BIG_ENDIAN"
++  "sha1h\\t%s0, %s1"
++  [(set_attr "type" "crypto_sha1_fast")]
++)
++
++(define_insn "aarch64_be_crypto_sha1hv4si"
++  [(set (match_operand:SI 0 "register_operand" "=w")
++	(unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w")
++		     (parallel [(const_int 3)]))]
++	 UNSPEC_SHA1H))]
++  "TARGET_SIMD && TARGET_CRYPTO && BYTES_BIG_ENDIAN"
++  "sha1h\\t%s0, %s1"
++  [(set_attr "type" "crypto_sha1_fast")]
++)
++
+ (define_insn "aarch64_crypto_sha1su1v4si"
+   [(set (match_operand:V4SI 0 "register_operand" "=w")
+         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+--- a/src/gcc/config/aarch64/aarch64-tune.md
++++ b/src/gcc/config/aarch64/aarch64-tune.md
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from aarch64-cores.def
+ (define_attr "tune"
+-	"cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
++	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
+ 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
+--- a/src/gcc/config/aarch64/aarch64-tuning-flags.def
++++ b/src/gcc/config/aarch64/aarch64-tuning-flags.def
+@@ -29,5 +29,8 @@
+      AARCH64_TUNE_ to give an enum name. */
+ 
+ AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS)
+-AARCH64_EXTRA_TUNING_OPTION ("approx_rsqrt", APPROX_RSQRT)
+ 
++/* Don't create non-8 byte aligned load/store pair.  That is if the
++two load/stores are not at least 8 byte aligned don't create load/store
++pairs.   */
++AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW)
+--- a/src/gcc/config/aarch64/aarch64.c
++++ b/src/gcc/config/aarch64/aarch64.c
+@@ -26,6 +26,7 @@
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "cfgloop.h"
+@@ -152,7 +153,7 @@ enum aarch64_processor aarch64_tune = cortexa53;
+ unsigned long aarch64_tune_flags = 0;
+ 
+ /* Global flag for PC relative loads.  */
+-bool aarch64_nopcrelative_literal_loads;
++bool aarch64_pcrelative_literal_loads;
+ 
+ /* Support for command line parsing of boolean flags in the tuning
+    structures.  */
+@@ -250,6 +251,38 @@ static const struct cpu_addrcost_table xgene1_addrcost_table =
+   0, /* imm_offset  */
+ };
+ 
++static const struct cpu_addrcost_table qdf24xx_addrcost_table =
++{
++    {
++      1, /* hi  */
++      0, /* si  */
++      0, /* di  */
++      1, /* ti  */
++    },
++  0, /* pre_modify  */
++  0, /* post_modify  */
++  0, /* register_offset  */
++  0, /* register_sextend  */
++  0, /* register_zextend  */
++  0 /* imm_offset  */
++};
++
++static const struct cpu_addrcost_table vulcan_addrcost_table =
++{
++    {
++      0, /* hi  */
++      0, /* si  */
++      0, /* di  */
++      2, /* ti  */
++    },
++  0, /* pre_modify  */
++  0, /* post_modify  */
++  2, /* register_offset  */
++  3, /* register_sextend  */
++  3, /* register_zextend  */
++  0, /* imm_offset  */
++};
++
+ static const struct cpu_regmove_cost generic_regmove_cost =
+ {
+   1, /* GP2GP  */
+@@ -308,6 +341,24 @@ static const struct cpu_regmove_cost xgene1_regmove_cost =
+   2 /* FP2FP  */
+ };
+ 
++static const struct cpu_regmove_cost qdf24xx_regmove_cost =
++{
++  2, /* GP2GP  */
++  /* Avoid the use of int<->fp moves for spilling.  */
++  6, /* GP2FP  */
++  6, /* FP2GP  */
++  4 /* FP2FP  */
++};
++
++static const struct cpu_regmove_cost vulcan_regmove_cost =
++{
++  1, /* GP2GP  */
++  /* Avoid the use of int<->fp moves for spilling.  */
++  8, /* GP2FP  */
++  8, /* FP2GP  */
++  4  /* FP2FP  */
++};
++
+ /* Generic costs for vector insn classes.  */
+ static const struct cpu_vector_cost generic_vector_cost =
+ {
+@@ -326,18 +377,36 @@ static const struct cpu_vector_cost generic_vector_cost =
+   1 /* cond_not_taken_branch_cost  */
+ };
+ 
++/* ThunderX costs for vector insn classes.  */
++static const struct cpu_vector_cost thunderx_vector_cost =
++{
++  1, /* scalar_stmt_cost  */
++  3, /* scalar_load_cost  */
++  1, /* scalar_store_cost  */
++  4, /* vec_stmt_cost  */
++  4, /* vec_permute_cost  */
++  2, /* vec_to_scalar_cost  */
++  2, /* scalar_to_vec_cost  */
++  3, /* vec_align_load_cost  */
++  10, /* vec_unalign_load_cost  */
++  10, /* vec_unalign_store_cost  */
++  1, /* vec_store_cost  */
++  3, /* cond_taken_branch_cost  */
++  3 /* cond_not_taken_branch_cost  */
++};
++
+ /* Generic costs for vector insn classes.  */
+ static const struct cpu_vector_cost cortexa57_vector_cost =
+ {
+   1, /* scalar_stmt_cost  */
+   4, /* scalar_load_cost  */
+   1, /* scalar_store_cost  */
+-  3, /* vec_stmt_cost  */
++  2, /* vec_stmt_cost  */
+   3, /* vec_permute_cost  */
+   8, /* vec_to_scalar_cost  */
+   8, /* scalar_to_vec_cost  */
+-  5, /* vec_align_load_cost  */
+-  5, /* vec_unalign_load_cost  */
++  4, /* vec_align_load_cost  */
++  4, /* vec_unalign_load_cost  */
+   1, /* vec_unalign_store_cost  */
+   1, /* vec_store_cost  */
+   1, /* cond_taken_branch_cost  */
+@@ -379,6 +448,24 @@ static const struct cpu_vector_cost xgene1_vector_cost =
+   1 /* cond_not_taken_branch_cost  */
+ };
+ 
++/* Costs for vector insn classes for Vulcan.  */
++static const struct cpu_vector_cost vulcan_vector_cost =
++{
++  6, /* scalar_stmt_cost  */
++  4, /* scalar_load_cost  */
++  1, /* scalar_store_cost  */
++  6, /* vec_stmt_cost  */
++  3, /* vec_permute_cost  */
++  6, /* vec_to_scalar_cost  */
++  5, /* scalar_to_vec_cost  */
++  8, /* vec_align_load_cost  */
++  8, /* vec_unalign_load_cost  */
++  4, /* vec_unalign_store_cost  */
++  4, /* vec_store_cost  */
++  2, /* cond_taken_branch_cost  */
++  1  /* cond_not_taken_branch_cost  */
++};
++
+ /* Generic costs for branch instructions.  */
+ static const struct cpu_branch_cost generic_branch_cost =
+ {
+@@ -393,6 +480,37 @@ static const struct cpu_branch_cost cortexa57_branch_cost =
+   3   /* Unpredictable.  */
+ };
+ 
++/* Branch costs for Vulcan.  */
++static const struct cpu_branch_cost vulcan_branch_cost =
++{
++  1,  /* Predictable.  */
++  3   /* Unpredictable.  */
++};
++
++/* Generic approximation modes.  */
++static const cpu_approx_modes generic_approx_modes =
++{
++  AARCH64_APPROX_NONE,	/* division  */
++  AARCH64_APPROX_NONE,	/* sqrt  */
++  AARCH64_APPROX_NONE	/* recip_sqrt  */
++};
++
++/* Approximation modes for Exynos M1.  */
++static const cpu_approx_modes exynosm1_approx_modes =
++{
++  AARCH64_APPROX_NONE,	/* division  */
++  AARCH64_APPROX_ALL,	/* sqrt  */
++  AARCH64_APPROX_ALL	/* recip_sqrt  */
++};
++
++/* Approximation modes for X-Gene 1.  */
++static const cpu_approx_modes xgene1_approx_modes =
++{
++  AARCH64_APPROX_NONE,	/* division  */
++  AARCH64_APPROX_NONE,	/* sqrt  */
++  AARCH64_APPROX_ALL	/* recip_sqrt  */
++};
++
+ static const struct tune_params generic_tunings =
+ {
+   &cortexa57_extra_costs,
+@@ -400,6 +518,7 @@ static const struct tune_params generic_tunings =
+   &generic_regmove_cost,
+   &generic_vector_cost,
+   &generic_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   2, /* issue_rate  */
+   AARCH64_FUSE_NOTHING, /* fusible_ops  */
+@@ -423,14 +542,15 @@ static const struct tune_params cortexa35_tunings =
+   &generic_addrcost_table,
+   &cortexa53_regmove_cost,
+   &generic_vector_cost,
+-  &generic_branch_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   1, /* issue_rate  */
+-  (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
++  (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops  */
+-  8,	/* function_align.  */
++  16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -448,14 +568,15 @@ static const struct tune_params cortexa53_tunings =
+   &generic_addrcost_table,
+   &cortexa53_regmove_cost,
+   &generic_vector_cost,
+-  &generic_branch_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   2, /* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops  */
+-  8,	/* function_align.  */
++  16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -474,13 +595,14 @@ static const struct tune_params cortexa57_tunings =
+   &cortexa57_regmove_cost,
+   &cortexa57_vector_cost,
+   &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   3, /* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops  */
+   16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -498,14 +620,15 @@ static const struct tune_params cortexa72_tunings =
+   &cortexa57_addrcost_table,
+   &cortexa57_regmove_cost,
+   &cortexa57_vector_cost,
+-  &generic_branch_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   3, /* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops  */
+   16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -513,7 +636,33 @@ static const struct tune_params cortexa72_tunings =
+   2,	/* min_div_recip_mul_df.  */
+   0,	/* max_case_values.  */
+   0,	/* cache_line_size.  */
+-  tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
++  tune_params::AUTOPREFETCHER_WEAK,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++};
++
++static const struct tune_params cortexa73_tunings =
++{
++  &cortexa57_extra_costs,
++  &cortexa57_addrcost_table,
++  &cortexa57_regmove_cost,
++  &cortexa57_vector_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
++  4, /* memmov_cost.  */
++  2, /* issue_rate.  */
++  (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
++   | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  8,	/* loop_align.  */
++  2,	/* int_reassoc_width.  */
++  4,	/* fp_reassoc_width.  */
++  1,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  0,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_WEAK,	/* autoprefetcher_model.  */
+   (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
+ };
+ 
+@@ -524,6 +673,7 @@ static const struct tune_params exynosm1_tunings =
+   &exynosm1_regmove_cost,
+   &exynosm1_vector_cost,
+   &generic_branch_cost,
++  &exynosm1_approx_modes,
+   4,	/* memmov_cost  */
+   3,	/* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC), /* fusible_ops  */
+@@ -538,7 +688,7 @@ static const struct tune_params exynosm1_tunings =
+   48,	/* max_case_values.  */
+   64,	/* cache_line_size.  */
+   tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model.  */
+-  (AARCH64_EXTRA_TUNE_APPROX_RSQRT) /* tune_flags.  */
++  (AARCH64_EXTRA_TUNE_NONE) /* tune_flags.  */
+ };
+ 
+ static const struct tune_params thunderx_tunings =
+@@ -546,8 +696,9 @@ static const struct tune_params thunderx_tunings =
+   &thunderx_extra_costs,
+   &generic_addrcost_table,
+   &thunderx_regmove_cost,
+-  &generic_vector_cost,
++  &thunderx_vector_cost,
+   &generic_branch_cost,
++  &generic_approx_modes,
+   6, /* memmov_cost  */
+   2, /* issue_rate  */
+   AARCH64_FUSE_CMP_BRANCH, /* fusible_ops  */
+@@ -562,7 +713,7 @@ static const struct tune_params thunderx_tunings =
+   0,	/* max_case_values.  */
+   0,	/* cache_line_size.  */
+   tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
+-  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++  (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)	/* tune_flags.  */
+ };
+ 
+ static const struct tune_params xgene1_tunings =
+@@ -572,6 +723,7 @@ static const struct tune_params xgene1_tunings =
+   &xgene1_regmove_cost,
+   &xgene1_vector_cost,
+   &generic_branch_cost,
++  &xgene1_approx_modes,
+   6, /* memmov_cost  */
+   4, /* issue_rate  */
+   AARCH64_FUSE_NOTHING, /* fusible_ops  */
+@@ -586,7 +738,58 @@ static const struct tune_params xgene1_tunings =
+   0,	/* max_case_values.  */
+   0,	/* cache_line_size.  */
+   tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
+-  (AARCH64_EXTRA_TUNE_APPROX_RSQRT)	/* tune_flags.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++};
++
++static const struct tune_params qdf24xx_tunings =
++{
++  &qdf24xx_extra_costs,
++  &qdf24xx_addrcost_table,
++  &qdf24xx_regmove_cost,
++  &generic_vector_cost,
++  &generic_branch_cost,
++  &generic_approx_modes,
++  4, /* memmov_cost  */
++  4, /* issue_rate  */
++  (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
++   | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  16,	/* loop_align.  */
++  2,	/* int_reassoc_width.  */
++  4,	/* fp_reassoc_width.  */
++  1,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  64,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_STRONG,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)		/* tune_flags.  */
++};
++
++static const struct tune_params vulcan_tunings =
++{
++  &vulcan_extra_costs,
++  &vulcan_addrcost_table,
++  &vulcan_regmove_cost,
++  &vulcan_vector_cost,
++  &vulcan_branch_cost,
++  &generic_approx_modes,
++  4, /* memmov_cost.  */
++  4, /* issue_rate.  */
++  AARCH64_FUSE_NOTHING, /* fuseable_ops.  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  16,	/* loop_align.  */
++  3,	/* int_reassoc_width.  */
++  2,	/* fp_reassoc_width.  */
++  2,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  64,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
+ };
+ 
+ /* Support for fine-grained override of the tuning structures.  */
+@@ -663,16 +866,6 @@ struct aarch64_option_extension
+   const unsigned long flags_off;
+ };
+ 
+-/* ISA extensions in AArch64.  */
+-static const struct aarch64_option_extension all_extensions[] =
+-{
+-#define AARCH64_OPT_EXTENSION(NAME, X, FLAGS_ON, FLAGS_OFF, FEATURE_STRING) \
+-  {NAME, FLAGS_ON, FLAGS_OFF},
+-#include "aarch64-option-extensions.def"
+-#undef AARCH64_OPT_EXTENSION
+-  {NULL, 0, 0}
+-};
+-
+ typedef enum aarch64_cond_code
+ {
+   AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL,
+@@ -1703,7 +1896,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
+ 	     we need to expand the literal pool access carefully.
+ 	     This is something that needs to be done in a number
+ 	     of places, so could well live as a separate function.  */
+-	  if (aarch64_nopcrelative_literal_loads)
++	  if (!aarch64_pcrelative_literal_loads)
+ 	    {
+ 	      gcc_assert (can_create_pseudo_p ());
+ 	      base = gen_reg_rtx (ptr_mode);
+@@ -1766,6 +1959,88 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
+   aarch64_internal_mov_immediate (dest, imm, true, GET_MODE (dest));
+ }
+ 
++/* Add DELTA to REGNUM in mode MODE.  SCRATCHREG can be used to hold a
++   temporary value if necessary.  FRAME_RELATED_P should be true if
++   the RTX_FRAME_RELATED flag should be set and CFA adjustments added
++   to the generated instructions.  If SCRATCHREG is known to hold
++   abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
++   immediate again.
++
++   Since this function may be used to adjust the stack pointer, we must
++   ensure that it cannot cause transient stack deallocation (for example
++   by first incrementing SP and then decrementing when adjusting by a
++   large immediate).  */
++
++static void
++aarch64_add_constant_internal (machine_mode mode, int regnum, int scratchreg,
++			       HOST_WIDE_INT delta, bool frame_related_p,
++			       bool emit_move_imm)
++{
++  HOST_WIDE_INT mdelta = abs_hwi (delta);
++  rtx this_rtx = gen_rtx_REG (mode, regnum);
++  rtx_insn *insn;
++
++  if (!mdelta)
++    return;
++
++  /* Single instruction adjustment.  */
++  if (aarch64_uimm12_shift (mdelta))
++    {
++      insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (delta)));
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      return;
++    }
++
++  /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
++     Only do this if mdelta is not a 16-bit move as adjusting using a move
++     is better.  */
++  if (mdelta < 0x1000000 && !aarch64_move_imm (mdelta, mode))
++    {
++      HOST_WIDE_INT low_off = mdelta & 0xfff;
++
++      low_off = delta < 0 ? -low_off : low_off;
++      insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (low_off)));
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (delta - low_off)));
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      return;
++    }
++
++  /* Emit a move immediate if required and an addition/subtraction.  */
++  rtx scratch_rtx = gen_rtx_REG (mode, scratchreg);
++  if (emit_move_imm)
++    aarch64_internal_mov_immediate (scratch_rtx, GEN_INT (mdelta), true, mode);
++  insn = emit_insn (delta < 0 ? gen_sub2_insn (this_rtx, scratch_rtx)
++			      : gen_add2_insn (this_rtx, scratch_rtx));
++  if (frame_related_p)
++    {
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      rtx adj = plus_constant (mode, this_rtx, delta);
++      add_reg_note (insn , REG_CFA_ADJUST_CFA, gen_rtx_SET (this_rtx, adj));
++    }
++}
++
++static inline void
++aarch64_add_constant (machine_mode mode, int regnum, int scratchreg,
++		      HOST_WIDE_INT delta)
++{
++  aarch64_add_constant_internal (mode, regnum, scratchreg, delta, false, true);
++}
++
++static inline void
++aarch64_add_sp (int scratchreg, HOST_WIDE_INT delta, bool emit_move_imm)
++{
++  aarch64_add_constant_internal (Pmode, SP_REGNUM, scratchreg, delta,
++				 true, emit_move_imm);
++}
++
++static inline void
++aarch64_sub_sp (int scratchreg, HOST_WIDE_INT delta, bool frame_related_p)
++{
++  aarch64_add_constant_internal (Pmode, SP_REGNUM, scratchreg, -delta,
++				 frame_related_p, true);
++}
++
+ static bool
+ aarch64_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
+ 				 tree exp ATTRIBUTE_UNUSED)
+@@ -2494,7 +2769,7 @@ static void
+ aarch64_layout_frame (void)
+ {
+   HOST_WIDE_INT offset = 0;
+-  int regno;
++  int regno, last_fp_reg = INVALID_REGNUM;
+ 
+   if (reload_completed && cfun->machine->frame.laid_out)
+     return;
+@@ -2502,8 +2777,8 @@ aarch64_layout_frame (void)
+ #define SLOT_NOT_REQUIRED (-2)
+ #define SLOT_REQUIRED     (-1)
+ 
+-  cfun->machine->frame.wb_candidate1 = FIRST_PSEUDO_REGISTER;
+-  cfun->machine->frame.wb_candidate2 = FIRST_PSEUDO_REGISTER;
++  cfun->machine->frame.wb_candidate1 = INVALID_REGNUM;
++  cfun->machine->frame.wb_candidate2 = INVALID_REGNUM;
+ 
+   /* First mark all the registers that really need to be saved...  */
+   for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++)
+@@ -2528,7 +2803,10 @@ aarch64_layout_frame (void)
+   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
+     if (df_regs_ever_live_p (regno)
+ 	&& !call_used_regs[regno])
+-      cfun->machine->frame.reg_offset[regno] = SLOT_REQUIRED;
++      {
++	cfun->machine->frame.reg_offset[regno] = SLOT_REQUIRED;
++	last_fp_reg = regno;
++      }
+ 
+   if (frame_pointer_needed)
+     {
+@@ -2537,7 +2815,6 @@ aarch64_layout_frame (void)
+       cfun->machine->frame.wb_candidate1 = R29_REGNUM;
+       cfun->machine->frame.reg_offset[R30_REGNUM] = UNITS_PER_WORD;
+       cfun->machine->frame.wb_candidate2 = R30_REGNUM;
+-      cfun->machine->frame.hardfp_offset = 2 * UNITS_PER_WORD;
+       offset += 2 * UNITS_PER_WORD;
+     }
+ 
+@@ -2546,35 +2823,46 @@ aarch64_layout_frame (void)
+     if (cfun->machine->frame.reg_offset[regno] == SLOT_REQUIRED)
+       {
+ 	cfun->machine->frame.reg_offset[regno] = offset;
+-	if (cfun->machine->frame.wb_candidate1 == FIRST_PSEUDO_REGISTER)
++	if (cfun->machine->frame.wb_candidate1 == INVALID_REGNUM)
+ 	  cfun->machine->frame.wb_candidate1 = regno;
+-	else if (cfun->machine->frame.wb_candidate2 == FIRST_PSEUDO_REGISTER)
++	else if (cfun->machine->frame.wb_candidate2 == INVALID_REGNUM)
+ 	  cfun->machine->frame.wb_candidate2 = regno;
+ 	offset += UNITS_PER_WORD;
+       }
+ 
++  HOST_WIDE_INT max_int_offset = offset;
++  offset = ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT);
++  bool has_align_gap = offset != max_int_offset;
++
+   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
+     if (cfun->machine->frame.reg_offset[regno] == SLOT_REQUIRED)
+       {
++	/* If there is an alignment gap between integer and fp callee-saves,
++	   allocate the last fp register to it if possible.  */
++	if (regno == last_fp_reg && has_align_gap && (offset & 8) == 0)
++	  {
++	    cfun->machine->frame.reg_offset[regno] = max_int_offset;
++	    break;
++	  }
++
+ 	cfun->machine->frame.reg_offset[regno] = offset;
+-	if (cfun->machine->frame.wb_candidate1 == FIRST_PSEUDO_REGISTER)
++	if (cfun->machine->frame.wb_candidate1 == INVALID_REGNUM)
+ 	  cfun->machine->frame.wb_candidate1 = regno;
+-	else if (cfun->machine->frame.wb_candidate2 == FIRST_PSEUDO_REGISTER
++	else if (cfun->machine->frame.wb_candidate2 == INVALID_REGNUM
+ 		 && cfun->machine->frame.wb_candidate1 >= V0_REGNUM)
+ 	  cfun->machine->frame.wb_candidate2 = regno;
+ 	offset += UNITS_PER_WORD;
+       }
+ 
+-  cfun->machine->frame.padding0 =
+-    (ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT) - offset);
+   offset = ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT);
+ 
+   cfun->machine->frame.saved_regs_size = offset;
+ 
++  HOST_WIDE_INT varargs_and_saved_regs_size
++    = offset + cfun->machine->frame.saved_varargs_size;
++
+   cfun->machine->frame.hard_fp_offset
+-    = ROUND_UP (cfun->machine->frame.saved_varargs_size
+-		+ get_frame_size ()
+-		+ cfun->machine->frame.saved_regs_size,
++    = ROUND_UP (varargs_and_saved_regs_size + get_frame_size (),
+ 		STACK_BOUNDARY / BITS_PER_UNIT);
+ 
+   cfun->machine->frame.frame_size
+@@ -2582,15 +2870,92 @@ aarch64_layout_frame (void)
+ 		+ crtl->outgoing_args_size,
+ 		STACK_BOUNDARY / BITS_PER_UNIT);
+ 
++  cfun->machine->frame.locals_offset = cfun->machine->frame.saved_varargs_size;
++
++  cfun->machine->frame.initial_adjust = 0;
++  cfun->machine->frame.final_adjust = 0;
++  cfun->machine->frame.callee_adjust = 0;
++  cfun->machine->frame.callee_offset = 0;
++
++  HOST_WIDE_INT max_push_offset = 0;
++  if (cfun->machine->frame.wb_candidate2 != INVALID_REGNUM)
++    max_push_offset = 512;
++  else if (cfun->machine->frame.wb_candidate1 != INVALID_REGNUM)
++    max_push_offset = 256;
++
++  if (cfun->machine->frame.frame_size < max_push_offset
++      && crtl->outgoing_args_size == 0)
++    {
++      /* Simple, small frame with no outgoing arguments:
++	 stp reg1, reg2, [sp, -frame_size]!
++	 stp reg3, reg4, [sp, 16]  */
++      cfun->machine->frame.callee_adjust = cfun->machine->frame.frame_size;
++    }
++  else if ((crtl->outgoing_args_size
++	    + cfun->machine->frame.saved_regs_size < 512)
++	   && !(cfun->calls_alloca
++		&& cfun->machine->frame.hard_fp_offset < max_push_offset))
++    {
++      /* Frame with small outgoing arguments:
++	 sub sp, sp, frame_size
++	 stp reg1, reg2, [sp, outgoing_args_size]
++	 stp reg3, reg4, [sp, outgoing_args_size + 16]  */
++      cfun->machine->frame.initial_adjust = cfun->machine->frame.frame_size;
++      cfun->machine->frame.callee_offset
++	= cfun->machine->frame.frame_size - cfun->machine->frame.hard_fp_offset;
++    }
++  else if (cfun->machine->frame.hard_fp_offset < max_push_offset)
++    {
++      /* Frame with large outgoing arguments but a small local area:
++	 stp reg1, reg2, [sp, -hard_fp_offset]!
++	 stp reg3, reg4, [sp, 16]
++	 sub sp, sp, outgoing_args_size  */
++      cfun->machine->frame.callee_adjust = cfun->machine->frame.hard_fp_offset;
++      cfun->machine->frame.final_adjust
++	= cfun->machine->frame.frame_size - cfun->machine->frame.callee_adjust;
++    }
++  else if (!frame_pointer_needed
++	   && varargs_and_saved_regs_size < max_push_offset)
++    {
++      /* Frame with large local area and outgoing arguments (this pushes the
++	 callee-saves first, followed by the locals and outgoing area):
++	 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
++	 stp reg3, reg4, [sp, 16]
++	 sub sp, sp, frame_size - varargs_and_saved_regs_size  */
++      cfun->machine->frame.callee_adjust = varargs_and_saved_regs_size;
++      cfun->machine->frame.final_adjust
++	= cfun->machine->frame.frame_size - cfun->machine->frame.callee_adjust;
++      cfun->machine->frame.hard_fp_offset = cfun->machine->frame.callee_adjust;
++      cfun->machine->frame.locals_offset = cfun->machine->frame.hard_fp_offset;
++    }
++  else
++    {
++      /* Frame with large local area and outgoing arguments using frame pointer:
++	 sub sp, sp, hard_fp_offset
++	 stp x29, x30, [sp, 0]
++	 add x29, sp, 0
++	 stp reg3, reg4, [sp, 16]
++	 sub sp, sp, outgoing_args_size  */
++      cfun->machine->frame.initial_adjust = cfun->machine->frame.hard_fp_offset;
++      cfun->machine->frame.final_adjust
++	= cfun->machine->frame.frame_size - cfun->machine->frame.initial_adjust;
++    }
++
+   cfun->machine->frame.laid_out = true;
+ }
+ 
++/* Return true if the register REGNO is saved on entry to
++   the current function.  */
++
+ static bool
+ aarch64_register_saved_on_entry (int regno)
+ {
+   return cfun->machine->frame.reg_offset[regno] >= 0;
+ }
+ 
++/* Return the next register up from REGNO up to LIMIT for the callee
++   to save.  */
++
+ static unsigned
+ aarch64_next_callee_save (unsigned regno, unsigned limit)
+ {
+@@ -2599,6 +2964,9 @@ aarch64_next_callee_save (unsigned regno, unsigned limit)
+   return regno;
+ }
+ 
++/* Push the register number REGNO of mode MODE to the stack with write-back
++   adjusting the stack by ADJUSTMENT.  */
++
+ static void
+ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno,
+ 			   HOST_WIDE_INT adjustment)
+@@ -2615,6 +2983,10 @@ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno,
+   RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ 
++/* Generate and return an instruction to store the pair of registers
++   REG and REG2 of mode MODE to location BASE with write-back adjusting
++   the stack location BASE by ADJUSTMENT.  */
++
+ static rtx
+ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+ 			  HOST_WIDE_INT adjustment)
+@@ -2634,11 +3006,18 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+     }
+ }
+ 
++/* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
++   stack pointer by ADJUSTMENT.  */
++
+ static void
+-aarch64_pushwb_pair_reg (machine_mode mode, unsigned regno1,
+-			 unsigned regno2, HOST_WIDE_INT adjustment)
++aarch64_push_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment)
+ {
+   rtx_insn *insn;
++  machine_mode mode = (regno1 <= R30_REGNUM) ? DImode : DFmode;
++
++  if (regno2 == INVALID_REGNUM)
++    return aarch64_pushwb_single_reg (mode, regno1, adjustment);
++
+   rtx reg1 = gen_rtx_REG (mode, regno1);
+   rtx reg2 = gen_rtx_REG (mode, regno2);
+ 
+@@ -2649,6 +3028,9 @@ aarch64_pushwb_pair_reg (machine_mode mode, unsigned regno1,
+   RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ 
++/* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
++   adjusting it by ADJUSTMENT afterwards.  */
++
+ static rtx
+ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+ 			 HOST_WIDE_INT adjustment)
+@@ -2666,6 +3048,37 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+     }
+ }
+ 
++/* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
++   afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
++   into CFI_OPS.  */
++
++static void
++aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment,
++		  rtx *cfi_ops)
++{
++  machine_mode mode = (regno1 <= R30_REGNUM) ? DImode : DFmode;
++  rtx reg1 = gen_rtx_REG (mode, regno1);
++
++  *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg1, *cfi_ops);
++
++  if (regno2 == INVALID_REGNUM)
++    {
++      rtx mem = plus_constant (Pmode, stack_pointer_rtx, adjustment);
++      mem = gen_rtx_POST_MODIFY (Pmode, stack_pointer_rtx, mem);
++      emit_move_insn (reg1, gen_rtx_MEM (mode, mem));
++    }
++  else
++    {
++      rtx reg2 = gen_rtx_REG (mode, regno2);
++      *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg2, *cfi_ops);
++      emit_insn (aarch64_gen_loadwb_pair (mode, stack_pointer_rtx, reg1,
++					  reg2, adjustment));
++    }
++}
++
++/* Generate and return a store pair instruction of mode MODE to store
++   register REG1 to MEM1 and register REG2 to MEM2.  */
++
+ static rtx
+ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
+ 			rtx reg2)
+@@ -2683,6 +3096,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
+     }
+ }
+ 
++/* Generate and regurn a load pair isntruction of mode MODE to load register
++   REG1 from MEM1 and register REG2 from MEM2.  */
++
+ static rtx
+ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
+ 		       rtx mem2)
+@@ -2700,6 +3116,9 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
+     }
+ }
+ 
++/* Emit code to save the callee-saved registers from register number START
++   to LIMIT to the stack at the location starting at offset START_OFFSET,
++   skipping any write-back candidates if SKIP_WB is true.  */
+ 
+ static void
+ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset,
+@@ -2758,6 +3177,11 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset,
+     }
+ }
+ 
++/* Emit code to restore the callee registers of mode MODE from register
++   number START up to and including LIMIT.  Restore from the stack offset
++   START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
++   Write the appropriate REG_CFA_RESTORE notes into CFI_OPS.  */
++
+ static void
+ aarch64_restore_callee_saves (machine_mode mode,
+ 			      HOST_WIDE_INT start_offset, unsigned start,
+@@ -2852,23 +3276,16 @@ aarch64_restore_callee_saves (machine_mode mode,
+ void
+ aarch64_expand_prologue (void)
+ {
+-  /* sub sp, sp, #<frame_size>
+-     stp {fp, lr}, [sp, #<frame_size> - 16]
+-     add fp, sp, #<frame_size> - hardfp_offset
+-     stp {cs_reg}, [fp, #-16] etc.
+-
+-     sub sp, sp, <final_adjustment_if_any>
+-  */
+-  HOST_WIDE_INT frame_size, offset;
+-  HOST_WIDE_INT fp_offset;		/* Offset from hard FP to SP.  */
+-  HOST_WIDE_INT hard_fp_offset;
+-  rtx_insn *insn;
+-
+   aarch64_layout_frame ();
+ 
+-  offset = frame_size = cfun->machine->frame.frame_size;
+-  hard_fp_offset = cfun->machine->frame.hard_fp_offset;
+-  fp_offset = frame_size - hard_fp_offset;
++  HOST_WIDE_INT frame_size = cfun->machine->frame.frame_size;
++  HOST_WIDE_INT initial_adjust = cfun->machine->frame.initial_adjust;
++  HOST_WIDE_INT callee_adjust = cfun->machine->frame.callee_adjust;
++  HOST_WIDE_INT final_adjust = cfun->machine->frame.final_adjust;
++  HOST_WIDE_INT callee_offset = cfun->machine->frame.callee_offset;
++  unsigned reg1 = cfun->machine->frame.wb_candidate1;
++  unsigned reg2 = cfun->machine->frame.wb_candidate2;
++  rtx_insn *insn;
+ 
+   if (flag_stack_usage_info)
+     current_function_static_stack_size = frame_size;
+@@ -2885,129 +3302,28 @@ aarch64_expand_prologue (void)
+ 	aarch64_emit_probe_stack_range (STACK_CHECK_PROTECT, frame_size);
+     }
+ 
+-  /* Store pairs and load pairs have a range only -512 to 504.  */
+-  if (offset >= 512)
+-    {
+-      /* When the frame has a large size, an initial decrease is done on
+-	 the stack pointer to jump over the callee-allocated save area for
+-	 register varargs, the local variable area and/or the callee-saved
+-	 register area.  This will allow the pre-index write-back
+-	 store pair instructions to be used for setting up the stack frame
+-	 efficiently.  */
+-      offset = hard_fp_offset;
+-      if (offset >= 512)
+-	offset = cfun->machine->frame.saved_regs_size;
+-
+-      frame_size -= (offset + crtl->outgoing_args_size);
+-      fp_offset = 0;
++  aarch64_sub_sp (IP0_REGNUM, initial_adjust, true);
+ 
+-      if (frame_size >= 0x1000000)
+-	{
+-	  rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
+-	  emit_move_insn (op0, GEN_INT (-frame_size));
+-	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
++  if (callee_adjust != 0)
++    aarch64_push_regs (reg1, reg2, callee_adjust);
+ 
+-	  add_reg_note (insn, REG_CFA_ADJUST_CFA,
+-			gen_rtx_SET (stack_pointer_rtx,
+-				     plus_constant (Pmode, stack_pointer_rtx,
+-						    -frame_size)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	}
+-      else if (frame_size > 0)
+-	{
+-	  int hi_ofs = frame_size & 0xfff000;
+-	  int lo_ofs = frame_size & 0x000fff;
+-
+-	  if (hi_ofs)
+-	    {
+-	      insn = emit_insn (gen_add2_insn
+-				(stack_pointer_rtx, GEN_INT (-hi_ofs)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	    }
+-	  if (lo_ofs)
+-	    {
+-	      insn = emit_insn (gen_add2_insn
+-				(stack_pointer_rtx, GEN_INT (-lo_ofs)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	    }
+-	}
+-    }
+-  else
+-    frame_size = -1;
+-
+-  if (offset > 0)
+-    {
+-      bool skip_wb = false;
+-
+-      if (frame_pointer_needed)
+-	{
+-	  skip_wb = true;
+-
+-	  if (fp_offset)
+-	    {
+-	      insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+-					       GEN_INT (-offset)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-
+-	      aarch64_save_callee_saves (DImode, fp_offset, R29_REGNUM,
+-					 R30_REGNUM, false);
+-	    }
+-	  else
+-	    aarch64_pushwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, offset);
+-
+-	  /* Set up frame pointer to point to the location of the
+-	     previous frame pointer on the stack.  */
+-	  insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
+-					   stack_pointer_rtx,
+-					   GEN_INT (fp_offset)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	  emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
+-	}
+-      else
+-	{
+-	  unsigned reg1 = cfun->machine->frame.wb_candidate1;
+-	  unsigned reg2 = cfun->machine->frame.wb_candidate2;
+-
+-	  if (fp_offset
+-	      || reg1 == FIRST_PSEUDO_REGISTER
+-	      || (reg2 == FIRST_PSEUDO_REGISTER
+-		  && offset >= 256))
+-	    {
+-	      insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+-					       GEN_INT (-offset)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	    }
+-	  else
+-	    {
+-	      machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
+-
+-	      skip_wb = true;
+-
+-	      if (reg2 == FIRST_PSEUDO_REGISTER)
+-		aarch64_pushwb_single_reg (mode1, reg1, offset);
+-	      else
+-		aarch64_pushwb_pair_reg (mode1, reg1, reg2, offset);
+-	    }
+-	}
+-
+-      aarch64_save_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM,
+-				 skip_wb);
+-      aarch64_save_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
+-				 skip_wb);
+-    }
+-
+-  /* when offset >= 512,
+-     sub sp, sp, #<outgoing_args_size> */
+-  if (frame_size > -1)
+-    {
+-      if (crtl->outgoing_args_size > 0)
+-	{
+-	  insn = emit_insn (gen_add2_insn
+-			    (stack_pointer_rtx,
+-			     GEN_INT (- crtl->outgoing_args_size)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	}
++  if (frame_pointer_needed)
++    {
++      if (callee_adjust == 0)
++	aarch64_save_callee_saves (DImode, callee_offset, R29_REGNUM,
++				   R30_REGNUM, false);
++      insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
++				       stack_pointer_rtx,
++				       GEN_INT (callee_offset)));
++      RTX_FRAME_RELATED_P (insn) = 1;
++      emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
+     }
++
++  aarch64_save_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
++			     callee_adjust != 0 || frame_pointer_needed);
++  aarch64_save_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
++			     callee_adjust != 0 || frame_pointer_needed);
++  aarch64_sub_sp (IP1_REGNUM, final_adjust, !frame_pointer_needed);
+ }
+ 
+ /* Return TRUE if we can use a simple_return insn.
+@@ -3030,151 +3346,80 @@ aarch64_use_return_insn_p (void)
+   return cfun->machine->frame.frame_size == 0;
+ }
+ 
+-/* Generate the epilogue instructions for returning from a function.  */
++/* Generate the epilogue instructions for returning from a function.
++   This is almost exactly the reverse of the prolog sequence, except
++   that we need to insert barriers to avoid scheduling loads that read
++   from a deallocated stack, and we optimize the unwind records by
++   emitting them all together if possible.  */
+ void
+ aarch64_expand_epilogue (bool for_sibcall)
+ {
+-  HOST_WIDE_INT frame_size, offset;
+-  HOST_WIDE_INT fp_offset;
+-  HOST_WIDE_INT hard_fp_offset;
+-  rtx_insn *insn;
+-  /* We need to add memory barrier to prevent read from deallocated stack.  */
+-  bool need_barrier_p = (get_frame_size () != 0
+-			 || cfun->machine->frame.saved_varargs_size
+-			 || crtl->calls_eh_return);
+-
+   aarch64_layout_frame ();
+ 
+-  offset = frame_size = cfun->machine->frame.frame_size;
+-  hard_fp_offset = cfun->machine->frame.hard_fp_offset;
+-  fp_offset = frame_size - hard_fp_offset;
++  HOST_WIDE_INT initial_adjust = cfun->machine->frame.initial_adjust;
++  HOST_WIDE_INT callee_adjust = cfun->machine->frame.callee_adjust;
++  HOST_WIDE_INT final_adjust = cfun->machine->frame.final_adjust;
++  HOST_WIDE_INT callee_offset = cfun->machine->frame.callee_offset;
++  unsigned reg1 = cfun->machine->frame.wb_candidate1;
++  unsigned reg2 = cfun->machine->frame.wb_candidate2;
++  rtx cfi_ops = NULL;
++  rtx_insn *insn;
+ 
+-  /* Store pairs and load pairs have a range only -512 to 504.  */
+-  if (offset >= 512)
+-    {
+-      offset = hard_fp_offset;
+-      if (offset >= 512)
+-	offset = cfun->machine->frame.saved_regs_size;
++  /* We need to add memory barrier to prevent read from deallocated stack.  */
++  bool need_barrier_p = (get_frame_size ()
++			 + cfun->machine->frame.saved_varargs_size) != 0;
+ 
+-      frame_size -= (offset + crtl->outgoing_args_size);
+-      fp_offset = 0;
+-      if (!frame_pointer_needed && crtl->outgoing_args_size > 0)
+-	{
+-	  insn = emit_insn (gen_add2_insn
+-			    (stack_pointer_rtx,
+-			     GEN_INT (crtl->outgoing_args_size)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	}
++  /* Emit a barrier to prevent loads from a deallocated stack.  */
++  if (final_adjust > crtl->outgoing_args_size || cfun->calls_alloca
++      || crtl->calls_eh_return)
++    {
++      emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
++      need_barrier_p = false;
+     }
+-  else
+-    frame_size = -1;
+ 
+-  /* If there were outgoing arguments or we've done dynamic stack
+-     allocation, then restore the stack pointer from the frame
+-     pointer.  This is at most one insn and more efficient than using
+-     GCC's internal mechanism.  */
+-  if (frame_pointer_needed
+-      && (crtl->outgoing_args_size || cfun->calls_alloca))
++  /* Restore the stack pointer from the frame pointer if it may not
++     be the same as the stack pointer.  */
++  if (frame_pointer_needed && (final_adjust || cfun->calls_alloca))
+     {
+-      if (cfun->calls_alloca)
+-	emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+-
+       insn = emit_insn (gen_add3_insn (stack_pointer_rtx,
+ 				       hard_frame_pointer_rtx,
+-				       GEN_INT (0)));
+-      offset = offset - fp_offset;
++				       GEN_INT (-callee_offset)));
++      /* If writeback is used when restoring callee-saves, the CFA
++	 is restored on the instruction doing the writeback.  */
++      RTX_FRAME_RELATED_P (insn) = callee_adjust == 0;
+     }
++  else
++    aarch64_add_sp (IP1_REGNUM, final_adjust, df_regs_ever_live_p (IP1_REGNUM));
+ 
+-  if (offset > 0)
+-    {
+-      unsigned reg1 = cfun->machine->frame.wb_candidate1;
+-      unsigned reg2 = cfun->machine->frame.wb_candidate2;
+-      bool skip_wb = true;
+-      rtx cfi_ops = NULL;
+-
+-      if (frame_pointer_needed)
+-	fp_offset = 0;
+-      else if (fp_offset
+-	       || reg1 == FIRST_PSEUDO_REGISTER
+-	       || (reg2 == FIRST_PSEUDO_REGISTER
+-		   && offset >= 256))
+-	skip_wb = false;
+-
+-      aarch64_restore_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM,
+-				    skip_wb, &cfi_ops);
+-      aarch64_restore_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
+-				    skip_wb, &cfi_ops);
+-
+-      if (need_barrier_p)
+-	emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+-
+-      if (skip_wb)
+-	{
+-	  machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
+-	  rtx rreg1 = gen_rtx_REG (mode1, reg1);
++  aarch64_restore_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
++				callee_adjust != 0, &cfi_ops);
++  aarch64_restore_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
++				callee_adjust != 0, &cfi_ops);
+ 
+-	  cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg1, cfi_ops);
+-	  if (reg2 == FIRST_PSEUDO_REGISTER)
+-	    {
+-	      rtx mem = plus_constant (Pmode, stack_pointer_rtx, offset);
+-	      mem = gen_rtx_POST_MODIFY (Pmode, stack_pointer_rtx, mem);
+-	      mem = gen_rtx_MEM (mode1, mem);
+-	      insn = emit_move_insn (rreg1, mem);
+-	    }
+-	  else
+-	    {
+-	      rtx rreg2 = gen_rtx_REG (mode1, reg2);
++  if (need_barrier_p)
++    emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+ 
+-	      cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg2, cfi_ops);
+-	      insn = emit_insn (aarch64_gen_loadwb_pair
+-				(mode1, stack_pointer_rtx, rreg1,
+-				 rreg2, offset));
+-	    }
+-	}
+-      else
+-	{
+-	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+-					   GEN_INT (offset)));
+-	}
++  if (callee_adjust != 0)
++    aarch64_pop_regs (reg1, reg2, callee_adjust, &cfi_ops);
+ 
+-      /* Reset the CFA to be SP + FRAME_SIZE.  */
+-      rtx new_cfa = stack_pointer_rtx;
+-      if (frame_size > 0)
+-	new_cfa = plus_constant (Pmode, new_cfa, frame_size);
+-      cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
+-      REG_NOTES (insn) = cfi_ops;
++  if (callee_adjust != 0 || initial_adjust > 65536)
++    {
++      /* Emit delayed restores and set the CFA to be SP + initial_adjust.  */
++      insn = get_last_insn ();
++      rtx new_cfa = plus_constant (Pmode, stack_pointer_rtx, initial_adjust);
++      REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
+       RTX_FRAME_RELATED_P (insn) = 1;
++      cfi_ops = NULL;
+     }
+ 
+-  if (frame_size > 0)
+-    {
+-      if (need_barrier_p)
+-	emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+-
+-      if (frame_size >= 0x1000000)
+-	{
+-	  rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
+-	  emit_move_insn (op0, GEN_INT (frame_size));
+-	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
+-	}
+-      else
+-	{
+-          int hi_ofs = frame_size & 0xfff000;
+-          int lo_ofs = frame_size & 0x000fff;
+-
+-	  if (hi_ofs && lo_ofs)
+-	    {
+-	      insn = emit_insn (gen_add2_insn
+-				(stack_pointer_rtx, GEN_INT (hi_ofs)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	      frame_size = lo_ofs;
+-	    }
+-	  insn = emit_insn (gen_add2_insn
+-			    (stack_pointer_rtx, GEN_INT (frame_size)));
+-	}
++  aarch64_add_sp (IP0_REGNUM, initial_adjust, df_regs_ever_live_p (IP0_REGNUM));
+ 
+-      /* Reset the CFA to be SP + 0.  */
+-      add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx);
++  if (cfi_ops)
++    {
++      /* Emit delayed restores and reset the CFA to be SP.  */
++      insn = get_last_insn ();
++      cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, stack_pointer_rtx, cfi_ops);
++      REG_NOTES (insn) = cfi_ops;
+       RTX_FRAME_RELATED_P (insn) = 1;
+     }
+ 
+@@ -3230,122 +3475,6 @@ aarch64_eh_return_handler_rtx (void)
+   return tmp;
+ }
+ 
+-/* Possibly output code to build up a constant in a register.  For
+-   the benefit of the costs infrastructure, returns the number of
+-   instructions which would be emitted.  GENERATE inhibits or
+-   enables code generation.  */
+-
+-static int
+-aarch64_build_constant (int regnum, HOST_WIDE_INT val, bool generate)
+-{
+-  int insns = 0;
+-
+-  if (aarch64_bitmask_imm (val, DImode))
+-    {
+-      if (generate)
+-	emit_move_insn (gen_rtx_REG (Pmode, regnum), GEN_INT (val));
+-      insns = 1;
+-    }
+-  else
+-    {
+-      int i;
+-      int ncount = 0;
+-      int zcount = 0;
+-      HOST_WIDE_INT valp = val >> 16;
+-      HOST_WIDE_INT valm;
+-      HOST_WIDE_INT tval;
+-
+-      for (i = 16; i < 64; i += 16)
+-	{
+-	  valm = (valp & 0xffff);
+-
+-	  if (valm != 0)
+-	    ++ zcount;
+-
+-	  if (valm != 0xffff)
+-	    ++ ncount;
+-
+-	  valp >>= 16;
+-	}
+-
+-      /* zcount contains the number of additional MOVK instructions
+-	 required if the constant is built up with an initial MOVZ instruction,
+-	 while ncount is the number of MOVK instructions required if starting
+-	 with a MOVN instruction.  Choose the sequence that yields the fewest
+-	 number of instructions, preferring MOVZ instructions when they are both
+-	 the same.  */
+-      if (ncount < zcount)
+-	{
+-	  if (generate)
+-	    emit_move_insn (gen_rtx_REG (Pmode, regnum),
+-			    GEN_INT (val | ~(HOST_WIDE_INT) 0xffff));
+-	  tval = 0xffff;
+-	  insns++;
+-	}
+-      else
+-	{
+-	  if (generate)
+-	    emit_move_insn (gen_rtx_REG (Pmode, regnum),
+-			    GEN_INT (val & 0xffff));
+-	  tval = 0;
+-	  insns++;
+-	}
+-
+-      val >>= 16;
+-
+-      for (i = 16; i < 64; i += 16)
+-	{
+-	  if ((val & 0xffff) != tval)
+-	    {
+-	      if (generate)
+-		emit_insn (gen_insv_immdi (gen_rtx_REG (Pmode, regnum),
+-					   GEN_INT (i),
+-					   GEN_INT (val & 0xffff)));
+-	      insns++;
+-	    }
+-	  val >>= 16;
+-	}
+-    }
+-  return insns;
+-}
+-
+-static void
+-aarch64_add_constant (int regnum, int scratchreg, HOST_WIDE_INT delta)
+-{
+-  HOST_WIDE_INT mdelta = delta;
+-  rtx this_rtx = gen_rtx_REG (Pmode, regnum);
+-  rtx scratch_rtx = gen_rtx_REG (Pmode, scratchreg);
+-
+-  if (mdelta < 0)
+-    mdelta = -mdelta;
+-
+-  if (mdelta >= 4096 * 4096)
+-    {
+-      (void) aarch64_build_constant (scratchreg, delta, true);
+-      emit_insn (gen_add3_insn (this_rtx, this_rtx, scratch_rtx));
+-    }
+-  else if (mdelta > 0)
+-    {
+-      if (mdelta >= 4096)
+-	{
+-	  emit_insn (gen_rtx_SET (scratch_rtx, GEN_INT (mdelta / 4096)));
+-	  rtx shift = gen_rtx_ASHIFT (Pmode, scratch_rtx, GEN_INT (12));
+-	  if (delta < 0)
+-	    emit_insn (gen_rtx_SET (this_rtx,
+-				    gen_rtx_MINUS (Pmode, this_rtx, shift)));
+-	  else
+-	    emit_insn (gen_rtx_SET (this_rtx,
+-				    gen_rtx_PLUS (Pmode, this_rtx, shift)));
+-	}
+-      if (mdelta % 4096 != 0)
+-	{
+-	  scratch_rtx = GEN_INT ((delta < 0 ? -1 : 1) * (mdelta % 4096));
+-	  emit_insn (gen_rtx_SET (this_rtx,
+-				  gen_rtx_PLUS (Pmode, this_rtx, scratch_rtx)));
+-	}
+-    }
+-}
+-
+ /* Output code to add DELTA to the first argument, and then jump
+    to FUNCTION.  Used for C++ multiple inheritance.  */
+ static void
+@@ -3366,7 +3495,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+   emit_note (NOTE_INSN_PROLOGUE_END);
+ 
+   if (vcall_offset == 0)
+-    aarch64_add_constant (this_regno, IP1_REGNUM, delta);
++    aarch64_add_constant (Pmode, this_regno, IP1_REGNUM, delta);
+   else
+     {
+       gcc_assert ((vcall_offset & (POINTER_BYTES - 1)) == 0);
+@@ -3382,7 +3511,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+ 	    addr = gen_rtx_PRE_MODIFY (Pmode, this_rtx,
+ 				       plus_constant (Pmode, this_rtx, delta));
+ 	  else
+-	    aarch64_add_constant (this_regno, IP1_REGNUM, delta);
++	    aarch64_add_constant (Pmode, this_regno, IP1_REGNUM, delta);
+ 	}
+ 
+       if (Pmode == ptr_mode)
+@@ -3396,7 +3525,8 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+ 	  addr = plus_constant (Pmode, temp0, vcall_offset);
+       else
+ 	{
+-	  (void) aarch64_build_constant (IP1_REGNUM, vcall_offset, true);
++	  aarch64_internal_mov_immediate (temp1, GEN_INT (vcall_offset), true,
++					  Pmode);
+ 	  addr = gen_rtx_PLUS (Pmode, temp0, temp1);
+ 	}
+ 
+@@ -3575,7 +3705,12 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
+   return aarch64_tls_referenced_p (x);
+ }
+ 
+-/* Implement TARGET_CASE_VALUES_THRESHOLD.  */
++/* Implement TARGET_CASE_VALUES_THRESHOLD.
++   The expansion for a table switch is quite expensive due to the number
++   of instructions, the table lookup and hard to predict indirect jump.
++   When optimizing for speed, and -O3 enabled, use the per-core tuning if 
++   set, otherwise use tables for > 16 cases as a tradeoff between size and
++   performance.  When optimizing for size, use the default setting.  */
+ 
+ static unsigned int
+ aarch64_case_values_threshold (void)
+@@ -3586,7 +3721,7 @@ aarch64_case_values_threshold (void)
+       && selected_cpu->tune->max_case_values != 0)
+     return selected_cpu->tune->max_case_values;
+   else
+-    return default_case_values_threshold ();
++    return optimize_size ? default_case_values_threshold () : 17;
+ }
+ 
+ /* Return true if register REGNO is a valid index register.
+@@ -3921,9 +4056,11 @@ aarch64_classify_address (struct aarch64_address_info *info,
+ 	     X,X: 7-bit signed scaled offset
+ 	     Q:   9-bit signed offset
+ 	     We conservatively require an offset representable in either mode.
+-	   */
++	     When performing the check for pairs of X registers i.e.  LDP/STP
++	     pass down DImode since that is the natural size of the LDP/STP
++	     instruction memory accesses.  */
+ 	  if (mode == TImode || mode == TFmode)
+-	    return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
++	    return (aarch64_offset_7bit_signed_scaled_p (DImode, offset)
+ 		    && offset_9bit_signed_unscaled_p (mode, offset));
+ 
+ 	  /* A 7bit offset check because OImode will emit a ldp/stp
+@@ -4031,7 +4168,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
+ 	  return ((GET_CODE (sym) == LABEL_REF
+ 		   || (GET_CODE (sym) == SYMBOL_REF
+ 		       && CONSTANT_POOL_ADDRESS_P (sym)
+-		       && !aarch64_nopcrelative_literal_loads)));
++		       && aarch64_pcrelative_literal_loads)));
+ 	}
+       return false;
+ 
+@@ -4125,6 +4262,24 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x,
+   return aarch64_classify_address (&addr, x, mode, outer_code, strict_p);
+ }
+ 
++/* Split an out-of-range address displacement into a base and offset.
++   Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
++   to increase opportunities for sharing the base address of different sizes.
++   For TI/TFmode and unaligned accesses use a 256-byte range.  */
++static bool
++aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode)
++{
++  HOST_WIDE_INT mask = GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3fff;
++
++  if (mode == TImode || mode == TFmode ||
++      (INTVAL (*disp) & (GET_MODE_SIZE (mode) - 1)) != 0)
++    mask = 0xff;
++
++  *off = GEN_INT (INTVAL (*disp) & ~mask);
++  *disp = GEN_INT (INTVAL (*disp) & mask);
++  return true;
++}
++
+ /* Return TRUE if rtx X is immediate constant 0.0 */
+ bool
+ aarch64_float_const_zero_rtx_p (rtx x)
+@@ -4198,6 +4353,14 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
+       && (GET_MODE (x) == HImode || GET_MODE (x) == QImode))
+     return CC_NZmode;
+ 
++  /* Similarly, comparisons of zero_extends from shorter modes can
++     be performed using an ANDS with an immediate mask.  */
++  if (y == const0_rtx && GET_CODE (x) == ZERO_EXTEND
++      && (GET_MODE (x) == SImode || GET_MODE (x) == DImode)
++      && (GET_MODE (XEXP (x, 0)) == HImode || GET_MODE (XEXP (x, 0)) == QImode)
++      && (code == EQ || code == NE))
++    return CC_NZmode;
++
+   if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
+       && y == const0_rtx
+       && (code == EQ || code == NE || code == LT || code == GE)
+@@ -4225,14 +4388,6 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
+       && GET_CODE (x) == NEG)
+     return CC_Zmode;
+ 
+-  /* A compare of a mode narrower than SI mode against zero can be done
+-     by extending the value in the comparison.  */
+-  if ((GET_MODE (x) == QImode || GET_MODE (x) == HImode)
+-      && y == const0_rtx)
+-    /* Only use sign-extension if we really need it.  */
+-    return ((code == GT || code == GE || code == LE || code == LT)
+-	    ? CC_SESWPmode : CC_ZESWPmode);
+-
+   /* A test for unsigned overflow.  */
+   if ((GET_MODE (x) == DImode || GET_MODE (x) == TImode)
+       && code == NE
+@@ -4301,8 +4456,6 @@ aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code)
+       break;
+ 
+     case CC_SWPmode:
+-    case CC_ZESWPmode:
+-    case CC_SESWPmode:
+       switch (comp_code)
+ 	{
+ 	case NE: return AARCH64_NE;
+@@ -4957,7 +5110,7 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x  */, machine_mode mode)
+   if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
+     {
+       rtx base = XEXP (x, 0);
+-      rtx offset_rtx XEXP (x, 1);
++      rtx offset_rtx = XEXP (x, 1);
+       HOST_WIDE_INT offset = INTVAL (offset_rtx);
+ 
+       if (GET_CODE (base) == PLUS)
+@@ -5015,120 +5168,6 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x  */, machine_mode mode)
+   return x;
+ }
+ 
+-/* Try a machine-dependent way of reloading an illegitimate address
+-   operand.  If we find one, push the reload and return the new rtx.  */
+-
+-rtx
+-aarch64_legitimize_reload_address (rtx *x_p,
+-				   machine_mode mode,
+-				   int opnum, int type,
+-				   int ind_levels ATTRIBUTE_UNUSED)
+-{
+-  rtx x = *x_p;
+-
+-  /* Do not allow mem (plus (reg, const)) if vector struct mode.  */
+-  if (aarch64_vect_struct_mode_p (mode)
+-      && GET_CODE (x) == PLUS
+-      && REG_P (XEXP (x, 0))
+-      && CONST_INT_P (XEXP (x, 1)))
+-    {
+-      rtx orig_rtx = x;
+-      x = copy_rtx (x);
+-      push_reload (orig_rtx, NULL_RTX, x_p, NULL,
+-		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
+-		   opnum, (enum reload_type) type);
+-      return x;
+-    }
+-
+-  /* We must recognize output that we have already generated ourselves.  */
+-  if (GET_CODE (x) == PLUS
+-      && GET_CODE (XEXP (x, 0)) == PLUS
+-      && REG_P (XEXP (XEXP (x, 0), 0))
+-      && CONST_INT_P (XEXP (XEXP (x, 0), 1))
+-      && CONST_INT_P (XEXP (x, 1)))
+-    {
+-      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+-		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
+-		   opnum, (enum reload_type) type);
+-      return x;
+-    }
+-
+-  /* We wish to handle large displacements off a base register by splitting
+-     the addend across an add and the mem insn.  This can cut the number of
+-     extra insns needed from 3 to 1.  It is only useful for load/store of a
+-     single register with 12 bit offset field.  */
+-  if (GET_CODE (x) == PLUS
+-      && REG_P (XEXP (x, 0))
+-      && CONST_INT_P (XEXP (x, 1))
+-      && HARD_REGISTER_P (XEXP (x, 0))
+-      && mode != TImode
+-      && mode != TFmode
+-      && aarch64_regno_ok_for_base_p (REGNO (XEXP (x, 0)), true))
+-    {
+-      HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
+-      HOST_WIDE_INT low = val & 0xfff;
+-      HOST_WIDE_INT high = val - low;
+-      HOST_WIDE_INT offs;
+-      rtx cst;
+-      machine_mode xmode = GET_MODE (x);
+-
+-      /* In ILP32, xmode can be either DImode or SImode.  */
+-      gcc_assert (xmode == DImode || xmode == SImode);
+-
+-      /* Reload non-zero BLKmode offsets.  This is because we cannot ascertain
+-	 BLKmode alignment.  */
+-      if (GET_MODE_SIZE (mode) == 0)
+-	return NULL_RTX;
+-
+-      offs = low % GET_MODE_SIZE (mode);
+-
+-      /* Align misaligned offset by adjusting high part to compensate.  */
+-      if (offs != 0)
+-	{
+-	  if (aarch64_uimm12_shift (high + offs))
+-	    {
+-	      /* Align down.  */
+-	      low = low - offs;
+-	      high = high + offs;
+-	    }
+-	  else
+-	    {
+-	      /* Align up.  */
+-	      offs = GET_MODE_SIZE (mode) - offs;
+-	      low = low + offs;
+-	      high = high + (low & 0x1000) - offs;
+-	      low &= 0xfff;
+-	    }
+-	}
+-
+-      /* Check for overflow.  */
+-      if (high + low != val)
+-	return NULL_RTX;
+-
+-      cst = GEN_INT (high);
+-      if (!aarch64_uimm12_shift (high))
+-	cst = force_const_mem (xmode, cst);
+-
+-      /* Reload high part into base reg, leaving the low part
+-	 in the mem instruction.
+-	 Note that replacing this gen_rtx_PLUS with plus_constant is
+-	 wrong in this case because we rely on the
+-	 (plus (plus reg c1) c2) structure being preserved so that
+-	 XEXP (*p, 0) in push_reload below uses the correct term.  */
+-      x = gen_rtx_PLUS (xmode,
+-			gen_rtx_PLUS (xmode, XEXP (x, 0), cst),
+-			GEN_INT (low));
+-
+-      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+-		   BASE_REG_CLASS, xmode, VOIDmode, 0, 0,
+-		   opnum, (enum reload_type) type);
+-      return x;
+-    }
+-
+-  return NULL_RTX;
+-}
+-
+-
+ /* Return the reload icode required for a constant pool in mode.  */
+ static enum insn_code
+ aarch64_constant_pool_reload_icode (machine_mode mode)
+@@ -5186,7 +5225,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
+   if (MEM_P (x) && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)
+       && (SCALAR_FLOAT_MODE_P (GET_MODE (x))
+ 	  || targetm.vector_mode_supported_p (GET_MODE (x)))
+-      && aarch64_nopcrelative_literal_loads)
++      && !aarch64_pcrelative_literal_loads)
+     {
+       sri->icode = aarch64_constant_pool_reload_icode (mode);
+       return NO_REGS;
+@@ -5260,18 +5299,18 @@ aarch64_initial_elimination_offset (unsigned from, unsigned to)
+   if (to == HARD_FRAME_POINTER_REGNUM)
+     {
+       if (from == ARG_POINTER_REGNUM)
+-	return cfun->machine->frame.frame_size - crtl->outgoing_args_size;
++	return cfun->machine->frame.hard_fp_offset;
+ 
+       if (from == FRAME_POINTER_REGNUM)
+-	return (cfun->machine->frame.hard_fp_offset
+-		- cfun->machine->frame.saved_varargs_size);
++	return cfun->machine->frame.hard_fp_offset
++	       - cfun->machine->frame.locals_offset;
+     }
+ 
+   if (to == STACK_POINTER_REGNUM)
+     {
+       if (from == FRAME_POINTER_REGNUM)
+-	  return (cfun->machine->frame.frame_size
+-		  - cfun->machine->frame.saved_varargs_size);
++	  return cfun->machine->frame.frame_size
++		 - cfun->machine->frame.locals_offset;
+     }
+ 
+   return cfun->machine->frame.frame_size;
+@@ -5418,7 +5457,10 @@ aarch64_elf_asm_constructor (rtx symbol, int priority)
+   else
+     {
+       section *s;
+-      char buf[18];
++      /* While priority is known to be in range [0, 65535], so 18 bytes
++         would be enough, the compiler might not know that.  To avoid
++         -Wformat-truncation false positive, use a larger size.  */
++      char buf[23];
+       snprintf (buf, sizeof (buf), ".init_array.%.5u", priority);
+       s = get_section (buf, SECTION_WRITE, NULL);
+       switch_to_section (s);
+@@ -5435,7 +5477,10 @@ aarch64_elf_asm_destructor (rtx symbol, int priority)
+   else
+     {
+       section *s;
+-      char buf[18];
++      /* While priority is known to be in range [0, 65535], so 18 bytes
++         would be enough, the compiler might not know that.  To avoid
++         -Wformat-truncation false positive, use a larger size.  */
++      char buf[23];
+       snprintf (buf, sizeof (buf), ".fini_array.%.5u", priority);
+       s = get_section (buf, SECTION_WRITE, NULL);
+       switch_to_section (s);
+@@ -5520,7 +5565,7 @@ aarch64_uxt_size (int shift, HOST_WIDE_INT mask)
+ static inline bool
+ aarch64_can_use_per_function_literal_pools_p (void)
+ {
+-  return (!aarch64_nopcrelative_literal_loads
++  return (aarch64_pcrelative_literal_loads
+ 	  || aarch64_cmodel == AARCH64_CMODEL_LARGE);
+ }
+ 
+@@ -6139,6 +6184,19 @@ aarch64_extend_bitfield_pattern_p (rtx x)
+   return op;
+ }
+ 
++/* Return true if the mask and a shift amount from an RTX of the form
++   (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
++   mode MODE.  See the *andim_ashift<mode>_bfiz pattern.  */
++
++bool
++aarch64_mask_and_shift_for_ubfiz_p (machine_mode mode, rtx mask, rtx shft_amnt)
++{
++  return CONST_INT_P (mask) && CONST_INT_P (shft_amnt)
++	 && INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode)
++	 && exact_log2 ((INTVAL (mask) >> INTVAL (shft_amnt)) + 1) >= 0
++	 && (INTVAL (mask) & ((1 << INTVAL (shft_amnt)) - 1)) == 0;
++}
++
+ /* Calculate the cost of calculating X, storing it in *COST.  Result
+    is true if the total cost of the operation has now been calculated.  */
+ static bool
+@@ -6404,10 +6462,6 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
+           /* TODO: A write to the CC flags possibly costs extra, this
+ 	     needs encoding in the cost tables.  */
+ 
+-          /* CC_ZESWPmode supports zero extend for free.  */
+-          if (mode == CC_ZESWPmode && GET_CODE (op0) == ZERO_EXTEND)
+-            op0 = XEXP (op0, 0);
+-
+ 	  mode = GET_MODE (op0);
+           /* ANDS.  */
+           if (GET_CODE (op0) == AND)
+@@ -6717,17 +6771,31 @@ cost_plus:
+ 
+       if (GET_MODE_CLASS (mode) == MODE_INT)
+ 	{
+-	  /* We possibly get the immediate for free, this is not
+-	     modelled.  */
+-	  if (CONST_INT_P (op1)
+-	      && aarch64_bitmask_imm (INTVAL (op1), mode))
++	  if (CONST_INT_P (op1))
+ 	    {
+-	      *cost += rtx_cost (op0, mode, (enum rtx_code) code, 0, speed);
++	      /* We have a mask + shift version of a UBFIZ
++		 i.e. the *andim_ashift<mode>_bfiz pattern.  */
++	      if (GET_CODE (op0) == ASHIFT
++		  && aarch64_mask_and_shift_for_ubfiz_p (mode, op1,
++							  XEXP (op0, 1)))
++		{
++		  *cost += rtx_cost (XEXP (op0, 0), mode,
++				     (enum rtx_code) code, 0, speed);
++		  if (speed)
++		    *cost += extra_cost->alu.bfx;
+ 
+-	      if (speed)
+-		*cost += extra_cost->alu.logical;
++		  return true;
++		}
++	      else if (aarch64_bitmask_imm (INTVAL (op1), mode))
++		{
++		/* We possibly get the immediate for free, this is not
++		   modelled.  */
++		  *cost += rtx_cost (op0, mode, (enum rtx_code) code, 0, speed);
++		  if (speed)
++		    *cost += extra_cost->alu.logical;
+ 
+-	      return true;
++		  return true;
++		}
+ 	    }
+ 	  else
+ 	    {
+@@ -6831,11 +6899,12 @@ cost_plus:
+ 	{
+ 	  int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
+ 
+-	  if (!op_cost && speed)
+-	    /* MOV.  */
+-	    *cost += extra_cost->alu.extend;
+-	  else
+-	    /* Free, the cost is that of the SI mode operation.  */
++	/* If OP_COST is non-zero, then the cost of the zero extend
++	   is effectively the cost of the inner operation.  Otherwise
++	   we have a MOV instruction and we take the cost from the MOV
++	   itself.  This is true independently of whether we are
++	   optimizing for space or time.  */
++	  if (op_cost)
+ 	    *cost = op_cost;
+ 
+ 	  return true;
+@@ -6865,8 +6934,8 @@ cost_plus:
+ 	    }
+ 	  else
+ 	    {
+-	      /* UXTB/UXTH.  */
+-	      *cost += extra_cost->alu.extend;
++	      /* We generate an AND instead of UXTB/UXTH.  */
++	      *cost += extra_cost->alu.logical;
+ 	    }
+ 	}
+       return false;
+@@ -7445,12 +7514,12 @@ aarch64_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
+    to optimize 1.0/sqrt.  */
+ 
+ static bool
+-use_rsqrt_p (void)
++use_rsqrt_p (machine_mode mode)
+ {
+   return (!flag_trapping_math
+ 	  && flag_unsafe_math_optimizations
+-	  && ((aarch64_tune_params.extra_tuning_flags
+-	       & AARCH64_EXTRA_TUNE_APPROX_RSQRT)
++	  && ((aarch64_tune_params.approx_modes->recip_sqrt
++	       & AARCH64_APPROX_MODE (mode))
+ 	      || flag_mrecip_low_precision_sqrt));
+ }
+ 
+@@ -7460,89 +7529,225 @@ use_rsqrt_p (void)
+ static tree
+ aarch64_builtin_reciprocal (tree fndecl)
+ {
+-  if (!use_rsqrt_p ())
++  machine_mode mode = TYPE_MODE (TREE_TYPE (fndecl));
++
++  if (!use_rsqrt_p (mode))
+     return NULL_TREE;
+   return aarch64_builtin_rsqrt (DECL_FUNCTION_CODE (fndecl));
+ }
+ 
+ typedef rtx (*rsqrte_type) (rtx, rtx);
+ 
+-/* Select reciprocal square root initial estimate
+-   insn depending on machine mode.  */
++/* Select reciprocal square root initial estimate insn depending on machine
++   mode.  */
+ 
+-rsqrte_type
++static rsqrte_type
+ get_rsqrte_type (machine_mode mode)
+ {
+   switch (mode)
+   {
+-    case DFmode:   return gen_aarch64_rsqrte_df2;
+-    case SFmode:   return gen_aarch64_rsqrte_sf2;
+-    case V2DFmode: return gen_aarch64_rsqrte_v2df2;
+-    case V2SFmode: return gen_aarch64_rsqrte_v2sf2;
+-    case V4SFmode: return gen_aarch64_rsqrte_v4sf2;
++    case DFmode:   return gen_aarch64_rsqrtedf;
++    case SFmode:   return gen_aarch64_rsqrtesf;
++    case V2DFmode: return gen_aarch64_rsqrtev2df;
++    case V2SFmode: return gen_aarch64_rsqrtev2sf;
++    case V4SFmode: return gen_aarch64_rsqrtev4sf;
+     default: gcc_unreachable ();
+   }
+ }
+ 
+ typedef rtx (*rsqrts_type) (rtx, rtx, rtx);
+ 
+-/* Select reciprocal square root Newton-Raphson step
+-   insn depending on machine mode.  */
++/* Select reciprocal square root series step insn depending on machine mode.  */
+ 
+-rsqrts_type
++static rsqrts_type
+ get_rsqrts_type (machine_mode mode)
+ {
+   switch (mode)
+   {
+-    case DFmode:   return gen_aarch64_rsqrts_df3;
+-    case SFmode:   return gen_aarch64_rsqrts_sf3;
+-    case V2DFmode: return gen_aarch64_rsqrts_v2df3;
+-    case V2SFmode: return gen_aarch64_rsqrts_v2sf3;
+-    case V4SFmode: return gen_aarch64_rsqrts_v4sf3;
++    case DFmode:   return gen_aarch64_rsqrtsdf;
++    case SFmode:   return gen_aarch64_rsqrtssf;
++    case V2DFmode: return gen_aarch64_rsqrtsv2df;
++    case V2SFmode: return gen_aarch64_rsqrtsv2sf;
++    case V4SFmode: return gen_aarch64_rsqrtsv4sf;
+     default: gcc_unreachable ();
+   }
+ }
+ 
+-/* Emit instruction sequence to compute the reciprocal square root using the
+-   Newton-Raphson series.  Iterate over the series twice for SF
+-   and thrice for DF.  */
++/* Emit instruction sequence to compute either the approximate square root
++   or its approximate reciprocal, depending on the flag RECP, and return
++   whether the sequence was emitted or not.  */
+ 
+-void
+-aarch64_emit_approx_rsqrt (rtx dst, rtx src)
++bool
++aarch64_emit_approx_sqrt (rtx dst, rtx src, bool recp)
+ {
+-  machine_mode mode = GET_MODE (src);
+-  gcc_assert (
+-    mode == SFmode || mode == V2SFmode || mode == V4SFmode
+-	|| mode == DFmode || mode == V2DFmode);
++  machine_mode mode = GET_MODE (dst);
+ 
+-  rtx xsrc = gen_reg_rtx (mode);
+-  emit_move_insn (xsrc, src);
+-  rtx x0 = gen_reg_rtx (mode);
++  if (GET_MODE_INNER (mode) == HFmode)
++    return false;
++
++  machine_mode mmsk = mode_for_vector
++		        (int_mode_for_mode (GET_MODE_INNER (mode)),
++			 GET_MODE_NUNITS (mode));
++  bool use_approx_sqrt_p = (!recp
++			    && (flag_mlow_precision_sqrt
++			        || (aarch64_tune_params.approx_modes->sqrt
++				    & AARCH64_APPROX_MODE (mode))));
++  bool use_approx_rsqrt_p = (recp
++			     && (flag_mrecip_low_precision_sqrt
++				 || (aarch64_tune_params.approx_modes->recip_sqrt
++				     & AARCH64_APPROX_MODE (mode))));
++
++  if (!flag_finite_math_only
++      || flag_trapping_math
++      || !flag_unsafe_math_optimizations
++      || !(use_approx_sqrt_p || use_approx_rsqrt_p)
++      || optimize_function_for_size_p (cfun))
++    return false;
+ 
+-  emit_insn ((*get_rsqrte_type (mode)) (x0, xsrc));
++  rtx xmsk = gen_reg_rtx (mmsk);
++  if (!recp)
++    /* When calculating the approximate square root, compare the argument with
++       0.0 and create a mask.  */
++    emit_insn (gen_rtx_SET (xmsk, gen_rtx_NEG (mmsk, gen_rtx_EQ (mmsk, src,
++							  CONST0_RTX (mode)))));
+ 
+-  bool double_mode = (mode == DFmode || mode == V2DFmode);
++  /* Estimate the approximate reciprocal square root.  */
++  rtx xdst = gen_reg_rtx (mode);
++  emit_insn ((*get_rsqrte_type (mode)) (xdst, src));
+ 
+-  int iterations = double_mode ? 3 : 2;
++  /* Iterate over the series twice for SF and thrice for DF.  */
++  int iterations = (GET_MODE_INNER (mode) == DFmode) ? 3 : 2;
+ 
+-  /* Optionally iterate over the series one less time than otherwise.  */
+-  if (flag_mrecip_low_precision_sqrt)
++  /* Optionally iterate over the series once less for faster performance
++     while sacrificing the accuracy.  */
++  if ((recp && flag_mrecip_low_precision_sqrt)
++      || (!recp && flag_mlow_precision_sqrt))
+     iterations--;
+ 
+-  for (int i = 0; i < iterations; ++i)
++  /* Iterate over the series to calculate the approximate reciprocal square
++     root.  */
++  rtx x1 = gen_reg_rtx (mode);
++  while (iterations--)
+     {
+-      rtx x1 = gen_reg_rtx (mode);
+       rtx x2 = gen_reg_rtx (mode);
+-      rtx x3 = gen_reg_rtx (mode);
+-      emit_set_insn (x2, gen_rtx_MULT (mode, x0, x0));
++      emit_set_insn (x2, gen_rtx_MULT (mode, xdst, xdst));
++
++      emit_insn ((*get_rsqrts_type (mode)) (x1, src, x2));
++
++      if (iterations > 0)
++	emit_set_insn (xdst, gen_rtx_MULT (mode, xdst, x1));
++    }
++
++  if (!recp)
++    {
++      /* Qualify the approximate reciprocal square root when the argument is
++	 0.0 by squashing the intermediary result to 0.0.  */
++      rtx xtmp = gen_reg_rtx (mmsk);
++      emit_set_insn (xtmp, gen_rtx_AND (mmsk, gen_rtx_NOT (mmsk, xmsk),
++					      gen_rtx_SUBREG (mmsk, xdst, 0)));
++      emit_move_insn (xdst, gen_rtx_SUBREG (mode, xtmp, 0));
++
++      /* Calculate the approximate square root.  */
++      emit_set_insn (xdst, gen_rtx_MULT (mode, xdst, src));
++    }
++
++  /* Finalize the approximation.  */
++  emit_set_insn (dst, gen_rtx_MULT (mode, xdst, x1));
++
++  return true;
++}
++
++typedef rtx (*recpe_type) (rtx, rtx);
++
++/* Select reciprocal initial estimate insn depending on machine mode.  */
++
++static recpe_type
++get_recpe_type (machine_mode mode)
++{
++  switch (mode)
++  {
++    case SFmode:   return (gen_aarch64_frecpesf);
++    case V2SFmode: return (gen_aarch64_frecpev2sf);
++    case V4SFmode: return (gen_aarch64_frecpev4sf);
++    case DFmode:   return (gen_aarch64_frecpedf);
++    case V2DFmode: return (gen_aarch64_frecpev2df);
++    default:       gcc_unreachable ();
++  }
++}
++
++typedef rtx (*recps_type) (rtx, rtx, rtx);
++
++/* Select reciprocal series step insn depending on machine mode.  */
++
++static recps_type
++get_recps_type (machine_mode mode)
++{
++  switch (mode)
++  {
++    case SFmode:   return (gen_aarch64_frecpssf);
++    case V2SFmode: return (gen_aarch64_frecpsv2sf);
++    case V4SFmode: return (gen_aarch64_frecpsv4sf);
++    case DFmode:   return (gen_aarch64_frecpsdf);
++    case V2DFmode: return (gen_aarch64_frecpsv2df);
++    default:       gcc_unreachable ();
++  }
++}
++
++/* Emit the instruction sequence to compute the approximation for the division
++   of NUM by DEN in QUO and return whether the sequence was emitted or not.  */
++
++bool
++aarch64_emit_approx_div (rtx quo, rtx num, rtx den)
++{
++  machine_mode mode = GET_MODE (quo);
++
++  if (GET_MODE_INNER (mode) == HFmode)
++    return false;
++
++  bool use_approx_division_p = (flag_mlow_precision_div
++			        || (aarch64_tune_params.approx_modes->division
++				    & AARCH64_APPROX_MODE (mode)));
++
++  if (!flag_finite_math_only
++      || flag_trapping_math
++      || !flag_unsafe_math_optimizations
++      || optimize_function_for_size_p (cfun)
++      || !use_approx_division_p)
++    return false;
++
++  /* Estimate the approximate reciprocal.  */
++  rtx xrcp = gen_reg_rtx (mode);
++  emit_insn ((*get_recpe_type (mode)) (xrcp, den));
+ 
+-      emit_insn ((*get_rsqrts_type (mode)) (x3, xsrc, x2));
++  /* Iterate over the series twice for SF and thrice for DF.  */
++  int iterations = (GET_MODE_INNER (mode) == DFmode) ? 3 : 2;
+ 
+-      emit_set_insn (x1, gen_rtx_MULT (mode, x0, x3));
+-      x0 = x1;
++  /* Optionally iterate over the series once less for faster performance,
++     while sacrificing the accuracy.  */
++  if (flag_mlow_precision_div)
++    iterations--;
++
++  /* Iterate over the series to calculate the approximate reciprocal.  */
++  rtx xtmp = gen_reg_rtx (mode);
++  while (iterations--)
++    {
++      emit_insn ((*get_recps_type (mode)) (xtmp, xrcp, den));
++
++      if (iterations > 0)
++	emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xtmp));
+     }
+ 
+-  emit_move_insn (dst, x0);
++  if (num != CONST1_RTX (mode))
++    {
++      /* As the approximate reciprocal of DEN is already calculated, only
++	 calculate the approximate division when NUM is not 1.0.  */
++      rtx xnum = force_reg (mode, num);
++      emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xnum));
++    }
++
++  /* Finalize the approximation.  */
++  emit_set_insn (quo, gen_rtx_MULT (mode, xrcp, xtmp));
++  return true;
+ }
+ 
+ /* Return the number of instructions that can be issued per cycle.  */
+@@ -8046,32 +8251,37 @@ aarch64_override_options_after_change_1 (struct gcc_options *opts)
+ 	opts->x_align_functions = aarch64_tune_params.function_align;
+     }
+ 
+-  /* If nopcrelative_literal_loads is set on the command line, this
++  /* We default to no pc-relative literal loads.  */
++
++  aarch64_pcrelative_literal_loads = false;
++
++  /* If -mpc-relative-literal-loads is set on the command line, this
+      implies that the user asked for PC relative literal loads.  */
+-  if (opts->x_nopcrelative_literal_loads == 1)
+-    aarch64_nopcrelative_literal_loads = false;
++  if (opts->x_pcrelative_literal_loads == 1)
++    aarch64_pcrelative_literal_loads = true;
+ 
+-  /* If it is not set on the command line, we default to no pc
+-     relative literal loads, unless the workaround for Cortex-A53
+-     erratum 843419 is in effect.  */
+   /* This is PR70113. When building the Linux kernel with
+      CONFIG_ARM64_ERRATUM_843419, support for relocations
+      R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
+      removed from the kernel to avoid loading objects with possibly
+-     offending sequences. With nopcrelative_literal_loads, we would
++     offending sequences.  Without -mpc-relative-literal-loads we would
+      generate such relocations, preventing the kernel build from
+      succeeding.  */
+-  if (opts->x_nopcrelative_literal_loads == 2
+-      && !TARGET_FIX_ERR_A53_843419)
+-    aarch64_nopcrelative_literal_loads = true;
++  if (opts->x_pcrelative_literal_loads == 2
++      && TARGET_FIX_ERR_A53_843419)
++    aarch64_pcrelative_literal_loads = true;
+ 
+-  /* In the tiny memory model it makes no sense
+-     to disallow non PC relative literal pool loads
+-     as many other things will break anyway.  */
+-  if (opts->x_nopcrelative_literal_loads
+-      && (aarch64_cmodel == AARCH64_CMODEL_TINY
+-	  || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC))
+-    aarch64_nopcrelative_literal_loads = false;
++  /* In the tiny memory model it makes no sense to disallow PC relative
++     literal pool loads.  */
++  if (aarch64_cmodel == AARCH64_CMODEL_TINY
++      || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
++    aarch64_pcrelative_literal_loads = true;
++
++  /* When enabling the lower precision Newton series for the square root, also
++     enable it for the reciprocal square root, since the latter is an
++     intermediary step for the former.  */
++  if (flag_mlow_precision_sqrt)
++    flag_mrecip_low_precision_sqrt = true;
+ }
+ 
+ /* 'Unpack' up the internal tuning structs and update the options
+@@ -9279,15 +9489,18 @@ aarch64_classify_symbol (rtx x, rtx offset)
+       switch (aarch64_cmodel)
+ 	{
+ 	case AARCH64_CMODEL_TINY:
+-	  /* When we retreive symbol + offset address, we have to make sure
++	  /* When we retrieve symbol + offset address, we have to make sure
+ 	     the offset does not cause overflow of the final address.  But
+ 	     we have no way of knowing the address of symbol at compile time
+ 	     so we can't accurately say if the distance between the PC and
+ 	     symbol + offset is outside the addressible range of +/-1M in the
+ 	     TINY code model.  So we rely on images not being greater than
+ 	     1M and cap the offset at 1M and anything beyond 1M will have to
+-	     be loaded using an alternative mechanism.  */
+-	  if (SYMBOL_REF_WEAK (x)
++	     be loaded using an alternative mechanism.  Furthermore if the
++	     symbol is a weak reference to something that isn't known to
++	     resolve to a symbol in this module, then force to memory.  */
++	  if ((SYMBOL_REF_WEAK (x)
++	       && !aarch64_symbol_binds_local_p (x))
+ 	      || INTVAL (offset) < -1048575 || INTVAL (offset) > 1048575)
+ 	    return SYMBOL_FORCE_TO_MEM;
+ 	  return SYMBOL_TINY_ABSOLUTE;
+@@ -9295,7 +9508,8 @@ aarch64_classify_symbol (rtx x, rtx offset)
+ 	case AARCH64_CMODEL_SMALL:
+ 	  /* Same reasoning as the tiny code model, but the offset cap here is
+ 	     4G.  */
+-	  if (SYMBOL_REF_WEAK (x)
++	  if ((SYMBOL_REF_WEAK (x)
++	       && !aarch64_symbol_binds_local_p (x))
+ 	      || !IN_RANGE (INTVAL (offset), HOST_WIDE_INT_C (-4294967263),
+ 			    HOST_WIDE_INT_C (4294967264)))
+ 	    return SYMBOL_FORCE_TO_MEM;
+@@ -9317,8 +9531,7 @@ aarch64_classify_symbol (rtx x, rtx offset)
+ 	  /* This is alright even in PIC code as the constant
+ 	     pool reference is always PC relative and within
+ 	     the same translation unit.  */
+-	  if (nopcrelative_literal_loads
+-	      && CONSTANT_POOL_ADDRESS_P (x))
++	  if (CONSTANT_POOL_ADDRESS_P (x))
+ 	    return SYMBOL_SMALL_ABSOLUTE;
+ 	  else
+ 	    return SYMBOL_FORCE_TO_MEM;
+@@ -9454,6 +9667,13 @@ aarch64_build_builtin_va_list (void)
+ 			FIELD_DECL, get_identifier ("__vr_offs"),
+ 			integer_type_node);
+ 
++  /* Tell tree-stdarg pass about our internal offset fields.
++     NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
++     purpose to identify whether the code is updating va_list internal
++     offset fields through irregular way.  */
++  va_list_gpr_counter_field = f_groff;
++  va_list_fpr_counter_field = f_vroff;
++
+   DECL_ARTIFICIAL (f_stack) = 1;
+   DECL_ARTIFICIAL (f_grtop) = 1;
+   DECL_ARTIFICIAL (f_vrtop) = 1;
+@@ -9486,15 +9706,17 @@ aarch64_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
+   tree f_stack, f_grtop, f_vrtop, f_groff, f_vroff;
+   tree stack, grtop, vrtop, groff, vroff;
+   tree t;
+-  int gr_save_area_size;
+-  int vr_save_area_size;
++  int gr_save_area_size = cfun->va_list_gpr_size;
++  int vr_save_area_size = cfun->va_list_fpr_size;
+   int vr_offset;
+ 
+   cum = &crtl->args.info;
+-  gr_save_area_size
+-    = (NUM_ARG_REGS - cum->aapcs_ncrn) * UNITS_PER_WORD;
+-  vr_save_area_size
+-    = (NUM_FP_ARG_REGS - cum->aapcs_nvrn) * UNITS_PER_VREG;
++  if (cfun->va_list_gpr_size)
++    gr_save_area_size = MIN ((NUM_ARG_REGS - cum->aapcs_ncrn) * UNITS_PER_WORD,
++			     cfun->va_list_gpr_size);
++  if (cfun->va_list_fpr_size)
++    vr_save_area_size = MIN ((NUM_FP_ARG_REGS - cum->aapcs_nvrn)
++			     * UNITS_PER_VREG, cfun->va_list_fpr_size);
+ 
+   if (!TARGET_FLOAT)
+     {
+@@ -9823,7 +10045,8 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+ {
+   CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
+   CUMULATIVE_ARGS local_cum;
+-  int gr_saved, vr_saved;
++  int gr_saved = cfun->va_list_gpr_size;
++  int vr_saved = cfun->va_list_fpr_size;
+ 
+   /* The caller has advanced CUM up to, but not beyond, the last named
+      argument.  Advance a local copy of CUM past the last "real" named
+@@ -9831,9 +10054,14 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+   local_cum = *cum;
+   aarch64_function_arg_advance (pack_cumulative_args(&local_cum), mode, type, true);
+ 
+-  /* Found out how many registers we need to save.  */
+-  gr_saved = NUM_ARG_REGS - local_cum.aapcs_ncrn;
+-  vr_saved = NUM_FP_ARG_REGS - local_cum.aapcs_nvrn;
++  /* Found out how many registers we need to save.
++     Honor tree-stdvar analysis results.  */
++  if (cfun->va_list_gpr_size)
++    gr_saved = MIN (NUM_ARG_REGS - local_cum.aapcs_ncrn,
++		    cfun->va_list_gpr_size / UNITS_PER_WORD);
++  if (cfun->va_list_fpr_size)
++    vr_saved = MIN (NUM_FP_ARG_REGS - local_cum.aapcs_nvrn,
++		    cfun->va_list_fpr_size / UNITS_PER_VREG);
+ 
+   if (!TARGET_FLOAT)
+     {
+@@ -9861,7 +10089,7 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+ 	  /* We can't use move_block_from_reg, because it will use
+ 	     the wrong mode, storing D regs only.  */
+ 	  machine_mode mode = TImode;
+-	  int off, i;
++	  int off, i, vr_start;
+ 
+ 	  /* Set OFF to the offset from virtual_incoming_args_rtx of
+ 	     the first vector register.  The VR save area lies below
+@@ -9870,14 +10098,15 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+ 			   STACK_BOUNDARY / BITS_PER_UNIT);
+ 	  off -= vr_saved * UNITS_PER_VREG;
+ 
+-	  for (i = local_cum.aapcs_nvrn; i < NUM_FP_ARG_REGS; ++i)
++	  vr_start = V0_REGNUM + local_cum.aapcs_nvrn;
++	  for (i = 0; i < vr_saved; ++i)
+ 	    {
+ 	      rtx ptr, mem;
+ 
+ 	      ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
+ 	      mem = gen_frame_mem (mode, ptr);
+ 	      set_mem_alias_set (mem, get_varargs_alias_set ());
+-	      aarch64_emit_move (mem, gen_rtx_REG (mode, V0_REGNUM + i));
++	      aarch64_emit_move (mem, gen_rtx_REG (mode, vr_start + i));
+ 	      off += UNITS_PER_VREG;
+ 	    }
+ 	}
+@@ -10839,33 +11068,6 @@ aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode,
+ 		      gen_rtx_REG (mode, rsrc + count - i - 1));
+ }
+ 
+-/* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
+-   one of VSTRUCT modes: OI, CI or XI.  */
+-int
+-aarch64_simd_attr_length_move (rtx_insn *insn)
+-{
+-  machine_mode mode;
+-
+-  extract_insn_cached (insn);
+-
+-  if (REG_P (recog_data.operand[0]) && REG_P (recog_data.operand[1]))
+-    {
+-      mode = GET_MODE (recog_data.operand[0]);
+-      switch (mode)
+-	{
+-	case OImode:
+-	  return 8;
+-	case CImode:
+-	  return 12;
+-	case XImode:
+-	  return 16;
+-	default:
+-	  gcc_unreachable ();
+-	}
+-    }
+-  return 4;
+-}
+-
+ /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
+    one of VSTRUCT modes: OI, CI, or XI.  */
+ int
+@@ -11947,12 +12149,11 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
+         info.value = GEN_INT (0);
+       else
+ 	{
+-#define buf_size 20
++	  const unsigned int buf_size = 20;
+ 	  char float_buf[buf_size] = {'\0'};
+ 	  real_to_decimal_for_mode (float_buf,
+ 				    CONST_DOUBLE_REAL_VALUE (info.value),
+ 				    buf_size, buf_size, 1, mode);
+-#undef buf_size
+ 
+ 	  if (lane_count == 1)
+ 	    snprintf (templ, sizeof (templ), "fmov\t%%d0, %s", float_buf);
+@@ -12186,6 +12387,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_trn2v4si; break;
+ 	case V2SImode: gen = gen_aarch64_trn2v2si; break;
+ 	case V2DImode: gen = gen_aarch64_trn2v2di; break;
++	case V4HFmode: gen = gen_aarch64_trn2v4hf; break;
++	case V8HFmode: gen = gen_aarch64_trn2v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_trn2v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_trn2v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_trn2v2df; break;
+@@ -12204,6 +12407,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_trn1v4si; break;
+ 	case V2SImode: gen = gen_aarch64_trn1v2si; break;
+ 	case V2DImode: gen = gen_aarch64_trn1v2di; break;
++	case V4HFmode: gen = gen_aarch64_trn1v4hf; break;
++	case V8HFmode: gen = gen_aarch64_trn1v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_trn1v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_trn1v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_trn1v2df; break;
+@@ -12269,6 +12474,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_uzp2v4si; break;
+ 	case V2SImode: gen = gen_aarch64_uzp2v2si; break;
+ 	case V2DImode: gen = gen_aarch64_uzp2v2di; break;
++	case V4HFmode: gen = gen_aarch64_uzp2v4hf; break;
++	case V8HFmode: gen = gen_aarch64_uzp2v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_uzp2v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_uzp2v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_uzp2v2df; break;
+@@ -12287,6 +12494,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_uzp1v4si; break;
+ 	case V2SImode: gen = gen_aarch64_uzp1v2si; break;
+ 	case V2DImode: gen = gen_aarch64_uzp1v2di; break;
++	case V4HFmode: gen = gen_aarch64_uzp1v4hf; break;
++	case V8HFmode: gen = gen_aarch64_uzp1v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_uzp1v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_uzp1v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_uzp1v2df; break;
+@@ -12357,6 +12566,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_zip2v4si; break;
+ 	case V2SImode: gen = gen_aarch64_zip2v2si; break;
+ 	case V2DImode: gen = gen_aarch64_zip2v2di; break;
++	case V4HFmode: gen = gen_aarch64_zip2v4hf; break;
++	case V8HFmode: gen = gen_aarch64_zip2v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_zip2v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_zip2v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_zip2v2df; break;
+@@ -12375,6 +12586,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_zip1v4si; break;
+ 	case V2SImode: gen = gen_aarch64_zip1v2si; break;
+ 	case V2DImode: gen = gen_aarch64_zip1v2di; break;
++	case V4HFmode: gen = gen_aarch64_zip1v4hf; break;
++	case V8HFmode: gen = gen_aarch64_zip1v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_zip1v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_zip1v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_zip1v2df; break;
+@@ -12419,6 +12632,8 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d)
+     case V8HImode: gen = gen_aarch64_extv8hi; break;
+     case V2SImode: gen = gen_aarch64_extv2si; break;
+     case V4SImode: gen = gen_aarch64_extv4si; break;
++    case V4HFmode: gen = gen_aarch64_extv4hf; break;
++    case V8HFmode: gen = gen_aarch64_extv8hf; break;
+     case V2SFmode: gen = gen_aarch64_extv2sf; break;
+     case V4SFmode: gen = gen_aarch64_extv4sf; break;
+     case V2DImode: gen = gen_aarch64_extv2di; break;
+@@ -12494,6 +12709,8 @@ aarch64_evpc_rev (struct expand_vec_perm_d *d)
+ 	case V2SImode: gen = gen_aarch64_rev64v2si;  break;
+ 	case V4SFmode: gen = gen_aarch64_rev64v4sf;  break;
+ 	case V2SFmode: gen = gen_aarch64_rev64v2sf;  break;
++	case V8HFmode: gen = gen_aarch64_rev64v8hf;  break;
++	case V4HFmode: gen = gen_aarch64_rev64v4hf;  break;
+ 	default:
+ 	  return false;
+ 	}
+@@ -12737,24 +12954,6 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
+   return ret;
+ }
+ 
+-/* Implement target hook CANNOT_CHANGE_MODE_CLASS.  */
+-bool
+-aarch64_cannot_change_mode_class (machine_mode from,
+-				  machine_mode to,
+-				  enum reg_class rclass)
+-{
+-  /* We cannot allow word_mode subregs of full vector modes.
+-     Otherwise the middle-end will assume it's ok to store to
+-     (subreg:DI (reg:TI 100) 0) in order to modify only the low 64 bits
+-     of the 128-bit register.  However, after reload the subreg will
+-     be dropped leaving a plain DImode store.  See PR67609 for a more
+-     detailed dicussion.  In all other cases, we want to be permissive
+-     and return false.  */
+-  return (reg_classes_intersect_p (FP_REGS, rclass)
+-	  && GET_MODE_SIZE (to) == UNITS_PER_WORD
+-	  && GET_MODE_SIZE (from) > UNITS_PER_WORD);
+-}
+-
+ rtx
+ aarch64_reverse_mask (enum machine_mode mode)
+ {
+@@ -12776,7 +12975,14 @@ aarch64_reverse_mask (enum machine_mode mode)
+   return force_reg (V16QImode, mask);
+ }
+ 
+-/* Implement MODES_TIEABLE_P.  */
++/* Implement MODES_TIEABLE_P.  In principle we should always return true.
++   However due to issues with register allocation it is preferable to avoid
++   tieing integer scalar and FP scalar modes.  Executing integer operations
++   in general registers is better than treating them as scalar vector
++   operations.  This reduces latency and avoids redundant int<->FP moves.
++   So tie modes if they are either the same class, or vector modes with
++   other vector modes, vector structs or any scalar mode.
++*/
+ 
+ bool
+ aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
+@@ -12787,9 +12993,12 @@ aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
+   /* We specifically want to allow elements of "structure" modes to
+      be tieable to the structure.  This more general condition allows
+      other rarer situations too.  */
+-  if (TARGET_SIMD
+-      && aarch64_vector_mode_p (mode1)
+-      && aarch64_vector_mode_p (mode2))
++  if (aarch64_vector_mode_p (mode1) && aarch64_vector_mode_p (mode2))
++    return true;
++
++  /* Also allow any scalar modes with vectors.  */
++  if (aarch64_vector_mode_supported_p (mode1)
++      || aarch64_vector_mode_supported_p (mode2))
+     return true;
+ 
+   return false;
+@@ -13305,6 +13514,14 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
+   return false;
+ }
+ 
++/* Return true iff the instruction fusion described by OP is enabled.  */
++
++bool
++aarch64_fusion_enabled_p (enum aarch64_fusion_pairs op)
++{
++  return (aarch64_tune_params.fusible_ops & op) != 0;
++}
++
+ /* If MEM is in the form of [base+offset], extract the two parts
+    of address and set to BASE and OFFSET, otherwise return false
+    after clearing BASE and OFFSET.  */
+@@ -13449,6 +13666,26 @@ aarch64_sched_fusion_priority (rtx_insn *insn, int max_pri,
+   return;
+ }
+ 
++/* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
++   Adjust priority of sha1h instructions so they are scheduled before
++   other SHA1 instructions.  */
++
++static int
++aarch64_sched_adjust_priority (rtx_insn *insn, int priority)
++{
++  rtx x = PATTERN (insn);
++
++  if (GET_CODE (x) == SET)
++    {
++      x = SET_SRC (x);
++
++      if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SHA1H)
++	return priority + 10;
++    }
++
++  return priority;
++}
++
+ /* Given OPERANDS of consecutive load/store, check if we can merge
+    them into ldp/stp.  LOAD is true if they are load instructions.
+    MODE is the mode of memory operands.  */
+@@ -13483,6 +13720,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
+   if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2))
+     return false;
+ 
++  /* If we have SImode and slow unaligned ldp,
++     check the alignment to be at least 8 byte. */
++  if (mode == SImode
++      && (aarch64_tune_params.extra_tuning_flags
++          & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)
++      && !optimize_size
++      && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT)
++    return false;
++
+   /* Check if the addresses are in the form of [base+offset].  */
+   extract_base_offset_in_addr (mem_1, &base_1, &offset_1);
+   if (base_1 == NULL_RTX || offset_1 == NULL_RTX)
+@@ -13642,6 +13888,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
+ 	return false;
+     }
+ 
++  /* If we have SImode and slow unaligned ldp,
++     check the alignment to be at least 8 byte. */
++  if (mode == SImode
++      && (aarch64_tune_params.extra_tuning_flags
++          & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)
++      && !optimize_size
++      && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT)
++    return false;
++
+   if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1)))
+     rclass_1 = FP_REGS;
+   else
+@@ -13877,13 +14132,13 @@ aarch64_promoted_type (const_tree t)
+ /* Implement the TARGET_OPTAB_SUPPORTED_P hook.  */
+ 
+ static bool
+-aarch64_optab_supported_p (int op, machine_mode, machine_mode,
++aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode,
+ 			   optimization_type opt_type)
+ {
+   switch (op)
+     {
+     case rsqrt_optab:
+-      return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ();
++      return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p (mode1);
+ 
+     default:
+       return true;
+@@ -14017,6 +14272,10 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_LEGITIMATE_CONSTANT_P
+ #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
+ 
++#undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
++#define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
++  aarch64_legitimize_address_displacement
++
+ #undef TARGET_LIBGCC_CMP_RETURN_MODE
+ #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
+ 
+@@ -14196,6 +14455,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_CAN_USE_DOLOOP_P
+ #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
+ 
++#undef TARGET_SCHED_ADJUST_PRIORITY
++#define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
++
+ #undef TARGET_SCHED_MACRO_FUSION_P
+ #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
+ 
+@@ -14220,6 +14482,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_OPTAB_SUPPORTED_P
+ #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
+ 
++#undef TARGET_OMIT_STRUCT_RETURN_REG
++#define TARGET_OMIT_STRUCT_RETURN_REG true
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ 
+ #include "gt-aarch64.h"
+--- a/src/gcc/config/aarch64/aarch64.h
++++ b/src/gcc/config/aarch64/aarch64.h
+@@ -132,9 +132,12 @@ extern unsigned aarch64_architecture_version;
+ #define AARCH64_FL_FP         (1 << 1)	/* Has FP.  */
+ #define AARCH64_FL_CRYPTO     (1 << 2)	/* Has crypto.  */
+ #define AARCH64_FL_CRC        (1 << 3)	/* Has CRC.  */
+-/* ARMv8.1 architecture extensions.  */
++/* ARMv8.1-A architecture extensions.  */
+ #define AARCH64_FL_LSE	      (1 << 4)  /* Has Large System Extensions.  */
+-#define AARCH64_FL_V8_1	      (1 << 5)  /* Has ARMv8.1 extensions.  */
++#define AARCH64_FL_V8_1	      (1 << 5)  /* Has ARMv8.1-A extensions.  */
++/* ARMv8.2-A architecture extensions.  */
++#define AARCH64_FL_V8_2	      (1 << 8)  /* Has ARMv8.2-A features.  */
++#define AARCH64_FL_F16	      (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
+ 
+ /* Has FP and SIMD.  */
+ #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
+@@ -146,6 +149,8 @@ extern unsigned aarch64_architecture_version;
+ #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
+ #define AARCH64_FL_FOR_ARCH8_1			       \
+   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1)
++#define AARCH64_FL_FOR_ARCH8_2			\
++  (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
+ 
+ /* Macros to test ISA flags.  */
+ 
+@@ -155,6 +160,8 @@ extern unsigned aarch64_architecture_version;
+ #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
+ #define AARCH64_ISA_LSE		   (aarch64_isa_flags & AARCH64_FL_LSE)
+ #define AARCH64_ISA_RDMA	   (aarch64_isa_flags & AARCH64_FL_V8_1)
++#define AARCH64_ISA_V8_2	   (aarch64_isa_flags & AARCH64_FL_V8_2)
++#define AARCH64_ISA_F16		   (aarch64_isa_flags & AARCH64_FL_F16)
+ 
+ /* Crypto is an optional extension to AdvSIMD.  */
+ #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
+@@ -165,6 +172,10 @@ extern unsigned aarch64_architecture_version;
+ /* Atomic instructions that can be enabled through the +lse extension.  */
+ #define TARGET_LSE (AARCH64_ISA_LSE)
+ 
++/* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
++#define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
++#define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
++
+ /* Make sure this is always defined so we don't have to check for ifdefs
+    but rather use normal ifs.  */
+ #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
+@@ -193,7 +204,7 @@ extern unsigned aarch64_architecture_version;
+   ((aarch64_fix_a53_err843419 == 2)	\
+   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
+ 
+-/* ARMv8.1 Adv.SIMD support.  */
++/* ARMv8.1-A Adv.SIMD support.  */
+ #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
+ 
+ /* Standard register usage.  */
+@@ -539,11 +550,14 @@ struct GTY (()) aarch64_frame
+      STACK_BOUNDARY.  */
+   HOST_WIDE_INT saved_varargs_size;
+ 
++  /* The size of the saved callee-save int/FP registers.  */
++
+   HOST_WIDE_INT saved_regs_size;
+-  /* Padding if needed after the all the callee save registers have
+-     been saved.  */
+-  HOST_WIDE_INT padding0;
+-  HOST_WIDE_INT hardfp_offset;	/* HARD_FRAME_POINTER_REGNUM */
++
++  /* Offset from the base of the frame (incomming SP) to the
++     top of the locals area.  This value is always a multiple of
++     STACK_BOUNDARY.  */
++  HOST_WIDE_INT locals_offset;
+ 
+   /* Offset from the base of the frame (incomming SP) to the
+      hard_frame_pointer.  This value is always a multiple of
+@@ -553,12 +567,25 @@ struct GTY (()) aarch64_frame
+   /* The size of the frame.  This value is the offset from base of the
+    * frame (incomming SP) to the stack_pointer.  This value is always
+    * a multiple of STACK_BOUNDARY.  */
++  HOST_WIDE_INT frame_size;
++
++  /* The size of the initial stack adjustment before saving callee-saves.  */
++  HOST_WIDE_INT initial_adjust;
++
++  /* The writeback value when pushing callee-save registers.
++     It is zero when no push is used.  */
++  HOST_WIDE_INT callee_adjust;
++
++  /* The offset from SP to the callee-save registers after initial_adjust.
++     It may be non-zero if no push is used (ie. callee_adjust == 0).  */
++  HOST_WIDE_INT callee_offset;
++
++  /* The size of the stack adjustment after saving callee-saves.  */
++  HOST_WIDE_INT final_adjust;
+ 
+   unsigned wb_candidate1;
+   unsigned wb_candidate2;
+ 
+-  HOST_WIDE_INT frame_size;
+-
+   bool laid_out;
+ };
+ 
+@@ -652,21 +679,6 @@ typedef struct
+ 
+ #define CONSTANT_ADDRESS_P(X)		aarch64_constant_address_p(X)
+ 
+-/* Try a machine-dependent way of reloading an illegitimate address
+-   operand.  If we find one, push the reload and jump to WIN.  This
+-   macro is used in only one place: `find_reloads_address' in reload.c.  */
+-
+-#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN)	     \
+-do {									     \
+-  rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE,    \
+-						 IND_L);		     \
+-  if (new_x)								     \
+-    {									     \
+-      X = new_x;							     \
+-      goto WIN;								     \
+-    }									     \
+-} while (0)
+-
+ #define REGNO_OK_FOR_BASE_P(REGNO)	\
+   aarch64_regno_ok_for_base_p (REGNO, true)
+ 
+@@ -722,7 +734,12 @@ do {									     \
+ #define USE_STORE_PRE_INCREMENT(MODE)   0
+ #define USE_STORE_PRE_DECREMENT(MODE)   0
+ 
+-/* ?? #define WORD_REGISTER_OPERATIONS  */
++/* WORD_REGISTER_OPERATIONS does not hold for AArch64.
++   The assigned word_mode is DImode but operations narrower than SImode
++   behave as 32-bit operations if using the W-form of the registers rather
++   than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
++   expects.  */
++#define WORD_REGISTER_OPERATIONS 0
+ 
+ /* Define if loading from memory in MODE, an integral mode narrower than
+    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
+@@ -842,10 +859,7 @@ do {									     \
+   extern void  __aarch64_sync_cache_range (void *, void *);	\
+   __aarch64_sync_cache_range (beg, end)
+ 
+-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)	\
+-  aarch64_cannot_change_mode_class (FROM, TO, CLASS)
+-
+-#define SHIFT_COUNT_TRUNCATED !TARGET_SIMD
++#define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
+ 
+ /* Choose appropriate mode for caller saves, so we do the minimum
+    required size of load/store.  */
+--- a/src/gcc/config/aarch64/aarch64.md
++++ b/src/gcc/config/aarch64/aarch64.md
+@@ -75,6 +75,8 @@
+     UNSPEC_CRC32H
+     UNSPEC_CRC32W
+     UNSPEC_CRC32X
++    UNSPEC_FCVTZS
++    UNSPEC_FCVTZU
+     UNSPEC_URECPE
+     UNSPEC_FRECPE
+     UNSPEC_FRECPS
+@@ -105,6 +107,7 @@
+     UNSPEC_NOP
+     UNSPEC_PRLG_STK
+     UNSPEC_RBIT
++    UNSPEC_SCVTF
+     UNSPEC_SISD_NEG
+     UNSPEC_SISD_SSHL
+     UNSPEC_SISD_USHL
+@@ -122,6 +125,7 @@
+     UNSPEC_TLSLE24
+     UNSPEC_TLSLE32
+     UNSPEC_TLSLE48
++    UNSPEC_UCVTF
+     UNSPEC_USHL_2S
+     UNSPEC_VSTRUCTDUMMY
+     UNSPEC_SP_SET
+@@ -837,13 +841,6 @@
+ 	   || aarch64_is_noplt_call_p (callee)))
+       XEXP (operands[0], 0) = force_reg (Pmode, callee);
+ 
+-    /* FIXME: This is a band-aid.  Need to analyze why expand_expr_addr_expr
+-       is generating an SImode symbol reference.  See PR 64971.  */
+-    if (TARGET_ILP32
+-	&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
+-	&& GET_MODE (XEXP (operands[0], 0)) == SImode)
+-      XEXP (operands[0], 0) = convert_memory_address (Pmode,
+-						      XEXP (operands[0], 0));
+     if (operands[2] == NULL_RTX)
+       operands[2] = const0_rtx;
+ 
+@@ -875,14 +872,6 @@
+ 	   || aarch64_is_noplt_call_p (callee)))
+       XEXP (operands[1], 0) = force_reg (Pmode, callee);
+ 
+-    /* FIXME: This is a band-aid.  Need to analyze why expand_expr_addr_expr
+-       is generating an SImode symbol reference.  See PR 64971.  */
+-    if (TARGET_ILP32
+-	&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+-	&& GET_MODE (XEXP (operands[1], 0)) == SImode)
+-      XEXP (operands[1], 0) = convert_memory_address (Pmode,
+-						      XEXP (operands[1], 0));
+-
+     if (operands[3] == NULL_RTX)
+       operands[3] = const0_rtx;
+ 
+@@ -1160,11 +1149,12 @@
+ )
+ 
+ (define_insn "*movhf_aarch64"
+-  [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r")
+-	(match_operand:HF 1 "general_operand"      "?rY, w,w,m,w,m,rY,r"))]
++  [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w  ,?r,w,w,m,r,m ,r")
++	(match_operand:HF 1 "general_operand"      "Y ,?rY, w,w,m,w,m,rY,r"))]
+   "TARGET_FLOAT && (register_operand (operands[0], HFmode)
+     || aarch64_reg_or_fp_zero (operands[1], HFmode))"
+   "@
++   movi\\t%0.4h, #0
+    mov\\t%0.h[0], %w1
+    umov\\t%w0, %1.h[0]
+    mov\\t%0.h[0], %1.h[0]
+@@ -1173,18 +1163,18 @@
+    ldrh\\t%w0, %1
+    strh\\t%w1, %0
+    mov\\t%w0, %w1"
+-  [(set_attr "type" "neon_from_gp,neon_to_gp,neon_move,\
++  [(set_attr "type" "neon_move,neon_from_gp,neon_to_gp,neon_move,\
+                      f_loads,f_stores,load1,store1,mov_reg")
+-   (set_attr "simd" "yes,yes,yes,*,*,*,*,*")
+-   (set_attr "fp"   "*,*,*,yes,yes,*,*,*")]
++   (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*")]
+ )
+ 
+ (define_insn "*movsf_aarch64"
+-  [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w  ,w,m,r,m ,r")
+-	(match_operand:SF 1 "general_operand"      "?rY, w,w,Ufc,m,w,m,rY,r"))]
++  [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w  ,?r,w,w  ,w,m,r,m ,r")
++	(match_operand:SF 1 "general_operand"      "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
+   "TARGET_FLOAT && (register_operand (operands[0], SFmode)
+     || aarch64_reg_or_fp_zero (operands[1], SFmode))"
+   "@
++   movi\\t%0.2s, #0
+    fmov\\t%s0, %w1
+    fmov\\t%w0, %s1
+    fmov\\t%s0, %s1
+@@ -1194,16 +1184,18 @@
+    ldr\\t%w0, %1
+    str\\t%w1, %0
+    mov\\t%w0, %w1"
+-  [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
+-                     f_loads,f_stores,load1,store1,mov_reg")]
++  [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,\
++                     f_loads,f_stores,load1,store1,mov_reg")
++   (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
+ )
+ 
+ (define_insn "*movdf_aarch64"
+-  [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w  ,w,m,r,m ,r")
+-	(match_operand:DF 1 "general_operand"      "?rY, w,w,Ufc,m,w,m,rY,r"))]
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=w,w  ,?r,w,w  ,w,m,r,m ,r")
++	(match_operand:DF 1 "general_operand"      "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
+   "TARGET_FLOAT && (register_operand (operands[0], DFmode)
+     || aarch64_reg_or_fp_zero (operands[1], DFmode))"
+   "@
++   movi\\t%d0, #0
+    fmov\\t%d0, %x1
+    fmov\\t%x0, %d1
+    fmov\\t%d0, %d1
+@@ -1213,8 +1205,9 @@
+    ldr\\t%x0, %1
+    str\\t%x1, %0
+    mov\\t%x0, %x1"
+-  [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\
+-                     f_loadd,f_stored,load1,store1,mov_reg")]
++  [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,\
++                     f_loadd,f_stored,load1,store1,mov_reg")
++   (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
+ )
+ 
+ (define_insn "*movtf_aarch64"
+@@ -1239,7 +1232,6 @@
+   [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\
+                      f_loadd,f_stored,load2,store2,store2")
+    (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4")
+-   (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*,*")
+    (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")]
+ )
+ 
+@@ -1552,10 +1544,10 @@
+         (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))]
+   ""
+   "@
+-   uxt<SHORT:size>\t%<GPI:w>0, %w1
++   and\t%<GPI:w>0, %<GPI:w>1, <SHORT:short_mask>
+    ldr<SHORT:size>\t%w0, %1
+    ldr\t%<SHORT:size>0, %1"
+-  [(set_attr "type" "extend,load1,load1")]
++  [(set_attr "type" "logic_imm,load1,load1")]
+ )
+ 
+ (define_expand "<optab>qihi2"
+@@ -1564,16 +1556,26 @@
+   ""
+ )
+ 
+-(define_insn "*<optab>qihi2_aarch64"
++(define_insn "*extendqihi2_aarch64"
+   [(set (match_operand:HI 0 "register_operand" "=r,r")
+-        (ANY_EXTEND:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
++	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+   ""
+   "@
+-   <su>xtb\t%w0, %w1
+-   <ldrxt>b\t%w0, %1"
++   sxtb\t%w0, %w1
++   ldrsb\t%w0, %1"
+   [(set_attr "type" "extend,load1")]
+ )
+ 
++(define_insn "*zero_extendqihi2_aarch64"
++  [(set (match_operand:HI 0 "register_operand" "=r,r")
++	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
++  ""
++  "@
++   and\t%w0, %w1, 255
++   ldrb\t%w0, %1"
++  [(set_attr "type" "logic_imm,load1")]
++)
++
+ ;; -------------------------------------------------------------------
+ ;; Simple arithmetic
+ ;; -------------------------------------------------------------------
+@@ -1585,25 +1587,16 @@
+ 	      (match_operand:GPI 2 "aarch64_pluslong_operand" "")))]
+   ""
+ {
+-  if (aarch64_pluslong_strict_immedate (operands[2], <MODE>mode))
+-    {
+-      /* Give CSE the opportunity to share this constant across additions.  */
+-      if (!cse_not_expected && can_create_pseudo_p ())
+-        operands[2] = force_reg (<MODE>mode, operands[2]);
+-
+-      /* Split will refuse to operate on a modification to the stack pointer.
+-	 Aid the prologue and epilogue expanders by splitting this now.  */
+-      else if (reload_completed && operands[0] == stack_pointer_rtx)
+-	{
+-	  HOST_WIDE_INT i = INTVAL (operands[2]);
+-	  HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
+-	  emit_insn (gen_rtx_SET (operands[0],
+-				  gen_rtx_PLUS (<MODE>mode, operands[1],
+-						GEN_INT (i - s))));
+-	  operands[1] = operands[0];
+-	  operands[2] = GEN_INT (s);
+-	}
+-    }
++  /* If operands[1] is a subreg extract the inner RTX.  */
++  rtx op1 = REG_P (operands[1]) ? operands[1] : SUBREG_REG (operands[1]);
++
++  /* If the constant is too large for a single instruction and isn't frame
++     based, split off the immediate so it is available for CSE.  */
++  if (!aarch64_plus_immediate (operands[2], <MODE>mode)
++      && can_create_pseudo_p ()
++      && (!REG_P (op1)
++	 || !REGNO_PTR_FRAME_P (REGNO (op1))))
++    operands[2] = force_reg (<MODE>mode, operands[2]);
+ })
+ 
+ (define_insn "*add<mode>3_aarch64"
+@@ -1765,7 +1758,7 @@
+   "aarch64_zero_extend_const_eq (<DWI>mode, operands[2],
+ 				 <MODE>mode, operands[1])"
+   "@
+-  cmn\\t%<w>0, %<w>1
++  cmn\\t%<w>0, %1
+   cmp\\t%<w>0, #%n1"
+   [(set_attr "type" "alus_imm")]
+ )
+@@ -1797,11 +1790,11 @@
+   "aarch64_zero_extend_const_eq (<DWI>mode, operands[3],
+                                  <MODE>mode, operands[2])"
+   "@
+-  adds\\t%<w>0, %<w>1, %<w>2
++  adds\\t%<w>0, %<w>1, %2
+   subs\\t%<w>0, %<w>1, #%n2"
+   [(set_attr "type" "alus_imm")]
+ )
+- 
++
+ (define_insn "add<mode>3_compareC"
+   [(set (reg:CC_C CC_REGNUM)
+ 	(ne:CC_C
+@@ -3404,7 +3397,9 @@
+          (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r")
+ 		     (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))]
+   ""
+-  "<logical>\\t%w0, %w1, %w2"
++  "@
++   <logical>\\t%w0, %w1, %w2
++   <logical>\\t%w0, %w1, %2"
+   [(set_attr "type" "logic_reg,logic_imm")]
+ )
+ 
+@@ -3417,7 +3412,9 @@
+    (set (match_operand:GPI 0 "register_operand" "=r,r")
+ 	(and:GPI (match_dup 1) (match_dup 2)))]
+   ""
+-  "ands\\t%<w>0, %<w>1, %<w>2"
++  "@
++   ands\\t%<w>0, %<w>1, %<w>2
++   ands\\t%<w>0, %<w>1, %2"
+   [(set_attr "type" "logics_reg,logics_imm")]
+ )
+ 
+@@ -3431,7 +3428,9 @@
+    (set (match_operand:DI 0 "register_operand" "=r,r")
+ 	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
+   ""
+-  "ands\\t%w0, %w1, %w2"
++  "@
++   ands\\t%w0, %w1, %w2
++   ands\\t%w0, %w1, %2"
+   [(set_attr "type" "logics_reg,logics_imm")]
+ )
+ 
+@@ -3757,16 +3756,23 @@
+   [(set_attr "type" "rbit")]
+ )
+ 
+-(define_expand "ctz<mode>2"
+-  [(match_operand:GPI 0 "register_operand")
+-   (match_operand:GPI 1 "register_operand")]
++;; Split after reload into RBIT + CLZ.  Since RBIT is represented as an UNSPEC
++;; it is unlikely to fold with any other operation, so keep this as a CTZ
++;; expression and split after reload to enable scheduling them apart if
++;; needed.
++
++(define_insn_and_split "ctz<mode>2"
++ [(set (match_operand:GPI           0 "register_operand" "=r")
++       (ctz:GPI (match_operand:GPI  1 "register_operand" "r")))]
+   ""
+-  {
+-    emit_insn (gen_rbit<mode>2 (operands[0], operands[1]));
+-    emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+-    DONE;
+-  }
+-)
++  "#"
++  "reload_completed"
++  [(const_int 0)]
++  "
++  emit_insn (gen_rbit<mode>2 (operands[0], operands[1]));
++  emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
++  DONE;
++")
+ 
+ (define_insn "*and<mode>_compare0"
+   [(set (reg:CC_NZ CC_REGNUM)
+@@ -3778,6 +3784,18 @@
+   [(set_attr "type" "alus_imm")]
+ )
+ 
++(define_insn "*ands<mode>_compare0"
++  [(set (reg:CC_NZ CC_REGNUM)
++	(compare:CC_NZ
++	 (zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r"))
++	 (const_int 0)))
++   (set (match_operand:GPI 0 "register_operand" "=r")
++	(zero_extend:GPI (match_dup 1)))]
++  ""
++  "ands\\t%<GPI:w>0, %<GPI:w>1, <short_mask>"
++  [(set_attr "type" "alus_imm")]
++)
++
+ (define_insn "*and<mode>3nr_compare0"
+   [(set (reg:CC_NZ CC_REGNUM)
+ 	(compare:CC_NZ
+@@ -3785,7 +3803,9 @@
+ 		  (match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
+ 	 (const_int 0)))]
+   ""
+-  "tst\\t%<w>0, %<w>1"
++  "@
++   tst\\t%<w>0, %<w>1
++   tst\\t%<w>0, %1"
+   [(set_attr "type" "logics_reg,logics_imm")]
+ )
+ 
+@@ -3851,22 +3871,16 @@
+ (define_expand "ashl<mode>3"
+   [(set (match_operand:SHORT 0 "register_operand")
+ 	(ashift:SHORT (match_operand:SHORT 1 "register_operand")
+-		      (match_operand:QI 2 "nonmemory_operand")))]
++		      (match_operand:QI 2 "const_int_operand")))]
+   ""
+   {
+-    if (CONST_INT_P (operands[2]))
+-      {
+-        operands[2] = GEN_INT (INTVAL (operands[2])
+-                               & (GET_MODE_BITSIZE (<MODE>mode) - 1));
++    operands[2] = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (<MODE>mode));
+ 
+-        if (operands[2] == const0_rtx)
+-          {
+-	    emit_insn (gen_mov<mode> (operands[0], operands[1]));
+-	    DONE;
+-          }
++    if (operands[2] == const0_rtx)
++      {
++	emit_insn (gen_mov<mode> (operands[0], operands[1]));
++	DONE;
+       }
+-    else
+-      FAIL;
+   }
+ )
+ 
+@@ -3915,33 +3929,35 @@
+ 
+ ;; Logical left shift using SISD or Integer instruction
+ (define_insn "*aarch64_ashl_sisd_or_int_<mode>3"
+-  [(set (match_operand:GPI 0 "register_operand" "=r,w,w")
+-        (ashift:GPI
+-          (match_operand:GPI 1 "register_operand" "r,w,w")
+-          (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w")))]
++  [(set (match_operand:GPI 0 "register_operand" "=r,r,w,w")
++	(ashift:GPI
++	  (match_operand:GPI 1 "register_operand" "r,r,w,w")
++	  (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r,Us<cmode>,w")))]
+   ""
+   "@
++   lsl\t%<w>0, %<w>1, %2
+    lsl\t%<w>0, %<w>1, %<w>2
+    shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2
+    ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>"
+-  [(set_attr "simd" "no,yes,yes")
+-   (set_attr "type" "shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
++  [(set_attr "simd" "no,no,yes,yes")
++   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
+ )
+ 
+ ;; Logical right shift using SISD or Integer instruction
+ (define_insn "*aarch64_lshr_sisd_or_int_<mode>3"
+-  [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w")
+-        (lshiftrt:GPI
+-          (match_operand:GPI 1 "register_operand" "r,w,w,w")
+-          (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w,0")))]
++  [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w")
++	(lshiftrt:GPI
++	 (match_operand:GPI 1 "register_operand" "r,r,w,w,w")
++	 (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r,Us<cmode>,w,0")))]
+   ""
+   "@
++   lsr\t%<w>0, %<w>1, %2
+    lsr\t%<w>0, %<w>1, %<w>2
+    ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2
+    #
+    #"
+-  [(set_attr "simd" "no,yes,yes,yes")
+-   (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
++  [(set_attr "simd" "no,no,yes,yes,yes")
++   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+ )
+ 
+ (define_split
+@@ -3976,18 +3992,19 @@
+ 
+ ;; Arithmetic right shift using SISD or Integer instruction
+ (define_insn "*aarch64_ashr_sisd_or_int_<mode>3"
+-  [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w")
++  [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w")
+         (ashiftrt:GPI
+-          (match_operand:GPI 1 "register_operand" "r,w,w,w")
+-          (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "rUs<cmode>,Us<cmode>,w,0")))]
++          (match_operand:GPI 1 "register_operand" "r,r,w,w,w")
++          (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us<cmode>,r,Us<cmode>,w,0")))]
+   ""
+   "@
++   asr\t%<w>0, %<w>1, %2
+    asr\t%<w>0, %<w>1, %<w>2
+    sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2
+    #
+    #"
+-  [(set_attr "simd" "no,yes,yes,yes")
+-   (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
++  [(set_attr "simd" "no,no,yes,yes,yes")
++   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+ )
+ 
+ (define_split
+@@ -4079,21 +4096,25 @@
+   [(set (match_operand:GPI 0 "register_operand" "=r,r")
+      (rotatert:GPI
+        (match_operand:GPI 1 "register_operand" "r,r")
+-       (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "r,Us<cmode>")))]
++       (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r")))]
+   ""
+-  "ror\\t%<w>0, %<w>1, %<w>2"
+-  [(set_attr "type" "shift_reg, rotate_imm")]
++  "@
++   ror\\t%<w>0, %<w>1, %2
++   ror\\t%<w>0, %<w>1, %<w>2"
++  [(set_attr "type" "rotate_imm,shift_reg")]
+ )
+ 
+ ;; zero_extend version of above
+ (define_insn "*<optab>si3_insn_uxtw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
++  [(set (match_operand:DI 0 "register_operand" "=r,r")
+ 	(zero_extend:DI (SHIFT:SI
+-	 (match_operand:SI 1 "register_operand" "r")
+-	 (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))]
++	 (match_operand:SI 1 "register_operand" "r,r")
++	 (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Uss,r"))))]
+   ""
+-  "<shift>\\t%w0, %w1, %w2"
+-  [(set_attr "type" "shift_reg")]
++  "@
++   <shift>\\t%w0, %w1, %2
++   <shift>\\t%w0, %w1, %w2"
++  [(set_attr "type" "bfx,shift_reg")]
+ )
+ 
+ (define_insn "*<optab><mode>3_insn"
+@@ -4105,7 +4126,7 @@
+   operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
+   return "<bfshift>\t%w0, %w1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ (define_insn "*extr<mode>5_insn"
+@@ -4117,7 +4138,7 @@
+   "UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) &&
+    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
+   "extr\\t%<w>0, %<w>1, %<w>2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ ;; There are no canonicalisation rules for ashift and lshiftrt inside an ior
+@@ -4132,7 +4153,7 @@
+    && (UINTVAL (operands[3]) + UINTVAL (operands[4])
+        == GET_MODE_BITSIZE (<MODE>mode))"
+   "extr\\t%<w>0, %<w>1, %<w>2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ ;; zero_extend version of the above
+@@ -4146,7 +4167,7 @@
+   "UINTVAL (operands[3]) < 32 &&
+    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
+   "extr\\t%w0, %w1, %w2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ (define_insn "*extrsi5_insn_uxtw_alt"
+@@ -4159,7 +4180,7 @@
+   "UINTVAL (operands[3]) < 32 &&
+    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
+   "extr\\t%w0, %w1, %w2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ (define_insn "*ror<mode>3_insn"
+@@ -4198,7 +4219,7 @@
+   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
+   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ (define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>"
+@@ -4211,7 +4232,7 @@
+   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
+   return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ (define_insn "*extend<GPI:mode>_ashr<SHORT:mode>"
+@@ -4224,7 +4245,7 @@
+   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
+   return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ ;; -------------------------------------------------------------------
+@@ -4256,7 +4277,27 @@
+   "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]),
+ 	     1, GET_MODE_BITSIZE (<MODE>mode) - 1)"
+   "<su>bfx\\t%<w>0, %<w>1, %3, %2"
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
++)
++
++;; When the bit position and width add up to 32 we can use a W-reg LSR
++;; instruction taking advantage of the implicit zero-extension of the X-reg.
++(define_split
++  [(set (match_operand:DI 0 "register_operand")
++	(zero_extract:DI (match_operand:DI 1 "register_operand")
++			 (match_operand 2
++			   "aarch64_simd_shift_imm_offset_di")
++			 (match_operand 3
++			   "aarch64_simd_shift_imm_di")))]
++  "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), 1,
++	     GET_MODE_BITSIZE (DImode) - 1)
++   && (INTVAL (operands[2]) + INTVAL (operands[3]))
++       == GET_MODE_BITSIZE (SImode)"
++  [(set (match_dup 0)
++	(zero_extend:DI (lshiftrt:SI (match_dup 4) (match_dup 3))))]
++  {
++    operands[4] = gen_lowpart (SImode, operands[1]);
++  }
+ )
+ 
+ ;; Bitfield Insert (insv)
+@@ -4338,7 +4379,7 @@
+ 	      : GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
+   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ ;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below
+@@ -4348,11 +4389,27 @@
+ 	(and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
+ 			     (match_operand 2 "const_int_operand" "n"))
+ 		 (match_operand 3 "const_int_operand" "n")))]
+-  "(INTVAL (operands[2]) < (<GPI:sizen>))
+-   && exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
+-   && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"
++  "aarch64_mask_and_shift_for_ubfiz_p (<MODE>mode, operands[3], operands[2])"
+   "ubfiz\\t%<w>0, %<w>1, %2, %P3"
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
++)
++
++;; When the bit position and width of the equivalent extraction add up to 32
++;; we can use a W-reg LSL instruction taking advantage of the implicit
++;; zero-extension of the X-reg.
++(define_split
++  [(set (match_operand:DI 0 "register_operand")
++	(and:DI (ashift:DI (match_operand:DI 1 "register_operand")
++			     (match_operand 2 "const_int_operand"))
++		 (match_operand 3 "const_int_operand")))]
++ "aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2])
++  && (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3])))
++      == GET_MODE_BITSIZE (SImode)"
++  [(set (match_dup 0)
++	(zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))]
++  {
++    operands[4] = gen_lowpart (SImode, operands[1]);
++  }
+ )
+ 
+ (define_insn "bswap<mode>2"
+@@ -4420,22 +4477,23 @@
+ ;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
+ 
+ (define_insn "<frint_pattern><mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")]
+ 	 FRINT))]
+   "TARGET_FLOAT"
+   "frint<frint_suffix>\\t%<s>0, %<s>1"
+-  [(set_attr "type" "f_rint<s>")]
++  [(set_attr "type" "f_rint<stype>")]
+ )
+ 
+ ;; frcvt floating-point round to integer and convert standard patterns.
+ ;; Expands to lbtrunc, lceil, lfloor, lround.
+-(define_insn "l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2"
++(define_insn "l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2"
+   [(set (match_operand:GPI 0 "register_operand" "=r")
+-	(FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
+-		      FCVT)))]
++	(FIXUORS:GPI
++	  (unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")]
++	   FCVT)))]
+   "TARGET_FLOAT"
+-  "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1"
++  "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF_F16:s>1"
+   [(set_attr "type" "f_cvtf2i")]
+ )
+ 
+@@ -4461,23 +4519,24 @@
+ ;; fma - no throw
+ 
+ (define_insn "fma<mode>4"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (fma:GPF (match_operand:GPF 1 "register_operand" "w")
+-		 (match_operand:GPF 2 "register_operand" "w")
+-		 (match_operand:GPF 3 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++        (fma:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")
++		     (match_operand:GPF_F16 2 "register_operand" "w")
++		     (match_operand:GPF_F16 3 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3"
+-  [(set_attr "type" "fmac<s>")]
++  [(set_attr "type" "fmac<stype>")]
+ )
+ 
+ (define_insn "fnma<mode>4"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(fma:GPF (neg:GPF (match_operand:GPF 1 "register_operand" "w"))
+-		 (match_operand:GPF 2 "register_operand" "w")
+-		 (match_operand:GPF 3 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(fma:GPF_F16
++	  (neg:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w"))
++	  (match_operand:GPF_F16 2 "register_operand" "w")
++	  (match_operand:GPF_F16 3 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3"
+-  [(set_attr "type" "fmac<s>")]
++  [(set_attr "type" "fmac<stype>")]
+ )
+ 
+ (define_insn "fms<mode>4"
+@@ -4563,19 +4622,11 @@
+   [(set_attr "type" "f_cvt")]
+ )
+ 
+-(define_insn "fix_trunc<GPF:mode><GPI:mode>2"
++(define_insn "<optab>_trunc<GPF_F16:mode><GPI:mode>2"
+   [(set (match_operand:GPI 0 "register_operand" "=r")
+-        (fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
++	(FIXUORS:GPI (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+-  "fcvtzs\\t%<GPI:w>0, %<GPF:s>1"
+-  [(set_attr "type" "f_cvtf2i")]
+-)
+-
+-(define_insn "fixuns_trunc<GPF:mode><GPI:mode>2"
+-  [(set (match_operand:GPI 0 "register_operand" "=r")
+-        (unsigned_fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
+-  "TARGET_FLOAT"
+-  "fcvtzu\\t%<GPI:w>0, %<GPF:s>1"
++  "fcvtz<su>\t%<GPI:w>0, %<GPF_F16:s>1"
+   [(set_attr "type" "f_cvtf2i")]
+ )
+ 
+@@ -4599,38 +4650,116 @@
+   [(set_attr "type" "f_cvti2f")]
+ )
+ 
++(define_insn "<optab><mode>hf2"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(FLOATUORS:HF (match_operand:GPI 1 "register_operand" "r")))]
++  "TARGET_FP_F16INST"
++  "<su_optab>cvtf\t%h0, %<w>1"
++  [(set_attr "type" "f_cvti2f")]
++)
++
++;; Convert between fixed-point and floating-point (scalar modes)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3"
++  [(set (match_operand:<GPF:FCVT_TARGET> 0 "register_operand" "=r, w")
++	(unspec:<GPF:FCVT_TARGET> [(match_operand:GPF 1 "register_operand" "w, w")
++				   (match_operand:SI 2 "immediate_operand" "i, i")]
++	 FCVT_F2FIXED))]
++  ""
++  "@
++   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:w1>0, %<GPF:s>1, #%2
++   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:s>0, %<GPF:s>1, #%2"
++  [(set_attr "type" "f_cvtf2i, neon_fp_to_int_<GPF:Vetype>")
++   (set_attr "fp" "yes, *")
++   (set_attr "simd" "*, yes")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3"
++  [(set (match_operand:<GPI:FCVT_TARGET> 0 "register_operand" "=w, w")
++	(unspec:<GPI:FCVT_TARGET> [(match_operand:GPI 1 "register_operand" "r, w")
++				   (match_operand:SI 2 "immediate_operand" "i, i")]
++	 FCVT_FIXED2F))]
++  ""
++  "@
++   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:w>1, #%2
++   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:v>1, #%2"
++  [(set_attr "type" "f_cvti2f, neon_int_to_fp_<GPI:Vetype>")
++   (set_attr "fp" "yes, *")
++   (set_attr "simd" "*, yes")]
++)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf<mode>3"
++  [(set (match_operand:GPI 0 "register_operand" "=r")
++	(unspec:GPI [(match_operand:HF 1 "register_operand" "w")
++		     (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_F2FIXED))]
++  "TARGET_FP_F16INST"
++   "<FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPI:w>0, %h1, #%2"
++  [(set_attr "type" "f_cvtf2i")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><mode>hf3"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(unspec:HF [(match_operand:GPI 1 "register_operand" "r")
++		    (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_FIXED2F))]
++  "TARGET_FP_F16INST"
++  "<FCVT_FIXED2F:fcvt_fixed_insn>\t%h0, %<GPI:w>1, #%2"
++  [(set_attr "type" "f_cvti2f")]
++)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf3"
++  [(set (match_operand:HI 0 "register_operand" "=w")
++	(unspec:HI [(match_operand:HF 1 "register_operand" "w")
++		    (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_F2FIXED))]
++  "TARGET_SIMD"
++  "<FCVT_F2FIXED:fcvt_fixed_insn>\t%h0, %h1, #%2"
++  [(set_attr "type" "neon_fp_to_int_s")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn>hi3"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(unspec:HF [(match_operand:HI 1 "register_operand" "w")
++		    (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_FIXED2F))]
++  "TARGET_SIMD"
++  "<FCVT_FIXED2F:fcvt_fixed_insn>\t%h0, %h1, #%2"
++  [(set_attr "type" "neon_int_to_fp_s")]
++)
++
+ ;; -------------------------------------------------------------------
+ ;; Floating-point arithmetic
+ ;; -------------------------------------------------------------------
+ 
+ (define_insn "add<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (plus:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(plus:GPF_F16
++	 (match_operand:GPF_F16 1 "register_operand" "w")
++	 (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fadd\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fadd<s>")]
++  [(set_attr "type" "fadd<stype>")]
+ )
+ 
+ (define_insn "sub<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (minus:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(minus:GPF_F16
++	 (match_operand:GPF_F16 1 "register_operand" "w")
++	 (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fsub\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fadd<s>")]
++  [(set_attr "type" "fadd<stype>")]
+ )
+ 
+ (define_insn "mul<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (mult:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(mult:GPF_F16
++	 (match_operand:GPF_F16 1 "register_operand" "w")
++	 (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fmul\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fmul<s>")]
++  [(set_attr "type" "fmul<stype>")]
+ )
+ 
+ (define_insn "*fnmul<mode>3"
+@@ -4653,38 +4782,58 @@
+   [(set_attr "type" "fmul<s>")]
+ )
+ 
+-(define_insn "div<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (div:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++(define_expand "div<mode>3"
++ [(set (match_operand:GPF_F16 0 "register_operand")
++       (div:GPF_F16 (match_operand:GPF_F16 1 "general_operand")
++		    (match_operand:GPF_F16 2 "register_operand")))]
++ "TARGET_SIMD"
++{
++  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
++    DONE;
++
++  operands[1] = force_reg (<MODE>mode, operands[1]);
++})
++
++(define_insn "*div<mode>3"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(div:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")
++		     (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fdiv\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fdiv<s>")]
++  [(set_attr "type" "fdiv<stype>")]
+ )
+ 
+ (define_insn "neg<mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (neg:GPF (match_operand:GPF 1 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(neg:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fneg\\t%<s>0, %<s>1"
+-  [(set_attr "type" "ffarith<s>")]
++  [(set_attr "type" "ffarith<stype>")]
+ )
+ 
+-(define_insn "sqrt<mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (sqrt:GPF (match_operand:GPF 1 "register_operand" "w")))]
++(define_expand "sqrt<mode>2"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
++  "TARGET_FLOAT"
++{
++  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
++    DONE;
++})
++
++(define_insn "*sqrt<mode>2"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fsqrt\\t%<s>0, %<s>1"
+-  [(set_attr "type" "fsqrt<s>")]
++  [(set_attr "type" "fsqrt<stype>")]
+ )
+ 
+ (define_insn "abs<mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (abs:GPF (match_operand:GPF 1 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(abs:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fabs\\t%<s>0, %<s>1"
+-  [(set_attr "type" "ffarith<s>")]
++  [(set_attr "type" "ffarith<stype>")]
+ )
+ 
+ ;; Given that smax/smin do not specify the result when either input is NaN,
+@@ -4709,15 +4858,17 @@
+   [(set_attr "type" "f_minmax<s>")]
+ )
+ 
+-;; Scalar forms for the IEEE-754 fmax()/fmin() functions
+-(define_insn "<fmaxmin><mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")
+-		     (match_operand:GPF 2 "register_operand" "w")]
+-		     FMAXMIN))]
++;; Scalar forms for fmax, fmin, fmaxnm, fminnm.
++;; fmaxnm and fminnm are used for the fmax<mode>3 standard pattern names,
++;; which implement the IEEE fmax ()/fmin () functions.
++(define_insn "<maxmin_uns><mode>3"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")
++		     (match_operand:GPF_F16 2 "register_operand" "w")]
++		     FMAXMIN_UNS))]
+   "TARGET_FLOAT"
+-  "<fmaxmin_op>\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "f_minmax<s>")]
++  "<maxmin_uns_op>\\t%<s>0, %<s>1, %<s>2"
++  [(set_attr "type" "f_minmax<stype>")]
+ )
+ 
+ ;; For copysign (x, y), we want to generate:
+@@ -4775,7 +4926,7 @@
+  [(set (match_operand:GPF_TF 0 "register_operand" "=w")
+        (mem:GPF_TF (match_operand 1 "aarch64_constant_pool_symref" "S")))
+   (clobber (match_operand:P 2 "register_operand" "=&r"))]
+- "TARGET_FLOAT && aarch64_nopcrelative_literal_loads"
++ "TARGET_FLOAT"
+  {
+    aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+    emit_move_insn (operands[0], gen_rtx_MEM (<GPF_TF:MODE>mode, operands[2]));
+@@ -4788,7 +4939,7 @@
+  [(set (match_operand:VALL 0 "register_operand" "=w")
+        (mem:VALL (match_operand 1 "aarch64_constant_pool_symref" "S")))
+   (clobber (match_operand:P 2 "register_operand" "=&r"))]
+- "TARGET_FLOAT && aarch64_nopcrelative_literal_loads"
++ "TARGET_FLOAT"
+  {
+    aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+    emit_move_insn (operands[0], gen_rtx_MEM (<VALL:MODE>mode, operands[2]));
+@@ -5182,7 +5333,7 @@
+ 	 UNSPEC_SP_TEST))
+    (clobber (match_scratch:PTR 3 "=&r"))]
+   ""
+-  "ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0"
++  "ldr\t%<w>3, %1\;ldr\t%<w>0, %2\;eor\t%<w>0, %<w>3, %<w>0"
+   [(set_attr "length" "12")
+    (set_attr "type" "multiple")])
+ 
+--- a/src/gcc/config/aarch64/aarch64.opt
++++ b/src/gcc/config/aarch64/aarch64.opt
+@@ -146,10 +146,24 @@ EnumValue
+ Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
+ 
+ mpc-relative-literal-loads
+-Target Report Save Var(nopcrelative_literal_loads) Init(2) Save
++Target Report Save Var(pcrelative_literal_loads) Init(2) Save
+ PC relative literal loads.
+ 
+ mlow-precision-recip-sqrt
+ Common Var(flag_mrecip_low_precision_sqrt) Optimization
+-When calculating the reciprocal square root approximation,
+-uses one less step than otherwise, thus reducing latency and precision.
++Enable the reciprocal square root approximation.  Enabling this reduces
++precision of reciprocal square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++
++mlow-precision-sqrt
++Common Var(flag_mlow_precision_sqrt) Optimization
++Enable the square root approximation.  Enabling this reduces
++precision of square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++If enabled, it implies -mlow-precision-recip-sqrt.
++
++mlow-precision-div
++Common Var(flag_mlow_precision_div) Optimization
++Enable the division approximation.  Enabling this reduces
++precision of division results to about 16 bits for
++single precision and to 32 bits for double precision.
+--- /dev/null
++++ b/src/gcc/config/aarch64/arm_fp16.h
+@@ -0,0 +1,579 @@
++/* ARM FP16 scalar intrinsics include file.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef _AARCH64_FP16_H_
++#define _AARCH64_FP16_H_
++
++#include <stdint.h>
++
++#pragma GCC push_options
++#pragma GCC target ("arch=armv8.2-a+fp16")
++
++typedef __fp16 float16_t;
++
++/* ARMv8.2-A FP16 one operand scalar intrinsics.  */
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vabsh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_abshf (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vceqzh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmeqhf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgezh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmgehf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgtzh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmgthf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vclezh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmlehf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcltzh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmlthf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s16 (int16_t __a)
++{
++  return __builtin_aarch64_floathihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s32 (int32_t __a)
++{
++  return __builtin_aarch64_floatsihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s64 (int64_t __a)
++{
++  return __builtin_aarch64_floatdihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u16 (uint16_t __a)
++{
++  return __builtin_aarch64_floatunshihf_us (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u32 (uint32_t __a)
++{
++  return __builtin_aarch64_floatunssihf_us (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u64 (uint64_t __a)
++{
++  return __builtin_aarch64_floatunsdihf_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvth_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fix_trunchfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fix_trunchfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvth_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fix_trunchfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvth_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fixuns_trunchfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fixuns_trunchfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvth_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fixuns_trunchfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtah_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lroundhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtah_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lroundhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtah_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lroundhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtah_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lrounduhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtah_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lrounduhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtah_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lrounduhfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtmh_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfloorhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtmh_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfloorhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtmh_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfloorhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtmh_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lflooruhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtmh_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lflooruhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtmh_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lflooruhfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtnh_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtnh_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtnh_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtnh_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnuhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtnh_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnuhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtnh_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnuhfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtph_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceilhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtph_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceilhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtph_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceilhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtph_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceiluhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtph_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceiluhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtph_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceiluhfdi_us (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vnegh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_neghf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrecpeh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_frecpehf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrecpxh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_frecpxhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_btrunchf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndah_f16 (float16_t __a)
++{
++  return __builtin_aarch64_roundhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndih_f16 (float16_t __a)
++{
++  return __builtin_aarch64_nearbyinthf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndmh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_floorhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndnh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_frintnhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndph_f16 (float16_t __a)
++{
++  return __builtin_aarch64_ceilhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndxh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_rinthf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrsqrteh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_rsqrtehf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsqrth_f16 (float16_t __a)
++{
++  return __builtin_aarch64_sqrthf (__a);
++}
++
++/* ARMv8.2-A FP16 two operands scalar intrinsics.  */
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vaddh_f16 (float16_t __a, float16_t __b)
++{
++  return __a + __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vabdh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fabdhf (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcageh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_facgehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcagth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_facgthf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcaleh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_faclehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcalth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_faclthf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vceqh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmeqhf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgeh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmgehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmgthf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcleh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmlehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vclth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmlthf_uss (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s16 (int16_t __a, const int __b)
++{
++  return __builtin_aarch64_scvtfhi (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s32 (int32_t __a, const int __b)
++{
++  return __builtin_aarch64_scvtfsihf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s64 (int64_t __a, const int __b)
++{
++  return __builtin_aarch64_scvtfdihf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u16 (uint16_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfhi_sus (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u32 (uint32_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfsihf_sus (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u64 (uint64_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfdihf_sus (__a, __b);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvth_n_s16_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzshf (__a, __b);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_n_s32_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzshfsi (__a, __b);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvth_n_s64_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzshfdi (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvth_n_u16_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzuhf_uss (__a, __b);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_n_u32_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzuhfsi_uss (__a, __b);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvth_n_u64_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzuhfdi_uss (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vdivh_f16 (float16_t __a, float16_t __b)
++{
++  return __a / __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmaxh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fmaxhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmaxnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fmaxhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vminh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fminhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vminnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fminhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmulh_f16 (float16_t __a, float16_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmulxh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fmulxhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrecpsh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_frecpshf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrsqrtsh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_rsqrtshf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsubh_f16 (float16_t __a, float16_t __b)
++{
++  return __a - __b;
++}
++
++/* ARMv8.2-A FP16 three operands scalar intrinsics.  */
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmah_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_aarch64_fmahf (__b, __c, __a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmsh_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_aarch64_fnmahf (__b, __c, __a);
++}
++
++#pragma GCC pop_options
++
++#endif
+--- a/src/gcc/config/aarch64/arm_neon.h
++++ b/src/gcc/config/aarch64/arm_neon.h
+@@ -58,6 +58,7 @@ typedef __Float64x2_t float64x2_t;
+ typedef __Poly8x16_t poly8x16_t;
+ typedef __Poly16x8_t poly16x8_t;
+ typedef __Poly64x2_t poly64x2_t;
++typedef __Poly64x1_t poly64x1_t;
+ typedef __Uint8x16_t uint8x16_t;
+ typedef __Uint16x8_t uint16x8_t;
+ typedef __Uint32x4_t uint32x4_t;
+@@ -202,6 +203,36 @@ typedef struct poly16x8x2_t
+   poly16x8_t val[2];
+ } poly16x8x2_t;
+ 
++typedef struct poly64x1x2_t
++{
++  poly64x1_t val[2];
++} poly64x1x2_t;
++
++typedef struct poly64x1x3_t
++{
++  poly64x1_t val[3];
++} poly64x1x3_t;
++
++typedef struct poly64x1x4_t
++{
++  poly64x1_t val[4];
++} poly64x1x4_t;
++
++typedef struct poly64x2x2_t
++{
++  poly64x2_t val[2];
++} poly64x2x2_t;
++
++typedef struct poly64x2x3_t
++{
++  poly64x2_t val[3];
++} poly64x2x3_t;
++
++typedef struct poly64x2x4_t
++{
++  poly64x2_t val[4];
++} poly64x2x4_t;
++
+ typedef struct int8x8x3_t
+ {
+   int8x8_t val[3];
+@@ -466,6 +497,8 @@ typedef struct poly16x8x4_t
+ #define __aarch64_vdup_lane_any(__size, __q, __a, __b) \
+   vdup##__q##_n_##__size (__aarch64_vget_lane_any (__a, __b))
+ 
++#define __aarch64_vdup_lane_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, , __a, __b)
+ #define __aarch64_vdup_lane_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, , __a, __b)
+ #define __aarch64_vdup_lane_f64(__a, __b) \
+@@ -474,6 +507,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, , __a, __b)
+ #define __aarch64_vdup_lane_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, , __a, __b)
++#define __aarch64_vdup_lane_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, , __a, __b)
+ #define __aarch64_vdup_lane_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, , __a, __b)
+ #define __aarch64_vdup_lane_s16(__a, __b) \
+@@ -492,6 +527,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (u64, , __a, __b)
+ 
+ /* __aarch64_vdup_laneq internal macros.  */
++#define __aarch64_vdup_laneq_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, , __a, __b)
+ #define __aarch64_vdup_laneq_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, , __a, __b)
+ #define __aarch64_vdup_laneq_f64(__a, __b) \
+@@ -500,6 +537,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, , __a, __b)
+ #define __aarch64_vdup_laneq_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, , __a, __b)
++#define __aarch64_vdup_laneq_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, , __a, __b)
+ #define __aarch64_vdup_laneq_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, , __a, __b)
+ #define __aarch64_vdup_laneq_s16(__a, __b) \
+@@ -518,6 +557,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (u64, , __a, __b)
+ 
+ /* __aarch64_vdupq_lane internal macros.  */
++#define __aarch64_vdupq_lane_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, q, __a, __b)
+ #define __aarch64_vdupq_lane_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, q, __a, __b)
+ #define __aarch64_vdupq_lane_f64(__a, __b) \
+@@ -526,6 +567,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, q, __a, __b)
+ #define __aarch64_vdupq_lane_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, q, __a, __b)
++#define __aarch64_vdupq_lane_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, q, __a, __b)
+ #define __aarch64_vdupq_lane_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, q, __a, __b)
+ #define __aarch64_vdupq_lane_s16(__a, __b) \
+@@ -544,6 +587,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (u64, q, __a, __b)
+ 
+ /* __aarch64_vdupq_laneq internal macros.  */
++#define __aarch64_vdupq_laneq_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, q, __a, __b)
+ #define __aarch64_vdupq_laneq_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, q, __a, __b)
+ #define __aarch64_vdupq_laneq_f64(__a, __b) \
+@@ -552,6 +597,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, q, __a, __b)
+ #define __aarch64_vdupq_laneq_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, q, __a, __b)
++#define __aarch64_vdupq_laneq_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, q, __a, __b)
+ #define __aarch64_vdupq_laneq_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, q, __a, __b)
+ #define __aarch64_vdupq_laneq_s16(__a, __b) \
+@@ -601,535 +648,619 @@ typedef struct poly16x8x4_t
+   })
+ 
+ /* vadd  */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddlv8qi ((int8x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddlv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddlv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddl2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddl2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddl2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddl2v16qi ((int8x16_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddl2v8hi ((int16x8_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddl2v4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddwv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddwv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddwv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddwv8qi ((int16x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddwv4hi ((int32x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddwv2si ((int64x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_s8 (int16x8_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddw2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_s16 (int32x4_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddw2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_s32 (int64x2_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddw2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_u8 (uint16x8_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddw2v16qi ((int16x8_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_u16 (uint32x4_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddw2v8hi ((int32x4_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_u32 (uint64x2_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddw2v4si ((int64x2_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_shaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_shaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_shaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_uhaddv8qi ((int8x8_t) __a,
+ 						  (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_uhaddv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_uhaddv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_shaddv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_shaddv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_shaddv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_uhaddv16qi ((int8x16_t) __a,
+ 						    (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uhaddv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uhaddv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_srhaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_srhaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_srhaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_urhaddv8qi ((int8x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_urhaddv4hi ((int16x4_t) __a,
+ 						    (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_urhaddv2si ((int32x2_t) __a,
+ 						    (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_srhaddv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_srhaddv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_srhaddv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_urhaddv16qi ((int8x16_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_urhaddv8hi ((int16x8_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_urhaddv4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_addhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_addhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_addhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_addhnv8hi ((int16x8_t) __a,
+ 						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_addhnv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_addhnv2di ((int64x2_t) __a,
+ 						   (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_raddhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_raddhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_raddhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_raddhnv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_raddhnv4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_raddhnv2di ((int64x2_t) __a,
+ 						    (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_addhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_addhn2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_addhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_addhn2v8hi ((int8x8_t) __a,
+@@ -1137,7 +1268,8 @@ vaddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						    (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_addhn2v4si ((int16x4_t) __a,
+@@ -1145,7 +1277,8 @@ vaddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						    (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_addhn2v2di ((int32x2_t) __a,
+@@ -1153,25 +1286,29 @@ vaddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						    (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_raddhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_raddhn2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_raddhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_raddhn2v8hi ((int8x8_t) __a,
+@@ -1179,7 +1316,8 @@ vraddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						     (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_raddhn2v4si ((int16x4_t) __a,
+@@ -1187,7 +1325,8 @@ vraddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						     (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_raddhn2v2di ((int32x2_t) __a,
+@@ -1195,1101 +1334,1280 @@ vraddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						     (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdiv_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdiv_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdivq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdivq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x8_t) __builtin_aarch64_pmulv8qi ((int8x8_t) __a,
+ 						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (poly8x16_t) __builtin_aarch64_pmulv16qi ((int8x16_t) __a,
+ 						   (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssublv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssublv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssublv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usublv8qi ((int8x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usublv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usublv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssubl2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssubl2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssubl2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usubl2v16qi ((int8x16_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usubl2v8hi ((int16x8_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usubl2v4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssubwv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssubwv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssubwv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usubwv8qi ((int16x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usubwv4hi ((int32x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usubwv2si ((int64x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_s8 (int16x8_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssubw2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_s16 (int32x4_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssubw2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_s32 (int64x2_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssubw2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_u8 (uint16x8_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usubw2v16qi ((int16x8_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_u16 (uint32x4_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usubw2v8hi ((int32x4_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_u32 (uint64x2_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usubw2v4si ((int64x2_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_sqaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqadddi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __builtin_aarch64_uqaddv8qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_aarch64_shsubv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_shsubv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_shsubv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_uhsubv8qi ((int8x8_t) __a,
+ 						  (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_uhsubv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_uhsubv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_shsubv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_shsubv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_shsubv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_uhsubv16qi ((int8x16_t) __a,
+ 						    (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uhsubv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uhsubv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_subhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_subhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_subhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_subhnv8hi ((int16x8_t) __a,
+ 						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_subhnv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_subhnv2di ((int64x2_t) __a,
+ 						   (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_rsubhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_rsubhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_rsubhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_rsubhnv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_rsubhnv4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_rsubhnv2di ((int64x2_t) __a,
+ 						    (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_rsubhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_rsubhn2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_rsubhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_rsubhn2v8hi ((int8x8_t) __a,
+@@ -2297,7 +2615,8 @@ vrsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						     (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_rsubhn2v4si ((int16x4_t) __a,
+@@ -2305,7 +2624,8 @@ vrsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						     (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_rsubhn2v2di ((int32x2_t) __a,
+@@ -2313,25 +2633,29 @@ vrsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						     (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_subhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_subhn2v4si (__a, __b, __c);;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_subhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_subhn2v8hi ((int8x8_t) __a,
+@@ -2339,7 +2663,8 @@ vsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						    (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_subhn2v4si ((int16x4_t) __a,
+@@ -2347,7 +2672,8 @@ vsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						    (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_subhn2v2di ((int32x2_t) __a,
+@@ -2355,453 +2681,542 @@ vsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						    (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __builtin_aarch64_uqaddv4hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __builtin_aarch64_uqaddv2si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t) {__builtin_aarch64_uqadddi_uuu (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_sqaddv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqaddv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqaddv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_sqaddv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __builtin_aarch64_uqaddv16qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __builtin_aarch64_uqaddv8hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __builtin_aarch64_uqaddv4si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __builtin_aarch64_uqaddv2di_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_sqsubv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqsubv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqsubv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqsubdi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __builtin_aarch64_uqsubv8qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __builtin_aarch64_uqsubv4hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __builtin_aarch64_uqsubv2si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t) {__builtin_aarch64_uqsubdi_uuu (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_sqsubv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqsubv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqsubv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_sqsubv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __builtin_aarch64_uqsubv16qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __builtin_aarch64_uqsubv8hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __builtin_aarch64_uqsubv4si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __builtin_aarch64_uqsubv2di_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_aarch64_sqnegv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_aarch64_sqnegv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s32 (int32x2_t __a)
+ {
+   return (int32x2_t) __builtin_aarch64_sqnegv2si (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s64 (int64x1_t __a)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqnegdi (__a[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_aarch64_sqnegv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_aarch64_sqnegv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t) __builtin_aarch64_sqnegv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_aarch64_sqabsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_aarch64_sqabsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s32 (int32x2_t __a)
+ {
+   return (int32x2_t) __builtin_aarch64_sqabsv2si (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s64 (int64x1_t __a)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqabsdi (__a[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_aarch64_sqabsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_aarch64_sqabsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t) __builtin_aarch64_sqabsv4si (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqdmulhv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqrdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqrdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqrdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqrdmulhv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s8 (uint64_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s16 (uint64_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s32 (uint64_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s64 (uint64_t __a)
+ {
+   return (int64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f16 (uint64_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f32 (uint64_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u8 (uint64_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u16 (uint64_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u32 (uint64_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u64 (uint64_t __a)
+ {
+   return (uint64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f64 (uint64_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p8 (uint64_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p16 (uint64_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcreate_p64 (uint64_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
+ /* vget_lane  */
+ 
+-__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f16 (float16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f64 (float64x1_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vget_lane_p64 (poly64x1_t __a, const int __b)
++{
++  return __aarch64_vget_lane_any (__a, __b);
++}
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+@@ -2809,79 +3224,99 @@ vget_lane_u64 (uint64x1_t __a, const int __b)
+ 
+ /* vgetq_lane  */
+ 
+-__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f16 (float16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f32 (float32x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f64 (float64x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p8 (poly8x16_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p16 (poly16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vgetq_lane_p64 (poly64x2_t __a, const int __b)
++{
++  return __aarch64_vget_lane_any (__a, __b);
++}
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s8 (int8x16_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s16 (int16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s32 (int32x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s64 (int64x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u8 (uint8x16_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u16 (uint16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u32 (uint32x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u64 (uint64x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+@@ -2889,1953 +3324,2832 @@ vgetq_lane_u64 (uint64x2_t __a, const int __b)
+ 
+ /* vreinterpret  */
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f16 (float16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f64 (float64x1_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s8 (int8x8_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s16 (int16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s32 (int32x2_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s64 (int64x1_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f32 (float32x2_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u8 (uint8x8_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u16 (uint16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u32 (uint32x2_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u64 (uint64x1_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_p16 (poly16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p8_p64 (poly64x1_t __a)
++{
++  return (poly8x8_t) __a;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f64 (float64x2_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s8 (int8x16_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s16 (int16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s32 (int32x4_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s64 (int64x2_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f16 (float16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f32 (float32x4_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u8 (uint8x16_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u16 (uint16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u32 (uint32x4_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u64 (uint64x2_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p16 (poly16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p8_p64 (poly64x2_t __a)
++{
++  return (poly8x16_t) __a;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p8_p128 (poly128_t __a)
++{
++  return (poly8x16_t)__a;
++}
++
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f16 (float16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f64 (float64x1_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s8 (int8x8_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s16 (int16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s32 (int32x2_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s64 (int64x1_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f32 (float32x2_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u8 (uint8x8_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u16 (uint16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u32 (uint32x2_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u64 (uint64x1_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_p8 (poly8x8_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p16_p64 (poly64x1_t __a)
++{
++  return (poly16x4_t) __a;
++}
++
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f64 (float64x2_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s8 (int8x16_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s16 (int16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s32 (int32x4_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s64 (int64x2_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f16 (float16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f32 (float32x4_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u8 (uint8x16_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u16 (uint16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u32 (uint32x4_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u64 (uint64x2_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p8 (poly8x16_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p16_p64 (poly64x2_t __a)
++{
++  return (poly16x8_t) __a;
++}
++
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p16_p128 (poly128_t __a)
++{
++  return (poly16x8_t)__a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_f16 (float16x4_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_f64 (float64x1_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s8 (int8x8_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s16 (int16x4_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s32 (int32x2_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s64 (int64x1_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_f32 (float32x2_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u8 (uint8x8_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u16 (uint16x4_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u32 (uint32x2_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u64 (uint64x1_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_p8 (poly8x8_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_p16 (poly16x4_t __a)
++{
++  return (poly64x1_t)__a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_f64 (float64x2_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s8 (int8x16_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s16 (int16x8_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s32 (int32x4_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s64 (int64x2_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_f16 (float16x8_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_f32 (float32x4_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_p128 (poly128_t __a)
++{
++  return (poly64x2_t)__a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u8 (uint8x16_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u16 (uint16x8_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_p16 (poly16x8_t __a)
++{
++  return (poly64x2_t)__a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u32 (uint32x4_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u64 (uint64x2_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_p8 (poly8x16_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_p8 (poly8x16_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_p16 (poly16x8_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_f16 (float16x8_t __a)
++{
++  return (poly128_t) __a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_f32 (float32x4_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_p64 (poly64x2_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s64 (int64x2_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u64 (uint64x2_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s8 (int8x16_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s16 (int16x8_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s32 (int32x4_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u8 (uint8x16_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u16 (uint16x8_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u32 (uint32x4_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_f64 (float64x1_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s8 (int8x8_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s16 (int16x4_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s32 (int32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s64 (int64x1_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_f32 (float32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u8 (uint8x8_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u16 (uint16x4_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u32 (uint32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u64 (uint64x1_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p8 (poly8x8_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p16 (poly16x4_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_f16_p64 (poly64x1_t __a)
++{
++  return (float16x4_t) __a;
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_f64 (float64x2_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s8 (int8x16_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s16 (int16x8_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s32 (int32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s64 (int64x2_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_f32 (float32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u8 (uint8x16_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u16 (uint16x8_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u32 (uint32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u64 (uint64x2_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p8 (poly8x16_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f16_p128 (poly128_t __a)
++{
++  return (float16x8_t) __a;
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p16 (poly16x8_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f16_p64 (poly64x2_t __a)
++{
++  return (float16x8_t) __a;
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_f16 (float16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_f64 (float64x1_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s8 (int8x8_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s16 (int16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s32 (int32x2_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s64 (int64x1_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u8 (uint8x8_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u16 (uint16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u32 (uint32x2_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u64 (uint64x1_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p8 (poly8x8_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p16 (poly16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_f32_p64 (poly64x1_t __a)
++{
++  return (float32x2_t) __a;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_f16 (float16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_f64 (float64x2_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s8 (int8x16_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s16 (int16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s32 (int32x4_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s64 (int64x2_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u8 (uint8x16_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u16 (uint16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u32 (uint32x4_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u64 (uint64x2_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p8 (poly8x16_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p16 (poly16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f32_p64 (poly64x2_t __a)
++{
++  return (float32x4_t) __a;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f32_p128 (poly128_t __a)
++{
++  return (float32x4_t)__a;
++}
++
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_f16 (float16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_f32 (float32x2_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_p8 (poly8x8_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_p16 (poly16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_f64_p64 (poly64x1_t __a)
++{
++  return (float64x1_t) __a;
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s8 (int8x8_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s16 (int16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s32 (int32x2_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s64 (int64x1_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u8 (uint8x8_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u16 (uint16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u32 (uint32x2_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u64 (uint64x1_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_f16 (float16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_f32 (float32x4_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_p8 (poly8x16_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_p16 (poly16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f64_p64 (poly64x2_t __a)
++{
++  return (float64x2_t) __a;
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s8 (int8x16_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s16 (int16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s32 (int32x4_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s64 (int64x2_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u8 (uint8x16_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u16 (uint16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u32 (uint32x4_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u64 (uint64x2_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f16 (float16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f64 (float64x1_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s8 (int8x8_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s16 (int16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s32 (int32x2_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f32 (float32x2_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u8 (uint8x8_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u16 (uint16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u32 (uint32x2_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u64 (uint64x1_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p8 (poly8x8_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p16 (poly16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s64_p64 (poly64x1_t __a)
++{
++  return (int64x1_t) __a;
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f64 (float64x2_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s8 (int8x16_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s16 (int16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s32 (int32x4_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f16 (float16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f32 (float32x4_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u8 (uint8x16_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u16 (uint16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u32 (uint32x4_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u64 (uint64x2_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p8 (poly8x16_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p16 (poly16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s64_p64 (poly64x2_t __a)
++{
++  return (int64x2_t) __a;
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s64_p128 (poly128_t __a)
++{
++  return (int64x2_t)__a;
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f16 (float16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f64 (float64x1_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s8 (int8x8_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s16 (int16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s32 (int32x2_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s64 (int64x1_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f32 (float32x2_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u8 (uint8x8_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u16 (uint16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u32 (uint32x2_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p8 (poly8x8_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p16 (poly16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u64_p64 (poly64x1_t __a)
++{
++  return (uint64x1_t) __a;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f64 (float64x2_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s8 (int8x16_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s16 (int16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s32 (int32x4_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s64 (int64x2_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f16 (float16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f32 (float32x4_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u8 (uint8x16_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u16 (uint16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u32 (uint32x4_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p8 (poly8x16_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p16 (poly16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u64_p64 (poly64x2_t __a)
++{
++  return (uint64x2_t) __a;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u64_p128 (poly128_t __a)
++{
++  return (uint64x2_t)__a;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f16 (float16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f64 (float64x1_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s16 (int16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s32 (int32x2_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s64 (int64x1_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f32 (float32x2_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u8 (uint8x8_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u16 (uint16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u32 (uint32x2_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u64 (uint64x1_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p8 (poly8x8_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p16 (poly16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s8_p64 (poly64x1_t __a)
++{
++  return (int8x8_t) __a;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f64 (float64x2_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s16 (int16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s32 (int32x4_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s64 (int64x2_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f16 (float16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f32 (float32x4_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u8 (uint8x16_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u16 (uint16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u32 (uint32x4_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u64 (uint64x2_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p8 (poly8x16_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p16 (poly16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s8_p64 (poly64x2_t __a)
++{
++  return (int8x16_t) __a;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s8_p128 (poly128_t __a)
++{
++  return (int8x16_t)__a;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f16 (float16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f64 (float64x1_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s8 (int8x8_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s32 (int32x2_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s64 (int64x1_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f32 (float32x2_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u8 (uint8x8_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u16 (uint16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u32 (uint32x2_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u64 (uint64x1_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p8 (poly8x8_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p16 (poly16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s16_p64 (poly64x1_t __a)
++{
++  return (int16x4_t) __a;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f64 (float64x2_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s8 (int8x16_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s32 (int32x4_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s64 (int64x2_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f16 (float16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f32 (float32x4_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u8 (uint8x16_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u16 (uint16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u32 (uint32x4_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u64 (uint64x2_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p8 (poly8x16_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p16 (poly16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s16_p64 (poly64x2_t __a)
++{
++  return (int16x8_t) __a;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s16_p128 (poly128_t __a)
++{
++  return (int16x8_t)__a;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f16 (float16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f64 (float64x1_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s8 (int8x8_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s16 (int16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s64 (int64x1_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f32 (float32x2_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u8 (uint8x8_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u16 (uint16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u32 (uint32x2_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u64 (uint64x1_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p8 (poly8x8_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p16 (poly16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s32_p64 (poly64x1_t __a)
++{
++  return (int32x2_t) __a;
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f64 (float64x2_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s8 (int8x16_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s16 (int16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s64 (int64x2_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f16 (float16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f32 (float32x4_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u8 (uint8x16_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u16 (uint16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u32 (uint32x4_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u64 (uint64x2_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p8 (poly8x16_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p16 (poly16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s32_p64 (poly64x2_t __a)
++{
++  return (int32x4_t) __a;
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s32_p128 (poly128_t __a)
++{
++  return (int32x4_t)__a;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f16 (float16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f64 (float64x1_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s8 (int8x8_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s16 (int16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s32 (int32x2_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s64 (int64x1_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f32 (float32x2_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u16 (uint16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u32 (uint32x2_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u64 (uint64x1_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p8 (poly8x8_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p16 (poly16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u8_p64 (poly64x1_t __a)
++{
++  return (uint8x8_t) __a;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f64 (float64x2_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s8 (int8x16_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s16 (int16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s32 (int32x4_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s64 (int64x2_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f16 (float16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f32 (float32x4_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u16 (uint16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u32 (uint32x4_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u64 (uint64x2_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p8 (poly8x16_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p16 (poly16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u8_p64 (poly64x2_t __a)
++{
++  return (uint8x16_t) __a;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u8_p128 (poly128_t __a)
++{
++  return (uint8x16_t)__a;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f16 (float16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f64 (float64x1_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s8 (int8x8_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s16 (int16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s32 (int32x2_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s64 (int64x1_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f32 (float32x2_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u8 (uint8x8_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u32 (uint32x2_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u64 (uint64x1_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p8 (poly8x8_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p16 (poly16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u16_p64 (poly64x1_t __a)
++{
++  return (uint16x4_t) __a;
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f64 (float64x2_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s8 (int8x16_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s16 (int16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s32 (int32x4_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s64 (int64x2_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f16 (float16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f32 (float32x4_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u8 (uint8x16_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u32 (uint32x4_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u64 (uint64x2_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p8 (poly8x16_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p16 (poly16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u16_p64 (poly64x2_t __a)
++{
++  return (uint16x8_t) __a;
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u16_p128 (poly128_t __a)
++{
++  return (uint16x8_t)__a;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f16 (float16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f64 (float64x1_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s8 (int8x8_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s16 (int16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s32 (int32x2_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s64 (int64x1_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f32 (float32x2_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u8 (uint8x8_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u16 (uint16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u64 (uint64x1_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p8 (poly8x8_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p16 (poly16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u32_p64 (poly64x1_t __a)
++{
++  return (uint32x2_t) __a;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f64 (float64x2_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s8 (int8x16_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s16 (int16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s32 (int32x4_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s64 (int64x2_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f16 (float16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f32 (float32x4_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u8 (uint8x16_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u16 (uint16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u64 (uint64x2_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p8 (poly8x16_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p16 (poly16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u32_p64 (poly64x2_t __a)
++{
++  return (uint32x4_t) __a;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u32_p128 (poly128_t __a)
++{
++  return (uint32x4_t)__a;
++}
++
+ /* vset_lane  */
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f16 (float16_t __elem, float16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f32 (float32_t __elem, float32x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f64 (float64_t __elem, float64x1_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p8 (poly8_t __elem, poly8x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p16 (poly16_t __elem, poly16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vset_lane_p64 (poly64_t __elem, poly64x1_t __vec, const int __index)
++{
++  return __aarch64_vset_lane_any (__elem, __vec, __index);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s8 (int8_t __elem, int8x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s16 (int16_t __elem, int16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s32 (int32_t __elem, int32x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s64 (int64_t __elem, int64x1_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u8 (uint8_t __elem, uint8x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u16 (uint16_t __elem, uint16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u32 (uint32_t __elem, uint32x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u64 (uint64_t __elem, uint64x1_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+@@ -4843,79 +6157,99 @@ vset_lane_u64 (uint64_t __elem, uint64x1_t __vec, const int __index)
+ 
+ /* vsetq_lane  */
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f16 (float16_t __elem, float16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f32 (float32_t __elem, float32x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f64 (float64_t __elem, float64x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p8 (poly8_t __elem, poly8x16_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p16 (poly16_t __elem, poly16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsetq_lane_p64 (poly64_t __elem, poly64x2_t __vec, const int __index)
++{
++  return __aarch64_vset_lane_any (__elem, __vec, __index);
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s8 (int8_t __elem, int8x16_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s16 (int16_t __elem, int16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s32 (int32_t __elem, int32x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s64 (int64_t __elem, int64x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u8 (uint8_t __elem, uint8x16_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u16 (uint16_t __elem, uint16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u32 (uint32_t __elem, uint32x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u64 (uint64_t __elem, uint64x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+@@ -4926,79 +6260,99 @@ vsetq_lane_u64 (uint64_t __elem, uint64x2_t __vec, const int __index)
+   uint64x1_t lo = vcreate_u64 (vgetq_lane_u64 (tmp, 0));  \
+   return vreinterpret_##__TYPE##_u64 (lo);
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f16 (float16x8_t __a)
+ {
+   __GET_LOW (f16);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f32 (float32x4_t __a)
+ {
+   __GET_LOW (f32);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f64 (float64x2_t __a)
+ {
+   return (float64x1_t) {vgetq_lane_f64 (__a, 0)};
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p8 (poly8x16_t __a)
+ {
+   __GET_LOW (p8);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p16 (poly16x8_t __a)
+ {
+   __GET_LOW (p16);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vget_low_p64 (poly64x2_t __a)
++{
++  __GET_LOW (p64);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s8 (int8x16_t __a)
+ {
+   __GET_LOW (s8);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s16 (int16x8_t __a)
+ {
+   __GET_LOW (s16);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s32 (int32x4_t __a)
+ {
+   __GET_LOW (s32);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s64 (int64x2_t __a)
+ {
+   __GET_LOW (s64);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u8 (uint8x16_t __a)
+ {
+   __GET_LOW (u8);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u16 (uint16x8_t __a)
+ {
+   __GET_LOW (u16);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u32 (uint32x4_t __a)
+ {
+   __GET_LOW (u32);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u64 (uint64x2_t __a)
+ {
+   return vcreate_u64 (vgetq_lane_u64 (__a, 0));
+@@ -5011,73 +6365,92 @@ vget_low_u64 (uint64x2_t __a)
+   uint64x1_t hi = vcreate_u64 (vgetq_lane_u64 (tmp, 1));	\
+   return vreinterpret_##__TYPE##_u64 (hi);
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f16 (float16x8_t __a)
+ {
+   __GET_HIGH (f16);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f32 (float32x4_t __a)
+ {
+   __GET_HIGH (f32);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f64 (float64x2_t __a)
+ {
+   __GET_HIGH (f64);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p8 (poly8x16_t __a)
+ {
+   __GET_HIGH (p8);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p16 (poly16x8_t __a)
+ {
+   __GET_HIGH (p16);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vget_high_p64 (poly64x2_t __a)
++{
++  __GET_HIGH (p64);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s8 (int8x16_t __a)
+ {
+   __GET_HIGH (s8);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s16 (int16x8_t __a)
+ {
+   __GET_HIGH (s16);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s32 (int32x4_t __a)
+ {
+   __GET_HIGH (s32);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s64 (int64x2_t __a)
+ {
+   __GET_HIGH (s64);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u8 (uint8x16_t __a)
+ {
+   __GET_HIGH (u8);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u16 (uint16x8_t __a)
+ {
+   __GET_HIGH (u16);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u32 (uint32x4_t __a)
+ {
+   __GET_HIGH (u32);
+@@ -5085,98 +6458,120 @@ vget_high_u32 (uint32x4_t __a)
+ 
+ #undef __GET_HIGH
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u64 (uint64x2_t __a)
+ {
+   return vcreate_u64 (vgetq_lane_u64 (__a, 1));
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_combinev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_combinev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_combinev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __builtin_aarch64_combinedi (__a[0], __b[0]);
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f16 (float16x4_t __a, float16x4_t __b)
+ {
+   return __builtin_aarch64_combinev4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x4_t) __builtin_aarch64_combinev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_combinev8qi ((int8x8_t) __a,
+ 						     (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_combinev4hi ((int16x4_t) __a,
+ 						     (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_combinev2si ((int32x2_t) __a,
+ 						     (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_combinedi (__a[0], __b[0]);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __builtin_aarch64_combinedf (__a[0], __b[0]);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x16_t) __builtin_aarch64_combinev8qi ((int8x8_t) __a,
+ 						     (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   return (poly16x8_t) __builtin_aarch64_combinev4hi ((int16x4_t) __a,
+ 						     (int16x4_t) __b);
+ }
+ 
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcombine_p64 (poly64x1_t __a, poly64x1_t __b)
++{
++  return (poly64x2_t) __builtin_aarch64_combinedi_ppp (__a[0], __b[0]);
++}
++
+ /* Start of temporary inline asm implementations.  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
+ {
+   int8x8_t result;
+@@ -5187,7 +6582,8 @@ vaba_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
+ {
+   int16x4_t result;
+@@ -5198,7 +6594,8 @@ vaba_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
+ {
+   int32x2_t result;
+@@ -5209,7 +6606,8 @@ vaba_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+   uint8x8_t result;
+@@ -5220,7 +6618,8 @@ vaba_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ {
+   uint16x4_t result;
+@@ -5231,7 +6630,8 @@ vaba_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ {
+   uint32x2_t result;
+@@ -5242,7 +6642,8 @@ vaba_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
+ {
+   int16x8_t result;
+@@ -5253,7 +6654,8 @@ vabal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+ {
+   int32x4_t result;
+@@ -5264,7 +6666,8 @@ vabal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+ {
+   int64x2_t result;
+@@ -5275,7 +6678,8 @@ vabal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint16x8_t result;
+@@ -5286,7 +6690,8 @@ vabal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint32x4_t result;
+@@ -5297,7 +6702,8 @@ vabal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint64x2_t result;
+@@ -5308,7 +6714,8 @@ vabal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+ {
+   int16x8_t result;
+@@ -5319,7 +6726,8 @@ vabal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+ {
+   int32x4_t result;
+@@ -5330,7 +6738,8 @@ vabal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+ {
+   int64x2_t result;
+@@ -5341,7 +6750,8 @@ vabal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+   uint16x8_t result;
+@@ -5352,7 +6762,8 @@ vabal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ {
+   uint32x4_t result;
+@@ -5363,7 +6774,8 @@ vabal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ {
+   uint64x2_t result;
+@@ -5374,7 +6786,8 @@ vabal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+ {
+   int8x16_t result;
+@@ -5385,7 +6798,8 @@ vabaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+ {
+   int16x8_t result;
+@@ -5396,7 +6810,8 @@ vabaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+ {
+   int32x4_t result;
+@@ -5407,7 +6822,8 @@ vabaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint8x16_t result;
+@@ -5418,7 +6834,8 @@ vabaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint16x8_t result;
+@@ -5429,7 +6846,8 @@ vabaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint32x4_t result;
+@@ -5440,18 +6858,8 @@ vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vabd_f32 (float32x2_t a, float32x2_t b)
+-{
+-  float32x2_t result;
+-  __asm__ ("fabd %0.2s, %1.2s, %2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s8 (int8x8_t a, int8x8_t b)
+ {
+   int8x8_t result;
+@@ -5462,7 +6870,8 @@ vabd_s8 (int8x8_t a, int8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s16 (int16x4_t a, int16x4_t b)
+ {
+   int16x4_t result;
+@@ -5473,7 +6882,8 @@ vabd_s16 (int16x4_t a, int16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s32 (int32x2_t a, int32x2_t b)
+ {
+   int32x2_t result;
+@@ -5484,7 +6894,8 @@ vabd_s32 (int32x2_t a, int32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u8 (uint8x8_t a, uint8x8_t b)
+ {
+   uint8x8_t result;
+@@ -5495,7 +6906,8 @@ vabd_u8 (uint8x8_t a, uint8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u16 (uint16x4_t a, uint16x4_t b)
+ {
+   uint16x4_t result;
+@@ -5506,7 +6918,8 @@ vabd_u16 (uint16x4_t a, uint16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u32 (uint32x2_t a, uint32x2_t b)
+ {
+   uint32x2_t result;
+@@ -5517,18 +6930,8 @@ vabd_u32 (uint32x2_t a, uint32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vabdd_f64 (float64_t a, float64_t b)
+-{
+-  float64_t result;
+-  __asm__ ("fabd %d0, %d1, %d2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_s8 (int8x16_t a, int8x16_t b)
+ {
+   int16x8_t result;
+@@ -5539,7 +6942,8 @@ vabdl_high_s8 (int8x16_t a, int8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_s16 (int16x8_t a, int16x8_t b)
+ {
+   int32x4_t result;
+@@ -5550,7 +6954,8 @@ vabdl_high_s16 (int16x8_t a, int16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_s32 (int32x4_t a, int32x4_t b)
+ {
+   int64x2_t result;
+@@ -5561,7 +6966,8 @@ vabdl_high_s32 (int32x4_t a, int32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_u8 (uint8x16_t a, uint8x16_t b)
+ {
+   uint16x8_t result;
+@@ -5572,7 +6978,8 @@ vabdl_high_u8 (uint8x16_t a, uint8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_u16 (uint16x8_t a, uint16x8_t b)
+ {
+   uint32x4_t result;
+@@ -5583,7 +6990,8 @@ vabdl_high_u16 (uint16x8_t a, uint16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_u32 (uint32x4_t a, uint32x4_t b)
+ {
+   uint64x2_t result;
+@@ -5594,7 +7002,8 @@ vabdl_high_u32 (uint32x4_t a, uint32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s8 (int8x8_t a, int8x8_t b)
+ {
+   int16x8_t result;
+@@ -5605,7 +7014,8 @@ vabdl_s8 (int8x8_t a, int8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s16 (int16x4_t a, int16x4_t b)
+ {
+   int32x4_t result;
+@@ -5616,7 +7026,8 @@ vabdl_s16 (int16x4_t a, int16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s32 (int32x2_t a, int32x2_t b)
+ {
+   int64x2_t result;
+@@ -5627,7 +7038,8 @@ vabdl_s32 (int32x2_t a, int32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u8 (uint8x8_t a, uint8x8_t b)
+ {
+   uint16x8_t result;
+@@ -5638,7 +7050,8 @@ vabdl_u8 (uint8x8_t a, uint8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u16 (uint16x4_t a, uint16x4_t b)
+ {
+   uint32x4_t result;
+@@ -5649,7 +7062,8 @@ vabdl_u16 (uint16x4_t a, uint16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u32 (uint32x2_t a, uint32x2_t b)
+ {
+   uint64x2_t result;
+@@ -5660,29 +7074,8 @@ vabdl_u32 (uint32x2_t a, uint32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vabdq_f32 (float32x4_t a, float32x4_t b)
+-{
+-  float32x4_t result;
+-  __asm__ ("fabd %0.4s, %1.4s, %2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vabdq_f64 (float64x2_t a, float64x2_t b)
+-{
+-  float64x2_t result;
+-  __asm__ ("fabd %0.2d, %1.2d, %2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s8 (int8x16_t a, int8x16_t b)
+ {
+   int8x16_t result;
+@@ -5693,7 +7086,8 @@ vabdq_s8 (int8x16_t a, int8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s16 (int16x8_t a, int16x8_t b)
+ {
+   int16x8_t result;
+@@ -5704,7 +7098,8 @@ vabdq_s16 (int16x8_t a, int16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s32 (int32x4_t a, int32x4_t b)
+ {
+   int32x4_t result;
+@@ -5715,7 +7110,8 @@ vabdq_s32 (int32x4_t a, int32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+   uint8x16_t result;
+@@ -5726,7 +7122,8 @@ vabdq_u8 (uint8x16_t a, uint8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u16 (uint16x8_t a, uint16x8_t b)
+ {
+   uint16x8_t result;
+@@ -5737,7 +7134,8 @@ vabdq_u16 (uint16x8_t a, uint16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+   uint32x4_t result;
+@@ -5748,18 +7146,8 @@ vabdq_u32 (uint32x4_t a, uint32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vabds_f32 (float32_t a, float32_t b)
+-{
+-  float32_t result;
+-  __asm__ ("fabd %s0, %s1, %s2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_s8 (int8x8_t a)
+ {
+   int16_t result;
+@@ -5770,7 +7158,8 @@ vaddlv_s8 (int8x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_s16 (int16x4_t a)
+ {
+   int32_t result;
+@@ -5781,7 +7170,8 @@ vaddlv_s16 (int16x4_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_u8 (uint8x8_t a)
+ {
+   uint16_t result;
+@@ -5792,7 +7182,8 @@ vaddlv_u8 (uint8x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_u16 (uint16x4_t a)
+ {
+   uint32_t result;
+@@ -5803,7 +7194,8 @@ vaddlv_u16 (uint16x4_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_s8 (int8x16_t a)
+ {
+   int16_t result;
+@@ -5814,7 +7206,8 @@ vaddlvq_s8 (int8x16_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_s16 (int16x8_t a)
+ {
+   int32_t result;
+@@ -5825,7 +7218,8 @@ vaddlvq_s16 (int16x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_s32 (int32x4_t a)
+ {
+   int64_t result;
+@@ -5836,7 +7230,8 @@ vaddlvq_s32 (int32x4_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_u8 (uint8x16_t a)
+ {
+   uint16_t result;
+@@ -5847,7 +7242,8 @@ vaddlvq_u8 (uint8x16_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_u16 (uint16x8_t a)
+ {
+   uint32_t result;
+@@ -5858,7 +7254,8 @@ vaddlvq_u16 (uint16x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_u32 (uint32x4_t a)
+ {
+   uint64_t result;
+@@ -5869,18584 +7266,23100 @@ vaddlvq_u32 (uint32x4_t a)
+   return result;
+ }
+ 
+-#define vcopyq_lane_f32(a, b, c, d)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32x4_t c_ = (c);                                            \
+-       float32x4_t a_ = (a);                                            \
+-       float32x4_t result;                                              \
+-       __asm__ ("ins %0.s[%2], %3.s[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtx_f32_f64 (float64x2_t a)
++{
++  float32x2_t result;
++  __asm__ ("fcvtxn %0.2s,%1.2d"
++           : "=w"(result)
++           : "w"(a)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtx_high_f32_f64 (float32x2_t a, float64x2_t b)
++{
++  float32x4_t result;
++  __asm__ ("fcvtxn2 %0.4s,%1.2d"
++           : "=w"(result)
++           : "w" (b), "0"(a)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtxd_f32_f64 (float64_t a)
++{
++  float32_t result;
++  __asm__ ("fcvtxn %s0,%d1"
++           : "=w"(result)
++           : "w"(a)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++{
++  float32x2_t result;
++  float32x2_t t1;
++  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fadd %0.2s, %0.2s, %1.2s"
++           : "=w"(result), "=w"(t1)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++{
++  int16x4_t result;
++  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++{
++  int32x2_t result;
++  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++{
++  int8x8_t result;
++  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++{
++  int16x4_t result;
++  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++{
++  int32x2_t result;
++  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++{
++  uint8x8_t result;
++  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcopyq_lane_f64(a, b, c, d)                                     \
++#define vmlal_high_lane_s16(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       float64x2_t c_ = (c);                                            \
+-       float64x2_t a_ = (a);                                            \
+-       float64x2_t result;                                              \
+-       __asm__ ("ins %0.d[%2], %3.d[%4]"                                \
++       int16x4_t c_ = (c);                                              \
++       int16x8_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_p8(a, b, c, d)                                      \
++#define vmlal_high_lane_s32(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       poly8x16_t c_ = (c);                                             \
+-       poly8x16_t a_ = (a);                                             \
+-       poly8x16_t result;                                               \
+-       __asm__ ("ins %0.b[%2], %3.b[%4]"                                \
++       int32x2_t c_ = (c);                                              \
++       int32x4_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_p16(a, b, c, d)                                     \
++#define vmlal_high_lane_u16(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       poly16x8_t c_ = (c);                                             \
+-       poly16x8_t a_ = (a);                                             \
+-       poly16x8_t result;                                               \
+-       __asm__ ("ins %0.h[%2], %3.h[%4]"                                \
++       uint16x4_t c_ = (c);                                             \
++       uint16x8_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_s8(a, b, c, d)                                      \
++#define vmlal_high_lane_u32(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       int8x16_t c_ = (c);                                              \
+-       int8x16_t a_ = (a);                                              \
+-       int8x16_t result;                                                \
+-       __asm__ ("ins %0.b[%2], %3.b[%4]"                                \
++       uint32x2_t c_ = (c);                                             \
++       uint32x4_t b_ = (b);                                             \
++       uint64x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_s16(a, b, c, d)                                     \
++#define vmlal_high_laneq_s16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t c_ = (c);                                              \
+-       int16x8_t a_ = (a);                                              \
+-       int16x8_t result;                                                \
+-       __asm__ ("ins %0.h[%2], %3.h[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vcopyq_lane_s32(a, b, c, d)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t c_ = (c);                                              \
++       int16x8_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("ins %0.s[%2], %3.s[%4]"                                \
++       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_s64(a, b, c, d)                                     \
++#define vmlal_high_laneq_s32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+-       int64x2_t c_ = (c);                                              \
++       int32x4_t c_ = (c);                                              \
++       int32x4_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("ins %0.d[%2], %3.d[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vcopyq_lane_u8(a, b, c, d)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint8x16_t c_ = (c);                                             \
+-       uint8x16_t a_ = (a);                                             \
+-       uint8x16_t result;                                               \
+-       __asm__ ("ins %0.b[%2], %3.b[%4]"                                \
++       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_u16(a, b, c, d)                                     \
++#define vmlal_high_laneq_u16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t c_ = (c);                                             \
+-       uint16x8_t a_ = (a);                                             \
+-       uint16x8_t result;                                               \
+-       __asm__ ("ins %0.h[%2], %3.h[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vcopyq_lane_u32(a, b, c, d)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t c_ = (c);                                             \
++       uint16x8_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("ins %0.s[%2], %3.s[%4]"                                \
++       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_u64(a, b, c, d)                                     \
++#define vmlal_high_laneq_u32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint64x2_t c_ = (c);                                             \
++       uint32x4_t c_ = (c);                                             \
++       uint32x4_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("ins %0.d[%2], %3.d[%4]"                                \
++       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvt_n_f32_s32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t a_ = (a);                                              \
+-       float32x2_t result;                                              \
+-       __asm__ ("scvtf %0.2s, %1.2s, #%2"                               \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
++{
++  int32x4_t result;
++  __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvt_n_f32_u32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t a_ = (a);                                             \
+-       float32x2_t result;                                              \
+-       __asm__ ("ucvtf %0.2s, %1.2s, #%2"                               \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
++{
++  int64x2_t result;
++  __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvt_n_s32_f32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32x2_t a_ = (a);                                            \
+-       int32x2_t result;                                                \
+-       __asm__ ("fcvtzs %0.2s, %1.2s, #%2"                              \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvt_n_u32_f32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32x2_t a_ = (a);                                            \
+-       uint32x2_t result;                                               \
+-       __asm__ ("fcvtzu %0.2s, %1.2s, #%2"                              \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_f64_s64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64_t a_ = (a);                                                \
+-       float64_t result;                                                \
+-       __asm__ ("scvtf %d0,%d1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
++{
++  int16x8_t result;
++  __asm__ ("smlal2 %0.8h,%2.16b,%3.16b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_f64_u64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64_t a_ = (a);                                               \
+-       float64_t result;                                                \
+-       __asm__ ("ucvtf %d0,%d1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
++{
++  int32x4_t result;
++  __asm__ ("smlal2 %0.4s,%2.8h,%3.8h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_s64_f64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float64_t a_ = (a);                                              \
+-       int64_t result;                                                  \
+-       __asm__ ("fcvtzs %d0,%d1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
++{
++  int64x2_t result;
++  __asm__ ("smlal2 %0.2d,%2.4s,%3.4s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_u64_f64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float64_t a_ = (a);                                              \
+-       uint64_t result;                                                 \
+-       __asm__ ("fcvtzu %d0,%d1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
++{
++  uint16x8_t result;
++  __asm__ ("umlal2 %0.8h,%2.16b,%3.16b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal2 %0.4s,%2.8h,%3.8h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal2 %0.2d,%2.4s,%3.4s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtq_n_f32_s32(a, b)                                           \
++#define vmlal_lane_s16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
++       int16x4_t c_ = (c);                                              \
++       int16x4_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+-       float32x4_t result;                                              \
+-       __asm__ ("scvtf %0.4s, %1.4s, #%2"                               \
++       int32x4_t result;                                                \
++       __asm__ ("smlal %0.4s,%2.4h,%3.h[%4]"                            \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_f32_u32(a, b)                                           \
++#define vmlal_lane_s32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x4_t a_ = (a);                                             \
+-       float32x4_t result;                                              \
+-       __asm__ ("ucvtf %0.4s, %1.4s, #%2"                               \
++       int32x2_t c_ = (c);                                              \
++       int32x2_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smlal %0.2d,%2.2s,%3.s[%4]"                            \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_f64_s64(a, b)                                           \
++#define vmlal_lane_u16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+-       int64x2_t a_ = (a);                                              \
+-       float64x2_t result;                                              \
+-       __asm__ ("scvtf %0.2d, %1.2d, #%2"                               \
++       uint16x4_t c_ = (c);                                             \
++       uint16x4_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umlal %0.4s,%2.4h,%3.h[%4]"                            \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_f64_u64(a, b)                                           \
++#define vmlal_lane_u32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
++       uint32x2_t c_ = (c);                                             \
++       uint32x2_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+-       float64x2_t result;                                              \
+-       __asm__ ("ucvtf %0.2d, %1.2d, #%2"                               \
++       uint64x2_t result;                                               \
++       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_s32_f32(a, b)                                           \
++#define vmlal_laneq_s16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float32x4_t a_ = (a);                                            \
++       int16x8_t c_ = (c);                                              \
++       int16x4_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("fcvtzs %0.4s, %1.4s, #%2"                              \
++       __asm__ ("smlal %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_s64_f64(a, b)                                           \
++#define vmlal_laneq_s32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float64x2_t a_ = (a);                                            \
++       int32x4_t c_ = (c);                                              \
++       int32x2_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("fcvtzs %0.2d, %1.2d, #%2"                              \
++       __asm__ ("smlal %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_u32_f32(a, b)                                           \
++#define vmlal_laneq_u16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float32x4_t a_ = (a);                                            \
++       uint16x8_t c_ = (c);                                             \
++       uint16x4_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("fcvtzu %0.4s, %1.4s, #%2"                              \
++       __asm__ ("umlal %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_u64_f64(a, b)                                           \
++#define vmlal_laneq_u32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float64x2_t a_ = (a);                                            \
+-       uint64x2_t result;                                               \
+-       __asm__ ("fcvtzu %0.2d, %1.2d, #%2"                              \
++       uint32x4_t c_ = (c);                                             \
++       uint32x2_t b_ = (b);                                             \
++       uint64x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvts_n_f32_s32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32_t a_ = (a);                                                \
+-       float32_t result;                                                \
+-       __asm__ ("scvtf %s0,%s1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
++{
++  int32x4_t result;
++  __asm__ ("smlal %0.4s,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvts_n_f32_u32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32_t a_ = (a);                                               \
+-       float32_t result;                                                \
+-       __asm__ ("ucvtf %s0,%s1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
++{
++  int64x2_t result;
++  __asm__ ("smlal %0.2d,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvts_n_s32_f32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32_t a_ = (a);                                              \
+-       int32_t result;                                                  \
+-       __asm__ ("fcvtzs %s0,%s1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal %0.4s,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvts_n_u32_f32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32_t a_ = (a);                                              \
+-       uint32_t result;                                                 \
+-       __asm__ ("fcvtzu %s0,%s1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal %0.2d,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvtx_f32_f64 (float64x2_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+ {
+-  float32x2_t result;
+-  __asm__ ("fcvtxn %0.2s,%1.2d"
++  int16x8_t result;
++  __asm__ ("smlal %0.8h,%2.8b,%3.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvtx_high_f32_f64 (float32x2_t a, float64x2_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+ {
+-  float32x4_t result;
+-  __asm__ ("fcvtxn2 %0.4s,%1.2d"
++  int32x4_t result;
++  __asm__ ("smlal %0.4s,%2.4h,%3.4h"
+            : "=w"(result)
+-           : "w" (b), "0"(a)
++           : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vcvtxd_f32_f64 (float64_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+ {
+-  float32_t result;
+-  __asm__ ("fcvtxn %s0,%d1"
++  int64x2_t result;
++  __asm__ ("smlal %0.2d,%2.2s,%3.2s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+-  float32x2_t result;
+-  float32x2_t t1;
+-  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fadd %0.2s, %0.2s, %1.2s"
++  uint16x8_t result;
++  __asm__ ("umlal %0.8h,%2.8b,%3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal %0.4s,%2.4h,%3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal %0.2d,%2.2s,%3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
++{
++  float32x4_t result;
++  float32x4_t t1;
++  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fadd %0.4s, %0.4s, %1.4s"
+            : "=w"(result), "=w"(t1)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
+ {
+-  int16x4_t result;
+-  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++  int16x8_t result;
++  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
+ {
+-  int32x2_t result;
+-  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++  int32x4_t result;
++  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++  uint16x8_t result;
++  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++  uint32x4_t result;
++  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+ {
+-  int8x8_t result;
+-  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++  int8x16_t result;
++  __asm__ ("mla %0.16b, %2.16b, %3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+ {
+-  int16x4_t result;
+-  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++  int16x8_t result;
++  __asm__ ("mla %0.8h, %2.8h, %3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+ {
+-  int32x2_t result;
+-  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++  int32x4_t result;
++  __asm__ ("mla %0.4s, %2.4s, %3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ {
+-  uint8x8_t result;
+-  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++  uint8x16_t result;
++  __asm__ ("mla %0.16b, %2.16b, %3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++  uint16x8_t result;
++  __asm__ ("mla %0.8h, %2.8h, %3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++  uint32x4_t result;
++  __asm__ ("mla %0.4s, %2.4s, %3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlal_high_lane_s16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x4_t c_ = (c);                                              \
+-       int16x8_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmlal_high_lane_s32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t c_ = (c);                                              \
+-       int32x4_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++{
++  float32x2_t result;
++  float32x2_t t1;
++  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fsub %0.2s, %0.2s, %1.2s"
++           : "=w"(result), "=w"(t1)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlal_high_lane_u16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x4_t c_ = (c);                                             \
+-       uint16x8_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++{
++  int16x4_t result;
++  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlal_high_lane_u32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t c_ = (c);                                             \
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++{
++  int32x2_t result;
++  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++{
++  int8x8_t result;
++  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++{
++  int16x4_t result;
++  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++{
++  int32x2_t result;
++  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++{
++  uint8x8_t result;
++  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++#define vmlsl_high_lane_s16(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x4_t c_ = (c);                                              \
++       int16x8_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmlsl_high_lane_s32(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x2_t c_ = (c);                                              \
++       int32x4_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmlsl_high_lane_u16(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x4_t c_ = (c);                                             \
++       uint16x8_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmlsl_high_lane_u32(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x2_t c_ = (c);                                             \
+        uint32x4_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
++       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_s16(a, b, c, d)                                \
++#define vmlsl_high_laneq_s16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t c_ = (c);                                              \
+        int16x8_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
++       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_s32(a, b, c, d)                                \
++#define vmlsl_high_laneq_s32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x4_t c_ = (c);                                              \
+        int32x4_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
++       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_u16(a, b, c, d)                                \
++#define vmlsl_high_laneq_u16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t c_ = (c);                                             \
+        uint16x8_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
++       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_u32(a, b, c, d)                                \
++#define vmlsl_high_laneq_u32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x4_t c_ = (c);                                             \
+        uint32x4_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
++       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]"
++  __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]"
++  __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]"
++  __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]"
++  __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("smlal2 %0.8h,%2.16b,%3.16b"
++  __asm__ ("smlsl2 %0.8h,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal2 %0.4s,%2.8h,%3.8h"
++  __asm__ ("smlsl2 %0.4s,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal2 %0.2d,%2.4s,%3.4s"
++  __asm__ ("smlsl2 %0.2d,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("umlal2 %0.8h,%2.16b,%3.16b"
++  __asm__ ("umlsl2 %0.8h,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal2 %0.4s,%2.8h,%3.8h"
++  __asm__ ("umlsl2 %0.4s,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal2 %0.2d,%2.4s,%3.4s"
++  __asm__ ("umlsl2 %0.2d,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlal_lane_s16(a, b, c, d)                                      \
++#define vmlsl_lane_s16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x4_t c_ = (c);                                              \
+        int16x4_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlal %0.4s,%2.4h,%3.h[%4]"                            \
++       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_lane_s32(a, b, c, d)                                      \
++#define vmlsl_lane_s32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x2_t c_ = (c);                                              \
+        int32x2_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlal %0.2d,%2.2s,%3.s[%4]"                            \
++       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_lane_u16(a, b, c, d)                                      \
++#define vmlsl_lane_u16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x4_t c_ = (c);                                             \
+        uint16x4_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlal %0.4s,%2.4h,%3.h[%4]"                            \
++       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_lane_u32(a, b, c, d)                                      \
++#define vmlsl_lane_u32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x2_t c_ = (c);                                             \
+        uint32x2_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_s16(a, b, c, d)                                     \
++#define vmlsl_laneq_s16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t c_ = (c);                                              \
+        int16x4_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlal %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_s32(a, b, c, d)                                     \
++#define vmlsl_laneq_s32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x4_t c_ = (c);                                              \
+        int32x2_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlal %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_u16(a, b, c, d)                                     \
++#define vmlsl_laneq_u16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t c_ = (c);                                             \
+        uint16x4_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlal %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_u32(a, b, c, d)                                     \
++#define vmlsl_laneq_u32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x4_t c_ = (c);                                             \
+        uint32x2_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal %0.4s,%2.4h,%3.h[0]"
++  __asm__ ("smlsl %0.4s, %2.4h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal %0.2d,%2.2s,%3.s[0]"
++  __asm__ ("smlsl %0.2d, %2.2s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal %0.4s,%2.4h,%3.h[0]"
++  __asm__ ("umlsl %0.4s, %2.4h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal %0.2d,%2.2s,%3.s[0]"
++  __asm__ ("umlsl %0.2d, %2.2s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("smlal %0.8h,%2.8b,%3.8b"
++  __asm__ ("smlsl %0.8h, %2.8b, %3.8b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal %0.4s,%2.4h,%3.4h"
++  __asm__ ("smlsl %0.4s, %2.4h, %3.4h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal %0.2d,%2.2s,%3.2s"
++  __asm__ ("smlsl %0.2d, %2.2s, %3.2s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("umlal %0.8h,%2.8b,%3.8b"
++  __asm__ ("umlsl %0.8h, %2.8b, %3.8b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal %0.4s,%2.4h,%3.4h"
++  __asm__ ("umlsl %0.4s, %2.4h, %3.4h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal %0.2d,%2.2s,%3.2s"
++  __asm__ ("umlsl %0.2d, %2.2s, %3.2s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
+ {
+   float32x4_t result;
+   float32x4_t t1;
+-  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fadd %0.4s, %0.4s, %1.4s"
++  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fsub %0.4s, %0.4s, %1.4s"
+            : "=w"(result), "=w"(t1)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
++  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
++  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
++  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
++  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+ {
+   int8x16_t result;
+-  __asm__ ("mla %0.16b, %2.16b, %3.16b"
++  __asm__ ("mls %0.16b,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("mla %0.8h, %2.8h, %3.8h"
++  __asm__ ("mls %0.8h,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("mla %0.4s, %2.4s, %3.4s"
++  __asm__ ("mls %0.4s,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint8x16_t result;
+-  __asm__ ("mla %0.16b, %2.16b, %3.16b"
++  __asm__ ("mls %0.16b,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("mla %0.8h, %2.8h, %3.8h"
++  __asm__ ("mls %0.8h,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("mla %0.4s, %2.4s, %3.4s"
++  __asm__ ("mls %0.4s,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_s8 (int8x16_t a)
+ {
+-  float32x2_t result;
+-  float32x2_t t1;
+-  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fsub %0.2s, %0.2s, %1.2s"
+-           : "=w"(result), "=w"(t1)
+-           : "0"(a), "w"(b), "w"(c)
++  int16x8_t result;
++  __asm__ ("sshll2 %0.8h,%1.16b,#0"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_s16 (int16x8_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++  int32x4_t result;
++  __asm__ ("sshll2 %0.4s,%1.8h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_s32 (int32x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++  int64x2_t result;
++  __asm__ ("sshll2 %0.2d,%1.4s,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_u8 (uint8x16_t a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++  uint16x8_t result;
++  __asm__ ("ushll2 %0.8h,%1.16b,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_u16 (uint16x8_t a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++  uint32x4_t result;
++  __asm__ ("ushll2 %0.4s,%1.8h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_u32 (uint32x4_t a)
+ {
+-  int8x8_t result;
+-  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++  uint64x2_t result;
++  __asm__ ("ushll2 %0.2d,%1.4s,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_s8 (int8x8_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++  int16x8_t result;
++  __asm__ ("sshll %0.8h,%1.8b,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_s16 (int16x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++  int32x4_t result;
++  __asm__ ("sshll %0.4s,%1.4h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_s32 (int32x2_t a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++  int64x2_t result;
++  __asm__ ("sshll %0.2d,%1.2s,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_u8 (uint8x8_t a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++  uint16x8_t result;
++  __asm__ ("ushll %0.8h,%1.8b,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_u16 (uint16x4_t a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++  uint32x4_t result;
++  __asm__ ("ushll %0.4s,%1.4h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlsl_high_lane_s16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x4_t c_ = (c);                                              \
+-       int16x8_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_u32 (uint32x2_t a)
++{
++  uint64x2_t result;
++  __asm__ ("ushll %0.2d,%1.2s,#0"
++           : "=w"(result)
++           : "w"(a)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_lane_s32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t c_ = (c);                                              \
+-       int32x4_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_s16 (int8x8_t a, int16x8_t b)
++{
++  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.16b,%1.8h"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_lane_u16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x4_t c_ = (c);                                             \
+-       uint16x8_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_s32 (int16x4_t a, int32x4_t b)
++{
++  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.8h,%1.4s"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_lane_u32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t c_ = (c);                                             \
+-       uint32x4_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_s64 (int32x2_t a, int64x2_t b)
++{
++  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.4s,%1.2d"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_laneq_s16(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t c_ = (c);                                              \
+-       int16x8_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_u16 (uint8x8_t a, uint16x8_t b)
++{
++  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.16b,%1.8h"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_laneq_s32(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t c_ = (c);                                              \
+-       int32x4_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmlsl_high_laneq_u16(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t c_ = (c);                                             \
+-       uint16x8_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmlsl_high_laneq_u32(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t c_ = (c);                                             \
+-       uint32x4_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
+-{
+-  int32x4_t result;
+-  __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
+-{
+-  int64x2_t result;
+-  __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_u32 (uint16x4_t a, uint32x4_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.8h,%1.4s"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_u64 (uint32x2_t a, uint64x2_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.4s,%1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsl_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_s16 (int16x8_t a)
+ {
+-  int16x8_t result;
+-  __asm__ ("smlsl2 %0.8h,%2.16b,%3.16b"
++  int8x8_t result;
++  __asm__ ("xtn %0.8b,%1.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_s32 (int32x4_t a)
+ {
+-  int32x4_t result;
+-  __asm__ ("smlsl2 %0.4s,%2.8h,%3.8h"
++  int16x4_t result;
++  __asm__ ("xtn %0.4h,%1.4s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_s64 (int64x2_t a)
+ {
+-  int64x2_t result;
+-  __asm__ ("smlsl2 %0.2d,%2.4s,%3.4s"
++  int32x2_t result;
++  __asm__ ("xtn %0.2s,%1.2d"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsl_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_u16 (uint16x8_t a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("umlsl2 %0.8h,%2.16b,%3.16b"
++  uint8x8_t result;
++  __asm__ ("xtn %0.8b,%1.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_u32 (uint32x4_t a)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umlsl2 %0.4s,%2.8h,%3.8h"
++  uint16x4_t result;
++  __asm__ ("xtn %0.4h,%1.4s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_u64 (uint64x2_t a)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umlsl2 %0.2d,%2.4s,%3.4s"
++  uint32x2_t result;
++  __asm__ ("xtn %0.2s,%1.2d"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlsl_lane_s16(a, b, c, d)                                      \
++#define vmull_high_lane_s16(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       int16x4_t c_ = (c);                                              \
+        int16x4_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
++       int16x8_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_lane_s32(a, b, c, d)                                      \
++#define vmull_high_lane_s32(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       int32x2_t c_ = (c);                                              \
+        int32x2_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
++       int32x4_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_lane_u16(a, b, c, d)                                      \
++#define vmull_high_lane_u16(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint16x4_t c_ = (c);                                             \
+        uint16x4_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
++       uint16x8_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_lane_u32(a, b, c, d)                                      \
++#define vmull_high_lane_u32(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x2_t c_ = (c);                                             \
+        uint32x2_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
++       uint32x4_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_s16(a, b, c, d)                                     \
++#define vmull_high_laneq_s16(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       int16x8_t c_ = (c);                                              \
+-       int16x4_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
++       int16x8_t b_ = (b);                                              \
++       int16x8_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_s32(a, b, c, d)                                     \
++#define vmull_high_laneq_s32(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       int32x4_t c_ = (c);                                              \
+-       int32x2_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
++       int32x4_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_u16(a, b, c, d)                                     \
++#define vmull_high_laneq_u16(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint16x8_t c_ = (c);                                             \
+-       uint16x4_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
++       uint16x8_t b_ = (b);                                             \
++       uint16x8_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_u32(a, b, c, d)                                     \
++#define vmull_high_laneq_u32(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x4_t c_ = (c);                                             \
+-       uint32x2_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
++       uint32x4_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_s16 (int16x8_t a, int16_t b)
+ {
+   int32x4_t result;
+-  __asm__ ("smlsl %0.4s, %2.4h, %3.h[0]"
++  __asm__ ("smull2 %0.4s,%1.8h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_s32 (int32x4_t a, int32_t b)
+ {
+   int64x2_t result;
+-  __asm__ ("smlsl %0.2d, %2.2s, %3.s[0]"
++  __asm__ ("smull2 %0.2d,%1.4s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_u16 (uint16x8_t a, uint16_t b)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlsl %0.4s, %2.4h, %3.h[0]"
++  __asm__ ("umull2 %0.4s,%1.8h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_u32 (uint32x4_t a, uint32_t b)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlsl %0.2d, %2.2s, %3.s[0]"
++  __asm__ ("umull2 %0.2d,%1.4s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_p8 (poly8x16_t a, poly8x16_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("smlsl %0.8h, %2.8b, %3.8b"
++  poly16x8_t result;
++  __asm__ ("pmull2 %0.8h,%1.16b,%2.16b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_s8 (int8x16_t a, int8x16_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("smlsl %0.4s, %2.4h, %3.4h"
++  int16x8_t result;
++  __asm__ ("smull2 %0.8h,%1.16b,%2.16b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_s16 (int16x8_t a, int16x8_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("smlsl %0.2d, %2.2s, %3.2s"
++  int32x4_t result;
++  __asm__ ("smull2 %0.4s,%1.8h,%2.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsl_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_s32 (int32x4_t a, int32x4_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("umlsl %0.8h, %2.8b, %3.8b"
++  int64x2_t result;
++  __asm__ ("smull2 %0.2d,%1.4s,%2.4s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umlsl %0.4s, %2.4h, %3.4h"
++  uint16x8_t result;
++  __asm__ ("umull2 %0.8h,%1.16b,%2.16b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_u16 (uint16x8_t a, uint16x8_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umlsl %0.2d, %2.2s, %3.2s"
++  uint32x4_t result;
++  __asm__ ("umull2 %0.4s,%1.8h,%2.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  float32x4_t result;
+-  float32x4_t t1;
+-  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fsub %0.4s, %0.4s, %1.4s"
+-           : "=w"(result), "=w"(t1)
+-           : "0"(a), "w"(b), "w"(c)
++  uint64x2_t result;
++  __asm__ ("umull2 %0.2d,%1.4s,%2.4s"
++           : "=w"(result)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
++#define vmull_lane_s16(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smull %0.4s,%1.4h,%2.h[%3]"                            \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_lane_s32(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x2_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smull %0.2d,%1.2s,%2.s[%3]"                            \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_lane_u16(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umull %0.4s,%1.4h,%2.h[%3]"                            \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_lane_u32(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_s16(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smull %0.4s, %1.4h, %2.h[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_s32(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smull %0.2d, %1.2s, %2.s[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_u16(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umull %0.4s, %1.4h, %2.h[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_u32(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_s16 (int16x4_t a, int16_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
++  int32x4_t result;
++  __asm__ ("smull %0.4s,%1.4h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_s32 (int32x2_t a, int32_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
++  int64x2_t result;
++  __asm__ ("smull %0.2d,%1.2s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_u16 (uint16x4_t a, uint16_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
++  uint32x4_t result;
++  __asm__ ("umull %0.4s,%1.4h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_u32 (uint32x2_t a, uint32_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
++  uint64x2_t result;
++  __asm__ ("umull %0.2d,%1.2s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_p8 (poly8x8_t a, poly8x8_t b)
+ {
+-  int8x16_t result;
+-  __asm__ ("mls %0.16b,%2.16b,%3.16b"
++  poly16x8_t result;
++  __asm__ ("pmull %0.8h, %1.8b, %2.8b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_s8 (int8x8_t a, int8x8_t b)
+ {
+   int16x8_t result;
+-  __asm__ ("mls %0.8h,%2.8h,%3.8h"
++  __asm__ ("smull %0.8h, %1.8b, %2.8b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_s16 (int16x4_t a, int16x4_t b)
+ {
+   int32x4_t result;
+-  __asm__ ("mls %0.4s,%2.4s,%3.4s"
++  __asm__ ("smull %0.4s, %1.4h, %2.4h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_s32 (int32x2_t a, int32x2_t b)
+ {
+-  uint8x16_t result;
+-  __asm__ ("mls %0.16b,%2.16b,%3.16b"
++  int64x2_t result;
++  __asm__ ("smull %0.2d, %1.2s, %2.2s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_u8 (uint8x8_t a, uint8x8_t b)
+ {
+   uint16x8_t result;
+-  __asm__ ("mls %0.8h,%2.8h,%3.8h"
++  __asm__ ("umull %0.8h, %1.8b, %2.8b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_u16 (uint16x4_t a, uint16x4_t b)
+ {
+   uint32x4_t result;
+-  __asm__ ("mls %0.4s,%2.4s,%3.4s"
++  __asm__ ("umull %0.4s, %1.4h, %2.4h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovl_high_s8 (int8x16_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sshll2 %0.8h,%1.16b,#0"
++  uint64x2_t result;
++  __asm__ ("umull %0.2d, %1.2s, %2.2s"
+            : "=w"(result)
+-           : "w"(a)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovl_high_s16 (int16x8_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_s8 (int16x4_t a, int8x8_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sshll2 %0.4s,%1.8h,#0"
++  int16x4_t result;
++  __asm__ ("sadalp %0.4h,%2.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmovl_high_s32 (int32x4_t a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_s16 (int32x2_t a, int16x4_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("sshll2 %0.2d,%1.4s,#0"
++  int32x2_t result;
++  __asm__ ("sadalp %0.2s,%2.4h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovl_high_u8 (uint8x16_t a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_s32 (int64x1_t a, int32x2_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("ushll2 %0.8h,%1.16b,#0"
++  int64x1_t result;
++  __asm__ ("sadalp %0.1d,%2.2s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovl_high_u16 (uint16x8_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_u8 (uint16x4_t a, uint8x8_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("ushll2 %0.4s,%1.8h,#0"
++  uint16x4_t result;
++  __asm__ ("uadalp %0.4h,%2.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmovl_high_u32 (uint32x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_u16 (uint32x2_t a, uint16x4_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("ushll2 %0.2d,%1.4s,#0"
++  uint32x2_t result;
++  __asm__ ("uadalp %0.2s,%2.4h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovl_s8 (int8x8_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_u32 (uint64x1_t a, uint32x2_t b)
++{
++  uint64x1_t result;
++  __asm__ ("uadalp %0.1d,%2.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_s8 (int16x8_t a, int8x16_t b)
+ {
+   int16x8_t result;
+-  __asm__ ("sshll %0.8h,%1.8b,#0"
++  __asm__ ("sadalp %0.8h,%2.16b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovl_s16 (int16x4_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_s16 (int32x4_t a, int16x8_t b)
+ {
+   int32x4_t result;
+-  __asm__ ("sshll %0.4s,%1.4h,#0"
++  __asm__ ("sadalp %0.4s,%2.8h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmovl_s32 (int32x2_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_s32 (int64x2_t a, int32x4_t b)
+ {
+   int64x2_t result;
+-  __asm__ ("sshll %0.2d,%1.2s,#0"
++  __asm__ ("sadalp %0.2d,%2.4s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovl_u8 (uint8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_u8 (uint16x8_t a, uint8x16_t b)
+ {
+   uint16x8_t result;
+-  __asm__ ("ushll %0.8h,%1.8b,#0"
++  __asm__ ("uadalp %0.8h,%2.16b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovl_u16 (uint16x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_u16 (uint32x4_t a, uint16x8_t b)
+ {
+   uint32x4_t result;
+-  __asm__ ("ushll %0.4s,%1.4h,#0"
++  __asm__ ("uadalp %0.4s,%2.8h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmovl_u32 (uint32x2_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_u32 (uint64x2_t a, uint32x4_t b)
+ {
+   uint64x2_t result;
+-  __asm__ ("ushll %0.2d,%1.2s,#0"
++  __asm__ ("uadalp %0.2d,%2.4s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmovn_high_s16 (int8x8_t a, int16x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_s8 (int8x8_t a)
+ {
+-  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.16b,%1.8h"
+-           : "+w"(result)
+-           : "w"(b)
++  int16x4_t result;
++  __asm__ ("saddlp %0.4h,%1.8b"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovn_high_s32 (int16x4_t a, int32x4_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_s16 (int16x4_t a)
+ {
+-  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.8h,%1.4s"
+-           : "+w"(result)
+-           : "w"(b)
++  int32x2_t result;
++  __asm__ ("saddlp %0.2s,%1.4h"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovn_high_s64 (int32x2_t a, int64x2_t b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_s32 (int32x2_t a)
+ {
+-  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.4s,%1.2d"
+-           : "+w"(result)
+-           : "w"(b)
++  int64x1_t result;
++  __asm__ ("saddlp %0.1d,%1.2s"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmovn_high_u16 (uint8x8_t a, uint16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_u8 (uint8x8_t a)
+ {
+-  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.16b,%1.8h"
+-           : "+w"(result)
+-           : "w"(b)
++  uint16x4_t result;
++  __asm__ ("uaddlp %0.4h,%1.8b"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovn_high_u32 (uint16x4_t a, uint32x4_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_u16 (uint16x4_t a)
+ {
+-  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.8h,%1.4s"
+-           : "+w"(result)
+-           : "w"(b)
++  uint32x2_t result;
++  __asm__ ("uaddlp %0.2s,%1.4h"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovn_high_u64 (uint32x2_t a, uint64x2_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_u32 (uint32x2_t a)
+ {
+-  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.4s,%1.2d"
+-           : "+w"(result)
+-           : "w"(b)
++  uint64x1_t result;
++  __asm__ ("uaddlp %0.1d,%1.2s"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmovn_s16 (int16x8_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_s8 (int8x16_t a)
+ {
+-  int8x8_t result;
+-  __asm__ ("xtn %0.8b,%1.8h"
++  int16x8_t result;
++  __asm__ ("saddlp %0.8h,%1.16b"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmovn_s32 (int32x4_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_s16 (int16x8_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("xtn %0.4h,%1.4s"
++  int32x4_t result;
++  __asm__ ("saddlp %0.4s,%1.8h"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmovn_s64 (int64x2_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_s32 (int32x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("xtn %0.2s,%1.2d"
++  int64x2_t result;
++  __asm__ ("saddlp %0.2d,%1.4s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmovn_u16 (uint16x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_u8 (uint8x16_t a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("xtn %0.8b,%1.8h"
++  uint16x8_t result;
++  __asm__ ("uaddlp %0.8h,%1.16b"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmovn_u32 (uint32x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_u16 (uint16x8_t a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("xtn %0.4h,%1.4s"
++  uint32x4_t result;
++  __asm__ ("uaddlp %0.4s,%1.8h"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmovn_u64 (uint64x2_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_u32 (uint32x4_t a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("xtn %0.2s,%1.2d"
++  uint64x2_t result;
++  __asm__ ("uaddlp %0.2d,%1.4s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmul_n_f32 (float32x2_t a, float32_t b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  float32x2_t result;
+-  __asm__ ("fmul %0.2s,%1.2s,%2.s[0]"
++  int8x16_t result;
++  __asm__ ("addp %0.16b,%1.16b,%2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s16 (int16x8_t a, int16x8_t b)
++{
++  int16x8_t result;
++  __asm__ ("addp %0.8h,%1.8h,%2.8h"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s32 (int32x4_t a, int32x4_t b)
++{
++  int32x4_t result;
++  __asm__ ("addp %0.4s,%1.4s,%2.4s"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s64 (int64x2_t a, int64x2_t b)
++{
++  int64x2_t result;
++  __asm__ ("addp %0.2d,%1.2d,%2.2d"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u8 (uint8x16_t a, uint8x16_t b)
++{
++  uint8x16_t result;
++  __asm__ ("addp %0.16b,%1.16b,%2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u16 (uint16x8_t a, uint16x8_t b)
++{
++  uint16x8_t result;
++  __asm__ ("addp %0.8h,%1.8h,%2.8h"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u32 (uint32x4_t a, uint32x4_t b)
++{
++  uint32x4_t result;
++  __asm__ ("addp %0.4s,%1.4s,%2.4s"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u64 (uint64x2_t a, uint64x2_t b)
++{
++  uint64x2_t result;
++  __asm__ ("addp %0.2d,%1.2d,%2.2d"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmul_n_s16 (int16x4_t a, int16_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_n_s16 (int16x4_t a, int16_t b)
+ {
+   int16x4_t result;
+-  __asm__ ("mul %0.4h,%1.4h,%2.h[0]"
++  __asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]"
+            : "=w"(result)
+            : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmul_n_s32 (int32x2_t a, int32_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_n_s32 (int32x2_t a, int32_t b)
+ {
+   int32x2_t result;
+-  __asm__ ("mul %0.2s,%1.2s,%2.s[0]"
++  __asm__ ("sqdmulh %0.2s,%1.2s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmul_n_u16 (uint16x4_t a, uint16_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_n_s16 (int16x8_t a, int16_t b)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mul %0.4h,%1.4h,%2.h[0]"
++  int16x8_t result;
++  __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]"
+            : "=w"(result)
+            : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmul_n_u32 (uint32x2_t a, uint32_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_n_s32 (int32x4_t a, int32_t b)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mul %0.2s,%1.2s,%2.s[0]"
++  int32x4_t result;
++  __asm__ ("sqdmulh %0.4s,%1.4s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmull_high_lane_s16(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x4_t b_ = (b);                                              \
+-       int16x8_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_s16 (int8x8_t a, int16x8_t b)
++{
++  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtn2 %0.16b, %1.8h"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmull_high_lane_s32(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_lane_u16(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x4_t b_ = (b);                                             \
+-       uint16x8_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_lane_u32(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_s16(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int16x8_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_s32(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_u16(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint16x8_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_u32(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_s32 (int16x4_t a, int32x4_t b)
++{
++  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtn2 %0.8h, %1.4s"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_high_n_s16 (int16x8_t a, int16_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_s64 (int32x2_t a, int64x2_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("smull2 %0.4s,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
++  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtn2 %0.4s, %1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_high_n_s32 (int32x4_t a, int32_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_u16 (uint8x8_t a, uint16x8_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("smull2 %0.2d,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("uqxtn2 %0.16b, %1.8h"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_high_n_u16 (uint16x8_t a, uint16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_u32 (uint16x4_t a, uint32x4_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umull2 %0.4s,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
++  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("uqxtn2 %0.8h, %1.4s"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_high_n_u32 (uint32x4_t a, uint32_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_u64 (uint32x2_t a, uint64x2_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umull2 %0.2d,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("uqxtn2 %0.4s, %1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vmull_high_p8 (poly8x16_t a, poly8x16_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_high_s16 (uint8x8_t a, int16x8_t b)
+ {
+-  poly16x8_t result;
+-  __asm__ ("pmull2 %0.8h,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtun2 %0.16b, %1.8h"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmull_high_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_high_s32 (uint16x4_t a, int32x4_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("smull2 %0.8h,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtun2 %0.8h, %1.4s"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_high_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_high_s64 (uint32x2_t a, int64x2_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("smull2 %0.4s,%1.8h,%2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtun2 %0.4s, %1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_high_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_n_s16 (int16x4_t a, int16_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("smull2 %0.2d,%1.4s,%2.4s"
++  int16x4_t result;
++  __asm__ ("sqrdmulh %0.4h,%1.4h,%2.h[0]"
+            : "=w"(result)
+-           : "w"(a), "w"(b)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmull_high_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_n_s32 (int32x2_t a, int32_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("umull2 %0.8h,%1.16b,%2.16b"
++  int32x2_t result;
++  __asm__ ("sqrdmulh %0.2s,%1.2s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_high_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_n_s16 (int16x8_t a, int16_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umull2 %0.4s,%1.8h,%2.8h"
++  int16x8_t result;
++  __asm__ ("sqrdmulh %0.8h,%1.8h,%2.h[0]"
+            : "=w"(result)
+-           : "w"(a), "w"(b)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_high_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_n_s32 (int32x4_t a, int32_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umull2 %0.2d,%1.4s,%2.4s"
++  int32x4_t result;
++  __asm__ ("sqrdmulh %0.4s,%1.4s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmull_lane_s16(a, b, c)                                         \
++#define vqrshrn_high_n_s16(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       int16x4_t b_ = (b);                                              \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqrshrn2 %0.16b, %1.8h, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqrshrn_high_n_s32(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
+        int16x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull %0.4s,%1.4h,%2.h[%3]"                            \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqrshrn2 %0.8h, %1.4s, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_lane_s32(a, b, c)                                         \
++#define vqrshrn_high_n_s64(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       int32x2_t b_ = (b);                                              \
++       int64x2_t b_ = (b);                                              \
+        int32x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull %0.2d,%1.2s,%2.s[%3]"                            \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqrshrn2 %0.4s, %1.2d, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_lane_u16(a, b, c)                                         \
++#define vqrshrn_high_n_u16(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint16x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull %0.4s,%1.4h,%2.h[%3]"                            \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       uint16x8_t b_ = (b);                                             \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqrshrn2 %0.16b, %1.8h, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_lane_u32(a, b, c)                                         \
++#define vqrshrn_high_n_u32(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x2_t b_ = (b);                                             \
++       uint32x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqrshrn2 %0.8h, %1.4s, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqrshrn_high_n_u64(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
+        uint32x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqrshrn2 %0.4s, %1.2d, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_s16(a, b, c)                                        \
++#define vqrshrun_high_n_s16(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull %0.4s, %1.4h, %2.h[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqrshrun2 %0.16b, %1.8h, #%2"                          \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_s32(a, b, c)                                        \
++#define vqrshrun_high_n_s32(a, b, c)                                    \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqrshrun2 %0.8h, %1.4s, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqrshrun_high_n_s64(a, b, c)                                    \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqrshrun2 %0.4s, %1.2d, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqshrn_high_n_s16(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqshrn2 %0.16b, %1.8h, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqshrn_high_n_s32(a, b, c)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqshrn2 %0.8h, %1.4s, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqshrn_high_n_s64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
+        int32x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull %0.2d, %1.2s, %2.s[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqshrn2 %0.4s, %1.2d, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_u16(a, b, c)                                        \
++#define vqshrn_high_n_u16(a, b, c)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull %0.4s, %1.4h, %2.h[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqshrn2 %0.16b, %1.8h, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_u32(a, b, c)                                        \
++#define vqshrn_high_n_u32(a, b, c)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x4_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqshrn2 %0.8h, %1.4s, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_n_s16 (int16x4_t a, int16_t b)
+-{
+-  int32x4_t result;
+-  __asm__ ("smull %0.4s,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrn_high_n_u64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqshrn2 %0.4s, %1.2d, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_n_s32 (int32x2_t a, int32_t b)
+-{
+-  int64x2_t result;
+-  __asm__ ("smull %0.2d,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrun_high_n_s16(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqshrun2 %0.16b, %1.8h, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_n_u16 (uint16x4_t a, uint16_t b)
+-{
+-  uint32x4_t result;
+-  __asm__ ("umull %0.4s,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrun_high_n_s32(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqshrun2 %0.8h, %1.4s, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_n_u32 (uint32x2_t a, uint32_t b)
+-{
+-  uint64x2_t result;
+-  __asm__ ("umull %0.2d,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrun_high_n_s64(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqshrun2 %0.4s, %1.2d, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vmull_p8 (poly8x8_t a, poly8x8_t b)
+-{
+-  poly16x8_t result;
+-  __asm__ ("pmull %0.8h, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_s16(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmull_s8 (int8x8_t a, int8x8_t b)
+-{
+-  int16x8_t result;
+-  __asm__ ("smull %0.8h, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_s16 (int16x4_t a, int16x4_t b)
+-{
+-  int32x4_t result;
+-  __asm__ ("smull %0.4s, %1.4h, %2.4h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_s32 (int32x2_t a, int32x2_t b)
+-{
+-  int64x2_t result;
+-  __asm__ ("smull %0.2d, %1.2s, %2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmull_u8 (uint8x8_t a, uint8x8_t b)
+-{
+-  uint16x8_t result;
+-  __asm__ ("umull %0.8h, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_s32(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_u16 (uint16x4_t a, uint16x4_t b)
+-{
+-  uint32x4_t result;
+-  __asm__ ("umull %0.4s, %1.4h, %2.4h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_s64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_u32 (uint32x2_t a, uint32x2_t b)
+-{
+-  uint64x2_t result;
+-  __asm__ ("umull %0.2d, %1.2s, %2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_u16(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t b_ = (b);                                             \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                            (a_, vcreate_u8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulq_n_f32 (float32x4_t a, float32_t b)
+-{
+-  float32x4_t result;
+-  __asm__ ("fmul %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_u32(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                            (a_, vcreate_u16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulq_n_f64 (float64x2_t a, float64_t b)
+-{
+-  float64x2_t result;
+-  __asm__ ("fmul %0.2d,%1.2d,%2.d[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_u64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                            (a_, vcreate_u32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmulq_n_s16 (int16x8_t a, int16_t b)
+-{
+-  int16x8_t result;
+-  __asm__ ("mul %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_s16(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t a_ = (a);                                              \
++       int8x8_t result;                                                 \
++       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmulq_n_s32 (int32x4_t a, int32_t b)
+-{
+-  int32x4_t result;
+-  __asm__ ("mul %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_s32(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t a_ = (a);                                              \
++       int16x4_t result;                                                \
++       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmulq_n_u16 (uint16x8_t a, uint16_t b)
+-{
+-  uint16x8_t result;
+-  __asm__ ("mul %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_s64(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t a_ = (a);                                              \
++       int32x2_t result;                                                \
++       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmulq_n_u32 (uint32x4_t a, uint32_t b)
+-{
+-  uint32x4_t result;
+-  __asm__ ("mul %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_u16(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t a_ = (a);                                             \
++       uint8x8_t result;                                                \
++       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vmvn_p8 (poly8x8_t a)
+-{
+-  poly8x8_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_u32(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t a_ = (a);                                             \
++       uint16x4_t result;                                               \
++       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmvn_s8 (int8x8_t a)
+-{
+-  int8x8_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_u64(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t a_ = (a);                                             \
++       uint32x2_t result;                                               \
++       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmvn_s16 (int16x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_u32 (uint32x2_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
++  uint32x2_t result;
++  __asm__ ("ursqrte %0.2s,%1.2s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmvn_s32 (int32x2_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_u32 (uint32x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
++  uint32x4_t result;
++  __asm__ ("ursqrte %0.4s,%1.4s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmvn_u8 (uint8x8_t a)
+-{
++#define vshrn_high_n_s16(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_s32(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_s64(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_u16(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t b_ = (b);                                             \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                            (a_, vcreate_u8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_u32(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                            (a_, vcreate_u16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_u64(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                            (a_, vcreate_u32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_s16(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t a_ = (a);                                              \
++       int8x8_t result;                                                 \
++       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_s32(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t a_ = (a);                                              \
++       int16x4_t result;                                                \
++       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_s64(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t a_ = (a);                                              \
++       int32x2_t result;                                                \
++       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_u16(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t a_ = (a);                                             \
++       uint8x8_t result;                                                \
++       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_u32(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t a_ = (a);                                             \
++       uint16x4_t result;                                               \
++       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_u64(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t a_ = (a);                                             \
++       uint32x2_t result;                                               \
++       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsli_n_p8(a, b, c)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x8_t b_ = (b);                                              \
++       poly8x8_t a_ = (a);                                              \
++       poly8x8_t result;                                                \
++       __asm__ ("sli %0.8b,%2.8b,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsli_n_p16(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x4_t b_ = (b);                                             \
++       poly16x4_t a_ = (a);                                             \
++       poly16x4_t result;                                               \
++       __asm__ ("sli %0.4h,%2.4h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsliq_n_p8(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x16_t b_ = (b);                                             \
++       poly8x16_t a_ = (a);                                             \
++       poly8x16_t result;                                               \
++       __asm__ ("sli %0.16b,%2.16b,%3"                                  \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsliq_n_p16(a, b, c)                                            \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x8_t b_ = (b);                                             \
++       poly16x8_t a_ = (a);                                             \
++       poly16x8_t result;                                               \
++       __asm__ ("sli %0.8h,%2.8h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsri_n_p8(a, b, c)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x8_t b_ = (b);                                              \
++       poly8x8_t a_ = (a);                                              \
++       poly8x8_t result;                                                \
++       __asm__ ("sri %0.8b,%2.8b,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsri_n_p16(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x4_t b_ = (b);                                             \
++       poly16x4_t a_ = (a);                                             \
++       poly16x4_t result;                                               \
++       __asm__ ("sri %0.4h,%2.4h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsri_n_p64(a, b, c)						\
++  __extension__								\
++    ({									\
++       poly64x1_t b_ = (b);						\
++       poly64x1_t a_ = (a);						\
++       poly64x1_t result;						\
++       __asm__ ("sri %d0,%d2,%3"					\
++		: "=w"(result)						\
++		: "0"(a_), "w"(b_), "i"(c)				\
++		: /* No clobbers.  */);					\
++       result;								\
++     })
++
++#define vsriq_n_p8(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x16_t b_ = (b);                                             \
++       poly8x16_t a_ = (a);                                             \
++       poly8x16_t result;                                               \
++       __asm__ ("sri %0.16b,%2.16b,%3"                                  \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsriq_n_p16(a, b, c)                                            \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x8_t b_ = (b);                                             \
++       poly16x8_t a_ = (a);                                             \
++       poly16x8_t result;                                               \
++       __asm__ ("sri %0.8h,%2.8h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsriq_n_p64(a, b, c)						\
++  __extension__								\
++    ({									\
++       poly64x2_t b_ = (b);						\
++       poly64x2_t a_ = (a);						\
++       poly64x2_t result;						\
++       __asm__ ("sri %0.2d,%2.2d,%3"					\
++		: "=w"(result)						\
++		: "0"(a_), "w"(b_), "i"(c)				\
++		: /* No clobbers.  */);					\
++       result;								\
++     })
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_p8 (poly8x8_t a, poly8x8_t b)
++{
++  uint8x8_t result;
++  __asm__ ("cmtst %0.8b, %1.8b, %2.8b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_p16 (poly16x4_t a, poly16x4_t b)
++{
++  uint16x4_t result;
++  __asm__ ("cmtst %0.4h, %1.4h, %2.4h"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_p8 (poly8x16_t a, poly8x16_t b)
++{
++  uint8x16_t result;
++  __asm__ ("cmtst %0.16b, %1.16b, %2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_p16 (poly16x8_t a, poly16x8_t b)
++{
++  uint16x8_t result;
++  __asm__ ("cmtst %0.8h, %1.8h, %2.8h"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++/* End of temporary inline asm implementations.  */
++
++/* Start of temporary inline asm for vldn, vstn and friends.  */
++
++/* Create struct element types for duplicating loads.
++
++   Create 2 element structures of:
++
++   +------+----+----+----+----+
++   |      | 8  | 16 | 32 | 64 |
++   +------+----+----+----+----+
++   |int   | Y  | Y  | N  | N  |
++   +------+----+----+----+----+
++   |uint  | Y  | Y  | N  | N  |
++   +------+----+----+----+----+
++   |float | -  | Y  | N  | N  |
++   +------+----+----+----+----+
++   |poly  | Y  | Y  | -  | -  |
++   +------+----+----+----+----+
++
++   Create 3 element structures of:
++
++   +------+----+----+----+----+
++   |      | 8  | 16 | 32 | 64 |
++   +------+----+----+----+----+
++   |int   | Y  | Y  | Y  | Y  |
++   +------+----+----+----+----+
++   |uint  | Y  | Y  | Y  | Y  |
++   +------+----+----+----+----+
++   |float | -  | Y  | Y  | Y  |
++   +------+----+----+----+----+
++   |poly  | Y  | Y  | -  | -  |
++   +------+----+----+----+----+
++
++   Create 4 element structures of:
++
++   +------+----+----+----+----+
++   |      | 8  | 16 | 32 | 64 |
++   +------+----+----+----+----+
++   |int   | Y  | N  | N  | Y  |
++   +------+----+----+----+----+
++   |uint  | Y  | N  | N  | Y  |
++   +------+----+----+----+----+
++   |float | -  | N  | N  | Y  |
++   +------+----+----+----+----+
++   |poly  | Y  | N  | -  | -  |
++   +------+----+----+----+----+
++
++  This is required for casting memory reference.  */
++#define __STRUCTN(t, sz, nelem)			\
++  typedef struct t ## sz ## x ## nelem ## _t {	\
++    t ## sz ## _t val[nelem];			\
++  }  t ## sz ## x ## nelem ## _t;
++
++/* 2-element structs.  */
++__STRUCTN (int, 8, 2)
++__STRUCTN (int, 16, 2)
++__STRUCTN (uint, 8, 2)
++__STRUCTN (uint, 16, 2)
++__STRUCTN (float, 16, 2)
++__STRUCTN (poly, 8, 2)
++__STRUCTN (poly, 16, 2)
++/* 3-element structs.  */
++__STRUCTN (int, 8, 3)
++__STRUCTN (int, 16, 3)
++__STRUCTN (int, 32, 3)
++__STRUCTN (int, 64, 3)
++__STRUCTN (uint, 8, 3)
++__STRUCTN (uint, 16, 3)
++__STRUCTN (uint, 32, 3)
++__STRUCTN (uint, 64, 3)
++__STRUCTN (float, 16, 3)
++__STRUCTN (float, 32, 3)
++__STRUCTN (float, 64, 3)
++__STRUCTN (poly, 8, 3)
++__STRUCTN (poly, 16, 3)
++/* 4-element structs.  */
++__STRUCTN (int, 8, 4)
++__STRUCTN (int, 64, 4)
++__STRUCTN (uint, 8, 4)
++__STRUCTN (uint, 64, 4)
++__STRUCTN (poly, 8, 4)
++__STRUCTN (float, 64, 4)
++#undef __STRUCTN
++
++
++#define __ST2_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
++			qmode, ptr_mode, funcsuffix, signedtype)	     \
++__extension__ extern __inline void					     \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst2_lane_ ## funcsuffix (ptrtype *__ptr,				     \
++			  intype __b, const int __c)			     \
++{									     \
++  __builtin_aarch64_simd_oi __o;					     \
++  largetype __temp;							     \
++  __temp.val[0]								     \
++    = vcombine_##funcsuffix (__b.val[0],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[1]								     \
++    = vcombine_##funcsuffix (__b.val[1],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
++					     (signedtype) __temp.val[0], 0); \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
++					     (signedtype) __temp.val[1], 1); \
++  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
++				     __ptr, __o, __c);			     \
++}
++
++__ST2_LANE_FUNC (float16x4x2_t, float16x8x2_t, float16_t, v4hf, v8hf, hf, f16,
++		 float16x8_t)
++__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32,
++		 float32x4_t)
++__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, df, v2df, df, f64,
++		 float64x2_t)
++__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16,
++		 int16x8_t)
++__ST2_LANE_FUNC (poly64x1x2_t, poly64x2x2_t, poly64_t, di, v2di_ssps, di, p64,
++		 poly64x2_t)
++__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16,
++		 int16x8_t)
++__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32,
++		 int32x4_t)
++__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, di, v2di, di, u64,
++		 int64x2_t)
++
++#undef __ST2_LANE_FUNC
++#define __ST2_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
++__extension__ extern __inline void					    \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst2q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
++			   intype __b, const int __c)			    \
++{									    \
++  union { intype __i;							    \
++	  __builtin_aarch64_simd_oi __o; } __temp = { __b };		    \
++  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
++				    __ptr, __temp.__o, __c);		    \
++}
++
++__ST2_LANE_FUNC (float16x8x2_t, float16_t, v8hf, hf, f16)
++__ST2_LANE_FUNC (float32x4x2_t, float32_t, v4sf, sf, f32)
++__ST2_LANE_FUNC (float64x2x2_t, float64_t, v2df, df, f64)
++__ST2_LANE_FUNC (poly8x16x2_t, poly8_t, v16qi, qi, p8)
++__ST2_LANE_FUNC (poly16x8x2_t, poly16_t, v8hi, hi, p16)
++__ST2_LANE_FUNC (poly64x2x2_t, poly64_t, v2di, di, p64)
++__ST2_LANE_FUNC (int8x16x2_t, int8_t, v16qi, qi, s8)
++__ST2_LANE_FUNC (int16x8x2_t, int16_t, v8hi, hi, s16)
++__ST2_LANE_FUNC (int32x4x2_t, int32_t, v4si, si, s32)
++__ST2_LANE_FUNC (int64x2x2_t, int64_t, v2di, di, s64)
++__ST2_LANE_FUNC (uint8x16x2_t, uint8_t, v16qi, qi, u8)
++__ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16)
++__ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32)
++__ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64)
++
++#define __ST3_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
++			qmode, ptr_mode, funcsuffix, signedtype)	     \
++__extension__ extern __inline void					     \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst3_lane_ ## funcsuffix (ptrtype *__ptr,				     \
++			  intype __b, const int __c)			     \
++{									     \
++  __builtin_aarch64_simd_ci __o;					     \
++  largetype __temp;							     \
++  __temp.val[0]								     \
++    = vcombine_##funcsuffix (__b.val[0],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[1]								     \
++    = vcombine_##funcsuffix (__b.val[1],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[2]								     \
++    = vcombine_##funcsuffix (__b.val[2],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
++					     (signedtype) __temp.val[0], 0); \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
++					     (signedtype) __temp.val[1], 1); \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
++					     (signedtype) __temp.val[2], 2); \
++  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
++				     __ptr, __o, __c);			     \
++}
++
++__ST3_LANE_FUNC (float16x4x3_t, float16x8x3_t, float16_t, v4hf, v8hf, hf, f16,
++		 float16x8_t)
++__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32,
++		 float32x4_t)
++__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, df, v2df, df, f64,
++		 float64x2_t)
++__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16,
++		 int16x8_t)
++__ST3_LANE_FUNC (poly64x1x3_t, poly64x2x3_t, poly64_t, di, v2di_ssps, di, p64,
++		 poly64x2_t)
++__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16,
++		 int16x8_t)
++__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32,
++		 int32x4_t)
++__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, di, v2di, di, u64,
++		 int64x2_t)
++
++#undef __ST3_LANE_FUNC
++#define __ST3_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
++__extension__ extern __inline void					    \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst3q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
++			   intype __b, const int __c)			    \
++{									    \
++  union { intype __i;							    \
++	  __builtin_aarch64_simd_ci __o; } __temp = { __b };		    \
++  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
++				    __ptr, __temp.__o, __c);		    \
++}
++
++__ST3_LANE_FUNC (float16x8x3_t, float16_t, v8hf, hf, f16)
++__ST3_LANE_FUNC (float32x4x3_t, float32_t, v4sf, sf, f32)
++__ST3_LANE_FUNC (float64x2x3_t, float64_t, v2df, df, f64)
++__ST3_LANE_FUNC (poly8x16x3_t, poly8_t, v16qi, qi, p8)
++__ST3_LANE_FUNC (poly16x8x3_t, poly16_t, v8hi, hi, p16)
++__ST3_LANE_FUNC (poly64x2x3_t, poly64_t, v2di, di, p64)
++__ST3_LANE_FUNC (int8x16x3_t, int8_t, v16qi, qi, s8)
++__ST3_LANE_FUNC (int16x8x3_t, int16_t, v8hi, hi, s16)
++__ST3_LANE_FUNC (int32x4x3_t, int32_t, v4si, si, s32)
++__ST3_LANE_FUNC (int64x2x3_t, int64_t, v2di, di, s64)
++__ST3_LANE_FUNC (uint8x16x3_t, uint8_t, v16qi, qi, u8)
++__ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16)
++__ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32)
++__ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64)
++
++#define __ST4_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
++			qmode, ptr_mode, funcsuffix, signedtype)	     \
++__extension__ extern __inline void					     \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst4_lane_ ## funcsuffix (ptrtype *__ptr,				     \
++			  intype __b, const int __c)			     \
++{									     \
++  __builtin_aarch64_simd_xi __o;					     \
++  largetype __temp;							     \
++  __temp.val[0]								     \
++    = vcombine_##funcsuffix (__b.val[0],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[1]								     \
++    = vcombine_##funcsuffix (__b.val[1],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[2]								     \
++    = vcombine_##funcsuffix (__b.val[2],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[3]								     \
++    = vcombine_##funcsuffix (__b.val[3],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[0], 0); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[1], 1); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[2], 2); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[3], 3); \
++  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
++				     __ptr, __o, __c);			     \
++}
++
++__ST4_LANE_FUNC (float16x4x4_t, float16x8x4_t, float16_t, v4hf, v8hf, hf, f16,
++		 float16x8_t)
++__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32,
++		 float32x4_t)
++__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, df, v2df, df, f64,
++		 float64x2_t)
++__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16,
++		 int16x8_t)
++__ST4_LANE_FUNC (poly64x1x4_t, poly64x2x4_t, poly64_t, di, v2di_ssps, di, p64,
++		 poly64x2_t)
++__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16,
++		 int16x8_t)
++__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32,
++		 int32x4_t)
++__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, di, v2di, di, u64,
++		 int64x2_t)
++
++#undef __ST4_LANE_FUNC
++#define __ST4_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
++__extension__ extern __inline void					    \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst4q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
++			   intype __b, const int __c)			    \
++{									    \
++  union { intype __i;							    \
++	  __builtin_aarch64_simd_xi __o; } __temp = { __b };		    \
++  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
++				    __ptr, __temp.__o, __c);		    \
++}
++
++__ST4_LANE_FUNC (float16x8x4_t, float16_t, v8hf, hf, f16)
++__ST4_LANE_FUNC (float32x4x4_t, float32_t, v4sf, sf, f32)
++__ST4_LANE_FUNC (float64x2x4_t, float64_t, v2df, df, f64)
++__ST4_LANE_FUNC (poly8x16x4_t, poly8_t, v16qi, qi, p8)
++__ST4_LANE_FUNC (poly16x8x4_t, poly16_t, v8hi, hi, p16)
++__ST4_LANE_FUNC (poly64x2x4_t, poly64_t, v2di, di, p64)
++__ST4_LANE_FUNC (int8x16x4_t, int8_t, v16qi, qi, s8)
++__ST4_LANE_FUNC (int16x8x4_t, int16_t, v8hi, hi, s16)
++__ST4_LANE_FUNC (int32x4x4_t, int32_t, v4si, si, s32)
++__ST4_LANE_FUNC (int64x2x4_t, int64_t, v2di, di, s64)
++__ST4_LANE_FUNC (uint8x16x4_t, uint8_t, v16qi, qi, u8)
++__ST4_LANE_FUNC (uint16x8x4_t, uint16_t, v8hi, hi, u16)
++__ST4_LANE_FUNC (uint32x4x4_t, uint32_t, v4si, si, u32)
++__ST4_LANE_FUNC (uint64x2x4_t, uint64_t, v2di, di, u64)
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddlv_s32 (int32x2_t a)
++{
++  int64_t result;
++  __asm__ ("saddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
++  return result;
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddlv_u32 (uint32x2_t a)
++{
++  uint64_t result;
++  __asm__ ("uaddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv4si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++{
++  return  __builtin_aarch64_sqrdmulh_laneqv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqrdmulh_laneqv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++{
++  return __builtin_aarch64_sqrdmulh_laneqv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqrdmulh_laneqv4si (__a, __b, __c);
++}
++
++/* Table intrinsics.  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1_p8 (poly8x16_t a, uint8x8_t b)
++{
++  poly8x8_t result;
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1_s8 (int8x16_t a, uint8x8_t b)
++{
++  int8x8_t result;
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1_u8 (uint8x16_t a, uint8x8_t b)
++{
++  uint8x8_t result;
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1q_p8 (poly8x16_t a, uint8x16_t b)
++{
++  poly8x16_t result;
++  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1q_s8 (int8x16_t a, uint8x16_t b)
++{
++  int8x16_t result;
++  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1q_u8 (uint8x16_t a, uint8x16_t b)
++{
++  uint8x16_t result;
++  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1_s8 (int8x8_t r, int8x16_t tab, uint8x8_t idx)
++{
++  int8x8_t result = r;
++  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1_u8 (uint8x8_t r, uint8x16_t tab, uint8x8_t idx)
++{
++  uint8x8_t result = r;
++  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1_p8 (poly8x8_t r, poly8x16_t tab, uint8x8_t idx)
++{
++  poly8x8_t result = r;
++  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1q_s8 (int8x16_t r, int8x16_t tab, uint8x16_t idx)
++{
++  int8x16_t result = r;
++  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1q_u8 (uint8x16_t r, uint8x16_t tab, uint8x16_t idx)
++{
++  uint8x16_t result = r;
++  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1q_p8 (poly8x16_t r, poly8x16_t tab, uint8x16_t idx)
++{
++  poly8x16_t result = r;
++  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++/* V7 legacy table intrinsics.  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl1_s8 (int8x8_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl1_u8 (uint8x8_t tab, uint8x8_t idx)
++{
+   uint8x8_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
++  uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl1_p8 (poly8x8_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl2_s8 (int8x8x2_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl2_u8 (uint8x8x2_t tab, uint8x8_t idx)
++{
++  uint8x8_t result;
++  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl2_p8 (poly8x8x2_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl3_s8 (int8x8x3_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = __builtin_aarch64_tbl3v8qi (__o, idx);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl3_u8 (uint8x8x3_t tab, uint8x8_t idx)
++{
++  uint8x8_t result;
++  uint8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl3_p8 (poly8x8x3_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl4_s8 (int8x8x4_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_s8 (tab.val[2], tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = __builtin_aarch64_tbl3v8qi (__o, idx);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl4_u8 (uint8x8x4_t tab, uint8x8_t idx)
++{
++  uint8x8_t result;
++  uint8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_u8 (tab.val[2], tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl4_p8 (poly8x8x4_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_p8 (tab.val[2], tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx2_s8 (int8x8_t r, int8x8x2_t tab, int8x8_t idx)
++{
++  int8x8_t result = r;
++  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
++           : "+w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx2_u8 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx)
++{
++  uint8x8_t result = r;
++  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
++           : "+w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx2_p8 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx)
++{
++  poly8x8_t result = r;
++  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
++           : "+w"(result)
++           : "w"(temp), "w"(idx)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmvn_u16 (uint16x4_t a)
++/* End of temporary inline asm.  */
++
++/* Start of optimal implementations in approved order.  */
++
++/* vabd.  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabds_f32 (float32_t __a, float32_t __b)
++{
++  return __builtin_aarch64_fabdsf (__a, __b);
++}
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdd_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_aarch64_fabddf (__a, __b);
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return __builtin_aarch64_fabdv2sf (__a, __b);
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (float64x1_t) {vabdd_f64 (vget_lane_f64 (__a, 0),
++				   vget_lane_f64 (__b, 0))};
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return __builtin_aarch64_fabdv4sf (__a, __b);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return __builtin_aarch64_fabdv2df (__a, __b);
++}
++
++/* vabs  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f32 (float32x2_t __a)
++{
++  return __builtin_aarch64_absv2sf (__a);
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f64 (float64x1_t __a)
++{
++  return (float64x1_t) {__builtin_fabs (__a[0])};
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s8 (int8x8_t __a)
++{
++  return __builtin_aarch64_absv8qi (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s16 (int16x4_t __a)
++{
++  return __builtin_aarch64_absv4hi (__a);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s32 (int32x2_t __a)
++{
++  return __builtin_aarch64_absv2si (__a);
++}
++
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s64 (int64x1_t __a)
++{
++  return (int64x1_t) {__builtin_aarch64_absdi (__a[0])};
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f32 (float32x4_t __a)
++{
++  return __builtin_aarch64_absv4sf (__a);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f64 (float64x2_t __a)
++{
++  return __builtin_aarch64_absv2df (__a);
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s8 (int8x16_t __a)
++{
++  return __builtin_aarch64_absv16qi (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s16 (int16x8_t __a)
++{
++  return __builtin_aarch64_absv8hi (__a);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s32 (int32x4_t __a)
++{
++  return __builtin_aarch64_absv4si (__a);
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s64 (int64x2_t __a)
++{
++  return __builtin_aarch64_absv2di (__a);
++}
++
++/* vadd */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddd_s64 (int64_t __a, int64_t __b)
++{
++  return __a + __b;
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddd_u64 (uint64_t __a, uint64_t __b)
++{
++  return __a + __b;
++}
++
++/* vaddv */
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_s8 (int8x8_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v8qi (__a);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_s16 (int16x4_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v4hi (__a);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_s32 (int32x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2si (__a);
++}
++
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_u8 (uint8x8_t __a)
++{
++  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v8qi ((int8x8_t) __a);
++}
++
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_u16 (uint16x4_t __a)
++{
++  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v4hi ((int16x4_t) __a);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_u32 (uint32x2_t __a)
++{
++  return (int32_t) __builtin_aarch64_reduc_plus_scal_v2si ((int32x2_t) __a);
++}
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s8 (int8x16_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v16qi (__a);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s16 (int16x8_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v8hi (__a);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s32 (int32x4_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v4si (__a);
++}
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s64 (int64x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2di (__a);
++}
++
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u8 (uint8x16_t __a)
++{
++  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v16qi ((int8x16_t) __a);
++}
++
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u16 (uint16x8_t __a)
++{
++  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v8hi ((int16x8_t) __a);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u32 (uint32x4_t __a)
++{
++  return (uint32_t) __builtin_aarch64_reduc_plus_scal_v4si ((int32x4_t) __a);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u64 (uint64x2_t __a)
++{
++  return (uint64_t) __builtin_aarch64_reduc_plus_scal_v2di ((int64x2_t) __a);
++}
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_f32 (float32x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2sf (__a);
++}
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_f32 (float32x4_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v4sf (__a);
++}
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_f64 (float64x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
++}
++
++/* vbsl  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f16 (uint16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2sf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f64 (uint64x1_t __a, float64x1_t __b, float64x1_t __c)
++{
++  return (float64x1_t)
++    { __builtin_aarch64_simd_bsldf_suss (__a[0], __b[0], __c[0]) };
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8qi_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hi_pupp (__a, __b, __c);
++}
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_p64 (uint64x1_t __a, poly64x1_t __b, poly64x1_t __c)
++{
++  return (poly64x1_t)
++      {__builtin_aarch64_simd_bsldi_pupp (__a[0], __b[0], __c[0])};
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8qi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2si_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
++{
++  return (int64x1_t)
++      {__builtin_aarch64_simd_bsldi_suss (__a[0], __b[0], __c[0])};
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8qi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2si_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
++{
++  return (uint64x1_t)
++      {__builtin_aarch64_simd_bsldi_uuuu (__a[0], __b[0], __c[0])};
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f16 (uint16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4sf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f64 (uint64x2_t __a, float64x2_t __b, float64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2df_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
++{
++  return __builtin_aarch64_simd_bslv16qi_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hi_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
++{
++  return __builtin_aarch64_simd_bslv16qi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_p64 (uint64x2_t __a, poly64x2_t __b, poly64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2di_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4si_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2di_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
++{
++  return __builtin_aarch64_simd_bslv16qi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4si_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c);
++}
++
++/* ARMv8.1-A instrinsics.  */
++#pragma GCC push_options
++#pragma GCC target ("arch=armv8.1-a")
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv4si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv4si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlah_laneqv4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqv2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqv8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqv4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlsh_laneqv4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqv2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqv8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqv4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlah_lanev4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanev2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanev8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanev4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahh_s16 (int16_t __a, int16_t __b, int16_t __c)
++{
++  return (int16_t) __builtin_aarch64_sqrdmlahhi (__a, __b, __c);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanehi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqhi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahs_s32 (int32_t __a, int32_t __b, int32_t __c)
++{
++  return (int32_t) __builtin_aarch64_sqrdmlahsi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanesi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqsi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlsh_lanev4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanev2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanev8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanev4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshh_s16 (int16_t __a, int16_t __b, int16_t __c)
++{
++  return (int16_t) __builtin_aarch64_sqrdmlshhi (__a, __b, __c);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanehi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqhi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshs_s32 (int32_t __a, int32_t __b, int32_t __c)
++{
++  return (int32_t) __builtin_aarch64_sqrdmlshsi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanesi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqsi (__a, __b, __c, __d);
++}
++#pragma GCC pop_options
++
++#pragma GCC push_options
++#pragma GCC target ("+nothing+crypto")
++/* vaes  */
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaeseq_u8 (uint8x16_t data, uint8x16_t key)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesev16qi_uuu (data, key);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmvn_u32 (uint32x2_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaesdq_u8 (uint8x16_t data, uint8x16_t key)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesdv16qi_uuu (data, key);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vmvnq_p8 (poly8x16_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaesmcq_u8 (uint8x16_t data)
+ {
+-  poly8x16_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesmcv16qi_uu (data);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmvnq_s8 (int8x16_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaesimcq_u8 (uint8x16_t data)
+ {
+-  int8x16_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesimcv16qi_uu (data);
+ }
++#pragma GCC pop_options
++
++/* vcage  */
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmvnq_s16 (int16x8_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return vabs_f64 (__a) >= vabs_f64 (__b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmvnq_s32 (int32x4_t a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcages_f32 (float32_t __a, float32_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_fabsf (__a) >= __builtin_fabsf (__b) ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmvnq_u8 (uint8x16_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  uint8x16_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return vabs_f32 (__a) >= vabs_f32 (__b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmvnq_u16 (uint16x8_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return vabsq_f32 (__a) >= vabsq_f32 (__b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmvnq_u32 (uint32x4_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaged_f64 (float64_t __a, float64_t __b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_fabs (__a) >= __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) >= vabsq_f64 (__b);
+ }
+ 
++/* vcagt  */
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpadal_s8 (int16x4_t a, int8x8_t b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagts_f32 (float32_t __a, float32_t __b)
+ {
+-  int16x4_t result;
+-  __asm__ ("sadalp %0.4h,%2.8b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_fabsf (__a) > __builtin_fabsf (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return vabs_f32 (__a) > vabs_f32 (__b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return vabs_f64 (__a) > vabs_f64 (__b);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return vabsq_f32 (__a) > vabsq_f32 (__b);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtd_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_fabs (__a) > __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) > vabsq_f64 (__b);
++}
++
++/* vcale  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return vabs_f32 (__a) <= vabs_f32 (__b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return vabs_f64 (__a) <= vabs_f64 (__b);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaled_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcales_f32 (float32_t __a, float32_t __b)
++{
++  return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return vabsq_f32 (__a) <= vabsq_f32 (__b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) <= vabsq_f64 (__b);
++}
++
++/* vcalt  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return vabs_f32 (__a) < vabs_f32 (__b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return vabs_f64 (__a) < vabs_f64 (__b);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltd_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return vabsq_f32 (__a) < vabsq_f32 (__b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) < vabsq_f64 (__b);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalts_f32 (float32_t __a, float32_t __b)
++{
++  return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
++}
++
++/* vceq - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return (uint32x2_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (uint64x1_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_p8 (poly8x8_t __a, poly8x8_t __b)
++{
++  return (uint8x8_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_p64 (poly64x1_t __a, poly64x1_t __b)
++{
++  return (uint64x1_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s8 (int8x8_t __a, int8x8_t __b)
++{
++  return (uint8x8_t) (__a == __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a == __b);
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s32 (int32x2_t __a, int32x2_t __b)
++{
++  return (uint32x2_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (uint64x1_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u8 (uint8x8_t __a, uint8x8_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u16 (uint16x4_t __a, uint16x4_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u32 (uint32x2_t __a, uint32x2_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u64 (uint64x1_t __a, uint64x1_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return (uint32x4_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return (uint64x2_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_p8 (poly8x16_t __a, poly8x16_t __b)
++{
++  return (uint8x16_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s8 (int8x16_t __a, int8x16_t __b)
++{
++  return (uint8x16_t) (__a == __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpadal_s16 (int32x2_t a, int16x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int32x2_t result;
+-  __asm__ ("sadalp %0.2s,%2.4h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a == __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vpadal_s32 (int64x1_t a, int32x2_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  int64x1_t result;
+-  __asm__ ("sadalp %0.1d,%2.2s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a == __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpadal_u8 (uint16x4_t a, uint8x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  uint16x4_t result;
+-  __asm__ ("uadalp %0.4h,%2.8b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a == __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpadal_u16 (uint32x2_t a, uint16x4_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  uint32x2_t result;
+-  __asm__ ("uadalp %0.2s,%2.4h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vpadal_u32 (uint64x1_t a, uint32x2_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  uint64x1_t result;
+-  __asm__ ("uadalp %0.1d,%2.2s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpadalq_s8 (int16x8_t a, int8x16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sadalp %0.8h,%2.16b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpadalq_s16 (int32x4_t a, int16x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sadalp %0.4s,%2.8h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vpadalq_s32 (int64x2_t a, int32x4_t b)
++/* vceq - scalar.  */
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqs_f32 (float32_t __a, float32_t __b)
+ {
+-  int64x2_t result;
+-  __asm__ ("sadalp %0.2d,%2.4s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpadalq_u8 (uint16x8_t a, uint8x16_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqd_s64 (int64_t __a, int64_t __b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("uadalp %0.8h,%2.16b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpadalq_u16 (uint32x4_t a, uint16x8_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("uadalp %0.4s,%2.8h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vpadalq_u32 (uint64x2_t a, uint32x4_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqd_f64 (float64_t __a, float64_t __b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("uadalp %0.2d,%2.4s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpadd_f32 (float32x2_t a, float32x2_t b)
++/* vceqz - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f32 (float32x2_t __a)
+ {
+-  float32x2_t result;
+-  __asm__ ("faddp %0.2s,%1.2s,%2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a == 0.0f);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpaddl_s8 (int8x8_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f64 (float64x1_t __a)
+ {
+-  int16x4_t result;
+-  __asm__ ("saddlp %0.4h,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a == (float64x1_t) {0.0});
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpaddl_s16 (int16x4_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_p8 (poly8x8_t __a)
+ {
+-  int32x2_t result;
+-  __asm__ ("saddlp %0.2s,%1.4h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vpaddl_s32 (int32x2_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s8 (int8x8_t __a)
+ {
+-  int64x1_t result;
+-  __asm__ ("saddlp %0.1d,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpaddl_u8 (uint8x8_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s16 (int16x4_t __a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("uaddlp %0.4h,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x4_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpaddl_u16 (uint16x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s32 (int32x2_t __a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("uaddlp %0.2s,%1.4h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vpaddl_u32 (uint32x2_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s64 (int64x1_t __a)
+ {
+-  uint64x1_t result;
+-  __asm__ ("uaddlp %0.1d,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a == __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpaddlq_s8 (int8x16_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u8 (uint8x8_t __a)
+ {
+-  int16x8_t result;
+-  __asm__ ("saddlp %0.8h,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpaddlq_s16 (int16x8_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u16 (uint16x4_t __a)
+ {
+-  int32x4_t result;
+-  __asm__ ("saddlp %0.4s,%1.8h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vpaddlq_s32 (int32x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u32 (uint32x2_t __a)
+ {
+-  int64x2_t result;
+-  __asm__ ("saddlp %0.2d,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpaddlq_u8 (uint8x16_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u64 (uint64x1_t __a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("uaddlp %0.8h,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpaddlq_u16 (uint16x8_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f32 (float32x4_t __a)
+ {
+-  uint32x4_t result;
+-  __asm__ ("uaddlp %0.4s,%1.8h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a == 0.0f);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vpaddlq_u32 (uint32x4_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f64 (float64x2_t __a)
+ {
+-  uint64x2_t result;
+-  __asm__ ("uaddlp %0.2d,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a == 0.0f);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpaddq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_p8 (poly8x16_t __a)
+ {
+-  float32x4_t result;
+-  __asm__ ("faddp %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpaddq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s8 (int8x16_t __a)
+ {
+-  float64x2_t result;
+-  __asm__ ("faddp %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vpaddq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s16 (int16x8_t __a)
+ {
+-  int8x16_t result;
+-  __asm__ ("addp %0.16b,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpaddq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s32 (int32x4_t __a)
+ {
+-  int16x8_t result;
+-  __asm__ ("addp %0.8h,%1.8h,%2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a == 0);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s64 (int64x2_t __a)
++{
++  return (uint64x2_t) (__a == __AARCH64_INT64_C (0));
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u8 (uint8x16_t __a)
++{
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpaddq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u16 (uint16x8_t __a)
+ {
+-  int32x4_t result;
+-  __asm__ ("addp %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vpaddq_s64 (int64x2_t a, int64x2_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u32 (uint32x4_t __a)
+ {
+-  int64x2_t result;
+-  __asm__ ("addp %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vpaddq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u64 (uint64x2_t __a)
+ {
+-  uint8x16_t result;
+-  __asm__ ("addp %0.16b,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpaddq_u16 (uint16x8_t a, uint16x8_t b)
++/* vceqz - scalar.  */
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzs_f32 (float32_t __a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("addp %0.8h,%1.8h,%2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0.0f ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpaddq_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzd_s64 (int64_t __a)
+ {
+-  uint32x4_t result;
+-  __asm__ ("addp %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vpaddq_u64 (uint64x2_t a, uint64x2_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzd_u64 (uint64_t __a)
+ {
+-  uint64x2_t result;
+-  __asm__ ("addp %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpadds_f32 (float32x2_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzd_f64 (float64_t __a)
+ {
+-  float32_t result;
+-  __asm__ ("faddp %s0,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0.0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqdmulh_n_s16 (int16x4_t a, int16_t b)
++/* vcge - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  int16x4_t result;
+-  __asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqdmulh_n_s32 (int32x2_t a, int32_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int32x2_t result;
+-  __asm__ ("sqdmulh %0.2s,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqdmulhq_n_s16 (int16x8_t a, int16_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmulhq_n_s32 (int32x4_t a, int32_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sqdmulh %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x4_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqmovn_high_s16 (int8x8_t a, int16x8_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtn2 %0.16b, %1.8h"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqmovn_high_s32 (int16x4_t a, int32x4_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtn2 %0.8h, %1.4s"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqmovn_high_s64 (int32x2_t a, int64x2_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtn2 %0.4s, %1.2d"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqmovn_high_u16 (uint8x8_t a, uint16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("uqxtn2 %0.16b, %1.8h"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqmovn_high_u32 (uint16x4_t a, uint32x4_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("uqxtn2 %0.8h, %1.4s"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqmovn_high_u64 (uint32x2_t a, uint64x2_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+-  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("uqxtn2 %0.4s, %1.2d"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqmovun_high_s16 (uint8x8_t a, int16x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtun2 %0.16b, %1.8h"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqmovun_high_s32 (uint16x4_t a, int32x4_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtun2 %0.8h, %1.4s"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqmovun_high_s64 (uint32x2_t a, int64x2_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtun2 %0.4s, %1.2d"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmulh_n_s16 (int16x4_t a, int16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int16x4_t result;
+-  __asm__ ("sqrdmulh %0.4h,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmulh_n_s32 (int32x2_t a, int32_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  int32x2_t result;
+-  __asm__ ("sqrdmulh %0.2s,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmulhq_n_s16 (int16x8_t a, int16_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sqrdmulh %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmulhq_n_s32 (int32x4_t a, int32_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sqrdmulh %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-#define vqrshrn_high_n_s16(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqrshrn2 %0.16b, %1.8h, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
++{
++  return (__a >= __b);
++}
+ 
+-#define vqrshrn_high_n_s32(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqrshrn2 %0.8h, %1.4s, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
++{
++  return (__a >= __b);
++}
+ 
+-#define vqrshrn_high_n_s64(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqrshrn2 %0.4s, %1.2d, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)
++{
++  return (__a >= __b);
++}
+ 
+-#define vqrshrn_high_n_u16(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqrshrn2 %0.16b, %1.8h, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcge - scalar.  */
+ 
+-#define vqrshrn_high_n_u32(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqrshrn2 %0.8h, %1.4s, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcges_f32 (float32_t __a, float32_t __b)
++{
++  return __a >= __b ? -1 : 0;
++}
+ 
+-#define vqrshrn_high_n_u64(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqrshrn2 %0.4s, %1.2d, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcged_s64 (int64_t __a, int64_t __b)
++{
++  return __a >= __b ? -1ll : 0ll;
++}
+ 
+-#define vqrshrun_high_n_s16(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqrshrun2 %0.16b, %1.8h, #%2"                          \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcged_u64 (uint64_t __a, uint64_t __b)
++{
++  return __a >= __b ? -1ll : 0ll;
++}
+ 
+-#define vqrshrun_high_n_s32(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqrshrun2 %0.8h, %1.4s, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcged_f64 (float64_t __a, float64_t __b)
++{
++  return __a >= __b ? -1ll : 0ll;
++}
+ 
+-#define vqrshrun_high_n_s64(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqrshrun2 %0.4s, %1.2d, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgez - vector.  */
+ 
+-#define vqshrn_high_n_s16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqshrn2 %0.16b, %1.8h, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f32 (float32x2_t __a)
++{
++  return (uint32x2_t) (__a >= 0.0f);
++}
+ 
+-#define vqshrn_high_n_s32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqshrn2 %0.8h, %1.4s, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f64 (float64x1_t __a)
++{
++  return (uint64x1_t) (__a[0] >= (float64x1_t) {0.0});
++}
+ 
+-#define vqshrn_high_n_s64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqshrn2 %0.4s, %1.2d, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s8 (int8x8_t __a)
++{
++  return (uint8x8_t) (__a >= 0);
++}
+ 
+-#define vqshrn_high_n_u16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqshrn2 %0.16b, %1.8h, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s16 (int16x4_t __a)
++{
++  return (uint16x4_t) (__a >= 0);
++}
+ 
+-#define vqshrn_high_n_u32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqshrn2 %0.8h, %1.4s, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s32 (int32x2_t __a)
++{
++  return (uint32x2_t) (__a >= 0);
++}
+ 
+-#define vqshrn_high_n_u64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqshrn2 %0.4s, %1.2d, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s64 (int64x1_t __a)
++{
++  return (uint64x1_t) (__a >= __AARCH64_INT64_C (0));
++}
+ 
+-#define vqshrun_high_n_s16(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqshrun2 %0.16b, %1.8h, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f32 (float32x4_t __a)
++{
++  return (uint32x4_t) (__a >= 0.0f);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f64 (float64x2_t __a)
++{
++  return (uint64x2_t) (__a >= 0.0);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s8 (int8x16_t __a)
++{
++  return (uint8x16_t) (__a >= 0);
++}
+ 
+-#define vqshrun_high_n_s32(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqshrun2 %0.8h, %1.4s, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s16 (int16x8_t __a)
++{
++  return (uint16x8_t) (__a >= 0);
++}
+ 
+-#define vqshrun_high_n_s64(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqshrun2 %0.4s, %1.2d, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s32 (int32x4_t __a)
++{
++  return (uint32x4_t) (__a >= 0);
++}
+ 
+-#define vrshrn_high_n_s16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s64 (int64x2_t __a)
++{
++  return (uint64x2_t) (__a >= __AARCH64_INT64_C (0));
++}
+ 
+-#define vrshrn_high_n_s32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgez - scalar.  */
+ 
+-#define vrshrn_high_n_s64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezs_f32 (float32_t __a)
++{
++  return __a >= 0.0f ? -1 : 0;
++}
+ 
+-#define vrshrn_high_n_u16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                            (a_, vcreate_u8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezd_s64 (int64_t __a)
++{
++  return __a >= 0 ? -1ll : 0ll;
++}
+ 
+-#define vrshrn_high_n_u32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                            (a_, vcreate_u16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezd_f64 (float64_t __a)
++{
++  return __a >= 0.0 ? -1ll : 0ll;
++}
+ 
+-#define vrshrn_high_n_u64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                            (a_, vcreate_u32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgt - vector.  */
+ 
+-#define vrshrn_n_s16(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t a_ = (a);                                              \
+-       int8x8_t result;                                                 \
+-       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return (uint32x2_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_s32(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t a_ = (a);                                              \
+-       int16x4_t result;                                                \
+-       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (uint64x1_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_s64(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t a_ = (a);                                              \
+-       int32x2_t result;                                                \
+-       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s8 (int8x8_t __a, int8x8_t __b)
++{
++  return (uint8x8_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_u16(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t a_ = (a);                                             \
+-       uint8x8_t result;                                                \
+-       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_u32(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t a_ = (a);                                             \
+-       uint16x4_t result;                                               \
+-       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s32 (int32x2_t __a, int32x2_t __b)
++{
++  return (uint32x2_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_u64(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t a_ = (a);                                             \
+-       uint32x2_t result;                                               \
+-       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (uint64x1_t) (__a > __b);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrsqrte_f32 (float32x2_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  float32x2_t result;
+-  __asm__ ("frsqrte %0.2s,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrsqrte_f64 (float64x1_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  float64x1_t result;
+-  __asm__ ("frsqrte %d0,%d1"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrsqrte_u32 (uint32x2_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint32x2_t result;
+-  __asm__ ("ursqrte %0.2s,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrsqrted_f64 (float64_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+-  float64_t result;
+-  __asm__ ("frsqrte %d0,%d1"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrsqrteq_f32 (float32x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  float32x4_t result;
+-  __asm__ ("frsqrte %0.4s,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrsqrteq_f64 (float64x2_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  float64x2_t result;
+-  __asm__ ("frsqrte %0.2d,%1.2d"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrsqrteq_u32 (uint32x4_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("ursqrte %0.4s,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrsqrtes_f32 (float32_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  float32_t result;
+-  __asm__ ("frsqrte %s0,%s1"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrsqrts_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  float32x2_t result;
+-  __asm__ ("frsqrts %0.2s,%1.2s,%2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrsqrtsd_f64 (float64_t a, float64_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  float64_t result;
+-  __asm__ ("frsqrts %d0,%d1,%d2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrsqrtsq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  float32x4_t result;
+-  __asm__ ("frsqrts %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrsqrtsq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  float64x2_t result;
+-  __asm__ ("frsqrts %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrsqrtss_f32 (float32_t a, float32_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  float32_t result;
+-  __asm__ ("frsqrts %s0,%s1,%s2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-#define vshrn_high_n_s16(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_s32(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_s64(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_u16(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                            (a_, vcreate_u8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_u32(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                            (a_, vcreate_u16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_u64(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                            (a_, vcreate_u32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)
++{
++  return (__a > __b);
++}
+ 
+-#define vshrn_n_s16(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t a_ = (a);                                              \
+-       int8x8_t result;                                                 \
+-       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgt - scalar.  */
+ 
+-#define vshrn_n_s32(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t a_ = (a);                                              \
+-       int16x4_t result;                                                \
+-       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgts_f32 (float32_t __a, float32_t __b)
++{
++  return __a > __b ? -1 : 0;
++}
+ 
+-#define vshrn_n_s64(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t a_ = (a);                                              \
+-       int32x2_t result;                                                \
+-       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtd_s64 (int64_t __a, int64_t __b)
++{
++  return __a > __b ? -1ll : 0ll;
++}
+ 
+-#define vshrn_n_u16(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t a_ = (a);                                             \
+-       uint8x8_t result;                                                \
+-       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtd_u64 (uint64_t __a, uint64_t __b)
++{
++  return __a > __b ? -1ll : 0ll;
++}
+ 
+-#define vshrn_n_u32(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t a_ = (a);                                             \
+-       uint16x4_t result;                                               \
+-       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtd_f64 (float64_t __a, float64_t __b)
++{
++  return __a > __b ? -1ll : 0ll;
++}
+ 
+-#define vshrn_n_u64(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t a_ = (a);                                             \
+-       uint32x2_t result;                                               \
+-       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgtz - vector.  */
+ 
+-#define vsli_n_p8(a, b, c)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x8_t b_ = (b);                                              \
+-       poly8x8_t a_ = (a);                                              \
+-       poly8x8_t result;                                                \
+-       __asm__ ("sli %0.8b,%2.8b,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f32 (float32x2_t __a)
++{
++  return (uint32x2_t) (__a > 0.0f);
++}
+ 
+-#define vsli_n_p16(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x4_t b_ = (b);                                             \
+-       poly16x4_t a_ = (a);                                             \
+-       poly16x4_t result;                                               \
+-       __asm__ ("sli %0.4h,%2.4h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f64 (float64x1_t __a)
++{
++  return (uint64x1_t) (__a > (float64x1_t) {0.0});
++}
+ 
+-#define vsliq_n_p8(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x16_t b_ = (b);                                             \
+-       poly8x16_t a_ = (a);                                             \
+-       poly8x16_t result;                                               \
+-       __asm__ ("sli %0.16b,%2.16b,%3"                                  \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s8 (int8x8_t __a)
++{
++  return (uint8x8_t) (__a > 0);
++}
+ 
+-#define vsliq_n_p16(a, b, c)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x8_t b_ = (b);                                             \
+-       poly16x8_t a_ = (a);                                             \
+-       poly16x8_t result;                                               \
+-       __asm__ ("sli %0.8h,%2.8h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s16 (int16x4_t __a)
++{
++  return (uint16x4_t) (__a > 0);
++}
+ 
+-#define vsri_n_p8(a, b, c)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x8_t b_ = (b);                                              \
+-       poly8x8_t a_ = (a);                                              \
+-       poly8x8_t result;                                                \
+-       __asm__ ("sri %0.8b,%2.8b,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s32 (int32x2_t __a)
++{
++  return (uint32x2_t) (__a > 0);
++}
+ 
+-#define vsri_n_p16(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x4_t b_ = (b);                                             \
+-       poly16x4_t a_ = (a);                                             \
+-       poly16x4_t result;                                               \
+-       __asm__ ("sri %0.4h,%2.4h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s64 (int64x1_t __a)
++{
++  return (uint64x1_t) (__a > __AARCH64_INT64_C (0));
++}
+ 
+-#define vsriq_n_p8(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x16_t b_ = (b);                                             \
+-       poly8x16_t a_ = (a);                                             \
+-       poly8x16_t result;                                               \
+-       __asm__ ("sri %0.16b,%2.16b,%3"                                  \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f32 (float32x4_t __a)
++{
++  return (uint32x4_t) (__a > 0.0f);
++}
+ 
+-#define vsriq_n_p16(a, b, c)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x8_t b_ = (b);                                             \
+-       poly16x8_t a_ = (a);                                             \
+-       poly16x8_t result;                                               \
+-       __asm__ ("sri %0.8h,%2.8h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f64 (float64x2_t __a)
++{
++    return (uint64x2_t) (__a > 0.0);
++}
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtst_p8 (poly8x8_t a, poly8x8_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s8 (int8x16_t __a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("cmtst %0.8b, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a > 0);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtst_p16 (poly16x4_t a, poly16x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s16 (int16x8_t __a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("cmtst %0.4h, %1.4h, %2.4h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a > 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtstq_p8 (poly8x16_t a, poly8x16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s32 (int32x4_t __a)
+ {
+-  uint8x16_t result;
+-  __asm__ ("cmtst %0.16b, %1.16b, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a > 0);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtstq_p16 (poly16x8_t a, poly16x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s64 (int64x2_t __a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("cmtst %0.8h, %1.8h, %2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a > __AARCH64_INT64_C (0));
+ }
+ 
+-/* End of temporary inline asm implementations.  */
++/* vcgtz - scalar.  */
+ 
+-/* Start of temporary inline asm for vldn, vstn and friends.  */
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzs_f32 (float32_t __a)
++{
++  return __a > 0.0f ? -1 : 0;
++}
+ 
+-/* Create struct element types for duplicating loads.
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzd_s64 (int64_t __a)
++{
++  return __a > 0 ? -1ll : 0ll;
++}
+ 
+-   Create 2 element structures of:
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzd_f64 (float64_t __a)
++{
++  return __a > 0.0 ? -1ll : 0ll;
++}
+ 
+-   +------+----+----+----+----+
+-   |      | 8  | 16 | 32 | 64 |
+-   +------+----+----+----+----+
+-   |int   | Y  | Y  | N  | N  |
+-   +------+----+----+----+----+
+-   |uint  | Y  | Y  | N  | N  |
+-   +------+----+----+----+----+
+-   |float | -  | Y  | N  | N  |
+-   +------+----+----+----+----+
+-   |poly  | Y  | Y  | -  | -  |
+-   +------+----+----+----+----+
++/* vcle - vector.  */
+ 
+-   Create 3 element structures of:
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return (uint32x2_t) (__a <= __b);
++}
+ 
+-   +------+----+----+----+----+
+-   |      | 8  | 16 | 32 | 64 |
+-   +------+----+----+----+----+
+-   |int   | Y  | Y  | Y  | Y  |
+-   +------+----+----+----+----+
+-   |uint  | Y  | Y  | Y  | Y  |
+-   +------+----+----+----+----+
+-   |float | -  | Y  | Y  | Y  |
+-   +------+----+----+----+----+
+-   |poly  | Y  | Y  | -  | -  |
+-   +------+----+----+----+----+
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (uint64x1_t) (__a <= __b);
++}
+ 
+-   Create 4 element structures of:
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s8 (int8x8_t __a, int8x8_t __b)
++{
++  return (uint8x8_t) (__a <= __b);
++}
+ 
+-   +------+----+----+----+----+
+-   |      | 8  | 16 | 32 | 64 |
+-   +------+----+----+----+----+
+-   |int   | Y  | N  | N  | Y  |
+-   +------+----+----+----+----+
+-   |uint  | Y  | N  | N  | Y  |
+-   +------+----+----+----+----+
+-   |float | -  | N  | N  | Y  |
+-   +------+----+----+----+----+
+-   |poly  | Y  | N  | -  | -  |
+-   +------+----+----+----+----+
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a <= __b);
++}
+ 
+-  This is required for casting memory reference.  */
+-#define __STRUCTN(t, sz, nelem)			\
+-  typedef struct t ## sz ## x ## nelem ## _t {	\
+-    t ## sz ## _t val[nelem];			\
+-  }  t ## sz ## x ## nelem ## _t;
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s32 (int32x2_t __a, int32x2_t __b)
++{
++  return (uint32x2_t) (__a <= __b);
++}
+ 
+-/* 2-element structs.  */
+-__STRUCTN (int, 8, 2)
+-__STRUCTN (int, 16, 2)
+-__STRUCTN (uint, 8, 2)
+-__STRUCTN (uint, 16, 2)
+-__STRUCTN (float, 16, 2)
+-__STRUCTN (poly, 8, 2)
+-__STRUCTN (poly, 16, 2)
+-/* 3-element structs.  */
+-__STRUCTN (int, 8, 3)
+-__STRUCTN (int, 16, 3)
+-__STRUCTN (int, 32, 3)
+-__STRUCTN (int, 64, 3)
+-__STRUCTN (uint, 8, 3)
+-__STRUCTN (uint, 16, 3)
+-__STRUCTN (uint, 32, 3)
+-__STRUCTN (uint, 64, 3)
+-__STRUCTN (float, 16, 3)
+-__STRUCTN (float, 32, 3)
+-__STRUCTN (float, 64, 3)
+-__STRUCTN (poly, 8, 3)
+-__STRUCTN (poly, 16, 3)
+-/* 4-element structs.  */
+-__STRUCTN (int, 8, 4)
+-__STRUCTN (int, 64, 4)
+-__STRUCTN (uint, 8, 4)
+-__STRUCTN (uint, 64, 4)
+-__STRUCTN (poly, 8, 4)
+-__STRUCTN (float, 64, 4)
+-#undef __STRUCTN
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (uint64x1_t) (__a <= __b);
++}
+ 
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u8 (uint8x8_t __a, uint8x8_t __b)
++{
++  return (__a <= __b);
++}
+ 
+-#define __ST2_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+-			qmode, ptr_mode, funcsuffix, signedtype)	     \
+-__extension__ static __inline void					     \
+-__attribute__ ((__always_inline__))					     \
+-vst2_lane_ ## funcsuffix (ptrtype *__ptr,				     \
+-			  intype __b, const int __c)			     \
+-{									     \
+-  __builtin_aarch64_simd_oi __o;					     \
+-  largetype __temp;							     \
+-  __temp.val[0]								     \
+-    = vcombine_##funcsuffix (__b.val[0],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[1]								     \
+-    = vcombine_##funcsuffix (__b.val[1],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
+-					     (signedtype) __temp.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
+-					     (signedtype) __temp.val[1], 1); \
+-  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
+-				     __ptr, __o, __c);			     \
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u16 (uint16x4_t __a, uint16x4_t __b)
++{
++  return (__a <= __b);
+ }
+ 
+-__ST2_LANE_FUNC (float16x4x2_t, float16x8x2_t, float16_t, v4hf, v8hf, hf, f16,
+-		 float16x8_t)
+-__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32,
+-		 float32x4_t)
+-__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, df, v2df, df, f64,
+-		 float64x2_t)
+-__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16,
+-		 int16x8_t)
+-__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16,
+-		 int16x8_t)
+-__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32,
+-		 int32x4_t)
+-__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, di, v2di, di, u64,
+-		 int64x2_t)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u32 (uint32x2_t __a, uint32x2_t __b)
++{
++  return (__a <= __b);
++}
+ 
+-#undef __ST2_LANE_FUNC
+-#define __ST2_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
+-__extension__ static __inline void					    \
+-__attribute__ ((__always_inline__))					    \
+-vst2q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
+-			   intype __b, const int __c)			    \
+-{									    \
+-  union { intype __i;							    \
+-	  __builtin_aarch64_simd_oi __o; } __temp = { __b };		    \
+-  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
+-				    __ptr, __temp.__o, __c);		    \
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u64 (uint64x1_t __a, uint64x1_t __b)
++{
++  return (__a <= __b);
+ }
+ 
+-__ST2_LANE_FUNC (float16x8x2_t, float16_t, v8hf, hf, f16)
+-__ST2_LANE_FUNC (float32x4x2_t, float32_t, v4sf, sf, f32)
+-__ST2_LANE_FUNC (float64x2x2_t, float64_t, v2df, df, f64)
+-__ST2_LANE_FUNC (poly8x16x2_t, poly8_t, v16qi, qi, p8)
+-__ST2_LANE_FUNC (poly16x8x2_t, poly16_t, v8hi, hi, p16)
+-__ST2_LANE_FUNC (int8x16x2_t, int8_t, v16qi, qi, s8)
+-__ST2_LANE_FUNC (int16x8x2_t, int16_t, v8hi, hi, s16)
+-__ST2_LANE_FUNC (int32x4x2_t, int32_t, v4si, si, s32)
+-__ST2_LANE_FUNC (int64x2x2_t, int64_t, v2di, di, s64)
+-__ST2_LANE_FUNC (uint8x16x2_t, uint8_t, v16qi, qi, u8)
+-__ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16)
+-__ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32)
+-__ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return (uint32x4_t) (__a <= __b);
++}
+ 
+-#define __ST3_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+-			qmode, ptr_mode, funcsuffix, signedtype)	     \
+-__extension__ static __inline void					     \
+-__attribute__ ((__always_inline__))					     \
+-vst3_lane_ ## funcsuffix (ptrtype *__ptr,				     \
+-			  intype __b, const int __c)			     \
+-{									     \
+-  __builtin_aarch64_simd_ci __o;					     \
+-  largetype __temp;							     \
+-  __temp.val[0]								     \
+-    = vcombine_##funcsuffix (__b.val[0],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[1]								     \
+-    = vcombine_##funcsuffix (__b.val[1],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[2]								     \
+-    = vcombine_##funcsuffix (__b.val[2],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+-					     (signedtype) __temp.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+-					     (signedtype) __temp.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+-					     (signedtype) __temp.val[2], 2); \
+-  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
+-				     __ptr, __o, __c);			     \
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return (uint64x2_t) (__a <= __b);
+ }
+ 
+-__ST3_LANE_FUNC (float16x4x3_t, float16x8x3_t, float16_t, v4hf, v8hf, hf, f16,
+-		 float16x8_t)
+-__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32,
+-		 float32x4_t)
+-__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, df, v2df, df, f64,
+-		 float64x2_t)
+-__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16,
+-		 int16x8_t)
+-__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16,
+-		 int16x8_t)
+-__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32,
+-		 int32x4_t)
+-__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, di, v2di, di, u64,
+-		 int64x2_t)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s8 (int8x16_t __a, int8x16_t __b)
++{
++  return (uint8x16_t) (__a <= __b);
++}
+ 
+-#undef __ST3_LANE_FUNC
+-#define __ST3_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
+-__extension__ static __inline void					    \
+-__attribute__ ((__always_inline__))					    \
+-vst3q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
+-			   intype __b, const int __c)			    \
+-{									    \
+-  union { intype __i;							    \
+-	  __builtin_aarch64_simd_ci __o; } __temp = { __b };		    \
+-  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
+-				    __ptr, __temp.__o, __c);		    \
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s16 (int16x8_t __a, int16x8_t __b)
++{
++  return (uint16x8_t) (__a <= __b);
+ }
+ 
+-__ST3_LANE_FUNC (float16x8x3_t, float16_t, v8hf, hf, f16)
+-__ST3_LANE_FUNC (float32x4x3_t, float32_t, v4sf, sf, f32)
+-__ST3_LANE_FUNC (float64x2x3_t, float64_t, v2df, df, f64)
+-__ST3_LANE_FUNC (poly8x16x3_t, poly8_t, v16qi, qi, p8)
+-__ST3_LANE_FUNC (poly16x8x3_t, poly16_t, v8hi, hi, p16)
+-__ST3_LANE_FUNC (int8x16x3_t, int8_t, v16qi, qi, s8)
+-__ST3_LANE_FUNC (int16x8x3_t, int16_t, v8hi, hi, s16)
+-__ST3_LANE_FUNC (int32x4x3_t, int32_t, v4si, si, s32)
+-__ST3_LANE_FUNC (int64x2x3_t, int64_t, v2di, di, s64)
+-__ST3_LANE_FUNC (uint8x16x3_t, uint8_t, v16qi, qi, u8)
+-__ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16)
+-__ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32)
+-__ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s32 (int32x4_t __a, int32x4_t __b)
++{
++  return (uint32x4_t) (__a <= __b);
++}
+ 
+-#define __ST4_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+-			qmode, ptr_mode, funcsuffix, signedtype)	     \
+-__extension__ static __inline void					     \
+-__attribute__ ((__always_inline__))					     \
+-vst4_lane_ ## funcsuffix (ptrtype *__ptr,				     \
+-			  intype __b, const int __c)			     \
+-{									     \
+-  __builtin_aarch64_simd_xi __o;					     \
+-  largetype __temp;							     \
+-  __temp.val[0]								     \
+-    = vcombine_##funcsuffix (__b.val[0],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[1]								     \
+-    = vcombine_##funcsuffix (__b.val[1],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[2]								     \
+-    = vcombine_##funcsuffix (__b.val[2],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[3]								     \
+-    = vcombine_##funcsuffix (__b.val[3],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[2], 2); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[3], 3); \
+-  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
+-				     __ptr, __o, __c);			     \
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s64 (int64x2_t __a, int64x2_t __b)
++{
++  return (uint64x2_t) (__a <= __b);
+ }
+ 
+-__ST4_LANE_FUNC (float16x4x4_t, float16x8x4_t, float16_t, v4hf, v8hf, hf, f16,
+-		 float16x8_t)
+-__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32,
+-		 float32x4_t)
+-__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, df, v2df, df, f64,
+-		 float64x2_t)
+-__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16,
+-		 int16x8_t)
+-__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16,
+-		 int16x8_t)
+-__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32,
+-		 int32x4_t)
+-__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, di, v2di, di, u64,
+-		 int64x2_t)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
++{
++  return (__a <= __b);
++}
+ 
+-#undef __ST4_LANE_FUNC
+-#define __ST4_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
+-__extension__ static __inline void					    \
+-__attribute__ ((__always_inline__))					    \
+-vst4q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
+-			   intype __b, const int __c)			    \
+-{									    \
+-  union { intype __i;							    \
+-	  __builtin_aarch64_simd_xi __o; } __temp = { __b };		    \
+-  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
+-				    __ptr, __temp.__o, __c);		    \
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
++{
++  return (__a <= __b);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
++{
++  return (__a <= __b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u64 (uint64x2_t __a, uint64x2_t __b)
++{
++  return (__a <= __b);
+ }
+ 
+-__ST4_LANE_FUNC (float16x8x4_t, float16_t, v8hf, hf, f16)
+-__ST4_LANE_FUNC (float32x4x4_t, float32_t, v4sf, sf, f32)
+-__ST4_LANE_FUNC (float64x2x4_t, float64_t, v2df, df, f64)
+-__ST4_LANE_FUNC (poly8x16x4_t, poly8_t, v16qi, qi, p8)
+-__ST4_LANE_FUNC (poly16x8x4_t, poly16_t, v8hi, hi, p16)
+-__ST4_LANE_FUNC (int8x16x4_t, int8_t, v16qi, qi, s8)
+-__ST4_LANE_FUNC (int16x8x4_t, int16_t, v8hi, hi, s16)
+-__ST4_LANE_FUNC (int32x4x4_t, int32_t, v4si, si, s32)
+-__ST4_LANE_FUNC (int64x2x4_t, int64_t, v2di, di, s64)
+-__ST4_LANE_FUNC (uint8x16x4_t, uint8_t, v16qi, qi, u8)
+-__ST4_LANE_FUNC (uint16x8x4_t, uint16_t, v8hi, hi, u16)
+-__ST4_LANE_FUNC (uint32x4x4_t, uint32_t, v4si, si, u32)
+-__ST4_LANE_FUNC (uint64x2x4_t, uint64_t, v2di, di, u64)
++/* vcle - scalar.  */
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vaddlv_s32 (int32x2_t a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcles_f32 (float32_t __a, float32_t __b)
+ {
+-  int64_t result;
+-  __asm__ ("saddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
+-  return result;
++  return __a <= __b ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vaddlv_u32 (uint32x2_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcled_s64 (int64_t __a, int64_t __b)
+ {
+-  uint64_t result;
+-  __asm__ ("uaddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
+-  return result;
++  return __a <= __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcled_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv4hi (__a, __b, __c);
++  return __a <= __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcled_f64 (float64_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv2si (__a, __b, __c);
++  return __a <= __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++/* vclez - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv8hi (__a, __b, __c);
++  return (uint32x2_t) (__a <= 0.0f);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv4si (__a, __b, __c);
++  return (uint64x1_t) (__a <= (float64x1_t) {0.0});
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s8 (int8x8_t __a)
+ {
+-  return  __builtin_aarch64_sqrdmulh_laneqv4hi (__a, __b, __c);
++  return (uint8x8_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s16 (int16x4_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqv2si (__a, __b, __c);
++  return (uint16x4_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s32 (int32x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqv8hi (__a, __b, __c);
++  return (uint32x2_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s64 (int64x1_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqv4si (__a, __b, __c);
++  return (uint64x1_t) (__a <= __AARCH64_INT64_C (0));
+ }
+ 
+-/* Table intrinsics.  */
+-
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl1_p8 (poly8x16_t a, uint8x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f32 (float32x4_t __a)
+ {
+-  poly8x8_t result;
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a <= 0.0f);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl1_s8 (int8x16_t a, uint8x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f64 (float64x2_t __a)
+ {
+-  int8x8_t result;
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a <= 0.0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl1_u8 (uint8x16_t a, uint8x8_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s8 (int8x16_t __a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl1q_p8 (poly8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s16 (int16x8_t __a)
+ {
+-  poly8x16_t result;
+-  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl1q_s8 (int8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s32 (int32x4_t __a)
+ {
+-  int8x16_t result;
+-  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl1q_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s64 (int64x2_t __a)
+ {
+-  uint8x16_t result;
+-  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a <= __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx1_s8 (int8x8_t r, int8x16_t tab, uint8x8_t idx)
++/* vclez - scalar.  */
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezs_f32 (float32_t __a)
+ {
+-  int8x8_t result = r;
+-  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return __a <= 0.0f ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx1_u8 (uint8x8_t r, uint8x16_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezd_s64 (int64_t __a)
+ {
+-  uint8x8_t result = r;
+-  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return __a <= 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx1_p8 (poly8x8_t r, poly8x16_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezd_f64 (float64_t __a)
+ {
+-  poly8x8_t result = r;
+-  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return __a <= 0.0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx1q_s8 (int8x16_t r, int8x16_t tab, uint8x16_t idx)
++/* vclt - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  int8x16_t result = r;
+-  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx1q_u8 (uint8x16_t r, uint8x16_t tab, uint8x16_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  uint8x16_t result = r;
+-  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx1q_p8 (poly8x16_t r, poly8x16_t tab, uint8x16_t idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  poly8x16_t result = r;
+-  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a < __b);
+ }
+ 
+-/* V7 legacy table intrinsics.  */
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a < __b);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl1_s8 (int8x8_t tab, int8x8_t idx)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  int8x8_t result;
+-  int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl1_u8 (uint8x8_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl1_p8 (poly8x8_t tab, uint8x8_t idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl2_s8 (int8x8x2_t tab, int8x8_t idx)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  int8x8_t result;
+-  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl2_u8 (uint8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl2_p8 (poly8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl3_s8 (int8x8x3_t tab, int8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  int8x8_t result;
+-  int8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = __builtin_aarch64_tbl3v8qi (__o, idx);
+-  return result;
++  return (uint32x4_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl3_u8 (uint8x8x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint64x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl3_p8 (poly8x8x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint8x16_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl4_s8 (int8x8x4_t tab, int8x8_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int8x8_t result;
+-  int8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_s8 (tab.val[2], tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = __builtin_aarch64_tbl3v8qi (__o, idx);
+-  return result;
++  return (uint16x8_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl4_u8 (uint8x8x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_u8 (tab.val[2], tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint32x4_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl4_p8 (poly8x8x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_p8 (tab.val[2], tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint64x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx2_s8 (int8x8_t r, int8x8x2_t tab, int8x8_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  int8x8_t result = r;
+-  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
+-           : "+w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx2_u8 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  uint8x8_t result = r;
+-  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
+-           : "+w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx2_p8 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  poly8x8_t result = r;
+-  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
+-           : "+w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-/* End of temporary inline asm.  */
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u64 (uint64x2_t __a, uint64x2_t __b)
++{
++  return (__a < __b);
++}
+ 
+-/* Start of optimal implementations in approved order.  */
++/* vclt - scalar.  */
+ 
+-/* vabs  */
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclts_f32 (float32_t __a, float32_t __b)
++{
++  return __a < __b ? -1 : 0;
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vabs_f32 (float32x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_absv2sf (__a);
++  return __a < __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vabs_f64 (float64x1_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return (float64x1_t) {__builtin_fabs (__a[0])};
++  return __a < __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vabs_s8 (int8x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltd_f64 (float64_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_absv8qi (__a);
++  return __a < __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vabs_s16 (int16x4_t __a)
++/* vcltz - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_absv4hi (__a);
++  return (uint32x2_t) (__a < 0.0f);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vabs_s32 (int32x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_absv2si (__a);
++  return (uint64x1_t) (__a < (float64x1_t) {0.0});
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vabs_s64 (int64x1_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s8 (int8x8_t __a)
+ {
+-  return (int64x1_t) {__builtin_aarch64_absdi (__a[0])};
++  return (uint8x8_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vabsq_f32 (float32x4_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s16 (int16x4_t __a)
+ {
+-  return __builtin_aarch64_absv4sf (__a);
++  return (uint16x4_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vabsq_f64 (float64x2_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s32 (int32x2_t __a)
+ {
+-  return __builtin_aarch64_absv2df (__a);
++  return (uint32x2_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vabsq_s8 (int8x16_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s64 (int64x1_t __a)
+ {
+-  return __builtin_aarch64_absv16qi (__a);
++  return (uint64x1_t) (__a < __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vabsq_s16 (int16x8_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_absv8hi (__a);
++  return (uint32x4_t) (__a < 0.0f);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vabsq_s32 (int32x4_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_absv4si (__a);
++  return (uint64x2_t) (__a < 0.0);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vabsq_s64 (int64x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_absv2di (__a);
++  return (uint8x16_t) (__a < 0);
+ }
+ 
+-/* vadd */
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s16 (int16x8_t __a)
++{
++  return (uint16x8_t) (__a < 0);
++}
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vaddd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s32 (int32x4_t __a)
+ {
+-  return __a + __b;
++  return (uint32x4_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vaddd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s64 (int64x2_t __a)
+ {
+-  return __a + __b;
++  return (uint64x2_t) (__a < __AARCH64_INT64_C (0));
+ }
+ 
+-/* vaddv */
++/* vcltz - scalar.  */
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vaddv_s8 (int8x8_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzs_f32 (float32_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v8qi (__a);
++  return __a < 0.0f ? -1 : 0;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vaddv_s16 (int16x4_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzd_s64 (int64_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v4hi (__a);
++  return __a < 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vaddv_s32 (int32x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzd_f64 (float64_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2si (__a);
++  return __a < 0.0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vaddv_u8 (uint8x8_t __a)
++/* vcls.  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcls_s8 (int8x8_t __a)
+ {
+-  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v8qi ((int8x8_t) __a);
++  return __builtin_aarch64_clrsbv8qi (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vaddv_u16 (uint16x4_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcls_s16 (int16x4_t __a)
+ {
+-  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v4hi ((int16x4_t) __a);
++  return __builtin_aarch64_clrsbv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vaddv_u32 (uint32x2_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcls_s32 (int32x2_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_reduc_plus_scal_v2si ((int32x2_t) __a);
++  return __builtin_aarch64_clrsbv2si (__a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vaddvq_s8 (int8x16_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclsq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v16qi (__a);
++  return __builtin_aarch64_clrsbv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vaddvq_s16 (int16x8_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclsq_s16 (int16x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v8hi (__a);
++  return __builtin_aarch64_clrsbv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vaddvq_s32 (int32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclsq_s32 (int32x4_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v4si (__a);
++  return __builtin_aarch64_clrsbv4si (__a);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vaddvq_s64 (int64x2_t __a)
++/* vclz.  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_s8 (int8x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2di (__a);
++  return __builtin_aarch64_clzv8qi (__a);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vaddvq_u8 (uint8x16_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_s16 (int16x4_t __a)
+ {
+-  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v16qi ((int8x16_t) __a);
++  return __builtin_aarch64_clzv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vaddvq_u16 (uint16x8_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_s32 (int32x2_t __a)
+ {
+-  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v8hi ((int16x8_t) __a);
++  return __builtin_aarch64_clzv2si (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vaddvq_u32 (uint32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_u8 (uint8x8_t __a)
+ {
+-  return (uint32_t) __builtin_aarch64_reduc_plus_scal_v4si ((int32x4_t) __a);
++  return (uint8x8_t)__builtin_aarch64_clzv8qi ((int8x8_t)__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vaddvq_u64 (uint64x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_u16 (uint16x4_t __a)
+ {
+-  return (uint64_t) __builtin_aarch64_reduc_plus_scal_v2di ((int64x2_t) __a);
++  return (uint16x4_t)__builtin_aarch64_clzv4hi ((int16x4_t)__a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vaddv_f32 (float32x2_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_u32 (uint32x2_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2sf (__a);
++  return (uint32x2_t)__builtin_aarch64_clzv2si ((int32x2_t)__a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vaddvq_f32 (float32x4_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v4sf (__a);
++  return __builtin_aarch64_clzv16qi (__a);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vaddvq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_s16 (int16x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
++  return __builtin_aarch64_clzv8hi (__a);
+ }
+ 
+-/* vbsl  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_s32 (int32x4_t __a)
++{
++  return __builtin_aarch64_clzv4si (__a);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_u8 (uint8x16_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv2sf_suss (__a, __b, __c);
++  return (uint8x16_t)__builtin_aarch64_clzv16qi ((int8x16_t)__a);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vbsl_f64 (uint64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_u16 (uint16x8_t __a)
+ {
+-  return (float64x1_t)
+-    { __builtin_aarch64_simd_bsldf_suss (__a[0], __b[0], __c[0]) };
++  return (uint16x8_t)__builtin_aarch64_clzv8hi ((int16x8_t)__a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_u32 (uint32x4_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv8qi_pupp (__a, __b, __c);
++  return (uint32x4_t)__builtin_aarch64_clzv4si ((int32x4_t)__a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
++/* vcnt.  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcnt_p8 (poly8x8_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv4hi_pupp (__a, __b, __c);
++  return (poly8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcnt_s8 (int8x8_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv8qi_suss (__a, __b, __c);
++  return __builtin_aarch64_popcountv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcnt_u8 (uint8x8_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv4hi_suss (__a, __b, __c);
++  return (uint8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcntq_p8 (poly8x16_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv2si_suss (__a, __b, __c);
++  return (poly8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcntq_s8 (int8x16_t __a)
+ {
+-  return (int64x1_t)
+-      {__builtin_aarch64_simd_bsldi_suss (__a[0], __b[0], __c[0])};
++  return __builtin_aarch64_popcountv16qi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcntq_u8 (uint8x16_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv8qi_uuuu (__a, __b, __c);
++  return (uint8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
++/* vcopy_lane.  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_f32 (float32x2_t __a, const int __lane1,
++		float32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4hi_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_f64 (float64x1_t __a, const int __lane1,
++		float64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2si_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_p8 (poly8x8_t __a, const int __lane1,
++	       poly8x8_t __b, const int __lane2)
+ {
+-  return (uint64x1_t)
+-      {__builtin_aarch64_simd_bsldi_uuuu (__a[0], __b[0], __c[0])};
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_p16 (poly16x4_t __a, const int __lane1,
++		poly16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4sf_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vbslq_f64 (uint64x2_t __a, float64x2_t __b, float64x2_t __c)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_p64 (poly64x1_t __a, const int __lane1,
++		poly64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2df_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s8 (int8x8_t __a, const int __lane1,
++	       int8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv16qi_pupp (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s16 (int16x4_t __a, const int __lane1,
++		int16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv8hi_pupp (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s32 (int32x2_t __a, const int __lane1,
++		int32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv16qi_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s64 (int64x1_t __a, const int __lane1,
++		int64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv8hi_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u8 (uint8x8_t __a, const int __lane1,
++	       uint8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4si_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u16 (uint16x4_t __a, const int __lane1,
++		uint16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2di_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u32 (uint32x2_t __a, const int __lane1,
++		uint32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv16qi_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u64 (uint64x1_t __a, const int __lane1,
++		uint64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv8hi_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
++/* vcopy_laneq.  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_f32 (float32x2_t __a, const int __lane1,
++		 float32x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4si_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_f64 (float64x1_t __a, const int __lane1,
++		 float64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-/* ARMv8.1 instrinsics.  */
+-#pragma GCC push_options
+-#pragma GCC target ("arch=armv8.1-a")
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_p8 (poly8x8_t __a, const int __lane1,
++		poly8x16_t __b, const int __lane2)
++{
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
++}
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_p16 (poly16x4_t __a, const int __lane1,
++		 poly16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv4hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_p64 (poly64x1_t __a, const int __lane1,
++		 poly64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv2si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s8 (int8x8_t __a, const int __lane1,
++		int8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv8hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s16 (int16x4_t __a, const int __lane1,
++		 int16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv4si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s32 (int32x2_t __a, const int __lane1,
++		 int32x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv4hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s64 (int64x1_t __a, const int __lane1,
++		 int64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv2si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u8 (uint8x8_t __a, const int __lane1,
++		uint8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv8hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u16 (uint16x4_t __a, const int __lane1,
++		 uint16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv4si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlah_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u32 (uint32x2_t __a, const int __lane1,
++		 uint32x4_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlah_laneqv4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlah_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u64 (uint64x1_t __a, const int __lane1,
++		 uint64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqv2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlahq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++/* vcopyq_lane.  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_f32 (float32x4_t __a, const int __lane1,
++		 float32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqv8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlahq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_f64 (float64x2_t __a, const int __lane1,
++		 float64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqv4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlsh_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_p8 (poly8x16_t __a, const int __lane1,
++		poly8x8_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlsh_laneqv4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlsh_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_p16 (poly16x8_t __a, const int __lane1,
++		 poly16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqv2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlshq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_p64 (poly64x2_t __a, const int __lane1,
++		 poly64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqv8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlshq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s8 (int8x16_t __a, const int __lane1,
++		int8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqv4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s16 (int16x8_t __a, const int __lane1,
++		 int16x4_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlah_lanev4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s32 (int32x4_t __a, const int __lane1,
++		 int32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanev2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s64 (int64x2_t __a, const int __lane1,
++		 int64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanev8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u8 (uint8x16_t __a, const int __lane1,
++		uint8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanev4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlahh_s16 (int16_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u16 (uint16x8_t __a, const int __lane1,
++		 uint16x4_t __b, const int __lane2)
+ {
+-  return (int16_t) __builtin_aarch64_sqrdmlahhi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlahh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u32 (uint32x4_t __a, const int __lane1,
++		 uint32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanehi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlahh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u64 (uint64x2_t __a, const int __lane1,
++		 uint64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqhi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlahs_s32 (int32_t __a, int32_t __b, int32_t __c)
++/* vcopyq_laneq.  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_f32 (float32x4_t __a, const int __lane1,
++		  float32x4_t __b, const int __lane2)
+ {
+-  return (int32_t) __builtin_aarch64_sqrdmlahsi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlahs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_f64 (float64x2_t __a, const int __lane1,
++		  float64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanesi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlahs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_p8 (poly8x16_t __a, const int __lane1,
++		 poly8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqsi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_p16 (poly16x8_t __a, const int __lane1,
++		  poly16x8_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlsh_lanev4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_p64 (poly64x2_t __a, const int __lane1,
++		  poly64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanev2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s8 (int8x16_t __a, const int __lane1,
++		 int8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanev8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s16 (int16x8_t __a, const int __lane1,
++		  int16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanev4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlshh_s16 (int16_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s32 (int32x4_t __a, const int __lane1,
++		  int32x4_t __b, const int __lane2)
+ {
+-  return (int16_t) __builtin_aarch64_sqrdmlshhi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlshh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s64 (int64x2_t __a, const int __lane1,
++		  int64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanehi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlshh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u8 (uint8x16_t __a, const int __lane1,
++		 uint8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqhi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlshs_s32 (int32_t __a, int32_t __b, int32_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u16 (uint16x8_t __a, const int __lane1,
++		  uint16x8_t __b, const int __lane2)
+ {
+-  return (int32_t) __builtin_aarch64_sqrdmlshsi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlshs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u32 (uint32x4_t __a, const int __lane1,
++		  uint32x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanesi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u64 (uint64x2_t __a, const int __lane1,
++		  uint64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqsi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+-#pragma GCC pop_options
+ 
+-#pragma GCC push_options
+-#pragma GCC target ("+nothing+crypto")
+-/* vaes  */
++/* vcvt (double -> float).  */
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaeseq_u8 (uint8x16_t data, uint8x16_t key)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_crypto_aesev16qi_uuu (data, key);
++  return __builtin_aarch64_float_truncate_lo_v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesdq_u8 (uint8x16_t data, uint8x16_t key)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f16_f32 (float16x4_t __a, float32x4_t __b)
+ {
+-  return __builtin_aarch64_crypto_aesdv16qi_uuu (data, key);
++  return __builtin_aarch64_float_truncate_hi_v8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesmcq_u8 (uint8x16_t data)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_crypto_aesmcv16qi_uu (data);
++  return __builtin_aarch64_float_truncate_lo_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesimcq_u8 (uint8x16_t data)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __b)
+ {
+-  return __builtin_aarch64_crypto_aesimcv16qi_uu (data);
++  return __builtin_aarch64_float_truncate_hi_v4sf (__a, __b);
+ }
+-#pragma GCC pop_options
+ 
+-/* vcage  */
++/* vcvt (float -> double).  */
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcage_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_f16 (float16x4_t __a)
+ {
+-  return vabs_f64 (__a) >= vabs_f64 (__b);
++  return __builtin_aarch64_float_extend_lo_v4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcages_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f64_f32 (float32x2_t __a)
+ {
+-  return __builtin_fabsf (__a) >= __builtin_fabsf (__b) ? -1 : 0;
++
++  return __builtin_aarch64_float_extend_lo_v2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcage_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f32_f16 (float16x8_t __a)
+ {
+-  return vabs_f32 (__a) >= vabs_f32 (__b);
++  return __builtin_aarch64_vec_unpacks_hi_v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcageq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f64_f32 (float32x4_t __a)
+ {
+-  return vabsq_f32 (__a) >= vabsq_f32 (__b);
++  return __builtin_aarch64_vec_unpacks_hi_v4sf (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcaged_f64 (float64_t __a, float64_t __b)
++/* vcvt (<u>fixed-point -> float).  */
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_f64_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) >= __builtin_fabs (__b) ? -1 : 0;
++  return __builtin_aarch64_scvtfdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcageq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_f64_u64 (uint64_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) >= vabsq_f64 (__b);
++  return __builtin_aarch64_ucvtfdi_sus (__a, __b);
+ }
+ 
+-/* vcagt  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcagts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_f32_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_fabsf (__a) > __builtin_fabsf (__b) ? -1 : 0;
++  return __builtin_aarch64_scvtfsi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcagt_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_f32_u32 (uint32_t __a, const int __b)
+ {
+-  return vabs_f32 (__a) > vabs_f32 (__b);
++  return __builtin_aarch64_ucvtfsi_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcagt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f32_s32 (int32x2_t __a, const int __b)
+ {
+-  return vabs_f64 (__a) > vabs_f64 (__b);
++  return __builtin_aarch64_scvtfv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcagtq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f32_u32 (uint32x2_t __a, const int __b)
+ {
+-  return vabsq_f32 (__a) > vabsq_f32 (__b);
++  return __builtin_aarch64_ucvtfv2si_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcagtd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f64_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) > __builtin_fabs (__b) ? -1 : 0;
++  return (float64x1_t)
++    { __builtin_aarch64_scvtfdi (vget_lane_s64 (__a, 0), __b) };
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcagtq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f64_u64 (uint64x1_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) > vabsq_f64 (__b);
++  return (float64x1_t)
++    { __builtin_aarch64_ucvtfdi_sus (vget_lane_u64 (__a, 0), __b) };
+ }
+ 
+-/* vcale  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcale_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f32_s32 (int32x4_t __a, const int __b)
+ {
+-  return vabs_f32 (__a) <= vabs_f32 (__b);
++  return __builtin_aarch64_scvtfv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcale_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f32_u32 (uint32x4_t __a, const int __b)
+ {
+-  return vabs_f64 (__a) <= vabs_f64 (__b);
++  return __builtin_aarch64_ucvtfv4si_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcaled_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f64_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
++  return __builtin_aarch64_scvtfv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcales_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f64_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
++  return __builtin_aarch64_ucvtfv2di_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcaleq_f32 (float32x4_t __a, float32x4_t __b)
++/* vcvt (float -> <u>fixed-point).  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_s64_f64 (float64_t __a, const int __b)
+ {
+-  return vabsq_f32 (__a) <= vabsq_f32 (__b);
++  return __builtin_aarch64_fcvtzsdf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcaleq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_u64_f64 (float64_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) <= vabsq_f64 (__b);
++  return __builtin_aarch64_fcvtzudf_uss (__a, __b);
+ }
+ 
+-/* vcalt  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcalt_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_s32_f32 (float32_t __a, const int __b)
+ {
+-  return vabs_f32 (__a) < vabs_f32 (__b);
++  return __builtin_aarch64_fcvtzssf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcalt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_u32_f32 (float32_t __a, const int __b)
+ {
+-  return vabs_f64 (__a) < vabs_f64 (__b);
++  return __builtin_aarch64_fcvtzusf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcaltd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s32_f32 (float32x2_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
++  return __builtin_aarch64_fcvtzsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcaltq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u32_f32 (float32x2_t __a, const int __b)
+ {
+-  return vabsq_f32 (__a) < vabsq_f32 (__b);
++  return __builtin_aarch64_fcvtzuv2sf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcaltq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s64_f64 (float64x1_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) < vabsq_f64 (__b);
++  return (int64x1_t)
++    { __builtin_aarch64_fcvtzsdf (vget_lane_f64 (__a, 0), __b) };
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcalts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u64_f64 (float64x1_t __a, const int __b)
+ {
+-  return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
++  return (uint64x1_t)
++    { __builtin_aarch64_fcvtzudf_uss (vget_lane_f64 (__a, 0), __b) };
+ }
+ 
+-/* vceq - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceq_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s32_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a == __b);
++  return __builtin_aarch64_fcvtzsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u32_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a == __b);
++  return __builtin_aarch64_fcvtzuv4sf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceq_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s64_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a == __b);
++  return __builtin_aarch64_fcvtzsv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceq_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u64_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a == __b);
++  return __builtin_aarch64_fcvtzuv2df_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceq_s16 (int16x4_t __a, int16x4_t __b)
++/* vcvt  (<u>int -> float)  */
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_f64_s64 (int64_t __a)
+ {
+-  return (uint16x4_t) (__a == __b);
++  return (float64_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceq_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_f64_u64 (uint64_t __a)
+ {
+-  return (uint32x2_t) (__a == __b);
++  return (float64_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_f32_s32 (int32_t __a)
+ {
+-  return (uint64x1_t) (__a == __b);
++  return (float32_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceq_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_f32_u32 (uint32_t __a)
+ {
+-  return (__a == __b);
++  return (float32_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceq_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_s32 (int32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_floatv2siv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceq_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_u32 (uint32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_floatunsv2siv2sf ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f64_s64 (int64x1_t __a)
+ {
+-  return (__a == __b);
++  return (float64x1_t) { vget_lane_s64 (__a, 0) };
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f64_u64 (uint64x1_t __a)
+ {
+-  return (uint32x4_t) (__a == __b);
++  return (float64x1_t) { vget_lane_u64 (__a, 0) };
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f32_s32 (int32x4_t __a)
+ {
+-  return (uint64x2_t) (__a == __b);
++  return __builtin_aarch64_floatv4siv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqq_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f32_u32 (uint32x4_t __a)
+ {
+-  return (uint8x16_t) (__a == __b);
++  return __builtin_aarch64_floatunsv4siv4sf ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f64_s64 (int64x2_t __a)
+ {
+-  return (uint8x16_t) (__a == __b);
++  return __builtin_aarch64_floatv2div2df (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f64_u64 (uint64x2_t __a)
+ {
+-  return (uint16x8_t) (__a == __b);
++  return __builtin_aarch64_floatunsv2div2df ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqq_s32 (int32x4_t __a, int32x4_t __b)
++/* vcvt (float -> <u>int)  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_s64_f64 (float64_t __a)
+ {
+-  return (uint32x4_t) (__a == __b);
++  return (int64_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_u64_f64 (float64_t __a)
+ {
+-  return (uint64x2_t) (__a == __b);
++  return (uint64_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_s32_f32 (float32_t __a)
+ {
+-  return (__a == __b);
++  return (int32_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_u32_f32 (float32_t __a)
+ {
+-  return (__a == __b);
++  return (uint32_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s32_f32 (float32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_lbtruncv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u32_f32 (float32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_lbtruncuv2sfv2si_us (__a);
+ }
+ 
+-/* vceq - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vceqs_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s32_f32 (float32x4_t __a)
+ {
+-  return __a == __b ? -1 : 0;
++  return __builtin_aarch64_lbtruncv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u32_f32 (float32x4_t __a)
+ {
+-  return __a == __b ? -1ll : 0ll;
++  return __builtin_aarch64_lbtruncuv4sfv4si_us (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s64_f64 (float64x1_t __a)
+ {
+-  return __a == __b ? -1ll : 0ll;
++  return (int64x1_t) {vcvtd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u64_f64 (float64x1_t __a)
+ {
+-  return __a == __b ? -1ll : 0ll;
++  return (uint64x1_t) {vcvtd_u64_f64 (__a[0])};
+ }
+ 
+-/* vceqz - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceqz_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s64_f64 (float64x2_t __a)
+ {
+-  return (uint32x2_t) (__a == 0.0f);
++  return __builtin_aarch64_lbtruncv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceqz_f64 (float64x1_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u64_f64 (float64x2_t __a)
+ {
+-  return (uint64x1_t) (__a == (float64x1_t) {0.0});
++  return __builtin_aarch64_lbtruncuv2dfv2di_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceqz_p8 (poly8x8_t __a)
++/* vcvta  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtad_s64_f64 (float64_t __a)
+ {
+-  return (uint8x8_t) (__a == 0);
++  return __builtin_aarch64_lrounddfdi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceqz_s8 (int8x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtad_u64_f64 (float64_t __a)
+ {
+-  return (uint8x8_t) (__a == 0);
++  return __builtin_aarch64_lroundudfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceqz_s16 (int16x4_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtas_s32_f32 (float32_t __a)
+ {
+-  return (uint16x4_t) (__a == 0);
++  return __builtin_aarch64_lroundsfsi (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceqz_s32 (int32x2_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtas_u32_f32 (float32_t __a)
+ {
+-  return (uint32x2_t) (__a == 0);
++  return __builtin_aarch64_lroundusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceqz_s64 (int64x1_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s32_f32 (float32x2_t __a)
+ {
+-  return (uint64x1_t) (__a == __AARCH64_INT64_C (0));
++  return __builtin_aarch64_lroundv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceqz_u8 (uint8x8_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u32_f32 (float32x2_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lrounduv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceqz_u16 (uint16x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lroundv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceqz_u32 (uint32x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lrounduv4sfv4si_us (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceqz_u64 (uint64x1_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s64_f64 (float64x1_t __a)
+ {
+-  return (__a == __AARCH64_UINT64_C (0));
++  return (int64x1_t) {vcvtad_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqzq_f32 (float32x4_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u64_f64 (float64x1_t __a)
+ {
+-  return (uint32x4_t) (__a == 0.0f);
++  return (uint64x1_t) {vcvtad_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqzq_f64 (float64x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s64_f64 (float64x2_t __a)
+ {
+-  return (uint64x2_t) (__a == 0.0f);
++  return __builtin_aarch64_lroundv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqzq_p8 (poly8x16_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u64_f64 (float64x2_t __a)
+ {
+-  return (uint8x16_t) (__a == 0);
++  return __builtin_aarch64_lrounduv2dfv2di_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqzq_s8 (int8x16_t __a)
++/* vcvtm  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmd_s64_f64 (float64_t __a)
+ {
+-  return (uint8x16_t) (__a == 0);
++  return __builtin_llfloor (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqzq_s16 (int16x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmd_u64_f64 (float64_t __a)
+ {
+-  return (uint16x8_t) (__a == 0);
++  return __builtin_aarch64_lfloorudfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqzq_s32 (int32x4_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtms_s32_f32 (float32_t __a)
+ {
+-  return (uint32x4_t) (__a == 0);
++  return __builtin_ifloorf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqzq_s64 (int64x2_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtms_u32_f32 (float32_t __a)
+ {
+-  return (uint64x2_t) (__a == __AARCH64_INT64_C (0));
++  return __builtin_aarch64_lfloorusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqzq_u8 (uint8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s32_f32 (float32x2_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lfloorv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqzq_u16 (uint16x8_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u32_f32 (float32x2_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lflooruv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqzq_u32 (uint32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lfloorv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqzq_u64 (uint64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a == __AARCH64_UINT64_C (0));
++  return __builtin_aarch64_lflooruv4sfv4si_us (__a);
+ }
+ 
+-/* vceqz - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vceqzs_f32 (float32_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s64_f64 (float64x1_t __a)
+ {
+-  return __a == 0.0f ? -1 : 0;
++  return (int64x1_t) {vcvtmd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqzd_s64 (int64_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u64_f64 (float64x1_t __a)
+ {
+-  return __a == 0 ? -1ll : 0ll;
++  return (uint64x1_t) {vcvtmd_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqzd_u64 (uint64_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s64_f64 (float64x2_t __a)
+ {
+-  return __a == 0 ? -1ll : 0ll;
++  return __builtin_aarch64_lfloorv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqzd_f64 (float64_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u64_f64 (float64x2_t __a)
+ {
+-  return __a == 0.0 ? -1ll : 0ll;
++  return __builtin_aarch64_lflooruv2dfv2di_us (__a);
+ }
+ 
+-/* vcge - vector.  */
++/* vcvtn  */
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcge_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnd_s64_f64 (float64_t __a)
+ {
+-  return (uint32x2_t) (__a >= __b);
++  return __builtin_aarch64_lfrintndfdi (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcge_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnd_u64_f64 (float64_t __a)
+ {
+-  return (uint64x1_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnudfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcge_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtns_s32_f32 (float32_t __a)
+ {
+-  return (uint8x8_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnsfsi (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcge_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtns_u32_f32 (float32_t __a)
+ {
+-  return (uint16x4_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcge_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s32_f32 (float32x2_t __a)
+ {
+-  return (uint32x2_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcge_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u32_f32 (float32x2_t __a)
+ {
+-  return (uint64x1_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnuv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcge_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lfrintnv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcge_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lfrintnuv4sfv4si_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcge_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s64_f64 (float64x1_t __a)
+ {
+-  return (__a >= __b);
++  return (int64x1_t) {vcvtnd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcge_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u64_f64 (float64x1_t __a)
+ {
+-  return (__a >= __b);
++  return (uint64x1_t) {vcvtnd_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgeq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s64_f64 (float64x2_t __a)
+ {
+-  return (uint32x4_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgeq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u64_f64 (float64x2_t __a)
+ {
+-  return (uint64x2_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnuv2dfv2di_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgeq_s8 (int8x16_t __a, int8x16_t __b)
++/* vcvtp  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpd_s64_f64 (float64_t __a)
+ {
+-  return (uint8x16_t) (__a >= __b);
++  return __builtin_llceil (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgeq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpd_u64_f64 (float64_t __a)
+ {
+-  return (uint16x8_t) (__a >= __b);
++  return __builtin_aarch64_lceiludfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgeq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtps_s32_f32 (float32_t __a)
+ {
+-  return (uint32x4_t) (__a >= __b);
++  return __builtin_iceilf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgeq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtps_u32_f32 (float32_t __a)
+ {
+-  return (uint64x2_t) (__a >= __b);
++  return __builtin_aarch64_lceilusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s32_f32 (float32x2_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceilv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u32_f32 (float32x2_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceiluv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceilv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceiluv4sfv4si_us (__a);
+ }
+ 
+-/* vcge - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcges_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s64_f64 (float64x1_t __a)
+ {
+-  return __a >= __b ? -1 : 0;
++  return (int64x1_t) {vcvtpd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcged_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u64_f64 (float64x1_t __a)
+ {
+-  return __a >= __b ? -1ll : 0ll;
++  return (uint64x1_t) {vcvtpd_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcged_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s64_f64 (float64x2_t __a)
+ {
+-  return __a >= __b ? -1ll : 0ll;
++  return __builtin_aarch64_lceilv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcged_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u64_f64 (float64x2_t __a)
+ {
+-  return __a >= __b ? -1ll : 0ll;
++  return __builtin_aarch64_lceiluv2dfv2di_us (__a);
+ }
+ 
+-/* vcgez - vector.  */
++/* vdup_n  */
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgez_f32 (float32x2_t __a)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f16 (float16_t __a)
+ {
+-  return (uint32x2_t) (__a >= 0.0f);
++  return (float16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgez_f64 (float64x1_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f32 (float32_t __a)
+ {
+-  return (uint64x1_t) (__a[0] >= (float64x1_t) {0.0});
++  return (float32x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgez_s8 (int8x8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f64 (float64_t __a)
+ {
+-  return (uint8x8_t) (__a >= 0);
++  return (float64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgez_s16 (int16x4_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_p8 (poly8_t __a)
+ {
+-  return (uint16x4_t) (__a >= 0);
++  return (poly8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgez_s32 (int32x2_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_p16 (poly16_t __a)
+ {
+-  return (uint32x2_t) (__a >= 0);
++  return (poly16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgez_s64 (int64x1_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_p64 (poly64_t __a)
+ {
+-  return (uint64x1_t) (__a >= __AARCH64_INT64_C (0));
++  return (poly64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgezq_f32 (float32x4_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s8 (int8_t __a)
+ {
+-  return (uint32x4_t) (__a >= 0.0f);
++  return (int8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgezq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s16 (int16_t __a)
+ {
+-  return (uint64x2_t) (__a >= 0.0);
++  return (int16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgezq_s8 (int8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s32 (int32_t __a)
+ {
+-  return (uint8x16_t) (__a >= 0);
++  return (int32x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgezq_s16 (int16x8_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s64 (int64_t __a)
+ {
+-  return (uint16x8_t) (__a >= 0);
++  return (int64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgezq_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u8 (uint8_t __a)
+ {
+-  return (uint32x4_t) (__a >= 0);
++  return (uint8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgezq_s64 (int64x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u16 (uint16_t __a)
+ {
+-  return (uint64x2_t) (__a >= __AARCH64_INT64_C (0));
++  return (uint16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-/* vcgez - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcgezs_f32 (float32_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u32 (uint32_t __a)
+ {
+-  return __a >= 0.0f ? -1 : 0;
++  return (uint32x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgezd_s64 (int64_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u64 (uint64_t __a)
+ {
+-  return __a >= 0 ? -1ll : 0ll;
++  return (uint64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgezd_f64 (float64_t __a)
++/* vdupq_n  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f16 (float16_t __a)
+ {
+-  return __a >= 0.0 ? -1ll : 0ll;
++  return (float16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-/* vcgt - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgt_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f32 (float32_t __a)
+ {
+-  return (uint32x2_t) (__a > __b);
++  return (float32x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f64 (float64_t __a)
+ {
+-  return (uint64x1_t) (__a > __b);
++  return (float64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgt_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_p8 (uint32_t __a)
+ {
+-  return (uint8x8_t) (__a > __b);
++  return (poly8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
++		       __a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgt_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_p16 (uint32_t __a)
+ {
+-  return (uint16x4_t) (__a > __b);
++  return (poly16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgt_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_p64 (uint64_t __a)
+ {
+-  return (uint32x2_t) (__a > __b);
++  return (poly64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgt_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s8 (int32_t __a)
+ {
+-  return (uint64x1_t) (__a > __b);
++  return (int8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
++		      __a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s16 (int32_t __a)
+ {
+-  return (__a > __b);
++  return (int16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s32 (int32_t __a)
+ {
+-  return (__a > __b);
++  return (int32x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s64 (int64_t __a)
+ {
+-  return (__a > __b);
++  return (int64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgt_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u8 (uint32_t __a)
+ {
+-  return (__a > __b);
++  return (uint8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
++		       __a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u16 (uint32_t __a)
+ {
+-  return (uint32x4_t) (__a > __b);
++  return (uint16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u32 (uint32_t __a)
+ {
+-  return (uint64x2_t) (__a > __b);
++  return (uint32x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgtq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u64 (uint64_t __a)
+ {
+-  return (uint8x16_t) (__a > __b);
++  return (uint64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgtq_s16 (int16x8_t __a, int16x8_t __b)
++/* vdup_lane  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f16 (float16x4_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a > __b);
++  return __aarch64_vdup_lane_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f32 (float32x2_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a > __b);
++  return __aarch64_vdup_lane_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f64 (float64x1_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a > __b);
++  return __aarch64_vdup_lane_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_p8 (poly8x8_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_p16 (poly16x4_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_p16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_p64 (poly64x1_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s8 (int8x8_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_s8 (__a, __b);
+ }
+ 
+-/* vcgt - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcgts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s16 (int16x4_t __a, const int __b)
+ {
+-  return __a > __b ? -1 : 0;
++  return __aarch64_vdup_lane_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s32 (int32x2_t __a, const int __b)
+ {
+-  return __a > __b ? -1ll : 0ll;
++  return __aarch64_vdup_lane_s32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s64 (int64x1_t __a, const int __b)
+ {
+-  return __a > __b ? -1ll : 0ll;
++  return __aarch64_vdup_lane_s64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __a > __b ? -1ll : 0ll;
++  return __aarch64_vdup_lane_u8 (__a, __b);
+ }
+ 
+-/* vcgtz - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgtz_f32 (float32x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u16 (uint16x4_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a > 0.0f);
++  return __aarch64_vdup_lane_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgtz_f64 (float64x1_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u32 (uint32x2_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a > (float64x1_t) {0.0});
++  return __aarch64_vdup_lane_u32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgtz_s8 (int8x8_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u64 (uint64x1_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a > 0);
++  return __aarch64_vdup_lane_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgtz_s16 (int16x4_t __a)
++/* vdup_laneq  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_f16 (float16x8_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a > 0);
++  return __aarch64_vdup_laneq_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgtz_s32 (int32x2_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a > 0);
++  return __aarch64_vdup_laneq_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgtz_s64 (int64x1_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a > __AARCH64_INT64_C (0));
++  return __aarch64_vdup_laneq_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtzq_f32 (float32x4_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_p8 (poly8x16_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a > 0.0f);
++  return __aarch64_vdup_laneq_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtzq_f64 (float64x2_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_p16 (poly16x8_t __a, const int __b)
+ {
+-    return (uint64x2_t) (__a > 0.0);
++  return __aarch64_vdup_laneq_p16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgtzq_s8 (int8x16_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_p64 (poly64x2_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a > 0);
++  return __aarch64_vdup_laneq_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgtzq_s16 (int16x8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s8 (int8x16_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a > 0);
++  return __aarch64_vdup_laneq_s8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtzq_s32 (int32x4_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s16 (int16x8_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a > 0);
++  return __aarch64_vdup_laneq_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtzq_s64 (int64x2_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s32 (int32x4_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a > __AARCH64_INT64_C (0));
++  return __aarch64_vdup_laneq_s32 (__a, __b);
+ }
+ 
+-/* vcgtz - scalar.  */
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s64 (int64x2_t __a, const int __b)
++{
++  return __aarch64_vdup_laneq_s64 (__a, __b);
++}
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcgtzs_f32 (float32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __a > 0.0f ? -1 : 0;
++  return __aarch64_vdup_laneq_u8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtzd_s64 (int64_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __a > 0 ? -1ll : 0ll;
++  return __aarch64_vdup_laneq_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtzd_f64 (float64_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __a > 0.0 ? -1ll : 0ll;
++  return __aarch64_vdup_laneq_u32 (__a, __b);
+ }
+ 
+-/* vcle - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcle_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u64 (uint64x2_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= __b);
++  return __aarch64_vdup_laneq_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcle_f64 (float64x1_t __a, float64x1_t __b)
++/* vdupq_lane  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f16 (float16x4_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= __b);
++  return __aarch64_vdupq_lane_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcle_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f32 (float32x2_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a <= __b);
++  return __aarch64_vdupq_lane_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcle_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f64 (float64x1_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a <= __b);
++  return __aarch64_vdupq_lane_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcle_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_p8 (poly8x8_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= __b);
++  return __aarch64_vdupq_lane_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcle_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_p16 (poly16x4_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= __b);
++  return __aarch64_vdupq_lane_p16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcle_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_p64 (poly64x1_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcle_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s8 (int8x8_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_s8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcle_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s16 (int16x4_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcle_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s32 (int32x2_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_s32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcleq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s64 (int64x1_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= __b);
++  return __aarch64_vdupq_lane_s64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcleq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u8 (uint8x8_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcleq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u16 (uint16x4_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcleq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u32 (uint32x2_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcleq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u64 (uint64x1_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcleq_s64 (int64x2_t __a, int64x2_t __b)
++/* vdupq_laneq  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_f16 (float16x8_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= __b);
++  return __aarch64_vdupq_laneq_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_f32 (float32x4_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_f64 (float64x2_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_p8 (poly8x16_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcleq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_p16 (poly16x8_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_p16 (__a, __b);
+ }
+ 
+-/* vcle - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcles_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_p64 (poly64x2_t __a, const int __b)
+ {
+-  return __a <= __b ? -1 : 0;
++  return __aarch64_vdupq_laneq_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcled_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s8 (int8x16_t __a, const int __b)
+ {
+-  return __a <= __b ? -1ll : 0ll;
++  return __aarch64_vdupq_laneq_s8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcled_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s16 (int16x8_t __a, const int __b)
+ {
+-  return __a <= __b ? -1ll : 0ll;
++  return __aarch64_vdupq_laneq_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcled_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s32 (int32x4_t __a, const int __b)
+ {
+-  return __a <= __b ? -1ll : 0ll;
++  return __aarch64_vdupq_laneq_s32 (__a, __b);
+ }
+ 
+-/* vclez - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclez_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s64 (int64x2_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= 0.0f);
++  return __aarch64_vdupq_laneq_s64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclez_f64 (float64x1_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u8 (uint8x16_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= (float64x1_t) {0.0});
++  return __aarch64_vdupq_laneq_u8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclez_s8 (int8x8_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u16 (uint16x8_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a <= 0);
++  return __aarch64_vdupq_laneq_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclez_s16 (int16x4_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u32 (uint32x4_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a <= 0);
++  return __aarch64_vdupq_laneq_u32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclez_s32 (int32x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u64 (uint64x2_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= 0);
++  return __aarch64_vdupq_laneq_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclez_s64 (int64x1_t __a)
++/* vdupb_lane  */
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_lane_p8 (poly8x8_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= __AARCH64_INT64_C (0));
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vclezq_f32 (float32x4_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_lane_s8 (int8x8_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= 0.0f);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vclezq_f64 (float64x2_t __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_lane_u8 (uint8x8_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= 0.0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vclezq_s8 (int8x16_t __a)
++/* vduph_lane  */
++
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_f16 (float16x4_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a <= 0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vclezq_s16 (int16x8_t __a)
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_p16 (poly16x4_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a <= 0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vclezq_s32 (int32x4_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_s16 (int16x4_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= 0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vclezq_s64 (int64x2_t __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_u16 (uint16x4_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= __AARCH64_INT64_C (0));
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-/* vclez - scalar.  */
++/* vdups_lane  */
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vclezs_f32 (float32_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_lane_f32 (float32x2_t __a, const int __b)
+ {
+-  return __a <= 0.0f ? -1 : 0;
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vclezd_s64 (int64_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_lane_s32 (int32x2_t __a, const int __b)
+ {
+-  return __a <= 0 ? -1ll : 0ll;
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vclezd_f64 (float64_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_lane_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __a <= 0.0 ? -1ll : 0ll;
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-/* vclt - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclt_f32 (float32x2_t __a, float32x2_t __b)
++/* vdupd_lane  */
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_lane_f64 (float64x1_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __b);
++  return __a[0];
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_lane_s64 (int64x1_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __b);
++  return __a[0];
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclt_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_lane_u64 (uint64x1_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __b);
++  return __a[0];
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclt_s16 (int16x4_t __a, int16x4_t __b)
++/* vdupb_laneq  */
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_laneq_p8 (poly8x16_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclt_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_laneq_s8 (int8x16_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclt_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_laneq_u8 (uint8x16_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclt_u8 (uint8x8_t __a, uint8x8_t __b)
+-{
+-  return (__a < __b);
+-}
++/* vduph_laneq  */
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclt_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_f16 (float16x8_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclt_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_p16 (poly16x8_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclt_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_s16 (int16x8_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_u16 (uint16x8_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltq_f64 (float64x2_t __a, float64x2_t __b)
++/* vdups_laneq  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_laneq_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcltq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_laneq_s32 (int32x4_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcltq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_laneq_u32 (uint32x4_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltq_s32 (int32x4_t __a, int32x4_t __b)
++/* vdupd_laneq  */
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_laneq_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_laneq_s64 (int64x2_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_laneq_u64 (uint64x2_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
++/* vext  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f16 (float16x4_t __a, float16x4_t __b, __const int __c)
+ {
+-  return (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++			    (uint16x4_t) {4 - __c, 5 - __c, 6 - __c, 7 - __c});
++#else
++  return __builtin_shuffle (__a, __b,
++			    (uint16x4_t) {__c, __c + 1, __c + 2, __c + 3});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f32 (float32x2_t __a, float32x2_t __b, __const int __c)
+ {
+-  return (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f64 (float64x1_t __a, float64x1_t __b, __const int __c)
+ {
+-  return (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+-
+-/* vclt - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vclts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_p8 (poly8x8_t __a, poly8x8_t __b, __const int __c)
+ {
+-  return __a < __b ? -1 : 0;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_p16 (poly16x4_t __a, poly16x4_t __b, __const int __c)
+ {
+-  return __a < __b ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_p64 (poly64x1_t __a, poly64x1_t __b, __const int __c)
+ {
+-  return __a < __b ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s8 (int8x8_t __a, int8x8_t __b, __const int __c)
+ {
+-  return __a < __b ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-/* vcltz - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcltz_f32 (float32x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s16 (int16x4_t __a, int16x4_t __b, __const int __c)
+ {
+-  return (uint32x2_t) (__a < 0.0f);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcltz_f64 (float64x1_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s32 (int32x2_t __a, int32x2_t __b, __const int __c)
+ {
+-  return (uint64x1_t) (__a < (float64x1_t) {0.0});
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcltz_s8 (int8x8_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s64 (int64x1_t __a, int64x1_t __b, __const int __c)
+ {
+-  return (uint8x8_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcltz_s16 (int16x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u8 (uint8x8_t __a, uint8x8_t __b, __const int __c)
+ {
+-  return (uint16x4_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcltz_s32 (int32x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u16 (uint16x4_t __a, uint16x4_t __b, __const int __c)
+ {
+-  return (uint32x2_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcltz_s64 (int64x1_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u32 (uint32x2_t __a, uint32x2_t __b, __const int __c)
+ {
+-  return (uint64x1_t) (__a < __AARCH64_INT64_C (0));
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltzq_f32 (float32x4_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u64 (uint64x1_t __a, uint64x1_t __b, __const int __c)
+ {
+-  return (uint32x4_t) (__a < 0.0f);
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltzq_f64 (float64x2_t __a)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f16 (float16x8_t __a, float16x8_t __b, __const int __c)
+ {
+-  return (uint64x2_t) (__a < 0.0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++			    (uint16x8_t) {8 - __c, 9 - __c, 10 - __c, 11 - __c,
++					  12 - __c, 13 - __c, 14 - __c,
++					  15 - __c});
++#else
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {__c, __c + 1, __c + 2, __c + 3,
++					  __c + 4, __c + 5, __c + 6, __c + 7});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcltzq_s8 (int8x16_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f32 (float32x4_t __a, float32x4_t __b, __const int __c)
+ {
+-  return (uint8x16_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcltzq_s16 (int16x8_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f64 (float64x2_t __a, float64x2_t __b, __const int __c)
+ {
+-  return (uint16x8_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltzq_s32 (int32x4_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_p8 (poly8x16_t __a, poly8x16_t __b, __const int __c)
+ {
+-  return (uint32x4_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x16_t)
++      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
++       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
++       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltzq_s64 (int64x2_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_p16 (poly16x8_t __a, poly16x8_t __b, __const int __c)
+ {
+-  return (uint64x2_t) (__a < __AARCH64_INT64_C (0));
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint16x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-/* vcltz - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcltzs_f32 (float32_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_p64 (poly64x2_t __a, poly64x2_t __b, __const int __c)
+ {
+-  return __a < 0.0f ? -1 : 0;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltzd_s64 (int64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s8 (int8x16_t __a, int8x16_t __b, __const int __c)
+ {
+-  return __a < 0 ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x16_t)
++      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
++       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
++       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltzd_f64 (float64_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s16 (int16x8_t __a, int16x8_t __b, __const int __c)
+ {
+-  return __a < 0.0 ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint16x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-/* vcls.  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vcls_s8 (int8x8_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s32 (int32x4_t __a, int32x4_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv8qi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vcls_s16 (int16x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s64 (int64x2_t __a, int64x2_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv4hi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcls_s32 (int32x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u8 (uint8x16_t __a, uint8x16_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv2si (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x16_t)
++      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
++       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
++       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
++#endif
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vclsq_s8 (int8x16_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u16 (uint16x8_t __a, uint16x8_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv16qi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint16x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vclsq_s16 (int16x8_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u32 (uint32x4_t __a, uint32x4_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv8hi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vclsq_s32 (int32x4_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u64 (uint64x2_t __a, uint64x2_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv4si (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-/* vclz.  */
++/* vfma  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vclz_s8 (int8x8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  return __builtin_aarch64_clzv8qi (__a);
++  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vclz_s16 (int16x4_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+-  return __builtin_aarch64_clzv4hi (__a);
++  return __builtin_aarch64_fmav2sf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vclz_s32 (int32x2_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+-  return __builtin_aarch64_clzv2si (__a);
++  return __builtin_aarch64_fmav4sf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclz_u8 (uint8x8_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
+ {
+-  return (uint8x8_t)__builtin_aarch64_clzv8qi ((int8x8_t)__a);
++  return __builtin_aarch64_fmav2df (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclz_u16 (uint16x4_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+-  return (uint16x4_t)__builtin_aarch64_clzv4hi ((int16x4_t)__a);
++  return __builtin_aarch64_fmav2sf (__b, vdup_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclz_u32 (uint32x2_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_n_f64 (float64x1_t __a, float64x1_t __b, float64_t __c)
+ {
+-  return (uint32x2_t)__builtin_aarch64_clzv2si ((int32x2_t)__a);
++  return (float64x1_t) {__b[0] * __c + __a[0]};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vclzq_s8 (int8x16_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+-  return __builtin_aarch64_clzv16qi (__a);
++  return __builtin_aarch64_fmav4sf (__b, vdupq_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vclzq_s16 (int16x8_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_n_f64 (float64x2_t __a, float64x2_t __b, float64_t __c)
+ {
+-  return __builtin_aarch64_clzv8hi (__a);
++  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c), __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vclzq_s32 (int32x4_t __a)
++/* vfma_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_clzv4si (__a);
++  return __builtin_aarch64_fmav2sf (__b,
++				    __aarch64_vdup_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vclzq_u8 (uint8x16_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_lane_f64 (float64x1_t __a, float64x1_t __b,
++	       float64x1_t __c, const int __lane)
+ {
+-  return (uint8x16_t)__builtin_aarch64_clzv16qi ((int8x16_t)__a);
++  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vclzq_u16 (uint16x8_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmad_lane_f64 (float64_t __a, float64_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return (uint16x8_t)__builtin_aarch64_clzv8hi ((int16x8_t)__a);
++  return __builtin_fma (__b, __c[0], __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vclzq_u32 (uint32x4_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmas_lane_f32 (float32_t __a, float32_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return (uint32x4_t)__builtin_aarch64_clzv4si ((int32x4_t)__a);
++  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-/* vcnt.  */
++/* vfma_laneq  */
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vcnt_p8 (poly8x8_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	        float32x4_t __c, const int __lane)
+ {
+-  return (poly8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
++  return __builtin_aarch64_fmav2sf (__b,
++				    __aarch64_vdup_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vcnt_s8 (int8x8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_laneq_f64 (float64x1_t __a, float64x1_t __b,
++	        float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_popcountv8qi (__a);
++  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
++  return (float64x1_t) {__builtin_fma (__b[0], __c0, __a[0])};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcnt_u8 (uint8x8_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmad_laneq_f64 (float64_t __a, float64_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return (uint8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
++  return __builtin_fma (__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vcntq_p8 (poly8x16_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmas_laneq_f32 (float32_t __a, float32_t __b,
++		 float32x4_t __c, const int __lane)
+ {
+-  return (poly8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
++  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vcntq_s8 (int8x16_t __a)
++/* vfmaq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_lane_f32 (float32x4_t __a, float32x4_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_popcountv16qi (__a);
++  return __builtin_aarch64_fmav4sf (__b,
++				    __aarch64_vdupq_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcntq_u8 (uint8x16_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_lane_f64 (float64x2_t __a, float64x2_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return (uint8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
++  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c[0]), __a);
+ }
+ 
+-/* vcvt (double -> float).  */
++/* vfmaq_laneq  */
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vcvt_f16_f32 (float32x4_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++	         float32x4_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_float_truncate_lo_v4hf (__a);
++  return __builtin_aarch64_fmav4sf (__b,
++				    __aarch64_vdupq_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vcvt_high_f16_f32 (float16x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_laneq_f64 (float64x2_t __a, float64x2_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_float_truncate_hi_v8hf (__a, __b);
++  return __builtin_aarch64_fmav2df (__b,
++				    __aarch64_vdupq_laneq_f64 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvt_f32_f64 (float64x2_t __a)
++/* vfms  */
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  return __builtin_aarch64_float_truncate_lo_v2sf (__a);
++  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+-  return __builtin_aarch64_float_truncate_hi_v4sf (__a, __b);
++  return __builtin_aarch64_fmav2sf (-__b, __c, __a);
+ }
+ 
+-/* vcvt (float -> double).  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvt_f32_f16 (float16x4_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+-  return __builtin_aarch64_float_extend_lo_v4sf (__a);
++  return __builtin_aarch64_fmav4sf (-__b, __c, __a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvt_f64_f32 (float32x2_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
+ {
+-
+-  return __builtin_aarch64_float_extend_lo_v2df (__a);
++  return __builtin_aarch64_fmav2df (-__b, __c, __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvt_high_f32_f16 (float16x8_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+-  return __builtin_aarch64_vec_unpacks_hi_v8hf (__a);
++  return __builtin_aarch64_fmav2sf (-__b, vdup_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvt_high_f64_f32 (float32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_n_f64 (float64x1_t __a, float64x1_t __b, float64_t __c)
+ {
+-  return __builtin_aarch64_vec_unpacks_hi_v4sf (__a);
++  return (float64x1_t) {-__b[0] * __c + __a[0]};
+ }
+ 
+-/* vcvt  (<u>int -> float)  */
+-
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vcvtd_f64_s64 (int64_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+-  return (float64_t) __a;
++  return __builtin_aarch64_fmav4sf (-__b, vdupq_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vcvtd_f64_u64 (uint64_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_n_f64 (float64x2_t __a, float64x2_t __b, float64_t __c)
+ {
+-  return (float64_t) __a;
++  return __builtin_aarch64_fmav2df (-__b, vdupq_n_f64 (__c), __a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vcvts_f32_s32 (int32_t __a)
++/* vfms_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  return (float32_t) __a;
++  return __builtin_aarch64_fmav2sf (-__b,
++				    __aarch64_vdup_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vcvts_f32_u32 (uint32_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_lane_f64 (float64x1_t __a, float64x1_t __b,
++	       float64x1_t __c, const int __lane)
+ {
+-  return (float32_t) __a;
++  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvt_f32_s32 (int32x2_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsd_lane_f64 (float64_t __a, float64_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatv2siv2sf (__a);
++  return __builtin_fma (-__b, __c[0], __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvt_f32_u32 (uint32x2_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmss_lane_f32 (float32_t __a, float32_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatunsv2siv2sf ((int32x2_t) __a);
++  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvtq_f32_s32 (int32x4_t __a)
++/* vfms_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	        float32x4_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatv4siv4sf (__a);
++  return __builtin_aarch64_fmav2sf (-__b,
++				    __aarch64_vdup_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvtq_f32_u32 (uint32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_laneq_f64 (float64x1_t __a, float64x1_t __b,
++	        float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatunsv4siv4sf ((int32x4_t) __a);
++  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
++  return (float64x1_t) {__builtin_fma (-__b[0], __c0, __a[0])};
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvtq_f64_s64 (int64x2_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsd_laneq_f64 (float64_t __a, float64_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatv2div2df (__a);
++  return __builtin_fma (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvtq_f64_u64 (uint64x2_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmss_laneq_f32 (float32_t __a, float32_t __b,
++		 float32x4_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatunsv2div2df ((int64x2_t) __a);
++  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-/* vcvt (float -> <u>int)  */
++/* vfmsq_lane  */
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtd_s64_f64 (float64_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_lane_f32 (float32x4_t __a, float32x4_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return (int64_t) __a;
++  return __builtin_aarch64_fmav4sf (-__b,
++				    __aarch64_vdupq_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtd_u64_f64 (float64_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_lane_f64 (float64x2_t __a, float64x2_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return (uint64_t) __a;
++  return __builtin_aarch64_fmav2df (-__b, vdupq_n_f64 (__c[0]), __a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvts_s32_f32 (float32_t __a)
++/* vfmsq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++	         float32x4_t __c, const int __lane)
+ {
+-  return (int32_t) __a;
++  return __builtin_aarch64_fmav4sf (-__b,
++				    __aarch64_vdupq_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvts_u32_f32 (float32_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_laneq_f64 (float64x2_t __a, float64x2_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return (uint32_t) __a;
++  return __builtin_aarch64_fmav2df (-__b,
++				    __aarch64_vdupq_laneq_f64 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvt_s32_f32 (float32x2_t __a)
++/* vld1 */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_f16 (const float16_t *__a)
+ {
+-  return __builtin_aarch64_lbtruncv2sfv2si (__a);
++  return __builtin_aarch64_ld1v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvt_u32_f32 (float32x2_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_f32 (const float32_t *a)
+ {
+-  return __builtin_aarch64_lbtruncuv2sfv2si_us (__a);
++  return __builtin_aarch64_ld1v2sf ((const __builtin_aarch64_simd_sf *) a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_f64 (const float64_t *a)
+ {
+-  return __builtin_aarch64_lbtruncv4sfv4si (__a);
++  return (float64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_p8 (const poly8_t *a)
+ {
+-  return __builtin_aarch64_lbtruncuv4sfv4si_us (__a);
++  return (poly8x8_t)
++    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvt_s64_f64 (float64x1_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_p16 (const poly16_t *a)
+ {
+-  return (int64x1_t) {vcvtd_s64_f64 (__a[0])};
++  return (poly16x4_t)
++    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvt_u64_f64 (float64x1_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_p64 (const poly64_t *a)
+ {
+-  return (uint64x1_t) {vcvtd_u64_f64 (__a[0])};
++  return (poly64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s8 (const int8_t *a)
+ {
+-  return __builtin_aarch64_lbtruncv2dfv2di (__a);
++  return __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s16 (const int16_t *a)
+ {
+-  return __builtin_aarch64_lbtruncuv2dfv2di_us (__a);
++  return __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-/* vcvta  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtad_s64_f64 (float64_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s32 (const int32_t *a)
+ {
+-  return __builtin_aarch64_lrounddfdi (__a);
++  return __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtad_u64_f64 (float64_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s64 (const int64_t *a)
+ {
+-  return __builtin_aarch64_lroundudfdi_us (__a);
++  return (int64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtas_s32_f32 (float32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u8 (const uint8_t *a)
+ {
+-  return __builtin_aarch64_lroundsfsi (__a);
++  return (uint8x8_t)
++    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtas_u32_f32 (float32_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u16 (const uint16_t *a)
+ {
+-  return __builtin_aarch64_lroundusfsi_us (__a);
++  return (uint16x4_t)
++    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvta_s32_f32 (float32x2_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u32 (const uint32_t *a)
+ {
+-  return __builtin_aarch64_lroundv2sfv2si (__a);
++  return (uint32x2_t)
++    __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvta_u32_f32 (float32x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u64 (const uint64_t *a)
+ {
+-  return __builtin_aarch64_lrounduv2sfv2si_us (__a);
++  return (uint64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtaq_s32_f32 (float32x4_t __a)
++/* vld1q */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_f16 (const float16_t *__a)
+ {
+-  return __builtin_aarch64_lroundv4sfv4si (__a);
++  return __builtin_aarch64_ld1v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtaq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_f32 (const float32_t *a)
+ {
+-  return __builtin_aarch64_lrounduv4sfv4si_us (__a);
++  return __builtin_aarch64_ld1v4sf ((const __builtin_aarch64_simd_sf *) a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvta_s64_f64 (float64x1_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_f64 (const float64_t *a)
+ {
+-  return (int64x1_t) {vcvtad_s64_f64 (__a[0])};
++  return __builtin_aarch64_ld1v2df ((const __builtin_aarch64_simd_df *) a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvta_u64_f64 (float64x1_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_p8 (const poly8_t *a)
+ {
+-  return (uint64x1_t) {vcvtad_u64_f64 (__a[0])};
++  return (poly8x16_t)
++    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtaq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_p16 (const poly16_t *a)
+ {
+-  return __builtin_aarch64_lroundv2dfv2di (__a);
++  return (poly16x8_t)
++    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtaq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_p64 (const poly64_t *a)
+ {
+-  return __builtin_aarch64_lrounduv2dfv2di_us (__a);
++  return (poly64x2_t)
++    __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
+ }
+ 
+-/* vcvtm  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtmd_s64_f64 (float64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s8 (const int8_t *a)
+ {
+-  return __builtin_llfloor (__a);
++  return __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtmd_u64_f64 (float64_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s16 (const int16_t *a)
+ {
+-  return __builtin_aarch64_lfloorudfdi_us (__a);
++  return __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtms_s32_f32 (float32_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s32 (const int32_t *a)
+ {
+-  return __builtin_ifloorf (__a);
++  return __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtms_u32_f32 (float32_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s64 (const int64_t *a)
+ {
+-  return __builtin_aarch64_lfloorusfsi_us (__a);
++  return __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvtm_s32_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u8 (const uint8_t *a)
+ {
+-  return __builtin_aarch64_lfloorv2sfv2si (__a);
++  return (uint8x16_t)
++    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvtm_u32_f32 (float32x2_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u16 (const uint16_t *a)
+ {
+-  return __builtin_aarch64_lflooruv2sfv2si_us (__a);
++  return (uint16x8_t)
++    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtmq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u32 (const uint32_t *a)
+ {
+-  return __builtin_aarch64_lfloorv4sfv4si (__a);
++  return (uint32x4_t)
++    __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtmq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u64 (const uint64_t *a)
+ {
+-  return __builtin_aarch64_lflooruv4sfv4si_us (__a);
++  return (uint64x2_t)
++    __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvtm_s64_f64 (float64x1_t __a)
++/* vld1_dup  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_f16 (const float16_t* __a)
+ {
+-  return (int64x1_t) {vcvtmd_s64_f64 (__a[0])};
++  return vdup_n_f16 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvtm_u64_f64 (float64x1_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_f32 (const float32_t* __a)
+ {
+-  return (uint64x1_t) {vcvtmd_u64_f64 (__a[0])};
++  return vdup_n_f32 (*__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtmq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_f64 (const float64_t* __a)
+ {
+-  return __builtin_aarch64_lfloorv2dfv2di (__a);
++  return vdup_n_f64 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtmq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_p8 (const poly8_t* __a)
+ {
+-  return __builtin_aarch64_lflooruv2dfv2di_us (__a);
++  return vdup_n_p8 (*__a);
+ }
+ 
+-/* vcvtn  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtnd_s64_f64 (float64_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_p16 (const poly16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintndfdi (__a);
++  return vdup_n_p16 (*__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtnd_u64_f64 (float64_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_p64 (const poly64_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnudfdi_us (__a);
++  return vdup_n_p64 (*__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtns_s32_f32 (float32_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s8 (const int8_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnsfsi (__a);
++  return vdup_n_s8 (*__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtns_u32_f32 (float32_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s16 (const int16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnusfsi_us (__a);
++  return vdup_n_s16 (*__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvtn_s32_f32 (float32x2_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s32 (const int32_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnv2sfv2si (__a);
++  return vdup_n_s32 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvtn_u32_f32 (float32x2_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s64 (const int64_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnuv2sfv2si_us (__a);
++  return vdup_n_s64 (*__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtnq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u8 (const uint8_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnv4sfv4si (__a);
++  return vdup_n_u8 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtnq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u16 (const uint16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnuv4sfv4si_us (__a);
++  return vdup_n_u16 (*__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvtn_s64_f64 (float64x1_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u32 (const uint32_t* __a)
+ {
+-  return (int64x1_t) {vcvtnd_s64_f64 (__a[0])};
++  return vdup_n_u32 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvtn_u64_f64 (float64x1_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u64 (const uint64_t* __a)
+ {
+-  return (uint64x1_t) {vcvtnd_u64_f64 (__a[0])};
++  return vdup_n_u64 (*__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtnq_s64_f64 (float64x2_t __a)
++/* vld1q_dup  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_f16 (const float16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnv2dfv2di (__a);
++  return vdupq_n_f16 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtnq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_f32 (const float32_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnuv2dfv2di_us (__a);
++  return vdupq_n_f32 (*__a);
+ }
+ 
+-/* vcvtp  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtpd_s64_f64 (float64_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_f64 (const float64_t* __a)
+ {
+-  return __builtin_llceil (__a);
++  return vdupq_n_f64 (*__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtpd_u64_f64 (float64_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_p8 (const poly8_t* __a)
+ {
+-  return __builtin_aarch64_lceiludfdi_us (__a);
++  return vdupq_n_p8 (*__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtps_s32_f32 (float32_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_p16 (const poly16_t* __a)
+ {
+-  return __builtin_iceilf (__a);
++  return vdupq_n_p16 (*__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtps_u32_f32 (float32_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_p64 (const poly64_t* __a)
+ {
+-  return __builtin_aarch64_lceilusfsi_us (__a);
++  return vdupq_n_p64 (*__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvtp_s32_f32 (float32x2_t __a)
++ __extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s8 (const int8_t* __a)
+ {
+-  return __builtin_aarch64_lceilv2sfv2si (__a);
++  return vdupq_n_s8 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvtp_u32_f32 (float32x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s16 (const int16_t* __a)
+ {
+-  return __builtin_aarch64_lceiluv2sfv2si_us (__a);
++  return vdupq_n_s16 (*__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtpq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s32 (const int32_t* __a)
+ {
+-  return __builtin_aarch64_lceilv4sfv4si (__a);
++  return vdupq_n_s32 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtpq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s64 (const int64_t* __a)
+ {
+-  return __builtin_aarch64_lceiluv4sfv4si_us (__a);
++  return vdupq_n_s64 (*__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvtp_s64_f64 (float64x1_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u8 (const uint8_t* __a)
+ {
+-  return (int64x1_t) {vcvtpd_s64_f64 (__a[0])};
++  return vdupq_n_u8 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvtp_u64_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u16 (const uint16_t* __a)
+ {
+-  return (uint64x1_t) {vcvtpd_u64_f64 (__a[0])};
++  return vdupq_n_u16 (*__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtpq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u32 (const uint32_t* __a)
+ {
+-  return __builtin_aarch64_lceilv2dfv2di (__a);
++  return vdupq_n_u32 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtpq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u64 (const uint64_t* __a)
+ {
+-  return __builtin_aarch64_lceiluv2dfv2di_us (__a);
++  return vdupq_n_u64 (*__a);
+ }
+ 
+-/* vdup_n  */
++/* vld1_lane  */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vdup_n_f32 (float32_t __a)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_f16 (const float16_t *__src, float16x4_t __vec, const int __lane)
+ {
+-  return (float32x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vdup_n_f64 (float64_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_f32 (const float32_t *__src, float32x2_t __vec, const int __lane)
+ {
+-  return (float64x1_t) {__a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vdup_n_p8 (poly8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_f64 (const float64_t *__src, float64x1_t __vec, const int __lane)
+ {
+-  return (poly8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vdup_n_p16 (poly16_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_p8 (const poly8_t *__src, poly8x8_t __vec, const int __lane)
+ {
+-  return (poly16x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vdup_n_s8 (int8_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_p16 (const poly16_t *__src, poly16x4_t __vec, const int __lane)
+ {
+-  return (int8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vdup_n_s16 (int16_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_p64 (const poly64_t *__src, poly64x1_t __vec, const int __lane)
+ {
+-  return (int16x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vdup_n_s32 (int32_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s8 (const int8_t *__src, int8x8_t __vec, const int __lane)
+ {
+-  return (int32x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vdup_n_s64 (int64_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s16 (const int16_t *__src, int16x4_t __vec, const int __lane)
+ {
+-  return (int64x1_t) {__a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vdup_n_u8 (uint8_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s32 (const int32_t *__src, int32x2_t __vec, const int __lane)
+ {
+-  return (uint8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vdup_n_u16 (uint16_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s64 (const int64_t *__src, int64x1_t __vec, const int __lane)
+ {
+-  return (uint16x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vdup_n_u32 (uint32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u8 (const uint8_t *__src, uint8x8_t __vec, const int __lane)
+ {
+-  return (uint32x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vdup_n_u64 (uint64_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u16 (const uint16_t *__src, uint16x4_t __vec, const int __lane)
+ {
+-  return (uint64x1_t) {__a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-/* vdupq_n  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vdupq_n_f32 (float32_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u32 (const uint32_t *__src, uint32x2_t __vec, const int __lane)
+ {
+-  return (float32x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vdupq_n_f64 (float64_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u64 (const uint64_t *__src, uint64x1_t __vec, const int __lane)
+ {
+-  return (float64x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vdupq_n_p8 (uint32_t __a)
++/* vld1q_lane  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_f16 (const float16_t *__src, float16x8_t __vec, const int __lane)
+ {
+-  return (poly8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
+-		       __a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vdupq_n_p16 (uint32_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_f32 (const float32_t *__src, float32x4_t __vec, const int __lane)
+ {
+-  return (poly16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vdupq_n_s8 (int32_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_f64 (const float64_t *__src, float64x2_t __vec, const int __lane)
+ {
+-  return (int8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
+-		      __a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vdupq_n_s16 (int32_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_p8 (const poly8_t *__src, poly8x16_t __vec, const int __lane)
+ {
+-  return (int16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vdupq_n_s32 (int32_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_p16 (const poly16_t *__src, poly16x8_t __vec, const int __lane)
+ {
+-  return (int32x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vdupq_n_s64 (int64_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_p64 (const poly64_t *__src, poly64x2_t __vec, const int __lane)
+ {
+-  return (int64x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vdupq_n_u8 (uint32_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s8 (const int8_t *__src, int8x16_t __vec, const int __lane)
+ {
+-  return (uint8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
+-		       __a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vdupq_n_u16 (uint32_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s16 (const int16_t *__src, int16x8_t __vec, const int __lane)
+ {
+-  return (uint16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vdupq_n_u32 (uint32_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s32 (const int32_t *__src, int32x4_t __vec, const int __lane)
+ {
+-  return (uint32x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vdupq_n_u64 (uint64_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s64 (const int64_t *__src, int64x2_t __vec, const int __lane)
+ {
+-  return (uint64x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-/* vdup_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vdup_lane_f32 (float32x2_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u8 (const uint8_t *__src, uint8x16_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_f32 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vdup_lane_f64 (float64x1_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u16 (const uint16_t *__src, uint16x8_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_f64 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vdup_lane_p8 (poly8x8_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u32 (const uint32_t *__src, uint32x4_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_p8 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vdup_lane_p16 (poly16x4_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u64 (const uint64_t *__src, uint64x2_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_p16 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vdup_lane_s8 (int8x8_t __a, const int __b)
++/* vldn */
++
++__extension__ extern __inline int64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vdup_lane_s8 (__a, __b);
++  int64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vdup_lane_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline uint64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vdup_lane_s16 (__a, __b);
++  uint64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vdup_lane_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline float64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vdup_lane_s32 (__a, __b);
++  float64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vdup_lane_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline int8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdup_lane_s64 (__a, __b);
++  int8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vdup_lane_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline poly8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdup_lane_u8 (__a, __b);
++  poly8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vdup_lane_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline poly64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_p64 (const poly64_t * __a)
+ {
+-  return __aarch64_vdup_lane_u16 (__a, __b);
++  poly64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vdup_lane_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline int16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vdup_lane_u32 (__a, __b);
++  int16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vdup_lane_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline poly16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vdup_lane_u64 (__a, __b);
++  poly16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-/* vdup_laneq  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vdup_laneq_f32 (float32x4_t __a, const int __b)
++__extension__ extern __inline int32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_f32 (__a, __b);
++  int32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vdup_laneq_f64 (float64x2_t __a, const int __b)
++__extension__ extern __inline uint8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vdup_laneq_f64 (__a, __b);
++  uint8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vdup_laneq_p8 (poly8x16_t __a, const int __b)
++__extension__ extern __inline uint16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_p8 (__a, __b);
++  uint16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vdup_laneq_p16 (poly16x8_t __a, const int __b)
++__extension__ extern __inline uint32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_p16 (__a, __b);
++  uint32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vdup_laneq_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline float16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s8 (__a, __b);
++  float16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hf (__a);
++  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_dregoiv4hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vdup_laneq_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline float32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_f32 (const float32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s16 (__a, __b);
++  float32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vdup_laneq_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline int8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s32 (__a, __b);
++  int8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vdup_laneq_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline poly8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s64 (__a, __b);
++  poly8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vdup_laneq_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline int16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u8 (__a, __b);
++  int16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vdup_laneq_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline poly16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u16 (__a, __b);
++  poly16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vdup_laneq_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline poly64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_p64 (const poly64_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u32 (__a, __b);
++  poly64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vdup_laneq_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline int32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u64 (__a, __b);
++  int32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-/* vdupq_lane  */
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vdupq_lane_f32 (float32x2_t __a, const int __b)
++__extension__ extern __inline int64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_f32 (__a, __b);
++  int64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vdupq_lane_f64 (float64x1_t __a, const int __b)
++__extension__ extern __inline uint8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vdupq_lane_f64 (__a, __b);
++  uint8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vdupq_lane_p8 (poly8x8_t __a, const int __b)
++__extension__ extern __inline uint16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vdupq_lane_p8 (__a, __b);
++  uint16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vdupq_lane_p16 (poly16x4_t __a, const int __b)
++__extension__ extern __inline uint32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vdupq_lane_p16 (__a, __b);
++  uint32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vdupq_lane_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline uint64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s8 (__a, __b);
++  uint64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vdupq_lane_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline float16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s16 (__a, __b);
++  float16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hf (__a);
++  ret.val[0] = __builtin_aarch64_get_qregoiv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vdupq_lane_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline float32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_f32 (const float32_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s32 (__a, __b);
++  float32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vdupq_lane_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline float64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s64 (__a, __b);
++  float64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vdupq_lane_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline int64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u8 (__a, __b);
++  int64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vdupq_lane_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline uint64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u16 (__a, __b);
++  uint64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vdupq_lane_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline float64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u32 (__a, __b);
++  float64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vdupq_lane_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline int8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u64 (__a, __b);
++  int8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupq_laneq  */
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vdupq_laneq_f32 (float32x4_t __a, const int __b)
++__extension__ extern __inline poly8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_f32 (__a, __b);
++  poly8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vdupq_laneq_f64 (float64x2_t __a, const int __b)
++__extension__ extern __inline int16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_f64 (__a, __b);
++  int16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vdupq_laneq_p8 (poly8x16_t __a, const int __b)
++__extension__ extern __inline poly16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_p8 (__a, __b);
++  poly16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vdupq_laneq_p16 (poly16x8_t __a, const int __b)
++__extension__ extern __inline int32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_p16 (__a, __b);
++  int32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline uint8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s8 (__a, __b);
++  uint8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline uint16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s16 (__a, __b);
++  uint16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s32 (__a, __b);
++  uint32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline float16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s64 (__a, __b);
++  float16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hf (__a);
++  ret.val[0] = __builtin_aarch64_get_dregciv4hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_dregciv4hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_dregciv4hf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline float32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_f32 (const float32_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u8 (__a, __b);
++  float32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline poly64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_p64 (const poly64_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u16 (__a, __b);
++  poly64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u32 (__a, __b);
++  int8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline poly8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u64 (__a, __b);
++  poly8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupb_lane  */
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
+-vdupb_lane_p8 (poly8x8_t __a, const int __b)
++__extension__ extern __inline int16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vdupb_lane_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline poly16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  poly16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vdupb_lane_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline int32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-/* vduph_lane  */
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
+-vduph_lane_p16 (poly16x4_t __a, const int __b)
++__extension__ extern __inline int64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vduph_lane_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline uint8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vduph_lane_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline uint16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-/* vdups_lane  */
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vdups_lane_f32 (float32x2_t __a, const int __b)
++__extension__ extern __inline uint32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vdups_lane_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline uint64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vdups_lane_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline float16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  float16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hf (__a);
++  ret.val[0] = __builtin_aarch64_get_qregciv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregciv8hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_qregciv8hf (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupd_lane  */
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vdupd_lane_f64 (float64x1_t __a, const int __b)
++__extension__ extern __inline float32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __b);
+-  return __a[0];
++  float32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vdupd_lane_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline float64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_f64 (const float64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __b);
+-  return __a[0];
++  float64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vdupd_lane_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline poly64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_p64 (const poly64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __b);
+-  return __a[0];
++  poly64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupb_laneq  */
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
+-vdupb_laneq_p8 (poly8x16_t __a, const int __b)
++__extension__ extern __inline int64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vdupb_laneq_s8 (int8x16_t __a, const int __attribute__ ((unused)) __b)
++__extension__ extern __inline uint64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vdupb_laneq_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline float64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  float64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
++  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
++  return ret;
+ }
+ 
+-/* vduph_laneq  */
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
+-vduph_laneq_p16 (poly16x8_t __a, const int __b)
++__extension__ extern __inline int8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vduph_laneq_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline poly8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  poly8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vduph_laneq_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline int16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-/* vdups_laneq  */
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vdups_laneq_f32 (float32x4_t __a, const int __b)
++__extension__ extern __inline poly16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  poly16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vdups_laneq_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline int32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vdups_laneq_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline uint8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-/* vdupd_laneq  */
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vdupd_laneq_f64 (float64x2_t __a, const int __b)
++__extension__ extern __inline uint16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vdupd_laneq_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vdupd_laneq_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline float16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  float16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hf (__a);
++  ret.val[0] = __builtin_aarch64_get_dregxiv4hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_dregxiv4hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_dregxiv4hf (__o, 2);
++  ret.val[3] = __builtin_aarch64_get_dregxiv4hf (__o, 3);
++  return ret;
+ }
+ 
+-/* vext  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vext_f32 (float32x2_t __a, float32x2_t __b, __const int __c)
++__extension__ extern __inline float32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
+-#endif
++  float32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
++  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vext_f64 (float64x1_t __a, float64x1_t __b, __const int __c)
++__extension__ extern __inline poly64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_p64 (const poly64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-  /* The only possible index to the assembler instruction returns element 0.  */
+-  return __a;
++  poly64x1x4_t  ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 2);
++  ret.val[3] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 3);
++  return ret;
+ }
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vext_p8 (poly8x8_t __a, poly8x8_t __b, __const int __c)
++
++__extension__ extern __inline int8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s8 (const int8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  int8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vext_p16 (poly16x4_t __a, poly16x4_t __b, __const int __c)
++__extension__ extern __inline poly8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_p8 (const poly8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  poly8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vext_s8 (int8x8_t __a, int8x8_t __b, __const int __c)
++__extension__ extern __inline int16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s16 (const int16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  int16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vext_s16 (int16x4_t __a, int16x4_t __b, __const int __c)
++__extension__ extern __inline poly16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_p16 (const poly16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  poly16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vext_s32 (int32x2_t __a, int32x2_t __b, __const int __c)
++__extension__ extern __inline int32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s32 (const int32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
+-#endif
++  int32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vext_s64 (int64x1_t __a, int64x1_t __b, __const int __c)
++__extension__ extern __inline int64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s64 (const int64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-  /* The only possible index to the assembler instruction returns element 0.  */
+-  return __a;
++  int64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vext_u8 (uint8x8_t __a, uint8x8_t __b, __const int __c)
++__extension__ extern __inline uint8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u8 (const uint8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  uint8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vext_u16 (uint16x4_t __a, uint16x4_t __b, __const int __c)
++__extension__ extern __inline uint16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u16 (const uint16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  uint16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vext_u32 (uint32x2_t __a, uint32x2_t __b, __const int __c)
++__extension__ extern __inline uint32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u32 (const uint32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
+-#endif
++  uint32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vext_u64 (uint64x1_t __a, uint64x1_t __b, __const int __c)
++__extension__ extern __inline uint64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u64 (const uint64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-  /* The only possible index to the assembler instruction returns element 0.  */
+-  return __a;
++  uint64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vextq_f32 (float32x4_t __a, float32x4_t __b, __const int __c)
++__extension__ extern __inline float16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_f16 (const float16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  float16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hf (__a);
++  ret.val[0] = __builtin_aarch64_get_qregxiv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregxiv8hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_qregxiv8hf (__o, 2);
++  ret.val[3] = __builtin_aarch64_get_qregxiv8hf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vextq_f64 (float64x2_t __a, float64x2_t __b, __const int __c)
++__extension__ extern __inline float32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
+-#endif
++  float32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
++  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vextq_p8 (poly8x16_t __a, poly8x16_t __b, __const int __c)
++__extension__ extern __inline float64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_f64 (const float64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x16_t)
+-      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
+-       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
+-       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
+-#endif
++  float64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
++  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vextq_p16 (poly16x8_t __a, poly16x8_t __b, __const int __c)
++__extension__ extern __inline poly64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_p64 (const poly64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint16x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  poly64x2x4_t  ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 2);
++  ret.val[3] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vextq_s8 (int8x16_t __a, int8x16_t __b, __const int __c)
++/* vldn_dup */
++
++__extension__ extern __inline int8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s8 (const int8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x16_t)
+-      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
+-       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
+-       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
+-#endif
++  int8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vextq_s16 (int16x8_t __a, int16x8_t __b, __const int __c)
++__extension__ extern __inline int16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s16 (const int16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint16x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  int16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vextq_s32 (int32x4_t __a, int32x4_t __b, __const int __c)
++__extension__ extern __inline int32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s32 (const int32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  int32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vextq_s64 (int64x2_t __a, int64x2_t __b, __const int __c)
++__extension__ extern __inline float16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_f16 (const float16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
+-#endif
++  float16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
++  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregoiv4hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vextq_u8 (uint8x16_t __a, uint8x16_t __b, __const int __c)
++__extension__ extern __inline float32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x16_t)
+-      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
+-       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
+-       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
+-#endif
++  float32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vextq_u16 (uint16x8_t __a, uint16x8_t __b, __const int __c)
++__extension__ extern __inline float64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_f64 (const float64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint16x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  float64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rdf ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vextq_u32 (uint32x4_t __a, uint32x4_t __b, __const int __c)
++__extension__ extern __inline uint8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u8 (const uint8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  uint8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vextq_u64 (uint64x2_t __a, uint64x2_t __b, __const int __c)
++__extension__ extern __inline uint16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u16 (const uint16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
+-#endif
++  uint16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-/* vfma  */
+-
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfma_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline uint32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u32 (const uint32_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
++  uint32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
++__extension__ extern __inline poly8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b, __c, __a);
++  poly8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
++__extension__ extern __inline poly16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b, __c, __a);
++  poly16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
++__extension__ extern __inline poly64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_p64 (const poly64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b, __c, __a);
++  poly64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
++
++__extension__ extern __inline int64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s64 (const int64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b, vdup_n_f32 (__c), __a);
++  int64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
++__extension__ extern __inline uint64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b, vdupq_n_f32 (__c), __a);
++  uint64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_n_f64 (float64x2_t __a, float64x2_t __b, float64_t __c)
++__extension__ extern __inline int8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c), __a);
++  int8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-/* vfma_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline poly8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b,
+-				    __aarch64_vdup_lane_f32 (__c, __lane),
+-				    __a);
++  poly8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfma_lane_f64 (float64x1_t __a, float64x1_t __b,
+-	       float64x1_t __c, const int __lane)
++__extension__ extern __inline int16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s16 (const int16_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
++  int16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmad_lane_f64 (float64_t __a, float64_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline poly16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_fma (__b, __c[0], __a);
++  poly16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmas_lane_f32 (float32_t __a, float32_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s32 (const int32_t * __a)
+ {
+-  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  int32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-/* vfma_laneq  */
++__extension__ extern __inline int64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s64 (const int64_t * __a)
++{
++  int64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	        float32x4_t __c, const int __lane)
++__extension__ extern __inline uint8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u8 (const uint8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b,
+-				    __aarch64_vdup_laneq_f32 (__c, __lane),
+-				    __a);
++  uint8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfma_laneq_f64 (float64x1_t __a, float64x1_t __b,
+-	        float64x2_t __c, const int __lane)
++__extension__ extern __inline uint16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u16 (const uint16_t * __a)
+ {
+-  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
+-  return (float64x1_t) {__builtin_fma (__b[0], __c0, __a[0])};
++  uint16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmad_laneq_f64 (float64_t __a, float64_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline uint32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_fma (__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  uint32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmas_laneq_f32 (float32_t __a, float32_t __b,
+-		 float32x4_t __c, const int __lane)
++__extension__ extern __inline uint64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  uint64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
+ }
+ 
+-/* vfmaq_lane  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline float16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b,
+-				    __aarch64_vdupq_lane_f32 (__c, __lane),
+-				    __a);
++  float16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregoiv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_lane_f64 (float64x2_t __a, float64x2_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline float32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_f32 (const float32_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c[0]), __a);
++  float32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
++  return ret;
+ }
+ 
+-/* vfmaq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-	         float32x4_t __c, const int __lane)
++__extension__ extern __inline float64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_f64 (const float64_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b,
+-				    __aarch64_vdupq_laneq_f32 (__c, __lane),
+-				    __a);
++  float64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_laneq_f64 (float64x2_t __a, float64x2_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline poly64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_p64 (const poly64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b,
+-				    __aarch64_vdupq_laneq_f64 (__c, __lane),
+-				    __a);
++  poly64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 1);
++  return ret;
+ }
+ 
+-/* vfms  */
+-
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfms_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline int64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s64 (const int64_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
++  int64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
++__extension__ extern __inline uint64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (-__b, __c, __a);
++  uint64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
++__extension__ extern __inline float64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_f64 (const float64_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (-__b, __c, __a);
++  float64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rdf ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmsq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
++__extension__ extern __inline int8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (-__b, __c, __a);
++  int8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-
+-/* vfms_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfms_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline poly8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (-__b,
+-				    __aarch64_vdup_lane_f32 (__c, __lane),
+-				    __a);
++  poly8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfms_lane_f64 (float64x1_t __a, float64x1_t __b,
+-	       float64x1_t __c, const int __lane)
++__extension__ extern __inline int16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s16 (const int16_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
++  int16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmsd_lane_f64 (float64_t __a, float64_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline poly16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_fma (-__b, __c[0], __a);
++  poly16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmss_lane_f32 (float32_t __a, float32_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline int32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s32 (const int32_t * __a)
+ {
+-  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  int32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-/* vfms_laneq  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfms_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	        float32x4_t __c, const int __lane)
++__extension__ extern __inline uint8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u8 (const uint8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (-__b,
+-				    __aarch64_vdup_laneq_f32 (__c, __lane),
+-				    __a);
++  uint8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfms_laneq_f64 (float64x1_t __a, float64x1_t __b,
+-	        float64x2_t __c, const int __lane)
++__extension__ extern __inline uint16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u16 (const uint16_t * __a)
+ {
+-  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
+-  return (float64x1_t) {__builtin_fma (-__b[0], __c0, __a[0])};
++  uint16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmsd_laneq_f64 (float64_t __a, float64_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline uint32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_fma (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  uint32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmss_laneq_f32 (float32_t __a, float32_t __b,
+-		 float32x4_t __c, const int __lane)
++__extension__ extern __inline float16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  float16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 0);
++  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 1);
++  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 2);
++  return ret;
+ }
+ 
+-/* vfmsq_lane  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmsq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline float32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_f32 (const float32_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (-__b,
+-				    __aarch64_vdupq_lane_f32 (__c, __lane),
+-				    __a);
++  float32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmsq_lane_f64 (float64x2_t __a, float64x2_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline poly64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_p64 (const poly64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (-__b, vdupq_n_f64 (__c[0]), __a);
++  poly64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 2);
++  return ret;
+ }
+ 
+-/* vfmsq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-	         float32x4_t __c, const int __lane)
++__extension__ extern __inline int8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (-__b,
+-				    __aarch64_vdupq_laneq_f32 (__c, __lane),
+-				    __a);
++  int8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmsq_laneq_f64 (float64x2_t __a, float64x2_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline poly8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (-__b,
+-				    __aarch64_vdupq_laneq_f64 (__c, __lane),
+-				    __a);
++  poly8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-/* vld1 */
++__extension__ extern __inline int16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s16 (const int16_t * __a)
++{
++  int16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
++}
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vld1_f16 (const float16_t *__a)
++__extension__ extern __inline poly16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4hf (__a);
++  poly16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vld1_f32 (const float32_t *a)
++__extension__ extern __inline int32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s32 (const int32_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2sf ((const __builtin_aarch64_simd_sf *) a);
++  int32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vld1_f64 (const float64_t *a)
++__extension__ extern __inline int64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s64 (const int64_t * __a)
+ {
+-  return (float64x1_t) {*a};
++  int64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vld1_p8 (const poly8_t *a)
++__extension__ extern __inline uint8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u8 (const uint8_t * __a)
+ {
+-  return (poly8x8_t)
+-    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
++  uint8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vld1_p16 (const poly16_t *a)
++__extension__ extern __inline uint16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u16 (const uint16_t * __a)
+ {
+-  return (poly16x4_t)
+-    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
++  uint16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vld1_s8 (const int8_t *a)
++__extension__ extern __inline uint32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
++  uint32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vld1_s16 (const int16_t *a)
++__extension__ extern __inline uint64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
++  uint64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vld1_s32 (const int32_t *a)
++__extension__ extern __inline float16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
++  float16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 0);
++  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 1);
++  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vld1_s64 (const int64_t *a)
++__extension__ extern __inline float32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_f32 (const float32_t * __a)
+ {
+-  return (int64x1_t) {*a};
++  float32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vld1_u8 (const uint8_t *a)
++__extension__ extern __inline float64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_f64 (const float64_t * __a)
+ {
+-  return (uint8x8_t)
+-    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
++  float64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vld1_u16 (const uint16_t *a)
++__extension__ extern __inline poly64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_p64 (const poly64_t * __a)
+ {
+-  return (uint16x4_t)
+-    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
++  poly64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vld1_u32 (const uint32_t *a)
++__extension__ extern __inline int64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s64 (const int64_t * __a)
+ {
+-  return (uint32x2_t)
+-    __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
++  int64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vld1_u64 (const uint64_t *a)
++__extension__ extern __inline uint64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u64 (const uint64_t * __a)
+ {
+-  return (uint64x1_t) {*a};
++  uint64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-/* vld1q */
++__extension__ extern __inline float64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_f64 (const float64_t * __a)
++{
++  float64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rdf ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
++  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
++  return ret;
++}
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vld1q_f16 (const float16_t *__a)
++__extension__ extern __inline int8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_ld1v8hf (__a);
++  int8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vld1q_f32 (const float32_t *a)
++__extension__ extern __inline poly8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4sf ((const __builtin_aarch64_simd_sf *) a);
++  poly8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vld1q_f64 (const float64_t *a)
++__extension__ extern __inline int16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s16 (const int16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2df ((const __builtin_aarch64_simd_df *) a);
++  int16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vld1q_p8 (const poly8_t *a)
++__extension__ extern __inline poly16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_p16 (const poly16_t * __a)
+ {
+-  return (poly8x16_t)
+-    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
++  poly16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vld1q_p16 (const poly16_t *a)
++__extension__ extern __inline int32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s32 (const int32_t * __a)
+ {
+-  return (poly16x8_t)
+-    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
++  int32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vld1q_s8 (const int8_t *a)
++__extension__ extern __inline uint8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u8 (const uint8_t * __a)
+ {
+-  return __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
++  uint8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vld1q_s16 (const int16_t *a)
++__extension__ extern __inline uint16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u16 (const uint16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
++  uint16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vld1q_s32 (const int32_t *a)
++__extension__ extern __inline uint32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
++  uint32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vld1q_s64 (const int64_t *a)
++__extension__ extern __inline float16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
++  float16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 0);
++  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 1);
++  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 2);
++  ret.val[3] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vld1q_u8 (const uint8_t *a)
++__extension__ extern __inline float32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_f32 (const float32_t * __a)
+ {
+-  return (uint8x16_t)
+-    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
++  float32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
++  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vld1q_u16 (const uint16_t *a)
++__extension__ extern __inline poly64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_p64 (const poly64_t * __a)
+ {
+-  return (uint16x8_t)
+-    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
++  poly64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 2);
++  ret.val[3] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vld1q_u32 (const uint32_t *a)
++__extension__ extern __inline int8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s8 (const int8_t * __a)
+ {
+-  return (uint32x4_t)
+-    __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
++  int8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vld1q_u64 (const uint64_t *a)
++__extension__ extern __inline poly8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_p8 (const poly8_t * __a)
+ {
+-  return (uint64x2_t)
+-    __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
++  poly8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-/* vld1_dup  */
+-
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_f16 (const float16_t* __a)
++__extension__ extern __inline int16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s16 (const int16_t * __a)
+ {
+-  float16_t __f = *__a;
+-  return (float16x4_t) { __f, __f, __f, __f };
++  int16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vld1_dup_f32 (const float32_t* __a)
++__extension__ extern __inline poly16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_p16 (const poly16_t * __a)
+ {
+-  return vdup_n_f32 (*__a);
++  poly16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vld1_dup_f64 (const float64_t* __a)
++__extension__ extern __inline int32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s32 (const int32_t * __a)
+ {
+-  return vdup_n_f64 (*__a);
++  int32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vld1_dup_p8 (const poly8_t* __a)
++__extension__ extern __inline int64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s64 (const int64_t * __a)
+ {
+-  return vdup_n_p8 (*__a);
++  int64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_p16 (const poly16_t* __a)
++__extension__ extern __inline uint8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u8 (const uint8_t * __a)
+ {
+-  return vdup_n_p16 (*__a);
++  uint8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vld1_dup_s8 (const int8_t* __a)
++__extension__ extern __inline uint16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u16 (const uint16_t * __a)
+ {
+-  return vdup_n_s8 (*__a);
++  uint16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_s16 (const int16_t* __a)
++__extension__ extern __inline uint32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u32 (const uint32_t * __a)
+ {
+-  return vdup_n_s16 (*__a);
++  uint32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vld1_dup_s32 (const int32_t* __a)
++__extension__ extern __inline uint64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u64 (const uint64_t * __a)
+ {
+-  return vdup_n_s32 (*__a);
++  uint64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vld1_dup_s64 (const int64_t* __a)
++__extension__ extern __inline float16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_f16 (const float16_t * __a)
+ {
+-  return vdup_n_s64 (*__a);
++  float16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 0);
++  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 1);
++  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 2);
++  ret.val[3] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vld1_dup_u8 (const uint8_t* __a)
++__extension__ extern __inline float32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_f32 (const float32_t * __a)
+ {
+-  return vdup_n_u8 (*__a);
++  float32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
++  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_u16 (const uint16_t* __a)
++__extension__ extern __inline float64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_f64 (const float64_t * __a)
+ {
+-  return vdup_n_u16 (*__a);
++  float64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
++  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vld1_dup_u32 (const uint32_t* __a)
++__extension__ extern __inline poly64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_p64 (const poly64_t * __a)
+ {
+-  return vdup_n_u32 (*__a);
++  poly64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 2);
++  ret.val[3] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vld1_dup_u64 (const uint64_t* __a)
+-{
+-  return vdup_n_u64 (*__a);
++/* vld2_lane */
++
++#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
++			 qmode, ptrmode, funcsuffix, signedtype)	   \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
++{									   \
++  __builtin_aarch64_simd_oi __o;					   \
++  largetype __temp;							   \
++  __temp.val[0] =							   \
++    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
++  __temp.val[1] =							   \
++    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
++					    (signedtype) __temp.val[0],	   \
++					    0);				   \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
++					    (signedtype) __temp.val[1],	   \
++					    1);				   \
++  __o =	__builtin_aarch64_ld2_lane##mode (				   \
++	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
++  __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0);	   \
++  __b.val[1] = (vectype) __builtin_aarch64_get_dregoidi (__o, 1);	   \
++  return __b;								   \
+ }
+ 
+-/* vld1q_dup  */
++__LD2_LANE_FUNC (float16x4x2_t, float16x4_t, float16x8x2_t, float16_t, v4hf,
++		 v8hf, hf, f16, float16x8_t)
++__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v2sf, v4sf,
++		 sf, f32, float32x4_t)
++__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, df, v2df,
++		 df, f64, float64x2_t)
++__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi,
++		 p16, int16x8_t)
++__LD2_LANE_FUNC (poly64x1x2_t, poly64x1_t, poly64x2x2_t, poly64_t, di,
++		 v2di_ssps, di, p64, poly64x2_t)
++__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi,
++		 u16, int16x8_t)
++__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si,
++		 u32, int32x4_t)
++__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, di, v2di, di,
++		 u64, int64x2_t)
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_f16 (const float16_t* __a)
+-{
+-  float16_t __f = *__a;
+-  return (float16x8_t) { __f, __f, __f, __f, __f, __f, __f, __f };
++#undef __LD2_LANE_FUNC
++
++/* vld2q_lane */
++
++#define __LD2_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld2q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
++{									   \
++  __builtin_aarch64_simd_oi __o;					   \
++  intype ret;								   \
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[0], 0); \
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[1], 1); \
++  __o = __builtin_aarch64_ld2_lane##mode (				   \
++	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
++  ret.val[0] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 0);	   \
++  ret.val[1] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 1);	   \
++  return ret;								   \
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vld1q_dup_f32 (const float32_t* __a)
+-{
+-  return vdupq_n_f32 (*__a);
++__LD2_LANE_FUNC (float16x8x2_t, float16x8_t, float16_t, v8hf, hf, f16)
++__LD2_LANE_FUNC (float32x4x2_t, float32x4_t, float32_t, v4sf, sf, f32)
++__LD2_LANE_FUNC (float64x2x2_t, float64x2_t, float64_t, v2df, df, f64)
++__LD2_LANE_FUNC (poly8x16x2_t, poly8x16_t, poly8_t, v16qi, qi, p8)
++__LD2_LANE_FUNC (poly16x8x2_t, poly16x8_t, poly16_t, v8hi, hi, p16)
++__LD2_LANE_FUNC (poly64x2x2_t, poly64x2_t, poly64_t, v2di, di, p64)
++__LD2_LANE_FUNC (int8x16x2_t, int8x16_t, int8_t, v16qi, qi, s8)
++__LD2_LANE_FUNC (int16x8x2_t, int16x8_t, int16_t, v8hi, hi, s16)
++__LD2_LANE_FUNC (int32x4x2_t, int32x4_t, int32_t, v4si, si, s32)
++__LD2_LANE_FUNC (int64x2x2_t, int64x2_t, int64_t, v2di, di, s64)
++__LD2_LANE_FUNC (uint8x16x2_t, uint8x16_t, uint8_t, v16qi, qi, u8)
++__LD2_LANE_FUNC (uint16x8x2_t, uint16x8_t, uint16_t, v8hi, hi, u16)
++__LD2_LANE_FUNC (uint32x4x2_t, uint32x4_t, uint32_t, v4si, si, u32)
++__LD2_LANE_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, v2di, di, u64)
++
++#undef __LD2_LANE_FUNC
++
++/* vld3_lane */
++
++#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
++			 qmode, ptrmode, funcsuffix, signedtype)	   \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
++{									   \
++  __builtin_aarch64_simd_ci __o;					   \
++  largetype __temp;							   \
++  __temp.val[0] =							   \
++    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
++  __temp.val[1] =							   \
++    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
++  __temp.val[2] =							   \
++    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
++					    (signedtype) __temp.val[0],	   \
++					    0);				   \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
++					    (signedtype) __temp.val[1],	   \
++					    1);				   \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
++					    (signedtype) __temp.val[2],	   \
++					    2);				   \
++  __o =	__builtin_aarch64_ld3_lane##mode (				   \
++	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
++  __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0);	   \
++  __b.val[1] = (vectype) __builtin_aarch64_get_dregcidi (__o, 1);	   \
++  __b.val[2] = (vectype) __builtin_aarch64_get_dregcidi (__o, 2);	   \
++  return __b;								   \
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vld1q_dup_f64 (const float64_t* __a)
+-{
+-  return vdupq_n_f64 (*__a);
+-}
++__LD3_LANE_FUNC (float16x4x3_t, float16x4_t, float16x8x3_t, float16_t, v4hf,
++		 v8hf, hf, f16, float16x8_t)
++__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v2sf, v4sf,
++		 sf, f32, float32x4_t)
++__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, df, v2df,
++		 df, f64, float64x2_t)
++__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi,
++		 p16, int16x8_t)
++__LD3_LANE_FUNC (poly64x1x3_t, poly64x1_t, poly64x2x3_t, poly64_t, di,
++		 v2di_ssps, di, p64, poly64x2_t)
++__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi,
++		 u16, int16x8_t)
++__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v2si, v4si, si,
++		 u32, int32x4_t)
++__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, di, v2di, di,
++		 u64, int64x2_t)
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vld1q_dup_p8 (const poly8_t* __a)
+-{
+-  return vdupq_n_p8 (*__a);
+-}
++#undef __LD3_LANE_FUNC
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_p16 (const poly16_t* __a)
+-{
+-  return vdupq_n_p16 (*__a);
+-}
++/* vld3q_lane */
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vld1q_dup_s8 (const int8_t* __a)
+-{
+-  return vdupq_n_s8 (*__a);
++#define __LD3_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld3q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
++{									   \
++  __builtin_aarch64_simd_ci __o;					   \
++  intype ret;								   \
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[0], 0); \
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[1], 1); \
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[2], 2); \
++  __o = __builtin_aarch64_ld3_lane##mode (				   \
++	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
++  ret.val[0] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 0);	   \
++  ret.val[1] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 1);	   \
++  ret.val[2] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 2);	   \
++  return ret;								   \
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_s16 (const int16_t* __a)
+-{
+-  return vdupq_n_s16 (*__a);
+-}
++__LD3_LANE_FUNC (float16x8x3_t, float16x8_t, float16_t, v8hf, hf, f16)
++__LD3_LANE_FUNC (float32x4x3_t, float32x4_t, float32_t, v4sf, sf, f32)
++__LD3_LANE_FUNC (float64x2x3_t, float64x2_t, float64_t, v2df, df, f64)
++__LD3_LANE_FUNC (poly8x16x3_t, poly8x16_t, poly8_t, v16qi, qi, p8)
++__LD3_LANE_FUNC (poly16x8x3_t, poly16x8_t, poly16_t, v8hi, hi, p16)
++__LD3_LANE_FUNC (poly64x2x3_t, poly64x2_t, poly64_t, v2di, di, p64)
++__LD3_LANE_FUNC (int8x16x3_t, int8x16_t, int8_t, v16qi, qi, s8)
++__LD3_LANE_FUNC (int16x8x3_t, int16x8_t, int16_t, v8hi, hi, s16)
++__LD3_LANE_FUNC (int32x4x3_t, int32x4_t, int32_t, v4si, si, s32)
++__LD3_LANE_FUNC (int64x2x3_t, int64x2_t, int64_t, v2di, di, s64)
++__LD3_LANE_FUNC (uint8x16x3_t, uint8x16_t, uint8_t, v16qi, qi, u8)
++__LD3_LANE_FUNC (uint16x8x3_t, uint16x8_t, uint16_t, v8hi, hi, u16)
++__LD3_LANE_FUNC (uint32x4x3_t, uint32x4_t, uint32_t, v4si, si, u32)
++__LD3_LANE_FUNC (uint64x2x3_t, uint64x2_t, uint64_t, v2di, di, u64)
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vld1q_dup_s32 (const int32_t* __a)
+-{
+-  return vdupq_n_s32 (*__a);
+-}
++#undef __LD3_LANE_FUNC
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vld1q_dup_s64 (const int64_t* __a)
+-{
+-  return vdupq_n_s64 (*__a);
+-}
++/* vld4_lane */
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vld1q_dup_u8 (const uint8_t* __a)
+-{
+-  return vdupq_n_u8 (*__a);
++#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
++			 qmode, ptrmode, funcsuffix, signedtype)	   \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
++{									   \
++  __builtin_aarch64_simd_xi __o;					   \
++  largetype __temp;							   \
++  __temp.val[0] =							   \
++    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
++  __temp.val[1] =							   \
++    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
++  __temp.val[2] =							   \
++    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
++  __temp.val[3] =							   \
++    vcombine_##funcsuffix (__b.val[3], vcreate_##funcsuffix (0));	   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[0],	   \
++					    0);				   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[1],	   \
++					    1);				   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[2],	   \
++					    2);				   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[3],	   \
++					    3);				   \
++  __o =	__builtin_aarch64_ld4_lane##mode (				   \
++	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
++  __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0);	   \
++  __b.val[1] = (vectype) __builtin_aarch64_get_dregxidi (__o, 1);	   \
++  __b.val[2] = (vectype) __builtin_aarch64_get_dregxidi (__o, 2);	   \
++  __b.val[3] = (vectype) __builtin_aarch64_get_dregxidi (__o, 3);	   \
++  return __b;								   \
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_u16 (const uint16_t* __a)
+-{
+-  return vdupq_n_u16 (*__a);
+-}
++/* vld4q_lane */
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vld1q_dup_u32 (const uint32_t* __a)
+-{
+-  return vdupq_n_u32 (*__a);
+-}
++__LD4_LANE_FUNC (float16x4x4_t, float16x4_t, float16x8x4_t, float16_t, v4hf,
++		 v8hf, hf, f16, float16x8_t)
++__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v2sf, v4sf,
++		 sf, f32, float32x4_t)
++__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, df, v2df,
++		 df, f64, float64x2_t)
++__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi,
++		 p16, int16x8_t)
++__LD4_LANE_FUNC (poly64x1x4_t, poly64x1_t, poly64x2x4_t, poly64_t, di,
++		 v2di_ssps, di, p64, poly64x2_t)
++__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi,
++		 u16, int16x8_t)
++__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v2si, v4si, si,
++		 u32, int32x4_t)
++__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, di, v2di, di,
++		 u64, int64x2_t)
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vld1q_dup_u64 (const uint64_t* __a)
+-{
+-  return vdupq_n_u64 (*__a);
+-}
++#undef __LD4_LANE_FUNC
+ 
+-/* vld1_lane  */
++/* vld4q_lane */
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_f16 (const float16_t *__src, float16x4_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++#define __LD4_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld4q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
++{									   \
++  __builtin_aarch64_simd_xi __o;					   \
++  intype ret;								   \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[0], 0); \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[1], 1); \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[2], 2); \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[3], 3); \
++  __o = __builtin_aarch64_ld4_lane##mode (				   \
++	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
++  ret.val[0] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 0);	   \
++  ret.val[1] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 1);	   \
++  ret.val[2] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 2);	   \
++  ret.val[3] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 3);	   \
++  return ret;								   \
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vld1_lane_f32 (const float32_t *__src, float32x2_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+-}
++__LD4_LANE_FUNC (float16x8x4_t, float16x8_t, float16_t, v8hf, hf, f16)
++__LD4_LANE_FUNC (float32x4x4_t, float32x4_t, float32_t, v4sf, sf, f32)
++__LD4_LANE_FUNC (float64x2x4_t, float64x2_t, float64_t, v2df, df, f64)
++__LD4_LANE_FUNC (poly8x16x4_t, poly8x16_t, poly8_t, v16qi, qi, p8)
++__LD4_LANE_FUNC (poly16x8x4_t, poly16x8_t, poly16_t, v8hi, hi, p16)
++__LD4_LANE_FUNC (poly64x2x4_t, poly64x2_t, poly64_t, v2di, di, p64)
++__LD4_LANE_FUNC (int8x16x4_t, int8x16_t, int8_t, v16qi, qi, s8)
++__LD4_LANE_FUNC (int16x8x4_t, int16x8_t, int16_t, v8hi, hi, s16)
++__LD4_LANE_FUNC (int32x4x4_t, int32x4_t, int32_t, v4si, si, s32)
++__LD4_LANE_FUNC (int64x2x4_t, int64x2_t, int64_t, v2di, di, s64)
++__LD4_LANE_FUNC (uint8x16x4_t, uint8x16_t, uint8_t, v16qi, qi, u8)
++__LD4_LANE_FUNC (uint16x8x4_t, uint16x8_t, uint16_t, v8hi, hi, u16)
++__LD4_LANE_FUNC (uint32x4x4_t, uint32x4_t, uint32_t, v4si, si, u32)
++__LD4_LANE_FUNC (uint64x2x4_t, uint64x2_t, uint64_t, v2di, di, u64)
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vld1_lane_f64 (const float64_t *__src, float64x1_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+-}
++#undef __LD4_LANE_FUNC
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vld1_lane_p8 (const poly8_t *__src, poly8x8_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+-}
++/* vmax */
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_p16 (const poly16_t *__src, poly16x4_t __vec, const int __lane)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smax_nanv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vld1_lane_s8 (const int8_t *__src, int8x8_t __vec, const int __lane)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++    return (float64x1_t)
++      { __builtin_aarch64_smax_nandf (vget_lane_f64 (__a, 0),
++				      vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_s16 (const int16_t *__src, int16x4_t __vec, const int __lane)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vld1_lane_s32 (const int32_t *__src, int32x2_t __vec, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vld1_lane_s64 (const int64_t *__src, int64x1_t __vec, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vld1_lane_u8 (const uint8_t *__src, uint8x8_t __vec, const int __lane)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint8x8_t) __builtin_aarch64_umaxv8qi ((int8x8_t) __a,
++						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_u16 (const uint16_t *__src, uint16x4_t __vec, const int __lane)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint16x4_t) __builtin_aarch64_umaxv4hi ((int16x4_t) __a,
++						  (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vld1_lane_u32 (const uint32_t *__src, uint32x2_t __vec, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint32x2_t) __builtin_aarch64_umaxv2si ((int32x2_t) __a,
++						  (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vld1_lane_u64 (const uint64_t *__src, uint64x1_t __vec, const int __lane)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smax_nanv4sf (__a, __b);
+ }
+ 
+-/* vld1q_lane  */
+-
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_f16 (const float16_t *__src, float16x8_t __vec, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smax_nanv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vld1q_lane_f32 (const float32_t *__src, float32x4_t __vec, const int __lane)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vld1q_lane_f64 (const float64_t *__src, float64x2_t __vec, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vld1q_lane_p8 (const poly8_t *__src, poly8x16_t __vec, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_p16 (const poly16_t *__src, poly16x8_t __vec, const int __lane)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint8x16_t) __builtin_aarch64_umaxv16qi ((int8x16_t) __a,
++						   (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vld1q_lane_s8 (const int8_t *__src, int8x16_t __vec, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint16x8_t) __builtin_aarch64_umaxv8hi ((int16x8_t) __a,
++						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_s16 (const int16_t *__src, int16x8_t __vec, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint32x4_t) __builtin_aarch64_umaxv4si ((int32x4_t) __a,
++						  (int32x4_t) __b);
+ }
++/* vmulx */
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vld1q_lane_s32 (const int32_t *__src, int32x4_t __vec, const int __lane)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vld1q_lane_s64 (const int64_t *__src, int64x2_t __vec, const int __lane)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vld1q_lane_u8 (const uint8_t *__src, uint8x16_t __vec, const int __lane)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (float64x1_t) {__builtin_aarch64_fmulxdf (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_u16 (const uint16_t *__src, uint16x8_t __vec, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vld1q_lane_u32 (const uint32_t *__src, uint32x4_t __vec, const int __lane)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxs_f32 (float32_t __a, float32_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxsf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vld1q_lane_u64 (const uint64_t *__src, uint64x2_t __vec, const int __lane)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxd_f64 (float64_t __a, float64_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxdf (__a, __b);
+ }
+ 
+-/* vldn */
+-
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
+-vld2_s64 (const int64_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_lane_f32 (float32x2_t __a, float32x2_t __v, const int __lane)
+ {
+-  int64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return vmulx_f32 (__a, __aarch64_vdup_lane_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
+-vld2_u64 (const uint64_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_lane_f64 (float64x1_t __a, float64x1_t __v, const int __lane)
+ {
+-  uint64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return vmulx_f64 (__a, __aarch64_vdup_lane_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline float64x1x2_t __attribute__ ((__always_inline__))
+-vld2_f64 (const float64_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_lane_f32 (float32x4_t __a, float32x2_t __v, const int __lane)
+ {
+-  float64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
+-  return ret;
++  return vmulxq_f32 (__a, __aarch64_vdupq_lane_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
+-vld2_s8 (const int8_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_lane_f64 (float64x2_t __a, float64x1_t __v, const int __lane)
+ {
+-  int8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return vmulxq_f64 (__a, __aarch64_vdupq_lane_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
+-vld2_p8 (const poly8_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_laneq_f32 (float32x2_t __a, float32x4_t __v, const int __lane)
+ {
+-  poly8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return vmulx_f32 (__a, __aarch64_vdup_laneq_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
+-vld2_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_laneq_f64 (float64x1_t __a, float64x2_t __v, const int __lane)
+ {
+-  int16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return vmulx_f64 (__a, __aarch64_vdup_laneq_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
+-vld2_p16 (const poly16_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_laneq_f32 (float32x4_t __a, float32x4_t __v, const int __lane)
+ {
+-  poly16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return vmulxq_f32 (__a, __aarch64_vdupq_laneq_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
+-vld2_s32 (const int32_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_laneq_f64 (float64x2_t __a, float64x2_t __v, const int __lane)
+ {
+-  int32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return vmulxq_f64 (__a, __aarch64_vdupq_laneq_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
+-vld2_u8 (const uint8_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxs_lane_f32 (float32_t __a, float32x2_t __v, const int __lane)
+ {
+-  uint8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
+-vld2_u16 (const uint16_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxs_laneq_f32 (float32_t __a, float32x4_t __v, const int __lane)
+ {
+-  uint16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
+-vld2_u32 (const uint32_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxd_lane_f64 (float64_t __a, float64x1_t __v, const int __lane)
+ {
+-  uint32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
+-vld2_f16 (const float16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxd_laneq_f64 (float64_t __a, float64x2_t __v, const int __lane)
+ {
+-  float16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_dregoiv4hf (__o, 1);
+-  return ret;
++  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
+-vld2_f32 (const float32_t * __a)
++/* vpmax  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_s8 (int8x8_t a, int8x8_t b)
+ {
+-  float32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv8qi (a, b);
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_s8 (const int8_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_s16 (int16x4_t a, int16x4_t b)
+ {
+-  int8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv4hi (a, b);
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_p8 (const poly8_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_s32 (int32x2_t a, int32x2_t b)
+ {
+-  poly8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv2si (a, b);
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_s16 (const int16_t * __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_u8 (uint8x8_t a, uint8x8_t b)
+ {
+-  int16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return (uint8x8_t) __builtin_aarch64_umaxpv8qi ((int8x8_t) a,
++						  (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_p16 (const poly16_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_u16 (uint16x4_t a, uint16x4_t b)
+ {
+-  poly16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return (uint16x4_t) __builtin_aarch64_umaxpv4hi ((int16x4_t) a,
++						   (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_s32 (const int32_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  int32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return (uint32x2_t) __builtin_aarch64_umaxpv2si ((int32x2_t) a,
++						   (int32x2_t) b);
+ }
+ 
+-__extension__ static __inline int64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_s64 (const int64_t * __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  int64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv16qi (a, b);
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_u8 (const uint8_t * __a)
+-{
+-  uint8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_s16 (int16x8_t a, int16x8_t b)
++{
++  return __builtin_aarch64_smaxpv8hi (a, b);
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_u16 (const uint16_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_s32 (int32x4_t a, int32x4_t b)
+ {
+-  uint16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv4si (a, b);
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_u32 (const uint32_t * __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  uint32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return (uint8x16_t) __builtin_aarch64_umaxpv16qi ((int8x16_t) a,
++						    (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline uint64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_u64 (const uint64_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_u16 (uint16x8_t a, uint16x8_t b)
+ {
+-  uint64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return (uint16x8_t) __builtin_aarch64_umaxpv8hi ((int16x8_t) a,
++						   (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_f16 (const float16_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  float16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_qregoiv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
+-  return ret;
++  return (uint32x4_t) __builtin_aarch64_umaxpv4si ((int32x4_t) a,
++						   (int32x4_t) b);
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_f32 (const float32_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_f32 (float32x2_t a, float32x2_t b)
+ {
+-  float32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smax_nanpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline float64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_f64 (const float64_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  float64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smax_nanpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
+-vld3_s64 (const int64_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  int64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smax_nanpv2df (a, b);
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
+-vld3_u64 (const uint64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxqd_f64 (float64x2_t a)
+ {
+-  uint64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline float64x1x3_t __attribute__ ((__always_inline__))
+-vld3_f64 (const float64_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxs_f32 (float32x2_t a)
+ {
+-  float64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
+-vld3_s8 (const int8_t * __a)
++/* vpmaxnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnm_f32 (float32x2_t a, float32x2_t b)
+ {
+-  int8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smaxpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
+-vld3_p8 (const poly8_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  poly8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smaxpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
+-vld3_s16 (const int16_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  int16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smaxpv2df (a, b);
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
+-vld3_p16 (const poly16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmqd_f64 (float64x2_t a)
+ {
+-  poly16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
+-vld3_s32 (const int32_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnms_f32 (float32x2_t a)
+ {
+-  int32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
+-vld3_u8 (const uint8_t * __a)
++/* vpmin  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_s8 (int8x8_t a, int8x8_t b)
+ {
+-  uint8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv8qi (a, b);
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
+-vld3_u16 (const uint16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_s16 (int16x4_t a, int16x4_t b)
+ {
+-  uint16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv4hi (a, b);
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
+-vld3_u32 (const uint32_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_s32 (int32x2_t a, int32x2_t b)
+ {
+-  uint32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv2si (a, b);
+ }
+ 
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
+-vld3_f16 (const float16_t * __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_u8 (uint8x8_t a, uint8x8_t b)
+ {
+-  float16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_dregciv4hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_dregciv4hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_dregciv4hf (__o, 2);
+-  return ret;
++  return (uint8x8_t) __builtin_aarch64_uminpv8qi ((int8x8_t) a,
++						  (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
+-vld3_f32 (const float32_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_u16 (uint16x4_t a, uint16x4_t b)
+ {
+-  float32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
+-  return ret;
++  return (uint16x4_t) __builtin_aarch64_uminpv4hi ((int16x4_t) a,
++						   (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_s8 (const int8_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  int8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (uint32x2_t) __builtin_aarch64_uminpv2si ((int32x2_t) a,
++						   (int32x2_t) b);
+ }
+ 
+-__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_p8 (const poly8_t * __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  poly8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv16qi (a, b);
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_s16 (const int16_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_s16 (int16x8_t a, int16x8_t b)
+ {
+-  int16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv8hi (a, b);
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_p16 (const poly16_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_s32 (int32x4_t a, int32x4_t b)
+ {
+-  poly16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv4si (a, b);
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_s32 (const int32_t * __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  int32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return (uint8x16_t) __builtin_aarch64_uminpv16qi ((int8x16_t) a,
++						    (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline int64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_s64 (const int64_t * __a)
+-{
+-  int64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_u16 (uint16x8_t a, uint16x8_t b)
++{
++  return (uint16x8_t) __builtin_aarch64_uminpv8hi ((int16x8_t) a,
++						   (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_u8 (const uint8_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  uint8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (uint32x4_t) __builtin_aarch64_uminpv4si ((int32x4_t) a,
++						   (int32x4_t) b);
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_u16 (const uint16_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_f32 (float32x2_t a, float32x2_t b)
+ {
+-  uint16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smin_nanpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_u32 (const uint32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  uint32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smin_nanpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline uint64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_u64 (const uint64_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  uint64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smin_nanpv2df (a, b);
+ }
+ 
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_f16 (const float16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminqd_f64 (float64x2_t a)
+ {
+-  float16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_qregciv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregciv8hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_qregciv8hf (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_f32 (const float32_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmins_f32 (float32x2_t a)
+ {
+-  float32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline float64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_f64 (const float64_t * __a)
++/* vpminnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnm_f32 (float32x2_t a, float32x2_t b)
+ {
+-  float64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
+-vld4_s64 (const int64_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  int64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_sminpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
+-vld4_u64 (const uint64_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  uint64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_sminpv2df (a, b);
+ }
+ 
+-__extension__ static __inline float64x1x4_t __attribute__ ((__always_inline__))
+-vld4_f64 (const float64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmqd_f64 (float64x2_t a)
+ {
+-  float64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
+-  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
+-vld4_s8 (const int8_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnms_f32 (float32x2_t a)
+ {
+-  int8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
+-vld4_p8 (const poly8_t * __a)
++/* vmaxnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  poly8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_fmaxv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
+-vld4_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return (float64x1_t)
++    { __builtin_aarch64_fmaxdf (vget_lane_f64 (__a, 0),
++				vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
+-vld4_p16 (const poly16_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  poly16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_fmaxv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
+-vld4_s32 (const int32_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  int32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_fmaxv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
+-vld4_u8 (const uint8_t * __a)
++/* vmaxv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_f32 (float32x2_t __a)
+ {
+-  uint8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
+-vld4_u16 (const uint16_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_s8 (int8x8_t __a)
+ {
+-  uint16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v8qi (__a);
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
+-vld4_u32 (const uint32_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_s16 (int16x4_t __a)
+ {
+-  uint32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v4hi (__a);
+ }
+ 
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
+-vld4_f16 (const float16_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_s32 (int32x2_t __a)
+ {
+-  float16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_dregxiv4hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_dregxiv4hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_dregxiv4hf (__o, 2);
+-  ret.val[3] = __builtin_aarch64_get_dregxiv4hf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
+-vld4_f32 (const float32_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_u8 (uint8x8_t __a)
+ {
+-  float32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
+-  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v8qi_uu (__a);
+ }
+ 
+-__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_s8 (const int8_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_u16 (uint16x4_t __a)
+ {
+-  int8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v4hi_uu (__a);
+ }
+ 
+-__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_p8 (const poly8_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_u32 (uint32x2_t __a)
+ {
+-  poly8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v2si_uu (__a);
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_s16 (const int16_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_f32 (float32x4_t __a)
+ {
+-  int16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_p16 (const poly16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_f64 (float64x2_t __a)
+ {
+-  poly16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_s32 (const int32_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_s8 (int8x16_t __a)
+ {
+-  int32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v16qi (__a);
+ }
+ 
+-__extension__ static __inline int64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_s64 (const int64_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_s16 (int16x8_t __a)
+ {
+-  int64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v8hi (__a);
+ }
+ 
+-__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_u8 (const uint8_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_s32 (int32x4_t __a)
+ {
+-  uint8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v4si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_u16 (const uint16_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_u8 (uint8x16_t __a)
+ {
+-  uint16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v16qi_uu (__a);
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_u32 (const uint32_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_u16 (uint16x8_t __a)
+ {
+-  uint32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v8hi_uu (__a);
+ }
+ 
+-__extension__ static __inline uint64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_u64 (const uint64_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_u32 (uint32x4_t __a)
+ {
+-  uint64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v4si_uu (__a);
+ }
+ 
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_f16 (const float16_t * __a)
++/* vmaxnmv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmv_f32 (float32x2_t __a)
+ {
+-  float16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_qregxiv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregxiv8hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_qregxiv8hf (__o, 2);
+-  ret.val[3] = __builtin_aarch64_get_qregxiv8hf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_f32 (const float32_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmvq_f32 (float32x4_t __a)
+ {
+-  float32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
+-  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline float64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_f64 (const float64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmvq_f64 (float64x2_t __a)
+ {
+-  float64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
+-  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2df (__a);
+ }
+ 
+-/* vldn_dup */
++/* vmin  */
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s8 (const int8_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  int8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smin_nanv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++    return (float64x1_t)
++	  { __builtin_aarch64_smin_nandf (vget_lane_f64 (__a, 0),
++					  vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s32 (const int32_t * __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  int32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_f16 (const float16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  float16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
+-  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregoiv4hf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
+-vld2_dup_f32 (const float32_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  float32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1x2_t __attribute__ ((__always_inline__))
+-vld2_dup_f64 (const float64_t * __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  float64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rdf ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
+-  return ret;
++  return (uint8x8_t) __builtin_aarch64_uminv8qi ((int8x8_t) __a,
++						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  uint8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return (uint16x4_t) __builtin_aarch64_uminv4hi ((int16x4_t) __a,
++						  (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return (uint32x2_t) __builtin_aarch64_uminv2si ((int32x2_t) __a,
++						  (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smin_nanv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
+-vld2_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  poly8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smin_nanv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  poly16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s64 (const int64_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  uint64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s8 (const int8_t * __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  int8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return (uint8x16_t) __builtin_aarch64_uminv16qi ((int8x16_t) __a,
++						   (int8x16_t) __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_u16 (uint16x8_t __a, uint16x8_t __b)
++{
++  return (uint16x8_t) __builtin_aarch64_uminv8hi ((int16x8_t) __a,
++						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_u32 (uint32x4_t __a, uint32x4_t __b)
++{
++  return (uint32x4_t) __builtin_aarch64_uminv4si ((int32x4_t) __a,
++						  (int32x4_t) __b);
++}
++
++/* vminnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  poly8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_fminv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return (float64x1_t)
++    { __builtin_aarch64_fmindf (vget_lane_f64 (__a, 0),
++				vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  poly16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_fminv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s32 (const int32_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  int32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_fminv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s64 (const int64_t * __a)
++/* vminv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_f32 (float32x2_t __a)
+ {
+-  int64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_s8 (int8x8_t __a)
+ {
+-  uint8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v8qi (__a);
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_s16 (int16x4_t __a)
+ {
+-  uint16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v4hi (__a);
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_s32 (int32x2_t __a)
+ {
+-  uint32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_u8 (uint8x8_t __a)
+ {
+-  uint64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v8qi_uu (__a);
+ }
+ 
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_f16 (const float16_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_u16 (uint16x4_t __a)
+ {
+-  float16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregoiv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v4hi_uu (__a);
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_f32 (const float32_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_u32 (uint32x2_t __a)
+ {
+-  float32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v2si_uu (__a);
+ }
+ 
+-__extension__ static __inline float64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_f64 (const float64_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_f32 (float32x4_t __a)
+ {
+-  float64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s64 (const int64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_f64 (float64x2_t __a)
+ {
+-  int64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_s8 (int8x16_t __a)
+ {
+-  uint64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v16qi (__a);
+ }
+ 
+-__extension__ static __inline float64x1x3_t __attribute__ ((__always_inline__))
+-vld3_dup_f64 (const float64_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_s16 (int16x8_t __a)
+ {
+-  float64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rdf ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v8hi (__a);
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s8 (const int8_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_s32 (int32x4_t __a)
+ {
+-  int8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v4si (__a);
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
+-vld3_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_u8 (uint8x16_t __a)
+ {
+-  poly8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v16qi_uu (__a);
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s16 (const int16_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_u16 (uint16x8_t __a)
+ {
+-  int16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v8hi_uu (__a);
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_u32 (uint32x4_t __a)
+ {
+-  poly16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v4si_uu (__a);
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s32 (const int32_t * __a)
++/* vminnmv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmv_f32 (float32x2_t __a)
+ {
+-  int32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmvq_f32 (float32x4_t __a)
+ {
+-  uint8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmvq_f64 (float64x2_t __a)
+ {
+-  uint16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u32 (const uint32_t * __a)
++/* vmla */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
+ {
+-  uint32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return a + b * c;
+ }
+ 
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_f16 (const float16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  float16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 0);
+-  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 1);
+-  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 2);
+-  return ret;
++  return __a + __b * __c;
+ }
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
+-vld3_dup_f32 (const float32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
+ {
+-  float32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
+-  return ret;
++  return a + b * c;
+ }
+ 
+-__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s8 (const int8_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
+ {
+-  int8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return a + b * c;
+ }
+ 
+-__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_p8 (const poly8_t * __a)
++/* vmla_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  poly8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s16 (const int16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_s16 (int16x4_t __a, int16x4_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  int16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_s32 (int32x2_t __a, int32x2_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  poly16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s32 (const int32_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  int32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s64 (const int64_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b,
++	       uint32x2_t __c, const int __lane)
+ {
+-  int64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u8 (const uint8_t * __a)
++/* vmla_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	        float32x4_t __c, const int __lane)
+ {
+-  uint8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_s16 (int16x4_t __a, int16x4_t __b,
++		int16x8_t __c, const int __lane)
+ {
+-  uint16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_s32 (int32x2_t __a, int32x2_t __b,
++		int32x4_t __c, const int __lane)
+ {
+-  uint32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x8_t __c, const int __lane)
+ {
+-  uint64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_f16 (const float16_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
++		uint32x4_t __c, const int __lane)
+ {
+-  float16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 0);
+-  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 1);
+-  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_f32 (const float32_t * __a)
++/* vmlaq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b,
++		float32x2_t __c, const int __lane)
+ {
+-  float32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_f64 (const float64_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  float64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s64 (const int64_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  int64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  uint64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float64x1x4_t __attribute__ ((__always_inline__))
+-vld4_dup_f64 (const float64_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x2_t __c, const int __lane)
+ {
+-  float64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rdf ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
+-  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s8 (const int8_t * __a)
++  /* vmlaq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++		 float32x4_t __c, const int __lane)
+ {
+-  int8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
+-vld4_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_s16 (int16x8_t __a, int16x8_t __b,
++		int16x8_t __c, const int __lane)
+ {
+-  poly8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s16 (const int16_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_s32 (int32x4_t __a, int32x4_t __b,
++		int32x4_t __c, const int __lane)
+ {
+-  int16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x8_t __c, const int __lane)
+ {
+-  poly16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s32 (const int32_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x4_t __c, const int __lane)
+ {
+-  int32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u8 (const uint8_t * __a)
++/* vmls  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
+ {
+-  uint8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return a - b * c;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  uint16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return __a - __b * __c;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
+ {
+-  uint32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return a - b * c;
+ }
+ 
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_f16 (const float16_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
+ {
+-  float16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 0);
+-  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 1);
+-  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 2);
+-  ret.val[3] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 3);
+-  return ret;
++  return a - b * c;
+ }
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
+-vld4_dup_f32 (const float32_t * __a)
++/* vmls_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  float32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
+-  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s8 (const int8_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_s16 (int16x4_t __a, int16x4_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  int8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_s32 (int32x2_t __a, int32x2_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  poly8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s16 (const int16_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  int16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b,
++	       uint32x2_t __c, const int __lane)
+ {
+-  poly16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s32 (const int32_t * __a)
++/* vmls_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x4_t __c, const int __lane)
+ {
+-  int32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s64 (const int64_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_s16 (int16x4_t __a, int16x4_t __b,
++		int16x8_t __c, const int __lane)
+ {
+-  int64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_s32 (int32x2_t __a, int32x2_t __b,
++		int32x4_t __c, const int __lane)
+ {
+-  uint8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x8_t __c, const int __lane)
+ {
+-  uint16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
++		uint32x4_t __c, const int __lane)
+ {
+-  uint32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u64 (const uint64_t * __a)
++/* vmlsq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b,
++		float32x2_t __c, const int __lane)
+ {
+-  uint64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_f16 (const float16_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  float16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 0);
+-  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 1);
+-  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 2);
+-  ret.val[3] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_f32 (const float32_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  float32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
+-  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_f64 (const float64_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  float64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
+-  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-/* vld2_lane */
+-
+-#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+-			 qmode, ptrmode, funcsuffix, signedtype)	   \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
+-{									   \
+-  __builtin_aarch64_simd_oi __o;					   \
+-  largetype __temp;							   \
+-  __temp.val[0] =							   \
+-    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
+-  __temp.val[1] =							   \
+-    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
+-					    (signedtype) __temp.val[0],	   \
+-					    0);				   \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
+-					    (signedtype) __temp.val[1],	   \
+-					    1);				   \
+-  __o =	__builtin_aarch64_ld2_lane##mode (				   \
+-	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
+-  __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0);	   \
+-  __b.val[1] = (vectype) __builtin_aarch64_get_dregoidi (__o, 1);	   \
+-  return __b;								   \
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x2_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__LD2_LANE_FUNC (float16x4x2_t, float16x4_t, float16x8x2_t, float16_t, v4hf,
+-		 v8hf, hf, f16, float16x8_t)
+-__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v2sf, v4sf,
+-		 sf, f32, float32x4_t)
+-__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, df, v2df,
+-		 df, f64, float64x2_t)
+-__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi,
+-		 p16, int16x8_t)
+-__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi,
+-		 u16, int16x8_t)
+-__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si,
+-		 u32, int32x4_t)
+-__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, di, v2di, di,
+-		 u64, int64x2_t)
++  /* vmlsq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++		float32x4_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
+ 
+-#undef __LD2_LANE_FUNC
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_s16 (int16x8_t __a, int16x8_t __b,
++		int16x8_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
+ 
+-/* vld2q_lane */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_s32 (int32x4_t __a, int32x4_t __b,
++		int32x4_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x8_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
+ 
+-#define __LD2_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld2q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
+-{									   \
+-  __builtin_aarch64_simd_oi __o;					   \
+-  intype ret;								   \
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[1], 1); \
+-  __o = __builtin_aarch64_ld2_lane##mode (				   \
+-	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
+-  ret.val[0] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 0);	   \
+-  ret.val[1] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 1);	   \
+-  return ret;								   \
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x4_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__LD2_LANE_FUNC (float16x8x2_t, float16x8_t, float16_t, v8hf, hf, f16)
+-__LD2_LANE_FUNC (float32x4x2_t, float32x4_t, float32_t, v4sf, sf, f32)
+-__LD2_LANE_FUNC (float64x2x2_t, float64x2_t, float64_t, v2df, df, f64)
+-__LD2_LANE_FUNC (poly8x16x2_t, poly8x16_t, poly8_t, v16qi, qi, p8)
+-__LD2_LANE_FUNC (poly16x8x2_t, poly16x8_t, poly16_t, v8hi, hi, p16)
+-__LD2_LANE_FUNC (int8x16x2_t, int8x16_t, int8_t, v16qi, qi, s8)
+-__LD2_LANE_FUNC (int16x8x2_t, int16x8_t, int16_t, v8hi, hi, s16)
+-__LD2_LANE_FUNC (int32x4x2_t, int32x4_t, int32_t, v4si, si, s32)
+-__LD2_LANE_FUNC (int64x2x2_t, int64x2_t, int64_t, v2di, di, s64)
+-__LD2_LANE_FUNC (uint8x16x2_t, uint8x16_t, uint8_t, v16qi, qi, u8)
+-__LD2_LANE_FUNC (uint16x8x2_t, uint16x8_t, uint16_t, v8hi, hi, u16)
+-__LD2_LANE_FUNC (uint32x4x2_t, uint32x4_t, uint32_t, v4si, si, u32)
+-__LD2_LANE_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, v2di, di, u64)
++/* vmov_n_  */
+ 
+-#undef __LD2_LANE_FUNC
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f16 (float16_t __a)
++{
++  return vdup_n_f16 (__a);
++}
+ 
+-/* vld3_lane */
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f32 (float32_t __a)
++{
++  return vdup_n_f32 (__a);
++}
+ 
+-#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+-			 qmode, ptrmode, funcsuffix, signedtype)	   \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
+-{									   \
+-  __builtin_aarch64_simd_ci __o;					   \
+-  largetype __temp;							   \
+-  __temp.val[0] =							   \
+-    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
+-  __temp.val[1] =							   \
+-    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
+-  __temp.val[2] =							   \
+-    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+-					    (signedtype) __temp.val[0],	   \
+-					    0);				   \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+-					    (signedtype) __temp.val[1],	   \
+-					    1);				   \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+-					    (signedtype) __temp.val[2],	   \
+-					    2);				   \
+-  __o =	__builtin_aarch64_ld3_lane##mode (				   \
+-	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
+-  __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0);	   \
+-  __b.val[1] = (vectype) __builtin_aarch64_get_dregcidi (__o, 1);	   \
+-  __b.val[2] = (vectype) __builtin_aarch64_get_dregcidi (__o, 2);	   \
+-  return __b;								   \
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f64 (float64_t __a)
++{
++  return (float64x1_t) {__a};
+ }
+ 
+-__LD3_LANE_FUNC (float16x4x3_t, float16x4_t, float16x8x3_t, float16_t, v4hf,
+-		 v8hf, hf, f16, float16x8_t)
+-__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v2sf, v4sf,
+-		 sf, f32, float32x4_t)
+-__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, df, v2df,
+-		 df, f64, float64x2_t)
+-__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi,
+-		 p16, int16x8_t)
+-__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi,
+-		 u16, int16x8_t)
+-__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v2si, v4si, si,
+-		 u32, int32x4_t)
+-__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, di, v2di, di,
+-		 u64, int64x2_t)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_p8 (poly8_t __a)
++{
++  return vdup_n_p8 (__a);
++}
+ 
+-#undef __LD3_LANE_FUNC
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_p16 (poly16_t __a)
++{
++  return vdup_n_p16 (__a);
++}
+ 
+-/* vld3q_lane */
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_p64 (poly64_t __a)
++{
++  return vdup_n_p64 (__a);
++}
+ 
+-#define __LD3_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld3q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
+-{									   \
+-  __builtin_aarch64_simd_ci __o;					   \
+-  intype ret;								   \
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[2], 2); \
+-  __o = __builtin_aarch64_ld3_lane##mode (				   \
+-	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
+-  ret.val[0] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 0);	   \
+-  ret.val[1] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 1);	   \
+-  ret.val[2] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 2);	   \
+-  return ret;								   \
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s8 (int8_t __a)
++{
++  return vdup_n_s8 (__a);
+ }
+ 
+-__LD3_LANE_FUNC (float16x8x3_t, float16x8_t, float16_t, v8hf, hf, f16)
+-__LD3_LANE_FUNC (float32x4x3_t, float32x4_t, float32_t, v4sf, sf, f32)
+-__LD3_LANE_FUNC (float64x2x3_t, float64x2_t, float64_t, v2df, df, f64)
+-__LD3_LANE_FUNC (poly8x16x3_t, poly8x16_t, poly8_t, v16qi, qi, p8)
+-__LD3_LANE_FUNC (poly16x8x3_t, poly16x8_t, poly16_t, v8hi, hi, p16)
+-__LD3_LANE_FUNC (int8x16x3_t, int8x16_t, int8_t, v16qi, qi, s8)
+-__LD3_LANE_FUNC (int16x8x3_t, int16x8_t, int16_t, v8hi, hi, s16)
+-__LD3_LANE_FUNC (int32x4x3_t, int32x4_t, int32_t, v4si, si, s32)
+-__LD3_LANE_FUNC (int64x2x3_t, int64x2_t, int64_t, v2di, di, s64)
+-__LD3_LANE_FUNC (uint8x16x3_t, uint8x16_t, uint8_t, v16qi, qi, u8)
+-__LD3_LANE_FUNC (uint16x8x3_t, uint16x8_t, uint16_t, v8hi, hi, u16)
+-__LD3_LANE_FUNC (uint32x4x3_t, uint32x4_t, uint32_t, v4si, si, u32)
+-__LD3_LANE_FUNC (uint64x2x3_t, uint64x2_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s16 (int16_t __a)
++{
++  return vdup_n_s16 (__a);
++}
+ 
+-#undef __LD3_LANE_FUNC
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s32 (int32_t __a)
++{
++  return vdup_n_s32 (__a);
++}
+ 
+-/* vld4_lane */
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s64 (int64_t __a)
++{
++  return (int64x1_t) {__a};
++}
+ 
+-#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+-			 qmode, ptrmode, funcsuffix, signedtype)	   \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
+-{									   \
+-  __builtin_aarch64_simd_xi __o;					   \
+-  largetype __temp;							   \
+-  __temp.val[0] =							   \
+-    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
+-  __temp.val[1] =							   \
+-    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
+-  __temp.val[2] =							   \
+-    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
+-  __temp.val[3] =							   \
+-    vcombine_##funcsuffix (__b.val[3], vcreate_##funcsuffix (0));	   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[0],	   \
+-					    0);				   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[1],	   \
+-					    1);				   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[2],	   \
+-					    2);				   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[3],	   \
+-					    3);				   \
+-  __o =	__builtin_aarch64_ld4_lane##mode (				   \
+-	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
+-  __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0);	   \
+-  __b.val[1] = (vectype) __builtin_aarch64_get_dregxidi (__o, 1);	   \
+-  __b.val[2] = (vectype) __builtin_aarch64_get_dregxidi (__o, 2);	   \
+-  __b.val[3] = (vectype) __builtin_aarch64_get_dregxidi (__o, 3);	   \
+-  return __b;								   \
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u8 (uint8_t __a)
++{
++  return vdup_n_u8 (__a);
+ }
+ 
+-/* vld4q_lane */
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u16 (uint16_t __a)
++{
++    return vdup_n_u16 (__a);
++}
+ 
+-__LD4_LANE_FUNC (float16x4x4_t, float16x4_t, float16x8x4_t, float16_t, v4hf,
+-		 v8hf, hf, f16, float16x8_t)
+-__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v2sf, v4sf,
+-		 sf, f32, float32x4_t)
+-__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, df, v2df,
+-		 df, f64, float64x2_t)
+-__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi,
+-		 p16, int16x8_t)
+-__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi,
+-		 u16, int16x8_t)
+-__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v2si, v4si, si,
+-		 u32, int32x4_t)
+-__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, di, v2di, di,
+-		 u64, int64x2_t)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u32 (uint32_t __a)
++{
++   return vdup_n_u32 (__a);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u64 (uint64_t __a)
++{
++  return (uint64x1_t) {__a};
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f16 (float16_t __a)
++{
++  return vdupq_n_f16 (__a);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f32 (float32_t __a)
++{
++  return vdupq_n_f32 (__a);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f64 (float64_t __a)
++{
++  return vdupq_n_f64 (__a);
++}
+ 
+-#undef __LD4_LANE_FUNC
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_p8 (poly8_t __a)
++{
++  return vdupq_n_p8 (__a);
++}
+ 
+-/* vld4q_lane */
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_p16 (poly16_t __a)
++{
++  return vdupq_n_p16 (__a);
++}
+ 
+-#define __LD4_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld4q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
+-{									   \
+-  __builtin_aarch64_simd_xi __o;					   \
+-  intype ret;								   \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[2], 2); \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[3], 3); \
+-  __o = __builtin_aarch64_ld4_lane##mode (				   \
+-	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
+-  ret.val[0] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 0);	   \
+-  ret.val[1] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 1);	   \
+-  ret.val[2] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 2);	   \
+-  ret.val[3] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 3);	   \
+-  return ret;								   \
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_p64 (poly64_t __a)
++{
++  return vdupq_n_p64 (__a);
+ }
+ 
+-__LD4_LANE_FUNC (float16x8x4_t, float16x8_t, float16_t, v8hf, hf, f16)
+-__LD4_LANE_FUNC (float32x4x4_t, float32x4_t, float32_t, v4sf, sf, f32)
+-__LD4_LANE_FUNC (float64x2x4_t, float64x2_t, float64_t, v2df, df, f64)
+-__LD4_LANE_FUNC (poly8x16x4_t, poly8x16_t, poly8_t, v16qi, qi, p8)
+-__LD4_LANE_FUNC (poly16x8x4_t, poly16x8_t, poly16_t, v8hi, hi, p16)
+-__LD4_LANE_FUNC (int8x16x4_t, int8x16_t, int8_t, v16qi, qi, s8)
+-__LD4_LANE_FUNC (int16x8x4_t, int16x8_t, int16_t, v8hi, hi, s16)
+-__LD4_LANE_FUNC (int32x4x4_t, int32x4_t, int32_t, v4si, si, s32)
+-__LD4_LANE_FUNC (int64x2x4_t, int64x2_t, int64_t, v2di, di, s64)
+-__LD4_LANE_FUNC (uint8x16x4_t, uint8x16_t, uint8_t, v16qi, qi, u8)
+-__LD4_LANE_FUNC (uint16x8x4_t, uint16x8_t, uint16_t, v8hi, hi, u16)
+-__LD4_LANE_FUNC (uint32x4x4_t, uint32x4_t, uint32_t, v4si, si, u32)
+-__LD4_LANE_FUNC (uint64x2x4_t, uint64x2_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s8 (int8_t __a)
++{
++  return vdupq_n_s8 (__a);
++}
+ 
+-#undef __LD4_LANE_FUNC
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s16 (int16_t __a)
++{
++  return vdupq_n_s16 (__a);
++}
+ 
+-/* vmax */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s32 (int32_t __a)
++{
++  return vdupq_n_s32 (__a);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmax_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s64 (int64_t __a)
+ {
+-  return __builtin_aarch64_smax_nanv2sf (__a, __b);
++  return vdupq_n_s64 (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmax_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u8 (uint8_t __a)
+ {
+-  return __builtin_aarch64_smaxv8qi (__a, __b);
++  return vdupq_n_u8 (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmax_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u16 (uint16_t __a)
+ {
+-  return __builtin_aarch64_smaxv4hi (__a, __b);
++  return vdupq_n_u16 (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmax_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u32 (uint32_t __a)
+ {
+-  return __builtin_aarch64_smaxv2si (__a, __b);
++  return vdupq_n_u32 (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmax_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u64 (uint64_t __a)
+ {
+-  return (uint8x8_t) __builtin_aarch64_umaxv8qi ((int8x8_t) __a,
+-						 (int8x8_t) __b);
++  return vdupq_n_u64 (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmax_u16 (uint16x4_t __a, uint16x4_t __b)
++/* vmul_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f32 (float32x2_t __a, float32x2_t __b, const int __lane)
+ {
+-  return (uint16x4_t) __builtin_aarch64_umaxv4hi ((int16x4_t) __a,
+-						  (int16x4_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmax_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f64 (float64x1_t __a, float64x1_t __b, const int __lane)
+ {
+-  return (uint32x2_t) __builtin_aarch64_umaxv2si ((int32x2_t) __a,
+-						  (int32x2_t) __b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmaxq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_s16 (int16x4_t __a, int16x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smax_nanv4sf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmaxq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_s32 (int32x2_t __a, int32x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smax_nanv2df (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmaxq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smaxv16qi (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmaxq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smaxv8hi (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmaxq_s32 (int32x4_t __a, int32x4_t __b)
++/* vmuld_lane  */
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuld_lane_f64 (float64_t __a, float64x1_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smaxv4si (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuld_laneq_f64 (float64_t __a, float64x2_t __b, const int __lane)
+ {
+-  return (uint8x16_t) __builtin_aarch64_umaxv16qi ((int8x16_t) __a,
+-						   (int8x16_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
++/* vmuls_lane  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuls_lane_f32 (float32_t __a, float32x2_t __b, const int __lane)
+ {
+-  return (uint16x8_t) __builtin_aarch64_umaxv8hi ((int16x8_t) __a,
+-						  (int16x8_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuls_laneq_f32 (float32_t __a, float32x4_t __b, const int __lane)
+ {
+-  return (uint32x4_t) __builtin_aarch64_umaxv4si ((int32x4_t) __a,
+-						  (int32x4_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+-/* vmulx */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmulx_f32 (float32x2_t __a, float32x2_t __b)
++/* vmul_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_f32 (float32x2_t __a, float32x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxv2sf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulxq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_f64 (float64x1_t __a, float64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxv4sf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmulx_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __lane)
+ {
+-  return (float64x1_t) {__builtin_aarch64_fmulxdf (__a[0], __b[0])};
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulxq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxv2df (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmulxs_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_u16 (uint16x4_t __a, uint16x8_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxsf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmulxd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_u32 (uint32x2_t __a, uint32x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxdf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmulx_lane_f32 (float32x2_t __a, float32x2_t __v, const int __lane)
++/* vmul_n  */
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f64  (float64x1_t __a, float64_t __b)
+ {
+-  return vmulx_f32 (__a, __aarch64_vdup_lane_f32 (__v, __lane));
++  return (float64x1_t) { vget_lane_f64 (__a, 0) * __b };
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmulx_lane_f64 (float64x1_t __a, float64x1_t __v, const int __lane)
++/* vmulq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f32 (float32x4_t __a, float32x2_t __b, const int __lane)
+ {
+-  return vmulx_f64 (__a, __aarch64_vdup_lane_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulxq_lane_f32 (float32x4_t __a, float32x2_t __v, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f64 (float64x2_t __a, float64x1_t __b, const int __lane)
+ {
+-  return vmulxq_f32 (__a, __aarch64_vdupq_lane_f32 (__v, __lane));
++  __AARCH64_LANE_CHECK (__a, __lane);
++  return __a * __b[0];
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulxq_lane_f64 (float64x2_t __a, float64x1_t __v, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __lane)
+ {
+-  return vmulxq_f64 (__a, __aarch64_vdupq_lane_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmulx_laneq_f32 (float32x2_t __a, float32x4_t __v, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __lane)
+ {
+-  return vmulx_f32 (__a, __aarch64_vdup_laneq_f32 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmulx_laneq_f64 (float64x1_t __a, float64x2_t __v, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_u16 (uint16x8_t __a, uint16x4_t __b, const int __lane)
+ {
+-  return vmulx_f64 (__a, __aarch64_vdup_laneq_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulxq_laneq_f32 (float32x4_t __a, float32x4_t __v, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_u32 (uint32x4_t __a, uint32x2_t __b, const int __lane)
+ {
+-  return vmulxq_f32 (__a, __aarch64_vdupq_laneq_f32 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulxq_laneq_f64 (float64x2_t __a, float64x2_t __v, const int __lane)
++/* vmulq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_f32 (float32x4_t __a, float32x4_t __b, const int __lane)
+ {
+-  return vmulxq_f64 (__a, __aarch64_vdupq_laneq_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmulxs_lane_f32 (float32_t __a, float32x2_t __v, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_f64 (float64x2_t __a, float64x2_t __b, const int __lane)
+ {
+-  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmulxs_laneq_f32 (float32_t __a, float32x4_t __v, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __lane)
+ {
+-  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmulxd_lane_f64 (float64_t __a, float64x1_t __v, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __lane)
+ {
+-  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmulxd_laneq_f64 (float64_t __a, float64x2_t __v, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_u16 (uint16x8_t __a, uint16x8_t __b, const int __lane)
+ {
+-  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-/* vpmax  */
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_u32 (uint32x4_t __a, uint32x4_t __b, const int __lane)
++{
++  return __a * __aarch64_vget_lane_any (__b, __lane);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vpmax_s8 (int8x8_t a, int8x8_t b)
++/* vmul_n.  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f32 (float32x2_t __a, float32_t __b)
+ {
+-  return __builtin_aarch64_smaxpv8qi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpmax_s16 (int16x4_t a, int16x4_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f32 (float32x4_t __a, float32_t __b)
+ {
+-  return __builtin_aarch64_smaxpv4hi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpmax_s32 (int32x2_t a, int32x2_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f64 (float64x2_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_smaxpv2si (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vpmax_u8 (uint8x8_t a, uint8x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_s16 (int16x4_t __a, int16_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_umaxpv8qi ((int8x8_t) a,
+-						  (int8x8_t) b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpmax_u16 (uint16x4_t a, uint16x4_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+-  return (uint16x4_t) __builtin_aarch64_umaxpv4hi ((int16x4_t) a,
+-						   (int16x4_t) b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpmax_u32 (uint32x2_t a, uint32x2_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_s32 (int32x2_t __a, int32_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_umaxpv2si ((int32x2_t) a,
+-						   (int32x2_t) b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vpmaxq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_smaxpv16qi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpmaxq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_u16 (uint16x4_t __a, uint16_t __b)
+ {
+-  return __builtin_aarch64_smaxpv8hi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpmaxq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_u16 (uint16x8_t __a, uint16_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_u32 (uint32x2_t __a, uint32_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_u32 (uint32x4_t __a, uint32_t __b)
++{
++  return __a * __b;
++}
++
++/* vmvn  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_p8 (poly8x8_t __a)
+ {
+-  return __builtin_aarch64_smaxpv4si (a, b);
++  return (poly8x8_t) ~((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vpmaxq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_s8 (int8x8_t __a)
+ {
+-  return (uint8x16_t) __builtin_aarch64_umaxpv16qi ((int8x16_t) a,
+-						    (int8x16_t) b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpmaxq_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_s16 (int16x4_t __a)
+ {
+-  return (uint16x8_t) __builtin_aarch64_umaxpv8hi ((int16x8_t) a,
+-						   (int16x8_t) b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpmaxq_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_s32 (int32x2_t __a)
+ {
+-  return (uint32x4_t) __builtin_aarch64_umaxpv4si ((int32x4_t) a,
+-						   (int32x4_t) b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpmax_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_u8 (uint8x8_t __a)
+ {
+-  return __builtin_aarch64_smax_nanpv2sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpmaxq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_u16 (uint16x4_t __a)
+ {
+-  return __builtin_aarch64_smax_nanpv4sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpmaxq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_u32 (uint32x2_t __a)
+ {
+-  return __builtin_aarch64_smax_nanpv2df (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpmaxqd_f64 (float64x2_t a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_p8 (poly8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2df (a);
++  return (poly8x16_t) ~((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpmaxs_f32 (float32x2_t a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (a);
++  return ~__a;
+ }
+ 
+-/* vpmaxnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpmaxnm_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_s16 (int16x8_t __a)
+ {
+-  return __builtin_aarch64_smaxpv2sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpmaxnmq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_s32 (int32x4_t __a)
+ {
+-  return __builtin_aarch64_smaxpv4sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpmaxnmq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_u8 (uint8x16_t __a)
+ {
+-  return __builtin_aarch64_smaxpv2df (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpmaxnmqd_f64 (float64x2_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_u16 (uint16x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2df (a);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpmaxnms_f32 (float32x2_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_u32 (uint32x4_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2sf (a);
++  return ~__a;
+ }
+ 
+-/* vpmin  */
++/* vneg  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vpmin_s8 (int8x8_t a, int8x8_t b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sminpv8qi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpmin_s16 (int16x4_t a, int16x4_t b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sminpv4hi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpmin_s32 (int32x2_t a, int32x2_t b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s8 (int8x8_t __a)
+ {
+-  return __builtin_aarch64_sminpv2si (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vpmin_u8 (uint8x8_t a, uint8x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s16 (int16x4_t __a)
+ {
+-  return (uint8x8_t) __builtin_aarch64_uminpv8qi ((int8x8_t) a,
+-						  (int8x8_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpmin_u16 (uint16x4_t a, uint16x4_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s32 (int32x2_t __a)
+ {
+-  return (uint16x4_t) __builtin_aarch64_uminpv4hi ((int16x4_t) a,
+-						   (int16x4_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpmin_u32 (uint32x2_t a, uint32x2_t b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s64 (int64x1_t __a)
+ {
+-  return (uint32x2_t) __builtin_aarch64_uminpv2si ((int32x2_t) a,
+-						   (int32x2_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vpminq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_sminpv16qi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpminq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sminpv8hi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpminq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_sminpv4si (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vpminq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s16 (int16x8_t __a)
+ {
+-  return (uint8x16_t) __builtin_aarch64_uminpv16qi ((int8x16_t) a,
+-						    (int8x16_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpminq_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s32 (int32x4_t __a)
+ {
+-  return (uint16x8_t) __builtin_aarch64_uminpv8hi ((int16x8_t) a,
+-						   (int16x8_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpminq_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s64 (int64x2_t __a)
+ {
+-  return (uint32x4_t) __builtin_aarch64_uminpv4si ((int32x4_t) a,
+-						   (int32x4_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpmin_f32 (float32x2_t a, float32x2_t b)
++/* vpadd  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __builtin_aarch64_smin_nanpv2sf (a, b);
++  return __builtin_aarch64_faddpv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpminq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __builtin_aarch64_smin_nanpv4sf (a, b);
++  return __builtin_aarch64_faddpv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpminq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __builtin_aarch64_smin_nanpv2df (a, b);
++  return __builtin_aarch64_faddpv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpminqd_f64 (float64x2_t a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2df (a);
++  return __builtin_aarch64_addpv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpmins_f32 (float32x2_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (a);
++  return __builtin_aarch64_addpv4hi (__a, __b);
+ }
+ 
+-/* vpminnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpminnm_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_sminpv2sf (a, b);
++  return __builtin_aarch64_addpv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpminnmq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  return __builtin_aarch64_sminpv4sf (a, b);
++  return (uint8x8_t) __builtin_aarch64_addpv8qi ((int8x8_t) __a,
++						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpminnmq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  return __builtin_aarch64_sminpv2df (a, b);
++  return (uint16x4_t) __builtin_aarch64_addpv4hi ((int16x4_t) __a,
++						  (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpminnmqd_f64 (float64x2_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2df (a);
++  return (uint32x2_t) __builtin_aarch64_addpv2si ((int32x2_t) __a,
++						  (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpminnms_f32 (float32x2_t a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadds_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2sf (a);
++  return __builtin_aarch64_reduc_plus_scal_v2sf (__a);
+ }
+ 
+-/* vmaxnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmaxnm_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddd_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_fmaxv2sf (__a, __b);
++  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddd_s64 (int64x2_t __a)
+ {
+-  return __builtin_aarch64_fmaxv4sf (__a, __b);
++  return __builtin_aarch64_addpdi (__a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmaxnmq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddd_u64 (uint64x2_t __a)
+ {
+-  return __builtin_aarch64_fmaxv2df (__a, __b);
++  return __builtin_aarch64_addpdi ((int64x2_t) __a);
+ }
+ 
+-/* vmaxv  */
++/* vqabs */
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxv_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsq_s64 (int64x2_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (__a);
++  return (int64x2_t) __builtin_aarch64_sqabsv2di (__a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vmaxv_s8 (int8x8_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsb_s8 (int8_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v8qi (__a);
++  return (int8_t) __builtin_aarch64_sqabsqi (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vmaxv_s16 (int16x4_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsh_s16 (int16_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v4hi (__a);
++  return (int16_t) __builtin_aarch64_sqabshi (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vmaxv_s32 (int32x2_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabss_s32 (int32_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2si (__a);
++  return (int32_t) __builtin_aarch64_sqabssi (__a);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vmaxv_u8 (uint8x8_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsd_s64 (int64_t __a)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v8qi_uu (__a);
++  return __builtin_aarch64_sqabsdi (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vmaxv_u16 (uint16x4_t __a)
+-{
+-  return __builtin_aarch64_reduc_umax_scal_v4hi_uu (__a);
+-}
++/* vqadd */
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vmaxv_u32 (uint32x2_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddb_s8 (int8_t __a, int8_t __b)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v2si_uu (__a);
++  return (int8_t) __builtin_aarch64_sqaddqi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxvq_f32 (float32x4_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddh_s16 (int16_t __a, int16_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v4sf (__a);
++  return (int16_t) __builtin_aarch64_sqaddhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmaxvq_f64 (float64x2_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqadds_s32 (int32_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2df (__a);
++  return (int32_t) __builtin_aarch64_sqaddsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vmaxvq_s8 (int8x16_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v16qi (__a);
++  return __builtin_aarch64_sqadddi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vmaxvq_s16 (int16x8_t __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v8hi (__a);
++  return (uint8_t) __builtin_aarch64_uqaddqi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vmaxvq_s32 (int32x4_t __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v4si (__a);
++  return (uint16_t) __builtin_aarch64_uqaddhi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vmaxvq_u8 (uint8x16_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqadds_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v16qi_uu (__a);
++  return (uint32_t) __builtin_aarch64_uqaddsi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vmaxvq_u16 (uint16x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v8hi_uu (__a);
++  return __builtin_aarch64_uqadddi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vmaxvq_u32 (uint32x4_t __a)
++/* vqdmlal */
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v4si_uu (__a);
++  return __builtin_aarch64_sqdmlalv4hi (__a, __b, __c);
+ }
+ 
+-/* vmaxnmv  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxnmv_f32 (float32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2sf (__a);
++  return __builtin_aarch64_sqdmlal2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxnmvq_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
++		       int const __d)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v4sf (__a);
++  return __builtin_aarch64_sqdmlal2_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmaxnmvq_f64 (float64x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2df (__a);
++  return __builtin_aarch64_sqdmlal2_laneqv8hi (__a, __b, __c, __d);
+ }
+ 
+-/* vmin  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmin_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_smin_nanv2sf (__a, __b);
++  return __builtin_aarch64_sqdmlal2_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmin_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv8qi (__a, __b);
++  return __builtin_aarch64_sqdmlal_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmin_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv4hi (__a, __b);
++  return __builtin_aarch64_sqdmlal_laneqv4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmin_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_sminv2si (__a, __b);
++  return __builtin_aarch64_sqdmlal_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmin_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+-  return (uint8x8_t) __builtin_aarch64_uminv8qi ((int8x8_t) __a,
+-						 (int8x8_t) __b);
++  return __builtin_aarch64_sqdmlalv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmin_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+ {
+-  return (uint16x4_t) __builtin_aarch64_uminv4hi ((int16x4_t) __a,
+-						  (int16x4_t) __b);
++  return __builtin_aarch64_sqdmlal2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmin_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
++		       int const __d)
+ {
+-  return (uint32x2_t) __builtin_aarch64_uminv2si ((int32x2_t) __a,
+-						  (int32x2_t) __b);
++  return __builtin_aarch64_sqdmlal2_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vminq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_smin_nanv4sf (__a, __b);
++  return __builtin_aarch64_sqdmlal2_laneqv4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vminq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_smin_nanv2df (__a, __b);
++  return __builtin_aarch64_sqdmlal2_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vminq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv16qi (__a, __b);
++  return __builtin_aarch64_sqdmlal_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vminq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv8hi (__a, __b);
++  return __builtin_aarch64_sqdmlal_laneqv2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vminq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_sminv4si (__a, __b);
++  return __builtin_aarch64_sqdmlal_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vminq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlalh_s16 (int32_t __a, int16_t __b, int16_t __c)
+ {
+-  return (uint8x16_t) __builtin_aarch64_uminv16qi ((int8x16_t) __a,
+-						   (int8x16_t) __b);
++  return __builtin_aarch64_sqdmlalhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vminq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlalh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
+ {
+-  return (uint16x8_t) __builtin_aarch64_uminv8hi ((int16x8_t) __a,
+-						  (int16x8_t) __b);
++  return __builtin_aarch64_sqdmlal_lanehi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vminq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlalh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
+ {
+-  return (uint32x4_t) __builtin_aarch64_uminv4si ((int32x4_t) __a,
+-						  (int32x4_t) __b);
++  return __builtin_aarch64_sqdmlal_laneqhi (__a, __b, __c, __d);
+ }
+ 
+-/* vminnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vminnm_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlals_s32 (int64_t __a, int32_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_fminv2sf (__a, __b);
++  return __builtin_aarch64_sqdmlalsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vminnmq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlals_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
+ {
+-  return __builtin_aarch64_fminv4sf (__a, __b);
++  return __builtin_aarch64_sqdmlal_lanesi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vminnmq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlals_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
+ {
+-  return __builtin_aarch64_fminv2df (__a, __b);
++  return __builtin_aarch64_sqdmlal_laneqsi (__a, __b, __c, __d);
+ }
+ 
+-/* vminv  */
++/* vqdmlsl */
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminv_f32 (float32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (__a);
++  return __builtin_aarch64_sqdmlslv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vminv_s8 (int8x8_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v8qi (__a);
++  return __builtin_aarch64_sqdmlsl2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vminv_s16 (int16x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
++		       int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v4hi (__a);
++  return __builtin_aarch64_sqdmlsl2_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vminv_s32 (int32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2si (__a);
++  return __builtin_aarch64_sqdmlsl2_laneqv8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vminv_u8 (uint8x8_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v8qi_uu (__a);
++  return __builtin_aarch64_sqdmlsl2_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vminv_u16 (uint16x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v4hi_uu (__a);
++  return __builtin_aarch64_sqdmlsl_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vminv_u32 (uint32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v2si_uu (__a);
++  return __builtin_aarch64_sqdmlsl_laneqv4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminvq_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v4sf (__a);
++  return __builtin_aarch64_sqdmlsl_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vminvq_f64 (float64x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2df (__a);
++  return __builtin_aarch64_sqdmlslv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vminvq_s8 (int8x16_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v16qi (__a);
++  return __builtin_aarch64_sqdmlsl2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vminvq_s16 (int16x8_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
++		       int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v8hi (__a);
++  return __builtin_aarch64_sqdmlsl2_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vminvq_s32 (int32x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v4si (__a);
++  return __builtin_aarch64_sqdmlsl2_laneqv4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vminvq_u8 (uint8x16_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v16qi_uu (__a);
++  return __builtin_aarch64_sqdmlsl2_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vminvq_u16 (uint16x8_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v8hi_uu (__a);
++  return __builtin_aarch64_sqdmlsl_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vminvq_u32 (uint32x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v4si_uu (__a);
++  return __builtin_aarch64_sqdmlsl_laneqv2si (__a, __b, __c, __d);
+ }
+ 
+-/* vminnmv  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminnmv_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2sf (__a);
++  return __builtin_aarch64_sqdmlsl_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminnmvq_f32 (float32x4_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlslh_s16 (int32_t __a, int16_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v4sf (__a);
++  return __builtin_aarch64_sqdmlslhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vminnmvq_f64 (float64x2_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlslh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2df (__a);
++  return __builtin_aarch64_sqdmlsl_lanehi (__a, __b, __c, __d);
+ }
+ 
+-/* vmla */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlslh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
+ {
+-  return a + b * c;
++  return __builtin_aarch64_sqdmlsl_laneqhi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmla_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsls_s32 (int64_t __a, int32_t __b, int32_t __c)
+ {
+-  return __a + __b * __c;
++  return __builtin_aarch64_sqdmlslsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsls_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
+ {
+-  return a + b * c;
++  return __builtin_aarch64_sqdmlsl_lanesi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmlaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsls_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
+ {
+-  return a + b * c;
++  return __builtin_aarch64_sqdmlsl_laneqsi (__a, __b, __c, __d);
+ }
+ 
+-/* vmla_lane  */
++/* vqdmulh */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_lane_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_lane_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b,
+-	       uint32x2_t __c, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhh_s16 (int16_t __a, int16_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int16_t) __builtin_aarch64_sqdmulhhi (__a, __b);
+ }
+ 
+-/* vmla_laneq  */
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_lanehi (__a, __b, __c);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	        float32x4_t __c, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_laneqhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_laneq_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhs_s32 (int32_t __a, int32_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int32_t) __builtin_aarch64_sqdmulhsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_laneq_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x4_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanesi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x8_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_laneqsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
+-		uint32x4_t __c, const int __lane)
++/* vqdmull */
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmullv4hi (__a, __b);
+ }
+ 
+-/* vmlaq_lane  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_s16 (int16x8_t __a, int16x8_t __b)
++{
++  return __builtin_aarch64_sqdmull2v8hi (__a, __b);
++}
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-		float32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_lane_s16 (int16x8_t __a, int16x4_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_lanev8hi (__a, __b,__c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_laneq_s16 (int16x8_t __a, int16x8_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_laneqv8hi (__a, __b,__c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_n_s16 (int16x8_t __a, int16_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_laneq_s16 (int16x4_t __a, int16x8_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_laneqv4hi (__a, __b, __c);
+ }
+ 
+-  /* vmlaq_laneq  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_n_s16 (int16x4_t __a, int16_t __b)
++{
++  return __builtin_aarch64_sqdmull_nv4hi (__a, __b);
++}
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-		 float32x4_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmullv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x4_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_lane_s32 (int32x4_t __a, int32x2_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x8_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_laneqv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x4_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_n_s32 (int32x4_t __a, int32_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_nv4si (__a, __b);
+ }
+ 
+-/* vmls  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, int const __c)
+ {
+-  return a - b * c;
++  return __builtin_aarch64_sqdmull_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmls_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b, int const __c)
+ {
+-  return __a - __b * __c;
++  return __builtin_aarch64_sqdmull_laneqv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_n_s32 (int32x2_t __a, int32_t __b)
+ {
+-  return a - b * c;
++  return __builtin_aarch64_sqdmull_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmlsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmullh_s16 (int16_t __a, int16_t __b)
+ {
+-  return a - b * c;
++  return (int32_t) __builtin_aarch64_sqdmullhi (__a, __b);
+ }
+ 
+-/* vmls_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmullh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_lanehi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_lane_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmullh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_laneqhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_lane_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulls_s32 (int32_t __a, int32_t __b)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmullsi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulls_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_lanesi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b,
+-	       uint32x2_t __c, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulls_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_laneqsi (__a, __b, __c);
+ }
+ 
+-/* vmls_laneq  */
++/* vqmovn */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x4_t __c, const int __lane)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_s16 (int16x8_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int8x8_t) __builtin_aarch64_sqmovnv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_laneq_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_s32 (int32x4_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int16x4_t) __builtin_aarch64_sqmovnv4si (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_laneq_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x4_t __c, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_s64 (int64x2_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int32x2_t) __builtin_aarch64_sqmovnv2di (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x8_t __c, const int __lane)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_u16 (uint16x8_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint8x8_t) __builtin_aarch64_uqmovnv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
+-		uint32x4_t __c, const int __lane)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_u32 (uint32x4_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint16x4_t) __builtin_aarch64_uqmovnv4si ((int32x4_t) __a);
+ }
+ 
+-/* vmlsq_lane  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-		float32x2_t __c, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_u64 (uint64x2_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint32x2_t) __builtin_aarch64_uqmovnv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnh_s16 (int16_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int8_t) __builtin_aarch64_sqmovnhi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovns_s32 (int32_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int16_t) __builtin_aarch64_sqmovnsi (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnd_s64 (int64_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int32_t) __builtin_aarch64_sqmovndi (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x2_t __c, const int __lane)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnh_u16 (uint16_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint8_t) __builtin_aarch64_uqmovnhi (__a);
+ }
+ 
+-  /* vmlsq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-		float32x4_t __c, const int __lane)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovns_u32 (uint32_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint16_t) __builtin_aarch64_uqmovnsi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnd_u64 (uint64_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint32_t) __builtin_aarch64_uqmovndi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x4_t __c, const int __lane)
++/* vqmovun */
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_s16 (int16x8_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint8x8_t) __builtin_aarch64_sqmovunv8hi (__a);
+ }
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x8_t __c, const int __lane)
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_s32 (int32x4_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint16x4_t) __builtin_aarch64_sqmovunv4si (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x4_t __c, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_s64 (int64x2_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint32x2_t) __builtin_aarch64_sqmovunv2di (__a);
+ }
+ 
+-/* vmov_n_  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmov_n_f32 (float32_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovunh_s16 (int16_t __a)
+ {
+-  return vdup_n_f32 (__a);
++  return (int8_t) __builtin_aarch64_sqmovunhi (__a);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmov_n_f64 (float64_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovuns_s32 (int32_t __a)
+ {
+-  return (float64x1_t) {__a};
++  return (int16_t) __builtin_aarch64_sqmovunsi (__a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vmov_n_p8 (poly8_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovund_s64 (int64_t __a)
+ {
+-  return vdup_n_p8 (__a);
++  return (int32_t) __builtin_aarch64_sqmovundi (__a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vmov_n_p16 (poly16_t __a)
++/* vqneg */
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegq_s64 (int64x2_t __a)
+ {
+-  return vdup_n_p16 (__a);
++  return (int64x2_t) __builtin_aarch64_sqnegv2di (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmov_n_s8 (int8_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegb_s8 (int8_t __a)
+ {
+-  return vdup_n_s8 (__a);
++  return (int8_t) __builtin_aarch64_sqnegqi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmov_n_s16 (int16_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegh_s16 (int16_t __a)
+ {
+-  return vdup_n_s16 (__a);
++  return (int16_t) __builtin_aarch64_sqneghi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmov_n_s32 (int32_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegs_s32 (int32_t __a)
+ {
+-  return vdup_n_s32 (__a);
++  return (int32_t) __builtin_aarch64_sqnegsi (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vmov_n_s64 (int64_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegd_s64 (int64_t __a)
+ {
+-  return (int64x1_t) {__a};
++  return __builtin_aarch64_sqnegdi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmov_n_u8 (uint8_t __a)
++/* vqrdmulh */
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return vdup_n_u8 (__a);
++  return  __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmov_n_u16 (uint16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-    return vdup_n_u16 (__a);
++  return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmov_n_u32 (uint32_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+-   return vdup_n_u32 (__a);
++  return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vmov_n_u64 (uint64_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+-  return (uint64x1_t) {__a};
++  return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmovq_n_f32 (float32_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhh_s16 (int16_t __a, int16_t __b)
+ {
+-  return vdupq_n_f32 (__a);
++  return (int16_t) __builtin_aarch64_sqrdmulhhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmovq_n_f64 (float64_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
+ {
+-  return vdupq_n_f64 (__a);
++  return __builtin_aarch64_sqrdmulh_lanehi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vmovq_n_p8 (poly8_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+-  return vdupq_n_p8 (__a);
++  return __builtin_aarch64_sqrdmulh_laneqhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vmovq_n_p16 (poly16_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhs_s32 (int32_t __a, int32_t __b)
+ {
+-  return vdupq_n_p16 (__a);
++  return (int32_t) __builtin_aarch64_sqrdmulhsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmovq_n_s8 (int8_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+-  return vdupq_n_s8 (__a);
++  return __builtin_aarch64_sqrdmulh_lanesi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovq_n_s16 (int16_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+-  return vdupq_n_s16 (__a);
++  return __builtin_aarch64_sqrdmulh_laneqsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovq_n_s32 (int32_t __a)
++/* vqrshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return vdupq_n_s32 (__a);
++  return __builtin_aarch64_sqrshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmovq_n_s64 (int64_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return vdupq_n_s64 (__a);
++  return __builtin_aarch64_sqrshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmovq_n_u8 (uint8_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return vdupq_n_u8 (__a);
++  return __builtin_aarch64_sqrshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovq_n_u16 (uint16_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return vdupq_n_u16 (__a);
++  return (int64x1_t) {__builtin_aarch64_sqrshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovq_n_u32 (uint32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return vdupq_n_u32 (__a);
++  return __builtin_aarch64_uqrshlv8qi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmovq_n_u64 (uint64_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return vdupq_n_u64 (__a);
++  return __builtin_aarch64_uqrshlv4hi_uus ( __a, __b);
+ }
+ 
+-/* vmul_lane  */
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u32 (uint32x2_t __a, int32x2_t __b)
++{
++  return __builtin_aarch64_uqrshlv2si_uus ( __a, __b);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmul_lane_f32 (float32x2_t __a, float32x2_t __b, const int __lane)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (uint64x1_t) {__builtin_aarch64_uqrshldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmul_lane_f64 (float64x1_t __a, float64x1_t __b, const int __lane)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __a * __b;
++  return __builtin_aarch64_sqrshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmul_lane_s16 (int16x4_t __a, int16x4_t __b, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmul_lane_s32 (int32x2_t __a, int32x2_t __b, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmul_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmul_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __lane)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv16qi_uus ( __a, __b);
+ }
+ 
+-/* vmuld_lane  */
+-
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmuld_lane_f64 (float64_t __a, float64x1_t __b, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmuld_laneq_f64 (float64_t __a, float64x2_t __b, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv4si_uus ( __a, __b);
+ }
+ 
+-/* vmuls_lane  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmuls_lane_f32 (float32_t __a, float32x2_t __b, const int __lane)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv2di_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmuls_laneq_f32 (float32_t __a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlb_s8 (int8_t __a, int8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlqi (__a, __b);
+ }
+ 
+-/* vmul_laneq  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmul_laneq_f32 (float32x2_t __a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlh_s16 (int16_t __a, int16_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmul_laneq_f64 (float64x1_t __a, float64x2_t __b, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshls_s32 (int32_t __a, int32_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmul_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshldi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmul_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __lane)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmul_laneq_u16 (uint16x4_t __a, uint16x8_t __b, const int __lane)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmul_laneq_u32 (uint32x2_t __a, uint32x4_t __b, const int __lane)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshls_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlsi_uus (__a, __b);
+ }
+ 
+-/* vmul_n  */
+-
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmul_n_f64  (float64x1_t __a, float64_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshld_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return (float64x1_t) { vget_lane_f64 (__a, 0) * __b };
++  return __builtin_aarch64_uqrshldi_uus (__a, __b);
+ }
+ 
+-/* vmulq_lane  */
++/* vqrshrn */
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulq_lane_f32 (float32x4_t __a, float32x2_t __b, const int __lane)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int8x8_t) __builtin_aarch64_sqrshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulq_lane_f64 (float64x2_t __a, float64x1_t __b, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+-  __AARCH64_LANE_CHECK (__a, __lane);
+-  return __a * __b[0];
++  return (int16x4_t) __builtin_aarch64_sqrshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmulq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int32x2_t) __builtin_aarch64_sqrshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmulq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __lane)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmulq_lane_u16 (uint16x8_t __a, uint16x4_t __b, const int __lane)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nv4si_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmulq_lane_u32 (uint32x4_t __a, uint32x2_t __b, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nv2di_uus ( __a, __b);
+ }
+ 
+-/* vmulq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulq_laneq_f32 (float32x4_t __a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int8_t) __builtin_aarch64_sqrshrn_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulq_laneq_f64 (float64x2_t __a, float64x2_t __b, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrns_n_s32 (int32_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int16_t) __builtin_aarch64_sqrshrn_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmulq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int32_t) __builtin_aarch64_sqrshrn_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmulq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __lane)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnh_n_u16 (uint16_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmulq_laneq_u16 (uint16x8_t __a, uint16x8_t __b, const int __lane)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrns_n_u32 (uint32_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmulq_laneq_u32 (uint32x4_t __a, uint32x4_t __b, const int __lane)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_ndi_uus (__a, __b);
+ }
+ 
+-/* vneg  */
++/* vqrshrun */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vneg_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return -__a;
++  return (uint8x8_t) __builtin_aarch64_sqrshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vneg_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return -__a;
++  return (uint16x4_t) __builtin_aarch64_sqrshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vneg_s8 (int8x8_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return -__a;
++  return (uint32x2_t) __builtin_aarch64_sqrshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vneg_s16 (int16x4_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrunh_n_s16 (int16_t __a, const int __b)
+ {
+-  return -__a;
++  return (int8_t) __builtin_aarch64_sqrshrun_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vneg_s32 (int32x2_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshruns_n_s32 (int32_t __a, const int __b)
+ {
+-  return -__a;
++  return (int16_t) __builtin_aarch64_sqrshrun_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vneg_s64 (int64x1_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrund_n_s64 (int64_t __a, const int __b)
+ {
+-  return -__a;
++  return (int32_t) __builtin_aarch64_sqrshrun_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vnegq_f32 (float32x4_t __a)
++/* vqshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_sqshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vnegq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_sqshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vnegq_s8 (int8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_sqshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vnegq_s16 (int16x8_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return -__a;
++  return (int64x1_t) {__builtin_aarch64_sqshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vnegq_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_uqshlv8qi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vnegq_s64 (int64x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_uqshlv4hi_uus ( __a, __b);
+ }
+ 
+-/* vpadd  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vpadd_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_addpv8qi (__a, __b);
++  return __builtin_aarch64_uqshlv2si_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpadd_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_addpv4hi (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_uqshldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpadd_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_addpv2si (__a, __b);
++  return __builtin_aarch64_sqshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_addpv8qi ((int8x8_t) __a,
+-						 (int8x8_t) __b);
++  return __builtin_aarch64_sqshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return (uint16x4_t) __builtin_aarch64_addpv4hi ((int16x4_t) __a,
+-						  (int16x4_t) __b);
++  return __builtin_aarch64_sqshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_addpv2si ((int32x2_t) __a,
+-						  (int32x2_t) __b);
++  return __builtin_aarch64_sqshlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpaddd_f64 (float64x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
++  return __builtin_aarch64_uqshlv16qi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vpaddd_s64 (int64x2_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_addpdi (__a);
++  return __builtin_aarch64_uqshlv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vpaddd_u64 (uint64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_addpdi ((int64x2_t) __a);
++  return __builtin_aarch64_uqshlv4si_uus ( __a, __b);
+ }
+ 
+-/* vqabs */
+-
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqabsq_s64 (int64x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return (int64x2_t) __builtin_aarch64_sqabsv2di (__a);
++  return __builtin_aarch64_uqshlv2di_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqabsb_s8 (int8_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_s8 (int8_t __a, int8_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqabsqi (__a);
++  return __builtin_aarch64_sqshlqi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqabsh_s16 (int16_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_s16 (int16_t __a, int16_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqabshi (__a);
++  return __builtin_aarch64_sqshlhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqabss_s32 (int32_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_s32 (int32_t __a, int32_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqabssi (__a);
++  return __builtin_aarch64_sqshlsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqabsd_s64 (int64_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_sqabsdi (__a);
++  return __builtin_aarch64_sqshldi (__a, __b);
+ }
+ 
+-/* vqadd */
+-
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqaddb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqaddqi (__a, __b);
++  return __builtin_aarch64_uqshlqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqaddh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqaddhi (__a, __b);
++  return __builtin_aarch64_uqshlhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqadds_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqaddsi (__a, __b);
++  return __builtin_aarch64_uqshlsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqaddd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_sqadddi (__a, __b);
++  return __builtin_aarch64_uqshldi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqaddb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return (uint8_t) __builtin_aarch64_uqaddqi_uuu (__a, __b);
++  return (int8x8_t) __builtin_aarch64_sqshl_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqaddh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return (uint16_t) __builtin_aarch64_uqaddhi_uuu (__a, __b);
++  return (int16x4_t) __builtin_aarch64_sqshl_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqadds_u32 (uint32_t __a, uint32_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return (uint32_t) __builtin_aarch64_uqaddsi_uuu (__a, __b);
++  return (int32x2_t) __builtin_aarch64_sqshl_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqaddd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqadddi_uuu (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_sqshl_ndi (__a[0], __b)};
+ }
+ 
+-/* vqdmlal */
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalv4hi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2v8hi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
+-		       int const __d)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_lanev8hi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
+-			int const __d)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_laneqv8hi (__a, __b, __c, __d);
++  return (uint64x1_t) {__builtin_aarch64_uqshl_ndi_uus (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_nv8hi (__a, __b, __c);
++  return (int8x16_t) __builtin_aarch64_sqshl_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanev4hi (__a, __b, __c, __d);
++  return (int16x8_t) __builtin_aarch64_sqshl_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqv4hi (__a, __b, __c, __d);
++  return (int32x4_t) __builtin_aarch64_sqshl_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_nv4hi (__a, __b, __c);
++  return (int64x2_t) __builtin_aarch64_sqshl_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalv2si (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2v4si (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
+-		       int const __d)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_lanev4si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
+-			int const __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_laneqv4si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_n_s8 (int8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_nv4si (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqshl_nqi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanev2si (__a, __b, __c, __d);
++  return (int16_t) __builtin_aarch64_sqshl_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_n_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqv2si (__a, __b, __c, __d);
++  return (int32_t) __builtin_aarch64_sqshl_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_nv2si (__a, __b, __c);
++  return __builtin_aarch64_sqshl_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlalh_s16 (int32_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_n_u8 (uint8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalhi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlalh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_n_u16 (uint16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanehi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlalh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_n_u32 (uint32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqhi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlals_s32 (int64_t __a, int32_t __b, int32_t __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalsi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_ndi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlals_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
++/* vqshlu */
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanesi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv8qi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlals_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqsi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv4hi_uss (__a, __b);
+ }
+ 
+-/* vqdmlsl */
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslv4hi (__a, __b, __c);
++  return __builtin_aarch64_sqshlu_nv2si_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2v8hi (__a, __b, __c);
++  return (uint64x1_t) {__builtin_aarch64_sqshlu_ndi_uss (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
+-		       int const __d)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_lanev8hi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv16qi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
+-			int const __d)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_laneqv8hi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv8hi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_nv8hi (__a, __b, __c);
++  return __builtin_aarch64_sqshlu_nv4si_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanev4hi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv2di_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlub_n_s8 (int8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqv4hi (__a, __b, __c, __d);
++  return (int8_t) __builtin_aarch64_sqshlu_nqi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_nv4hi (__a, __b, __c);
++  return (int16_t) __builtin_aarch64_sqshlu_nhi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlus_n_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslv2si (__a, __b, __c);
++  return (int32_t) __builtin_aarch64_sqshlu_nsi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlud_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2v4si (__a, __b, __c);
++  return __builtin_aarch64_sqshlu_ndi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
+-		       int const __d)
++/* vqshrn */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_lanev4si (__a, __b, __c, __d);
++  return (int8x8_t) __builtin_aarch64_sqshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
+-			int const __d)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_laneqv4si (__a, __b, __c, __d);
++  return (int16x4_t) __builtin_aarch64_sqshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_nv4si (__a, __b, __c);
++  return (int32x2_t) __builtin_aarch64_sqshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanev2si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_nv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqv2si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_nv4si_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_nv2si (__a, __b, __c);
++  return __builtin_aarch64_uqshrn_nv2di_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlslh_s16 (int32_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslhi (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqshrn_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlslh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrns_n_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanehi (__a, __b, __c, __d);
++  return (int16_t) __builtin_aarch64_sqshrn_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlslh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqhi (__a, __b, __c, __d);
++  return (int32_t) __builtin_aarch64_sqshrn_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlsls_s32 (int64_t __a, int32_t __b, int32_t __c)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnh_n_u16 (uint16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslsi (__a, __b, __c);
++  return __builtin_aarch64_uqshrn_nhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlsls_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrns_n_u32 (uint32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanesi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_nsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlsls_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqsi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_ndi_uus (__a, __b);
+ }
+ 
+-/* vqdmulh */
++/* vqshrun */
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c);
++  return (uint8x8_t) __builtin_aarch64_sqshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c);
++  return (uint16x4_t) __builtin_aarch64_sqshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c);
++  return (uint32x2_t) __builtin_aarch64_sqshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrunh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqshrun_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqdmulhh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshruns_n_s32 (int32_t __a, const int __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqdmulhhi (__a, __b);
++  return (int16_t) __builtin_aarch64_sqshrun_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrund_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanehi (__a, __b, __c);
++  return (int32_t) __builtin_aarch64_sqshrun_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
++/* vqsub */
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubb_s8 (int8_t __a, int8_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqhi (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqsubqi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmulhs_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubh_s16 (int16_t __a, int16_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqdmulhsi (__a, __b);
++  return (int16_t) __builtin_aarch64_sqsubhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubs_s32 (int32_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanesi (__a, __b, __c);
++  return (int32_t) __builtin_aarch64_sqsubsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqsi (__a, __b, __c);
++  return __builtin_aarch64_sqsubdi (__a, __b);
+ }
+ 
+-/* vqdmull */
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return __builtin_aarch64_sqdmullv4hi (__a, __b);
++  return (uint8_t) __builtin_aarch64_uqsubqi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return __builtin_aarch64_sqdmull2v8hi (__a, __b);
++  return (uint16_t) __builtin_aarch64_uqsubhi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_lane_s16 (int16x8_t __a, int16x4_t __b, int const __c)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubs_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return __builtin_aarch64_sqdmull2_lanev8hi (__a, __b,__c);
++  return (uint32_t) __builtin_aarch64_uqsubsi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_laneq_s16 (int16x8_t __a, int16x8_t __b, int const __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_sqdmull2_laneqv8hi (__a, __b,__c);
++  return __builtin_aarch64_uqsubdi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_n_s16 (int16x8_t __a, int16_t __b)
++/* vqtbl2 */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2_s8 (int8x16x2_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_nv8hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
++  return __builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, int const __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2_u8 (uint8x16x2_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanev4hi (__a, __b, __c);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_laneq_s16 (int16x4_t __a, int16x8_t __b, int const __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2_p8 (poly8x16x2_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqv4hi (__a, __b, __c);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_n_s16 (int16x4_t __a, int16_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2q_s8 (int8x16x2_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_nv4hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return __builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2q_u8 (uint8x16x2_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmullv2si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2q_p8 (poly8x16x2_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2v4si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_lane_s32 (int32x4_t __a, int32x2_t __b, int const __c)
++/* vqtbl3 */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3_s8 (int8x16x3_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_lanev4si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return __builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b, int const __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3_u8 (uint8x16x3_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_laneqv4si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_n_s32 (int32x4_t __a, int32_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3_p8 (poly8x16x3_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_nv4si (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, int const __c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3q_s8 (int8x16x3_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanev2si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return __builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b, int const __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3q_u8 (uint8x16x3_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqv2si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_n_s32 (int32x2_t __a, int32_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3q_p8 (poly8x16x3_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_nv2si (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmullh_s16 (int16_t __a, int16_t __b)
++/* vqtbl4 */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4_s8 (int8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (int32_t) __builtin_aarch64_sqdmullhi (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return __builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmullh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4_u8 (uint8x16x4_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanehi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmullh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4_p8 (poly8x16x4_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqhi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmulls_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4q_s8 (int8x16x4_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmullsi (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return __builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmulls_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4q_u8 (uint8x16x4_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanesi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmulls_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4q_p8 (poly8x16x4_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqsi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-/* vqmovn */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqmovn_s16 (int16x8_t __a)
++/* vqtbx2 */
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2_s8 (int8x8_t r, int8x16x2_t tab, uint8x8_t idx)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqmovnv8hi (__a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
++  return __builtin_aarch64_tbx4v8qi (r, __o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqmovn_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2_u8 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqmovnv4si (__a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
++						(int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqmovn_s64 (int64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2_p8 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqmovnv2di (__a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
++						(int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqmovn_u16 (uint16x8_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2q_s8 (int8x16_t r, int8x16x2_t tab, uint8x16_t idx)
+ {
+-  return (uint8x8_t) __builtin_aarch64_uqmovnv8hi ((int16x8_t) __a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
++  return __builtin_aarch64_tbx4v16qi (r, __o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqmovn_u32 (uint32x4_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2q_u8 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx)
+ {
+-  return (uint16x4_t) __builtin_aarch64_uqmovnv4si ((int32x4_t) __a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
++						  (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqmovn_u64 (uint64x2_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2q_p8 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx)
+ {
+-  return (uint32x2_t) __builtin_aarch64_uqmovnv2di ((int64x2_t) __a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
++						  (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqmovnh_s16 (int16_t __a)
++/* vqtbx3 */
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3_s8 (int8x8_t r, int8x16x3_t tab, uint8x8_t idx)
+ {
+-  return (int8_t) __builtin_aarch64_sqmovnhi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
++  return __builtin_aarch64_qtbx3v8qi (r, __o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqmovns_s32 (int32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3_u8 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx)
+ {
+-  return (int16_t) __builtin_aarch64_sqmovnsi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqmovnd_s64 (int64_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3_p8 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx)
+ {
+-  return (int32_t) __builtin_aarch64_sqmovndi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqmovnh_u16 (uint16_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3q_s8 (int8x16_t r, int8x16x3_t tab, uint8x16_t idx)
+ {
+-  return (uint8_t) __builtin_aarch64_uqmovnhi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
++  return __builtin_aarch64_qtbx3v16qi (r, __o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqmovns_u32 (uint32_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3q_u8 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx)
+ {
+-  return (uint16_t) __builtin_aarch64_uqmovnsi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqmovnd_u64 (uint64_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3q_p8 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx)
+ {
+-  return (uint32_t) __builtin_aarch64_uqmovndi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-/* vqmovun */
++/* vqtbx4 */
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqmovun_s16 (int16x8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4_s8 (int8x8_t r, int8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (uint8x8_t) __builtin_aarch64_sqmovunv8hi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
++  return __builtin_aarch64_qtbx4v8qi (r, __o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqmovun_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4_u8 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (uint16x4_t) __builtin_aarch64_sqmovunv4si (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqmovun_s64 (int64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4_p8 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (uint32x2_t) __builtin_aarch64_sqmovunv2di (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqmovunh_s16 (int16_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4q_s8 (int8x16_t r, int8x16x4_t tab, uint8x16_t idx)
+ {
+-  return (int8_t) __builtin_aarch64_sqmovunhi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
++  return __builtin_aarch64_qtbx4v16qi (r, __o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqmovuns_s32 (int32_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4q_u8 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx)
+ {
+-  return (int16_t) __builtin_aarch64_sqmovunsi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqmovund_s64 (int64_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4q_p8 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx)
+ {
+-  return (int32_t) __builtin_aarch64_sqmovundi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-/* vqneg */
++/* vrbit  */
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqnegq_s64 (int64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbit_p8 (poly8x8_t __a)
+ {
+-  return (int64x2_t) __builtin_aarch64_sqnegv2di (__a);
++  return (poly8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqnegb_s8 (int8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbit_s8 (int8x8_t __a)
+ {
+-  return (int8_t) __builtin_aarch64_sqnegqi (__a);
++  return __builtin_aarch64_rbitv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqnegh_s16 (int16_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbit_u8 (uint8x8_t __a)
+ {
+-  return (int16_t) __builtin_aarch64_sqneghi (__a);
++  return (uint8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqnegs_s32 (int32_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbitq_p8 (poly8x16_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_sqnegsi (__a);
++  return (poly8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t)__a);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqnegd_s64 (int64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbitq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_sqnegdi (__a);
++  return __builtin_aarch64_rbitv16qi (__a);
+ }
+ 
+-/* vqrdmulh */
+-
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbitq_u8 (uint8x16_t __a)
+ {
+-  return  __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c);
++  return (uint8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++/* vrecpe  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_u32 (uint32x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c);
++  return (uint32x2_t) __builtin_aarch64_urecpev2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_u32 (uint32x4_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c);
++  return (uint32x4_t) __builtin_aarch64_urecpev4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpes_f32 (float32_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c);
++  return __builtin_aarch64_frecpesf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmulhh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecped_f64 (float64_t __a)
+ {
+-  return (int16_t) __builtin_aarch64_sqrdmulhhi (__a, __b);
++  return __builtin_aarch64_frecpedf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanehi (__a, __b, __c);
++  return __builtin_aarch64_frecpev2sf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqhi (__a, __b, __c);
++  return (float64x1_t) { vrecped_f64 (vget_lane_f64 (__a, 0)) };
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmulhs_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f32 (float32x4_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_sqrdmulhsi (__a, __b);
++  return __builtin_aarch64_frecpev4sf (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanesi (__a, __b, __c);
++  return __builtin_aarch64_frecpev2df (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
++/* vrecps  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpss_f32 (float32_t __a, float32_t __b)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqsi (__a, __b, __c);
++  return __builtin_aarch64_frecpssf (__a, __b);
+ }
+ 
+-/* vqrshl */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqrshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsd_f64 (float64_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_sqrshlv8qi (__a, __b);
++  return __builtin_aarch64_frecpsdf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __builtin_aarch64_sqrshlv4hi (__a, __b);
++  return __builtin_aarch64_frecpsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrshl_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return __builtin_aarch64_sqrshlv2si (__a, __b);
++  return (float64x1_t) { vrecpsd_f64 (vget_lane_f64 (__a, 0),
++				      vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vqrshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sqrshldi (__a[0], __b[0])};
++  return __builtin_aarch64_frecpsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqrshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __builtin_aarch64_uqrshlv8qi_uus ( __a, __b);
++  return __builtin_aarch64_frecpsv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqrshl_u16 (uint16x4_t __a, int16x4_t __b)
++/* vrecpx  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpxs_f32 (float32_t __a)
+ {
+-  return __builtin_aarch64_uqrshlv4hi_uus ( __a, __b);
++  return __builtin_aarch64_frecpxsf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqrshl_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpxd_f64 (float64_t __a)
+ {
+-  return __builtin_aarch64_uqrshlv2si_uus ( __a, __b);
++  return __builtin_aarch64_frecpxdf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqrshl_u64 (uint64x1_t __a, int64x1_t __b)
++
++/* vrev  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16_p8 (poly8x8_t a)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_uqrshldi_uus (__a[0], __b[0])};
++  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqrshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16_s8 (int8x8_t a)
+ {
+-  return __builtin_aarch64_sqrshlv16qi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrshlq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16_u8 (uint8x8_t a)
+ {
+-  return __builtin_aarch64_sqrshlv8hi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrshlq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16q_p8 (poly8x16_t a)
+ {
+-  return __builtin_aarch64_sqrshlv4si (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqrshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16q_s8 (int8x16_t a)
+ {
+-  return __builtin_aarch64_sqrshlv2di (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqrshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16q_u8 (uint8x16_t a)
+ {
+-  return __builtin_aarch64_uqrshlv16qi_uus ( __a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqrshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_p8 (poly8x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlv8hi_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqrshlq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_p16 (poly16x4_t a)
+ {
+-  return __builtin_aarch64_uqrshlv4si_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqrshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_s8 (int8x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlv2di_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqrshlb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_s16 (int16x4_t a)
+ {
+-  return __builtin_aarch64_sqrshlqi (__a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrshlh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_u8 (uint8x8_t a)
+ {
+-  return __builtin_aarch64_sqrshlhi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrshls_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_u16 (uint16x4_t a)
+ {
+-  return __builtin_aarch64_sqrshlsi (__a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqrshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_p8 (poly8x16_t a)
+ {
+-  return __builtin_aarch64_sqrshldi (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqrshlb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_p16 (poly16x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlqi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqrshlh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_s8 (int8x16_t a)
+ {
+-  return __builtin_aarch64_uqrshlhi_uus (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqrshls_u32 (uint32_t __a, uint32_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_s16 (int16x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlsi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqrshld_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_u8 (uint8x16_t a)
+ {
+-  return __builtin_aarch64_uqrshldi_uus (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-/* vqrshrn */
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_u16 (uint16x8_t a)
++{
++  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqrshrn_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_f16 (float16x4_t __a)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqrshrn_nv8hi (__a, __b);
++  return __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrshrn_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_f32 (float32x2_t a)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqrshrn_nv4si (__a, __b);
++  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrshrn_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_p8 (poly8x8_t a)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqrshrn_nv2di (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqrshrn_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_p16 (poly16x4_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nv8hi_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqrshrn_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_s8 (int8x8_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nv4si_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqrshrn_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_s16 (int16x4_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nv2di_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqrshrnh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_s32 (int32x2_t a)
+ {
+-  return (int8_t) __builtin_aarch64_sqrshrn_nhi (__a, __b);
++  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrshrns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_u8 (uint8x8_t a)
+ {
+-  return (int16_t) __builtin_aarch64_sqrshrn_nsi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrshrnd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_u16 (uint16x4_t a)
+ {
+-  return (int32_t) __builtin_aarch64_sqrshrn_ndi (__a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqrshrnh_n_u16 (uint16_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_u32 (uint32x2_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nhi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqrshrns_n_u32 (uint32_t __a, const int __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_f16 (float16x8_t __a)
+ {
+-  return __builtin_aarch64_uqrshrn_nsi_uus (__a, __b);
++  return __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqrshrnd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_f32 (float32x4_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_ndi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-/* vqrshrun */
+-
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqrshrun_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_p8 (poly8x16_t a)
+ {
+-  return (uint8x8_t) __builtin_aarch64_sqrshrun_nv8hi (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqrshrun_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_p16 (poly16x8_t a)
+ {
+-  return (uint16x4_t) __builtin_aarch64_sqrshrun_nv4si (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqrshrun_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_s8 (int8x16_t a)
+ {
+-  return (uint32x2_t) __builtin_aarch64_sqrshrun_nv2di (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqrshrunh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_s16 (int16x8_t a)
+ {
+-  return (int8_t) __builtin_aarch64_sqrshrun_nhi (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrshruns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_s32 (int32x4_t a)
+ {
+-  return (int16_t) __builtin_aarch64_sqrshrun_nsi (__a, __b);
++  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrshrund_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_u8 (uint8x16_t a)
+ {
+-  return (int32_t) __builtin_aarch64_sqrshrun_ndi (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-/* vqshl */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_u16 (uint16x8_t a)
+ {
+-  return __builtin_aarch64_sqshlv8qi (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_u32 (uint32x4_t a)
+ {
+-  return __builtin_aarch64_sqshlv4hi (__a, __b);
++  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqshl_s32 (int32x2_t __a, int32x2_t __b)
++/* vrnd  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlv2si (__a, __b);
++  return __builtin_aarch64_btruncv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vqshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f64 (float64x1_t __a)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sqshldi (__a[0], __b[0])};
++  return vset_lane_f64 (__builtin_trunc (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshlv8qi_uus ( __a, __b);
++  return __builtin_aarch64_btruncv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshl_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv4hi_uus ( __a, __b);
++  return __builtin_aarch64_btruncv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshl_u32 (uint32x2_t __a, int32x2_t __b)
++/* vrnda  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv2si_uus ( __a, __b);
++  return __builtin_aarch64_roundv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqshl_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f64 (float64x1_t __a)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_uqshldi_uus (__a[0], __b[0])};
++  return vset_lane_f64 (__builtin_round (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_sqshlv16qi (__a, __b);
++  return __builtin_aarch64_roundv4sf (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqshlq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlv8hi (__a, __b);
++  return __builtin_aarch64_roundv2df (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqshlq_s32 (int32x4_t __a, int32x4_t __b)
++/* vrndi  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndi_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlv4si (__a, __b);
++  return __builtin_aarch64_nearbyintv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndi_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqshlv2di (__a, __b);
++  return vset_lane_f64 (__builtin_nearbyint (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndiq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshlv16qi_uus ( __a, __b);
++  return __builtin_aarch64_nearbyintv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndiq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv8hi_uus ( __a, __b);
++  return __builtin_aarch64_nearbyintv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqshlq_u32 (uint32x4_t __a, int32x4_t __b)
++/* vrndm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv4si_uus ( __a, __b);
++  return __builtin_aarch64_floorv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_uqshlv2di_uus ( __a, __b);
++  return vset_lane_f64 (__builtin_floor (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshlb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_sqshlqi (__a, __b);
++  return __builtin_aarch64_floorv4sf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshlh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlhi (__a, __b);
++  return __builtin_aarch64_floorv2df (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshls_s32 (int32_t __a, int32_t __b)
++/* vrndn  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlsi (__a, __b);
++  return __builtin_aarch64_frintnv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqshldi (__a, __b);
++  return (float64x1_t) {__builtin_aarch64_frintndf (__a[0])};
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqshlb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshlqi_uus (__a, __b);
++  return __builtin_aarch64_frintnv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqshlh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlhi_uus (__a, __b);
++  return __builtin_aarch64_frintnv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqshls_u32 (uint32_t __a, uint32_t __b)
++/* vrndp  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlsi_uus (__a, __b);
++  return __builtin_aarch64_ceilv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqshld_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_uqshldi_uus (__a, __b);
++  return vset_lane_f64 (__builtin_ceil (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqshl_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f32 (float32x4_t __a)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqshl_nv8qi (__a, __b);
++  return __builtin_aarch64_ceilv4sf (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqshl_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f64 (float64x2_t __a)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqshl_nv4hi (__a, __b);
++  return __builtin_aarch64_ceilv2df (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqshl_n_s32 (int32x2_t __a, const int __b)
++/* vrndx  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f32 (float32x2_t __a)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqshl_nv2si (__a, __b);
++  return __builtin_aarch64_rintv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vqshl_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f64 (float64x1_t __a)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sqshl_ndi (__a[0], __b)};
++  return vset_lane_f64 (__builtin_rint (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshl_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshl_nv8qi_uus (__a, __b);
++  return __builtin_aarch64_rintv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshl_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshl_nv4hi_uus (__a, __b);
++  return __builtin_aarch64_rintv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshl_n_u32 (uint32x2_t __a, const int __b)
++/* vrshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv2si_uus (__a, __b);
++  return (int8x8_t) __builtin_aarch64_srshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqshl_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_uqshl_ndi_uus (__a[0], __b)};
++  return (int16x4_t) __builtin_aarch64_srshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqshlq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return (int8x16_t) __builtin_aarch64_sqshl_nv16qi (__a, __b);
++  return (int32x2_t) __builtin_aarch64_srshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqshlq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return (int16x8_t) __builtin_aarch64_sqshl_nv8hi (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_srshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqshlq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return (int32x4_t) __builtin_aarch64_sqshl_nv4si (__a, __b);
++  return __builtin_aarch64_urshlv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqshlq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return (int64x2_t) __builtin_aarch64_sqshl_nv2di (__a, __b);
++  return __builtin_aarch64_urshlv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqshlq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv16qi_uus (__a, __b);
++  return __builtin_aarch64_urshlv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqshlq_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv8hi_uus (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_urshldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqshlq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv4si_uus (__a, __b);
++  return (int8x16_t) __builtin_aarch64_srshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqshlq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv2di_uus (__a, __b);
++  return (int16x8_t) __builtin_aarch64_srshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshlb_n_s8 (int8_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqshl_nqi (__a, __b);
++  return (int32x4_t) __builtin_aarch64_srshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshlh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqshl_nhi (__a, __b);
++  return (int64x2_t) __builtin_aarch64_srshlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshls_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqshl_nsi (__a, __b);
++  return __builtin_aarch64_urshlv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqshld_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_sqshl_ndi (__a, __b);
++  return __builtin_aarch64_urshlv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqshlb_n_u8 (uint8_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nqi_uus (__a, __b);
++  return __builtin_aarch64_urshlv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqshlh_n_u16 (uint16_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nhi_uus (__a, __b);
++  return __builtin_aarch64_urshlv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqshls_n_u32 (uint32_t __a, const int __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nsi_uus (__a, __b);
++  return __builtin_aarch64_srshldi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqshld_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshld_u64 (uint64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_uqshl_ndi_uus (__a, __b);
++  return __builtin_aarch64_urshldi_uus (__a, __b);
+ }
+ 
+-/* vqshlu */
++/* vrshr */
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshlu_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv8qi_uss (__a, __b);
++  return (int8x8_t) __builtin_aarch64_srshr_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshlu_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv4hi_uss (__a, __b);
++  return (int16x4_t) __builtin_aarch64_srshr_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshlu_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv2si_uss (__a, __b);
++  return (int32x2_t) __builtin_aarch64_srshr_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqshlu_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_sqshlu_ndi_uss (__a[0], __b)};
++  return (int64x1_t) {__builtin_aarch64_srshr_ndi (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqshluq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv16qi_uss (__a, __b);
++  return __builtin_aarch64_urshr_nv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqshluq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv8hi_uss (__a, __b);
++  return __builtin_aarch64_urshr_nv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqshluq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv4si_uss (__a, __b);
++  return __builtin_aarch64_urshr_nv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqshluq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv2di_uss (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_urshr_ndi_uus (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshlub_n_s8 (int8_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqshlu_nqi_uss (__a, __b);
++  return (int8x16_t) __builtin_aarch64_srshr_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshluh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqshlu_nhi_uss (__a, __b);
++  return (int16x8_t) __builtin_aarch64_srshr_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshlus_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqshlu_nsi_uss (__a, __b);
++  return (int32x4_t) __builtin_aarch64_srshr_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqshlud_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_ndi_uss (__a, __b);
++  return (int64x2_t) __builtin_aarch64_srshr_nv2di (__a, __b);
+ }
+ 
+-/* vqshrn */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqshrn_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqshrn_nv8hi (__a, __b);
++  return __builtin_aarch64_urshr_nv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqshrn_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqshrn_nv4si (__a, __b);
++  return __builtin_aarch64_urshr_nv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqshrn_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqshrn_nv2di (__a, __b);
++  return __builtin_aarch64_urshr_nv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshrn_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqshrn_nv8hi_uus ( __a, __b);
++  return __builtin_aarch64_urshr_nv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshrn_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqshrn_nv4si_uus ( __a, __b);
++  return __builtin_aarch64_srshr_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshrn_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqshrn_nv2di_uus ( __a, __b);
++  return __builtin_aarch64_urshr_ndi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshrnh_n_s16 (int16_t __a, const int __b)
++/* vrsqrte.  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtes_f32 (float32_t __a)
+ {
+-  return (int8_t) __builtin_aarch64_sqshrn_nhi (__a, __b);
++  return __builtin_aarch64_rsqrtesf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshrns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrted_f64 (float64_t __a)
+ {
+-  return (int16_t) __builtin_aarch64_sqshrn_nsi (__a, __b);
++  return __builtin_aarch64_rsqrtedf (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshrnd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f32 (float32x2_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_sqshrn_ndi (__a, __b);
++  return __builtin_aarch64_rsqrtev2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqshrnh_n_u16 (uint16_t __a, const int __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_uqshrn_nhi_uus (__a, __b);
++  return (float64x1_t) {vrsqrted_f64 (vget_lane_f64 (__a, 0))};
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqshrns_n_u32 (uint32_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshrn_nsi_uus (__a, __b);
++  return __builtin_aarch64_rsqrtev4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqshrnd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshrn_ndi_uus (__a, __b);
++  return __builtin_aarch64_rsqrtev2df (__a);
+ }
+ 
+-/* vqshrun */
++/* vrsqrts.  */
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshrun_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtss_f32 (float32_t __a, float32_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_sqshrun_nv8hi (__a, __b);
++  return __builtin_aarch64_rsqrtssf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshrun_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsd_f64 (float64_t __a, float64_t __b)
+ {
+-  return (uint16x4_t) __builtin_aarch64_sqshrun_nv4si (__a, __b);
++  return __builtin_aarch64_rsqrtsdf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshrun_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_sqshrun_nv2di (__a, __b);
++  return __builtin_aarch64_rsqrtsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshrunh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqshrun_nhi (__a, __b);
++  return (float64x1_t) {vrsqrtsd_f64 (vget_lane_f64 (__a, 0),
++				      vget_lane_f64 (__b, 0))};
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshruns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqshrun_nsi (__a, __b);
++  return __builtin_aarch64_rsqrtsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshrund_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqshrun_ndi (__a, __b);
++  return __builtin_aarch64_rsqrtsv2df (__a, __b);
+ }
+ 
+-/* vqsub */
++/* vrsra */
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqsubb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return (int8_t) __builtin_aarch64_sqsubqi (__a, __b);
++  return (int8x8_t) __builtin_aarch64_srsra_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqsubh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (int16_t) __builtin_aarch64_sqsubhi (__a, __b);
++  return (int16x4_t) __builtin_aarch64_srsra_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqsubs_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (int32_t) __builtin_aarch64_sqsubsi (__a, __b);
++  return (int32x2_t) __builtin_aarch64_srsra_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqsubd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_sqsubdi (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_srsra_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqsubb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return (uint8_t) __builtin_aarch64_uqsubqi_uuu (__a, __b);
++  return __builtin_aarch64_ursra_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqsubh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return (uint16_t) __builtin_aarch64_uqsubhi_uuu (__a, __b);
++  return __builtin_aarch64_ursra_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqsubs_u32 (uint32_t __a, uint32_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return (uint32_t) __builtin_aarch64_uqsubsi_uuu (__a, __b);
++  return __builtin_aarch64_ursra_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqsubd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_uqsubdi_uuu (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_ursra_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-/* vqtbl2 */
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++{
++  return (int8x16_t) __builtin_aarch64_srsra_nv16qi (__a, __b, __c);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl2_s8 (int8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
+-  return __builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return (int16x8_t) __builtin_aarch64_srsra_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl2_u8 (uint8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return (int32x4_t) __builtin_aarch64_srsra_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl2_p8 (poly8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return (int64x2_t) __builtin_aarch64_srsra_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl2q_s8 (int8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return __builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_ursra_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl2q_u8 (uint8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_ursra_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl2q_p8 (poly8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_ursra_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-/* vqtbl3 */
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++{
++  return __builtin_aarch64_ursra_nv2di_uuus (__a, __b, __c);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl3_s8 (int8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return __builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_srsra_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl3_u8 (uint8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_ursra_ndi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl3_p8 (poly8x16x3_t tab, uint8x8_t idx)
++#pragma GCC push_options
++#pragma GCC target ("+nothing+crypto")
++
++/* vsha1  */
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha1cv4si_uuuu (hash_abcd, hash_e, wk);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl3q_s8 (int8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return __builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha1mv4si_uuuu (hash_abcd, hash_e, wk);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl3q_u8 (uint8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha1pv4si_uuuu (hash_abcd, hash_e, wk);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1h_u32 (uint32_t hash_e)
++{
++  return __builtin_aarch64_crypto_sha1hsi_uu (hash_e);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl3q_p8 (poly8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha1su0v4si_uuuu (w0_3, w4_7, w8_11);
+ }
+ 
+-/* vqtbl4 */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl4_s8 (int8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return __builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha1su1v4si_uuu (tw0_3, w12_15);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl4_u8 (uint8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha256hv4si_uuuu (hash_abcd, hash_efgh, wk);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl4_p8 (poly8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha256h2v4si_uuuu (hash_efgh, hash_abcd, wk);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl4q_s8 (int8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return __builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha256su0v4si_uuu (w0_3, w4_7);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl4q_u8 (uint8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha256su1v4si_uuuu (tw0_3, w8_11, w12_15);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl4q_p8 (poly8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline poly128_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_p64 (poly64_t a, poly64_t b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
++  return
++    __builtin_aarch64_crypto_pmulldi_ppp (a, b);
+ }
+ 
+-
+-/* vqtbx2 */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx2_s8 (int8x8_t r, int8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline poly128_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_p64 (poly64x2_t a, poly64x2_t b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
+-  return __builtin_aarch64_tbx4v8qi (r, __o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_pmullv2di_ppp (a, b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx2_u8 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx)
++#pragma GCC pop_options
++
++/* vshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s8 (int8x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
+-						(int8x8_t)idx);
++  return (int8x8_t) __builtin_aarch64_ashlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx2_p8 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s16 (int16x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
+-						(int8x8_t)idx);
++  return (int16x4_t) __builtin_aarch64_ashlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx2q_s8 (int8x16_t r, int8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s32 (int32x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
+-  return __builtin_aarch64_tbx4v16qi (r, __o, (int8x16_t)idx);
++  return (int32x2_t) __builtin_aarch64_ashlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx2q_u8 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s64 (int64x1_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
+-						  (int8x16_t)idx);
++  return (int64x1_t) {__builtin_aarch64_ashldi (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx2q_p8 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
+-						  (int8x16_t)idx);
++  return (uint8x8_t) __builtin_aarch64_ashlv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-/* vqtbx3 */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx3_s8 (int8x8_t r, int8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
+-  return __builtin_aarch64_qtbx3v8qi (r, __o, (int8x8_t)idx);
++  return (uint16x4_t) __builtin_aarch64_ashlv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx3_u8 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint32x2_t) __builtin_aarch64_ashlv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx3_p8 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint64x1_t) {__builtin_aarch64_ashldi ((int64_t) __a[0], __b)};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx3q_s8 (int8x16_t r, int8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
+-  return __builtin_aarch64_qtbx3v16qi (r, __o, (int8x16_t)idx);
++  return (int8x16_t) __builtin_aarch64_ashlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx3q_u8 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return (int16x8_t) __builtin_aarch64_ashlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx3q_p8 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return (int32x4_t) __builtin_aarch64_ashlv4si (__a, __b);
+ }
+ 
+-/* vqtbx4 */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx4_s8 (int8x8_t r, int8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
+-  return __builtin_aarch64_qtbx4v8qi (r, __o, (int8x8_t)idx);
++  return (int64x2_t) __builtin_aarch64_ashlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx4_u8 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint8x16_t) __builtin_aarch64_ashlv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx4_p8 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint16x8_t) __builtin_aarch64_ashlv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx4q_s8 (int8x16_t r, int8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
+-  return __builtin_aarch64_qtbx4v16qi (r, __o, (int8x16_t)idx);
++  return (uint32x4_t) __builtin_aarch64_ashlv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx4q_u8 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return (uint64x2_t) __builtin_aarch64_ashlv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx4q_p8 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_n_s64 (int64_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return __builtin_aarch64_ashldi (__a, __b);
+ }
+ 
+-/* vrbit  */
+-
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrbit_p8 (poly8x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_n_u64 (uint64_t __a, const int __b)
+ {
+-  return (poly8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
++  return (uint64_t) __builtin_aarch64_ashldi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrbit_s8 (int8x8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_rbitv8qi (__a);
++  return __builtin_aarch64_sshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrbit_u8 (uint8x8_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
++  return __builtin_aarch64_sshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrbitq_p8 (poly8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return (poly8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t)__a);
++  return __builtin_aarch64_sshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrbitq_s8 (int8x16_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_rbitv16qi (__a);
++  return (int64x1_t) {__builtin_aarch64_sshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrbitq_u8 (uint8x16_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return (uint8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t) __a);
++  return __builtin_aarch64_ushlv8qi_uus (__a, __b);
+ }
+ 
+-/* vrecpe  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrecpe_u32 (uint32x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_urecpev2si ((int32x2_t) __a);
++  return __builtin_aarch64_ushlv4hi_uus (__a, __b);
+ }
+- 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrecpeq_u32 (uint32x4_t __a)
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return (uint32x4_t) __builtin_aarch64_urecpev4si ((int32x4_t) __a);
++  return __builtin_aarch64_ushlv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrecpes_f32 (float32_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_frecpesf (__a);
++  return (uint64x1_t) {__builtin_aarch64_ushldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrecped_f64 (float64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_frecpedf (__a);
++  return __builtin_aarch64_sshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrecpe_f32 (float32x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_frecpev2sf (__a);
++  return __builtin_aarch64_sshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrecpeq_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_frecpev4sf (__a);
++  return __builtin_aarch64_sshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrecpeq_f64 (float64x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_frecpev2df (__a);
++  return __builtin_aarch64_sshlv2di (__a, __b);
+ }
+ 
+-/* vrecps  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrecpss_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_frecpssf (__a, __b);
++  return __builtin_aarch64_ushlv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrecpsd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_frecpsdf (__a, __b);
++  return __builtin_aarch64_ushlv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrecps_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_frecpsv2sf (__a, __b);
++  return __builtin_aarch64_ushlv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrecpsq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_frecpsv4sf (__a, __b);
++  return __builtin_aarch64_ushlv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrecpsq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_frecpsv2df (__a, __b);
++  return __builtin_aarch64_sshldi (__a, __b);
+ }
+ 
+-/* vrecpx  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrecpxs_f32 (float32_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_frecpxsf (__a);
++  return __builtin_aarch64_ushldi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrecpxd_f64 (float64_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_frecpxdf (__a);
++  return __builtin_aarch64_sshll2_nv16qi (__a, __b);
+ }
+ 
+-
+-/* vrev  */
+-
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrev16_p8 (poly8x8_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return __builtin_aarch64_sshll2_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrev16_s8 (int8x8_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return __builtin_aarch64_sshll2_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrev16_u8 (uint8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (uint16x8_t) __builtin_aarch64_ushll2_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrev16q_p8 (poly8x16_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
++  return (uint32x4_t) __builtin_aarch64_ushll2_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrev16q_s8 (int8x16_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
++  return (uint64x2_t) __builtin_aarch64_ushll2_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrev16q_u8 (uint8x16_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
++  return __builtin_aarch64_sshll_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrev32_p8 (poly8x8_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_sshll_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vrev32_p16 (poly16x4_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_sshll_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrev32_s8 (int8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_ushll_nv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrev32_s16 (int16x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_ushll_nv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrev32_u8 (uint8x8_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_ushll_nv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrev32_u16 (uint16x4_t a)
++/* vshr */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
++  return (int8x8_t) __builtin_aarch64_ashrv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrev32q_p8 (poly8x16_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
++  return (int16x4_t) __builtin_aarch64_ashrv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vrev32q_p16 (poly16x8_t a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (int32x2_t) __builtin_aarch64_ashrv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrev32q_s8 (int8x16_t a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
++  return (int64x1_t) {__builtin_aarch64_ashr_simddi (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrev32q_s16 (int16x8_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (uint8x8_t) __builtin_aarch64_lshrv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrev32q_u8 (uint8x16_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
++  return (uint16x4_t) __builtin_aarch64_lshrv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrev32q_u16 (uint16x8_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (uint32x2_t) __builtin_aarch64_lshrv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrev64_f32 (float32x2_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
++  return (uint64x1_t) {__builtin_aarch64_lshr_simddi_uus ( __a[0], __b)};
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrev64_p8 (poly8x8_t a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
++  return (int8x16_t) __builtin_aarch64_ashrv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vrev64_p16 (poly16x4_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
++  return (int16x8_t) __builtin_aarch64_ashrv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrev64_s8 (int8x8_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
++  return (int32x4_t) __builtin_aarch64_ashrv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrev64_s16 (int16x4_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
++  return (int64x2_t) __builtin_aarch64_ashrv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrev64_s32 (int32x2_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
++  return (uint8x16_t) __builtin_aarch64_lshrv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrev64_u8 (uint8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
++  return (uint16x8_t) __builtin_aarch64_lshrv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrev64_u16 (uint16x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
++  return (uint32x4_t) __builtin_aarch64_lshrv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrev64_u32 (uint32x2_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
++  return (uint64x2_t) __builtin_aarch64_lshrv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrev64q_f32 (float32x4_t a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_ashr_simddi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrev64q_p8 (poly8x16_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
++  return __builtin_aarch64_lshr_simddi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vrev64q_p16 (poly16x8_t a)
++/* vsli */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return (int8x8_t) __builtin_aarch64_ssli_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrev64q_s8 (int8x16_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
++  return (int16x4_t) __builtin_aarch64_ssli_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrev64q_s16 (int16x8_t a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return (int32x2_t) __builtin_aarch64_ssli_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrev64q_s32 (int32x4_t a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
++  return (int64x1_t) {__builtin_aarch64_ssli_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrev64q_u8 (uint8x16_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
++  return __builtin_aarch64_usli_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrev64q_u16 (uint16x8_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_usli_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrev64q_u32 (uint32x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_usli_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-/* vrnd  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrnd_f32 (float32x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_btruncv2sf (__a);
++  return (uint64x1_t) {__builtin_aarch64_usli_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrnd_f64 (float64x1_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+-  return vset_lane_f64 (__builtin_trunc (vget_lane_f64 (__a, 0)), __a, 0);
++  return (poly64x1_t) {__builtin_aarch64_ssli_ndi_ppps (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndq_f32 (float32x4_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+-  return __builtin_aarch64_btruncv4sf (__a);
++  return (int8x16_t) __builtin_aarch64_ssli_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_btruncv2df (__a);
++  return (int16x8_t) __builtin_aarch64_ssli_nv8hi (__a, __b, __c);
+ }
+ 
+-/* vrnda  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++{
++  return (int32x4_t) __builtin_aarch64_ssli_nv4si (__a, __b, __c);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrnda_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_roundv2sf (__a);
++  return (int64x2_t) __builtin_aarch64_ssli_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrnda_f64 (float64x1_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  return vset_lane_f64 (__builtin_round (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_usli_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndaq_f32 (float32x4_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_roundv4sf (__a);
++  return __builtin_aarch64_usli_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndaq_f64 (float64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_roundv2df (__a);
++  return __builtin_aarch64_usli_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-/* vrndi  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndi_f32 (float32x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_nearbyintv2sf (__a);
++  return __builtin_aarch64_usli_nv2di_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndi_f64 (float64x1_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+-  return vset_lane_f64 (__builtin_nearbyint (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_ssli_nv2di_ppps (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndiq_f32 (float32x4_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vslid_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_nearbyintv4sf (__a);
++  return __builtin_aarch64_ssli_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndiq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vslid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_nearbyintv2df (__a);
++  return __builtin_aarch64_usli_ndi_uuus (__a, __b, __c);
+ }
+ 
+-/* vrndm  */
++/* vsqadd */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndm_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_floorv2sf (__a);
++  return __builtin_aarch64_usqaddv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndm_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return vset_lane_f64 (__builtin_floor (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_usqaddv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndmq_f32 (float32x4_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_floorv4sf (__a);
++  return __builtin_aarch64_usqaddv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndmq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_floorv2df (__a);
++  return (uint64x1_t) {__builtin_aarch64_usqadddi_uus (__a[0], __b[0])};
+ }
+ 
+-/* vrndn  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndn_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_frintnv2sf (__a);
++  return __builtin_aarch64_usqaddv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndn_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return (float64x1_t) {__builtin_aarch64_frintndf (__a[0])};
++  return __builtin_aarch64_usqaddv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndnq_f32 (float32x4_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_frintnv4sf (__a);
++  return __builtin_aarch64_usqaddv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndnq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_frintnv2df (__a);
++  return __builtin_aarch64_usqaddv2di_uus (__a, __b);
+ }
+ 
+-/* vrndp  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndp_f32 (float32x2_t __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddb_u8 (uint8_t __a, int8_t __b)
+ {
+-  return __builtin_aarch64_ceilv2sf (__a);
++  return __builtin_aarch64_usqaddqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndp_f64 (float64x1_t __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddh_u16 (uint16_t __a, int16_t __b)
+ {
+-  return vset_lane_f64 (__builtin_ceil (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_usqaddhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndpq_f32 (float32x4_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadds_u32 (uint32_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_ceilv4sf (__a);
++  return __builtin_aarch64_usqaddsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndpq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddd_u64 (uint64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_ceilv2df (__a);
++  return __builtin_aarch64_usqadddi_uus (__a, __b);
+ }
+ 
+-/* vrndx  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndx_f32 (float32x2_t __a)
++/* vsqrt */
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrt_f32 (float32x2_t a)
+ {
+-  return __builtin_aarch64_rintv2sf (__a);
++  return __builtin_aarch64_sqrtv2sf (a);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndx_f64 (float64x1_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrtq_f32 (float32x4_t a)
+ {
+-  return vset_lane_f64 (__builtin_rint (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_sqrtv4sf (a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndxq_f32 (float32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrt_f64 (float64x1_t a)
+ {
+-  return __builtin_aarch64_rintv4sf (__a);
++  return (float64x1_t) { __builtin_aarch64_sqrtdf (a[0]) };
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndxq_f64 (float64x2_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrtq_f64 (float64x2_t a)
+ {
+-  return __builtin_aarch64_rintv2df (__a);
++  return __builtin_aarch64_sqrtv2df (a);
+ }
+ 
+-/* vrshl */
++/* vsra */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return (int8x8_t) __builtin_aarch64_srshlv8qi (__a, __b);
++  return (int8x8_t) __builtin_aarch64_ssra_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (int16x4_t) __builtin_aarch64_srshlv4hi (__a, __b);
++  return (int16x4_t) __builtin_aarch64_ssra_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrshl_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (int32x2_t) __builtin_aarch64_srshlv2si (__a, __b);
++  return (int32x2_t) __builtin_aarch64_ssra_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vrshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return (int64x1_t) {__builtin_aarch64_srshldi (__a[0], __b[0])};
++  return (int64x1_t) {__builtin_aarch64_ssra_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv8qi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrshl_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv4hi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrshl_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv2si_uus (__a, __b);
++  return __builtin_aarch64_usra_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vrshl_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_urshldi_uus (__a[0], __b[0])};
++  return (uint64x1_t) {__builtin_aarch64_usra_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+-  return (int8x16_t) __builtin_aarch64_srshlv16qi (__a, __b);
++  return (int8x16_t) __builtin_aarch64_ssra_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrshlq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  return (int16x8_t) __builtin_aarch64_srshlv8hi (__a, __b);
++  return (int16x8_t) __builtin_aarch64_ssra_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrshlq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+-  return (int32x4_t) __builtin_aarch64_srshlv4si (__a, __b);
++  return (int32x4_t) __builtin_aarch64_ssra_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vrshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  return (int64x2_t) __builtin_aarch64_srshlv2di (__a, __b);
++  return (int64x2_t) __builtin_aarch64_ssra_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv16qi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv8hi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrshlq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv4si_uus (__a, __b);
++  return __builtin_aarch64_usra_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vrshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv2di_uus (__a, __b);
++  return __builtin_aarch64_usra_nv2di_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vrshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_srshldi (__a, __b);
++  return __builtin_aarch64_ssra_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vrshld_u64 (uint64_t __a, int64_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshldi_uus (__a, __b);
++  return __builtin_aarch64_usra_ndi_uuus (__a, __b, __c);
+ }
+ 
+-/* vrshr */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrshr_n_s8 (int8x8_t __a, const int __b)
+-{
+-  return (int8x8_t) __builtin_aarch64_srshr_nv8qi (__a, __b);
+-}
++/* vsri */
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrshr_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return (int16x4_t) __builtin_aarch64_srshr_nv4hi (__a, __b);
++  return (int8x8_t) __builtin_aarch64_ssri_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrshr_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (int32x2_t) __builtin_aarch64_srshr_nv2si (__a, __b);
++  return (int16x4_t) __builtin_aarch64_ssri_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vrshr_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (int64x1_t) {__builtin_aarch64_srshr_ndi (__a[0], __b)};
++  return (int32x2_t) __builtin_aarch64_ssri_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrshr_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv8qi_uus (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_ssri_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrshr_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv4hi_uus (__a, __b);
++  return __builtin_aarch64_usri_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrshr_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv2si_uus (__a, __b);
++  return __builtin_aarch64_usri_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vrshr_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_urshr_ndi_uus (__a[0], __b)};
++  return __builtin_aarch64_usri_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrshrq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return (int8x16_t) __builtin_aarch64_srshr_nv16qi (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_usri_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrshrq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+-  return (int16x8_t) __builtin_aarch64_srshr_nv8hi (__a, __b);
++  return (int8x16_t) __builtin_aarch64_ssri_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrshrq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  return (int32x4_t) __builtin_aarch64_srshr_nv4si (__a, __b);
++  return (int16x8_t) __builtin_aarch64_ssri_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vrshrq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+-  return (int64x2_t) __builtin_aarch64_srshr_nv2di (__a, __b);
++  return (int32x4_t) __builtin_aarch64_ssri_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrshrq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv16qi_uus (__a, __b);
++  return (int64x2_t) __builtin_aarch64_ssri_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrshrq_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv8hi_uus (__a, __b);
++  return __builtin_aarch64_usri_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrshrq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv4si_uus (__a, __b);
++  return __builtin_aarch64_usri_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vrshrq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv2di_uus (__a, __b);
++  return __builtin_aarch64_usri_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vrshrd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_srshr_ndi (__a, __b);
++  return __builtin_aarch64_usri_nv2di_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vrshrd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrid_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_ndi_uus (__a, __b);
++  return __builtin_aarch64_ssri_ndi (__a, __b, __c);
+ }
+ 
+-/* vrsra */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  return (int8x8_t) __builtin_aarch64_srsra_nv8qi (__a, __b, __c);
++  return __builtin_aarch64_usri_ndi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+-{
+-  return (int16x4_t) __builtin_aarch64_srsra_nv4hi (__a, __b, __c);
+-}
++/* vst1 */
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_f16 (float16_t *__a, float16x4_t __b)
+ {
+-  return (int32x2_t) __builtin_aarch64_srsra_nv2si (__a, __b, __c);
++  __builtin_aarch64_st1v4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_f32 (float32_t *a, float32x2_t b)
+ {
+-  return (int64x1_t) {__builtin_aarch64_srsra_ndi (__a[0], __b[0], __c)};
++  __builtin_aarch64_st1v2sf ((__builtin_aarch64_simd_sf *) a, b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_f64 (float64_t *a, float64x1_t b)
+ {
+-  return __builtin_aarch64_ursra_nv8qi_uuus (__a, __b, __c);
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_p8 (poly8_t *a, poly8x8_t b)
+ {
+-  return __builtin_aarch64_ursra_nv4hi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
++			     (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_p16 (poly16_t *a, poly16x4_t b)
+ {
+-  return __builtin_aarch64_ursra_nv2si_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_p64 (poly64_t *a, poly64x1_t b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_ursra_ndi_uuus (__a[0], __b[0], __c)};
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s8 (int8_t *a, int8x8_t b)
+ {
+-  return (int8x16_t) __builtin_aarch64_srsra_nv16qi (__a, __b, __c);
++  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a, b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s16 (int16_t *a, int16x4_t b)
+ {
+-  return (int16x8_t) __builtin_aarch64_srsra_nv8hi (__a, __b, __c);
++  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a, b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s32 (int32_t *a, int32x2_t b)
+ {
+-  return (int32x4_t) __builtin_aarch64_srsra_nv4si (__a, __b, __c);
++  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a, b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s64 (int64_t *a, int64x1_t b)
+ {
+-  return (int64x2_t) __builtin_aarch64_srsra_nv2di (__a, __b, __c);
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u8 (uint8_t *a, uint8x8_t b)
+ {
+-  return __builtin_aarch64_ursra_nv16qi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
++			     (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u16 (uint16_t *a, uint16x4_t b)
+ {
+-  return __builtin_aarch64_ursra_nv8hi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u32 (uint32_t *a, uint32x2_t b)
+ {
+-  return __builtin_aarch64_ursra_nv4si_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a,
++			     (int32x2_t) b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u64 (uint64_t *a, uint64x1_t b)
+ {
+-  return __builtin_aarch64_ursra_nv2di_uuus (__a, __b, __c);
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vrsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
++/* vst1q */
++
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_f16 (float16_t *__a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_srsra_ndi (__a, __b, __c);
++  __builtin_aarch64_st1v8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_f32 (float32_t *a, float32x4_t b)
+ {
+-  return __builtin_aarch64_ursra_ndi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v4sf ((__builtin_aarch64_simd_sf *) a, b);
+ }
+ 
+-#pragma GCC push_options
+-#pragma GCC target ("+nothing+crypto")
+-
+-/* vsha1  */
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_f64 (float64_t *a, float64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1cv4si_uuuu (hash_abcd, hash_e, wk);
++  __builtin_aarch64_st1v2df ((__builtin_aarch64_simd_df *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_p8 (poly8_t *a, poly8x16_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1mv4si_uuuu (hash_abcd, hash_e, wk);
++  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
++			      (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_p16 (poly16_t *a, poly16x8_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1pv4si_uuuu (hash_abcd, hash_e, wk);
++  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vsha1h_u32 (uint32_t hash_e)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_p64 (poly64_t *a, poly64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1hsi_uu (hash_e);
++  __builtin_aarch64_st1v2di_sp ((__builtin_aarch64_simd_di *) a,
++				(poly64x2_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s8 (int8_t *a, int8x16_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1su0v4si_uuuu (w0_3, w4_7, w8_11);
++  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s16 (int16_t *a, int16x8_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1su1v4si_uuu (tw0_3, w12_15);
++  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s32 (int32_t *a, int32x4_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256hv4si_uuuu (hash_abcd, hash_efgh, wk);
++  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s64 (int64_t *a, int64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256h2v4si_uuuu (hash_efgh, hash_abcd, wk);
++  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u8 (uint8_t *a, uint8x16_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256su0v4si_uuu (w0_3, w4_7);
++  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
++			      (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u16 (uint16_t *a, uint16x8_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256su1v4si_uuuu (tw0_3, w8_11, w12_15);
++  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_p64 (poly64_t a, poly64_t b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u32 (uint32_t *a, uint32x4_t b)
+ {
+-  return
+-    __builtin_aarch64_crypto_pmulldi_ppp (a, b);
++  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a,
++			     (int32x4_t) b);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_high_p64 (poly64x2_t a, poly64x2_t b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u64 (uint64_t *a, uint64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_pmullv2di_ppp (a, b);
++  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a,
++			     (int64x2_t) b);
+ }
+ 
+-#pragma GCC pop_options
++/* vst1_lane */
+ 
+-/* vshl */
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_f16 (float16_t *__a, float16x4_t __b, const int __lane)
++{
++  *__a = __aarch64_vget_lane_any (__b, __lane);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vshl_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_f32 (float32_t *__a, float32x2_t __b, const int __lane)
+ {
+-  return (int8x8_t) __builtin_aarch64_ashlv8qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vshl_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_f64 (float64_t *__a, float64x1_t __b, const int __lane)
+ {
+-  return (int16x4_t) __builtin_aarch64_ashlv4hi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vshl_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_p8 (poly8_t *__a, poly8x8_t __b, const int __lane)
+ {
+-  return (int32x2_t) __builtin_aarch64_ashlv2si (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vshl_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_p16 (poly16_t *__a, poly16x4_t __b, const int __lane)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ashldi (__a[0], __b)};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vshl_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_p64 (poly64_t *__a, poly64x1_t __b, const int __lane)
+ {
+-  return (uint8x8_t) __builtin_aarch64_ashlv8qi ((int8x8_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vshl_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s8 (int8_t *__a, int8x8_t __b, const int __lane)
+ {
+-  return (uint16x4_t) __builtin_aarch64_ashlv4hi ((int16x4_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vshl_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s16 (int16_t *__a, int16x4_t __b, const int __lane)
+ {
+-  return (uint32x2_t) __builtin_aarch64_ashlv2si ((int32x2_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vshl_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s32 (int32_t *__a, int32x2_t __b, const int __lane)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_ashldi ((int64_t) __a[0], __b)};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vshlq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s64 (int64_t *__a, int64x1_t __b, const int __lane)
+ {
+-  return (int8x16_t) __builtin_aarch64_ashlv16qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshlq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u8 (uint8_t *__a, uint8x8_t __b, const int __lane)
+ {
+-  return (int16x8_t) __builtin_aarch64_ashlv8hi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshlq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u16 (uint16_t *__a, uint16x4_t __b, const int __lane)
+ {
+-  return (int32x4_t) __builtin_aarch64_ashlv4si (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshlq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u32 (uint32_t *__a, uint32x2_t __b, const int __lane)
+ {
+-  return (int64x2_t) __builtin_aarch64_ashlv2di (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vshlq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u64 (uint64_t *__a, uint64x1_t __b, const int __lane)
+ {
+-  return (uint8x16_t) __builtin_aarch64_ashlv16qi ((int8x16_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshlq_n_u16 (uint16x8_t __a, const int __b)
++/* vst1q_lane */
++
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_f16 (float16_t *__a, float16x8_t __b, const int __lane)
+ {
+-  return (uint16x8_t) __builtin_aarch64_ashlv8hi ((int16x8_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshlq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_f32 (float32_t *__a, float32x4_t __b, const int __lane)
+ {
+-  return (uint32x4_t) __builtin_aarch64_ashlv4si ((int32x4_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshlq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_f64 (float64_t *__a, float64x2_t __b, const int __lane)
+ {
+-  return (uint64x2_t) __builtin_aarch64_ashlv2di ((int64x2_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vshld_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_p8 (poly8_t *__a, poly8x16_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ashldi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vshld_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_p16 (poly16_t *__a, poly16x8_t __b, const int __lane)
+ {
+-  return (uint64_t) __builtin_aarch64_ashldi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_p64 (poly64_t *__a, poly64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv8qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s8 (int8_t *__a, int8x16_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv4hi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vshl_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s16 (int16_t *__a, int16x8_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv2si (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s32 (int32_t *__a, int32x4_t __b, const int __lane)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sshldi (__a[0], __b[0])};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s64 (int64_t *__a, int64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ushlv8qi_uus (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vshl_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u8 (uint8_t *__a, uint8x16_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ushlv4hi_uus (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vshl_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u16 (uint16_t *__a, uint16x8_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ushlv2si_uus (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vshl_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u32 (uint32_t *__a, uint32x4_t __b, const int __lane)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_ushldi_uus (__a[0], __b[0])};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u64 (uint64_t *__a, uint64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv16qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshlq_s16 (int16x8_t __a, int16x8_t __b)
++/* vstn */
++
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s64 (int64_t * __a, int64x1x2_t val)
+ {
+-  return __builtin_aarch64_sshlv8hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int64x2x2_t temp;
++  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshlq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u64 (uint64_t * __a, uint64x1x2_t val)
+ {
+-  return __builtin_aarch64_sshlv4si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint64x2x2_t temp;
++  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_f64 (float64_t * __a, float64x1x2_t val)
+ {
+-  return __builtin_aarch64_sshlv2di (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  float64x2x2_t temp;
++  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s8 (int8_t * __a, int8x8x2_t val)
+ {
+-  return __builtin_aarch64_ushlv16qi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int8x16x2_t temp;
++  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_p8 (poly8_t * __a, poly8x8x2_t val)
+ {
+-  return __builtin_aarch64_ushlv8hi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  poly8x16x2_t temp;
++  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshlq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s16 (int16_t * __a, int16x4x2_t val)
+ {
+-  return __builtin_aarch64_ushlv4si_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int16x8x2_t temp;
++  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_p16 (poly16_t * __a, poly16x4x2_t val)
+ {
+-  return __builtin_aarch64_ushlv2di_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  poly16x8x2_t temp;
++  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s32 (int32_t * __a, int32x2x2_t val)
+ {
+-  return __builtin_aarch64_sshldi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int32x4x2_t temp;
++  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vshld_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u8 (uint8_t * __a, uint8x8x2_t val)
+ {
+-  return __builtin_aarch64_ushldi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint8x16x2_t temp;
++  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshll_high_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u16 (uint16_t * __a, uint16x4x2_t val)
+ {
+-  return __builtin_aarch64_sshll2_nv16qi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint16x8x2_t temp;
++  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshll_high_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u32 (uint32_t * __a, uint32x2x2_t val)
+ {
+-  return __builtin_aarch64_sshll2_nv8hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint32x4x2_t temp;
++  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshll_high_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_f16 (float16_t * __a, float16x4x2_t val)
+ {
+-  return __builtin_aarch64_sshll2_nv4si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  float16x8x2_t temp;
++  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[1], 1);
++  __builtin_aarch64_st2v4hf (__a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshll_high_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_f32 (float32_t * __a, float32x2x2_t val)
+ {
+-  return (uint16x8_t) __builtin_aarch64_ushll2_nv16qi ((int8x16_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  float32x4x2_t temp;
++  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[1], 1);
++  __builtin_aarch64_st2v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshll_high_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_p64 (poly64_t * __a, poly64x1x2_t val)
+ {
+-  return (uint32x4_t) __builtin_aarch64_ushll2_nv8hi ((int16x8_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  poly64x2x2_t temp;
++  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshll_high_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s8 (int8_t * __a, int8x16x2_t val)
+ {
+-  return (uint64x2_t) __builtin_aarch64_ushll2_nv4si ((int32x4_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshll_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_p8 (poly8_t * __a, poly8x16x2_t val)
+ {
+-  return __builtin_aarch64_sshll_nv8qi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshll_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s16 (int16_t * __a, int16x8x2_t val)
+ {
+-  return __builtin_aarch64_sshll_nv4hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshll_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_p16 (poly16_t * __a, poly16x8x2_t val)
+ {
+-  return __builtin_aarch64_sshll_nv2si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshll_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s32 (int32_t * __a, int32x4x2_t val)
+ {
+-  return __builtin_aarch64_ushll_nv8qi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
++  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshll_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s64 (int64_t * __a, int64x2x2_t val)
+ {
+-  return __builtin_aarch64_ushll_nv4hi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshll_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u8 (uint8_t * __a, uint8x16x2_t val)
+ {
+-  return __builtin_aarch64_ushll_nv2si_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-/* vshr */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vshr_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u16 (uint16_t * __a, uint16x8x2_t val)
+ {
+-  return (int8x8_t) __builtin_aarch64_ashrv8qi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vshr_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u32 (uint32_t * __a, uint32x4x2_t val)
+ {
+-  return (int16x4_t) __builtin_aarch64_ashrv4hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
++  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vshr_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u64 (uint64_t * __a, uint64x2x2_t val)
+ {
+-  return (int32x2_t) __builtin_aarch64_ashrv2si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vshr_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_f16 (float16_t * __a, float16x8x2_t val)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ashr_simddi (__a[0], __b)};
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[1], 1);
++  __builtin_aarch64_st2v8hf (__a, __o);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vshr_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_f32 (float32_t * __a, float32x4x2_t val)
+ {
+-  return (uint8x8_t) __builtin_aarch64_lshrv8qi ((int8x8_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[1], 1);
++  __builtin_aarch64_st2v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vshr_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_f64 (float64_t * __a, float64x2x2_t val)
+ {
+-  return (uint16x4_t) __builtin_aarch64_lshrv4hi ((int16x4_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vshr_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_p64 (poly64_t * __a, poly64x2x2_t val)
+ {
+-  return (uint32x2_t) __builtin_aarch64_lshrv2si ((int32x2_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vshr_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s64 (int64_t * __a, int64x1x3_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_lshr_simddi_uus ( __a[0], __b)};
++  __builtin_aarch64_simd_ci __o;
++  int64x2x3_t temp;
++  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vshrq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u64 (uint64_t * __a, uint64x1x3_t val)
+ {
+-  return (int8x16_t) __builtin_aarch64_ashrv16qi (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint64x2x3_t temp;
++  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshrq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_f64 (float64_t * __a, float64x1x3_t val)
+ {
+-  return (int16x8_t) __builtin_aarch64_ashrv8hi (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  float64x2x3_t temp;
++  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshrq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s8 (int8_t * __a, int8x8x3_t val)
+ {
+-  return (int32x4_t) __builtin_aarch64_ashrv4si (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  int8x16x3_t temp;
++  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshrq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_p8 (poly8_t * __a, poly8x8x3_t val)
+ {
+-  return (int64x2_t) __builtin_aarch64_ashrv2di (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  poly8x16x3_t temp;
++  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vshrq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s16 (int16_t * __a, int16x4x3_t val)
+ {
+-  return (uint8x16_t) __builtin_aarch64_lshrv16qi ((int8x16_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  int16x8x3_t temp;
++  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshrq_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_p16 (poly16_t * __a, poly16x4x3_t val)
+ {
+-  return (uint16x8_t) __builtin_aarch64_lshrv8hi ((int16x8_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  poly16x8x3_t temp;
++  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshrq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s32 (int32_t * __a, int32x2x3_t val)
+ {
+-  return (uint32x4_t) __builtin_aarch64_lshrv4si ((int32x4_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  int32x4x3_t temp;
++  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
++  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshrq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u8 (uint8_t * __a, uint8x8x3_t val)
+ {
+-  return (uint64x2_t) __builtin_aarch64_lshrv2di ((int64x2_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint8x16x3_t temp;
++  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vshrd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u16 (uint16_t * __a, uint16x4x3_t val)
+ {
+-  return __builtin_aarch64_ashr_simddi (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint16x8x3_t temp;
++  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vshrd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u32 (uint32_t * __a, uint32x2x3_t val)
+ {
+-  return __builtin_aarch64_lshr_simddi_uus (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint32x4x3_t temp;
++  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
++  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-/* vsli */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_f16 (float16_t * __a, float16x4x3_t val)
+ {
+-  return (int8x8_t) __builtin_aarch64_ssli_nv8qi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  float16x8x3_t temp;
++  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_f32 (float32_t * __a, float32x2x3_t val)
+ {
+-  return (int16x4_t) __builtin_aarch64_ssli_nv4hi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  float32x4x3_t temp;
++  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[2], 2);
++  __builtin_aarch64_st3v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_p64 (poly64_t * __a, poly64x1x3_t val)
+ {
+-  return (int32x2_t) __builtin_aarch64_ssli_nv2si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  poly64x2x3_t temp;
++  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p64 (val.val[2], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s8 (int8_t * __a, int8x16x3_t val)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ssli_ndi (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
++  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_p8 (poly8_t * __a, poly8x16x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv8qi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
++  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s16 (int16_t * __a, int16x8x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv4hi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_p16 (poly16_t * __a, poly16x8x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv2si_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s32 (int32_t * __a, int32x4x3_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usli_ndi_uuus (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
++  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s64 (int64_t * __a, int64x2x3_t val)
+ {
+-  return (int8x16_t) __builtin_aarch64_ssli_nv16qi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u8 (uint8_t * __a, uint8x16x3_t val)
+ {
+-  return (int16x8_t) __builtin_aarch64_ssli_nv8hi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
++  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u16 (uint16_t * __a, uint16x8x3_t val)
+ {
+-  return (int32x4_t) __builtin_aarch64_ssli_nv4si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u32 (uint32_t * __a, uint32x4x3_t val)
+ {
+-  return (int64x2_t) __builtin_aarch64_ssli_nv2di (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
++  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u64 (uint64_t * __a, uint64x2x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv16qi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_f16 (float16_t * __a, float16x8x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv8hi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_f32 (float32_t * __a, float32x4x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv4si_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[2], 2);
++  __builtin_aarch64_st3v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_f64 (float64_t * __a, float64x2x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv2di_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vslid_n_s64 (int64_t __a, int64_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_p64 (poly64_t * __a, poly64x2x3_t val)
+ {
+-  return __builtin_aarch64_ssli_ndi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vslid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s64 (int64_t * __a, int64x1x4_t val)
+ {
+-  return __builtin_aarch64_usli_ndi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  int64x2x4_t temp;
++  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-/* vsqadd */
+-
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsqadd_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u64 (uint64_t * __a, uint64x1x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv8qi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint64x2x4_t temp;
++  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsqadd_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_f64 (float64_t * __a, float64x1x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv4hi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  float64x2x4_t temp;
++  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsqadd_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s8 (int8_t * __a, int8x8x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv2si_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  int8x16x4_t temp;
++  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
++  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsqadd_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_p8 (poly8_t * __a, poly8x8x4_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usqadddi_uus (__a[0], __b[0])};
++  __builtin_aarch64_simd_xi __o;
++  poly8x16x4_t temp;
++  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
++  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsqaddq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s16 (int16_t * __a, int16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv16qi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  int16x8x4_t temp;
++  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsqaddq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_p16 (poly16_t * __a, poly16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv8hi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  poly16x8x4_t temp;
++  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsqaddq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s32 (int32_t * __a, int32x2x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv4si_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  int32x4x4_t temp;
++  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
++  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsqaddq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u8 (uint8_t * __a, uint8x8x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv2di_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint8x16x4_t temp;
++  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
++  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vsqaddb_u8 (uint8_t __a, int8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u16 (uint16_t * __a, uint16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddqi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint16x8x4_t temp;
++  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vsqaddh_u16 (uint16_t __a, int16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u32 (uint32_t * __a, uint32x2x4_t val)
+ {
+-  return __builtin_aarch64_usqaddhi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint32x4x4_t temp;
++  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
++  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vsqadds_u32 (uint32_t __a, int32_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_f16 (float16_t * __a, float16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddsi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  float16x8x4_t temp;
++  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_f16 (val.val[3], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsqaddd_u64 (uint64_t __a, int64_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_f32 (float32_t * __a, float32x2x4_t val)
+ {
+-  return __builtin_aarch64_usqadddi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  float32x4x4_t temp;
++  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[3], 3);
++  __builtin_aarch64_st4v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-/* vsqrt */
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vsqrt_f32 (float32x2_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_p64 (poly64_t * __a, poly64x1x4_t val)
+ {
+-  return __builtin_aarch64_sqrtv2sf (a);
++  __builtin_aarch64_simd_xi __o;
++  poly64x2x4_t temp;
++  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p64 (val.val[2], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_p64 (val.val[3], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vsqrtq_f32 (float32x4_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s8 (int8_t * __a, int8x16x4_t val)
+ {
+-  return __builtin_aarch64_sqrtv4sf (a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
++  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vsqrt_f64 (float64x1_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_p8 (poly8_t * __a, poly8x16x4_t val)
+ {
+-  return (float64x1_t) { __builtin_aarch64_sqrtdf (a[0]) };
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
++  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vsqrtq_f64 (float64x2_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s16 (int16_t * __a, int16x8x4_t val)
+ {
+-  return __builtin_aarch64_sqrtv2df (a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-/* vsra */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_p16 (poly16_t * __a, poly16x8x4_t val)
+ {
+-  return (int8x8_t) __builtin_aarch64_ssra_nv8qi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s32 (int32_t * __a, int32x4x4_t val)
+ {
+-  return (int16x4_t) __builtin_aarch64_ssra_nv4hi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
++  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s64 (int64_t * __a, int64x2x4_t val)
+ {
+-  return (int32x2_t) __builtin_aarch64_ssra_nv2si (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u8 (uint8_t * __a, uint8x16x4_t val)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ssra_ndi (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
++  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u16 (uint16_t * __a, uint16x8x4_t val)
+ {
+-  return __builtin_aarch64_usra_nv8qi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u32 (uint32_t * __a, uint32x4x4_t val)
+ {
+-  return __builtin_aarch64_usra_nv4hi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
++  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u64 (uint64_t * __a, uint64x2x4_t val)
+ {
+-  return __builtin_aarch64_usra_nv2si_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_f16 (float16_t * __a, float16x8x4_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usra_ndi_uuus (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_f32 (float32_t * __a, float32x4x4_t val)
+ {
+-  return (int8x16_t) __builtin_aarch64_ssra_nv16qi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[3], 3);
++  __builtin_aarch64_st4v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_f64 (float64_t * __a, float64x2x4_t val)
+ {
+-  return (int16x8_t) __builtin_aarch64_ssra_nv8hi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_p64 (poly64_t * __a, poly64x2x4_t val)
+ {
+-  return (int32x4_t) __builtin_aarch64_ssra_nv4si (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+-{
+-  return (int64x2_t) __builtin_aarch64_ssra_nv2di (__a, __b, __c);
+-}
++/* vsub */
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsubd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_usra_nv16qi_uuus (__a, __b, __c);
++  return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsubd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_usra_nv8hi_uuus (__a, __b, __c);
++  return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+-{
+-  return __builtin_aarch64_usra_nv4si_uuus (__a, __b, __c);
+-}
++/* vtbx1  */
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx1_s8 (int8x8_t __r, int8x8_t __tab, int8x8_t __idx)
+ {
+-  return __builtin_aarch64_usra_nv2di_uuus (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
++			      vmov_n_u8 (8));
++  int8x8_t __tbl = vtbl1_s8 (__tab, __idx);
++
++  return vbsl_s8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx1_u8 (uint8x8_t __r, uint8x8_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_ssra_ndi (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
++  uint8x8_t __tbl = vtbl1_u8 (__tab, __idx);
++
++  return vbsl_u8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx1_p8 (poly8x8_t __r, poly8x8_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_usra_ndi_uuus (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
++  poly8x8_t __tbl = vtbl1_p8 (__tab, __idx);
++
++  return vbsl_p8 (__mask, __tbl, __r);
+ }
+ 
+-/* vsri */
++/* vtbx3  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx3_s8 (int8x8_t __r, int8x8x3_t __tab, int8x8_t __idx)
+ {
+-  return (int8x8_t) __builtin_aarch64_ssri_nv8qi (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
++			      vmov_n_u8 (24));
++  int8x8_t __tbl = vtbl3_s8 (__tab, __idx);
++
++  return vbsl_s8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx3_u8 (uint8x8_t __r, uint8x8x3_t __tab, uint8x8_t __idx)
+ {
+-  return (int16x4_t) __builtin_aarch64_ssri_nv4hi (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
++  uint8x8_t __tbl = vtbl3_u8 (__tab, __idx);
++
++  return vbsl_u8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx3_p8 (poly8x8_t __r, poly8x8x3_t __tab, uint8x8_t __idx)
+ {
+-  return (int32x2_t) __builtin_aarch64_ssri_nv2si (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
++  poly8x8_t __tbl = vtbl3_p8 (__tab, __idx);
++
++  return vbsl_p8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++/* vtbx4  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx4_s8 (int8x8_t __r, int8x8x4_t __tab, int8x8_t __idx)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ssri_ndi (__a[0], __b[0], __c)};
++  int8x8_t result;
++  int8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_s8 (__tab.val[0], __tab.val[1]);
++  temp.val[1] = vcombine_s8 (__tab.val[2], __tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = __builtin_aarch64_tbx4v8qi (__r, __o, __idx);
++  return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx4_u8 (uint8x8_t __r, uint8x8x4_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_usri_nv8qi_uuus (__a, __b, __c);
++  uint8x8_t result;
++  uint8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_u8 (__tab.val[0], __tab.val[1]);
++  temp.val[1] = vcombine_u8 (__tab.val[2], __tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
++						  (int8x8_t)__idx);
++  return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx4_p8 (poly8x8_t __r, poly8x8x4_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_usri_nv4hi_uuus (__a, __b, __c);
++  poly8x8_t result;
++  poly8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_p8 (__tab.val[0], __tab.val[1]);
++  temp.val[1] = vcombine_p8 (__tab.val[2], __tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
++						  (int8x8_t)__idx);
++  return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++/* vtrn */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_usri_nv2si_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usri_ndi_uuus (__a[0], __b[0], __c)};
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  return (int8x16_t) __builtin_aarch64_ssri_nv16qi (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  return (int16x8_t) __builtin_aarch64_ssri_nv8hi (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return (int32x4_t) __builtin_aarch64_ssri_nv4si (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (int64x2_t) __builtin_aarch64_ssri_nv2di (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_usri_nv16qi_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  return __builtin_aarch64_usri_nv8hi_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  return __builtin_aarch64_usri_nv4si_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  return __builtin_aarch64_usri_nv2di_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vsrid_n_s64 (int64_t __a, int64_t __b, const int __c)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_ssri_ndi (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsrid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __builtin_aarch64_usri_ndi_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-/* vst1 */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_f16 (float16_t *__a, float16x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_st1v4hf (__a, __b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_f32 (float32_t *a, float32x2_t b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_st1v2sf ((__builtin_aarch64_simd_sf *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_f64 (float64_t *a, float64x1_t b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  *a = b[0];
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_p8 (poly8_t *a, poly8x8_t b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
+-			     (int8x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_p16 (poly16_t *a, poly16x4_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x4_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s8 (int8_t *a, int8x8_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s16 (int16_t *a, int16x4_t b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s32 (int32_t *a, int32x2_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s64 (int64_t *a, int64x1_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  *a = b[0];
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u8 (uint8_t *a, uint8x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
+-			     (int8x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u16 (uint16_t *a, uint16x4_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x4_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u32 (uint32_t *a, uint32x2_t b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a,
+-			     (int32x2_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u64 (uint64_t *a, uint64x1_t b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  *a = b[0];
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-/* vst1q */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_f16 (float16_t *__a, float16x8_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  __builtin_aarch64_st1v8hf (__a, __b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_f32 (float32_t *a, float32x4_t b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  __builtin_aarch64_st1v4sf ((__builtin_aarch64_simd_sf *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_f64 (float64_t *a, float64x2_t b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_st1v2df ((__builtin_aarch64_simd_df *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_p8 (poly8_t *a, poly8x16_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
+-			      (int8x16_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_p16 (poly16_t *a, poly16x8_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s8 (int8_t *a, int8x16_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s16 (int16_t *a, int16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s32 (int32_t *a, int32x4_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s64 (int64_t *a, int64x2_t b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u8 (uint8_t *a, uint8x16_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
+-			      (int8x16_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u16 (uint16_t *a, uint16x8_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u32 (uint32_t *a, uint32x4_t b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a,
+-			     (int32x4_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u64 (uint64_t *a, uint64x2_t b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a,
+-			     (int64x2_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-/* vst1_lane */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_f16 (float16_t *__a, float16x4_t __b, const int __lane)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_f32 (float32_t *__a, float32x2_t __b, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_f64 (float64_t *__a, float64x1_t __b, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_p8 (poly8_t *__a, poly8x8_t __b, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_p16 (poly16_t *__a, poly16x4_t __b, const int __lane)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s8 (int8_t *__a, int8x8_t __b, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s16 (int16_t *__a, int16x4_t __b, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s32 (int32_t *__a, int32x2_t __b, const int __lane)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s64 (int64_t *__a, int64x1_t __b, const int __lane)
++__extension__ extern __inline float16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float16x4x2_t) {vtrn1_f16 (__a, __b), vtrn2_f16 (__a, __b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u8 (uint8_t *__a, uint8x8_t __b, const int __lane)
++__extension__ extern __inline float32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_f32 (float32x2_t a, float32x2_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float32x2x2_t) {vtrn1_f32 (a, b), vtrn2_f32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u16 (uint16_t *__a, uint16x4_t __b, const int __lane)
++__extension__ extern __inline poly8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_p8 (poly8x8_t a, poly8x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly8x8x2_t) {vtrn1_p8 (a, b), vtrn2_p8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u32 (uint32_t *__a, uint32x2_t __b, const int __lane)
++__extension__ extern __inline poly16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_p16 (poly16x4_t a, poly16x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly16x4x2_t) {vtrn1_p16 (a, b), vtrn2_p16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u64 (uint64_t *__a, uint64x1_t __b, const int __lane)
++__extension__ extern __inline int8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_s8 (int8x8_t a, int8x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int8x8x2_t) {vtrn1_s8 (a, b), vtrn2_s8 (a, b)};
+ }
+ 
+-/* vst1q_lane */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_f16 (float16_t *__a, float16x8_t __b, const int __lane)
++__extension__ extern __inline int16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_s16 (int16x4_t a, int16x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int16x4x2_t) {vtrn1_s16 (a, b), vtrn2_s16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_f32 (float32_t *__a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_s32 (int32x2_t a, int32x2_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int32x2x2_t) {vtrn1_s32 (a, b), vtrn2_s32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_f64 (float64_t *__a, float64x2_t __b, const int __lane)
++__extension__ extern __inline uint8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_u8 (uint8x8_t a, uint8x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint8x8x2_t) {vtrn1_u8 (a, b), vtrn2_u8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_p8 (poly8_t *__a, poly8x16_t __b, const int __lane)
++__extension__ extern __inline uint16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_u16 (uint16x4_t a, uint16x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint16x4x2_t) {vtrn1_u16 (a, b), vtrn2_u16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_p16 (poly16_t *__a, poly16x8_t __b, const int __lane)
++__extension__ extern __inline uint32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint32x2x2_t) {vtrn1_u32 (a, b), vtrn2_u32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s8 (int8_t *__a, int8x16_t __b, const int __lane)
++__extension__ extern __inline float16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float16x8x2_t) {vtrn1q_f16 (__a, __b), vtrn2q_f16 (__a, __b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s16 (int16_t *__a, int16x8_t __b, const int __lane)
++__extension__ extern __inline float32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float32x4x2_t) {vtrn1q_f32 (a, b), vtrn2q_f32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s32 (int32_t *__a, int32x4_t __b, const int __lane)
++__extension__ extern __inline poly8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_p8 (poly8x16_t a, poly8x16_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly8x16x2_t) {vtrn1q_p8 (a, b), vtrn2q_p8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s64 (int64_t *__a, int64x2_t __b, const int __lane)
++__extension__ extern __inline poly16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_p16 (poly16x8_t a, poly16x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly16x8x2_t) {vtrn1q_p16 (a, b), vtrn2q_p16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u8 (uint8_t *__a, uint8x16_t __b, const int __lane)
++__extension__ extern __inline int8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int8x16x2_t) {vtrn1q_s8 (a, b), vtrn2q_s8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u16 (uint16_t *__a, uint16x8_t __b, const int __lane)
++__extension__ extern __inline int16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_s16 (int16x8_t a, int16x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int16x8x2_t) {vtrn1q_s16 (a, b), vtrn2q_s16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u32 (uint32_t *__a, uint32x4_t __b, const int __lane)
++__extension__ extern __inline int32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_s32 (int32x4_t a, int32x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int32x4x2_t) {vtrn1q_s32 (a, b), vtrn2q_s32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u64 (uint64_t *__a, uint64x2_t __b, const int __lane)
++__extension__ extern __inline uint8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint8x16x2_t) {vtrn1q_u8 (a, b), vtrn2q_u8 (a, b)};
+ }
+ 
+-/* vstn */
+-
+-__extension__ static __inline void
+-vst2_s64 (int64_t * __a, int64x1x2_t val)
++__extension__ extern __inline uint16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_u16 (uint16x8_t a, uint16x8_t b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int64x2x2_t temp;
+-  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return (uint16x8x2_t) {vtrn1q_u16 (a, b), vtrn2q_u16 (a, b)};
+ }
+ 
+-__extension__ static __inline void
+-vst2_u64 (uint64_t * __a, uint64x1x2_t val)
++__extension__ extern __inline uint32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint64x2x2_t temp;
+-  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return (uint32x4x2_t) {vtrn1q_u32 (a, b), vtrn2q_u32 (a, b)};
+ }
+ 
+-__extension__ static __inline void
+-vst2_f64 (float64_t * __a, float64x1x2_t val)
+-{
+-  __builtin_aarch64_simd_oi __o;
+-  float64x2x2_t temp;
+-  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[1], 1);
+-  __builtin_aarch64_st2df ((__builtin_aarch64_simd_df *) __a, __o);
+-}
++/* vtst */
+ 
+-__extension__ static __inline void
+-vst2_s8 (int8_t * __a, int8x8x2_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int8x16x2_t temp;
+-  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint8x8_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_p8 (poly8_t * __a, poly8x8x2_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  poly8x16x2_t temp;
+-  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint16x4_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_s16 (int16_t * __a, int16x4x2_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int16x8x2_t temp;
+-  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return (uint32x2_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_p16 (poly16_t * __a, poly16x4x2_t val)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  poly16x8x2_t temp;
+-  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return (uint64x1_t) ((__a & __b) != __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_s32 (int32_t * __a, int32x2x2_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int32x4x2_t temp;
+-  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_u8 (uint8_t * __a, uint8x8x2_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint8x16x2_t temp;
+-  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_u16 (uint16_t * __a, uint16x4x2_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint16x8x2_t temp;
+-  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_u32 (uint32_t * __a, uint32x2x2_t val)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint32x4x2_t temp;
+-  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
++  return ((__a & __b) != __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_f16 (float16_t * __a, float16x4x2_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  float16x8x2_t temp;
+-  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[1], 1);
+-  __builtin_aarch64_st2v4hf (__a, __o);
++  return (uint8x16_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_f32 (float32_t * __a, float32x2x2_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  float32x4x2_t temp;
+-  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
++  return (uint16x8_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s8 (int8_t * __a, int8x16x2_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint32x4_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_p8 (poly8_t * __a, poly8x16x2_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint64x2_t) ((__a & __b) != __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s16 (int16_t * __a, int16x8x2_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_p16 (poly16_t * __a, poly16x8x2_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s32 (int32_t * __a, int32x4x2_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s64 (int64_t * __a, int64x2x2_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return ((__a & __b) != __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u8 (uint8_t * __a, uint8x16x2_t val)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstd_s64 (int64_t __a, int64_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (__a & __b) ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u16 (uint16_t * __a, uint16x8x2_t val)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return (__a & __b) ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u32 (uint32_t * __a, uint32x4x2_t val)
++/* vuqadd */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s8 (int8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
++  return __builtin_aarch64_suqaddv8qi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u64 (uint64_t * __a, uint64x2x2_t val)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s16 (int16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return __builtin_aarch64_suqaddv4hi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_f16 (float16_t * __a, float16x8x2_t val)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s32 (int32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[1], 1);
+-  __builtin_aarch64_st2v8hf (__a, __o);
++  return __builtin_aarch64_suqaddv2si_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_f32 (float32_t * __a, float32x4x2_t val)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s64 (int64x1_t __a, uint64x1_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[1], 1);
+-  __builtin_aarch64_st2v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
++  return (int64x1_t) {__builtin_aarch64_suqadddi_ssu (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_f64 (float64_t * __a, float64x2x2_t val)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s8 (int8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[1], 1);
+-  __builtin_aarch64_st2v2df ((__builtin_aarch64_simd_df *) __a, __o);
++  return __builtin_aarch64_suqaddv16qi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_s64 (int64_t * __a, int64x1x3_t val)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s16 (int16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int64x2x3_t temp;
+-  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
++  return __builtin_aarch64_suqaddv8hi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_u64 (uint64_t * __a, uint64x1x3_t val)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s32 (int32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint64x2x3_t temp;
+-  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
++  return __builtin_aarch64_suqaddv4si_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_f64 (float64_t * __a, float64x1x3_t val)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s64 (int64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  float64x2x3_t temp;
+-  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[2], 2);
+-  __builtin_aarch64_st3df ((__builtin_aarch64_simd_df *) __a, __o);
++  return __builtin_aarch64_suqaddv2di_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_s8 (int8_t * __a, int8x8x3_t val)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddb_s8 (int8_t __a, uint8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int8x16x3_t temp;
+-  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return __builtin_aarch64_suqaddqi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_p8 (poly8_t * __a, poly8x8x3_t val)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddh_s16 (int16_t __a, uint16_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  poly8x16x3_t temp;
+-  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return __builtin_aarch64_suqaddhi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_s16 (int16_t * __a, int16x4x3_t val)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadds_s32 (int32_t __a, uint32_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int16x8x3_t temp;
+-  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return __builtin_aarch64_suqaddsi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_p16 (poly16_t * __a, poly16x4x3_t val)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddd_s64 (int64_t __a, uint64_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  poly16x8x3_t temp;
+-  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return __builtin_aarch64_suqadddi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_s32 (int32_t * __a, int32x2x3_t val)
++#define __DEFINTERLEAVE(op, rettype, intype, funcsuffix, Q) 		\
++  __extension__ extern __inline rettype					\
++  __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++  v ## op ## Q ## _ ## funcsuffix (intype a, intype b)			\
++  {									\
++    return (rettype) {v ## op ## 1 ## Q ## _ ## funcsuffix (a, b),	\
++		      v ## op ## 2 ## Q ## _ ## funcsuffix (a, b)};	\
++  }
++
++#define __INTERLEAVE_LIST(op)					\
++  __DEFINTERLEAVE (op, float16x4x2_t, float16x4_t, f16,)	\
++  __DEFINTERLEAVE (op, float32x2x2_t, float32x2_t, f32,)	\
++  __DEFINTERLEAVE (op, poly8x8x2_t, poly8x8_t, p8,)		\
++  __DEFINTERLEAVE (op, poly16x4x2_t, poly16x4_t, p16,)		\
++  __DEFINTERLEAVE (op, int8x8x2_t, int8x8_t, s8,)		\
++  __DEFINTERLEAVE (op, int16x4x2_t, int16x4_t, s16,)		\
++  __DEFINTERLEAVE (op, int32x2x2_t, int32x2_t, s32,)		\
++  __DEFINTERLEAVE (op, uint8x8x2_t, uint8x8_t, u8,)		\
++  __DEFINTERLEAVE (op, uint16x4x2_t, uint16x4_t, u16,)		\
++  __DEFINTERLEAVE (op, uint32x2x2_t, uint32x2_t, u32,)		\
++  __DEFINTERLEAVE (op, float16x8x2_t, float16x8_t, f16, q)	\
++  __DEFINTERLEAVE (op, float32x4x2_t, float32x4_t, f32, q)	\
++  __DEFINTERLEAVE (op, poly8x16x2_t, poly8x16_t, p8, q)		\
++  __DEFINTERLEAVE (op, poly16x8x2_t, poly16x8_t, p16, q)	\
++  __DEFINTERLEAVE (op, int8x16x2_t, int8x16_t, s8, q)		\
++  __DEFINTERLEAVE (op, int16x8x2_t, int16x8_t, s16, q)		\
++  __DEFINTERLEAVE (op, int32x4x2_t, int32x4_t, s32, q)		\
++  __DEFINTERLEAVE (op, uint8x16x2_t, uint8x16_t, u8, q)		\
++  __DEFINTERLEAVE (op, uint16x8x2_t, uint16x8_t, u16, q)	\
++  __DEFINTERLEAVE (op, uint32x4x2_t, uint32x4_t, u32, q)
++
++/* vuzp */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int32x4x3_t temp;
+-  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_u8 (uint8_t * __a, uint8x8x3_t val)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint8x16x3_t temp;
+-  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_u16 (uint16_t * __a, uint16x4x3_t val)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint16x8x3_t temp;
+-  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_u32 (uint32_t * __a, uint32x2x3_t val)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint32x4x3_t temp;
+-  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_f16 (float16_t * __a, float16x4x3_t val)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  float16x8x3_t temp;
+-  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_f32 (float32_t * __a, float32x2x3_t val)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  float32x4x3_t temp;
+-  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s8 (int8_t * __a, int8x16x3_t val)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_p8 (poly8_t * __a, poly8x16x3_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s16 (int16_t * __a, int16x8x3_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_p16 (poly16_t * __a, poly16x8x3_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s32 (int32_t * __a, int32x4x3_t val)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
+-  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s64 (int64_t * __a, int64x2x3_t val)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
+-  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u8 (uint8_t * __a, uint8x16x3_t val)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u16 (uint16_t * __a, uint16x8x3_t val)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u32 (uint32_t * __a, uint32x4x3_t val)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
+-  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u64 (uint64_t * __a, uint64x2x3_t val)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
+-  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_f16 (float16_t * __a, float16x8x3_t val)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_f32 (float32_t * __a, float32x4x3_t val)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[2], 2);
+-  __builtin_aarch64_st3v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_f64 (float64_t * __a, float64x2x3_t val)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[2], 2);
+-  __builtin_aarch64_st3v2df ((__builtin_aarch64_simd_df *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_s64 (int64_t * __a, int64x1x4_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int64x2x4_t temp;
+-  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
+-  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_u64 (uint64_t * __a, uint64x1x4_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint64x2x4_t temp;
+-  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
+-  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_f64 (float64_t * __a, float64x1x4_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  float64x2x4_t temp;
+-  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[3], 3);
+-  __builtin_aarch64_st4df ((__builtin_aarch64_simd_df *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_s8 (int8_t * __a, int8x8x4_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int8x16x4_t temp;
+-  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_f16 (float16x4_t __a, float16x4_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_p8 (poly8_t * __a, poly8x8x4_t val)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  poly8x16x4_t temp;
+-  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_s16 (int16_t * __a, int16x4x4_t val)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int16x8x4_t temp;
+-  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_p16 (poly16_t * __a, poly16x4x4_t val)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  poly16x8x4_t temp;
+-  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_s32 (int32_t * __a, int32x2x4_t val)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int32x4x4_t temp;
+-  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_u8 (uint8_t * __a, uint8x8x4_t val)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint8x16x4_t temp;
+-  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_u16 (uint16_t * __a, uint16x4x4_t val)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint16x8x4_t temp;
+-  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_u32 (uint32_t * __a, uint32x2x4_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint32x4x4_t temp;
+-  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_f16 (float16_t * __a, float16x4x4_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  float16x8x4_t temp;
+-  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_f16 (val.val[3], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_f32 (float32_t * __a, float32x2x4_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  float32x4x4_t temp;
+-  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s8 (int8_t * __a, int8x16x4_t val)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
+-  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_p8 (poly8_t * __a, poly8x16x4_t val)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
+-  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s16 (int16_t * __a, int16x8x4_t val)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_p16 (poly16_t * __a, poly16x8x4_t val)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s32 (int32_t * __a, int32x4x4_t val)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
+-  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s64 (int64_t * __a, int64x2x4_t val)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
+-  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u8 (uint8_t * __a, uint8x16x4_t val)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
+-  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u16 (uint16_t * __a, uint16x8x4_t val)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u32 (uint32_t * __a, uint32x4x4_t val)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
+-  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u64 (uint64_t * __a, uint64x2x4_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
+-  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_f16 (float16_t * __a, float16x8x4_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_f32 (float32_t * __a, float32x4x4_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[3], 3);
+-  __builtin_aarch64_st4v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_f64 (float64_t * __a, float64x2x4_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[3], 3);
+-  __builtin_aarch64_st4v2df ((__builtin_aarch64_simd_df *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-/* vsub */
++__INTERLEAVE_LIST (uzp)
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vsubd_s64 (int64_t __a, int64_t __b)
++/* vzip */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __a - __b;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsubd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __a - __b;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-/* vtbx1  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx1_s8 (int8x8_t __r, int8x8_t __tab, int8x8_t __idx)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
+-			      vmov_n_u8 (8));
+-  int8x8_t __tbl = vtbl1_s8 (__tab, __idx);
+-
+-  return vbsl_s8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx1_u8 (uint8x8_t __r, uint8x8_t __tab, uint8x8_t __idx)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
+-  uint8x8_t __tbl = vtbl1_u8 (__tab, __idx);
+-
+-  return vbsl_u8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx1_p8 (poly8x8_t __r, poly8x8_t __tab, uint8x8_t __idx)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
+-  poly8x8_t __tbl = vtbl1_p8 (__tab, __idx);
+-
+-  return vbsl_p8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
+ }
+ 
+-/* vtbx3  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx3_s8 (int8x8_t __r, int8x8x3_t __tab, int8x8_t __idx)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
+-			      vmov_n_u8 (24));
+-  int8x8_t __tbl = vtbl3_s8 (__tab, __idx);
+-
+-  return vbsl_s8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx3_u8 (uint8x8_t __r, uint8x8x3_t __tab, uint8x8_t __idx)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
+-  uint8x8_t __tbl = vtbl3_u8 (__tab, __idx);
+-
+-  return vbsl_u8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx3_p8 (poly8x8_t __r, poly8x8x3_t __tab, uint8x8_t __idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
+-  poly8x8_t __tbl = vtbl3_p8 (__tab, __idx);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
++}
+ 
+-  return vbsl_p8 (__mask, __tbl, __r);
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_u16 (uint16x4_t __a, uint16x4_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-/* vtbx4  */
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_u32 (uint32x2_t __a, uint32x2_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx4_s8 (int8x8_t __r, int8x8x4_t __tab, int8x8_t __idx)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  int8x8_t result;
+-  int8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_s8 (__tab.val[0], __tab.val[1]);
+-  temp.val[1] = vcombine_s8 (__tab.val[2], __tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = __builtin_aarch64_tbx4v8qi (__r, __o, __idx);
+-  return result;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx4_u8 (uint8x8_t __r, uint8x8x4_t __tab, uint8x8_t __idx)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_u8 (__tab.val[0], __tab.val[1]);
+-  temp.val[1] = vcombine_u8 (__tab.val[2], __tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
+-						  (int8x8_t)__idx);
+-  return result;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx4_p8 (poly8x8_t __r, poly8x8x4_t __tab, uint8x8_t __idx)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_p8 (__tab.val[0], __tab.val[1]);
+-  temp.val[1] = vcombine_p8 (__tab.val[2], __tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
+-						  (int8x8_t)__idx);
+-  return result;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-/* vtrn */
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_p8 (poly8x16_t __a, poly8x16_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
++#endif
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vtrn1_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {12, 4, 13, 5, 14, 6, 15, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtrn1_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+ #endif
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vtrn1_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {12, 4, 13, 5, 14, 6, 15, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+ #endif
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtrn1_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+ #endif
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vtrn1_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+ #endif
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vtrn1_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtrn1_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {12, 4, 13, 5, 14, 6, 15, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+ #endif
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtrn1_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+ #endif
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtrn1_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+ #endif
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vtrn1q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_f16 (float16x4_t __a, float16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vtrn1q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_f32 (float32x2_t __a, float32x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vtrn1q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vtrn1q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vtrn1q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_s8 (int8x8_t __a, int8x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vtrn1q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_s16 (int16x4_t __a, int16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vtrn1q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_s32 (int32x2_t __a, int32x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vtrn1q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtrn1q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtrn1q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtrn1q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtrn1q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vtrn2_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtrn2_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+ #endif
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vtrn2_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtrn2_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+ #endif
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vtrn2_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vtrn2_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtrn2_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtrn2_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+ #endif
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtrn2_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vtrn2q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vtrn2q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+   return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+@@ -24455,1319 +30368,1184 @@ vtrn2q_f64 (float64x2_t __a, float64x2_t __b)
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vtrn2q_p8 (poly8x16_t __a, poly8x16_t __b)
++__INTERLEAVE_LIST (zip)
++
++#undef __INTERLEAVE_LIST
++#undef __DEFINTERLEAVE
++
++/* End of optimal implementations in approved order.  */
++
++#pragma GCC pop_options
++
++/* ARMv8.2-A FP16 intrinsics.  */
++
++#include "arm_fp16.h"
++
++#pragma GCC push_options
++#pragma GCC target ("arch=armv8.2-a+fp16")
++
++/* ARMv8.2-A FP16 one operand vector intrinsics.  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_absv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_absv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmeqv4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmeqv8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmgev4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmgev8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmgtv4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmgtv8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmlev4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmlev8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmltv4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmltv8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_s16 (int16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
+-#endif
++  return __builtin_aarch64_floatv4hiv4hf (__a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vtrn2q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_s16 (int16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
+-#endif
++  return __builtin_aarch64_floatv8hiv8hf (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vtrn2q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_u16 (uint16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
+-#endif
++  return __builtin_aarch64_floatunsv4hiv4hf ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vtrn2q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_u16 (uint16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
+-#endif
++  return __builtin_aarch64_floatunsv8hiv8hf ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vtrn2q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s16_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
+-#endif
++  return __builtin_aarch64_lbtruncv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vtrn2q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s16_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_lbtruncv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtrn2q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u16_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
+-#endif
++  return __builtin_aarch64_lbtruncuv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtrn2q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u16_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
+-#endif
++  return __builtin_aarch64_lbtruncuv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtrn2q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s16_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
+-#endif
++  return __builtin_aarch64_lroundv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtrn2q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s16_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_lroundv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
+-vtrn_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u16_f16 (float16x4_t __a)
+ {
+-  return (float32x2x2_t) {vtrn1_f32 (a, b), vtrn2_f32 (a, b)};
++  return __builtin_aarch64_lrounduv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
+-vtrn_p8 (poly8x8_t a, poly8x8_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u16_f16 (float16x8_t __a)
+ {
+-  return (poly8x8x2_t) {vtrn1_p8 (a, b), vtrn2_p8 (a, b)};
++  return __builtin_aarch64_lrounduv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
+-vtrn_p16 (poly16x4_t a, poly16x4_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s16_f16 (float16x4_t __a)
+ {
+-  return (poly16x4x2_t) {vtrn1_p16 (a, b), vtrn2_p16 (a, b)};
++  return __builtin_aarch64_lfloorv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
+-vtrn_s8 (int8x8_t a, int8x8_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s16_f16 (float16x8_t __a)
+ {
+-  return (int8x8x2_t) {vtrn1_s8 (a, b), vtrn2_s8 (a, b)};
++  return __builtin_aarch64_lfloorv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
+-vtrn_s16 (int16x4_t a, int16x4_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u16_f16 (float16x4_t __a)
+ {
+-  return (int16x4x2_t) {vtrn1_s16 (a, b), vtrn2_s16 (a, b)};
++  return __builtin_aarch64_lflooruv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
+-vtrn_s32 (int32x2_t a, int32x2_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u16_f16 (float16x8_t __a)
+ {
+-  return (int32x2x2_t) {vtrn1_s32 (a, b), vtrn2_s32 (a, b)};
++  return __builtin_aarch64_lflooruv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
+-vtrn_u8 (uint8x8_t a, uint8x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s16_f16 (float16x4_t __a)
+ {
+-  return (uint8x8x2_t) {vtrn1_u8 (a, b), vtrn2_u8 (a, b)};
++  return __builtin_aarch64_lfrintnv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
+-vtrn_u16 (uint16x4_t a, uint16x4_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s16_f16 (float16x8_t __a)
+ {
+-  return (uint16x4x2_t) {vtrn1_u16 (a, b), vtrn2_u16 (a, b)};
++  return __builtin_aarch64_lfrintnv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
+-vtrn_u32 (uint32x2_t a, uint32x2_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u16_f16 (float16x4_t __a)
+ {
+-  return (uint32x2x2_t) {vtrn1_u32 (a, b), vtrn2_u32 (a, b)};
++  return __builtin_aarch64_lfrintnuv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
+-vtrnq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u16_f16 (float16x8_t __a)
+ {
+-  return (float32x4x2_t) {vtrn1q_f32 (a, b), vtrn2q_f32 (a, b)};
++  return __builtin_aarch64_lfrintnuv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
+-vtrnq_p8 (poly8x16_t a, poly8x16_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s16_f16 (float16x4_t __a)
+ {
+-  return (poly8x16x2_t) {vtrn1q_p8 (a, b), vtrn2q_p8 (a, b)};
++  return __builtin_aarch64_lceilv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
+-vtrnq_p16 (poly16x8_t a, poly16x8_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s16_f16 (float16x8_t __a)
+ {
+-  return (poly16x8x2_t) {vtrn1q_p16 (a, b), vtrn2q_p16 (a, b)};
++  return __builtin_aarch64_lceilv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
+-vtrnq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u16_f16 (float16x4_t __a)
+ {
+-  return (int8x16x2_t) {vtrn1q_s8 (a, b), vtrn2q_s8 (a, b)};
++  return __builtin_aarch64_lceiluv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
+-vtrnq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u16_f16 (float16x8_t __a)
+ {
+-  return (int16x8x2_t) {vtrn1q_s16 (a, b), vtrn2q_s16 (a, b)};
++  return __builtin_aarch64_lceiluv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
+-vtrnq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f16 (float16x4_t __a)
+ {
+-  return (int32x4x2_t) {vtrn1q_s32 (a, b), vtrn2q_s32 (a, b)};
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
+-vtrnq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f16 (float16x8_t __a)
+ {
+-  return (uint8x16x2_t) {vtrn1q_u8 (a, b), vtrn2q_u8 (a, b)};
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
+-vtrnq_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f16 (float16x4_t __a)
+ {
+-  return (uint16x8x2_t) {vtrn1q_u16 (a, b), vtrn2q_u16 (a, b)};
++  return __builtin_aarch64_frecpev4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
+-vtrnq_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f16 (float16x8_t __a)
+ {
+-  return (uint32x4x2_t) {vtrn1q_u32 (a, b), vtrn2q_u32 (a, b)};
++  return __builtin_aarch64_frecpev8hf (__a);
+ }
+ 
+-/* vtst */
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_btruncv4hf (__a);
++}
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtst_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f16 (float16x8_t __a)
+ {
+-  return (uint8x8_t) ((__a & __b) != 0);
++  return __builtin_aarch64_btruncv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtst_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f16 (float16x4_t __a)
+ {
+-  return (uint16x4_t) ((__a & __b) != 0);
++  return __builtin_aarch64_roundv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtst_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f16 (float16x8_t __a)
+ {
+-  return (uint32x2_t) ((__a & __b) != 0);
++  return __builtin_aarch64_roundv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vtst_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndi_f16 (float16x4_t __a)
+ {
+-  return (uint64x1_t) ((__a & __b) != __AARCH64_INT64_C (0));
++  return __builtin_aarch64_nearbyintv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtst_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndiq_f16 (float16x8_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_nearbyintv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtst_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f16 (float16x4_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_floorv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtst_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f16 (float16x8_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_floorv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vtst_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f16 (float16x4_t __a)
+ {
+-  return ((__a & __b) != __AARCH64_UINT64_C (0));
++  return __builtin_aarch64_frintnv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtstq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f16 (float16x8_t __a)
+ {
+-  return (uint8x16_t) ((__a & __b) != 0);
++  return __builtin_aarch64_frintnv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtstq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f16 (float16x4_t __a)
+ {
+-  return (uint16x8_t) ((__a & __b) != 0);
++  return __builtin_aarch64_ceilv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtstq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f16 (float16x8_t __a)
+ {
+-  return (uint32x4_t) ((__a & __b) != 0);
++  return __builtin_aarch64_ceilv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtstq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f16 (float16x4_t __a)
+ {
+-  return (uint64x2_t) ((__a & __b) != __AARCH64_INT64_C (0));
++  return __builtin_aarch64_rintv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtstq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f16 (float16x8_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_rintv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtstq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f16 (float16x4_t a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_rsqrtev4hf (a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtstq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f16 (float16x8_t a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_rsqrtev8hf (a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtstq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrt_f16 (float16x4_t a)
+ {
+-  return ((__a & __b) != __AARCH64_UINT64_C (0));
++  return __builtin_aarch64_sqrtv4hf (a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vtstd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrtq_f16 (float16x8_t a)
+ {
+-  return (__a & __b) ? -1ll : 0ll;
++  return __builtin_aarch64_sqrtv8hf (a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vtstd_u64 (uint64_t __a, uint64_t __b)
++/* ARMv8.2-A FP16 two operands vector intrinsics.  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vadd_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return (__a & __b) ? -1ll : 0ll;
++  return __a + __b;
+ }
+ 
+-/* vuqadd */
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __a + __b;
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vuqadd_s8 (int8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f16 (float16x4_t a, float16x4_t b)
+ {
+-  return __builtin_aarch64_suqaddv8qi_ssu (__a,  __b);
++  return __builtin_aarch64_fabdv4hf (a, b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vuqadd_s16 (int16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f16 (float16x8_t a, float16x8_t b)
+ {
+-  return __builtin_aarch64_suqaddv4hi_ssu (__a,  __b);
++  return __builtin_aarch64_fabdv8hf (a, b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vuqadd_s32 (int32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddv2si_ssu (__a,  __b);
++  return __builtin_aarch64_facgev4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vuqadd_s64 (int64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return (int64x1_t) {__builtin_aarch64_suqadddi_ssu (__a[0], __b[0])};
++  return __builtin_aarch64_facgev8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vuqaddq_s8 (int8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddv16qi_ssu (__a,  __b);
++  return __builtin_aarch64_facgtv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vuqaddq_s16 (int16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqaddv8hi_ssu (__a,  __b);
++  return __builtin_aarch64_facgtv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vuqaddq_s32 (int32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddv4si_ssu (__a,  __b);
++  return __builtin_aarch64_faclev4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vuqaddq_s64 (int64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqaddv2di_ssu (__a,  __b);
++  return __builtin_aarch64_faclev8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vuqaddb_s8 (int8_t __a, uint8_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddqi_ssu (__a,  __b);
++  return __builtin_aarch64_facltv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vuqaddh_s16 (int16_t __a, uint16_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqaddhi_ssu (__a,  __b);
++  return __builtin_aarch64_facltv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vuqadds_s32 (int32_t __a, uint32_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddsi_ssu (__a,  __b);
++  return __builtin_aarch64_cmeqv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vuqaddd_s64 (int64_t __a, uint64_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqadddi_ssu (__a,  __b);
++  return __builtin_aarch64_cmeqv8hf_uss (__a, __b);
+ }
+ 
+-#define __DEFINTERLEAVE(op, rettype, intype, funcsuffix, Q) 		\
+-  __extension__ static __inline rettype					\
+-  __attribute__ ((__always_inline__))					\
+-  v ## op ## Q ## _ ## funcsuffix (intype a, intype b)			\
+-  {									\
+-    return (rettype) {v ## op ## 1 ## Q ## _ ## funcsuffix (a, b),	\
+-		      v ## op ## 2 ## Q ## _ ## funcsuffix (a, b)};	\
+-  }
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_aarch64_cmgev4hf_uss (__a, __b);
++}
+ 
+-#define __INTERLEAVE_LIST(op)					\
+-  __DEFINTERLEAVE (op, float32x2x2_t, float32x2_t, f32,)	\
+-  __DEFINTERLEAVE (op, poly8x8x2_t, poly8x8_t, p8,)		\
+-  __DEFINTERLEAVE (op, poly16x4x2_t, poly16x4_t, p16,)		\
+-  __DEFINTERLEAVE (op, int8x8x2_t, int8x8_t, s8,)		\
+-  __DEFINTERLEAVE (op, int16x4x2_t, int16x4_t, s16,)		\
+-  __DEFINTERLEAVE (op, int32x2x2_t, int32x2_t, s32,)		\
+-  __DEFINTERLEAVE (op, uint8x8x2_t, uint8x8_t, u8,)		\
+-  __DEFINTERLEAVE (op, uint16x4x2_t, uint16x4_t, u16,)		\
+-  __DEFINTERLEAVE (op, uint32x2x2_t, uint32x2_t, u32,)		\
+-  __DEFINTERLEAVE (op, float32x4x2_t, float32x4_t, f32, q)	\
+-  __DEFINTERLEAVE (op, poly8x16x2_t, poly8x16_t, p8, q)		\
+-  __DEFINTERLEAVE (op, poly16x8x2_t, poly16x8_t, p16, q)	\
+-  __DEFINTERLEAVE (op, int8x16x2_t, int8x16_t, s8, q)		\
+-  __DEFINTERLEAVE (op, int16x8x2_t, int16x8_t, s16, q)		\
+-  __DEFINTERLEAVE (op, int32x4x2_t, int32x4_t, s32, q)		\
+-  __DEFINTERLEAVE (op, uint8x16x2_t, uint8x16_t, u8, q)		\
+-  __DEFINTERLEAVE (op, uint16x8x2_t, uint16x8_t, u16, q)	\
+-  __DEFINTERLEAVE (op, uint32x4x2_t, uint32x4_t, u32, q)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_aarch64_cmgev8hf_uss (__a, __b);
++}
+ 
+-/* vuzp */
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_aarch64_cmgtv4hf_uss (__a, __b);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vuzp1_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_cmgtv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vuzp1_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_cmlev4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vuzp1_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_cmlev8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vuzp1_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_cmltv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vuzp1_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_cmltv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vuzp1_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_s16 (int16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_scvtfv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vuzp1_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_s16 (int16x8_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_scvtfv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vuzp1_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_u16 (uint16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_ucvtfv4hi_sus (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_u16 (uint16x8_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfv8hi_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vuzp1_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s16_f16 (float16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fcvtzsv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vuzp1q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s16_f16 (float16x8_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_fcvtzsv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vuzp1q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u16_f16 (float16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fcvtzuv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vuzp1q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u16_f16 (float16x8_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
+-#endif
++  return __builtin_aarch64_fcvtzuv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vuzp1q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdiv_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __a / __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vuzp1q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdivq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
+-#endif
++  return __a / __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vuzp1q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_smax_nanv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vuzp1q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_smax_nanv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vuzp1q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fmaxv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vuzp1q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
+-#endif
++  return __builtin_aarch64_fmaxv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vuzp1q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_smin_nanv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vuzp1q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_smin_nanv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vuzp1q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fminv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vuzp2_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_fminv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vuzp2_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vuzp2_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
+-#endif
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vuzp2_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_fmulxv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vuzp2_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_fmulxv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vuzp2_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_faddpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vuzp2_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_faddpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vuzp2_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_smax_nanpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vuzp2_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_smax_nanpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vuzp2q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnm_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_smaxpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vuzp2q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_smaxpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vuzp2q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
+-#endif
++  return __builtin_aarch64_smin_nanpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vuzp2q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_smin_nanpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vuzp2q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnm_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
+-#endif
++  return __builtin_aarch64_sminpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vuzp2q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_sminpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vuzp2q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_frecpsv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vuzp2q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_frecpsv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vuzp2q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
+-#endif
++  return __builtin_aarch64_rsqrtsv4hf (a, b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vuzp2q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_rsqrtsv8hf (a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vuzp2q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsub_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
+-#endif
++  return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vuzp2q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsubq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __a - __b;
+ }
+ 
+-__INTERLEAVE_LIST (uzp)
+-
+-/* vzip */
++/* ARMv8.2-A FP16 three operands vector intrinsics.  */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vzip1_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fmav4hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vzip1_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return __builtin_aarch64_fmav8hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vzip1_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
+-#endif
++  return __builtin_aarch64_fnmav4hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vzip1_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return __builtin_aarch64_fnmav8hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vzip1_s16 (int16x4_t __a, int16x4_t __b)
+-{
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
+-#endif
++/* ARMv8.2-A FP16 lane vector intrinsics.  */
++
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmah_lane_f16 (float16_t __a, float16_t __b,
++		float16x4_t __c, const int __lane)
++{
++  return vfmah_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vzip1_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmah_laneq_f16 (float16_t __a, float16_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return vfmah_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vzip1_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_lane_f16 (float16x4_t __a, float16x4_t __b,
++	       float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfma_f16 (__a, __b, __aarch64_vdup_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vzip1_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_lane_f16 (float16x8_t __a, float16x8_t __b,
++		float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmaq_f16 (__a, __b, __aarch64_vdupq_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vzip1_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_laneq_f16 (float16x4_t __a, float16x4_t __b,
++		float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return vfma_f16 (__a, __b, __aarch64_vdup_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vzip1q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_laneq_f16 (float16x8_t __a, float16x8_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmaq_f16 (__a, __b, __aarch64_vdupq_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vzip1q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_n_f16 (float16x4_t __a, float16x4_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return vfma_f16 (__a, __b, vdup_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vzip1q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+-#endif
++  return vfmaq_f16 (__a, __b, vdupq_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vzip1q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsh_lane_f16 (float16_t __a, float16_t __b,
++		float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfmsh_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vzip1q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsh_laneq_f16 (float16_t __a, float16_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+-#endif
++  return vfmsh_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vzip1q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_lane_f16 (float16x4_t __a, float16x4_t __b,
++	       float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfms_f16 (__a, __b, __aarch64_vdup_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vzip1q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_lane_f16 (float16x8_t __a, float16x8_t __b,
++		float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmsq_f16 (__a, __b, __aarch64_vdupq_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vzip1q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_laneq_f16 (float16x4_t __a, float16x4_t __b,
++		float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return vfms_f16 (__a, __b, __aarch64_vdup_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vzip1q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_laneq_f16 (float16x8_t __a, float16x8_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+-#endif
++  return vfmsq_f16 (__a, __b, __aarch64_vdupq_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vzip1q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_n_f16 (float16x4_t __a, float16x4_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfms_f16 (__a, __b, vdup_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vzip1q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmsq_f16 (__a, __b, vdupq_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vzip1q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulh_lane_f16 (float16_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vzip2_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f16 (float16x4_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return vmul_f16 (__a, vdup_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vzip2_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulq_f16 (__a, vdupq_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vzip2_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulh_laneq_f16 (float16_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+-#endif
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vzip2_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_f16 (float16x4_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmul_f16 (__a, vdup_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vzip2_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_f16 (float16x8_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+-#endif
++  return vmulq_f16 (__a, vdupq_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vzip2_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f16 (float16x4_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return vmul_lane_f16 (__a, vdup_n_f16 (__b), 0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vzip2_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f16 (float16x8_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulq_laneq_f16 (__a, vdupq_n_f16 (__b), 0);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vzip2_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxh_lane_f16 (float16_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+-#endif
++  return vmulxh_f16 (__a, __aarch64_vget_lane_any (__b, __lane));
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vzip2_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_lane_f16 (float16x4_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return vmulx_f16 (__a, __aarch64_vdup_lane_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vzip2q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+-#endif
++  return vmulxq_f16 (__a, __aarch64_vdupq_lane_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vzip2q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxh_laneq_f16 (float16_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return vmulxh_f16 (__a, __aarch64_vget_lane_any (__b, __lane));
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vzip2q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_laneq_f16 (float16x4_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+-#endif
++  return vmulx_f16 (__a, __aarch64_vdup_laneq_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vzip2q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_laneq_f16 (float16x8_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulxq_f16 (__a, __aarch64_vdupq_laneq_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vzip2q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_n_f16 (float16x4_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+-#endif
++  return vmulx_f16 (__a, vdup_n_f16 (__b));
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vzip2q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_n_f16 (float16x8_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulxq_f16 (__a, vdupq_n_f16 (__b));
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vzip2q_s32 (int32x4_t __a, int32x4_t __b)
++/* ARMv8.2-A FP16 reduction vector intrinsics.  */
++
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+-#endif
++  return __builtin_aarch64_reduc_smax_nan_scal_v4hf (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vzip2q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_reduc_smax_nan_scal_v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vzip2q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+-#endif
++  return __builtin_aarch64_reduc_smin_nan_scal_v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vzip2q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return __builtin_aarch64_reduc_smin_nan_scal_v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vzip2q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmv_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+-#endif
++  return __builtin_aarch64_reduc_smax_scal_v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vzip2q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmvq_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_reduc_smax_scal_v8hf (__a);
+ }
+ 
+-__INTERLEAVE_LIST (zip)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmv_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_reduc_smin_scal_v4hf (__a);
++}
+ 
+-#undef __INTERLEAVE_LIST
+-#undef __DEFINTERLEAVE
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmvq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_reduc_smin_scal_v8hf (__a);
++}
+ 
+-/* End of optimal implementations in approved order.  */
++#pragma GCC pop_options
+ 
+ #undef __aarch64_vget_lane_any
+ 
+ #undef __aarch64_vdup_lane_any
++#undef __aarch64_vdup_lane_f16
+ #undef __aarch64_vdup_lane_f32
+ #undef __aarch64_vdup_lane_f64
+ #undef __aarch64_vdup_lane_p8
+@@ -25780,6 +31558,7 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdup_lane_u16
+ #undef __aarch64_vdup_lane_u32
+ #undef __aarch64_vdup_lane_u64
++#undef __aarch64_vdup_laneq_f16
+ #undef __aarch64_vdup_laneq_f32
+ #undef __aarch64_vdup_laneq_f64
+ #undef __aarch64_vdup_laneq_p8
+@@ -25792,6 +31571,7 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdup_laneq_u16
+ #undef __aarch64_vdup_laneq_u32
+ #undef __aarch64_vdup_laneq_u64
++#undef __aarch64_vdupq_lane_f16
+ #undef __aarch64_vdupq_lane_f32
+ #undef __aarch64_vdupq_lane_f64
+ #undef __aarch64_vdupq_lane_p8
+@@ -25804,6 +31584,7 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdupq_lane_u16
+ #undef __aarch64_vdupq_lane_u32
+ #undef __aarch64_vdupq_lane_u64
++#undef __aarch64_vdupq_laneq_f16
+ #undef __aarch64_vdupq_laneq_f32
+ #undef __aarch64_vdupq_laneq_f64
+ #undef __aarch64_vdupq_laneq_p8
+@@ -25817,6 +31598,4 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdupq_laneq_u32
+ #undef __aarch64_vdupq_laneq_u64
+ 
+-#pragma GCC pop_options
+-
+ #endif
+--- a/src/gcc/config/aarch64/atomics.md
++++ b/src/gcc/config/aarch64/atomics.md
+@@ -583,7 +583,7 @@
+   }
+ )
+ 
+-;; ARMv8.1 LSE instructions.
++;; ARMv8.1-A LSE instructions.
+ 
+ ;; Atomic swap with memory.
+ (define_insn "aarch64_atomic_swp<mode>"
+--- a/src/gcc/config/aarch64/geniterators.sh
++++ b/src/gcc/config/aarch64/geniterators.sh
+@@ -23,10 +23,7 @@
+ # BUILTIN_<ITERATOR> macros, which expand to VAR<N> Macros covering the
+ # same set of modes as the iterator in iterators.md
+ #
+-# Find the <ITERATOR> definitions (may span several lines), skip the ones
+-# which does not have a simple format because it contains characters we
+-# don't want to or can't handle (e.g P, PTR iterators change depending on
+-# Pmode and ptr_mode).
++# Find the <ITERATOR> definitions (may span several lines).
+ LC_ALL=C awk '
+ BEGIN {
+ 	print "/* -*- buffer-read-only: t -*- */"
+@@ -49,12 +46,24 @@ iterdef {
+ 	sub(/.*\(define_mode_iterator/, "", s)
+ }
+ 
+-iterdef && s ~ /\)/ {
++iterdef {
++	# Count the parentheses, the iterator definition ends
++	# if there are more closing ones than opening ones.
++	nopen = gsub(/\(/, "(", s)
++	nclose = gsub(/\)/, ")", s)
++	if (nopen >= nclose)
++		next
++
+ 	iterdef = 0
+ 
+ 	gsub(/[ \t]+/, " ", s)
+-	sub(/ *\).*/, "", s)
++	sub(/ *\)[^)]*$/, "", s)
+ 	sub(/^ /, "", s)
++
++	# Drop the conditions.
++	gsub(/ *"[^"]*" *\)/, "", s)
++	gsub(/\( */, "", s)
++
+ 	if (s !~ /^[A-Za-z0-9_]+ \[[A-Z0-9 ]*\]$/)
+ 		next
+ 	sub(/\[ */, "", s)
+--- a/src/gcc/config/aarch64/iterators.md
++++ b/src/gcc/config/aarch64/iterators.md
+@@ -26,6 +26,9 @@
+ ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
+ (define_mode_iterator GPI [SI DI])
+ 
++;; Iterator for HI, SI, DI, some instructions can only work on these modes.
++(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
++
+ ;; Iterator for QI and HI modes
+ (define_mode_iterator SHORT [QI HI])
+ 
+@@ -38,6 +41,9 @@
+ ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
+ (define_mode_iterator GPF [SF DF])
+ 
++;; Iterator for all scalar floating point modes (HF, SF, DF)
++(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
++
+ ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
+ (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
+ 
+@@ -88,11 +94,22 @@
+ ;; Vector Float modes suitable for moving, loading and storing.
+ (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
+ 
+-;; Vector Float modes, barring HF modes.
++;; Vector Float modes.
+ (define_mode_iterator VDQF [V2SF V4SF V2DF])
++(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
++			     (V8HF "TARGET_SIMD_F16INST")
++			     V2SF V4SF V2DF])
+ 
+ ;; Vector Float modes, and DF.
+ (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
++(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
++				(V8HF "TARGET_SIMD_F16INST")
++				V2SF V4SF V2DF DF])
++(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
++				  (V8HF "TARGET_SIMD_F16INST")
++				  V2SF V4SF V2DF
++				  (HF "TARGET_SIMD_F16INST")
++				  SF DF])
+ 
+ ;; Vector single Float modes.
+ (define_mode_iterator VDQSF [V2SF V4SF])
+@@ -150,10 +167,30 @@
+ 
+ ;; Vector modes except double int.
+ (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
++(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
++                                 V4HF V8HF V2SF V4SF V2DF])
+ 
+ ;; Vector modes for S type.
+ (define_mode_iterator VDQ_SI [V2SI V4SI])
+ 
++;; Vector modes for S and D
++(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
++
++;; Vector modes for H, S and D
++(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
++				(V8HI "TARGET_SIMD_F16INST")
++				V2SI V4SI V2DI])
++
++;; Scalar and Vector modes for S and D
++(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
++
++;; Scalar and Vector modes for S and D, Vector modes for H.
++(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
++				 (V8HI "TARGET_SIMD_F16INST")
++				 V2SI V4SI V2DI
++				 (HI "TARGET_SIMD_F16INST")
++				 SI DI])
++
+ ;; Vector modes for Q and H types.
+ (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
+ 
+@@ -193,7 +230,10 @@
+ (define_mode_iterator DX [DI DF])
+ 
+ ;; Modes available for <f>mul lane operations.
+-(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
++(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
++			    (V4HF "TARGET_SIMD_F16INST")
++			    (V8HF "TARGET_SIMD_F16INST")
++			    V2SF V4SF V2DF])
+ 
+ ;; Modes available for <f>mul lane operations changing lane count.
+ (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
+@@ -342,8 +382,8 @@
+ (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
+ 
+ ;; For inequal width int to float conversion
+-(define_mode_attr w1 [(SF "w") (DF "x")])
+-(define_mode_attr w2 [(SF "x") (DF "w")])
++(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
++(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
+ 
+ (define_mode_attr short_mask [(HI "65535") (QI "255")])
+ 
+@@ -355,12 +395,13 @@
+ 
+ ;; For scalar usage of vector/FP registers
+ (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
+-		    (SF "s") (DF "d")
++		    (HF  "h") (SF "s") (DF "d")
+ 		    (V8QI "") (V16QI "")
+ 		    (V4HI "") (V8HI "")
+ 		    (V2SI "") (V4SI  "")
+ 		    (V2DI "") (V2SF "")
+-		    (V4SF "") (V2DF "")])
++		    (V4SF "") (V4HF "")
++		    (V8HF "") (V2DF "")])
+ 
+ ;; For scalar usage of vector/FP registers, narrowing
+ (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
+@@ -385,7 +426,7 @@
+ (define_mode_attr vas [(DI "") (SI ".2s")])
+ 
+ ;; Map a floating point mode to the appropriate register name prefix
+-(define_mode_attr s [(SF "s") (DF "d")])
++(define_mode_attr s [(HF "h") (SF "s") (DF "d")])
+ 
+ ;; Give the length suffix letter for a sign- or zero-extension.
+ (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
+@@ -421,8 +462,8 @@
+ 			 (V4SF ".4s") (V2DF ".2d")
+ 			 (DI   "")    (SI   "")
+ 			 (HI   "")    (QI   "")
+-			 (TI   "")    (SF   "")
+-			 (DF   "")])
++			 (TI   "")    (HF   "")
++			 (SF   "")    (DF   "")])
+ 
+ ;; Register suffix narrowed modes for VQN.
+ (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
+@@ -437,10 +478,21 @@
+ 			  (V2DI "d") (V4HF "h")
+ 			  (V8HF "h") (V2SF  "s")
+ 			  (V4SF "s") (V2DF  "d")
++			  (HF   "h")
+ 			  (SF   "s") (DF  "d")
+ 			  (QI "b")   (HI "h")
+ 			  (SI "s")   (DI "d")])
+ 
++;; Vetype is used everywhere in scheduling type and assembly output,
++;; sometimes they are not the same, for example HF modes on some
++;; instructions.  stype is defined to represent scheduling type
++;; more accurately.
++(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
++			 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
++			 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
++			 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
++			 (SI "s") (DI "d")])
++
+ ;; Mode-to-bitwise operation type mapping.
+ (define_mode_attr Vbtype [(V8QI "8b")  (V16QI "16b")
+ 			  (V4HI "8b") (V8HI  "16b")
+@@ -598,7 +650,7 @@
+ 				(V4HF "V4HI") (V8HF  "V8HI")
+ 				(V2SF "V2SI") (V4SF  "V4SI")
+ 				(V2DF "V2DI") (DF    "DI")
+-				(SF   "SI")])
++				(SF   "SI")   (HF    "HI")])
+ 
+ ;; Lower case mode of results of comparison operations.
+ (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
+@@ -648,12 +700,21 @@
+ (define_mode_attr atomic_sfx
+   [(QI "b") (HI "h") (SI "") (DI "")])
+ 
+-(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
+-(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
++(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
++			       (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
++			       (SF "si") (DF "di") (SI "sf") (DI "df")
++			       (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
++			       (V8HI "v8hf") (HF "hi") (HI "hf")])
++(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
++			       (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
++			       (SF "SI") (DF "DI") (SI "SF") (DI "DF")
++			       (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
++			       (V8HI "V8HF") (HF "HI") (HI "HF")])
++
+ 
+ ;; for the inequal width integer to fp conversions
+-(define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
+-(define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
++(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
++(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
+ 
+ (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
+ 				(V4HI "V8HI") (V8HI  "V4HI")
+@@ -676,6 +737,7 @@
+ ;; the 'x' constraint.  All other modes may use the 'w' constraint.
+ (define_mode_attr h_con [(V2SI "w") (V4SI "w")
+ 			 (V4HI "x") (V8HI "x")
++			 (V4HF "w") (V8HF "w")
+ 			 (V2SF "w") (V4SF "w")
+ 			 (V2DF "w") (DF "w")])
+ 
+@@ -684,6 +746,7 @@
+ 		     (V4HI "")  (V8HI  "")
+ 		     (V2SI "")  (V4SI  "")
+ 		     (DI   "")  (V2DI  "")
++		     (V4HF "f") (V8HF  "f")
+ 		     (V2SF "f") (V4SF  "f")
+ 		     (V2DF "f") (DF    "f")])
+ 
+@@ -692,6 +755,7 @@
+ 		      (V4HI "")  (V8HI  "")
+ 		      (V2SI "")  (V4SI  "")
+ 		      (DI   "")  (V2DI  "")
++		      (V4HF "_fp") (V8HF  "_fp")
+ 		      (V2SF "_fp") (V4SF  "_fp")
+ 		      (V2DF "_fp") (DF    "_fp")
+ 		      (SF "_fp")])
+@@ -704,17 +768,19 @@
+ 		     (V4HF "") (V8HF "_q")
+ 		     (V2SF "") (V4SF  "_q")
+ 			       (V2DF  "_q")
+-		     (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
++		     (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
+ 
+ (define_mode_attr vp [(V8QI "v") (V16QI "v")
+ 		      (V4HI "v") (V8HI  "v")
+ 		      (V2SI "p") (V4SI  "v")
+-		      (V2DI  "p") (V2DF  "p")
+-		      (V2SF "p") (V4SF  "v")])
++		      (V2DI "p") (V2DF  "p")
++		      (V2SF "p") (V4SF  "v")
++		      (V4HF "v") (V8HF  "v")])
+ 
+ (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
+ (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
+ 
++;; Sum of lengths of instructions needed to move vector registers of a mode.
+ (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
+ 
+ ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
+@@ -876,9 +942,6 @@
+ ;; Similar, but when not(op)
+ (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
+ 
+-;; Sign- or zero-extending load
+-(define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
+-
+ ;; Sign- or zero-extending data-op
+ (define_code_attr su [(sign_extend "s") (zero_extend "u")
+ 		      (sign_extract "s") (zero_extract "u")
+@@ -953,9 +1016,8 @@
+ (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
+ 			        UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
+ 
+-(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN])
+-
+-(define_int_iterator FMAXMIN [UNSPEC_FMAXNM UNSPEC_FMINNM])
++(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
++				  UNSPEC_FMAXNM UNSPEC_FMINNM])
+ 
+ (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
+ 
+@@ -1001,6 +1063,9 @@
+ (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
+ 			    UNSPEC_FRINTA UNSPEC_FRINTN])
+ 
++(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
++(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
++
+ (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
+ 
+ (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
+@@ -1036,7 +1101,9 @@
+ 			      (UNSPEC_FMAXV "smax_nan")
+ 			      (UNSPEC_FMIN "smin_nan")
+ 			      (UNSPEC_FMINNMV "smin")
+-			      (UNSPEC_FMINV "smin_nan")])
++			      (UNSPEC_FMINV "smin_nan")
++			      (UNSPEC_FMAXNM "fmax")
++			      (UNSPEC_FMINNM "fmin")])
+ 
+ (define_int_attr  maxmin_uns_op [(UNSPEC_UMAXV "umax")
+ 				 (UNSPEC_UMINV "umin")
+@@ -1047,13 +1114,9 @@
+ 				 (UNSPEC_FMAXV "fmax")
+ 				 (UNSPEC_FMIN "fmin")
+ 				 (UNSPEC_FMINNMV "fminnm")
+-				 (UNSPEC_FMINV "fmin")])
+-
+-(define_int_attr fmaxmin [(UNSPEC_FMAXNM "fmax")
+-			  (UNSPEC_FMINNM "fmin")])
+-
+-(define_int_attr fmaxmin_op [(UNSPEC_FMAXNM "fmaxnm")
+-			     (UNSPEC_FMINNM "fminnm")])
++				 (UNSPEC_FMINV "fmin")
++				 (UNSPEC_FMAXNM "fmaxnm")
++				 (UNSPEC_FMINNM "fminnm")])
+ 
+ (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
+ 		      (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
+@@ -1137,6 +1200,11 @@
+ 			       (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
+ 			       (UNSPEC_FRINTN "frintn")])
+ 
++(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
++				  (UNSPEC_UCVTF "ucvtf")
++				  (UNSPEC_FCVTZS "fcvtzs")
++				  (UNSPEC_FCVTZU "fcvtzu")])
++
+ (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
+ 			    (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
+ 			    (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
+--- a/src/gcc/config/aarch64/t-aarch64
++++ b/src/gcc/config/aarch64/t-aarch64
+@@ -52,7 +52,7 @@ aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \
+ 		$(srcdir)/config/arm/aarch-common.c
+ 
+ aarch64-c.o: $(srcdir)/config/aarch64/aarch64-c.c $(CONFIG_H) $(SYSTEM_H) \
+-    coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H)
++    coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H) $(TARGET_H)
+ 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ 		$(srcdir)/config/aarch64/aarch64-c.c
+ 
+--- a/src/gcc/config/aarch64/thunderx.md
++++ b/src/gcc/config/aarch64/thunderx.md
+@@ -39,7 +39,7 @@
+ 
+ (define_insn_reservation "thunderx_shift" 1
+   (and (eq_attr "tune" "thunderx")
+-       (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
++       (eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
+   "thunderx_pipe0 | thunderx_pipe1")
+ 
+ 
+--- a/src/gcc/config/alpha/alpha.c
++++ b/src/gcc/config/alpha/alpha.c
+@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "df.h"
+ #include "tm_p.h"
+--- a/src/gcc/config/arm/aarch-cost-tables.h
++++ b/src/gcc/config/arm/aarch-cost-tables.h
+@@ -191,35 +191,35 @@ const struct cpu_cost_table cortexa53_extra_costs =
+   {
+     /* FP SFmode */
+     {
+-      COSTS_N_INSNS (15),	/* div.  */
+-      COSTS_N_INSNS (3),	/* mult.  */
+-      COSTS_N_INSNS (7),	/* mult_addsub. */
+-      COSTS_N_INSNS (7),	/* fma.  */
+-      COSTS_N_INSNS (3),	/* addsub.  */
+-      COSTS_N_INSNS (1),	/* fpconst. */
+-      COSTS_N_INSNS (2),	/* neg.  */
+-      COSTS_N_INSNS (1),	/* compare.  */
+-      COSTS_N_INSNS (3),	/* widen.  */
+-      COSTS_N_INSNS (3),	/* narrow.  */
+-      COSTS_N_INSNS (3),	/* toint.  */
+-      COSTS_N_INSNS (3),	/* fromint.  */
+-      COSTS_N_INSNS (3)		/* roundint.  */
++      COSTS_N_INSNS (5),	/* div.  */
++      COSTS_N_INSNS (1),	/* mult.  */
++      COSTS_N_INSNS (2),	/* mult_addsub.  */
++      COSTS_N_INSNS (2),	/* fma.  */
++      COSTS_N_INSNS (1),	/* addsub.  */
++      0,			/* fpconst.  */
++      COSTS_N_INSNS (1),	/* neg.  */
++      0,			/* compare.  */
++      COSTS_N_INSNS (1),	/* widen.  */
++      COSTS_N_INSNS (1),	/* narrow.  */
++      COSTS_N_INSNS (1),	/* toint.  */
++      COSTS_N_INSNS (1),	/* fromint.  */
++      COSTS_N_INSNS (1)		/* roundint.  */
+     },
+     /* FP DFmode */
+     {
+-      COSTS_N_INSNS (30),	/* div.  */
+-      COSTS_N_INSNS (3),	/* mult.  */
+-      COSTS_N_INSNS (7),	/* mult_addsub.  */
+-      COSTS_N_INSNS (7),	/* fma.  */
+-      COSTS_N_INSNS (3),	/* addsub.  */
+-      COSTS_N_INSNS (1),	/* fpconst.  */
+-      COSTS_N_INSNS (2),	/* neg.  */
+-      COSTS_N_INSNS (1),	/* compare.  */
+-      COSTS_N_INSNS (3),	/* widen.  */
+-      COSTS_N_INSNS (3),	/* narrow.  */
+-      COSTS_N_INSNS (3),	/* toint.  */
+-      COSTS_N_INSNS (3),	/* fromint.  */
+-      COSTS_N_INSNS (3)		/* roundint.  */
++      COSTS_N_INSNS (10),	/* div.  */
++      COSTS_N_INSNS (1),	/* mult.  */
++      COSTS_N_INSNS (2),	/* mult_addsub.  */
++      COSTS_N_INSNS (2),	/* fma.  */
++      COSTS_N_INSNS (1),	/* addsub.  */
++      0,			/* fpconst.  */
++      COSTS_N_INSNS (1),	/* neg.  */
++      0,			/* compare.  */
++      COSTS_N_INSNS (1),	/* widen.  */
++      COSTS_N_INSNS (1),	/* narrow.  */
++      COSTS_N_INSNS (1),	/* toint.  */
++      COSTS_N_INSNS (1),	/* fromint.  */
++      COSTS_N_INSNS (1)		/* roundint.  */
+     }
+   },
+   /* Vector */
+@@ -294,35 +294,35 @@ const struct cpu_cost_table cortexa57_extra_costs =
+   {
+     /* FP SFmode */
+     {
+-      COSTS_N_INSNS (17),      /* div.  */
+-      COSTS_N_INSNS (5),       /* mult.  */
+-      COSTS_N_INSNS (9),       /* mult_addsub. */
+-      COSTS_N_INSNS (9),       /* fma.  */
+-      COSTS_N_INSNS (4),       /* addsub.  */
+-      COSTS_N_INSNS (2),       /* fpconst. */
+-      COSTS_N_INSNS (2),       /* neg.  */
+-      COSTS_N_INSNS (2),       /* compare.  */
+-      COSTS_N_INSNS (4),       /* widen.  */
+-      COSTS_N_INSNS (4),       /* narrow.  */
+-      COSTS_N_INSNS (4),       /* toint.  */
+-      COSTS_N_INSNS (4),       /* fromint.  */
+-      COSTS_N_INSNS (4)        /* roundint.  */
++      COSTS_N_INSNS (6),      /* div.  */
++      COSTS_N_INSNS (1),       /* mult.  */
++      COSTS_N_INSNS (2),       /* mult_addsub.  */
++      COSTS_N_INSNS (2),       /* fma.  */
++      COSTS_N_INSNS (1),       /* addsub.  */
++      0,		       /* fpconst.  */
++      0,		       /* neg.  */
++      0,		       /* compare.  */
++      COSTS_N_INSNS (1),       /* widen.  */
++      COSTS_N_INSNS (1),       /* narrow.  */
++      COSTS_N_INSNS (1),       /* toint.  */
++      COSTS_N_INSNS (1),       /* fromint.  */
++      COSTS_N_INSNS (1)        /* roundint.  */
+     },
+     /* FP DFmode */
+     {
+-      COSTS_N_INSNS (31),      /* div.  */
+-      COSTS_N_INSNS (5),       /* mult.  */
+-      COSTS_N_INSNS (9),       /* mult_addsub.  */
+-      COSTS_N_INSNS (9),       /* fma.  */
+-      COSTS_N_INSNS (4),       /* addsub.  */
+-      COSTS_N_INSNS (2),       /* fpconst.  */
+-      COSTS_N_INSNS (2),       /* neg.  */
+-      COSTS_N_INSNS (2),       /* compare.  */
+-      COSTS_N_INSNS (4),       /* widen.  */
+-      COSTS_N_INSNS (4),       /* narrow.  */
+-      COSTS_N_INSNS (4),       /* toint.  */
+-      COSTS_N_INSNS (4),       /* fromint.  */
+-      COSTS_N_INSNS (4)        /* roundint.  */
++      COSTS_N_INSNS (11),      /* div.  */
++      COSTS_N_INSNS (1),       /* mult.  */
++      COSTS_N_INSNS (2),       /* mult_addsub.  */
++      COSTS_N_INSNS (2),       /* fma.  */
++      COSTS_N_INSNS (1),       /* addsub.  */
++      0,		       /* fpconst.  */
++      0,		       /* neg.  */
++      0,		       /* compare.  */
++      COSTS_N_INSNS (1),       /* widen.  */
++      COSTS_N_INSNS (1),       /* narrow.  */
++      COSTS_N_INSNS (1),       /* toint.  */
++      COSTS_N_INSNS (1),       /* fromint.  */
++      COSTS_N_INSNS (1)        /* roundint.  */
+     }
+   },
+   /* Vector */
+@@ -537,4 +537,107 @@ const struct cpu_cost_table xgene1_extra_costs =
+   }
+ };
+ 
++const struct cpu_cost_table qdf24xx_extra_costs =
++{
++  /* ALU */
++  {
++    0,                 /* arith.  */
++    0,                 /* logical.  */
++    0,                 /* shift.  */
++    0,                 /* shift_reg.  */
++    COSTS_N_INSNS (1), /* arith_shift.  */
++    COSTS_N_INSNS (1), /* arith_shift_reg.  */
++    0,                 /* log_shift.  */
++    0,                 /* log_shift_reg.  */
++    0,                 /* extend.  */
++    0,                 /* extend_arith.  */
++    0,                 /* bfi.  */
++    0,                 /* bfx.  */
++    0,                 /* clz.  */
++    0,	               /* rev.  */
++    0,                 /* non_exec.  */
++    true               /* non_exec_costs_exec.  */
++  },
++  {
++    /* MULT SImode */
++    {
++      COSTS_N_INSNS (2),       /* simple.  */
++      COSTS_N_INSNS (2),       /* flag_setting.  */
++      COSTS_N_INSNS (2),       /* extend.  */
++      COSTS_N_INSNS (2),       /* add.  */
++      COSTS_N_INSNS (2),       /* extend_add.  */
++      COSTS_N_INSNS (4)       /* idiv.  */
++    },
++    /* MULT DImode */
++    {
++      COSTS_N_INSNS (3),       /* simple.  */
++      0,                       /* flag_setting (N/A).  */
++      COSTS_N_INSNS (3),       /* extend.  */
++      COSTS_N_INSNS (3),       /* add.  */
++      COSTS_N_INSNS (3),       /* extend_add.  */
++      COSTS_N_INSNS (9)       /* idiv.  */
++    }
++  },
++  /* LD/ST */
++  {
++    COSTS_N_INSNS (2),         /* load.  */
++    COSTS_N_INSNS (2),         /* load_sign_extend.  */
++    COSTS_N_INSNS (2),         /* ldrd.  */
++    COSTS_N_INSNS (2),         /* ldm_1st.  */
++    1,                         /* ldm_regs_per_insn_1st.  */
++    2,                         /* ldm_regs_per_insn_subsequent.  */
++    COSTS_N_INSNS (2),         /* loadf.  */
++    COSTS_N_INSNS (2),         /* loadd.  */
++    COSTS_N_INSNS (3),         /* load_unaligned.  */
++    0,                         /* store.  */
++    0,                         /* strd.  */
++    0,                         /* stm_1st.  */
++    1,                         /* stm_regs_per_insn_1st.  */
++    2,                         /* stm_regs_per_insn_subsequent.  */
++    0,                         /* storef.  */
++    0,                         /* stored.  */
++    COSTS_N_INSNS (1),         /* store_unaligned.  */
++    COSTS_N_INSNS (1),         /* loadv.  */
++    COSTS_N_INSNS (1)          /* storev.  */
++  },
++  {
++    /* FP SFmode */
++    {
++      COSTS_N_INSNS (6),      /* div.  */
++      COSTS_N_INSNS (5),       /* mult.  */
++      COSTS_N_INSNS (5),       /* mult_addsub. */
++      COSTS_N_INSNS (5),       /* fma.  */
++      COSTS_N_INSNS (3),       /* addsub.  */
++      COSTS_N_INSNS (1),       /* fpconst. */
++      COSTS_N_INSNS (1),       /* neg.  */
++      COSTS_N_INSNS (2),       /* compare.  */
++      COSTS_N_INSNS (4),       /* widen.  */
++      COSTS_N_INSNS (4),       /* narrow.  */
++      COSTS_N_INSNS (4),       /* toint.  */
++      COSTS_N_INSNS (4),       /* fromint.  */
++      COSTS_N_INSNS (2)        /* roundint.  */
++    },
++    /* FP DFmode */
++    {
++      COSTS_N_INSNS (11),      /* div.  */
++      COSTS_N_INSNS (6),       /* mult.  */
++      COSTS_N_INSNS (6),       /* mult_addsub.  */
++      COSTS_N_INSNS (6),       /* fma.  */
++      COSTS_N_INSNS (3),       /* addsub.  */
++      COSTS_N_INSNS (1),       /* fpconst.  */
++      COSTS_N_INSNS (1),       /* neg.  */
++      COSTS_N_INSNS (2),       /* compare.  */
++      COSTS_N_INSNS (4),       /* widen.  */
++      COSTS_N_INSNS (4),       /* narrow.  */
++      COSTS_N_INSNS (4),       /* toint.  */
++      COSTS_N_INSNS (4),       /* fromint.  */
++      COSTS_N_INSNS (2)        /* roundint.  */
++    }
++  },
++  /* Vector */
++  {
++    COSTS_N_INSNS (1)  /* alu.  */
++  }
++};
++
+ #endif /* GCC_AARCH_COST_TABLES_H */
+--- a/src/gcc/config/arm/arm-arches.def
++++ b/src/gcc/config/arm/arm-arches.def
+@@ -58,10 +58,22 @@ ARM_ARCH("armv7e-m", cortexm4,  7EM,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_F
+ ARM_ARCH("armv8-a", cortexa53,  8A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH8A))
+ ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A))
+ ARM_ARCH("armv8.1-a", cortexa53,  8A,
+-	  ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8A,  FL2_FOR_ARCH8_1A))
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
++			 FL2_FOR_ARCH8_1A))
+ ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
+ 	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
+ 			 FL2_FOR_ARCH8_1A))
++ARM_ARCH ("armv8.2-a", cortexa53,  8A,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
++			 FL2_FOR_ARCH8_2A))
++ARM_ARCH ("armv8.2-a+fp16", cortexa53,  8A,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
++			 FL2_FOR_ARCH8_2A | FL2_FP16INST))
++ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
++	  ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
++ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
++ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ ARM_ARCH("iwmmxt",  iwmmxt,     5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
+ ARM_ARCH("iwmmxt2", iwmmxt2,    5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
+-
+--- a/src/gcc/config/arm/arm-builtins.c
++++ b/src/gcc/config/arm/arm-builtins.c
+@@ -190,6 +190,8 @@ arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ #define ti_UP	 TImode
+ #define ei_UP	 EImode
+ #define oi_UP	 OImode
++#define hf_UP	 HFmode
++#define si_UP	 SImode
+ 
+ #define UP(X) X##_UP
+ 
+@@ -239,12 +241,22 @@ typedef struct {
+   VAR11 (T, N, A, B, C, D, E, F, G, H, I, J, K) \
+   VAR1 (T, N, L)
+ 
+-/* The NEON builtin data can be found in arm_neon_builtins.def.
+-   The mode entries in the following table correspond to the "key" type of the
+-   instruction variant, i.e. equivalent to that which would be specified after
+-   the assembler mnemonic, which usually refers to the last vector operand.
+-   The modes listed per instruction should be the same as those defined for
+-   that instruction's pattern in neon.md.  */
++/* The NEON builtin data can be found in arm_neon_builtins.def and
++   arm_vfp_builtins.def.  The entries in arm_neon_builtins.def require
++   TARGET_NEON to be true.  The feature tests are checked when the
++   builtins are expanded.
++
++   The mode entries in the following table correspond to the "key"
++   type of the instruction variant, i.e. equivalent to that which
++   would be specified after the assembler mnemonic, which usually
++   refers to the last vector operand.  The modes listed per
++   instruction should be the same as those defined for that
++   instruction's pattern in neon.md.  */
++
++static neon_builtin_datum vfp_builtin_data[] =
++{
++#include "arm_vfp_builtins.def"
++};
+ 
+ static neon_builtin_datum neon_builtin_data[] =
+ {
+@@ -515,6 +527,8 @@ enum arm_builtins
+   ARM_BUILTIN_GET_FPSCR,
+   ARM_BUILTIN_SET_FPSCR,
+ 
++  ARM_BUILTIN_CMSE_NONSECURE_CALLER,
++
+ #undef CRYPTO1
+ #undef CRYPTO2
+ #undef CRYPTO3
+@@ -534,6 +548,10 @@ enum arm_builtins
+ #undef CRYPTO2
+ #undef CRYPTO3
+ 
++  ARM_BUILTIN_VFP_BASE,
++
++#include "arm_vfp_builtins.def"
++
+   ARM_BUILTIN_NEON_BASE,
+   ARM_BUILTIN_NEON_LANE_CHECK = ARM_BUILTIN_NEON_BASE,
+ 
+@@ -542,8 +560,11 @@ enum arm_builtins
+   ARM_BUILTIN_MAX
+ };
+ 
++#define ARM_BUILTIN_VFP_PATTERN_START \
++  (ARM_BUILTIN_VFP_BASE + 1)
++
+ #define ARM_BUILTIN_NEON_PATTERN_START \
+-    (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data))
++  (ARM_BUILTIN_NEON_BASE + 1)
+ 
+ #undef CF
+ #undef VAR1
+@@ -895,6 +916,110 @@ arm_init_simd_builtin_scalar_types (void)
+ 					     "__builtin_neon_uti");
+ }
+ 
++/* Set up a NEON builtin.  */
++
++static void
++arm_init_neon_builtin (unsigned int fcode,
++		       neon_builtin_datum *d)
++{
++  bool print_type_signature_p = false;
++  char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 };
++  char namebuf[60];
++  tree ftype = NULL;
++  tree fndecl = NULL;
++
++  d->fcode = fcode;
++
++  /* We must track two variables here.  op_num is
++     the operand number as in the RTL pattern.  This is
++     required to access the mode (e.g. V4SF mode) of the
++     argument, from which the base type can be derived.
++     arg_num is an index in to the qualifiers data, which
++     gives qualifiers to the type (e.g. const unsigned).
++     The reason these two variables may differ by one is the
++     void return type.  While all return types take the 0th entry
++     in the qualifiers array, there is no operand for them in the
++     RTL pattern.  */
++  int op_num = insn_data[d->code].n_operands - 1;
++  int arg_num = d->qualifiers[0] & qualifier_void
++    ? op_num + 1
++    : op_num;
++  tree return_type = void_type_node, args = void_list_node;
++  tree eltype;
++
++  /* Build a function type directly from the insn_data for this
++     builtin.  The build_function_type () function takes care of
++     removing duplicates for us.  */
++  for (; op_num >= 0; arg_num--, op_num--)
++    {
++      machine_mode op_mode = insn_data[d->code].operand[op_num].mode;
++      enum arm_type_qualifiers qualifiers = d->qualifiers[arg_num];
++
++      if (qualifiers & qualifier_unsigned)
++	{
++	  type_signature[arg_num] = 'u';
++	  print_type_signature_p = true;
++	}
++      else if (qualifiers & qualifier_poly)
++	{
++	  type_signature[arg_num] = 'p';
++	  print_type_signature_p = true;
++	}
++      else
++	type_signature[arg_num] = 's';
++
++      /* Skip an internal operand for vget_{low, high}.  */
++      if (qualifiers & qualifier_internal)
++	continue;
++
++      /* Some builtins have different user-facing types
++	 for certain arguments, encoded in d->mode.  */
++      if (qualifiers & qualifier_map_mode)
++	op_mode = d->mode;
++
++      /* For pointers, we want a pointer to the basic type
++	 of the vector.  */
++      if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode))
++	op_mode = GET_MODE_INNER (op_mode);
++
++      eltype = arm_simd_builtin_type
++	(op_mode,
++	 (qualifiers & qualifier_unsigned) != 0,
++	 (qualifiers & qualifier_poly) != 0);
++      gcc_assert (eltype != NULL);
++
++      /* Add qualifiers.  */
++      if (qualifiers & qualifier_const)
++	eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
++
++      if (qualifiers & qualifier_pointer)
++	eltype = build_pointer_type (eltype);
++
++      /* If we have reached arg_num == 0, we are at a non-void
++	 return type.  Otherwise, we are still processing
++	 arguments.  */
++      if (arg_num == 0)
++	return_type = eltype;
++      else
++	args = tree_cons (NULL_TREE, eltype, args);
++    }
++
++  ftype = build_function_type (return_type, args);
++
++  gcc_assert (ftype != NULL);
++
++  if (print_type_signature_p)
++    snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s_%s",
++	      d->name, type_signature);
++  else
++    snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s",
++	      d->name);
++
++  fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD,
++				 NULL, NULL_TREE);
++  arm_builtin_decls[fcode] = fndecl;
++}
++
+ /* Set up all the NEON builtins, even builtins for instructions that are not
+    in the current target ISA to allow the user to compile particular modules
+    with different target specific options that differ from the command line
+@@ -924,103 +1049,22 @@ arm_init_neon_builtins (void)
+ 
+   for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++, fcode++)
+     {
+-      bool print_type_signature_p = false;
+-      char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 };
+       neon_builtin_datum *d = &neon_builtin_data[i];
+-      char namebuf[60];
+-      tree ftype = NULL;
+-      tree fndecl = NULL;
+-
+-      d->fcode = fcode;
+-
+-      /* We must track two variables here.  op_num is
+-	 the operand number as in the RTL pattern.  This is
+-	 required to access the mode (e.g. V4SF mode) of the
+-	 argument, from which the base type can be derived.
+-	 arg_num is an index in to the qualifiers data, which
+-	 gives qualifiers to the type (e.g. const unsigned).
+-	 The reason these two variables may differ by one is the
+-	 void return type.  While all return types take the 0th entry
+-	 in the qualifiers array, there is no operand for them in the
+-	 RTL pattern.  */
+-      int op_num = insn_data[d->code].n_operands - 1;
+-      int arg_num = d->qualifiers[0] & qualifier_void
+-		      ? op_num + 1
+-		      : op_num;
+-      tree return_type = void_type_node, args = void_list_node;
+-      tree eltype;
+-
+-      /* Build a function type directly from the insn_data for this
+-	 builtin.  The build_function_type () function takes care of
+-	 removing duplicates for us.  */
+-      for (; op_num >= 0; arg_num--, op_num--)
+-	{
+-	  machine_mode op_mode = insn_data[d->code].operand[op_num].mode;
+-	  enum arm_type_qualifiers qualifiers = d->qualifiers[arg_num];
+-
+-	  if (qualifiers & qualifier_unsigned)
+-	    {
+-	      type_signature[arg_num] = 'u';
+-	      print_type_signature_p = true;
+-	    }
+-	  else if (qualifiers & qualifier_poly)
+-	    {
+-	      type_signature[arg_num] = 'p';
+-	      print_type_signature_p = true;
+-	    }
+-	  else
+-	    type_signature[arg_num] = 's';
+-
+-	  /* Skip an internal operand for vget_{low, high}.  */
+-	  if (qualifiers & qualifier_internal)
+-	    continue;
+-
+-	  /* Some builtins have different user-facing types
+-	     for certain arguments, encoded in d->mode.  */
+-	  if (qualifiers & qualifier_map_mode)
+-	      op_mode = d->mode;
+-
+-	  /* For pointers, we want a pointer to the basic type
+-	     of the vector.  */
+-	  if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode))
+-	    op_mode = GET_MODE_INNER (op_mode);
+-
+-	  eltype = arm_simd_builtin_type
+-		     (op_mode,
+-		      (qualifiers & qualifier_unsigned) != 0,
+-		      (qualifiers & qualifier_poly) != 0);
+-	  gcc_assert (eltype != NULL);
+-
+-	  /* Add qualifiers.  */
+-	  if (qualifiers & qualifier_const)
+-	    eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
+-
+-	  if (qualifiers & qualifier_pointer)
+-	      eltype = build_pointer_type (eltype);
+-
+-	  /* If we have reached arg_num == 0, we are at a non-void
+-	     return type.  Otherwise, we are still processing
+-	     arguments.  */
+-	  if (arg_num == 0)
+-	    return_type = eltype;
+-	  else
+-	    args = tree_cons (NULL_TREE, eltype, args);
+-	}
+-
+-      ftype = build_function_type (return_type, args);
++      arm_init_neon_builtin (fcode, d);
++    }
++}
+ 
+-      gcc_assert (ftype != NULL);
++/* Set up all the scalar floating point builtins.  */
+ 
+-      if (print_type_signature_p)
+-	snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s_%s",
+-		  d->name, type_signature);
+-      else
+-	snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s",
+-		  d->name);
++static void
++arm_init_vfp_builtins (void)
++{
++  unsigned int i, fcode = ARM_BUILTIN_VFP_PATTERN_START;
+ 
+-      fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD,
+-				     NULL, NULL_TREE);
+-      arm_builtin_decls[fcode] = fndecl;
++  for (i = 0; i < ARRAY_SIZE (vfp_builtin_data); i++, fcode++)
++    {
++      neon_builtin_datum *d = &vfp_builtin_data[i];
++      arm_init_neon_builtin (fcode, d);
+     }
+ }
+ 
+@@ -1768,14 +1812,14 @@ arm_init_builtins (void)
+   if (TARGET_HARD_FLOAT)
+     {
+       arm_init_neon_builtins ();
+-
++      arm_init_vfp_builtins ();
+       arm_init_crypto_builtins ();
+     }
+ 
+   if (TARGET_CRC32)
+     arm_init_crc32_builtins ();
+ 
+-  if (TARGET_VFP && TARGET_HARD_FLOAT)
++  if (TARGET_HARD_FLOAT)
+     {
+       tree ftype_set_fpscr
+ 	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
+@@ -1789,6 +1833,17 @@ arm_init_builtins (void)
+ 	= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
+ 				ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+     }
++
++  if (use_cmse)
++    {
++      tree ftype_cmse_nonsecure_caller
++	= build_function_type_list (unsigned_type_node, NULL);
++      arm_builtin_decls[ARM_BUILTIN_CMSE_NONSECURE_CALLER]
++	= add_builtin_function ("__builtin_arm_cmse_nonsecure_caller",
++				ftype_cmse_nonsecure_caller,
++				ARM_BUILTIN_CMSE_NONSECURE_CALLER, BUILT_IN_MD,
++				NULL, NULL_TREE);
++    }
+ }
+ 
+ /* Return the ARM builtin for CODE.  */
+@@ -2211,40 +2266,16 @@ constant_arg:
+   return target;
+ }
+ 
+-/* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds.
+-   Most of these are "special" because they don't have symbolic
+-   constants defined per-instruction or per instruction-variant. Instead, the
+-   required info is looked up in the table neon_builtin_data.  */
++/* Expand a neon builtin.  This is also used for vfp builtins, which behave in
++   the same way.  These builtins are "special" because they don't have symbolic
++   constants defined per-instruction or per instruction-variant.  Instead, the
++   required info is looked up in the NEON_BUILTIN_DATA record that is passed
++   into the function.  */
++
+ static rtx
+-arm_expand_neon_builtin (int fcode, tree exp, rtx target)
++arm_expand_neon_builtin_1 (int fcode, tree exp, rtx target,
++			   neon_builtin_datum *d)
+ {
+-  /* Check in the context of the function making the call whether the
+-     builtin is supported.  */
+-  if (! TARGET_NEON)
+-    {
+-      fatal_error (input_location,
+-		   "You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use these intrinsics.");
+-      return const0_rtx;
+-    }
+-
+-  if (fcode == ARM_BUILTIN_NEON_LANE_CHECK)
+-    {
+-      /* Builtin is only to check bounds of the lane passed to some intrinsics
+-	 that are implemented with gcc vector extensions in arm_neon.h.  */
+-
+-      tree nlanes = CALL_EXPR_ARG (exp, 0);
+-      gcc_assert (TREE_CODE (nlanes) == INTEGER_CST);
+-      rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1));
+-      if (CONST_INT_P (lane_idx))
+-	neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp);
+-      else
+-	error ("%Klane index must be a constant immediate", exp);
+-      /* Don't generate any RTL.  */
+-      return const0_rtx;
+-    }
+-
+-  neon_builtin_datum *d =
+-		&neon_builtin_data[fcode - ARM_BUILTIN_NEON_PATTERN_START];
+   enum insn_code icode = d->code;
+   builtin_arg args[SIMD_MAX_BUILTIN_ARGS + 1];
+   int num_args = insn_data[d->code].n_operands;
+@@ -2260,8 +2291,8 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+       /* We have four arrays of data, each indexed in a different fashion.
+ 	 qualifiers - element 0 always describes the function return type.
+ 	 operands - element 0 is either the operand for return value (if
+-	   the function has a non-void return type) or the operand for the
+-	   first argument.
++	 the function has a non-void return type) or the operand for the
++	 first argument.
+ 	 expr_args - element 0 always holds the first argument.
+ 	 args - element 0 is always used for the return type.  */
+       int qualifiers_k = k;
+@@ -2283,7 +2314,7 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+ 	  bool op_const_int_p =
+ 	    (CONST_INT_P (arg)
+ 	     && (*insn_data[icode].operand[operands_k].predicate)
+-		(arg, insn_data[icode].operand[operands_k].mode));
++	     (arg, insn_data[icode].operand[operands_k].mode));
+ 	  args[k] = op_const_int_p ? NEON_ARG_CONSTANT : NEON_ARG_COPY_TO_REG;
+ 	}
+       else if (d->qualifiers[qualifiers_k] & qualifier_pointer)
+@@ -2296,8 +2327,68 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+   /* The interface to arm_expand_neon_args expects a 0 if
+      the function is void, and a 1 if it is not.  */
+   return arm_expand_neon_args
+-	  (target, d->mode, fcode, icode, !is_void, exp,
+-	   &args[1]);
++    (target, d->mode, fcode, icode, !is_void, exp,
++     &args[1]);
++}
++
++/* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds.
++   Most of these are "special" because they don't have symbolic
++   constants defined per-instruction or per instruction-variant.  Instead, the
++   required info is looked up in the table neon_builtin_data.  */
++
++static rtx
++arm_expand_neon_builtin (int fcode, tree exp, rtx target)
++{
++  if (fcode >= ARM_BUILTIN_NEON_BASE && ! TARGET_NEON)
++    {
++      fatal_error (input_location,
++		   "You must enable NEON instructions"
++		   " (e.g. -mfloat-abi=softfp -mfpu=neon)"
++		   " to use these intrinsics.");
++      return const0_rtx;
++    }
++
++  if (fcode == ARM_BUILTIN_NEON_LANE_CHECK)
++    {
++      /* Builtin is only to check bounds of the lane passed to some intrinsics
++	 that are implemented with gcc vector extensions in arm_neon.h.  */
++
++      tree nlanes = CALL_EXPR_ARG (exp, 0);
++      gcc_assert (TREE_CODE (nlanes) == INTEGER_CST);
++      rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1));
++      if (CONST_INT_P (lane_idx))
++	neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp);
++      else
++	error ("%Klane index must be a constant immediate", exp);
++      /* Don't generate any RTL.  */
++      return const0_rtx;
++    }
++
++  neon_builtin_datum *d
++    = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_PATTERN_START];
++
++  return arm_expand_neon_builtin_1 (fcode, exp, target, d);
++}
++
++/* Expand a VFP builtin.  These builtins are treated like
++   neon builtins except that the data is looked up in table
++   VFP_BUILTIN_DATA.  */
++
++static rtx
++arm_expand_vfp_builtin (int fcode, tree exp, rtx target)
++{
++  if (fcode >= ARM_BUILTIN_VFP_BASE && ! TARGET_HARD_FLOAT)
++    {
++      fatal_error (input_location,
++		   "You must enable VFP instructions"
++		   " to use these intrinsics.");
++      return const0_rtx;
++    }
++
++  neon_builtin_datum *d
++    = &vfp_builtin_data[fcode - ARM_BUILTIN_VFP_PATTERN_START];
++
++  return arm_expand_neon_builtin_1 (fcode, exp, target, d);
+ }
+ 
+ /* Expand an expression EXP that calls a built-in function,
+@@ -2337,13 +2428,18 @@ arm_expand_builtin (tree exp,
+   if (fcode >= ARM_BUILTIN_NEON_BASE)
+     return arm_expand_neon_builtin (fcode, exp, target);
+ 
++  if (fcode >= ARM_BUILTIN_VFP_BASE)
++    return arm_expand_vfp_builtin (fcode, exp, target);
++
+   /* Check in the context of the function making the call whether the
+      builtin is supported.  */
+   if (fcode >= ARM_BUILTIN_CRYPTO_BASE
+       && (!TARGET_CRYPTO || !TARGET_HARD_FLOAT))
+     {
+       fatal_error (input_location,
+-		   "You must enable crypto intrinsics (e.g. include -mfloat-abi=softfp -mfpu=crypto-neon...) to use these intrinsics.");
++		   "You must enable crypto instructions"
++		   " (e.g. include -mfloat-abi=softfp -mfpu=crypto-neon...)"
++		   " to use these intrinsics.");
+       return const0_rtx;
+     }
+ 
+@@ -2368,6 +2464,12 @@ arm_expand_builtin (tree exp,
+       emit_insn (pat);
+       return target;
+ 
++    case ARM_BUILTIN_CMSE_NONSECURE_CALLER:
++      target = gen_reg_rtx (SImode);
++      op0 = arm_return_addr (0, NULL_RTX);
++      emit_insn (gen_addsi3 (target, op0, const1_rtx));
++      return target;
++
+     case ARM_BUILTIN_TEXTRMSB:
+     case ARM_BUILTIN_TEXTRMUB:
+     case ARM_BUILTIN_TEXTRMSH:
+@@ -2995,7 +3097,7 @@ arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+   tree new_fenv_var, reload_fenv, restore_fnenv;
+   tree update_call, atomic_feraiseexcept, hold_fnclex;
+ 
+-  if (!TARGET_VFP || !TARGET_HARD_FLOAT)
++  if (!TARGET_HARD_FLOAT)
+     return;
+ 
+   /* Generate the equivalent of :
+--- a/src/gcc/config/arm/arm-c.c
++++ b/src/gcc/config/arm/arm-c.c
+@@ -76,6 +76,14 @@ arm_cpu_builtins (struct cpp_reader* pfile)
+ 
+   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
+ 
++  if (arm_arch8 && !arm_arch_notm)
++    {
++      if (arm_arch_cmse && use_cmse)
++	builtin_define_with_int_value ("__ARM_FEATURE_CMSE", 3);
++      else
++	builtin_define ("__ARM_FEATURE_CMSE");
++    }
++
+   if (TARGET_ARM_FEATURE_LDREX)
+     builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
+ 				   TARGET_ARM_FEATURE_LDREX);
+@@ -86,6 +94,9 @@ arm_cpu_builtins (struct cpp_reader* pfile)
+ 		      ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB)
+ 		       || TARGET_ARM_ARCH_ISA_THUMB >=2));
+ 
++  def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",
++		      TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_FPU_ARMV8);
++
+   def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD);
+ 
+   builtin_define_with_int_value ("__ARM_SIZEOF_MINIMAL_ENUM",
+@@ -128,17 +139,24 @@ arm_cpu_builtins (struct cpp_reader* pfile)
+   if (TARGET_SOFT_FLOAT)
+     builtin_define ("__SOFTFP__");
+ 
+-  def_or_undef_macro (pfile, "__VFP_FP__", TARGET_VFP);
++  builtin_define ("__VFP_FP__");
+ 
+   if (TARGET_ARM_FP)
+     builtin_define_with_int_value ("__ARM_FP", TARGET_ARM_FP);
+   else
+     cpp_undef (pfile, "__ARM_FP");
+ 
+-  if (arm_fp16_format == ARM_FP16_FORMAT_IEEE)
+-    builtin_define ("__ARM_FP16_FORMAT_IEEE");
+-  if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
+-    builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE");
++  def_or_undef_macro (pfile, "__ARM_FP16_FORMAT_IEEE",
++		      arm_fp16_format == ARM_FP16_FORMAT_IEEE);
++  def_or_undef_macro (pfile, "__ARM_FP16_FORMAT_ALTERNATIVE",
++		      arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE);
++  def_or_undef_macro (pfile, "__ARM_FP16_ARGS",
++		      arm_fp16_format != ARM_FP16_FORMAT_NONE);
++
++  def_or_undef_macro (pfile, "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC",
++		      TARGET_VFP_FP16INST);
++  def_or_undef_macro (pfile, "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC",
++		      TARGET_NEON_FP16INST);
+ 
+   def_or_undef_macro (pfile, "__ARM_FEATURE_FMA", TARGET_FMA);
+   def_or_undef_macro (pfile, "__ARM_NEON__", TARGET_NEON);
+--- a/src/gcc/config/arm/arm-cores.def
++++ b/src/gcc/config/arm/arm-cores.def
+@@ -166,15 +166,21 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_
+ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ 
+ /* V8 Architecture Processors */
++ARM_CORE("cortex-m23",	cortexm23, cortexm23,	8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m)
+ ARM_CORE("cortex-a32",	cortexa32, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
++ARM_CORE("cortex-m33",	cortexm33, cortexm33,	8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
+ ARM_CORE("cortex-a35",	cortexa35, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
+ ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
++ARM_CORE("cortex-a73",	cortexa73, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ ARM_CORE("exynos-m1",	exynosm1,  exynosm1,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
+-ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
++ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ ARM_CORE("xgene1",      xgene1,    xgene1,      8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A),            xgene1)
+ 
+ /* V8 big.LITTLE implementations */
+ ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
++ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
++ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
++
+--- /dev/null
++++ b/src/gcc/config/arm/arm-flags.h
+@@ -0,0 +1,212 @@
++/* Flags used to identify the presence of processor capabilities.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_ARM_FLAGS_H
++#define GCC_ARM_FLAGS_H
++
++/* Flags used to identify the presence of processor capabilities.  */
++
++/* Bit values used to identify processor capabilities.  */
++#define FL_NONE	      (0U)		/* No flags.  */
++#define FL_ANY	      (0xffffffffU)	/* All flags.  */
++#define FL_CO_PROC    (1U << 0)		/* Has external co-processor bus.  */
++#define FL_ARCH3M     (1U << 1)		/* Extended multiply.  */
++#define FL_MODE26     (1U << 2)		/* 26-bit mode support.  */
++#define FL_MODE32     (1U << 3)		/* 32-bit mode support.  */
++#define FL_ARCH4      (1U << 4)		/* Architecture rel 4.  */
++#define FL_ARCH5      (1U << 5)		/* Architecture rel 5.  */
++#define FL_THUMB      (1U << 6)		/* Thumb aware.  */
++#define FL_LDSCHED    (1U << 7)		/* Load scheduling necessary.  */
++#define FL_STRONG     (1U << 8)		/* StrongARM.  */
++#define FL_ARCH5E     (1U << 9)		/* DSP extensions to v5.  */
++#define FL_XSCALE     (1U << 10)	/* XScale.  */
++/* spare	      (1U << 11) */
++#define FL_ARCH6      (1U << 12)	/* Architecture rel 6.  Adds
++					   media instructions.  */
++#define FL_VFPV2      (1U << 13)	/* Vector Floating Point V2.  */
++#define FL_WBUF	      (1U << 14)	/* Schedule for write buffer ops.
++					   Note: ARM6 & 7 derivatives only.  */
++#define FL_ARCH6K     (1U << 15)	/* Architecture rel 6 K extensions.  */
++#define FL_THUMB2     (1U << 16)	/* Thumb-2.  */
++#define FL_NOTM	      (1U << 17)	/* Instructions not present in the 'M'
++					   profile.  */
++#define FL_THUMB_DIV  (1U << 18)	/* Hardware divide (Thumb mode).  */
++#define FL_VFPV3      (1U << 19)	/* Vector Floating Point V3.  */
++#define FL_NEON       (1U << 20)	/* Neon instructions.  */
++#define FL_ARCH7EM    (1U << 21)	/* Instructions present in the ARMv7E-M
++					   architecture.  */
++#define FL_ARCH7      (1U << 22)	/* Architecture 7.  */
++#define FL_ARM_DIV    (1U << 23)	/* Hardware divide (ARM mode).  */
++#define FL_ARCH8      (1U << 24)	/* Architecture 8.  */
++#define FL_CRC32      (1U << 25)	/* ARMv8 CRC32 instructions.  */
++#define FL_SMALLMUL   (1U << 26)	/* Small multiply supported.  */
++#define FL_NO_VOLATILE_CE  (1U << 27)	/* No volatile memory in IT block.  */
++
++#define FL_IWMMXT     (1U << 29)	/* XScale v2 or "Intel Wireless MMX
++					   technology".  */
++#define FL_IWMMXT2    (1U << 30)	/* "Intel Wireless MMX2
++					    technology".  */
++#define FL_ARCH6KZ    (1U << 31)	/* ARMv6KZ architecture.  */
++
++#define FL2_ARCH8_1   (1U << 0)		/* Architecture 8.1.  */
++#define FL2_ARCH8_2   (1U << 1)		/* Architecture 8.2.  */
++#define FL2_FP16INST  (1U << 2)		/* FP16 Instructions for ARMv8.2 and
++					   later.  */
++#define FL2_CMSE      (1U << 3)		/* ARMv8-M Security Extensions.  */
++
++/* Flags that only effect tuning, not available instructions.  */
++#define FL_TUNE		(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
++			 | FL_CO_PROC)
++
++#define FL_FOR_ARCH2		FL_NOTM
++#define FL_FOR_ARCH3		(FL_FOR_ARCH2 | FL_MODE32)
++#define FL_FOR_ARCH3M		(FL_FOR_ARCH3 | FL_ARCH3M)
++#define FL_FOR_ARCH4		(FL_FOR_ARCH3M | FL_ARCH4)
++#define FL_FOR_ARCH4T		(FL_FOR_ARCH4 | FL_THUMB)
++#define FL_FOR_ARCH5		(FL_FOR_ARCH4 | FL_ARCH5)
++#define FL_FOR_ARCH5T		(FL_FOR_ARCH5 | FL_THUMB)
++#define FL_FOR_ARCH5E		(FL_FOR_ARCH5 | FL_ARCH5E)
++#define FL_FOR_ARCH5TE		(FL_FOR_ARCH5E | FL_THUMB)
++#define FL_FOR_ARCH5TEJ		FL_FOR_ARCH5TE
++#define FL_FOR_ARCH6		(FL_FOR_ARCH5TE | FL_ARCH6)
++#define FL_FOR_ARCH6J		FL_FOR_ARCH6
++#define FL_FOR_ARCH6K		(FL_FOR_ARCH6 | FL_ARCH6K)
++#define FL_FOR_ARCH6Z		FL_FOR_ARCH6
++#define FL_FOR_ARCH6ZK		FL_FOR_ARCH6K
++#define FL_FOR_ARCH6KZ		(FL_FOR_ARCH6K | FL_ARCH6KZ)
++#define FL_FOR_ARCH6T2		(FL_FOR_ARCH6 | FL_THUMB2)
++#define FL_FOR_ARCH6M		(FL_FOR_ARCH6 & ~FL_NOTM)
++#define FL_FOR_ARCH7		((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
++#define FL_FOR_ARCH7A		(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
++#define FL_FOR_ARCH7VE		(FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
++#define FL_FOR_ARCH7R		(FL_FOR_ARCH7A | FL_THUMB_DIV)
++#define FL_FOR_ARCH7M		(FL_FOR_ARCH7 | FL_THUMB_DIV)
++#define FL_FOR_ARCH7EM		(FL_FOR_ARCH7M | FL_ARCH7EM)
++#define FL_FOR_ARCH8A		(FL_FOR_ARCH7VE | FL_ARCH8)
++#define FL2_FOR_ARCH8_1A	FL2_ARCH8_1
++#define FL2_FOR_ARCH8_2A	(FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
++#define FL_FOR_ARCH8M_BASE	(FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
++#define FL_FOR_ARCH8M_MAIN	(FL_FOR_ARCH7M | FL_ARCH8)
++
++/* There are too many feature bits to fit in a single word so the set of cpu and
++   fpu capabilities is a structure.  A feature set is created and manipulated
++   with the ARM_FSET macros.  */
++
++typedef struct
++{
++  unsigned cpu[2];
++} arm_feature_set;
++
++
++/* Initialize a feature set.  */
++
++#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
++
++#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
++#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
++
++/* Accessors.  */
++
++#define ARM_FSET_CPU1(S) ((S).cpu[0])
++#define ARM_FSET_CPU2(S) ((S).cpu[1])
++
++/* Useful combinations.  */
++
++#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
++#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
++
++/* Tests for a specific CPU feature.  */
++
++#define ARM_FSET_HAS_CPU1(A, F)  \
++  (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
++#define ARM_FSET_HAS_CPU2(A, F)  \
++  (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
++#define ARM_FSET_HAS_CPU(A, F1, F2)				\
++  (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
++
++/* Add a feature to a feature set.  */
++
++#define ARM_FSET_ADD_CPU1(DST, F)		\
++  do {						\
++    (DST).cpu[0] |= (F);			\
++  } while (0)
++
++#define ARM_FSET_ADD_CPU2(DST, F)		\
++  do {						\
++    (DST).cpu[1] |= (F);			\
++  } while (0)
++
++/* Remove a feature from a feature set.  */
++
++#define ARM_FSET_DEL_CPU1(DST, F)		\
++  do {						\
++    (DST).cpu[0] &= ~(F);			\
++  } while (0)
++
++#define ARM_FSET_DEL_CPU2(DST, F)		\
++  do {						\
++    (DST).cpu[1] &= ~(F);			\
++  } while (0)
++
++/* Union of feature sets.  */
++
++#define ARM_FSET_UNION(DST,F1,F2)		\
++  do {						\
++    (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];	\
++    (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];	\
++  } while (0)
++
++/* Intersection of feature sets.  */
++
++#define ARM_FSET_INTER(DST,F1,F2)		\
++  do {						\
++    (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];	\
++    (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];	\
++  } while (0)
++
++/* Exclusive disjunction.  */
++
++#define ARM_FSET_XOR(DST,F1,F2)				\
++  do {							\
++    (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];		\
++    (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];		\
++  } while (0)
++
++/* Difference of feature sets: F1 excluding the elements of F2.  */
++
++#define ARM_FSET_EXCLUDE(DST,F1,F2)		\
++  do {						\
++    (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];	\
++    (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];	\
++  } while (0)
++
++/* Test for an empty feature set.  */
++
++#define ARM_FSET_IS_EMPTY(A)		\
++  (!((A).cpu[0]) && !((A).cpu[1]))
++
++/* Tests whether the cpu features of A are a subset of B.  */
++
++#define ARM_FSET_CPU_SUBSET(A,B)					\
++  ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])				\
++   && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
++
++#endif /* GCC_ARM_FLAGS_H */
+--- a/src/gcc/config/arm/arm-fpus.def
++++ b/src/gcc/config/arm/arm-fpus.def
+@@ -19,30 +19,29 @@
+ 
+ /* Before using #include to read this file, define a macro:
+ 
+-      ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES)
++      ARM_FPU(NAME, REV, VFP_REGS, FEATURES)
+ 
+    The arguments are the fields of struct arm_fpu_desc.
+ 
+    genopt.sh assumes no whitespace up to the first "," in each entry.  */
+ 
+-ARM_FPU("vfp",		ARM_FP_MODEL_VFP, 2, VFP_REG_D16, FPU_FL_NONE)
+-ARM_FPU("vfpv3",	ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE)
+-ARM_FPU("vfpv3-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_FP16)
+-ARM_FPU("vfpv3-d16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_NONE)
+-ARM_FPU("vfpv3-d16-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_FP16)
+-ARM_FPU("vfpv3xd",	ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_NONE)
+-ARM_FPU("vfpv3xd-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_FP16)
+-ARM_FPU("neon",		ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON)
+-ARM_FPU("neon-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
+-ARM_FPU("vfpv4",	ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_FP16)
+-ARM_FPU("vfpv4-d16",	ARM_FP_MODEL_VFP, 4, VFP_REG_D16, FPU_FL_FP16)
+-ARM_FPU("fpv4-sp-d16",	ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, FPU_FL_FP16)
+-ARM_FPU("fpv5-sp-d16",	ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, FPU_FL_FP16)
+-ARM_FPU("fpv5-d16",	ARM_FP_MODEL_VFP, 5, VFP_REG_D16, FPU_FL_FP16)
+-ARM_FPU("neon-vfpv4",	ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
+-ARM_FPU("fp-armv8",	ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_FP16)
+-ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
+-ARM_FPU("crypto-neon-fp-armv8",
+-			ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
++ARM_FPU("vfp",		2, VFP_REG_D16, FPU_FL_NONE)
++ARM_FPU("vfpv3",	3, VFP_REG_D32, FPU_FL_NONE)
++ARM_FPU("vfpv3-fp16",	3, VFP_REG_D32, FPU_FL_FP16)
++ARM_FPU("vfpv3-d16",	3, VFP_REG_D16, FPU_FL_NONE)
++ARM_FPU("vfpv3-d16-fp16", 3, VFP_REG_D16, FPU_FL_FP16)
++ARM_FPU("vfpv3xd",	3, VFP_REG_SINGLE, FPU_FL_NONE)
++ARM_FPU("vfpv3xd-fp16",	3, VFP_REG_SINGLE, FPU_FL_FP16)
++ARM_FPU("neon",		3, VFP_REG_D32, FPU_FL_NEON)
++ARM_FPU("neon-fp16",	3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
++ARM_FPU("vfpv4",	4, VFP_REG_D32, FPU_FL_FP16)
++ARM_FPU("vfpv4-d16",	4, VFP_REG_D16, FPU_FL_FP16)
++ARM_FPU("fpv4-sp-d16",	4, VFP_REG_SINGLE, FPU_FL_FP16)
++ARM_FPU("fpv5-sp-d16",	5, VFP_REG_SINGLE, FPU_FL_FP16)
++ARM_FPU("fpv5-d16",	5, VFP_REG_D16, FPU_FL_FP16)
++ARM_FPU("neon-vfpv4",	4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
++ARM_FPU("fp-armv8",	8, VFP_REG_D32, FPU_FL_FP16)
++ARM_FPU("neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
++ARM_FPU("crypto-neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
+ /* Compatibility aliases.  */
+-ARM_FPU("vfp3",		ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE)
++ARM_FPU("vfp3",		3, VFP_REG_D32, FPU_FL_NONE)
+--- a/src/gcc/config/arm/arm-modes.def
++++ b/src/gcc/config/arm/arm-modes.def
+@@ -59,6 +59,7 @@ CC_MODE (CC_DGEU);
+ CC_MODE (CC_DGTU);
+ CC_MODE (CC_C);
+ CC_MODE (CC_N);
++CC_MODE (CC_V);
+ 
+ /* Vector modes.  */
+ VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
+--- a/src/gcc/config/arm/arm-opts.h
++++ b/src/gcc/config/arm/arm-opts.h
+@@ -25,6 +25,8 @@
+ #ifndef ARM_OPTS_H
+ #define ARM_OPTS_H
+ 
++#include "arm-flags.h"
++
+ /* The various ARM cores.  */
+ enum processor_type
+ {
+@@ -77,4 +79,24 @@ enum arm_tls_type {
+   TLS_GNU,
+   TLS_GNU2
+ };
++
++struct arm_arch_core_flag
++{
++  const char *const name;
++  const arm_feature_set flags;
++};
++
++static const struct arm_arch_core_flag arm_arch_core_flags[] =
++{
++#undef ARM_CORE
++#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
++  {NAME, FLAGS},
++#include "arm-cores.def"
++#undef ARM_CORE
++#undef ARM_ARCH
++#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
++  {NAME, FLAGS},
++#include "arm-arches.def"
++#undef ARM_ARCH
++};
+ #endif
+--- a/src/gcc/config/arm/arm-protos.h
++++ b/src/gcc/config/arm/arm-protos.h
+@@ -22,6 +22,8 @@
+ #ifndef GCC_ARM_PROTOS_H
+ #define GCC_ARM_PROTOS_H
+ 
++#include "arm-flags.h"
++
+ extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
+ extern int use_return_insn (int, rtx);
+ extern bool use_simple_return_p (void);
+@@ -31,6 +33,7 @@ extern int arm_volatile_func (void);
+ extern void arm_expand_prologue (void);
+ extern void arm_expand_epilogue (bool);
+ extern void arm_declare_function_name (FILE *, const char *, tree);
++extern void arm_asm_declare_function_name (FILE *, const char *, tree);
+ extern void thumb2_expand_return (bool);
+ extern const char *arm_strip_name_encoding (const char *);
+ extern void arm_asm_output_labelref (FILE *, const char *);
+@@ -50,8 +53,12 @@ extern tree arm_builtin_decl (unsigned code, bool initialize_p
+ 			      ATTRIBUTE_UNUSED);
+ extern void arm_init_builtins (void);
+ extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
+-
++extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high);
++extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
++						 bool high);
+ #ifdef RTX_CODE
++extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
++				      rtx label_ref);
+ extern bool arm_vector_mode_supported_p (machine_mode);
+ extern bool arm_small_register_classes_for_mode_p (machine_mode);
+ extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
+@@ -130,6 +137,7 @@ extern int arm_const_double_inline_cost (rtx);
+ extern bool arm_const_double_by_parts (rtx);
+ extern bool arm_const_double_by_immediates (rtx);
+ extern void arm_emit_call_insn (rtx, rtx, bool);
++bool detect_cmse_nonsecure_call (tree);
+ extern const char *output_call (rtx *);
+ void arm_emit_movpair (rtx, rtx);
+ extern const char *output_mov_long_double_arm_from_arm (rtx *);
+@@ -161,6 +169,7 @@ extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool)
+ extern const char *arm_output_iwmmxt_tinsr (rtx *);
+ extern unsigned int arm_sync_loop_insns (rtx , rtx *);
+ extern int arm_attr_length_push_multi(rtx, rtx);
++extern int arm_attr_length_pop_multi(rtx *, bool, bool);
+ extern void arm_expand_compare_and_swap (rtx op[]);
+ extern void arm_split_compare_and_swap (rtx op[]);
+ extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
+@@ -192,7 +201,6 @@ extern const char *thumb_call_via_reg (rtx);
+ extern void thumb_expand_movmemqi (rtx *);
+ extern rtx arm_return_addr (int, rtx);
+ extern void thumb_reload_out_hi (rtx *);
+-extern void thumb_reload_in_hi (rtx *);
+ extern void thumb_set_return_address (rtx, rtx);
+ extern const char *thumb1_output_casesi (rtx *);
+ extern const char *thumb2_output_casesi (rtx *);
+@@ -256,7 +264,6 @@ struct cpu_cost_table;
+ 
+ struct tune_params
+ {
+-  bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
+   const struct cpu_cost_table *insn_extra_cost;
+   bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
+   int (*branch_cost) (bool, bool);
+@@ -319,6 +326,7 @@ extern int vfp3_const_double_for_bits (rtx);
+ 
+ extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
+ 					   rtx);
++extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
+ extern bool arm_valid_symbolic_address_p (rtx);
+ extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
+ #endif /* RTX_CODE */
+@@ -344,184 +352,6 @@ extern void arm_cpu_cpp_builtins (struct cpp_reader *);
+ 
+ extern bool arm_is_constant_pool_ref (rtx);
+ 
+-/* Flags used to identify the presence of processor capabilities.  */
+-
+-/* Bit values used to identify processor capabilities.  */
+-#define FL_NONE	      (0)	      /* No flags.  */
+-#define FL_ANY	      (0xffffffff)    /* All flags.  */
+-#define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */
+-#define FL_ARCH3M     (1 << 1)        /* Extended multiply */
+-#define FL_MODE26     (1 << 2)        /* 26-bit mode support */
+-#define FL_MODE32     (1 << 3)        /* 32-bit mode support */
+-#define FL_ARCH4      (1 << 4)        /* Architecture rel 4 */
+-#define FL_ARCH5      (1 << 5)        /* Architecture rel 5 */
+-#define FL_THUMB      (1 << 6)        /* Thumb aware */
+-#define FL_LDSCHED    (1 << 7)	      /* Load scheduling necessary */
+-#define FL_STRONG     (1 << 8)	      /* StrongARM */
+-#define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */
+-#define FL_XSCALE     (1 << 10)	      /* XScale */
+-/* spare	      (1 << 11)	*/
+-#define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
+-					 media instructions.  */
+-#define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
+-#define FL_WBUF	      (1 << 14)	      /* Schedule for write buffer ops.
+-					 Note: ARM6 & 7 derivatives only.  */
+-#define FL_ARCH6K     (1 << 15)       /* Architecture rel 6 K extensions.  */
+-#define FL_THUMB2     (1 << 16)	      /* Thumb-2.  */
+-#define FL_NOTM	      (1 << 17)	      /* Instructions not present in the 'M'
+-					 profile.  */
+-#define FL_THUMB_DIV  (1 << 18)	      /* Hardware divide (Thumb mode).  */
+-#define FL_VFPV3      (1 << 19)       /* Vector Floating Point V3.  */
+-#define FL_NEON       (1 << 20)       /* Neon instructions.  */
+-#define FL_ARCH7EM    (1 << 21)	      /* Instructions present in the ARMv7E-M
+-					 architecture.  */
+-#define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
+-#define FL_ARM_DIV    (1 << 23)	      /* Hardware divide (ARM mode).  */
+-#define FL_ARCH8      (1 << 24)       /* Architecture 8.  */
+-#define FL_CRC32      (1 << 25)	      /* ARMv8 CRC32 instructions.  */
+-
+-#define FL_SMALLMUL   (1 << 26)       /* Small multiply supported.  */
+-#define FL_NO_VOLATILE_CE   (1 << 27) /* No volatile memory in IT block.  */
+-
+-#define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
+-#define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
+-#define FL_ARCH6KZ    (1 << 31)       /* ARMv6KZ architecture.  */
+-
+-#define FL2_ARCH8_1   (1 << 0)	      /* Architecture 8.1.  */
+-
+-/* Flags that only effect tuning, not available instructions.  */
+-#define FL_TUNE		(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
+-			 | FL_CO_PROC)
+-
+-#define FL_FOR_ARCH2	FL_NOTM
+-#define FL_FOR_ARCH3	(FL_FOR_ARCH2 | FL_MODE32)
+-#define FL_FOR_ARCH3M	(FL_FOR_ARCH3 | FL_ARCH3M)
+-#define FL_FOR_ARCH4	(FL_FOR_ARCH3M | FL_ARCH4)
+-#define FL_FOR_ARCH4T	(FL_FOR_ARCH4 | FL_THUMB)
+-#define FL_FOR_ARCH5	(FL_FOR_ARCH4 | FL_ARCH5)
+-#define FL_FOR_ARCH5T	(FL_FOR_ARCH5 | FL_THUMB)
+-#define FL_FOR_ARCH5E	(FL_FOR_ARCH5 | FL_ARCH5E)
+-#define FL_FOR_ARCH5TE	(FL_FOR_ARCH5E | FL_THUMB)
+-#define FL_FOR_ARCH5TEJ	FL_FOR_ARCH5TE
+-#define FL_FOR_ARCH6	(FL_FOR_ARCH5TE | FL_ARCH6)
+-#define FL_FOR_ARCH6J	FL_FOR_ARCH6
+-#define FL_FOR_ARCH6K	(FL_FOR_ARCH6 | FL_ARCH6K)
+-#define FL_FOR_ARCH6Z	FL_FOR_ARCH6
+-#define FL_FOR_ARCH6KZ	(FL_FOR_ARCH6K | FL_ARCH6KZ)
+-#define FL_FOR_ARCH6T2	(FL_FOR_ARCH6 | FL_THUMB2)
+-#define FL_FOR_ARCH6M	(FL_FOR_ARCH6 & ~FL_NOTM)
+-#define FL_FOR_ARCH7	((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
+-#define FL_FOR_ARCH7A	(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
+-#define FL_FOR_ARCH7VE	(FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
+-#define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_THUMB_DIV)
+-#define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_THUMB_DIV)
+-#define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
+-#define FL_FOR_ARCH8A	(FL_FOR_ARCH7VE | FL_ARCH8)
+-#define FL2_FOR_ARCH8_1A	FL2_ARCH8_1
+-
+-/* There are too many feature bits to fit in a single word so the set of cpu and
+-   fpu capabilities is a structure.  A feature set is created and manipulated
+-   with the ARM_FSET macros.  */
+-
+-typedef struct
+-{
+-  unsigned long cpu[2];
+-} arm_feature_set;
+-
+-
+-/* Initialize a feature set.  */
+-
+-#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
+-
+-#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
+-#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
+-
+-/* Accessors.  */
+-
+-#define ARM_FSET_CPU1(S) ((S).cpu[0])
+-#define ARM_FSET_CPU2(S) ((S).cpu[1])
+-
+-/* Useful combinations.  */
+-
+-#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
+-#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
+-
+-/* Tests for a specific CPU feature.  */
+-
+-#define ARM_FSET_HAS_CPU1(A, F)  \
+-  (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
+-#define ARM_FSET_HAS_CPU2(A, F)  \
+-  (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
+-#define ARM_FSET_HAS_CPU(A, F1, F2)				\
+-  (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
+-
+-/* Add a feature to a feature set.  */
+-
+-#define ARM_FSET_ADD_CPU1(DST, F)		\
+-  do {						\
+-    (DST).cpu[0] |= (F);			\
+-  } while (0)
+-
+-#define ARM_FSET_ADD_CPU2(DST, F)		\
+-  do {						\
+-    (DST).cpu[1] |= (F);			\
+-  } while (0)
+-
+-/* Remove a feature from a feature set.  */
+-
+-#define ARM_FSET_DEL_CPU1(DST, F)		\
+-  do {						\
+-    (DST).cpu[0] &= ~(F);			\
+-  } while (0)
+-
+-#define ARM_FSET_DEL_CPU2(DST, F)		\
+-  do {						\
+-    (DST).cpu[1] &= ~(F);			\
+-  } while (0)
+-
+-/* Union of feature sets.  */
+-
+-#define ARM_FSET_UNION(DST,F1,F2)		\
+-  do {						\
+-    (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];	\
+-    (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];	\
+-  } while (0)
+-
+-/* Intersection of feature sets.  */
+-
+-#define ARM_FSET_INTER(DST,F1,F2)		\
+-  do {						\
+-    (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];	\
+-    (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];	\
+-  } while (0)
+-
+-/* Exclusive disjunction.  */
+-
+-#define ARM_FSET_XOR(DST,F1,F2)				\
+-  do {							\
+-    (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];		\
+-    (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];		\
+-  } while (0)
+-
+-/* Difference of feature sets: F1 excluding the elements of F2.  */
+-
+-#define ARM_FSET_EXCLUDE(DST,F1,F2)		\
+-  do {						\
+-    (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];	\
+-    (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];	\
+-  } while (0)
+-
+-/* Test for an empty feature set.  */
+-
+-#define ARM_FSET_IS_EMPTY(A)		\
+-  (!((A).cpu[0]) && !((A).cpu[1]))
+-
+-/* Tests whether the cpu features of A are a subset of B.  */
+-
+-#define ARM_FSET_CPU_SUBSET(A,B)					\
+-  ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])				\
+-   && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
+-
+ /* The bits in this mask specify which
+    instructions we are allowed to generate.  */
+ extern arm_feature_set insn_flags;
+@@ -601,6 +431,9 @@ extern int arm_tune_cortex_a9;
+    interworking clean.  */
+ extern int arm_cpp_interwork;
+ 
++/* Nonzero if chip supports Thumb 1.  */
++extern int arm_arch_thumb1;
++
+ /* Nonzero if chip supports Thumb 2.  */
+ extern int arm_arch_thumb2;
+ 
+--- a/src/gcc/config/arm/arm-tables.opt
++++ b/src/gcc/config/arm/arm-tables.opt
+@@ -307,9 +307,15 @@ EnumValue
+ Enum(processor_type) String(cortex-a17.cortex-a7) Value(cortexa17cortexa7)
+ 
+ EnumValue
++Enum(processor_type) String(cortex-m23) Value(cortexm23)
++
++EnumValue
+ Enum(processor_type) String(cortex-a32) Value(cortexa32)
+ 
+ EnumValue
++Enum(processor_type) String(cortex-m33) Value(cortexm33)
++
++EnumValue
+ Enum(processor_type) String(cortex-a35) Value(cortexa35)
+ 
+ EnumValue
+@@ -322,6 +328,9 @@ EnumValue
+ Enum(processor_type) String(cortex-a72) Value(cortexa72)
+ 
+ EnumValue
++Enum(processor_type) String(cortex-a73) Value(cortexa73)
++
++EnumValue
+ Enum(processor_type) String(exynos-m1) Value(exynosm1)
+ 
+ EnumValue
+@@ -336,6 +345,12 @@ Enum(processor_type) String(cortex-a57.cortex-a53) Value(cortexa57cortexa53)
+ EnumValue
+ Enum(processor_type) String(cortex-a72.cortex-a53) Value(cortexa72cortexa53)
+ 
++EnumValue
++Enum(processor_type) String(cortex-a73.cortex-a35) Value(cortexa73cortexa35)
++
++EnumValue
++Enum(processor_type) String(cortex-a73.cortex-a53) Value(cortexa73cortexa53)
++
+ Enum
+ Name(arm_arch) Type(int)
+ Known ARM architectures (for use with the -march= option):
+@@ -428,10 +443,25 @@ EnumValue
+ Enum(arm_arch) String(armv8.1-a+crc) Value(28)
+ 
+ EnumValue
+-Enum(arm_arch) String(iwmmxt) Value(29)
++Enum(arm_arch) String(armv8.2-a) Value(29)
++
++EnumValue
++Enum(arm_arch) String(armv8.2-a+fp16) Value(30)
++
++EnumValue
++Enum(arm_arch) String(armv8-m.base) Value(31)
++
++EnumValue
++Enum(arm_arch) String(armv8-m.main) Value(32)
++
++EnumValue
++Enum(arm_arch) String(armv8-m.main+dsp) Value(33)
++
++EnumValue
++Enum(arm_arch) String(iwmmxt) Value(34)
+ 
+ EnumValue
+-Enum(arm_arch) String(iwmmxt2) Value(30)
++Enum(arm_arch) String(iwmmxt2) Value(35)
+ 
+ Enum
+ Name(arm_fpu) Type(int)
+--- a/src/gcc/config/arm/arm-tune.md
++++ b/src/gcc/config/arm/arm-tune.md
+@@ -32,8 +32,10 @@
+ 	cortexr4f,cortexr5,cortexr7,
+ 	cortexr8,cortexm7,cortexm4,
+ 	cortexm3,marvell_pj4,cortexa15cortexa7,
+-	cortexa17cortexa7,cortexa32,cortexa35,
+-	cortexa53,cortexa57,cortexa72,
++	cortexa17cortexa7,cortexm23,cortexa32,
++	cortexm33,cortexa35,cortexa53,
++	cortexa57,cortexa72,cortexa73,
+ 	exynosm1,qdf24xx,xgene1,
+-	cortexa57cortexa53,cortexa72cortexa53"
++	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
++	cortexa73cortexa53"
+ 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
+--- a/src/gcc/config/arm/arm.c
++++ b/src/gcc/config/arm/arm.c
+@@ -27,6 +27,7 @@
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "cfghooks.h"
+ #include "df.h"
+ #include "tm_p.h"
+@@ -61,6 +62,7 @@
+ #include "builtins.h"
+ #include "tm-constrs.h"
+ #include "rtl-iter.h"
++#include "gimplify.h"
+ 
+ /* This file should be included last.  */
+ #include "target-def.h"
+@@ -104,7 +106,6 @@ static void arm_print_operand_address (FILE *, machine_mode, rtx);
+ static bool arm_print_operand_punct_valid_p (unsigned char code);
+ static const char *fp_const_from_val (REAL_VALUE_TYPE *);
+ static arm_cc get_arm_condition_code (rtx);
+-static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
+ static const char *output_multi_immediate (rtx *, const char *, const char *,
+ 					   int, HOST_WIDE_INT);
+ static const char *shift_op (rtx, HOST_WIDE_INT *);
+@@ -135,6 +136,8 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
+ #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
+ static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
+ #endif
++static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
++static tree arm_handle_cmse_nonsecure_call (tree *, tree, tree, int, bool *);
+ static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
+ static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
+ static int arm_comp_type_attributes (const_tree, const_tree);
+@@ -164,12 +167,6 @@ static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
+ static bool arm_have_conditional_execution (void);
+ static bool arm_cannot_force_const_mem (machine_mode, rtx);
+ static bool arm_legitimate_constant_p (machine_mode, rtx);
+-static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
+-static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+-static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+-static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+-static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+-static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+ static bool arm_rtx_costs (rtx, machine_mode, int, int, int *, bool);
+ static int arm_address_cost (rtx, machine_mode, addr_space_t, bool);
+ static int arm_register_move_cost (machine_mode, reg_class_t, reg_class_t);
+@@ -249,8 +246,6 @@ static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
+ static bool arm_output_addr_const_extra (FILE *, rtx);
+ static bool arm_allocate_stack_slots_for_args (void);
+ static bool arm_warn_func_return (tree);
+-static const char *arm_invalid_parameter_type (const_tree t);
+-static const char *arm_invalid_return_type (const_tree t);
+ static tree arm_promoted_type (const_tree t);
+ static tree arm_convert_to_type (tree type, tree expr);
+ static bool arm_scalar_mode_supported_p (machine_mode);
+@@ -300,6 +295,9 @@ static void arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
+ static unsigned HOST_WIDE_INT arm_asan_shadow_offset (void);
+ 
+ static void arm_sched_fusion_priority (rtx_insn *, int, int *, int*);
++static bool arm_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT,
++				     const_tree);
++
+ 
+ /* Table of machine attributes.  */
+ static const struct attribute_spec arm_attribute_table[] =
+@@ -343,6 +341,11 @@ static const struct attribute_spec arm_attribute_table[] =
+   { "notshared",    0, 0, false, true, false, arm_handle_notshared_attribute,
+     false },
+ #endif
++  /* ARMv8-M Security Extensions support.  */
++  { "cmse_nonsecure_entry", 0, 0, true, false, false,
++    arm_handle_cmse_nonsecure_entry, false },
++  { "cmse_nonsecure_call", 0, 0, true, false, false,
++    arm_handle_cmse_nonsecure_call, true },
+   { NULL,           0, 0, false, false, false, NULL, false }
+ };
+ 
+@@ -463,7 +466,7 @@ static const struct attribute_spec arm_attribute_table[] =
+ #undef  TARGET_ASM_OUTPUT_MI_THUNK
+ #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
+ #undef  TARGET_ASM_CAN_OUTPUT_MI_THUNK
+-#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
++#define TARGET_ASM_CAN_OUTPUT_MI_THUNK arm_can_output_mi_thunk
+ 
+ #undef  TARGET_RTX_COSTS
+ #define TARGET_RTX_COSTS arm_rtx_costs
+@@ -654,12 +657,6 @@ static const struct attribute_spec arm_attribute_table[] =
+ #undef TARGET_PREFERRED_RELOAD_CLASS
+ #define TARGET_PREFERRED_RELOAD_CLASS arm_preferred_reload_class
+ 
+-#undef TARGET_INVALID_PARAMETER_TYPE
+-#define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
+-
+-#undef TARGET_INVALID_RETURN_TYPE
+-#define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
+-
+ #undef TARGET_PROMOTED_TYPE
+ #define TARGET_PROMOTED_TYPE arm_promoted_type
+ 
+@@ -820,6 +817,13 @@ int arm_arch8 = 0;
+ /* Nonzero if this chip supports the ARMv8.1 extensions.  */
+ int arm_arch8_1 = 0;
+ 
++/* Nonzero if this chip supports the ARM Architecture 8.2 extensions.  */
++int arm_arch8_2 = 0;
++
++/* Nonzero if this chip supports the FP16 instructions extension of ARM
++   Architecture 8.2.  */
++int arm_fp16_inst = 0;
++
+ /* Nonzero if this chip can benefit from load scheduling.  */
+ int arm_ld_sched = 0;
+ 
+@@ -852,6 +856,9 @@ int arm_tune_cortex_a9 = 0;
+    interworking clean.  */
+ int arm_cpp_interwork = 0;
+ 
++/* Nonzero if chip supports Thumb 1.  */
++int arm_arch_thumb1;
++
+ /* Nonzero if chip supports Thumb 2.  */
+ int arm_arch_thumb2;
+ 
+@@ -892,6 +899,9 @@ int arm_condexec_masklen = 0;
+ /* Nonzero if chip supports the ARMv8 CRC instructions.  */
+ int arm_arch_crc = 0;
+ 
++/* Nonzero if chip supports the ARMv8-M security extensions.  */
++int arm_arch_cmse = 0;
++
+ /* Nonzero if the core has a very small, high-latency, multiply unit.  */
+ int arm_m_profile_small_mul = 0;
+ 
+@@ -1684,8 +1694,7 @@ const struct cpu_cost_table v7m_extra_costs =
+ 
+ const struct tune_params arm_slowmul_tune =
+ {
+-  arm_slowmul_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1707,8 +1716,7 @@ const struct tune_params arm_slowmul_tune =
+ 
+ const struct tune_params arm_fastmul_tune =
+ {
+-  arm_fastmul_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1733,8 +1741,7 @@ const struct tune_params arm_fastmul_tune =
+ 
+ const struct tune_params arm_strongarm_tune =
+ {
+-  arm_fastmul_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1756,8 +1763,7 @@ const struct tune_params arm_strongarm_tune =
+ 
+ const struct tune_params arm_xscale_tune =
+ {
+-  arm_xscale_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   xscale_sched_adjust_cost,
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1779,8 +1785,7 @@ const struct tune_params arm_xscale_tune =
+ 
+ const struct tune_params arm_9e_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1802,8 +1807,7 @@ const struct tune_params arm_9e_tune =
+ 
+ const struct tune_params arm_marvell_pj4_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1825,8 +1829,7 @@ const struct tune_params arm_marvell_pj4_tune =
+ 
+ const struct tune_params arm_v6t2_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1850,7 +1853,6 @@ const struct tune_params arm_v6t2_tune =
+ /* Generic Cortex tuning.  Use more specific tunings if appropriate.  */
+ const struct tune_params arm_cortex_tune =
+ {
+-  arm_9e_rtx_costs,
+   &generic_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1873,7 +1875,6 @@ const struct tune_params arm_cortex_tune =
+ 
+ const struct tune_params arm_cortex_a8_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa8_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1896,7 +1897,6 @@ const struct tune_params arm_cortex_a8_tune =
+ 
+ const struct tune_params arm_cortex_a7_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa7_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1919,7 +1919,6 @@ const struct tune_params arm_cortex_a7_tune =
+ 
+ const struct tune_params arm_cortex_a15_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa15_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1942,7 +1941,6 @@ const struct tune_params arm_cortex_a15_tune =
+ 
+ const struct tune_params arm_cortex_a35_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa53_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1965,7 +1963,6 @@ const struct tune_params arm_cortex_a35_tune =
+ 
+ const struct tune_params arm_cortex_a53_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa53_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1988,7 +1985,6 @@ const struct tune_params arm_cortex_a53_tune =
+ 
+ const struct tune_params arm_cortex_a57_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa57_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2011,7 +2007,6 @@ const struct tune_params arm_cortex_a57_tune =
+ 
+ const struct tune_params arm_exynosm1_tune =
+ {
+-  arm_9e_rtx_costs,
+   &exynosm1_extra_costs,
+   NULL,						/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2034,7 +2029,6 @@ const struct tune_params arm_exynosm1_tune =
+ 
+ const struct tune_params arm_xgene1_tune =
+ {
+-  arm_9e_rtx_costs,
+   &xgene1_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2055,12 +2049,33 @@ const struct tune_params arm_xgene1_tune =
+   tune_params::SCHED_AUTOPREF_OFF
+ };
+ 
++const struct tune_params arm_qdf24xx_tune =
++{
++  &qdf24xx_extra_costs,
++  NULL,                                         /* Scheduler cost adjustment.  */
++  arm_default_branch_cost,
++  &arm_default_vec_cost,			/* Vectorizer costs.  */
++  1,						/* Constant limit.  */
++  2,						/* Max cond insns.  */
++  8,						/* Memset max inline.  */
++  4,						/* Issue rate.  */
++  ARM_PREFETCH_BENEFICIAL (0, -1, 64),
++  tune_params::PREF_CONST_POOL_FALSE,
++  tune_params::PREF_LDRD_TRUE,
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,	/* Thumb.  */
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,	/* ARM.  */
++  tune_params::DISPARAGE_FLAGS_ALL,
++  tune_params::PREF_NEON_64_FALSE,
++  tune_params::PREF_NEON_STRINGOPS_TRUE,
++  FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
++  tune_params::SCHED_AUTOPREF_FULL
++};
++
+ /* Branches can be dual-issued on Cortex-A5, so conditional execution is
+    less appealing.  Set max_insns_skipped to a low value.  */
+ 
+ const struct tune_params arm_cortex_a5_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa5_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_cortex_a5_branch_cost,
+@@ -2083,7 +2098,6 @@ const struct tune_params arm_cortex_a5_tune =
+ 
+ const struct tune_params arm_cortex_a9_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa9_extra_costs,
+   cortex_a9_sched_adjust_cost,
+   arm_default_branch_cost,
+@@ -2106,7 +2120,6 @@ const struct tune_params arm_cortex_a9_tune =
+ 
+ const struct tune_params arm_cortex_a12_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa12_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2127,6 +2140,28 @@ const struct tune_params arm_cortex_a12_tune =
+   tune_params::SCHED_AUTOPREF_OFF
+ };
+ 
++const struct tune_params arm_cortex_a73_tune =
++{
++  &cortexa57_extra_costs,
++  NULL,						/* Sched adj cost.  */
++  arm_default_branch_cost,
++  &arm_default_vec_cost,			/* Vectorizer costs.  */
++  1,						/* Constant limit.  */
++  2,						/* Max cond insns.  */
++  8,						/* Memset max inline.  */
++  2,						/* Issue rate.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  tune_params::PREF_CONST_POOL_FALSE,
++  tune_params::PREF_LDRD_TRUE,
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,		/* Thumb.  */
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,		/* ARM.  */
++  tune_params::DISPARAGE_FLAGS_ALL,
++  tune_params::PREF_NEON_64_FALSE,
++  tune_params::PREF_NEON_STRINGOPS_TRUE,
++  FUSE_OPS (tune_params::FUSE_AES_AESMC | tune_params::FUSE_MOVW_MOVT),
++  tune_params::SCHED_AUTOPREF_FULL
++};
++
+ /* armv7m tuning.  On Cortex-M4 cores for example, MOVW/MOVT take a single
+    cycle to execute each.  An LDR from the constant pool also takes two cycles
+    to execute, but mildly increases pipelining opportunity (consecutive
+@@ -2136,7 +2171,6 @@ const struct tune_params arm_cortex_a12_tune =
+ 
+ const struct tune_params arm_v7m_tune =
+ {
+-  arm_9e_rtx_costs,
+   &v7m_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_cortex_m_branch_cost,
+@@ -2161,7 +2195,6 @@ const struct tune_params arm_v7m_tune =
+ 
+ const struct tune_params arm_cortex_m7_tune =
+ {
+-  arm_9e_rtx_costs,
+   &v7m_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_cortex_m7_branch_cost,
+@@ -2183,11 +2216,11 @@ const struct tune_params arm_cortex_m7_tune =
+ };
+ 
+ /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
+-   arm_v6t2_tune. It is used for cortex-m0, cortex-m1 and cortex-m0plus.  */
++   arm_v6t2_tune.  It is used for cortex-m0, cortex-m1, cortex-m0plus and
++   cortex-m23.  */
+ const struct tune_params arm_v6m_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,                        /* Vectorizer costs.  */
+@@ -2209,8 +2242,7 @@ const struct tune_params arm_v6m_tune =
+ 
+ const struct tune_params arm_fa726te_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,				/* Insn extra costs.  */
+   fa726te_sched_adjust_cost,
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -2264,16 +2296,18 @@ static const struct processors *arm_selected_arch;
+ static const struct processors *arm_selected_cpu;
+ static const struct processors *arm_selected_tune;
+ 
+-/* The name of the preprocessor macro to define for this architecture.  */
++/* The name of the preprocessor macro to define for this architecture.  PROFILE
++   is replaced by the architecture name (eg. 8A) in arm_option_override () and
++   is thus chosen to be big enough to hold the longest architecture name.  */
+ 
+-char arm_arch_name[] = "__ARM_ARCH_0UNK__";
++char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
+ 
+ /* Available values for -mfpu=.  */
+ 
+ const struct arm_fpu_desc all_fpus[] =
+ {
+-#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES) \
+-  { NAME, MODEL, REV, VFP_REGS, FEATURES },
++#define ARM_FPU(NAME, REV, VFP_REGS, FEATURES) \
++  { NAME, REV, VFP_REGS, FEATURES },
+ #include "arm-fpus.def"
+ #undef ARM_FPU
+ };
+@@ -2752,8 +2786,8 @@ arm_option_check_internal (struct gcc_options *opts)
+   const struct arm_fpu_desc *fpu_desc = &all_fpus[opts->x_arm_fpu_index];
+ 
+   /* iWMMXt and NEON are incompatible.  */
+-    if (TARGET_IWMMXT && TARGET_VFP
+-      && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
++    if (TARGET_IWMMXT
++	&& ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
+     error ("iWMMXt and NEON are incompatible");
+ 
+   /* Make sure that the processor choice does not conflict with any of the
+@@ -2907,7 +2941,8 @@ arm_option_override_internal (struct gcc_options *opts,
+   if (! opts_set->x_arm_restrict_it)
+     opts->x_arm_restrict_it = arm_arch8;
+ 
+-  if (!TARGET_THUMB2_P (opts->x_target_flags))
++  /* ARM execution state and M profile don't have [restrict] IT.  */
++  if (!TARGET_THUMB2_P (opts->x_target_flags) || !arm_arch_notm)
+     opts->x_arm_restrict_it = 0;
+ 
+   /* Enable -munaligned-access by default for
+@@ -2918,7 +2953,8 @@ arm_option_override_internal (struct gcc_options *opts,
+ 
+      Disable -munaligned-access by default for
+      - all pre-ARMv6 architecture-based processors
+-     - ARMv6-M architecture-based processors.  */
++     - ARMv6-M architecture-based processors
++     - ARMv8-M Baseline processors.  */
+ 
+   if (! opts_set->x_unaligned_access)
+     {
+@@ -3170,6 +3206,8 @@ arm_option_override (void)
+   arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
+   arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
+   arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
++  arm_arch8_2 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_2);
++  arm_arch_thumb1 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB);
+   arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
+   arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
+ 
+@@ -3184,7 +3222,15 @@ arm_option_override (void)
+   arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE);
+   arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
+   arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
++  arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE);
+   arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL);
++  arm_fp16_inst = ARM_FSET_HAS_CPU2 (insn_flags, FL2_FP16INST);
++  if (arm_fp16_inst)
++    {
++      if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
++	error ("selected fp16 options are incompatible.");
++      arm_fp16_format = ARM_FP16_FORMAT_IEEE;
++    }
+ 
+   /* V5 code we generate is completely interworking capable, so we turn off
+      TARGET_INTERWORK here to avoid many tests later on.  */
+@@ -3222,10 +3268,8 @@ arm_option_override (void)
+   /* If soft-float is specified then don't use FPU.  */
+   if (TARGET_SOFT_FLOAT)
+     arm_fpu_attr = FPU_NONE;
+-  else if (TARGET_VFP)
+-    arm_fpu_attr = FPU_VFP;
+   else
+-    gcc_unreachable();
++    arm_fpu_attr = FPU_VFP;
+ 
+   if (TARGET_AAPCS_BASED)
+     {
+@@ -3245,15 +3289,14 @@ arm_option_override (void)
+       if (arm_abi == ARM_ABI_IWMMXT)
+ 	arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
+       else if (arm_float_abi == ARM_FLOAT_ABI_HARD
+-	       && TARGET_HARD_FLOAT
+-	       && TARGET_VFP)
++	       && TARGET_HARD_FLOAT)
+ 	arm_pcs_default = ARM_PCS_AAPCS_VFP;
+       else
+ 	arm_pcs_default = ARM_PCS_AAPCS;
+     }
+   else
+     {
+-      if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
++      if (arm_float_abi == ARM_FLOAT_ABI_HARD)
+ 	sorry ("-mfloat-abi=hard and VFP");
+ 
+       if (arm_abi == ARM_ABI_APCS)
+@@ -3298,6 +3341,20 @@ arm_option_override (void)
+ 	}
+     }
+ 
++  if (TARGET_VXWORKS_RTP)
++    {
++      if (!global_options_set.x_arm_pic_data_is_text_relative)
++	arm_pic_data_is_text_relative = 0;
++    }
++  else if (flag_pic
++	   && !arm_pic_data_is_text_relative
++	   && !(global_options_set.x_target_flags & MASK_SINGLE_PIC_BASE))
++    /* When text & data segments don't have a fixed displacement, the
++       intended use is with a single, read only, pic base register.
++       Unless the user explicitly requested not to do that, set
++       it.  */
++    target_flags |= MASK_SINGLE_PIC_BASE;
++
+   /* If stack checking is disabled, we can use r10 as the PIC register,
+      which keeps r9 available.  The EABI specifies r9 as the PIC register.  */
+   if (flag_pic && TARGET_SINGLE_PIC_BASE)
+@@ -3329,10 +3386,6 @@ arm_option_override (void)
+ 	arm_pic_register = pic_register;
+     }
+ 
+-  if (TARGET_VXWORKS_RTP
+-      && !global_options_set.x_arm_pic_data_is_text_relative)
+-    arm_pic_data_is_text_relative = 0;
+-
+   /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores.  */
+   if (fix_cm3_ldrd == 2)
+     {
+@@ -3436,6 +3489,9 @@ arm_option_override (void)
+   if (target_slow_flash_data)
+     arm_disable_literal_pool = true;
+ 
++  if (use_cmse && !arm_arch_cmse)
++    error ("target CPU does not support ARMv8-M Security Extensions");
++
+   /* Disable scheduling fusion by default if it's not armv7 processor
+      or doesn't prefer ldrd/strd.  */
+   if (flag_schedule_fusion == 2
+@@ -3568,6 +3624,9 @@ arm_compute_func_type (void)
+   else
+     type |= arm_isr_value (TREE_VALUE (a));
+ 
++  if (lookup_attribute ("cmse_nonsecure_entry", attr))
++    type |= ARM_FT_CMSE_ENTRY;
++
+   return type;
+ }
+ 
+@@ -3794,6 +3853,11 @@ use_return_insn (int iscond, rtx sibling)
+ 	return 0;
+     }
+ 
++  /* ARMv8-M nonsecure entry function need to use bxns to return and thus need
++     several instructions if anything needs to be popped.  */
++  if (saved_int_regs && IS_CMSE_ENTRY (func_type))
++    return 0;
++
+   /* If there are saved registers but the LR isn't saved, then we need
+      two instructions for the return.  */
+   if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
+@@ -3801,7 +3865,7 @@ use_return_insn (int iscond, rtx sibling)
+ 
+   /* Can't be done if any of the VFP regs are pushed,
+      since this also requires an insn.  */
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
+       if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
+ 	return 0;
+@@ -3899,7 +3963,7 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
+     {
+     case SET:
+       /* See if we can use movw.  */
+-      if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
++      if (TARGET_HAVE_MOVT && (i & 0xffff0000) == 0)
+ 	return 1;
+       else
+ 	/* Otherwise, try mvn.  */
+@@ -4118,7 +4182,7 @@ optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
+      yield a shorter sequence, we may as well use zero.  */
+   insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
+   if (best_start != 0
+-      && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
++      && ((HOST_WIDE_INT_1U << best_start) < val))
+     {
+       insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
+       if (insns2 <= insns1)
+@@ -4949,7 +5013,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
+   if (mode == VOIDmode)
+     mode = GET_MODE (*op1);
+ 
+-  maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
++  maxval = (HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1)) - 1;
+ 
+   /* For DImode, we have GE/LT/GEU/LTU comparisons.  In ARM mode
+      we can also use cmp/cmpeq for GTU/LEU.  GT/LE must be either
+@@ -5255,7 +5319,6 @@ arm_function_value_regno_p (const unsigned int regno)
+   if (regno == ARG_REGISTER (1)
+       || (TARGET_32BIT
+ 	  && TARGET_AAPCS_BASED
+-	  && TARGET_VFP
+ 	  && TARGET_HARD_FLOAT
+ 	  && regno == FIRST_VFP_REGNUM)
+       || (TARGET_IWMMXT_ABI
+@@ -5274,7 +5337,7 @@ arm_apply_result_size (void)
+ 
+   if (TARGET_32BIT)
+     {
+-      if (TARGET_HARD_FLOAT_ABI && TARGET_VFP)
++      if (TARGET_HARD_FLOAT_ABI)
+ 	size += 32;
+       if (TARGET_IWMMXT_ABI)
+ 	size += 8;
+@@ -5549,7 +5612,7 @@ aapcs_vfp_sub_candidate (const_tree type, machine_mode *modep)
+     {
+     case REAL_TYPE:
+       mode = TYPE_MODE (type);
+-      if (mode != DFmode && mode != SFmode)
++      if (mode != DFmode && mode != SFmode && mode != HFmode)
+ 	return -1;
+ 
+       if (*modep == VOIDmode)
+@@ -5722,7 +5785,7 @@ use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
+   if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
+     return false;
+ 
+-  return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT &&
++  return (TARGET_32BIT && TARGET_HARD_FLOAT &&
+ 	  (TARGET_VFP_DOUBLE || !is_double));
+ }
+ 
+@@ -5797,11 +5860,16 @@ aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+ 						&pcum->aapcs_vfp_rcount);
+ }
+ 
++/* Implement the allocate field in aapcs_cp_arg_layout.  See the comment there
++   for the behaviour of this function.  */
++
+ static bool
+ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+ 		    const_tree type  ATTRIBUTE_UNUSED)
+ {
+-  int shift = GET_MODE_SIZE (pcum->aapcs_vfp_rmode) / GET_MODE_SIZE (SFmode);
++  int rmode_size
++    = MAX (GET_MODE_SIZE (pcum->aapcs_vfp_rmode), GET_MODE_SIZE (SFmode));
++  int shift = rmode_size / GET_MODE_SIZE (SFmode);
+   unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1;
+   int regno;
+ 
+@@ -5850,6 +5918,9 @@ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+   return false;
+ }
+ 
++/* Implement the allocate_return_reg field in aapcs_cp_arg_layout.  See the
++   comment there for the behaviour of this function.  */
++
+ static rtx
+ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
+ 			       machine_mode mode,
+@@ -5940,13 +6011,13 @@ static struct
+      required for a return from FUNCTION_ARG.  */
+   bool (*allocate) (CUMULATIVE_ARGS *, machine_mode, const_tree);
+ 
+-  /* Return true if a result of mode MODE (or type TYPE if MODE is
+-     BLKmode) is can be returned in this co-processor's registers.  */
++  /* Return true if a result of mode MODE (or type TYPE if MODE is BLKmode) can
++     be returned in this co-processor's registers.  */
+   bool (*is_return_candidate) (enum arm_pcs, machine_mode, const_tree);
+ 
+-  /* Allocate and return an RTX element to hold the return type of a
+-     call, this routine must not fail and will only be called if
+-     is_return_candidate returned true with the same parameters.  */
++  /* Allocate and return an RTX element to hold the return type of a call.  This
++     routine must not fail and will only be called if is_return_candidate
++     returned true with the same parameters.  */
+   rtx (*allocate_return_reg) (enum arm_pcs, machine_mode, const_tree);
+ 
+   /* Finish processing this argument and prepare to start processing
+@@ -6561,6 +6632,185 @@ arm_handle_notshared_attribute (tree *node,
+ }
+ #endif
+ 
++/* This function returns true if a function with declaration FNDECL and type
++   FNTYPE uses the stack to pass arguments or return variables and false
++   otherwise.  This is used for functions with the attributes
++   'cmse_nonsecure_call' or 'cmse_nonsecure_entry' and this function will issue
++   diagnostic messages if the stack is used.  NAME is the name of the attribute
++   used.  */
++
++static bool
++cmse_func_args_or_return_in_stack (tree fndecl, tree name, tree fntype)
++{
++  function_args_iterator args_iter;
++  CUMULATIVE_ARGS args_so_far_v;
++  cumulative_args_t args_so_far;
++  bool first_param = true;
++  tree arg_type, prev_arg_type = NULL_TREE, ret_type;
++
++  /* Error out if any argument is passed on the stack.  */
++  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
++  args_so_far = pack_cumulative_args (&args_so_far_v);
++  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
++    {
++      rtx arg_rtx;
++      machine_mode arg_mode = TYPE_MODE (arg_type);
++
++      prev_arg_type = arg_type;
++      if (VOID_TYPE_P (arg_type))
++	continue;
++
++      if (!first_param)
++	arm_function_arg_advance (args_so_far, arg_mode, arg_type, true);
++      arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type, true);
++      if (!arg_rtx
++	  || arm_arg_partial_bytes (args_so_far, arg_mode, arg_type, true))
++	{
++	  error ("%qE attribute not available to functions with arguments "
++		 "passed on the stack", name);
++	  return true;
++	}
++      first_param = false;
++    }
++
++  /* Error out for variadic functions since we cannot control how many
++     arguments will be passed and thus stack could be used.  stdarg_p () is not
++     used for the checking to avoid browsing arguments twice.  */
++  if (prev_arg_type != NULL_TREE && !VOID_TYPE_P (prev_arg_type))
++    {
++      error ("%qE attribute not available to functions with variable number "
++	     "of arguments", name);
++      return true;
++    }
++
++  /* Error out if return value is passed on the stack.  */
++  ret_type = TREE_TYPE (fntype);
++  if (arm_return_in_memory (ret_type, fntype))
++    {
++      error ("%qE attribute not available to functions that return value on "
++	     "the stack", name);
++      return true;
++    }
++  return false;
++}
++
++/* Called upon detection of the use of the cmse_nonsecure_entry attribute, this
++   function will check whether the attribute is allowed here and will add the
++   attribute to the function declaration tree or otherwise issue a warning.  */
++
++static tree
++arm_handle_cmse_nonsecure_entry (tree *node, tree name,
++				 tree /* args */,
++				 int /* flags */,
++				 bool *no_add_attrs)
++{
++  tree fndecl;
++
++  if (!use_cmse)
++    {
++      *no_add_attrs = true;
++      warning (OPT_Wattributes, "%qE attribute ignored without -mcmse option.",
++	       name);
++      return NULL_TREE;
++    }
++
++  /* Ignore attribute for function types.  */
++  if (TREE_CODE (*node) != FUNCTION_DECL)
++    {
++      warning (OPT_Wattributes, "%qE attribute only applies to functions",
++	       name);
++      *no_add_attrs = true;
++      return NULL_TREE;
++    }
++
++  fndecl = *node;
++
++  /* Warn for static linkage functions.  */
++  if (!TREE_PUBLIC (fndecl))
++    {
++      warning (OPT_Wattributes, "%qE attribute has no effect on functions "
++	       "with static linkage", name);
++      *no_add_attrs = true;
++      return NULL_TREE;
++    }
++
++  *no_add_attrs |= cmse_func_args_or_return_in_stack (fndecl, name,
++						TREE_TYPE (fndecl));
++  return NULL_TREE;
++}
++
++
++/* Called upon detection of the use of the cmse_nonsecure_call attribute, this
++   function will check whether the attribute is allowed here and will add the
++   attribute to the function type tree or otherwise issue a diagnostic.  The
++   reason we check this at declaration time is to only allow the use of the
++   attribute with declarations of function pointers and not function
++   declarations.  This function checks NODE is of the expected type and issues
++   diagnostics otherwise using NAME.  If it is not of the expected type
++   *NO_ADD_ATTRS will be set to true.  */
++
++static tree
++arm_handle_cmse_nonsecure_call (tree *node, tree name,
++				 tree /* args */,
++				 int /* flags */,
++				 bool *no_add_attrs)
++{
++  tree decl = NULL_TREE, fntype = NULL_TREE;
++  tree type;
++
++  if (!use_cmse)
++    {
++      *no_add_attrs = true;
++      warning (OPT_Wattributes, "%qE attribute ignored without -mcmse option.",
++	       name);
++      return NULL_TREE;
++    }
++
++  if (TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == TYPE_DECL)
++    {
++      decl = *node;
++      fntype = TREE_TYPE (decl);
++    }
++
++  while (fntype != NULL_TREE && TREE_CODE (fntype) == POINTER_TYPE)
++    fntype = TREE_TYPE (fntype);
++
++  if (!decl || TREE_CODE (fntype) != FUNCTION_TYPE)
++    {
++	warning (OPT_Wattributes, "%qE attribute only applies to base type of a "
++		 "function pointer", name);
++	*no_add_attrs = true;
++	return NULL_TREE;
++    }
++
++  *no_add_attrs |= cmse_func_args_or_return_in_stack (NULL, name, fntype);
++
++  if (*no_add_attrs)
++    return NULL_TREE;
++
++  /* Prevent trees being shared among function types with and without
++     cmse_nonsecure_call attribute.  */
++  type = TREE_TYPE (decl);
++
++  type = build_distinct_type_copy (type);
++  TREE_TYPE (decl) = type;
++  fntype = type;
++
++  while (TREE_CODE (fntype) != FUNCTION_TYPE)
++    {
++      type = fntype;
++      fntype = TREE_TYPE (fntype);
++      fntype = build_distinct_type_copy (fntype);
++      TREE_TYPE (type) = fntype;
++    }
++
++  /* Construct a type attribute and add it to the function type.  */
++  tree attrs = tree_cons (get_identifier ("cmse_nonsecure_call"), NULL_TREE,
++			  TYPE_ATTRIBUTES (fntype));
++  TYPE_ATTRIBUTES (fntype) = attrs;
++  return NULL_TREE;
++}
++
+ /* Return 0 if the attributes for two types are incompatible, 1 if they
+    are compatible, and 2 if they are nearly compatible (which causes a
+    warning to be generated).  */
+@@ -6601,6 +6851,14 @@ arm_comp_type_attributes (const_tree type1, const_tree type2)
+   if (l1 != l2)
+     return 0;
+ 
++  l1 = lookup_attribute ("cmse_nonsecure_call",
++			 TYPE_ATTRIBUTES (type1)) != NULL;
++  l2 = lookup_attribute ("cmse_nonsecure_call",
++			 TYPE_ATTRIBUTES (type2)) != NULL;
++
++  if (l1 != l2)
++    return 0;
++
+   return 1;
+ }
+ 
+@@ -6711,7 +6969,7 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
+      may be used both as target of the call and base register for restoring
+      the VFP registers  */
+   if (TARGET_APCS_FRAME && TARGET_ARM
+-      && TARGET_HARD_FLOAT && TARGET_VFP
++      && TARGET_HARD_FLOAT
+       && decl && arm_is_long_call_p (decl))
+     return false;
+ 
+@@ -6727,6 +6985,20 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
+   if (IS_INTERRUPT (func_type))
+     return false;
+ 
++  /* ARMv8-M non-secure entry functions need to return with bxns which is only
++     generated for entry functions themselves.  */
++  if (IS_CMSE_ENTRY (arm_current_func_type ()))
++    return false;
++
++  /* We do not allow ARMv8-M non-secure calls to be turned into sibling calls,
++     this would complicate matters for later code generation.  */
++  if (TREE_CODE (exp) == CALL_EXPR)
++    {
++      tree fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
++      if (lookup_attribute ("cmse_nonsecure_call", TYPE_ATTRIBUTES (fntype)))
++	return false;
++    }
++
+   if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
+     {
+       /* Check that the return value locations are the same.  For
+@@ -7187,8 +7459,7 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer,
+     return 1;
+ 
+   use_ldrd = (TARGET_LDRD
+-	      && (mode == DImode
+-		  || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
++	      && (mode == DImode || mode == DFmode));
+ 
+   if (code == POST_INC || code == PRE_DEC
+       || ((code == PRE_INC || code == POST_DEC)
+@@ -7273,8 +7544,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
+     return 1;
+ 
+   use_ldrd = (TARGET_LDRD
+-	      && (mode == DImode
+-		  || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
++	      && (mode == DImode || mode == DFmode));
+ 
+   if (code == POST_INC || code == PRE_DEC
+       || ((code == PRE_INC || code == POST_DEC)
+@@ -7367,7 +7637,6 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
+ 
+   /* Standard coprocessor addressing modes.  */
+   if (TARGET_HARD_FLOAT
+-      && TARGET_VFP
+       && (mode == SFmode || mode == DFmode))
+     return (code == CONST_INT && INTVAL (index) < 1024
+ 	    && INTVAL (index) > -1024
+@@ -7487,7 +7756,6 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
+   /* ??? Combine arm and thumb2 coprocessor addressing modes.  */
+   /* Standard coprocessor addressing modes.  */
+   if (TARGET_HARD_FLOAT
+-      && TARGET_VFP
+       && (mode == SFmode || mode == DFmode))
+     return (code == CONST_INT && INTVAL (index) < 1024
+ 	    /* Thumb-2 allows only > -256 index range for it's core register
+@@ -8033,8 +8301,7 @@ arm_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
+ 
+ 	  /* VFP addressing modes actually allow greater offsets, but for
+ 	     now we just stick with the lowest common denominator.  */
+-	  if (mode == DImode
+-	      || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
++	  if (mode == DImode || mode == DFmode)
+ 	    {
+ 	      low_n = n & 0x0f;
+ 	      n &= ~0x0f;
+@@ -8226,6 +8493,12 @@ arm_legitimate_constant_p_1 (machine_mode, rtx x)
+ static bool
+ thumb_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
+ {
++  /* Splitters for TARGET_USE_MOVT call arm_emit_movpair which creates high
++     RTX.  These RTX must therefore be allowed for Thumb-1 so that when run
++     for ARMv8-M Baseline or later the result is valid.  */
++  if (TARGET_HAVE_MOVT && GET_CODE (x) == HIGH)
++    x = XEXP (x, 0);
++
+   return (CONST_INT_P (x)
+ 	  || CONST_DOUBLE_P (x)
+ 	  || CONSTANT_ADDRESS_P (x)
+@@ -8312,7 +8585,9 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+     case CONST_INT:
+       if (outer == SET)
+ 	{
+-	  if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
++	  if (UINTVAL (x) < 256
++	      /* 16-bit constant.  */
++	      || (TARGET_HAVE_MOVT && !(INTVAL (x) & 0xffff0000)))
+ 	    return 0;
+ 	  if (thumb_shiftable_const (INTVAL (x)))
+ 	    return COSTS_N_INSNS (2);
+@@ -8329,8 +8604,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+ 	  int i;
+ 	  /* This duplicates the tests in the andsi3 expander.  */
+ 	  for (i = 9; i <= 31; i++)
+-	    if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
+-		|| (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
++	    if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (x)
++		|| (HOST_WIDE_INT_1 << i) - 1 == ~INTVAL (x))
+ 	      return COSTS_N_INSNS (2);
+ 	}
+       else if (outer == ASHIFT || outer == ASHIFTRT
+@@ -8393,1006 +8668,162 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+     }
+ }
+ 
+-static inline bool
+-arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
++/* Estimates the size cost of thumb1 instructions.
++   For now most of the code is copied from thumb1_rtx_costs. We need more
++   fine grain tuning when we have more related test cases.  */
++static inline int
++thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+ {
+   machine_mode mode = GET_MODE (x);
+-  enum rtx_code subcode;
+-  rtx operand;
+-  enum rtx_code code = GET_CODE (x);
+-  *total = 0;
++  int words, cost;
+ 
+   switch (code)
+     {
+-    case MEM:
+-      /* Memory costs quite a lot for the first word, but subsequent words
+-	 load at the equivalent of a single insn each.  */
+-      *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
+-      return true;
+-
+-    case DIV:
+-    case MOD:
+-    case UDIV:
+-    case UMOD:
+-      if (TARGET_HARD_FLOAT && mode == SFmode)
+-	*total = COSTS_N_INSNS (2);
+-      else if (TARGET_HARD_FLOAT && mode == DFmode && !TARGET_VFP_SINGLE)
+-	*total = COSTS_N_INSNS (4);
+-      else
+-	*total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    case ROTATE:
+-      if (REG_P (XEXP (x, 1)))
+-	*total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
+-      else if (!CONST_INT_P (XEXP (x, 1)))
+-	*total = rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-
+-      /* Fall through */
++    case ASHIFT:
++    case ASHIFTRT:
++    case LSHIFTRT:
+     case ROTATERT:
+-      if (mode != SImode)
+-	{
+-	  *total += COSTS_N_INSNS (4);
+-	  return true;
+-	}
++      return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
+ 
+-      /* Fall through */
+-    case ASHIFT: case LSHIFTRT: case ASHIFTRT:
+-      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      if (mode == DImode)
+-	{
+-	  *total += COSTS_N_INSNS (3);
+-	  return true;
+-	}
++    case PLUS:
++    case MINUS:
++      /* Thumb-1 needs two instructions to fulfill shiftadd/shiftsub0/shiftsub1
++	 defined by RTL expansion, especially for the expansion of
++	 multiplication.  */
++      if ((GET_CODE (XEXP (x, 0)) == MULT
++	   && power_of_two_operand (XEXP (XEXP (x,0),1), SImode))
++	  || (GET_CODE (XEXP (x, 1)) == MULT
++	      && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode)))
++	return COSTS_N_INSNS (2);
++      /* On purpose fall through for normal RTX.  */
++    case COMPARE:
++    case NEG:
++    case NOT:
++      return COSTS_N_INSNS (1);
+ 
+-      *total += COSTS_N_INSNS (1);
+-      /* Increase the cost of complex shifts because they aren't any faster,
+-         and reduce dual issue opportunities.  */
+-      if (arm_tune_cortex_a9
+-	  && outer != SET && !CONST_INT_P (XEXP (x, 1)))
+-	++*total;
++    case MULT:
++      if (CONST_INT_P (XEXP (x, 1)))
++        {
++          /* Thumb1 mul instruction can't operate on const. We must Load it
++             into a register first.  */
++          int const_size = thumb1_size_rtx_costs (XEXP (x, 1), CONST_INT, SET);
++	  /* For the targets which have a very small and high-latency multiply
++	     unit, we prefer to synthesize the mult with up to 5 instructions,
++	     giving a good balance between size and performance.  */
++	  if (arm_arch6m && arm_m_profile_small_mul)
++	    return COSTS_N_INSNS (5);
++	  else
++	    return COSTS_N_INSNS (1) + const_size;
++        }
++      return COSTS_N_INSNS (1);
+ 
+-      return true;
++    case SET:
++      /* A SET doesn't have a mode, so let's look at the SET_DEST to get
++	 the mode.  */
++      words = ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x))));
++      cost = COSTS_N_INSNS (words);
++      if (satisfies_constraint_J (SET_SRC (x))
++	  || satisfies_constraint_K (SET_SRC (x))
++	     /* Too big an immediate for a 2-byte mov, using MOVT.  */
++	  || (CONST_INT_P (SET_SRC (x))
++	      && UINTVAL (SET_SRC (x)) >= 256
++	      && TARGET_HAVE_MOVT
++	      && satisfies_constraint_j (SET_SRC (x)))
++	     /* thumb1_movdi_insn.  */
++	  || ((words > 1) && MEM_P (SET_SRC (x))))
++	cost += COSTS_N_INSNS (1);
++      return cost;
+ 
+-    case MINUS:
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-	  if (CONST_INT_P (XEXP (x, 0))
+-	      && const_ok_for_arm (INTVAL (XEXP (x, 0))))
+-	    {
+-	      *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	      return true;
+-	    }
++    case CONST_INT:
++      if (outer == SET)
++        {
++          if (UINTVAL (x) < 256)
++            return COSTS_N_INSNS (1);
++	  /* movw is 4byte long.  */
++	  if (TARGET_HAVE_MOVT && !(INTVAL (x) & 0xffff0000))
++	    return COSTS_N_INSNS (2);
++	  /* See split "TARGET_THUMB1 && satisfies_constraint_J".  */
++	  if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
++            return COSTS_N_INSNS (2);
++	  /* See split "TARGET_THUMB1 && satisfies_constraint_K".  */
++          if (thumb_shiftable_const (INTVAL (x)))
++            return COSTS_N_INSNS (2);
++          return COSTS_N_INSNS (3);
++        }
++      else if ((outer == PLUS || outer == COMPARE)
++               && INTVAL (x) < 256 && INTVAL (x) > -256)
++        return 0;
++      else if ((outer == IOR || outer == XOR || outer == AND)
++               && INTVAL (x) < 256 && INTVAL (x) >= -256)
++        return COSTS_N_INSNS (1);
++      else if (outer == AND)
++        {
++          int i;
++          /* This duplicates the tests in the andsi3 expander.  */
++          for (i = 9; i <= 31; i++)
++            if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (x)
++                || (HOST_WIDE_INT_1 << i) - 1 == ~INTVAL (x))
++              return COSTS_N_INSNS (2);
++        }
++      else if (outer == ASHIFT || outer == ASHIFTRT
++               || outer == LSHIFTRT)
++        return 0;
++      return COSTS_N_INSNS (2);
+ 
+-	  if (CONST_INT_P (XEXP (x, 1))
+-	      && const_ok_for_arm (INTVAL (XEXP (x, 1))))
+-	    {
+-	      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	      return true;
+-	    }
++    case CONST:
++    case CONST_DOUBLE:
++    case LABEL_REF:
++    case SYMBOL_REF:
++      return COSTS_N_INSNS (3);
+ 
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      if (CONST_DOUBLE_P (XEXP (x, 0))
+-		  && arm_const_double_rtx (XEXP (x, 0)))
+-		{
+-		  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-		  return true;
+-		}
+-
+-	      if (CONST_DOUBLE_P (XEXP (x, 1))
+-		  && arm_const_double_rtx (XEXP (x, 1)))
+-		{
+-		  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-		  return true;
+-		}
+-
+-	      return false;
+-	    }
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-
+-      *total = COSTS_N_INSNS (1);
+-      if (CONST_INT_P (XEXP (x, 0))
+-	  && const_ok_for_arm (INTVAL (XEXP (x, 0))))
+-	{
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  return true;
+-	}
+-
+-      subcode = GET_CODE (XEXP (x, 1));
+-      if (subcode == ASHIFT || subcode == ASHIFTRT
+-	  || subcode == LSHIFTRT
+-	  || subcode == ROTATE || subcode == ROTATERT)
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 1), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      /* A shift as a part of RSB costs no more than RSB itself.  */
+-      if (GET_CODE (XEXP (x, 0)) == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, code, 0, speed);
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode))
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 1), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE
+-	  || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  if (REG_P (XEXP (XEXP (x, 1), 0))
+-	      && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM)
+-	    *total += COSTS_N_INSNS (1);
+-
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-
+-    case PLUS:
+-      if (code == PLUS && arm_arch6 && mode == SImode
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), VOIDmode,
+-			      GET_CODE (XEXP (x, 0)), 0, speed);
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  return true;
+-	}
+-
+-      /* MLA: All arguments must be registers.  We filter out
+-	 multiplication by a power of two, so that we fall down into
+-	 the code below.  */
+-      if (GET_CODE (XEXP (x, 0)) == MULT
+-	  && !power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  /* The cost comes from the cost of the multiply.  */
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      if (CONST_DOUBLE_P (XEXP (x, 1))
+-		  && arm_const_double_rtx (XEXP (x, 1)))
+-		{
+-		  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-		  return true;
+-		}
+-
+-	      return false;
+-	    }
+-
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-
+-      if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE
+-	  || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), mode, code,
+-						 1, speed);
+-	  if (REG_P (XEXP (XEXP (x, 0), 0))
+-	      && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM)
+-	    *total += COSTS_N_INSNS (1);
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-
+-    case AND: case XOR: case IOR:
+-
+-      /* Normally the frame registers will be spilt into reg+const during
+-	 reload, so it is a bad idea to combine them with other instructions,
+-	 since then they might not be moved outside of loops.  As a compromise
+-	 we allow integration with ops that have a constant as their second
+-	 operand.  */
+-      if (REG_OR_SUBREG_REG (XEXP (x, 0))
+-	  && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
+-	  && !CONST_INT_P (XEXP (x, 1)))
+-	*total = COSTS_N_INSNS (1);
+-
+-      if (mode == DImode)
+-	{
+-	  *total += COSTS_N_INSNS (2);
+-	  if (CONST_INT_P (XEXP (x, 1))
+-	      && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
+-	    {
+-	      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	      return true;
+-	    }
+-
+-	  return false;
+-	}
+-
+-      *total += COSTS_N_INSNS (1);
+-      if (CONST_INT_P (XEXP (x, 1))
+-	  && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  return true;
+-	}
+-      subcode = GET_CODE (XEXP (x, 0));
+-      if (subcode == ASHIFT || subcode == ASHIFTRT
+-	  || subcode == LSHIFTRT
+-	  || subcode == ROTATE || subcode == ROTATERT)
+-	{
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == UMIN || subcode == UMAX
+-	  || subcode == SMIN || subcode == SMAX)
+-	{
+-	  *total = COSTS_N_INSNS (3);
+-	  return true;
+-	}
+-
+-      return false;
+-
+-    case MULT:
+-      /* This should have been handled by the CPU specific routines.  */
+-      gcc_unreachable ();
+-
+-    case TRUNCATE:
+-      if (arm_arch3m && mode == SImode
+-	  && GET_CODE (XEXP (x, 0)) == LSHIFTRT
+-	  && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
+-	  && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
+-	      == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
+-	  && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
+-	{
+-	  *total = rtx_cost (XEXP (XEXP (x, 0), 0), VOIDmode, LSHIFTRT,
+-			     0, speed);
+-	  return true;
+-	}
+-      *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */
+-      return false;
+-
+-    case NEG:
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-      /* Fall through */
+-    case NOT:
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS(mode));
+-      if (mode == SImode && code == NOT)
+-	{
+-	  subcode = GET_CODE (XEXP (x, 0));
+-	  if (subcode == ASHIFT || subcode == ASHIFTRT
+-	      || subcode == LSHIFTRT
+-	      || subcode == ROTATE || subcode == ROTATERT
+-	      || (subcode == MULT
+-		  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)))
+-	    {
+-	      *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode,
+-				  0, speed);
+-	      /* Register shifts cost an extra cycle.  */
+-	      if (!CONST_INT_P (XEXP (XEXP (x, 0), 1)))
+-		*total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1),
+-							mode, subcode,
+-							1, speed);
+-	      return true;
+-	    }
+-	}
+-
+-      return false;
+-
+-    case IF_THEN_ELSE:
+-      if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
+-	{
+-	  *total = COSTS_N_INSNS (4);
+-	  return true;
+-	}
+-
+-      operand = XEXP (x, 0);
+-
+-      if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE
+-	     || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE)
+-	    && REG_P (XEXP (operand, 0))
+-	    && REGNO (XEXP (operand, 0)) == CC_REGNUM))
+-	*total += COSTS_N_INSNS (1);
+-      *total += rtx_cost (XEXP (x, 1), VOIDmode, code, 1, speed);
+-      *total += rtx_cost (XEXP (x, 2), VOIDmode, code, 2, speed);
+-      return true;
+-
+-    case NE:
+-      if (mode == SImode && XEXP (x, 1) == const0_rtx)
+-	{
+-	  *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  return true;
+-	}
+-      goto scc_insn;
+-
+-    case GE:
+-      if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
+-	  && mode == SImode && XEXP (x, 1) == const0_rtx)
+-	{
+-	  *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  return true;
+-	}
+-      goto scc_insn;
+-
+-    case LT:
+-      if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
+-	  && mode == SImode && XEXP (x, 1) == const0_rtx)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  return true;
+-	}
+-      goto scc_insn;
+-
+-    case EQ:
+-    case GT:
+-    case LE:
+-    case GEU:
+-    case LTU:
+-    case GTU:
+-    case LEU:
+-    case UNORDERED:
+-    case ORDERED:
+-    case UNEQ:
+-    case UNGE:
+-    case UNLT:
+-    case UNGT:
+-    case UNLE:
+-    scc_insn:
+-      /* SCC insns.  In the case where the comparison has already been
+-	 performed, then they cost 2 instructions.  Otherwise they need
+-	 an additional comparison before them.  */
+-      *total = COSTS_N_INSNS (2);
+-      if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
+-	{
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-    case COMPARE:
+-      if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
+-	{
+-	  *total = 0;
+-	  return true;
+-	}
+-
+-      *total += COSTS_N_INSNS (1);
+-      if (CONST_INT_P (XEXP (x, 1))
+-	  && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), VOIDmode, code, 0, speed);
+-	  return true;
+-	}
+-
+-      subcode = GET_CODE (XEXP (x, 0));
+-      if (subcode == ASHIFT || subcode == ASHIFTRT
+-	  || subcode == LSHIFTRT
+-	  || subcode == ROTATE || subcode == ROTATERT)
+-	{
+-	  mode = GET_MODE (XEXP (x, 0));
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  mode = GET_MODE (XEXP (x, 0));
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      return false;
+-
+-    case UMIN:
+-    case UMAX:
+-    case SMIN:
+-    case SMAX:
+-      *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      if (!CONST_INT_P (XEXP (x, 1))
+-	  || !const_ok_for_arm (INTVAL (XEXP (x, 1))))
+-	*total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-      return true;
+-
+-    case ABS:
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-      *total = COSTS_N_INSNS (1);
+-      if (mode == DImode)
+-	*total += COSTS_N_INSNS (3);
+-      return false;
+-
+-    case SIGN_EXTEND:
+-    case ZERO_EXTEND:
+-      *total = 0;
+-      if (GET_MODE_CLASS (mode) == MODE_INT)
+-	{
+-	  rtx op = XEXP (x, 0);
+-	  machine_mode opmode = GET_MODE (op);
+-
+-	  if (mode == DImode)
+-	    *total += COSTS_N_INSNS (1);
+-
+-	  if (opmode != SImode)
+-	    {
+-	      if (MEM_P (op))
+-		{
+-		  /* If !arm_arch4, we use one of the extendhisi2_mem
+-		     or movhi_bytes patterns for HImode.  For a QImode
+-		     sign extension, we first zero-extend from memory
+-		     and then perform a shift sequence.  */
+-		  if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND))
+-		    *total += COSTS_N_INSNS (2);
+-		}
+-	      else if (arm_arch6)
+-		*total += COSTS_N_INSNS (1);
+-
+-	      /* We don't have the necessary insn, so we need to perform some
+-		 other operation.  */
+-	      else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode)
+-		/* An and with constant 255.  */
+-		*total += COSTS_N_INSNS (1);
+-	      else
+-		/* A shift sequence.  Increase costs slightly to avoid
+-		   combining two shifts into an extend operation.  */
+-		*total += COSTS_N_INSNS (2) + 1;
+-	    }
+-
+-	  return false;
+-	}
+-
+-      switch (GET_MODE (XEXP (x, 0)))
+-	{
+-	case V8QImode:
+-	case V4HImode:
+-	case V2SImode:
+-	case V4QImode:
+-	case V2HImode:
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-
+-	default:
+-	  gcc_unreachable ();
+-	}
+-      gcc_unreachable ();
+-
+-    case ZERO_EXTRACT:
+-    case SIGN_EXTRACT:
+-      mode = GET_MODE (XEXP (x, 0));
+-      *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      return true;
+-
+-    case CONST_INT:
+-      if (const_ok_for_arm (INTVAL (x))
+-	  || const_ok_for_arm (~INTVAL (x)))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX,
+-						  INTVAL (x), NULL_RTX,
+-						  NULL_RTX, 0, 0));
+-      return true;
+-
+-    case CONST:
+-    case LABEL_REF:
+-    case SYMBOL_REF:
+-      *total = COSTS_N_INSNS (3);
+-      return true;
+-
+-    case HIGH:
+-      *total = COSTS_N_INSNS (1);
+-      return true;
+-
+-    case LO_SUM:
+-      *total = COSTS_N_INSNS (1);
+-      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      return true;
+-
+-    case CONST_DOUBLE:
+-      if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x)
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (4);
+-      return true;
+-
+-    case SET:
+-      /* The vec_extract patterns accept memory operands that require an
+-	 address reload.  Account for the cost of that reload to give the
+-	 auto-inc-dec pass an incentive to try to replace them.  */
+-      if (TARGET_NEON && MEM_P (SET_DEST (x))
+-	  && GET_CODE (SET_SRC (x)) == VEC_SELECT)
+-	{
+-	  mode = GET_MODE (SET_DEST (x));
+-	  *total = rtx_cost (SET_DEST (x), mode, code, 0, speed);
+-	  if (!neon_vector_mem_operand (SET_DEST (x), 2, true))
+-	    *total += COSTS_N_INSNS (1);
+-	  return true;
+-	}
+-      /* Likewise for the vec_set patterns.  */
+-      if (TARGET_NEON && GET_CODE (SET_SRC (x)) == VEC_MERGE
+-	  && GET_CODE (XEXP (SET_SRC (x), 0)) == VEC_DUPLICATE
+-	  && MEM_P (XEXP (XEXP (SET_SRC (x), 0), 0)))
+-	{
+-	  rtx mem = XEXP (XEXP (SET_SRC (x), 0), 0);
+-	  mode = GET_MODE (SET_DEST (x));
+-	  *total = rtx_cost (mem, mode, code, 0, speed);
+-	  if (!neon_vector_mem_operand (mem, 2, true))
+-	    *total += COSTS_N_INSNS (1);
+-	  return true;
+-	}
+-      return false;
+-
+-    case UNSPEC:
+-      /* We cost this as high as our memory costs to allow this to
+-	 be hoisted from loops.  */
+-      if (XINT (x, 1) == UNSPEC_PIC_UNIFIED)
+-	{
+-	  *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
+-	}
+-      return true;
+-
+-    case CONST_VECTOR:
+-      if (TARGET_NEON
+-	  && TARGET_HARD_FLOAT
+-	  && outer == SET
+-	  && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
+-	  && neon_immediate_valid_for_move (x, mode, NULL, NULL))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (4);
+-      return true;
+-
+-    default:
+-      *total = COSTS_N_INSNS (4);
+-      return false;
+-    }
+-}
+-
+-/* Estimates the size cost of thumb1 instructions.
+-   For now most of the code is copied from thumb1_rtx_costs. We need more
+-   fine grain tuning when we have more related test cases.  */
+-static inline int
+-thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+-{
+-  machine_mode mode = GET_MODE (x);
+-  int words;
+-
+-  switch (code)
+-    {
+-    case ASHIFT:
+-    case ASHIFTRT:
+-    case LSHIFTRT:
+-    case ROTATERT:
+-      return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
+-
+-    case PLUS:
+-    case MINUS:
+-      /* Thumb-1 needs two instructions to fulfill shiftadd/shiftsub0/shiftsub1
+-	 defined by RTL expansion, especially for the expansion of
+-	 multiplication.  */
+-      if ((GET_CODE (XEXP (x, 0)) == MULT
+-	   && power_of_two_operand (XEXP (XEXP (x,0),1), SImode))
+-	  || (GET_CODE (XEXP (x, 1)) == MULT
+-	      && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode)))
+-	return COSTS_N_INSNS (2);
+-      /* On purpose fall through for normal RTX.  */
+-    case COMPARE:
+-    case NEG:
+-    case NOT:
+-      return COSTS_N_INSNS (1);
+-
+-    case MULT:
+-      if (CONST_INT_P (XEXP (x, 1)))
+-        {
+-          /* Thumb1 mul instruction can't operate on const. We must Load it
+-             into a register first.  */
+-          int const_size = thumb1_size_rtx_costs (XEXP (x, 1), CONST_INT, SET);
+-	  /* For the targets which have a very small and high-latency multiply
+-	     unit, we prefer to synthesize the mult with up to 5 instructions,
+-	     giving a good balance between size and performance.  */
+-	  if (arm_arch6m && arm_m_profile_small_mul)
+-	    return COSTS_N_INSNS (5);
+-	  else
+-	    return COSTS_N_INSNS (1) + const_size;
+-        }
+-      return COSTS_N_INSNS (1);
+-
+-    case SET:
+-      /* A SET doesn't have a mode, so let's look at the SET_DEST to get
+-	 the mode.  */
+-      words = ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x))));
+-      return COSTS_N_INSNS (words)
+-	     + COSTS_N_INSNS (1) * (satisfies_constraint_J (SET_SRC (x))
+-				    || satisfies_constraint_K (SET_SRC (x))
+-				       /* thumb1_movdi_insn.  */
+-				    || ((words > 1) && MEM_P (SET_SRC (x))));
+-
+-    case CONST_INT:
+-      if (outer == SET)
+-        {
+-          if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
+-            return COSTS_N_INSNS (1);
+-	  /* See split "TARGET_THUMB1 && satisfies_constraint_J".  */
+-	  if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
+-            return COSTS_N_INSNS (2);
+-	  /* See split "TARGET_THUMB1 && satisfies_constraint_K".  */
+-          if (thumb_shiftable_const (INTVAL (x)))
+-            return COSTS_N_INSNS (2);
+-          return COSTS_N_INSNS (3);
+-        }
+-      else if ((outer == PLUS || outer == COMPARE)
+-               && INTVAL (x) < 256 && INTVAL (x) > -256)
+-        return 0;
+-      else if ((outer == IOR || outer == XOR || outer == AND)
+-               && INTVAL (x) < 256 && INTVAL (x) >= -256)
+-        return COSTS_N_INSNS (1);
+-      else if (outer == AND)
+-        {
+-          int i;
+-          /* This duplicates the tests in the andsi3 expander.  */
+-          for (i = 9; i <= 31; i++)
+-            if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
+-                || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
+-              return COSTS_N_INSNS (2);
+-        }
+-      else if (outer == ASHIFT || outer == ASHIFTRT
+-               || outer == LSHIFTRT)
+-        return 0;
+-      return COSTS_N_INSNS (2);
+-
+-    case CONST:
+-    case CONST_DOUBLE:
+-    case LABEL_REF:
+-    case SYMBOL_REF:
+-      return COSTS_N_INSNS (3);
+-
+-    case UDIV:
+-    case UMOD:
+-    case DIV:
+-    case MOD:
+-      return 100;
+-
+-    case TRUNCATE:
+-      return 99;
+-
+-    case AND:
+-    case XOR:
+-    case IOR:
+-      return COSTS_N_INSNS (1);
+-
+-    case MEM:
+-      return (COSTS_N_INSNS (1)
+-	      + COSTS_N_INSNS (1)
+-		* ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
+-              + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
+-                 ? COSTS_N_INSNS (1) : 0));
+-
+-    case IF_THEN_ELSE:
+-      /* XXX a guess.  */
+-      if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
+-        return 14;
+-      return 2;
+-
+-    case ZERO_EXTEND:
+-      /* XXX still guessing.  */
+-      switch (GET_MODE (XEXP (x, 0)))
+-        {
+-          case QImode:
+-            return (1 + (mode == DImode ? 4 : 0)
+-                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+-
+-          case HImode:
+-            return (4 + (mode == DImode ? 4 : 0)
+-                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+-
+-          case SImode:
+-            return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+-
+-          default:
+-            return 99;
+-        }
+-
+-    default:
+-      return 99;
+-    }
+-}
+-
+-/* RTX costs when optimizing for size.  */
+-static bool
+-arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		    int *total)
+-{
+-  machine_mode mode = GET_MODE (x);
+-  if (TARGET_THUMB1)
+-    {
+-      *total = thumb1_size_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions.  */
+-  switch (code)
+-    {
+-    case MEM:
+-      /* A memory access costs 1 insn if the mode is small, or the address is
+-	 a single register, otherwise it costs one insn per word.  */
+-      if (REG_P (XEXP (x, 0)))
+-	*total = COSTS_N_INSNS (1);
+-      else if (flag_pic
+-	       && GET_CODE (XEXP (x, 0)) == PLUS
+-	       && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))
+-	/* This will be split into two instructions.
+-	   See arm.md:calculate_pic_address.  */
+-	*total = COSTS_N_INSNS (2);
+-      else
+-	*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return true;
+-
+-    case DIV:
+-    case MOD:
+-    case UDIV:
+-    case UMOD:
+-      /* Needs a libcall, so it costs about this.  */
+-      *total = COSTS_N_INSNS (2);
+-      return false;
+-
+-    case ROTATE:
+-      if (mode == SImode && REG_P (XEXP (x, 1)))
+-	{
+-	  *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, false);
+-	  return true;
+-	}
+-      /* Fall through */
+-    case ROTATERT:
+-    case ASHIFT:
+-    case LSHIFTRT:
+-    case ASHIFTRT:
+-      if (mode == DImode && CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, false);
+-	  return true;
+-	}
+-      else if (mode == SImode)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, false);
+-	  /* Slightly disparage register shifts, but not by much.  */
+-	  if (!CONST_INT_P (XEXP (x, 1)))
+-	    *total += 1 + rtx_cost (XEXP (x, 1), mode, code, 1, false);
+-	  return true;
+-	}
+-
+-      /* Needs a libcall.  */
+-      *total = COSTS_N_INSNS (2);
+-      return false;
+-
+-    case MINUS:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      if (mode == SImode)
+-	{
+-	  enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
+-	  enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
+-
+-	  if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
+-	      || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
+-	      || subcode1 == ROTATE || subcode1 == ROTATERT
+-	      || subcode1 == ASHIFT || subcode1 == LSHIFTRT
+-	      || subcode1 == ASHIFTRT)
+-	    {
+-	      /* It's just the cost of the two operands.  */
+-	      *total = 0;
+-	      return false;
+-	    }
+-
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return false;
+-
+-    case PLUS:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      /* A shift as a part of ADD costs nothing.  */
+-      if (GET_CODE (XEXP (x, 0)) == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  *total = COSTS_N_INSNS (TARGET_THUMB2 ? 2 : 1);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, code, 0, false);
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, false);
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-    case AND: case XOR: case IOR:
+-      if (mode == SImode)
+-	{
+-	  enum rtx_code subcode = GET_CODE (XEXP (x, 0));
+-
+-	  if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
+-	      || subcode == LSHIFTRT || subcode == ASHIFTRT
+-	      || (code == AND && subcode == NOT))
+-	    {
+-	      /* It's just the cost of the two operands.  */
+-	      *total = 0;
+-	      return false;
+-	    }
+-	}
+-
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return false;
+-
+-    case MULT:
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return false;
+-
+-    case NEG:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      /* Fall through */
+-    case NOT:
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-
+-      return false;
+-
+-    case IF_THEN_ELSE:
+-      *total = 0;
+-      return false;
+-
+-    case COMPARE:
+-      if (cc_register (XEXP (x, 0), VOIDmode))
+-	* total = 0;
+-      else
+-	*total = COSTS_N_INSNS (1);
+-      return false;
++    case UDIV:
++    case UMOD:
++    case DIV:
++    case MOD:
++      return 100;
+ 
+-    case ABS:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
+-      return false;
++    case TRUNCATE:
++      return 99;
+ 
+-    case SIGN_EXTEND:
+-    case ZERO_EXTEND:
+-      return arm_rtx_costs_1 (x, outer_code, total, 0);
++    case AND:
++    case XOR:
++    case IOR:
++      return COSTS_N_INSNS (1);
+ 
+-    case CONST_INT:
+-      if (const_ok_for_arm (INTVAL (x)))
+-	/* A multiplication by a constant requires another instruction
+-	   to load the constant to a register.  */
+-	*total = COSTS_N_INSNS ((outer_code == SET || outer_code == MULT)
+-				? 1 : 0);
+-      else if (const_ok_for_arm (~INTVAL (x)))
+-	*total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
+-      else if (const_ok_for_arm (-INTVAL (x)))
+-	{
+-	  if (outer_code == COMPARE || outer_code == PLUS
+-	      || outer_code == MINUS)
+-	    *total = 0;
+-	  else
+-	    *total = COSTS_N_INSNS (1);
+-	}
+-      else
+-	*total = COSTS_N_INSNS (2);
+-      return true;
++    case MEM:
++      return (COSTS_N_INSNS (1)
++	      + COSTS_N_INSNS (1)
++		* ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
++              + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
++                 ? COSTS_N_INSNS (1) : 0));
+ 
+-    case CONST:
+-    case LABEL_REF:
+-    case SYMBOL_REF:
+-      *total = COSTS_N_INSNS (2);
+-      return true;
++    case IF_THEN_ELSE:
++      /* XXX a guess.  */
++      if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
++        return 14;
++      return 2;
+ 
+-    case CONST_DOUBLE:
+-      *total = COSTS_N_INSNS (4);
+-      return true;
++    case ZERO_EXTEND:
++      /* XXX still guessing.  */
++      switch (GET_MODE (XEXP (x, 0)))
++        {
++          case QImode:
++            return (1 + (mode == DImode ? 4 : 0)
++                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+ 
+-    case CONST_VECTOR:
+-      if (TARGET_NEON
+-	  && TARGET_HARD_FLOAT
+-	  && outer_code == SET
+-	  && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
+-	  && neon_immediate_valid_for_move (x, mode, NULL, NULL))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (4);
+-      return true;
++          case HImode:
++            return (4 + (mode == DImode ? 4 : 0)
++                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+ 
+-    case HIGH:
+-    case LO_SUM:
+-      /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
+-	 cost of these slightly.  */
+-      *total = COSTS_N_INSNS (1) + 1;
+-      return true;
++          case SImode:
++            return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+ 
+-    case SET:
+-      return false;
++          default:
++            return 99;
++        }
+ 
+     default:
+-      if (mode != VOIDmode)
+-	*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      else
+-	*total = COSTS_N_INSNS (4); /* How knows?  */
+-      return false;
++      return 99;
+     }
+ }
+ 
+@@ -9519,7 +8950,7 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost)
+    flags are live or not, and thus no realistic way to determine what
+    the size will eventually be.  */
+ static bool
+-arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
++arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
+ 		   const struct cpu_cost_table *extra_cost,
+ 		   int *cost, bool speed_p)
+ {
+@@ -10771,8 +10202,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+       if ((arm_arch4 || GET_MODE (XEXP (x, 0)) == SImode)
+ 	  && MEM_P (XEXP (x, 0)))
+ 	{
+-	  *cost = rtx_cost (XEXP (x, 0), VOIDmode, code, 0, speed_p);
+-
+ 	  if (mode == DImode)
+ 	    *cost += COSTS_N_INSNS (1);
+ 
+@@ -11164,390 +10593,70 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+ 	  /* Vector costs? */
+ 	}
+       *cost = LIBCALL_COST (1);
+-      return false;
+-
+-    case FLOAT:
+-    case UNSIGNED_FLOAT:
+-      if (TARGET_HARD_FLOAT)
+-	{
+-	  /* ??? Increase the cost to deal with transferring from CORE
+-	     -> FP registers?  */
+-	  if (speed_p)
+-	    *cost += extra_cost->fp[mode == DFmode].fromint;
+-	  return false;
+-	}
+-      *cost = LIBCALL_COST (1);
+-      return false;
+-
+-    case CALL:
+-      return true;
+-
+-    case ASM_OPERANDS:
+-      {
+-      /* Just a guess.  Guess number of instructions in the asm
+-         plus one insn per input.  Always a minimum of COSTS_N_INSNS (1)
+-         though (see PR60663).  */
+-        int asm_length = MAX (1, asm_str_count (ASM_OPERANDS_TEMPLATE (x)));
+-        int num_operands = ASM_OPERANDS_INPUT_LENGTH (x);
+-
+-        *cost = COSTS_N_INSNS (asm_length + num_operands);
+-        return true;
+-      }
+-    default:
+-      if (mode != VOIDmode)
+-	*cost = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      else
+-	*cost = COSTS_N_INSNS (4); /* Who knows?  */
+-      return false;
+-    }
+-}
+-
+-#undef HANDLE_NARROW_SHIFT_ARITH
+-
+-/* RTX costs when optimizing for size.  */
+-static bool
+-arm_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
+-	       int opno ATTRIBUTE_UNUSED, int *total, bool speed)
+-{
+-  bool result;
+-  int code = GET_CODE (x);
+-
+-  if (TARGET_OLD_RTX_COSTS
+-      || (!current_tune->insn_extra_cost && !TARGET_NEW_GENERIC_COSTS))
+-    {
+-      /* Old way.  (Deprecated.)  */
+-      if (!speed)
+-	result = arm_size_rtx_costs (x, (enum rtx_code) code,
+-				     (enum rtx_code) outer_code, total);
+-      else
+-	result = current_tune->rtx_costs (x,  (enum rtx_code) code,
+-					  (enum rtx_code) outer_code, total,
+-					  speed);
+-    }
+-  else
+-    {
+-    /* New way.  */
+-      if (current_tune->insn_extra_cost)
+-        result =  arm_new_rtx_costs (x, (enum rtx_code) code,
+-				     (enum rtx_code) outer_code,
+-				     current_tune->insn_extra_cost,
+-				     total, speed);
+-    /* TARGET_NEW_GENERIC_COSTS && !TARGET_OLD_RTX_COSTS
+-       && current_tune->insn_extra_cost != NULL  */
+-      else
+-        result =  arm_new_rtx_costs (x, (enum rtx_code) code,
+-				    (enum rtx_code) outer_code,
+-				    &generic_extra_costs, total, speed);
+-    }
+-
+-  if (dump_file && (dump_flags & TDF_DETAILS))
+-    {
+-      print_rtl_single (dump_file, x);
+-      fprintf (dump_file, "\n%s cost: %d (%s)\n", speed ? "Hot" : "Cold",
+-	       *total, result ? "final" : "partial");
+-    }
+-  return result;
+-}
+-
+-/* RTX costs for cores with a slow MUL implementation.  Thumb-2 is not
+-   supported on any "slowmul" cores, so it can be ignored.  */
+-
+-static bool
+-arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		       int *total, bool speed)
+-{
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB)
+-    {
+-      *total = thumb1_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  switch (code)
+-    {
+-    case MULT:
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  || mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-
+-      if (CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
+-				      & (unsigned HOST_WIDE_INT) 0xffffffff);
+-	  int cost, const_ok = const_ok_for_arm (i);
+-	  int j, booth_unit_size;
+-
+-	  /* Tune as appropriate.  */
+-	  cost = const_ok ? 4 : 8;
+-	  booth_unit_size = 2;
+-	  for (j = 0; i && j < 32; j += booth_unit_size)
+-	    {
+-	      i >>= booth_unit_size;
+-	      cost++;
+-	    }
+-
+-	  *total = COSTS_N_INSNS (cost);
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  return true;
+-	}
+-
+-      *total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);;
+-    }
+-}
+-
+-
+-/* RTX cost for cores with a fast multiply unit (M variants).  */
+-
+-static bool
+-arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		       int *total, bool speed)
+-{
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB1)
+-    {
+-      *total = thumb1_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  /* ??? should thumb2 use different costs?  */
+-  switch (code)
+-    {
+-    case MULT:
+-      /* There is no point basing this on the tuning, since it is always the
+-	 fast variant if it exists at all.  */
+-      if (mode == DImode
+-	  && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS(2);
+-	  return false;
+-	}
+-
+-
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (5);
+-	  return false;
+-	}
+-
+-      if (CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
+-				      & (unsigned HOST_WIDE_INT) 0xffffffff);
+-	  int cost, const_ok = const_ok_for_arm (i);
+-	  int j, booth_unit_size;
+-
+-	  /* Tune as appropriate.  */
+-	  cost = const_ok ? 4 : 8;
+-	  booth_unit_size = 8;
+-	  for (j = 0; i && j < 32; j += booth_unit_size)
+-	    {
+-	      i >>= booth_unit_size;
+-	      cost++;
+-	    }
+-
+-	  *total = COSTS_N_INSNS(cost);
+-	  return false;
+-	}
+-
+-      if (mode == SImode)
+-	{
+-	  *total = COSTS_N_INSNS (4);
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	}
+-
+-      /* Requires a lib call */
+-      *total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);
+-    }
+-}
+-
+-
+-/* RTX cost for XScale CPUs.  Thumb-2 is not supported on any xscale cores,
+-   so it can be ignored.  */
+-
+-static bool
+-arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		      int *total, bool speed)
+-{
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB)
+-    {
+-      *total = thumb1_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  switch (code)
+-    {
+-    case COMPARE:
+-      if (GET_CODE (XEXP (x, 0)) != MULT)
+-	return arm_rtx_costs_1 (x, outer_code, total, speed);
+-
+-      /* A COMPARE of a MULT is slow on XScale; the muls instruction
+-	 will stall until the multiplication is complete.  */
+-      *total = COSTS_N_INSNS (3);
+-      return false;
+-
+-    case MULT:
+-      /* There is no point basing this on the tuning, since it is always the
+-	 fast variant if it exists at all.  */
+-      if (mode == DImode
+-	  && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (5);
+-	  return false;
+-	}
+-
+-      if (CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  /* If operand 1 is a constant we can more accurately
+-	     calculate the cost of the multiply.  The multiplier can
+-	     retire 15 bits on the first cycle and a further 12 on the
+-	     second.  We do, of course, have to load the constant into
+-	     a register first.  */
+-	  unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
+-	  /* There's a general overhead of one cycle.  */
+-	  int cost = 1;
+-	  unsigned HOST_WIDE_INT masked_const;
+-
+-	  if (i & 0x80000000)
+-	    i = ~i;
+-
+-	  i &= (unsigned HOST_WIDE_INT) 0xffffffff;
+-
+-	  masked_const = i & 0xffff8000;
+-	  if (masked_const != 0)
+-	    {
+-	      cost++;
+-	      masked_const = i & 0xf8000000;
+-	      if (masked_const != 0)
+-		cost++;
+-	    }
+-	  *total = COSTS_N_INSNS (cost);
+-	  return false;
+-	}
++      return false;
+ 
+-      if (mode == SImode)
++    case FLOAT:
++    case UNSIGNED_FLOAT:
++      if (TARGET_HARD_FLOAT)
+ 	{
+-	  *total = COSTS_N_INSNS (3);
++	  /* ??? Increase the cost to deal with transferring from CORE
++	     -> FP registers?  */
++	  if (speed_p)
++	    *cost += extra_cost->fp[mode == DFmode].fromint;
+ 	  return false;
+ 	}
+-
+-      /* Requires a lib call */
+-      *total = COSTS_N_INSNS (20);
++      *cost = LIBCALL_COST (1);
+       return false;
+ 
++    case CALL:
++      return true;
++
++    case ASM_OPERANDS:
++      {
++      /* Just a guess.  Guess number of instructions in the asm
++         plus one insn per input.  Always a minimum of COSTS_N_INSNS (1)
++         though (see PR60663).  */
++        int asm_length = MAX (1, asm_str_count (ASM_OPERANDS_TEMPLATE (x)));
++        int num_operands = ASM_OPERANDS_INPUT_LENGTH (x);
++
++        *cost = COSTS_N_INSNS (asm_length + num_operands);
++        return true;
++      }
+     default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);
++      if (mode != VOIDmode)
++	*cost = COSTS_N_INSNS (ARM_NUM_REGS (mode));
++      else
++	*cost = COSTS_N_INSNS (4); /* Who knows?  */
++      return false;
+     }
+ }
+ 
++#undef HANDLE_NARROW_SHIFT_ARITH
+ 
+-/* RTX costs for 9e (and later) cores.  */
++/* RTX costs entry point.  */
+ 
+ static bool
+-arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		  int *total, bool speed)
++arm_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
++	       int opno ATTRIBUTE_UNUSED, int *total, bool speed)
+ {
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB1)
+-    {
+-      switch (code)
+-	{
+-	case MULT:
+-	  /* Small multiply: 32 cycles for an integer multiply inst.  */
+-	  if (arm_arch6m && arm_m_profile_small_mul)
+-	    *total = COSTS_N_INSNS (32);
+-	  else
+-	    *total = COSTS_N_INSNS (3);
+-	  return true;
++  bool result;
++  int code = GET_CODE (x);
++  gcc_assert (current_tune->insn_extra_cost);
+ 
+-	default:
+-	  *total = thumb1_rtx_costs (x, code, outer_code);
+-	  return true;
+-	}
+-    }
++  result =  arm_rtx_costs_internal (x, (enum rtx_code) code,
++				(enum rtx_code) outer_code,
++				current_tune->insn_extra_cost,
++				total, speed);
+ 
+-  switch (code)
++  if (dump_file && (dump_flags & TDF_DETAILS))
+     {
+-    case MULT:
+-      /* There is no point basing this on the tuning, since it is always the
+-	 fast variant if it exists at all.  */
+-      if (mode == DImode
+-	  && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (5);
+-	  return false;
+-	}
+-
+-      if (mode == SImode)
+-	{
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	}
+-
+-      *total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);
++      print_rtl_single (dump_file, x);
++      fprintf (dump_file, "\n%s cost: %d (%s)\n", speed ? "Hot" : "Cold",
++	       *total, result ? "final" : "partial");
+     }
++  return result;
+ }
++
+ /* All address computations that can be done are free, but rtx cost returns
+    the same for practically all of them.  So we weight the different types
+    of address here in the order (most pref first):
+@@ -12269,7 +11378,7 @@ vfp3_const_double_index (rtx x)
+ 
+   /* We can permit four significant bits of mantissa only, plus a high bit
+      which is always 1.  */
+-  mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
++  mask = (HOST_WIDE_INT_1U << (point_pos - 5)) - 1;
+   if ((mantissa & mask) != 0)
+     return -1;
+ 
+@@ -12423,6 +11532,12 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse,
+ 	return 18;
+     }
+ 
++  /* The tricks done in the code below apply for little-endian vector layout.
++     For big-endian vectors only allow vectors of the form { a, a, a..., a }.
++     FIXME: Implement logic for big-endian vectors.  */
++  if (BYTES_BIG_ENDIAN && vector && !const_vec_duplicate_p (op))
++    return -1;
++
+   /* Splat vector constant out into a byte vector.  */
+   for (i = 0; i < n_elts; i++)
+     {
+@@ -13151,7 +12266,7 @@ coproc_secondary_reload_class (machine_mode mode, rtx x, bool wb)
+ {
+   if (mode == HFmode)
+     {
+-      if (!TARGET_NEON_FP16)
++      if (!TARGET_NEON_FP16 && !TARGET_VFP_FP16INST)
+ 	return GENERAL_REGS;
+       if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2, true))
+ 	return NO_REGS;
+@@ -15988,14 +15103,17 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
+   /* If the same input register is used in both stores
+      when storing different constants, try to find a free register.
+      For example, the code
+-        mov r0, 0
+-        str r0, [r2]
+-        mov r0, 1
+-        str r0, [r2, #4]
++	mov r0, 0
++	str r0, [r2]
++	mov r0, 1
++	str r0, [r2, #4]
+      can be transformed into
+-        mov r1, 0
+-        strd r1, r0, [r2]
+-     in Thumb mode assuming that r1 is free.  */
++	mov r1, 0
++	mov r0, 1
++	strd r1, r0, [r2]
++     in Thumb mode assuming that r1 is free.
++     For ARM mode do the same but only if the starting register
++     can be made to be even.  */
+   if (const_store
+       && REGNO (operands[0]) == REGNO (operands[1])
+       && INTVAL (operands[4]) != INTVAL (operands[5]))
+@@ -16014,7 +15132,6 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
+       }
+     else if (TARGET_ARM)
+       {
+-        return false;
+         int regno = REGNO (operands[0]);
+         if (!peep2_reg_dead_p (4, operands[0]))
+           {
+@@ -16368,7 +15485,7 @@ get_jump_table_size (rtx_jump_table_data *insn)
+ 	{
+ 	case 1:
+ 	  /* Round up size  of TBB table to a halfword boundary.  */
+-	  size = (size + 1) & ~(HOST_WIDE_INT)1;
++	  size = (size + 1) & ~HOST_WIDE_INT_1;
+ 	  break;
+ 	case 2:
+ 	  /* No padding necessary for TBH.  */
+@@ -16837,35 +15954,37 @@ dump_minipool (rtx_insn *scan)
+ 	      fputc ('\n', dump_file);
+ 	    }
+ 
++	  rtx val = copy_rtx (mp->value);
++
+ 	  switch (GET_MODE_SIZE (mp->mode))
+ 	    {
+ #ifdef HAVE_consttable_1
+ 	    case 1:
+-	      scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_1 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_2
+ 	    case 2:
+-	      scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_2 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_4
+ 	    case 4:
+-	      scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_4 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_8
+ 	    case 8:
+-	      scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_8 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_16
+ 	    case 16:
+-              scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
++              scan = emit_insn_after (gen_consttable_16 (val), scan);
+               break;
+ 
+ #endif
+@@ -17269,6 +16388,470 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT address, int do_pushes)
+   return;
+ }
+ 
++/* This function computes the clear mask and PADDING_BITS_TO_CLEAR for structs
++   and unions in the context of ARMv8-M Security Extensions.  It is used as a
++   helper function for both 'cmse_nonsecure_call' and 'cmse_nonsecure_entry'
++   functions.  The PADDING_BITS_TO_CLEAR pointer can be the base to either one
++   or four masks, depending on whether it is being computed for a
++   'cmse_nonsecure_entry' return value or a 'cmse_nonsecure_call' argument
++   respectively.  The tree for the type of the argument or a field within an
++   argument is passed in ARG_TYPE, the current register this argument or field
++   starts in is kept in the pointer REGNO and updated accordingly, the bit this
++   argument or field starts at is passed in STARTING_BIT and the last used bit
++   is kept in LAST_USED_BIT which is also updated accordingly.  */
++
++static unsigned HOST_WIDE_INT
++comp_not_to_clear_mask_str_un (tree arg_type, int * regno,
++			       uint32_t * padding_bits_to_clear,
++			       unsigned starting_bit, int * last_used_bit)
++
++{
++  unsigned HOST_WIDE_INT not_to_clear_reg_mask = 0;
++
++  if (TREE_CODE (arg_type) == RECORD_TYPE)
++    {
++      unsigned current_bit = starting_bit;
++      tree field;
++      long int offset, size;
++
++
++      field = TYPE_FIELDS (arg_type);
++      while (field)
++	{
++	  /* The offset within a structure is always an offset from
++	     the start of that structure.  Make sure we take that into the
++	     calculation of the register based offset that we use here.  */
++	  offset = starting_bit;
++	  offset += TREE_INT_CST_ELT (DECL_FIELD_BIT_OFFSET (field), 0);
++	  offset %= 32;
++
++	  /* This is the actual size of the field, for bitfields this is the
++	     bitfield width and not the container size.  */
++	  size = TREE_INT_CST_ELT (DECL_SIZE (field), 0);
++
++	  if (*last_used_bit != offset)
++	    {
++	      if (offset < *last_used_bit)
++		{
++		  /* This field's offset is before the 'last_used_bit', that
++		     means this field goes on the next register.  So we need to
++		     pad the rest of the current register and increase the
++		     register number.  */
++		  uint32_t mask;
++		  mask  = ((uint32_t)-1) - ((uint32_t) 1 << *last_used_bit);
++		  mask++;
++
++		  padding_bits_to_clear[*regno] |= mask;
++		  not_to_clear_reg_mask |= HOST_WIDE_INT_1U << *regno;
++		  (*regno)++;
++		}
++	      else
++		{
++		  /* Otherwise we pad the bits between the last field's end and
++		     the start of the new field.  */
++		  uint32_t mask;
++
++		  mask = ((uint32_t)-1) >> (32 - offset);
++		  mask -= ((uint32_t) 1 << *last_used_bit) - 1;
++		  padding_bits_to_clear[*regno] |= mask;
++		}
++	      current_bit = offset;
++	    }
++
++	  /* Calculate further padding bits for inner structs/unions too.  */
++	  if (RECORD_OR_UNION_TYPE_P (TREE_TYPE (field)))
++	    {
++	      *last_used_bit = current_bit;
++	      not_to_clear_reg_mask
++		|= comp_not_to_clear_mask_str_un (TREE_TYPE (field), regno,
++						  padding_bits_to_clear, offset,
++						  last_used_bit);
++	    }
++	  else
++	    {
++	      /* Update 'current_bit' with this field's size.  If the
++		 'current_bit' lies in a subsequent register, update 'regno' and
++		 reset 'current_bit' to point to the current bit in that new
++		 register.  */
++	      current_bit += size;
++	      while (current_bit >= 32)
++		{
++		  current_bit-=32;
++		  not_to_clear_reg_mask |= HOST_WIDE_INT_1U << *regno;
++		  (*regno)++;
++		}
++	      *last_used_bit = current_bit;
++	    }
++
++	  field = TREE_CHAIN (field);
++	}
++      not_to_clear_reg_mask |= HOST_WIDE_INT_1U << *regno;
++    }
++  else if (TREE_CODE (arg_type) == UNION_TYPE)
++    {
++      tree field, field_t;
++      int i, regno_t, field_size;
++      int max_reg = -1;
++      int max_bit = -1;
++      uint32_t mask;
++      uint32_t padding_bits_to_clear_res[NUM_ARG_REGS]
++	= {-1, -1, -1, -1};
++
++      /* To compute the padding bits in a union we only consider bits as
++	 padding bits if they are always either a padding bit or fall outside a
++	 fields size for all fields in the union.  */
++      field = TYPE_FIELDS (arg_type);
++      while (field)
++	{
++	  uint32_t padding_bits_to_clear_t[NUM_ARG_REGS]
++	    = {0U, 0U, 0U, 0U};
++	  int last_used_bit_t = *last_used_bit;
++	  regno_t = *regno;
++	  field_t = TREE_TYPE (field);
++
++	  /* If the field's type is either a record or a union make sure to
++	     compute their padding bits too.  */
++	  if (RECORD_OR_UNION_TYPE_P (field_t))
++	    not_to_clear_reg_mask
++	      |= comp_not_to_clear_mask_str_un (field_t, &regno_t,
++						&padding_bits_to_clear_t[0],
++						starting_bit, &last_used_bit_t);
++	  else
++	    {
++	      field_size = TREE_INT_CST_ELT (DECL_SIZE (field), 0);
++	      regno_t = (field_size / 32) + *regno;
++	      last_used_bit_t = (starting_bit + field_size) % 32;
++	    }
++
++	  for (i = *regno; i < regno_t; i++)
++	    {
++	      /* For all but the last register used by this field only keep the
++		 padding bits that were padding bits in this field.  */
++	      padding_bits_to_clear_res[i] &= padding_bits_to_clear_t[i];
++	    }
++
++	    /* For the last register, keep all padding bits that were padding
++	       bits in this field and any padding bits that are still valid
++	       as padding bits but fall outside of this field's size.  */
++	    mask = (((uint32_t) -1) - ((uint32_t) 1 << last_used_bit_t)) + 1;
++	    padding_bits_to_clear_res[regno_t]
++	      &= padding_bits_to_clear_t[regno_t] | mask;
++
++	  /* Update the maximum size of the fields in terms of registers used
++	     ('max_reg') and the 'last_used_bit' in said register.  */
++	  if (max_reg < regno_t)
++	    {
++	      max_reg = regno_t;
++	      max_bit = last_used_bit_t;
++	    }
++	  else if (max_reg == regno_t && max_bit < last_used_bit_t)
++	    max_bit = last_used_bit_t;
++
++	  field = TREE_CHAIN (field);
++	}
++
++      /* Update the current padding_bits_to_clear using the intersection of the
++	 padding bits of all the fields.  */
++      for (i=*regno; i < max_reg; i++)
++	padding_bits_to_clear[i] |= padding_bits_to_clear_res[i];
++
++      /* Do not keep trailing padding bits, we do not know yet whether this
++	 is the end of the argument.  */
++      mask = ((uint32_t) 1 << max_bit) - 1;
++      padding_bits_to_clear[max_reg]
++	|= padding_bits_to_clear_res[max_reg] & mask;
++
++      *regno = max_reg;
++      *last_used_bit = max_bit;
++    }
++  else
++    /* This function should only be used for structs and unions.  */
++    gcc_unreachable ();
++
++  return not_to_clear_reg_mask;
++}
++
++/* In the context of ARMv8-M Security Extensions, this function is used for both
++   'cmse_nonsecure_call' and 'cmse_nonsecure_entry' functions to compute what
++   registers are used when returning or passing arguments, which is then
++   returned as a mask.  It will also compute a mask to indicate padding/unused
++   bits for each of these registers, and passes this through the
++   PADDING_BITS_TO_CLEAR pointer.  The tree of the argument type is passed in
++   ARG_TYPE, the rtl representation of the argument is passed in ARG_RTX and
++   the starting register used to pass this argument or return value is passed
++   in REGNO.  It makes use of 'comp_not_to_clear_mask_str_un' to compute these
++   for struct and union types.  */
++
++static unsigned HOST_WIDE_INT
++compute_not_to_clear_mask (tree arg_type, rtx arg_rtx, int regno,
++			     uint32_t * padding_bits_to_clear)
++
++{
++  int last_used_bit = 0;
++  unsigned HOST_WIDE_INT not_to_clear_mask;
++
++  if (RECORD_OR_UNION_TYPE_P (arg_type))
++    {
++      not_to_clear_mask
++	= comp_not_to_clear_mask_str_un (arg_type, &regno,
++					 padding_bits_to_clear, 0,
++					 &last_used_bit);
++
++
++      /* If the 'last_used_bit' is not zero, that means we are still using a
++	 part of the last 'regno'.  In such cases we must clear the trailing
++	 bits.  Otherwise we are not using regno and we should mark it as to
++	 clear.  */
++      if (last_used_bit != 0)
++	padding_bits_to_clear[regno]
++	  |= ((uint32_t)-1) - ((uint32_t) 1 << last_used_bit) + 1;
++      else
++	not_to_clear_mask &= ~(HOST_WIDE_INT_1U << regno);
++    }
++  else
++    {
++      not_to_clear_mask = 0;
++      /* We are not dealing with structs nor unions.  So these arguments may be
++	 passed in floating point registers too.  In some cases a BLKmode is
++	 used when returning or passing arguments in multiple VFP registers.  */
++      if (GET_MODE (arg_rtx) == BLKmode)
++	{
++	  int i, arg_regs;
++	  rtx reg;
++
++	  /* This should really only occur when dealing with the hard-float
++	     ABI.  */
++	  gcc_assert (TARGET_HARD_FLOAT_ABI);
++
++	  for (i = 0; i < XVECLEN (arg_rtx, 0); i++)
++	    {
++	      reg = XEXP (XVECEXP (arg_rtx, 0, i), 0);
++	      gcc_assert (REG_P (reg));
++
++	      not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO (reg);
++
++	      /* If we are dealing with DF mode, make sure we don't
++		 clear either of the registers it addresses.  */
++	      arg_regs = ARM_NUM_REGS (GET_MODE (reg));
++	      if (arg_regs > 1)
++		{
++		  unsigned HOST_WIDE_INT mask;
++		  mask = HOST_WIDE_INT_1U << (REGNO (reg) + arg_regs);
++		  mask -= HOST_WIDE_INT_1U << REGNO (reg);
++		  not_to_clear_mask |= mask;
++		}
++	    }
++	}
++      else
++	{
++	  /* Otherwise we can rely on the MODE to determine how many registers
++	     are being used by this argument.  */
++	  int arg_regs = ARM_NUM_REGS (GET_MODE (arg_rtx));
++	  not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO (arg_rtx);
++	  if (arg_regs > 1)
++	    {
++	      unsigned HOST_WIDE_INT
++	      mask = HOST_WIDE_INT_1U << (REGNO (arg_rtx) + arg_regs);
++	      mask -= HOST_WIDE_INT_1U << REGNO (arg_rtx);
++	      not_to_clear_mask |= mask;
++	    }
++	}
++    }
++
++  return not_to_clear_mask;
++}
++
++/* Saves callee saved registers, clears callee saved registers and caller saved
++   registers not used to pass arguments before a cmse_nonsecure_call.  And
++   restores the callee saved registers after.  */
++
++static void
++cmse_nonsecure_call_clear_caller_saved (void)
++{
++  basic_block bb;
++
++  FOR_EACH_BB_FN (bb, cfun)
++    {
++      rtx_insn *insn;
++
++      FOR_BB_INSNS (bb, insn)
++	{
++	  uint64_t to_clear_mask, float_mask;
++	  rtx_insn *seq;
++	  rtx pat, call, unspec, reg, cleared_reg, tmp;
++	  unsigned int regno, maxregno;
++	  rtx address;
++	  CUMULATIVE_ARGS args_so_far_v;
++	  cumulative_args_t args_so_far;
++	  tree arg_type, fntype;
++	  bool using_r4, first_param = true;
++	  function_args_iterator args_iter;
++	  uint32_t padding_bits_to_clear[4] = {0U, 0U, 0U, 0U};
++	  uint32_t * padding_bits_to_clear_ptr = &padding_bits_to_clear[0];
++
++	  if (!NONDEBUG_INSN_P (insn))
++	    continue;
++
++	  if (!CALL_P (insn))
++	    continue;
++
++	  pat = PATTERN (insn);
++	  gcc_assert (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 0);
++	  call = XVECEXP (pat, 0, 0);
++
++	  /* Get the real call RTX if the insn sets a value, ie. returns.  */
++	  if (GET_CODE (call) == SET)
++	      call = SET_SRC (call);
++
++	  /* Check if it is a cmse_nonsecure_call.  */
++	  unspec = XEXP (call, 0);
++	  if (GET_CODE (unspec) != UNSPEC
++	      || XINT (unspec, 1) != UNSPEC_NONSECURE_MEM)
++	    continue;
++
++	  /* Determine the caller-saved registers we need to clear.  */
++	  to_clear_mask = (1LL << (NUM_ARG_REGS)) - 1;
++	  maxregno = NUM_ARG_REGS - 1;
++	  /* Only look at the caller-saved floating point registers in case of
++	     -mfloat-abi=hard.  For -mfloat-abi=softfp we will be using the
++	     lazy store and loads which clear both caller- and callee-saved
++	     registers.  */
++	  if (TARGET_HARD_FLOAT_ABI)
++	    {
++	      float_mask = (1LL << (D7_VFP_REGNUM + 1)) - 1;
++	      float_mask &= ~((1LL << FIRST_VFP_REGNUM) - 1);
++	      to_clear_mask |= float_mask;
++	      maxregno = D7_VFP_REGNUM;
++	    }
++
++	  /* Make sure the register used to hold the function address is not
++	     cleared.  */
++	  address = RTVEC_ELT (XVEC (unspec, 0), 0);
++	  gcc_assert (MEM_P (address));
++	  gcc_assert (REG_P (XEXP (address, 0)));
++	  to_clear_mask &= ~(1LL << REGNO (XEXP (address, 0)));
++
++	  /* Set basic block of call insn so that df rescan is performed on
++	     insns inserted here.  */
++	  set_block_for_insn (insn, bb);
++	  df_set_flags (DF_DEFER_INSN_RESCAN);
++	  start_sequence ();
++
++	  /* Make sure the scheduler doesn't schedule other insns beyond
++	     here.  */
++	  emit_insn (gen_blockage ());
++
++	  /* Walk through all arguments and clear registers appropriately.
++	  */
++	  fntype = TREE_TYPE (MEM_EXPR (address));
++	  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX,
++				    NULL_TREE);
++	  args_so_far = pack_cumulative_args (&args_so_far_v);
++	  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
++	    {
++	      rtx arg_rtx;
++	      machine_mode arg_mode = TYPE_MODE (arg_type);
++
++	      if (VOID_TYPE_P (arg_type))
++		continue;
++
++	      if (!first_param)
++		arm_function_arg_advance (args_so_far, arg_mode, arg_type,
++					  true);
++
++	      arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type,
++					  true);
++	      gcc_assert (REG_P (arg_rtx));
++	      to_clear_mask
++		&= ~compute_not_to_clear_mask (arg_type, arg_rtx,
++					       REGNO (arg_rtx),
++					       padding_bits_to_clear_ptr);
++
++	      first_param = false;
++	    }
++
++	  /* Clear padding bits where needed.  */
++	  cleared_reg = XEXP (address, 0);
++	  reg = gen_rtx_REG (SImode, IP_REGNUM);
++	  using_r4 = false;
++	  for (regno = R0_REGNUM; regno < NUM_ARG_REGS; regno++)
++	    {
++	      if (padding_bits_to_clear[regno] == 0)
++		continue;
++
++	      /* If this is a Thumb-1 target copy the address of the function
++		 we are calling from 'r4' into 'ip' such that we can use r4 to
++		 clear the unused bits in the arguments.  */
++	      if (TARGET_THUMB1 && !using_r4)
++		{
++		  using_r4 =  true;
++		  reg = cleared_reg;
++		  emit_move_insn (gen_rtx_REG (SImode, IP_REGNUM),
++					  reg);
++		}
++
++	      tmp = GEN_INT ((((~padding_bits_to_clear[regno]) << 16u) >> 16u));
++	      emit_move_insn (reg, tmp);
++	      /* Also fill the top half of the negated
++		 padding_bits_to_clear.  */
++	      if (((~padding_bits_to_clear[regno]) >> 16) > 0)
++		{
++		  tmp = GEN_INT ((~padding_bits_to_clear[regno]) >> 16);
++		  emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode, reg,
++								GEN_INT (16),
++								GEN_INT (16)),
++					  tmp));
++		}
++
++	      emit_insn (gen_andsi3 (gen_rtx_REG (SImode, regno),
++				     gen_rtx_REG (SImode, regno),
++				     reg));
++
++	    }
++	  if (using_r4)
++	    emit_move_insn (cleared_reg,
++			    gen_rtx_REG (SImode, IP_REGNUM));
++
++	  /* We use right shift and left shift to clear the LSB of the address
++	     we jump to instead of using bic, to avoid having to use an extra
++	     register on Thumb-1.  */
++	  tmp = gen_rtx_LSHIFTRT (SImode, cleared_reg, const1_rtx);
++	  emit_insn (gen_rtx_SET (cleared_reg, tmp));
++	  tmp = gen_rtx_ASHIFT (SImode, cleared_reg, const1_rtx);
++	  emit_insn (gen_rtx_SET (cleared_reg, tmp));
++
++	  /* Clearing all registers that leak before doing a non-secure
++	     call.  */
++	  for (regno = R0_REGNUM; regno <= maxregno; regno++)
++	    {
++	      if (!(to_clear_mask & (1LL << regno)))
++		continue;
++
++	      /* If regno is an even vfp register and its successor is also to
++		 be cleared, use vmov.  */
++	      if (IS_VFP_REGNUM (regno))
++		{
++		  if (TARGET_VFP_DOUBLE
++		      && VFP_REGNO_OK_FOR_DOUBLE (regno)
++		      && to_clear_mask & (1LL << (regno + 1)))
++		    emit_move_insn (gen_rtx_REG (DFmode, regno++),
++				    CONST0_RTX (DFmode));
++		  else
++		    emit_move_insn (gen_rtx_REG (SFmode, regno),
++				    CONST0_RTX (SFmode));
++		}
++	      else
++		emit_move_insn (gen_rtx_REG (SImode, regno), cleared_reg);
++	    }
++
++	  seq = get_insns ();
++	  end_sequence ();
++	  emit_insn_before (seq, insn);
++
++	}
++    }
++}
++
+ /* Rewrite move insn into subtract of 0 if the condition codes will
+    be useful in next conditional jump insn.  */
+ 
+@@ -17569,6 +17152,8 @@ arm_reorg (void)
+   HOST_WIDE_INT address = 0;
+   Mfix * fix;
+ 
++  if (use_cmse)
++    cmse_nonsecure_call_clear_caller_saved ();
+   if (TARGET_THUMB1)
+     thumb1_reorg ();
+   else if (TARGET_THUMB2)
+@@ -17941,6 +17526,23 @@ vfp_emit_fstmd (int base_reg, int count)
+   return count * 8;
+ }
+ 
++/* Returns true if -mcmse has been passed and the function pointed to by 'addr'
++   has the cmse_nonsecure_call attribute and returns false otherwise.  */
++
++bool
++detect_cmse_nonsecure_call (tree addr)
++{
++  if (!addr)
++    return FALSE;
++
++  tree fntype = TREE_TYPE (addr);
++  if (use_cmse && lookup_attribute ("cmse_nonsecure_call",
++				    TYPE_ATTRIBUTES (fntype)))
++    return TRUE;
++  return FALSE;
++}
++
++
+ /* Emit a call instruction with pattern PAT.  ADDR is the address of
+    the call target.  */
+ 
+@@ -18600,6 +18202,8 @@ output_move_vfp (rtx *operands)
+   rtx reg, mem, addr, ops[2];
+   int load = REG_P (operands[0]);
+   int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
++  int sp = (!TARGET_VFP_FP16INST
++	    || GET_MODE_SIZE (GET_MODE (operands[0])) == 4);
+   int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
+   const char *templ;
+   char buff[50];
+@@ -18612,8 +18216,10 @@ output_move_vfp (rtx *operands)
+ 
+   gcc_assert (REG_P (reg));
+   gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
+-  gcc_assert (mode == SFmode
++  gcc_assert ((mode == HFmode && TARGET_HARD_FLOAT)
++	      || mode == SFmode
+ 	      || mode == DFmode
++	      || mode == HImode
+ 	      || mode == SImode
+ 	      || mode == DImode
+               || (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
+@@ -18644,7 +18250,7 @@ output_move_vfp (rtx *operands)
+ 
+   sprintf (buff, templ,
+ 	   load ? "ld" : "st",
+-	   dp ? "64" : "32",
++	   dp ? "64" : sp ? "32" : "16",
+ 	   dp ? "P" : "",
+ 	   integer_p ? "\t%@ int" : "");
+   output_asm_insn (buff, ops);
+@@ -19070,7 +18676,8 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
+ 	  return NULL;
+ 	}
+ 
+-      *amountp = int_log2 (*amountp);
++      *amountp = exact_log2 (*amountp);
++      gcc_assert (IN_RANGE (*amountp, 0, 31));
+       return ARM_LSL_NAME;
+ 
+     default:
+@@ -19102,22 +18709,6 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
+   return mnem;
+ }
+ 
+-/* Obtain the shift from the POWER of two.  */
+-
+-static HOST_WIDE_INT
+-int_log2 (HOST_WIDE_INT power)
+-{
+-  HOST_WIDE_INT shift = 0;
+-
+-  while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
+-    {
+-      gcc_assert (shift <= 31);
+-      shift++;
+-    }
+-
+-  return shift;
+-}
+-
+ /* Output a .ascii pseudo-op, keeping track of lengths.  This is
+    because /bin/as is horribly restrictive.  The judgement about
+    whether or not each character is 'printable' (and can be output as
+@@ -19474,7 +19065,7 @@ arm_get_vfp_saved_size (void)
+ 
+   saved = 0;
+   /* Space for saved VFP registers.  */
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       count = 0;
+       for (regno = FIRST_VFP_REGNUM;
+@@ -19563,6 +19154,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
+ 	 (e.g. interworking) then we can load the return address
+ 	 directly into the PC.  Otherwise we must load it into LR.  */
+       if (really_return
++	  && !IS_CMSE_ENTRY (func_type)
+ 	  && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
+ 	return_reg = reg_names[PC_REGNUM];
+       else
+@@ -19703,18 +19295,93 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
+ 	  break;
+ 
+ 	default:
++	  if (IS_CMSE_ENTRY (func_type))
++	    {
++	      /* Check if we have to clear the 'GE bits' which is only used if
++		 parallel add and subtraction instructions are available.  */
++	      if (TARGET_INT_SIMD)
++		snprintf (instr, sizeof (instr),
++			  "msr%s\tAPSR_nzcvqg, %%|lr", conditional);
++	      else
++		snprintf (instr, sizeof (instr),
++			  "msr%s\tAPSR_nzcvq, %%|lr", conditional);
++
++	      output_asm_insn (instr, & operand);
++	      if (TARGET_HARD_FLOAT && !TARGET_THUMB1)
++		{
++		  /* Clear the cumulative exception-status bits (0-4,7) and the
++		     condition code bits (28-31) of the FPSCR.  We need to
++		     remember to clear the first scratch register used (IP) and
++		     save and restore the second (r4).  */
++		  snprintf (instr, sizeof (instr), "push\t{%%|r4}");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "vmrs\t%%|ip, fpscr");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "movw\t%%|r4, #65376");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "movt\t%%|r4, #4095");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "and\t%%|ip, %%|r4");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "vmsr\tfpscr, %%|ip");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "pop\t{%%|r4}");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "mov\t%%|ip, %%|lr");
++		  output_asm_insn (instr, & operand);
++		}
++	      snprintf (instr, sizeof (instr), "bxns\t%%|lr");
++	    }
+ 	  /* Use bx if it's available.  */
+-	  if (arm_arch5 || arm_arch4t)
++	  else if (arm_arch5 || arm_arch4t)
+ 	    sprintf (instr, "bx%s\t%%|lr", conditional);
+ 	  else
+ 	    sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
+ 	  break;
+ 	}
+ 
+-      output_asm_insn (instr, & operand);
++      output_asm_insn (instr, & operand);
++    }
++
++  return "";
++}
++
++/* Output in FILE asm statements needed to declare the NAME of the function
++   defined by its DECL node.  */
++
++void
++arm_asm_declare_function_name (FILE *file, const char *name, tree decl)
++{
++  size_t cmse_name_len;
++  char *cmse_name = 0;
++  char cmse_prefix[] = "__acle_se_";
++
++  /* When compiling with ARMv8-M Security Extensions enabled, we should print an
++     extra function label for each function with the 'cmse_nonsecure_entry'
++     attribute.  This extra function label should be prepended with
++     '__acle_se_', telling the linker that it needs to create secure gateway
++     veneers for this function.  */
++  if (use_cmse && lookup_attribute ("cmse_nonsecure_entry",
++				    DECL_ATTRIBUTES (decl)))
++    {
++      cmse_name_len = sizeof (cmse_prefix) + strlen (name);
++      cmse_name = XALLOCAVEC (char, cmse_name_len);
++      snprintf (cmse_name, cmse_name_len, "%s%s", cmse_prefix, name);
++      targetm.asm_out.globalize_label (file, cmse_name);
++
++      ARM_DECLARE_FUNCTION_NAME (file, cmse_name, decl);
++      ASM_OUTPUT_TYPE_DIRECTIVE (file, cmse_name, "function");
+     }
+ 
+-  return "";
++  ARM_DECLARE_FUNCTION_NAME (file, name, decl);
++  ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
++  ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
++  ASM_OUTPUT_LABEL (file, name);
++
++  if (cmse_name)
++    ASM_OUTPUT_LABEL (file, cmse_name);
++
++  ARM_OUTPUT_FN_UNWIND (file, TRUE);
+ }
+ 
+ /* Write the function name into the code section, directly preceding
+@@ -19766,10 +19433,6 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
+ {
+   unsigned long func_type;
+ 
+-  /* ??? Do we want to print some of the below anyway?  */
+-  if (TARGET_THUMB1)
+-    return;
+-
+   /* Sanity check.  */
+   gcc_assert (!arm_ccfsm_state && !arm_target_insn);
+ 
+@@ -19804,6 +19467,8 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
+     asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
+   if (IS_STACKALIGN (func_type))
+     asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
++  if (IS_CMSE_ENTRY (func_type))
++    asm_fprintf (f, "\t%@ Non-secure entry function: called from non-secure code.\n");
+ 
+   asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
+ 	       crtl->args.size,
+@@ -20473,7 +20138,7 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
+   REG_NOTES (par) = dwarf;
+ 
+   /* Make sure cfa doesn't leave with IP_REGNUM to allow unwinding fron FP.  */
+-  if (TARGET_VFP && REGNO (base_reg) == IP_REGNUM)
++  if (REGNO (base_reg) == IP_REGNUM)
+     {
+       RTX_FRAME_RELATED_P (par) = 1;
+       add_reg_note (par, REG_CFA_DEF_CFA, hard_frame_pointer_rtx);
+@@ -20934,7 +20599,7 @@ arm_get_frame_offsets (void)
+       func_type = arm_current_func_type ();
+       /* Space for saved VFP registers.  */
+       if (! IS_VOLATILE (func_type)
+-	  && TARGET_HARD_FLOAT && TARGET_VFP)
++	  && TARGET_HARD_FLOAT)
+ 	saved += arm_get_vfp_saved_size ();
+     }
+   else /* TARGET_THUMB1 */
+@@ -21155,7 +20820,7 @@ arm_save_coproc_regs(void)
+ 	saved_size += 8;
+       }
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       start_reg = FIRST_VFP_REGNUM;
+ 
+@@ -22941,6 +22606,8 @@ maybe_get_arm_condition_code (rtx comparison)
+ 	{
+ 	case LTU: return ARM_CS;
+ 	case GEU: return ARM_CC;
++	case NE: return ARM_CS;
++	case EQ: return ARM_CC;
+ 	default: return ARM_NV;
+ 	}
+ 
+@@ -22966,6 +22633,14 @@ maybe_get_arm_condition_code (rtx comparison)
+ 	default: return ARM_NV;
+ 	}
+ 
++    case CC_Vmode:
++      switch (comp_code)
++	{
++	case NE: return ARM_VS;
++	case EQ: return ARM_VC;
++	default: return ARM_NV;
++	}
++
+     case CCmode:
+       switch (comp_code)
+ 	{
+@@ -23396,7 +23071,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+ {
+   if (GET_MODE_CLASS (mode) == MODE_CC)
+     return (regno == CC_REGNUM
+-	    || (TARGET_HARD_FLOAT && TARGET_VFP
++	    || (TARGET_HARD_FLOAT
+ 		&& regno == VFPCC_REGNUM));
+ 
+   if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC)
+@@ -23410,8 +23085,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+        start of an even numbered register pair.  */
+     return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP
+-      && IS_VFP_REGNUM (regno))
++  if (TARGET_HARD_FLOAT && IS_VFP_REGNUM (regno))
+     {
+       if (mode == SFmode || mode == SImode)
+ 	return VFP_REGNO_OK_FOR_SINGLE (regno);
+@@ -23419,10 +23093,12 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+       if (mode == DFmode)
+ 	return VFP_REGNO_OK_FOR_DOUBLE (regno);
+ 
+-      /* VFP registers can hold HFmode values, but there is no point in
+-	 putting them there unless we have hardware conversion insns. */
+       if (mode == HFmode)
+-	return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno);
++	return VFP_REGNO_OK_FOR_SINGLE (regno);
++
++      /* VFP registers can hold HImode values.  */
++      if (mode == HImode)
++	return VFP_REGNO_OK_FOR_SINGLE (regno);
+ 
+       if (TARGET_NEON)
+         return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
+@@ -23626,26 +23302,6 @@ arm_debugger_arg_offset (int value, rtx addr)
+   return value;
+ }
+ 
+-/* Implement TARGET_INVALID_PARAMETER_TYPE.  */
+-
+-static const char *
+-arm_invalid_parameter_type (const_tree t)
+-{
+-  if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
+-    return N_("function parameters cannot have __fp16 type");
+-  return NULL;
+-}
+-
+-/* Implement TARGET_INVALID_PARAMETER_TYPE.  */
+-
+-static const char *
+-arm_invalid_return_type (const_tree t)
+-{
+-  if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
+-    return N_("functions cannot return __fp16 type");
+-  return NULL;
+-}
+-
+ /* Implement TARGET_PROMOTED_TYPE.  */
+ 
+ static tree
+@@ -23885,8 +23541,8 @@ thumb_pop (FILE *f, unsigned long mask)
+   if (mask & (1 << PC_REGNUM))
+     {
+       /* Catch popping the PC.  */
+-      if (TARGET_INTERWORK || TARGET_BACKTRACE
+-	  || crtl->calls_eh_return)
++      if (TARGET_INTERWORK || TARGET_BACKTRACE || crtl->calls_eh_return
++	  || IS_CMSE_ENTRY (arm_current_func_type ()))
+ 	{
+ 	  /* The PC is never poped directly, instead
+ 	     it is popped into r3 and then BX is used.  */
+@@ -23947,7 +23603,14 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+       if (crtl->calls_eh_return)
+ 	asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
+ 
+-      asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
++      if (IS_CMSE_ENTRY (arm_current_func_type ()))
++	{
++	  asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n",
++		       reg_containing_return_addr);
++	  asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr);
++	}
++      else
++	asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
+       return;
+     }
+   /* Otherwise if we are not supporting interworking and we have not created
+@@ -23956,7 +23619,8 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+   else if (!TARGET_INTERWORK
+ 	   && !TARGET_BACKTRACE
+ 	   && !is_called_in_ARM_mode (current_function_decl)
+-	   && !crtl->calls_eh_return)
++	   && !crtl->calls_eh_return
++	   && !IS_CMSE_ENTRY (arm_current_func_type ()))
+     {
+       asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
+       return;
+@@ -24179,7 +23843,21 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+     asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
+ 
+   /* Return to caller.  */
+-  asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
++  if (IS_CMSE_ENTRY (arm_current_func_type ()))
++    {
++      /* This is for the cases where LR is not being used to contain the return
++         address.  It may therefore contain information that we might not want
++	 to leak, hence it must be cleared.  The value in R0 will never be a
++	 secret at this point, so it is safe to use it, see the clearing code
++	 in 'cmse_nonsecure_entry_clear_before_return'.  */
++      if (reg_containing_return_addr != LR_REGNUM)
++	asm_fprintf (f, "\tmov\tlr, r0\n");
++
++      asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n", reg_containing_return_addr);
++      asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr);
++    }
++  else
++    asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
+ }
+ 
+ /* Scan INSN just before assembler is output for it.
+@@ -25044,6 +24722,149 @@ thumb1_expand_prologue (void)
+     cfun->machine->lr_save_eliminated = 0;
+ }
+ 
++/* Clear caller saved registers not used to pass return values and leaked
++   condition flags before exiting a cmse_nonsecure_entry function.  */
++
++void
++cmse_nonsecure_entry_clear_before_return (void)
++{
++  uint64_t to_clear_mask[2];
++  uint32_t padding_bits_to_clear = 0;
++  uint32_t * padding_bits_to_clear_ptr = &padding_bits_to_clear;
++  int regno, maxregno = IP_REGNUM;
++  tree result_type;
++  rtx result_rtl;
++
++  to_clear_mask[0] = (1ULL << (NUM_ARG_REGS)) - 1;
++  to_clear_mask[0] |= (1ULL << IP_REGNUM);
++
++  /* If we are not dealing with -mfloat-abi=soft we will need to clear VFP
++     registers.  We also check that TARGET_HARD_FLOAT and !TARGET_THUMB1 hold
++     to make sure the instructions used to clear them are present.  */
++  if (TARGET_HARD_FLOAT && !TARGET_THUMB1)
++    {
++      uint64_t float_mask = (1ULL << (D7_VFP_REGNUM + 1)) - 1;
++      maxregno = LAST_VFP_REGNUM;
++
++      float_mask &= ~((1ULL << FIRST_VFP_REGNUM) - 1);
++      to_clear_mask[0] |= float_mask;
++
++      float_mask = (1ULL << (maxregno - 63)) - 1;
++      to_clear_mask[1] = float_mask;
++
++      /* Make sure we don't clear the two scratch registers used to clear the
++	 relevant FPSCR bits in output_return_instruction.  */
++      emit_use (gen_rtx_REG (SImode, IP_REGNUM));
++      to_clear_mask[0] &= ~(1ULL << IP_REGNUM);
++      emit_use (gen_rtx_REG (SImode, 4));
++      to_clear_mask[0] &= ~(1ULL << 4);
++    }
++
++  /* If the user has defined registers to be caller saved, these are no longer
++     restored by the function before returning and must thus be cleared for
++     security purposes.  */
++  for (regno = NUM_ARG_REGS; regno < LAST_VFP_REGNUM; regno++)
++    {
++      /* We do not touch registers that can be used to pass arguments as per
++	 the AAPCS, since these should never be made callee-saved by user
++	 options.  */
++      if (IN_RANGE (regno, FIRST_VFP_REGNUM, D7_VFP_REGNUM))
++	continue;
++      if (IN_RANGE (regno, IP_REGNUM, PC_REGNUM))
++	continue;
++      if (call_used_regs[regno])
++	to_clear_mask[regno / 64] |= (1ULL << (regno % 64));
++    }
++
++  /* Make sure we do not clear the registers used to return the result in.  */
++  result_type = TREE_TYPE (DECL_RESULT (current_function_decl));
++  if (!VOID_TYPE_P (result_type))
++    {
++      result_rtl = arm_function_value (result_type, current_function_decl, 0);
++
++      /* No need to check that we return in registers, because we don't
++	 support returning on stack yet.  */
++      to_clear_mask[0]
++	&= ~compute_not_to_clear_mask (result_type, result_rtl, 0,
++				       padding_bits_to_clear_ptr);
++    }
++
++  if (padding_bits_to_clear != 0)
++    {
++      rtx reg_rtx;
++      /* Padding bits to clear is not 0 so we know we are dealing with
++	 returning a composite type, which only uses r0.  Let's make sure that
++	 r1-r3 is cleared too, we will use r1 as a scratch register.  */
++      gcc_assert ((to_clear_mask[0] & 0xe) == 0xe);
++
++      reg_rtx = gen_rtx_REG (SImode, R1_REGNUM);
++
++      /* Fill the lower half of the negated padding_bits_to_clear.  */
++      emit_move_insn (reg_rtx,
++		      GEN_INT ((((~padding_bits_to_clear) << 16u) >> 16u)));
++
++      /* Also fill the top half of the negated padding_bits_to_clear.  */
++      if (((~padding_bits_to_clear) >> 16) > 0)
++	emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode, reg_rtx,
++						      GEN_INT (16),
++						      GEN_INT (16)),
++				GEN_INT ((~padding_bits_to_clear) >> 16)));
++
++      emit_insn (gen_andsi3 (gen_rtx_REG (SImode, R0_REGNUM),
++			   gen_rtx_REG (SImode, R0_REGNUM),
++			   reg_rtx));
++    }
++
++  for (regno = R0_REGNUM; regno <= maxregno; regno++)
++    {
++      if (!(to_clear_mask[regno / 64] & (1ULL << (regno % 64))))
++	continue;
++
++      if (IS_VFP_REGNUM (regno))
++	{
++	  /* If regno is an even vfp register and its successor is also to
++	     be cleared, use vmov.  */
++	  if (TARGET_VFP_DOUBLE
++	      && VFP_REGNO_OK_FOR_DOUBLE (regno)
++	      && to_clear_mask[regno / 64] & (1ULL << ((regno % 64) + 1)))
++	    {
++	      emit_move_insn (gen_rtx_REG (DFmode, regno),
++			      CONST1_RTX (DFmode));
++	      emit_use (gen_rtx_REG (DFmode, regno));
++	      regno++;
++	    }
++	  else
++	    {
++	      emit_move_insn (gen_rtx_REG (SFmode, regno),
++			      CONST1_RTX (SFmode));
++	      emit_use (gen_rtx_REG (SFmode, regno));
++	    }
++	}
++      else
++	{
++	  if (TARGET_THUMB1)
++	    {
++	      if (regno == R0_REGNUM)
++		emit_move_insn (gen_rtx_REG (SImode, regno),
++				const0_rtx);
++	      else
++		/* R0 has either been cleared before, see code above, or it
++		   holds a return value, either way it is not secret
++		   information.  */
++		emit_move_insn (gen_rtx_REG (SImode, regno),
++				gen_rtx_REG (SImode, R0_REGNUM));
++	      emit_use (gen_rtx_REG (SImode, regno));
++	    }
++	  else
++	    {
++	      emit_move_insn (gen_rtx_REG (SImode, regno),
++			      gen_rtx_REG (SImode, LR_REGNUM));
++	      emit_use (gen_rtx_REG (SImode, regno));
++	    }
++	}
++    }
++}
++
+ /* Generate pattern *pop_multiple_with_stack_update_and_return if single
+    POP instruction can be generated.  LR should be replaced by PC.  All
+    the checks required are already done by  USE_RETURN_INSN ().  Hence,
+@@ -25065,6 +24886,12 @@ thumb2_expand_return (bool simple_return)
+ 
+   if (!simple_return && saved_regs_mask)
+     {
++      /* TODO: Verify that this path is never taken for cmse_nonsecure_entry
++	 functions or adapt code to handle according to ACLE.  This path should
++	 not be reachable for cmse_nonsecure_entry functions though we prefer
++	 to assert it for now to ensure that future code changes do not silently
++	 change this behavior.  */
++      gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ()));
+       if (num_regs == 1)
+         {
+           rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
+@@ -25087,6 +24914,8 @@ thumb2_expand_return (bool simple_return)
+     }
+   else
+     {
++      if (IS_CMSE_ENTRY (arm_current_func_type ()))
++	cmse_nonsecure_entry_clear_before_return ();
+       emit_jump_insn (simple_return_rtx);
+     }
+ }
+@@ -25145,6 +24974,10 @@ thumb1_expand_epilogue (void)
+ 
+   if (! df_regs_ever_live_p (LR_REGNUM))
+     emit_use (gen_rtx_REG (SImode, LR_REGNUM));
++
++  /* Clear all caller-saved regs that are not used to return.  */
++  if (IS_CMSE_ENTRY (arm_current_func_type ()))
++    cmse_nonsecure_entry_clear_before_return ();
+ }
+ 
+ /* Epilogue code for APCS frame.  */
+@@ -25179,7 +25012,7 @@ arm_expand_epilogue_apcs_frame (bool really_return)
+         floats_from_frame += 4;
+       }
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       int start_reg;
+       rtx ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
+@@ -25425,7 +25258,7 @@ arm_expand_epilogue (bool really_return)
+         }
+     }
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       /* Generate VFP register multi-pop.  */
+       int end_reg = LAST_VFP_REGNUM + 1;
+@@ -25482,6 +25315,7 @@ arm_expand_epilogue (bool really_return)
+ 
+       if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
+           && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
++	  && !IS_CMSE_ENTRY (func_type)
+           && !IS_STACKALIGN (func_type)
+           && really_return
+           && crtl->args.pretend_args_size == 0
+@@ -25578,6 +25412,14 @@ arm_expand_epilogue (bool really_return)
+ 				   stack_pointer_rtx, stack_pointer_rtx);
+     }
+ 
++    /* Clear all caller-saved regs that are not used to return.  */
++    if (IS_CMSE_ENTRY (arm_current_func_type ()))
++      {
++	/* CMSE_ENTRY always returns.  */
++	gcc_assert (really_return);
++	cmse_nonsecure_entry_clear_before_return ();
++      }
++
+   if (!really_return)
+     return;
+ 
+@@ -25874,13 +25716,6 @@ thumb_reload_out_hi (rtx *operands)
+   emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
+ }
+ 
+-/* Handle reading a half-word from memory during reload.  */
+-void
+-thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
+-{
+-  gcc_unreachable ();
+-}
+-
+ /* Return the length of a function name prefix
+     that starts with the character 'c'.  */
+ static int
+@@ -26018,7 +25853,7 @@ arm_file_start (void)
+ 	      const char* pos = strchr (arm_selected_arch->name, '+');
+ 	      if (pos)
+ 		{
+-		  char buf[15];
++		  char buf[32];
+ 		  gcc_assert (strlen (arm_selected_arch->name)
+ 			      <= sizeof (buf) / sizeof (*pos));
+ 		  strncpy (buf, arm_selected_arch->name,
+@@ -26043,7 +25878,7 @@ arm_file_start (void)
+       if (print_tune_info)
+ 	arm_print_tune_info ();
+ 
+-      if (! TARGET_SOFT_FLOAT && TARGET_VFP)
++      if (! TARGET_SOFT_FLOAT)
+ 	{
+ 	  if (TARGET_HARD_FLOAT && TARGET_VFP_SINGLE)
+ 	    arm_emit_eabi_attribute ("Tag_ABI_HardFP_use", 27, 1);
+@@ -26160,11 +25995,10 @@ arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
+ 
+ /* Output code to add DELTA to the first argument, and then jump
+    to FUNCTION.  Used for C++ multiple inheritance.  */
++
+ static void
+-arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+-		     HOST_WIDE_INT delta,
+-		     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+-		     tree function)
++arm_thumb1_mi_thunk (FILE *file, tree, HOST_WIDE_INT delta,
++		     HOST_WIDE_INT, tree function)
+ {
+   static int thunk_label = 0;
+   char label[256];
+@@ -26305,6 +26139,76 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+   final_end_function ();
+ }
+ 
++/* MI thunk handling for TARGET_32BIT.  */
++
++static void
++arm32_output_mi_thunk (FILE *file, tree, HOST_WIDE_INT delta,
++		       HOST_WIDE_INT vcall_offset, tree function)
++{
++  /* On ARM, this_regno is R0 or R1 depending on
++     whether the function returns an aggregate or not.
++  */
++  int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)),
++				       function)
++		    ? R1_REGNUM : R0_REGNUM);
++
++  rtx temp = gen_rtx_REG (Pmode, IP_REGNUM);
++  rtx this_rtx = gen_rtx_REG (Pmode, this_regno);
++  reload_completed = 1;
++  emit_note (NOTE_INSN_PROLOGUE_END);
++
++  /* Add DELTA to THIS_RTX.  */
++  if (delta != 0)
++    arm_split_constant (PLUS, Pmode, NULL_RTX,
++			delta, this_rtx, this_rtx, false);
++
++  /* Add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX.  */
++  if (vcall_offset != 0)
++    {
++      /* Load *THIS_RTX.  */
++      emit_move_insn (temp, gen_rtx_MEM (Pmode, this_rtx));
++      /* Compute *THIS_RTX + VCALL_OFFSET.  */
++      arm_split_constant (PLUS, Pmode, NULL_RTX, vcall_offset, temp, temp,
++			  false);
++      /* Compute *(*THIS_RTX + VCALL_OFFSET).  */
++      emit_move_insn (temp, gen_rtx_MEM (Pmode, temp));
++      emit_insn (gen_add3_insn (this_rtx, this_rtx, temp));
++    }
++
++  /* Generate a tail call to the target function.  */
++  if (!TREE_USED (function))
++    {
++      assemble_external (function);
++      TREE_USED (function) = 1;
++    }
++  rtx funexp = XEXP (DECL_RTL (function), 0);
++  funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
++  rtx_insn * insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
++  SIBLING_CALL_P (insn) = 1;
++
++  insn = get_insns ();
++  shorten_branches (insn);
++  final_start_function (insn, file, 1);
++  final (insn, file, 1);
++  final_end_function ();
++
++  /* Stop pretending this is a post-reload pass.  */
++  reload_completed = 0;
++}
++
++/* Output code to add DELTA to the first argument, and then jump
++   to FUNCTION.  Used for C++ multiple inheritance.  */
++
++static void
++arm_output_mi_thunk (FILE *file, tree thunk, HOST_WIDE_INT delta,
++		     HOST_WIDE_INT vcall_offset, tree function)
++{
++  if (TARGET_32BIT)
++    arm32_output_mi_thunk (file, thunk, delta, vcall_offset, function);
++  else
++    arm_thumb1_mi_thunk (file, thunk, delta, vcall_offset, function);
++}
++
+ int
+ arm_emit_vector_const (FILE *file, rtx x)
+ {
+@@ -27543,7 +27447,7 @@ arm_mangle_type (const_tree type)
+ static const int thumb_core_reg_alloc_order[] =
+ {
+    3,  2,  1,  0,  4,  5,  6,  7,
+-  14, 12,  8,  9, 10, 11
++  12, 14,  8,  9, 10, 11
+ };
+ 
+ /* Adjust register allocation order when compiling for Thumb.  */
+@@ -27689,7 +27593,7 @@ arm_conditional_register_usage (void)
+   if (TARGET_THUMB1)
+     fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
+ 
+-  if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_32BIT && TARGET_HARD_FLOAT)
+     {
+       /* VFPv3 registers are disabled when earlier VFP
+ 	 versions are selected due to the definition of
+@@ -27760,7 +27664,7 @@ arm_preferred_rename_class (reg_class_t rclass)
+     return NO_REGS;
+ }
+ 
+-/* Compute the atrribute "length" of insn "*push_multi".
++/* Compute the attribute "length" of insn "*push_multi".
+    So this function MUST be kept in sync with that insn pattern.  */
+ int
+ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+@@ -27777,6 +27681,11 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+ 
+   /* Thumb2 mode.  */
+   regno = REGNO (first_op);
++  /* For PUSH/STM under Thumb2 mode, we can use 16-bit encodings if the register
++     list is 8-bit.  Normally this means all registers in the list must be
++     LO_REGS, that is (R0 -R7).  If any HI_REGS used, then we must use 32-bit
++     encodings.  There is one exception for PUSH that LR in HI_REGS can be used
++     with 16-bit encoding.  */
+   hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
+   for (i = 1; i < num_saves && !hi_reg; i++)
+     {
+@@ -27789,6 +27698,56 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+   return 4;
+ }
+ 
++/* Compute the attribute "length" of insn.  Currently, this function is used
++   for "*load_multiple_with_writeback", "*pop_multiple_with_return" and
++   "*pop_multiple_with_writeback_and_return".  OPERANDS is the toplevel PARALLEL
++   rtx, RETURN_PC is true if OPERANDS contains return insn.  WRITE_BACK_P is
++   true if OPERANDS contains insn which explicit updates base register.  */
++
++int
++arm_attr_length_pop_multi (rtx *operands, bool return_pc, bool write_back_p)
++{
++  /* ARM mode.  */
++  if (TARGET_ARM)
++    return 4;
++  /* Thumb1 mode.  */
++  if (TARGET_THUMB1)
++    return 2;
++
++  rtx parallel_op = operands[0];
++  /* Initialize to elements number of PARALLEL.  */
++  unsigned indx = XVECLEN (parallel_op, 0) - 1;
++  /* Initialize the value to base register.  */
++  unsigned regno = REGNO (operands[1]);
++  /* Skip return and write back pattern.
++     We only need register pop pattern for later analysis.  */
++  unsigned first_indx = 0;
++  first_indx += return_pc ? 1 : 0;
++  first_indx += write_back_p ? 1 : 0;
++
++  /* A pop operation can be done through LDM or POP.  If the base register is SP
++     and if it's with write back, then a LDM will be alias of POP.  */
++  bool pop_p = (regno == SP_REGNUM && write_back_p);
++  bool ldm_p = !pop_p;
++
++  /* Check base register for LDM.  */
++  if (ldm_p && REGNO_REG_CLASS (regno) == HI_REGS)
++    return 4;
++
++  /* Check each register in the list.  */
++  for (; indx >= first_indx; indx--)
++    {
++      regno = REGNO (XEXP (XVECEXP (parallel_op, 0, indx), 0));
++      /* For POP, PC in HI_REGS can be used with 16-bit encoding.  See similar
++	 comment in arm_attr_length_push_multi.  */
++      if (REGNO_REG_CLASS (regno) == HI_REGS
++	  && (regno != PC_REGNUM || ldm_p))
++	return 4;
++    }
++
++  return 2;
++}
++
+ /* Compute the number of instructions emitted by output_move_double.  */
+ int
+ arm_count_output_move_double_insns (rtx *operands)
+@@ -27820,7 +27779,11 @@ vfp3_const_double_for_fract_bits (rtx operand)
+ 	  HOST_WIDE_INT value = real_to_integer (&r0);
+ 	  value = value & 0xffffffff;
+ 	  if ((value != 0) && ( (value & (value - 1)) == 0))
+-	    return int_log2 (value);
++	    {
++	      int ret = exact_log2 (value);
++	      gcc_assert (IN_RANGE (ret, 0, 31));
++	      return ret;
++	    }
+ 	}
+     }
+   return 0;
+@@ -27960,9 +27923,9 @@ emit_unlikely_jump (rtx insn)
+ void
+ arm_expand_compare_and_swap (rtx operands[])
+ {
+-  rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
++  rtx bval, bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
+   machine_mode mode;
+-  rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
++  rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+ 
+   bval = operands[0];
+   rval = operands[1];
+@@ -28019,43 +27982,54 @@ arm_expand_compare_and_swap (rtx operands[])
+       gcc_unreachable ();
+     }
+ 
+-  emit_insn (gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
++  bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CCmode, CC_REGNUM);
++  emit_insn (gen (bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f));
+ 
+   if (mode == QImode || mode == HImode)
+     emit_move_insn (operands[1], gen_lowpart (mode, rval));
+ 
+   /* In all cases, we arrange for success to be signaled by Z set.
+      This arrangement allows for the boolean result to be used directly
+-     in a subsequent branch, post optimization.  */
+-  x = gen_rtx_REG (CCmode, CC_REGNUM);
+-  x = gen_rtx_EQ (SImode, x, const0_rtx);
+-  emit_insn (gen_rtx_SET (bval, x));
++     in a subsequent branch, post optimization.  For Thumb-1 targets, the
++     boolean negation of the result is also stored in bval because Thumb-1
++     backend lacks dependency tracking for CC flag due to flag-setting not
++     being represented at RTL level.  */
++  if (TARGET_THUMB1)
++      emit_insn (gen_cstoresi_eq0_thumb1 (bval, bdst));
++  else
++    {
++      x = gen_rtx_EQ (SImode, bdst, const0_rtx);
++      emit_insn (gen_rtx_SET (bval, x));
++    }
+ }
+ 
+ /* Split a compare and swap pattern.  It is IMPLEMENTATION DEFINED whether
+    another memory store between the load-exclusive and store-exclusive can
+    reset the monitor from Exclusive to Open state.  This means we must wait
+    until after reload to split the pattern, lest we get a register spill in
+-   the middle of the atomic sequence.  */
++   the middle of the atomic sequence.  Success of the compare and swap is
++   indicated by the Z flag set for 32bit targets and by neg_bval being zero
++   for Thumb-1 targets (ie. negation of the boolean value returned by
++   atomic_compare_and_swapmode standard pattern in operand 0).  */
+ 
+ void
+ arm_split_compare_and_swap (rtx operands[])
+ {
+-  rtx rval, mem, oldval, newval, scratch;
++  rtx rval, mem, oldval, newval, neg_bval;
+   machine_mode mode;
+   enum memmodel mod_s, mod_f;
+   bool is_weak;
+   rtx_code_label *label1, *label2;
+   rtx x, cond;
+ 
+-  rval = operands[0];
+-  mem = operands[1];
+-  oldval = operands[2];
+-  newval = operands[3];
+-  is_weak = (operands[4] != const0_rtx);
+-  mod_s = memmodel_from_int (INTVAL (operands[5]));
+-  mod_f = memmodel_from_int (INTVAL (operands[6]));
+-  scratch = operands[7];
++  rval = operands[1];
++  mem = operands[2];
++  oldval = operands[3];
++  newval = operands[4];
++  is_weak = (operands[5] != const0_rtx);
++  mod_s = memmodel_from_int (INTVAL (operands[6]));
++  mod_f = memmodel_from_int (INTVAL (operands[7]));
++  neg_bval = TARGET_THUMB1 ? operands[0] : operands[8];
+   mode = GET_MODE (mem);
+ 
+   bool is_armv8_sync = arm_arch8 && is_mm_sync (mod_s);
+@@ -28087,26 +28061,44 @@ arm_split_compare_and_swap (rtx operands[])
+ 
+   arm_emit_load_exclusive (mode, rval, mem, use_acquire);
+ 
+-  cond = arm_gen_compare_reg (NE, rval, oldval, scratch);
+-  x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
+-  x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
+-			    gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
+-  emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++  /* Z is set to 0 for 32bit targets (resp. rval set to 1) if oldval != rval,
++     as required to communicate with arm_expand_compare_and_swap.  */
++  if (TARGET_32BIT)
++    {
++      cond = arm_gen_compare_reg (NE, rval, oldval, neg_bval);
++      x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
++      x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
++				gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
++      emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++    }
++  else
++    {
++      emit_move_insn (neg_bval, const1_rtx);
++      cond = gen_rtx_NE (VOIDmode, rval, oldval);
++      if (thumb1_cmpneg_operand (oldval, SImode))
++	emit_unlikely_jump (gen_cbranchsi4_scratch (neg_bval, rval, oldval,
++						    label2, cond));
++      else
++	emit_unlikely_jump (gen_cbranchsi4_insn (cond, rval, oldval, label2));
++    }
+ 
+-  arm_emit_store_exclusive (mode, scratch, mem, newval, use_release);
++  arm_emit_store_exclusive (mode, neg_bval, mem, newval, use_release);
+ 
+   /* Weak or strong, we want EQ to be true for success, so that we
+      match the flags that we got from the compare above.  */
+-  cond = gen_rtx_REG (CCmode, CC_REGNUM);
+-  x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx);
+-  emit_insn (gen_rtx_SET (cond, x));
++  if (TARGET_32BIT)
++    {
++      cond = gen_rtx_REG (CCmode, CC_REGNUM);
++      x = gen_rtx_COMPARE (CCmode, neg_bval, const0_rtx);
++      emit_insn (gen_rtx_SET (cond, x));
++    }
+ 
+   if (!is_weak)
+     {
+-      x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
+-      x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
+-				gen_rtx_LABEL_REF (Pmode, label1), pc_rtx);
+-      emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++      /* Z is set to boolean value of !neg_bval, as required to communicate
++	 with arm_expand_compare_and_swap.  */
++      x = gen_rtx_NE (VOIDmode, neg_bval, const0_rtx);
++      emit_unlikely_jump (gen_cbranchsi4 (x, neg_bval, const0_rtx, label1));
+     }
+ 
+   if (!is_mm_relaxed (mod_f))
+@@ -28121,6 +28113,15 @@ arm_split_compare_and_swap (rtx operands[])
+     emit_label (label2);
+ }
+ 
++/* Split an atomic operation pattern.  Operation is given by CODE and is one
++   of PLUS, MINUS, IOR, XOR, SET (for an exchange operation) or NOT (for a nand
++   operation).  Operation is performed on the content at MEM and on VALUE
++   following the memory model MODEL_RTX.  The content at MEM before and after
++   the operation is returned in OLD_OUT and NEW_OUT respectively while the
++   success of the operation is returned in COND.  Using a scratch register or
++   an operand register for these determines what result is returned for that
++   pattern.  */
++
+ void
+ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+ 		     rtx value, rtx model_rtx, rtx cond)
+@@ -28129,6 +28130,7 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+   machine_mode mode = GET_MODE (mem);
+   machine_mode wmode = (mode == DImode ? DImode : SImode);
+   rtx_code_label *label;
++  bool all_low_regs, bind_old_new;
+   rtx x;
+ 
+   bool is_armv8_sync = arm_arch8 && is_mm_sync (model);
+@@ -28163,6 +28165,28 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+ 
+   arm_emit_load_exclusive (mode, old_out, mem, use_acquire);
+ 
++  /* Does the operation require destination and first operand to use the same
++     register?  This is decided by register constraints of relevant insn
++     patterns in thumb1.md.  */
++  gcc_assert (!new_out || REG_P (new_out));
++  all_low_regs = REG_P (value) && REGNO_REG_CLASS (REGNO (value)) == LO_REGS
++		 && new_out && REGNO_REG_CLASS (REGNO (new_out)) == LO_REGS
++		 && REGNO_REG_CLASS (REGNO (old_out)) == LO_REGS;
++  bind_old_new =
++    (TARGET_THUMB1
++     && code != SET
++     && code != MINUS
++     && (code != PLUS || (!all_low_regs && !satisfies_constraint_L (value))));
++
++  /* We want to return the old value while putting the result of the operation
++     in the same register as the old value so copy the old value over to the
++     destination register and use that register for the operation.  */
++  if (old_out && bind_old_new)
++    {
++      emit_move_insn (new_out, old_out);
++      old_out = new_out;
++    }
++
+   switch (code)
+     {
+     case SET:
+@@ -28377,6 +28401,8 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
+     case V8QImode:  gen = gen_neon_vuzpv8qi_internal;  break;
+     case V8HImode:  gen = gen_neon_vuzpv8hi_internal;  break;
+     case V4HImode:  gen = gen_neon_vuzpv4hi_internal;  break;
++    case V8HFmode:  gen = gen_neon_vuzpv8hf_internal;  break;
++    case V4HFmode:  gen = gen_neon_vuzpv4hf_internal;  break;
+     case V4SImode:  gen = gen_neon_vuzpv4si_internal;  break;
+     case V2SImode:  gen = gen_neon_vuzpv2si_internal;  break;
+     case V2SFmode:  gen = gen_neon_vuzpv2sf_internal;  break;
+@@ -28450,6 +28476,8 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
+     case V8QImode:  gen = gen_neon_vzipv8qi_internal;  break;
+     case V8HImode:  gen = gen_neon_vzipv8hi_internal;  break;
+     case V4HImode:  gen = gen_neon_vzipv4hi_internal;  break;
++    case V8HFmode:  gen = gen_neon_vzipv8hf_internal;  break;
++    case V4HFmode:  gen = gen_neon_vzipv4hf_internal;  break;
+     case V4SImode:  gen = gen_neon_vzipv4si_internal;  break;
+     case V2SImode:  gen = gen_neon_vzipv2si_internal;  break;
+     case V2SFmode:  gen = gen_neon_vzipv2sf_internal;  break;
+@@ -28502,6 +28530,8 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
+ 	case V8QImode:  gen = gen_neon_vrev32v8qi;  break;
+ 	case V8HImode:  gen = gen_neon_vrev64v8hi;  break;
+ 	case V4HImode:  gen = gen_neon_vrev64v4hi;  break;
++	case V8HFmode:  gen = gen_neon_vrev64v8hf;  break;
++	case V4HFmode:  gen = gen_neon_vrev64v4hf;  break;
+ 	default:
+ 	  return false;
+ 	}
+@@ -28585,6 +28615,8 @@ arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
+     case V8QImode:  gen = gen_neon_vtrnv8qi_internal;  break;
+     case V8HImode:  gen = gen_neon_vtrnv8hi_internal;  break;
+     case V4HImode:  gen = gen_neon_vtrnv4hi_internal;  break;
++    case V8HFmode:  gen = gen_neon_vtrnv8hf_internal;  break;
++    case V4HFmode:  gen = gen_neon_vtrnv4hf_internal;  break;
+     case V4SImode:  gen = gen_neon_vtrnv4si_internal;  break;
+     case V2SImode:  gen = gen_neon_vtrnv2si_internal;  break;
+     case V2SFmode:  gen = gen_neon_vtrnv2sf_internal;  break;
+@@ -28660,6 +28692,8 @@ arm_evpc_neon_vext (struct expand_vec_perm_d *d)
+     case V8HImode: gen = gen_neon_vextv8hi; break;
+     case V2SImode: gen = gen_neon_vextv2si; break;
+     case V4SImode: gen = gen_neon_vextv4si; break;
++    case V4HFmode: gen = gen_neon_vextv4hf; break;
++    case V8HFmode: gen = gen_neon_vextv8hf; break;
+     case V2SFmode: gen = gen_neon_vextv2sf; break;
+     case V4SFmode: gen = gen_neon_vextv4sf; break;
+     case V2DImode: gen = gen_neon_vextv2di; break;
+@@ -29185,7 +29219,7 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
+ {
+   enum rtx_code code = GET_CODE (*comparison);
+   int code_int;
+-  machine_mode mode = (GET_MODE (*op1) == VOIDmode) 
++  machine_mode mode = (GET_MODE (*op1) == VOIDmode)
+     ? GET_MODE (*op2) : GET_MODE (*op1);
+ 
+   gcc_assert (GET_MODE (*op1) != VOIDmode || GET_MODE (*op2) != VOIDmode);
+@@ -29213,11 +29247,19 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
+ 	*op2 = force_reg (mode, *op2);
+       return true;
+ 
++    case HFmode:
++      if (!TARGET_VFP_FP16INST)
++	break;
++      /* FP16 comparisons are done in SF mode.  */
++      mode = SFmode;
++      *op1 = convert_to_mode (mode, *op1, 1);
++      *op2 = convert_to_mode (mode, *op2, 1);
++      /* Fall through.  */
+     case SFmode:
+     case DFmode:
+-      if (!arm_float_compare_operand (*op1, mode))
++      if (!vfp_compare_operand (*op1, mode))
+ 	*op1 = force_reg (mode, *op1);
+-      if (!arm_float_compare_operand (*op2, mode))
++      if (!vfp_compare_operand (*op2, mode))
+ 	*op2 = force_reg (mode, *op2);
+       return true;
+     default:
+@@ -29759,11 +29801,57 @@ arm_macro_fusion_p (void)
+   return current_tune->fusible_ops != tune_params::FUSE_NOTHING;
+ }
+ 
++/* Return true if the two back-to-back sets PREV_SET, CURR_SET are suitable
++   for MOVW / MOVT macro fusion.  */
++
++static bool
++arm_sets_movw_movt_fusible_p (rtx prev_set, rtx curr_set)
++{
++  /* We are trying to fuse
++     movw imm / movt imm
++    instructions as a group that gets scheduled together.  */
++
++  rtx set_dest = SET_DEST (curr_set);
++
++  if (GET_MODE (set_dest) != SImode)
++    return false;
++
++  /* We are trying to match:
++     prev (movw)  == (set (reg r0) (const_int imm16))
++     curr (movt) == (set (zero_extract (reg r0)
++					(const_int 16)
++					(const_int 16))
++			  (const_int imm16_1))
++     or
++     prev (movw) == (set (reg r1)
++			  (high (symbol_ref ("SYM"))))
++    curr (movt) == (set (reg r0)
++			(lo_sum (reg r1)
++				(symbol_ref ("SYM"))))  */
++
++    if (GET_CODE (set_dest) == ZERO_EXTRACT)
++      {
++	if (CONST_INT_P (SET_SRC (curr_set))
++	    && CONST_INT_P (SET_SRC (prev_set))
++	    && REG_P (XEXP (set_dest, 0))
++	    && REG_P (SET_DEST (prev_set))
++	    && REGNO (XEXP (set_dest, 0)) == REGNO (SET_DEST (prev_set)))
++	  return true;
++
++      }
++    else if (GET_CODE (SET_SRC (curr_set)) == LO_SUM
++	     && REG_P (SET_DEST (curr_set))
++	     && REG_P (SET_DEST (prev_set))
++	     && GET_CODE (SET_SRC (prev_set)) == HIGH
++	     && REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set)))
++      return true;
++
++  return false;
++}
+ 
+ static bool
+ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
+ {
+-  rtx set_dest;
+   rtx prev_set = single_set (prev);
+   rtx curr_set = single_set (curr);
+ 
+@@ -29781,54 +29869,26 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
+       && aarch_crypto_can_dual_issue (prev, curr))
+     return true;
+ 
+-  if (current_tune->fusible_ops & tune_params::FUSE_MOVW_MOVT)
+-    {
+-      /* We are trying to fuse
+-	 movw imm / movt imm
+-	 instructions as a group that gets scheduled together.  */
+-
+-      set_dest = SET_DEST (curr_set);
+-
+-      if (GET_MODE (set_dest) != SImode)
+-	return false;
++  if (current_tune->fusible_ops & tune_params::FUSE_MOVW_MOVT
++      && arm_sets_movw_movt_fusible_p (prev_set, curr_set))
++    return true;
+ 
+-      /* We are trying to match:
+-	 prev (movw)  == (set (reg r0) (const_int imm16))
+-	 curr (movt) == (set (zero_extract (reg r0)
+-					  (const_int 16)
+-					   (const_int 16))
+-			     (const_int imm16_1))
+-	 or
+-	 prev (movw) == (set (reg r1)
+-			      (high (symbol_ref ("SYM"))))
+-	 curr (movt) == (set (reg r0)
+-			     (lo_sum (reg r1)
+-				     (symbol_ref ("SYM"))))  */
+-      if (GET_CODE (set_dest) == ZERO_EXTRACT)
+-	{
+-	  if (CONST_INT_P (SET_SRC (curr_set))
+-	      && CONST_INT_P (SET_SRC (prev_set))
+-	      && REG_P (XEXP (set_dest, 0))
+-	      && REG_P (SET_DEST (prev_set))
+-	      && REGNO (XEXP (set_dest, 0)) == REGNO (SET_DEST (prev_set)))
+-	    return true;
+-	}
+-      else if (GET_CODE (SET_SRC (curr_set)) == LO_SUM
+-	       && REG_P (SET_DEST (curr_set))
+-	       && REG_P (SET_DEST (prev_set))
+-	       && GET_CODE (SET_SRC (prev_set)) == HIGH
+-	       && REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set)))
+-	     return true;
+-    }
+   return false;
+ }
+ 
++/* Return true iff the instruction fusion described by OP is enabled.  */
++bool
++arm_fusion_enabled_p (tune_params::fuse_ops op)
++{
++  return current_tune->fusible_ops & op;
++}
++
+ /* Implement the TARGET_ASAN_SHADOW_OFFSET hook.  */
+ 
+ static unsigned HOST_WIDE_INT
+ arm_asan_shadow_offset (void)
+ {
+-  return (unsigned HOST_WIDE_INT) 1 << 29;
++  return HOST_WIDE_INT_1U << 29;
+ }
+ 
+ 
+@@ -29853,9 +29913,9 @@ arm_const_not_ok_for_debug_p (rtx p)
+ 	      && GET_CODE (XEXP (p, 0)) == SYMBOL_REF
+ 	      && (decl_op0 = SYMBOL_REF_DECL (XEXP (p, 0))))
+ 	    {
+-	      if ((TREE_CODE (decl_op1) == VAR_DECL
++	      if ((VAR_P (decl_op1)
+ 		   || TREE_CODE (decl_op1) == CONST_DECL)
+-		  && (TREE_CODE (decl_op0) == VAR_DECL
++		  && (VAR_P (decl_op0)
+ 		      || TREE_CODE (decl_op0) == CONST_DECL))
+ 		return (get_variable_section (decl_op1, false)
+ 			!= get_variable_section (decl_op0, false));
+@@ -29988,9 +30048,8 @@ arm_can_inline_p (tree caller, tree callee)
+   if ((caller_fpu->features & callee_fpu->features) != callee_fpu->features)
+     return false;
+ 
+-  /* Need same model and regs.  */
+-  if (callee_fpu->model != caller_fpu->model
+-      || callee_fpu->regs != callee_fpu->regs)
++  /* Need same FPU regs.  */
++  if (callee_fpu->regs != callee_fpu->regs)
+     return false;
+ 
+   /* OK to inline between different modes.
+@@ -30333,4 +30392,113 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
+   return;
+ }
+ 
++
++/* Construct and return a PARALLEL RTX vector with elements numbering the
++   lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
++   the vector - from the perspective of the architecture.  This does not
++   line up with GCC's perspective on lane numbers, so we end up with
++   different masks depending on our target endian-ness.  The diagram
++   below may help.  We must draw the distinction when building masks
++   which select one half of the vector.  An instruction selecting
++   architectural low-lanes for a big-endian target, must be described using
++   a mask selecting GCC high-lanes.
++
++                 Big-Endian             Little-Endian
++
++GCC             0   1   2   3           3   2   1   0
++              | x | x | x | x |       | x | x | x | x |
++Architecture    3   2   1   0           3   2   1   0
++
++Low Mask:         { 2, 3 }                { 0, 1 }
++High Mask:        { 0, 1 }                { 2, 3 }
++*/
++
++rtx
++arm_simd_vect_par_cnst_half (machine_mode mode, bool high)
++{
++  int nunits = GET_MODE_NUNITS (mode);
++  rtvec v = rtvec_alloc (nunits / 2);
++  int high_base = nunits / 2;
++  int low_base = 0;
++  int base;
++  rtx t1;
++  int i;
++
++  if (BYTES_BIG_ENDIAN)
++    base = high ? low_base : high_base;
++  else
++    base = high ? high_base : low_base;
++
++  for (i = 0; i < nunits / 2; i++)
++    RTVEC_ELT (v, i) = GEN_INT (base + i);
++
++  t1 = gen_rtx_PARALLEL (mode, v);
++  return t1;
++}
++
++/* Check OP for validity as a PARALLEL RTX vector with elements
++   numbering the lanes of either the high (HIGH == TRUE) or low lanes,
++   from the perspective of the architecture.  See the diagram above
++   arm_simd_vect_par_cnst_half_p for more details.  */
++
++bool
++arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
++				       bool high)
++{
++  rtx ideal = arm_simd_vect_par_cnst_half (mode, high);
++  HOST_WIDE_INT count_op = XVECLEN (op, 0);
++  HOST_WIDE_INT count_ideal = XVECLEN (ideal, 0);
++  int i = 0;
++
++  if (!VECTOR_MODE_P (mode))
++    return false;
++
++  if (count_op != count_ideal)
++    return false;
++
++  for (i = 0; i < count_ideal; i++)
++    {
++      rtx elt_op = XVECEXP (op, 0, i);
++      rtx elt_ideal = XVECEXP (ideal, 0, i);
++
++      if (!CONST_INT_P (elt_op)
++	  || INTVAL (elt_ideal) != INTVAL (elt_op))
++	return false;
++    }
++  return true;
++}
++
++/* Can output mi_thunk for all cases except for non-zero vcall_offset
++   in Thumb1.  */
++static bool
++arm_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT vcall_offset,
++			 const_tree)
++{
++  /* For now, we punt and not handle this for TARGET_THUMB1.  */
++  if (vcall_offset && TARGET_THUMB1)
++    return false;
++
++  /* Otherwise ok.  */
++  return true;
++}
++
++/* Generate RTL for a conditional branch with rtx comparison CODE in
++   mode CC_MODE. The destination of the unlikely conditional branch
++   is LABEL_REF.  */
++
++void
++arm_gen_unlikely_cbranch (enum rtx_code code, machine_mode cc_mode,
++			  rtx label_ref)
++{
++  rtx x;
++  x = gen_rtx_fmt_ee (code, VOIDmode,
++		      gen_rtx_REG (cc_mode, CC_REGNUM),
++		      const0_rtx);
++
++  x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
++			    gen_rtx_LABEL_REF (VOIDmode, label_ref),
++			    pc_rtx);
++  emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++}
++
+ #include "gt-arm.h"
+--- a/src/gcc/config/arm/arm.h
++++ b/src/gcc/config/arm/arm.h
+@@ -80,11 +80,6 @@ extern arm_cc arm_current_cc;
+ extern int arm_target_label;
+ extern int arm_ccfsm_state;
+ extern GTY(()) rtx arm_target_insn;
+-/* The label of the current constant pool.  */
+-extern rtx pool_vector_label;
+-/* Set to 1 when a return insn is output, this means that the epilogue
+-   is not needed.  */
+-extern int return_used_this_function;
+ /* Callback to output language specific object attributes.  */
+ extern void (*arm_lang_output_object_attributes_hook)(void);
+ 
+@@ -139,7 +134,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ #define TARGET_HARD_FLOAT		(arm_float_abi != ARM_FLOAT_ABI_SOFT)
+ /* Use hardware floating point calling convention.  */
+ #define TARGET_HARD_FLOAT_ABI		(arm_float_abi == ARM_FLOAT_ABI_HARD)
+-#define TARGET_VFP		        (TARGET_FPU_MODEL == ARM_FP_MODEL_VFP)
+ #define TARGET_IWMMXT			(arm_arch_iwmmxt)
+ #define TARGET_IWMMXT2			(arm_arch_iwmmxt2)
+ #define TARGET_REALLY_IWMMXT		(TARGET_IWMMXT && TARGET_32BIT)
+@@ -177,50 +171,57 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+    to be more careful with TARGET_NEON as noted below.  */
+ 
+ /* FPU is has the full VFPv3/NEON register file of 32 D registers.  */
+-#define TARGET_VFPD32 (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_D32)
++#define TARGET_VFPD32 (TARGET_FPU_REGS == VFP_REG_D32)
+ 
+ /* FPU supports VFPv3 instructions.  */
+-#define TARGET_VFP3 (TARGET_VFP && TARGET_FPU_REV >= 3)
++#define TARGET_VFP3 (TARGET_FPU_REV >= 3)
+ 
+ /* FPU supports FPv5 instructions.  */
+-#define TARGET_VFP5 (TARGET_VFP && TARGET_FPU_REV >= 5)
++#define TARGET_VFP5 (TARGET_FPU_REV >= 5)
+ 
+ /* FPU only supports VFP single-precision instructions.  */
+-#define TARGET_VFP_SINGLE (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_SINGLE)
++#define TARGET_VFP_SINGLE (TARGET_FPU_REGS == VFP_REG_SINGLE)
+ 
+ /* FPU supports VFP double-precision instructions.  */
+-#define TARGET_VFP_DOUBLE (TARGET_VFP && TARGET_FPU_REGS != VFP_REG_SINGLE)
++#define TARGET_VFP_DOUBLE (TARGET_FPU_REGS != VFP_REG_SINGLE)
+ 
+ /* FPU supports half-precision floating-point with NEON element load/store.  */
+-#define TARGET_NEON_FP16						\
+-  (TARGET_VFP								\
+-   && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON | FPU_FL_FP16))
++#define TARGET_NEON_FP16					\
++  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)		\
++   && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+ 
+ /* FPU supports VFP half-precision floating-point.  */
+ #define TARGET_FP16							\
+-  (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
++  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+ 
+ /* FPU supports fused-multiply-add operations.  */
+-#define TARGET_FMA (TARGET_VFP && TARGET_FPU_REV >= 4)
++#define TARGET_FMA (TARGET_FPU_REV >= 4)
+ 
+ /* FPU is ARMv8 compatible.  */
+-#define TARGET_FPU_ARMV8 (TARGET_VFP && TARGET_FPU_REV >= 8)
++#define TARGET_FPU_ARMV8 (TARGET_FPU_REV >= 8)
+ 
+ /* FPU supports Crypto extensions.  */
+ #define TARGET_CRYPTO							\
+-  (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
++  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
+ 
+ /* FPU supports Neon instructions.  The setting of this macro gets
+    revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
+    and TARGET_HARD_FLOAT to ensure that NEON instructions are
+    available.  */
+ #define TARGET_NEON							\
+-  (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP			\
++  (TARGET_32BIT && TARGET_HARD_FLOAT					\
+    && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
+ 
+ /* FPU supports ARMv8.1 Adv.SIMD extensions.  */
+ #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
+ 
++/* FPU supports the floating point FP16 instructions for ARMv8.2 and later.  */
++#define TARGET_VFP_FP16INST \
++  (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 && arm_fp16_inst)
++
++/* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later.  */
++#define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA)
++
+ /* Q-bit is present.  */
+ #define TARGET_ARM_QBIT \
+   (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
+@@ -236,7 +237,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ 
+ /* Should MOVW/MOVT be used in preference to a constant pool.  */
+ #define TARGET_USE_MOVT \
+-  (arm_arch_thumb2 \
++  (TARGET_HAVE_MOVT \
+    && (arm_disable_literal_pool \
+        || (!optimize_size && !current_tune->prefer_constant_pool)))
+ 
+@@ -251,14 +252,18 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
+ 
+ /* Nonzero if this chip supports ldrex and strex */
+-#define TARGET_HAVE_LDREX        ((arm_arch6 && TARGET_ARM) || arm_arch7)
++#define TARGET_HAVE_LDREX        ((arm_arch6 && TARGET_ARM)	\
++				  || arm_arch7			\
++				  || (arm_arch8 && !arm_arch_notm))
+ 
+ /* Nonzero if this chip supports LPAE.  */
+ #define TARGET_HAVE_LPAE						\
+   (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE))
+ 
+ /* Nonzero if this chip supports ldrex{bh} and strex{bh}.  */
+-#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
++#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM)		\
++			     || arm_arch7			\
++			     || (arm_arch8 && !arm_arch_notm))
+ 
+ /* Nonzero if this chip supports ldrexd and strexd.  */
+ #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \
+@@ -267,9 +272,20 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ /* Nonzero if this chip supports load-acquire and store-release.  */
+ #define TARGET_HAVE_LDACQ	(TARGET_ARM_ARCH >= 8)
+ 
++/* Nonzero if this chip supports LDAEXD and STLEXD.  */
++#define TARGET_HAVE_LDACQEXD	(TARGET_ARM_ARCH >= 8	\
++				 && TARGET_32BIT	\
++				 && arm_arch_notm)
++
++/* Nonzero if this chip provides the MOVW and MOVT instructions.  */
++#define TARGET_HAVE_MOVT	(arm_arch_thumb2 || arm_arch8)
++
++/* Nonzero if this chip provides the CBZ and CBNZ instructions.  */
++#define TARGET_HAVE_CBZ		(arm_arch_thumb2 || arm_arch8)
++
+ /* Nonzero if integer division instructions supported.  */
+ #define TARGET_IDIV	((TARGET_ARM && arm_arch_arm_hwdiv)	\
+-			 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
++			 || (TARGET_THUMB && arm_arch_thumb_hwdiv))
+ 
+ /* Nonzero if disallow volatile memory access in IT block.  */
+ #define TARGET_NO_VOLATILE_CE		(arm_arch_no_volatile_ce)
+@@ -349,7 +365,6 @@ enum vfp_reg_type
+ extern const struct arm_fpu_desc
+ {
+   const char *name;
+-  enum arm_fp_model model;
+   int rev;
+   enum vfp_reg_type regs;
+   arm_fpu_feature_set features;
+@@ -358,7 +373,6 @@ extern const struct arm_fpu_desc
+ /* Accessors.  */
+ 
+ #define TARGET_FPU_NAME     (all_fpus[arm_fpu_index].name)
+-#define TARGET_FPU_MODEL    (all_fpus[arm_fpu_index].model)
+ #define TARGET_FPU_REV      (all_fpus[arm_fpu_index].rev)
+ #define TARGET_FPU_REGS     (all_fpus[arm_fpu_index].regs)
+ #define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)
+@@ -402,7 +416,9 @@ enum base_architecture
+   BASE_ARCH_7R = 7,
+   BASE_ARCH_7M = 7,
+   BASE_ARCH_7EM = 7,
+-  BASE_ARCH_8A = 8
++  BASE_ARCH_8A = 8,
++  BASE_ARCH_8M_BASE = 8,
++  BASE_ARCH_8M_MAIN = 8
+ };
+ 
+ /* The major revision number of the ARM Architecture implemented by the target.  */
+@@ -447,6 +463,13 @@ extern int arm_arch8;
+ /* Nonzero if this chip supports the ARM Architecture 8.1 extensions.  */
+ extern int arm_arch8_1;
+ 
++/* Nonzero if this chip supports the ARM Architecture 8.2 extensions.  */
++extern int arm_arch8_2;
++
++/* Nonzero if this chip supports the FP16 instructions extension of ARM
++   Architecture 8.2.  */
++extern int arm_fp16_inst;
++
+ /* Nonzero if this chip can benefit from load scheduling.  */
+ extern int arm_ld_sched;
+ 
+@@ -478,6 +501,9 @@ extern int arm_tune_cortex_a9;
+    interworking clean.  */
+ extern int arm_cpp_interwork;
+ 
++/* Nonzero if chip supports Thumb 1.  */
++extern int arm_arch_thumb1;
++
+ /* Nonzero if chip supports Thumb 2.  */
+ extern int arm_arch_thumb2;
+ 
+@@ -502,6 +528,9 @@ extern bool arm_disable_literal_pool;
+ /* Nonzero if chip supports the ARMv8 CRC instructions.  */
+ extern int arm_arch_crc;
+ 
++/* Nonzero if chip supports the ARMv8-M Security Extensions.  */
++extern int arm_arch_cmse;
++
+ #ifndef TARGET_DEFAULT
+ #define TARGET_DEFAULT  (MASK_APCS_FRAME)
+ #endif
+@@ -1191,7 +1220,7 @@ enum reg_class
+    the data layout happens to be consistent for big-endian, so we explicitly allow
+    that case.  */
+ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)		\
+-  (TARGET_VFP && TARGET_BIG_END					\
++  (TARGET_BIG_END						\
+    && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8)	\
+    && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD			\
+        || GET_MODE_SIZE (TO) > UNITS_PER_WORD)			\
+@@ -1242,8 +1271,7 @@ enum reg_class
+    NO_REGS is returned.  */
+ #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)		\
+   /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
+-  ((TARGET_VFP && TARGET_HARD_FLOAT				\
+-    && IS_VFP_CLASS (CLASS))					\
++  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS))			\
+    ? coproc_secondary_reload_class (MODE, X, FALSE)		\
+    : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS)			\
+    ? coproc_secondary_reload_class (MODE, X, TRUE)		\
+@@ -1255,8 +1283,7 @@ enum reg_class
+ /* If we need to load shorts byte-at-a-time, then we need a scratch.  */
+ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)		\
+   /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
+-  ((TARGET_VFP && TARGET_HARD_FLOAT				\
+-    && IS_VFP_CLASS (CLASS))					\
++  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS))			\
+     ? coproc_secondary_reload_class (MODE, X, FALSE) :		\
+     (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ?			\
+     coproc_secondary_reload_class (MODE, X, TRUE) :		\
+@@ -1363,6 +1390,7 @@ enum reg_class
+ #define ARM_FT_VOLATILE		(1 << 4) /* Does not return.  */
+ #define ARM_FT_NESTED		(1 << 5) /* Embedded inside another func.  */
+ #define ARM_FT_STACKALIGN	(1 << 6) /* Called with misaligned stack.  */
++#define ARM_FT_CMSE_ENTRY	(1 << 7) /* ARMv8-M non-secure entry function.  */
+ 
+ /* Some macros to test these flags.  */
+ #define ARM_FUNC_TYPE(t)	(t & ARM_FT_TYPE_MASK)
+@@ -1371,6 +1399,7 @@ enum reg_class
+ #define IS_NAKED(t)        	(t & ARM_FT_NAKED)
+ #define IS_NESTED(t)       	(t & ARM_FT_NESTED)
+ #define IS_STACKALIGN(t)       	(t & ARM_FT_STACKALIGN)
++#define IS_CMSE_ENTRY(t)	(t & ARM_FT_CMSE_ENTRY)
+ 
+ 
+ /* Structure used to hold the function stack frame layout.  Offsets are
+@@ -1516,7 +1545,7 @@ typedef struct
+    On the ARM, r0-r3 are used to pass args.  */
+ #define FUNCTION_ARG_REGNO_P(REGNO)					\
+    (IN_RANGE ((REGNO), 0, 3)						\
+-    || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT		\
++    || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT				\
+ 	&& IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15))	\
+     || (TARGET_IWMMXT_ABI						\
+ 	&& IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
+@@ -2187,13 +2216,9 @@ extern int making_const_table;
+ #define TARGET_ARM_ARCH	\
+   (arm_base_arch)	\
+ 
+-#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
+-#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
+-
+ /* The highest Thumb instruction set version supported by the chip.  */
+-#define TARGET_ARM_ARCH_ISA_THUMB 		\
+-  (arm_arch_thumb2 ? 2				\
+-	           : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
++#define TARGET_ARM_ARCH_ISA_THUMB		\
++  (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0))
+ 
+ /* Expands to an upper-case char of the target's architectural
+    profile.  */
+@@ -2245,13 +2270,18 @@ extern const char *arm_rewrite_mcpu (int argc, const char **argv);
+    "   :%{march=*:-march=%*}}"					\
+    BIG_LITTLE_SPEC
+ 
++extern const char *arm_target_thumb_only (int argc, const char **argv);
++#define TARGET_MODE_SPEC_FUNCTIONS					\
++  { "target_mode_check", arm_target_thumb_only },
++
+ /* -mcpu=native handling only makes sense with compiler running on
+    an ARM chip.  */
+ #if defined(__arm__)
+ extern const char *host_detect_local_cpu (int argc, const char **argv);
+ # define EXTRA_SPEC_FUNCTIONS						\
+   { "local_cpu_detect", host_detect_local_cpu },			\
+-  BIG_LITTLE_CPU_SPEC_FUNCTIONS
++  BIG_LITTLE_CPU_SPEC_FUNCTIONS						\
++  TARGET_MODE_SPEC_FUNCTIONS
+ 
+ # define MCPU_MTUNE_NATIVE_SPECS					\
+    " %{march=native:%<march=native %:local_cpu_detect(arch)}"		\
+@@ -2259,10 +2289,21 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
+    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
+ #else
+ # define MCPU_MTUNE_NATIVE_SPECS ""
+-# define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
++# define EXTRA_SPEC_FUNCTIONS						\
++	BIG_LITTLE_CPU_SPEC_FUNCTIONS					\
++	TARGET_MODE_SPEC_FUNCTIONS
+ #endif
+ 
+-#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
++/* Automatically add -mthumb for Thumb-only targets if mode isn't specified
++   via the configuration option --with-mode or via the command line. The
++   function target_mode_check is called to do the check with either:
++   - an array of -march values if any is given;
++   - an array of -mcpu values if any is given;
++   - an empty array.  */
++#define TARGET_MODE_SPECS						\
++  " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:%*;mcpu=*:%*;:})}}"
++
++#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS TARGET_MODE_SPECS
+ #define TARGET_SUPPORTS_WIDE_INT 1
+ 
+ /* For switching between functions with different target attributes.  */
+--- a/src/gcc/config/arm/arm.md
++++ b/src/gcc/config/arm/arm.md
+@@ -118,10 +118,10 @@
+ ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
+ ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode.  "v6"
+ ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
+-; arm_arch6.  "v6t2" for Thumb-2 with arm_arch6.  This attribute is
+-; used to compute attribute "enabled", use type "any" to enable an
+-; alternative in all cases.
+-(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3"
++; arm_arch6.  "v6t2" for Thumb-2 with arm_arch6 and "v8mb" for ARMv8-M
++; Baseline.  This attribute is used to compute attribute "enabled",
++; use type "any" to enable an alternative in all cases.
++(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon"
+   (const_string "any"))
+ 
+ (define_attr "arch_enabled" "no,yes"
+@@ -160,6 +160,10 @@
+ 	      (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2"))
+ 	 (const_string "yes")
+ 
++	 (and (eq_attr "arch" "v8mb")
++	      (match_test "TARGET_THUMB1 && arm_arch8"))
++	 (const_string "yes")
++
+ 	 (and (eq_attr "arch" "avoid_neon_for_64bits")
+ 	      (match_test "TARGET_NEON")
+ 	      (not (match_test "TARGET_PREFER_NEON_64BITS")))
+@@ -177,6 +181,10 @@
+ 	 (and (eq_attr "arch" "armv6_or_vfpv3")
+ 	      (match_test "arm_arch6 || TARGET_VFP3"))
+ 	 (const_string "yes")
++
++	 (and (eq_attr "arch" "neon")
++	      (match_test "TARGET_NEON"))
++	 (const_string "yes")
+ 	]
+ 
+ 	(const_string "no")))
+@@ -539,6 +547,32 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++(define_expand "addv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_add<mode>3_compareV (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
++
++  DONE;
++})
++
++(define_expand "uaddv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_add<mode>3_compareC (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]);
++
++  DONE;
++})
++
+ (define_expand "addsi3"
+   [(set (match_operand:SI          0 "s_register_operand" "")
+ 	(plus:SI (match_operand:SI 1 "s_register_operand" "")
+@@ -617,6 +651,165 @@
+  ]
+ )
+ 
++(define_insn_and_split "adddi3_compareV"
++  [(set (reg:CC_V CC_REGNUM)
++	(ne:CC_V
++	  (plus:TI
++	    (sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
++	    (sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
++	  (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
++   (set (match_operand:DI 0 "register_operand" "=&r")
++	(plus:DI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC_C CC_REGNUM)
++		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
++				 (match_dup 1)))
++	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
++   (parallel [(set (reg:CC_V CC_REGNUM)
++		   (ne:CC_V
++		    (plus:DI (plus:DI
++			      (sign_extend:DI (match_dup 4))
++			      (sign_extend:DI (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++		    (plus:DI (sign_extend:DI
++			      (plus:SI (match_dup 4) (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++	     (set (match_dup 3) (plus:SI (plus:SI
++					  (match_dup 4) (match_dup 5))
++					 (ltu:SI (reg:CC_C CC_REGNUM)
++						 (const_int 0))))])]
++  "
++  {
++    operands[3] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[4] = gen_highpart (SImode, operands[1]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++    operands[5] = gen_highpart (SImode, operands[2]);
++    operands[2] = gen_lowpart (SImode, operands[2]);
++  }"
++ [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
++(define_insn "addsi3_compareV"
++  [(set (reg:CC_V CC_REGNUM)
++	(ne:CC_V
++	  (plus:DI
++	    (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	    (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	  (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(plus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "adds%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_sreg")]
++)
++
++(define_insn "*addsi3_compareV_upper"
++  [(set (reg:CC_V CC_REGNUM)
++	(ne:CC_V
++	  (plus:DI
++	   (plus:DI
++	    (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	    (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++	  (plus:DI (sign_extend:DI
++		    (plus:SI (match_dup 1) (match_dup 2)))
++		   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(plus:SI
++	 (plus:SI (match_dup 1) (match_dup 2))
++	 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  "TARGET_32BIT"
++  "adcs%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "adcs_reg")]
++)
++
++(define_insn_and_split "adddi3_compareC"
++  [(set (reg:CC_C CC_REGNUM)
++	(ne:CC_C
++	  (plus:TI
++	    (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
++	    (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
++	  (zero_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
++   (set (match_operand:DI 0 "register_operand" "=&r")
++	(plus:DI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC_C CC_REGNUM)
++		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
++				 (match_dup 1)))
++	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
++   (parallel [(set (reg:CC_C CC_REGNUM)
++		   (ne:CC_C
++		    (plus:DI (plus:DI
++			      (zero_extend:DI (match_dup 4))
++			      (zero_extend:DI (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++		    (plus:DI (zero_extend:DI
++			      (plus:SI (match_dup 4) (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++	     (set (match_dup 3) (plus:SI
++				 (plus:SI (match_dup 4) (match_dup 5))
++				 (ltu:SI (reg:CC_C CC_REGNUM)
++					 (const_int 0))))])]
++  "
++  {
++    operands[3] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[4] = gen_highpart (SImode, operands[1]);
++    operands[5] = gen_highpart (SImode, operands[2]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++    operands[2] = gen_lowpart (SImode, operands[2]);
++  }"
++ [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
++(define_insn "*addsi3_compareC_upper"
++  [(set (reg:CC_C CC_REGNUM)
++	(ne:CC_C
++	  (plus:DI
++	   (plus:DI
++	    (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	    (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++	  (plus:DI (zero_extend:DI
++		    (plus:SI (match_dup 1) (match_dup 2)))
++		   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(plus:SI
++	 (plus:SI (match_dup 1) (match_dup 2))
++	 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  "TARGET_32BIT"
++  "adcs%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "adcs_reg")]
++)
++
++(define_insn "addsi3_compareC"
++   [(set (reg:CC_C CC_REGNUM)
++	 (ne:CC_C
++	  (plus:DI
++	   (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	   (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	  (zero_extend:DI
++	   (plus:SI (match_dup 1) (match_dup 2)))))
++    (set (match_operand:SI 0 "register_operand" "=r")
++	 (plus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "adds%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_sreg")]
++)
++
+ (define_insn "addsi3_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+@@ -866,20 +1059,90 @@
+     (set_attr "type" "adcs_reg")]
+ )
+ 
++(define_expand "subv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
++
++  DONE;
++})
++
++(define_expand "usubv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
++
++  DONE;
++})
++
++(define_insn_and_split "subdi3_compare1"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC
++	  (match_operand:DI 1 "register_operand" "r")
++	  (match_operand:DI 2 "register_operand" "r")))
++   (set (match_operand:DI 0 "register_operand" "=&r")
++	(minus:DI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (match_dup 1) (match_dup 2)))
++	      (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
++   (parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (match_dup 4) (match_dup 5)))
++	     (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
++			       (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])]
++  {
++    operands[3] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[4] = gen_highpart (SImode, operands[1]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++    operands[5] = gen_highpart (SImode, operands[2]);
++    operands[2] = gen_lowpart (SImode, operands[2]);
++   }
++  [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
++(define_insn "subsi3_compare1"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC
++	  (match_operand:SI 1 "register_operand" "r")
++	  (match_operand:SI 2 "register_operand" "r")))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(minus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "subs%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_sreg")]
++)
++
+ (define_insn "*subsi3_carryin"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+-        (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I")
+-                            (match_operand:SI 2 "s_register_operand" "r,r"))
+-                  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
++	(minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I,Pz")
++			    (match_operand:SI 2 "s_register_operand" "r,r,r"))
++		  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+   "TARGET_32BIT"
+   "@
+    sbc%?\\t%0, %1, %2
+-   rsc%?\\t%0, %2, %1"
++   rsc%?\\t%0, %2, %1
++   sbc%?\\t%0, %2, %2, lsl #1"
+   [(set_attr "conds" "use")
+-   (set_attr "arch" "*,a")
++   (set_attr "arch" "*,a,t2")
+    (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+-   (set_attr "type" "adc_reg,adc_imm")]
++   (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
+ )
+ 
+ (define_insn "*subsi3_carryin_const"
+@@ -1895,7 +2158,7 @@
+   [(set (match_operand:SF 0 "s_register_operand" "")
+ 	(div:SF (match_operand:SF 1 "s_register_operand" "")
+ 		(match_operand:SF 2 "s_register_operand" "")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "")
+ 
+ (define_expand "divdf3"
+@@ -2137,13 +2400,13 @@
+ 
+           for (i = 9; i <= 31; i++)
+ 	    {
+-	      if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (operands[2]))
++	      if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (operands[2]))
+ 	        {
+ 	          emit_insn (gen_extzv (operands[0], operands[1], GEN_INT (i),
+ 			 	        const0_rtx));
+ 	          DONE;
+ 	        }
+-	      else if ((((HOST_WIDE_INT) 1) << i) - 1
++	      else if ((HOST_WIDE_INT_1 << i) - 1
+ 		       == ~INTVAL (operands[2]))
+ 	        {
+ 	          rtx shift = GEN_INT (i);
+@@ -2442,7 +2705,7 @@
+   {
+     int start_bit = INTVAL (operands[2]);
+     int width = INTVAL (operands[1]);
+-    HOST_WIDE_INT mask = (((HOST_WIDE_INT)1) << width) - 1;
++    HOST_WIDE_INT mask = (HOST_WIDE_INT_1 << width) - 1;
+     rtx target, subtarget;
+ 
+     if (arm_arch_thumb2)
+@@ -3050,7 +3313,14 @@
+ 	(xor:DI (match_operand:DI 1 "s_register_operand" "")
+ 		(match_operand:DI 2 "arm_xordi_operand" "")))]
+   "TARGET_32BIT"
+-  ""
++  {
++    /* The iWMMXt pattern for xordi3 accepts only register operands but we want
++       to reuse this expander for all TARGET_32BIT targets so just force the
++       constants into a register.  Unlike for the anddi3 and iordi3 there are
++       no NEON instructions that take an immediate.  */
++    if (TARGET_IWMMXT && !REG_P (operands[2]))
++      operands[2] = force_reg (DImode, operands[2]);
++  }
+ )
+ 
+ (define_insn_and_split "*xordi3_insn"
+@@ -3744,8 +4014,7 @@
+     {
+       rtx scratch1, scratch2;
+ 
+-      if (CONST_INT_P (operands[2])
+-	  && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
++      if (operands[2] == CONST1_RTX (SImode))
+         {
+           emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
+           DONE;
+@@ -3790,7 +4059,7 @@
+   "TARGET_EITHER"
+   "
+   if (CONST_INT_P (operands[2])
+-      && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++      && (UINTVAL (operands[2])) > 31)
+     {
+       emit_insn (gen_movsi (operands[0], const0_rtx));
+       DONE;
+@@ -3818,8 +4087,7 @@
+     {
+       rtx scratch1, scratch2;
+ 
+-      if (CONST_INT_P (operands[2])
+-	  && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
++      if (operands[2] == CONST1_RTX (SImode))
+         {
+           emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1]));
+           DONE;
+@@ -3864,7 +4132,7 @@
+   "TARGET_EITHER"
+   "
+   if (CONST_INT_P (operands[2])
+-      && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++      && UINTVAL (operands[2]) > 31)
+     operands[2] = GEN_INT (31);
+   "
+ )
+@@ -3889,8 +4157,7 @@
+     {
+       rtx scratch1, scratch2;
+ 
+-      if (CONST_INT_P (operands[2])
+-	  && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
++      if (operands[2] == CONST1_RTX (SImode))
+         {
+           emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1]));
+           DONE;
+@@ -3935,7 +4202,7 @@
+   "TARGET_EITHER"
+   "
+   if (CONST_INT_P (operands[2])
+-      && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++      && (UINTVAL (operands[2])) > 31)
+     {
+       emit_insn (gen_movsi (operands[0], const0_rtx));
+       DONE;
+@@ -3969,7 +4236,7 @@
+   if (TARGET_32BIT)
+     {
+       if (CONST_INT_P (operands[2])
+-          && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++          && UINTVAL (operands[2]) > 31)
+         operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
+     }
+   else /* TARGET_THUMB1 */
+@@ -4300,9 +4567,11 @@
+ (define_insn "*extv_reg"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
+-                         (match_operand:SI 2 "const_int_M_operand" "M")
+-                         (match_operand:SI 3 "const_int_M_operand" "M")))]
+-  "arm_arch_thumb2"
++			  (match_operand:SI 2 "const_int_operand" "n")
++			  (match_operand:SI 3 "const_int_operand" "n")))]
++  "arm_arch_thumb2
++   && IN_RANGE (INTVAL (operands[3]), 0, 31)
++   && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
+   "sbfx%?\t%0, %1, %3, %2"
+   [(set_attr "length" "4")
+    (set_attr "predicable" "yes")
+@@ -4313,9 +4582,11 @@
+ (define_insn "extzv_t2"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(zero_extract:SI (match_operand:SI 1 "s_register_operand" "r")
+-                         (match_operand:SI 2 "const_int_M_operand" "M")
+-                         (match_operand:SI 3 "const_int_M_operand" "M")))]
+-  "arm_arch_thumb2"
++			  (match_operand:SI 2 "const_int_operand" "n")
++			  (match_operand:SI 3 "const_int_operand" "n")))]
++  "arm_arch_thumb2
++   && IN_RANGE (INTVAL (operands[3]), 0, 31)
++   && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
+   "ubfx%?\t%0, %1, %3, %2"
+   [(set_attr "length" "4")
+    (set_attr "predicable" "yes")
+@@ -4326,23 +4597,29 @@
+ 
+ ;; Division instructions
+ (define_insn "divsi3"
+-  [(set (match_operand:SI	  0 "s_register_operand" "=r")
+-	(div:SI (match_operand:SI 1 "s_register_operand"  "r")
+-		(match_operand:SI 2 "s_register_operand"  "r")))]
++  [(set (match_operand:SI	  0 "s_register_operand" "=r,r")
++	(div:SI (match_operand:SI 1 "s_register_operand"  "r,r")
++		(match_operand:SI 2 "s_register_operand"  "r,r")))]
+   "TARGET_IDIV"
+-  "sdiv%?\t%0, %1, %2"
+-  [(set_attr "predicable" "yes")
++  "@
++   sdiv%?\t%0, %1, %2
++   sdiv\t%0, %1, %2"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+    (set_attr "type" "sdiv")]
+ )
+ 
+ (define_insn "udivsi3"
+-  [(set (match_operand:SI	   0 "s_register_operand" "=r")
+-	(udiv:SI (match_operand:SI 1 "s_register_operand"  "r")
+-		 (match_operand:SI 2 "s_register_operand"  "r")))]
++  [(set (match_operand:SI	   0 "s_register_operand" "=r,r")
++	(udiv:SI (match_operand:SI 1 "s_register_operand"  "r,r")
++		 (match_operand:SI 2 "s_register_operand"  "r,r")))]
+   "TARGET_IDIV"
+-  "udiv%?\t%0, %1, %2"
+-  [(set_attr "predicable" "yes")
++  "@
++   udiv%?\t%0, %1, %2
++   udiv\t%0, %1, %2"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+    (set_attr "type" "udiv")]
+ )
+@@ -4350,6 +4627,63 @@
+ 
+ ;; Unary arithmetic insns
+ 
++(define_expand "negvsi3"
++  [(match_operand:SI 0 "register_operand")
++   (match_operand:SI 1 "register_operand")
++   (match_operand 2 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
++
++  DONE;
++})
++
++(define_expand "negvdi3"
++  [(match_operand:DI 0 "register_operand")
++   (match_operand:DI 1 "register_operand")
++   (match_operand 2 "")]
++  "TARGET_ARM"
++{
++  emit_insn (gen_negdi2_compare (operands[0], operands[1]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
++
++  DONE;
++})
++
++
++(define_insn_and_split "negdi2_compare"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC
++	  (const_int 0)
++	  (match_operand:DI 1 "register_operand" "0,r")))
++   (set (match_operand:DI 0 "register_operand" "=r,&r")
++	(minus:DI (const_int 0) (match_dup 1)))]
++  "TARGET_ARM"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (const_int 0) (match_dup 1)))
++	      (set (match_dup 0) (minus:SI (const_int 0)
++					   (match_dup 1)))])
++   (parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (const_int 0) (match_dup 3)))
++	     (set (match_dup 2)
++		  (minus:SI
++		   (minus:SI (const_int 0) (match_dup 3))
++		   (ltu:SI (reg:CC_C CC_REGNUM)
++			   (const_int 0))))])]
++  {
++    operands[2] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[3] = gen_highpart (SImode, operands[1]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++  }
++  [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
+ (define_expand "negdi2"
+  [(parallel
+    [(set (match_operand:DI 0 "s_register_operand" "")
+@@ -4367,12 +4701,13 @@
+ 
+ ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
+ ;; The first alternative allows the common case of a *full* overlap.
+-(define_insn_and_split "*arm_negdi2"
++(define_insn_and_split "*negdi2_insn"
+   [(set (match_operand:DI         0 "s_register_operand" "=r,&r")
+ 	(neg:DI (match_operand:DI 1 "s_register_operand"  "0,r")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM"
+-  "#"   ; "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
++  "TARGET_32BIT"
++  "#"	; rsbs %Q0, %Q1, #0; rsc %R0, %R1, #0	       (ARM)
++	; negs %Q0, %Q1    ; sbc %R0, %R1, %R1, lsl #1 (Thumb-2)
+   "&& reload_completed"
+   [(parallel [(set (reg:CC CC_REGNUM)
+ 		   (compare:CC (const_int 0) (match_dup 1)))
+@@ -4390,6 +4725,20 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++(define_insn "*negsi2_carryin_compare"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC (const_int 0)
++		    (match_operand:SI 1 "s_register_operand" "r")))
++   (set (match_operand:SI 0 "s_register_operand" "=r")
++	(minus:SI (minus:SI (const_int 0)
++			    (match_dup 1))
++		  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  "TARGET_ARM"
++  "rscs\\t%0, %1, #0"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_imm")]
++)
++
+ (define_expand "negsi2"
+   [(set (match_operand:SI         0 "s_register_operand" "")
+ 	(neg:SI (match_operand:SI 1 "s_register_operand" "")))]
+@@ -4412,7 +4761,7 @@
+ (define_expand "negsf2"
+   [(set (match_operand:SF         0 "s_register_operand" "")
+ 	(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   ""
+ )
+ 
+@@ -4685,7 +5034,7 @@
+ (define_expand "sqrtsf2"
+   [(set (match_operand:SF 0 "s_register_operand" "")
+ 	(sqrt:SF (match_operand:SF 1 "s_register_operand" "")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "")
+ 
+ (define_expand "sqrtdf2"
+@@ -4854,7 +5203,7 @@
+   ""
+ )
+ 
+-/* DFmode -> HFmode conversions have to go through SFmode.  */
++;; DFmode to HFmode conversions have to go through SFmode.
+ (define_expand "truncdfhf2"
+   [(set (match_operand:HF  0 "general_operand" "")
+ 	(float_truncate:HF
+@@ -5117,7 +5466,7 @@
+ 		     (match_operator 5 "subreg_lowpart_operator"
+ 		      [(match_operand:SI 4 "s_register_operand" "")]))))]
+   "TARGET_32BIT
+-   && ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
++   && (UINTVAL (operands[3])
+        == (GET_MODE_MASK (GET_MODE (operands[5]))
+            & (GET_MODE_MASK (GET_MODE (operands[5]))
+ 	      << (INTVAL (operands[2])))))"
+@@ -5361,7 +5710,7 @@
+   ""
+ )
+ 
+-/* HFmode -> DFmode conversions have to go through SFmode.  */
++;; HFmode -> DFmode conversions have to go through SFmode.
+ (define_expand "extendhfdf2"
+   [(set (match_operand:DF                  0 "general_operand" "")
+ 	(float_extend:DF (match_operand:HF 1 "general_operand"  "")))]
+@@ -5490,7 +5839,7 @@
+   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, q, m")
+ 	(match_operand:DI 1 "di_operand"              "rDa,Db,Dc,mi,q"))]
+   "TARGET_32BIT
+-   && !(TARGET_HARD_FLOAT && TARGET_VFP)
++   && !(TARGET_HARD_FLOAT)
+    && !TARGET_IWMMXT
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))"
+@@ -5699,12 +6048,15 @@
+ ;; LO_SUM adds in the high bits.  Fortunately these are opaque operations
+ ;; so this does not matter.
+ (define_insn "*arm_movt"
+-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+-	(lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+-		   (match_operand:SI 2 "general_operand"      "i")))]
+-  "arm_arch_thumb2 && arm_valid_symbolic_address_p (operands[2])"
+-  "movt%?\t%0, #:upper16:%c2"
+-  [(set_attr "predicable" "yes")
++  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r")
++	(lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
++		   (match_operand:SI 2 "general_operand"      "i,i")))]
++  "TARGET_HAVE_MOVT && arm_valid_symbolic_address_p (operands[2])"
++  "@
++   movt%?\t%0, #:upper16:%c2
++   movt\t%0, #:upper16:%c2"
++  [(set_attr "arch"  "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+    (set_attr "length" "4")
+    (set_attr "type" "alu_sreg")]
+@@ -5713,8 +6065,7 @@
+ (define_insn "*arm_movsi_insn"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
+ 	(match_operand:SI 1 "general_operand"      "rk, I,K,j,mi,rk"))]
+-  "TARGET_ARM && ! TARGET_IWMMXT
+-   && !(TARGET_HARD_FLOAT && TARGET_VFP)
++  "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], SImode)
+        || register_operand (operands[1], SImode))"
+   "@
+@@ -5726,6 +6077,7 @@
+    str%?\\t%1, %0"
+   [(set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_imm,load1,store1")
+    (set_attr "predicable" "yes")
++   (set_attr "arch" "*,*,*,v6t2,*,*")
+    (set_attr "pool_range" "*,*,*,*,4096,*")
+    (set_attr "neg_pool_range" "*,*,*,*,4084,*")]
+ )
+@@ -5762,7 +6114,8 @@
+   [(set (match_operand:SI 0 "arm_general_register_operand" "")
+ 	(const:SI (plus:SI (match_operand:SI 1 "general_operand" "")
+ 			   (match_operand:SI 2 "const_int_operand" ""))))]
+-  "TARGET_THUMB2
++  "TARGET_THUMB
++   && TARGET_HAVE_MOVT
+    && arm_disable_literal_pool
+    && reload_completed
+    && GET_CODE (operands[1]) == SYMBOL_REF"
+@@ -5793,8 +6146,7 @@
+ (define_split
+   [(set (match_operand:SI 0 "arm_general_register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))]
+-  "TARGET_32BIT
+-   && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
++  "TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
+    && !flag_pic && !target_word_relocations
+    && !arm_tls_referenced_p (operands[1])"
+   [(clobber (const_int 0))]
+@@ -6362,7 +6714,7 @@
+   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
+ 	(match_operand:HI 1 "general_operand"      "rIk,K,n,r,mi"))]
+   "TARGET_ARM
+-   && arm_arch4
++   && arm_arch4 && !TARGET_HARD_FLOAT
+    && (register_operand (operands[0], HImode)
+        || register_operand (operands[1], HImode))"
+   "@
+@@ -6388,7 +6740,7 @@
+ (define_insn "*movhi_bytes"
+   [(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
+ 	(match_operand:HI 1 "arm_rhs_operand"  "I,rk,K"))]
+-  "TARGET_ARM"
++  "TARGET_ARM && !TARGET_HARD_FLOAT"
+   "@
+    mov%?\\t%0, %1\\t%@ movhi
+    mov%?\\t%0, %1\\t%@ movhi
+@@ -6396,7 +6748,7 @@
+   [(set_attr "predicable" "yes")
+    (set_attr "type" "mov_imm,mov_reg,mvn_imm")]
+ )
+-	
++
+ ;; We use a DImode scratch because we may occasionally need an additional
+ ;; temporary if the address isn't offsettable -- push_reload doesn't seem
+ ;; to take any notice of the "o" constraints on reload_memory_operand operand.
+@@ -6518,7 +6870,7 @@
+    strb%?\\t%1, %0"
+   [(set_attr "type" "mov_reg,mov_reg,mov_imm,mov_imm,mvn_imm,load1,store1,load1,store1")
+    (set_attr "predicable" "yes")
+-   (set_attr "predicable_short_it" "yes,yes,yes,no,no,no,no,no,no")
++   (set_attr "predicable_short_it" "yes,yes,no,yes,no,no,no,no,no")
+    (set_attr "arch" "t2,any,any,t2,any,t2,t2,any,any")
+    (set_attr "length" "2,4,4,2,4,2,2,4,4")]
+ )
+@@ -6548,7 +6900,7 @@
+ (define_insn "*arm32_movhf"
+   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
+ 	(match_operand:HF 1 "general_operand"	   " m,r,r,F"))]
+-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16)
++  "TARGET_32BIT && !TARGET_HARD_FLOAT
+    && (	  s_register_operand (operands[0], HFmode)
+        || s_register_operand (operands[1], HFmode))"
+   "*
+@@ -6892,7 +7244,7 @@
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:SF 1 "s_register_operand" "")
+-	        (match_operand:SF 2 "arm_float_compare_operand" "")])
++	        (match_operand:SF 2 "vfp_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+ 	      (pc)))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -6904,7 +7256,7 @@
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:DF 1 "s_register_operand" "")
+-	        (match_operand:DF 2 "arm_float_compare_operand" "")])
++	        (match_operand:DF 2 "vfp_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+ 	      (pc)))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+@@ -7366,11 +7718,29 @@
+   DONE;
+ }")
+ 
++(define_expand "cstorehf4"
++  [(set (match_operand:SI 0 "s_register_operand")
++	(match_operator:SI 1 "expandable_comparison_operator"
++	 [(match_operand:HF 2 "s_register_operand")
++	  (match_operand:HF 3 "vfp_compare_operand")]))]
++  "TARGET_VFP_FP16INST"
++  {
++    if (!arm_validize_comparison (&operands[1],
++				  &operands[2],
++				  &operands[3]))
++       FAIL;
++
++    emit_insn (gen_cstore_cc (operands[0], operands[1],
++			      operands[2], operands[3]));
++    DONE;
++  }
++)
++
+ (define_expand "cstoresf4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:SF 2 "s_register_operand" "")
+-	  (match_operand:SF 3 "arm_float_compare_operand" "")]))]
++	  (match_operand:SF 3 "vfp_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "emit_insn (gen_cstore_cc (operands[0], operands[1],
+ 			     operands[2], operands[3])); DONE;"
+@@ -7380,7 +7750,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:DF 2 "s_register_operand" "")
+-	  (match_operand:DF 3 "arm_float_compare_operand" "")]))]
++	  (match_operand:DF 3 "vfp_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+   "emit_insn (gen_cstore_cc (operands[0], operands[1],
+ 			     operands[2], operands[3])); DONE;"
+@@ -7418,9 +7788,31 @@
+     rtx ccreg;
+ 
+     if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0), 
+-       				  &XEXP (operands[1], 1)))
++				  &XEXP (operands[1], 1)))
+       FAIL;
+-    
++
++    code = GET_CODE (operands[1]);
++    ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
++				 XEXP (operands[1], 1), NULL_RTX);
++    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
++  }"
++)
++
++(define_expand "movhfcc"
++  [(set (match_operand:HF 0 "s_register_operand")
++	(if_then_else:HF (match_operand 1 "arm_cond_move_operator")
++			 (match_operand:HF 2 "s_register_operand")
++			 (match_operand:HF 3 "s_register_operand")))]
++  "TARGET_VFP_FP16INST"
++  "
++  {
++    enum rtx_code code = GET_CODE (operands[1]);
++    rtx ccreg;
++
++    if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
++				  &XEXP (operands[1], 1)))
++      FAIL;
++
+     code = GET_CODE (operands[1]);
+     ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
+ 				 XEXP (operands[1], 1), NULL_RTX);
+@@ -7439,7 +7831,7 @@
+     enum rtx_code code = GET_CODE (operands[1]);
+     rtx ccreg;
+ 
+-    if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0), 
++    if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
+        				  &XEXP (operands[1], 1)))
+        FAIL;
+ 
+@@ -7504,6 +7896,37 @@
+    (set_attr "type" "fcsel")]
+ )
+ 
++(define_insn "*cmovhf"
++    [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(if_then_else:HF (match_operator 1 "arm_vsel_comparison_operator"
++			 [(match_operand 2 "cc_register" "") (const_int 0)])
++			  (match_operand:HF 3 "s_register_operand" "t")
++			  (match_operand:HF 4 "s_register_operand" "t")))]
++  "TARGET_VFP_FP16INST"
++  "*
++  {
++    enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);
++    switch (code)
++      {
++      case ARM_GE:
++      case ARM_GT:
++      case ARM_EQ:
++      case ARM_VS:
++	return \"vsel%d1.f16\\t%0, %3, %4\";
++      case ARM_LT:
++      case ARM_LE:
++      case ARM_NE:
++      case ARM_VC:
++	return \"vsel%D1.f16\\t%0, %4, %3\";
++      default:
++	gcc_unreachable ();
++      }
++    return \"\";
++  }"
++  [(set_attr "conds" "use")
++   (set_attr "type" "fcsel")]
++)
++
+ (define_insn_and_split "*movsicc_insn"
+   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
+ 	(if_then_else:SI
+@@ -7627,6 +8050,7 @@
+   "
+   {
+     rtx callee, pat;
++    tree addr = MEM_EXPR (operands[0]);
+     
+     /* In an untyped call, we can get NULL for operand 2.  */
+     if (operands[2] == NULL_RTX)
+@@ -7641,8 +8065,17 @@
+ 	: !REG_P (callee))
+       XEXP (operands[0], 0) = force_reg (Pmode, callee);
+ 
+-    pat = gen_call_internal (operands[0], operands[1], operands[2]);
+-    arm_emit_call_insn (pat, XEXP (operands[0], 0), false);
++    if (detect_cmse_nonsecure_call (addr))
++      {
++	pat = gen_nonsecure_call_internal (operands[0], operands[1],
++					   operands[2]);
++	emit_call_insn (pat);
++      }
++    else
++      {
++	pat = gen_call_internal (operands[0], operands[1], operands[2]);
++	arm_emit_call_insn (pat, XEXP (operands[0], 0), false);
++      }
+     DONE;
+   }"
+ )
+@@ -7653,6 +8086,24 @@
+ 	      (use (match_operand 2 "" ""))
+ 	      (clobber (reg:SI LR_REGNUM))])])
+ 
++(define_expand "nonsecure_call_internal"
++  [(parallel [(call (unspec:SI [(match_operand 0 "memory_operand" "")]
++			       UNSPEC_NONSECURE_MEM)
++		    (match_operand 1 "general_operand" ""))
++	      (use (match_operand 2 "" ""))
++	      (clobber (reg:SI LR_REGNUM))
++	      (clobber (reg:SI 4))])]
++  "use_cmse"
++  "
++  {
++    rtx tmp;
++    tmp = copy_to_suggested_reg (XEXP (operands[0], 0),
++				 gen_rtx_REG (SImode, 4),
++				 SImode);
++
++    operands[0] = replace_equiv_address (operands[0], tmp);
++  }")
++
+ (define_insn "*call_reg_armv5"
+   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
+          (match_operand 1 "" ""))
+@@ -7688,6 +8139,7 @@
+   "
+   {
+     rtx pat, callee;
++    tree addr = MEM_EXPR (operands[1]);
+     
+     /* In an untyped call, we can get NULL for operand 2.  */
+     if (operands[3] == 0)
+@@ -7702,9 +8154,18 @@
+ 	: !REG_P (callee))
+       XEXP (operands[1], 0) = force_reg (Pmode, callee);
+ 
+-    pat = gen_call_value_internal (operands[0], operands[1],
+-				   operands[2], operands[3]);
+-    arm_emit_call_insn (pat, XEXP (operands[1], 0), false);
++    if (detect_cmse_nonsecure_call (addr))
++      {
++	pat = gen_nonsecure_call_value_internal (operands[0], operands[1],
++						 operands[2], operands[3]);
++	emit_call_insn (pat);
++      }
++    else
++      {
++	pat = gen_call_value_internal (operands[0], operands[1],
++				       operands[2], operands[3]);
++	arm_emit_call_insn (pat, XEXP (operands[1], 0), false);
++      }
+     DONE;
+   }"
+ )
+@@ -7716,6 +8177,25 @@
+ 	      (use (match_operand 3 "" ""))
+ 	      (clobber (reg:SI LR_REGNUM))])])
+ 
++(define_expand "nonsecure_call_value_internal"
++  [(parallel [(set (match_operand       0 "" "")
++		   (call (unspec:SI [(match_operand 1 "memory_operand" "")]
++				    UNSPEC_NONSECURE_MEM)
++			 (match_operand 2 "general_operand" "")))
++	      (use (match_operand 3 "" ""))
++	      (clobber (reg:SI LR_REGNUM))
++	      (clobber (reg:SI 4))])]
++  "use_cmse"
++  "
++  {
++    rtx tmp;
++    tmp = copy_to_suggested_reg (XEXP (operands[1], 0),
++				 gen_rtx_REG (SImode, 4),
++				 SImode);
++
++    operands[1] = replace_equiv_address (operands[1], tmp);
++  }")
++
+ (define_insn "*call_value_reg_armv5"
+   [(set (match_operand 0 "" "")
+         (call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+@@ -8153,8 +8633,8 @@
+ )
+ 
+ (define_insn "probe_stack"
+-  [(set (match_operand 0 "memory_operand" "=m")
+-        (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
++  [(set (match_operand:SI 0 "memory_operand" "=m")
++        (unspec:SI [(const_int 0)] UNSPEC_PROBE_STACK))]
+   "TARGET_32BIT"
+   "str%?\\tr0, %0"
+   [(set_attr "type" "store1")
+@@ -10221,8 +10701,8 @@
+ 	 (match_operand 1 "const_int_operand" "")))
+    (clobber (match_scratch:SI 2 ""))]
+   "TARGET_ARM
+-   && (((unsigned HOST_WIDE_INT) INTVAL (operands[1]))
+-       == (((unsigned HOST_WIDE_INT) INTVAL (operands[1])) >> 24) << 24)"
++   && ((UINTVAL (operands[1]))
++       == ((UINTVAL (operands[1])) >> 24) << 24)"
+   [(set (match_dup 2) (zero_extend:SI (match_dup 0)))
+    (set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 1)))]
+   "
+@@ -10562,7 +11042,11 @@
+   }
+   "
+   [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
++   (set_attr "predicable" "yes")
++   (set (attr "length")
++	(symbol_ref "arm_attr_length_pop_multi (operands,
++						/*return_pc=*/false,
++						/*write_back_p=*/true)"))]
+ )
+ 
+ ;; Pop with return (as used in epilogue RTL)
+@@ -10591,7 +11075,10 @@
+   }
+   "
+   [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
++   (set_attr "predicable" "yes")
++   (set (attr "length")
++	(symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
++						/*write_back_p=*/true)"))]
+ )
+ 
+ (define_insn "*pop_multiple_with_return"
+@@ -10611,7 +11098,10 @@
+   }
+   "
+   [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
++   (set_attr "predicable" "yes")
++   (set (attr "length")
++	(symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
++						/*write_back_p=*/false)"))]
+ )
+ 
+ ;; Load into PC and return
+@@ -10632,7 +11122,7 @@
+                    (match_operand:SI 2 "const_int_I_operand" "I")))
+      (set (match_operand:DF 3 "vfp_hard_register_operand" "")
+           (mem:DF (match_dup 1)))])]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "*
+   {
+     int num_regs = XVECLEN (operands[0], 0);
+@@ -10822,19 +11312,22 @@
+    (set_attr "predicable_short_it" "no")
+    (set_attr "type" "clz")])
+ 
+-(define_expand "ctzsi2"
+- [(set (match_operand:SI           0 "s_register_operand" "")
+-       (ctz:SI (match_operand:SI  1 "s_register_operand" "")))]
++;; Keep this as a CTZ expression until after reload and then split
++;; into RBIT + CLZ.  Since RBIT is represented as an UNSPEC it is unlikely
++;; to fold with any other expression.
++
++(define_insn_and_split "ctzsi2"
++ [(set (match_operand:SI           0 "s_register_operand" "=r")
++       (ctz:SI (match_operand:SI  1 "s_register_operand" "r")))]
+   "TARGET_32BIT && arm_arch_thumb2"
++  "#"
++  "&& reload_completed"
++  [(const_int 0)]
+   "
+-   {
+-     rtx tmp = gen_reg_rtx (SImode); 
+-     emit_insn (gen_rbitsi2 (tmp, operands[1]));
+-     emit_insn (gen_clzsi2 (operands[0], tmp));
+-   }
+-   DONE;
+-  "
+-)
++  emit_insn (gen_rbitsi2 (operands[0], operands[1]));
++  emit_insn (gen_clzsi2 (operands[0], operands[0]));
++  DONE;
++")
+ 
+ ;; V5E instructions.
+ 
+@@ -10958,13 +11451,16 @@
+ ;; We only care about the lower 16 bits of the constant 
+ ;; being inserted into the upper 16 bits of the register.
+ (define_insn "*arm_movtas_ze" 
+-  [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
++  [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r,r")
+                    (const_int 16)
+                    (const_int 16))
+         (match_operand:SI 1 "const_int_operand" ""))]
+-  "arm_arch_thumb2"
+-  "movt%?\t%0, %L1"
+- [(set_attr "predicable" "yes")
++  "TARGET_HAVE_MOVT"
++  "@
++   movt%?\t%0, %L1
++   movt\t%0, %L1"
++ [(set_attr "arch" "32,v8mb")
++  (set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")
+   (set_attr "length" "4")
+   (set_attr "type" "alu_sreg")]
+--- a/src/gcc/config/arm/arm.opt
++++ b/src/gcc/config/arm/arm.opt
+@@ -109,6 +109,10 @@ mfloat-abi=
+ Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI)
+ Specify if floating point hardware should be used.
+ 
++mcmse
++Target RejectNegative Var(use_cmse)
++Specify that the compiler should target secure code as per ARMv8-M Security Extensions.
++
+ Enum
+ Name(float_abi_type) Type(enum float_abi_type)
+ Known floating-point ABIs (for use with the -mfloat-abi= option):
+@@ -253,14 +257,6 @@ mrestrict-it
+ Target Report Var(arm_restrict_it) Init(2) Save
+ Generate IT blocks appropriate for ARMv8.
+ 
+-mold-rtx-costs
+-Target Report Mask(OLD_RTX_COSTS)
+-Use the old RTX costing tables (transitional).
+-
+-mnew-generic-costs
+-Target Report Mask(NEW_GENERIC_COSTS)
+-Use the new generic RTX cost tables if new core-specific cost table not available (transitional).
+-
+ mfix-cortex-m3-ldrd
+ Target Report Var(fix_cm3_ldrd) Init(2)
+ Avoid overlapping destination and address registers on LDRD instructions
+--- /dev/null
++++ b/src/gcc/config/arm/arm_cmse.h
+@@ -0,0 +1,199 @@
++/* ARMv8-M Secure Extensions intrinsics include file.
++
++   Copyright (C) 2015-2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++
++#ifndef _GCC_ARM_CMSE_H
++#define _GCC_ARM_CMSE_H
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#if __ARM_FEATURE_CMSE & 1
++
++#include <stddef.h>
++#include <stdint.h>
++
++#ifdef __ARM_BIG_ENDIAN
++
++typedef union {
++  struct cmse_address_info {
++#if __ARM_FEATURE_CMSE & 2
++    unsigned idau_region:8;
++    unsigned idau_region_valid:1;
++    unsigned secure:1;
++    unsigned nonsecure_readwrite_ok:1;
++    unsigned nonsecure_read_ok:1;
++#else
++    unsigned :12;
++#endif
++    unsigned readwrite_ok:1;
++    unsigned read_ok:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region_valid:1;
++#else
++    unsigned :1;
++#endif
++    unsigned mpu_region_valid:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region:8;
++#else
++    unsigned :8;
++#endif
++    unsigned mpu_region:8;
++  } flags;
++  unsigned value;
++} cmse_address_info_t;
++
++#else
++
++typedef union {
++  struct cmse_address_info {
++    unsigned mpu_region:8;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region:8;
++#else
++    unsigned :8;
++#endif
++    unsigned mpu_region_valid:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region_valid:1;
++#else
++    unsigned :1;
++#endif
++    unsigned read_ok:1;
++    unsigned readwrite_ok:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned nonsecure_read_ok:1;
++    unsigned nonsecure_readwrite_ok:1;
++    unsigned secure:1;
++    unsigned idau_region_valid:1;
++    unsigned idau_region:8;
++#else
++    unsigned :12;
++#endif
++  } flags;
++  unsigned value;
++} cmse_address_info_t;
++
++#endif /* __ARM_BIG_ENDIAN */
++
++#define cmse_TT_fptr(p) (__cmse_TT_fptr ((__cmse_fptr)(p)))
++
++typedef void (*__cmse_fptr)(void);
++
++#define __CMSE_TT_ASM(flags) \
++{ \
++  cmse_address_info_t __result; \
++   __asm__ ("tt" # flags " %0,%1" \
++	   : "=r"(__result) \
++	   : "r"(__p) \
++	   : "memory"); \
++  return __result; \
++}
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++__cmse_TT_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM ()
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++cmse_TT (void *__p)
++__CMSE_TT_ASM ()
++
++#define cmse_TTT_fptr(p) (__cmse_TTT_fptr ((__cmse_fptr)(p)))
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++__cmse_TTT_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM (t)
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++cmse_TTT (void *__p)
++__CMSE_TT_ASM (t)
++
++#if __ARM_FEATURE_CMSE & 2
++
++#define cmse_TTA_fptr(p) (__cmse_TTA_fptr ((__cmse_fptr)(p)))
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++__cmse_TTA_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM (a)
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++cmse_TTA (void *__p)
++__CMSE_TT_ASM (a)
++
++#define cmse_TTAT_fptr(p) (__cmse_TTAT_fptr ((__cmse_fptr)(p)))
++
++__extension__ static __inline cmse_address_info_t
++__attribute__ ((__always_inline__))
++__cmse_TTAT_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM (at)
++
++__extension__ static __inline cmse_address_info_t
++__attribute__ ((__always_inline__))
++cmse_TTAT (void *__p)
++__CMSE_TT_ASM (at)
++
++/* FIXME: diagnose use outside cmse_nonsecure_entry functions.  */
++__extension__ static __inline int __attribute__ ((__always_inline__))
++cmse_nonsecure_caller (void)
++{
++  return __builtin_arm_cmse_nonsecure_caller ();
++}
++
++#define CMSE_AU_NONSECURE	2
++#define CMSE_MPU_NONSECURE	16
++#define CMSE_NONSECURE		18
++
++#define cmse_nsfptr_create(p) ((typeof ((p))) ((intptr_t) (p) & ~1))
++
++#define cmse_is_nsfptr(p) (!((intptr_t) (p) & 1))
++
++#endif /* __ARM_FEATURE_CMSE & 2 */
++
++#define CMSE_MPU_UNPRIV		4
++#define CMSE_MPU_READWRITE	1
++#define CMSE_MPU_READ		8
++
++__extension__ void *
++cmse_check_address_range (void *, size_t, int);
++
++#define cmse_check_pointed_object(p, f) \
++  ((typeof ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f)))
++
++#endif /* __ARM_FEATURE_CMSE & 1 */
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _GCC_ARM_CMSE_H */
+--- /dev/null
++++ b/src/gcc/config/arm/arm_fp16.h
+@@ -0,0 +1,255 @@
++/* ARM FP16 intrinsics include file.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef _GCC_ARM_FP16_H
++#define _GCC_ARM_FP16_H 1
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include <stdint.h>
++
++/* Intrinsics for FP16 instructions.  */
++#pragma GCC push_options
++#pragma GCC target ("fpu=fp-armv8")
++
++#if defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
++
++typedef __fp16 float16_t;
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vabsh_f16 (float16_t __a)
++{
++  return __builtin_neon_vabshf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vaddh_f16 (float16_t __a, float16_t __b)
++{
++  return __a + __b;
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtah_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtahssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtah_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtahusi (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s32 (int32_t __a)
++{
++  return __builtin_neon_vcvthshf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u32 (uint32_t __a)
++{
++  return __builtin_neon_vcvthuhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s32 (int32_t __a, const int __b)
++{
++  return __builtin_neon_vcvths_nhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u32 (uint32_t __a, const int __b)
++{
++  return __builtin_neon_vcvthu_nhf ((int32_t)__a, __b);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_n_s32_f16 (float16_t __a, const int __b)
++{
++  return __builtin_neon_vcvths_nsi (__a, __b);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_n_u32_f16 (float16_t __a, const int __b)
++{
++  return (uint32_t)__builtin_neon_vcvthu_nsi (__a, __b);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvthssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvthusi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtmh_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtmhssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtmh_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtmhusi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtnh_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtnhssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtnh_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtnhusi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtph_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtphssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtph_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtphusi (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vdivh_f16 (float16_t __a, float16_t __b)
++{
++  return __a / __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmah_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_neon_vfmahf (__a, __b, __c);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmsh_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_neon_vfmshf (__a, __b, __c);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmaxnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_neon_vmaxnmhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vminnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_neon_vminnmhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmulh_f16 (float16_t __a, float16_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vnegh_f16 (float16_t __a)
++{
++  return  - __a;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndah_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndahf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndih_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndmh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndmhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndnh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndnhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndph_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndphf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndxh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndxhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsqrth_f16 (float16_t __a)
++{
++  return __builtin_neon_vsqrthf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsubh_f16 (float16_t __a, float16_t __b)
++{
++  return __a - __b;
++}
++
++#endif /* __ARM_FEATURE_FP16_SCALAR_ARITHMETIC  */
++#pragma GCC pop_options
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif
+--- a/src/gcc/config/arm/arm_neon.h
++++ b/src/gcc/config/arm/arm_neon.h
+@@ -38,6 +38,7 @@
+ extern "C" {
+ #endif
+ 
++#include <arm_fp16.h>
+ #include <stdint.h>
+ 
+ typedef __simd64_int8_t int8x8_t;
+@@ -509,528 +510,614 @@ typedef struct poly64x2x4_t
+ #pragma GCC pop_options
+ 
+ /* vadd  */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a + __b;
+ #else
+   return (float32x2_t) __builtin_neon_vaddv2sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a + __b;
+ #else
+   return (float32x4_t) __builtin_neon_vaddv4sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vaddlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vaddlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vaddlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vaddluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vaddluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vaddluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vaddwsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vaddwsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vaddwsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vaddwuv8qi ((int16x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vaddwuv4hi ((int32x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vaddwuv2si ((int64x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vhaddsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vhaddsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vhaddsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vhadduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vhadduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vhadduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vhaddsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vhaddsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vhaddsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vhadduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vhadduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vhadduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vrhaddsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vrhaddsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vrhaddsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrhadduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrhadduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrhadduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vrhaddsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vrhaddsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vrhaddsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vrhadduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vrhadduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vrhadduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqaddsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqaddsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqaddsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqaddsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqadduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqadduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqadduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqaddudi ((int64x1_t) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqaddsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqaddsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqaddsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqaddsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqadduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqadduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqadduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqadduv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vaddhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vaddhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vaddhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vaddhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vaddhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vaddhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vraddhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vraddhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vraddhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vraddhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vraddhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vraddhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a * __b;
+ #else
+   return (float32x2_t) __builtin_neon_vmulfv2sf (__a, __b);
+@@ -1038,493 +1125,574 @@ vmul_f32 (float32x2_t __a, float32x2_t __b)
+ 
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a * __b;
+ #else
+   return (float32x4_t) __builtin_neon_vmulfv4sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x8_t)__builtin_neon_vmulpv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (poly8x16_t)__builtin_neon_vmulpv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmulhv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmulhv4si (__a, __b);
+ }
+ 
+ #ifdef __ARM_FEATURE_QRDMX
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlahv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlahv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlahv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlahv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlshv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlshv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlshv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlshv4si (__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vmullsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmullsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vmullsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vmulluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmulluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vmulluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly16x8_t)__builtin_neon_vmullpv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmullv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqdmullv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vmlav8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmlav4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmlav2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmlav2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vmlav8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmlav4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmlav2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vmlav16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlav8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlav4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmlav4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vmlav16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlav8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlav4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlalsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlalsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlalsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlaluv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlaluv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlaluv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlalv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlalv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vmlsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmlsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmlsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmlsv2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vmlsv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmlsv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmlsv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vmlsv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlsv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlsv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmlsv4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vmlsv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlsv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlsv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlslsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlslsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlslsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlsluv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlsluv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlsluv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlslv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlslv2si (__a, __b, __c);
+@@ -1532,25 +1700,29 @@ vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=neon-vfpv4")
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfma_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vfmav2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vfmav4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vfmsv2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vfmsv4sf (__a, __b, __c);
+@@ -1558,7 +1730,8 @@ vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ #pragma GCC pop_options
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndn_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintnv2sf (__a);
+@@ -1566,7 +1739,8 @@ vrndn_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndnq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintnv4sf (__a);
+@@ -1574,7 +1748,8 @@ vrndnq_f32 (float32x4_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrnda_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintav2sf (__a);
+@@ -1582,7 +1757,8 @@ vrnda_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndaq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintav4sf (__a);
+@@ -1590,7 +1766,8 @@ vrndaq_f32 (float32x4_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndp_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintpv2sf (__a);
+@@ -1598,7 +1775,8 @@ vrndp_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndpq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintpv4sf (__a);
+@@ -1606,7 +1784,8 @@ vrndpq_f32 (float32x4_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndm_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintmv2sf (__a);
+@@ -1614,7 +1793,8 @@ vrndm_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndmq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintmv4sf (__a);
+@@ -1623,7 +1803,8 @@ vrndmq_f32 (float32x4_t __a)
+ #endif
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndx_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintxv2sf (__a);
+@@ -1632,7 +1813,8 @@ vrndx_f32 (float32x2_t __a)
+ #endif
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndxq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintxv4sf (__a);
+@@ -1641,7 +1823,8 @@ vrndxq_f32 (float32x4_t __a)
+ #endif
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrnd_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintzv2sf (__a);
+@@ -1649,7 +1832,8 @@ vrnd_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintzv4sf (__a);
+@@ -1657,2907 +1841,3436 @@ vrndq_f32 (float32x4_t __a)
+ 
+ #endif
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a - __b;
+ #else
+   return (float32x2_t) __builtin_neon_vsubv2sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a - __b;
+ #else
+   return (float32x4_t) __builtin_neon_vsubv4sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vsublsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vsublsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vsublsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vsubluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vsubluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vsubluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vsubwsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vsubwsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vsubwsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vsubwuv8qi ((int16x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vsubwuv4hi ((int32x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vsubwuv2si ((int64x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vhsubsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vhsubsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vhsubsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vhsubuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vhsubuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vhsubuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vhsubsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vhsubsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vhsubsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vhsubuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vhsubuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vhsubuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqsubsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqsubsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqsubsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqsubsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqsubuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqsubuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqsubuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqsubudi ((int64x1_t) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqsubsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqsubsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqsubsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqsubsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqsubuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqsubuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqsubuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqsubuv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vsubhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vsubhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vsubhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vsubhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vsubhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vsubhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vrsubhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vrsubhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vrsubhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrsubhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrsubhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrsubhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vceqv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vceqv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vceqv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vceqv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vceqv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vceqv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vceqv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vceqv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vceqv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vceqv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vceqv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vceqv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vceqv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vceqv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vceqv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vceqv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgeuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgeuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgeuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgev16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgev8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgeuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgeuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgeuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgev8qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgev4hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgeuv8qi ((int8x8_t) __b, (int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgeuv4hi ((int16x4_t) __b, (int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgeuv2si ((int32x2_t) __b, (int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgev16qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgev8hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgeuv16qi ((int8x16_t) __b, (int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgeuv8hi ((int16x8_t) __b, (int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgeuv4si ((int32x4_t) __b, (int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtv8qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtv4hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtuv8qi ((int8x8_t) __b, (int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtuv4hi ((int16x4_t) __b, (int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtuv2si ((int32x2_t) __b, (int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtv16qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtv8hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtuv16qi ((int8x16_t) __b, (int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtuv8hi ((int16x8_t) __b, (int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtuv4si ((int32x4_t) __b, (int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcage_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcageq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcale_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagev2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcaleq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagev4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcagt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagtv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcagtq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagtv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcalt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagtv2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcaltq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagtv4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtstv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vtstv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vtstv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vtstv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_p16 (poly16x4_t __a, poly16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vtstv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vtstv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vtstv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vtstv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_p16 (poly16x8_t __a, poly16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vabdsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vabdsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vabdsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vabdfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vabduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vabduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vabduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vabdsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vabdsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vabdsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vabdfv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vabduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vabduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vabduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vabdlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vabdlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vabdlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vabdluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vabdluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vabdluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vabasv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vabasv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vabasv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vabauv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vabauv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vabauv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vabasv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vabasv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vabasv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vabauv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vabauv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vabauv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vabalsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vabalsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vabalsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vabaluv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vabaluv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vabaluv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vmaxsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vmaxsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vmaxsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vmaxfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vmaxuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vmaxuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vmaxuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vmaxsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vmaxsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmaxsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vmaxfv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++#pragma GCC push_options
++#pragma GCC target ("fpu=neon-fp-armv8")
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f32 (float32x2_t a, float32x2_t b)
++{
++  return (float32x2_t)__builtin_neon_vmaxnmv2sf (a, b);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f32 (float32x4_t a, float32x4_t b)
++{
++  return (float32x4_t)__builtin_neon_vmaxnmv4sf (a, b);
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f32 (float32x2_t a, float32x2_t b)
++{
++  return (float32x2_t)__builtin_neon_vminnmv2sf (a, b);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f32 (float32x4_t a, float32x4_t b)
++{
++  return (float32x4_t)__builtin_neon_vminnmv4sf (a, b);
++}
++#pragma GCC pop_options
++
++
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vmaxuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vmaxuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmaxuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vminsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vminsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vminsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vminfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vminuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vminuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vminuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vminsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vminsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vminsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vminfv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vminuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vminuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vminuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vpaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vpaddv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vpaddv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpaddv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpaddv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_s8 (int8x8_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vpaddlsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_s16 (int16x4_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vpaddlsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_s32 (int32x2_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vpaddlsv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_u8 (uint8x8_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vpaddluv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_u16 (uint16x4_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vpaddluv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_u32 (uint32x2_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vpaddluv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_s8 (int8x16_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vpaddlsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_s16 (int16x8_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vpaddlsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_s32 (int32x4_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vpaddlsv4si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_u8 (uint8x16_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vpaddluv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_u16 (uint16x8_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vpaddluv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_u32 (uint32x4_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vpaddluv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_s8 (int16x4_t __a, int8x8_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpadalsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_s16 (int32x2_t __a, int16x4_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpadalsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_s32 (int64x1_t __a, int32x2_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vpadalsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_u8 (uint16x4_t __a, uint8x8_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpadaluv8qi ((int16x4_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_u16 (uint32x2_t __a, uint16x4_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpadaluv4hi ((int32x2_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_u32 (uint64x1_t __a, uint32x2_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vpadaluv2si ((int64x1_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_s8 (int16x8_t __a, int8x16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vpadalsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_s16 (int32x4_t __a, int16x8_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vpadalsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_s32 (int64x2_t __a, int32x4_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vpadalsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_u8 (uint16x8_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vpadaluv16qi ((int16x8_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_u16 (uint32x4_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vpadaluv8hi ((int32x4_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_u32 (uint64x2_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vpadaluv4si ((int64x2_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vpmaxsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpmaxsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpmaxsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vpmaxfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vpmaxuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpmaxuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpmaxuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vpminsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpminsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpminsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vpminfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vpminuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpminuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpminuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecps_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vrecpsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vrecpsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrts_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vrsqrtsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrtsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vrsqrtsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vrshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vrshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vrshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vrshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vrshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vrshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vrshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vrshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vrshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vrshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vrshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vrshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vrshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqrshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqrshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqrshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqrshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqrshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqrshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqrshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqrshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqrshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqrshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqrshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqrshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqrshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqrshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vshrs_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vshrs_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vshrs_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vshrs_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshru_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshru_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshru_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vshru_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vshrs_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vshrs_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vshrs_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vshrs_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vshru_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshru_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshru_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshru_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vrshrs_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vrshrs_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vrshrs_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vrshrs_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrshru_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrshru_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrshru_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vrshru_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vrshrs_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vrshrs_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vrshrs_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vrshrs_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vrshru_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vrshru_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vrshru_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vrshru_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshrn_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshrn_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshrn_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vrshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vrshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vrshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrshrn_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrshrn_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrshrn_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vqshrns_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vqshrns_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vqshrns_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshrnu_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshrnu_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshrnu_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vqrshrns_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrshrns_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrshrns_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqrshrnu_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqrshrnu_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqrshrnu_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqrshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqrshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqrshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vshl_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vshl_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vshl_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vshl_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshl_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshl_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshl_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vshl_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vshl_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vshl_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vshl_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vshl_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vshl_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshl_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshl_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshl_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vqshl_s_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vqshl_s_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vqshl_s_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vqshl_s_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshl_u_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshl_u_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshl_u_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqshl_u_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vqshl_s_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vqshl_s_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vqshl_s_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vqshl_s_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqshl_u_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqshl_u_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqshl_u_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqshl_u_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshlu_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshlu_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshlu_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqshlu_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqshlu_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqshlu_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqshlu_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqshlu_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vshlls_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vshlls_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vshlls_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshllu_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshllu_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshllu_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vsras_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vsras_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vsras_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vsras_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vsrau_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vsrau_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vsrau_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vsrau_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vsras_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vsras_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vsras_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vsras_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vsrau_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vsrau_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vsrau_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vsrau_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vrsras_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vrsras_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vrsras_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vrsras_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vrsrau_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vrsrau_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vrsrau_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vrsrau_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vrsras_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vrsras_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vrsras_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vrsras_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vrsrau_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vrsrau_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vrsrau_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vrsrau_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+@@ -4565,68 +5278,79 @@ vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vsri_ndi (__a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vsri_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vsri_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vsri_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vsri_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vsri_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vsri_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vsri_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vsri_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_p8 (poly8x8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vsri_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vsri_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+@@ -4634,68 +5358,79 @@ vsri_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vsri_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vsri_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vsri_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vsri_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vsri_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vsri_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vsri_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vsri_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vsri_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_p8 (poly8x16_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vsri_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vsri_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+@@ -4703,68 +5438,79 @@ vsriq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vsli_ndi (__a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vsli_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vsli_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vsli_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vsli_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vsli_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vsli_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vsli_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vsli_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_p8 (poly8x8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vsli_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vsli_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+@@ -4772,530 +5518,618 @@ vsli_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vsli_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vsli_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vsli_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vsli_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vsli_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vsli_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vsli_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vsli_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vsli_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_p8 (poly8x16_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vsli_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vsli_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vabsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vabsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vabsv2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vabsv2sf (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vabsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vabsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vabsv4si (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vabsv4sf (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vqabsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vqabsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vqabsv2si (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vqabsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vqabsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vqabsv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vnegv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vnegv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vnegv2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vnegv2sf (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vnegv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vnegv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vnegv4si (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vnegv4sf (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vqnegv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vqnegv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vqnegv2si (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vqnegv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vqnegv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vqnegv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vmvnv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vmvnv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vmvnv2si (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vmvnv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vmvnv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vmvnv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vmvnv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vmvnv4si (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vmvnv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vmvnv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcls_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vclsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcls_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vclsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcls_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vclsv2si (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vclsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vclsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vclsv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vclzv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vclzv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vclzv2si (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vclzv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vclzv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vclzv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vclzv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vclzv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vclzv4si (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vclzv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vclzv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vclzv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcnt_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vcntv8qi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcnt_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vcntv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcnt_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vcntv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcntq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vcntv16qi (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcntq_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vcntv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcntq_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vcntv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpe_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrecpev2sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpe_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vrecpev2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpeq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrecpev4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpeq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vrecpev4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrte_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrsqrtev2sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrte_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vrsqrtev2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrteq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrsqrtev4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrteq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vrsqrtev4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8_t)__builtin_neon_vget_lanev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16_t)__builtin_neon_vget_lanev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32_t)__builtin_neon_vget_lanev2si (__a, __b);
+@@ -5328,67 +6162,88 @@ vget_lane_s32 (int32x2_t __a, const int __b)
+   })
+ #endif
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return (float32_t)__builtin_neon_vget_lanev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8_t)__builtin_neon_vget_laneuv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16_t)__builtin_neon_vget_laneuv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32_t)__builtin_neon_vget_laneuv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return (poly8_t)__builtin_neon_vget_laneuv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return (poly16_t)__builtin_neon_vget_laneuv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64_t)__builtin_neon_vget_lanedi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++#pragma GCC push_options
++#pragma GCC target ("fpu=crypto-neon-fp-armv8")
++__extension__ extern __inline poly64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vget_lane_p64 (poly64x1_t __a, const int __b)
++{
++  return (poly64_t)__builtin_neon_vget_lanedi ((int64x1_t) __a, __b);
++}
++
++#pragma GCC pop_options
++__extension__ extern __inline uint64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64_t)__builtin_neon_vget_lanedi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8_t)__builtin_neon_vget_lanev16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16_t)__builtin_neon_vget_lanev8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32_t)__builtin_neon_vget_lanev4si (__a, __b);
+@@ -5405,67 +6260,78 @@ vgetq_lane_s32 (int32x4_t __a, const int __b)
+   })
+ #endif
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f32 (float32x4_t __a, const int __b)
+ {
+   return (float32_t)__builtin_neon_vget_lanev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8_t)__builtin_neon_vget_laneuv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16_t)__builtin_neon_vget_laneuv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32_t)__builtin_neon_vget_laneuv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p8 (poly8x16_t __a, const int __b)
+ {
+   return (poly8_t)__builtin_neon_vget_laneuv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p16 (poly16x8_t __a, const int __b)
+ {
+   return (poly16_t)__builtin_neon_vget_laneuv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64_t)__builtin_neon_vget_lanev2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64_t)__builtin_neon_vget_lanev2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s8 (int8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vset_lanev2si ((__builtin_neon_si) __a, __b, __c);
+@@ -5483,67 +6349,78 @@ vset_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+   })
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f32 (float32_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vset_lanev2sf ((__builtin_neon_sf) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u8 (uint8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u16 (uint16_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u32 (uint32_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vset_lanev2si ((__builtin_neon_si) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p8 (poly8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p16 (poly16_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s64 (int64_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u64 (uint64_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s8 (int8_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vset_lanev4si ((__builtin_neon_si) __a, __b, __c);
+@@ -5561,49 +6438,57 @@ vsetq_lane_s32 (int32_t __a, int32x4_t __b, const int __c)
+   })
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f32 (float32_t __a, float32x4_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vset_lanev4sf ((__builtin_neon_sf) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u8 (uint8_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u16 (uint16_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u32 (uint32_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vset_lanev4si ((__builtin_neon_si) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p8 (poly8_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p16 (poly16_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s64 (int64_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u64 (uint64_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, (int64x2_t) __b, __c);
+@@ -5611,136 +6496,158 @@ vsetq_lane_u64 (uint64_t __a, uint64x2_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p64 (uint64_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s8 (uint64_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s16 (uint64_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s32 (uint64_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s64 (uint64_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f16 (uint64_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f32 (uint64_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vcreatev2sf ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u8 (uint64_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u16 (uint64_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u32 (uint64_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u64 (uint64_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p8 (uint64_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p16 (uint64_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s8 (int8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s16 (int16_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s32 (int32_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_f32 (float32_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vdup_nv2sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u8 (uint8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u16 (uint16_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u32 (uint32_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_p8 (poly8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_p16 (poly16_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+@@ -5748,20 +6655,23 @@ vdup_n_p16 (poly16_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_p64 (poly64_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s64 (int64_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u64 (uint64_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+@@ -5769,260 +6679,303 @@ vdup_n_u64 (uint64_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_p64 (poly64_t __a)
+ {
+   return (poly64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s8 (int8_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s16 (int16_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s32 (int32_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_f32 (float32_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vdup_nv4sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u8 (uint8_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u16 (uint16_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u32 (uint32_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_p8 (poly8_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_p16 (poly16_t __a)
+ {
+   return (poly16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s64 (int64_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u64 (uint64_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s8 (int8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s16 (int16_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s32 (int32_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_f32 (float32_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vdup_nv2sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u8 (uint8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u16 (uint16_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u32 (uint32_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_p8 (poly8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_p16 (poly16_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s64 (int64_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u64 (uint64_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s8 (int8_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s16 (int16_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s32 (int32_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_f32 (float32_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vdup_nv4sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u8 (uint8_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u16 (uint16_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u32 (uint32_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_p8 (poly8_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_p16 (poly16_t __a)
+ {
+   return (poly16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s64 (int64_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u64 (uint64_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vdup_lanev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vdup_lanev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vdup_lanev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return (float32x2_t)__builtin_neon_vdup_lanev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vdup_lanev8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vdup_lanev4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vdup_lanev2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return (poly8x8_t)__builtin_neon_vdup_lanev8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return (poly16x4_t)__builtin_neon_vdup_lanev4hi ((int16x4_t) __a, __b);
+@@ -6030,74 +6983,86 @@ vdup_lane_p16 (poly16x4_t __a, const int __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_p64 (poly64x1_t __a, const int __b)
+ {
+   return (poly64x1_t)__builtin_neon_vdup_lanedi (__a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vdup_lanedi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vdup_lanedi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vdup_lanev16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vdup_lanev8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vdup_lanev4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return (float32x4_t)__builtin_neon_vdup_lanev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vdup_lanev16qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vdup_lanev8hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vdup_lanev4si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return (poly8x16_t)__builtin_neon_vdup_lanev16qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return (poly16x8_t)__builtin_neon_vdup_lanev8hi ((int16x4_t) __a, __b);
+@@ -6105,20 +7070,23 @@ vdupq_lane_p16 (poly16x4_t __a, const int __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_p64 (poly64x1_t __a, const int __b)
+ {
+   return (poly64x2_t)__builtin_neon_vdup_lanev2di (__a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vdup_lanev2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vdup_lanev2di ((int64x1_t) __a, __b);
+@@ -6126,82 +7094,95 @@ vdupq_lane_u64 (uint64x1_t __a, const int __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p64 (poly64x1_t __a, poly64x1_t __b)
+ {
+   return (poly64x2_t)__builtin_neon_vcombinedi (__a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vcombinev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vcombinev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vcombinev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vcombinedi (__a, __b);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f16 (float16x4_t __a, float16x4_t __b)
+ {
+   return __builtin_neon_vcombinev4hf (__a, __b);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vcombinev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcombinev8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcombinev4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcombinev2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vcombinedi ((int64x1_t) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x16_t)__builtin_neon_vcombinev8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   return (poly16x8_t)__builtin_neon_vcombinev4hi ((int16x4_t) __a, (int16x4_t) __b);
+@@ -6209,144 +7190,167 @@ vcombine_p16 (poly16x4_t __a, poly16x4_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p64 (poly64x2_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vget_highv2di ((int64x2_t) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s8 (int8x16_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vget_highv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s16 (int16x8_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vget_highv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s32 (int32x4_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vget_highv4si (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s64 (int64x2_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vget_highv2di (__a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f16 (float16x8_t __a)
+ {
+   return __builtin_neon_vget_highv8hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f32 (float32x4_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vget_highv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u8 (uint8x16_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vget_highv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u16 (uint16x8_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vget_highv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u32 (uint32x4_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vget_highv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u64 (uint64x2_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vget_highv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p8 (poly8x16_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vget_highv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p16 (poly16x8_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vget_highv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s8 (int8x16_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vget_lowv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s16 (int16x8_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vget_lowv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s32 (int32x4_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vget_lowv4si (__a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f16 (float16x8_t __a)
+ {
+   return __builtin_neon_vget_lowv8hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f32 (float32x4_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vget_lowv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u8 (uint8x16_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vget_lowv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u16 (uint16x8_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u32 (uint32x4_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p8 (poly8x16_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vget_lowv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p16 (poly16x8_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a);
+@@ -6354,68 +7358,79 @@ vget_low_p16 (poly16x8_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p64 (poly64x2_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s64 (int64x2_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vget_lowv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u64 (uint64x2_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_s32_f32 (float32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vcvtsv2sf (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f32_s32 (int32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vcvtsv2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f32_u32 (uint32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vcvtuv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_u32_f32 (float32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vcvtuv2sf (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_s32_f32 (float32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vcvtsv4sf (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_f32_s32 (int32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vcvtsv4si (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_f32_u32 (uint32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vcvtuv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_u32_f32 (float32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vcvtuv4sf (__a);
+@@ -6424,7 +7439,8 @@ vcvtq_u32_f32 (float32x4_t __a)
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=neon-fp16")
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f16_f32 (float32x4_t __a)
+ {
+   return (float16x4_t)__builtin_neon_vcvtv4hfv4sf (__a);
+@@ -6432,7 +7448,8 @@ vcvt_f16_f32 (float32x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f32_f16 (float16x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vcvtv4sfv4hf (__a);
+@@ -6440,1059 +7457,1232 @@ vcvt_f32_f16 (float16x4_t __a)
+ #endif
+ #pragma GCC pop_options
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_s32_f32 (float32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vcvts_nv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_f32_s32 (int32x2_t __a, const int __b)
+ {
+   return (float32x2_t)__builtin_neon_vcvts_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_f32_u32 (uint32x2_t __a, const int __b)
+ {
+   return (float32x2_t)__builtin_neon_vcvtu_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_u32_f32 (float32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcvtu_nv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_s32_f32 (float32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vcvts_nv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_f32_s32 (int32x4_t __a, const int __b)
+ {
+   return (float32x4_t)__builtin_neon_vcvts_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_f32_u32 (uint32x4_t __a, const int __b)
+ {
+   return (float32x4_t)__builtin_neon_vcvtu_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_u32_f32 (float32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcvtu_nv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_s16 (int16x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vmovnv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_s32 (int32x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vmovnv4si (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_s64 (int64x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vmovnv2di (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_u16 (uint16x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vmovnv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_u32 (uint32x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vmovnv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_u64 (uint64x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vmovnv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_s16 (int16x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vqmovnsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_s32 (int32x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vqmovnsv4si (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_s64 (int64x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vqmovnsv2di (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_u16 (uint16x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vqmovnuv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_u32 (uint32x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vqmovnuv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_u64 (uint64x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vqmovnuv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovun_s16 (int16x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vqmovunv8hi (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovun_s32 (int32x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vqmovunv4si (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovun_s64 (int64x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vqmovunv2di (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_s8 (int8x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vmovlsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_s16 (int16x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vmovlsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_s32 (int32x2_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vmovlsv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_u8 (uint8x8_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vmovluv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_u16 (uint16x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vmovluv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_u32 (uint32x2_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vmovluv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vtbl1v8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtbl1v8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl1_p8 (poly8x8_t __a, uint8x8_t __b)
+ {
+   return (poly8x8_t)__builtin_neon_vtbl1v8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl2_s8 (int8x8x2_t __a, int8x8_t __b)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a };
+   return (int8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl2_u8 (uint8x8x2_t __a, uint8x8_t __b)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a };
+   return (uint8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl2_p8 (poly8x8x2_t __a, uint8x8_t __b)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a };
+   return (poly8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl3_s8 (int8x8x3_t __a, int8x8_t __b)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a };
+   return (int8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl3_u8 (uint8x8x3_t __a, uint8x8_t __b)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a };
+   return (uint8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl3_p8 (poly8x8x3_t __a, uint8x8_t __b)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a };
+   return (poly8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl4_s8 (int8x8x4_t __a, int8x8_t __b)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a };
+   return (int8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl4_u8 (uint8x8x4_t __a, uint8x8_t __b)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a };
+   return (uint8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl4_p8 (poly8x8x4_t __a, uint8x8_t __b)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a };
+   return (poly8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx1_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vtbx1v8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx1_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vtbx1v8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx1_p8 (poly8x8_t __a, poly8x8_t __b, uint8x8_t __c)
+ {
+   return (poly8x8_t)__builtin_neon_vtbx1v8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx2_s8 (int8x8_t __a, int8x8x2_t __b, int8x8_t __c)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   return (int8x8_t)__builtin_neon_vtbx2v8qi (__a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx2_u8 (uint8x8_t __a, uint8x8x2_t __b, uint8x8_t __c)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   return (uint8x8_t)__builtin_neon_vtbx2v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx2_p8 (poly8x8_t __a, poly8x8x2_t __b, uint8x8_t __c)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   return (poly8x8_t)__builtin_neon_vtbx2v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx3_s8 (int8x8_t __a, int8x8x3_t __b, int8x8_t __c)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   return (int8x8_t)__builtin_neon_vtbx3v8qi (__a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx3_u8 (uint8x8_t __a, uint8x8x3_t __b, uint8x8_t __c)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   return (uint8x8_t)__builtin_neon_vtbx3v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx3_p8 (poly8x8_t __a, poly8x8x3_t __b, uint8x8_t __c)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   return (poly8x8_t)__builtin_neon_vtbx3v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx4_s8 (int8x8_t __a, int8x8x4_t __b, int8x8_t __c)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   return (int8x8_t)__builtin_neon_vtbx4v8qi (__a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx4_u8 (uint8x8_t __a, uint8x8x4_t __b, uint8x8_t __c)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   return (uint8x8_t)__builtin_neon_vtbx4v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx4_p8 (poly8x8_t __a, poly8x8x4_t __b, uint8x8_t __c)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   return (poly8x8_t)__builtin_neon_vtbx4v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vmul_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vmul_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_f32 (float32x2_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vmul_lanev2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmul_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmul_lanev2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vmul_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vmul_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_f32 (float32x4_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vmul_lanev4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_u16 (uint16x8_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmul_lanev8hi ((int16x8_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_u32 (uint32x4_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmul_lanev4si ((int32x4_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vmla_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vmla_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x2_t)__builtin_neon_vmla_lanev2sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x4_t)__builtin_neon_vmla_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x2_t)__builtin_neon_vmla_lanev2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vmla_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmla_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x4_t)__builtin_neon_vmla_lanev4sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x8_t)__builtin_neon_vmla_lanev8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmla_lanev4si ((int32x4_t) __a, (int32x4_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmlals_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vmlals_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmlalu_lanev4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint64x2_t)__builtin_neon_vmlalu_lanev2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlal_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlal_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vmls_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vmls_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x2_t)__builtin_neon_vmls_lanev2sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x4_t)__builtin_neon_vmls_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x2_t)__builtin_neon_vmls_lanev2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vmls_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmls_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x4_t)__builtin_neon_vmls_lanev4sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x8_t)__builtin_neon_vmls_lanev8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmls_lanev4si ((int32x4_t) __a, (int32x4_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmlsls_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vmlsls_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmlslu_lanev4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint64x2_t)__builtin_neon_vmlslu_lanev2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlsl_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlsl_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vmulls_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vmulls_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmullu_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmullu_lanev2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmull_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmull_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vqdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vqdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vqdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+ #ifdef __ARM_FEATURE_QRDMX
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlah_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlah_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlah_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlah_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlsh_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlsh_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlsh_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlsh_lanev2si (__a, __b, __c, __d);
+ }
+ #endif
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vmul_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vmul_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_f32 (float32x2_t __a, float32_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vmul_nv2sf (__a, (__builtin_neon_sf) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_u16 (uint16x4_t __a, uint16_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vmul_nv4hi ((int16x4_t) __a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_u32 (uint32x2_t __a, uint32_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vmul_nv2si ((int32x2_t) __a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vmul_nv8hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmul_nv4si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_f32 (float32x4_t __a, float32_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vmul_nv4sf (__a, (__builtin_neon_sf) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_u16 (uint16x8_t __a, uint16_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vmul_nv8hi ((int16x8_t) __a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_u32 (uint32x4_t __a, uint32_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmul_nv4si ((int32x4_t) __a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmulls_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vmulls_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_u16 (uint16x4_t __a, uint16_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmullu_nv4hi ((int16x4_t) __a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_u32 (uint32x2_t __a, uint32_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vmullu_nv2si ((int32x2_t) __a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmull_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqdmull_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqdmulh_nv8hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmulh_nv4si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqdmulh_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqdmulh_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmulh_nv8hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmulh_nv4si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmulh_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmulh_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmla_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmla_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmla_nv2sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmla_nv4hi ((int16x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmla_nv2si ((int32x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmla_nv8hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmla_nv4si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmla_nv4sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmla_nv8hi ((int16x8_t) __a, (int16x8_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmla_nv4si ((int32x4_t) __a, (int32x4_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlals_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlals_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlalu_nv4hi ((int32x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlalu_nv2si ((int64x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlal_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlal_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmls_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmls_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmls_nv2sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmls_nv4hi ((int16x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmls_nv2si ((int32x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmls_nv8hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmls_nv4si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmls_nv4sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmls_nv8hi ((int16x8_t) __a, (int16x8_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmls_nv4si ((int32x4_t) __a, (int32x4_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlsls_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlsls_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlslu_nv4hi ((int32x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlslu_nv2si ((int64x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlsl_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlsl_nv2si (__a, __b, (__builtin_neon_si) __c);
+@@ -7500,74 +8690,86 @@ vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vextdi (__a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vextv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vextv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vextv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vextdi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_f32 (float32x2_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vextv2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vextv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vextv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vextv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vextdi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_p8 (poly8x8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vextv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vextv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+@@ -7575,290 +8777,338 @@ vext_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vextv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vextv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vextv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vextv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vextv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_f32 (float32x4_t __a, float32x4_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vextv4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vextv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vextv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vextv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vextv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_p8 (poly8x16_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vextv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vextv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_s32 (int32x2_t __a)
+ {
+   return (int32x2_t) __builtin_shuffle (__a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_f32 (float32x2_t __a)
+ {
+   return (float32x2_t) __builtin_shuffle (__a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t) __builtin_shuffle (__a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_p16 (poly16x4_t __a)
+ {
+   return (poly16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_s32 (int32x4_t __a)
+ {
+   return (int32x4_t) __builtin_shuffle (__a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_f32 (float32x4_t __a)
+ {
+   return (float32x4_t) __builtin_shuffle (__a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t) __builtin_shuffle (__a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_p16 (poly16x8_t __a)
+ {
+   return (poly16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_p16 (poly16x4_t __a)
+ {
+   return (poly16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_p16 (poly16x8_t __a)
+ {
+   return (poly16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16q_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16q_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16q_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+@@ -7866,74 +9116,86 @@ vrev16q_p8 (poly8x16_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_p64 (uint64x1_t __a, poly64x1_t __b, poly64x1_t __c)
+ {
+   return (poly64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vbslv2si ((int32x2_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
+ {
+   return (int64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vbslv2sf ((int32x2_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vbslv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
+ {
+   return (uint64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, (int64x1_t) __b, (int64x1_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
+ {
+   return (poly8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
+ {
+   return (poly16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+@@ -7941,74 +9203,86 @@ vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_p64 (uint64x2_t __a, poly64x2_t __b, poly64x2_t __c)
+ {
+   return (poly64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, (int64x2_t) __b, (int64x2_t) __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vbslv4si ((int32x4_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vbslv4sf ((int32x4_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vbslv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, (int64x2_t) __b, (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
+ {
+   return (poly8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
+ {
+   return (poly16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+@@ -8025,7 +9299,8 @@ vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
+    vector, and will itself be loaded in reverse order (again, relative to the
+    neon intrinsics view, i.e. that would result from a "vld1" instruction).  */
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   int8x8x2_t __rv;
+@@ -8043,7 +9318,8 @@ vtrn_s8 (int8x8_t __a, int8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   int16x4x2_t __rv;
+@@ -8057,7 +9333,8 @@ vtrn_s16 (int16x4_t __a, int16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   uint8x8x2_t __rv;
+@@ -8075,7 +9352,8 @@ vtrn_u8 (uint8x8_t __a, uint8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   uint16x4x2_t __rv;
+@@ -8089,7 +9367,8 @@ vtrn_u16 (uint16x4_t __a, uint16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   poly8x8x2_t __rv;
+@@ -8107,7 +9386,8 @@ vtrn_p8 (poly8x8_t __a, poly8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   poly16x4x2_t __rv;
+@@ -8121,7 +9401,8 @@ vtrn_p16 (poly16x4_t __a, poly16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   int32x2x2_t __rv;
+@@ -8135,7 +9416,8 @@ vtrn_s32 (int32x2_t __a, int32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   float32x2x2_t __rv;
+@@ -8149,7 +9431,8 @@ vtrn_f32 (float32x2_t __a, float32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   uint32x2x2_t __rv;
+@@ -8163,7 +9446,8 @@ vtrn_u32 (uint32x2_t __a, uint32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   int8x16x2_t __rv;
+@@ -8181,7 +9465,8 @@ vtrnq_s8 (int8x16_t __a, int8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   int16x8x2_t __rv;
+@@ -8199,7 +9484,8 @@ vtrnq_s16 (int16x8_t __a, int16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   int32x4x2_t __rv;
+@@ -8213,7 +9499,8 @@ vtrnq_s32 (int32x4_t __a, int32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   float32x4x2_t __rv;
+@@ -8227,7 +9514,8 @@ vtrnq_f32 (float32x4_t __a, float32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   uint8x16x2_t __rv;
+@@ -8245,7 +9533,8 @@ vtrnq_u8 (uint8x16_t __a, uint8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   uint16x8x2_t __rv;
+@@ -8263,7 +9552,8 @@ vtrnq_u16 (uint16x8_t __a, uint16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   uint32x4x2_t __rv;
+@@ -8277,7 +9567,8 @@ vtrnq_u32 (uint32x4_t __a, uint32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   poly8x16x2_t __rv;
+@@ -8295,7 +9586,8 @@ vtrnq_p8 (poly8x16_t __a, poly8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+   poly16x8x2_t __rv;
+@@ -8313,7 +9605,8 @@ vtrnq_p16 (poly16x8_t __a, poly16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   int8x8x2_t __rv;
+@@ -8331,7 +9624,8 @@ vzip_s8 (int8x8_t __a, int8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   int16x4x2_t __rv;
+@@ -8345,7 +9639,8 @@ vzip_s16 (int16x4_t __a, int16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   uint8x8x2_t __rv;
+@@ -8363,7 +9658,8 @@ vzip_u8 (uint8x8_t __a, uint8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   uint16x4x2_t __rv;
+@@ -8377,7 +9673,8 @@ vzip_u16 (uint16x4_t __a, uint16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   poly8x8x2_t __rv;
+@@ -8395,7 +9692,8 @@ vzip_p8 (poly8x8_t __a, poly8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   poly16x4x2_t __rv;
+@@ -8409,7 +9707,8 @@ vzip_p16 (poly16x4_t __a, poly16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   int32x2x2_t __rv;
+@@ -8423,7 +9722,8 @@ vzip_s32 (int32x2_t __a, int32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   float32x2x2_t __rv;
+@@ -8437,7 +9737,8 @@ vzip_f32 (float32x2_t __a, float32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   uint32x2x2_t __rv;
+@@ -8451,7 +9752,8 @@ vzip_u32 (uint32x2_t __a, uint32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   int8x16x2_t __rv;
+@@ -8469,7 +9771,8 @@ vzipq_s8 (int8x16_t __a, int8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   int16x8x2_t __rv;
+@@ -8487,7 +9790,8 @@ vzipq_s16 (int16x8_t __a, int16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   int32x4x2_t __rv;
+@@ -8501,7 +9805,8 @@ vzipq_s32 (int32x4_t __a, int32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   float32x4x2_t __rv;
+@@ -8515,7 +9820,8 @@ vzipq_f32 (float32x4_t __a, float32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   uint8x16x2_t __rv;
+@@ -8533,7 +9839,8 @@ vzipq_u8 (uint8x16_t __a, uint8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   uint16x8x2_t __rv;
+@@ -8551,7 +9858,8 @@ vzipq_u16 (uint16x8_t __a, uint16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   uint32x4x2_t __rv;
+@@ -8565,7 +9873,8 @@ vzipq_u32 (uint32x4_t __a, uint32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   poly8x16x2_t __rv;
+@@ -8583,7 +9892,8 @@ vzipq_p8 (poly8x16_t __a, poly8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+   poly16x8x2_t __rv;
+@@ -8601,7 +9911,8 @@ vzipq_p16 (poly16x8_t __a, poly16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   int8x8x2_t __rv;
+@@ -8619,7 +9930,8 @@ vuzp_s8 (int8x8_t __a, int8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   int16x4x2_t __rv;
+@@ -8633,7 +9945,8 @@ vuzp_s16 (int16x4_t __a, int16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   int32x2x2_t __rv;
+@@ -8647,7 +9960,8 @@ vuzp_s32 (int32x2_t __a, int32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   float32x2x2_t __rv;
+@@ -8661,7 +9975,8 @@ vuzp_f32 (float32x2_t __a, float32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   uint8x8x2_t __rv;
+@@ -8679,7 +9994,8 @@ vuzp_u8 (uint8x8_t __a, uint8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   uint16x4x2_t __rv;
+@@ -8693,7 +10009,8 @@ vuzp_u16 (uint16x4_t __a, uint16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   uint32x2x2_t __rv;
+@@ -8707,7 +10024,8 @@ vuzp_u32 (uint32x2_t __a, uint32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   poly8x8x2_t __rv;
+@@ -8725,7 +10043,8 @@ vuzp_p8 (poly8x8_t __a, poly8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   poly16x4x2_t __rv;
+@@ -8739,7 +10058,8 @@ vuzp_p16 (poly16x4_t __a, poly16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   int8x16x2_t __rv;
+@@ -8757,7 +10077,8 @@ vuzpq_s8 (int8x16_t __a, int8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   int16x8x2_t __rv;
+@@ -8775,7 +10096,8 @@ vuzpq_s16 (int16x8_t __a, int16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   int32x4x2_t __rv;
+@@ -8789,7 +10111,8 @@ vuzpq_s32 (int32x4_t __a, int32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   float32x4x2_t __rv;
+@@ -8803,7 +10126,8 @@ vuzpq_f32 (float32x4_t __a, float32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   uint8x16x2_t __rv;
+@@ -8821,7 +10145,8 @@ vuzpq_u8 (uint8x16_t __a, uint8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   uint16x8x2_t __rv;
+@@ -8839,7 +10164,8 @@ vuzpq_u16 (uint16x8_t __a, uint16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   uint32x4x2_t __rv;
+@@ -8853,7 +10179,8 @@ vuzpq_u32 (uint32x4_t __a, uint32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   poly8x16x2_t __rv;
+@@ -8871,7 +10198,8 @@ vuzpq_p8 (poly8x16_t __a, poly8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+   poly16x8x2_t __rv;
+@@ -8891,82 +10219,95 @@ vuzpq_p16 (poly16x8_t __a, poly16x8_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_p64 (const poly64_t * __a)
+ {
+   return (poly64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s8 (const int8_t * __a)
+ {
+   return (int8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s16 (const int16_t * __a)
+ {
+   return (int16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s32 (const int32_t * __a)
+ {
+   return (int32x2_t)__builtin_neon_vld1v2si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s64 (const int64_t * __a)
+ {
+   return (int64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_f16 (const float16_t * __a)
+ {
+   return __builtin_neon_vld1v4hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_f32 (const float32_t * __a)
+ {
+   return (float32x2_t)__builtin_neon_vld1v2sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u8 (const uint8_t * __a)
+ {
+   return (uint8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u16 (const uint16_t * __a)
+ {
+   return (uint16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u32 (const uint32_t * __a)
+ {
+   return (uint32x2_t)__builtin_neon_vld1v2si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u64 (const uint64_t * __a)
+ {
+   return (uint64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_p8 (const poly8_t * __a)
+ {
+   return (poly8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_p16 (const poly16_t * __a)
+ {
+   return (poly16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a);
+@@ -8974,144 +10315,167 @@ vld1_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_p64 (const poly64_t * __a)
+ {
+   return (poly64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s8 (const int8_t * __a)
+ {
+   return (int8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s16 (const int16_t * __a)
+ {
+   return (int16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s32 (const int32_t * __a)
+ {
+   return (int32x4_t)__builtin_neon_vld1v4si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s64 (const int64_t * __a)
+ {
+   return (int64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_f16 (const float16_t * __a)
+ {
+   return __builtin_neon_vld1v8hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_f32 (const float32_t * __a)
+ {
+   return (float32x4_t)__builtin_neon_vld1v4sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u8 (const uint8_t * __a)
+ {
+   return (uint8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u16 (const uint16_t * __a)
+ {
+   return (uint16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u32 (const uint32_t * __a)
+ {
+   return (uint32x4_t)__builtin_neon_vld1v4si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u64 (const uint64_t * __a)
+ {
+   return (uint64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_p8 (const poly8_t * __a)
+ {
+   return (poly8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_p16 (const poly16_t * __a)
+ {
+   return (poly16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s16 (const int16_t * __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s32 (const int32_t * __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vld1_lanev2si ((const __builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_f16 (const float16_t * __a, float16x4_t __b, const int __c)
+ {
+   return vset_lane_f16 (*__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_f32 (const float32_t * __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vld1_lanev2sf ((const __builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u8 (const uint8_t * __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u16 (const uint16_t * __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u32 (const uint32_t * __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vld1_lanev2si ((const __builtin_neon_si *) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_p8 (const poly8_t * __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_p16 (const poly16_t * __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+@@ -9119,82 +10483,95 @@ vld1_lane_p16 (const poly16_t * __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_p64 (const poly64_t * __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s64 (const int64_t * __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u64 (const uint64_t * __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s8 (const int8_t * __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s16 (const int16_t * __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s32 (const int32_t * __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vld1_lanev4si ((const __builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_f16 (const float16_t * __a, float16x8_t __b, const int __c)
+ {
+   return vsetq_lane_f16 (*__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_f32 (const float32_t * __a, float32x4_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vld1_lanev4sf ((const __builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u8 (const uint8_t * __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u16 (const uint16_t * __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u32 (const uint32_t * __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vld1_lanev4si ((const __builtin_neon_si *) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_p8 (const poly8_t * __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_p16 (const poly16_t * __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+@@ -9202,45 +10579,52 @@ vld1q_lane_p16 (const poly16_t * __a, poly16x8_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_p64 (const poly64_t * __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s64 (const int64_t * __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u64 (const uint64_t * __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s8 (const int8_t * __a)
+ {
+   return (int8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s16 (const int16_t * __a)
+ {
+   return (int16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s32 (const int32_t * __a)
+ {
+   return (int32x2_t)__builtin_neon_vld1_dupv2si ((const __builtin_neon_si *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_f16 (const float16_t * __a)
+ {
+   float16_t __f = *__a;
+@@ -9248,37 +10632,43 @@ vld1_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_f32 (const float32_t * __a)
+ {
+   return (float32x2_t)__builtin_neon_vld1_dupv2sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u8 (const uint8_t * __a)
+ {
+   return (uint8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u16 (const uint16_t * __a)
+ {
+   return (uint16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u32 (const uint32_t * __a)
+ {
+   return (uint32x2_t)__builtin_neon_vld1_dupv2si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_p8 (const poly8_t * __a)
+ {
+   return (poly8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_p16 (const poly16_t * __a)
+ {
+   return (poly16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a);
+@@ -9286,45 +10676,52 @@ vld1_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_p64 (const poly64_t * __a)
+ {
+   return (poly64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s64 (const int64_t * __a)
+ {
+   return (int64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u64 (const uint64_t * __a)
+ {
+   return (uint64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s8 (const int8_t * __a)
+ {
+   return (int8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s16 (const int16_t * __a)
+ {
+   return (int16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s32 (const int32_t * __a)
+ {
+   return (int32x4_t)__builtin_neon_vld1_dupv4si ((const __builtin_neon_si *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_f16 (const float16_t * __a)
+ {
+   float16_t __f = *__a;
+@@ -9332,37 +10729,43 @@ vld1q_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_f32 (const float32_t * __a)
+ {
+   return (float32x4_t)__builtin_neon_vld1_dupv4sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u8 (const uint8_t * __a)
+ {
+   return (uint8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u16 (const uint16_t * __a)
+ {
+   return (uint16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u32 (const uint32_t * __a)
+ {
+   return (uint32x4_t)__builtin_neon_vld1_dupv4si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_p8 (const poly8_t * __a)
+ {
+   return (poly8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_p16 (const poly16_t * __a)
+ {
+   return (poly16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a);
+@@ -9370,20 +10773,23 @@ vld1q_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_p64 (const poly64_t * __a)
+ {
+   return (poly64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s64 (const int64_t * __a)
+ {
+   return (int64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u64 (const uint64_t * __a)
+ {
+   return (uint64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a);
+@@ -9391,82 +10797,95 @@ vld1q_dup_u64 (const uint64_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_p64 (poly64_t * __a, poly64x1_t __b)
+ {
+   __builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s8 (int8_t * __a, int8x8_t __b)
+ {
+   __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s16 (int16_t * __a, int16x4_t __b)
+ {
+   __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s32 (int32_t * __a, int32x2_t __b)
+ {
+   __builtin_neon_vst1v2si ((__builtin_neon_si *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s64 (int64_t * __a, int64x1_t __b)
+ {
+   __builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_f16 (float16_t * __a, float16x4_t __b)
+ {
+   __builtin_neon_vst1v4hf (__a, __b);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_f32 (float32_t * __a, float32x2_t __b)
+ {
+   __builtin_neon_vst1v2sf ((__builtin_neon_sf *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u8 (uint8_t * __a, uint8x8_t __b)
+ {
+   __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u16 (uint16_t * __a, uint16x4_t __b)
+ {
+   __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u32 (uint32_t * __a, uint32x2_t __b)
+ {
+   __builtin_neon_vst1v2si ((__builtin_neon_si *) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u64 (uint64_t * __a, uint64x1_t __b)
+ {
+   __builtin_neon_vst1di ((__builtin_neon_di *) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_p8 (poly8_t * __a, poly8x8_t __b)
+ {
+   __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_p16 (poly16_t * __a, poly16x4_t __b)
+ {
+   __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b);
+@@ -9474,144 +10893,167 @@ vst1_p16 (poly16_t * __a, poly16x4_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_p64 (poly64_t * __a, poly64x2_t __b)
+ {
+   __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s8 (int8_t * __a, int8x16_t __b)
+ {
+   __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s16 (int16_t * __a, int16x8_t __b)
+ {
+   __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s32 (int32_t * __a, int32x4_t __b)
+ {
+   __builtin_neon_vst1v4si ((__builtin_neon_si *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s64 (int64_t * __a, int64x2_t __b)
+ {
+   __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, __b);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_f16 (float16_t * __a, float16x8_t __b)
+ {
+   __builtin_neon_vst1v8hf (__a, __b);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_f32 (float32_t * __a, float32x4_t __b)
+ {
+   __builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u8 (uint8_t * __a, uint8x16_t __b)
+ {
+   __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u16 (uint16_t * __a, uint16x8_t __b)
+ {
+   __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u32 (uint32_t * __a, uint32x4_t __b)
+ {
+   __builtin_neon_vst1v4si ((__builtin_neon_si *) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u64 (uint64_t * __a, uint64x2_t __b)
+ {
+   __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_p8 (poly8_t * __a, poly8x16_t __b)
+ {
+   __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_p16 (poly16_t * __a, poly16x8_t __b)
+ {
+   __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s16 (int16_t * __a, int16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s32 (int32_t * __a, int32x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2si ((__builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_f16 (float16_t * __a, float16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hf (__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_f32 (float32_t * __a, float32x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2sf ((__builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u8 (uint8_t * __a, uint8x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u16 (uint16_t * __a, uint16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u32 (uint32_t * __a, uint32x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2si ((__builtin_neon_si *) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_p8 (poly8_t * __a, poly8x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_p16 (poly16_t * __a, poly16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+@@ -9619,82 +11061,95 @@ vst1_lane_p16 (poly16_t * __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_p64 (poly64_t * __a, poly64x1_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s64 (int64_t * __a, int64x1_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u64 (uint64_t * __a, uint64x1_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s8 (int8_t * __a, int8x16_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s16 (int16_t * __a, int16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s32 (int32_t * __a, int32x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4si ((__builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_f16 (float16_t * __a, float16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hf (__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_f32 (float32_t * __a, float32x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4sf ((__builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u8 (uint8_t * __a, uint8x16_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u16 (uint16_t * __a, uint16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u32 (uint32_t * __a, uint32x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4si ((__builtin_neon_si *) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_p8 (poly8_t * __a, poly8x16_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_p16 (poly16_t * __a, poly16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+@@ -9702,26 +11157,30 @@ vst1q_lane_p16 (poly16_t * __a, poly16x8_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_p64 (poly64_t * __a, poly64x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s64 (int64_t * __a, int64x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u64 (uint64_t * __a, uint64x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s8 (const int8_t * __a)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9729,7 +11188,8 @@ vld2_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s16 (const int16_t * __a)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9737,7 +11197,8 @@ vld2_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s32 (const int32_t * __a)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9746,7 +11207,8 @@ vld2_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_f16 (const float16_t * __a)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9755,7 +11217,8 @@ vld2_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_f32 (const float32_t * __a)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9763,7 +11226,8 @@ vld2_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9771,7 +11235,8 @@ vld2_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9779,7 +11244,8 @@ vld2_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9787,7 +11253,8 @@ vld2_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9795,7 +11262,8 @@ vld2_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9805,7 +11273,8 @@ vld2_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9814,7 +11283,8 @@ vld2_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s64 (const int64_t * __a)
+ {
+   union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9822,7 +11292,8 @@ vld2_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9830,7 +11301,8 @@ vld2_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_s8 (const int8_t * __a)
+ {
+   union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9838,7 +11310,8 @@ vld2q_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_s16 (const int16_t * __a)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9846,7 +11319,8 @@ vld2q_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_s32 (const int32_t * __a)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9855,7 +11329,8 @@ vld2q_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_f16 (const float16_t * __a)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9864,7 +11339,8 @@ vld2q_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_f32 (const float32_t * __a)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9872,7 +11348,8 @@ vld2q_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_u8 (const uint8_t * __a)
+ {
+   union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9880,7 +11357,8 @@ vld2q_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_u16 (const uint16_t * __a)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9888,7 +11366,8 @@ vld2q_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_u32 (const uint32_t * __a)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9896,7 +11375,8 @@ vld2q_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_p8 (const poly8_t * __a)
+ {
+   union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9904,7 +11384,8 @@ vld2q_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_p16 (const poly16_t * __a)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9912,7 +11393,8 @@ vld2q_p16 (const poly16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_s8 (const int8_t * __a, int8x8x2_t __b, const int __c)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9921,7 +11403,8 @@ vld2_lane_s8 (const int8_t * __a, int8x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_s16 (const int16_t * __a, int16x4x2_t __b, const int __c)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9930,7 +11413,8 @@ vld2_lane_s16 (const int16_t * __a, int16x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_s32 (const int32_t * __a, int32x2x2_t __b, const int __c)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9940,7 +11424,8 @@ vld2_lane_s32 (const int32_t * __a, int32x2x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_f16 (const float16_t * __a, float16x4x2_t __b, const int __c)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9950,7 +11435,8 @@ vld2_lane_f16 (const float16_t * __a, float16x4x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_f32 (const float32_t * __a, float32x2x2_t __b, const int __c)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9959,7 +11445,8 @@ vld2_lane_f32 (const float32_t * __a, float32x2x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_u8 (const uint8_t * __a, uint8x8x2_t __b, const int __c)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9968,7 +11455,8 @@ vld2_lane_u8 (const uint8_t * __a, uint8x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_u16 (const uint16_t * __a, uint16x4x2_t __b, const int __c)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9977,7 +11465,8 @@ vld2_lane_u16 (const uint16_t * __a, uint16x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_u32 (const uint32_t * __a, uint32x2x2_t __b, const int __c)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9986,7 +11475,8 @@ vld2_lane_u32 (const uint32_t * __a, uint32x2x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_p8 (const poly8_t * __a, poly8x8x2_t __b, const int __c)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9995,7 +11485,8 @@ vld2_lane_p8 (const poly8_t * __a, poly8x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_p16 (const poly16_t * __a, poly16x4x2_t __b, const int __c)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10004,7 +11495,8 @@ vld2_lane_p16 (const poly16_t * __a, poly16x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_s16 (const int16_t * __a, int16x8x2_t __b, const int __c)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10013,7 +11505,8 @@ vld2q_lane_s16 (const int16_t * __a, int16x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_s32 (const int32_t * __a, int32x4x2_t __b, const int __c)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10023,7 +11516,8 @@ vld2q_lane_s32 (const int32_t * __a, int32x4x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_f16 (const float16_t * __a, float16x8x2_t __b, const int __c)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10033,7 +11527,8 @@ vld2q_lane_f16 (const float16_t * __a, float16x8x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_f32 (const float32_t * __a, float32x4x2_t __b, const int __c)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10042,7 +11537,8 @@ vld2q_lane_f32 (const float32_t * __a, float32x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_u16 (const uint16_t * __a, uint16x8x2_t __b, const int __c)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10051,7 +11547,8 @@ vld2q_lane_u16 (const uint16_t * __a, uint16x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_u32 (const uint32_t * __a, uint32x4x2_t __b, const int __c)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10060,7 +11557,8 @@ vld2q_lane_u32 (const uint32_t * __a, uint32x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_p16 (const poly16_t * __a, poly16x8x2_t __b, const int __c)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10069,7 +11567,8 @@ vld2q_lane_p16 (const poly16_t * __a, poly16x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s8 (const int8_t * __a)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10077,7 +11576,8 @@ vld2_dup_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s16 (const int16_t * __a)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10085,7 +11585,8 @@ vld2_dup_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s32 (const int32_t * __a)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10094,7 +11595,8 @@ vld2_dup_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_f16 (const float16_t * __a)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10103,7 +11605,8 @@ vld2_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_f32 (const float32_t * __a)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10111,7 +11614,8 @@ vld2_dup_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10119,7 +11623,8 @@ vld2_dup_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10127,7 +11632,8 @@ vld2_dup_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10135,7 +11641,8 @@ vld2_dup_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10143,7 +11650,8 @@ vld2_dup_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10153,7 +11661,8 @@ vld2_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10162,7 +11671,8 @@ vld2_dup_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s64 (const int64_t * __a)
+ {
+   union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10170,7 +11680,8 @@ vld2_dup_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10178,21 +11689,24 @@ vld2_dup_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s8 (int8_t * __a, int8x8x2_t __b)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s16 (int16_t * __a, int16x4x2_t __b)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s32 (int32_t * __a, int32x2x2_t __b)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10200,7 +11714,8 @@ vst2_s32 (int32_t * __a, int32x2x2_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_f16 (float16_t * __a, float16x4x2_t __b)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10208,42 +11723,48 @@ vst2_f16 (float16_t * __a, float16x4x2_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_f32 (float32_t * __a, float32x2x2_t __b)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u8 (uint8_t * __a, uint8x8x2_t __b)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u16 (uint16_t * __a, uint16x4x2_t __b)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u32 (uint32_t * __a, uint32x2x2_t __b)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v2si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_p8 (poly8_t * __a, poly8x8x2_t __b)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_p16 (poly16_t * __a, poly16x4x2_t __b)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10252,7 +11773,8 @@ vst2_p16 (poly16_t * __a, poly16x4x2_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_p64 (poly64_t * __a, poly64x1x2_t __b)
+ {
+   union { poly64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10260,35 +11782,40 @@ vst2_p64 (poly64_t * __a, poly64x1x2_t __b)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s64 (int64_t * __a, int64x1x2_t __b)
+ {
+   union { int64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u64 (uint64_t * __a, uint64x1x2_t __b)
+ {
+   union { uint64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_s8 (int8_t * __a, int8x16x2_t __b)
+ {
+   union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_s16 (int16_t * __a, int16x8x2_t __b)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_s32 (int32_t * __a, int32x4x2_t __b)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10296,7 +11823,8 @@ vst2q_s32 (int32_t * __a, int32x4x2_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_f16 (float16_t * __a, float16x8x2_t __b)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10304,63 +11832,72 @@ vst2q_f16 (float16_t * __a, float16x8x2_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_f32 (float32_t * __a, float32x4x2_t __b)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v4sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_u8 (uint8_t * __a, uint8x16x2_t __b)
+ {
+   union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_u16 (uint16_t * __a, uint16x8x2_t __b)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_u32 (uint32_t * __a, uint32x4x2_t __b)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v4si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_p8 (poly8_t * __a, poly8x16x2_t __b)
+ {
+   union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_p16 (poly16_t * __a, poly16x8x2_t __b)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_s8 (int8_t * __a, int8x8x2_t __b, const int __c)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_s16 (int16_t * __a, int16x4x2_t __b, const int __c)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_s32 (int32_t * __a, int32x2x2_t __b, const int __c)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10368,7 +11905,8 @@ vst2_lane_s32 (int32_t * __a, int32x2x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_f16 (float16_t * __a, float16x4x2_t __b, const int __c)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10376,56 +11914,64 @@ vst2_lane_f16 (float16_t * __a, float16x4x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_f32 (float32_t * __a, float32x2x2_t __b, const int __c)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_u8 (uint8_t * __a, uint8x8x2_t __b, const int __c)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_u16 (uint16_t * __a, uint16x4x2_t __b, const int __c)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_u32 (uint32_t * __a, uint32x2x2_t __b, const int __c)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_p8 (poly8_t * __a, poly8x8x2_t __b, const int __c)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_p16 (poly16_t * __a, poly16x4x2_t __b, const int __c)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_s16 (int16_t * __a, int16x8x2_t __b, const int __c)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_s32 (int32_t * __a, int32x4x2_t __b, const int __c)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10433,7 +11979,8 @@ vst2q_lane_s32 (int32_t * __a, int32x4x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_f16 (float16_t * __a, float16x8x2_t __b, const int __c)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10441,35 +11988,40 @@ vst2q_lane_f16 (float16_t * __a, float16x8x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_f32 (float32_t * __a, float32x4x2_t __b, const int __c)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_u16 (uint16_t * __a, uint16x8x2_t __b, const int __c)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_u32 (uint32_t * __a, uint32x4x2_t __b, const int __c)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_p16 (poly16_t * __a, poly16x8x2_t __b, const int __c)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s8 (const int8_t * __a)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10477,7 +12029,8 @@ vld3_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s16 (const int16_t * __a)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10485,7 +12038,8 @@ vld3_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s32 (const int32_t * __a)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10494,7 +12048,8 @@ vld3_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_f16 (const float16_t * __a)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10503,7 +12058,8 @@ vld3_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_f32 (const float32_t * __a)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10511,7 +12067,8 @@ vld3_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10519,7 +12076,8 @@ vld3_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10527,7 +12085,8 @@ vld3_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10535,7 +12094,8 @@ vld3_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10543,7 +12103,8 @@ vld3_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10553,7 +12114,8 @@ vld3_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10562,7 +12124,8 @@ vld3_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s64 (const int64_t * __a)
+ {
+   union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10570,7 +12133,8 @@ vld3_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10578,7 +12142,8 @@ vld3_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_s8 (const int8_t * __a)
+ {
+   union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10586,7 +12151,8 @@ vld3q_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_s16 (const int16_t * __a)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10594,7 +12160,8 @@ vld3q_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_s32 (const int32_t * __a)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10603,7 +12170,8 @@ vld3q_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_f16 (const float16_t * __a)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10612,7 +12180,8 @@ vld3q_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_f32 (const float32_t * __a)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10620,7 +12189,8 @@ vld3q_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_u8 (const uint8_t * __a)
+ {
+   union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10628,7 +12198,8 @@ vld3q_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_u16 (const uint16_t * __a)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10636,7 +12207,8 @@ vld3q_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_u32 (const uint32_t * __a)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10644,7 +12216,8 @@ vld3q_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_p8 (const poly8_t * __a)
+ {
+   union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10652,7 +12225,8 @@ vld3q_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_p16 (const poly16_t * __a)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10660,7 +12234,8 @@ vld3q_p16 (const poly16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_s8 (const int8_t * __a, int8x8x3_t __b, const int __c)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10669,7 +12244,8 @@ vld3_lane_s8 (const int8_t * __a, int8x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_s16 (const int16_t * __a, int16x4x3_t __b, const int __c)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10678,7 +12254,8 @@ vld3_lane_s16 (const int16_t * __a, int16x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_s32 (const int32_t * __a, int32x2x3_t __b, const int __c)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10688,7 +12265,8 @@ vld3_lane_s32 (const int32_t * __a, int32x2x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_f16 (const float16_t * __a, float16x4x3_t __b, const int __c)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10698,7 +12276,8 @@ vld3_lane_f16 (const float16_t * __a, float16x4x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_f32 (const float32_t * __a, float32x2x3_t __b, const int __c)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10707,7 +12286,8 @@ vld3_lane_f32 (const float32_t * __a, float32x2x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_u8 (const uint8_t * __a, uint8x8x3_t __b, const int __c)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10716,7 +12296,8 @@ vld3_lane_u8 (const uint8_t * __a, uint8x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_u16 (const uint16_t * __a, uint16x4x3_t __b, const int __c)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10725,7 +12306,8 @@ vld3_lane_u16 (const uint16_t * __a, uint16x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_u32 (const uint32_t * __a, uint32x2x3_t __b, const int __c)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10734,7 +12316,8 @@ vld3_lane_u32 (const uint32_t * __a, uint32x2x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_p8 (const poly8_t * __a, poly8x8x3_t __b, const int __c)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10743,7 +12326,8 @@ vld3_lane_p8 (const poly8_t * __a, poly8x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_p16 (const poly16_t * __a, poly16x4x3_t __b, const int __c)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10752,7 +12336,8 @@ vld3_lane_p16 (const poly16_t * __a, poly16x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_s16 (const int16_t * __a, int16x8x3_t __b, const int __c)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10761,7 +12346,8 @@ vld3q_lane_s16 (const int16_t * __a, int16x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_s32 (const int32_t * __a, int32x4x3_t __b, const int __c)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10771,7 +12357,8 @@ vld3q_lane_s32 (const int32_t * __a, int32x4x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_f16 (const float16_t * __a, float16x8x3_t __b, const int __c)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10781,7 +12368,8 @@ vld3q_lane_f16 (const float16_t * __a, float16x8x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_f32 (const float32_t * __a, float32x4x3_t __b, const int __c)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10790,7 +12378,8 @@ vld3q_lane_f32 (const float32_t * __a, float32x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_u16 (const uint16_t * __a, uint16x8x3_t __b, const int __c)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10799,7 +12388,8 @@ vld3q_lane_u16 (const uint16_t * __a, uint16x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_u32 (const uint32_t * __a, uint32x4x3_t __b, const int __c)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10808,7 +12398,8 @@ vld3q_lane_u32 (const uint32_t * __a, uint32x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_p16 (const poly16_t * __a, poly16x8x3_t __b, const int __c)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10817,7 +12408,8 @@ vld3q_lane_p16 (const poly16_t * __a, poly16x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s8 (const int8_t * __a)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10825,7 +12417,8 @@ vld3_dup_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s16 (const int16_t * __a)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10833,7 +12426,8 @@ vld3_dup_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s32 (const int32_t * __a)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10842,7 +12436,8 @@ vld3_dup_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_f16 (const float16_t * __a)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10851,7 +12446,8 @@ vld3_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_f32 (const float32_t * __a)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10859,7 +12455,8 @@ vld3_dup_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10867,7 +12464,8 @@ vld3_dup_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10875,7 +12473,8 @@ vld3_dup_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10883,7 +12482,8 @@ vld3_dup_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10891,7 +12491,8 @@ vld3_dup_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10901,7 +12502,8 @@ vld3_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10910,7 +12512,8 @@ vld3_dup_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s64 (const int64_t * __a)
+ {
+   union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10918,7 +12521,8 @@ vld3_dup_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10926,21 +12530,24 @@ vld3_dup_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s8 (int8_t * __a, int8x8x3_t __b)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s16 (int16_t * __a, int16x4x3_t __b)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s32 (int32_t * __a, int32x2x3_t __b)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10948,7 +12555,8 @@ vst3_s32 (int32_t * __a, int32x2x3_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_f16 (float16_t * __a, float16x4x3_t __b)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10956,42 +12564,48 @@ vst3_f16 (float16_t * __a, float16x4x3_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_f32 (float32_t * __a, float32x2x3_t __b)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u8 (uint8_t * __a, uint8x8x3_t __b)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u16 (uint16_t * __a, uint16x4x3_t __b)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u32 (uint32_t * __a, uint32x2x3_t __b)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v2si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_p8 (poly8_t * __a, poly8x8x3_t __b)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_p16 (poly16_t * __a, poly16x4x3_t __b)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11000,7 +12614,8 @@ vst3_p16 (poly16_t * __a, poly16x4x3_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_p64 (poly64_t * __a, poly64x1x3_t __b)
+ {
+   union { poly64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11008,35 +12623,40 @@ vst3_p64 (poly64_t * __a, poly64x1x3_t __b)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s64 (int64_t * __a, int64x1x3_t __b)
+ {
+   union { int64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u64 (uint64_t * __a, uint64x1x3_t __b)
+ {
+   union { uint64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_s8 (int8_t * __a, int8x16x3_t __b)
+ {
+   union { int8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_s16 (int16_t * __a, int16x8x3_t __b)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_s32 (int32_t * __a, int32x4x3_t __b)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11044,7 +12664,8 @@ vst3q_s32 (int32_t * __a, int32x4x3_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_f16 (float16_t * __a, float16x8x3_t __b)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11052,63 +12673,72 @@ vst3q_f16 (float16_t * __a, float16x8x3_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_f32 (float32_t * __a, float32x4x3_t __b)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v4sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_u8 (uint8_t * __a, uint8x16x3_t __b)
+ {
+   union { uint8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_u16 (uint16_t * __a, uint16x8x3_t __b)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_u32 (uint32_t * __a, uint32x4x3_t __b)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v4si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_p8 (poly8_t * __a, poly8x16x3_t __b)
+ {
+   union { poly8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_p16 (poly16_t * __a, poly16x8x3_t __b)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_s8 (int8_t * __a, int8x8x3_t __b, const int __c)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_s16 (int16_t * __a, int16x4x3_t __b, const int __c)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_s32 (int32_t * __a, int32x2x3_t __b, const int __c)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11116,7 +12746,8 @@ vst3_lane_s32 (int32_t * __a, int32x2x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_f16 (float16_t * __a, float16x4x3_t __b, const int __c)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11124,56 +12755,64 @@ vst3_lane_f16 (float16_t * __a, float16x4x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_f32 (float32_t * __a, float32x2x3_t __b, const int __c)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_u8 (uint8_t * __a, uint8x8x3_t __b, const int __c)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_u16 (uint16_t * __a, uint16x4x3_t __b, const int __c)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_u32 (uint32_t * __a, uint32x2x3_t __b, const int __c)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_p8 (poly8_t * __a, poly8x8x3_t __b, const int __c)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_p16 (poly16_t * __a, poly16x4x3_t __b, const int __c)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_s16 (int16_t * __a, int16x8x3_t __b, const int __c)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_s32 (int32_t * __a, int32x4x3_t __b, const int __c)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11181,7 +12820,8 @@ vst3q_lane_s32 (int32_t * __a, int32x4x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_f16 (float16_t * __a, float16x8x3_t __b, const int __c)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11189,35 +12829,40 @@ vst3q_lane_f16 (float16_t * __a, float16x8x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_f32 (float32_t * __a, float32x4x3_t __b, const int __c)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_u16 (uint16_t * __a, uint16x8x3_t __b, const int __c)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_u32 (uint32_t * __a, uint32x4x3_t __b, const int __c)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_p16 (poly16_t * __a, poly16x8x3_t __b, const int __c)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s8 (const int8_t * __a)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11225,7 +12870,8 @@ vld4_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s16 (const int16_t * __a)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11233,7 +12879,8 @@ vld4_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s32 (const int32_t * __a)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11242,7 +12889,8 @@ vld4_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_f16 (const float16_t * __a)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11251,7 +12899,8 @@ vld4_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_f32 (const float32_t * __a)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11259,7 +12908,8 @@ vld4_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11267,7 +12917,8 @@ vld4_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11275,7 +12926,8 @@ vld4_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11283,7 +12935,8 @@ vld4_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11291,7 +12944,8 @@ vld4_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11301,7 +12955,8 @@ vld4_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11310,7 +12965,8 @@ vld4_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s64 (const int64_t * __a)
+ {
+   union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11318,7 +12974,8 @@ vld4_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11326,7 +12983,8 @@ vld4_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_s8 (const int8_t * __a)
+ {
+   union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11334,7 +12992,8 @@ vld4q_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_s16 (const int16_t * __a)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11342,7 +13001,8 @@ vld4q_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_s32 (const int32_t * __a)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11351,7 +13011,8 @@ vld4q_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_f16 (const float16_t * __a)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11360,7 +13021,8 @@ vld4q_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_f32 (const float32_t * __a)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11368,7 +13030,8 @@ vld4q_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_u8 (const uint8_t * __a)
+ {
+   union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11376,7 +13039,8 @@ vld4q_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_u16 (const uint16_t * __a)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11384,7 +13048,8 @@ vld4q_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_u32 (const uint32_t * __a)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11392,7 +13057,8 @@ vld4q_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_p8 (const poly8_t * __a)
+ {
+   union { poly8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11400,7 +13066,8 @@ vld4q_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_p16 (const poly16_t * __a)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11408,7 +13075,8 @@ vld4q_p16 (const poly16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_s8 (const int8_t * __a, int8x8x4_t __b, const int __c)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11417,7 +13085,8 @@ vld4_lane_s8 (const int8_t * __a, int8x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_s16 (const int16_t * __a, int16x4x4_t __b, const int __c)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11426,7 +13095,8 @@ vld4_lane_s16 (const int16_t * __a, int16x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_s32 (const int32_t * __a, int32x2x4_t __b, const int __c)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11436,7 +13106,8 @@ vld4_lane_s32 (const int32_t * __a, int32x2x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_f16 (const float16_t * __a, float16x4x4_t __b, const int __c)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11447,7 +13118,8 @@ vld4_lane_f16 (const float16_t * __a, float16x4x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_f32 (const float32_t * __a, float32x2x4_t __b, const int __c)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11456,7 +13128,8 @@ vld4_lane_f32 (const float32_t * __a, float32x2x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_u8 (const uint8_t * __a, uint8x8x4_t __b, const int __c)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11465,7 +13138,8 @@ vld4_lane_u8 (const uint8_t * __a, uint8x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_u16 (const uint16_t * __a, uint16x4x4_t __b, const int __c)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11474,7 +13148,8 @@ vld4_lane_u16 (const uint16_t * __a, uint16x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_u32 (const uint32_t * __a, uint32x2x4_t __b, const int __c)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11483,7 +13158,8 @@ vld4_lane_u32 (const uint32_t * __a, uint32x2x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_p8 (const poly8_t * __a, poly8x8x4_t __b, const int __c)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11492,7 +13168,8 @@ vld4_lane_p8 (const poly8_t * __a, poly8x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_p16 (const poly16_t * __a, poly16x4x4_t __b, const int __c)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11501,7 +13178,8 @@ vld4_lane_p16 (const poly16_t * __a, poly16x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_s16 (const int16_t * __a, int16x8x4_t __b, const int __c)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11510,7 +13188,8 @@ vld4q_lane_s16 (const int16_t * __a, int16x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_s32 (const int32_t * __a, int32x4x4_t __b, const int __c)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11520,7 +13199,8 @@ vld4q_lane_s32 (const int32_t * __a, int32x4x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_f16 (const float16_t * __a, float16x8x4_t __b, const int __c)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11531,7 +13211,8 @@ vld4q_lane_f16 (const float16_t * __a, float16x8x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_f32 (const float32_t * __a, float32x4x4_t __b, const int __c)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11540,7 +13221,8 @@ vld4q_lane_f32 (const float32_t * __a, float32x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_u16 (const uint16_t * __a, uint16x8x4_t __b, const int __c)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11549,7 +13231,8 @@ vld4q_lane_u16 (const uint16_t * __a, uint16x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_u32 (const uint32_t * __a, uint32x4x4_t __b, const int __c)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11558,7 +13241,8 @@ vld4q_lane_u32 (const uint32_t * __a, uint32x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_p16 (const poly16_t * __a, poly16x8x4_t __b, const int __c)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11567,7 +13251,8 @@ vld4q_lane_p16 (const poly16_t * __a, poly16x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s8 (const int8_t * __a)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11575,7 +13260,8 @@ vld4_dup_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s16 (const int16_t * __a)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11583,7 +13269,8 @@ vld4_dup_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s32 (const int32_t * __a)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11592,7 +13279,8 @@ vld4_dup_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_f16 (const float16_t * __a)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11601,7 +13289,8 @@ vld4_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_f32 (const float32_t * __a)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11609,7 +13298,8 @@ vld4_dup_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11617,7 +13307,8 @@ vld4_dup_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11625,7 +13316,8 @@ vld4_dup_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11633,7 +13325,8 @@ vld4_dup_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11641,7 +13334,8 @@ vld4_dup_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11651,7 +13345,8 @@ vld4_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11660,7 +13355,8 @@ vld4_dup_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s64 (const int64_t * __a)
+ {
+   union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11668,7 +13364,8 @@ vld4_dup_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11676,21 +13373,24 @@ vld4_dup_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s8 (int8_t * __a, int8x8x4_t __b)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s16 (int16_t * __a, int16x4x4_t __b)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s32 (int32_t * __a, int32x2x4_t __b)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11698,7 +13398,8 @@ vst4_s32 (int32_t * __a, int32x2x4_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_f16 (float16_t * __a, float16x4x4_t __b)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11706,42 +13407,48 @@ vst4_f16 (float16_t * __a, float16x4x4_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_f32 (float32_t * __a, float32x2x4_t __b)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u8 (uint8_t * __a, uint8x8x4_t __b)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u16 (uint16_t * __a, uint16x4x4_t __b)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u32 (uint32_t * __a, uint32x2x4_t __b)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v2si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_p8 (poly8_t * __a, poly8x8x4_t __b)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_p16 (poly16_t * __a, poly16x4x4_t __b)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11750,7 +13457,8 @@ vst4_p16 (poly16_t * __a, poly16x4x4_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_p64 (poly64_t * __a, poly64x1x4_t __b)
+ {
+   union { poly64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11758,35 +13466,40 @@ vst4_p64 (poly64_t * __a, poly64x1x4_t __b)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s64 (int64_t * __a, int64x1x4_t __b)
+ {
+   union { int64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u64 (uint64_t * __a, uint64x1x4_t __b)
+ {
+   union { uint64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_s8 (int8_t * __a, int8x16x4_t __b)
+ {
+   union { int8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_s16 (int16_t * __a, int16x8x4_t __b)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_s32 (int32_t * __a, int32x4x4_t __b)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11794,7 +13507,8 @@ vst4q_s32 (int32_t * __a, int32x4x4_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_f16 (float16_t * __a, float16x8x4_t __b)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11802,63 +13516,72 @@ vst4q_f16 (float16_t * __a, float16x8x4_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_f32 (float32_t * __a, float32x4x4_t __b)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v4sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_u8 (uint8_t * __a, uint8x16x4_t __b)
+ {
+   union { uint8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_u16 (uint16_t * __a, uint16x8x4_t __b)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_u32 (uint32_t * __a, uint32x4x4_t __b)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v4si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_p8 (poly8_t * __a, poly8x16x4_t __b)
+ {
+   union { poly8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_p16 (poly16_t * __a, poly16x8x4_t __b)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_s8 (int8_t * __a, int8x8x4_t __b, const int __c)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_s16 (int16_t * __a, int16x4x4_t __b, const int __c)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_s32 (int32_t * __a, int32x2x4_t __b, const int __c)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11866,7 +13589,8 @@ vst4_lane_s32 (int32_t * __a, int32x2x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_f16 (float16_t * __a, float16x4x4_t __b, const int __c)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11874,56 +13598,64 @@ vst4_lane_f16 (float16_t * __a, float16x4x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_f32 (float32_t * __a, float32x2x4_t __b, const int __c)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_u8 (uint8_t * __a, uint8x8x4_t __b, const int __c)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_u16 (uint16_t * __a, uint16x4x4_t __b, const int __c)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_u32 (uint32_t * __a, uint32x2x4_t __b, const int __c)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_p8 (poly8_t * __a, poly8x8x4_t __b, const int __c)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_p16 (poly16_t * __a, poly16x4x4_t __b, const int __c)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_s16 (int16_t * __a, int16x8x4_t __b, const int __c)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_s32 (int32_t * __a, int32x4x4_t __b, const int __c)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11931,7 +13663,8 @@ vst4q_lane_s32 (int32_t * __a, int32x4x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_f16 (float16_t * __a, float16x8x4_t __b, const int __c)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11939,529 +13672,616 @@ vst4q_lane_f16 (float16_t * __a, float16x8x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_f32 (float32_t * __a, float32x4x4_t __b, const int __c)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_u16 (uint16_t * __a, uint16x8x4_t __b, const int __c)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_u32 (uint32_t * __a, uint32x4x4_t __b, const int __c)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_p16 (poly16_t * __a, poly16x8x4_t __b, const int __c)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_p16 (poly16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f16 (float16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f32 (float32x2_t __a)
+ {
+   return (poly8x8_t)__a;
+@@ -12469,76 +14289,88 @@ vreinterpret_p8_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_p64 (poly64x1_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s64 (int64x1_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u64 (uint64x1_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s8 (int8x8_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s16 (int16x4_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s32 (int32x2_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u8 (uint8x8_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u16 (uint16x4_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u32 (uint32x2_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_p8 (poly8x8_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f16 (float16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f32 (float32x2_t __a)
+ {
+   return (poly16x4_t)__a;
+@@ -12546,63 +14378,73 @@ vreinterpret_p16_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_p64 (poly64x1_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s64 (int64x1_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u64 (uint64x1_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s8 (int8x8_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s16 (int16x4_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s32 (int32x2_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u8 (uint8x8_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u16 (uint16x4_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u32 (uint32x2_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p8 (poly8x8_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12610,7 +14452,8 @@ vreinterpret_f16_p8 (poly8x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p16 (poly16x4_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12618,7 +14461,8 @@ vreinterpret_f16_p16 (poly16x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_f32 (float32x2_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12628,7 +14472,8 @@ vreinterpret_f16_f32 (float32x2_t __a)
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p64 (poly64x1_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12637,7 +14482,8 @@ vreinterpret_f16_p64 (poly64x1_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s64 (int64x1_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12645,7 +14491,8 @@ vreinterpret_f16_s64 (int64x1_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u64 (uint64x1_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12653,7 +14500,8 @@ vreinterpret_f16_u64 (uint64x1_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s8 (int8x8_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12661,7 +14509,8 @@ vreinterpret_f16_s8 (int8x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s16 (int16x4_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12669,7 +14518,8 @@ vreinterpret_f16_s16 (int16x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s32 (int32x2_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12677,7 +14527,8 @@ vreinterpret_f16_s32 (int32x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u8 (uint8x8_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12685,7 +14536,8 @@ vreinterpret_f16_u8 (uint8x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u16 (uint16x4_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12693,27 +14545,31 @@ vreinterpret_f16_u16 (uint16x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u32 (uint32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p8 (poly8x8_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p16 (poly16x4_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_f16 (float16x4_t __a)
+ {
+   return (float32x2_t) __a;
+@@ -12722,56 +14578,65 @@ vreinterpret_f32_f16 (float16x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p64 (poly64x1_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s64 (int64x1_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u64 (uint64x1_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s8 (int8x8_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s16 (int16x4_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s32 (int32x2_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u8 (uint8x8_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u16 (uint16x4_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u32 (uint32x2_t __a)
+ {
+   return (float32x2_t)__a;
+@@ -12779,102 +14644,118 @@ vreinterpret_f32_u32 (uint32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_p8 (poly8x8_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_p16 (poly16x4_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_f16 (float16x4_t __a)
+ {
+   return (poly64x1_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_f32 (float32x2_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s64 (int64x1_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u64 (uint64x1_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s8 (int8x8_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s16 (int16x4_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s32 (int32x2_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u8 (uint8x8_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u16 (uint16x4_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u32 (uint32x2_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p8 (poly8x8_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p16 (poly16x4_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f16 (float16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f32 (float32x2_t __a)
+ {
+   return (int64x1_t)__a;
+@@ -12882,76 +14763,88 @@ vreinterpret_s64_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p64 (poly64x1_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u64 (uint64x1_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s8 (int8x8_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s16 (int16x4_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s32 (int32x2_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u8 (uint8x8_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u16 (uint16x4_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u32 (uint32x2_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p8 (poly8x8_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p16 (poly16x4_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f16 (float16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f32 (float32x2_t __a)
+ {
+   return (uint64x1_t)__a;
+@@ -12959,76 +14852,88 @@ vreinterpret_u64_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p64 (poly64x1_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s64 (int64x1_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s8 (int8x8_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s16 (int16x4_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s32 (int32x2_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u8 (uint8x8_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u16 (uint16x4_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u32 (uint32x2_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p8 (poly8x8_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p16 (poly16x4_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f16 (float16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f32 (float32x2_t __a)
+ {
+   return (int8x8_t)__a;
+@@ -13036,76 +14941,88 @@ vreinterpret_s8_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p64 (poly64x1_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s64 (int64x1_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u64 (uint64x1_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s16 (int16x4_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s32 (int32x2_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u8 (uint8x8_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u16 (uint16x4_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u32 (uint32x2_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p8 (poly8x8_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p16 (poly16x4_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f16 (float16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f32 (float32x2_t __a)
+ {
+   return (int16x4_t)__a;
+@@ -13113,76 +15030,88 @@ vreinterpret_s16_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p64 (poly64x1_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s64 (int64x1_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u64 (uint64x1_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s8 (int8x8_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s32 (int32x2_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u8 (uint8x8_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u16 (uint16x4_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u32 (uint32x2_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p8 (poly8x8_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p16 (poly16x4_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f16 (float16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f32 (float32x2_t __a)
+ {
+   return (int32x2_t)__a;
+@@ -13190,76 +15119,88 @@ vreinterpret_s32_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p64 (poly64x1_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s64 (int64x1_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u64 (uint64x1_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s8 (int8x8_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s16 (int16x4_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u8 (uint8x8_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u16 (uint16x4_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u32 (uint32x2_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p8 (poly8x8_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p16 (poly16x4_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f16 (float16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f32 (float32x2_t __a)
+ {
+   return (uint8x8_t)__a;
+@@ -13267,76 +15208,88 @@ vreinterpret_u8_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p64 (poly64x1_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s64 (int64x1_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u64 (uint64x1_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s8 (int8x8_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s16 (int16x4_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s32 (int32x2_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u16 (uint16x4_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u32 (uint32x2_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p8 (poly8x8_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p16 (poly16x4_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f16 (float16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f32 (float32x2_t __a)
+ {
+   return (uint16x4_t)__a;
+@@ -13344,76 +15297,88 @@ vreinterpret_u16_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p64 (poly64x1_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s64 (int64x1_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u64 (uint64x1_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s8 (int8x8_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s16 (int16x4_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s32 (int32x2_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u8 (uint8x8_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u32 (uint32x2_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p8 (poly8x8_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p16 (poly16x4_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f16 (float16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f32 (float32x2_t __a)
+ {
+   return (uint32x2_t)__a;
+@@ -13421,70 +15386,81 @@ vreinterpret_u32_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p64 (poly64x1_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s64 (int64x1_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u64 (uint64x1_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s8 (int8x8_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s16 (int16x4_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s32 (int32x2_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u8 (uint8x8_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u16 (uint16x4_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p16 (poly16x8_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f16 (float16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f32 (float32x4_t __a)
+ {
+   return (poly8x16_t)__a;
+@@ -13492,83 +15468,96 @@ vreinterpretq_p8_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p64 (poly64x2_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p128 (poly128_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s64 (int64x2_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u64 (uint64x2_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s8 (int8x16_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s16 (int16x8_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s32 (int32x4_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u8 (uint8x16_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u16 (uint16x8_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u32 (uint32x4_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p8 (poly8x16_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f16 (float16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f32 (float32x4_t __a)
+ {
+   return (poly16x8_t)__a;
+@@ -13576,69 +15565,80 @@ vreinterpretq_p16_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p64 (poly64x2_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p128 (poly128_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s64 (int64x2_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u64 (uint64x2_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s8 (int8x16_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s16 (int16x8_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s32 (int32x4_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u8 (uint8x16_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u16 (uint16x8_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u32 (uint32x4_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p8 (poly8x16_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13646,7 +15646,8 @@ vreinterpretq_f16_p8 (poly8x16_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p16 (poly16x8_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13654,7 +15655,8 @@ vreinterpretq_f16_p16 (poly16x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_f32 (float32x4_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13665,7 +15667,8 @@ vreinterpretq_f16_f32 (float32x4_t __a)
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p64 (poly64x2_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13673,7 +15676,8 @@ vreinterpretq_f16_p64 (poly64x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p128 (poly128_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13683,7 +15687,8 @@ vreinterpretq_f16_p128 (poly128_t __a)
+ #pragma GCC pop_options
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s64 (int64x2_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13691,7 +15696,8 @@ vreinterpretq_f16_s64 (int64x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u64 (uint64x2_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13699,7 +15705,8 @@ vreinterpretq_f16_u64 (uint64x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s8 (int8x16_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13707,7 +15714,8 @@ vreinterpretq_f16_s8 (int8x16_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s16 (int16x8_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13715,7 +15723,8 @@ vreinterpretq_f16_s16 (int16x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s32 (int32x4_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13723,7 +15732,8 @@ vreinterpretq_f16_s32 (int32x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u8 (uint8x16_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13731,7 +15741,8 @@ vreinterpretq_f16_u8 (uint8x16_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u16 (uint16x8_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13739,27 +15750,31 @@ vreinterpretq_f16_u16 (uint16x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u32 (uint32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p8 (poly8x16_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p16 (poly16x8_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_f16 (float16x8_t __a)
+ {
+   return (float32x4_t) __a;
+@@ -13768,62 +15783,72 @@ vreinterpretq_f32_f16 (float16x8_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p64 (poly64x2_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p128 (poly128_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s64 (int64x2_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u64 (uint64x2_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s8 (int8x16_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s16 (int16x8_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s32 (int32x4_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u8 (uint8x16_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u16 (uint16x8_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u32 (uint32x4_t __a)
+ {
+   return (float32x4_t)__a;
+@@ -13831,188 +15856,218 @@ vreinterpretq_f32_u32 (uint32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_p8 (poly8x16_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_p16 (poly16x8_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_f16 (float16x8_t __a)
+ {
+   return (poly64x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_f32 (float32x4_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_p128 (poly128_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s64 (int64x2_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u64 (uint64x2_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s8 (int8x16_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s16 (int16x8_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s32 (int32x4_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u8 (uint8x16_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u16 (uint16x8_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u32 (uint32x4_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_p8 (poly8x16_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_p16 (poly16x8_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_f16 (float16x8_t __a)
+ {
+   return (poly128_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_f32 (float32x4_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_p64 (poly64x2_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s64 (int64x2_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u64 (uint64x2_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s8 (int8x16_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s16 (int16x8_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s32 (int32x4_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u8 (uint8x16_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u16 (uint16x8_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u32 (uint32x4_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p8 (poly8x16_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p16 (poly16x8_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f16 (float16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f32 (float32x4_t __a)
+ {
+   return (int64x2_t)__a;
+@@ -14020,82 +16075,95 @@ vreinterpretq_s64_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p64 (poly64x2_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p128 (poly128_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u64 (uint64x2_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s8 (int8x16_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s16 (int16x8_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s32 (int32x4_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u8 (uint8x16_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u16 (uint16x8_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u32 (uint32x4_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p8 (poly8x16_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p16 (poly16x8_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f16 (float16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f32 (float32x4_t __a)
+ {
+   return (uint64x2_t)__a;
+@@ -14103,82 +16171,95 @@ vreinterpretq_u64_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p64 (poly64x2_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p128 (poly128_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s64 (int64x2_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s8 (int8x16_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s16 (int16x8_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s32 (int32x4_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u8 (uint8x16_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u16 (uint16x8_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u32 (uint32x4_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p8 (poly8x16_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p16 (poly16x8_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f16 (float16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f32 (float32x4_t __a)
+ {
+   return (int8x16_t)__a;
+@@ -14186,82 +16267,95 @@ vreinterpretq_s8_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p64 (poly64x2_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p128 (poly128_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s64 (int64x2_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u64 (uint64x2_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s16 (int16x8_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s32 (int32x4_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u8 (uint8x16_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u16 (uint16x8_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u32 (uint32x4_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p8 (poly8x16_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p16 (poly16x8_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f16 (float16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f32 (float32x4_t __a)
+ {
+   return (int16x8_t)__a;
+@@ -14269,82 +16363,95 @@ vreinterpretq_s16_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p64 (poly64x2_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p128 (poly128_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s64 (int64x2_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u64 (uint64x2_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s8 (int8x16_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s32 (int32x4_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u8 (uint8x16_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u16 (uint16x8_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u32 (uint32x4_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p8 (poly8x16_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p16 (poly16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f16 (float16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ #endif
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f32 (float32x4_t __a)
+ {
+   return (int32x4_t)__a;
+@@ -14352,82 +16459,95 @@ vreinterpretq_s32_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p64 (poly64x2_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p128 (poly128_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s64 (int64x2_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u64 (uint64x2_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s8 (int8x16_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s16 (int16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u8 (uint8x16_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u16 (uint16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u32 (uint32x4_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p8 (poly8x16_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p16 (poly16x8_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f16 (float16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f32 (float32x4_t __a)
+ {
+   return (uint8x16_t)__a;
+@@ -14435,82 +16555,95 @@ vreinterpretq_u8_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p64 (poly64x2_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p128 (poly128_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s64 (int64x2_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u64 (uint64x2_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s8 (int8x16_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s16 (int16x8_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s32 (int32x4_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u16 (uint16x8_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u32 (uint32x4_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p8 (poly8x16_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p16 (poly16x8_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f16 (float16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f32 (float32x4_t __a)
+ {
+   return (uint16x8_t)__a;
+@@ -14518,82 +16651,95 @@ vreinterpretq_u16_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p64 (poly64x2_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p128 (poly128_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s64 (int64x2_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u64 (uint64x2_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s8 (int8x16_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s16 (int16x8_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s32 (int32x4_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u8 (uint8x16_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u32 (uint32x4_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p8 (poly8x16_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p16 (poly16x8_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f16 (float16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f32 (float32x4_t __a)
+ {
+   return (uint32x4_t)__a;
+@@ -14601,56 +16747,65 @@ vreinterpretq_u32_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p64 (poly64x2_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p128 (poly128_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s64 (int64x2_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u64 (uint64x2_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s8 (int8x16_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s16 (int16x8_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s32 (int32x4_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u8 (uint8x16_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u16 (uint16x8_t __a)
+ {
+   return (uint32x4_t)__a;
+@@ -14659,7 +16814,8 @@ vreinterpretq_u32_u16 (uint16x8_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vldrq_p128 (poly128_t const * __ptr)
+ {
+ #ifdef __ARM_BIG_ENDIAN
+@@ -14672,7 +16828,8 @@ vldrq_p128 (poly128_t const * __ptr)
+ #endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vstrq_p128 (poly128_t * __ptr, poly128_t __val)
+ {
+ #ifdef __ARM_BIG_ENDIAN
+@@ -14695,7 +16852,8 @@ vstrq_p128 (poly128_t * __ptr, poly128_t __val)
+    If the result is all zeroes for any half then the whole result is zeroes.
+    This is what the pairwise min reduction achieves.  */
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_p64 (poly64x1_t __a, poly64x1_t __b)
+ {
+   uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+@@ -14710,7 +16868,8 @@ vceq_p64 (poly64x1_t __a, poly64x1_t __b)
+    a reduction with max since if any two corresponding bits
+    in the two poly64_t's match, then the whole result must be all ones.  */
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_p64 (poly64x1_t __a, poly64x1_t __b)
+ {
+   uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+@@ -14720,31 +16879,36 @@ vtst_p64 (poly64x1_t __a, poly64x1_t __b)
+   return vreinterpret_u64_u32 (__m);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaeseq_u8 (uint8x16_t __data, uint8x16_t __key)
+ {
+   return __builtin_arm_crypto_aese (__data, __key);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaesdq_u8 (uint8x16_t __data, uint8x16_t __key)
+ {
+   return __builtin_arm_crypto_aesd (__data, __key);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaesmcq_u8 (uint8x16_t __data)
+ {
+   return __builtin_arm_crypto_aesmc (__data);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaesimcq_u8 (uint8x16_t __data)
+ {
+   return __builtin_arm_crypto_aesimc (__data);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1h_u32 (uint32_t __hash_e)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14753,7 +16917,8 @@ vsha1h_u32 (uint32_t __hash_e)
+   return vgetq_lane_u32 (__t, 0);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1cq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14761,7 +16926,8 @@ vsha1cq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+   return __builtin_arm_crypto_sha1c (__hash_abcd, __t, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1pq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14769,7 +16935,8 @@ vsha1pq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+   return __builtin_arm_crypto_sha1p (__hash_abcd, __t, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1mq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14777,49 +16944,57 @@ vsha1mq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+   return __builtin_arm_crypto_sha1m (__hash_abcd, __t, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7, uint32x4_t __w8_11)
+ {
+   return __builtin_arm_crypto_sha1su0 (__w0_3, __w4_7, __w8_11);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w12_15)
+ {
+   return __builtin_arm_crypto_sha1su1 (__tw0_3, __w12_15);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256hq_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+ {
+   return __builtin_arm_crypto_sha256h (__hash_abcd, __hash_efgh, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256h2q_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+ {
+   return __builtin_arm_crypto_sha256h2 (__hash_abcd, __hash_efgh, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7)
+ {
+   return __builtin_arm_crypto_sha256su0 (__w0_3, __w4_7);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15)
+ {
+   return __builtin_arm_crypto_sha256su1 (__tw0_3, __w8_11, __w12_15);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_p64 (poly64_t __a, poly64_t __b)
+ {
+   return (poly128_t) __builtin_arm_crypto_vmullp64 ((uint64_t) __a, (uint64_t) __b);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
+ {
+   poly64_t __t1 = vget_high_p64 (__a);
+@@ -14830,6 +17005,984 @@ vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
+ 
+ #pragma GCC pop_options
+ 
++  /* Intrinsics for FP16 instructions.  */
++#pragma GCC push_options
++#pragma GCC target ("fpu=neon-fp-armv8")
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vabdv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vabdv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vabsv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vabsv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vadd_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vaddv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vaddq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vaddv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcagev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcagev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcagtv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcagtv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcalev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcalev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcaltv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcaltv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vceqv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vceqv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vceqzv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vceqzv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcgev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcgev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcgezv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcgezv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcgtv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcgtv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcgtzv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcgtzv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vclev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vclev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vclezv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vclezv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcltv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcltv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcltzv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcltzv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_s16 (int16x4_t __a)
++{
++  return (float16x4_t)__builtin_neon_vcvtsv4hi (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_u16 (uint16x4_t __a)
++{
++  return (float16x4_t)__builtin_neon_vcvtuv4hi ((int16x4_t)__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s16_f16 (float16x4_t __a)
++{
++  return (int16x4_t)__builtin_neon_vcvtsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtuv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_s16 (int16x8_t __a)
++{
++  return (float16x8_t)__builtin_neon_vcvtsv8hi (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_u16 (uint16x8_t __a)
++{
++  return (float16x8_t)__builtin_neon_vcvtuv8hi ((int16x8_t)__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s16_f16 (float16x8_t __a)
++{
++  return (int16x8_t)__builtin_neon_vcvtsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtuv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtasv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtauv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtasv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtauv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtmsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtmuv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtmsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtmuv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtnsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtnuv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtnsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtnuv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtpsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtpuv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtpsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtpuv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_s16 (int16x4_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv4hi (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_u16 (uint16x4_t __a, const int __b)
++{
++  return __builtin_neon_vcvtu_nv4hi ((int16x4_t)__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_s16 (int16x8_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv8hi (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_u16 (uint16x8_t __a, const int __b)
++{
++  return __builtin_neon_vcvtu_nv8hi ((int16x8_t)__a, __b);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s16_f16 (float16x4_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u16_f16 (float16x4_t __a, const int __b)
++{
++  return (uint16x4_t)__builtin_neon_vcvtu_nv4hf (__a, __b);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s16_f16 (float16x8_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u16_f16 (float16x8_t __a, const int __b)
++{
++  return (uint16x8_t)__builtin_neon_vcvtu_nv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_neon_vfmav4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_neon_vfmav8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_neon_vfmsv4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_neon_vfmsv8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vmaxfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vmaxfv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vmaxnmv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vmaxnmv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vminfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vminfv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vminnmv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vminnmv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vmulfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f16 (float16x4_t __a, float16x4_t __b, const int __c)
++{
++  return __builtin_neon_vmul_lanev4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f16 (float16x4_t __a, float16_t __b)
++{
++  return __builtin_neon_vmul_nv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vmulfv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __c)
++{
++  return __builtin_neon_vmul_lanev8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f16 (float16x8_t __a, float16_t __b)
++{
++  return __builtin_neon_vmul_nv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vnegv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vnegv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vpaddv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vpmaxfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vpminfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrecpev4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrecpev8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndav4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndav8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndmv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndmv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndnv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndnv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndpv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndpv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndxv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndxv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrsqrtev4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrsqrtev8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vrecpsv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vrecpsv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vrsqrtsv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vrsqrtsv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vsub_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vsubv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vsubq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vsubv8hf (__a, __b);
++}
++
++#endif /* __ARM_FEATURE_VECTOR_FP16_ARITHMETIC.  */
++#pragma GCC pop_options
++
++  /* Half-precision data processing intrinsics.  */
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f16 (uint16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_neon_vbslv4hf ((int16x4_t)__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f16 (uint16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_neon_vbslv8hf ((int16x8_t)__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f16 (float16x4_t __a, const int __b)
++{
++  return __builtin_neon_vdup_lanev4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f16 (float16x4_t __a, const int __b)
++{
++  return __builtin_neon_vdup_lanev8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f16 (float16x4_t __a, float16x4_t __b, const int __c)
++{
++  return __builtin_neon_vextv4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f16 (float16x8_t __a, float16x8_t __b, const int __c)
++{
++  return __builtin_neon_vextv8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_f16 (float16x4_t __a)
++{
++  return (float16x4_t)__builtin_shuffle (__a, (uint16x4_t){ 3, 2, 1, 0 });
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_f16 (float16x8_t __a)
++{
++  return
++    (float16x8_t)__builtin_shuffle (__a,
++				    (uint16x8_t){ 3, 2, 1, 0, 7, 6, 5, 4 });
++}
++
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_f16 (float16x4_t __a, float16x4_t __b)
++{
++  float16x4x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 5, 1, 7, 3 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 4, 0, 6, 2 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 0, 4, 2, 6 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 1, 5, 3, 7 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  float16x8x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 9, 1, 11, 3, 13, 5, 15, 7 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 8, 0, 10, 2, 12, 4, 14, 6 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 0, 8, 2, 10, 4, 12, 6, 14 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 1, 9, 3, 11, 5, 13, 7, 15 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp_f16 (float16x4_t __a, float16x4_t __b)
++{
++  float16x4x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 5, 7, 1, 3 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 4, 6, 0, 2 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 0, 2, 4, 6 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 1, 3, 5, 7 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vuzpq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  float16x8x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 5, 7, 1, 3, 13, 15, 9, 11 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 4, 6, 0, 2, 12, 14, 8, 10 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 0, 2, 4, 6, 8, 10, 12, 14 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 1, 3, 5, 7, 9, 11, 13, 15 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vzip_f16 (float16x4_t __a, float16x4_t __b)
++{
++  float16x4x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 6, 2, 7, 3 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 4, 0, 5, 1 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 0, 4, 1, 5 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 2, 6, 3, 7 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vzipq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  float16x8x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 10, 2, 11, 3, 8, 0, 9, 1 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 14, 6, 15, 7, 12, 4, 13, 5 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 0, 8, 1, 9, 2, 10, 3, 11 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 4, 12, 5, 13, 6, 14, 7, 15 });
++#endif
++  return __rv;
++}
++
++#endif
++
+ #ifdef __cplusplus
+ }
+ #endif
+--- a/src/gcc/config/arm/arm_neon_builtins.def
++++ b/src/gcc/config/arm/arm_neon_builtins.def
+@@ -19,6 +19,7 @@
+    <http://www.gnu.org/licenses/>.  */
+ 
+ VAR2 (BINOP, vadd, v2sf, v4sf)
++VAR2 (BINOP, vadd, v8hf, v4hf)
+ VAR3 (BINOP, vaddls, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vaddlu, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vaddws, v8qi, v4hi, v2si)
+@@ -32,12 +33,15 @@ VAR8 (BINOP, vqaddu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR3 (BINOP, vaddhn, v8hi, v4si, v2di)
+ VAR3 (BINOP, vraddhn, v8hi, v4si, v2di)
+ VAR2 (BINOP, vmulf, v2sf, v4sf)
++VAR2 (BINOP, vmulf, v8hf, v4hf)
+ VAR2 (BINOP, vmulp, v8qi, v16qi)
+ VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR3 (TERNOP, vmlals, v8qi, v4hi, v2si)
+ VAR3 (TERNOP, vmlalu, v8qi, v4hi, v2si)
+ VAR2 (TERNOP, vfma, v2sf, v4sf)
++VAR2 (TERNOP, vfma, v4hf, v8hf)
+ VAR2 (TERNOP, vfms, v2sf, v4sf)
++VAR2 (TERNOP, vfms, v4hf, v8hf)
+ VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR3 (TERNOP, vmlsls, v8qi, v4hi, v2si)
+ VAR3 (TERNOP, vmlslu, v8qi, v4hi, v2si)
+@@ -94,6 +98,7 @@ VAR8 (TERNOP_IMM, vsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (TERNOP_IMM, vrsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (TERNOP_IMM, vrsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR2 (BINOP, vsub, v2sf, v4sf)
++VAR2 (BINOP, vsub, v8hf, v4hf)
+ VAR3 (BINOP, vsubls, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vsublu, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vsubws, v8qi, v4hi, v2si)
+@@ -111,12 +116,27 @@ VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vcage, v2sf, v4sf)
+ VAR2 (BINOP, vcagt, v2sf, v4sf)
++VAR2 (BINOP, vcage, v4hf, v8hf)
++VAR2 (BINOP, vcagt, v4hf, v8hf)
++VAR2 (BINOP, vcale, v4hf, v8hf)
++VAR2 (BINOP, vcalt, v4hf, v8hf)
++VAR2 (BINOP, vceq, v4hf, v8hf)
++VAR2 (BINOP, vcge, v4hf, v8hf)
++VAR2 (BINOP, vcgt, v4hf, v8hf)
++VAR2 (BINOP, vcle, v4hf, v8hf)
++VAR2 (BINOP, vclt, v4hf, v8hf)
++VAR2 (UNOP, vceqz, v4hf, v8hf)
++VAR2 (UNOP, vcgez, v4hf, v8hf)
++VAR2 (UNOP, vcgtz, v4hf, v8hf)
++VAR2 (UNOP, vclez, v4hf, v8hf)
++VAR2 (UNOP, vcltz, v4hf, v8hf)
+ VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vabds, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vabdu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vabdf, v2sf, v4sf)
+ VAR3 (BINOP, vabdls, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vabdlu, v8qi, v4hi, v2si)
++VAR2 (BINOP, vabd, v8hf, v4hf)
+ 
+ VAR6 (TERNOP, vabas, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (TERNOP, vabau, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+@@ -126,27 +146,38 @@ VAR3 (TERNOP, vabalu, v8qi, v4hi, v2si)
+ VAR6 (BINOP, vmaxs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vmaxu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vmaxf, v2sf, v4sf)
++VAR2 (BINOP, vmaxf, v8hf, v4hf)
++VAR4 (BINOP, vmaxnm, v2sf, v4sf, v4hf, v8hf)
+ VAR6 (BINOP, vmins, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vminu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vminf, v2sf, v4sf)
++VAR2 (BINOP, vminf, v4hf, v8hf)
++VAR4 (BINOP, vminnm, v2sf, v4sf, v8hf, v4hf)
+ 
+ VAR3 (BINOP, vpmaxs, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vpmaxu, v8qi, v4hi, v2si)
+ VAR1 (BINOP, vpmaxf, v2sf)
++VAR1 (BINOP, vpmaxf, v4hf)
+ VAR3 (BINOP, vpmins, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vpminu, v8qi, v4hi, v2si)
+ VAR1 (BINOP, vpminf, v2sf)
++VAR1 (BINOP, vpminf, v4hf)
+ 
+ VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf)
++VAR1 (BINOP, vpadd, v4hf)
+ VAR6 (UNOP, vpaddls, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (UNOP, vpaddlu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vpadals, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vpadalu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vrecps, v2sf, v4sf)
+ VAR2 (BINOP, vrsqrts, v2sf, v4sf)
++VAR2 (BINOP, vrecps, v4hf, v8hf)
++VAR2 (BINOP, vrsqrts, v4hf, v8hf)
+ VAR8 (TERNOP_IMM, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (TERNOP_IMM, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
++VAR2 (UNOP, vabs, v8hf, v4hf)
++VAR2 (UNOP, vneg, v8hf, v4hf)
+ VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+@@ -155,8 +186,16 @@ VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR5 (BSWAP, bswap, v4hi, v8hi, v2si, v4si, v2di)
+ VAR2 (UNOP, vcnt, v8qi, v16qi)
+ VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf)
++VAR2 (UNOP, vrecpe, v8hf, v4hf)
+ VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf)
++VAR2 (UNOP, vrsqrte, v4hf, v8hf)
+ VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
++VAR2 (UNOP, vrnd, v8hf, v4hf)
++VAR2 (UNOP, vrnda, v8hf, v4hf)
++VAR2 (UNOP, vrndm, v8hf, v4hf)
++VAR2 (UNOP, vrndn, v8hf, v4hf)
++VAR2 (UNOP, vrndp, v8hf, v4hf)
++VAR2 (UNOP, vrndx, v8hf, v4hf)
+   /* FIXME: vget_lane supports more variants than this!  */
+ VAR10 (GETLANE, vget_lane,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+@@ -166,8 +205,10 @@ VAR10 (SETLANE, vset_lane,
+ VAR5 (UNOP, vcreate, v8qi, v4hi, v2si, v2sf, di)
+ VAR10 (UNOP, vdup_n,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (UNOP, vdup_n, v8hf, v4hf)
+ VAR10 (GETLANE, vdup_lane,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (GETLANE, vdup_lane, v8hf, v4hf)
+ VAR6 (COMBINE, vcombine, v8qi, v4hi, v4hf, v2si, v2sf, di)
+ VAR6 (UNOP, vget_high, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
+ VAR6 (UNOP, vget_low, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
+@@ -177,7 +218,7 @@ VAR3 (UNOP, vqmovnu, v8hi, v4si, v2di)
+ VAR3 (UNOP, vqmovun, v8hi, v4si, v2di)
+ VAR3 (UNOP, vmovls, v8qi, v4hi, v2si)
+ VAR3 (UNOP, vmovlu, v8qi, v4hi, v2si)
+-VAR6 (SETLANE, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
++VAR8 (SETLANE, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf, v4hf, v8hf)
+ VAR6 (MAC_LANE, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+ VAR2 (MAC_LANE, vmlals_lane, v4hi, v2si)
+ VAR2 (MAC_LANE, vmlalu_lane, v4hi, v2si)
+@@ -186,7 +227,7 @@ VAR6 (MAC_LANE, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+ VAR2 (MAC_LANE, vmlsls_lane, v4hi, v2si)
+ VAR2 (MAC_LANE, vmlslu_lane, v4hi, v2si)
+ VAR2 (MAC_LANE, vqdmlsl_lane, v4hi, v2si)
+-VAR6 (BINOP, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
++VAR8 (BINOP, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf, v4hf, v8hf)
+ VAR6 (MAC_N, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+ VAR2 (MAC_N, vmlals_n, v4hi, v2si)
+ VAR2 (MAC_N, vmlalu_n, v4hi, v2si)
+@@ -197,17 +238,27 @@ VAR2 (MAC_N, vmlslu_n, v4hi, v2si)
+ VAR2 (MAC_N, vqdmlsl_n, v4hi, v2si)
+ VAR10 (SETLANE, vext,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (SETLANE, vext, v8hf, v4hf)
+ VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi)
+ VAR2 (UNOP, vrev16, v8qi, v16qi)
+ VAR4 (UNOP, vcvts, v2si, v2sf, v4si, v4sf)
++VAR2 (UNOP, vcvts, v4hi, v8hi)
++VAR2 (UNOP, vcvts, v4hf, v8hf)
++VAR2 (UNOP, vcvtu, v4hi, v8hi)
++VAR2 (UNOP, vcvtu, v4hf, v8hf)
+ VAR4 (UNOP, vcvtu, v2si, v2sf, v4si, v4sf)
+ VAR4 (BINOP, vcvts_n, v2si, v2sf, v4si, v4sf)
+ VAR4 (BINOP, vcvtu_n, v2si, v2sf, v4si, v4sf)
++VAR2 (BINOP, vcvts_n, v4hf, v8hf)
++VAR2 (BINOP, vcvtu_n, v4hi, v8hi)
++VAR2 (BINOP, vcvts_n, v4hi, v8hi)
++VAR2 (BINOP, vcvtu_n, v4hf, v8hf)
+ VAR1 (UNOP, vcvtv4sf, v4hf)
+ VAR1 (UNOP, vcvtv4hf, v4sf)
+ VAR10 (TERNOP, vbsl,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (TERNOP, vbsl, v8hf, v4hf)
+ VAR2 (UNOP, copysignf, v2sf, v4sf)
+ VAR2 (UNOP, vrintn, v2sf, v4sf)
+ VAR2 (UNOP, vrinta, v2sf, v4sf)
+@@ -219,6 +270,14 @@ VAR1 (UNOP, vcvtav2sf, v2si)
+ VAR1 (UNOP, vcvtav4sf, v4si)
+ VAR1 (UNOP, vcvtauv2sf, v2si)
+ VAR1 (UNOP, vcvtauv4sf, v4si)
++VAR2 (UNOP, vcvtas, v4hf, v8hf)
++VAR2 (UNOP, vcvtau, v4hf, v8hf)
++VAR2 (UNOP, vcvtms, v4hf, v8hf)
++VAR2 (UNOP, vcvtmu, v4hf, v8hf)
++VAR2 (UNOP, vcvtns, v4hf, v8hf)
++VAR2 (UNOP, vcvtnu, v4hf, v8hf)
++VAR2 (UNOP, vcvtps, v4hf, v8hf)
++VAR2 (UNOP, vcvtpu, v4hf, v8hf)
+ VAR1 (UNOP, vcvtpv2sf, v2si)
+ VAR1 (UNOP, vcvtpv4sf, v4si)
+ VAR1 (UNOP, vcvtpuv2sf, v2si)
+--- /dev/null
++++ b/src/gcc/config/arm/arm_vfp_builtins.def
+@@ -0,0 +1,51 @@
++/* VFP instruction builtin definitions.
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.  */
++
++/* This file lists the builtins that may be available when VFP is enabled but
++   not NEON is enabled.  The entries otherwise have the same requirements and
++   generate the same structures as those in the arm_neon_builtins.def.  */
++
++/* FP16 Arithmetic instructions.  */
++VAR1 (UNOP, vabs, hf)
++VAR2 (UNOP, vcvths, hf, si)
++VAR2 (UNOP, vcvthu, hf, si)
++VAR1 (UNOP, vcvtahs, si)
++VAR1 (UNOP, vcvtahu, si)
++VAR1 (UNOP, vcvtmhs, si)
++VAR1 (UNOP, vcvtmhu, si)
++VAR1 (UNOP, vcvtnhs, si)
++VAR1 (UNOP, vcvtnhu, si)
++VAR1 (UNOP, vcvtphs, si)
++VAR1 (UNOP, vcvtphu, si)
++VAR1 (UNOP, vrnd, hf)
++VAR1 (UNOP, vrnda, hf)
++VAR1 (UNOP, vrndi, hf)
++VAR1 (UNOP, vrndm, hf)
++VAR1 (UNOP, vrndn, hf)
++VAR1 (UNOP, vrndp, hf)
++VAR1 (UNOP, vrndx, hf)
++VAR1 (UNOP, vsqrt, hf)
++
++VAR2 (BINOP, vcvths_n, hf, si)
++VAR2 (BINOP, vcvthu_n, hf, si)
++VAR1 (BINOP, vmaxnm, hf)
++VAR1 (BINOP, vminnm, hf)
++
++VAR1 (TERNOP, vfma, hf)
++VAR1 (TERNOP, vfms, hf)
+--- a/src/gcc/config/arm/bpabi.h
++++ b/src/gcc/config/arm/bpabi.h
+@@ -75,6 +75,9 @@
+    |mcpu=cortex-a57.cortex-a53				\
+    |mcpu=cortex-a72					\
+    |mcpu=cortex-a72.cortex-a53				\
++   |mcpu=cortex-a73					\
++   |mcpu=cortex-a73.cortex-a35				\
++   |mcpu=cortex-a73.cortex-a53				\
+    |mcpu=exynos-m1                                      \
+    |mcpu=qdf24xx					\
+    |mcpu=xgene1                                         \
+@@ -90,6 +93,11 @@
+    |march=armv8-a+crc					\
+    |march=armv8.1-a					\
+    |march=armv8.1-a+crc					\
++   |march=armv8.2-a					\
++   |march=armv8.2-a+fp16				\
++   |march=armv8-m.base|mcpu=cortex-m23			\
++   |march=armv8-m.main					\
++   |march=armv8-m.main+dsp|mcpu=cortex-m33		\
+    :%{!r:--be8}}}"
+ #else
+ #define BE8_LINK_SPEC \
+@@ -105,6 +113,9 @@
+    |mcpu=cortex-a57.cortex-a53				\
+    |mcpu=cortex-a72					\
+    |mcpu=cortex-a72.cortex-a53				\
++   |mcpu=cortex-a73					\
++   |mcpu=cortex-a73.cortex-a35				\
++   |mcpu=cortex-a73.cortex-a53				\
+    |mcpu=exynos-m1                                      \
+    |mcpu=qdf24xx					\
+    |mcpu=xgene1                                         \
+@@ -121,6 +132,11 @@
+    |march=armv8-a+crc					\
+    |march=armv8.1-a					\
+    |march=armv8.1-a+crc					\
++   |march=armv8.2-a					\
++   |march=armv8.2-a+fp16				\
++   |march=armv8-m.base|mcpu=cortex-m23			\
++   |march=armv8-m.main					\
++   |march=armv8-m.main+dsp|mcpu=cortex-m33		\
+    :%{!r:--be8}}}"
+ #endif
+ 
+--- a/src/gcc/config/arm/constraints.md
++++ b/src/gcc/config/arm/constraints.md
+@@ -34,11 +34,13 @@
+ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp, Dz
+ ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
+ ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
++;; in all states: Pf
+ 
+ ;; The following memory constraints have been used:
+-;; in ARM/Thumb-2 state: Q, Uh, Ut, Uv, Uy, Un, Um, Us
++;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
+ ;; in ARM state: Uq
+ ;; in Thumb state: Uu, Uw
++;; in all states: Q
+ 
+ 
+ (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
+@@ -66,7 +68,7 @@
+ 
+ (define_constraint "j"
+  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
+- (and (match_test "TARGET_32BIT && arm_arch_thumb2")
++ (and (match_test "TARGET_HAVE_MOVT")
+       (ior (and (match_code "high")
+ 		(match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
+ 	   (and (match_code "const_int")
+@@ -180,6 +182,13 @@
+   (and (match_code "const_int")
+        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
+ 
++(define_constraint "Pf"
++  "Memory models except relaxed, consume or release ones."
++  (and (match_code "const_int")
++       (match_test "!is_mm_relaxed (memmodel_from_int (ival))
++		    && !is_mm_consume (memmodel_from_int (ival))
++		    && !is_mm_release (memmodel_from_int (ival))")))
++
+ (define_constraint "Ps"
+   "@internal In Thumb-2 state a constant in the range -255 to +255"
+   (and (match_code "const_int")
+@@ -333,13 +342,13 @@
+  "@internal
+   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
++       (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
+ 
+ (define_constraint "Dp"
+  "@internal
+   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP
++       (match_test "TARGET_32BIT
+ 		    && vfp3_const_double_for_bits (op) > 0")))
+ 
+ (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
+@@ -407,7 +416,7 @@
+ 
+ (define_memory_constraint "Q"
+  "@internal
+-  In ARM/Thumb-2 state an address that is a single base register."
++  An address that is a single base register."
+  (and (match_code "mem")
+       (match_test "REG_P (XEXP (op, 0))")))
+ 
+--- a/src/gcc/config/arm/cortex-a53.md
++++ b/src/gcc/config/arm/cortex-a53.md
+@@ -30,6 +30,7 @@
+ 
+ (define_cpu_unit "cortex_a53_slot0" "cortex_a53")
+ (define_cpu_unit "cortex_a53_slot1" "cortex_a53")
++(final_presence_set "cortex_a53_slot1" "cortex_a53_slot0")
+ 
+ (define_reservation "cortex_a53_slot_any"
+ 		    "cortex_a53_slot0\
+@@ -71,41 +72,43 @@
+ 
+ (define_insn_reservation "cortex_a53_shift" 2
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "adr,shift_imm,shift_reg,mov_imm,mvn_imm"))
++       (eq_attr "type" "adr,shift_imm,mov_imm,mvn_imm,mov_shift"))
+   "cortex_a53_slot_any")
+ 
+-(define_insn_reservation "cortex_a53_alu_rotate_imm" 2
++(define_insn_reservation "cortex_a53_shift_reg" 2
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "rotate_imm"))
+-  "(cortex_a53_slot1)
+-   | (cortex_a53_single_issue)")
++       (eq_attr "type" "shift_reg,mov_shift_reg"))
++  "cortex_a53_slot_any+cortex_a53_hazard")
+ 
+ (define_insn_reservation "cortex_a53_alu" 3
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,
+ 			alu_sreg,alus_sreg,logic_reg,logics_reg,
+ 			adc_imm,adcs_imm,adc_reg,adcs_reg,
+-			bfm,csel,clz,rbit,rev,alu_dsp_reg,
+-			mov_reg,mvn_reg,
+-			mrs,multiple,no_insn"))
++			csel,clz,rbit,rev,alu_dsp_reg,
++			mov_reg,mvn_reg,mrs,multiple,no_insn"))
+   "cortex_a53_slot_any")
+ 
+ (define_insn_reservation "cortex_a53_alu_shift" 3
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "alu_shift_imm,alus_shift_imm,
+ 			crc,logic_shift_imm,logics_shift_imm,
+-			alu_ext,alus_ext,
+-			extend,mov_shift,mvn_shift"))
++			alu_ext,alus_ext,bfm,bfx,extend,mvn_shift"))
+   "cortex_a53_slot_any")
+ 
+ (define_insn_reservation "cortex_a53_alu_shift_reg" 3
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "alu_shift_reg,alus_shift_reg,
+ 			logic_shift_reg,logics_shift_reg,
+-			mov_shift_reg,mvn_shift_reg"))
++			mvn_shift_reg"))
+   "cortex_a53_slot_any+cortex_a53_hazard")
+ 
+-(define_insn_reservation "cortex_a53_mul" 3
++(define_insn_reservation "cortex_a53_alu_extr" 3
++  (and (eq_attr "tune" "cortexa53")
++       (eq_attr "type" "rotate_imm"))
++  "cortex_a53_slot1|cortex_a53_single_issue")
++
++(define_insn_reservation "cortex_a53_mul" 4
+   (and (eq_attr "tune" "cortexa53")
+        (ior (eq_attr "mul32" "yes")
+ 	    (eq_attr "mul64" "yes")))
+@@ -189,49 +192,43 @@
+ (define_insn_reservation "cortex_a53_branch" 0
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "branch,call"))
+-  "cortex_a53_slot_any,cortex_a53_branch")
++  "cortex_a53_slot_any+cortex_a53_branch")
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; General-purpose register bypasses
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ 
+-;; Model bypasses for unshifted operands to ALU instructions.
++;; Model bypasses for ALU to ALU instructions.
++
++(define_bypass 0 "cortex_a53_shift*"
++		 "cortex_a53_alu")
+ 
+-(define_bypass 1 "cortex_a53_shift"
+-		 "cortex_a53_shift")
++(define_bypass 1 "cortex_a53_shift*"
++		 "cortex_a53_shift*,cortex_a53_alu_*")
+ 
+-(define_bypass 1 "cortex_a53_alu,
+-		  cortex_a53_alu_shift*,
+-		  cortex_a53_alu_rotate_imm,
+-		  cortex_a53_shift"
++(define_bypass 1 "cortex_a53_alu*"
+ 		 "cortex_a53_alu")
+ 
+-(define_bypass 2 "cortex_a53_alu,
+-		  cortex_a53_alu_shift*"
++(define_bypass 1 "cortex_a53_alu*"
+ 		 "cortex_a53_alu_shift*"
+ 		 "aarch_forward_to_shift_is_not_shifted_reg")
+ 
+-;; In our model, we allow any general-purpose register operation to
+-;; bypass to the accumulator operand of an integer MADD-like operation.
++(define_bypass 2 "cortex_a53_alu*"
++		 "cortex_a53_alu_*,cortex_a53_shift*")
++
++;; Model a bypass from MUL/MLA to MLA instructions.
+ 
+-(define_bypass 1 "cortex_a53_alu*,
+-		  cortex_a53_load*,
+-		  cortex_a53_mul"
++(define_bypass 1 "cortex_a53_mul"
+ 		 "cortex_a53_mul"
+ 		 "aarch_accumulator_forwarding")
+ 
+-;; Model a bypass from MLA/MUL to many ALU instructions.
++;; Model a bypass from MUL/MLA to ALU instructions.
+ 
+ (define_bypass 2 "cortex_a53_mul"
+-		 "cortex_a53_alu,
+-		  cortex_a53_alu_shift*")
+-
+-;; We get neater schedules by allowing an MLA/MUL to feed an
+-;; early load address dependency to a load.
++		 "cortex_a53_alu")
+ 
+-(define_bypass 2 "cortex_a53_mul"
+-		 "cortex_a53_load*"
+-		 "arm_early_load_addr_dep")
++(define_bypass 3 "cortex_a53_mul"
++		 "cortex_a53_alu_*,cortex_a53_shift*")
+ 
+ ;; Model bypasses for loads which are to be consumed by the ALU.
+ 
+@@ -239,47 +236,46 @@
+ 		 "cortex_a53_alu")
+ 
+ (define_bypass 3 "cortex_a53_load1"
+-		 "cortex_a53_alu_shift*")
++		 "cortex_a53_alu_*,cortex_a53_shift*")
++
++(define_bypass 3 "cortex_a53_load2"
++		 "cortex_a53_alu")
+ 
+ ;; Model a bypass for ALU instructions feeding stores.
+ 
+-(define_bypass 1 "cortex_a53_alu*"
+-		 "cortex_a53_store1,
+-		  cortex_a53_store2,
+-		  cortex_a53_store3plus"
++(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
++		 "cortex_a53_store*"
+ 		 "arm_no_early_store_addr_dep")
+ 
+ ;; Model a bypass for load and multiply instructions feeding stores.
+ 
+-(define_bypass 2 "cortex_a53_mul,
+-		  cortex_a53_load1,
+-		  cortex_a53_load2,
+-		  cortex_a53_load3plus"
+-		 "cortex_a53_store1,
+-		  cortex_a53_store2,
+-		  cortex_a53_store3plus"
++(define_bypass 1 "cortex_a53_mul,
++		  cortex_a53_load*"
++		 "cortex_a53_store*"
+ 		 "arm_no_early_store_addr_dep")
+ 
+ ;; Model a GP->FP register move as similar to stores.
+ 
+-(define_bypass 1 "cortex_a53_alu*"
++(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
+ 		 "cortex_a53_r2f")
+ 
+-(define_bypass 2 "cortex_a53_mul,
++(define_bypass 1 "cortex_a53_mul,
+ 		  cortex_a53_load1,
+-		  cortex_a53_load2,
+-		  cortex_a53_load3plus"
++		  cortex_a53_load2"
+ 		 "cortex_a53_r2f")
+ 
+-;; Shifts feeding Load/Store addresses may not be ready in time.
++(define_bypass 2 "cortex_a53_alu*"
++		 "cortex_a53_r2f_cvt")
+ 
+-(define_bypass 3 "cortex_a53_shift"
+-		 "cortex_a53_load*"
+-		 "arm_early_load_addr_dep")
++(define_bypass 3 "cortex_a53_mul,
++		  cortex_a53_load1,
++		  cortex_a53_load2"
++		 "cortex_a53_r2f_cvt")
+ 
+-(define_bypass 3 "cortex_a53_shift"
+-		 "cortex_a53_store*"
+-		 "arm_early_store_addr_dep")
++;; Model flag forwarding to branches.
++
++(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
++		 "cortex_a53_branch")
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; Floating-point/Advanced SIMD.
+@@ -535,19 +531,25 @@
+ ;; Floating-point to/from core transfers.
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ 
+-(define_insn_reservation "cortex_a53_r2f" 6
++(define_insn_reservation "cortex_a53_r2f" 2
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "f_mcr,f_mcrr,f_cvti2f,
+-			neon_from_gp, neon_from_gp_q"))
+-  "cortex_a53_slot_any,cortex_a53_store,
+-   nothing,cortex_a53_fp_alu")
++       (eq_attr "type" "f_mcr,f_mcrr"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
+ 
+-(define_insn_reservation "cortex_a53_f2r" 6
++(define_insn_reservation "cortex_a53_f2r" 4
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "f_mrc,f_mrrc,f_cvtf2i,
+-			neon_to_gp, neon_to_gp_q"))
+-  "cortex_a53_slot_any,cortex_a53_fp_alu,
+-   nothing,cortex_a53_store")
++       (eq_attr "type" "f_mrc,f_mrrc"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
++
++(define_insn_reservation "cortex_a53_r2f_cvt" 4
++  (and (eq_attr "tune" "cortexa53")
++       (eq_attr "type" "f_cvti2f, neon_from_gp, neon_from_gp_q"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
++
++(define_insn_reservation "cortex_a53_f2r_cvt" 5
++  (and (eq_attr "tune" "cortexa53")
++       (eq_attr "type" "f_cvtf2i, neon_to_gp, neon_to_gp_q"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; Floating-point flag transfer.
+--- a/src/gcc/config/arm/cortex-a57.md
++++ b/src/gcc/config/arm/cortex-a57.md
+@@ -297,7 +297,7 @@
+        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ 			alu_sreg,alus_sreg,logic_reg,logics_reg,\
+ 			adc_imm,adcs_imm,adc_reg,adcs_reg,\
+-			adr,bfm,clz,rbit,rev,alu_dsp_reg,\
++			adr,bfx,extend,clz,rbit,rev,alu_dsp_reg,\
+ 			rotate_imm,shift_imm,shift_reg,\
+ 			mov_imm,mov_reg,\
+ 			mvn_imm,mvn_reg,\
+@@ -307,7 +307,7 @@
+ ;; ALU ops with immediate shift
+ (define_insn_reservation "cortex_a57_alu_shift" 3
+   (and (eq_attr "tune" "cortexa57")
+-       (eq_attr "type" "extend,\
++       (eq_attr "type" "bfm,\
+ 			alu_shift_imm,alus_shift_imm,\
+ 			crc,logic_shift_imm,logics_shift_imm,\
+ 			mov_shift,mvn_shift"))
+@@ -726,7 +726,7 @@
+ 
+ (define_insn_reservation "cortex_a57_fp_cpys" 4
+   (and (eq_attr "tune" "cortexa57")
+-       (eq_attr "type" "fmov"))
++       (eq_attr "type" "fmov,fcsel"))
+   "(ca57_cx1|ca57_cx2)")
+ 
+ (define_insn_reservation "cortex_a57_fp_divs" 12
+--- a/src/gcc/config/arm/cortex-a8-neon.md
++++ b/src/gcc/config/arm/cortex-a8-neon.md
+@@ -357,30 +357,34 @@
+        (eq_attr "type" "fmuls"))
+   "cortex_a8_vfp,cortex_a8_vfplite*11")
+ 
++;; Don't model a reservation for more than 15 cycles as this explodes the
++;; state space of the automaton for little gain.  It is unlikely that the
++;; scheduler will find enough instructions to hide the full latency of the
++;; instructions.
+ (define_insn_reservation "cortex_a8_vfp_muld" 17
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fmuld"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*16")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_macs" 21
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fmacs,ffmas"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*20")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_macd" 26
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fmacd,ffmad"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*25")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_divs" 37
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fdivs, fsqrts"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*36")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_divd" 65
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fdivd, fsqrtd"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*64")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ ;; Comparisons can actually take 7 cycles sometimes instead of four,
+ ;; but given all the other instructions lumped into type=ffarith that
+--- a/src/gcc/config/arm/crypto.md
++++ b/src/gcc/config/arm/crypto.md
+@@ -18,14 +18,27 @@
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ 
++
++;; When AES/AESMC fusion is enabled we want the register allocation to
++;; look like:
++;;    AESE Vn, _
++;;    AESMC Vn, Vn
++;; So prefer to tie operand 1 to operand 0 when fusing.
++
+ (define_insn "crypto_<crypto_pattern>"
+-  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
++  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w,w")
+         (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1
+-                       "register_operand" "w")]
++                       "register_operand" "0,w")]
+          CRYPTO_UNARY))]
+   "TARGET_CRYPTO"
+   "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1"
+-  [(set_attr "type" "<crypto_type>")]
++  [(set_attr "type" "<crypto_type>")
++   (set_attr_alternative "enabled"
++     [(if_then_else (match_test
++		       "arm_fusion_enabled_p (tune_params::FUSE_AES_AESMC)")
++		     (const_string "yes" )
++		     (const_string "no"))
++      (const_string "yes")])]
+ )
+ 
+ (define_insn "crypto_<crypto_pattern>"
+--- a/src/gcc/config/arm/driver-arm.c
++++ b/src/gcc/config/arm/driver-arm.c
+@@ -46,6 +46,12 @@ static struct vendor_cpu arm_cpu_table[] = {
+     {"0xc0d", "armv7ve", "cortex-a12"},
+     {"0xc0e", "armv7ve", "cortex-a17"},
+     {"0xc0f", "armv7ve", "cortex-a15"},
++    {"0xd01", "armv8-a+crc", "cortex-a32"},
++    {"0xd04", "armv8-a+crc", "cortex-a35"},
++    {"0xd03", "armv8-a+crc", "cortex-a53"},
++    {"0xd07", "armv8-a+crc", "cortex-a57"},
++    {"0xd08", "armv8-a+crc", "cortex-a72"},
++    {"0xd09", "armv8-a+crc", "cortex-a73"},
+     {"0xc14", "armv7-r", "cortex-r4"},
+     {"0xc15", "armv7-r", "cortex-r5"},
+     {"0xc20", "armv6-m", "cortex-m0"},
+--- a/src/gcc/config/arm/elf.h
++++ b/src/gcc/config/arm/elf.h
+@@ -75,16 +75,7 @@
+ 
+ /* We might need a ARM specific header to function declarations.  */
+ #undef  ASM_DECLARE_FUNCTION_NAME
+-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)		\
+-  do								\
+-    {								\
+-      ARM_DECLARE_FUNCTION_NAME (FILE, NAME, DECL);		\
+-      ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function");	\
+-      ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));		\
+-      ASM_OUTPUT_LABEL(FILE, NAME);				\
+-      ARM_OUTPUT_FN_UNWIND (FILE, TRUE);			\
+-    }								\
+-  while (0)
++#define ASM_DECLARE_FUNCTION_NAME arm_asm_declare_function_name
+ 
+ /* We might need an ARM specific trailer for function declarations.  */
+ #undef  ASM_DECLARE_FUNCTION_SIZE
+@@ -148,8 +139,9 @@
+   while (0)
+ 
+ /* Horrible hack: We want to prevent some libgcc routines being included
+-   for some multilibs.  */
+-#ifndef __ARM_ARCH_6M__
++   for some multilibs.  The condition should match the one in
++   libgcc/config/arm/lib1funcs.S.  */
++#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
+ #undef L_fixdfsi
+ #undef L_fixunsdfsi
+ #undef L_truncdfsf2
+--- a/src/gcc/config/arm/exynos-m1.md
++++ b/src/gcc/config/arm/exynos-m1.md
+@@ -358,7 +358,7 @@
+ 	    (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
+ 			     alu_sreg, alus_sreg, logic_reg, logics_reg,\
+ 			     adc_imm, adcs_imm, adc_reg, adcs_reg,\
+-			     adr, bfm, clz, rbit, rev, csel, alu_dsp_reg,\
++			     adr, bfm, bfx, clz, rbit, rev, csel, alu_dsp_reg,\
+ 			     shift_imm, shift_reg, rotate_imm, extend,\
+ 			     mov_imm, mov_reg,\
+ 			     mvn_imm, mvn_reg,\
+@@ -372,7 +372,7 @@
+ 	    (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
+ 			     alu_sreg, alus_sreg, logic_reg, logics_reg,\
+ 			     adc_imm, adcs_imm, adc_reg, adcs_reg,\
+-			     adr, bfm, clz, rbit, rev, alu_dsp_reg,\
++			     adr, bfm, bfx, clz, rbit, rev, alu_dsp_reg,\
+ 			     shift_imm, shift_reg, rotate_imm, extend,\
+ 			     mov_imm, mov_reg,\
+ 			     mvn_imm, mvn_reg,\
+--- a/src/gcc/config/arm/iterators.md
++++ b/src/gcc/config/arm/iterators.md
+@@ -46,7 +46,7 @@
+ (define_mode_iterator SIDI [SI DI])
+ 
+ ;; A list of modes which the VFP unit can handle
+-(define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")])
++(define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
+ 
+ ;; Integer element sizes implemented by IWMMXT.
+ (define_mode_iterator VMMX [V2SI V4HI V8QI])
+@@ -119,6 +119,10 @@
+ ;; All supported vector modes (except those with 64-bit integer elements).
+ (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
+ 
++;; All supported vector modes including 16-bit float modes.
++(define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF
++			     V8HF V4HF])
++
+ ;; Supported integer vector modes (not 64 bit elements).
+ (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
+ 
+@@ -141,6 +145,9 @@
+ ;; Vector modes form int->float conversions.
+ (define_mode_iterator VCVTI [V2SI V4SI])
+ 
++;; Vector modes for int->half conversions.
++(define_mode_iterator VCVTHI [V4HI V8HI])
++
+ ;; Vector modes for doubleword multiply-accumulate, etc. insns.
+ (define_mode_iterator VMD [V4HI V2SI V2SF])
+ 
+@@ -174,6 +181,9 @@
+ ;; Modes with 8-bit, 16-bit and 32-bit elements.
+ (define_mode_iterator VU [V16QI V8HI V4SI])
+ 
++;; Vector modes for 16-bit floating-point support.
++(define_mode_iterator VH [V8HF V4HF])
++
+ ;; Iterators used for fixed-point support.
+ (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
+ 
+@@ -192,14 +202,17 @@
+ ;; Code iterators
+ ;;----------------------------------------------------------------------------
+ 
+-;; A list of condition codes used in compare instructions where 
+-;; the carry flag from the addition is used instead of doing the 
++;; A list of condition codes used in compare instructions where
++;; the carry flag from the addition is used instead of doing the
+ ;; compare a second time.
+ (define_code_iterator LTUGEU [ltu geu])
+ 
+ ;; The signed gt, ge comparisons
+ (define_code_iterator GTGE [gt ge])
+ 
++;; The signed gt, ge, lt, le comparisons
++(define_code_iterator GLTE [gt ge lt le])
++
+ ;; The unsigned gt, ge comparisons
+ (define_code_iterator GTUGEU [gtu geu])
+ 
+@@ -228,6 +241,12 @@
+ ;; Binary operators whose second operand can be shifted.
+ (define_code_iterator SHIFTABLE_OPS [plus minus ior xor and])
+ 
++;; Operations on the sign of a number.
++(define_code_iterator ABSNEG [abs neg])
++
++;; Conversions.
++(define_code_iterator FCVT [unsigned_float float])
++
+ ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
+ ;; a stack pointer opoerand.  The minus operation is a candidate for an rsub
+ ;; and hence only plus is supported.
+@@ -251,10 +270,14 @@
+ (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
+                             UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
+ 
+-(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE UNSPEC_VCLT UNSPEC_VCLE])
++(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
++				UNSPEC_VCLT UNSPEC_VCLE])
+ 
+ (define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT])
+ 
++(define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
++				  UNSPEC_VCALE UNSPEC_VCALT])
++
+ (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
+ 
+ (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
+@@ -323,6 +346,22 @@
+ 
+ (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N])
+ 
++(define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N])
++
++(define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N])
++
++(define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U
++				 UNSPEC_VCVTM_S UNSPEC_VCVTM_U
++				 UNSPEC_VCVTN_S UNSPEC_VCVTN_U
++				 UNSPEC_VCVTP_S UNSPEC_VCVTP_U])
++
++(define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U])
++
++;; Operators for FP16 instructions.
++(define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA
++			       UNSPEC_VRNDM UNSPEC_VRNDN
++			       UNSPEC_VRNDP UNSPEC_VRNDX])
++
+ (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U])
+ 
+ (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U])
+@@ -366,6 +405,8 @@
+ 
+ (define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
+ 
++(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
++
+ ;;----------------------------------------------------------------------------
+ ;; Mode attributes
+ ;;----------------------------------------------------------------------------
+@@ -384,6 +425,10 @@
+ (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
+                            (V4SI "v4sf") (V4SF "v4si")])
+ 
++;; (Opposite) mode to convert to/from for vector-half mode conversions.
++(define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI")
++			    (V8HI "V8HF") (V8HF "V8HI")])
++
+ ;; Define element mode for each vector mode.
+ (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
+ 			  (V4HI "HI") (V8HI "HI")
+@@ -427,12 +472,13 @@
+ 
+ ;; Register width from element mode
+ (define_mode_attr V_reg [(V8QI "P") (V16QI "q")
+-                         (V4HI "P") (V8HI  "q")
+-                         (V4HF "P") (V8HF  "q")
+-                         (V2SI "P") (V4SI  "q")
+-                         (V2SF "P") (V4SF  "q")
+-                         (DI   "P") (V2DI  "q")
+-                         (SF   "")  (DF    "P")])
++			 (V4HI "P") (V8HI  "q")
++			 (V4HF "P") (V8HF  "q")
++			 (V2SI "P") (V4SI  "q")
++			 (V2SF "P") (V4SF  "q")
++			 (DI   "P") (V2DI  "q")
++			 (SF   "")  (DF    "P")
++			 (HF   "")])
+ 
+ ;; Wider modes with the same number of elements.
+ (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
+@@ -448,7 +494,7 @@
+ (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
+ 			  (V8HF "V4HF") (V4SI  "V2SI")
+ 			  (V4SF "V2SF") (V2DF "DF")
+-                          (V2DI "DI")])
++			  (V2DI "DI") (V4HF "HF")])
+ 
+ ;; Same, but lower-case.
+ (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
+@@ -475,9 +521,10 @@
+ ;; Used for neon_vdup_lane, where the second operand is double-sized
+ ;; even when the first one is quad.
+ (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
+-                                        (V4SI "V2SI") (V4SF "V2SF")
+-                                        (V8QI "V8QI") (V4HI "V4HI")
+-                                        (V2SI "V2SI") (V2SF "V2SF")])
++					(V4SI "V2SI") (V4SF "V2SF")
++					(V8QI "V8QI") (V4HI "V4HI")
++					(V2SI "V2SI") (V2SF "V2SF")
++					(V8HF "V4HF") (V4HF "V4HF")])
+ 
+ ;; Mode of result of comparison operations (and bit-select operand 1).
+ (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
+@@ -496,18 +543,22 @@
+ ;; Get element type from double-width mode, for operations where we 
+ ;; don't care about signedness.
+ (define_mode_attr V_if_elem [(V8QI "i8")  (V16QI "i8")
+-                 (V4HI "i16") (V8HI  "i16")
+-                             (V2SI "i32") (V4SI  "i32")
+-                             (DI   "i64") (V2DI  "i64")
+-                 (V2SF "f32") (V4SF  "f32")
+-                 (SF "f32") (DF "f64")])
++			     (V4HI "i16") (V8HI  "i16")
++			     (V2SI "i32") (V4SI  "i32")
++			     (DI   "i64") (V2DI  "i64")
++			     (V2SF "f32") (V4SF  "f32")
++			     (SF   "f32") (DF    "f64")
++			     (HF   "f16") (V4HF  "f16")
++			     (V8HF "f16")])
+ 
+ ;; Same, but for operations which work on signed values.
+ (define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
+-                (V4HI "s16") (V8HI  "s16")
+-                            (V2SI "s32") (V4SI  "s32")
+-                            (DI   "s64") (V2DI  "s64")
+-                (V2SF "f32") (V4SF  "f32")])
++			    (V4HI "s16") (V8HI  "s16")
++			    (V2SI "s32") (V4SI  "s32")
++			    (DI   "s64") (V2DI  "s64")
++			    (V2SF "f32") (V4SF  "f32")
++			    (HF   "f16") (V4HF  "f16")
++			    (V8HF "f16")])
+ 
+ ;; Same, but for operations which work on unsigned values.
+ (define_mode_attr V_u_elem [(V8QI "u8")  (V16QI "u8")
+@@ -524,17 +575,22 @@
+                              (V2SF "32") (V4SF "32")])
+ 
+ (define_mode_attr V_sz_elem [(V8QI "8")  (V16QI "8")
+-                 (V4HI "16") (V8HI  "16")
+-                             (V2SI "32") (V4SI  "32")
+-                             (DI   "64") (V2DI  "64")
++			     (V4HI "16") (V8HI  "16")
++			     (V2SI "32") (V4SI  "32")
++			     (DI   "64") (V2DI  "64")
+ 			     (V4HF "16") (V8HF "16")
+-                 (V2SF "32") (V4SF  "32")])
++			     (V2SF "32") (V4SF  "32")])
+ 
+ (define_mode_attr V_elem_ch [(V8QI "b")  (V16QI "b")
+-                             (V4HI "h") (V8HI  "h")
+-                             (V2SI "s") (V4SI  "s")
+-                             (DI   "d") (V2DI  "d")
+-                             (V2SF "s") (V4SF  "s")])
++			     (V4HI "h") (V8HI  "h")
++			     (V2SI "s") (V4SI  "s")
++			     (DI   "d") (V2DI  "d")
++			     (V2SF "s") (V4SF  "s")
++			     (V2SF "s") (V4SF  "s")])
++
++(define_mode_attr VH_elem_ch [(V4HI "s") (V8HI  "s")
++			      (V4HF "s") (V8HF  "s")
++			      (HF "s")])
+ 
+ ;; Element sizes for duplicating ARM registers to all elements of a vector.
+ (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
+@@ -570,29 +626,30 @@
+ ;; This mode attribute is used to obtain the correct register constraints.
+ 
+ (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
+-                                         (V8HI "x") (V4SI "t") (V4SF "t")])
++					 (V8HI "x") (V4SI "t") (V4SF "t")
++					 (V8HF "x") (V4HF "x")])
+ 
+ ;; Predicates used for setting type for neon instructions
+ 
+ (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
+-                 (V4HI "false") (V8HI "false")
+-                 (V2SI "false") (V4SI "false")
+-                 (V4HF "true") (V8HF "true")
+-                 (V2SF "true") (V4SF "true")
+-                 (DI "false") (V2DI "false")])
++				 (V4HI "false") (V8HI "false")
++				 (V2SI "false") (V4SI "false")
++				 (V4HF "true") (V8HF "true")
++				 (V2SF "true") (V4SF "true")
++				 (DI "false") (V2DI "false")])
+ 
+ (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
+-                   (V4HI "true") (V8HI "true")
+-                   (V2SI "false") (V4SI "false")
+-                   (V2SF "false") (V4SF "false")
+-                   (DI "false") (V2DI "false")])
+-
++				   (V4HI "true") (V8HI "true")
++				   (V2SI "false") (V4SI "false")
++				   (V2SF "false") (V4SF "false")
++				   (DI "false") (V2DI "false")])
+ 
+ (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
+-                            (V4HI "true") (V8HI  "false")
+-                            (V2SI "true") (V4SI  "false")
+-                            (V2SF "true") (V4SF  "false")
+-                            (DI   "true") (V2DI  "false")])
++			    (V4HI "true") (V8HI  "false")
++			    (V2SI "true") (V4SI  "false")
++			    (V2SF "true") (V4SF  "false")
++			    (DI   "true") (V2DI  "false")
++			    (V4HF "true") (V8HF  "false")])
+ 
+ (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
+ 				 (V4HF "4") (V8HF "8")
+@@ -637,12 +694,14 @@
+ 
+ ;; Mode attribute used to build the "type" attribute.
+ (define_mode_attr q [(V8QI "") (V16QI "_q")
+-                     (V4HI "") (V8HI "_q")
+-                     (V2SI "") (V4SI "_q")
++		     (V4HI "") (V8HI "_q")
++		     (V2SI "") (V4SI "_q")
++		     (V4HF "") (V8HF "_q")
++		     (V2SF "") (V4SF "_q")
+ 		     (V4HF "") (V8HF "_q")
+-                     (V2SF "") (V4SF "_q")
+-                     (DI "")   (V2DI "_q")
+-                     (DF "")   (V2DF "_q")])
++		     (DI "")   (V2DI "_q")
++		     (DF "")   (V2DF "_q")
++		     (HF "")])
+ 
+ (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")])
+ 
+@@ -679,6 +738,16 @@
+ (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
+ (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
+ 
++;; String reprentations of operations on the sign of a number.
++(define_code_attr absneg_str [(abs "abs") (neg "neg")])
++
++;; Conversions.
++(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
++
++(define_code_attr float_sup [(unsigned_float "u") (float "s")])
++
++(define_code_attr float_SUP [(unsigned_float "U") (float "S")])
++
+ ;;----------------------------------------------------------------------------
+ ;; Int attributes
+ ;;----------------------------------------------------------------------------
+@@ -710,7 +779,13 @@
+   (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u")
+   (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u")
+   (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u")
++  (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u")
++  (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u")
++  (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u")
++  (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u")
+   (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u")
++  (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u")
++  (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u")
+   (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u")
+   (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u")
+   (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u")
+@@ -725,13 +800,30 @@
+   (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u")
+   (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u")
+   (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
+-
++  (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u")
+ ])
+ 
++(define_int_attr vcvth_op
++ [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a")
++  (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m")
++  (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n")
++  (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")])
++
++(define_int_attr fp16_rnd_str
++  [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda")
++   (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn")
++   (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")])
++
++(define_int_attr fp16_rnd_insn
++  [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta")
++   (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn")
++   (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")])
++
+ (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt")
+-                              (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
+-                              (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
+-                              (UNSPEC_VCAGT "gt")])
++			      (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
++			      (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
++			      (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le")
++			      (UNSPEC_VCALT "lt")])
+ 
+ (define_int_attr r [
+   (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r")
+@@ -847,3 +939,7 @@
+ 
+ ;; Attributes for VQRDMLAH/VQRDMLSH
+ (define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
++
++;; Attributes for VFMA_LANE/ VFMS_LANE
++(define_int_attr neon_vfm_lane_as
++ [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")])
+--- a/src/gcc/config/arm/neon-testgen.ml
++++ b/src//dev/null
+@@ -1,324 +0,0 @@
+-(* Auto-generate ARM Neon intrinsics tests.
+-   Copyright (C) 2006-2016 Free Software Foundation, Inc.
+-   Contributed by CodeSourcery.
+-
+-   This file is part of GCC.
+-
+-   GCC is free software; you can redistribute it and/or modify it under
+-   the terms of the GNU General Public License as published by the Free
+-   Software Foundation; either version 3, or (at your option) any later
+-   version.
+-
+-   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+-   WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-   for more details.
+-
+-   You should have received a copy of the GNU General Public License
+-   along with GCC; see the file COPYING3.  If not see
+-   <http://www.gnu.org/licenses/>.
+-
+-   This is an O'Caml program.  The O'Caml compiler is available from:
+-
+-     http://caml.inria.fr/
+-
+-   Or from your favourite OS's friendly packaging system. Tested with version
+-   3.09.2, though other versions will probably work too.
+-
+-   Compile with:
+-     ocamlc -c neon.ml
+-     ocamlc -o neon-testgen neon.cmo neon-testgen.ml
+-
+-   Run with:
+-     cd /path/to/gcc/testsuite/gcc.target/arm/neon
+-     /path/to/neon-testgen
+-*)
+-
+-open Neon
+-
+-type c_type_flags = Pointer | Const
+-
+-(* Open a test source file.  *)
+-let open_test_file dir name =
+-  try
+-    open_out (dir ^ "/" ^ name ^ ".c")
+-  with Sys_error str ->
+-    failwith ("Could not create test source file " ^ name ^ ": " ^ str)
+-
+-(* Emit prologue code to a test source file.  *)
+-let emit_prologue chan test_name effective_target compile_test_optim =
+-  Printf.fprintf chan "/* Test the `%s' ARM Neon intrinsic.  */\n" test_name;
+-  Printf.fprintf chan "/* This file was autogenerated by neon-testgen.  */\n\n";
+-  Printf.fprintf chan "/* { dg-do assemble } */\n";
+-  Printf.fprintf chan "/* { dg-require-effective-target %s_ok } */\n"
+-                 effective_target;
+-  Printf.fprintf chan "/* { dg-options \"-save-temps %s\" } */\n" compile_test_optim;
+-  Printf.fprintf chan "/* { dg-add-options %s } */\n" effective_target;
+-  Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"
+-
+-(* Emit declarations of variables that are going to be passed
+-   to an intrinsic, together with one to take a returned value if needed.  *)
+-let emit_variables chan c_types features spaces =
+-  let emit () =
+-    ignore (
+-      List.fold_left (fun arg_number -> fun (flags, ty) ->
+-                        let pointer_bit =
+-                          if List.mem Pointer flags then "*" else ""
+-                        in
+-                          (* Const arguments to builtins are directly
+-                             written in as constants.  *)
+-                          if not (List.mem Const flags) then
+-                            Printf.fprintf chan "%s%s %sarg%d_%s;\n"
+-                                           spaces ty pointer_bit arg_number ty;
+-                        arg_number + 1)
+-                     0 (List.tl c_types))
+-  in
+-    match c_types with
+-      (_, return_ty) :: tys ->
+-        if return_ty <> "void" then begin
+-          (* The intrinsic returns a value.  We need to do explicit register
+-             allocation for vget_low tests or they fail because of copy
+-             elimination.  *)
+-          ((if List.mem Fixed_vector_reg features then
+-              Printf.fprintf chan "%sregister %s out_%s asm (\"d18\");\n"
+-                             spaces return_ty return_ty
+-            else if List.mem Fixed_core_reg features then
+-              Printf.fprintf chan "%sregister %s out_%s asm (\"r0\");\n"
+-                             spaces return_ty return_ty
+-            else
+-              Printf.fprintf chan "%s%s out_%s;\n" spaces return_ty return_ty);
+-	   emit ())
+-        end else
+-          (* The intrinsic does not return a value.  *)
+-          emit ()
+-    | _ -> assert false
+-
+-(* Emit code to call an intrinsic.  *)
+-let emit_call chan const_valuator c_types name elt_ty =
+-  (if snd (List.hd c_types) <> "void" then
+-     Printf.fprintf chan "  out_%s = " (snd (List.hd c_types))
+-   else
+-     Printf.fprintf chan "  ");
+-  Printf.fprintf chan "%s_%s (" (intrinsic_name name) (string_of_elt elt_ty);
+-  let print_arg chan arg_number (flags, ty) =
+-    (* If the argument is of const type, then directly write in the
+-       constant now.  *)
+-    if List.mem Const flags then
+-      match const_valuator with
+-        None ->
+-          if List.mem Pointer flags then
+-            Printf.fprintf chan "0"
+-          else
+-            Printf.fprintf chan "1"
+-      | Some f -> Printf.fprintf chan "%s" (string_of_int (f arg_number))
+-    else
+-      Printf.fprintf chan "arg%d_%s" arg_number ty
+-  in
+-  let rec print_args arg_number tys =
+-    match tys with
+-      [] -> ()
+-    | [ty] -> print_arg chan arg_number ty
+-    | ty::tys ->
+-      print_arg chan arg_number ty;
+-      Printf.fprintf chan ", ";
+-      print_args (arg_number + 1) tys
+-  in
+-    print_args 0 (List.tl c_types);
+-    Printf.fprintf chan ");\n"
+-
+-(* Emit epilogue code to a test source file.  *)
+-let emit_epilogue chan features regexps =
+-  let no_op = List.exists (fun feature -> feature = No_op) features in
+-    Printf.fprintf chan "}\n\n";
+-    if not no_op then
+-      List.iter (fun regexp ->
+-                  Printf.fprintf chan
+-                    "/* { dg-final { scan-assembler \"%s\" } } */\n" regexp)
+-                regexps
+-    else
+-      ()
+-    
+-
+-(* Check a list of C types to determine which ones are pointers and which
+-   ones are const.  *)
+-let check_types tys =
+-  let tys' =
+-    List.map (fun ty ->
+-                let len = String.length ty in
+-                  if len > 2 && String.get ty (len - 2) = ' '
+-                             && String.get ty (len - 1) = '*'
+-                  then ([Pointer], String.sub ty 0 (len - 2))
+-                  else ([], ty)) tys
+-  in
+-    List.map (fun (flags, ty) ->
+-                if String.length ty > 6 && String.sub ty 0 6 = "const "
+-                then (Const :: flags, String.sub ty 6 ((String.length ty) - 6))
+-                else (flags, ty)) tys'
+-
+-(* Work out what the effective target should be.  *)
+-let effective_target features =
+-  try
+-    match List.find (fun feature ->
+-                       match feature with Requires_feature _ -> true
+-                                        | Requires_arch _ -> true
+-                                        | Requires_FP_bit 1 -> true
+-                                        | _ -> false)
+-                     features with
+-      Requires_feature "FMA" -> "arm_neonv2"
+-    | Requires_feature "CRYPTO" -> "arm_crypto"
+-    | Requires_arch 8 -> "arm_v8_neon"
+-    | Requires_FP_bit 1 -> "arm_neon_fp16"
+-    | _ -> assert false
+-  with Not_found -> "arm_neon"
+-
+-(* Work out what the testcase optimization level should be, default to -O0.  *)
+-let compile_test_optim features =
+-  try
+-    match List.find (fun feature ->
+-                       match feature with Compiler_optim _ -> true
+-                                        | _ -> false)
+-                     features with
+-      Compiler_optim opt -> opt
+-    | _ -> assert false
+-  with Not_found -> "-O0"
+-
+-(* Given an intrinsic shape, produce a regexp that will match
+-   the right-hand sides of instructions generated by an intrinsic of
+-   that shape.  *)
+-let rec analyze_shape shape =
+-  let rec n_things n thing =
+-    match n with
+-      0 -> []
+-    | n -> thing :: (n_things (n - 1) thing)
+-  in
+-  let rec analyze_shape_elt elt =
+-    match elt with
+-      Dreg -> "\\[dD\\]\\[0-9\\]+"
+-    | Qreg -> "\\[qQ\\]\\[0-9\\]+"
+-    | Corereg -> "\\[rR\\]\\[0-9\\]+"
+-    | Immed -> "#\\[0-9\\]+"
+-    | VecArray (1, elt) ->
+-        let elt_regexp = analyze_shape_elt elt in
+-          "((\\\\\\{" ^ elt_regexp ^ "\\\\\\})|(" ^ elt_regexp ^ "))"
+-    | VecArray (n, elt) ->
+-      let elt_regexp = analyze_shape_elt elt in
+-      let alt1 = elt_regexp ^ "-" ^ elt_regexp in
+-      let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
+-        "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
+-    | (PtrTo elt | CstPtrTo elt) ->
+-      "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
+-    | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+-    | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+-    | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
+-    | Alternatives (elts) -> "(" ^ (String.concat "|" (List.map analyze_shape_elt elts)) ^ ")"
+-  in
+-    match shape with
+-      All (n, elt) -> commas analyze_shape_elt (n_things n elt) ""
+-    | Long -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Dreg) ^
+-              ", " ^ (analyze_shape_elt Dreg)
+-    | Long_noreg elt -> (analyze_shape_elt elt) ^ ", " ^ (analyze_shape_elt elt)
+-    | Wide -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
+-              ", " ^ (analyze_shape_elt Dreg)
+-    | Wide_noreg elt -> analyze_shape (Long_noreg elt)
+-    | Narrow -> (analyze_shape_elt Dreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
+-                ", " ^ (analyze_shape_elt Qreg)
+-    | Use_operands elts -> commas analyze_shape_elt (Array.to_list elts) ""
+-    | By_scalar Dreg ->
+-        analyze_shape (Use_operands [| Dreg; Dreg; Element_of_dreg |])
+-    | By_scalar Qreg ->
+-        analyze_shape (Use_operands [| Qreg; Qreg; Element_of_dreg |])
+-    | By_scalar _ -> assert false
+-    | Wide_lane ->
+-        analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
+-    | Wide_scalar ->
+-        analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
+-    | Pair_result elt ->
+-      let elt_regexp = analyze_shape_elt elt in
+-        elt_regexp ^ ", " ^ elt_regexp
+-    | Unary_scalar _ -> "FIXME Unary_scalar"
+-    | Binary_imm elt -> analyze_shape (Use_operands [| elt; elt; Immed |])
+-    | Narrow_imm -> analyze_shape (Use_operands [| Dreg; Qreg; Immed |])
+-    | Long_imm -> analyze_shape (Use_operands [| Qreg; Dreg; Immed |])
+-
+-(* Generate tests for one intrinsic.  *)
+-let test_intrinsic dir opcode features shape name munge elt_ty =
+-  (* Open the test source file.  *)
+-  let test_name = name ^ (string_of_elt elt_ty) in
+-  let chan = open_test_file dir test_name in
+-  (* Work out what argument and return types the intrinsic has.  *)
+-  let c_arity, new_elt_ty = munge shape elt_ty in
+-  let c_types = check_types (strings_of_arity c_arity) in
+-  (* Extract any constant valuator (a function specifying what constant
+-     values are to be written into the intrinsic call) from the features
+-     list.  *)
+-  let const_valuator =
+-    try
+-      match (List.find (fun feature -> match feature with
+-                                         Const_valuator _ -> true
+-				       | _ -> false) features) with
+-        Const_valuator f -> Some f
+-      | _ -> assert false
+-    with Not_found -> None
+-  in
+-  (* Work out what instruction name(s) to expect.  *)
+-  let insns = get_insn_names features name in
+-  let no_suffix = (new_elt_ty = NoElts) in
+-  let insns =
+-    if no_suffix then insns
+-                 else List.map (fun insn ->
+-                                  let suffix = string_of_elt_dots new_elt_ty in
+-                                    insn ^ "\\." ^ suffix) insns
+-  in
+-  (* Construct a regexp to match against the expected instruction name(s).  *)
+-  let insn_regexp =
+-    match insns with
+-      [] -> assert false
+-    | [insn] -> insn
+-    | _ ->
+-      let rec calc_regexp insns cur_regexp =
+-        match insns with
+-          [] -> cur_regexp
+-        | [insn] -> cur_regexp ^ "(" ^ insn ^ "))"
+-        | insn::insns -> calc_regexp insns (cur_regexp ^ "(" ^ insn ^ ")|")
+-      in calc_regexp insns "("
+-  in
+-  (* Construct regexps to match against the instructions that this
+-     intrinsic expands to.  Watch out for any writeback character and
+-     comments after the instruction.  *)
+-  let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^
+-			  "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n")
+-                         (analyze_all_shapes features shape analyze_shape)
+-  in
+-  let effective_target = effective_target features in
+-  let compile_test_optim = compile_test_optim features
+-  in
+-    (* Emit file and function prologues.  *)
+-    emit_prologue chan test_name effective_target compile_test_optim;
+-
+-    if (compare compile_test_optim "-O0") <> 0 then
+-        (* Emit variable declarations.  *)
+-        emit_variables chan c_types features "";
+-
+-    Printf.fprintf chan "void test_%s (void)\n{\n" test_name;
+-
+-    if compare compile_test_optim "-O0" = 0 then
+-        (* Emit variable declarations.  *)
+-        emit_variables chan c_types features "  ";
+-
+-    Printf.fprintf chan "\n";
+-    (* Emit the call to the intrinsic.  *)
+-    emit_call chan const_valuator c_types name elt_ty;
+-    (* Emit the function epilogue and the DejaGNU scan-assembler directives.  *)
+-    emit_epilogue chan features regexps;
+-    (* Close the test file.  *)
+-    close_out chan
+-
+-(* Generate tests for one element of the "ops" table.  *)
+-let test_intrinsic_group dir (opcode, features, shape, name, munge, types) =
+-  List.iter (test_intrinsic dir opcode features shape name munge) types
+-
+-(* Program entry point.  *)
+-let _ =
+-  let directory = if Array.length Sys.argv <> 1 then Sys.argv.(1) else "." in
+-    List.iter (test_intrinsic_group directory) (reinterp @ reinterpq @ ops)
+-
+--- a/src/gcc/config/arm/neon.md
++++ b/src/gcc/config/arm/neon.md
+@@ -406,7 +406,7 @@
+    (match_operand:SI 2 "immediate_operand" "")]
+   "TARGET_NEON"
+ {
+-  HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
++  HOST_WIDE_INT elem = HOST_WIDE_INT_1 << INTVAL (operands[2]);
+   emit_insn (gen_vec_set<mode>_internal (operands[0], operands[1],
+ 					 GEN_INT (elem), operands[0]));
+   DONE;
+@@ -505,6 +505,20 @@
+                     (const_string "neon_add<q>")))]
+ )
+ 
++(define_insn "add<mode>3_fp16"
++  [(set
++    (match_operand:VH 0 "s_register_operand" "=w")
++    (plus:VH
++     (match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")))]
++ "TARGET_NEON_FP16INST"
++ "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set (attr "type")
++   (if_then_else (match_test "<Is_float_mode>")
++    (const_string "neon_fp_addsub_s<q>")
++    (const_string "neon_add<q>")))]
++)
++
+ (define_insn "adddi3_neon"
+   [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w,?&r,?&r,?&r")
+         (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,w,r,0,r")
+@@ -543,6 +557,17 @@
+                     (const_string "neon_sub<q>")))]
+ )
+ 
++(define_insn "sub<mode>3_fp16"
++ [(set
++   (match_operand:VH 0 "s_register_operand" "=w")
++   (minus:VH
++    (match_operand:VH 1 "s_register_operand" "w")
++    (match_operand:VH 2 "s_register_operand" "w")))]
++ "TARGET_NEON_FP16INST"
++ "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_sub<q>")]
++)
++
+ (define_insn "subdi3_neon"
+   [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r,?w")
+         (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0,w")
+@@ -591,6 +616,16 @@
+ 		    (const_string "neon_mla_<V_elem_ch><q>")))]
+ )
+ 
++(define_insn "mul<mode>3add<mode>_neon"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++	(plus:VH (mult:VH (match_operand:VH 2 "s_register_operand" "w")
++			  (match_operand:VH 3 "s_register_operand" "w"))
++		  (match_operand:VH 1 "s_register_operand" "0")))]
++  "TARGET_NEON_FP16INST && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
++  "vmla.f16\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
++  [(set_attr "type" "neon_fp_mla_s<q>")]
++)
++
+ (define_insn "mul<mode>3neg<mode>add<mode>_neon"
+   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+         (minus:VDQW (match_operand:VDQW 1 "s_register_operand" "0")
+@@ -629,6 +664,19 @@
+   [(set_attr "type" "neon_fp_mla_s<q>")]
+ )
+ 
++;; There is limited support for unsafe-math optimizations using the NEON FP16
++;; arithmetic instructions, so only the intrinsic is currently supported.
++(define_insn "fma<VH:mode>4_intrinsic"
++ [(set (match_operand:VH 0 "register_operand" "=w")
++   (fma:VH
++    (match_operand:VH 1 "register_operand" "w")
++    (match_operand:VH 2 "register_operand" "w")
++    (match_operand:VH 3 "register_operand" "0")))]
++ "TARGET_NEON_FP16INST"
++ "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_mla_s<q>")]
++)
++
+ (define_insn "*fmsub<VCVTF:mode>4"
+   [(set (match_operand:VCVTF 0 "register_operand" "=w")
+         (fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
+@@ -640,13 +688,25 @@
+ )
+ 
+ (define_insn "fmsub<VCVTF:mode>4_intrinsic"
+-  [(set (match_operand:VCVTF 0 "register_operand" "=w")
+-        (fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
+-		   (match_operand:VCVTF 2 "register_operand" "w")
+-		   (match_operand:VCVTF 3 "register_operand" "0")))]
+-  "TARGET_NEON && TARGET_FMA"
+-  "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+-  [(set_attr "type" "neon_fp_mla_s<q>")]
++ [(set (match_operand:VCVTF 0 "register_operand" "=w")
++   (fma:VCVTF
++    (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
++    (match_operand:VCVTF 2 "register_operand" "w")
++    (match_operand:VCVTF 3 "register_operand" "0")))]
++ "TARGET_NEON && TARGET_FMA"
++ "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_mla_s<q>")]
++)
++
++(define_insn "fmsub<VH:mode>4_intrinsic"
++ [(set (match_operand:VH 0 "register_operand" "=w")
++   (fma:VH
++    (neg:VH (match_operand:VH 1 "register_operand" "w"))
++    (match_operand:VH 2 "register_operand" "w")
++    (match_operand:VH 3 "register_operand" "0")))]
++ "TARGET_NEON_FP16INST"
++ "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_mla_s<q>")]
+ )
+ 
+ (define_insn "neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>"
+@@ -860,6 +920,44 @@
+   ""
+ )
+ 
++(define_insn "<absneg_str><mode>2"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (ABSNEG:VH (match_operand:VH 1 "s_register_operand" "w")))]
++ "TARGET_NEON_FP16INST"
++ "v<absneg_str>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
++ [(set_attr "type" "neon_abs<q>")]
++)
++
++(define_expand "neon_v<absneg_str><mode>"
++ [(set
++   (match_operand:VH 0 "s_register_operand")
++   (ABSNEG:VH (match_operand:VH 1 "s_register_operand")))]
++ "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_<absneg_str><mode>2 (operands[0], operands[1]));
++  DONE;
++})
++
++(define_insn "neon_v<fp16_rnd_str><mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH
++     [(match_operand:VH 1 "s_register_operand" "w")]
++     FP16_RND))]
++ "TARGET_NEON_FP16INST"
++ "<fp16_rnd_insn>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
++ [(set_attr "type" "neon_fp_round_s<q>")]
++)
++
++(define_insn "neon_vrsqrte<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH
++     [(match_operand:VH 1 "s_register_operand" "w")]
++     UNSPEC_VRSQRTE))]
++  "TARGET_NEON_FP16INST"
++  "vrsqrte.f16\t%<V_reg>0, %<V_reg>1"
++ [(set_attr "type" "neon_fp_rsqrte_s<q>")]
++)
++
+ (define_insn "*umin<mode>3_neon"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+ 	(umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
+@@ -1208,16 +1306,133 @@
+ 
+ ;; Widening operations
+ 
++(define_expand "widen_ssum<mode>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "")
++	(plus:<V_double_width>
++	 (sign_extend:<V_double_width>
++	  (match_operand:VQI 1 "s_register_operand" ""))
++	 (match_operand:<V_double_width> 2 "s_register_operand" "")))]
++  "TARGET_NEON"
++  {
++    machine_mode mode = GET_MODE (operands[1]);
++    rtx p1, p2;
++
++    p1  = arm_simd_vect_par_cnst_half (mode, false);
++    p2  = arm_simd_vect_par_cnst_half (mode, true);
++
++    if (operands[0] != operands[2])
++      emit_move_insn (operands[0], operands[2]);
++
++    emit_insn (gen_vec_sel_widen_ssum_lo<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p1,
++							 operands[0]));
++    emit_insn (gen_vec_sel_widen_ssum_hi<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p2,
++							 operands[0]));
++    DONE;
++  }
++)
++
++(define_insn "vec_sel_widen_ssum_lo<VQI:mode><VW:mode>3"
++  [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
++	(plus:<VW:V_widen>
++	 (sign_extend:<VW:V_widen>
++	  (vec_select:VW
++	   (match_operand:VQI 1 "s_register_operand" "%w")
++	   (match_operand:VQI 2 "vect_par_constant_low" "")))
++	 (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++  return BYTES_BIG_ENDIAN ?  "vaddw.<V_s_elem>\t%q0, %q3, %f1" :
++    "vaddw.<V_s_elem>\t%q0, %q3, %e1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
++(define_insn "vec_sel_widen_ssum_hi<VQI:mode><VW:mode>3"
++  [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
++	(plus:<VW:V_widen>
++	 (sign_extend:<VW:V_widen>
++	  (vec_select:VW (match_operand:VQI 1 "s_register_operand" "%w")
++			 (match_operand:VQI 2 "vect_par_constant_high" "")))
++	 (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++  return BYTES_BIG_ENDIAN ?  "vaddw.<V_s_elem>\t%q0, %q3, %e1" :
++    "vaddw.<V_s_elem>\t%q0, %q3, %f1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
+ (define_insn "widen_ssum<mode>3"
+   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
+-	(plus:<V_widen> (sign_extend:<V_widen>
+-			  (match_operand:VW 1 "s_register_operand" "%w"))
+-		        (match_operand:<V_widen> 2 "s_register_operand" "w")))]
++	(plus:<V_widen>
++	 (sign_extend:<V_widen>
++	  (match_operand:VW 1 "s_register_operand" "%w"))
++	 (match_operand:<V_widen> 2 "s_register_operand" "w")))]
+   "TARGET_NEON"
+   "vaddw.<V_s_elem>\t%q0, %q2, %P1"
+   [(set_attr "type" "neon_add_widen")]
+ )
+ 
++(define_expand "widen_usum<mode>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "")
++	(plus:<V_double_width>
++	 (zero_extend:<V_double_width>
++	  (match_operand:VQI 1 "s_register_operand" ""))
++	 (match_operand:<V_double_width> 2 "s_register_operand" "")))]
++  "TARGET_NEON"
++  {
++    machine_mode mode = GET_MODE (operands[1]);
++    rtx p1, p2;
++
++    p1  = arm_simd_vect_par_cnst_half (mode, false);
++    p2  = arm_simd_vect_par_cnst_half (mode, true);
++
++    if (operands[0] != operands[2])
++      emit_move_insn (operands[0], operands[2]);
++
++    emit_insn (gen_vec_sel_widen_usum_lo<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p1,
++							 operands[0]));
++    emit_insn (gen_vec_sel_widen_usum_hi<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p2,
++							 operands[0]));
++    DONE;
++  }
++)
++
++(define_insn "vec_sel_widen_usum_lo<VQI:mode><VW:mode>3"
++  [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
++	(plus:<VW:V_widen>
++	 (zero_extend:<VW:V_widen>
++	  (vec_select:VW
++	   (match_operand:VQI 1 "s_register_operand" "%w")
++	   (match_operand:VQI 2 "vect_par_constant_low" "")))
++	 (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++  return BYTES_BIG_ENDIAN ?  "vaddw.<V_u_elem>\t%q0, %q3, %f1" :
++    "vaddw.<V_u_elem>\t%q0, %q3, %e1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
++(define_insn "vec_sel_widen_usum_hi<VQI:mode><VW:mode>3"
++  [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
++	(plus:<VW:V_widen>
++	 (zero_extend:<VW:V_widen>
++	  (vec_select:VW (match_operand:VQI 1 "s_register_operand" "%w")
++			 (match_operand:VQI 2 "vect_par_constant_high" "")))
++	 (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++ return BYTES_BIG_ENDIAN ?  "vaddw.<V_u_elem>\t%q0, %q3, %e1" :
++    "vaddw.<V_u_elem>\t%q0, %q3, %f1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
+ (define_insn "widen_usum<mode>3"
+   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
+ 	(plus:<V_widen> (zero_extend:<V_widen>
+@@ -1488,6 +1703,17 @@
+                     (const_string "neon_reduc_add<q>")))]
+ )
+ 
++(define_insn "neon_vpaddv4hf"
++ [(set
++   (match_operand:V4HF 0 "s_register_operand" "=w")
++   (unspec:V4HF [(match_operand:V4HF 1 "s_register_operand" "w")
++		 (match_operand:V4HF 2 "s_register_operand" "w")]
++    UNSPEC_VPADD))]
++ "TARGET_NEON_FP16INST"
++ "vpadd.f16\t%P0, %P1, %P2"
++ [(set_attr "type" "neon_reduc_add")]
++)
++
+ (define_insn "neon_vpsmin<mode>"
+   [(set (match_operand:VD 0 "s_register_operand" "=w")
+ 	(unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
+@@ -1836,6 +2062,26 @@
+   DONE;
+ })
+ 
++(define_expand "neon_vadd<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_add<mode>3_fp16 (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
++(define_expand "neon_vsub<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_sub<mode>3_fp16 (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
+ ; Note that NEON operations don't support the full IEEE 754 standard: in
+ ; particular, denormal values are flushed to zero.  This means that GCC cannot
+ ; use those instructions for autovectorization, etc. unless
+@@ -1927,6 +2173,17 @@
+                     (const_string "neon_mul_<V_elem_ch><q>")))]
+ )
+ 
++(define_insn "neon_vmulf<mode>"
++ [(set
++   (match_operand:VH 0 "s_register_operand" "=w")
++   (mult:VH
++    (match_operand:VH 1 "s_register_operand" "w")
++    (match_operand:VH 2 "s_register_operand" "w")))]
++  "TARGET_NEON_FP16INST"
++  "vmul.f16\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_mul_<VH_elem_ch><q>")]
++)
++
+ (define_expand "neon_vmla<mode>"
+   [(match_operand:VDQW 0 "s_register_operand" "=w")
+    (match_operand:VDQW 1 "s_register_operand" "0")
+@@ -1955,6 +2212,18 @@
+   DONE;
+ })
+ 
++(define_expand "neon_vfma<VH:mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")
++   (match_operand:VH 3 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_fma<mode>4_intrinsic (operands[0], operands[2], operands[3],
++				       operands[1]));
++  DONE;
++})
++
+ (define_expand "neon_vfms<VCVTF:mode>"
+   [(match_operand:VCVTF 0 "s_register_operand")
+    (match_operand:VCVTF 1 "s_register_operand")
+@@ -1967,6 +2236,18 @@
+   DONE;
+ })
+ 
++(define_expand "neon_vfms<VH:mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")
++   (match_operand:VH 3 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_fmsub<mode>4_intrinsic (operands[0], operands[2], operands[3],
++					 operands[1]));
++  DONE;
++})
++
+ ; Used for intrinsics when flag_unsafe_math_optimizations is false.
+ 
+ (define_insn "neon_vmla<mode>_unspec"
+@@ -2267,6 +2548,72 @@
+   [(set_attr "type" "neon_fp_compare_s<q>")]
+ )
+ 
++(define_expand "neon_vc<cmp_op><mode>"
++ [(match_operand:<V_cmp_result> 0 "s_register_operand")
++  (neg:<V_cmp_result>
++   (COMPARISONS:VH
++    (match_operand:VH 1 "s_register_operand")
++    (match_operand:VH 2 "reg_or_zero_operand")))]
++ "TARGET_NEON_FP16INST"
++{
++  /* For FP comparisons use UNSPECS unless -funsafe-math-optimizations
++     are enabled.  */
++  if (GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT
++      && !flag_unsafe_math_optimizations)
++    emit_insn
++      (gen_neon_vc<cmp_op><mode>_fp16insn_unspec
++       (operands[0], operands[1], operands[2]));
++  else
++    emit_insn
++      (gen_neon_vc<cmp_op><mode>_fp16insn
++       (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
++(define_insn "neon_vc<cmp_op><mode>_fp16insn"
++ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
++   (neg:<V_cmp_result>
++    (COMPARISONS:<V_cmp_result>
++     (match_operand:VH 1 "s_register_operand" "w,w")
++     (match_operand:VH 2 "reg_or_zero_operand" "w,Dz"))))]
++ "TARGET_NEON_FP16INST
++  && !(GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT
++  && !flag_unsafe_math_optimizations)"
++{
++  char pattern[100];
++  sprintf (pattern, "vc<cmp_op>.%s%%#<V_sz_elem>\t%%<V_reg>0,"
++	   " %%<V_reg>1, %s",
++	   GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT
++	   ? "f" : "<cmp_type>",
++	   which_alternative == 0
++	   ? "%<V_reg>2" : "#0");
++  output_asm_insn (pattern, operands);
++  return "";
++}
++ [(set (attr "type")
++   (if_then_else (match_operand 2 "zero_operand")
++    (const_string "neon_compare_zero<q>")
++    (const_string "neon_compare<q>")))])
++
++(define_insn "neon_vc<cmp_op_unsp><mode>_fp16insn_unspec"
++ [(set
++   (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
++   (unspec:<V_cmp_result>
++    [(match_operand:VH 1 "s_register_operand" "w,w")
++     (match_operand:VH 2 "reg_or_zero_operand" "w,Dz")]
++    NEON_VCMP))]
++ "TARGET_NEON_FP16INST"
++{
++  char pattern[100];
++  sprintf (pattern, "vc<cmp_op_unsp>.f%%#<V_sz_elem>\t%%<V_reg>0,"
++	   " %%<V_reg>1, %s",
++	   which_alternative == 0
++	   ? "%<V_reg>2" : "#0");
++  output_asm_insn (pattern, operands);
++  return "";
++}
++ [(set_attr "type" "neon_fp_compare_s<q>")])
++
+ (define_insn "neon_vc<cmp_op>u<mode>"
+   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
+         (neg:<V_cmp_result>
+@@ -2318,6 +2665,60 @@
+   [(set_attr "type" "neon_fp_compare_s<q>")]
+ )
+ 
++(define_expand "neon_vca<cmp_op><mode>"
++  [(set
++    (match_operand:<V_cmp_result> 0 "s_register_operand")
++    (neg:<V_cmp_result>
++     (GLTE:<V_cmp_result>
++      (abs:VH (match_operand:VH 1 "s_register_operand"))
++      (abs:VH (match_operand:VH 2 "s_register_operand")))))]
++ "TARGET_NEON_FP16INST"
++{
++  if (flag_unsafe_math_optimizations)
++    emit_insn (gen_neon_vca<cmp_op><mode>_fp16insn
++	       (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (gen_neon_vca<cmp_op><mode>_fp16insn_unspec
++	       (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
++(define_insn "neon_vca<cmp_op><mode>_fp16insn"
++  [(set
++    (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
++    (neg:<V_cmp_result>
++     (GLTE:<V_cmp_result>
++      (abs:VH (match_operand:VH 1 "s_register_operand" "w"))
++      (abs:VH (match_operand:VH 2 "s_register_operand" "w")))))]
++ "TARGET_NEON_FP16INST && flag_unsafe_math_optimizations"
++ "vac<cmp_op>.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_compare_s<q>")]
++)
++
++(define_insn "neon_vca<cmp_op_unsp><mode>_fp16insn_unspec"
++ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
++   (unspec:<V_cmp_result>
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")]
++    NEON_VAGLTE))]
++ "TARGET_NEON"
++ "vac<cmp_op_unsp>.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_compare_s<q>")]
++)
++
++(define_expand "neon_vc<cmp_op>z<mode>"
++ [(set
++   (match_operand:<V_cmp_result> 0 "s_register_operand")
++   (COMPARISONS:<V_cmp_result>
++    (match_operand:VH 1 "s_register_operand")
++    (const_int 0)))]
++ "TARGET_NEON_FP16INST"
++ {
++  emit_insn (gen_neon_vc<cmp_op><mode> (operands[0], operands[1],
++					CONST0_RTX (<MODE>mode)));
++  DONE;
++})
++
+ (define_insn "neon_vtst<mode>"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+         (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
+@@ -2338,6 +2739,16 @@
+   [(set_attr "type" "neon_abd<q>")]
+ )
+ 
++(define_insn "neon_vabd<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		(match_operand:VH 2 "s_register_operand" "w")]
++     UNSPEC_VABD_F))]
++ "TARGET_NEON_FP16INST"
++ "vabd.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  [(set_attr "type" "neon_abd<q>")]
++)
++
+ (define_insn "neon_vabdf<mode>"
+   [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+         (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
+@@ -2400,6 +2811,51 @@
+   [(set_attr "type" "neon_fp_minmax_s<q>")]
+ )
+ 
++(define_insn "neon_v<maxmin>f<mode>"
++ [(set (match_operand:VH 0 "s_register_operand" "=w")
++   (unspec:VH
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")]
++    VMAXMINF))]
++ "TARGET_NEON_FP16INST"
++ "v<maxmin>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_minmax_s<q>")]
++)
++
++(define_insn "neon_vp<maxmin>fv4hf"
++ [(set (match_operand:V4HF 0 "s_register_operand" "=w")
++   (unspec:V4HF
++    [(match_operand:V4HF 1 "s_register_operand" "w")
++     (match_operand:V4HF 2 "s_register_operand" "w")]
++    VPMAXMINF))]
++ "TARGET_NEON_FP16INST"
++ "vp<maxmin>.f16\t%P0, %P1, %P2"
++  [(set_attr "type" "neon_reduc_minmax")]
++)
++
++(define_insn "neon_<fmaxmin_op><mode>"
++ [(set
++   (match_operand:VH 0 "s_register_operand" "=w")
++   (unspec:VH
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")]
++    VMAXMINFNM))]
++ "TARGET_NEON_FP16INST"
++ "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_minmax_s<q>")]
++)
++
++;; v<maxmin>nm intrinsics.
++(define_insn "neon_<fmaxmin_op><mode>"
++  [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
++	(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
++		       (match_operand:VCVTF 2 "s_register_operand" "w")]
++		       VMAXMINFNM))]
++  "TARGET_NEON && TARGET_FPU_ARMV8"
++  "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  [(set_attr "type" "neon_fp_minmax_s<q>")]
++)
++
+ ;; Vector forms for the IEEE-754 fmax()/fmin() functions
+ (define_insn "<fmaxmin><mode>3"
+   [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+@@ -2471,6 +2927,17 @@
+   [(set_attr "type" "neon_fp_recps_s<q>")]
+ )
+ 
++(define_insn "neon_vrecps<mode>"
++  [(set
++    (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		(match_operand:VH 2 "s_register_operand" "w")]
++     UNSPEC_VRECPS))]
++  "TARGET_NEON_FP16INST"
++  "vrecps.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  [(set_attr "type" "neon_fp_recps_s<q>")]
++)
++
+ (define_insn "neon_vrsqrts<mode>"
+   [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+         (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
+@@ -2481,6 +2948,17 @@
+   [(set_attr "type" "neon_fp_rsqrts_s<q>")]
+ )
+ 
++(define_insn "neon_vrsqrts<mode>"
++  [(set
++    (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		 (match_operand:VH 2 "s_register_operand" "w")]
++     UNSPEC_VRSQRTS))]
++ "TARGET_NEON_FP16INST"
++ "vrsqrts.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_rsqrts_s<q>")]
++)
++
+ (define_expand "neon_vabs<mode>"
+   [(match_operand:VDQW 0 "s_register_operand" "")
+    (match_operand:VDQW 1 "s_register_operand" "")]
+@@ -2596,6 +3074,15 @@
+ })
+ 
+ (define_insn "neon_vrecpe<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++	(unspec:VH [(match_operand:VH 1 "s_register_operand" "w")]
++		   UNSPEC_VRECPE))]
++  "TARGET_NEON_FP16INST"
++  "vrecpe.f16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_fp_recpe_s<q>")]
++)
++
++(define_insn "neon_vrecpe<mode>"
+   [(set (match_operand:V32 0 "s_register_operand" "=w")
+ 	(unspec:V32 [(match_operand:V32 1 "s_register_operand" "w")]
+                     UNSPEC_VRECPE))]
+@@ -2932,6 +3419,28 @@ if (BYTES_BIG_ENDIAN)
+   [(set_attr "type" "neon_dup<q>")]
+ )
+ 
++(define_insn "neon_vdup_lane<mode>_internal"
++ [(set (match_operand:VH 0 "s_register_operand" "=w")
++   (vec_duplicate:VH
++    (vec_select:<V_elem>
++     (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
++     (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
++ "TARGET_NEON && TARGET_FP16"
++{
++  if (BYTES_BIG_ENDIAN)
++    {
++      int elt = INTVAL (operands[2]);
++      elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt;
++      operands[2] = GEN_INT (elt);
++    }
++  if (<Is_d_reg>)
++    return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
++  else
++    return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
++}
++  [(set_attr "type" "neon_dup<q>")]
++)
++
+ (define_expand "neon_vdup_lane<mode>"
+   [(match_operand:VDQW 0 "s_register_operand" "=w")
+    (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
+@@ -2951,6 +3460,25 @@ if (BYTES_BIG_ENDIAN)
+     DONE;
+ })
+ 
++(define_expand "neon_vdup_lane<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:<V_double_vector_mode> 1 "s_register_operand")
++   (match_operand:SI 2 "immediate_operand")]
++  "TARGET_NEON && TARGET_FP16"
++{
++  if (BYTES_BIG_ENDIAN)
++    {
++      unsigned int elt = INTVAL (operands[2]);
++      unsigned int reg_nelts
++	= 64 / GET_MODE_UNIT_BITSIZE (<V_double_vector_mode>mode);
++      elt ^= reg_nelts - 1;
++      operands[2] = GEN_INT (elt);
++    }
++  emit_insn (gen_neon_vdup_lane<mode>_internal (operands[0], operands[1],
++						operands[2]));
++  DONE;
++})
++
+ ; Scalar index is ignored, since only zero is valid here.
+ (define_expand "neon_vdup_lanedi"
+   [(match_operand:DI 0 "s_register_operand" "=w")
+@@ -3097,6 +3625,28 @@ if (BYTES_BIG_ENDIAN)
+   [(set_attr "type" "neon_fp_cvt_narrow_s_q")]
+ )
+ 
++(define_insn "neon_vcvt<sup><mode>"
++ [(set
++   (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VCVTHI 1 "s_register_operand" "w")]
++    VCVT_US))]
++ "TARGET_NEON_FP16INST"
++ "vcvt.f16.<sup>%#16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_int_to_fp_<VH_elem_ch><q>")]
++)
++
++(define_insn "neon_vcvt<sup><mode>"
++ [(set
++   (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VH 1 "s_register_operand" "w")]
++    VCVT_US))]
++ "TARGET_NEON_FP16INST"
++ "vcvt.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
++)
++
+ (define_insn "neon_vcvt<sup>_n<mode>"
+   [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ 	(unspec:<V_CVTTO> [(match_operand:VCVTF 1 "s_register_operand" "w")
+@@ -3111,6 +3661,20 @@ if (BYTES_BIG_ENDIAN)
+ )
+ 
+ (define_insn "neon_vcvt<sup>_n<mode>"
++ [(set (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_US_N))]
++  "TARGET_NEON_FP16INST"
++{
++  neon_const_bounds (operands[2], 0, 17);
++  return "vcvt.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1, %2";
++}
++ [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
++)
++
++(define_insn "neon_vcvt<sup>_n<mode>"
+   [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ 	(unspec:<V_CVTTO> [(match_operand:VCVTI 1 "s_register_operand" "w")
+ 			   (match_operand:SI 2 "immediate_operand" "i")]
+@@ -3123,6 +3687,31 @@ if (BYTES_BIG_ENDIAN)
+   [(set_attr "type" "neon_int_to_fp_<V_elem_ch><q>")]
+ )
+ 
++(define_insn "neon_vcvt<sup>_n<mode>"
++ [(set (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VCVTHI 1 "s_register_operand" "w")
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_US_N))]
++ "TARGET_NEON_FP16INST"
++{
++  neon_const_bounds (operands[2], 0, 17);
++  return "vcvt.f16.<sup>%#16\t%<V_reg>0, %<V_reg>1, %2";
++}
++ [(set_attr "type" "neon_int_to_fp_<VH_elem_ch><q>")]
++)
++
++(define_insn "neon_vcvt<vcvth_op><sup><mode>"
++ [(set
++   (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VH 1 "s_register_operand" "w")]
++    VCVT_HF_US))]
++ "TARGET_NEON_FP16INST"
++ "vcvt<vcvth_op>.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
++)
++
+ (define_insn "neon_vmovn<mode>"
+   [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
+ 	(unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")]
+@@ -3193,6 +3782,18 @@ if (BYTES_BIG_ENDIAN)
+                    (const_string "neon_mul_<V_elem_ch>_scalar<q>")))]
+ )
+ 
++(define_insn "neon_vmul_lane<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++	(unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		    (match_operand:V4HF 2 "s_register_operand"
++		     "<scalar_mul_constraint>")
++		     (match_operand:SI 3 "immediate_operand" "i")]
++		     UNSPEC_VMUL_LANE))]
++  "TARGET_NEON_FP16INST"
++  "vmul.f16\t%<V_reg>0, %<V_reg>1, %P2[%c3]"
++  [(set_attr "type" "neon_fp_mul_s_scalar<q>")]
++)
++
+ (define_insn "neon_vmull<sup>_lane<mode>"
+   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
+ 	(unspec:<V_widen> [(match_operand:VMDI 1 "s_register_operand" "w")
+@@ -3447,6 +4048,19 @@ if (BYTES_BIG_ENDIAN)
+   DONE;
+ })
+ 
++(define_expand "neon_vmul_n<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:<V_elem> 2 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  rtx tmp = gen_reg_rtx (V4HFmode);
++  emit_insn (gen_neon_vset_lanev4hf (tmp, operands[2], tmp, const0_rtx));
++  emit_insn (gen_neon_vmul_lane<mode> (operands[0], operands[1], tmp,
++				       const0_rtx));
++  DONE;
++})
++
+ (define_expand "neon_vmulls_n<mode>"
+   [(match_operand:<V_widen> 0 "s_register_operand" "")
+    (match_operand:VMDI 1 "s_register_operand" "")
+@@ -4168,25 +4782,25 @@ if (BYTES_BIG_ENDIAN)
+ 
+ (define_expand "neon_vtrn<mode>_internal"
+   [(parallel
+-    [(set (match_operand:VDQW 0 "s_register_operand" "")
+-	  (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
+-			(match_operand:VDQW 2 "s_register_operand" "")]
++    [(set (match_operand:VDQWH 0 "s_register_operand")
++	  (unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand")
++			 (match_operand:VDQWH 2 "s_register_operand")]
+ 	   UNSPEC_VTRN1))
+-     (set (match_operand:VDQW 3 "s_register_operand" "")
+-          (unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VTRN2))])]
++     (set (match_operand:VDQWH 3 "s_register_operand")
++	  (unspec:VDQWH [(match_dup 1) (match_dup 2)] UNSPEC_VTRN2))])]
+   "TARGET_NEON"
+   ""
+ )
+ 
+ ;; Note: Different operand numbering to handle tied registers correctly.
+ (define_insn "*neon_vtrn<mode>_insn"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-                      (match_operand:VDQW 3 "s_register_operand" "2")]
+-                     UNSPEC_VTRN1))
+-   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
+-         (unspec:VDQW [(match_dup 1) (match_dup 3)]
+-                     UNSPEC_VTRN2))]
++  [(set (match_operand:VDQWH 0 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand" "0")
++		       (match_operand:VDQWH 3 "s_register_operand" "2")]
++	 UNSPEC_VTRN1))
++   (set (match_operand:VDQWH 2 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_dup 1) (match_dup 3)]
++	 UNSPEC_VTRN2))]
+   "TARGET_NEON"
+   "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+   [(set_attr "type" "neon_permute<q>")]
+@@ -4194,25 +4808,25 @@ if (BYTES_BIG_ENDIAN)
+ 
+ (define_expand "neon_vzip<mode>_internal"
+   [(parallel
+-    [(set (match_operand:VDQW 0 "s_register_operand" "")
+-	  (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
+-	  	        (match_operand:VDQW 2 "s_register_operand" "")]
+-		       UNSPEC_VZIP1))
+-    (set (match_operand:VDQW 3 "s_register_operand" "")
+-	 (unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VZIP2))])]
++    [(set (match_operand:VDQWH 0 "s_register_operand")
++	  (unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand")
++			 (match_operand:VDQWH 2 "s_register_operand")]
++	   UNSPEC_VZIP1))
++    (set (match_operand:VDQWH 3 "s_register_operand")
++	 (unspec:VDQWH [(match_dup 1) (match_dup 2)] UNSPEC_VZIP2))])]
+   "TARGET_NEON"
+   ""
+ )
+ 
+ ;; Note: Different operand numbering to handle tied registers correctly.
+ (define_insn "*neon_vzip<mode>_insn"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-                      (match_operand:VDQW 3 "s_register_operand" "2")]
+-                     UNSPEC_VZIP1))
+-   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_dup 1) (match_dup 3)]
+-                     UNSPEC_VZIP2))]
++  [(set (match_operand:VDQWH 0 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand" "0")
++		       (match_operand:VDQWH 3 "s_register_operand" "2")]
++	 UNSPEC_VZIP1))
++   (set (match_operand:VDQWH 2 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_dup 1) (match_dup 3)]
++	 UNSPEC_VZIP2))]
+   "TARGET_NEON"
+   "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+   [(set_attr "type" "neon_zip<q>")]
+@@ -4220,25 +4834,25 @@ if (BYTES_BIG_ENDIAN)
+ 
+ (define_expand "neon_vuzp<mode>_internal"
+   [(parallel
+-    [(set (match_operand:VDQW 0 "s_register_operand" "")
+-	  (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
+-			(match_operand:VDQW 2 "s_register_operand" "")]
++    [(set (match_operand:VDQWH 0 "s_register_operand")
++	  (unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand")
++			(match_operand:VDQWH 2 "s_register_operand")]
+ 	   UNSPEC_VUZP1))
+-     (set (match_operand:VDQW 3 "s_register_operand" "")
+-	  (unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VUZP2))])]
++     (set (match_operand:VDQWH 3 "s_register_operand" "")
++	  (unspec:VDQWH [(match_dup 1) (match_dup 2)] UNSPEC_VUZP2))])]
+   "TARGET_NEON"
+   ""
+ )
+ 
+ ;; Note: Different operand numbering to handle tied registers correctly.
+ (define_insn "*neon_vuzp<mode>_insn"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-                      (match_operand:VDQW 3 "s_register_operand" "2")]
+-                     UNSPEC_VUZP1))
+-   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_dup 1) (match_dup 3)]
+-                     UNSPEC_VUZP2))]
++  [(set (match_operand:VDQWH 0 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand" "0")
++		       (match_operand:VDQWH 3 "s_register_operand" "2")]
++	 UNSPEC_VUZP1))
++   (set (match_operand:VDQWH 2 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_dup 1) (match_dup 3)]
++	 UNSPEC_VUZP2))]
+   "TARGET_NEON"
+   "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+   [(set_attr "type" "neon_zip<q>")]
+--- a/src/gcc/config/arm/neon.ml
++++ b/src//dev/null
+@@ -1,2357 +0,0 @@
+-(* Common code for ARM NEON header file, documentation and test case
+-   generators.
+-
+-   Copyright (C) 2006-2016 Free Software Foundation, Inc.
+-   Contributed by CodeSourcery.
+-
+-   This file is part of GCC.
+-
+-   GCC is free software; you can redistribute it and/or modify it under
+-   the terms of the GNU General Public License as published by the Free
+-   Software Foundation; either version 3, or (at your option) any later
+-   version.
+-
+-   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+-   WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-   for more details.
+-
+-   You should have received a copy of the GNU General Public License
+-   along with GCC; see the file COPYING3.  If not see
+-   <http://www.gnu.org/licenses/>.  *)
+-
+-(* Shorthand types for vector elements.  *)
+-type elts = S8 | S16 | S32 | S64 | F16 | F32 | U8 | U16 | U32 | U64 | P8 | P16
+-          | P64 | P128 | I8 | I16 | I32 | I64 | B8 | B16 | B32 | B64 | Conv of elts * elts
+-          | Cast of elts * elts | NoElts
+-
+-type eltclass = Signed | Unsigned | Float | Poly | Int | Bits
+-	      | ConvClass of eltclass * eltclass | NoType
+-
+-(* These vector types correspond directly to C types.  *)
+-type vectype = T_int8x8    | T_int8x16
+-             | T_int16x4   | T_int16x8
+-	     | T_int32x2   | T_int32x4
+-	     | T_int64x1   | T_int64x2
+-	     | T_uint8x8   | T_uint8x16
+-	     | T_uint16x4  | T_uint16x8
+-	     | T_uint32x2  | T_uint32x4
+-	     | T_uint64x1  | T_uint64x2
+-	     | T_float16x4
+-	     | T_float32x2 | T_float32x4
+-	     | T_poly8x8   | T_poly8x16
+-	     | T_poly16x4  | T_poly16x8
+-	     | T_immediate of int * int
+-             | T_int8      | T_int16
+-             | T_int32     | T_int64
+-             | T_uint8     | T_uint16
+-             | T_uint32    | T_uint64
+-             | T_poly8     | T_poly16
+-             | T_poly64    | T_poly64x1
+-             | T_poly64x2  | T_poly128
+-             | T_float16   | T_float32
+-             | T_arrayof of int * vectype
+-             | T_ptrto of vectype | T_const of vectype
+-             | T_void      | T_intQI
+-             | T_intHI     | T_intSI
+-             | T_intDI     | T_intTI
+-             | T_floatHF   | T_floatSF
+-
+-(* The meanings of the following are:
+-     TImode : "Tetra", two registers (four words).
+-     EImode : "hExa", three registers (six words).
+-     OImode : "Octa", four registers (eight words).
+-     CImode : "dodeCa", six registers (twelve words).
+-     XImode : "heXadeca", eight registers (sixteen words).
+-*)
+-
+-type inttype = B_TImode | B_EImode | B_OImode | B_CImode | B_XImode
+-
+-type shape_elt = Dreg | Qreg | Corereg | Immed | VecArray of int * shape_elt
+-               | PtrTo of shape_elt | CstPtrTo of shape_elt
+-	       (* These next ones are used only in the test generator.  *)
+-	       | Element_of_dreg	(* Used for "lane" variants.  *)
+-	       | Element_of_qreg	(* Likewise.  *)
+-	       | All_elements_of_dreg	(* Used for "dup" variants.  *)
+-	       | Alternatives of shape_elt list (* Used for multiple valid operands *)
+-
+-type shape_form = All of int * shape_elt
+-                | Long
+-		| Long_noreg of shape_elt
+-		| Wide
+-		| Wide_noreg of shape_elt
+-		| Narrow
+-                | Long_imm
+-                | Narrow_imm
+-                | Binary_imm of shape_elt
+-                | Use_operands of shape_elt array
+-                | By_scalar of shape_elt
+-                | Unary_scalar of shape_elt
+-                | Wide_lane
+-                | Wide_scalar
+-                | Pair_result of shape_elt
+-
+-type arity = Arity0 of vectype
+-           | Arity1 of vectype * vectype
+-	   | Arity2 of vectype * vectype * vectype
+-	   | Arity3 of vectype * vectype * vectype * vectype
+-           | Arity4 of vectype * vectype * vectype * vectype * vectype
+-
+-type vecmode = V8QI | V4HI | V4HF |V2SI | V2SF | DI
+-             | V16QI | V8HI | V4SI | V4SF | V2DI | TI
+-             | QI | HI | SI | SF
+-
+-type opcode =
+-  (* Binary ops.  *)
+-    Vadd
+-  | Vmul
+-  | Vmla
+-  | Vmls
+-  | Vfma
+-  | Vfms
+-  | Vsub
+-  | Vceq
+-  | Vcge
+-  | Vcgt
+-  | Vcle
+-  | Vclt
+-  | Vcage
+-  | Vcagt
+-  | Vcale
+-  | Vcalt
+-  | Vtst
+-  | Vabd
+-  | Vaba
+-  | Vmax
+-  | Vmin
+-  | Vpadd
+-  | Vpada
+-  | Vpmax
+-  | Vpmin
+-  | Vrecps
+-  | Vrsqrts
+-  | Vshl
+-  | Vshr_n
+-  | Vshl_n
+-  | Vsra_n
+-  | Vsri
+-  | Vsli
+-  (* Logic binops.  *)
+-  | Vand
+-  | Vorr
+-  | Veor
+-  | Vbic
+-  | Vorn
+-  | Vbsl
+-  (* Ops with scalar.  *)
+-  | Vmul_lane
+-  | Vmla_lane
+-  | Vmls_lane
+-  | Vmul_n
+-  | Vmla_n
+-  | Vmls_n
+-  | Vmull_n
+-  | Vmull_lane
+-  | Vqdmull_n
+-  | Vqdmull_lane
+-  | Vqdmulh_n
+-  | Vqdmulh_lane
+-  (* Unary ops.  *)
+-  | Vrintn
+-  | Vrinta
+-  | Vrintp
+-  | Vrintm
+-  | Vrintz
+-  | Vabs
+-  | Vneg
+-  | Vcls
+-  | Vclz
+-  | Vcnt
+-  | Vrecpe
+-  | Vrsqrte
+-  | Vmvn
+-  (* Vector extract.  *)
+-  | Vext
+-  (* Reverse elements.  *)
+-  | Vrev64
+-  | Vrev32
+-  | Vrev16
+-  (* Transposition ops.  *)
+-  | Vtrn
+-  | Vzip
+-  | Vuzp
+-  (* Loads and stores (VLD1/VST1/VLD2...), elements and structures.  *)
+-  | Vldx of int
+-  | Vstx of int
+-  | Vldx_lane of int
+-  | Vldx_dup of int
+-  | Vstx_lane of int
+-  (* Set/extract lanes from a vector.  *)
+-  | Vget_lane
+-  | Vset_lane
+-  (* Initialize vector from bit pattern.  *)
+-  | Vcreate
+-  (* Set all lanes to same value.  *)
+-  | Vdup_n
+-  | Vmov_n  (* Is this the same?  *)
+-  (* Duplicate scalar to all lanes of vector.  *)
+-  | Vdup_lane
+-  (* Combine vectors.  *)
+-  | Vcombine
+-  (* Get quadword high/low parts.  *)
+-  | Vget_high
+-  | Vget_low
+-  (* Convert vectors.  *)
+-  | Vcvt
+-  | Vcvt_n
+-  (* Narrow/lengthen vectors.  *)
+-  | Vmovn
+-  | Vmovl
+-  (* Table lookup.  *)
+-  | Vtbl of int
+-  | Vtbx of int
+-  (* Reinterpret casts.  *)
+-  | Vreinterp
+-
+-let rev_elems revsize elsize nelts _ =
+-  let mask = (revsize / elsize) - 1 in
+-  let arr = Array.init nelts
+-    (fun i -> i lxor mask) in
+-  Array.to_list arr
+-
+-let permute_range i stride nelts increment =
+-  let rec build i = function
+-    0 -> []
+-  | nelts -> i :: (i + stride) :: build (i + increment) (pred nelts) in
+-  build i nelts
+-
+-(* Generate a list of integers suitable for vzip.  *)
+-let zip_range i stride nelts = permute_range i stride nelts 1
+-
+-(* Generate a list of integers suitable for vunzip.  *)
+-let uzip_range i stride nelts = permute_range i stride nelts 4
+-
+-(* Generate a list of integers suitable for trn.  *)
+-let trn_range i stride nelts = permute_range i stride nelts 2
+-
+-let zip_elems _ nelts part =
+-  match part with
+-    `lo -> zip_range 0 nelts (nelts / 2)
+-  | `hi -> zip_range (nelts / 2) nelts (nelts / 2)
+-
+-let uzip_elems _ nelts part =
+-  match part with
+-    `lo -> uzip_range 0 2 (nelts / 2)
+-  | `hi -> uzip_range 1 2 (nelts / 2)
+-
+-let trn_elems _ nelts part =
+-  match part with
+-    `lo -> trn_range 0 nelts (nelts / 2)
+-  | `hi -> trn_range 1 nelts (nelts / 2)
+-
+-(* Features used for documentation, to distinguish between some instruction
+-   variants, and to signal special requirements (e.g. swapping arguments).  *)
+-
+-type features =
+-    Halving
+-  | Rounding
+-  | Saturating
+-  | Dst_unsign
+-  | High_half
+-  | Doubling
+-  | Flipped of string  (* Builtin name to use with flipped arguments.  *)
+-  | InfoWord  (* Pass an extra word for signage/rounding etc. (always passed
+-                 for All _, Long, Wide, Narrow shape_forms.  *)
+-    (* Implement builtin as shuffle.  The parameter is a function which returns
+-       masks suitable for __builtin_shuffle: arguments are (element size,
+-       number of elements, high/low part selector).  *)
+-  | Use_shuffle of (int -> int -> [`lo|`hi] -> int list)
+-    (* A specification as to the shape of instruction expected upon
+-       disassembly, used if it differs from the shape used to build the
+-       intrinsic prototype.  Multiple entries in the constructor's argument
+-       indicate that the intrinsic expands to more than one assembly
+-       instruction, each with a corresponding shape specified here.  *)
+-  | Disassembles_as of shape_form list
+-  | Builtin_name of string  (* Override the name of the builtin.  *)
+-    (* Override the name of the instruction.  If more than one name
+-       is specified, it means that the instruction can have any of those
+-       names.  *)
+-  | Instruction_name of string list
+-    (* Mark that the intrinsic yields no instructions, or expands to yield
+-       behavior that the test generator cannot test.  *)
+-  | No_op
+-    (* Mark that the intrinsic has constant arguments that cannot be set
+-       to the defaults (zero for pointers and one otherwise) in the test
+-       cases.  The function supplied must return the integer to be written
+-       into the testcase for the argument number (0-based) supplied to it.  *)
+-  | Const_valuator of (int -> int)
+-  | Fixed_vector_reg
+-  | Fixed_core_reg
+-    (* Mark that the intrinsic requires __ARM_FEATURE_string to be defined.  *)
+-  | Requires_feature of string
+-    (* Mark that the intrinsic requires a particular architecture version.  *)
+-  | Requires_arch of int
+-    (* Mark that the intrinsic requires a particular bit in __ARM_FP to
+-    be set.   *)
+-  | Requires_FP_bit of int
+-    (* Compiler optimization level for the test.  *)
+-  | Compiler_optim of string
+-
+-exception MixedMode of elts * elts
+-
+-let rec elt_width = function
+-    S8 | U8 | P8 | I8 | B8 -> 8
+-  | S16 | U16 | P16 | I16 | B16 | F16 -> 16
+-  | S32 | F32 | U32 | I32 | B32 -> 32
+-  | S64 | U64 | P64 | I64 | B64 -> 64
+-  | P128 -> 128
+-  | Conv (a, b) ->
+-      let wa = elt_width a and wb = elt_width b in
+-      if wa = wb then wa else raise (MixedMode (a, b))
+-  | Cast (a, b) -> raise (MixedMode (a, b))
+-  | NoElts -> failwith "No elts"
+-
+-let rec elt_class = function
+-    S8 | S16 | S32 | S64 -> Signed
+-  | U8 | U16 | U32 | U64 -> Unsigned
+-  | P8 | P16 | P64 | P128 -> Poly
+-  | F16 | F32 -> Float
+-  | I8 | I16 | I32 | I64 -> Int
+-  | B8 | B16 | B32 | B64 -> Bits
+-  | Conv (a, b) | Cast (a, b) -> ConvClass (elt_class a, elt_class b)
+-  | NoElts -> NoType
+-
+-let elt_of_class_width c w =
+-  match c, w with
+-    Signed, 8 -> S8
+-  | Signed, 16 -> S16
+-  | Signed, 32 -> S32
+-  | Signed, 64 -> S64
+-  | Float, 16 -> F16
+-  | Float, 32 -> F32
+-  | Unsigned, 8 -> U8
+-  | Unsigned, 16 -> U16
+-  | Unsigned, 32 -> U32
+-  | Unsigned, 64 -> U64
+-  | Poly, 8 -> P8
+-  | Poly, 16 -> P16
+-  | Poly, 64 -> P64
+-  | Poly, 128 -> P128
+-  | Int, 8 -> I8
+-  | Int, 16 -> I16
+-  | Int, 32 -> I32
+-  | Int, 64 -> I64
+-  | Bits, 8 -> B8
+-  | Bits, 16 -> B16
+-  | Bits, 32 -> B32
+-  | Bits, 64 -> B64
+-  | _ -> failwith "Bad element type"
+-
+-(* Return unsigned integer element the same width as argument.  *)
+-let unsigned_of_elt elt =
+-  elt_of_class_width Unsigned (elt_width elt)
+-
+-let signed_of_elt elt =
+-  elt_of_class_width Signed (elt_width elt)
+-
+-(* Return untyped bits element the same width as argument.  *)
+-let bits_of_elt elt =
+-  elt_of_class_width Bits (elt_width elt)
+-
+-let non_signed_variant = function
+-    S8 -> I8
+-  | S16 -> I16
+-  | S32 -> I32
+-  | S64 -> I64
+-  | U8 -> I8
+-  | U16 -> I16
+-  | U32 -> I32
+-  | U64 -> I64
+-  | x -> x
+-
+-let poly_unsigned_variant v =
+-  let elclass = match elt_class v with
+-    Poly -> Unsigned
+-  | x -> x in
+-  elt_of_class_width elclass (elt_width v)
+-
+-let widen_elt elt =
+-  let w = elt_width elt
+-  and c = elt_class elt in
+-  elt_of_class_width c (w * 2)
+-
+-let narrow_elt elt =
+-  let w = elt_width elt
+-  and c = elt_class elt in
+-  elt_of_class_width c (w / 2)
+-
+-(* If we're trying to find a mode from a "Use_operands" instruction, use the
+-   last vector operand as the dominant mode used to invoke the correct builtin.
+-   We must stick to this rule in neon.md.  *)
+-let find_key_operand operands =
+-  let rec scan opno =
+-    match operands.(opno) with
+-      Qreg -> Qreg
+-    | Dreg -> Dreg
+-    | VecArray (_, Qreg) -> Qreg
+-    | VecArray (_, Dreg) -> Dreg
+-    | _ -> scan (opno-1)
+-  in
+-    scan ((Array.length operands) - 1)
+-
+-(* Find a vecmode from a shape_elt ELT for an instruction with shape_form
+-   SHAPE.  For a Use_operands shape, if ARGPOS is passed then return the mode
+-   for the given argument position, else determine which argument to return a
+-   mode for automatically.  *)
+-
+-let rec mode_of_elt ?argpos elt shape =
+-  let flt = match elt_class elt with
+-    Float | ConvClass(_, Float) -> true | _ -> false in
+-  let idx =
+-    match elt_width elt with
+-      8 -> 0 | 16 -> 1 | 32 -> 2 | 64 -> 3 | 128 -> 4
+-    | _ -> failwith "Bad element width"
+-  in match shape with
+-    All (_, Dreg) | By_scalar Dreg | Pair_result Dreg | Unary_scalar Dreg
+-  | Binary_imm Dreg | Long_noreg Dreg | Wide_noreg Dreg ->
+-      if flt then
+-        [| V8QI; V4HF; V2SF; DI |].(idx)
+-      else
+-        [| V8QI; V4HI; V2SI; DI |].(idx)
+-  | All (_, Qreg) | By_scalar Qreg | Pair_result Qreg | Unary_scalar Qreg
+-  | Binary_imm Qreg | Long_noreg Qreg | Wide_noreg Qreg ->
+-      [| V16QI; V8HI; if flt then V4SF else V4SI; V2DI; TI|].(idx)
+-  | All (_, (Corereg | PtrTo _ | CstPtrTo _)) ->
+-      [| QI; HI; if flt then SF else SI; DI |].(idx)
+-  | Long | Wide | Wide_lane | Wide_scalar
+-  | Long_imm ->
+-      [| V8QI; V4HI; V2SI; DI |].(idx)
+-  | Narrow | Narrow_imm -> [| V16QI; V8HI; V4SI; V2DI |].(idx)
+-  | Use_operands ops ->
+-      begin match argpos with
+-        None -> mode_of_elt ?argpos elt (All (0, (find_key_operand ops)))
+-      | Some pos -> mode_of_elt ?argpos elt (All (0, ops.(pos)))
+-      end
+-  | _ -> failwith "invalid shape"
+-
+-(* Modify an element type dependent on the shape of the instruction and the
+-   operand number.  *)
+-
+-let shapemap shape no =
+-  let ident = fun x -> x in
+-  match shape with
+-    All _ | Use_operands _ | By_scalar _ | Pair_result _ | Unary_scalar _
+-  | Binary_imm _ -> ident
+-  | Long | Long_noreg _ | Wide_scalar | Long_imm ->
+-      [| widen_elt; ident; ident |].(no)
+-  | Wide | Wide_noreg _ -> [| widen_elt; widen_elt; ident |].(no)
+-  | Wide_lane -> [| widen_elt; ident; ident; ident |].(no)
+-  | Narrow | Narrow_imm -> [| narrow_elt; ident; ident |].(no)
+-
+-(* Register type (D/Q) of an operand, based on shape and operand number.  *)
+-
+-let regmap shape no =
+-  match shape with
+-    All (_, reg) | Long_noreg reg | Wide_noreg reg -> reg
+-  | Long -> [| Qreg; Dreg; Dreg |].(no)
+-  | Wide -> [| Qreg; Qreg; Dreg |].(no)
+-  | Narrow -> [| Dreg; Qreg; Qreg |].(no)
+-  | Wide_lane -> [| Qreg; Dreg; Dreg; Immed |].(no)
+-  | Wide_scalar -> [| Qreg; Dreg; Corereg |].(no)
+-  | By_scalar reg -> [| reg; reg; Dreg; Immed |].(no)
+-  | Unary_scalar reg -> [| reg; Dreg; Immed |].(no)
+-  | Pair_result reg -> [| VecArray (2, reg); reg; reg |].(no)
+-  | Binary_imm reg -> [| reg; reg; Immed |].(no)
+-  | Long_imm -> [| Qreg; Dreg; Immed |].(no)
+-  | Narrow_imm -> [| Dreg; Qreg; Immed |].(no)
+-  | Use_operands these -> these.(no)
+-
+-let type_for_elt shape elt no =
+-  let elt = (shapemap shape no) elt in
+-  let reg = regmap shape no in
+-  let rec type_for_reg_elt reg elt =
+-    match reg with
+-      Dreg ->
+-        begin match elt with
+-          S8 -> T_int8x8
+-        | S16 -> T_int16x4
+-        | S32 -> T_int32x2
+-        | S64 -> T_int64x1
+-        | U8 -> T_uint8x8
+-        | U16 -> T_uint16x4
+-        | U32 -> T_uint32x2
+-        | U64 -> T_uint64x1
+-        | P64 -> T_poly64x1
+-        | P128 -> T_poly128
+-        | F16 -> T_float16x4
+-        | F32 -> T_float32x2
+-        | P8 -> T_poly8x8
+-        | P16 -> T_poly16x4
+-        | _ -> failwith "Bad elt type for Dreg"
+-        end
+-    | Qreg ->
+-        begin match elt with
+-          S8 -> T_int8x16
+-        | S16 -> T_int16x8
+-        | S32 -> T_int32x4
+-        | S64 -> T_int64x2
+-        | U8 -> T_uint8x16
+-        | U16 -> T_uint16x8
+-        | U32 -> T_uint32x4
+-        | U64 -> T_uint64x2
+-        | F32 -> T_float32x4
+-        | P8 -> T_poly8x16
+-        | P16 -> T_poly16x8
+-        | P64 -> T_poly64x2
+-        | P128 -> T_poly128
+-        | _ -> failwith "Bad elt type for Qreg"
+-        end
+-    | Corereg ->
+-        begin match elt with
+-          S8 -> T_int8
+-        | S16 -> T_int16
+-        | S32 -> T_int32
+-        | S64 -> T_int64
+-        | U8 -> T_uint8
+-        | U16 -> T_uint16
+-        | U32 -> T_uint32
+-        | U64 -> T_uint64
+-        | P8 -> T_poly8
+-        | P16 -> T_poly16
+-        | P64 -> T_poly64
+-        | P128 -> T_poly128
+-        | F32 -> T_float32
+-        | _ -> failwith "Bad elt type for Corereg"
+-        end
+-    | Immed ->
+-        T_immediate (0, 0)
+-    | VecArray (num, sub) ->
+-        T_arrayof (num, type_for_reg_elt sub elt)
+-    | PtrTo x ->
+-        T_ptrto (type_for_reg_elt x elt)
+-    | CstPtrTo x ->
+-        T_ptrto (T_const (type_for_reg_elt x elt))
+-    (* Anything else is solely for the use of the test generator.  *)
+-    | _ -> assert false
+-  in
+-    type_for_reg_elt reg elt
+-
+-(* Return size of a vector type, in bits.  *)
+-let vectype_size = function
+-    T_int8x8 | T_int16x4 | T_int32x2 | T_int64x1
+-  | T_uint8x8 | T_uint16x4 | T_uint32x2 | T_uint64x1
+-  | T_float32x2 | T_poly8x8 | T_poly64x1 | T_poly16x4 | T_float16x4 -> 64
+-  | T_int8x16 | T_int16x8 | T_int32x4 | T_int64x2
+-  | T_uint8x16 | T_uint16x8  | T_uint32x4  | T_uint64x2
+-  | T_float32x4 | T_poly8x16 | T_poly64x2 | T_poly16x8 -> 128
+-  | _ -> raise Not_found
+-
+-let inttype_for_array num elttype =
+-  let eltsize = vectype_size elttype in
+-  let numwords = (num * eltsize) / 32 in
+-  match numwords with
+-    4 -> B_TImode
+-  | 6 -> B_EImode
+-  | 8 -> B_OImode
+-  | 12 -> B_CImode
+-  | 16 -> B_XImode
+-  | _ -> failwith ("no int type for size " ^ string_of_int numwords)
+-
+-(* These functions return pairs of (internal, external) types, where "internal"
+-   types are those seen by GCC, and "external" are those seen by the assembler.
+-   These types aren't necessarily the same, since the intrinsics can munge more
+-   than one C type into each assembler opcode.  *)
+-
+-let make_sign_invariant func shape elt =
+-  let arity, elt' = func shape elt in
+-  arity, non_signed_variant elt'
+-
+-(* Don't restrict any types.  *)
+-
+-let elts_same make_arity shape elt =
+-  let vtype = type_for_elt shape elt in
+-  make_arity vtype, elt
+-
+-(* As sign_invar_*, but when sign matters.  *)
+-let elts_same_io_lane =
+-  elts_same (fun vtype -> Arity4 (vtype 0, vtype 0, vtype 1, vtype 2, vtype 3))
+-
+-let elts_same_io =
+-  elts_same (fun vtype -> Arity3 (vtype 0, vtype 0, vtype 1, vtype 2))
+-
+-let elts_same_2_lane =
+-  elts_same (fun vtype -> Arity3 (vtype 0, vtype 1, vtype 2, vtype 3))
+-
+-let elts_same_3 = elts_same_2_lane
+-
+-let elts_same_2 =
+-  elts_same (fun vtype -> Arity2 (vtype 0, vtype 1, vtype 2))
+-
+-let elts_same_1 =
+-  elts_same (fun vtype -> Arity1 (vtype 0, vtype 1))
+-
+-(* Use for signed/unsigned invariant operations (i.e. where the operation
+-   doesn't depend on the sign of the data.  *)
+-
+-let sign_invar_io_lane = make_sign_invariant elts_same_io_lane
+-let sign_invar_io = make_sign_invariant elts_same_io
+-let sign_invar_2_lane = make_sign_invariant elts_same_2_lane
+-let sign_invar_2 = make_sign_invariant elts_same_2
+-let sign_invar_1 = make_sign_invariant elts_same_1
+-
+-(* Sign-sensitive comparison.  *)
+-
+-let cmp_sign_matters shape elt =
+-  let vtype = type_for_elt shape elt
+-  and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in
+-  Arity2 (rtype, vtype 1, vtype 2), elt
+-
+-(* Signed/unsigned invariant comparison.  *)
+-
+-let cmp_sign_invar shape elt =
+-  let shape', elt' = cmp_sign_matters shape elt in
+-  let elt'' =
+-    match non_signed_variant elt' with
+-      P8 -> I8
+-    | x -> x
+-  in
+-    shape', elt''
+-
+-(* Comparison (VTST) where only the element width matters.  *)
+-
+-let cmp_bits shape elt =
+-  let vtype = type_for_elt shape elt
+-  and rtype = type_for_elt shape (unsigned_of_elt elt) 0
+-  and bits_only = bits_of_elt elt in
+-  Arity2 (rtype, vtype 1, vtype 2), bits_only
+-
+-let reg_shift shape elt =
+-  let vtype = type_for_elt shape elt
+-  and op2type = type_for_elt shape (signed_of_elt elt) 2 in
+-  Arity2 (vtype 0, vtype 1, op2type), elt
+-
+-(* Genericised constant-shift type-generating function.  *)
+-
+-let const_shift mkimm ?arity ?result shape elt =
+-  let op2type = (shapemap shape 2) elt in
+-  let op2width = elt_width op2type in
+-  let op2 = mkimm op2width
+-  and op1 = type_for_elt shape elt 1
+-  and r_elt =
+-    match result with
+-      None -> elt
+-    | Some restriction -> restriction elt in
+-  let rtype = type_for_elt shape r_elt 0 in
+-  match arity with
+-    None -> Arity2 (rtype, op1, op2), elt
+-  | Some mkarity -> mkarity rtype op1 op2, elt
+-
+-(* Use for immediate right-shifts.  *)
+-
+-let shift_right shape elt =
+-  const_shift (fun imm -> T_immediate (1, imm)) shape elt
+-
+-let shift_right_acc shape elt =
+-  const_shift (fun imm -> T_immediate (1, imm))
+-    ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt
+-
+-(* Use for immediate right-shifts when the operation doesn't care about
+-   signedness.  *)
+-
+-let shift_right_sign_invar =
+-  make_sign_invariant shift_right
+-
+-(* Immediate right-shift; result is unsigned even when operand is signed.  *)
+-
+-let shift_right_to_uns shape elt =
+-  const_shift (fun imm -> T_immediate (1, imm)) ~result:unsigned_of_elt
+-    shape elt
+-
+-(* Immediate left-shift.  *)
+-
+-let shift_left shape elt =
+-  const_shift (fun imm -> T_immediate (0, imm - 1)) shape elt
+-
+-(* Immediate left-shift, unsigned result.  *)
+-
+-let shift_left_to_uns shape elt =
+-  const_shift (fun imm -> T_immediate (0, imm - 1)) ~result:unsigned_of_elt
+-    shape elt
+-
+-(* Immediate left-shift, don't care about signs.  *)
+-
+-let shift_left_sign_invar =
+-  make_sign_invariant shift_left
+-
+-(* Shift left/right and insert: only element size matters.  *)
+-
+-let shift_insert shape elt =
+-  let arity, elt =
+-    const_shift (fun imm -> T_immediate (1, imm))
+-    ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt in
+-  arity, bits_of_elt elt
+-
+-(* Get/set lane.  *)
+-
+-let get_lane shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity2 (vtype 0, vtype 1, vtype 2),
+-    (match elt with P8 -> U8 | P16 -> U16 | S32 | U32 | F32 -> B32 | x -> x)
+-
+-let set_lane shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt
+-
+-let set_lane_notype shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), NoElts
+-
+-let create_vector shape elt =
+-  let vtype = type_for_elt shape U64 1
+-  and rtype = type_for_elt shape elt 0 in
+-  Arity1 (rtype, vtype), elt
+-
+-let conv make_arity shape elt =
+-  let edest, esrc = match elt with
+-    Conv (edest, esrc) | Cast (edest, esrc) -> edest, esrc
+-  | _ -> failwith "Non-conversion element in conversion" in
+-  let vtype = type_for_elt shape esrc
+-  and rtype = type_for_elt shape edest 0 in
+-  make_arity rtype vtype, elt
+-
+-let conv_1 = conv (fun rtype vtype -> Arity1 (rtype, vtype 1))
+-let conv_2 = conv (fun rtype vtype -> Arity2 (rtype, vtype 1, vtype 2))
+-
+-(* Operation has an unsigned result even if operands are signed.  *)
+-
+-let dst_unsign make_arity shape elt =
+-  let vtype = type_for_elt shape elt
+-  and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in
+-  make_arity rtype vtype, elt
+-
+-let dst_unsign_1 = dst_unsign (fun rtype vtype -> Arity1 (rtype, vtype 1))
+-
+-let make_bits_only func shape elt =
+-  let arity, elt' = func shape elt in
+-  arity, bits_of_elt elt'
+-
+-(* Extend operation.  *)
+-
+-let extend shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt
+-
+-(* Table look-up operations. Operand 2 is signed/unsigned for signed/unsigned
+-   integer ops respectively, or unsigned for polynomial ops.  *)
+-
+-let table mkarity shape elt =
+-  let vtype = type_for_elt shape elt in
+-  let op2 = type_for_elt shape (poly_unsigned_variant elt) 2 in
+-  mkarity vtype op2, bits_of_elt elt
+-
+-let table_2 = table (fun vtype op2 -> Arity2 (vtype 0, vtype 1, op2))
+-let table_io = table (fun vtype op2 -> Arity3 (vtype 0, vtype 0, vtype 1, op2))
+-
+-(* Operations where only bits matter.  *)
+-
+-let bits_1 = make_bits_only elts_same_1
+-let bits_2 = make_bits_only elts_same_2
+-let bits_3 = make_bits_only elts_same_3
+-
+-(* Store insns.  *)
+-let store_1 shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity2 (T_void, vtype 0, vtype 1), bits_of_elt elt
+-
+-let store_3 shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (T_void, vtype 0, vtype 1, vtype 2), bits_of_elt elt
+-
+-let make_notype func shape elt =
+-  let arity, _ = func shape elt in
+-  arity, NoElts
+-
+-let notype_1 = make_notype elts_same_1
+-let notype_2 = make_notype elts_same_2
+-let notype_3 = make_notype elts_same_3
+-
+-(* Bit-select operations (first operand is unsigned int).  *)
+-
+-let bit_select shape elt =
+-  let vtype = type_for_elt shape elt
+-  and itype = type_for_elt shape (unsigned_of_elt elt) in
+-  Arity3 (vtype 0, itype 1, vtype 2, vtype 3), NoElts
+-
+-(* Common lists of supported element types.  *)
+-
+-let s_8_32 = [S8; S16; S32]
+-let u_8_32 = [U8; U16; U32]
+-let su_8_32 = [S8; S16; S32; U8; U16; U32]
+-let su_8_64 = S64 :: U64 :: su_8_32
+-let su_16_64 = [S16; S32; S64; U16; U32; U64]
+-let pf_su_8_16 = [P8; P16; S8; S16; U8; U16]
+-let pf_su_8_32 = P8 :: P16 :: F32 :: su_8_32
+-let pf_su_8_64 = P8 :: P16 :: F32 :: su_8_64
+-let suf_32 = [S32; U32; F32]
+-
+-let ops =
+-  [
+-    (* Addition.  *)
+-    Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32;
+-    Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64];
+-    Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64;
+-    Vadd, [], Long, "vaddl", elts_same_2, su_8_32;
+-    Vadd, [], Wide, "vaddw", elts_same_2, su_8_32;
+-    Vadd, [Halving], All (3, Dreg), "vhadd", elts_same_2, su_8_32;
+-    Vadd, [Halving], All (3, Qreg), "vhaddQ", elts_same_2, su_8_32;
+-    Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving],
+-      All (3, Dreg), "vRhadd", elts_same_2, su_8_32;
+-    Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving],
+-      All (3, Qreg), "vRhaddQ", elts_same_2, su_8_32;
+-    Vadd, [Saturating], All (3, Dreg), "vqadd", elts_same_2, su_8_64;
+-    Vadd, [Saturating], All (3, Qreg), "vqaddQ", elts_same_2, su_8_64;
+-    Vadd, [High_half], Narrow, "vaddhn", sign_invar_2, su_16_64;
+-    Vadd, [Instruction_name ["vraddhn"]; Rounding; High_half],
+-      Narrow, "vRaddhn", sign_invar_2, su_16_64;
+-
+-    (* Multiplication.  *)
+-    Vmul, [], All (3, Dreg), "vmul", sign_invar_2, P8 :: F32 :: su_8_32;
+-    Vmul, [], All (3, Qreg), "vmulQ", sign_invar_2, P8 :: F32 :: su_8_32;
+-    Vmul, [Saturating; Doubling; High_half], All (3, Dreg), "vqdmulh",
+-      elts_same_2, [S16; S32];
+-    Vmul, [Saturating; Doubling; High_half], All (3, Qreg), "vqdmulhQ",
+-      elts_same_2, [S16; S32];
+-    Vmul,
+-      [Saturating; Rounding; Doubling; High_half;
+-       Instruction_name ["vqrdmulh"]],
+-      All (3, Dreg), "vqRdmulh",
+-      elts_same_2, [S16; S32];
+-    Vmul,
+-      [Saturating; Rounding; Doubling; High_half;
+-       Instruction_name ["vqrdmulh"]],
+-      All (3, Qreg), "vqRdmulhQ",
+-      elts_same_2, [S16; S32];
+-    Vmul, [], Long, "vmull", elts_same_2, P8 :: su_8_32;
+-    Vmul, [Saturating; Doubling], Long, "vqdmull", elts_same_2, [S16; S32];
+-
+-    (* Multiply-accumulate. *)
+-    Vmla, [], All (3, Dreg), "vmla", sign_invar_io, F32 :: su_8_32;
+-    Vmla, [], All (3, Qreg), "vmlaQ", sign_invar_io, F32 :: su_8_32;
+-    Vmla, [], Long, "vmlal", elts_same_io, su_8_32;
+-    Vmla, [Saturating; Doubling], Long, "vqdmlal", elts_same_io, [S16; S32];
+-
+-    (* Multiply-subtract.  *)
+-    Vmls, [], All (3, Dreg), "vmls", sign_invar_io, F32 :: su_8_32;
+-    Vmls, [], All (3, Qreg), "vmlsQ", sign_invar_io, F32 :: su_8_32;
+-    Vmls, [], Long, "vmlsl", elts_same_io, su_8_32;
+-    Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32];
+-
+-    (* Fused-multiply-accumulate. *)
+-    Vfma, [Requires_feature "FMA"], All (3, Dreg), "vfma", elts_same_io, [F32];
+-    Vfma, [Requires_feature "FMA"], All (3, Qreg), "vfmaQ", elts_same_io, [F32];
+-    Vfms, [Requires_feature "FMA"], All (3, Dreg), "vfms", elts_same_io, [F32];
+-    Vfms, [Requires_feature "FMA"], All (3, Qreg), "vfmsQ", elts_same_io, [F32];
+-
+-    (* Round to integral. *)
+-    Vrintn, [Builtin_name "vrintn"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrndn", elts_same_1, [F32];
+-    Vrintn, [Builtin_name "vrintn"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqn", elts_same_1, [F32];
+-    Vrinta, [Builtin_name "vrinta"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrnda", elts_same_1, [F32];
+-    Vrinta, [Builtin_name "vrinta"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqa", elts_same_1, [F32];
+-    Vrintp, [Builtin_name "vrintp"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrndp", elts_same_1, [F32];
+-    Vrintp, [Builtin_name "vrintp"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqp", elts_same_1, [F32];
+-    Vrintm, [Builtin_name "vrintm"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrndm", elts_same_1, [F32];
+-    Vrintm, [Builtin_name "vrintm"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqm", elts_same_1, [F32];
+-    Vrintz, [Builtin_name "vrintz"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrnd", elts_same_1, [F32];
+-    Vrintz, [Builtin_name "vrintz"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndq", elts_same_1, [F32];
+-    (* Subtraction.  *)
+-    Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32;
+-    Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2,  [S64; U64];
+-    Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64;
+-    Vsub, [], Long, "vsubl", elts_same_2, su_8_32;
+-    Vsub, [], Wide, "vsubw", elts_same_2, su_8_32;
+-    Vsub, [Halving], All (3, Dreg), "vhsub", elts_same_2, su_8_32;
+-    Vsub, [Halving], All (3, Qreg), "vhsubQ", elts_same_2, su_8_32;
+-    Vsub, [Saturating], All (3, Dreg), "vqsub", elts_same_2, su_8_64;
+-    Vsub, [Saturating], All (3, Qreg), "vqsubQ", elts_same_2, su_8_64;
+-    Vsub, [High_half], Narrow, "vsubhn", sign_invar_2, su_16_64;
+-    Vsub, [Instruction_name ["vrsubhn"]; Rounding; High_half],
+-      Narrow, "vRsubhn", sign_invar_2, su_16_64;
+-
+-    (* Comparison, equal.  *)
+-    Vceq, [], All (3, Dreg), "vceq", cmp_sign_invar, P8 :: F32 :: su_8_32;
+-    Vceq, [], All (3, Qreg), "vceqQ", cmp_sign_invar, P8 :: F32 :: su_8_32;
+-
+-    (* Comparison, greater-than or equal.  *)
+-    Vcge, [], All (3, Dreg), "vcge", cmp_sign_matters, F32 :: s_8_32;
+-    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
+-      All (3, Dreg), "vcge", cmp_sign_matters,
+-      u_8_32;
+-    Vcge, [], All (3, Qreg), "vcgeQ", cmp_sign_matters, F32 :: s_8_32;
+-    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
+-      All (3, Qreg), "vcgeQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Comparison, less-than or equal.  *)
+-    Vcle, [Flipped "vcge"], All (3, Dreg), "vcle", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeu"],
+-      All (3, Dreg), "vcle", cmp_sign_matters,
+-      u_8_32;
+-    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeQ"],
+-      All (3, Qreg), "vcleQ", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeuQ"],
+-      All (3, Qreg), "vcleQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Comparison, greater-than.  *)
+-    Vcgt, [], All (3, Dreg), "vcgt", cmp_sign_matters, F32 :: s_8_32;
+-    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
+-      All (3, Dreg), "vcgt", cmp_sign_matters,
+-      u_8_32;
+-    Vcgt, [], All (3, Qreg), "vcgtQ", cmp_sign_matters, F32 :: s_8_32;
+-    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
+-      All (3, Qreg), "vcgtQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Comparison, less-than.  *)
+-    Vclt, [Flipped "vcgt"], All (3, Dreg), "vclt", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtu"],
+-      All (3, Dreg), "vclt", cmp_sign_matters,
+-      u_8_32;
+-    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtQ"],
+-      All (3, Qreg), "vcltQ", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtuQ"],
+-      All (3, Qreg), "vcltQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Compare absolute greater-than or equal.  *)
+-    Vcage, [Instruction_name ["vacge"]],
+-      All (3, Dreg), "vcage", cmp_sign_matters, [F32];
+-    Vcage, [Instruction_name ["vacge"]],
+-      All (3, Qreg), "vcageQ", cmp_sign_matters, [F32];
+-
+-    (* Compare absolute less-than or equal.  *)
+-    Vcale, [Instruction_name ["vacge"]; Flipped "vcage"],
+-      All (3, Dreg), "vcale", cmp_sign_matters, [F32];
+-    Vcale, [Instruction_name ["vacge"]; Flipped "vcageQ"],
+-      All (3, Qreg), "vcaleQ", cmp_sign_matters, [F32];
+-
+-    (* Compare absolute greater-than or equal.  *)
+-    Vcagt, [Instruction_name ["vacgt"]],
+-      All (3, Dreg), "vcagt", cmp_sign_matters, [F32];
+-    Vcagt, [Instruction_name ["vacgt"]],
+-      All (3, Qreg), "vcagtQ", cmp_sign_matters, [F32];
+-
+-    (* Compare absolute less-than or equal.  *)
+-    Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagt"],
+-      All (3, Dreg), "vcalt", cmp_sign_matters, [F32];
+-    Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagtQ"],
+-      All (3, Qreg), "vcaltQ", cmp_sign_matters, [F32];
+-
+-    (* Test bits.  *)
+-    Vtst, [], All (3, Dreg), "vtst", cmp_bits, P8 :: su_8_32;
+-    Vtst, [], All (3, Qreg), "vtstQ", cmp_bits, P8 :: su_8_32;
+-
+-    (* Absolute difference.  *)
+-    Vabd, [], All (3, Dreg), "vabd", elts_same_2, F32 :: su_8_32;
+-    Vabd, [], All (3, Qreg), "vabdQ", elts_same_2, F32 :: su_8_32;
+-    Vabd, [], Long, "vabdl", elts_same_2, su_8_32;
+-
+-    (* Absolute difference and accumulate.  *)
+-    Vaba, [], All (3, Dreg), "vaba", elts_same_io, su_8_32;
+-    Vaba, [], All (3, Qreg), "vabaQ", elts_same_io, su_8_32;
+-    Vaba, [], Long, "vabal", elts_same_io, su_8_32;
+-
+-    (* Max.  *)
+-    Vmax, [], All (3, Dreg), "vmax", elts_same_2, F32 :: su_8_32;
+-    Vmax, [], All (3, Qreg), "vmaxQ", elts_same_2, F32 :: su_8_32;
+-
+-    (* Min.  *)
+-    Vmin, [], All (3, Dreg), "vmin", elts_same_2, F32 :: su_8_32;
+-    Vmin, [], All (3, Qreg), "vminQ", elts_same_2, F32 :: su_8_32;
+-
+-    (* Pairwise add.  *)
+-    Vpadd, [], All (3, Dreg), "vpadd", sign_invar_2, F32 :: su_8_32;
+-    Vpadd, [], Long_noreg Dreg, "vpaddl", elts_same_1, su_8_32;
+-    Vpadd, [], Long_noreg Qreg, "vpaddlQ", elts_same_1, su_8_32;
+-
+-    (* Pairwise add, widen and accumulate.  *)
+-    Vpada, [], Wide_noreg Dreg, "vpadal", elts_same_2, su_8_32;
+-    Vpada, [], Wide_noreg Qreg, "vpadalQ", elts_same_2, su_8_32;
+-
+-    (* Folding maximum, minimum.  *)
+-    Vpmax, [], All (3, Dreg), "vpmax", elts_same_2, F32 :: su_8_32;
+-    Vpmin, [], All (3, Dreg), "vpmin", elts_same_2, F32 :: su_8_32;
+-
+-    (* Reciprocal step.  *)
+-    Vrecps, [], All (3, Dreg), "vrecps", elts_same_2, [F32];
+-    Vrecps, [], All (3, Qreg), "vrecpsQ", elts_same_2, [F32];
+-    Vrsqrts, [], All (3, Dreg), "vrsqrts", elts_same_2, [F32];
+-    Vrsqrts, [], All (3, Qreg), "vrsqrtsQ", elts_same_2, [F32];
+-
+-    (* Vector shift left.  *)
+-    Vshl, [], All (3, Dreg), "vshl", reg_shift, su_8_64;
+-    Vshl, [], All (3, Qreg), "vshlQ", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vrshl"]; Rounding],
+-      All (3, Dreg), "vRshl", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vrshl"]; Rounding],
+-      All (3, Qreg), "vRshlQ", reg_shift, su_8_64;
+-    Vshl, [Saturating], All (3, Dreg), "vqshl", reg_shift, su_8_64;
+-    Vshl, [Saturating], All (3, Qreg), "vqshlQ", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding],
+-      All (3, Dreg), "vqRshl", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding],
+-      All (3, Qreg), "vqRshlQ", reg_shift, su_8_64;
+-
+-    (* Vector shift right by constant.  *)
+-    Vshr_n, [], Binary_imm Dreg, "vshr_n", shift_right, su_8_64;
+-    Vshr_n, [], Binary_imm Qreg, "vshrQ_n", shift_right, su_8_64;
+-    Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Dreg,
+-      "vRshr_n", shift_right, su_8_64;
+-    Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Qreg,
+-      "vRshrQ_n", shift_right, su_8_64;
+-    Vshr_n, [], Narrow_imm, "vshrn_n", shift_right_sign_invar, su_16_64;
+-    Vshr_n, [Instruction_name ["vrshrn"]; Rounding], Narrow_imm, "vRshrn_n",
+-      shift_right_sign_invar, su_16_64;
+-    Vshr_n, [Saturating], Narrow_imm, "vqshrn_n", shift_right, su_16_64;
+-    Vshr_n, [Instruction_name ["vqrshrn"]; Saturating; Rounding], Narrow_imm,
+-      "vqRshrn_n", shift_right, su_16_64;
+-    Vshr_n, [Saturating; Dst_unsign], Narrow_imm, "vqshrun_n",
+-      shift_right_to_uns, [S16; S32; S64];
+-    Vshr_n, [Instruction_name ["vqrshrun"]; Saturating; Dst_unsign; Rounding],
+-      Narrow_imm, "vqRshrun_n", shift_right_to_uns, [S16; S32; S64];
+-
+-    (* Vector shift left by constant.  *)
+-    Vshl_n, [], Binary_imm Dreg, "vshl_n", shift_left_sign_invar, su_8_64;
+-    Vshl_n, [], Binary_imm Qreg, "vshlQ_n", shift_left_sign_invar, su_8_64;
+-    Vshl_n, [Saturating], Binary_imm Dreg, "vqshl_n", shift_left, su_8_64;
+-    Vshl_n, [Saturating], Binary_imm Qreg, "vqshlQ_n", shift_left, su_8_64;
+-    Vshl_n, [Saturating; Dst_unsign], Binary_imm Dreg, "vqshlu_n",
+-      shift_left_to_uns, [S8; S16; S32; S64];
+-    Vshl_n, [Saturating; Dst_unsign], Binary_imm Qreg, "vqshluQ_n",
+-      shift_left_to_uns, [S8; S16; S32; S64];
+-    Vshl_n, [], Long_imm, "vshll_n", shift_left, su_8_32;
+-
+-    (* Vector shift right by constant and accumulate.  *)
+-    Vsra_n, [], Binary_imm Dreg, "vsra_n", shift_right_acc, su_8_64;
+-    Vsra_n, [], Binary_imm Qreg, "vsraQ_n", shift_right_acc, su_8_64;
+-    Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Dreg,
+-      "vRsra_n", shift_right_acc, su_8_64;
+-    Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Qreg,
+-      "vRsraQ_n", shift_right_acc, su_8_64;
+-
+-    (* Vector shift right and insert.  *)
+-    Vsri, [Requires_feature "CRYPTO"], Use_operands [| Dreg; Dreg; Immed |], "vsri_n", shift_insert,
+-      [P64];
+-    Vsri, [], Use_operands [| Dreg; Dreg; Immed |], "vsri_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-    Vsri, [Requires_feature "CRYPTO"], Use_operands [| Qreg; Qreg; Immed |], "vsriQ_n", shift_insert,
+-      [P64];
+-    Vsri, [], Use_operands [| Qreg; Qreg; Immed |], "vsriQ_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-
+-    (* Vector shift left and insert.  *)
+-    Vsli, [Requires_feature "CRYPTO"], Use_operands [| Dreg; Dreg; Immed |], "vsli_n", shift_insert,
+-      [P64];
+-    Vsli, [], Use_operands [| Dreg; Dreg; Immed |], "vsli_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-    Vsli, [Requires_feature "CRYPTO"], Use_operands [| Qreg; Qreg; Immed |], "vsliQ_n", shift_insert,
+-      [P64];
+-    Vsli, [], Use_operands [| Qreg; Qreg; Immed |], "vsliQ_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-
+-    (* Absolute value.  *)
+-    Vabs, [], All (2, Dreg), "vabs", elts_same_1, [S8; S16; S32; F32];
+-    Vabs, [], All (2, Qreg), "vabsQ", elts_same_1, [S8; S16; S32; F32];
+-    Vabs, [Saturating], All (2, Dreg), "vqabs", elts_same_1, [S8; S16; S32];
+-    Vabs, [Saturating], All (2, Qreg), "vqabsQ", elts_same_1, [S8; S16; S32];
+-
+-    (* Negate.  *)
+-    Vneg, [], All (2, Dreg), "vneg", elts_same_1, [S8; S16; S32; F32];
+-    Vneg, [], All (2, Qreg), "vnegQ", elts_same_1, [S8; S16; S32; F32];
+-    Vneg, [Saturating], All (2, Dreg), "vqneg", elts_same_1, [S8; S16; S32];
+-    Vneg, [Saturating], All (2, Qreg), "vqnegQ", elts_same_1, [S8; S16; S32];
+-
+-    (* Bitwise not.  *)
+-    Vmvn, [], All (2, Dreg), "vmvn", notype_1, P8 :: su_8_32;
+-    Vmvn, [], All (2, Qreg), "vmvnQ", notype_1, P8 :: su_8_32;
+-
+-    (* Count leading sign bits.  *)
+-    Vcls, [], All (2, Dreg), "vcls", elts_same_1, [S8; S16; S32];
+-    Vcls, [], All (2, Qreg), "vclsQ", elts_same_1, [S8; S16; S32];
+-
+-    (* Count leading zeros.  *)
+-    Vclz, [], All (2, Dreg), "vclz", sign_invar_1, su_8_32;
+-    Vclz, [], All (2, Qreg), "vclzQ", sign_invar_1, su_8_32;
+-
+-    (* Count number of set bits.  *)
+-    Vcnt, [], All (2, Dreg), "vcnt", bits_1, [P8; S8; U8];
+-    Vcnt, [], All (2, Qreg), "vcntQ", bits_1, [P8; S8; U8];
+-
+-    (* Reciprocal estimate.  *)
+-    Vrecpe, [], All (2, Dreg), "vrecpe", elts_same_1, [U32; F32];
+-    Vrecpe, [], All (2, Qreg), "vrecpeQ", elts_same_1, [U32; F32];
+-
+-    (* Reciprocal square-root estimate.  *)
+-    Vrsqrte, [], All (2, Dreg), "vrsqrte", elts_same_1, [U32; F32];
+-    Vrsqrte, [], All (2, Qreg), "vrsqrteQ", elts_same_1, [U32; F32];
+-
+-    (* Get lanes from a vector.  *)
+-    Vget_lane,
+-      [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]];
+-       Instruction_name ["vmov"]],
+-      Use_operands [| Corereg; Dreg; Immed |],
+-      "vget_lane", get_lane, pf_su_8_32;
+-    Vget_lane,
+-      [No_op;
+-       InfoWord;
+-       Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
+-       Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Corereg; Dreg; Immed |],
+-      "vget_lane", notype_2, [S64; U64];
+-    Vget_lane,
+-      [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]];
+-       Instruction_name ["vmov"]],
+-      Use_operands [| Corereg; Qreg; Immed |],
+-      "vgetQ_lane", get_lane, pf_su_8_32;
+-    Vget_lane,
+-      [InfoWord;
+-       Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
+-       Instruction_name ["vmov"; "fmrrd"]; Const_valuator (fun _ -> 0);
+-       Fixed_core_reg],
+-      Use_operands [| Corereg; Qreg; Immed |],
+-      "vgetQ_lane", notype_2, [S64; U64];
+-
+-    (* Set lanes in a vector.  *)
+-    Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]];
+-                Instruction_name ["vmov"]],
+-      Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
+-      set_lane, pf_su_8_32;
+-    Vset_lane, [No_op;
+-                Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
+-                Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
+-      set_lane_notype, [S64; U64];
+-    Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]];
+-                Instruction_name ["vmov"]],
+-      Use_operands [| Qreg; Corereg; Qreg; Immed |], "vsetQ_lane",
+-      set_lane, pf_su_8_32;
+-    Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
+-                Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Qreg; Corereg; Qreg; Immed |], "vsetQ_lane",
+-      set_lane_notype, [S64; U64];
+-
+-    (* Create vector from literal bit pattern.  *)
+-    Vcreate,
+-      [Requires_feature "CRYPTO"; No_op], (* Not really, but it can yield various things that are too
+-                                   hard for the test generator at this time.  *)
+-      Use_operands [| Dreg; Corereg |], "vcreate", create_vector,
+-      [P64];
+-    Vcreate,
+-      [No_op], (* Not really, but it can yield various things that are too
+-                  hard for the test generator at this time.  *)
+-      Use_operands [| Dreg; Corereg |], "vcreate", create_vector,
+-      pf_su_8_64;
+-
+-    (* Set all lanes to the same value.  *)
+-    Vdup_n,
+-      [Disassembles_as [Use_operands [| Dreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
+-      pf_su_8_32;
+-    Vdup_n,
+-      [No_op; Requires_feature "CRYPTO";
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
+-      [P64];
+-    Vdup_n,
+-      [No_op;
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
+-      [S64; U64];
+-    Vdup_n,
+-      [No_op; Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| Qreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
+-      [P64];
+-    Vdup_n,
+-      [Disassembles_as [Use_operands [| Qreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
+-      pf_su_8_32;
+-    Vdup_n,
+-      [No_op;
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
+-                        Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1,
+-      [S64; U64];
+-
+-    (* These are just aliases for the above.  *)
+-    Vmov_n,
+-      [Builtin_name "vdup_n";
+-       Disassembles_as [Use_operands [| Dreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Dreg; Corereg |],
+-      "vmov_n", bits_1, pf_su_8_32;
+-    Vmov_n,
+-      [No_op;
+-       Builtin_name "vdup_n";
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Dreg; Corereg |],
+-      "vmov_n", notype_1, [S64; U64];
+-    Vmov_n,
+-      [Builtin_name "vdupQ_n";
+-       Disassembles_as [Use_operands [| Qreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Qreg; Corereg |],
+-      "vmovQ_n", bits_1, pf_su_8_32;
+-    Vmov_n,
+-      [No_op;
+-       Builtin_name "vdupQ_n";
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
+-                        Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Qreg; Corereg |],
+-      "vmovQ_n", notype_1, [S64; U64];
+-
+-    (* Duplicate, lane version.  We can't use Use_operands here because the
+-       rightmost register (always Dreg) would be picked up by find_key_operand,
+-       when we want the leftmost register to be used in this case (otherwise
+-       the modes are indistinguishable in neon.md, etc.  *)
+-    Vdup_lane,
+-      [Disassembles_as [Use_operands [| Dreg; Element_of_dreg |]]],
+-      Unary_scalar Dreg, "vdup_lane", bits_2, pf_su_8_32;
+-    Vdup_lane,
+-      [No_op; Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Dreg, "vdup_lane", bits_2, [P64];
+-    Vdup_lane,
+-      [No_op; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Dreg, "vdup_lane", bits_2, [S64; U64];
+-    Vdup_lane,
+-      [Disassembles_as [Use_operands [| Qreg; Element_of_dreg |]]],
+-      Unary_scalar Qreg, "vdupQ_lane", bits_2, pf_su_8_32;
+-    Vdup_lane,
+-      [No_op; Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Qreg, "vdupQ_lane", bits_2, [P64];
+-    Vdup_lane,
+-      [No_op; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Qreg, "vdupQ_lane", bits_2, [S64; U64];
+-
+-    (* Combining vectors.  *)
+-    Vcombine, [Requires_feature "CRYPTO"; No_op],
+-      Use_operands [| Qreg; Dreg; Dreg |], "vcombine", notype_2,
+-      [P64];
+-    Vcombine, [No_op],
+-      Use_operands [| Qreg; Dreg; Dreg |], "vcombine", notype_2,
+-      pf_su_8_64;
+-
+-    (* Splitting vectors.  *)
+-    Vget_high, [Requires_feature "CRYPTO"; No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_high",
+-      notype_1, [P64];
+-    Vget_high, [No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_high",
+-      notype_1, pf_su_8_64;
+-    Vget_low, [Instruction_name ["vmov"];
+-               Disassembles_as [Use_operands [| Dreg; Dreg |]];
+-	       Fixed_vector_reg],
+-      Use_operands [| Dreg; Qreg |], "vget_low",
+-      notype_1, pf_su_8_32;
+-    Vget_low, [Requires_feature "CRYPTO"; No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_low",
+-      notype_1, [P64];
+-    Vget_low, [No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_low",
+-      notype_1, [S64; U64];
+-
+-    (* Conversions.  *)
+-    Vcvt, [InfoWord], All (2, Dreg), "vcvt", conv_1,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-    Vcvt, [InfoWord], All (2, Qreg), "vcvtQ", conv_1,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-    Vcvt, [Builtin_name "vcvt" ; Requires_FP_bit 1],
+-          Use_operands [| Dreg; Qreg; |], "vcvt", conv_1, [Conv (F16, F32)];
+-    Vcvt, [Builtin_name "vcvt" ; Requires_FP_bit 1],
+-          Use_operands [| Qreg; Dreg; |], "vcvt", conv_1, [Conv (F32, F16)];
+-    Vcvt_n, [InfoWord], Use_operands [| Dreg; Dreg; Immed |], "vcvt_n", conv_2,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-    Vcvt_n, [InfoWord], Use_operands [| Qreg; Qreg; Immed |], "vcvtQ_n", conv_2,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-
+-    (* Move, narrowing.  *)
+-    Vmovn, [Disassembles_as [Use_operands [| Dreg; Qreg |]]],
+-      Narrow, "vmovn", sign_invar_1, su_16_64;
+-    Vmovn, [Disassembles_as [Use_operands [| Dreg; Qreg |]]; Saturating],
+-      Narrow, "vqmovn", elts_same_1, su_16_64;
+-    Vmovn,
+-      [Disassembles_as [Use_operands [| Dreg; Qreg |]]; Saturating; Dst_unsign],
+-      Narrow, "vqmovun", dst_unsign_1,
+-      [S16; S32; S64];
+-
+-    (* Move, long.  *)
+-    Vmovl, [Disassembles_as [Use_operands [| Qreg; Dreg |]]],
+-      Long, "vmovl", elts_same_1, su_8_32;
+-
+-    (* Table lookup.  *)
+-    Vtbl 1,
+-      [Instruction_name ["vtbl"];
+-       Disassembles_as [Use_operands [| Dreg; VecArray (1, Dreg); Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg |], "vtbl1", table_2, [U8; S8; P8];
+-    Vtbl 2, [Instruction_name ["vtbl"]],
+-      Use_operands [| Dreg; VecArray (2, Dreg); Dreg |], "vtbl2", table_2,
+-      [U8; S8; P8];
+-    Vtbl 3, [Instruction_name ["vtbl"]],
+-      Use_operands [| Dreg; VecArray (3, Dreg); Dreg |], "vtbl3", table_2,
+-      [U8; S8; P8];
+-    Vtbl 4, [Instruction_name ["vtbl"]],
+-      Use_operands [| Dreg; VecArray (4, Dreg); Dreg |], "vtbl4", table_2,
+-      [U8; S8; P8];
+-
+-    (* Extended table lookup.  *)
+-    Vtbx 1,
+-      [Instruction_name ["vtbx"];
+-       Disassembles_as [Use_operands [| Dreg; VecArray (1, Dreg); Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg |], "vtbx1", table_io, [U8; S8; P8];
+-    Vtbx 2, [Instruction_name ["vtbx"]],
+-      Use_operands [| Dreg; VecArray (2, Dreg); Dreg |], "vtbx2", table_io,
+-      [U8; S8; P8];
+-    Vtbx 3, [Instruction_name ["vtbx"]],
+-      Use_operands [| Dreg; VecArray (3, Dreg); Dreg |], "vtbx3", table_io,
+-      [U8; S8; P8];
+-    Vtbx 4, [Instruction_name ["vtbx"]],
+-      Use_operands [| Dreg; VecArray (4, Dreg); Dreg |], "vtbx4", table_io,
+-      [U8; S8; P8];
+-
+-    (* Multiply, lane.  (note: these were undocumented at the time of
+-       writing).  *)
+-    Vmul_lane, [], By_scalar Dreg, "vmul_lane", sign_invar_2_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmul_lane, [], By_scalar Qreg, "vmulQ_lane", sign_invar_2_lane,
+-      [S16; S32; U16; U32; F32];
+-
+-    (* Multiply-accumulate, lane.  *)
+-    Vmla_lane, [], By_scalar Dreg, "vmla_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmla_lane, [], By_scalar Qreg, "vmlaQ_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmla_lane, [], Wide_lane, "vmlal_lane", elts_same_io_lane,
+-      [S16; S32; U16; U32];
+-    Vmla_lane, [Saturating; Doubling], Wide_lane, "vqdmlal_lane",
+-      elts_same_io_lane, [S16; S32];
+-
+-    (* Multiply-subtract, lane.  *)
+-    Vmls_lane, [], By_scalar Dreg, "vmls_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmls_lane, [], By_scalar Qreg, "vmlsQ_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmls_lane, [], Wide_lane, "vmlsl_lane", elts_same_io_lane,
+-      [S16; S32; U16; U32];
+-    Vmls_lane, [Saturating; Doubling], Wide_lane, "vqdmlsl_lane",
+-      elts_same_io_lane, [S16; S32];
+-
+-    (* Long multiply, lane.  *)
+-    Vmull_lane, [],
+-      Wide_lane, "vmull_lane", elts_same_2_lane, [S16; S32; U16; U32];
+-
+-    (* Saturating doubling long multiply, lane.  *)
+-    Vqdmull_lane, [Saturating; Doubling],
+-      Wide_lane, "vqdmull_lane", elts_same_2_lane, [S16; S32];
+-
+-    (* Saturating doubling long multiply high, lane.  *)
+-    Vqdmulh_lane, [Saturating; Halving],
+-      By_scalar Qreg, "vqdmulhQ_lane", elts_same_2_lane, [S16; S32];
+-    Vqdmulh_lane, [Saturating; Halving],
+-      By_scalar Dreg, "vqdmulh_lane", elts_same_2_lane, [S16; S32];
+-    Vqdmulh_lane, [Saturating; Halving; Rounding;
+-		   Instruction_name ["vqrdmulh"]],
+-      By_scalar Qreg, "vqRdmulhQ_lane", elts_same_2_lane, [S16; S32];
+-    Vqdmulh_lane, [Saturating; Halving; Rounding;
+-		   Instruction_name ["vqrdmulh"]],
+-      By_scalar Dreg, "vqRdmulh_lane", elts_same_2_lane, [S16; S32];
+-
+-    (* Vector multiply by scalar.  *)
+-    Vmul_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-             Use_operands [| Dreg; Dreg; Corereg |], "vmul_n",
+-      sign_invar_2, [S16; S32; U16; U32; F32];
+-    Vmul_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-             Use_operands [| Qreg; Qreg; Corereg |], "vmulQ_n",
+-      sign_invar_2, [S16; S32; U16; U32; F32];
+-
+-    (* Vector long multiply by scalar.  *)
+-    Vmull_n, [Instruction_name ["vmull"];
+-              Disassembles_as [Use_operands [| Qreg; Dreg; Element_of_dreg |]]],
+-              Wide_scalar, "vmull_n",
+-      elts_same_2, [S16; S32; U16; U32];
+-
+-    (* Vector saturating doubling long multiply by scalar.  *)
+-    Vqdmull_n, [Saturating; Doubling;
+-	        Disassembles_as [Use_operands [| Qreg; Dreg;
+-						 Element_of_dreg |]]],
+-                Wide_scalar, "vqdmull_n",
+-      elts_same_2, [S16; S32];
+-
+-    (* Vector saturating doubling long multiply high by scalar.  *)
+-    Vqdmulh_n,
+-      [Saturating; Halving; InfoWord;
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |],
+-      "vqdmulhQ_n", elts_same_2, [S16; S32];
+-    Vqdmulh_n,
+-      [Saturating; Halving; InfoWord;
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |],
+-      "vqdmulh_n", elts_same_2, [S16; S32];
+-    Vqdmulh_n,
+-      [Saturating; Halving; Rounding; InfoWord;
+-       Instruction_name ["vqrdmulh"];
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |],
+-      "vqRdmulhQ_n", elts_same_2, [S16; S32];
+-    Vqdmulh_n,
+-      [Saturating; Halving; Rounding; InfoWord;
+-       Instruction_name ["vqrdmulh"];
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |],
+-      "vqRdmulh_n", elts_same_2, [S16; S32];
+-
+-    (* Vector multiply-accumulate by scalar.  *)
+-    Vmla_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |], "vmla_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmla_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |], "vmlaQ_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmla_n, [], Wide_scalar, "vmlal_n", elts_same_io, [S16; S32; U16; U32];
+-    Vmla_n, [Saturating; Doubling], Wide_scalar, "vqdmlal_n", elts_same_io,
+-      [S16; S32];
+-
+-    (* Vector multiply subtract by scalar.  *)
+-    Vmls_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |], "vmls_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmls_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |], "vmlsQ_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmls_n, [], Wide_scalar, "vmlsl_n", elts_same_io, [S16; S32; U16; U32];
+-    Vmls_n, [Saturating; Doubling], Wide_scalar, "vqdmlsl_n", elts_same_io,
+-      [S16; S32];
+-
+-    (* Vector extract.  *)
+-    Vext, [Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; Dreg; Dreg; Immed |], "vext", extend,
+-      [P64];
+-    Vext, [Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; Dreg; Dreg; Immed |], "vext", extend,
+-      pf_su_8_64;
+-    Vext, [Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Qreg; Qreg; Qreg; Immed |], "vextQ", extend,
+-      [P64];
+-    Vext, [Const_valuator (fun _ -> 0)],
+-      Use_operands [| Qreg; Qreg; Qreg; Immed |], "vextQ", extend,
+-      pf_su_8_64;
+-
+-    (* Reverse elements.  *)
+-    Vrev64, [Use_shuffle (rev_elems 64)], All (2, Dreg), "vrev64", bits_1,
+-      P8 :: P16 :: F32 :: su_8_32;
+-    Vrev64, [Use_shuffle (rev_elems 64)], All (2, Qreg), "vrev64Q", bits_1,
+-      P8 :: P16 :: F32 :: su_8_32;
+-    Vrev32, [Use_shuffle (rev_elems 32)], All (2, Dreg), "vrev32", bits_1,
+-      [P8; P16; S8; U8; S16; U16];
+-    Vrev32, [Use_shuffle (rev_elems 32)], All (2, Qreg), "vrev32Q", bits_1,
+-      [P8; P16; S8; U8; S16; U16];
+-    Vrev16, [Use_shuffle (rev_elems 16)], All (2, Dreg), "vrev16", bits_1,
+-      [P8; S8; U8];
+-    Vrev16, [Use_shuffle (rev_elems 16)], All (2, Qreg), "vrev16Q", bits_1,
+-      [P8; S8; U8];
+-
+-    (* Bit selection.  *)
+-    Vbsl,
+-      [Requires_feature "CRYPTO"; Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg; Dreg |], "vbsl", bit_select,
+-      [P64];
+-    Vbsl,
+-      [Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg; Dreg |], "vbsl", bit_select,
+-      pf_su_8_64;
+-    Vbsl,
+-      [Requires_feature "CRYPTO"; Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Qreg |]]],
+-      Use_operands [| Qreg; Qreg; Qreg; Qreg |], "vbslQ", bit_select,
+-      [P64];
+-    Vbsl,
+-      [Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Qreg |]]],
+-      Use_operands [| Qreg; Qreg; Qreg; Qreg |], "vbslQ", bit_select,
+-      pf_su_8_64;
+-
+-    Vtrn, [Use_shuffle trn_elems], Pair_result Dreg, "vtrn", bits_2, pf_su_8_16;
+-    Vtrn, [Use_shuffle trn_elems; Instruction_name ["vuzp"]], Pair_result Dreg, "vtrn", bits_2, suf_32;
+-    Vtrn, [Use_shuffle trn_elems], Pair_result Qreg, "vtrnQ", bits_2, pf_su_8_32;
+-    (* Zip elements.  *)
+-    Vzip, [Use_shuffle zip_elems], Pair_result Dreg, "vzip", bits_2, pf_su_8_16;
+-    Vzip, [Use_shuffle zip_elems; Instruction_name ["vuzp"]], Pair_result Dreg, "vzip", bits_2, suf_32;
+-    Vzip, [Use_shuffle zip_elems], Pair_result Qreg, "vzipQ", bits_2, pf_su_8_32; 
+-
+-    (* Unzip elements.  *)
+-    Vuzp, [Use_shuffle uzip_elems], Pair_result Dreg, "vuzp", bits_2,
+-      pf_su_8_32;
+-    Vuzp, [Use_shuffle uzip_elems], Pair_result Qreg, "vuzpQ", bits_2,
+-      pf_su_8_32;
+-
+-    (* Element/structure loads.  VLD1 variants.  *)
+-    Vldx 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1", bits_1,
+-      [P64];
+-    Vldx 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1", bits_1,
+-      pf_su_8_64;
+-    Vldx 1, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q", bits_1,
+-      [P64];
+-    Vldx 1, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q", bits_1,
+-      pf_su_8_64;
+-
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |],
+-      "vld1_lane", bits_3, pf_su_8_32;
+-    Vldx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |],
+-      "vld1_lane", bits_3, [P64];
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |],
+-      "vld1_lane", bits_3, [S64; U64];
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |],
+-      "vld1Q_lane", bits_3, pf_su_8_32;
+-    Vldx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |],
+-      "vld1Q_lane", bits_3, [P64];
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |],
+-      "vld1Q_lane", bits_3, [S64; U64];
+-
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, All_elements_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup",
+-      bits_1, pf_su_8_32;
+-    Vldx_dup 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup",
+-      bits_1, [P64];
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup",
+-      bits_1, [S64; U64];
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (2, All_elements_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup",
+-      bits_1, pf_su_8_32;
+-    (* Treated identically to vld1_dup above as we now
+-       do a single load followed by a duplicate.  *)
+-    Vldx_dup 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup",
+-      bits_1, [P64];
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup",
+-      bits_1, [S64; U64];
+-
+-    (* VST1 variants.  *)
+-    Vstx 1, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Dreg |], "vst1",
+-      store_1, [P64];
+-    Vstx 1, [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Dreg |], "vst1",
+-      store_1, pf_su_8_64;
+-    Vstx 1, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg |], "vst1Q",
+-      store_1, [P64];
+-    Vstx 1, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg |], "vst1Q",
+-      store_1, pf_su_8_64;
+-
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Dreg; Immed |],
+-      "vst1_lane", store_3, pf_su_8_32;
+-    Vstx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| PtrTo Corereg; Dreg; Immed |],
+-      "vst1_lane", store_3, [P64];
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| PtrTo Corereg; Dreg; Immed |],
+-      "vst1_lane", store_3, [U64; S64];
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg; Immed |],
+-      "vst1Q_lane", store_3, pf_su_8_32;
+-    Vstx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg; Immed |],
+-      "vst1Q_lane", store_3, [P64];
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg; Immed |],
+-      "vst1Q_lane", store_3, [U64; S64];
+-
+-    (* VLD2 variants.  *)
+-    Vldx 2, [], Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2", bits_1, pf_su_8_32;
+-    Vldx 2, [Requires_feature "CRYPTO"; Instruction_name ["vld1"]],
+-       Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2", bits_1, [P64];
+-    Vldx 2, [Instruction_name ["vld1"]],
+-       Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2", bits_1, [S64; U64];
+-    Vldx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              CstPtrTo Corereg |];
+-                              Use_operands [| VecArray (2, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Qreg); CstPtrTo Corereg |],
+-      "vld2Q", bits_1, pf_su_8_32;
+-
+-    Vldx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg;
+-                      VecArray (2, Dreg); Immed |],
+-      "vld2_lane", bits_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vldx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Qreg); CstPtrTo Corereg;
+- 	              VecArray (2, Qreg); Immed |],
+-      "vld2Q_lane", bits_3, [P16; F32; U16; U32; S16; S32];
+-
+-    Vldx_dup 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, All_elements_of_dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2_dup", bits_1, pf_su_8_32;
+-    Vldx_dup 2,
+-      [Requires_feature "CRYPTO";
+-       Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (2, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2_dup", bits_1, [P64];
+-    Vldx_dup 2,
+-      [Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (2, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2_dup", bits_1, [S64; U64];
+-
+-    (* VST2 variants.  *)
+-    Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2",
+-      store_1, pf_su_8_32;
+-    Vstx 2, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2",
+-      store_1, [P64];
+-    Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2",
+-      store_1, [S64; U64];
+-    Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      PtrTo Corereg |];
+-                              Use_operands [| VecArray (2, Dreg);
+-				              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Qreg) |], "vst2Q",
+-      store_1, pf_su_8_32;
+-
+-    Vstx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg); Immed |], "vst2_lane",
+-      store_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vstx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Qreg); Immed |], "vst2Q_lane",
+-      store_3, [P16; F32; U16; U32; S16; S32];
+-
+-    (* VLD3 variants.  *)
+-    Vldx 3, [], Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3", bits_1, pf_su_8_32;
+-    Vldx 3, [Requires_feature "CRYPTO"; Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3", bits_1, [P64];
+-    Vldx 3, [Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3", bits_1, [S64; U64];
+-    Vldx 3, [Disassembles_as [Use_operands [| VecArray (3, Dreg);
+-					      CstPtrTo Corereg |];
+-                              Use_operands [| VecArray (3, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Qreg); CstPtrTo Corereg |],
+-      "vld3Q", bits_1, P8 :: P16 :: F32 :: su_8_32;
+-
+-    Vldx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg;
+-                                     VecArray (3, Dreg); Immed |],
+-      "vld3_lane", bits_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vldx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Qreg); CstPtrTo Corereg;
+-				     VecArray (3, Qreg); Immed |],
+-      "vld3Q_lane", bits_3, [P16; F32; U16; U32; S16; S32];
+-
+-    Vldx_dup 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, All_elements_of_dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3_dup", bits_1, pf_su_8_32;
+-    Vldx_dup 3,
+-      [Requires_feature "CRYPTO";
+-       Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (3, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3_dup", bits_1, [P64];
+-    Vldx_dup 3,
+-      [Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (3, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3_dup", bits_1, [S64; U64];
+-
+-    (* VST3 variants.  *)
+-    Vstx 3, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3",
+-      store_1, pf_su_8_32;
+-    Vstx 3, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3",
+-      store_1, [P64];
+-    Vstx 3, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3",
+-      store_1, [S64; U64];
+-    Vstx 3, [Disassembles_as [Use_operands [| VecArray (3, Dreg);
+-					      PtrTo Corereg |];
+-                              Use_operands [| VecArray (3, Dreg);
+-					      PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Qreg) |], "vst3Q",
+-      store_1, pf_su_8_32;
+-
+-    Vstx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg); Immed |], "vst3_lane",
+-      store_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vstx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Qreg); Immed |], "vst3Q_lane",
+-      store_3, [P16; F32; U16; U32; S16; S32];
+-
+-    (* VLD4/VST4 variants.  *)
+-    Vldx 4, [], Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4", bits_1, pf_su_8_32;
+-    Vldx 4, [Requires_feature "CRYPTO"; Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4", bits_1, [P64];
+-    Vldx 4, [Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4", bits_1, [S64; U64];
+-    Vldx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-					      CstPtrTo Corereg |];
+-                              Use_operands [| VecArray (4, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Qreg); CstPtrTo Corereg |],
+-      "vld4Q", bits_1, P8 :: P16 :: F32 :: su_8_32;
+-
+-    Vldx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg;
+-                                     VecArray (4, Dreg); Immed |],
+-      "vld4_lane", bits_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vldx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Qreg); CstPtrTo Corereg;
+-   	              VecArray (4, Qreg); Immed |],
+-      "vld4Q_lane", bits_3, [P16; F32; U16; U32; S16; S32];
+-
+-    Vldx_dup 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, All_elements_of_dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4_dup", bits_1, pf_su_8_32;
+-    Vldx_dup 4,
+-      [Requires_feature "CRYPTO";
+-       Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (4, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4_dup", bits_1, [P64];
+-    Vldx_dup 4,
+-      [Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (4, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4_dup", bits_1, [S64; U64];
+-
+-    Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4",
+-      store_1, pf_su_8_32;
+-    Vstx 4, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4",
+-      store_1, [P64];
+-    Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4",
+-      store_1, [S64; U64];
+-    Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-					      PtrTo Corereg |];
+-                              Use_operands [| VecArray (4, Dreg);
+-					      PtrTo Corereg |]]],
+-     Use_operands [| PtrTo Corereg; VecArray (4, Qreg) |], "vst4Q",
+-      store_1, pf_su_8_32;
+-
+-    Vstx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg); Immed |], "vst4_lane",
+-      store_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vstx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Qreg); Immed |], "vst4Q_lane",
+-      store_3, [P16; F32; U16; U32; S16; S32];
+-
+-    (* Logical operations. And.  *)
+-    Vand, [], All (3, Dreg), "vand", notype_2, su_8_32;
+-    Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64];
+-    Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64;
+-
+-    (* Or.  *)
+-    Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32;
+-    Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64];
+-    Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64;
+-
+-    (* Eor.  *)
+-    Veor, [], All (3, Dreg), "veor", notype_2, su_8_32;
+-    Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64];
+-    Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64;
+-
+-    (* Bic (And-not).  *)
+-    Vbic, [Compiler_optim "-O2"], All (3, Dreg), "vbic", notype_2, su_8_32;
+-    Vbic, [No_op; Compiler_optim "-O2"], All (3, Dreg), "vbic", notype_2, [S64; U64];
+-    Vbic, [Compiler_optim "-O2"], All (3, Qreg), "vbicQ", notype_2, su_8_64;
+-
+-    (* Or-not.  *)
+-    Vorn, [Compiler_optim "-O2"], All (3, Dreg), "vorn", notype_2, su_8_32;
+-    Vorn, [No_op; Compiler_optim "-O2"], All (3, Dreg), "vorn", notype_2, [S64; U64];
+-    Vorn, [Compiler_optim "-O2"], All (3, Qreg), "vornQ", notype_2, su_8_64;
+-  ]
+-
+-let type_in_crypto_only t
+-  = (t == P64) || (t == P128)
+-
+-let cross_product s1 s2
+-  = List.filter (fun (e, e') -> e <> e')
+-                (List.concat (List.map (fun e1 -> List.map (fun e2 -> (e1,e2)) s1) s2))
+-
+-let reinterp =
+-  let elems = P8 :: P16 :: F32 :: P64 :: su_8_64 in
+-  let casts = cross_product elems elems in
+-  List.map
+-    (fun (convto, convfrom) ->
+-       Vreinterp, (if (type_in_crypto_only convto) || (type_in_crypto_only convfrom)
+-                   then [Requires_feature "CRYPTO"] else []) @ [No_op], Use_operands [| Dreg; Dreg |],
+-                   "vreinterpret", conv_1, [Cast (convto, convfrom)])
+-    casts
+-
+-let reinterpq =
+-  let elems = P8 :: P16 :: F32 :: P64 :: P128 :: su_8_64 in
+-  let casts = cross_product elems elems in
+-  List.map
+-    (fun (convto, convfrom) ->
+-       Vreinterp, (if (type_in_crypto_only convto) || (type_in_crypto_only convfrom)
+-                   then [Requires_feature "CRYPTO"] else []) @ [No_op], Use_operands [| Qreg; Qreg |],
+-                   "vreinterpretQ", conv_1, [Cast (convto, convfrom)])
+-    casts
+-
+-(* Output routines.  *)
+-
+-let rec string_of_elt = function
+-    S8 -> "s8" | S16 -> "s16" | S32 -> "s32" | S64 -> "s64"
+-  | U8 -> "u8" | U16 -> "u16" | U32 -> "u32" | U64 -> "u64"
+-  | I8 -> "i8" | I16 -> "i16" | I32 -> "i32" | I64 -> "i64"
+-  | B8 -> "8" | B16 -> "16" | B32 -> "32" | B64 -> "64"
+-  | F16 -> "f16" | F32 -> "f32" | P8 -> "p8" | P16 -> "p16"
+-  | P64 -> "p64" | P128 -> "p128"
+-  | Conv (a, b) | Cast (a, b) -> string_of_elt a ^ "_" ^ string_of_elt b
+-  | NoElts -> failwith "No elts"
+-
+-let string_of_elt_dots elt =
+-  match elt with
+-    Conv (a, b) | Cast (a, b) -> string_of_elt a ^ "." ^ string_of_elt b
+-  | _ -> string_of_elt elt
+-
+-let string_of_vectype vt =
+-  let rec name affix = function
+-    T_int8x8 -> affix "int8x8"
+-  | T_int8x16 -> affix "int8x16"
+-  | T_int16x4 -> affix "int16x4"
+-  | T_int16x8 -> affix "int16x8"
+-  | T_int32x2 -> affix "int32x2"
+-  | T_int32x4 -> affix "int32x4"
+-  | T_int64x1 -> affix "int64x1"
+-  | T_int64x2 -> affix "int64x2"
+-  | T_uint8x8 -> affix "uint8x8"
+-  | T_uint8x16 -> affix "uint8x16"
+-  | T_uint16x4 -> affix "uint16x4"
+-  | T_uint16x8 -> affix "uint16x8"
+-  | T_uint32x2 -> affix "uint32x2"
+-  | T_uint32x4 -> affix "uint32x4"
+-  | T_uint64x1 -> affix "uint64x1"
+-  | T_uint64x2 -> affix "uint64x2"
+-  | T_float16x4 -> affix "float16x4"
+-  | T_float32x2 -> affix "float32x2"
+-  | T_float32x4 -> affix "float32x4"
+-  | T_poly8x8 -> affix "poly8x8"
+-  | T_poly8x16 -> affix "poly8x16"
+-  | T_poly16x4 -> affix "poly16x4"
+-  | T_poly16x8 -> affix "poly16x8"
+-  | T_int8 -> affix "int8"
+-  | T_int16 -> affix "int16"
+-  | T_int32 -> affix "int32"
+-  | T_int64 -> affix "int64"
+-  | T_uint8 -> affix "uint8"
+-  | T_uint16 -> affix "uint16"
+-  | T_uint32 -> affix "uint32"
+-  | T_uint64 -> affix "uint64"
+-  | T_poly8 -> affix "poly8"
+-  | T_poly16 -> affix "poly16"
+-  | T_poly64 -> affix "poly64"
+-  | T_poly64x1 -> affix "poly64x1"
+-  | T_poly64x2 -> affix "poly64x2"
+-  | T_poly128 -> affix "poly128"
+-  | T_float16 -> affix "float16"
+-  | T_float32 -> affix "float32"
+-  | T_immediate _ -> "const int"
+-  | T_void -> "void"
+-  | T_intQI -> "__builtin_neon_qi"
+-  | T_intHI -> "__builtin_neon_hi"
+-  | T_intSI -> "__builtin_neon_si"
+-  | T_intDI -> "__builtin_neon_di"
+-  | T_intTI -> "__builtin_neon_ti"
+-  | T_floatHF -> "__builtin_neon_hf"
+-  | T_floatSF -> "__builtin_neon_sf"
+-  | T_arrayof (num, base) ->
+-      let basename = name (fun x -> x) base in
+-      affix (Printf.sprintf "%sx%d" basename num)
+-  | T_ptrto x ->
+-      let basename = name affix x in
+-      Printf.sprintf "%s *" basename
+-  | T_const x ->
+-      let basename = name affix x in
+-      Printf.sprintf "const %s" basename
+-  in
+-    name (fun x -> x ^ "_t") vt
+-
+-let string_of_inttype = function
+-    B_TImode -> "__builtin_neon_ti"
+-  | B_EImode -> "__builtin_neon_ei"
+-  | B_OImode -> "__builtin_neon_oi"
+-  | B_CImode -> "__builtin_neon_ci"
+-  | B_XImode -> "__builtin_neon_xi"
+-
+-let string_of_mode = function
+-    V8QI -> "v8qi" | V4HI -> "v4hi" | V4HF  -> "v4hf"  | V2SI -> "v2si"
+-  | V2SF -> "v2sf" | DI   -> "di"   | V16QI -> "v16qi" | V8HI -> "v8hi"
+-  | V4SI -> "v4si" | V4SF -> "v4sf" | V2DI  -> "v2di"  | QI   -> "qi"
+-  | HI -> "hi" | SI -> "si" | SF -> "sf" | TI -> "ti"
+-
+-(* Use uppercase chars for letters which form part of the intrinsic name, but
+-   should be omitted from the builtin name (the info is passed in an extra
+-   argument, instead).  *)
+-let intrinsic_name name = String.lowercase name
+-
+-(* Allow the name of the builtin to be overridden by things (e.g. Flipped)
+-   found in the features list.  *)
+-let builtin_name features name =
+-  let name = List.fold_right
+-               (fun el name ->
+-                 match el with
+-                   Flipped x | Builtin_name x -> x
+-                 | _ -> name)
+-               features name in
+-  let islower x = let str = String.make 1 x in (String.lowercase str) = str
+-  and buf = Buffer.create (String.length name) in
+-  String.iter (fun c -> if islower c then Buffer.add_char buf c) name;
+-  Buffer.contents buf
+-
+-(* Transform an arity into a list of strings.  *)
+-let strings_of_arity a =
+-  match a with
+-  | Arity0 vt -> [string_of_vectype vt]
+-  | Arity1 (vt1, vt2) -> [string_of_vectype vt1; string_of_vectype vt2]
+-  | Arity2 (vt1, vt2, vt3) -> [string_of_vectype vt1;
+-			       string_of_vectype vt2;
+-                               string_of_vectype vt3]
+-  | Arity3 (vt1, vt2, vt3, vt4) -> [string_of_vectype vt1;
+-                                    string_of_vectype vt2;
+-                                    string_of_vectype vt3;
+-                                    string_of_vectype vt4]
+-  | Arity4 (vt1, vt2, vt3, vt4, vt5) -> [string_of_vectype vt1;
+-                                         string_of_vectype vt2;
+-                                         string_of_vectype vt3;
+-                                         string_of_vectype vt4;
+-                                         string_of_vectype vt5]
+-
+-(* Suffixes on the end of builtin names that are to be stripped in order
+-   to obtain the name used as an instruction.  They are only stripped if
+-   preceded immediately by an underscore.  *)
+-let suffixes_to_strip = [ "n"; "lane"; "dup" ]
+-
+-(* Get the possible names of an instruction corresponding to a "name" from the
+-   ops table.  This is done by getting the equivalent builtin name and
+-   stripping any suffixes from the list at the top of this file, unless
+-   the features list presents with an Instruction_name entry, in which
+-   case that is used; or unless the features list presents with a Flipped
+-   entry, in which case that is used.  If both such entries are present,
+-   the first in the list will be chosen.  *)
+-let get_insn_names features name =
+-  let names = try
+-  begin
+-    match List.find (fun feature -> match feature with
+-                                      Instruction_name _ -> true
+-				    | Flipped _ -> true
+-				    | _ -> false) features
+-    with
+-      Instruction_name names -> names
+-    | Flipped name -> [name]
+-    | _ -> assert false
+-  end
+-  with Not_found -> [builtin_name features name]
+-  in
+-  begin
+-    List.map (fun name' ->
+-      try
+-        let underscore = String.rindex name' '_' in
+-        let our_suffix = String.sub name' (underscore + 1)
+-                                    ((String.length name') - underscore - 1)
+-        in
+-          let rec strip remaining_suffixes =
+-            match remaining_suffixes with
+-              [] -> name'
+-            | s::ss when our_suffix = s -> String.sub name' 0 underscore
+-            | _::ss -> strip ss
+-          in
+-            strip suffixes_to_strip
+-      with (Not_found | Invalid_argument _) -> name') names
+-  end
+-
+-(* Apply a function to each element of a list and then comma-separate
+-   the resulting strings.  *)
+-let rec commas f elts acc =
+-  match elts with
+-    [] -> acc
+-  | [elt] -> acc ^ (f elt)
+-  | elt::elts ->
+-    commas f elts (acc ^ (f elt) ^ ", ")
+-
+-(* Given a list of features and the shape specified in the "ops" table, apply
+-   a function to each possible shape that the instruction may have.
+-   By default, this is the "shape" entry in "ops".  If the features list
+-   contains a Disassembles_as entry, the shapes contained in that entry are
+-   mapped to corresponding outputs and returned in a list.  If there is more
+-   than one Disassembles_as entry, only the first is used.  *)
+-let analyze_all_shapes features shape f =
+-  try
+-    match List.find (fun feature ->
+-                       match feature with Disassembles_as _ -> true
+-                                        | _ -> false)
+-                    features with
+-      Disassembles_as shapes -> List.map f shapes
+-    | _ -> assert false
+-  with Not_found -> [f shape]
+-
+-(* The crypto intrinsics have unconventional shapes and are not that
+-   numerous to be worth the trouble of encoding here.  We implement them
+-   explicitly here.  *)
+-let crypto_intrinsics =
+-"
+-#ifdef __ARM_FEATURE_CRYPTO
+-
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vldrq_p128 (poly128_t const * __ptr)
+-{
+-#ifdef __ARM_BIG_ENDIAN
+-  poly64_t* __ptmp = (poly64_t*) __ptr;
+-  poly64_t __d0 = vld1_p64 (__ptmp);
+-  poly64_t __d1 = vld1_p64 (__ptmp + 1);
+-  return vreinterpretq_p128_p64 (vcombine_p64 (__d1, __d0));
+-#else
+-  return vreinterpretq_p128_p64 (vld1q_p64 ((poly64_t*) __ptr));
+-#endif
+-}
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vstrq_p128 (poly128_t * __ptr, poly128_t __val)
+-{
+-#ifdef __ARM_BIG_ENDIAN
+-  poly64x2_t __tmp = vreinterpretq_p64_p128 (__val);
+-  poly64_t __d0 = vget_high_p64 (__tmp);
+-  poly64_t __d1 = vget_low_p64 (__tmp);
+-  vst1q_p64 ((poly64_t*) __ptr, vcombine_p64 (__d0, __d1));
+-#else
+-  vst1q_p64 ((poly64_t*) __ptr, vreinterpretq_p64_p128 (__val));
+-#endif
+-}
+-
+-/* The vceq_p64 intrinsic does not map to a single instruction.
+-   Instead we emulate it by performing a 32-bit variant of the vceq
+-   and applying a pairwise min reduction to the result.
+-   vceq_u32 will produce two 32-bit halves, each of which will contain either
+-   all ones or all zeros depending on whether the corresponding 32-bit
+-   halves of the poly64_t were equal.  The whole poly64_t values are equal
+-   if and only if both halves are equal, i.e. vceq_u32 returns all ones.
+-   If the result is all zeroes for any half then the whole result is zeroes.
+-   This is what the pairwise min reduction achieves.  */
+-
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_p64 (poly64x1_t __a, poly64x1_t __b)
+-{
+-  uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+-  uint32x2_t __t_b = vreinterpret_u32_p64 (__b);
+-  uint32x2_t __c = vceq_u32 (__t_a, __t_b);
+-  uint32x2_t __m = vpmin_u32 (__c, __c);
+-  return vreinterpret_u64_u32 (__m);
+-}
+-
+-/* The vtst_p64 intrinsic does not map to a single instruction.
+-   We emulate it in way similar to vceq_p64 above but here we do
+-   a reduction with max since if any two corresponding bits
+-   in the two poly64_t's match, then the whole result must be all ones.  */
+-
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vtst_p64 (poly64x1_t __a, poly64x1_t __b)
+-{
+-  uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+-  uint32x2_t __t_b = vreinterpret_u32_p64 (__b);
+-  uint32x2_t __c = vtst_u32 (__t_a, __t_b);
+-  uint32x2_t __m = vpmax_u32 (__c, __c);
+-  return vreinterpret_u64_u32 (__m);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaeseq_u8 (uint8x16_t __data, uint8x16_t __key)
+-{
+-  return __builtin_arm_crypto_aese (__data, __key);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesdq_u8 (uint8x16_t __data, uint8x16_t __key)
+-{
+-  return __builtin_arm_crypto_aesd (__data, __key);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesmcq_u8 (uint8x16_t __data)
+-{
+-  return __builtin_arm_crypto_aesmc (__data);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesimcq_u8 (uint8x16_t __data)
+-{
+-  return __builtin_arm_crypto_aesimc (__data);
+-}
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vsha1h_u32 (uint32_t __hash_e)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  __t = __builtin_arm_crypto_sha1h (__t);
+-  return vgetq_lane_u32 (__t, 0);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1cq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  return __builtin_arm_crypto_sha1c (__hash_abcd, __t, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1pq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  return __builtin_arm_crypto_sha1p (__hash_abcd, __t, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1mq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  return __builtin_arm_crypto_sha1m (__hash_abcd, __t, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7, uint32x4_t __w8_11)
+-{
+-  return __builtin_arm_crypto_sha1su0 (__w0_3, __w4_7, __w8_11);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w12_15)
+-{
+-  return __builtin_arm_crypto_sha1su1 (__tw0_3, __w12_15);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256hq_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+-{
+-  return __builtin_arm_crypto_sha256h (__hash_abcd, __hash_efgh, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256h2q_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+-{
+-  return __builtin_arm_crypto_sha256h2 (__hash_abcd, __hash_efgh, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7)
+-{
+-  return __builtin_arm_crypto_sha256su0 (__w0_3, __w4_7);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15)
+-{
+-  return __builtin_arm_crypto_sha256su1 (__tw0_3, __w8_11, __w12_15);
+-}
+-
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_p64 (poly64_t __a, poly64_t __b)
+-{
+-  return (poly128_t) __builtin_arm_crypto_vmullp64 ((uint64_t) __a, (uint64_t) __b);
+-}
+-
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
+-{
+-  poly64_t __t1 = vget_high_p64 (__a);
+-  poly64_t __t2 = vget_high_p64 (__b);
+-
+-  return (poly128_t) __builtin_arm_crypto_vmullp64 ((uint64_t) __t1, (uint64_t) __t2);
+-}
+-
+-#endif
+-"
+--- a/src/gcc/config/arm/predicates.md
++++ b/src/gcc/config/arm/predicates.md
+@@ -141,8 +141,7 @@
+        (match_test "const_ok_for_arm (~INTVAL (op))")))
+ 
+ (define_predicate "const0_operand"
+-  (and (match_code "const_int")
+-       (match_test "INTVAL (op) == 0")))
++  (match_test "op == CONST0_RTX (mode)"))
+ 
+ ;; Something valid on the RHS of an ARM data-processing instruction
+ (define_predicate "arm_rhs_operand"
+@@ -170,8 +169,7 @@
+ 
+ (define_predicate "const_neon_scalar_shift_amount_operand"
+   (and (match_code "const_int")
+-       (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
+-	&& ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
++       (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
+ 
+ (define_predicate "ldrd_strd_offset_operand"
+   (and (match_operand 0 "const_int_operand")
+@@ -243,11 +241,6 @@
+        (and (match_code "const_double")
+ 	    (match_test "arm_const_double_rtx (op)"))))
+ 
+-(define_predicate "arm_float_compare_operand"
+-  (if_then_else (match_test "TARGET_VFP")
+-		(match_operand 0 "vfp_compare_operand")
+-		(match_operand 0 "s_register_operand")))
+-
+ ;; True for valid index operands.
+ (define_predicate "index_operand"
+   (ior (match_operand 0 "s_register_operand")
+@@ -285,19 +278,19 @@
+ 		      (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
+ 		 (and (match_code "rotate")
+ 		      (match_test "CONST_INT_P (XEXP (op, 1))
+-				   && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
++				   && (UINTVAL (XEXP (op, 1))) < 32")))
+ 	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
+ 		 (match_test "!CONST_INT_P (XEXP (op, 1))
+-			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
++			      || (UINTVAL (XEXP (op, 1))) < 32")))
+        (match_test "mode == GET_MODE (op)")))
+ 
+ (define_special_predicate "shift_nomul_operator"
+   (and (ior (and (match_code "rotate")
+ 		 (match_test "CONST_INT_P (XEXP (op, 1))
+-			      && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))
++			      && (UINTVAL (XEXP (op, 1))) < 32"))
+ 	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
+ 		 (match_test "!CONST_INT_P (XEXP (op, 1))
+-			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
++			      || (UINTVAL (XEXP (op, 1))) < 32")))
+        (match_test "mode == GET_MODE (op)")))
+ 
+ ;; True for shift operators which can be used with saturation instructions.
+@@ -306,7 +299,7 @@
+                  (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
+             (and (match_code "ashift,ashiftrt")
+                  (match_test "CONST_INT_P (XEXP (op, 1))
+-		              && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
++		              && (UINTVAL (XEXP (op, 1)) < 32)")))
+        (match_test "mode == GET_MODE (op)")))
+ 
+ ;; True for MULT, to identify which variant of shift_operator is in use.
+@@ -398,6 +391,12 @@
+ 	     || mode == CC_DGTUmode));
+ })
+ 
++;; Any register, including CC
++(define_predicate "cc_register_operand"
++  (and (match_code "reg")
++       (ior (match_operand 0 "s_register_operand")
++	    (match_operand 0 "cc_register"))))
++
+ (define_special_predicate "arm_extendqisi_mem_op"
+   (and (match_operand 0 "memory_operand")
+        (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
+@@ -532,7 +531,7 @@
+   (ior (and (match_code "reg,subreg")
+ 	    (match_operand 0 "s_register_operand"))
+        (and (match_code "const_int")
+-	    (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
++	    (match_test "(UINTVAL (op)) < 256"))))
+ 
+ (define_predicate "thumb1_cmpneg_operand"
+   (and (match_code "const_int")
+@@ -612,69 +611,23 @@
+ (define_special_predicate "vect_par_constant_high" 
+   (match_code "parallel")
+ {
+-  HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int i;
+-  int base = GET_MODE_NUNITS (mode);
+-
+-  if ((count < 1)
+-      || (count != base/2))
+-    return false;
+-    
+-  if (!VECTOR_MODE_P (mode))
+-    return false;
+-
+-  for (i = 0; i < count; i++)
+-   {
+-     rtx elt = XVECEXP (op, 0, i);
+-     int val;
+-
+-     if (!CONST_INT_P (elt))
+-       return false;
+-
+-     val = INTVAL (elt);
+-     if (val != (base/2) + i)
+-       return false;
+-   }
+-  return true; 
++  return arm_simd_check_vect_par_cnst_half_p (op, mode, true);
+ })
+ 
+ (define_special_predicate "vect_par_constant_low"
+   (match_code "parallel")
+ {
+-  HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int i;
+-  int base = GET_MODE_NUNITS (mode);
+-
+-  if ((count < 1)
+-      || (count != base/2))
+-    return false;
+-    
+-  if (!VECTOR_MODE_P (mode))
+-    return false;
+-
+-  for (i = 0; i < count; i++)
+-   {
+-     rtx elt = XVECEXP (op, 0, i);
+-     int val;
+-
+-     if (!CONST_INT_P (elt))
+-       return false;
+-
+-     val = INTVAL (elt);
+-     if (val != i)
+-       return false;
+-   } 
+-  return true; 
++  return arm_simd_check_vect_par_cnst_half_p (op, mode, false);
+ })
+ 
+ (define_predicate "const_double_vcvt_power_of_two_reciprocal"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP
+-                   && vfp3_const_double_for_fract_bits (op)")))
++       (match_test "TARGET_32BIT
++		    && vfp3_const_double_for_fract_bits (op)")))
+ 
+ (define_predicate "const_double_vcvt_power_of_two"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP
++       (match_test "TARGET_32BIT
+ 		    && vfp3_const_double_for_bits (op) > 0")))
+ 
+ (define_predicate "neon_struct_operand"
+--- a/src/gcc/config/arm/sync.md
++++ b/src/gcc/config/arm/sync.md
+@@ -63,37 +63,59 @@
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "atomic_load<mode>"
+-  [(set (match_operand:QHSI 0 "register_operand" "=r")
++  [(set (match_operand:QHSI 0 "register_operand" "=r,r,l")
+     (unspec_volatile:QHSI
+-      [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q")
+-       (match_operand:SI 2 "const_int_operand")]		;; model
++      [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q,Q,Q")
++       (match_operand:SI 2 "const_int_operand" "n,Pf,n")]	;; model
+       VUNSPEC_LDA))]
+   "TARGET_HAVE_LDACQ"
+   {
+     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
+     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
+-      return \"ldr<sync_sfx>%?\\t%0, %1\";
++      {
++	if (TARGET_THUMB1)
++	  return \"ldr<sync_sfx>\\t%0, %1\";
++	else
++	  return \"ldr<sync_sfx>%?\\t%0, %1\";
++      }
+     else
+-      return \"lda<sync_sfx>%?\\t%0, %1\";
++      {
++	if (TARGET_THUMB1)
++	  return \"lda<sync_sfx>\\t%0, %1\";
++	else
++	  return \"lda<sync_sfx>%?\\t%0, %1\";
++      }
+   }
+-  [(set_attr "predicable" "yes")
++  [(set_attr "arch" "32,v8mb,any")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "atomic_store<mode>"
+-  [(set (match_operand:QHSI 0 "memory_operand" "=Q")
++  [(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q")
+     (unspec_volatile:QHSI
+-      [(match_operand:QHSI 1 "general_operand" "r")
+-       (match_operand:SI 2 "const_int_operand")]		;; model
++      [(match_operand:QHSI 1 "general_operand" "r,r,l")
++       (match_operand:SI 2 "const_int_operand" "n,Pf,n")]	;; model
+       VUNSPEC_STL))]
+   "TARGET_HAVE_LDACQ"
+   {
+     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
+     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
+-      return \"str<sync_sfx>%?\t%1, %0\";
++      {
++	if (TARGET_THUMB1)
++	  return \"str<sync_sfx>\t%1, %0\";
++	else
++	  return \"str<sync_sfx>%?\t%1, %0\";
++      }
+     else
+-      return \"stl<sync_sfx>%?\t%1, %0\";
++      {
++	if (TARGET_THUMB1)
++	  return \"stl<sync_sfx>\t%1, %0\";
++	else
++	  return \"stl<sync_sfx>%?\t%1, %0\";
++      }
+   }
+-  [(set_attr "predicable" "yes")
++  [(set_attr "arch" "32,v8mb,any")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ ;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets
+@@ -117,7 +139,7 @@
+   [(match_operand:DI 0 "s_register_operand")		;; val out
+    (match_operand:DI 1 "mem_noofs_operand")		;; memory
+    (match_operand:SI 2 "const_int_operand")]		;; model
+-  "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQ)
++  "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQEXD)
+    && ARM_DOUBLEWORD_ALIGN"
+ {
+   memmodel model = memmodel_from_int (INTVAL (operands[2]));
+@@ -125,7 +147,7 @@
+   /* For ARMv8-A we can use an LDAEXD to atomically load two 32-bit registers
+      when acquire or stronger semantics are needed.  When the relaxed model is
+      used this can be relaxed to a normal LDRD.  */
+-  if (TARGET_HAVE_LDACQ)
++  if (TARGET_HAVE_LDACQEXD)
+     {
+       if (is_mm_relaxed (model))
+ 	emit_insn (gen_arm_atomic_loaddi2_ldrd (operands[0], operands[1]));
+@@ -167,21 +189,23 @@
+   DONE;
+ })
+ 
++;; Constraints of this pattern must be at least as strict as those of the
++;; cbranchsi operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_compare_and_swap<mode>_1"
+-  [(set (reg:CC_Z CC_REGNUM)					;; bool out
++  [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l")		;; bool out
+ 	(unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS))
+-   (set (match_operand:SI 0 "s_register_operand" "=&r")		;; val out
++   (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h")	;; val out
+ 	(zero_extend:SI
+-	  (match_operand:NARROW 1 "mem_noofs_operand" "+Ua")))	;; memory
+-   (set (match_dup 1)
++	  (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")))	;; memory
++   (set (match_dup 2)
+ 	(unspec_volatile:NARROW
+-	  [(match_operand:SI 2 "arm_add_operand" "rIL")		;; expected
+-	   (match_operand:NARROW 3 "s_register_operand" "r")	;; desired
+-	   (match_operand:SI 4 "const_int_operand")		;; is_weak
+-	   (match_operand:SI 5 "const_int_operand")		;; mod_s
+-	   (match_operand:SI 6 "const_int_operand")]		;; mod_f
++	  [(match_operand:SI 3 "arm_add_operand" "rIL,lIL*h,J,*r")	;; expected
++	   (match_operand:NARROW 4 "s_register_operand" "r,r,r,r")	;; desired
++	   (match_operand:SI 5 "const_int_operand")		;; is_weak
++	   (match_operand:SI 6 "const_int_operand")		;; mod_s
++	   (match_operand:SI 7 "const_int_operand")]		;; mod_f
+ 	  VUNSPEC_ATOMIC_CAS))
+-   (clobber (match_scratch:SI 7 "=&r"))]
++   (clobber (match_scratch:SI 8 "=&r,X,X,X"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -189,27 +213,30 @@
+   {
+     arm_split_compare_and_swap (operands);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ 
+ (define_mode_attr cas_cmp_operand
+   [(SI "arm_add_operand") (DI "cmpdi_operand")])
+ (define_mode_attr cas_cmp_str
+   [(SI "rIL") (DI "rDi")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the
++;; cbranchsi operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_compare_and_swap<mode>_1"
+-  [(set (reg:CC_Z CC_REGNUM)					;; bool out
++  [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l")		;; bool out
+ 	(unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS))
+-   (set (match_operand:SIDI 0 "s_register_operand" "=&r")	;; val out
+-	(match_operand:SIDI 1 "mem_noofs_operand" "+Ua"))	;; memory
+-   (set (match_dup 1)
++   (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h")	;; val out
++	(match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))	;; memory
++   (set (match_dup 2)
+ 	(unspec_volatile:SIDI
+-	  [(match_operand:SIDI 2 "<cas_cmp_operand>" "<cas_cmp_str>") ;; expect
+-	   (match_operand:SIDI 3 "s_register_operand" "r")	;; desired
+-	   (match_operand:SI 4 "const_int_operand")		;; is_weak
+-	   (match_operand:SI 5 "const_int_operand")		;; mod_s
+-	   (match_operand:SI 6 "const_int_operand")]		;; mod_f
++	  [(match_operand:SIDI 3 "<cas_cmp_operand>" "<cas_cmp_str>,lIL*h,J,*r") ;; expect
++	   (match_operand:SIDI 4 "s_register_operand" "r,r,r,r")	;; desired
++	   (match_operand:SI 5 "const_int_operand")		;; is_weak
++	   (match_operand:SI 6 "const_int_operand")		;; mod_s
++	   (match_operand:SI 7 "const_int_operand")]		;; mod_f
+ 	  VUNSPEC_ATOMIC_CAS))
+-   (clobber (match_scratch:SI 7 "=&r"))]
++   (clobber (match_scratch:SI 8 "=&r,X,X,X"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -217,18 +244,19 @@
+   {
+     arm_split_compare_and_swap (operands);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ 
+ (define_insn_and_split "atomic_exchange<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")	;; output
+-	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua"))	;; memory
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,&r")	;; output
++	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua"))	;; memory
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+-	  [(match_operand:QHSD 2 "s_register_operand" "r")	;; input
++	  [(match_operand:QHSD 2 "s_register_operand" "r,r")	;; input
+ 	   (match_operand:SI 3 "const_int_operand" "")]		;; model
+ 	  VUNSPEC_ATOMIC_XCHG))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -237,7 +265,11 @@
+     arm_split_atomic_op (SET, operands[0], NULL, operands[1],
+ 			 operands[2], operands[3], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
++
++;; The following mode and code attribute are defined here because they are
++;; specific to atomics and are not needed anywhere else.
+ 
+ (define_mode_attr atomic_op_operand
+   [(QI "reg_or_int_operand")
+@@ -248,16 +280,24 @@
+ (define_mode_attr atomic_op_str
+   [(QI "rn") (HI "rn") (SI "rn") (DI "r")])
+ 
++(define_code_attr thumb1_atomic_op_str
++  [(ior "l,l") (xor "l,l") (and "l,l") (plus "lIJL,r") (minus "lPd,lPd")])
++
++(define_code_attr thumb1_atomic_newop_str
++  [(ior "&l,&l") (xor "&l,&l") (and "&l,&l") (plus "&l,&r") (minus "&l,&l")])
++
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_<sync_optab><mode>"
+-  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua")
++  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua,Ua,Ua")
+ 	(unspec_volatile:QHSD
+ 	  [(syncop:QHSD (match_dup 0)
+-	     (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>"))
++	     (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>,<thumb1_atomic_op_str>"))
+ 	   (match_operand:SI 2 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 3 "=&r"))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:QHSD 3 "=&r,<thumb1_atomic_newop_str>"))
++   (clobber (match_scratch:SI 4 "=&r,&l,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -266,19 +306,22 @@
+     arm_split_atomic_op (<CODE>, NULL, operands[3], operands[0],
+ 			 operands[1], operands[2], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic NANDs in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_nand<mode>"
+-  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua")
++  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua,Ua")
+ 	(unspec_volatile:QHSD
+ 	  [(not:QHSD
+ 	     (and:QHSD (match_dup 0)
+-	       (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>")))
++	       (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>,l")))
+ 	   (match_operand:SI 2 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 3 "=&r"))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:QHSD 3 "=&r,&l"))
++   (clobber (match_scratch:SI 4 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -287,20 +330,38 @@
+     arm_split_atomic_op (NOT, NULL, operands[3], operands[0],
+ 			 operands[1], operands[2], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
++
++;; 3 alternatives are needed to represent constraints after split from
++;; thumb1_addsi3: (i) case where operand1 and destination can be in different
++;; registers, (ii) case where they are in the same low register and (iii) case
++;; when they are in the same register without restriction on the register.  We
++;; disparage slightly alternatives that require copying the old value into the
++;; register for the new value (see bind_old_new in arm_split_atomic_op).
++(define_code_attr thumb1_atomic_fetch_op_str
++  [(ior "l,l,l") (xor "l,l,l") (and "l,l,l") (plus "lL,?IJ,?r") (minus "lPd,lPd,lPd")])
++
++(define_code_attr thumb1_atomic_fetch_newop_str
++  [(ior "&l,&l,&l") (xor "&l,&l,&l") (and "&l,&l,&l") (plus "&l,&l,&r") (minus "&l,&l,&l")])
+ 
++(define_code_attr thumb1_atomic_fetch_oldop_str
++  [(ior "&r,&r,&r") (xor "&r,&r,&r") (and "&r,&r,&r") (plus "&l,&r,&r") (minus "&l,&l,&l")])
++
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_fetch_<sync_optab><mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
+-	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua"))
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,<thumb1_atomic_fetch_oldop_str>")
++	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(syncop:QHSD (match_dup 1)
+-	     (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>"))
++	     (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,<thumb1_atomic_fetch_op_str>"))
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 4 "=&r"))
+-   (clobber (match_scratch:SI 5 "=&r"))]
++   (clobber (match_scratch:QHSD 4 "=&r,<thumb1_atomic_fetch_newop_str>"))
++   (clobber (match_scratch:SI 5 "=&r,&l,&l,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -309,21 +370,24 @@
+     arm_split_atomic_op (<CODE>, operands[0], operands[4], operands[1],
+ 			 operands[2], operands[3], operands[5]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic NANDs in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_fetch_nand<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
+-	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua"))
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,&r")
++	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua"))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(not:QHSD
+ 	     (and:QHSD (match_dup 1)
+-	       (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>")))
++	       (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,l")))
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 4 "=&r"))
+-   (clobber (match_scratch:SI 5 "=&r"))]
++   (clobber (match_scratch:QHSD 4 "=&r,&l"))
++   (clobber (match_scratch:SI 5 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -332,20 +396,23 @@
+     arm_split_atomic_op (NOT, operands[0], operands[4], operands[1],
+ 			 operands[2], operands[3], operands[5]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_<sync_optab>_fetch<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,<thumb1_atomic_newop_str>")
+ 	(syncop:QHSD
+-	  (match_operand:QHSD 1 "mem_noofs_operand" "+Ua")
+-	  (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>")))
++	  (match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua,Ua")
++	  (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,<thumb1_atomic_op_str>")))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(match_dup 1) (match_dup 2)
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "=&r,&l,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -354,21 +421,24 @@
+     arm_split_atomic_op (<CODE>, NULL, operands[0], operands[1],
+ 			 operands[2], operands[3], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic NANDs in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_nand_fetch<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,&l")
+ 	(not:QHSD
+ 	  (and:QHSD
+-	    (match_operand:QHSD 1 "mem_noofs_operand" "+Ua")
+-	    (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>"))))
++	    (match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua")
++	    (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,l"))))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(match_dup 1) (match_dup 2)
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -377,48 +447,61 @@
+     arm_split_atomic_op (NOT, NULL, operands[0], operands[1],
+ 			 operands[2], operands[3], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
+ 
+ (define_insn "arm_load_exclusive<mode>"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+         (zero_extend:SI
+ 	  (unspec_volatile:NARROW
+-	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")]
++	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")]
+ 	    VUNSPEC_LL)))]
+   "TARGET_HAVE_LDREXBH"
+-  "ldrex<sync_sfx>%?\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldrex<sync_sfx>%?\t%0, %C1
++   ldrex<sync_sfx>\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_acquire_exclusive<mode>"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+         (zero_extend:SI
+ 	  (unspec_volatile:NARROW
+-	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")]
++	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")]
+ 	    VUNSPEC_LAX)))]
+   "TARGET_HAVE_LDACQ"
+-  "ldaex<sync_sfx>%?\\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldaex<sync_sfx>%?\\t%0, %C1
++   ldaex<sync_sfx>\\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_exclusivesi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ 	(unspec_volatile:SI
+-	  [(match_operand:SI 1 "mem_noofs_operand" "Ua")]
++	  [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")]
+ 	  VUNSPEC_LL))]
+   "TARGET_HAVE_LDREX"
+-  "ldrex%?\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldrex%?\t%0, %C1
++   ldrex\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_acquire_exclusivesi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ 	(unspec_volatile:SI
+-	  [(match_operand:SI 1 "mem_noofs_operand" "Ua")]
++	  [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")]
+ 	  VUNSPEC_LAX))]
+   "TARGET_HAVE_LDACQ"
+-  "ldaex%?\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldaex%?\t%0, %C1
++   ldaex\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_exclusivedi"
+@@ -436,7 +519,7 @@
+ 	(unspec_volatile:DI
+ 	  [(match_operand:DI 1 "mem_noofs_operand" "Ua")]
+ 	  VUNSPEC_LAX))]
+-  "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
++  "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
+   "ldaexd%?\t%0, %H0, %C1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+@@ -452,16 +535,18 @@
+   {
+     if (<MODE>mode == DImode)
+       {
+-	rtx value = operands[2];
+ 	/* The restrictions on target registers in ARM mode are that the two
+ 	   registers are consecutive and the first one is even; Thumb is
+ 	   actually more flexible, but DI should give us this anyway.
+-	   Note that the 1st register always gets the lowest word in memory.  */
+-	gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
+-	operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
+-	return "strexd%?\t%0, %2, %3, %C1";
++	   Note that the 1st register always gets the
++	   lowest word in memory.  */
++	gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
++	return "strexd%?\t%0, %2, %H2, %C1";
+       }
+-    return "strex<sync_sfx>%?\t%0, %2, %C1";
++    if (TARGET_THUMB1)
++      return "strex<sync_sfx>\t%0, %2, %C1";
++    else
++      return "strex<sync_sfx>%?\t%0, %2, %C1";
+   }
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+@@ -473,25 +558,26 @@
+ 	(unspec_volatile:DI
+ 	  [(match_operand:DI 2 "s_register_operand" "r")]
+ 	  VUNSPEC_SLX))]
+-  "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
++  "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
+   {
+-    rtx value = operands[2];
+     /* See comment in arm_store_exclusive<mode> above.  */
+-    gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
+-    operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
+-    return "stlexd%?\t%0, %2, %3, %C1";
++    gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
++    return "stlexd%?\t%0, %2, %H2, %C1";
+   }
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_store_release_exclusive<mode>"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
+ 	(unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX))
+-   (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua")
++   (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua,Ua")
+ 	(unspec_volatile:QHSI
+-	  [(match_operand:QHSI 2 "s_register_operand" "r")]
++	  [(match_operand:QHSI 2 "s_register_operand" "r,r")]
+ 	  VUNSPEC_SLX))]
+   "TARGET_HAVE_LDACQ"
+-  "stlex<sync_sfx>%?\t%0, %2, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   stlex<sync_sfx>%?\t%0, %2, %C1
++   stlex<sync_sfx>\t%0, %2, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+--- a/src/gcc/config/arm/t-aprofile
++++ b/src/gcc/config/arm/t-aprofile
+@@ -49,38 +49,33 @@ MULTILIB_DIRNAMES      += fpv3 simdv1 fpv4 simdvfpv4 simdv8
+ MULTILIB_OPTIONS       += mfloat-abi=softfp/mfloat-abi=hard
+ MULTILIB_DIRNAMES      += softfp hard
+ 
+-# We don't build no-float libraries with an FPU.
+-MULTILIB_EXCEPTIONS    += *mfpu=vfpv3-d16
+-MULTILIB_EXCEPTIONS    += *mfpu=neon
+-MULTILIB_EXCEPTIONS    += *mfpu=vfpv4-d16
+-MULTILIB_EXCEPTIONS    += *mfpu=neon-vfpv4
+-MULTILIB_EXCEPTIONS    += *mfpu=neon-fp-armv8
+-
+-# We don't build libraries requiring an FPU at the CPU/Arch/ISA level.
+-MULTILIB_EXCEPTIONS    += mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += mfpu=*
+-MULTILIB_EXCEPTIONS    += mthumb/mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += mthumb/mfpu=*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/mfloat-abi=*
+-
+-# Ensure the correct FPU variants apply to the correct base architectures.
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/*mfpu=vfpv3-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/*mfpu=neon/*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=vfpv3-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=neon/*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/*mfpu=vfpv4-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/*mfpu=neon-vfpv4*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=vfpv4-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=neon-vfpv4*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/*mfpu=neon-fp-armv8*
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/*mfpu=neon-fp-armv8*
++
++# Option combinations to build library with
++
++# Default CPU/Arch (ARM is implicitly included because it uses the default
++# multilib)
++MULTILIB_REQUIRED      += mthumb
++
++# ARMv7-A
++MULTILIB_REQUIRED      += *march=armv7-a
++MULTILIB_REQUIRED      += *march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=*
++MULTILIB_REQUIRED      += *march=armv7-a/mfpu=neon/mfloat-abi=*
++
++# ARMv7VE
++MULTILIB_REQUIRED      += *march=armv7ve
++MULTILIB_REQUIRED      += *march=armv7ve/mfpu=vfpv4-d16/mfloat-abi=*
++MULTILIB_REQUIRED      += *march=armv7ve/mfpu=neon-vfpv4/mfloat-abi=*
++
++# ARMv8-A
++MULTILIB_REQUIRED      += *march=armv8-a
++MULTILIB_REQUIRED      += *march=armv8-a/mfpu=neon-fp-armv8/mfloat-abi=*
++
+ 
+ # CPU Matches
+ MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a8
+ MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a9
+ MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a5
++MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a7
+ MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a15
+ MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a12
+ MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a17
+@@ -93,6 +88,9 @@ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57.cortex-a53
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a72
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a72.cortex-a53
++MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a73
++MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a73.cortex-a35
++MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a73.cortex-a53
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?exynos-m1
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?qdf24xx
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?xgene1
+@@ -101,12 +99,17 @@ MULTILIB_MATCHES       += march?armv8-a=mcpu?xgene1
+ MULTILIB_MATCHES       += march?armv8-a=march?armv8-a+crc
+ MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a
+ MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a+crc
++MULTILIB_MATCHES       += march?armv8-a=march?armv8.2-a
++MULTILIB_MATCHES       += march?armv8-a=march?armv8.2-a+fp16
+ 
+ # FPU matches
+ MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3
+ MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
+-MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-fp16-d16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16
++MULTILIB_MATCHES       += mfpu?neon=mfpu?neon-fp16
+ MULTILIB_MATCHES       += mfpu?vfpv4-d16=mfpu?vfpv4
++MULTILIB_MATCHES       += mfpu?vfpv4-d16=mfpu?fpv5-d16
++MULTILIB_MATCHES       += mfpu?vfpv4-d16=mfpu?fp-armv8
+ MULTILIB_MATCHES       += mfpu?neon-fp-armv8=mfpu?crypto-neon-fp-armv8
+ 
+ 
+@@ -124,10 +127,6 @@ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
+ 
+ 
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7ve/mfpu.neon/mfloat-abi.hard
+@@ -140,10 +139,6 @@ MULTILIB_REUSE	      += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mf
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
+ 
+ 
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv7ve/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv7ve/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
+ MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+ 
+@@ -163,10 +158,6 @@ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthu
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
+ 
+ 
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.neon/mfloat-abi.hard
+@@ -179,10 +170,6 @@ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/ma
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
+ 
+ 
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv7ve/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
+ MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+ 
+--- a/src/gcc/config/arm/t-arm
++++ b/src/gcc/config/arm/t-arm
+@@ -95,7 +95,8 @@ arm.o: $(srcdir)/config/arm/arm.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
+   $(srcdir)/config/arm/arm-cores.def \
+   $(srcdir)/config/arm/arm-arches.def $(srcdir)/config/arm/arm-fpus.def \
+   $(srcdir)/config/arm/arm-protos.h \
+-  $(srcdir)/config/arm/arm_neon_builtins.def
++  $(srcdir)/config/arm/arm_neon_builtins.def \
++  $(srcdir)/config/arm/arm_vfp_builtins.def
+ 
+ arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(CONFIG_H) \
+   $(SYSTEM_H) coretypes.h $(TM_H) \
+@@ -103,6 +104,7 @@ arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(CONFIG_H) \
+   $(DIAGNOSTIC_CORE_H) $(OPTABS_H) \
+   $(srcdir)/config/arm/arm-protos.h \
+   $(srcdir)/config/arm/arm_neon_builtins.def \
++  $(srcdir)/config/arm/arm_vfp_builtins.def \
+   $(srcdir)/config/arm/arm-simd-builtin-types.def
+ 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ 		$(srcdir)/config/arm/arm-builtins.c
+--- /dev/null
++++ b/src/gcc/config/arm/t-rmprofile
+@@ -0,0 +1,176 @@
++# Copyright (C) 2016 Free Software Foundation, Inc.
++#
++# This file is part of GCC.
++#
++# GCC is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3, or (at your option)
++# any later version.
++#
++# GCC is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++# This is a target makefile fragment that attempts to get
++# multilibs built for the range of CPU's, FPU's and ABI's that
++# are relevant for the ARM architecture.  It should not be used in
++# conjunction with another make file fragment and assumes --with-arch,
++# --with-cpu, --with-fpu, --with-float, --with-mode have their default
++# values during the configure step.  We enforce this during the
++# top-level configury.
++
++MULTILIB_OPTIONS     =
++MULTILIB_DIRNAMES    =
++MULTILIB_EXCEPTIONS  =
++MULTILIB_MATCHES     =
++MULTILIB_REUSE       =
++
++# We have the following hierachy:
++#   ISA: A32 (.) or T16/T32 (thumb).
++#   Architecture: ARMv6S-M (v6-m), ARMv7-M (v7-m), ARMv7E-M (v7e-m),
++#                 ARMv8-M Baseline (v8-m.base) or ARMv8-M Mainline (v8-m.main).
++#   FPU: VFPv3-D16 (fpv3), FPV4-SP-D16 (fpv4-sp), FPV5-SP-D16 (fpv5-sp),
++#        VFPv5-D16 (fpv5), or None (.).
++#   Float-abi: Soft (.), softfp (softfp), or hard (hardfp).
++
++# Options to build libraries with
++
++MULTILIB_OPTIONS       += mthumb
++MULTILIB_DIRNAMES      += thumb
++
++MULTILIB_OPTIONS       += march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7/march=armv8-m.base/march=armv8-m.main
++MULTILIB_DIRNAMES      += v6-m v7-m v7e-m v7-ar v8-m.base v8-m.main
++
++MULTILIB_OPTIONS       += mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-sp-d16/mfpu=fpv5-d16
++MULTILIB_DIRNAMES      += fpv3 fpv4-sp fpv5-sp fpv5
++
++MULTILIB_OPTIONS       += mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES      += softfp hard
++
++
++# Option combinations to build library with
++
++# Default CPU/Arch
++MULTILIB_REQUIRED      += mthumb
++MULTILIB_REQUIRED      += mfloat-abi=hard
++
++# ARMv6-M
++MULTILIB_REQUIRED      += mthumb/march=armv6s-m
++
++# ARMv8-M Baseline
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.base
++
++# ARMv7-M
++MULTILIB_REQUIRED      += mthumb/march=armv7-m
++
++# ARMv7E-M
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=hard
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=hard
++
++# ARMv8-M Mainline
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=hard
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=hard
++
++# ARMv7-R as well as ARMv7-A and ARMv8-A if aprofile was not specified
++MULTILIB_REQUIRED      += mthumb/march=armv7
++MULTILIB_REQUIRED      += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=hard
++
++
++# Matches
++
++# CPU Matches
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0.small-multiply
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0plus
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0plus.small-multiply
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m1
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m1.small-multiply
++MULTILIB_MATCHES       += march?armv7-m=mcpu?cortex-m3
++MULTILIB_MATCHES       += march?armv7e-m=mcpu?cortex-m4
++MULTILIB_MATCHES       += march?armv7e-m=mcpu?cortex-m7
++MULTILIB_MATCHES       += march?armv8-m.base=mcpu?cortex-m23
++MULTILIB_MATCHES       += march?armv8-m.main=mcpu?cortex-m33
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r4
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r4f
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r5
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r8
++MULTILIB_MATCHES       += march?armv7=mcpu?marvell-pj4
++MULTILIB_MATCHES       += march?armv7=mcpu?generic-armv7-a
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a8
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a9
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a5
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a15
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a12
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a17
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a15.cortex-a7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a17.cortex-a7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a32
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a35
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a57
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a57.cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a72
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a72.cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a73
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a73.cortex-a35
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a73.cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?exynos-m1
++MULTILIB_MATCHES       += march?armv7=mcpu?qdf24xx
++MULTILIB_MATCHES       += march?armv7=mcpu?xgene1
++
++# Arch Matches
++MULTILIB_MATCHES       += march?armv6s-m=march?armv6-m
++MULTILIB_MATCHES       += march?armv8-m.main=march?armv8-m.main+dsp
++MULTILIB_MATCHES       += march?armv7=march?armv7-r
++ifeq (,$(HAS_APROFILE))
++MULTILIB_MATCHES       += march?armv7=march?armv7-a
++MULTILIB_MATCHES       += march?armv7=march?armv7ve
++MULTILIB_MATCHES       += march?armv7=march?armv8-a
++MULTILIB_MATCHES       += march?armv7=march?armv8-a+crc
++MULTILIB_MATCHES       += march?armv7=march?armv8.1-a
++MULTILIB_MATCHES       += march?armv7=march?armv8.1-a+crc
++MULTILIB_MATCHES       += march?armv7=march?armv8.2-a
++MULTILIB_MATCHES       += march?armv7=march?armv8.2-a+fp16
++endif
++
++# FPU matches
++ifeq (,$(HAS_APROFILE))
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?neon
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?neon-fp16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv4
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv4-d16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?neon-vfpv4
++MULTILIB_MATCHES       += mfpu?fpv5-d16=mfpu?fp-armv8
++MULTILIB_MATCHES       += mfpu?fpv5-d16=mfpu?neon-fp-armv8
++MULTILIB_MATCHES       += mfpu?fpv5-d16=mfpu?crypto-neon-fp-armv8
++endif
++
++
++# We map all requests for ARMv7-R or ARMv7-A in ARM mode to Thumb mode and
++# any FPU to VFPv3-d16 if possible.
++MULTILIB_REUSE         += mthumb/march.armv7=march.armv7
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.fpv5-d16/mfloat-abi.hard
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.hard
+--- a/src/gcc/config/arm/thumb1.md
++++ b/src/gcc/config/arm/thumb1.md
+@@ -55,6 +55,10 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic additions in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn_and_split "*thumb1_addsi3"
+   [(set (match_operand:SI          0 "register_operand" "=l,l,l,*rk,*hk,l,k,l,l,l")
+ 	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,k,k,0,l,k")
+@@ -114,8 +118,8 @@
+    (set (match_dup 0)
+ 	(plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]
+   "TARGET_THUMB1
+-   && (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
+-   && (INTVAL (operands[1]) & 3) == 0"
++   && UINTVAL (operands[1]) < 1024
++   && (UINTVAL (operands[1]) & 3) == 0"
+   [(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]
+   ""
+ )
+@@ -131,6 +135,10 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic subtractions in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "thumb1_subsi3_insn"
+   [(set (match_operand:SI           0 "register_operand" "=l")
+ 	(minus:SI (match_operand:SI 1 "register_operand" "l")
+@@ -142,11 +150,11 @@
+    (set_attr "type" "alus_sreg")]
+ )
+ 
+-; Unfortunately with the Thumb the '&'/'0' trick can fails when operands
+-; 1 and 2; are the same, because reload will make operand 0 match
+-; operand 1 without realizing that this conflicts with operand 2.  We fix
+-; this by adding another alternative to match this case, and then `reload'
+-; it ourselves.  This alternative must come first.
++;; Unfortunately on Thumb the '&'/'0' trick can fail when operands
++;; 1 and 2 are the same, because reload will make operand 0 match
++;; operand 1 without realizing that this conflicts with operand 2.  We fix
++;; this by adding another alternative to match this case, and then `reload'
++;; it ourselves.  This alternative must come first.
+ (define_insn "*thumb_mulsi3"
+   [(set (match_operand:SI          0 "register_operand" "=&l,&l,&l")
+ 	(mult:SI (match_operand:SI 1 "register_operand" "%l,*h,0")
+@@ -173,6 +181,10 @@
+    (set_attr "type" "muls")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic bitwise ANDs and NANDs in sync.md and to the logic for bind_old_new
++;; in arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "*thumb1_andsi3_insn"
+   [(set (match_operand:SI         0 "register_operand" "=l")
+ 	(and:SI (match_operand:SI 1 "register_operand" "%0")
+@@ -227,6 +239,10 @@
+    (set_attr "type" "logics_reg")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic inclusive ORs in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "*thumb1_iorsi3_insn"
+   [(set (match_operand:SI         0 "register_operand" "=l")
+ 	(ior:SI (match_operand:SI 1 "register_operand" "%0")
+@@ -237,6 +253,10 @@
+    (set_attr "conds" "set")
+    (set_attr "type" "logics_reg")])
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic exclusive ORs in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "*thumb1_xorsi3_insn"
+   [(set (match_operand:SI         0 "register_operand" "=l")
+ 	(xor:SI (match_operand:SI 1 "register_operand" "%0")
+@@ -590,8 +610,8 @@
+ ;;; ??? The 'i' constraint looks funny, but it should always be replaced by
+ ;;; thumb_reorg with a memory reference.
+ (define_insn "*thumb1_movdi_insn"
+-  [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r")
+-	(match_operand:DI 1 "general_operand"      "l, I,J,>,l,mi,l,*r"))]
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,r,l,>,l, m,*r")
++	(match_operand:DI 1 "general_operand"      "l, I,J,j,>,l,mi,l,*r"))]
+   "TARGET_THUMB1
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))"
+@@ -610,36 +630,41 @@
+       operands[1] = GEN_INT (- INTVAL (operands[1]));
+       return \"movs\\t%Q0, %1\;rsbs\\t%Q0, %Q0, #0\;asrs\\t%R0, %Q0, #31\";
+     case 3:
+-      return \"ldmia\\t%1, {%0, %H0}\";
++      gcc_assert (TARGET_HAVE_MOVT);
++      return \"movw\\t%Q0, %L1\;movs\\tR0, #0\";
+     case 4:
+-      return \"stmia\\t%0, {%1, %H1}\";
++      return \"ldmia\\t%1, {%0, %H0}\";
+     case 5:
+-      return thumb_load_double_from_address (operands);
++      return \"stmia\\t%0, {%1, %H1}\";
+     case 6:
++      return thumb_load_double_from_address (operands);
++    case 7:
+       operands[2] = gen_rtx_MEM (SImode,
+ 			     plus_constant (Pmode, XEXP (operands[0], 0), 4));
+       output_asm_insn (\"str\\t%1, %0\;str\\t%H1, %2\", operands);
+       return \"\";
+-    case 7:
++    case 8:
+       if (REGNO (operands[1]) == REGNO (operands[0]) + 1)
+ 	return \"mov\\t%0, %1\;mov\\t%H0, %H1\";
+       return \"mov\\t%H0, %H1\;mov\\t%0, %1\";
+     }
+   }"
+-  [(set_attr "length" "4,4,6,2,2,6,4,4")
+-   (set_attr "type" "multiple,multiple,multiple,load2,store2,load2,store2,multiple")
+-   (set_attr "pool_range" "*,*,*,*,*,1018,*,*")]
++  [(set_attr "length" "4,4,6,6,2,2,6,4,4")
++   (set_attr "type" "multiple,multiple,multiple,multiple,load2,store2,load2,store2,multiple")
++   (set_attr "arch" "t1,t1,t1,v8mb,t1,t1,t1,t1,t1")
++   (set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")]
+ )
+ 
+ (define_insn "*thumb1_movsi_insn"
+-  [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*l*h*k")
+-	(match_operand:SI 1 "general_operand"      "l, I,J,K,>,l,mi,l,*l*h*k"))]
++  [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,r,l,l,l,>,l, m,*l*h*k")
++	(match_operand:SI 1 "general_operand"      "l, I,j,J,K,>,l,mi,l,*l*h*k"))]
+   "TARGET_THUMB1
+    && (   register_operand (operands[0], SImode)
+        || register_operand (operands[1], SImode))"
+   "@
+    movs	%0, %1
+    movs	%0, %1
++   movw	%0, %1
+    #
+    #
+    ldmia\\t%1, {%0}
+@@ -647,10 +672,11 @@
+    ldr\\t%0, %1
+    str\\t%1, %0
+    mov\\t%0, %1"
+-  [(set_attr "length" "2,2,4,4,2,2,2,2,2")
+-   (set_attr "type" "mov_reg,mov_imm,multiple,multiple,load1,store1,load1,store1,mov_reg")
+-   (set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")
+-   (set_attr "conds" "set,clob,*,*,nocond,nocond,nocond,nocond,nocond")])
++  [(set_attr "length" "2,2,4,4,4,2,2,2,2,2")
++   (set_attr "type" "mov_reg,mov_imm,mov_imm,multiple,multiple,load1,store1,load1,store1,mov_reg")
++   (set_attr "pool_range" "*,*,*,*,*,*,*,1018,*,*")
++   (set_attr "arch" "t1,t1,v8mb,t1,t1,t1,t1,t1,t1,t1")
++   (set_attr "conds" "set,clob,nocond,*,*,nocond,nocond,nocond,nocond,nocond")])
+ 
+ ; Split the load of 64-bit constant into two loads for high and low 32-bit parts respectively
+ ; to see if we can load them in fewer instructions or fewer cycles.
+@@ -687,7 +713,8 @@
+ (define_split
+   [(set (match_operand:SI 0 "register_operand" "")
+ 	(match_operand:SI 1 "const_int_operand" ""))]
+-  "TARGET_THUMB1 && satisfies_constraint_K (operands[1])"
++  "TARGET_THUMB1 && satisfies_constraint_K (operands[1])
++   && !(TARGET_HAVE_MOVT && satisfies_constraint_j (operands[1]))"
+   [(set (match_dup 2) (match_dup 1))
+    (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))]
+   "
+@@ -714,7 +741,8 @@
+ (define_split
+   [(set (match_operand:SI 0 "register_operand" "")
+ 	(match_operand:SI 1 "const_int_operand" ""))]
+-  "TARGET_THUMB1 && satisfies_constraint_Pe (operands[1])"
++  "TARGET_THUMB1 && satisfies_constraint_Pe (operands[1])
++   && !(TARGET_HAVE_MOVT && satisfies_constraint_j (operands[1]))"
+   [(set (match_dup 2) (match_dup 1))
+    (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
+   "
+@@ -726,8 +754,8 @@
+ )
+ 
+ (define_insn "*thumb1_movhi_insn"
+-  [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l")
+-	(match_operand:HI 1 "general_operand"       "l,m,l,k*h,*r,I"))]
++  [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l,r")
++	(match_operand:HI 1 "general_operand"       "l,m,l,k*h,*r,I,n"))]
+   "TARGET_THUMB1
+    && (   register_operand (operands[0], HImode)
+        || register_operand (operands[1], HImode))"
+@@ -739,6 +767,8 @@
+     case 3: return \"mov	%0, %1\";
+     case 4: return \"mov	%0, %1\";
+     case 5: return \"movs	%0, %1\";
++    case 6: gcc_assert (TARGET_HAVE_MOVT);
++	    return \"movw	%0, %L1\";
+     default: gcc_unreachable ();
+     case 1:
+       /* The stack pointer can end up being taken as an index register.
+@@ -758,9 +788,10 @@
+ 	}
+       return \"ldrh	%0, %1\";
+     }"
+-  [(set_attr "length" "2,4,2,2,2,2")
+-   (set_attr "type" "alus_imm,load1,store1,mov_reg,mov_reg,mov_imm")
+-   (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
++  [(set_attr "length" "2,4,2,2,2,2,4")
++   (set_attr "type" "alus_imm,load1,store1,mov_reg,mov_reg,mov_imm,mov_imm")
++   (set_attr "arch" "t1,t1,t1,t1,t1,t1,v8mb")
++   (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob,nocond")])
+ 
+ (define_expand "thumb_movhi_clobber"
+   [(set (match_operand:HI     0 "memory_operand"   "")
+@@ -963,6 +994,94 @@
+   DONE;
+ })
+ 
++;; A pattern for the CB(N)Z instruction added in ARMv8-M Baseline profile,
++;; adapted from cbranchsi4_insn.  Modifying cbranchsi4_insn instead leads to
++;; code generation difference for ARMv6-M because the minimum length of the
++;; instruction becomes 2 even for ARMv6-M due to a limitation in genattrtab's
++;; handling of PC in the length condition.
++(define_insn "thumb1_cbz"
++  [(set (pc) (if_then_else
++	      (match_operator 0 "equality_operator"
++	       [(match_operand:SI 1 "s_register_operand" "l")
++		(const_int 0)])
++	      (label_ref (match_operand 2 "" ""))
++	      (pc)))]
++  "TARGET_THUMB1 && TARGET_HAVE_CBZ"
++{
++  if (get_attr_length (insn) == 2)
++    {
++      if (GET_CODE (operands[0]) == EQ)
++	return "cbz\t%1, %l2";
++      else
++	return "cbnz\t%1, %l2";
++    }
++  else
++    {
++      rtx t = cfun->machine->thumb1_cc_insn;
++      if (t != NULL_RTX)
++	{
++	  if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1])
++	      || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2]))
++	    t = NULL_RTX;
++	  if (cfun->machine->thumb1_cc_mode == CC_NOOVmode)
++	    {
++	      if (!noov_comparison_operator (operands[0], VOIDmode))
++		t = NULL_RTX;
++	    }
++	  else if (cfun->machine->thumb1_cc_mode != CCmode)
++	    t = NULL_RTX;
++	}
++      if (t == NULL_RTX)
++	{
++	  output_asm_insn ("cmp\t%1, #0", operands);
++	  cfun->machine->thumb1_cc_insn = insn;
++	  cfun->machine->thumb1_cc_op0 = operands[1];
++	  cfun->machine->thumb1_cc_op1 = operands[2];
++	  cfun->machine->thumb1_cc_mode = CCmode;
++	}
++      else
++	/* Ensure we emit the right type of condition code on the jump.  */
++	XEXP (operands[0], 0) = gen_rtx_REG (cfun->machine->thumb1_cc_mode,
++					     CC_REGNUM);
++
++      switch (get_attr_length (insn))
++	{
++	case 4:  return "b%d0\t%l2";
++	case 6:  return "b%D0\t.LCB%=;b\t%l2\t%@long jump\n.LCB%=:";
++	case 8:  return "b%D0\t.LCB%=;bl\t%l2\t%@far jump\n.LCB%=:";
++	default: gcc_unreachable ();
++	}
++    }
++}
++  [(set (attr "far_jump")
++	(if_then_else
++	    (eq_attr "length" "8")
++	    (const_string "yes")
++	    (const_string "no")))
++   (set (attr "length")
++	(if_then_else
++	    (and (ge (minus (match_dup 2) (pc)) (const_int 2))
++		 (le (minus (match_dup 2) (pc)) (const_int 128)))
++	    (const_int 2)
++	    (if_then_else
++		(and (ge (minus (match_dup 2) (pc)) (const_int -250))
++		     (le (minus (match_dup 2) (pc)) (const_int 256)))
++		(const_int 4)
++		(if_then_else
++		    (and (ge (minus (match_dup 2) (pc)) (const_int -2040))
++			 (le (minus (match_dup 2) (pc)) (const_int 2048)))
++		    (const_int 6)
++		    (const_int 8)))))
++   (set (attr "type")
++	(if_then_else
++	    (eq_attr "length" "2")
++	    (const_string "branch")
++	    (const_string "multiple")))]
++)
++
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic compare_and_swap splitters in sync.md.  These must be at least as
++;; strict as the constraints here and aim to be as permissive.
+ (define_insn "cbranchsi4_insn"
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "arm_comparison_operator"
+@@ -1024,6 +1143,9 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic compare_and_swap splitters in sync.md.  These must be at least as
++;; strict as the constraints here and aim to be as permissive.
+ (define_insn "cbranchsi4_scratch"
+   [(set (pc) (if_then_else
+ 	      (match_operator 4 "arm_comparison_operator"
+@@ -1609,6 +1731,19 @@
+    (set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_reg_thumb1_v5"
++  [(call (unspec:SI [(mem:SI (match_operand:SI 0 "register_operand" "l*r"))]
++		    UNSPEC_NONSECURE_MEM)
++	 (match_operand 1 "" ""))
++   (use (match_operand 2 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 0))]
++  "TARGET_THUMB1 && use_cmse && !SIBLING_CALL_P (insn)"
++  "bl\\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*call_reg_thumb1"
+   [(call (mem:SI (match_operand:SI 0 "register_operand" "l*r"))
+ 	 (match_operand 1 "" ""))
+@@ -1641,6 +1776,21 @@
+    (set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_value_reg_thumb1_v5"
++  [(set (match_operand 0 "" "")
++	(call (unspec:SI
++	       [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))]
++	       UNSPEC_NONSECURE_MEM)
++	      (match_operand 2 "" "")))
++   (use (match_operand 3 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 1))]
++  "TARGET_THUMB1 && use_cmse"
++  "bl\\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*call_value_reg_thumb1"
+   [(set (match_operand 0 "" "")
+ 	(call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
+@@ -1747,8 +1897,13 @@
+   "*
+     return thumb1_unexpanded_epilogue ();
+   "
+-  ; Length is absolute worst case
+-  [(set_attr "length" "44")
++  ; Length is absolute worst case, when using CMSE and if this is an entry
++  ; function an extra 4 (MSR) bytes will be added.
++  [(set (attr "length")
++	(if_then_else
++	 (match_test "IS_CMSE_ENTRY (arm_current_func_type ())")
++	 (const_int 48)
++	 (const_int 44)))
+    (set_attr "type" "block")
+    ;; We don't clobber the conditions, but the potential length of this
+    ;; operation is sufficient to make conditionalizing the sequence
+--- a/src/gcc/config/arm/thumb2.md
++++ b/src/gcc/config/arm/thumb2.md
+@@ -125,32 +125,6 @@
+    (set_attr "type" "multiple")]
+ )
+ 
+-;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
+-(define_insn_and_split "*thumb2_negdi2"
+-  [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
+-	(neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
+-   (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_THUMB2"
+-  "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1
+-  "&& reload_completed"
+-  [(parallel [(set (reg:CC CC_REGNUM)
+-		   (compare:CC (const_int 0) (match_dup 1)))
+-	      (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
+-   (set (match_dup 2) (minus:SI (minus:SI (match_dup 3)
+-                                          (ashift:SI (match_dup 3)
+-                                                     (const_int 1)))
+-                                (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+-  {
+-    operands[2] = gen_highpart (SImode, operands[0]);
+-    operands[0] = gen_lowpart (SImode, operands[0]);
+-    operands[3] = gen_highpart (SImode, operands[1]);
+-    operands[1] = gen_lowpart (SImode, operands[1]);
+-  }
+-  [(set_attr "conds" "clob")
+-   (set_attr "length" "8")
+-   (set_attr "type" "multiple")]
+-)
+-
+ (define_insn_and_split "*thumb2_abssi2"
+   [(set (match_operand:SI         0 "s_register_operand" "=&r,l,r")
+ 	(abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
+@@ -278,8 +252,7 @@
+ (define_insn "*thumb2_movsi_insn"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
+ 	(match_operand:SI 1 "general_operand"	   "rk,I,Py,K,j,mi,*mi,l,*hk"))]
+-  "TARGET_THUMB2 && ! TARGET_IWMMXT
+-   && !(TARGET_HARD_FLOAT && TARGET_VFP)
++  "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], SImode)
+        || register_operand (operands[1], SImode))"
+   "@
+@@ -581,6 +554,19 @@
+   [(set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_reg_thumb2"
++  [(call (unspec:SI [(mem:SI (match_operand:SI 0 "s_register_operand" "r"))]
++		    UNSPEC_NONSECURE_MEM)
++	 (match_operand 1 "" ""))
++   (use (match_operand 2 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 0))]
++  "TARGET_THUMB2 && use_cmse"
++  "bl\\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*call_value_reg_thumb2"
+   [(set (match_operand 0 "" "")
+ 	(call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
+@@ -592,6 +578,21 @@
+   [(set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_value_reg_thumb2"
++  [(set (match_operand 0 "" "")
++	(call
++	 (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))]
++		    UNSPEC_NONSECURE_MEM)
++	 (match_operand 2 "" "")))
++   (use (match_operand 3 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 1))]
++  "TARGET_THUMB2 && use_cmse"
++  "bl\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*thumb2_indirect_jump"
+   [(set (pc)
+ 	(match_operand:SI 0 "register_operand" "l*r"))]
+@@ -1115,12 +1116,31 @@
+ 
+ (define_insn "*thumb2_return"
+   [(simple_return)]
+-  "TARGET_THUMB2"
++  "TARGET_THUMB2 && !IS_CMSE_ENTRY (arm_current_func_type ())"
+   "* return output_return_instruction (const_true_rtx, true, false, true);"
+   [(set_attr "type" "branch")
+    (set_attr "length" "4")]
+ )
+ 
++(define_insn "*thumb2_cmse_entry_return"
++  [(simple_return)]
++  "TARGET_THUMB2 && IS_CMSE_ENTRY (arm_current_func_type ())"
++  "* return output_return_instruction (const_true_rtx, true, false, true);"
++  [(set_attr "type" "branch")
++   ; This is a return from a cmse_nonsecure_entry function so code will be
++   ; added to clear the APSR and potentially the FPSCR if VFP is available, so
++   ; we adapt the length accordingly.
++   (set (attr "length")
++     (if_then_else (match_test "TARGET_HARD_FLOAT")
++      (const_int 12)
++      (const_int 8)))
++   ; We do not support predicate execution of returns from cmse_nonsecure_entry
++   ; functions because we need to clear the APSR.  Since predicable has to be
++   ; a constant, we had to duplicate the thumb2_return pattern for CMSE entry
++   ; functions.
++   (set_attr "predicable" "no")]
++)
++
+ (define_insn_and_split "thumb2_eh_return"
+   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
+ 		    VUNSPEC_EH_RETURN)
+--- a/src/gcc/config/arm/types.md
++++ b/src/gcc/config/arm/types.md
+@@ -51,6 +51,7 @@
+ ; alus_shift_imm     as alu_shift_imm, setting condition flags.
+ ; alus_shift_reg     as alu_shift_reg, setting condition flags.
+ ; bfm                bitfield move operation.
++; bfx                bitfield extract operation.
+ ; block              blockage insn, this blocks all functional units.
+ ; branch             branch.
+ ; call               subroutine call.
+@@ -557,6 +558,7 @@
+   alus_shift_imm,\
+   alus_shift_reg,\
+   bfm,\
++  bfx,\
+   block,\
+   branch,\
+   call,\
+--- a/src/gcc/config/arm/unspecs.md
++++ b/src/gcc/config/arm/unspecs.md
+@@ -84,6 +84,8 @@
+   UNSPEC_VRINTA         ; Represent a float to integral float rounding
+                         ; towards nearest, ties away from zero.
+   UNSPEC_PROBE_STACK    ; Probe stack memory reference
++  UNSPEC_NONSECURE_MEM	; Represent non-secure memory in ARMv8-M with
++			; security extension
+ ])
+ 
+ (define_c_enum "unspec" [
+@@ -191,6 +193,8 @@
+   UNSPEC_VBSL
+   UNSPEC_VCAGE
+   UNSPEC_VCAGT
++  UNSPEC_VCALE
++  UNSPEC_VCALT
+   UNSPEC_VCEQ
+   UNSPEC_VCGE
+   UNSPEC_VCGEU
+@@ -203,6 +207,20 @@
+   UNSPEC_VCVT_U
+   UNSPEC_VCVT_S_N
+   UNSPEC_VCVT_U_N
++  UNSPEC_VCVT_HF_S_N
++  UNSPEC_VCVT_HF_U_N
++  UNSPEC_VCVT_SI_S_N
++  UNSPEC_VCVT_SI_U_N
++  UNSPEC_VCVTH_S
++  UNSPEC_VCVTH_U
++  UNSPEC_VCVTA_S
++  UNSPEC_VCVTA_U
++  UNSPEC_VCVTM_S
++  UNSPEC_VCVTM_U
++  UNSPEC_VCVTN_S
++  UNSPEC_VCVTN_U
++  UNSPEC_VCVTP_S
++  UNSPEC_VCVTP_U
+   UNSPEC_VEXT
+   UNSPEC_VHADD_S
+   UNSPEC_VHADD_U
+@@ -244,6 +262,8 @@
+   UNSPEC_VMLSL_S_LANE
+   UNSPEC_VMLSL_U_LANE
+   UNSPEC_VMLSL_LANE
++  UNSPEC_VFMA_LANE
++  UNSPEC_VFMS_LANE
+   UNSPEC_VMOVL_S
+   UNSPEC_VMOVL_U
+   UNSPEC_VMOVN
+@@ -365,5 +385,11 @@
+   UNSPEC_NVRINTN
+   UNSPEC_VQRDMLAH
+   UNSPEC_VQRDMLSH
++  UNSPEC_VRND
++  UNSPEC_VRNDA
++  UNSPEC_VRNDI
++  UNSPEC_VRNDM
++  UNSPEC_VRNDN
++  UNSPEC_VRNDP
++  UNSPEC_VRNDX
+ ])
+-
+--- a/src/gcc/config/arm/vec-common.md
++++ b/src/gcc/config/arm/vec-common.md
+@@ -124,6 +124,20 @@
+     FAIL;
+ })
+ 
++(define_expand "vec_perm_const<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")
++   (match_operand:<V_cmp_result> 3)]
++  "TARGET_NEON"
++{
++  if (arm_expand_vec_perm_const (operands[0], operands[1],
++				 operands[2], operands[3]))
++    DONE;
++  else
++    FAIL;
++})
++
+ (define_expand "vec_perm<mode>"
+   [(match_operand:VE 0 "s_register_operand" "")
+    (match_operand:VE 1 "s_register_operand" "")
+--- a/src/gcc/config/arm/vfp.md
++++ b/src/gcc/config/arm/vfp.md
+@@ -18,13 +18,206 @@
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.  */
+ 
++;; Patterns for HI moves which provide more data transfer instructions when VFP
++;; support is enabled.
++(define_insn "*arm_movhi_vfp"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=rk,  r, r, m, r, *t,  r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rIk, K, n, r, mi, r, *t, *t"))]
++ "TARGET_ARM && TARGET_HARD_FLOAT
++  && !TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 1:
++      return "mvn%?\t%0, #%B1\t%@ movhi";
++    case 2:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 3:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 4:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 5:
++    case 6:
++      return "vmov%?\t%0, %1\t%@ int";
++    case 7:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable" "yes")
++  (set_attr_alternative "type"
++   [(if_then_else
++     (match_operand 1 "const_int_operand" "")
++     (const_string "mov_imm")
++     (const_string "mov_reg"))
++    (const_string "mvn_imm")
++    (const_string "mov_imm")
++    (const_string "store1")
++    (const_string "load1")
++    (const_string "f_mcr")
++    (const_string "f_mrc")
++    (const_string "fmov")])
++  (set_attr "arch" "*, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, 256, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, 244, *, *, *")
++  (set_attr "length" "4")]
++)
++
++(define_insn "*thumb2_movhi_vfp"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=rk, r, l, r, m, r, *t, r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rk, I, Py, n, r, m, r, *t, *t"))]
++ "TARGET_THUMB2 && TARGET_HARD_FLOAT
++  && !TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++    case 1:
++    case 2:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 3:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 4:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 5:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 6:
++    case 7:
++      return "vmov%?\t%0, %1\t%@ int";
++    case 8:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable" "yes")
++  (set_attr "predicable_short_it"
++   "yes, no, yes, no, no, no, no, no, no")
++  (set_attr "type"
++   "mov_reg, mov_imm, mov_imm, mov_imm, store1, load1,\
++    f_mcr, f_mrc, fmov")
++  (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *")
++  (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4")]
++)
++
++;; Patterns for HI moves which provide more data transfer instructions when FP16
++;; instructions are available.
++(define_insn "*arm_movhi_fp16"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=r,  r, r, m, r, *t,  r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rIk, K, n, r, mi, r, *t, *t"))]
++ "TARGET_ARM && TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 1:
++      return "mvn%?\t%0, #%B1\t%@ movhi";
++    case 2:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 3:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 4:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 5:
++    case 6:
++      return "vmov.f16\t%0, %1\t%@ int";
++    case 7:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable" "yes, yes, yes, yes, yes, no, no, yes")
++  (set_attr_alternative "type"
++   [(if_then_else
++     (match_operand 1 "const_int_operand" "")
++     (const_string "mov_imm")
++     (const_string "mov_reg"))
++    (const_string "mvn_imm")
++    (const_string "mov_imm")
++    (const_string "store1")
++    (const_string "load1")
++    (const_string "f_mcr")
++    (const_string "f_mrc")
++    (const_string "fmov")])
++  (set_attr "arch" "*, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, 256, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, 244, *, *, *")
++  (set_attr "length" "4")]
++)
++
++(define_insn "*thumb2_movhi_fp16"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=rk, r, l, r, m, r, *t, r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rk, I, Py, n, r, m, r, *t, *t"))]
++ "TARGET_THUMB2 && TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++    case 1:
++    case 2:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 3:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 4:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 5:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 6:
++    case 7:
++      return "vmov.f16\t%0, %1\t%@ int";
++    case 8:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable"
++   "yes, yes, yes, yes, yes, yes, no, no, yes")
++  (set_attr "predicable_short_it"
++   "yes, no, yes, no, no, no, no, no, no")
++  (set_attr "type"
++   "mov_reg, mov_imm, mov_imm, mov_imm, store1, load1,\
++    f_mcr, f_mrc, fmov")
++  (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *")
++  (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4")]
++)
++
+ ;; SImode moves
+ ;; ??? For now do not allow loading constants into vfp regs.  This causes
+ ;; problems because small constants get converted into adds.
+ (define_insn "*arm_movsi_vfp"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
+       (match_operand:SI 1 "general_operand"	   "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
+-  "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
++  "TARGET_ARM && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SImode)
+        || s_register_operand (operands[1], SImode))"
+   "*
+@@ -53,7 +246,8 @@
+     }
+   "
+   [(set_attr "predicable" "yes")
+-   (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
++   (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,
++		     f_mcr,f_mrc,fmov,f_loads,f_stores")
+    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
+    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
+ )
+@@ -66,7 +260,7 @@
+ (define_insn "*thumb2_movsi_vfp"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t,  *Uv")
+ 	(match_operand:SI 1 "general_operand"	   "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
+-  "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SImode)
+        || s_register_operand (operands[1], SImode))"
+   "*
+@@ -112,7 +306,7 @@
+ (define_insn "*movdi_vfp"
+   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
+        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
++  "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune != cortexa8
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))
+    && !(TARGET_NEON && CONST_INT_P (operands[1])
+@@ -163,7 +357,7 @@
+ (define_insn "*movdi_vfp_cortexa8"
+   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
+        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
++  "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune == cortexa8
+     && (   register_operand (operands[0], DImode)
+         || register_operand (operands[1], DImode))
+     && !(TARGET_NEON && CONST_INT_P (operands[1])
+@@ -211,10 +405,87 @@
+  )
+ 
+ ;; HFmode moves
++
++(define_insn "*movhf_vfp_fp16"
++  [(set (match_operand:HF 0 "nonimmediate_operand"
++			  "= r,m,t,r,t,r,t,t,Um,r")
++	(match_operand:HF 1 "general_operand"
++			  "  m,r,t,r,r,t,Dv,Um,t,F"))]
++  "TARGET_32BIT
++   && TARGET_VFP_FP16INST
++   && (s_register_operand (operands[0], HFmode)
++       || s_register_operand (operands[1], HFmode))"
++ {
++  switch (which_alternative)
++    {
++    case 0: /* ARM register from memory.  */
++      return \"ldrh%?\\t%0, %1\\t%@ __fp16\";
++    case 1: /* Memory from ARM register.  */
++      return \"strh%?\\t%1, %0\\t%@ __fp16\";
++    case 2: /* S register from S register.  */
++      return \"vmov\\t%0, %1\t%@ __fp16\";
++    case 3: /* ARM register from ARM register.  */
++      return \"mov%?\\t%0, %1\\t%@ __fp16\";
++    case 4: /* S register from ARM register.  */
++    case 5: /* ARM register from S register.  */
++    case 6: /* S register from immediate.  */
++      return \"vmov.f16\\t%0, %1\t%@ __fp16\";
++    case 7: /* S register from memory.  */
++      return \"vld1.16\\t{%z0}, %A1\";
++    case 8: /* Memory from S register.  */
++      return \"vst1.16\\t{%z1}, %A0\";
++    case 9: /* ARM register from constant.  */
++      {
++	long bits;
++	rtx ops[4];
++
++	bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]),
++			       HFmode);
++	ops[0] = operands[0];
++	ops[1] = GEN_INT (bits);
++	ops[2] = GEN_INT (bits & 0xff00);
++	ops[3] = GEN_INT (bits & 0x00ff);
++
++	if (arm_arch_thumb2)
++	  output_asm_insn (\"movw\\t%0, %1\", ops);
++	else
++	  output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
++	return \"\";
++       }
++    default:
++      gcc_unreachable ();
++    }
++ }
++  [(set_attr "predicable" "yes, yes, no, yes, no, no, no, no, no, no")
++   (set_attr "predicable_short_it" "no, no, no, yes,\
++				    no, no, no, no,\
++				    no, no")
++   (set_attr_alternative "type"
++    [(const_string "load1") (const_string "store1")
++     (const_string "fmov") (const_string "mov_reg")
++     (const_string "f_mcr") (const_string "f_mrc")
++     (const_string "fconsts") (const_string "neon_load1_1reg")
++     (const_string "neon_store1_1reg")
++     (if_then_else (match_test "arm_arch_thumb2")
++      (const_string "mov_imm")
++      (const_string "multiple"))])
++   (set_attr_alternative "length"
++    [(const_int 4) (const_int 4)
++     (const_int 4) (const_int 4)
++     (const_int 4) (const_int 4)
++     (const_int 4) (const_int 4)
++     (const_int 4)
++     (if_then_else (match_test "arm_arch_thumb2")
++      (const_int 4)
++      (const_int 8))])]
++)
++
+ (define_insn "*movhf_vfp_neon"
+   [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
+ 	(match_operand:HF 1 "general_operand"	   " Um, t,m,r,t,r,r,t,F"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
++  "TARGET_32BIT
++   && TARGET_HARD_FLOAT && TARGET_NEON_FP16
++   && !TARGET_VFP_FP16INST
+    && (   s_register_operand (operands[0], HFmode)
+        || s_register_operand (operands[1], HFmode))"
+   "*
+@@ -268,7 +539,10 @@
+ (define_insn "*movhf_vfp"
+   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
+ 	(match_operand:HF 1 "general_operand"	   " m,r,t,r,r,t,F"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
++  "TARGET_32BIT
++   && TARGET_HARD_FLOAT
++   && !TARGET_NEON_FP16
++   && !TARGET_VFP_FP16INST
+    && (   s_register_operand (operands[0], HFmode)
+        || s_register_operand (operands[1], HFmode))"
+   "*
+@@ -321,7 +595,7 @@
+ (define_insn "*movsf_vfp"
+   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
+         (match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
++  "TARGET_ARM && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SFmode)
+        || s_register_operand (operands[1], SFmode))"
+   "*
+@@ -357,7 +631,7 @@
+ (define_insn "*thumb2_movsf_vfp"
+   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
+ 	(match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
+-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SFmode)
+        || s_register_operand (operands[1], SFmode))"
+   "*
+@@ -394,9 +668,9 @@
+ ;; DFmode moves
+ 
+ (define_insn "*movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r, m,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w  ,Uv,r, m,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,G,UvF,w ,mF,r,w,r"))]
++  "TARGET_ARM && TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], DFmode)
+        || register_operand (operands[1], DFmode))"
+   "*
+@@ -410,40 +684,44 @@
+       case 2:
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+         return \"vmov%?.f64\\t%P0, %1\";
+-      case 3: case 4:
++      case 3:
++	gcc_assert (TARGET_VFP_DOUBLE);
++	return \"vmov.i64\\t%P0, #0\\t%@ float\";
++      case 4: case 5:
+ 	return output_move_vfp (operands);
+-      case 5: case 6:
++      case 6: case 7:
+ 	return output_move_double (operands, true, NULL);
+-      case 7:
++      case 8:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
+ 	else
+ 	  return \"vmov%?.f64\\t%P0, %P1\";
+-      case 8:
++      case 9:
+         return \"#\";
+       default:
+ 	gcc_unreachable ();
+       }
+     }
+   "
+-  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
++  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,f_stored,\
+                      load2,store2,ffarithd,multiple")
+-   (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
+-			       (eq_attr "alternative" "7")
++   (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8)
++			       (eq_attr "alternative" "8")
+ 				(if_then_else
+ 				 (match_test "TARGET_VFP_SINGLE")
+ 				 (const_int 8)
+ 				 (const_int 4))]
+ 			      (const_int 4)))
+-   (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
+-   (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
++   (set_attr "predicable" "yes,yes,yes,no,yes,yes,yes,yes,yes,yes")
++   (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*")
++   (set_attr "neg_pool_range" "*,*,*,*,1004,*,1004,*,*,*")
++   (set_attr "arch" "any,any,any,neon,any,any,any,any,any,any")]
+ )
+ 
+ (define_insn "*thumb2_movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r ,m,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,UvF,w, mF,r, w,r"))]
+-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w  ,Uv,r ,m,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,G,UvF,w, mF,r, w,r"))]
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], DFmode)
+        || register_operand (operands[1], DFmode))"
+   "*
+@@ -457,11 +735,14 @@
+       case 2:
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+ 	return \"vmov%?.f64\\t%P0, %1\";
+-      case 3: case 4:
++      case 3:
++	gcc_assert (TARGET_VFP_DOUBLE);
++	return \"vmov.i64\\t%P0, #0\\t%@ float\";
++      case 4: case 5:
+ 	return output_move_vfp (operands);
+-      case 5: case 6: case 8:
++      case 6: case 7: case 9:
+ 	return output_move_double (operands, true, NULL);
+-      case 7:
++      case 8:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
+ 	else
+@@ -471,17 +752,18 @@
+       }
+     }
+   "
+-  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
++  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,\
+                      f_stored,load2,store2,ffarithd,multiple")
+-   (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
+-			       (eq_attr "alternative" "7")
++   (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8)
++			       (eq_attr "alternative" "8")
+ 				(if_then_else
+ 				 (match_test "TARGET_VFP_SINGLE")
+ 				 (const_int 8)
+ 				 (const_int 4))]
+ 			      (const_int 4)))
+-   (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*")
+-   (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
++   (set_attr "pool_range" "*,*,*,*,1018,*,4094,*,*,*")
++   (set_attr "neg_pool_range" "*,*,*,*,1008,*,0,*,*,*")
++   (set_attr "arch" "any,any,any,neon,any,any,any,any,any,any")]
+ )
+ 
+ 
+@@ -494,7 +776,7 @@
+ 	    [(match_operand 4 "cc_register" "") (const_int 0)])
+ 	  (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
+ 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_ARM && TARGET_HARD_FLOAT"
+   "@
+    vmov%D3.f32\\t%0, %2
+    vmov%d3.f32\\t%0, %1
+@@ -517,7 +799,7 @@
+ 	    [(match_operand 4 "cc_register" "") (const_int 0)])
+ 	  (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
+ 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
+-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT && !arm_restrict_it"
+   "@
+    it\\t%D3\;vmov%D3.f32\\t%0, %2
+    it\\t%d3\;vmov%d3.f32\\t%0, %1
+@@ -585,7 +867,7 @@
+ (define_insn "*abssf2_vfp"
+   [(set (match_operand:SF	  0 "s_register_operand" "=t")
+ 	(abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vabs%?.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -605,7 +887,7 @@
+ (define_insn "*negsf2_vfp"
+   [(set (match_operand:SF	  0 "s_register_operand" "=t,?r")
+ 	(neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "@
+    vneg%?.f32\\t%0, %1
+    eor%?\\t%0, %1, #-2147483648"
+@@ -661,14 +943,68 @@
+    (set_attr "type" "ffarithd")]
+ )
+ 
++;; ABS and NEG for FP16.
++(define_insn "<absneg_str>hf2"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++    (ABSNEG:HF (match_operand:HF 1 "s_register_operand" "w")))]
++ "TARGET_VFP_FP16INST"
++ "v<absneg_str>.f16\t%0, %1"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "ffariths")]
++)
++
++(define_expand "neon_vabshf"
++ [(set
++   (match_operand:HF 0 "s_register_operand")
++   (abs:HF (match_operand:HF 1 "s_register_operand")))]
++ "TARGET_VFP_FP16INST"
++{
++  emit_insn (gen_abshf2 (operands[0], operands[1]));
++  DONE;
++})
++
++;; VRND for FP16.
++(define_insn "neon_v<fp16_rnd_str>hf"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++    (unspec:HF
++     [(match_operand:HF 1 "s_register_operand" "w")]
++     FP16_RND))]
++ "TARGET_VFP_FP16INST"
++ "<fp16_rnd_insn>.f16\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "neon_fp_round_s")]
++)
++
++(define_insn "neon_vrndihf"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++    (unspec:HF
++     [(match_operand:HF 1 "s_register_operand" "w")]
++     UNSPEC_VRNDI))]
++  "TARGET_VFP_FP16INST"
++  "vrintr.f16\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "neon_fp_round_s")]
++)
+ 
+ ;; Arithmetic insns
+ 
++(define_insn "addhf3"
++  [(set
++    (match_operand:HF 0 "s_register_operand" "=w")
++    (plus:HF
++     (match_operand:HF 1 "s_register_operand" "w")
++     (match_operand:HF 2 "s_register_operand" "w")))]
++ "TARGET_VFP_FP16INST"
++ "vadd.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fadds")]
++)
++
+ (define_insn "*addsf3_vfp"
+   [(set (match_operand:SF	   0 "s_register_operand" "=t")
+ 	(plus:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		 (match_operand:SF 2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vadd%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -686,12 +1022,23 @@
+    (set_attr "type" "faddd")]
+ )
+ 
++(define_insn "subhf3"
++ [(set
++   (match_operand:HF 0 "s_register_operand" "=w")
++   (minus:HF
++    (match_operand:HF 1 "s_register_operand" "w")
++    (match_operand:HF 2 "s_register_operand" "w")))]
++ "TARGET_VFP_FP16INST"
++ "vsub.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fadds")]
++)
+ 
+ (define_insn "*subsf3_vfp"
+   [(set (match_operand:SF	    0 "s_register_operand" "=t")
+ 	(minus:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		  (match_operand:SF 2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vsub%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -712,6 +1059,19 @@
+ 
+ ;; Division insns
+ 
++;; FP16 Division.
++(define_insn "divhf3"
++  [(set
++    (match_operand:HF	   0 "s_register_operand" "=w")
++    (div:HF
++     (match_operand:HF 1 "s_register_operand" "w")
++     (match_operand:HF 2 "s_register_operand" "w")))]
++  "TARGET_VFP_FP16INST"
++  "vdiv.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fdivs")]
++)
++
+ ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
+ ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
+ ; earlier.
+@@ -719,7 +1079,7 @@
+   [(set (match_operand:SF	  0 "s_register_operand" "=&t,t")
+ 	(div:SF (match_operand:SF 1 "s_register_operand" "t,t")
+ 		(match_operand:SF 2 "s_register_operand" "t,t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vdiv%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -742,11 +1102,22 @@
+ 
+ ;; Multiplication insns
+ 
++(define_insn "mulhf3"
++ [(set
++   (match_operand:HF 0 "s_register_operand" "=w")
++   (mult:HF (match_operand:HF 1 "s_register_operand" "w")
++	    (match_operand:HF 2 "s_register_operand" "w")))]
++  "TARGET_VFP_FP16INST"
++  "vmul.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmuls")]
++)
++
+ (define_insn "*mulsf3_vfp"
+   [(set (match_operand:SF	   0 "s_register_operand" "=t")
+ 	(mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		 (match_operand:SF 2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmul%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -764,11 +1135,31 @@
+    (set_attr "type" "fmuld")]
+ )
+ 
++(define_insn "*mulsf3neghf_vfp"
++  [(set (match_operand:HF		   0 "s_register_operand" "=t")
++	(mult:HF (neg:HF (match_operand:HF 1 "s_register_operand" "t"))
++		 (match_operand:HF	   2 "s_register_operand" "t")))]
++  "TARGET_VFP_FP16INST && !flag_rounding_math"
++  "vnmul.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmuls")]
++)
++
++(define_insn "*negmulhf3_vfp"
++  [(set (match_operand:HF		   0 "s_register_operand" "=t")
++	(neg:HF (mult:HF (match_operand:HF 1 "s_register_operand" "t")
++		 (match_operand:HF	   2 "s_register_operand" "t"))))]
++  "TARGET_VFP_FP16INST"
++  "vnmul.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmuls")]
++)
++
+ (define_insn "*mulsf3negsf_vfp"
+   [(set (match_operand:SF		   0 "s_register_operand" "=t")
+ 	(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
+ 		 (match_operand:SF	   2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && !flag_rounding_math"
++  "TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math"
+   "vnmul%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -779,7 +1170,7 @@
+   [(set (match_operand:SF		   0 "s_register_operand" "=t")
+ 	(neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		 (match_operand:SF	   2 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vnmul%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -813,12 +1204,24 @@
+ ;; Multiply-accumulate insns
+ 
+ ;; 0 = 1 * 2 + 0
++(define_insn "*mulsf3addhf_vfp"
++ [(set (match_operand:HF 0 "s_register_operand" "=t")
++       (plus:HF
++	(mult:HF (match_operand:HF 2 "s_register_operand" "t")
++		 (match_operand:HF 3 "s_register_operand" "t"))
++	(match_operand:HF 1 "s_register_operand" "0")))]
++  "TARGET_VFP_FP16INST"
++  "vmla.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3addsf_vfp"
+   [(set (match_operand:SF		    0 "s_register_operand" "=t")
+ 	(plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
+ 			  (match_operand:SF 3 "s_register_operand" "t"))
+ 		 (match_operand:SF	    1 "s_register_operand" "0")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmla%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -838,12 +1241,23 @@
+ )
+ 
+ ;; 0 = 1 * 2 - 0
++(define_insn "*mulhf3subhf_vfp"
++  [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(minus:HF (mult:HF (match_operand:HF 2 "s_register_operand" "t")
++			   (match_operand:HF 3 "s_register_operand" "t"))
++		  (match_operand:HF 1 "s_register_operand" "0")))]
++  "TARGET_VFP_FP16INST"
++  "vnmls.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3subsf_vfp"
+   [(set (match_operand:SF		     0 "s_register_operand" "=t")
+ 	(minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
+ 			   (match_operand:SF 3 "s_register_operand" "t"))
+ 		  (match_operand:SF	     1 "s_register_operand" "0")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vnmls%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -863,12 +1277,23 @@
+ )
+ 
+ ;; 0 = -(1 * 2) + 0
++(define_insn "*mulhf3neghfaddhf_vfp"
++  [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(minus:HF (match_operand:HF 1 "s_register_operand" "0")
++		  (mult:HF (match_operand:HF 2 "s_register_operand" "t")
++			   (match_operand:HF 3 "s_register_operand" "t"))))]
++  "TARGET_VFP_FP16INST"
++  "vmls.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3negsfaddsf_vfp"
+   [(set (match_operand:SF		     0 "s_register_operand" "=t")
+ 	(minus:SF (match_operand:SF	     1 "s_register_operand" "0")
+ 		  (mult:SF (match_operand:SF 2 "s_register_operand" "t")
+ 			   (match_operand:SF 3 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmls%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -889,13 +1314,25 @@
+ 
+ 
+ ;; 0 = -(1 * 2) - 0
++(define_insn "*mulhf3neghfsubhf_vfp"
++  [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(minus:HF (mult:HF
++		   (neg:HF (match_operand:HF 2 "s_register_operand" "t"))
++		   (match_operand:HF 3 "s_register_operand" "t"))
++		  (match_operand:HF 1 "s_register_operand" "0")))]
++  "TARGET_VFP_FP16INST"
++  "vnmla.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3negsfsubsf_vfp"
+   [(set (match_operand:SF		      0 "s_register_operand" "=t")
+ 	(minus:SF (mult:SF
+ 		    (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
+ 		    (match_operand:SF	      3 "s_register_operand" "t"))
+ 		  (match_operand:SF	      1 "s_register_operand" "0")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vnmla%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -917,6 +1354,30 @@
+ 
+ ;; Fused-multiply-accumulate
+ 
++(define_insn "fmahf4"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++    (fma:HF
++     (match_operand:HF 1 "register_operand" "w")
++     (match_operand:HF 2 "register_operand" "w")
++     (match_operand:HF 3 "register_operand" "0")))]
++ "TARGET_VFP_FP16INST"
++ "vfma.f16\\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "ffmas")]
++)
++
++(define_expand "neon_vfmahf"
++  [(match_operand:HF 0 "s_register_operand")
++   (match_operand:HF 1 "s_register_operand")
++   (match_operand:HF 2 "s_register_operand")
++   (match_operand:HF 3 "s_register_operand")]
++  "TARGET_VFP_FP16INST"
++{
++  emit_insn (gen_fmahf4 (operands[0], operands[2], operands[3],
++			 operands[1]));
++  DONE;
++})
++
+ (define_insn "fma<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+@@ -929,6 +1390,30 @@
+    (set_attr "type" "ffma<vfp_type>")]
+ )
+ 
++(define_insn "fmsubhf4_fp16"
++ [(set (match_operand:HF 0 "register_operand" "=w")
++   (fma:HF
++    (neg:HF (match_operand:HF 1 "register_operand" "w"))
++    (match_operand:HF 2 "register_operand" "w")
++    (match_operand:HF 3 "register_operand" "0")))]
++ "TARGET_VFP_FP16INST"
++ "vfms.f16\\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "ffmas")]
++)
++
++(define_expand "neon_vfmshf"
++  [(match_operand:HF 0 "s_register_operand")
++   (match_operand:HF 1 "s_register_operand")
++   (match_operand:HF 2 "s_register_operand")
++   (match_operand:HF 3 "s_register_operand")]
++  "TARGET_VFP_FP16INST"
++{
++  emit_insn (gen_fmsubhf4_fp16 (operands[0], operands[2], operands[3],
++				operands[1]));
++  DONE;
++})
++
+ (define_insn "*fmsub<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ 	(fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
+@@ -942,6 +1427,17 @@
+    (set_attr "type" "ffma<vfp_type>")]
+ )
+ 
++(define_insn "*fnmsubhf4"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(fma:HF (match_operand:HF 1 "register_operand" "w")
++		 (match_operand:HF 2 "register_operand" "w")
++		 (neg:HF (match_operand:HF 3 "register_operand" "0"))))]
++  "TARGET_VFP_FP16INST"
++  "vfnms.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "ffmas")]
++)
++
+ (define_insn "*fnmsub<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ 	(fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+@@ -954,6 +1450,17 @@
+    (set_attr "type" "ffma<vfp_type>")]
+ )
+ 
++(define_insn "*fnmaddhf4"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(fma:HF (neg:HF (match_operand:HF 1 "register_operand" "w"))
++		 (match_operand:HF 2 "register_operand" "w")
++		 (neg:HF (match_operand:HF 3 "register_operand" "0"))))]
++  "TARGET_VFP_FP16INST"
++  "vfnma.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "ffmas")]
++)
++
+ (define_insn "*fnmadd<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ 	(fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
+@@ -993,7 +1500,7 @@
+ (define_insn "extendhfsf2"
+   [(set (match_operand:SF		   0 "s_register_operand" "=t")
+ 	(float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
++  "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
+   "vcvtb%?.f32.f16\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1003,7 +1510,7 @@
+ (define_insn "truncsfhf2"
+   [(set (match_operand:HF		   0 "s_register_operand" "=t")
+ 	(float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
++  "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
+   "vcvtb%?.f16.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1013,7 +1520,7 @@
+ (define_insn "*truncsisf2_vfp"
+   [(set (match_operand:SI		  0 "s_register_operand" "=t")
+ 	(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.s32.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1034,7 +1541,7 @@
+ (define_insn "fixuns_truncsfsi2"
+   [(set (match_operand:SI		  0 "s_register_operand" "=t")
+ 	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.u32.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1055,7 +1562,7 @@
+ (define_insn "*floatsisf2_vfp"
+   [(set (match_operand:SF	    0 "s_register_operand" "=t")
+ 	(float:SF (match_operand:SI 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.f32.s32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1076,7 +1583,7 @@
+ (define_insn "floatunssisf2"
+   [(set (match_operand:SF	    0 "s_register_operand" "=t")
+ 	(unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.f32.u32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1096,13 +1603,34 @@
+ 
+ ;; Sqrt insns.
+ 
++(define_insn "neon_vsqrthf"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++	(sqrt:HF (match_operand:HF 1 "s_register_operand" "w")))]
++  "TARGET_VFP_FP16INST"
++  "vsqrt.f16\t%0, %1"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fsqrts")]
++)
++
++(define_insn "neon_vrsqrtshf"
++  [(set
++    (match_operand:HF 0 "s_register_operand" "=w")
++    (unspec:HF [(match_operand:HF 1 "s_register_operand" "w")
++		(match_operand:HF 2 "s_register_operand" "w")]
++     UNSPEC_VRSQRTS))]
++ "TARGET_VFP_FP16INST"
++ "vrsqrts.f16\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "fsqrts")]
++)
++
+ ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
+ ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
+ ; earlier.
+ (define_insn "*sqrtsf2_vfp"
+   [(set (match_operand:SF	   0 "s_register_operand" "=&t,t")
+ 	(sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vsqrt%?.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1127,7 +1655,7 @@
+ (define_insn "*movcc_vfp"
+   [(set (reg CC_REGNUM)
+ 	(reg VFPCC_REGNUM))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmrs%?\\tAPSR_nzcv, FPSCR"
+   [(set_attr "conds" "set")
+    (set_attr "type" "f_flag")]
+@@ -1137,9 +1665,9 @@
+   [(set (reg:CCFP CC_REGNUM)
+ 	(compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
+ 		      (match_operand:SF 1 "vfp_compare_operand" "tG")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "#"
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   [(set (reg:CCFP VFPCC_REGNUM)
+ 	(compare:CCFP (match_dup 0)
+ 		      (match_dup 1)))
+@@ -1152,9 +1680,9 @@
+   [(set (reg:CCFPE CC_REGNUM)
+ 	(compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
+ 		       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "#"
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   [(set (reg:CCFPE VFPCC_REGNUM)
+ 	(compare:CCFPE (match_dup 0)
+ 		       (match_dup 1)))
+@@ -1203,7 +1731,7 @@
+   [(set (reg:CCFP VFPCC_REGNUM)
+ 	(compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
+ 		      (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "@
+    vcmp%?.f32\\t%0, %1
+    vcmp%?.f32\\t%0, #0"
+@@ -1216,7 +1744,7 @@
+   [(set (reg:CCFPE VFPCC_REGNUM)
+ 	(compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
+ 		       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "@
+    vcmpe%?.f32\\t%0, %1
+    vcmpe%?.f32\\t%0, #0"
+@@ -1252,9 +1780,6 @@
+ )
+ 
+ ;; Fixed point to floating point conversions.
+-(define_code_iterator FCVT [unsigned_float float])
+-(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
+-
+ (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
+   [(set (match_operand:SF 0 "s_register_operand" "=t")
+ 	(mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
+@@ -1299,13 +1824,132 @@
+    (set_attr "type" "f_cvtf2i")]
+  )
+ 
++;; FP16 conversions.
++(define_insn "neon_vcvth<sup>hf"
++ [(set (match_operand:HF 0 "s_register_operand" "=w")
++   (unspec:HF
++    [(match_operand:SI 1 "s_register_operand" "w")]
++    VCVTH_US))]
++ "TARGET_VFP_FP16INST"
++ "vcvt.f16.<sup>%#32\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "f_cvti2f")]
++)
++
++(define_insn "neon_vcvth<sup>si"
++ [(set (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(match_operand:HF 1 "s_register_operand" "w")]
++    VCVTH_US))]
++ "TARGET_VFP_FP16INST"
++ "vcvt.<sup>%#32.f16\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "f_cvtf2i")]
++)
++
++;; The neon_vcvth<sup>_nhf patterns are used to generate the instruction for the
++;; vcvth_n_f16_<sup>32 arm_fp16 intrinsics.  They are complicated by the
++;; hardware requirement that the source and destination registers are the same
++;; despite having different machine modes.  The approach is to use a temporary
++;; register for the conversion and move that to the correct destination.
++
++;; Generate an unspec pattern for the intrinsic.
++(define_insn "neon_vcvth<sup>_nhf_unspec"
++ [(set
++   (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(match_operand:SI 1 "s_register_operand" "0")
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_HF_US_N))
++ (set
++  (match_operand:HF 3 "s_register_operand" "=w")
++  (float_truncate:HF (float:SF (match_dup 0))))]
++ "TARGET_VFP_FP16INST"
++{
++  neon_const_bounds (operands[2], 1, 33);
++  return "vcvt.f16.<sup>32\t%0, %0, %2\;vmov.f32\t%3, %0";
++}
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "f_cvti2f")]
++)
++
++;; Generate the instruction patterns needed for vcvth_n_f16_s32 neon intrinsics.
++(define_expand "neon_vcvth<sup>_nhf"
++ [(match_operand:HF 0 "s_register_operand")
++  (unspec:HF [(match_operand:SI 1 "s_register_operand")
++	      (match_operand:SI 2 "immediate_operand")]
++   VCVT_HF_US_N)]
++"TARGET_VFP_FP16INST"
++{
++  rtx op1 = gen_reg_rtx (SImode);
++
++  neon_const_bounds (operands[2], 1, 33);
++
++  emit_move_insn (op1, operands[1]);
++  emit_insn (gen_neon_vcvth<sup>_nhf_unspec (op1, op1, operands[2],
++					     operands[0]));
++  DONE;
++})
++
++;; The neon_vcvth<sup>_nsi patterns are used to generate the instruction for the
++;; vcvth_n_<sup>32_f16 arm_fp16 intrinsics.  They have the same restrictions and
++;; are implemented in the same way as the neon_vcvth<sup>_nhf patterns.
++
++;; Generate an unspec pattern, constraining the registers.
++(define_insn "neon_vcvth<sup>_nsi_unspec"
++ [(set (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(fix:SI
++      (fix:SF
++       (float_extend:SF
++	(match_operand:HF 1 "s_register_operand" "w"))))
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_SI_US_N))]
++ "TARGET_VFP_FP16INST"
++{
++  neon_const_bounds (operands[2], 1, 33);
++  return "vmov.f32\t%0, %1\;vcvt.<sup>%#32.f16\t%0, %0, %2";
++}
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "f_cvtf2i")]
++)
++
++;; Generate the instruction patterns needed for vcvth_n_f16_s32 neon intrinsics.
++(define_expand "neon_vcvth<sup>_nsi"
++ [(match_operand:SI 0 "s_register_operand")
++  (unspec:SI
++   [(match_operand:HF 1 "s_register_operand")
++    (match_operand:SI 2 "immediate_operand")]
++   VCVT_SI_US_N)]
++ "TARGET_VFP_FP16INST"
++{
++  rtx op1 = gen_reg_rtx (SImode);
++
++  neon_const_bounds (operands[2], 1, 33);
++  emit_insn (gen_neon_vcvth<sup>_nsi_unspec (op1, operands[1], operands[2]));
++  emit_move_insn (operands[0], op1);
++  DONE;
++})
++
++(define_insn "neon_vcvt<vcvth_op>h<sup>si"
++ [(set
++   (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(match_operand:HF 1 "s_register_operand" "w")]
++    VCVT_HF_US))]
++ "TARGET_VFP_FP16INST"
++ "vcvt<vcvth_op>.<sup>%#32.f16\t%0, %1"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "f_cvtf2i")]
++)
++
+ ;; Store multiple insn used in function prologue.
+ (define_insn "*push_multi_vfp"
+   [(match_parallel 2 "multi_register_push"
+     [(set (match_operand:BLK 0 "memory_operand" "=m")
+ 	  (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
+ 		      UNSPEC_PUSH_MULT))])]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "* return vfp_output_vstmd (operands);"
+   [(set_attr "type" "f_stored")]
+ )
+@@ -1368,6 +2012,20 @@
+ )
+ 
+ ;; Scalar forms for the IEEE-754 fmax()/fmin() functions
++
++(define_insn "neon_<fmaxmin_op>hf"
++ [(set
++   (match_operand:HF 0 "s_register_operand" "=w")
++   (unspec:HF
++    [(match_operand:HF 1 "s_register_operand" "w")
++     (match_operand:HF 2 "s_register_operand" "w")]
++    VMAXMINFNM))]
++ "TARGET_VFP_FP16INST"
++ "<fmaxmin_op>.f16\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "f_minmaxs")]
++)
++
+ (define_insn "<fmaxmin><mode>3"
+   [(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>")
+ 	(unspec:SDF [(match_operand:SDF 1 "s_register_operand" "<F_constraint>")
+@@ -1382,7 +2040,7 @@
+ ;; Write Floating-point Status and Control Register.
+ (define_insn "set_fpscr"
+   [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
+-  "TARGET_VFP && TARGET_HARD_FLOAT"
++  "TARGET_HARD_FLOAT"
+   "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
+   [(set_attr "type" "mrs")])
+ 
+@@ -1390,7 +2048,7 @@
+ (define_insn "get_fpscr"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+         (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
+-  "TARGET_VFP && TARGET_HARD_FLOAT"
++  "TARGET_HARD_FLOAT"
+   "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
+   [(set_attr "type" "mrs")])
+ 
+--- a/src/gcc/config/arm/xgene1.md
++++ b/src/gcc/config/arm/xgene1.md
+@@ -164,7 +164,7 @@
+ 
+ (define_insn_reservation "xgene1_bfm" 2
+   (and (eq_attr "tune" "xgene1")
+-       (eq_attr "type" "bfm"))
++       (eq_attr "type" "bfm,bfx"))
+   "xgene1_decode1op,xgene1_fsu")
+ 
+ (define_insn_reservation "xgene1_f_rint" 5
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "backend.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "cfgloop.h"
+--- a/src/gcc/config/ia64/ia64.c
++++ b/src/gcc/config/ia64/ia64.c
+@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "cfghooks.h"
+ #include "df.h"
+ #include "tm_p.h"
+--- a/src/gcc/config/linux.c
++++ b/src/gcc/config/linux.c
+@@ -26,7 +26,7 @@ along with GCC; see the file COPYING3.  If not see
+ bool
+ linux_libc_has_function (enum function_class fn_class)
+ {
+-  if (OPTION_GLIBC)
++  if (OPTION_GLIBC || OPTION_MUSL)
+     return true;
+   if (OPTION_BIONIC)
+     if (fn_class == function_c94
+--- a/src/gcc/config/mips/mips.c
++++ b/src/gcc/config/mips/mips.c
+@@ -28,6 +28,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "df.h"
+--- a/src/gcc/config/rs6000/rs6000.c
++++ b/src/gcc/config/rs6000/rs6000.c
+@@ -24,6 +24,7 @@
+ #include "backend.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "cfgloop.h"
+--- a/src/gcc/config/sparc/sparc.c
++++ b/src/gcc/config/sparc/sparc.c
+@@ -27,6 +27,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "df.h"
+ #include "tm_p.h"
+--- a/src/gcc/configure
++++ b/src/gcc/configure
+@@ -1711,7 +1711,8 @@ Optional Packages:
+   --with-stabs            arrange to use stabs instead of host debug format
+   --with-dwarf2           force the default debug format to be DWARF 2
+   --with-specs=SPECS      add SPECS to driver command-line processing
+-  --with-pkgversion=PKG   Use PKG in the version string in place of "GCC"
++  --with-pkgversion=PKG   Use PKG in the version string in place of "Linaro
++                          GCC `cat $srcdir/LINARO-VERSION`"
+   --with-bugurl=URL       Direct users to URL to report a bug
+   --with-multilib-list    select multilibs (AArch64, SH and x86-64 only)
+   --with-gnu-ld           assume the C compiler uses GNU ld default=no
+@@ -7658,7 +7659,7 @@ if test "${with_pkgversion+set}" = set; then :
+       *)   PKGVERSION="($withval) " ;;
+      esac
+ else
+-  PKGVERSION="(GCC) "
++  PKGVERSION="(Linaro GCC `cat $srcdir/LINARO-VERSION`) "
+ 
+ fi
+ 
+@@ -18460,7 +18461,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 18463 "configure"
++#line 18464 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -18566,7 +18567,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 18569 "configure"
++#line 18570 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -910,7 +910,7 @@ AC_ARG_WITH(specs,
+ )
+ AC_SUBST(CONFIGURE_SPECS)
+ 
+-ACX_PKGVERSION([GCC])
++ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`])
+ ACX_BUGURL([http://gcc.gnu.org/bugs.html])
+ 
+ # Sanity check enable_languages in case someone does not run the toplevel
+--- a/src/gcc/cppbuiltin.c
++++ b/src/gcc/cppbuiltin.c
+@@ -52,18 +52,41 @@ parse_basever (int *major, int *minor, int *patchlevel)
+     *patchlevel = s_patchlevel;
+ }
+ 
++/* Parse a LINAROVER version string of the format "M.m-year.month[-spin][~dev]"
++   to create Linaro release number YYYYMM and spin version.  */
++static void
++parse_linarover (int *release, int *spin)
++{
++  static int s_year = -1, s_month, s_spin;
++
++  if (s_year == -1)
++    if (sscanf (LINAROVER, "%*[^-]-%d.%d-%d", &s_year, &s_month, &s_spin) != 3)
++      {
++	sscanf (LINAROVER, "%*[^-]-%d.%d", &s_year, &s_month);
++	s_spin = 0;
++      }
++
++  if (release)
++    *release = s_year * 100 + s_month;
++
++  if (spin)
++    *spin = s_spin;
++}
+ 
+ /* Define __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__ and __VERSION__.  */
+ static void
+ define__GNUC__ (cpp_reader *pfile)
+ {
+-  int major, minor, patchlevel;
++  int major, minor, patchlevel, linaro_release, linaro_spin;
+ 
+   parse_basever (&major, &minor, &patchlevel);
++  parse_linarover (&linaro_release, &linaro_spin);
+   cpp_define_formatted (pfile, "__GNUC__=%d", major);
+   cpp_define_formatted (pfile, "__GNUC_MINOR__=%d", minor);
+   cpp_define_formatted (pfile, "__GNUC_PATCHLEVEL__=%d", patchlevel);
+   cpp_define_formatted (pfile, "__VERSION__=\"%s\"", version_string);
++  cpp_define_formatted (pfile, "__LINARO_RELEASE__=%d", linaro_release);
++  cpp_define_formatted (pfile, "__LINARO_SPIN__=%d", linaro_spin);
+   cpp_define_formatted (pfile, "__ATOMIC_RELAXED=%d", MEMMODEL_RELAXED);
+   cpp_define_formatted (pfile, "__ATOMIC_SEQ_CST=%d", MEMMODEL_SEQ_CST);
+   cpp_define_formatted (pfile, "__ATOMIC_ACQUIRE=%d", MEMMODEL_ACQUIRE);
+--- a/src/gcc/defaults.h
++++ b/src/gcc/defaults.h
+@@ -971,11 +971,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ #define REG_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN
+ #endif
+ 
+-#ifdef TARGET_FLT_EVAL_METHOD
+-#define TARGET_FLT_EVAL_METHOD_NON_DEFAULT 1
+-#else
++#ifndef TARGET_FLT_EVAL_METHOD
+ #define TARGET_FLT_EVAL_METHOD 0
+-#define TARGET_FLT_EVAL_METHOD_NON_DEFAULT 0
+ #endif
+ 
+ #ifndef TARGET_DEC_EVAL_METHOD
+--- a/src/gcc/expmed.c
++++ b/src/gcc/expmed.c
+@@ -2522,16 +2522,8 @@ expand_variable_shift (enum tree_code code, machine_mode mode, rtx shifted,
+ }
+ 
+ 
+-/* Indicates the type of fixup needed after a constant multiplication.
+-   BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
+-   the result should be negated, and ADD_VARIANT means that the
+-   multiplicand should be added to the result.  */
+-enum mult_variant {basic_variant, negate_variant, add_variant};
+-
+ static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
+ 			const struct mult_cost *, machine_mode mode);
+-static bool choose_mult_variant (machine_mode, HOST_WIDE_INT,
+-				 struct algorithm *, enum mult_variant *, int);
+ static rtx expand_mult_const (machine_mode, rtx, HOST_WIDE_INT, rtx,
+ 			      const struct algorithm *, enum mult_variant);
+ static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
+@@ -3021,7 +3013,7 @@ synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
+    Return true if the cheapest of these cost less than MULT_COST,
+    describing the algorithm in *ALG and final fixup in *VARIANT.  */
+ 
+-static bool
++bool
+ choose_mult_variant (machine_mode mode, HOST_WIDE_INT val,
+ 		     struct algorithm *alg, enum mult_variant *variant,
+ 		     int mult_cost)
+--- a/src/gcc/expmed.h
++++ b/src/gcc/expmed.h
+@@ -35,6 +35,15 @@ enum alg_code {
+   alg_impossible
+ };
+ 
++/* Indicates the type of fixup needed after a constant multiplication.
++   BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
++   the result should be negated, and ADD_VARIANT means that the
++   multiplicand should be added to the result.  */
++enum mult_variant {basic_variant, negate_variant, add_variant};
++
++bool choose_mult_variant (machine_mode, HOST_WIDE_INT,
++			  struct algorithm *, enum mult_variant *, int);
++
+ /* This structure holds the "cost" of a multiply sequence.  The
+    "cost" field holds the total rtx_cost of every operator in the
+    synthetic multiplication sequence, hence cost(a op b) is defined
+--- a/src/gcc/fold-const.c
++++ b/src/gcc/fold-const.c
+@@ -7216,7 +7216,16 @@ native_encode_real (const_tree expr, unsigned char *ptr, int len, int off)
+ 	    offset += byte % UNITS_PER_WORD;
+ 	}
+       else
+-	offset = BYTES_BIG_ENDIAN ? 3 - byte : byte;
++	{
++	  offset = byte;
++	  if (BYTES_BIG_ENDIAN)
++	    {
++	      /* Reverse bytes within each long, or within the entire float
++		 if it's smaller than a long (for HFmode).  */
++	      offset = MIN (3, total_bytes - 1) - offset;
++	      gcc_assert (offset >= 0);
++	    }
++	}
+       offset = offset + ((bitpos / BITS_PER_UNIT) & ~3);
+       if (offset >= off
+ 	  && offset - off < len)
+--- a/src/gcc/fortran/options.c
++++ b/src/gcc/fortran/options.c
+@@ -208,8 +208,7 @@ gfc_post_options (const char **pfilename)
+ 
+   /* Excess precision other than "fast" requires front-end
+      support.  */
+-  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-      && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+     sorry ("-fexcess-precision=standard for Fortran");
+   flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+ 
+--- a/src/gcc/genconditions.c
++++ b/src/gcc/genconditions.c
+@@ -94,6 +94,7 @@ write_header (void)
+ #include \"resource.h\"\n\
+ #include \"diagnostic-core.h\"\n\
+ #include \"reload.h\"\n\
++#include \"memmodel.h\"\n\
+ #include \"tm-constrs.h\"\n");
+ 
+   if (saw_eh_return)
+--- a/src/gcc/genemit.c
++++ b/src/gcc/genemit.c
+@@ -792,6 +792,7 @@ from the machine description file `md'.  */\n\n");
+   printf ("#include \"reload.h\"\n");
+   printf ("#include \"diagnostic-core.h\"\n");
+   printf ("#include \"regs.h\"\n");
++  printf ("#include \"memmodel.h\"\n");
+   printf ("#include \"tm-constrs.h\"\n");
+   printf ("#include \"ggc.h\"\n");
+   printf ("#include \"dumpfile.h\"\n");
+--- a/src/gcc/genmultilib
++++ b/src/gcc/genmultilib
+@@ -186,7 +186,8 @@ fi
+ EOF
+ chmod +x tmpmultilib
+ 
+-combinations=`initial=/ ./tmpmultilib ${options}`
++combination_space=`initial=/ ./tmpmultilib ${options}`
++combinations="$combination_space"
+ 
+ # If there exceptions, weed them out now
+ if [ -n "${exceptions}" ]; then
+@@ -472,14 +473,19 @@ for rrule in ${multilib_reuse}; do
+   # in this variable, it means no multilib will be built for current reuse
+   # rule.  Thus the reuse purpose specified by current rule is meaningless.
+   if expr "${combinations} " : ".*/${combo}/.*" > /dev/null; then
+-    combo="/${combo}/"
+-    dirout=`./tmpmultilib3 "${combo}" "${todirnames}" "${toosdirnames}" "${enable_multilib}"`
+-    copts="/${copts}/"
+-    optout=`./tmpmultilib4 "${copts}" "${options}"`
+-    # Output the line with all appropriate matches.
+-    dirout="${dirout}" optout="${optout}" ./tmpmultilib2
++    if expr "${combination_space} " : ".*/${copts}/.*" > /dev/null; then
++      combo="/${combo}/"
++      dirout=`./tmpmultilib3 "${combo}" "${todirnames}" "${toosdirnames}" "${enable_multilib}"`
++      copts="/${copts}/"
++      optout=`./tmpmultilib4 "${copts}" "${options}"`
++      # Output the line with all appropriate matches.
++      dirout="${dirout}" optout="${optout}" ./tmpmultilib2
++    else
++      echo "The rule ${rrule} contains an option absent from MULTILIB_OPTIONS." >&2
++      exit 1
++    fi
+   else
+-    echo "The rule ${rrule} is trying to reuse nonexistent multilib."
++    echo "The rule ${rrule} is trying to reuse nonexistent multilib." >&2
+     exit 1
+   fi
+ done
+--- a/src/gcc/genoutput.c
++++ b/src/gcc/genoutput.c
+@@ -231,6 +231,7 @@ output_prologue (void)
+   printf ("#include \"diagnostic-core.h\"\n");
+   printf ("#include \"output.h\"\n");
+   printf ("#include \"target.h\"\n");
++  printf ("#include \"memmodel.h\"\n");
+   printf ("#include \"tm-constrs.h\"\n");
+ }
+ 
+--- a/src/gcc/genpeep.c
++++ b/src/gcc/genpeep.c
+@@ -373,6 +373,7 @@ from the machine description file `md'.  */\n\n");
+   printf ("#include \"except.h\"\n");
+   printf ("#include \"diagnostic-core.h\"\n");
+   printf ("#include \"flags.h\"\n");
++  printf ("#include \"memmodel.h\"\n");
+   printf ("#include \"tm-constrs.h\"\n\n");
+ 
+   printf ("extern rtx peep_operand[];\n\n");
+--- a/src/gcc/genpreds.c
++++ b/src/gcc/genpreds.c
+@@ -1577,6 +1577,7 @@ write_insn_preds_c (void)
+ #include \"reload.h\"\n\
+ #include \"regs.h\"\n\
+ #include \"emit-rtl.h\"\n\
++#include \"memmodel.h\"\n\
+ #include \"tm-constrs.h\"\n");
+ 
+   FOR_ALL_PREDICATES (p)
+--- a/src/gcc/genrecog.c
++++ b/src/gcc/genrecog.c
+@@ -4172,6 +4172,7 @@ write_header (void)
+ #include \"diagnostic-core.h\"\n\
+ #include \"reload.h\"\n\
+ #include \"regs.h\"\n\
++#include \"memmodel.h\"\n\
+ #include \"tm-constrs.h\"\n\
+ \n");
+ 
+--- a/src/gcc/gimple-fold.c
++++ b/src/gcc/gimple-fold.c
+@@ -1379,6 +1379,55 @@ gimple_fold_builtin_strncpy (gimple_stmt_iterator *gsi,
+   return true;
+ }
+ 
++/* Simplify strchr (str, 0) into str + strlen (str).
++   In general strlen is significantly faster than strchr
++   due to being a simpler operation.  */
++static bool
++gimple_fold_builtin_strchr (gimple_stmt_iterator *gsi)
++{
++  gimple *stmt = gsi_stmt (*gsi);
++  tree str = gimple_call_arg (stmt, 0);
++  tree c = gimple_call_arg (stmt, 1);
++  location_t loc = gimple_location (stmt);
++
++  if (optimize_function_for_size_p (cfun))
++    return false;
++
++  if (!integer_zerop (c) || !gimple_call_lhs (stmt))
++    return false;
++
++  tree len;
++  tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN);
++
++  if (!strlen_fn)
++    return false;
++
++  /* Create newstr = strlen (str).  */
++  gimple_seq stmts = NULL;
++  gimple *new_stmt = gimple_build_call (strlen_fn, 1, str);
++  gimple_set_location (new_stmt, loc);
++  if (gimple_in_ssa_p (cfun))
++    len = make_ssa_name (size_type_node);
++  else
++    len = create_tmp_reg (size_type_node);
++  gimple_call_set_lhs (new_stmt, len);
++  gimple_seq_add_stmt_without_update (&stmts, new_stmt);
++
++  /* Create (str p+ strlen (str)).  */
++  new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
++				  POINTER_PLUS_EXPR, str, len);
++  gimple_seq_add_stmt_without_update (&stmts, new_stmt);
++  gsi_replace_with_seq_vops (gsi, stmts);
++  /* gsi now points at the assignment to the lhs, get a
++     stmt iterator to the strlen.
++     ???  We can't use gsi_for_stmt as that doesn't work when the
++     CFG isn't built yet.  */
++  gimple_stmt_iterator gsi2 = *gsi;
++  gsi_prev (&gsi2);
++  fold_stmt (&gsi2);
++  return true;
++}
++
+ /* Simplify a call to the strcat builtin.  DST and SRC are the arguments
+    to the call.
+ 
+@@ -2820,6 +2869,11 @@ gimple_fold_builtin (gimple_stmt_iterator *gsi)
+ 					 gimple_call_arg (stmt, 1));
+     case BUILT_IN_STRNCAT:
+       return gimple_fold_builtin_strncat (gsi);
++    case BUILT_IN_STRCHR:
++      if (gimple_fold_builtin_strchr (gsi))
++	return true;
++      /* Perform additional folding in builtin.c.  */
++      break;
+     case BUILT_IN_FPUTS:
+       return gimple_fold_builtin_fputs (gsi, gimple_call_arg (stmt, 0),
+ 					gimple_call_arg (stmt, 1), false);
+--- a/src/gcc/ifcvt.c
++++ b/src/gcc/ifcvt.c
+@@ -813,10 +813,15 @@ struct noce_if_info
+ 
+   /* Estimated cost of the particular branch instruction.  */
+   unsigned int branch_cost;
++
++  /* The name of the noce transform that succeeded in if-converting
++     this structure.  Used for debugging.  */
++  const char *transform_name;
+ };
+ 
+ static rtx noce_emit_store_flag (struct noce_if_info *, rtx, int, int);
+ static int noce_try_move (struct noce_if_info *);
++static int noce_try_ifelse_collapse (struct noce_if_info *);
+ static int noce_try_store_flag (struct noce_if_info *);
+ static int noce_try_addcc (struct noce_if_info *);
+ static int noce_try_store_flag_constants (struct noce_if_info *);
+@@ -1115,11 +1120,45 @@ noce_try_move (struct noce_if_info *if_info)
+ 	  emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
+ 	}
++      if_info->transform_name = "noce_try_move";
+       return TRUE;
+     }
+   return FALSE;
+ }
+ 
++/* Try forming an IF_THEN_ELSE (cond, b, a) and collapsing that
++   through simplify_rtx.  Sometimes that can eliminate the IF_THEN_ELSE.
++   If that is the case, emit the result into x.  */
++
++static int
++noce_try_ifelse_collapse (struct noce_if_info * if_info)
++{
++  if (!noce_simple_bbs (if_info))
++    return FALSE;
++
++  machine_mode mode = GET_MODE (if_info->x);
++  rtx if_then_else = simplify_gen_ternary (IF_THEN_ELSE, mode, mode,
++					    if_info->cond, if_info->b,
++					    if_info->a);
++
++  if (GET_CODE (if_then_else) == IF_THEN_ELSE)
++    return FALSE;
++
++  rtx_insn *seq;
++  start_sequence ();
++  noce_emit_move_insn (if_info->x, if_then_else);
++  seq = end_ifcvt_sequence (if_info);
++  if (!seq)
++    return FALSE;
++
++  emit_insn_before_setloc (seq, if_info->jump,
++			  INSN_LOCATION (if_info->insn_a));
++
++  if_info->transform_name = "noce_try_ifelse_collapse";
++  return TRUE;
++}
++
++
+ /* Convert "if (test) x = 1; else x = 0".
+ 
+    Only try 0 and STORE_FLAG_VALUE here.  Other combinations will be
+@@ -1163,6 +1202,7 @@ noce_try_store_flag (struct noce_if_info *if_info)
+ 
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
++      if_info->transform_name = "noce_try_store_flag";
+       return TRUE;
+     }
+   else
+@@ -1241,6 +1281,7 @@ noce_try_inverse_constants (struct noce_if_info *if_info)
+ 
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
++      if_info->transform_name = "noce_try_inverse_constants";
+       return true;
+     }
+ 
+@@ -1461,6 +1502,8 @@ noce_try_store_flag_constants (struct noce_if_info *if_info)
+ 
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
++      if_info->transform_name = "noce_try_store_flag_constants";
++
+       return TRUE;
+     }
+ 
+@@ -1513,6 +1556,8 @@ noce_try_addcc (struct noce_if_info *if_info)
+ 
+ 	      emit_insn_before_setloc (seq, if_info->jump,
+ 				       INSN_LOCATION (if_info->insn_a));
++	      if_info->transform_name = "noce_try_addcc";
++
+ 	      return TRUE;
+ 	    }
+ 	  end_sequence ();
+@@ -1553,6 +1598,7 @@ noce_try_addcc (struct noce_if_info *if_info)
+ 
+ 	      emit_insn_before_setloc (seq, if_info->jump,
+ 				       INSN_LOCATION (if_info->insn_a));
++	      if_info->transform_name = "noce_try_addcc";
+ 	      return TRUE;
+ 	    }
+ 	  end_sequence ();
+@@ -1617,6 +1663,8 @@ noce_try_store_flag_mask (struct noce_if_info *if_info)
+ 
+ 	  emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
++	  if_info->transform_name = "noce_try_store_flag_mask";
++
+ 	  return TRUE;
+ 	}
+ 
+@@ -1767,6 +1815,8 @@ noce_try_cmove (struct noce_if_info *if_info)
+ 
+ 	  emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
++	  if_info->transform_name = "noce_try_cmove";
++
+ 	  return TRUE;
+ 	}
+       /* If both a and b are constants try a last-ditch transformation:
+@@ -1820,6 +1870,7 @@ noce_try_cmove (struct noce_if_info *if_info)
+ 
+ 	      emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
++	      if_info->transform_name = "noce_try_cmove";
+ 	      return TRUE;
+ 	    }
+ 	  else
+@@ -2273,6 +2324,7 @@ noce_try_cmove_arith (struct noce_if_info *if_info)
+ 
+   emit_insn_before_setloc (ifcvt_seq, if_info->jump,
+ 			   INSN_LOCATION (if_info->insn_a));
++  if_info->transform_name = "noce_try_cmove_arith";
+   return TRUE;
+ 
+  end_seq_and_fail:
+@@ -2364,28 +2416,32 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target,
+ 	  switch (code)
+ 	    {
+ 	    case LT:
+-	      if (actual_val == desired_val + 1)
++	      if (desired_val != HOST_WIDE_INT_MAX
++		  && actual_val == desired_val + 1)
+ 		{
+ 		  code = LE;
+ 		  op_b = GEN_INT (desired_val);
+ 		}
+ 	      break;
+ 	    case LE:
+-	      if (actual_val == desired_val - 1)
++	      if (desired_val != HOST_WIDE_INT_MIN
++		  && actual_val == desired_val - 1)
+ 		{
+ 		  code = LT;
+ 		  op_b = GEN_INT (desired_val);
+ 		}
+ 	      break;
+ 	    case GT:
+-	      if (actual_val == desired_val - 1)
++	      if (desired_val != HOST_WIDE_INT_MIN
++		  && actual_val == desired_val - 1)
+ 		{
+ 		  code = GE;
+ 		  op_b = GEN_INT (desired_val);
+ 		}
+ 	      break;
+ 	    case GE:
+-	      if (actual_val == desired_val + 1)
++	      if (desired_val != HOST_WIDE_INT_MAX
++		  && actual_val == desired_val + 1)
+ 		{
+ 		  code = GT;
+ 		  op_b = GEN_INT (desired_val);
+@@ -2525,6 +2581,7 @@ noce_try_minmax (struct noce_if_info *if_info)
+   emit_insn_before_setloc (seq, if_info->jump, INSN_LOCATION (if_info->insn_a));
+   if_info->cond = cond;
+   if_info->cond_earliest = earliest;
++  if_info->transform_name = "noce_try_minmax";
+ 
+   return TRUE;
+ }
+@@ -2691,6 +2748,7 @@ noce_try_abs (struct noce_if_info *if_info)
+   emit_insn_before_setloc (seq, if_info->jump, INSN_LOCATION (if_info->insn_a));
+   if_info->cond = cond;
+   if_info->cond_earliest = earliest;
++  if_info->transform_name = "noce_try_abs";
+ 
+   return TRUE;
+ }
+@@ -2772,6 +2830,8 @@ noce_try_sign_mask (struct noce_if_info *if_info)
+     return FALSE;
+ 
+   emit_insn_before_setloc (seq, if_info->jump, INSN_LOCATION (if_info->insn_a));
++  if_info->transform_name = "noce_try_sign_mask";
++
+   return TRUE;
+ }
+ 
+@@ -2877,6 +2937,7 @@ noce_try_bitop (struct noce_if_info *if_info)
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
+     }
++  if_info->transform_name = "noce_try_bitop";
+   return TRUE;
+ }
+ 
+@@ -3167,6 +3228,41 @@ noce_convert_multiple_sets (struct noce_if_info *if_info)
+       if (if_info->then_else_reversed)
+ 	std::swap (old_val, new_val);
+ 
++
++      /* We allow simple lowpart register subreg SET sources in
++	 bb_ok_for_noce_convert_multiple_sets.  Be careful when processing
++	 sequences like:
++	 (set (reg:SI r1) (reg:SI r2))
++	 (set (reg:HI r3) (subreg:HI (r1)))
++	 For the second insn new_val or old_val (r1 in this example) will be
++	 taken from the temporaries and have the wider mode which will not
++	 match with the mode of the other source of the conditional move, so
++	 we'll end up trying to emit r4:HI = cond ? (r1:SI) : (r3:HI).
++	 Wrap the two cmove operands into subregs if appropriate to prevent
++	 that.  */
++      if (GET_MODE (new_val) != GET_MODE (temp))
++	{
++	  machine_mode src_mode = GET_MODE (new_val);
++	  machine_mode dst_mode = GET_MODE (temp);
++	  if (GET_MODE_SIZE (src_mode) <= GET_MODE_SIZE (dst_mode))
++	    {
++	      end_sequence ();
++	      return FALSE;
++	    }
++	  new_val = lowpart_subreg (dst_mode, new_val, src_mode);
++	}
++      if (GET_MODE (old_val) != GET_MODE (temp))
++	{
++	  machine_mode src_mode = GET_MODE (old_val);
++	  machine_mode dst_mode = GET_MODE (temp);
++	  if (GET_MODE_SIZE (src_mode) <= GET_MODE_SIZE (dst_mode))
++	    {
++	      end_sequence ();
++	      return FALSE;
++	    }
++	  old_val = lowpart_subreg (dst_mode, old_val, src_mode);
++	}
++
+       /* Actually emit the conditional move.  */
+       rtx temp_dest = noce_emit_cmove (if_info, temp, cond_code,
+ 				       x, y, new_val, old_val);
+@@ -3240,6 +3336,7 @@ noce_convert_multiple_sets (struct noce_if_info *if_info)
+     }
+ 
+   num_updated_if_blocks++;
++  if_info->transform_name = "noce_convert_multiple_sets";
+   return TRUE;
+ }
+ 
+@@ -3277,9 +3374,15 @@ bb_ok_for_noce_convert_multiple_sets (basic_block test_bb,
+       rtx src = SET_SRC (set);
+ 
+       /* We can possibly relax this, but for now only handle REG to REG
+-	 moves.  This avoids any issues that might come from introducing
+-	 loads/stores that might violate data-race-freedom guarantees.  */
+-      if (!(REG_P (src) && REG_P (dest)))
++	 (including subreg) moves.  This avoids any issues that might come
++	 from introducing loads/stores that might violate data-race-freedom
++	 guarantees.  */
++      if (!REG_P (dest))
++	return false;
++
++      if (!(REG_P (src)
++	   || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
++	       && subreg_lowpart_p (src))))
+ 	return false;
+ 
+       /* Destination must be appropriate for a conditional write.  */
+@@ -3336,7 +3439,12 @@ noce_process_if_block (struct noce_if_info *if_info)
+       && bb_ok_for_noce_convert_multiple_sets (then_bb, if_info))
+     {
+       if (noce_convert_multiple_sets (if_info))
+-	return TRUE;
++	{
++	  if (dump_file && if_info->transform_name)
++	    fprintf (dump_file, "if-conversion succeeded through %s\n",
++		     if_info->transform_name);
++	  return TRUE;
++	}
+     }
+ 
+   if (! bb_valid_for_noce_process_p (then_bb, cond, &if_info->then_cost,
+@@ -3493,6 +3601,8 @@ noce_process_if_block (struct noce_if_info *if_info)
+ 
+   if (noce_try_move (if_info))
+     goto success;
++  if (noce_try_ifelse_collapse (if_info))
++    goto success;
+   if (noce_try_store_flag (if_info))
+     goto success;
+   if (noce_try_bitop (if_info))
+@@ -3533,6 +3643,9 @@ noce_process_if_block (struct noce_if_info *if_info)
+   return FALSE;
+ 
+  success:
++  if (dump_file && if_info->transform_name)
++    fprintf (dump_file, "if-conversion succeeded through %s\n",
++	     if_info->transform_name);
+ 
+   /* If we used a temporary, fix it up now.  */
+   if (orig_x != x)
+--- a/src/gcc/internal-fn.c
++++ b/src/gcc/internal-fn.c
+@@ -1810,11 +1810,7 @@ expand_arith_overflow (enum tree_code code, gimple *stmt)
+       /* For sub-word operations, retry with a wider type first.  */
+       if (orig_precres == precres && precop <= BITS_PER_WORD)
+ 	{
+-#if WORD_REGISTER_OPERATIONS
+-	  int p = BITS_PER_WORD;
+-#else
+-	  int p = precop;
+-#endif
++	  int p = WORD_REGISTER_OPERATIONS ? BITS_PER_WORD : precop;
+ 	  enum machine_mode m = smallest_mode_for_size (p, MODE_INT);
+ 	  tree optype = build_nonstandard_integer_type (GET_MODE_PRECISION (m),
+ 							uns0_p && uns1_p
+--- a/src/gcc/java/lang.c
++++ b/src/gcc/java/lang.c
+@@ -569,8 +569,7 @@ java_post_options (const char **pfilename)
+ 
+   /* Excess precision other than "fast" requires front-end
+      support.  */
+-  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-      && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+     sorry ("-fexcess-precision=standard for Java");
+   flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+ 
+--- a/src/gcc/lra-constraints.c
++++ b/src/gcc/lra-constraints.c
+@@ -1326,7 +1326,22 @@ process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **aft
+ 
+   subreg_p = GET_CODE (*loc) == SUBREG;
+   if (subreg_p)
+-    loc = &SUBREG_REG (*loc);
++    {
++      reg = SUBREG_REG (*loc);
++      mode = GET_MODE (reg);
++
++      /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
++	 between two registers with different classes, but there normally will
++	 be "mov" which transfers element of vector register into the general
++	 register, and this normally will be a subreg which should be reloaded
++	 as a whole.  This is particularly likely to be triggered when
++	 -fno-split-wide-types specified.  */
++      if (!REG_P (reg)
++	  || in_class_p (reg, cl, &new_class)
++	  || GET_MODE_SIZE (mode) <= GET_MODE_SIZE (ptr_mode))
++       loc = &SUBREG_REG (*loc);
++    }
++
+   reg = *loc;
+   mode = GET_MODE (reg);
+   if (! REG_P (reg))
+@@ -2475,14 +2490,29 @@ process_alt_operands (int only_alternative)
+ 	      /* We are trying to spill pseudo into memory.  It is
+ 		 usually more costly than moving to a hard register
+ 		 although it might takes the same number of
+-		 reloads.  */
+-	      if (no_regs_p && REG_P (op) && hard_regno[nop] >= 0)
++		 reloads.
++
++		 Non-pseudo spill may happen also.  Suppose a target allows both
++		 register and memory in the operand constraint alternatives,
++		 then it's typical that an eliminable register has a substition
++		 of "base + offset" which can either be reloaded by a simple
++		 "new_reg <= base + offset" which will match the register
++		 constraint, or a similar reg addition followed by further spill
++		 to and reload from memory which will match the memory
++		 constraint, but this memory spill will be much more costly
++		 usually.
++
++		 Code below increases the reject for both pseudo and non-pseudo
++		 spill.  */
++	      if (no_regs_p
++		  && !(MEM_P (op) && offmemok)
++		  && !(REG_P (op) && hard_regno[nop] < 0))
+ 		{
+ 		  if (lra_dump_file != NULL)
+ 		    fprintf
+ 		      (lra_dump_file,
+-		       "            %d Spill pseudo into memory: reject+=3\n",
+-		       nop);
++		       "            %d Spill %spseudo into memory: reject+=3\n",
++		       nop, REG_P (op) ? "" : "Non-");
+ 		  reject += 3;
+ 		  if (VECTOR_MODE_P (mode))
+ 		    {
+--- a/src/gcc/lto/lto-partition.c
++++ b/src/gcc/lto/lto-partition.c
+@@ -447,7 +447,7 @@ add_sorted_nodes (vec<symtab_node *> &next_nodes, ltrans_partition partition)
+    and in-partition calls was reached.  */
+ 
+ void
+-lto_balanced_map (int n_lto_partitions)
++lto_balanced_map (int n_lto_partitions, int max_partition_size)
+ {
+   int n_nodes = 0;
+   int n_varpool_nodes = 0, varpool_pos = 0, best_varpool_pos = 0;
+@@ -511,6 +511,9 @@ lto_balanced_map (int n_lto_partitions)
+   varpool_order.qsort (varpool_node_cmp);
+ 
+   /* Compute partition size and create the first partition.  */
++  if (PARAM_VALUE (MIN_PARTITION_SIZE) > max_partition_size)
++    fatal_error (input_location, "min partition size cannot be greater than max partition size");
++
+   partition_size = total_size / n_lto_partitions;
+   if (partition_size < PARAM_VALUE (MIN_PARTITION_SIZE))
+     partition_size = PARAM_VALUE (MIN_PARTITION_SIZE);
+@@ -719,7 +722,8 @@ lto_balanced_map (int n_lto_partitions)
+ 		 best_cost, best_internal, best_i);
+       /* Partition is too large, unwind into step when best cost was reached and
+ 	 start new partition.  */
+-      if (partition->insns > 2 * partition_size)
++      if (partition->insns > 2 * partition_size
++	  || partition->insns > max_partition_size)
+ 	{
+ 	  if (best_i != i)
+ 	    {
+--- a/src/gcc/lto/lto-partition.h
++++ b/src/gcc/lto/lto-partition.h
+@@ -35,7 +35,7 @@ extern vec<ltrans_partition> ltrans_partitions;
+ 
+ void lto_1_to_1_map (void);
+ void lto_max_map (void);
+-void lto_balanced_map (int);
++void lto_balanced_map (int, int);
+ void lto_promote_cross_file_statics (void);
+ void free_ltrans_partitions (void);
+ void lto_promote_statics_nonwpa (void);
+--- a/src/gcc/lto/lto.c
++++ b/src/gcc/lto/lto.c
+@@ -3123,9 +3123,10 @@ do_whole_program_analysis (void)
+   else if (flag_lto_partition == LTO_PARTITION_MAX)
+     lto_max_map ();
+   else if (flag_lto_partition == LTO_PARTITION_ONE)
+-    lto_balanced_map (1);
++    lto_balanced_map (1, INT_MAX);
+   else if (flag_lto_partition == LTO_PARTITION_BALANCED)
+-    lto_balanced_map (PARAM_VALUE (PARAM_LTO_PARTITIONS));
++    lto_balanced_map (PARAM_VALUE (PARAM_LTO_PARTITIONS),
++		      PARAM_VALUE (MAX_PARTITION_SIZE));
+   else
+     gcc_unreachable ();
+ 
+--- a/src/gcc/match.pd
++++ b/src/gcc/match.pd
+@@ -468,6 +468,12 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
+  (bit_and:c (convert? @0) (convert? (bit_not @0)))
+   { build_zero_cst (type); })
+ 
++/* PR71636: Transform x & ((1U << b) - 1) -> x & ~(~0U << b);  */
++(simplify
++  (bit_and:c @0 (plus:s (lshift:s integer_onep @1) integer_minus_onep))
++  (if (TYPE_UNSIGNED (type))
++    (bit_and @0 (bit_not (lshift { build_all_ones_cst (type); } @1)))))
++
+ /* Fold (A & ~B) - (A & B) into (A ^ B) - B.  */
+ (simplify
+  (minus (bit_and:cs @0 (bit_not @1)) (bit_and:cs @0 @1))
+--- /dev/null
++++ b/src/gcc/memmodel.h
+@@ -0,0 +1,86 @@
++/* Prototypes of memory model helper functions.
++   Copyright (C) 2015-2016 Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it under
++the terms of the GNU General Public License as published by the Free
++Software Foundation; either version 3, or (at your option) any later
++version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_MEMMODEL_H
++#define GCC_MEMMODEL_H
++
++/* Return the memory model from a host integer.  */
++static inline enum memmodel
++memmodel_from_int (unsigned HOST_WIDE_INT val)
++{
++  return (enum memmodel) (val & MEMMODEL_MASK);
++}
++
++/* Return the base memory model from a host integer.  */
++static inline enum memmodel
++memmodel_base (unsigned HOST_WIDE_INT val)
++{
++  return (enum memmodel) (val & MEMMODEL_BASE_MASK);
++}
++
++/* Return TRUE if the memory model is RELAXED.  */
++static inline bool
++is_mm_relaxed (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELAXED;
++}
++
++/* Return TRUE if the memory model is CONSUME.  */
++static inline bool
++is_mm_consume (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_CONSUME;
++}
++
++/* Return TRUE if the memory model is ACQUIRE.  */
++static inline bool
++is_mm_acquire (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQUIRE;
++}
++
++/* Return TRUE if the memory model is RELEASE.  */
++static inline bool
++is_mm_release (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELEASE;
++}
++
++/* Return TRUE if the memory model is ACQ_REL.  */
++static inline bool
++is_mm_acq_rel (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQ_REL;
++}
++
++/* Return TRUE if the memory model is SEQ_CST.  */
++static inline bool
++is_mm_seq_cst (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_SEQ_CST;
++}
++
++/* Return TRUE if the memory model is a SYNC variant.  */
++static inline bool
++is_mm_sync (enum memmodel model)
++{
++  return (model & MEMMODEL_SYNC);
++}
++
++#endif  /* GCC_MEMMODEL_H  */
+--- a/src/gcc/optabs.c
++++ b/src/gcc/optabs.c
+@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "predict.h"
+ #include "tm_p.h"
+ #include "expmed.h"
+--- a/src/gcc/params.def
++++ b/src/gcc/params.def
+@@ -1027,7 +1027,12 @@ DEFPARAM (PARAM_LTO_PARTITIONS,
+ DEFPARAM (MIN_PARTITION_SIZE,
+ 	  "lto-min-partition",
+ 	  "Minimal size of a partition for LTO (in estimated instructions).",
+-	  1000, 0, 0)
++	  10000, 0, 0)
++
++DEFPARAM (MAX_PARTITION_SIZE,
++	  "lto-max-partition",
++	  "Maximal size of a partition for LTO (in estimated instructions).",
++	  1000000, 0, INT_MAX)
+ 
+ /* Diagnostic parameters.  */
+ 
+--- a/src/gcc/rtlanal.c
++++ b/src/gcc/rtlanal.c
+@@ -3663,6 +3663,16 @@ subreg_get_info (unsigned int xregno, machine_mode xmode,
+ 	  info->offset = offset / regsize_xmode;
+ 	  return;
+ 	}
++      /* It's not valid to extract a subreg of mode YMODE at OFFSET that
++	 would go outside of XMODE.  */
++      if (!rknown
++	  && GET_MODE_SIZE (ymode) + offset > GET_MODE_SIZE (xmode))
++	{
++	  info->representable_p = false;
++	  info->nregs = nregs_ymode;
++	  info->offset = offset / regsize_xmode;
++	  return;
++	}
+       /* Quick exit for the simple and common case of extracting whole
+ 	 subregisters from a multiregister value.  */
+       /* ??? It would be better to integrate this into the code below,
+@@ -4590,13 +4600,14 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
+ 	  nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
+ 					  known_x, known_mode, known_ret);
+ 
+-#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
++#ifdef LOAD_EXTEND_OP
+ 	  /* If this is a typical RISC machine, we only have to worry
+ 	     about the way loads are extended.  */
+-	  if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
+-	       ? val_signbit_known_set_p (inner_mode, nonzero)
+-	       : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
+-	      || !MEM_P (SUBREG_REG (x)))
++	  if (WORD_REGISTER_OPERATIONS
++	      && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
++		     ? val_signbit_known_set_p (inner_mode, nonzero)
++		     : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
++		   || !MEM_P (SUBREG_REG (x))))
+ #endif
+ 	    {
+ 	      /* On many CISC machines, accessing an object in a wider mode
+--- a/src/gcc/simplify-rtx.c
++++ b/src/gcc/simplify-rtx.c
+@@ -5274,6 +5274,50 @@ simplify_const_relational_operation (enum rtx_code code,
+ 
+   return 0;
+ }
++
++/* Recognize expressions of the form (X CMP 0) ? VAL : OP (X)
++   where OP is CLZ or CTZ and VAL is the value from CLZ_DEFINED_VALUE_AT_ZERO
++   or CTZ_DEFINED_VALUE_AT_ZERO respectively and return OP (X) if the expression
++   can be simplified to that or NULL_RTX if not.
++   Assume X is compared against zero with CMP_CODE and the true
++   arm is TRUE_VAL and the false arm is FALSE_VAL.  */
++
++static rtx
++simplify_cond_clz_ctz (rtx x, rtx_code cmp_code, rtx true_val, rtx false_val)
++{
++  if (cmp_code != EQ && cmp_code != NE)
++    return NULL_RTX;
++
++  /* Result on X == 0 and X !=0 respectively.  */
++  rtx on_zero, on_nonzero;
++  if (cmp_code == EQ)
++    {
++      on_zero = true_val;
++      on_nonzero = false_val;
++    }
++  else
++    {
++      on_zero = false_val;
++      on_nonzero = true_val;
++    }
++
++  rtx_code op_code = GET_CODE (on_nonzero);
++  if ((op_code != CLZ && op_code != CTZ)
++      || !rtx_equal_p (XEXP (on_nonzero, 0), x)
++      || !CONST_INT_P (on_zero))
++    return NULL_RTX;
++
++  HOST_WIDE_INT op_val;
++  if (((op_code == CLZ
++	&& CLZ_DEFINED_VALUE_AT_ZERO (GET_MODE (on_nonzero), op_val))
++      || (op_code == CTZ
++	  && CTZ_DEFINED_VALUE_AT_ZERO (GET_MODE (on_nonzero), op_val)))
++      && op_val == INTVAL (on_zero))
++    return on_nonzero;
++
++  return NULL_RTX;
++}
++
+ 
+ /* Simplify CODE, an operation with result mode MODE and three operands,
+    OP0, OP1, and OP2.  OP0_MODE was the mode of OP0 before it became
+@@ -5407,6 +5451,19 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
+ 	    }
+ 	}
+ 
++      /* Convert x == 0 ? N : clz (x) into clz (x) when
++	 CLZ_DEFINED_VALUE_AT_ZERO is defined to N for the mode of x.
++	 Similarly for ctz (x).  */
++      if (COMPARISON_P (op0) && !side_effects_p (op0)
++	  && XEXP (op0, 1) == const0_rtx)
++	{
++	  rtx simplified
++	    = simplify_cond_clz_ctz (XEXP (op0, 0), GET_CODE (op0),
++				     op1, op2);
++	  if (simplified)
++	    return simplified;
++	}
++
+       if (COMPARISON_P (op0) && ! side_effects_p (op0))
+ 	{
+ 	  machine_mode cmp_mode = (GET_MODE (XEXP (op0, 0)) == VOIDmode
+--- a/src/gcc/system.h
++++ b/src/gcc/system.h
+@@ -971,7 +971,8 @@ extern void fancy_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
+ 	EXTRA_ADDRESS_CONSTRAINT CONST_DOUBLE_OK_FOR_CONSTRAINT_P	   \
+ 	CALLER_SAVE_PROFITABLE LARGEST_EXPONENT_IS_NORMAL		   \
+ 	ROUND_TOWARDS_ZERO SF_SIZE DF_SIZE XF_SIZE TF_SIZE LIBGCC2_TF_CEXT \
+-	LIBGCC2_LONG_DOUBLE_TYPE_SIZE STRUCT_VALUE EH_FRAME_IN_DATA_SECTION
++	LIBGCC2_LONG_DOUBLE_TYPE_SIZE STRUCT_VALUE			   \
++	EH_FRAME_IN_DATA_SECTION TARGET_FLT_EVAL_METHOD_NON_DEFAULT
+ 
+ /* Hooks that are no longer used.  */
+  #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE	\
+--- a/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c
++++ b/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c
+@@ -29,6 +29,10 @@ int main(int argc, char **argv) {
+   char *sp = child_stack + kStackSize;  /* Stack grows down. */
+   printf("Parent: %p\n", sp);
+   pid_t clone_pid = clone(Child, sp, CLONE_FILES | CLONE_VM, NULL, 0, 0, 0);
++  if (clone_pid == -1) {
++    perror("clone");
++    return 1;
++  }
+   int status;
+   pid_t wait_result = waitpid(clone_pid, &status, __WCLONE);
+   if (wait_result < 0) {
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include "arm-fp16-ops.h"
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -ffast-math" } */
+ 
+ #include "arm-fp16-ops.h"
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-param-1.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-param-1.C
+@@ -1,10 +1,14 @@
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot have parameters of type __fp16.  */
+-extern void f (__fp16);		/* { dg-error "parameters cannot have __fp16 type" } */
+-extern void (*pf) (__fp16);	/* { dg-error "parameters cannot have __fp16 type" } */
++/* Test that the ACLE macro is defined.  */
++#if __ARM_FP16_ARGS != 1
++#error Unexpected value for __ARM_FP16_ARGS
++#endif
++
++/* Test that __fp16 is supported as a parameter type.  */
++extern void f (__fp16);
++extern void (*pf) (__fp16);
+ 
+-/* These should be OK.  */
+ extern void g (__fp16 *);
+ extern void (*pg) (__fp16 *);
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-return-1.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-return-1.C
+@@ -1,10 +1,9 @@
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot return type __fp16.  */
+-extern __fp16 f (void);		/* { dg-error "cannot return __fp16" } */
+-extern __fp16 (*pf) (void);	/* { dg-error "cannot return __fp16" } */
++/* Test that __fp16 is supported as a return type.  */
++extern __fp16 f (void);
++extern __fp16 (*pf) (void);
+ 
+-/* These should be OK.  */
+ extern __fp16 *g (void);
+ extern __fp16 *(*pg) (void);
+--- a/src/gcc/testsuite/g++.dg/inherit/thunk1.C
++++ b/src/gcc/testsuite/g++.dg/inherit/thunk1.C
+@@ -1,4 +1,5 @@
+-// { dg-do run { target i?86-*-* x86_64-*-* s390*-*-* alpha*-*-* ia64-*-* sparc*-*-* } }
++// { dg-do run { target arm*-*-* aarch64*-*-* i?86-*-* x86_64-*-* s390*-*-* alpha*-*-* ia64-*-* sparc*-*-* } }
++// { dg-skip-if "" { arm_thumb1_ok } }
+ 
+ #include <stdarg.h>
+ 
+--- a/src/gcc/testsuite/g++.dg/lto/pr69589_0.C
++++ b/src/gcc/testsuite/g++.dg/lto/pr69589_0.C
+@@ -1,6 +1,8 @@
+ // { dg-lto-do link }
+-// { dg-lto-options "-O2 -rdynamic" } 
++// { dg-lto-options "-O2 -rdynamic" }
+ // { dg-extra-ld-options "-r -nostdlib" }
++// { dg-skip-if "Skip targets without -rdynamic support" { arm*-none-eabi aarch64*-*-elf } { "*" } { "" } }
++
+ #pragma GCC visibility push(hidden)
+ struct A { int &operator[] (long); };
+ template <typename> struct B;
+--- /dev/null
++++ b/src/gcc/testsuite/g++.dg/opt/pr78201.C
+@@ -0,0 +1,13 @@
++// PR middle-end/78201
++// { dg-do compile }
++// { dg-options "-O2" }
++
++struct B { long d (); } *c;
++long e;
++
++void
++foo ()
++{
++  char a[e] = "";
++  c && c->d();
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr71295.c
+@@ -0,0 +1,12 @@
++extern void fn2 (long long);
++int a;
++
++void
++fn1 ()
++{
++  long long b[3];
++  a = 0;
++  for (; a < 3; a++)
++    b[a] = 1;
++  fn2 (b[1]);
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr78362.c
+@@ -0,0 +1,11 @@
++/* PR target/78362.  */
++
++long a;
++
++void
++foo (void)
++{
++  for (;; a--)
++    if ((int) a)
++      break;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr78694.c
+@@ -0,0 +1,118 @@
++/* PR target/78694.  */
++
++enum
++{
++  MEMMODEL_RELAXED,
++  MEMMODEL_ACQUIRE,
++  PRIORITY_INSERT_END
++};
++enum
++{
++  PQ_CHILDREN,
++  PQ_TASKGROUP
++};
++struct gomp_team_state
++{
++  struct gomp_team *team;
++};
++enum gomp_task_kind
++{
++  GOMP_TASK_UNDEFERRED,
++  GOMP_TASK_WAITING
++};
++struct gomp_taskwait
++{
++  _Bool in_taskwait;
++};
++struct gomp_task
++{
++  struct gomp_task *parent;
++  int children_queue;
++  struct gomp_taskgroup *taskgroup;
++  int dependers;
++  struct gomp_taskwait taskwait;
++  enum gomp_task_kind kind;
++  _Bool in_tied_task;
++} j, q, *n;
++struct gomp_taskgroup
++{
++  _Bool in_taskgroup_wait;
++  int num_children;
++} l;
++struct gomp_team
++{
++  int task_queue;
++  int task_running_count;
++};
++struct gomp_thread
++{
++  struct gomp_team_state ts;
++  struct gomp_task task;
++} extern __thread a;
++
++int b, c, d, e, f, g, h, i, k, m, o, p, r;
++
++void priority_queue_next_task (struct gomp_task *, int, int);
++int gomp_task_run_pre (struct gomp_task *, struct gomp_task, struct gomp_team);
++void priority_queue_insert (int, struct gomp_task);
++void priority_queue_insert2 (int, struct gomp_task, int, int, int);
++void priority_queue_insert3 (int, struct gomp_task, int, int, int);
++void gomp_sem_post (int);
++void free (void *);
++
++_Bool s;
++int
++GOMP_taskgroup_end ()
++{
++  struct gomp_thread *t = &a;
++  struct gomp_team u = *t->ts.team;
++  struct gomp_task *v = &t->task, *w;
++  if (__atomic_load_n (&l.num_children, MEMMODEL_ACQUIRE))
++    while (1)
++      {
++	if (l.num_children)
++	  priority_queue_next_task (v, u.task_queue, r);
++	else if (w)
++	  free (w);
++	if (n->kind == GOMP_TASK_WAITING)
++	  {
++	    s = gomp_task_run_pre (n, q, u);
++	    if (__builtin_expect (s, 0))
++	      {
++		if (w)
++		  free (w);
++		goto finish_cancelled;
++	      }
++	    n = 0;
++	    l.in_taskgroup_wait = 1;
++	  }
++	if (w)
++	  {
++	    t->task = *n;
++	    if (__builtin_expect (p, 0))
++	      if (o)
++		t->task = *v;
++	  }
++	if (n)
++	  {
++	    struct gomp_task x = x;
++	    for (; i; b++)
++	      {
++		struct gomp_task y = j;
++		if (g)
++		  continue;
++		priority_queue_insert (PQ_CHILDREN, x);
++		if (x.taskwait.in_taskwait)
++		  priority_queue_insert2 (PQ_TASKGROUP, y, e, 0, d);
++		if (h)
++		  gomp_sem_post (f);
++		priority_queue_insert3 (k, y, PRIORITY_INSERT_END, 0, d);
++		++c;
++	      }
++	  }
++      finish_cancelled:
++	w = (struct gomp_task *) (n - u.task_running_count - v);
++      }
++  v->taskgroup = (struct gomp_taskgroup *) m;
++  return 1;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr37780.c
+@@ -0,0 +1,49 @@
++/* PR middle-end/37780.  */
++
++#define VAL (8 * sizeof (int))
++
++int __attribute__ ((noinline, noclone))
++fooctz (int i)
++{
++  return (i == 0) ? VAL : __builtin_ctz (i);
++}
++
++int __attribute__ ((noinline, noclone))
++fooctz2 (int i)
++{
++  return (i != 0) ? __builtin_ctz (i) : VAL;
++}
++
++unsigned int __attribute__ ((noinline, noclone))
++fooctz3 (unsigned int i)
++{
++  return (i > 0) ?  __builtin_ctz (i) : VAL;
++}
++
++int __attribute__ ((noinline, noclone))
++fooclz (int i)
++{
++  return (i == 0) ? VAL : __builtin_clz (i);
++}
++
++int __attribute__ ((noinline, noclone))
++fooclz2 (int i)
++{
++  return (i != 0) ? __builtin_clz (i) : VAL;
++}
++
++unsigned int __attribute__ ((noinline, noclone))
++fooclz3 (unsigned int i)
++{
++  return (i > 0) ? __builtin_clz (i) : VAL;
++}
++
++int
++main (void)
++{
++  if (fooctz (0) != VAL || fooctz2 (0) != VAL || fooctz3 (0) != VAL
++      || fooclz (0) != VAL || fooclz2 (0) != VAL || fooclz3 (0) != VAL)
++    __builtin_abort ();
++
++  return 0;
++}
+\ No newline at end of file
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr66940.c
+@@ -0,0 +1,20 @@
++long long __attribute__ ((noinline, noclone))
++foo (long long ival)
++{
++ if (ival <= 0)
++    return -0x7fffffffffffffffL - 1;
++
++ return 0x7fffffffffffffffL;
++}
++
++int
++main (void)
++{
++  if (foo (-1) != (-0x7fffffffffffffffL - 1))
++    __builtin_abort ();
++
++  if (foo (1) != 0x7fffffffffffffffL)
++    __builtin_abort ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.dg/asr_div1.c
++++ b/src/gcc/testsuite/gcc.dg/asr_div1.c
+@@ -1,6 +1,7 @@
+ /* Test division by const int generates only one shift.  */
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fdump-rtl-combine-all" } */
++/* { dg-options "-O2 -fdump-rtl-combine-all -mtune=cortex-a53" { target aarch64*-*-* } } */
+ 
+ extern void abort (void);
+ 
+--- a/src/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
++++ b/src/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
+@@ -24,7 +24,7 @@
+ 			 | FE_OVERFLOW		\
+ 			 | FE_UNDERFLOW)
+ 
+-#if defined __alpha__
++#if defined __alpha__ || defined __aarch64__
+   #define ITER_COUNT 100
+ #else
+   #define ITER_COUNT 10000
+--- a/src/gcc/testsuite/gcc.dg/cpp/trad/include.c
++++ b/src/gcc/testsuite/gcc.dg/cpp/trad/include.c
+@@ -2,11 +2,5 @@
+ 
+ /* Test that macros are not expanded in the <> quotes of #inlcude.  */
+ 
+-/* vxWorksCommon.h uses the "#" operator to construct the name of an
+-   include file, thus making the file incompatible with -traditional-cpp.
+-   Newlib uses ## when including stdlib.h as of 2007-09-07.  */
+-/* { dg-do preprocess { target { { ! vxworks_kernel } && { ! newlib } } } } */
+-
+-#define __STDC__ 1		/* Stop complaints about non-ISO compilers.  */
+-#define stdlib 1
+-#include <stdlib.h>		/* { dg-bogus "o such file or directory" } */
++#define builtins 1
++#include <builtins.h>		/* { dg-bogus "o such file or directory" } */
+--- a/src/gcc/testsuite/gcc.dg/cpp/trad/trad.exp
++++ b/src/gcc/testsuite/gcc.dg/cpp/trad/trad.exp
+@@ -29,7 +29,7 @@ load_lib gcc-dg.exp
+ # If a testcase doesn't have special options, use these.
+ global DEFAULT_TRADCPPFLAGS
+ if ![info exists DEFAULT_TRADCPPFLAGS] then {
+-    set DEFAULT_TRADCPPFLAGS " -traditional-cpp"
++    set DEFAULT_TRADCPPFLAGS " -traditional-cpp -I$srcdir/$subdir/"
+ }
+ 
+ # Initialize `dg'.
+--- a/src/gcc/testsuite/gcc.dg/cpp/warn-undef-2.c
++++ b/src/gcc/testsuite/gcc.dg/cpp/warn-undef-2.c
+@@ -1,5 +1,5 @@
+ // { dg-do preprocess }
+ // { dg-options "-std=gnu99 -fdiagnostics-show-option -Werror=undef" }
+ /* { dg-message "some warnings being treated as errors" "" {target "*-*-*"} 0 } */
+-#if x  // { dg-error "\"x\" is not defined .-Werror=undef." }
++#if x  // { dg-error "\"x\" is not defined, evaluates to 0 .-Werror=undef." }
+ #endif
+--- a/src/gcc/testsuite/gcc.dg/cpp/warn-undef.c
++++ b/src/gcc/testsuite/gcc.dg/cpp/warn-undef.c
+@@ -1,5 +1,5 @@
+ // { dg-do preprocess }
+ // { dg-options "-std=gnu99 -fdiagnostics-show-option -Wundef" }
+ 
+-#if x  // { dg-warning "\"x\" is not defined .-Wundef." }
++#if x  // { dg-warning "\"x\" is not defined, evaluates to 0 .-Wundef." }
+ #endif
+--- a/src/gcc/testsuite/gcc.dg/lto/pr54709_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/pr54709_0.c
+@@ -1,6 +1,7 @@
+ /* { dg-lto-do link } */
+ /* { dg-require-visibility "hidden" } */
+ /* { dg-require-effective-target fpic } */
++/* { dg-require-effective-target shared } */
+ /* { dg-extra-ld-options { -shared } } */
+ /* { dg-lto-options { { -fPIC -fvisibility=hidden -flto } } } */
+ 
+--- a/src/gcc/testsuite/gcc.dg/lto/pr61526_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/pr61526_0.c
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target fpic } */
++/* { dg-require-effective-target shared } */
+ /* { dg-lto-do link } */
+ /* { dg-lto-options { { -fPIC -flto -flto-partition=1to1 } } } */
+ /* { dg-extra-ld-options { -shared } } */
+--- a/src/gcc/testsuite/gcc.dg/lto/pr64415_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/pr64415_0.c
+@@ -1,5 +1,6 @@
+ /* { dg-lto-do link } */
+ /* { dg-require-effective-target fpic } */
++/* { dg-require-effective-target shared } */
+ /* { dg-lto-options { { -O -flto -fpic } } } */
+ /* { dg-extra-ld-options { -shared } } */
+ /* { dg-extra-ld-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */
+--- a/src/gcc/testsuite/gcc.dg/plugin/plugin.exp
++++ b/src/gcc/testsuite/gcc.dg/plugin/plugin.exp
+@@ -87,6 +87,12 @@ foreach plugin_test $plugin_test_list {
+     if ![runtest_file_p $runtests $plugin_src] then {
+         continue
+     }
++    # Skip tail call tests on targets that do not have sibcall_epilogue.
++    if {[regexp ".*must_tail_call_plugin.c" $plugin_src]
++	&& [istarget arm*-*-*]
++	&& [check_effective_target_arm_thumb1]} then {
++	continue
++    }
+     set plugin_input_tests [lreplace $plugin_test 0 0]
+     plugin-test-execute $plugin_src $plugin_input_tests
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr59833.c
+@@ -0,0 +1,18 @@
++/* { dg-do run { target { *-*-linux* *-*-gnu* } } } */
++/* { dg-options "-O0 -lm" } */
++/* { dg-require-effective-target issignaling } */
++
++#define _GNU_SOURCE
++#include <math.h>
++
++int main (void)
++{
++  float sNaN = __builtin_nansf ("");
++  double x = (double) sNaN;
++  if (issignaling(x))
++  {
++    __builtin_abort();
++  }
++
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr68217.c
+@@ -0,0 +1,14 @@
++
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-vrp1" } */
++
++int foo (void)
++{
++    volatile int a = -1;
++    long long b = (1LL << (sizeof (b) * 8 - 1)); // LLONG_MIN
++    long long x = (a & b); // x == 0x8000000000000000
++    if (x < 1LL) { ; } else { __builtin_abort(); }
++    return 0;
++}
++
++/* { dg-final { scan-tree-dump "\\\[-INF, 0\\\]" "vrp1" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr71636-1.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-fdump-tree-gimple" } */
++
++unsigned f(unsigned x, unsigned b)
++{
++  return x & ((1U << b) - 1);
++}
++
++/* { dg-final { scan-tree-dump-not "1 <<" "gimple" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr71636-2.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-forwprop-details" } */
++
++unsigned f(unsigned x, unsigned b)
++{
++  unsigned t1 = 1U << b;
++  unsigned t2 = t1 - 1;
++  unsigned t3 = x & t2;
++  return t3;
++}
++
++/* { dg-final { scan-tree-dump "_\[0-9\] = ~_\[0-9\]" "forwprop1" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-20.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-20.c
+@@ -86,9 +86,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-21.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-21.c
+@@ -57,9 +57,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 3 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-22.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-22.c
+@@ -31,9 +31,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 4 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-22g.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-22g.c
+@@ -5,9 +5,9 @@
+ #define USE_GNU
+ #include "strlenopt-22.c"
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 0 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 1 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-26.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-26.c
+@@ -21,4 +21,5 @@ main (void)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-5.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-5.c
+@@ -48,9 +48,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 0 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 2 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-7.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-7.c
+@@ -40,11 +40,11 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 0 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "\\*r_\[0-9\]* = 0;" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "return 3;" 1 "optimized" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-9.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-9.c
+@@ -98,10 +98,10 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 5 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 6 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 3 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "return 4;" 1 "optimized" } } */
+--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c
++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c
+@@ -1,5 +1,6 @@
+ /* Test floating-point conversions.  Standard types and __fp16.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok }
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include "fp-int-convert.h"
+--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c
++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok }
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include "arm-fp16-ops.h"
+--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c
++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok }
+ /* { dg-options "-mfp16-format=alternative -ffast-math" } */
+ 
+ #include "arm-fp16-ops.h"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/torture/pr71594.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "--param max-rtl-if-conversion-insns=2" } */
++
++unsigned short a;
++int b, c;
++int *d;
++void fn1() {
++  *d = 24;
++  for (; *d <= 65;) {
++    unsigned short *e = &a;
++    b = (a &= 0 <= 0) < (c ?: (*e %= *d));
++    for (; *d <= 83;)
++      ;
++  }
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_1.c
+@@ -0,0 +1,44 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do run } */
++/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-optimized" } */
++/* { dg-require-effective-target int32plus } */
++
++__attribute__ ((noinline))
++int foo ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) >> (1LU <= b);
++  if (c == 486097858)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++__attribute__ ((noinline))
++int bar ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) >> (b ? 2 : 3);
++  if (c == 243048929)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++int main ()
++{
++  foo ();
++  bar ();
++}
++
++/* Scan for c = 972195717) >> [0, 1] in function foo.  */
++/* { dg-final { scan-tree-dump-times "486097858 : 972195717" 1  "vrp1" } } */
++/* Scan for c = 972195717) >> [2, 3] in function bar.  */
++/* { dg-final { scan-tree-dump-times "243048929 : 121524464" 2  "vrp1" } } */
++/* { dg-final { scan-tree-dump-times "486097858" 0  "optimized" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_2.c
+@@ -0,0 +1,54 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-vrp1" } */
++/* { dg-require-effective-target int32plus } */
++
++__attribute__ ((noinline))
++int foo ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) / (b ? 1 : 0);
++  if (c == 972195717)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++__attribute__ ((noinline))
++int bar ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) % (b ? 1 : 0);
++  if (c == 972195717)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++__attribute__ ((noinline))
++int bar2 ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195716) % (b ? 1 : 2);
++  if (c == 972195715)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++
++/* Dont optimize 972195717 / 0 in function foo.  */
++/* { dg-final { scan-tree-dump-times "972195717 / _" 1  "vrp1" } } */
++/* Dont optimize 972195717 % 0 in function bar.  */
++/* { dg-final { scan-tree-dump-times "972195717 % _" 1 "vrp1" } } */
++/* Optimize in function bar2.  */
++/* { dg-final { scan-tree-dump-times "972195715 % _" 0 "vrp1" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_3.c
+@@ -0,0 +1,26 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do run } */
++/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-optimized" } */
++
++__attribute__ ((noinline))
++int foo (int a, unsigned b)
++{
++  int c = 1;
++  b =  a ? 12 : 13;
++  c = b << 8;
++  if (c == 3072)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++int main ()
++{
++  volatile unsigned b = 1U;
++  foo (-1, b);
++}
++
++/* Scan for c [12, 13] << 8 in function foo.  */
++/* { dg-final { scan-tree-dump-times "3072 : 3328" 2  "vrp1" } } */
++/* { dg-final { scan-tree-dump-times "3072" 0  "optimized" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_4.c
+@@ -0,0 +1,28 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do run } */
++/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-optimized" } */
++/* { dg-require-effective-target int32plus } */
++
++__attribute__ ((noinline))
++int foo (int a, unsigned b)
++{
++  unsigned c = 1;
++  if (b >= 1 && b <= ((unsigned)(-1) - 1))
++    return 0;
++  c = b >> 4;
++  if (c == 268435455)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++int main ()
++{
++  volatile unsigned b = (unsigned)(-1);
++  foo (-1, b);
++}
++
++/* Scan for ~[1, 4294967294] >> 4 in function foo.  */
++/* { dg-final { scan-tree-dump-times "0 : 268435455" 1  "vrp1" } } */
++/* { dg-final { scan-tree-dump-times "268435455" 0  "optimized" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/scev-11.c
+@@ -0,0 +1,28 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++
++int a[128];
++extern int b[];
++
++int bar (int *);
++
++int
++foo (int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    {
++      unsigned char uc = (unsigned char)i;
++      a[i] = i;
++      b[uc] = 0;
++    }
++
++  bar (a);
++  return 0;
++}
++
++/* Address of array reference to b is scev.  */
++/* { dg-final { scan-tree-dump-times "use \[0-9\]\n  address" 2 "ivopts" } } */
++
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/scev-12.c
+@@ -0,0 +1,30 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++
++int a[128];
++extern int b[];
++
++int bar (int *);
++
++int
++foo (int x, int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    {
++      unsigned char uc = (unsigned char)i;
++      if (x)
++	a[i] = i;
++      b[uc] = 0;
++    }
++
++  bar (a);
++  return 0;
++}
++
++/* Address of array reference to b is not scev.  */
++/* { dg-final { scan-tree-dump-times "use \[0-9\]\n  address" 1 "ivopts" } } */
++
++
++
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-2.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-2.c
+@@ -25,6 +25,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -45,6 +46,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 8 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 1 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 8 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -60,6 +62,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and 1 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and 16 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[1-9\]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[1-9\]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+@@ -78,6 +81,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -96,6 +100,7 @@ f5 (int i, ...)
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -116,6 +121,7 @@ f6 (int i, ...)
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 24 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 3 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 24 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -133,6 +139,7 @@ f7 (int i, ...)
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -152,6 +159,7 @@ f8 (int i, ...)
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -169,6 +177,7 @@ f9 (int i, ...)
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -188,6 +197,7 @@ f10 (int i, ...)
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -208,6 +218,7 @@ f11 (int i, ...)
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save 24 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save 3 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save 24 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -228,6 +239,7 @@ f12 (int i, ...)
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 24 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 0 GPR units and 3 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 0 GPR units and 48 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -248,6 +260,7 @@ f13 (int i, ...)
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 24 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 0 GPR units and 3 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 0 GPR units and 48 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -268,6 +281,7 @@ f14 (int i, ...)
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[148\] GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save 24 GPR units and 3" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save 1 GPR units and 2 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save 8 GPR units and 32 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -291,6 +305,7 @@ f15 (int i, ...)
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 0, needs to save \[148\] GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 0, needs to save \[148\] GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 0, needs to save 1 GPR units and 2 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f15: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ /* We may be able to improve upon this after fixing PR66010/PR66013.  */
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-3.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-3.c
+@@ -24,6 +24,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -39,6 +40,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -57,6 +59,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -73,6 +76,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -89,6 +93,7 @@ f5 (int i, ...)
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -107,6 +112,7 @@ f6 (int i, ...)
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -123,6 +129,7 @@ f7 (int i, ...)
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -139,6 +146,7 @@ f8 (int i, ...)
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -155,6 +163,7 @@ f10 (int i, ...)
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -171,6 +180,7 @@ f11 (int i, ...)
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -187,6 +197,7 @@ f12 (int i, ...)
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-4.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-4.c
+@@ -27,6 +27,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -44,6 +45,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 0 GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 0 GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 0 GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -67,6 +69,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 1 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -88,6 +91,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 8 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 0 GPR units and 1 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 0 GPR units and 16 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-5.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-5.c
+@@ -25,6 +25,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f2 (int i, ...)
+@@ -38,6 +39,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and all FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ /* Here va_arg can be executed at most as many times as va_start.  */
+ void
+@@ -56,6 +58,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 32 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 1 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f4 (int i, ...)
+@@ -74,6 +77,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 16 GPR units and 16 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 24 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 2 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 24 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f5 (int i, ...)
+@@ -88,6 +92,7 @@ f5 (int i, ...)
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save 16 GPR units and 0 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save 32 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save (4|2) GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save 16 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f6 (int i, ...)
+@@ -102,6 +107,7 @@ f6 (int i, ...)
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 8 GPR units and 32 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 32 GPR units and 3" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|2) GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 8 GPR units and 32 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f7 (int i, ...)
+@@ -116,3 +122,4 @@ f7 (int i, ...)
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 0 GPR units and 64 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 32 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 2 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 0 GPR units and 64 FPR units" "stdarg" { target aarch64*-*-* } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-6.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-6.c
+@@ -30,6 +30,7 @@ bar (int x, char const *y, ...)
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-vect-70.c
+@@ -0,0 +1,33 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target section_anchors } */
++/* { dg-require-effective-target vect_int } */
++
++#define N 32
++
++/* Increase alignment of struct if an array's offset is multiple of alignment of
++   vector type corresponding to it's scalar type.
++   For the below test-case:
++   offsetof(e) == 8 bytes. 
++   i) For arm: let x = alignment of vector type corresponding to int,
++   x == 8 bytes.
++   Since offsetof(e) % x == 0, set DECL_ALIGN(a, b, c) to x.
++   ii) For aarch64, ppc: x == 16 bytes.
++   Since offsetof(e) % x != 0, don't increase alignment of a, b, c.
++*/
++
++static struct A {
++  int p1, p2;
++  int e[N];
++} a, b, c;
++
++int foo(void)
++{
++  for (int i = 0; i < N; i++)
++    a.e[i] = b.e[i] + c.e[i];
++
++   return a.e[0];
++}
++
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target aarch64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target powerpc64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 3 "increase_alignment" { target arm*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-vect-71.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target section_anchors } */
++/* { dg-require-effective-target vect_int } */
++
++/* Should not increase alignment of the struct because
++   sizeof (A.e) < sizeof(corresponding vector type).  */
++
++#define N 3
++
++static struct A {
++  int p1, p2;
++  int e[N];
++} a, b, c;
++
++int foo(void)
++{
++  for (int i = 0; i < N; i++)
++    a.e[i] = b.e[i] + c.e[i];
++
++   return a.e[0];
++}
++
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target aarch64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target powerpc64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target arm*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-vect-72.c
+@@ -0,0 +1,29 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target section_anchors } */
++/* { dg-require-effective-target vect_int } */
++
++#define N 32
++
++/* Clone of section-anchors-vect-70.c having nested struct.  */
++
++struct S
++{
++  int e[N];
++};
++
++static struct A {
++  int p1, p2;
++  struct S s; 
++} a, b, c;
++
++int foo(void)
++{
++  for (int i = 0; i < N; i++)
++    a.s.e[i] = b.s.e[i] + c.s.e[i];
++
++   return a.s.e[0];
++}
++
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target aarch64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target powerpc64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 3 "increase_alignment" { target arm*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/pr57206.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target vect_float } */
++
++void bad0(float * d, unsigned int n)
++{
++  unsigned int i;
++  for (i=n; i>0; --i) 
++    d[n-i] = 0.0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/pr65951.c
+@@ -0,0 +1,63 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 512
++
++/* These multiplications should be vectorizable with additions when
++   no vector shift is available.  */
++
++__attribute__ ((noinline)) void
++foo (int *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= 2;
++}
++
++__attribute__ ((noinline)) void
++foo2 (int *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= 4;
++}
++
++int
++main (void)
++{
++  check_vect ();
++  int data[N];
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / 2 != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo2 (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / 4 != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/pr71818.c
+@@ -0,0 +1,16 @@
++/* { dg-do compile } */
++
++char a;
++short b;
++int c, d;
++void fn1() {
++  char e = 75, g;
++  unsigned char *f = &e;
++  a = 21;
++  for (; a <= 48; a++) {
++    for (; e <= 6;)
++      ;
++    g -= e -= b || g <= c;
++  }
++  d = *f;
++}
+--- a/src/gcc/testsuite/gcc.dg/vect/vect-iv-9.c
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-iv-9.c
+@@ -33,5 +33,4 @@ int main (void)
+   return 0;
+ } 
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_int_mult } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {! vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-load-lanes-peeling-1.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_load_lanes } */
++
++void
++f (int *__restrict a, int *__restrict b)
++{
++  for (int i = 0; i < 96; ++i)
++    a[i] = b[i * 3] + b[i * 3 + 1] + b[i * 3 + 2];
++}
++
++/* { dg-final { scan-tree-dump-not "Data access with gaps" "vect" } } */
++/* { dg-final { scan-tree-dump-not "epilog loop required" "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c
+@@ -0,0 +1,41 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 256
++
++__attribute__ ((noinline)) void
++foo (long long *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= 123;
++}
++
++int
++main (void)
++{
++  check_vect ();
++  long long data[N];
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / 123 != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect"  { target aarch64*-*-* } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target aarch64*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c
+@@ -0,0 +1,40 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 256
++
++__attribute__ ((noinline)) void
++foo (long long *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= -19594LL;
++}
++
++int
++main (void)
++{
++  check_vect ();
++  long long data[N];
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / -19594LL != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect"  { target aarch64*-*-* } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target aarch64*-*-* } } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp
+@@ -53,7 +53,10 @@ torture-init
+ set-torture-options $C_TORTURE_OPTIONS {{}} $LTO_TORTURE_OPTIONS
+ 
+ # Make sure Neon flags are provided, if necessary.  Use fp16 if we can.
+-if {[check_effective_target_arm_neon_fp16_ok]} then {
++# Use fp16 arithmetic operations if the hardware supports it.
++if {[check_effective_target_arm_v8_2a_fp16_neon_hw]} then {
++  set additional_flags [add_options_for_arm_v8_2a_fp16_neon ""]
++} elseif {[check_effective_target_arm_neon_fp16_ok]} then {
+   set additional_flags [add_options_for_arm_neon_fp16 ""]
+ } else {
+   set additional_flags [add_options_for_arm_neon ""]
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+@@ -16,6 +16,14 @@ extern void *memset(void *, int, size_t);
+ extern void *memcpy(void *, const void *, size_t);
+ extern size_t strlen(const char *);
+ 
++/* Helper macro to select FP16 tests.  */
++#if (defined (__ARM_FP16_FORMAT_IEEE) \
++     || defined (__ARM_FP16_FORMAT_ALTERNATIVE))
++#define FP16_SUPPORTED (1)
++#else
++#undef FP16_SUPPORTED
++#endif
++
+ /* Various string construction helpers.  */
+ 
+ /*
+@@ -24,6 +32,13 @@ extern size_t strlen(const char *);
+    VECT_VAR(expected, int, 16, 4) -> expected_int16x4
+    VECT_VAR_DECL(expected, int, 16, 4) -> int16x4_t expected_int16x4
+ */
++/* Some instructions don't exist on ARM.
++   Use this macro to guard against them.  */
++#ifdef __aarch64__
++#define AARCH64_ONLY(X) X
++#else
++#define AARCH64_ONLY(X)
++#endif
+ 
+ #define xSTR(X) #X
+ #define STR(X) xSTR(X)
+@@ -81,7 +96,7 @@ extern size_t strlen(const char *);
+ 	  abort();							\
+ 	}								\
+       }									\
+-    fprintf(stderr, "CHECKED %s\n", MSG);				\
++    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
+   }
+ 
+ /* Floating-point variant.  */
+@@ -110,7 +125,36 @@ extern size_t strlen(const char *);
+ 	  abort();							\
+ 	}								\
+       }									\
+-    fprintf(stderr, "CHECKED %s\n", MSG);				\
++    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
++  }
++
++/* poly variant.  */
++#define CHECK_POLY(MSG,T,W,N,FMT,EXPECTED,COMMENT)			\
++  {									\
++    int i;								\
++    for(i=0; i<N ; i++)							\
++      {									\
++	union poly_operand {						\
++	  uint##W##_t i;						\
++	  poly##W##_t p;						\
++	} tmp_res, tmp_exp;						\
++	tmp_res.p = VECT_VAR(result, T, W, N)[i];			\
++	tmp_exp.i = VECT_VAR(EXPECTED, T, W, N)[i];			\
++	if (tmp_res.i != tmp_exp.i) {					\
++	  fprintf(stderr,						\
++		  "ERROR in %s (%s line %d in buffer '%s') at type %s "	\
++		  "index %d: got 0x%" FMT " != 0x%" FMT " %s\n",	\
++		  MSG, __FILE__, __LINE__,				\
++		  STR(EXPECTED),					\
++		  STR(VECT_NAME(T, W, N)),				\
++		  i,							\
++		  tmp_res.i,						\
++		  tmp_exp.i,						\
++		  strlen(COMMENT) > 0 ? COMMENT : "");			\
++	  abort();							\
++	}								\
++      }									\
++    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
+   }
+ 
+ /* Clean buffer with a non-zero pattern to help diagnose buffer
+@@ -133,10 +177,16 @@ static ARRAY(result, uint, 32, 2);
+ static ARRAY(result, uint, 64, 1);
+ static ARRAY(result, poly, 8, 8);
+ static ARRAY(result, poly, 16, 4);
++#if defined (__ARM_FEATURE_CRYPTO)
++static ARRAY(result, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ static ARRAY(result, float, 16, 4);
+ #endif
+ static ARRAY(result, float, 32, 2);
++#ifdef __aarch64__
++static ARRAY(result, float, 64, 1);
++#endif
+ static ARRAY(result, int, 8, 16);
+ static ARRAY(result, int, 16, 8);
+ static ARRAY(result, int, 32, 4);
+@@ -147,6 +197,9 @@ static ARRAY(result, uint, 32, 4);
+ static ARRAY(result, uint, 64, 2);
+ static ARRAY(result, poly, 8, 16);
+ static ARRAY(result, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++static ARRAY(result, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ static ARRAY(result, float, 16, 8);
+ #endif
+@@ -169,6 +222,7 @@ extern ARRAY(expected, poly, 8, 8);
+ extern ARRAY(expected, poly, 16, 4);
+ extern ARRAY(expected, hfloat, 16, 4);
+ extern ARRAY(expected, hfloat, 32, 2);
++extern ARRAY(expected, hfloat, 64, 1);
+ extern ARRAY(expected, int, 8, 16);
+ extern ARRAY(expected, int, 16, 8);
+ extern ARRAY(expected, int, 32, 4);
+@@ -193,8 +247,8 @@ extern ARRAY(expected, hfloat, 64, 2);
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+ 									\
+     CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment);		\
+@@ -205,8 +259,8 @@ extern ARRAY(expected, hfloat, 64, 2);
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 2, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment);	\
+   }									\
+ 
+@@ -335,7 +389,8 @@ extern int VECT_VAR(expected_cumulative_sat, uint, 64, 2);
+ 	      strlen(COMMENT) > 0 ? " " COMMENT : "");			\
+       abort();								\
+     }									\
+-    fprintf(stderr, "CHECKED CUMULATIVE SAT %s\n", MSG);		\
++    fprintf(stderr, "CHECKED CUMULATIVE SAT %s %s\n",			\
++	    STR(VECT_TYPE(T, W, N)), MSG);				\
+   }
+ 
+ #define CHECK_CUMULATIVE_SAT_NAMED(test_name,EXPECTED,comment)		\
+@@ -379,6 +434,9 @@ static void clean_results (void)
+   CLEAN(result, uint, 64, 1);
+   CLEAN(result, poly, 8, 8);
+   CLEAN(result, poly, 16, 4);
++#if defined (__ARM_FEATURE_CRYPTO)
++  CLEAN(result, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CLEAN(result, float, 16, 4);
+ #endif
+@@ -394,6 +452,9 @@ static void clean_results (void)
+   CLEAN(result, uint, 64, 2);
+   CLEAN(result, poly, 8, 16);
+   CLEAN(result, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++  CLEAN(result, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CLEAN(result, float, 16, 8);
+ #endif
+@@ -419,6 +480,13 @@ static void clean_results (void)
+ #define DECL_VARIABLE(VAR, T1, W, N)		\
+   VECT_TYPE(T1, W, N) VECT_VAR(VAR, T1, W, N)
+ 
++#if defined (__ARM_FEATURE_CRYPTO)
++#define DECL_VARIABLE_CRYPTO(VAR, T1, W, N) \
++  DECL_VARIABLE(VAR, T1, W, N)
++#else
++#define DECL_VARIABLE_CRYPTO(VAR, T1, W, N)
++#endif
++
+ /* Declare only 64 bits signed variants.  */
+ #define DECL_VARIABLE_64BITS_SIGNED_VARIANTS(VAR)	\
+   DECL_VARIABLE(VAR, int, 8, 8);			\
+@@ -454,6 +522,7 @@ static void clean_results (void)
+   DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 8);		\
+   DECL_VARIABLE(VAR, poly, 16, 4);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 1);	\
+   DECL_VARIABLE(VAR, float, 16, 4);		\
+   DECL_VARIABLE(VAR, float, 32, 2)
+ #else
+@@ -462,6 +531,7 @@ static void clean_results (void)
+   DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 8);		\
+   DECL_VARIABLE(VAR, poly, 16, 4);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 1);	\
+   DECL_VARIABLE(VAR, float, 32, 2)
+ #endif
+ 
+@@ -472,6 +542,7 @@ static void clean_results (void)
+   DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 16);		\
+   DECL_VARIABLE(VAR, poly, 16, 8);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 2);	\
+   DECL_VARIABLE(VAR, float, 16, 8);		\
+   DECL_VARIABLE(VAR, float, 32, 4)
+ #else
+@@ -480,6 +551,7 @@ static void clean_results (void)
+   DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 16);		\
+   DECL_VARIABLE(VAR, poly, 16, 8);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 2);	\
+   DECL_VARIABLE(VAR, float, 32, 4)
+ #endif
+ /* Declare all variants.  */
+@@ -500,15 +572,6 @@ static void clean_results (void)
+ /* Helpers to initialize vectors.  */
+ #define VDUP(VAR, Q, T1, T2, W, N, V)			\
+   VECT_VAR(VAR, T1, W, N) = vdup##Q##_n_##T2##W(V)
+-#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-/* Work around that there is no vdup_n_f16 intrinsic.  */
+-#define vdup_n_f16(VAL)		\
+-  __extension__			\
+-    ({				\
+-      float16_t f = VAL;	\
+-      vld1_dup_f16(&f);		\
+-    })
+-#endif
+ 
+ #define VSET_LANE(VAR, Q, T1, T2, W, N, L, V)				\
+   VECT_VAR(VAR, T1, W, N) = vset##Q##_lane_##T2##W(V,			\
+@@ -521,6 +584,13 @@ static void clean_results (void)
+ 
+ /* Helpers to call macros with 1 constant and 5 variable
+    arguments.  */
++#if defined (__ARM_FEATURE_CRYPTO)
++#define MACRO_CRYPTO(MACRO, VAR1, VAR2, T1, T2, T3, W, N) \
++  MACRO(VAR1, VAR2, T1, T2, T3, W, N)
++#else
++#define MACRO_CRYPTO(MACRO, VAR1, VAR2, T1, T2, T3, W, N)
++#endif
++
+ #define TEST_MACRO_64BITS_SIGNED_VARIANTS_1_5(MACRO, VAR)	\
+   MACRO(VAR, , int, s, 8, 8);					\
+   MACRO(VAR, , int, s, 16, 4);					\
+@@ -591,13 +661,15 @@ static void clean_results (void)
+   TEST_MACRO_64BITS_SIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   TEST_MACRO_64BITS_UNSIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   MACRO(VAR1, VAR2, , poly, p, 8, 8);				\
+-  MACRO(VAR1, VAR2, , poly, p, 16, 4)
++  MACRO(VAR1, VAR2, , poly, p, 16, 4);				\
++  MACRO_CRYPTO(MACRO, VAR1, VAR2, , poly, p, 64, 1)
+ 
+ #define TEST_MACRO_128BITS_VARIANTS_2_5(MACRO, VAR1, VAR2)	\
+   TEST_MACRO_128BITS_SIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   TEST_MACRO_128BITS_UNSIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   MACRO(VAR1, VAR2, q, poly, p, 8, 16);				\
+-  MACRO(VAR1, VAR2, q, poly, p, 16, 8)
++  MACRO(VAR1, VAR2, q, poly, p, 16, 8);				\
++  MACRO_CRYPTO(MACRO, VAR1, VAR2, q, poly, p, 64, 2)
+ 
+ #define TEST_MACRO_ALL_VARIANTS_2_5(MACRO, VAR1, VAR2)	\
+   TEST_MACRO_64BITS_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc
+@@ -0,0 +1,170 @@
++/* Floating-point only version of binary_op_no64.inc template.  Currently only
++   float16_t is used.  */
++
++#include <math.h>
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1(NAME)
++
++void FNNAME (INSN_NAME) (void)
++{
++  int i;
++
++  /* Basic test: z = INSN (x, y), then store the result.  */
++#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)				\
++  VECT_VAR(vector_res, T1, W, N) =					\
++    INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N),			\
++		      VECT_VAR(vector2, T1, W, N));			\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N)   \
++  TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)	\
++
++#ifdef HAS_FLOAT16_VARIANT
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
++#ifdef HAS_FLOAT_VARIANT
++  DECL_VARIABLE(vector, float, 32, 2);
++  DECL_VARIABLE(vector2, float, 32, 2);
++  DECL_VARIABLE(vector_res, float, 32, 2);
++
++  DECL_VARIABLE(vector, float, 32, 4);
++  DECL_VARIABLE(vector2, float, 32, 4);
++  DECL_VARIABLE(vector_res, float, 32, 4);
++#endif
++
++  clean_results ();
++
++  /* Initialize input "vector" from "buffer".  */
++#ifdef HAS_FLOAT16_VARIANT
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++#ifdef HAS_FLOAT_VARIANT
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++#endif
++
++  /* Choose init value arbitrarily, will be used as comparison value.  */
++#ifdef HAS_FLOAT16_VARIANT
++  VDUP(vector2, , float, f, 16, 4, -15.5f);
++  VDUP(vector2, q, float, f, 16, 8, -14.5f);
++#endif
++#ifdef HAS_FLOAT_VARIANT
++  VDUP(vector2, , float, f, 32, 2, -15.5f);
++  VDUP(vector2, q, float, f, 32, 4, -14.5f);
++#endif
++
++#ifdef HAS_FLOAT16_VARIANT
++#define FLOAT16_VARIANT(MACRO, VAR)			\
++  MACRO(VAR, , float, f, 16, 4);			\
++  MACRO(VAR, q, float, f, 16, 8);
++#else
++#define FLOAT16_VARIANT(MACRO, VAR)
++#endif
++
++#ifdef HAS_FLOAT_VARIANT
++#define FLOAT_VARIANT(MACRO, VAR)			\
++  MACRO(VAR, , float, f, 32, 2);			\
++  MACRO(VAR, q, float, f, 32, 4);
++#else
++#define FLOAT_VARIANT(MACRO, VAR)
++#endif
++
++#define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR)	\
++
++  /* Apply a binary operator named INSN_NAME.  */
++  FLOAT16_VARIANT(TEST_BINARY_OP, INSN_NAME);
++  FLOAT_VARIANT(TEST_BINARY_OP, INSN_NAME);
++
++#ifdef HAS_FLOAT16_VARIANT
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++
++  /* Extra FP tests with special values (NaN, ....)  */
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan,
++	   " FP special (NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, -NAN);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_mnan,
++	   " FP special (-NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_inf,
++	   " FP special (inf)");
++
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_minf,
++	   " FP special (-inf)");
++
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, -0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero1,
++	   " FP special (-0.0)");
++
++  VDUP(vector, q, float, f, 16, 8, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero2,
++	   " FP special (-0.0)");
++#endif
++
++#ifdef HAS_FLOAT_VARIANT
++  CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
++
++  /* Extra FP tests with special values (NaN, ....)  */
++  VDUP(vector, q, float, f, 32, 4, 1.0f);
++  VDUP(vector2, q, float, f, 32, 4, NAN);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, " FP special (NaN)");
++
++  VDUP(vector, q, float, f, 32, 4, -NAN);
++  VDUP(vector2, q, float, f, 32, 4, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_mnan, " FP special (-NaN)");
++
++  VDUP(vector, q, float, f, 32, 4, 1.0f);
++  VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_inf, " FP special (inf)");
++
++  VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
++  VDUP(vector2, q, float, f, 32, 4, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_minf, " FP special (-inf)");
++
++  VDUP(vector, q, float, f, 32, 4, 0.0f);
++  VDUP(vector2, q, float, f, 32, 4, -0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero1, " FP special (-0.0)");
++
++  VDUP(vector, q, float, f, 32, 4, -0.0f);
++  VDUP(vector2, q, float, f, 32, 4, 0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero2, " FP special (-0.0)");
++#endif
++}
++
++int main (void)
++{
++  FNNAME (INSN_NAME) ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
+@@ -28,6 +28,10 @@ void FNNAME (INSN_NAME) (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#ifdef HAS_FLOAT16_VARIANT
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+ #ifdef HAS_FLOAT_VARIANT
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+@@ -46,15 +50,27 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 8, 16, 0xf9);
+   VDUP(vector2, q, uint, u, 16, 8, 0xfff2);
+   VDUP(vector2, q, uint, u, 32, 4, 0xfffffff1);
++#ifdef HAS_FLOAT16_VARIANT
++  VDUP(vector2, , float, f, 16, 4, -15.5f);
++  VDUP(vector2, q, float, f, 16, 8, -14.5f);
++#endif
+ #ifdef HAS_FLOAT_VARIANT
+   VDUP(vector2, , float, f, 32, 2, -15.5f);
+   VDUP(vector2, q, float, f, 32, 4, -14.5f);
+ #endif
+ 
++#ifdef HAS_FLOAT16_VARIANT
++#define FLOAT16_VARIANT(MACRO, VAR)			\
++  MACRO(VAR, , float, f, 16, 4);			\
++  MACRO(VAR, q, float, f, 16, 8);
++#else
++#define FLOAT16_VARIANT(MACRO, VAR)
++#endif
++
+ #ifdef HAS_FLOAT_VARIANT
+ #define FLOAT_VARIANT(MACRO, VAR)			\
+   MACRO(VAR, , float, f, 32, 2);			\
+-  MACRO(VAR, q, float, f, 32, 4)
++  MACRO(VAR, q, float, f, 32, 4);
+ #else
+ #define FLOAT_VARIANT(MACRO, VAR)
+ #endif
+@@ -72,7 +88,8 @@ void FNNAME (INSN_NAME) (void)
+   MACRO(VAR, q, uint, u, 8, 16);			\
+   MACRO(VAR, q, uint, u, 16, 8);			\
+   MACRO(VAR, q, uint, u, 32, 4);			\
+-  FLOAT_VARIANT(MACRO, VAR)
++  FLOAT_VARIANT(MACRO, VAR);				\
++  FLOAT16_VARIANT(MACRO, VAR);
+ 
+   /* Apply a binary operator named INSN_NAME.  */
+   TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME);
+@@ -90,6 +107,42 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ 
++#ifdef HAS_FLOAT16_VARIANT
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++
++  /* Extra FP tests with special values (NaN, ....)  */
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan, " FP special (NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, -NAN);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_mnan, " FP special (-NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_inf, " FP special (inf)");
++
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_minf, " FP special (-inf)");
++
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, -0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero1, " FP special (-0.0)");
++
++  VDUP(vector, q, float, f, 16, 8, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero2, " FP special (-0.0)");
++#endif
++
+ #ifdef HAS_FLOAT_VARIANT
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc
+@@ -0,0 +1,160 @@
++/* Template file for binary scalar operator validation.
++
++   This file is meant to be included by test files for binary scalar
++   operations.  */
++
++/* Check for required settings.  */
++
++#ifndef INSN_NAME
++#error INSN_NAME (the intrinsic to test) must be defined.
++#endif
++
++#ifndef INPUT_TYPE
++#error INPUT_TYPE (basic type of an input value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE
++#error OUTPUT_TYPE (basic type of an output value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE_SIZE
++#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
++#endif
++
++/* Optional settings:
++
++   INPUT_1: Input values for the first parameter.  Must be of type INPUT_TYPE.
++   INPUT_2: Input values for the first parameter.  Must be of type
++   INPUT_TYPE.  */
++
++#ifndef TEST_MSG
++#define TEST_MSG "unnamed test"
++#endif
++
++/* The test framework.  */
++
++#include <stdio.h>
++
++extern void abort ();
++
++#define INFF __builtin_inf ()
++
++/* Stringify a macro.  */
++#define STR0(A) #A
++#define STR(A) STR0 (A)
++
++/* Macro concatenation.  */
++#define CAT0(A, B) A##B
++#define CAT(A, B) CAT0 (A, B)
++
++/* Format strings for error reporting.  */
++#define FMT16 "0x%04x"
++#define FMT32 "0x%08x"
++#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
++
++/* Type construction: forms TS_t, where T is the base type and S the size in
++   bits.  */
++#define MK_TYPE0(T, S) T##S##_t
++#define MK_TYPE(T, S) MK_TYPE0 (T, S)
++
++/* Convenience types for input and output data.  */
++typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
++
++/* Conversion between typed values and their hexadecimal representation.  */
++typedef union
++{
++  OUTPUT_TYPE value;
++  output_hex_type hex;
++} output_conv_type;
++
++/* Default input values.  */
++
++float16_t input_1_float16_t[] =
++{
++  0.0, -0.0,
++  2.0, 3.1,
++  20.0, 0.40,
++  -2.3, 1.33,
++  -7.6, 0.31,
++  0.3353, 0.5,
++  1.0, 13.13,
++  -6.3, 20.0,
++  (float16_t)INFF, (float16_t)-INFF,
++};
++
++float16_t input_2_float16_t[] =
++{
++  1.0, 1.0,
++  -4.33, 100.0,
++  30.0, -0.02,
++  0.5, -7.231,
++  -6.3, 20.0,
++  -7.231, 2.3,
++  -7.6, 5.1,
++  0.31, 0.33353,
++  (float16_t)-INFF, (float16_t)INFF,
++};
++
++#ifndef INPUT_1
++#define INPUT_1 CAT (input_1_,INPUT_TYPE)
++#endif
++
++#ifndef INPUT_2
++#define INPUT_2 CAT (input_2_,INPUT_TYPE)
++#endif
++
++/* Support macros and routines for the test function.  */
++
++#define CHECK()						\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
++    actual.value = INSN_NAME ((INPUT_1)[index],			\
++			      (INPUT_2)[index]);		\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++/* The test function.  */
++
++void
++FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
++     against EXPECTED[i].  */
++
++  const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]);
++  int index;
++
++  for (index = 0; index < num_tests; index++)
++    CHECK ();
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS ();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc
+@@ -15,6 +15,10 @@
+    each test file.  */
+ extern ARRAY(expected2, uint, 32, 2);
+ extern ARRAY(expected2, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++extern ARRAY(expected2, uint, 16, 4);
++extern ARRAY(expected2, uint, 16, 8);
++#endif
+ 
+ #define FNNAME1(NAME) exec_ ## NAME
+ #define FNNAME(NAME) FNNAME1(NAME)
+@@ -37,17 +41,33 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector2, float, 32, 4);
+   DECL_VARIABLE(vector_res, uint, 32, 2);
+   DECL_VARIABLE(vector_res, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector_res, uint, 16, 4);
++  DECL_VARIABLE(vector_res, uint, 16, 8);
++#endif
+ 
+   clean_results ();
+ 
+   /* Initialize input "vector" from "buffer".  */
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+ 
+   /* Choose init value arbitrarily, will be used for vector
+      comparison.  */
+   VDUP(vector2, , float, f, 32, 2, -16.0f);
+   VDUP(vector2, q, float, f, 32, 4, -14.0f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, -16.0f);
++  VDUP(vector2, q, float, f, 16, 8, -14.0f);
++#endif
+ 
+   /* Apply operator named INSN_NAME.  */
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+@@ -56,15 +76,36 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP(INSN_NAME, , float, f, uint, 16, 4);
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
++
++  TEST_VCOMP(INSN_NAME, q, float, f, uint, 16, 8);
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
++#endif
++
+   /* Test again, with different input values.  */
+   VDUP(vector2, , float, f, 32, 2, -10.0f);
+   VDUP(vector2, q, float, f, 32, 4, 10.0f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, -10.0f);
++  VDUP(vector2, q, float, f, 16, 8, 10.0f);
++#endif
++
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected2, "");
+ 
+   TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected2,"");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP(INSN_NAME, , float, f, uint, 16, 4);
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected2, "");
++
++  TEST_VCOMP(INSN_NAME, q, float, f, uint, 16, 8);
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected2,"");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc
+@@ -11,6 +11,17 @@ extern ARRAY(expected_uint, uint, 32, 2);
+ extern ARRAY(expected_q_uint, uint, 8, 16);
+ extern ARRAY(expected_q_uint, uint, 16, 8);
+ extern ARRAY(expected_q_uint, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++extern ARRAY(expected_float, uint, 16, 4);
++extern ARRAY(expected_q_float, uint, 16, 8);
++extern ARRAY(expected_nan, uint, 16, 4);
++extern ARRAY(expected_mnan, uint, 16, 4);
++extern ARRAY(expected_nan2, uint, 16, 4);
++extern ARRAY(expected_inf, uint, 16, 4);
++extern ARRAY(expected_minf, uint, 16, 4);
++extern ARRAY(expected_inf2, uint, 16, 4);
++extern ARRAY(expected_mzero, uint, 16, 4);
++#endif
+ extern ARRAY(expected_float, uint, 32, 2);
+ extern ARRAY(expected_q_float, uint, 32, 4);
+ extern ARRAY(expected_uint2, uint, 32, 2);
+@@ -48,6 +59,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector, uint, 8, 8);
+   DECL_VARIABLE(vector, uint, 16, 4);
+   DECL_VARIABLE(vector, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, int, 8, 16);
+   DECL_VARIABLE(vector, int, 16, 8);
+@@ -55,6 +69,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector, uint, 8, 16);
+   DECL_VARIABLE(vector, uint, 16, 8);
+   DECL_VARIABLE(vector, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
+   DECL_VARIABLE(vector2, int, 8, 8);
+@@ -63,6 +80,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector2, uint, 8, 8);
+   DECL_VARIABLE(vector2, uint, 16, 4);
+   DECL_VARIABLE(vector2, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector2, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+   DECL_VARIABLE(vector2, int, 8, 16);
+   DECL_VARIABLE(vector2, int, 16, 8);
+@@ -70,6 +90,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector2, uint, 8, 16);
+   DECL_VARIABLE(vector2, uint, 16, 8);
+   DECL_VARIABLE(vector2, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector2, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 4);
+ 
+   DECL_VARIABLE(vector_res, uint, 8, 8);
+@@ -88,6 +111,9 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, , uint, u, 8, 8);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD (vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+ 
+   VLOAD(vector, buffer, q, int, s, 8, 16);
+@@ -96,6 +122,9 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, q, uint, u, 8, 16);
+   VLOAD(vector, buffer, q, uint, u, 16, 8);
+   VLOAD(vector, buffer, q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD (vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Choose init value arbitrarily, will be used for vector
+@@ -106,6 +135,9 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, , uint, u, 8, 8, 0xF3);
+   VDUP(vector2, , uint, u, 16, 4, 0xFFF2);
+   VDUP(vector2, , uint, u, 32, 2, 0xFFFFFFF1);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector2, , float, f, 16, 4, -15.0f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, -15.0f);
+ 
+   VDUP(vector2, q, int, s, 8, 16, -4);
+@@ -114,6 +146,9 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 8, 16, 0xF4);
+   VDUP(vector2, q, uint, u, 16, 8, 0xFFF6);
+   VDUP(vector2, q, uint, u, 32, 4, 0xFFFFFFF2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector2, q, float, f, 16, 8, -14.0f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, -14.0f);
+ 
+   /* The comparison operators produce only unsigned results, which
+@@ -154,9 +189,17 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_q_uint, "");
+ 
+   /* The float variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_float, "");
++#endif
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_float, "");
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP (INSN_NAME, q, float, f, uint, 16, 8);
++  CHECK (TEST_MSG, uint, 16, 8, PRIx16, expected_q_float, "");
++#endif
+   TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_q_float, "");
+ 
+@@ -176,6 +219,43 @@ void FNNAME (INSN_NAME) (void)
+ 
+ 
+   /* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan, "FP special (NaN)");
++
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, -NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mnan, " FP special (-NaN)");
++
++  VDUP (vector, , float, f, 16, 4, NAN);
++  VDUP (vector2, , float, f, 16, 4, 1.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan2, " FP special (NaN)");
++
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf, " FP special (inf)");
++
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, -HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_minf, " FP special (-inf)");
++
++  VDUP (vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP (vector2, , float, f, 16, 4, 1.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf2, " FP special (inf)");
++
++  VDUP (vector, , float, f, 16, 4, -0.0);
++  VDUP (vector2, , float, f, 16, 4, 0.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mzero, " FP special (-0.0)");
++#endif
++
+   VDUP(vector, , float, f, 32, 2, 1.0);
+   VDUP(vector2, , float, f, 32, 2, NAN);
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc
+@@ -0,0 +1,111 @@
++/* Template file for the validation of compare against zero operators.
++
++   This file is base on cmp_op.inc.  It is meant to be included by the relevant
++   test files, which have to define the intrinsic family to test.  If a given
++   intrinsic supports variants which are not supported by all the other
++   operators, these can be tested by providing a definition for EXTRA_TESTS.  */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Additional expected results declaration, they are initialized in
++   each test file.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++extern ARRAY(expected_float, uint, 16, 4);
++extern ARRAY(expected_q_float, uint, 16, 8);
++extern ARRAY(expected_uint2, uint, 16, 4);
++extern ARRAY(expected_uint3, uint, 16, 4);
++extern ARRAY(expected_uint4, uint, 16, 4);
++extern ARRAY(expected_nan, uint, 16, 4);
++extern ARRAY(expected_mnan, uint, 16, 4);
++extern ARRAY(expected_inf, uint, 16, 4);
++extern ARRAY(expected_minf, uint, 16, 4);
++extern ARRAY(expected_zero, uint, 16, 4);
++extern ARRAY(expected_mzero, uint, 16, 4);
++#endif
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1(NAME)
++
++void FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y=vcomp(x1,x2), then store the result.  */
++#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)				\
++  VECT_VAR(vector_res, T3, W, N) =					\
++    INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N));			\
++  vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vector_res, T3, W, N))
++
++#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N)				\
++  TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)
++
++  /* No need for 64 bits elements.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector, float, 16, 4);
++  DECL_VARIABLE (vector, float, 16, 8);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, uint, 16, 4);
++  DECL_VARIABLE(vector_res, uint, 16, 8);
++#endif
++
++  clean_results ();
++
++  /* Choose init value arbitrarily, will be used for vector
++     comparison.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector, , float, f, 16, 4, -15.0f);
++  VDUP (vector, q, float, f, 16, 8, 14.0f);
++#endif
++
++  /* Float variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  TEST_VCOMP (INSN_NAME, q, float, f, uint, 16, 8);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_float, "");
++  CHECK (TEST_MSG, uint, 16, 8, PRIx16, expected_q_float, "");
++#endif
++
++  /* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector, , float, f, 16, 4, NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan, "FP special (NaN)");
++
++  VDUP (vector, , float, f, 16, 4, -NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mnan, " FP special (-NaN)");
++
++  VDUP (vector, , float, f, 16, 4, HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf, " FP special (inf)");
++
++  VDUP (vector, , float, f, 16, 4, -HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_minf, " FP special (-inf)");
++
++  VDUP (vector, , float, f, 16, 4, 0.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_zero, " FP special (0.0)");
++
++  VDUP (vector, , float, f, 16, 4, 0.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mzero, " FP special (-0.0)");
++#endif
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS();
++#endif
++}
++
++int main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
+@@ -118,6 +118,10 @@ VECT_VAR_DECL_INIT(buffer, uint, 32, 2);
+ PAD(buffer_pad, uint, 32, 2);
+ VECT_VAR_DECL_INIT(buffer, uint, 64, 1);
+ PAD(buffer_pad, uint, 64, 1);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT(buffer, poly, 64, 1);
++PAD(buffer_pad, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT(buffer, float, 16, 4);
+ PAD(buffer_pad, float, 16, 4);
+@@ -144,6 +148,10 @@ VECT_VAR_DECL_INIT(buffer, poly, 8, 16);
+ PAD(buffer_pad, poly, 8, 16);
+ VECT_VAR_DECL_INIT(buffer, poly, 16, 8);
+ PAD(buffer_pad, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT(buffer, poly, 64, 2);
++PAD(buffer_pad, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT(buffer, float, 16, 8);
+ PAD(buffer_pad, float, 16, 8);
+@@ -178,6 +186,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 8);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 8, 8);
+ VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 4);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 16, 4);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT4(buffer_dup, poly, 64, 1);
++VECT_VAR_DECL(buffer_dup_pad, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT4(buffer_dup, float, 16, 4);
+ VECT_VAR_DECL(buffer_dup_pad, float, 16, 4);
+@@ -205,6 +217,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 16);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 8, 16);
+ VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 8);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT4(buffer_dup, poly, 64, 2);
++VECT_VAR_DECL(buffer_dup_pad, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT(buffer_dup, float, 16, 8);
+ VECT_VAR_DECL(buffer_dup_pad, float, 16, 8);
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
+@@ -0,0 +1,1024 @@
++/* This file contains tests for all the *p64 intrinsics, except for
++   vreinterpret which have their own testcase.  */
++
++/* { dg-require-effective-target arm_crypto_ok { target { arm*-*-* } } } */
++/* { dg-add-options arm_crypto } */
++/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results: vbsl.  */
++VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 };
++VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1,
++					      0xfffffff1 };
++
++/* Expected results: vceq.  */
++VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 };
++
++/* Expected results: vcombine.  */
++VECT_VAR_DECL(vcombine_expected,poly,64,2) [] = { 0xfffffffffffffff0, 0x88 };
++
++/* Expected results: vcreate.  */
++VECT_VAR_DECL(vcreate_expected,poly,64,1) [] = { 0x123456789abcdef0 };
++
++/* Expected results: vdup_lane.  */
++VECT_VAR_DECL(vdup_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vdup_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff0 };
++
++/* Expected results: vdup_n.  */
++VECT_VAR_DECL(vdup_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vdup_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
++						 0xfffffffffffffff0 };
++VECT_VAR_DECL(vdup_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vdup_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
++						 0xfffffffffffffff1 };
++VECT_VAR_DECL(vdup_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vdup_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
++						 0xfffffffffffffff2 };
++
++/* Expected results: vmov_n.  */
++VECT_VAR_DECL(vmov_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vmov_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
++						 0xfffffffffffffff0 };
++VECT_VAR_DECL(vmov_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vmov_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
++						 0xfffffffffffffff1 };
++VECT_VAR_DECL(vmov_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vmov_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
++						 0xfffffffffffffff2 };
++
++/* Expected results: vext.  */
++VECT_VAR_DECL(vext_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vext_expected,poly,64,2) [] = { 0xfffffffffffffff1, 0x88 };
++
++/* Expected results: vget_low.  */
++VECT_VAR_DECL(vget_low_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++
++/* Expected results: vget_high.  */
++VECT_VAR_DECL(vget_high_expected,poly,64,1) [] = { 0xfffffffffffffff1 };
++
++/* Expected results: vld1.  */
++VECT_VAR_DECL(vld1_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++					      0xfffffffffffffff1 };
++
++/* Expected results: vld1_dup.  */
++VECT_VAR_DECL(vld1_dup_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_dup_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_dup_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld1_dup_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(vld1_dup_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld1_dup_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
++						   0xfffffffffffffff2 };
++
++/* Expected results: vld1_lane.  */
++VECT_VAR_DECL(vld1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xaaaaaaaaaaaaaaaa };
++
++/* Expected results: vldX.  */
++VECT_VAR_DECL(vld2_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld2_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld3_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld4_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld4_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 };
++
++/* Expected results: vldX_dup.  */
++VECT_VAR_DECL(vld2_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld2_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld3_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld4_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld4_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_dup_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 };
++
++/* Expected results: vsli.  */
++VECT_VAR_DECL(vsli_expected,poly,64,1) [] = { 0x10 };
++VECT_VAR_DECL(vsli_expected,poly,64,2) [] = { 0x7ffffffffffff0,
++					      0x7ffffffffffff1 };
++VECT_VAR_DECL(vsli_expected_max_shift,poly,64,1) [] = { 0x7ffffffffffffff0 };
++VECT_VAR_DECL(vsli_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0,
++							0xfffffffffffffff1 };
++
++/* Expected results: vsri.  */
++VECT_VAR_DECL(vsri_expected,poly,64,1) [] = { 0xe000000000000000 };
++VECT_VAR_DECL(vsri_expected,poly,64,2) [] = { 0xfffffffffffff800,
++					      0xfffffffffffff800 };
++VECT_VAR_DECL(vsri_expected_max_shift,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vsri_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0,
++							0xfffffffffffffff1 };
++
++/* Expected results: vst1_lane.  */
++VECT_VAR_DECL(vst1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vst1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0x3333333333333333 };
++
++/* Expected results: vldX_lane.  */
++VECT_VAR_DECL(expected_vld_st2_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected_vld_st2_0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st2_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st2_1,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st3_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected_vld_st3_0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st3_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st3_1,poly,64,2) [] = { 0xfffffffffffffff2,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st3_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(expected_vld_st3_2,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st4_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected_vld_st4_0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st4_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st4_1,poly,64,2) [] = { 0xfffffffffffffff2,
++						   0xfffffffffffffff3 };
++VECT_VAR_DECL(expected_vld_st4_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(expected_vld_st4_2,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st4_3,poly,64,1) [] = { 0xfffffffffffffff3 };
++VECT_VAR_DECL(expected_vld_st4_3,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++
++/* Expected results: vget_lane.  */
++VECT_VAR_DECL(vget_lane_expected,poly,64,1) = 0xfffffffffffffff0;
++VECT_VAR_DECL(vget_lane_expected,poly,64,2) = 0xfffffffffffffff0;
++
++int main (void)
++{
++  int i;
++
++  /* vbsl_p64 tests.  */
++#define TEST_MSG "VBSL/VBSLQ"
++
++#define TEST_VBSL(T3, Q, T1, T2, W, N)					\
++  VECT_VAR(vbsl_vector_res, T1, W, N) =					\
++    vbsl##Q##_##T2##W(VECT_VAR(vbsl_vector_first, T3, W, N),		\
++		      VECT_VAR(vbsl_vector, T1, W, N),			\
++		      VECT_VAR(vbsl_vector2, T1, W, N));		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vbsl_vector_res, T1, W, N))
++
++  DECL_VARIABLE(vbsl_vector, poly, 64, 1);
++  DECL_VARIABLE(vbsl_vector, poly, 64, 2);
++  DECL_VARIABLE(vbsl_vector2, poly, 64, 1);
++  DECL_VARIABLE(vbsl_vector2, poly, 64, 2);
++  DECL_VARIABLE(vbsl_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vbsl_vector_res, poly, 64, 2);
++
++  DECL_VARIABLE(vbsl_vector_first, uint, 64, 1);
++  DECL_VARIABLE(vbsl_vector_first, uint, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vbsl_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vbsl_vector, buffer, q, poly, p, 64, 2);
++
++  VDUP(vbsl_vector2, , poly, p, 64, 1, 0xFFFFFFF3);
++  VDUP(vbsl_vector2, q, poly, p, 64, 2, 0xFFFFFFF3);
++
++  VDUP(vbsl_vector_first, , uint, u, 64, 1, 0xFFFFFFF2);
++  VDUP(vbsl_vector_first, q, uint, u, 64, 2, 0xFFFFFFF2);
++
++  TEST_VBSL(uint, , poly, p, 64, 1);
++  TEST_VBSL(uint, q, poly, p, 64, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vbsl_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vbsl_expected, "");
++
++  /* vceq_p64 tests. */
++#undef TEST_MSG
++#define TEST_MSG "VCEQ"
++
++#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)				\
++  VECT_VAR(vceq_vector_res, T3, W, N) =					\
++    INSN##Q##_##T2##W(VECT_VAR(vceq_vector, T1, W, N),			\
++		      VECT_VAR(vceq_vector2, T1, W, N));		\
++  vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vceq_vector_res, T3, W, N))
++
++#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N)				\
++  TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)
++
++  DECL_VARIABLE(vceq_vector, poly, 64, 1);
++  DECL_VARIABLE(vceq_vector2, poly, 64, 1);
++  DECL_VARIABLE(vceq_vector_res, uint, 64, 1);
++
++  CLEAN(result, uint, 64, 1);
++
++  VLOAD(vceq_vector, buffer, , poly, p, 64, 1);
++
++  VDUP(vceq_vector2, , poly, p, 64, 1, 0x88);
++
++  TEST_VCOMP(vceq, , poly, p, uint, 64, 1);
++
++  CHECK(TEST_MSG, uint, 64, 1, PRIx64, vceq_expected, "");
++
++  /* vcombine_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VCOMBINE"
++
++#define TEST_VCOMBINE(T1, T2, W, N, N2)					\
++  VECT_VAR(vcombine_vector128, T1, W, N2) =				\
++    vcombine_##T2##W(VECT_VAR(vcombine_vector64_a, T1, W, N),		\
++		     VECT_VAR(vcombine_vector64_b, T1, W, N));		\
++  vst1q_##T2##W(VECT_VAR(result, T1, W, N2), VECT_VAR(vcombine_vector128, T1, W, N2))
++
++  DECL_VARIABLE(vcombine_vector64_a, poly, 64, 1);
++  DECL_VARIABLE(vcombine_vector64_b, poly, 64, 1);
++  DECL_VARIABLE(vcombine_vector128, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vcombine_vector64_a, buffer, , poly, p, 64, 1);
++
++  VDUP(vcombine_vector64_b, , poly, p, 64, 1, 0x88);
++
++  TEST_VCOMBINE(poly, p, 64, 1, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vcombine_expected, "");
++
++  /* vcreate_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VCREATE"
++
++#define TEST_VCREATE(T1, T2, W, N)					\
++  VECT_VAR(vcreate_vector_res, T1, W, N) =				\
++    vcreate_##T2##W(VECT_VAR(vcreate_val, T1, W, N));			\
++  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vcreate_vector_res, T1, W, N))
++
++#define DECL_VAL(VAR, T1, W, N)			\
++  uint64_t VECT_VAR(VAR, T1, W, N)
++
++  DECL_VAL(vcreate_val, poly, 64, 1);
++  DECL_VARIABLE(vcreate_vector_res, poly, 64, 1);
++
++  CLEAN(result, poly, 64, 2);
++
++  VECT_VAR(vcreate_val, poly, 64, 1) = 0x123456789abcdef0ULL;
++
++  TEST_VCREATE(poly, p, 64, 1);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vcreate_expected, "");
++
++  /* vdup_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VDUP_LANE/VDUP_LANEQ"
++
++#define TEST_VDUP_LANE(Q, T1, T2, W, N, N2, L)				\
++  VECT_VAR(vdup_lane_vector_res, T1, W, N) =				\
++    vdup##Q##_lane_##T2##W(VECT_VAR(vdup_lane_vector, T1, W, N2), L);	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_lane_vector_res, T1, W, N))
++
++  DECL_VARIABLE(vdup_lane_vector, poly, 64, 1);
++  DECL_VARIABLE(vdup_lane_vector, poly, 64, 2);
++  DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vdup_lane_vector, buffer, , poly, p, 64, 1);
++
++  TEST_VDUP_LANE(, poly, p, 64, 1, 1, 0);
++  TEST_VDUP_LANE(q, poly, p, 64, 2, 1, 0);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_lane_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_lane_expected, "");
++
++  /* vdup_n_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VDUP/VDUPQ"
++
++#define TEST_VDUP(Q, T1, T2, W, N)					\
++  VECT_VAR(vdup_n_vector, T1, W, N) =					\
++    vdup##Q##_n_##T2##W(VECT_VAR(buffer_dup, T1, W, N)[i]);		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_n_vector, T1, W, N))
++
++  DECL_VARIABLE(vdup_n_vector, poly, 64, 1);
++  DECL_VARIABLE(vdup_n_vector, poly, 64, 2);
++
++  /* Try to read different places from the input buffer.  */
++  for (i=0; i< 3; i++) {
++    CLEAN(result, poly, 64, 1);
++    CLEAN(result, poly, 64, 2);
++
++    TEST_VDUP(, poly, p, 64, 1);
++    TEST_VDUP(q, poly, p, 64, 2);
++
++    switch (i) {
++    case 0:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected0, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected0, "");
++      break;
++    case 1:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected1, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected1, "");
++      break;
++    case 2:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected2, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected2, "");
++      break;
++    default:
++      abort();
++    }
++  }
++
++  /* vexit_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VEXT/VEXTQ"
++
++#define TEST_VEXT(Q, T1, T2, W, N, V)					\
++  VECT_VAR(vext_vector_res, T1, W, N) =					\
++    vext##Q##_##T2##W(VECT_VAR(vext_vector1, T1, W, N),			\
++		      VECT_VAR(vext_vector2, T1, W, N),			\
++		      V);						\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vext_vector_res, T1, W, N))
++
++  DECL_VARIABLE(vext_vector1, poly, 64, 1);
++  DECL_VARIABLE(vext_vector1, poly, 64, 2);
++  DECL_VARIABLE(vext_vector2, poly, 64, 1);
++  DECL_VARIABLE(vext_vector2, poly, 64, 2);
++  DECL_VARIABLE(vext_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vext_vector_res, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vext_vector1, buffer, , poly, p, 64, 1);
++  VLOAD(vext_vector1, buffer, q, poly, p, 64, 2);
++
++  VDUP(vext_vector2, , poly, p, 64, 1, 0x88);
++  VDUP(vext_vector2, q, poly, p, 64, 2, 0x88);
++
++  TEST_VEXT(, poly, p, 64, 1, 0);
++  TEST_VEXT(q, poly, p, 64, 2, 1);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vext_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vext_expected, "");
++
++  /* vget_low_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VGET_LOW"
++
++#define TEST_VGET_LOW(T1, T2, W, N, N2)					\
++  VECT_VAR(vget_low_vector64, T1, W, N) =				\
++    vget_low_##T2##W(VECT_VAR(vget_low_vector128, T1, W, N2));		\
++  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vget_low_vector64, T1, W, N))
++
++  DECL_VARIABLE(vget_low_vector64, poly, 64, 1);
++  DECL_VARIABLE(vget_low_vector128, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++
++  VLOAD(vget_low_vector128, buffer, q, poly, p, 64, 2);
++
++  TEST_VGET_LOW(poly, p, 64, 1, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vget_low_expected, "");
++
++  /* vget_high_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VGET_HIGH"
++
++#define TEST_VGET_HIGH(T1, T2, W, N, N2)					\
++  VECT_VAR(vget_high_vector64, T1, W, N) =				\
++    vget_high_##T2##W(VECT_VAR(vget_high_vector128, T1, W, N2));		\
++  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vget_high_vector64, T1, W, N))
++
++  DECL_VARIABLE(vget_high_vector64, poly, 64, 1);
++  DECL_VARIABLE(vget_high_vector128, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++
++  VLOAD(vget_high_vector128, buffer, q, poly, p, 64, 2);
++
++  TEST_VGET_HIGH(poly, p, 64, 1, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vget_high_expected, "");
++
++  /* vld1_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLD1/VLD1Q"
++
++#define TEST_VLD1(VAR, BUF, Q, T1, T2, W, N)				\
++  VECT_VAR(VAR, T1, W, N) = vld1##Q##_##T2##W(VECT_VAR(BUF, T1, W, N)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N))
++
++  DECL_VARIABLE(vld1_vector, poly, 64, 1);
++  DECL_VARIABLE(vld1_vector, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vld1_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vld1_vector, buffer, q, poly, p, 64, 2);
++
++  TEST_VLD1(vld1_vector, buffer, , poly, p, 64, 1);
++  TEST_VLD1(vld1_vector, buffer, q, poly, p, 64, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_expected, "");
++
++  /* vld1_dup_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLD1_DUP/VLD1_DUPQ"
++
++#define TEST_VLD1_DUP(VAR, BUF, Q, T1, T2, W, N)			\
++  VECT_VAR(VAR, T1, W, N) =						\
++    vld1##Q##_dup_##T2##W(&VECT_VAR(BUF, T1, W, N)[i]);			\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N))
++
++  DECL_VARIABLE(vld1_dup_vector, poly, 64, 1);
++  DECL_VARIABLE(vld1_dup_vector, poly, 64, 2);
++
++  /* Try to read different places from the input buffer.  */
++  for (i=0; i<3; i++) {
++    CLEAN(result, poly, 64, 1);
++    CLEAN(result, poly, 64, 2);
++
++    TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, , poly, p, 64, 1);
++    TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, q, poly, p, 64, 2);
++
++    switch (i) {
++    case 0:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected0, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected0, "");
++      break;
++    case 1:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected1, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected1, "");
++      break;
++    case 2:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected2, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected2, "");
++      break;
++    default:
++      abort();
++    }
++  }
++
++  /* vld1_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
++
++#define TEST_VLD1_LANE(Q, T1, T2, W, N, L)				\
++  memset (VECT_VAR(vld1_lane_buffer_src, T1, W, N), 0xAA, W/8*N);	\
++  VECT_VAR(vld1_lane_vector_src, T1, W, N) =				\
++    vld1##Q##_##T2##W(VECT_VAR(vld1_lane_buffer_src, T1, W, N));	\
++  VECT_VAR(vld1_lane_vector, T1, W, N) =				\
++    vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N),			\
++			   VECT_VAR(vld1_lane_vector_src, T1, W, N), L); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vld1_lane_vector, T1, W, N))
++
++  DECL_VARIABLE(vld1_lane_vector, poly, 64, 1);
++  DECL_VARIABLE(vld1_lane_vector, poly, 64, 2);
++  DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 1);
++  DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 2);
++
++  ARRAY(vld1_lane_buffer_src, poly, 64, 1);
++  ARRAY(vld1_lane_buffer_src, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VLD1_LANE(, poly, p, 64, 1, 0);
++  TEST_VLD1_LANE(q, poly, p, 64, 2, 0);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_lane_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_lane_expected, "");
++
++  /* vldX_p64 tests.  */
++#define DECL_VLDX(T1, W, N, X)						\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_vector, T1, W, N, X); \
++  VECT_VAR_DECL(vldX_result_bis_##X, T1, W, N)[X * N]
++
++#define TEST_VLDX(Q, T1, T2, W, N, X)					\
++  VECT_ARRAY_VAR(vldX_vector, T1, W, N, X) =				\
++    /* Use dedicated init buffer, of size X */				\
++    vld##X##Q##_##T2##W(VECT_ARRAY_VAR(buffer_vld##X, T1, W, N, X));	\
++  vst##X##Q##_##T2##W(VECT_VAR(vldX_result_bis_##X, T1, W, N),		\
++		      VECT_ARRAY_VAR(vldX_vector, T1, W, N, X));	\
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  /* Overwrite "result" with the contents of "result_bis"[Y].  */
++#define TEST_EXTRA_CHUNK(T1, W, N, X,Y)				\
++  memcpy(VECT_VAR(result, T1, W, N),				\
++	 &(VECT_VAR(vldX_result_bis_##X, T1, W, N)[Y*N]),	\
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  DECL_VLDX(poly, 64, 1, 2);
++  DECL_VLDX(poly, 64, 1, 3);
++  DECL_VLDX(poly, 64, 1, 4);
++
++  VECT_ARRAY_INIT2(buffer_vld2, poly, 64, 1);
++  PAD(buffer_vld2_pad, poly, 64, 1);
++  VECT_ARRAY_INIT3(buffer_vld3, poly, 64, 1);
++  PAD(buffer_vld3_pad, poly, 64, 1);
++  VECT_ARRAY_INIT4(buffer_vld4, poly, 64, 1);
++  PAD(buffer_vld4_pad, poly, 64, 1);
++
++#undef TEST_MSG
++#define TEST_MSG "VLD2/VLD2Q"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX(, poly, p, 64, 1, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 2, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_1, "chunk 1");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD3/VLD3Q"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX(, poly, p, 64, 1, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 3, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 3, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_2, "chunk 2");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD4/VLD4Q"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX(, poly, p, 64, 1, 4);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_2, "chunk 2");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_3, "chunk 3");
++
++  /* vldX_dup_p64 tests.  */
++#define DECL_VLDX_DUP(T1, W, N, X)					\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X); \
++  VECT_VAR_DECL(vldX_dup_result_bis_##X, T1, W, N)[X * N]
++
++#define TEST_VLDX_DUP(Q, T1, T2, W, N, X)				\
++  VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X) =			\
++    vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]);	\
++    									\
++  vst##X##Q##_##T2##W(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N),	\
++		      VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X));	\
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_dup_result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  /* Overwrite "result" with the contents of "result_bis"[Y].  */
++#define TEST_VLDX_DUP_EXTRA_CHUNK(T1, W, N, X,Y)		\
++  memcpy(VECT_VAR(result, T1, W, N),				\
++	 &(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N)[Y*N]),	\
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  DECL_VLDX_DUP(poly, 64, 1, 2);
++  DECL_VLDX_DUP(poly, 64, 1, 3);
++  DECL_VLDX_DUP(poly, 64, 1, 4);
++
++
++#undef TEST_MSG
++#define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP(, poly, p, 64, 1, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 2, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_1, "chunk 1");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP(, poly, p, 64, 1, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_2, "chunk 2");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP(, poly, p, 64, 1, 4);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_2, "chunk 2");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_3, "chunk 3");
++
++  /* vsli_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VSLI"
++
++#define TEST_VSXI1(INSN, Q, T1, T2, W, N, V)				\
++  VECT_VAR(vsXi_vector_res, T1, W, N) =					\
++    INSN##Q##_n_##T2##W(VECT_VAR(vsXi_vector, T1, W, N),		\
++		      VECT_VAR(vsXi_vector2, T1, W, N),			\
++		      V);						\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vsXi_vector_res, T1, W, N))
++
++#define TEST_VSXI(INSN, Q, T1, T2, W, N, V)	\
++  TEST_VSXI1(INSN, Q, T1, T2, W, N, V)
++
++  DECL_VARIABLE(vsXi_vector, poly, 64, 1);
++  DECL_VARIABLE(vsXi_vector, poly, 64, 2);
++  DECL_VARIABLE(vsXi_vector2, poly, 64, 1);
++  DECL_VARIABLE(vsXi_vector2, poly, 64, 2);
++  DECL_VARIABLE(vsXi_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vsXi_vector_res, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vsXi_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2);
++
++  VDUP(vsXi_vector2, , poly, p, 64, 1, 2);
++  VDUP(vsXi_vector2, q, poly, p, 64, 2, 3);
++
++  TEST_VSXI(vsli, , poly, p, 64, 1, 3);
++  TEST_VSXI(vsli, q, poly, p, 64, 2, 53);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected, "");
++
++  /* Test cases with maximum shift amount.  */
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VSXI(vsli, , poly, p, 64, 1, 63);
++  TEST_VSXI(vsli, q, poly, p, 64, 2, 63);
++
++#define COMMENT "(max shift amount)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected_max_shift, COMMENT);
++
++  /* vsri_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VSRI"
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vsXi_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2);
++
++  VDUP(vsXi_vector2, , poly, p, 64, 1, 2);
++  VDUP(vsXi_vector2, q, poly, p, 64, 2, 3);
++
++  TEST_VSXI(vsri, , poly, p, 64, 1, 3);
++  TEST_VSXI(vsri, q, poly, p, 64, 2, 53);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected, "");
++
++  /* Test cases with maximum shift amount.  */
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VSXI(vsri, , poly, p, 64, 1, 64);
++  TEST_VSXI(vsri, q, poly, p, 64, 2, 64);
++
++#define COMMENT "(max shift amount)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected_max_shift, COMMENT);
++
++  /* vst1_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VST1_LANE/VST1_LANEQ"
++
++#define TEST_VST1_LANE(Q, T1, T2, W, N, L)				\
++  VECT_VAR(vst1_lane_vector, T1, W, N) =				\
++    vld1##Q##_##T2##W(VECT_VAR(buffer, T1, W, N));			\
++  vst1##Q##_lane_##T2##W(VECT_VAR(result, T1, W, N),			\
++			 VECT_VAR(vst1_lane_vector, T1, W, N), L);
++
++  DECL_VARIABLE(vst1_lane_vector, poly, 64, 1);
++  DECL_VARIABLE(vst1_lane_vector, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VST1_LANE(, poly, p, 64, 1, 0);
++  TEST_VST1_LANE(q, poly, p, 64, 2, 0);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vst1_lane_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vst1_lane_expected, "");
++
++#ifdef __aarch64__
++
++  /* vmov_n_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VMOV/VMOVQ"
++
++#define TEST_VMOV(Q, T1, T2, W, N)					\
++  VECT_VAR(vmov_n_vector, T1, W, N) =					\
++    vmov##Q##_n_##T2##W(VECT_VAR(buffer_dup, T1, W, N)[i]);		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vmov_n_vector, T1, W, N))
++
++  DECL_VARIABLE(vmov_n_vector, poly, 64, 1);
++  DECL_VARIABLE(vmov_n_vector, poly, 64, 2);
++
++  /* Try to read different places from the input buffer.  */
++  for (i=0; i< 3; i++) {
++    CLEAN(result, poly, 64, 1);
++    CLEAN(result, poly, 64, 2);
++
++    TEST_VMOV(, poly, p, 64, 1);
++    TEST_VMOV(q, poly, p, 64, 2);
++
++    switch (i) {
++    case 0:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vmov_n_expected0, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vmov_n_expected0, "");
++      break;
++    case 1:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vmov_n_expected1, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vmov_n_expected1, "");
++      break;
++    case 2:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vmov_n_expected2, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vmov_n_expected2, "");
++      break;
++    default:
++      abort();
++    }
++  }
++
++  /* vget_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VGET_LANE/VGETQ_LANE"
++
++#define TEST_VGET_LANE(Q, T1, T2, W, N, L)				   \
++  VECT_VAR(vget_lane_vector, T1, W, N) = vget##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), L); \
++  if (VECT_VAR(vget_lane_vector, T1, W, N) != VECT_VAR(vget_lane_expected, T1, W, N)) {		\
++    fprintf(stderr,							   \
++	    "ERROR in %s (%s line %d in result '%s') at type %s "	   \
++	    "got 0x%" PRIx##W " != 0x%" PRIx##W "\n",			   \
++	    TEST_MSG, __FILE__, __LINE__,				   \
++	    STR(VECT_VAR(vget_lane_expected, T1, W, N)),		   \
++	    STR(VECT_NAME(T1, W, N)),					   \
++	    (uint##W##_t)VECT_VAR(vget_lane_vector, T1, W, N),		   \
++	    (uint##W##_t)VECT_VAR(vget_lane_expected, T1, W, N));	   \
++    abort ();								   \
++  }
++
++  /* Initialize input values.  */
++  DECL_VARIABLE(vector, poly, 64, 1);
++  DECL_VARIABLE(vector, poly, 64, 2);
++
++  VLOAD(vector, buffer,  , poly, p, 64, 1);
++  VLOAD(vector, buffer, q, poly, p, 64, 2);
++
++  VECT_VAR_DECL(vget_lane_vector, poly, 64, 1);
++  VECT_VAR_DECL(vget_lane_vector, poly, 64, 2);
++
++  TEST_VGET_LANE( , poly, p, 64, 1, 0);
++  TEST_VGET_LANE(q, poly, p, 64, 2, 0);
++
++  /* vldx_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLDX_LANE/VLDXQ_LANE"
++
++VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 64, 2);
++VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 64, 3);
++VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 64, 4);
++
++  /* In this case, input variables are arrays of vectors.  */
++#define DECL_VLD_STX_LANE(T1, W, N, X)					\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X);	\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector_src, T1, W, N, X);	\
++  VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
++
++  /* We need to use a temporary result buffer (result_bis), because
++     the one used for other tests is not large enough. A subset of the
++     result data is moved from result_bis to result, and it is this
++     subset which is used to check the actual behavior. The next
++     macro enables to move another chunk of data from result_bis to
++     result.  */
++  /* We also use another extra input buffer (buffer_src), which we
++     fill with 0xAA, and which it used to load a vector from which we
++     read a given lane.  */
++
++#define TEST_VLDX_LANE(Q, T1, T2, W, N, X, L)				\
++  memset (VECT_VAR(buffer_src, T1, W, N), 0xAA,				\
++	  sizeof(VECT_VAR(buffer_src, T1, W, N)));			\
++									\
++  VECT_ARRAY_VAR(vector_src, T1, W, N, X) =				\
++    vld##X##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N));		\
++									\
++  VECT_ARRAY_VAR(vector, T1, W, N, X) =					\
++    /* Use dedicated init buffer, of size.  X */			\
++    vld##X##Q##_lane_##T2##W(VECT_VAR(buffer_vld##X##_lane, T1, W, X),	\
++			     VECT_ARRAY_VAR(vector_src, T1, W, N, X),	\
++			     L);					\
++  vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N),		\
++		      VECT_ARRAY_VAR(vector, T1, W, N, X));		\
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)))
++
++  /* Overwrite "result" with the contents of "result_bis"[Y].  */
++#undef TEST_EXTRA_CHUNK
++#define TEST_EXTRA_CHUNK(T1, W, N, X, Y)		\
++  memcpy(VECT_VAR(result, T1, W, N),			\
++	 &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]),	\
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  /* Add some padding to try to catch out of bound accesses.  */
++#define ARRAY1(V, T, W, N) VECT_VAR_DECL(V,T,W,N)[1]={42}
++#define DUMMY_ARRAY(V, T, W, N, L) \
++  VECT_VAR_DECL(V,T,W,N)[N*L]={0}; \
++  ARRAY1(V##_pad,T,W,N)
++
++#define DECL_ALL_VLD_STX_LANE(X)     \
++  DECL_VLD_STX_LANE(poly, 64, 1, X); \
++  DECL_VLD_STX_LANE(poly, 64, 2, X);
++
++#define TEST_ALL_VLDX_LANE(X)		  \
++  TEST_VLDX_LANE(, poly, p, 64, 1, X, 0); \
++  TEST_VLDX_LANE(q, poly, p, 64, 2, X, 0);
++
++#define TEST_ALL_EXTRA_CHUNKS(X,Y)	     \
++  TEST_EXTRA_CHUNK(poly, 64, 1, X, Y) \
++  TEST_EXTRA_CHUNK(poly, 64, 2, X, Y)
++
++#define CHECK_RESULTS_VLD_STX_LANE(test_name,EXPECTED,comment)		\
++  CHECK_POLY(test_name, poly, 64, 1, PRIx64, EXPECTED, comment);	\
++  CHECK_POLY(test_name, poly, 64, 2, PRIx64, EXPECTED, comment);
++
++  /* Declare the temporary buffers / variables.  */
++  DECL_ALL_VLD_STX_LANE(2);
++  DECL_ALL_VLD_STX_LANE(3);
++  DECL_ALL_VLD_STX_LANE(4);
++
++  DUMMY_ARRAY(buffer_src, poly, 64, 1, 4);
++  DUMMY_ARRAY(buffer_src, poly, 64, 2, 4);
++
++  /* Check vld2_lane/vld2q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VLD2_LANE/VLD2Q_LANE"
++  TEST_ALL_VLDX_LANE(2);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st2_0, " chunk 0");
++
++  TEST_ALL_EXTRA_CHUNKS(2, 1);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st2_1, " chunk 1");
++
++  /* Check vld3_lane/vld3q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VLD3_LANE/VLD3Q_LANE"
++  TEST_ALL_VLDX_LANE(3);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st3_0, " chunk 0");
++
++  TEST_ALL_EXTRA_CHUNKS(3, 1);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st3_1, " chunk 1");
++
++  TEST_ALL_EXTRA_CHUNKS(3, 2);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st3_2, " chunk 2");
++
++  /* Check vld4_lane/vld4q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VLD4_LANE/VLD4Q_LANE"
++  TEST_ALL_VLDX_LANE(4);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_0, " chunk 0");
++
++  TEST_ALL_EXTRA_CHUNKS(4, 1);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_1, " chunk 1");
++
++  TEST_ALL_EXTRA_CHUNKS(4, 2);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_2, " chunk 2");
++
++  TEST_ALL_EXTRA_CHUNKS(4, 3);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_3, " chunk 3");
++
++  /* In this case, input variables are arrays of vectors.  */
++#define DECL_VSTX_LANE(T1, W, N, X)					\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X);	\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector_src, T1, W, N, X);	\
++  VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
++
++  /* We need to use a temporary result buffer (result_bis), because
++     the one used for other tests is not large enough. A subset of the
++     result data is moved from result_bis to result, and it is this
++     subset which is used to check the actual behavior. The next
++     macro enables to move another chunk of data from result_bis to
++     result.  */
++  /* We also use another extra input buffer (buffer_src), which we
++     fill with 0xAA, and which it used to load a vector from which we
++     read a given lane.  */
++#define TEST_VSTX_LANE(Q, T1, T2, W, N, X, L)				 \
++  memset (VECT_VAR(buffer_src, T1, W, N), 0xAA,				 \
++	  sizeof(VECT_VAR(buffer_src, T1, W, N)));			 \
++  memset (VECT_VAR(result_bis_##X, T1, W, N), 0,			 \
++	  sizeof(VECT_VAR(result_bis_##X, T1, W, N)));			 \
++									 \
++  VECT_ARRAY_VAR(vector_src, T1, W, N, X) =				 \
++    vld##X##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N));		 \
++									 \
++  VECT_ARRAY_VAR(vector, T1, W, N, X) =					 \
++    /* Use dedicated init buffer, of size X.  */			 \
++    vld##X##Q##_lane_##T2##W(VECT_VAR(buffer_vld##X##_lane, T1, W, X),	 \
++			     VECT_ARRAY_VAR(vector_src, T1, W, N, X),	 \
++			     L);					 \
++  vst##X##Q##_lane_##T2##W(VECT_VAR(result_bis_##X, T1, W, N),		 \
++			   VECT_ARRAY_VAR(vector, T1, W, N, X),		 \
++			   L);						 \
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++#define TEST_ALL_VSTX_LANE(X)		  \
++  TEST_VSTX_LANE(, poly, p, 64, 1, X, 0); \
++  TEST_VSTX_LANE(q, poly, p, 64, 2, X, 0);
++
++  /* Check vst2_lane/vst2q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VST2_LANE/VST2Q_LANE"
++  TEST_ALL_VSTX_LANE(2);
++
++#define CMT " (chunk 0)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st2_0, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(2, 1);
++#undef CMT
++#define CMT " chunk 1"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st2_1, CMT);
++
++  /* Check vst3_lane/vst3q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VST3_LANE/VST3Q_LANE"
++  TEST_ALL_VSTX_LANE(3);
++
++#undef CMT
++#define CMT " (chunk 0)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st3_0, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(3, 1);
++
++#undef CMT
++#define CMT " (chunk 1)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st3_1, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(3, 2);
++
++#undef CMT
++#define CMT " (chunk 2)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st3_2, CMT);
++
++  /* Check vst4_lane/vst4q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VST4_LANE/VST4Q_LANE"
++  TEST_ALL_VSTX_LANE(4);
++
++#undef CMT
++#define CMT " (chunk 0)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_0, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(4, 1);
++
++#undef CMT
++#define CMT " (chunk 1)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_1, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(4, 2);
++
++#undef CMT
++#define CMT " (chunk 2)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_2, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(4, 3);
++
++#undef CMT
++#define CMT " (chunk 3)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_3, CMT);
++
++#endif /* __aarch64__.  */
++
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc
+@@ -0,0 +1,206 @@
++/* Template file for ternary scalar operator validation.
++
++   This file is meant to be included by test files for binary scalar
++   operations.  */
++
++/* Check for required settings.  */
++
++#ifndef INSN_NAME
++#error INSN_NAME (the intrinsic to test) must be defined.
++#endif
++
++#ifndef INPUT_TYPE
++#error INPUT_TYPE (basic type of an input value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE
++#error OUTPUT_TYPE (basic type of an output value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE_SIZE
++#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
++#endif
++
++/* Optional settings:
++
++   INPUT_1: Input values for the first parameter.  Must be of type INPUT_TYPE.
++   INPUT_2: Input values for the second parameter.  Must be of type INPUT_TYPE.
++   INPUT_3: Input values for the third parameter.  Must be of type
++   INPUT_TYPE.  */
++
++#ifndef TEST_MSG
++#define TEST_MSG "unnamed test"
++#endif
++
++/* The test framework.  */
++
++#include <stdio.h>
++
++extern void abort ();
++
++#define INFF __builtin_inf ()
++
++/* Stringify a macro.  */
++#define STR0(A) #A
++#define STR(A) STR0 (A)
++
++/* Macro concatenation.  */
++#define CAT0(A, B) A##B
++#define CAT(A, B) CAT0 (A, B)
++
++/* Format strings for error reporting.  */
++#define FMT16 "0x%04x"
++#define FMT32 "0x%08x"
++#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
++
++/* Type construction: forms TS_t, where T is the base type and S the size in
++   bits.  */
++#define MK_TYPE0(T, S) T##S##_t
++#define MK_TYPE(T, S) MK_TYPE0 (T, S)
++
++/* Convenience types for input and output data.  */
++typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
++
++/* Conversion between typed values and their hexadecimal representation.  */
++typedef union
++{
++  OUTPUT_TYPE value;
++  output_hex_type hex;
++} output_conv_type;
++
++/* Default input values.  */
++
++float16_t input_1_float16_t[] =
++{
++  0.0,
++  -0.0,
++  2.0,
++  3.1,
++  20.0,
++  0.40,
++  -2.3,
++  1.33,
++  -7.6,
++  0.31,
++  0.3353,
++  0.5,
++  1.0,
++  13.13,
++  -6.3,
++  20.0,
++  (float16_t)INFF,
++  (float16_t)-INFF,
++};
++
++float16_t input_2_float16_t[] =
++{
++  1.0,
++  1.0,
++  -4.33,
++  100.0,
++  30.0,
++  -0.02,
++  0.5,
++  -7.231,
++  -6.3,
++  20.0,
++  -7.231,
++  2.3,
++  -7.6,
++  5.1,
++  0.31,
++  0.33353,
++  (float16_t)-INFF,
++  (float16_t)INFF,
++};
++
++float16_t input_3_float16_t[] =
++{
++  -0.0,
++  0.0,
++  0.31,
++  -0.31,
++  1.31,
++  2.1,
++  -6.3,
++  1.0,
++  -1.5,
++  5.1,
++  0.3353,
++  9.3,
++  -9.3,
++  -7.231,
++  0.5,
++  -0.33,
++  (float16_t)INFF,
++  (float16_t)INFF,
++};
++
++#ifndef INPUT_1
++#define INPUT_1 CAT (input_1_,INPUT_TYPE)
++#endif
++
++#ifndef INPUT_2
++#define INPUT_2 CAT (input_2_,INPUT_TYPE)
++#endif
++
++#ifndef INPUT_3
++#define INPUT_3 CAT (input_3_,INPUT_TYPE)
++#endif
++
++/* Support macros and routines for the test function.  */
++
++#define CHECK()							\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
++    actual.value = INSN_NAME ((INPUT_1)[index],			\
++			      (INPUT_2)[index],			\
++			      (INPUT_3)[index]);		\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++/* The test function.  */
++
++void
++FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
++     against EXPECTED[i].  */
++
++  const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]);
++  int index;
++
++  for (index = 0; index < num_tests; index++)
++    CHECK ();
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS ();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
+@@ -61,11 +61,11 @@ void FNNAME (INSN_NAME) (void)
+   TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat, "");
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 16, 4, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 32, 2, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
++  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 16, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 32, 4, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
++  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ 
+ #ifdef EXTRA_TESTS
+   EXTRA_TESTS();
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc
+@@ -0,0 +1,200 @@
++/* Template file for unary scalar operator validation.
++
++   This file is meant to be included by test files for unary scalar
++   operations.  */
++
++/* Check for required settings.  */
++
++#ifndef INSN_NAME
++#error INSN_NAME (the intrinsic to test) must be defined.
++#endif
++
++#ifndef INPUT_TYPE
++#error INPUT_TYPE (basic type of an input value) must be defined.
++#endif
++
++#ifndef SCALAR_OPERANDS
++#ifndef EXPECTED
++#error EXPECTED (an array of expected output values) must be defined.
++#endif
++#endif
++
++#ifndef OUTPUT_TYPE
++#error OUTPUT_TYPE (basic type of an output value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE_SIZE
++#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
++#endif
++
++/* Optional settings.  */
++
++/* SCALAR_OPERANDS: Defined iff the intrinsic has a scalar operand.
++
++   SCALAR_1, SCALAR_2, .., SCALAR_4: If SCALAR_OPERANDS is defined, SCALAR_<n>
++   is the scalar and EXPECTED_<n> is array of expected values.
++
++   INPUT: Input values for the first parameter.  Must be of type INPUT_TYPE.  */
++
++/* Additional comments for the error message.  */
++#ifndef COMMENT
++#define COMMENT ""
++#endif
++
++#ifndef TEST_MSG
++#define TEST_MSG "unnamed test"
++#endif
++
++/* The test framework.  */
++
++#include <stdio.h>
++
++extern void abort ();
++
++#define INFF __builtin_inf ()
++
++/* Stringify a macro.  */
++#define STR0(A) #A
++#define STR(A) STR0 (A)
++
++/* Macro concatenation.  */
++#define CAT0(A, B) A##B
++#define CAT(A, B) CAT0 (A, B)
++
++/* Format strings for error reporting.  */
++#define FMT16 "0x%04x"
++#define FMT32 "0x%08x"
++#define FMT64 "0x%016x"
++#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
++
++/* Type construction: forms TS_t, where T is the base type and S the size in
++   bits.  */
++#define MK_TYPE0(T, S) T##S##_t
++#define MK_TYPE(T, S) MK_TYPE0 (T, S)
++
++/* Convenience types for input and output data.  */
++typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
++
++/* Conversion between typed values and their hexadecimal representation.  */
++typedef union
++{
++  OUTPUT_TYPE value;
++  output_hex_type hex;
++} output_conv_type;
++
++/* Default input values.  */
++
++float16_t input_1_float16_t[] =
++{
++  0.0, -0.0,
++  2.0, 3.1,
++  20.0, 0.40,
++  -2.3, 1.33,
++  -7.6, 0.31,
++  0.3353, 0.5,
++  1.0, 13.13,
++  -6.3, 20.0,
++  (float16_t)INFF, (float16_t)-INFF,
++};
++
++#ifndef INPUT
++#define INPUT CAT(input_1_,INPUT_TYPE)
++#endif
++
++/* Support macros and routines for the test function.  */
++
++#define CHECK()							\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
++    actual.value = INSN_NAME ((INPUT)[index]);			\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define CHECK_N(SCALAR, EXPECTED)				\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex							\
++      = ((output_hex_type*)EXPECTED)[index];			\
++    actual.value = INSN_NAME ((INPUT)[index], (SCALAR));	\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++/* The test function.  */
++
++void
++FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
++     against EXPECTED[i].  */
++
++  const int num_tests = sizeof (INPUT) / sizeof (INPUT[0]);
++  int index;
++
++  for (index = 0; index < num_tests; index++)
++    {
++#if defined (SCALAR_OPERANDS)
++
++#ifdef SCALAR_1
++      CHECK_N (SCALAR_1, EXPECTED_1);
++#endif
++#ifdef SCALAR_2
++      CHECK_N (SCALAR_2, EXPECTED_2);
++#endif
++#ifdef SCALAR_3
++      CHECK_N (SCALAR_3, EXPECTED_3);
++#endif
++#ifdef SCALAR_4
++      CHECK_N (SCALAR_4, EXPECTED_4);
++#endif
++
++#else /* !defined (SCALAR_OPERAND).  */
++      CHECK ();
++#endif
++    }
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS ();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c
+@@ -30,10 +30,20 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffd0, 0xffffffd1,
+ 					 0xffffffd2, 0xffffffd3 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x42407ae1, 0x423c7ae1,
+ 					   0x42387ae1, 0x42347ae1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x4e13, 0x4dd3,
++					      0x4d93, 0x4d53 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x5204, 0x51e4, 0x51c4, 0x51a4,
++					      0x5184, 0x5164, 0x5144, 0x5124 };
++#endif
+ 
+ /* Additional expected results for float32 variants with specially
+    chosen input values.  */
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						      0x0, 0x0, 0x0, 0x0 };
++#endif
+ 
+ #define TEST_MSG "VABD/VABDQ"
+ void exec_vabd (void)
+@@ -65,6 +75,17 @@ void exec_vabd (void)
+   DECL_VABD_VAR(vector2);
+   DECL_VABD_VAR(vector_res);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector1, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
+@@ -82,6 +103,12 @@ void exec_vabd (void)
+   VLOAD(vector1, buffer, q, uint, u, 16, 8);
+   VLOAD(vector1, buffer, q, uint, u, 32, 4);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+ 
+   /* Choose init value arbitrarily.  */
+   VDUP(vector2, , int, s, 8, 8, 1);
+@@ -98,6 +125,10 @@ void exec_vabd (void)
+   VDUP(vector2, q, uint, u, 16, 8, 12);
+   VDUP(vector2, q, uint, u, 32, 4, 32);
+   VDUP(vector2, q, float, f, 32, 4, 32.12f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 8.3f);
++  VDUP(vector2, q, float, f, 16, 8, 32.12f);
++#endif
+ 
+   /* Execute the tests.  */
+   TEST_VABD(, int, s, 8, 8);
+@@ -115,6 +146,11 @@ void exec_vabd (void)
+   TEST_VABD(q, uint, u, 32, 4);
+   TEST_VABD(q, float, f, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VABD(, float, f, 16, 4);
++  TEST_VABD(q, float, f, 16, 8);
++#endif
++
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+@@ -129,7 +165,10 @@ void exec_vabd (void)
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+-
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+ 
+   /* Extra FP tests with special values (-0.0, ....) */
+   VDUP(vector1, q, float, f, 32, 4, -0.0f);
+@@ -137,11 +176,27 @@ void exec_vabd (void)
+   TEST_VABD(q, float, f, 32, 4);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, " FP special (-0.0)");
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector1, q, float, f, 16, 8, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 0.0);
++  TEST_VABD(q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16,
++	   " FP special (-0.0)");
++#endif
++
+   /* Extra FP tests with special values (-0.0, ....) */
+   VDUP(vector1, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, q, float, f, 32, 4, -0.0);
+   TEST_VABD(q, float, f, 32, 4);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, " FP special (-0.0)");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector1, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, -0.0);
++  TEST_VABD(q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16,
++	   " FP special (-0.0)");
++#endif
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c
+@@ -0,0 +1,44 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results.
++   Absolute difference between INPUT1 and INPUT2 in binary_scalar_op.inc.  */
++uint16_t expected[] =
++{
++  0x3C00,
++  0x3C00,
++  0x4654,
++  0x560E,
++  0x4900,
++  0x36B8,
++  0x419a,
++  0x4848,
++  0x3d34,
++  0x4cec,
++  0x4791,
++  0x3f34,
++  0x484d,
++  0x4804,
++  0x469c,
++  0x4ceb,
++  0x7c00,
++  0x7c00
++};
++
++#define TEST_MSG "VABDH_F16"
++#define INSN_NAME vabdh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c
+@@ -21,24 +21,52 @@ VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd };
+ /* Expected results for float32 variants. Needs to be separated since
+    the generic test function does not test floating-point
+    versions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0x409a, 0x409a,
++						      0x409a, 0x409a };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x42cd, 0x42cd,
++						      0x42cd, 0x42cd,
++						      0x42cd, 0x42cd,
++						      0x42cd, 0x42cd };
++#endif
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40133333, 0x40133333 };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x4059999a, 0x4059999a,
+ 						   0x4059999a, 0x4059999a };
+ 
+ void exec_vabs_f32(void)
+ {
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++#endif
+   VDUP(vector, , float, f, 32, 2, -2.3f);
+   VDUP(vector, q, float, f, 32, 4, 3.4f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_UNARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_UNARY_OP(INSN_NAME, q, float, f, 16, 8);
++#endif
+   TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2);
+   TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4233 /* 3.099609 */,
++  0x4d00 /* 20.000000 */,
++  0x3666 /* 0.399902 */,
++  0x409a /* 2.300781 */,
++  0x3d52 /* 1.330078 */,
++  0x479a /* 7.601562 */,
++  0x34f6 /* 0.310059 */,
++  0x355d /* 0.335205 */,
++  0x3800 /* 0.500000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a91 /* 13.132812 */,
++  0x464d /* 6.300781 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VABSH_F16"
++#define INSN_NAME vabsh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c
+@@ -43,6 +43,14 @@ VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3,
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40d9999a, 0x40d9999a };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x41100000, 0x41100000,
+ 						   0x41100000, 0x41100000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0x46cd, 0x46cd,
++						      0x46cd, 0x46cd };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x4880, 0x4880,
++						      0x4880, 0x4880,
++						      0x4880, 0x4880,
++						      0x4880, 0x4880 };
++#endif
+ 
+ void exec_vadd_f32(void)
+ {
+@@ -66,4 +74,27 @@ void exec_vadd_f32(void)
+ 
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++
++  VDUP(vector, , float, f, 16, 4, 2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++
++  VDUP(vector2, , float, f, 16, 4, 4.5f);
++  VDUP(vector2, q, float, f, 16, 8, 5.6f);
++
++  TEST_BINARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc0a8 /* -2.328125 */,
++  0x5672 /* 103.125000 */,
++  0x5240 /* 50.000000 */,
++  0x3614 /* 0.379883 */,
++  0xbf34 /* -1.800781 */,
++  0xc5e6 /* -5.898438 */,
++  0xcaf4 /* -13.906250 */,
++  0x4d14 /* 20.312500 */,
++  0xc6e5 /* -6.894531 */,
++  0x419a /* 2.800781 */,
++  0xc69a /* -6.601562 */,
++  0x4c8f /* 18.234375 */,
++  0xc5fe /* -5.992188 */,
++  0x4d15 /* 20.328125 */,
++  0x7e00 /* nan */,
++  0x7e00 /* nan */,
++};
++
++#define TEST_MSG "VADDH_F16"
++#define INSN_NAME vaddh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c
+@@ -16,6 +16,10 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffff1 };
+ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 					0xf7, 0xf7, 0xf7, 0xf7 };
+ VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff0, 0xfff2, 0xfff2 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc09, 0xcb89,
++					       0xcb09, 0xca89 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800004, 0xc1700004 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					0xf6, 0xf6, 0xf6, 0xf6,
+@@ -43,6 +47,12 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 					 0xf7, 0xf7, 0xf7, 0xf7 };
+ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff2, 0xfff2,
+ 					 0xfff4, 0xfff4, 0xfff6, 0xfff6 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc09, 0xcb89,
++					       0xcb09, 0xca89,
++					       0xca09, 0xc989,
++					       0xc909, 0xc889 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800001, 0xc1700001,
+ 					   0xc1600001, 0xc1500001 };
+ 
+@@ -66,6 +76,10 @@ void exec_vbsl (void)
+   clean_results ();
+ 
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -80,6 +94,9 @@ void exec_vbsl (void)
+   VDUP(vector2, , uint, u, 16, 4, 0xFFF2);
+   VDUP(vector2, , uint, u, 32, 2, 0xFFFFFFF0);
+   VDUP(vector2, , uint, u, 64, 1, 0xFFFFFFF3);
++#if defined (FP16_SUPPORTED)
++  VDUP(vector2, , float, f, 16, 4, -2.4f);   /* -2.4f is 0xC0CD.  */
++#endif
+   VDUP(vector2, , float, f, 32, 2, -30.3f);
+   VDUP(vector2, , poly, p, 8, 8, 0xF3);
+   VDUP(vector2, , poly, p, 16, 4, 0xFFF2);
+@@ -94,6 +111,9 @@ void exec_vbsl (void)
+   VDUP(vector2, q, uint, u, 64, 2, 0xFFFFFFF3);
+   VDUP(vector2, q, poly, p, 8, 16, 0xF3);
+   VDUP(vector2, q, poly, p, 16, 8, 0xFFF2);
++#if defined (FP16_SUPPORTED)
++  VDUP(vector2, q, float, f, 16, 8, -2.4f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, -30.4f);
+ 
+   VDUP(vector_first, , uint, u, 8, 8, 0xF4);
+@@ -111,10 +131,18 @@ void exec_vbsl (void)
+   TEST_VBSL(uint, , poly, p, 16, 4);
+   TEST_VBSL(uint, q, poly, p, 8, 16);
+   TEST_VBSL(uint, q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VBSL(uint, , float, f, 16, 4);
++  TEST_VBSL(uint, q, float, f, 16, 8);
++#endif
+   TEST_VBSL(uint, , float, f, 32, 2);
+   TEST_VBSL(uint, q, float, f, 32, 4);
+ 
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
+   CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c
+@@ -11,3 +11,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 					  0xffffffff, 0xffffffff };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0xffff, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0x0,
++					     0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
++					      0xffff, 0xffff, 0xffff, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
++			0xFFFF};
++
++#define TEST_MSG "VCAGEH_F16"
++#define INSN_NAME vcageh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c
+@@ -11,3 +11,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 					  0xffffffff, 0xffffffff };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0xffff, 0xffff, 0x0, 0x0,
++					     0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
++					      0xffff, 0xffff, 0x0, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0};
++
++#define TEST_MSG "VCAGTH_F16"
++#define INSN_NAME vcagth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c
+@@ -9,3 +9,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff };
+ 
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0x0, 0x0, 0xffff, 0xffff,
++					     0xffff, 0xffff, 0xffff, 0xffff };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++					      0x0, 0x0, 0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0x0, 0xFFFF, 0xFFFF};
++
++#define TEST_MSG "VCALEH_F16"
++#define INSN_NAME vcaleh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c
+@@ -9,3 +9,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff };
+ 
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0x0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0xffff,
++					     0xffff, 0xffff, 0xffff, 0xffff };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++					      0x0, 0x0, 0x0, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0x0, 0x0, 0x0};
++
++#define TEST_MSG "VCALTH_F16"
++#define INSN_NAME vcalth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c
+@@ -32,6 +32,12 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 						0x0, 0x0, 0xffff, 0x0 };
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0xffff, 0x0, 0x0 };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0xffff, 0x0,
++						     0x0, 0x0, 0x0, 0x0, };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0x0 };
+ 
+@@ -39,6 +45,18 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++
++#define TEST_MSG "VCEQH_F16"
++#define INSN_NAME vceqh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c
+@@ -0,0 +1,27 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vceqz
++#define TEST_MSG "VCEQZ/VCEQZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						     0x0, 0x0, 0x0, 0x0 };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++
++#define TEST_MSG "VCEQZH_F16"
++#define INSN_NAME vceqzh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c
+@@ -28,6 +28,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 						0, 0x0, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff };
+ 
+@@ -35,6 +43,20 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0xFFFF, 0x0};
++
++#define TEST_MSG "VCGEH_F16"
++#define INSN_NAME vcgeh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c
+@@ -0,0 +1,30 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vcgez
++#define TEST_MSG "VCGEZ/VCGEZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0,
++			0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
++			0x0, 0xFFFF, 0xFFFF, 0x0};
++
++#define TEST_MSG "VCGEZH_F16"
++#define INSN_NAME vcgezh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c
+@@ -28,6 +28,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 						0x0, 0x0, 0x0, 0xffff };
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0,
++						     0x0, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff };
+ 
+@@ -35,6 +43,19 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0x0, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0xFFFF, 0x0};
++
++#define TEST_MSG "VCGTH_F16"
++#define INSN_NAME vcgth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c
+@@ -0,0 +1,28 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vcgtz
++#define TEST_MSG "VCGTZ/VCGTZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0,
++			0xFFFF, 0xFFFF, 0x0};
++
++#define TEST_MSG "VCGTZH_F16"
++#define INSN_NAME vcgtzh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c
+@@ -31,6 +31,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff, 0x0, 0x0 };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0xffff, 0x0,
++						     0x0, 0x0,
++						     0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						 0xffffffff, 0x0 };
+@@ -39,6 +47,20 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0,
++			0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0x0,
++			0xFFFF};
++
++#define TEST_MSG "VCLEH_F16"
++#define INSN_NAME vcleh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclez_1.c
+@@ -0,0 +1,29 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vclez
++#define TEST_MSG "VCLEZ/VCLEZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF};
++
++#define TEST_MSG "VCLEZH_F16"
++#define INSN_NAME vclezh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c
+@@ -30,6 +30,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						0x0, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0x0, 0x0,
++						     0x0, 0x0,
++						     0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						 0x0, 0x0 };
+@@ -38,6 +46,19 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0x0, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0,
++			0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0x0,
++			0xFFFF};
++
++#define TEST_MSG "VCLTH_F16"
++#define INSN_NAME vclth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c
+@@ -0,0 +1,27 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vcltz
++#define TEST_MSG "VCLTZ/VCLTZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF};
++
++#define TEST_MSG "VCltZH_F16"
++#define INSN_NAME vcltzh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c
+@@ -65,10 +65,10 @@ FNNAME (INSN_NAME)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c
+@@ -93,8 +93,8 @@ void exec_vcombine (void)
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
+ #endif
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c
+@@ -106,8 +106,8 @@ FNNAME (INSN_NAME)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
+ #endif
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c
+@@ -4,36 +4,99 @@
+ #include <math.h>
+ 
+ /* Expected results for vcvt.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_s, hfloat, 16, 4) [] =
++{ 0xcc00, 0xcb80, 0xcb00, 0xca80 };
++VECT_VAR_DECL(expected_u, hfloat, 16, 4) [] =
++{ 0x7c00, 0x7c00, 0x7c00, 0x7c00, };
++VECT_VAR_DECL(expected_s, hfloat, 16, 8) [] =
++{ 0xcc00, 0xcb80, 0xcb00, 0xca80,
++  0xca00, 0xc980, 0xc900, 0xc880 };
++VECT_VAR_DECL(expected_u, hfloat, 16, 8) [] =
++{ 0x7c00, 0x7c00, 0x7c00, 0x7c00,
++  0x7c00, 0x7c00, 0x7c00, 0x7c00, };
++#endif
+ VECT_VAR_DECL(expected_s,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_u,hfloat,32,2) [] = { 0x4f800000, 0x4f800000 };
+ VECT_VAR_DECL(expected_s,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+-					   0xc1600000, 0xc1500000 };
++					     0xc1600000, 0xc1500000 };
+ VECT_VAR_DECL(expected_u,hfloat,32,4) [] = { 0x4f800000, 0x4f800000,
+-					   0x4f800000, 0x4f800000 };
++					     0x4f800000, 0x4f800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x5, 0xfff1, 0x5 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff1,
++					   0x0, 0x0, 0xf, 0xfff1 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0,
++					    0x0, 0x0, 0xf, 0x0 };
++#endif
+ VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0x5 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x5 };
+ VECT_VAR_DECL(expected,int,32,4) [] = { 0x0, 0x0, 0xf, 0xfffffff1 };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xf, 0x0 };
+ 
+ /* Expected results for vcvt_n.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n_s, hfloat, 16, 4) [] = { 0xc400, 0xc380,
++						       0xc300, 0xc280 };
++VECT_VAR_DECL(expected_vcvt_n_u, hfloat, 16, 4) [] = { 0x6000, 0x6000,
++						       0x6000, 0x6000 };
++VECT_VAR_DECL(expected_vcvt_n_s, hfloat, 16, 8) [] = { 0xb000, 0xaf80,
++						       0xaf00, 0xae80,
++						       0xae00, 0xad80,
++						       0xad00, 0xac80 };
++VECT_VAR_DECL(expected_vcvt_n_u, hfloat, 16, 8) [] = { 0x4c00, 0x4c00,
++						       0x4c00, 0x4c00,
++						       0x4c00, 0x4c00,
++						       0x4c00, 0x4c00 };
++#endif
+ VECT_VAR_DECL(expected_vcvt_n_s,hfloat,32,2) [] = { 0xc0800000, 0xc0700000 };
+ VECT_VAR_DECL(expected_vcvt_n_u,hfloat,32,2) [] = { 0x4c000000, 0x4c000000 };
+ VECT_VAR_DECL(expected_vcvt_n_s,hfloat,32,4) [] = { 0xb2800000, 0xb2700000,
+ 						  0xb2600000, 0xb2500000 };
+ VECT_VAR_DECL(expected_vcvt_n_u,hfloat,32,4) [] = { 0x49800000, 0x49800000,
+ 						  0x49800000, 0x49800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n, int, 16, 4) [] = { 0xffc3, 0x15,
++						  0xffc3, 0x15 };
++VECT_VAR_DECL(expected_vcvt_n, uint, 16, 4) [] = { 0x0, 0x2a6, 0x0, 0x2a6 };
++VECT_VAR_DECL(expected_vcvt_n, int, 16, 8) [] = { 0x0, 0x0, 0x78f, 0xf871,
++						  0x0, 0x0, 0x78f, 0xf871 };
++VECT_VAR_DECL(expected_vcvt_n, uint, 16, 8) [] = { 0x0, 0x0, 0xf1e0, 0x0,
++						   0x0, 0x0, 0xf1e0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_vcvt_n,int,32,2) [] = { 0xff0b3333, 0x54cccd };
+ VECT_VAR_DECL(expected_vcvt_n,uint,32,2) [] = { 0x0, 0x15 };
+ VECT_VAR_DECL(expected_vcvt_n,int,32,4) [] = { 0x0, 0x0, 0x1e3d7, 0xfffe1c29 };
+ VECT_VAR_DECL(expected_vcvt_n,uint,32,4) [] = { 0x0, 0x0, 0x1e, 0x0 };
+ 
+ /* Expected results for vcvt with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						    0x7d, 0x7d, 0x7d, 0x7d };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						     0x7d, 0x7d, 0x7d, 0x7d };
++#endif
+ VECT_VAR_DECL(expected_rounding,int,32,2) [] = { 0xa, 0xa };
+ VECT_VAR_DECL(expected_rounding,uint,32,2) [] = { 0xa, 0xa };
+ VECT_VAR_DECL(expected_rounding,int,32,4) [] = { 0x7d, 0x7d, 0x7d, 0x7d };
+ VECT_VAR_DECL(expected_rounding,uint,32,4) [] = { 0x7d, 0x7d, 0x7d, 0x7d };
+ 
+ /* Expected results for vcvt_n with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n_rounding, int, 16, 4) [] =
++{ 0x533, 0x533, 0x533, 0x533 };
++VECT_VAR_DECL(expected_vcvt_n_rounding, uint, 16, 4) [] =
++{ 0x533, 0x533, 0x533, 0x533 };
++VECT_VAR_DECL(expected_vcvt_n_rounding, int, 16, 8) [] =
++{ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
++  0x7fff, 0x7fff, 0x7fff, 0x7fff };
++VECT_VAR_DECL(expected_vcvt_n_rounding, uint, 16, 8) [] =
++{ 0xffff, 0xffff, 0xffff, 0xffff,
++  0xffff, 0xffff, 0xffff, 0xffff };
++#endif
+ VECT_VAR_DECL(expected_vcvt_n_rounding,int,32,2) [] = { 0xa66666, 0xa66666 };
+ VECT_VAR_DECL(expected_vcvt_n_rounding,uint,32,2) [] = { 0xa66666, 0xa66666 };
+ VECT_VAR_DECL(expected_vcvt_n_rounding,int,32,4) [] = { 0xfbccc, 0xfbccc,
+@@ -42,11 +105,17 @@ VECT_VAR_DECL(expected_vcvt_n_rounding,uint,32,4) [] = { 0xfbccc, 0xfbccc,
+ 						0xfbccc, 0xfbccc };
+ 
+ /* Expected results for vcvt_n with saturation.  */
+-VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,2) [] = { 0x7fffffff,
+-							  0x7fffffff };
+-VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,4) [] = { 0x7fffffff,
+-							  0x7fffffff,
+-					       0x7fffffff, 0x7fffffff };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n_saturation, int, 16, 4) [] =
++{ 0x533, 0x533, 0x533, 0x533 };
++VECT_VAR_DECL(expected_vcvt_n_saturation, int, 16, 8) [] =
++{ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
++  0x7fff, 0x7fff, 0x7fff, 0x7fff };
++#endif
++VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,2) [] =
++{ 0x7fffffff, 0x7fffffff };
++VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,4) [] =
++{ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff };
+ 
+ #define TEST_MSG "VCVT/VCVTQ"
+ void exec_vcvt (void)
+@@ -89,11 +158,26 @@ void exec_vcvt (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Make sure some elements have a fractional part, to exercise
+      integer conversions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, , float, f, 16, 4, 0, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 1, 5.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 2, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 3, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, 5.3f);
++#endif
++
+   VSET_LANE(vector, , float, f, 32, 2, 0, -15.3f);
+   VSET_LANE(vector, , float, f, 32, 2, 1, 5.3f);
+   VSET_LANE(vector, q, float, f, 32, 4, 2, -15.3f);
+@@ -103,23 +187,55 @@ void exec_vcvt (void)
+      before overwriting them.  */
+ #define TEST_MSG2 ""
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_f16_xx.  */
++  TEST_VCVT_FP(, float, f, 16, 4, int, s, expected_s);
++  TEST_VCVT_FP(, float, f, 16, 4, uint, u, expected_u);
++#endif
+   /* vcvt_f32_xx.  */
+   TEST_VCVT_FP(, float, f, 32, 2, int, s, expected_s);
+   TEST_VCVT_FP(, float, f, 32, 2, uint, u, expected_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_f16_xx.  */
++  TEST_VCVT_FP(q, float, f, 16, 8, int, s, expected_s);
++  TEST_VCVT_FP(q, float, f, 16, 8, uint, u, expected_u);
++#endif
+   /* vcvtq_f32_xx.  */
+   TEST_VCVT_FP(q, float, f, 32, 4, int, s, expected_s);
+   TEST_VCVT_FP(q, float, f, 32, 4, uint, u, expected_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_xx_f16.  */
++  TEST_VCVT(, int, s, 16, 4, float, f, expected);
++  TEST_VCVT(, uint, u, 16, 4, float, f, expected);
++#endif
+   /* vcvt_xx_f32.  */
+   TEST_VCVT(, int, s, 32, 2, float, f, expected);
+   TEST_VCVT(, uint, u, 32, 2, float, f, expected);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, q, float, f, 16, 8, 0, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 1, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 2, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 3, -15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, -15.12f);
++#endif
++
+   VSET_LANE(vector, q, float, f, 32, 4, 0, 0.0f);
+   VSET_LANE(vector, q, float, f, 32, 4, 1, -0.0f);
+   VSET_LANE(vector, q, float, f, 32, 4, 2, 15.12f);
+   VSET_LANE(vector, q, float, f, 32, 4, 3, -15.12f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_xx_f16.  */
++  TEST_VCVT(q, int, s, 16, 8, float, f, expected);
++  TEST_VCVT(q, uint, u, 16, 8, float, f, expected);
++#endif
++
+   /* vcvtq_xx_f32.  */
+   TEST_VCVT(q, int, s, 32, 4, float, f, expected);
+   TEST_VCVT(q, uint, u, 32, 4, float, f, expected);
+@@ -129,18 +245,38 @@ void exec_vcvt (void)
+ #undef TEST_MSG
+ #define TEST_MSG "VCVT_N/VCVTQ_N"
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_f16_xx.  */
++  TEST_VCVT_N_FP(, float, f, 16, 4, int, s, 2, expected_vcvt_n_s);
++  TEST_VCVT_N_FP(, float, f, 16, 4, uint, u, 7, expected_vcvt_n_u);
++#endif
+   /* vcvt_n_f32_xx.  */
+   TEST_VCVT_N_FP(, float, f, 32, 2, int, s, 2, expected_vcvt_n_s);
+   TEST_VCVT_N_FP(, float, f, 32, 2, uint, u, 7, expected_vcvt_n_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_f16_xx.  */
++  TEST_VCVT_N_FP(q, float, f, 16, 8, int, s, 7, expected_vcvt_n_s);
++  TEST_VCVT_N_FP(q, float, f, 16, 8, uint, u, 12, expected_vcvt_n_u);
++#endif
+   /* vcvtq_n_f32_xx.  */
+   TEST_VCVT_N_FP(q, float, f, 32, 4, int, s, 30, expected_vcvt_n_s);
+   TEST_VCVT_N_FP(q, float, f, 32, 4, uint, u, 12, expected_vcvt_n_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_xx_f16.  */
++  TEST_VCVT_N(, int, s, 16, 4, float, f, 2, expected_vcvt_n);
++  TEST_VCVT_N(, uint, u, 16, 4, float, f, 7, expected_vcvt_n);
++#endif
+   /* vcvt_n_xx_f32.  */
+   TEST_VCVT_N(, int, s, 32, 2, float, f, 20, expected_vcvt_n);
+   TEST_VCVT_N(, uint, u, 32, 2, float, f, 2, expected_vcvt_n);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_xx_f16.  */
++  TEST_VCVT_N(q, int, s, 16, 8, float, f, 7, expected_vcvt_n);
++  TEST_VCVT_N(q, uint, u, 16, 8, float, f, 12, expected_vcvt_n);
++#endif
+   /* vcvtq_n_xx_f32.  */
+   TEST_VCVT_N(q, int, s, 32, 4, float, f, 13, expected_vcvt_n);
+   TEST_VCVT_N(q, uint, u, 32, 4, float, f, 1, expected_vcvt_n);
+@@ -150,20 +286,49 @@ void exec_vcvt (void)
+ #define TEST_MSG "VCVT/VCVTQ"
+ #undef TEST_MSG2
+ #define TEST_MSG2 "(check rounding)"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 10.4f);
++  VDUP(vector, q, float, f, 16, 8, 125.9f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 10.4f);
+   VDUP(vector, q, float, f, 32, 4, 125.9f);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_xx_f16.  */
++  TEST_VCVT(, int, s, 16, 4, float, f, expected_rounding);
++  TEST_VCVT(, uint, u, 16, 4, float, f, expected_rounding);
++#endif
+   /* vcvt_xx_f32.  */
+   TEST_VCVT(, int, s, 32, 2, float, f, expected_rounding);
+   TEST_VCVT(, uint, u, 32, 2, float, f, expected_rounding);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_xx_f16.  */
++  TEST_VCVT(q, int, s, 16, 8, float, f, expected_rounding);
++  TEST_VCVT(q, uint, u, 16, 8, float, f, expected_rounding);
++#endif
+   /* vcvtq_xx_f32.  */
+   TEST_VCVT(q, int, s, 32, 4, float, f, expected_rounding);
+   TEST_VCVT(q, uint, u, 32, 4, float, f, expected_rounding);
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VCVT_N/VCVTQ_N"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_xx_f16.  */
++  TEST_VCVT_N(, int, s, 16, 4, float, f, 7, expected_vcvt_n_rounding);
++  TEST_VCVT_N(, uint, u, 16, 4, float, f, 7, expected_vcvt_n_rounding);
++#endif
+   /* vcvt_n_xx_f32.  */
+   TEST_VCVT_N(, int, s, 32, 2, float, f, 20, expected_vcvt_n_rounding);
+   TEST_VCVT_N(, uint, u, 32, 2, float, f, 20, expected_vcvt_n_rounding);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_xx_f16.  */
++  TEST_VCVT_N(q, int, s, 16, 8, float, f, 13, expected_vcvt_n_rounding);
++  TEST_VCVT_N(q, uint, u, 16, 8, float, f, 13, expected_vcvt_n_rounding);
++#endif
+   /* vcvtq_n_xx_f32.  */
+   TEST_VCVT_N(q, int, s, 32, 4, float, f, 13, expected_vcvt_n_rounding);
+   TEST_VCVT_N(q, uint, u, 32, 4, float, f, 13, expected_vcvt_n_rounding);
+@@ -172,8 +337,18 @@ void exec_vcvt (void)
+ #define TEST_MSG "VCVT_N/VCVTQ_N"
+ #undef TEST_MSG2
+ #define TEST_MSG2 "(check saturation)"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_xx_f16.  */
++  TEST_VCVT_N(, int, s, 16, 4, float, f, 7, expected_vcvt_n_saturation);
++#endif
+   /* vcvt_n_xx_f32.  */
+   TEST_VCVT_N(, int, s, 32, 2, float, f, 31, expected_vcvt_n_saturation);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_xx_f16.  */
++  TEST_VCVT_N(q, int, s, 16, 8, float, f, 13, expected_vcvt_n_saturation);
++#endif
+   /* vcvtq_n_xx_f32.  */
+   TEST_VCVT_N(q, int, s, 32, 4, float, f, 31, expected_vcvt_n_saturation);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc
+@@ -0,0 +1,113 @@
++/* Template file for VCVT operator validation.
++
++   This file is meant to be included by the relevant test files, which
++   have to define the intrinsic family to test.  If a given intrinsic
++   supports variants which are not supported by all the other vcvt
++   operators, these can be tested by providing a definition for
++   EXTRA_TESTS.
++
++   This file is only used for VCVT? tests, which currently have only f16 to
++   integer variants.  It is based on vcvt.c.  */
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++void FNNAME (INSN_NAME) (void)
++{
++  int i;
++
++  /* Basic test: y=vcvt(x), then store the result.  */
++#define TEST_VCVT1(INSN, Q, T1, T2, W, N, TS1, TS2, EXP)	\
++  VECT_VAR(vector_res, T1, W, N) =				\
++    INSN##Q##_##T2##W##_##TS2##W(VECT_VAR(vector, TS1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),			\
++		    VECT_VAR(vector_res, T1, W, N));		\
++  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXP, TEST_MSG2);
++
++#define TEST_VCVT(INSN, Q, T1, T2, W, N, TS1, TS2, EXP)		\
++  TEST_VCVT1 (INSN, Q, T1, T2, W, N, TS1, TS2, EXP)
++
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++
++  clean_results ();
++
++  /* Initialize input "vector" from "buffer".  */
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++
++  /* Make sure some elements have a fractional part, to exercise
++     integer conversions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, , float, f, 16, 4, 0, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 1, 5.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 2, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 3, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, 5.3f);
++#endif
++
++  /* The same result buffers are used multiple times, so we check them
++     before overwriting them.  */
++#define TEST_MSG2 ""
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?_xx_f16.  */
++  TEST_VCVT(INSN_NAME, , int, s, 16, 4, float, f, expected);
++  TEST_VCVT(INSN_NAME, , uint, u, 16, 4, float, f, expected);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, q, float, f, 16, 8, 0, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 1, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 2, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 3, -15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, -15.12f);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?q_xx_f16.  */
++  TEST_VCVT(INSN_NAME, q, int, s, 16, 8, float, f, expected);
++  TEST_VCVT(INSN_NAME, q, uint, u, 16, 8, float, f, expected);
++#endif
++
++  /* Check rounding.  */
++#undef TEST_MSG2
++#define TEST_MSG2 "(check rounding)"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 10.4f);
++  VDUP(vector, q, float, f, 16, 8, 125.9f);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?_xx_f16.  */
++  TEST_VCVT(INSN_NAME, , int, s, 16, 4, float, f, expected_rounding);
++  TEST_VCVT(INSN_NAME, , uint, u, 16, 4, float, f, expected_rounding);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?q_xx_f16.  */
++  TEST_VCVT(INSN_NAME, q, int, s, 16, 8, float, f, expected_rounding);
++  TEST_VCVT(INSN_NAME, q, uint, u, 16, 8, float, f, expected_rounding);
++#endif
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c
+@@ -0,0 +1,33 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x5, 0xfff1, 0x5 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff1,
++					   0x0, 0x0, 0xf, 0xfff1 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0,
++					    0x0, 0x0, 0xf, 0x0 };
++#endif
++
++/* Expected results with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						    0x7e, 0x7e, 0x7e, 0x7e };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						     0x7e, 0x7e, 0x7e, 0x7e };
++#endif
++
++#define TEST_MSG "VCVTA/VCVTAQ"
++#define INSN_NAME vcvta
++
++#include "vcvtX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTAH_S16_F16"
++#define INSN_NAME vcvtah_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffdd,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffb,
++  0x0000004d,
++  0xffffff6f,
++  0xffffffc7,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTAH_S32_F16"
++#define INSN_NAME vcvtah_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTAH_S64_F16"
++#define INSN_NAME vcvtah_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTAH_u16_F16"
++#define INSN_NAME vcvtah_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000
++};
++
++#define TEST_MSG "VCVTAH_U32_F16"
++#define INSN_NAME vcvtah_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTAH_u64_F16"
++#define INSN_NAME vcvtah_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++int16_t input[] = { 123, -567, 0, 1024, -63, 169, -4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0xE06E /* -567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.  */,
++			0xD3E0 /* -63.  */, 0x5948 /* 169.  */,
++			0xC400 /* -4.  */, 0x54D0 /* 77.  */ };
++
++#define TEST_MSG "VCVTH_F16_S16"
++#define INSN_NAME vcvth_f16_s16
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE int16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
+@@ -0,0 +1,52 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x57b0 /* 123.000000 */,
++  0xe06e /* -567.000000 */,
++  0xd040 /* -34.000000 */,
++  0x6400 /* 1024.000000 */,
++  0xd3e0 /* -63.000000 */,
++  0x5948 /* 169.000000 */,
++  0xc400 /* -4.000000 */,
++  0x54d0 /* 77.000000 */,
++  0xd880 /* -144.000000 */,
++  0xd300 /* -56.000000 */,
++  0xcc00 /* -16.000000 */,
++  0xcb80 /* -15.000000 */,
++  0xcb00 /* -14.000000 */,
++  0xca80 /* -13.000000 */
++};
++
++#define TEST_MSG "VCVTH_F16_S32"
++#define INSN_NAME vcvth_f16_s32
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE uint32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++int64_t input[] = { 123, -567, 0, 1024, -63, 169, -4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0xE06E /* -567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.  */,
++			0xD3E0 /* -63.  */, 0x5948 /* 169.  */,
++			0xC400 /* -4.  */, 0x54D0 /* 77.  */ };
++
++#define TEST_MSG "VCVTH_F16_S64"
++#define INSN_NAME vcvth_f16_s64
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE int64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t input[] = { 123, 567, 0, 1024, 63, 169, 4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0x606E /* 567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.0.  */,
++			0x53E0 /* 63.0.  */, 0x5948 /* 169.0.  */,
++			0x4400 /* 4.0.  */, 0x54D0 /* 77.0.  */ };
++
++#define TEST_MSG "VCVTH_F16_U16"
++#define INSN_NAME vcvth_f16_u16
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE uint16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
+@@ -0,0 +1,52 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++int32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x57b0 /* 123.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x6400 /* 1024.000000 */,
++  0x7c00 /* inf */,
++  0x5948 /* 169.000000 */,
++  0x7c00 /* inf */,
++  0x54d0 /* 77.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VCVTH_F16_U32"
++#define INSN_NAME vcvth_f16_u32
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE int32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint64_t input[] = { 123, 567, 0, 1024, 63, 169, 4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0x606E /* 567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.0.  */,
++			0x53E0 /* 63.0.  */, 0x5948 /* 169.0.  */,
++			0x4400 /* 4.0.  */, 0x54D0 /* 77.0.  */ };
++
++#define TEST_MSG "VCVTH_F16_U64"
++#define INSN_NAME vcvth_f16_u64
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE uint64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++int16_t input[] = { 1, 10, 48, 100, -1, -10, 7, -7 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0xB800 /* -0.5.  */,
++			  0xC500 /* -5.  */,
++			  0x4300 /* 3.5.  */,
++			  0xC300 /* -3.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0xB400 /* -0.25.  */,
++			  0xC100 /* -2.5.  */,
++			  0x3F00 /* 1.75.  */,
++			  0xBF00 /* -1.75.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_S16"
++#define INSN_NAME vcvth_n_f16_s16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE int16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
+@@ -0,0 +1,99 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x53b0 /* 61.500000 */,
++  0xdc6e /* -283.500000 */,
++  0xcc40 /* -17.000000 */,
++  0x6000 /* 512.000000 */,
++  0xcfe0 /* -31.500000 */,
++  0x5548 /* 84.500000 */,
++  0xc000 /* -2.000000 */,
++  0x50d0 /* 38.500000 */,
++  0xd480 /* -72.000000 */,
++  0xcf00 /* -28.000000 */,
++  0xc800 /* -8.000000 */,
++  0xc780 /* -7.500000 */,
++  0xc700 /* -7.000000 */,
++  0xc680 /* -6.500000 */
++};
++
++uint16_t expected_2[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x4fb0 /* 30.750000 */,
++  0xd86e /* -141.750000 */,
++  0xc840 /* -8.500000 */,
++  0x5c00 /* 256.000000 */,
++  0xcbe0 /* -15.750000 */,
++  0x5148 /* 42.250000 */,
++  0xbc00 /* -1.000000 */,
++  0x4cd0 /* 19.250000 */,
++  0xd080 /* -36.000000 */,
++  0xcb00 /* -14.000000 */,
++  0xc400 /* -4.000000 */,
++  0xc380 /* -3.750000 */,
++  0xc300 /* -3.500000 */,
++  0xc280 /* -3.250000 */
++};
++
++uint16_t expected_3[] =
++{
++ 0x0000 /* 0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x8002 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x0004 /* 0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x0001 /* 0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x8001 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */
++};
++
++#define TEST_MSG "VCVTH_N_F16_S32"
++#define INSN_NAME vcvth_n_f16_s32
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE int32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++int64_t input[] = { 1, 10, 48, 100, -1, -10, 7, -7 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0xB800 /* -0.5.  */,
++			  0xC500 /* -5.  */,
++			  0x4300 /* 3.5.  */,
++			  0xC300 /* -3.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0xB400 /* -0.25.  */,
++			  0xC100 /* -2.5.  */,
++			  0x3F00 /* 1.75.  */,
++			  0xBF00 /* -1.75.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_S64"
++#define INSN_NAME vcvth_n_f16_s64
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE int64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint16_t input[] = { 1, 10, 48, 100, 1000, 0, 500, 9 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0x5FD0 /* 500.  */,
++			  0x0000 /* 0.0.  */,
++			  0x5BD0 /* 250.  */,
++			  0x4480 /* 4.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0x5BD0 /* 250.  */,
++			  0x0000 /* 0.0.  */,
++			  0x57D0 /* 125.  */,
++			  0x4080 /* 2.25.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_U16"
++#define INSN_NAME vcvth_n_f16_u16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE uint16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
+@@ -0,0 +1,99 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x53b0 /* 61.500000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x6000 /* 512.000000 */,
++  0x7c00 /* inf */,
++  0x5548 /* 84.500000 */,
++  0x7c00 /* inf */,
++  0x50d0 /* 38.500000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++uint16_t expected_2[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x4fb0 /* 30.750000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x5c00 /* 256.000000 */,
++  0x7c00 /* inf */,
++  0x5148 /* 42.250000 */,
++  0x7c00 /* inf */,
++  0x4cd0 /* 19.250000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++uint16_t expected_3[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x0004 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x0001 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */
++};
++
++#define TEST_MSG "VCVTH_N_F16_U32"
++#define INSN_NAME vcvth_n_f16_u32
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE uint32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint64_t input[] = { 1, 10, 48, 100, 1000, 0, 500, 9 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0x5FD0 /* 500.  */,
++			  0x0000 /* 0.0.  */,
++			  0x5BD0 /* 250.  */,
++			  0x4480 /* 4.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0x5BD0 /* 250.  */,
++			  0x0000 /* 0.0.  */,
++			  0x57D0 /* 125.  */,
++			  0x4080 /* 2.25.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_U64"
++#define INSN_NAME vcvth_n_f16_u64
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE uint64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, -9.9, -5.0, 9.1, -4.8, 77 };
++int16_t expected_1[] = { 5, 200, 14, -19, -10, 18, -9, 154 };
++int16_t expected_2[] = { 10, 400, 28, -39, -20, 36, -19, 308 };
++
++#define TEST_MSG "VCVTH_N_S16_F16"
++#define INSN_NAME vcvth_n_s16_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
+@@ -0,0 +1,100 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected_1[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000000f6,
++  0xfffffb90,
++  0xffffffbb,
++  0x00000800,
++  0x0000052e,
++  0x00000152,
++  0xfffffff7,
++  0x0000009a,
++  0xfffffedf,
++  0xffffff8f,
++  0xffffffe0,
++  0xffffffe2,
++  0xffffffe4,
++  0xffffffe6,
++};
++
++uint32_t expected_2[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000001ed,
++  0xfffff720,
++  0xffffff75,
++  0x00001000,
++  0x00000a5c,
++  0x000002a4,
++  0xffffffed,
++  0x00000134,
++  0xfffffdbe,
++  0xffffff1d,
++  0xffffffc0,
++  0xffffffc4,
++  0xffffffc8,
++  0xffffffcc,
++};
++
++uint32_t expected_3[] =
++{
++  0x00000000,
++  0x00000000,
++  0x7fffffff,
++  0x80000000,
++  0x80000000,
++  0x7fffffff,
++  0x7fffffff,
++  0x7fffffff,
++  0x80000000,
++  0x7fffffff,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++};
++
++#define TEST_MSG "VCVTH_N_S32_F16"
++#define INSN_NAME vcvth_n_s32_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, -9.9, -5.0, 9.1, -4.8, 77 };
++int64_t expected_1[] = { 5, 200, 14, -19, -10, 18, -9, 154 };
++int64_t expected_2[] = { 10, 400, 28, -39, -20, 36, -19, 308 };
++
++#define TEST_MSG "VCVTH_N_S64_F16"
++#define INSN_NAME vcvth_n_s64_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, 9.9, 5.0, 9.1, 4.8, 77 };
++uint16_t expected_1[] = {5, 200, 14, 19, 10, 18, 9, 154};
++uint16_t expected_2[] = {10, 400, 28, 39, 20, 36, 19, 308};
++
++#define TEST_MSG "VCVTH_N_U16_F16"
++#define INSN_NAME vcvth_n_u16_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
+@@ -0,0 +1,100 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected_1[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000000f6,
++  0x00000000,
++  0x00000000,
++  0x00000800,
++  0x0000052e,
++  0x00000152,
++  0x00000000,
++  0x0000009a,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++uint32_t expected_2[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000001ed,
++  0x00000000,
++  0x00000000,
++  0x00001000,
++  0x00000a5c,
++  0x000002a4,
++  0x00000000,
++  0x00000134,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++uint32_t expected_3[] =
++{
++  0x00000000,
++  0x00000000,
++  0xffffffff,
++  0x00000000,
++  0x00000000,
++  0xffffffff,
++  0xffffffff,
++  0xffffffff,
++  0x00000000,
++  0xffffffff,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTH_N_U32_F16"
++#define INSN_NAME vcvth_n_u32_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, 9.9, 5.0, 9.1, 4.8, 77 };
++uint64_t expected_1[] = { 5, 200, 14, 19, 10, 18, 9, 154 };
++uint64_t expected_2[] = { 10, 400, 28, 39, 20, 36, 19, 308 };
++
++#define TEST_MSG "VCVTH_N_U64_F16"
++#define INSN_NAME vcvth_n_u64_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 123, -56, 0, 24, -63, 169, -4, 77 };
++
++#define TEST_MSG "VCVTH_S16_F16"
++#define INSN_NAME vcvth_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffde,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffc,
++  0x0000004d,
++  0xffffff70,
++  0xffffffc8,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3,
++};
++
++#define TEST_MSG "VCVTH_S32_F16"
++#define INSN_NAME vcvth_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 123, -56, 0, 24, -63, 169, -4, 77 };
++
++#define TEST_MSG "VCVTH_S64_F16"
++#define INSN_NAME vcvth_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTH_u16_F16"
++#define INSN_NAME vcvth_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTH_U32_F16"
++#define INSN_NAME vcvth_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTH_u64_F16"
++#define INSN_NAME vcvth_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c
+@@ -0,0 +1,33 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff0, 0x5, 0xfff0, 0x5 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff0, 0x0,
++					   0x0, 0xf, 0xfff0 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0,
++					    0x0, 0x0, 0xf, 0x0 };
++#endif
++
++/* Expected results with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						    0x7d, 0x7d, 0x7d, 0x7d };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						     0x7d, 0x7d, 0x7d, 0x7d };
++#endif
++
++#define TEST_MSG "VCVTM/VCVTMQ"
++#define INSN_NAME vcvtm
++
++#include "vcvtX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 123, -57, 0, 24, -64, 169, -5, 77 };
++
++#define TEST_MSG "VCVTMH_S16_F16"
++#define INSN_NAME vcvtmh_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffdd,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffb,
++  0x0000004d,
++  0xffffff6f,
++  0xffffffc7,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTMH_S32_F16"
++#define INSN_NAME vcvtmh_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 123, -57, 0, 24, -64, 169, -5, 77 };
++
++#define TEST_MSG "VCVTMH_S64_F16"
++#define INSN_NAME vcvtmh_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTMH_u16_F16"
++#define INSN_NAME vcvtmh_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTMH_U32_F16"
++#define INSN_NAME vcvtmh_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTMH_u64_F16"
++#define INSN_NAME vcvtmh_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTNH_S16_F16"
++#define INSN_NAME vcvtnh_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffdd,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffb,
++  0x0000004d,
++  0xffffff70,
++  0xffffffc7,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTNH_S32_F16"
++#define INSN_NAME vcvtnh_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTNH_S64_F16"
++#define INSN_NAME vcvtnh_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTNH_u16_F16"
++#define INSN_NAME vcvtnh_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTNH_U32_F16"
++#define INSN_NAME vcvtnh_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTNH_u64_F16"
++#define INSN_NAME vcvtnh_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c
+@@ -0,0 +1,33 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x6, 0xfff1, 0x6 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x6, 0x0, 0x6 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0x10, 0xfff1,
++					   0x0, 0x0, 0x10, 0xfff1 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0x10, 0x0,
++					    0x0, 0x0, 0x10, 0x0 };
++#endif
++
++/* Expected results with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xb, 0xb, 0xb, 0xb };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xb, 0xb, 0xb, 0xb };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						    0x7e, 0x7e, 0x7e, 0x7e };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						     0x7e, 0x7e, 0x7e, 0x7e };
++#endif
++
++#define TEST_MSG "VCVTP/VCVTPQ"
++#define INSN_NAME vcvtp
++
++#include "vcvtX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 124, -56, 1, 25, -63, 170, -4, 77 };
++
++#define TEST_MSG "VCVTPH_S16_F16"
++#define INSN_NAME vcvtph_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007c,
++  0xfffffdc8,
++  0xffffffde,
++  0x00000400,
++  0x00000297,
++  0x000000aa,
++  0xfffffffc,
++  0x0000004d,
++  0xffffff70,
++  0xffffffc8,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTPH_S32_F16"
++#define INSN_NAME vcvtph_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 124, -56, 1, 25, -63, 170, -4, 77 };
++
++#define TEST_MSG "VCVTPH_S64_F16"
++#define INSN_NAME vcvtph_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 124, 57, 1, 25, 64, 170, 5, 77 };
++
++#define TEST_MSG "VCVTPH_u16_F16"
++#define INSN_NAME vcvtph_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007c,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000aa,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTPH_U32_F16"
++#define INSN_NAME vcvtph_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 124, 57, 1, 25, 64, 170, 5, 77 };
++
++#define TEST_MSG "VCVTPH_u64_F16"
++#define INSN_NAME vcvtph_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c
+@@ -0,0 +1,86 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (-56.8)
++#define C FP16_C (-34.8)
++#define D FP16_C (12)
++#define E FP16_C (63.1)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (77)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++/* Expected results for vdiv.  */
++VECT_VAR_DECL (expected_div_static, hfloat, 16, 4) []
++  = { 0x32CC /* A / E.  */, 0xC1F3 /* B / F.  */,
++      0x4740 /* C / G.  */, 0x30FD /* D / H.  */ };
++
++VECT_VAR_DECL (expected_div_static, hfloat, 16, 8) []
++  = { 0x32CC /* A / E.  */, 0xC1F3 /* B / F.  */,
++      0x4740 /* C / G.  */, 0x30FD /* D / H.  */,
++      0x201D /* I / M.  */, 0x48E0 /* J / N.  */,
++      0xC91B /* K / O.  */, 0xC90D /* L / P.  */ };
++
++void exec_vdiv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VDIV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vdiv_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_div_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VDIVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vdivq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		 VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_div_static, "");
++}
++
++int
++main (void)
++{
++  exec_vdiv_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0xb765 /* -0.462158 */,
++  0x27ef /* 0.030991 */,
++  0x3955 /* 0.666504 */,
++  0xccff /* -19.984375 */,
++  0xc49a /* -4.601562 */,
++  0xb1e3 /* -0.183960 */,
++  0x3cd3 /* 1.206055 */,
++  0x23f0 /* 0.015503 */,
++  0xa9ef /* -0.046356 */,
++  0x32f4 /* 0.217285 */,
++  0xb036 /* -0.131592 */,
++  0x4126 /* 2.574219 */,
++  0xcd15 /* -20.328125 */,
++  0x537f /* 59.968750 */,
++  0x7e00 /* nan */,
++  0x7e00 /* nan */
++};
++
++#define TEST_MSG "VDIVH_F16"
++#define INSN_NAME vdivh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c
+@@ -19,6 +19,10 @@ VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 };
+ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 					 0xf0, 0xf0, 0xf0, 0xf0 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcc00,
++						0xcc00, 0xcc00 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 					 0xf0, 0xf0, 0xf0, 0xf0,
+@@ -46,6 +50,12 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 					  0xf0, 0xf0, 0xf0, 0xf0 };
+ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+ 					  0xfff0, 0xfff0, 0xfff0, 0xfff0 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xcc00,
++						0xcc00, 0xcc00,
++						0xcc00, 0xcc00,
++						0xcc00, 0xcc00 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1800000,
+ 					    0xc1800000, 0xc1800000 };
+ 
+@@ -63,6 +73,10 @@ VECT_VAR_DECL(expected1,uint,64,1) [] = { 0xfffffffffffffff1 };
+ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
+ 					 0xf1, 0xf1, 0xf1, 0xf1 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0xcb80, 0xcb80,
++						0xcb80, 0xcb80 };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
+ 					 0xf1, 0xf1, 0xf1, 0xf1,
+@@ -90,6 +104,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
+ 					  0xf1, 0xf1, 0xf1, 0xf1 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ 					  0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0xcb80, 0xcb80,
++						0xcb80, 0xcb80,
++						0xcb80, 0xcb80,
++						0xcb80, 0xcb80 };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
+ 					    0xc1700000, 0xc1700000 };
+ 
+@@ -107,6 +127,10 @@ VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff2 };
+ VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					 0xf2, 0xf2, 0xf2, 0xf2 };
+ VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0xcb00,
++						0xcb00, 0xcb00 };
++#endif
+ VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1600000, 0xc1600000 };
+ VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					 0xf2, 0xf2, 0xf2, 0xf2,
+@@ -134,6 +158,12 @@ VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					  0xf2, 0xf2, 0xf2, 0xf2 };
+ VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2,
+ 					  0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb00, 0xcb00,
++						0xcb00, 0xcb00,
++						0xcb00, 0xcb00,
++						0xcb00, 0xcb00 };
++#endif
+ VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1600000, 0xc1600000,
+ 					    0xc1600000, 0xc1600000 };
+ 
+@@ -171,6 +201,9 @@ void exec_vdup_vmov (void)
+     TEST_VDUP(, uint, u, 64, 1);
+     TEST_VDUP(, poly, p, 8, 8);
+     TEST_VDUP(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++    TEST_VDUP(, float, f, 16, 4);
++#endif
+     TEST_VDUP(, float, f, 32, 2);
+ 
+     TEST_VDUP(q, int, s, 8, 16);
+@@ -183,8 +216,26 @@ void exec_vdup_vmov (void)
+     TEST_VDUP(q, uint, u, 64, 2);
+     TEST_VDUP(q, poly, p, 8, 16);
+     TEST_VDUP(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++    TEST_VDUP(q, float, f, 16, 8);
++#endif
+     TEST_VDUP(q, float, f, 32, 4);
+ 
++#if defined (FP16_SUPPORTED)
++    switch (i) {
++    case 0:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected0, "");
++      break;
++    case 1:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected1, "");
++      break;
++    case 2:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++      break;
++    default:
++      abort();
++    }
++#else
+     switch (i) {
+     case 0:
+       CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, "");
+@@ -198,6 +249,7 @@ void exec_vdup_vmov (void)
+     default:
+       abort();
+     }
++#endif
+   }
+ 
+   /* Do the same tests with vmov. Use the same expected results.  */
+@@ -216,6 +268,9 @@ void exec_vdup_vmov (void)
+     TEST_VMOV(, uint, u, 64, 1);
+     TEST_VMOV(, poly, p, 8, 8);
+     TEST_VMOV(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++    TEST_VMOV(, float, f, 16, 4);
++#endif
+     TEST_VMOV(, float, f, 32, 2);
+ 
+     TEST_VMOV(q, int, s, 8, 16);
+@@ -228,8 +283,26 @@ void exec_vdup_vmov (void)
+     TEST_VMOV(q, uint, u, 64, 2);
+     TEST_VMOV(q, poly, p, 8, 16);
+     TEST_VMOV(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++    TEST_VMOV(q, float, f, 16, 8);
++#endif
+     TEST_VMOV(q, float, f, 32, 4);
+ 
++#if defined (FP16_SUPPORTED)
++    switch (i) {
++    case 0:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected0, "");
++      break;
++    case 1:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected1, "");
++      break;
++    case 2:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++      break;
++    default:
++      abort();
++    }
++#else
+     switch (i) {
+     case 0:
+       CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, "");
+@@ -243,6 +316,8 @@ void exec_vdup_vmov (void)
+     default:
+       abort();
+     }
++#endif
++
+   }
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c
+@@ -17,6 +17,10 @@ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
+ 					0xf7, 0xf7, 0xf7, 0xf7 };
+ VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xca80, 0xca80,
++					       0xca80, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					0xf2, 0xf2, 0xf2, 0xf2,
+ 					0xf2, 0xf2, 0xf2, 0xf2,
+@@ -43,10 +47,16 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
+ 					 0xf5, 0xf5, 0xf5, 0xf5 };
+ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ 					 0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xca80, 0xca80,
++					       0xca80, 0xca80,
++					       0xca80, 0xca80,
++					       0xca80, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
+ 					   0xc1700000, 0xc1700000 };
+ 
+-#define TEST_MSG "VDUP_LANE/VDUP_LANEQ"
++#define TEST_MSG "VDUP_LANE/VDUPQ_LANE"
+ void exec_vdup_lane (void)
+ {
+   /* Basic test: vec1=vdup_lane(vec2, lane), then store the result.  */
+@@ -63,6 +73,9 @@ void exec_vdup_lane (void)
+   clean_results ();
+ 
+   TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+ 
+   /* Choose lane arbitrarily.  */
+@@ -76,6 +89,9 @@ void exec_vdup_lane (void)
+   TEST_VDUP_LANE(, uint, u, 64, 1, 1, 0);
+   TEST_VDUP_LANE(, poly, p, 8, 8, 8, 7);
+   TEST_VDUP_LANE(, poly, p, 16, 4, 4, 3);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANE(, float, f, 16, 4, 4, 3);
++#endif
+   TEST_VDUP_LANE(, float, f, 32, 2, 2, 1);
+ 
+   TEST_VDUP_LANE(q, int, s, 8, 16, 8, 2);
+@@ -88,9 +104,133 @@ void exec_vdup_lane (void)
+   TEST_VDUP_LANE(q, uint, u, 64, 2, 1, 0);
+   TEST_VDUP_LANE(q, poly, p, 8, 16, 8, 5);
+   TEST_VDUP_LANE(q, poly, p, 16, 8, 4, 1);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANE(q, float, f, 16, 8, 4, 3);
++#endif
+   TEST_VDUP_LANE(q, float, f, 32, 4, 2, 1);
+ 
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
+   CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#if defined (__aarch64__)
++
++#undef TEST_MSG
++#define TEST_MSG "VDUP_LANEQ/VDUPQ_LANEQ"
++
++  /* Expected results for vdup*_laneq tests.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd,
++					0xfd, 0xfd, 0xfd, 0xfd };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
++					 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
++					 0xf7, 0xf7, 0xf7, 0xf7 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80,
++						0xca80, 0xca80 };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb,
++					 0xfb, 0xfb, 0xfb, 0xfb,
++					 0xfb, 0xfb, 0xfb, 0xfb,
++					 0xfb, 0xfb, 0xfb, 0xfb };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff7, 0xfff7, 0xfff7, 0xfff7,
++					 0xfff7, 0xfff7, 0xfff7, 0xfff7 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
++					 0xfffffff1, 0xfffffff1 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0,
++					 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
++					  0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff0, 0xfffffff0,
++					  0xfffffff0, 0xfffffff0 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0,
++					  0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
++					  0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xc880, 0xc880,
++						0xc880, 0xc880,
++						0xc880, 0xc880,
++						0xc880, 0xc880 };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
++					    0xc1700000, 0xc1700000 };
++
++  /* Clean all results for vdup*_laneq tests.  */
++  clean_results ();
++  /* Basic test: vec1=vdup_lane(vec2, lane), then store the result.  */
++#define TEST_VDUP_LANEQ(Q, T1, T2, W, N, N2, L)				\
++  VECT_VAR(vector_res, T1, W, N) =					\
++    vdup##Q##_laneq_##T2##W(VECT_VAR(vector, T1, W, N2), L);		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_128BITS_VARIANTS(vector);
++
++  clean_results ();
++
++  TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++
++  /* Choose lane arbitrarily.  */
++  TEST_VDUP_LANEQ(, int, s, 8, 8, 16, 13);
++  TEST_VDUP_LANEQ(, int, s, 16, 4, 8, 2);
++  TEST_VDUP_LANEQ(, int, s, 32, 2, 4, 1);
++  TEST_VDUP_LANEQ(, int, s, 64, 1, 2, 0);
++  TEST_VDUP_LANEQ(, uint, u, 8, 8, 16, 15);
++  TEST_VDUP_LANEQ(, uint, u, 16, 4, 8, 3);
++  TEST_VDUP_LANEQ(, uint, u, 32, 2, 4, 1);
++  TEST_VDUP_LANEQ(, uint, u, 64, 1, 2, 0);
++  TEST_VDUP_LANEQ(, poly, p, 8, 8, 16, 7);
++  TEST_VDUP_LANEQ(, poly, p, 16, 4, 8, 3);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANEQ(, float, f, 16, 4, 8, 3);
++#endif
++  TEST_VDUP_LANEQ(, float, f, 32, 2, 4, 1);
++
++  TEST_VDUP_LANEQ(q, int, s, 8, 16, 16, 11);
++  TEST_VDUP_LANEQ(q, int, s, 16, 8, 8, 7);
++  TEST_VDUP_LANEQ(q, int, s, 32, 4, 4, 1);
++  TEST_VDUP_LANEQ(q, int, s, 64, 2, 2, 0);
++  TEST_VDUP_LANEQ(q, uint, u, 8, 16, 16, 5);
++  TEST_VDUP_LANEQ(q, uint, u, 16, 8, 8, 1);
++  TEST_VDUP_LANEQ(q, uint, u, 32, 4, 4, 0);
++  TEST_VDUP_LANEQ(q, uint, u, 64, 2, 2, 0);
++  TEST_VDUP_LANEQ(q, poly, p, 8, 16, 16, 5);
++  TEST_VDUP_LANEQ(q, poly, p, 16, 8, 8, 1);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANEQ(q, float, f, 16, 8, 8, 7);
++#endif
++  TEST_VDUP_LANEQ(q, float, f, 32, 4, 4, 1);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++
++#endif /* __aarch64__.  */
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c
+@@ -0,0 +1,137 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define A -16
++#define B -15
++#define C -14
++#define D -13
++#define E -12
++#define F -11
++#define G -10
++#define H -9
++
++#define F16_C(a) ((__fp16) a)
++#define AF F16_C (A)
++#define BF F16_C (B)
++#define CF F16_C (C)
++#define DF F16_C (D)
++#define EF F16_C (E)
++#define FF F16_C (F)
++#define GF F16_C (G)
++#define HF F16_C (H)
++
++#define S16_C(a) ((int16_t) a)
++#define AS S16_C (A)
++#define BS S16_C (B)
++#define CS S16_C (C)
++#define DS S16_C (D)
++#define ES S16_C (E)
++#define FS S16_C (F)
++#define GS S16_C (G)
++#define HS S16_C (H)
++
++#define U16_C(a) ((int16_t) a)
++#define AU U16_C (A)
++#define BU U16_C (B)
++#define CU U16_C (C)
++#define DU U16_C (D)
++#define EU U16_C (E)
++#define FU U16_C (F)
++#define GU U16_C (G)
++#define HU U16_C (H)
++
++#define P16_C(a) ((poly16_t) a)
++#define AP P16_C (A)
++#define BP P16_C (B)
++#define CP P16_C (C)
++#define DP P16_C (D)
++#define EP P16_C (E)
++#define FP P16_C (F)
++#define GP P16_C (G)
++#define HP P16_C (H)
++
++/* Expected results for vduph_lane.  */
++float16_t expected_f16 = AF;
++int16_t expected_s16 = DS;
++uint16_t expected_u16 = BU;
++poly16_t expected_p16 = CP;
++
++/* Expected results for vduph_laneq.  */
++float16_t expected_q_f16 = EF;
++int16_t expected_q_s16 = BS;
++uint16_t expected_q_u16 = GU;
++poly16_t expected_q_p16 = FP;
++
++void exec_vduph_lane_f16 (void)
++{
++  /* vduph_lane.  */
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  DECL_VARIABLE(vsrc, int, 16, 4);
++  DECL_VARIABLE(vsrc, uint, 16, 4);
++  DECL_VARIABLE(vsrc, poly, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {AF, BF, CF, DF};
++  VECT_VAR_DECL (buf_src, int, 16, 4) [] = {AS, BS, CS, DS};
++  VECT_VAR_DECL (buf_src, uint, 16, 4) [] = {AU, BU, CU, DU};
++  VECT_VAR_DECL (buf_src, poly, 16, 4) [] = {AP, BP, CP, DP};
++  VLOAD (vsrc, buf_src, , int, s, 16, 4);
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  VLOAD (vsrc, buf_src, , uint, u, 16, 4);
++  VLOAD (vsrc, buf_src, , poly, p, 16, 4);
++
++  float16_t res_f = vduph_lane_f16 (VECT_VAR (vsrc, float, 16, 4), 0);
++  if (* (unsigned short *) &res_f != * (unsigned short *) &expected_f16)
++    abort ();
++
++  int16_t res_s = vduph_lane_s16 (VECT_VAR (vsrc, int, 16, 4), 3);
++  if (* (unsigned short *) &res_s != * (unsigned short *) &expected_s16)
++    abort ();
++
++  uint16_t res_u = vduph_lane_u16 (VECT_VAR (vsrc, uint, 16, 4), 1);
++  if (* (unsigned short *) &res_u != * (unsigned short *) &expected_u16)
++    abort ();
++
++  poly16_t res_p = vduph_lane_p16 (VECT_VAR (vsrc, poly, 16, 4), 2);
++  if (* (unsigned short *) &res_p != * (unsigned short *) &expected_p16)
++    abort ();
++
++  /* vduph_laneq.  */
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  DECL_VARIABLE(vsrc, int, 16, 8);
++  DECL_VARIABLE(vsrc, uint, 16, 8);
++  DECL_VARIABLE(vsrc, poly, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {AF, BF, CF, DF, EF, FF, GF, HF};
++  VECT_VAR_DECL (buf_src, int, 16, 8) [] = {AS, BS, CS, DS, ES, FS, GS, HS};
++  VECT_VAR_DECL (buf_src, uint, 16, 8) [] = {AU, BU, CU, DU, EU, FU, GU, HU};
++  VECT_VAR_DECL (buf_src, poly, 16, 8) [] = {AP, BP, CP, DP, EP, FP, GP, HP};
++  VLOAD (vsrc, buf_src, q, int, s, 16, 8);
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  VLOAD (vsrc, buf_src, q, uint, u, 16, 8);
++  VLOAD (vsrc, buf_src, q, poly, p, 16, 8);
++
++  res_f = vduph_laneq_f16 (VECT_VAR (vsrc, float, 16, 8), 4);
++  if (* (unsigned short *) &res_f != * (unsigned short *) &expected_q_f16)
++    abort ();
++
++  res_s = vduph_laneq_s16 (VECT_VAR (vsrc, int, 16, 8), 1);
++  if (* (unsigned short *) &res_s != * (unsigned short *) &expected_q_s16)
++    abort ();
++
++  res_u = vduph_laneq_u16 (VECT_VAR (vsrc, uint, 16, 8), 6);
++  if (* (unsigned short *) &res_u != * (unsigned short *) &expected_q_u16)
++    abort ();
++
++  res_p = vduph_laneq_p16 (VECT_VAR (vsrc, poly, 16, 8), 5);
++  if (* (unsigned short *) &res_p != * (unsigned short *) &expected_q_p16)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vduph_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c
+@@ -16,6 +16,10 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
+ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf6, 0xf7, 0x55, 0x55,
+ 					0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcb00, 0xca80,
++					       0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xfe, 0xff, 0x11, 0x11,
+ 					0x11, 0x11, 0x11, 0x11,
+@@ -39,6 +43,12 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xfc, 0xfd, 0xfe, 0xff,
+ 					 0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff6, 0xfff7, 0x66, 0x66,
+ 					 0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xc880, 0x4b4d,
++					       0x4b4d, 0x4b4d,
++					       0x4b4d, 0x4b4d,
++					       0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1500000, 0x4204cccd,
+ 					   0x4204cccd, 0x4204cccd };
+ 
+@@ -60,6 +70,10 @@ void exec_vext (void)
+   clean_results ();
+ 
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
++#ifdef FP16_SUPPORTED
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ 
+@@ -74,6 +88,9 @@ void exec_vext (void)
+   VDUP(vector2, , uint, u, 64, 1, 0x88);
+   VDUP(vector2, , poly, p, 8, 8, 0x55);
+   VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
+   VDUP(vector2, , float, f, 32, 2, 33.6f);
+ 
+   VDUP(vector2, q, int, s, 8, 16, 0x11);
+@@ -86,6 +103,9 @@ void exec_vext (void)
+   VDUP(vector2, q, uint, u, 64, 2, 0x88);
+   VDUP(vector2, q, poly, p, 8, 16, 0x55);
+   VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, 33.2f);
+ 
+   /* Choose arbitrary extract offsets.  */
+@@ -99,6 +119,9 @@ void exec_vext (void)
+   TEST_VEXT(, uint, u, 64, 1, 0);
+   TEST_VEXT(, poly, p, 8, 8, 6);
+   TEST_VEXT(, poly, p, 16, 4, 2);
++#if defined (FP16_SUPPORTED)
++  TEST_VEXT(, float, f, 16, 4, 2);
++#endif
+   TEST_VEXT(, float, f, 32, 2, 1);
+ 
+   TEST_VEXT(q, int, s, 8, 16, 14);
+@@ -111,9 +134,16 @@ void exec_vext (void)
+   TEST_VEXT(q, uint, u, 64, 2, 1);
+   TEST_VEXT(q, poly, p, 8, 16, 12);
+   TEST_VEXT(q, poly, p, 16, 8, 6);
++#if defined (FP16_SUPPORTED)
++  TEST_VEXT(q, float, f, 16, 8, 7);
++#endif
+   TEST_VEXT(q, float, f, 32, 4, 3);
+ 
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
+   CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c
+@@ -3,11 +3,19 @@
+ #include "compute-ref-data.h"
+ 
+ #ifdef __ARM_FEATURE_FMA
++
+ /* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x61c6, 0x61c8, 0x61ca, 0x61cc };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x6435, 0x6436, 0x6437, 0x6438,
++					      0x6439, 0x643a, 0x643b, 0x643c };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4438ca3d, 0x44390a3d };
+-VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x44869eb8, 0x4486beb8, 0x4486deb8, 0x4486feb8 };
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x44869eb8, 0x4486beb8,
++					   0x4486deb8, 0x4486feb8 };
+ #ifdef __aarch64__
+-VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0x408906e1532b8520, 0x40890ee1532b8520 };
++VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0x408906e1532b8520,
++					   0x40890ee1532b8520 };
+ #endif
+ 
+ #define TEST_MSG "VFMA/VFMAQ"
+@@ -44,6 +52,18 @@ void exec_vfma (void)
+   DECL_VARIABLE(VAR, float, 32, 4);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector3, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++
++  DECL_VARIABLE(vector1, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector3, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   DECL_VFMA_VAR(vector1);
+   DECL_VFMA_VAR(vector2);
+   DECL_VFMA_VAR(vector3);
+@@ -52,6 +72,10 @@ void exec_vfma (void)
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ #ifdef __aarch64__
+@@ -59,13 +83,21 @@ void exec_vfma (void)
+ #endif
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 9.3f);
++  VDUP(vector2, q, float, f, 16, 8, 29.7f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 9.3f);
+   VDUP(vector2, q, float, f, 32, 4, 29.7f);
+ #ifdef __aarch64__
+   VDUP(vector2, q, float, f, 64, 2, 15.8f);
+ #endif
+-  
++
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector3, , float, f, 16, 4, 81.2f);
++  VDUP(vector3, q, float, f, 16, 8, 36.8f);
++#endif
+   VDUP(vector3, , float, f, 32, 2, 81.2f);
+   VDUP(vector3, q, float, f, 32, 4, 36.8f);
+ #ifdef __aarch64__
+@@ -73,12 +105,20 @@ void exec_vfma (void)
+ #endif
+ 
+   /* Execute the tests.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VFMA(, float, f, 16, 4);
++  TEST_VFMA(q, float, f, 16, 8);
++#endif
+   TEST_VFMA(, float, f, 32, 2);
+   TEST_VFMA(q, float, f, 32, 4);
+ #ifdef __aarch64__
+   TEST_VFMA(q, float, f, 64, 2);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_VFMA_RESULTS (TEST_MSG, "");
+ }
+ #endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++ 0x0000 /* 0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x3944 /* 0.658203 */,
++ 0xcefa /* -27.906250 */,
++ 0x5369 /* 59.281250 */,
++ 0x35ba /* 0.357910 */,
++ 0xc574 /* -5.453125 */,
++ 0xc5e6 /* -5.898438 */,
++ 0x3f66 /* 1.849609 */,
++ 0x5665 /* 102.312500 */,
++ 0xc02d /* -2.087891 */,
++ 0x4d79 /* 21.890625 */,
++ 0x547b /* 71.687500 */,
++ 0xcdf0 /* -23.750000 */,
++ 0xc625 /* -6.144531 */,
++ 0x4cf9 /* 19.890625 */,
++ 0x7e00 /* nan */,
++ 0x7e00 /* nan */
++};
++
++#define TEST_MSG "VFMAH_F16"
++#define INSN_NAME vfmah_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "ternary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c
+@@ -0,0 +1,908 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define A1 FP16_C (-5.8)
++#define A2 FP16_C (-0.0)
++#define A3 FP16_C (10)
++#define A4 FP16_C (123412.43)
++#define A5 FP16_C (-5.8)
++#define A6 FP16_C (90.8)
++#define A7 FP16_C (24)
++
++#define B0 FP16_C (23.4)
++#define B1 FP16_C (-5.8)
++#define B2 FP16_C (8.9)
++#define B3 FP16_C (4.0)
++#define B4 FP16_C (3.4)
++#define B5 FP16_C (-550.8)
++#define B6 FP16_C (-31.8)
++#define B7 FP16_C (20000.0)
++
++/* Expected results for vfma_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */};
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */ };
++
++/* Expected results for vfmaq_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */,
++      0x7C00 /* A4 + B4 * B0.  */,
++      0xF24D /* A5 + B5 * B0.  */,
++      0xE11B /* A6 + B6 * B0.  */,
++      0x7C00 /* A7 + B7 * B0.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */,
++      0x7C00 /* A4 + B4 * B1.  */,
++      0x6A3B /* A5 + B5 * B1.  */,
++      0x5C4D /* A6 + B6 * B1.  */,
++      0xFC00 /* A7 + B7 * B1.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */,
++      0x7C00 /* A4 + B4 * B2.  */,
++      0xECCB /* A5 + B5 * B2.  */,
++      0xDA01 /* A6 + B6 * B2.  */,
++      0x7C00 /* A7 + B7 * B2.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */,
++      0x7C00 /* A4 + B4 * B3.  */,
++      0xE851 /* A5 + B5 * B3.  */,
++      0xD08C /* A6 + B6 * B3.  */,
++      0x7C00 /* A7 + B7 * B3.  */ };
++
++/* Expected results for vfma_laneq.  */
++VECT_VAR_DECL (expected0_laneq_static, hfloat, 16, 4) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */ };
++
++VECT_VAR_DECL (expected1_laneq_static, hfloat, 16, 4) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */ };
++
++VECT_VAR_DECL (expected2_laneq_static, hfloat, 16, 4) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */ };
++
++VECT_VAR_DECL (expected3_laneq_static, hfloat, 16, 4) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */ };
++
++VECT_VAR_DECL (expected4_laneq_static, hfloat, 16, 4) []
++  = { 0x5A58 /* A0 + B0 * B4.  */,
++      0xCE62 /* A1 + B1 * B4.  */,
++      0x4F91 /* A2 + B2 * B4.  */,
++      0x4DE6 /* A3 + B3 * B4.  */ };
++
++VECT_VAR_DECL (expected5_laneq_static, hfloat, 16, 4) []
++  = { 0xF23D /* A0 + B0 * B5.  */,
++      0x6A3B /* A1 + B1 * B5.  */,
++      0xECCA /* A2 + B2 * B5.  */,
++      0xE849 /* A3 + B3 * B5.  */ };
++
++VECT_VAR_DECL (expected6_laneq_static, hfloat, 16, 4) []
++  = { 0xE0DA /* A0 + B0 * B6.  */,
++      0x5995 /* A1 + B1 * B6.  */,
++      0xDC6C /* A2 + B2 * B6.  */,
++      0xD753 /* A3 + B3 * B6.  */ };
++
++VECT_VAR_DECL (expected7_laneq_static, hfloat, 16, 4) []
++  = { 0x7C00 /* A0 + B0 * B7.  */,
++      0xFC00 /* A1 + B1 * B7.  */,
++      0x7C00 /* A2 + B2 * B7.  */,
++      0x7C00 /* A3 + B3 * B7.  */ };
++
++/* Expected results for vfmaq_laneq.  */
++VECT_VAR_DECL (expected0_laneq_static, hfloat, 16, 8) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */,
++      0x7C00 /* A4 + B4 * B0.  */,
++      0xF24D /* A5 + B5 * B0.  */,
++      0xE11B /* A6 + B6 * B0.  */,
++      0x7C00 /* A7 + B7 * B0.  */ };
++
++VECT_VAR_DECL (expected1_laneq_static, hfloat, 16, 8) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */,
++      0x7C00 /* A4 + B4 * B1.  */,
++      0x6A3B /* A5 + B5 * B1.  */,
++      0x5C4D /* A6 + B6 * B1.  */,
++      0xFC00 /* A7 + B7 * B1.  */ };
++
++VECT_VAR_DECL (expected2_laneq_static, hfloat, 16, 8) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */,
++      0x7C00 /* A4 + B4 * B2.  */,
++      0xECCB /* A5 + B5 * B2.  */,
++      0xDA01 /* A6 + B6 * B2.  */,
++      0x7C00 /* A7 + B7 * B2.  */ };
++
++VECT_VAR_DECL (expected3_laneq_static, hfloat, 16, 8) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */,
++      0x7C00 /* A4 + B4 * B3.  */,
++      0xE851 /* A5 + B5 * B3.  */,
++      0xD08C /* A6 + B6 * B3.  */,
++      0x7C00 /* A7 + B7 * B3.  */ };
++
++VECT_VAR_DECL (expected4_laneq_static, hfloat, 16, 8) []
++  = { 0x5A58 /* A0 + B0 * B4.  */,
++      0xCE62 /* A1 + B1 * B4.  */,
++      0x4F91 /* A2 + B2 * B4.  */,
++      0x4DE6 /* A3 + B3 * B4.  */,
++      0x7C00 /* A4 + B4 * B4.  */,
++      0xE757 /* A5 + B5 * B4.  */,
++      0xCC54 /* A6 + B6 * B4.  */,
++      0x7C00 /* A7 + B7 * B4.  */ };
++
++VECT_VAR_DECL (expected5_laneq_static, hfloat, 16, 8) []
++  = { 0xF23D /* A0 + B0 * B5.  */,
++      0x6A3B /* A1 + B1 * B5.  */,
++      0xECCA /* A2 + B2 * B5.  */,
++      0xE849 /* A3 + B3 * B5.  */,
++      0x7C00 /* A4 + B4 * B5.  */,
++      0x7C00 /* A5 + B5 * B5.  */,
++      0x744D /* A6 + B6 * B5.  */,
++      0xFC00 /* A7 + B7 * B5.  */ };
++
++VECT_VAR_DECL (expected6_laneq_static, hfloat, 16, 8) []
++  = { 0xE0DA /* A0 + B0 * B6.  */,
++      0x5995 /* A1 + B1 * B6.  */,
++      0xDC6C /* A2 + B2 * B6.  */,
++      0xD753 /* A3 + B3 * B6.  */,
++      0x7C00 /* A4 + B4 * B6.  */,
++      0x7447 /* A5 + B5 * B6.  */,
++      0x644E /* A6 + B6 * B6.  */,
++      0xFC00 /* A7 + B7 * B6.  */ };
++
++VECT_VAR_DECL (expected7_laneq_static, hfloat, 16, 8) []
++  = { 0x7C00 /* A0 + B0 * B7.  */,
++      0xFC00 /* A1 + B1 * B7.  */,
++      0x7C00 /* A2 + B2 * B7.  */,
++      0x7C00 /* A3 + B3 * B7.  */,
++      0x7C00 /* A4 + B4 * B7.  */,
++      0xFC00 /* A5 + B5 * B7.  */,
++      0xFC00 /* A6 + B6 * B7.  */,
++      0x7C00 /* A7 + B7 * B7.  */ };
++
++/* Expected results for vfms_lane.  */
++VECT_VAR_DECL (expected0_fms_static, hfloat, 16, 4) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_static, hfloat, 16, 4) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_static, hfloat, 16, 4) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_static, hfloat, 16, 4) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */ };
++
++/* Expected results for vfmsq_lane.  */
++VECT_VAR_DECL (expected0_fms_static, hfloat, 16, 8) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */,
++      0x7C00 /* A4 + (-B4) * B0.  */,
++      0x724B /* A5 + (-B5) * B0.  */,
++      0x6286 /* A6 + (-B6) * B0.  */,
++      0xFC00 /* A7 + (-B7) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_static, hfloat, 16, 8) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */,
++      0x7C00 /* A4 + (-B4) * B1.  */,
++      0xEA41 /* A5 + (-B5) * B1.  */,
++      0xD5DA /* A6 + (-B6) * B1.  */,
++      0x7C00 /* A7 + (-B7) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_static, hfloat, 16, 8) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */,
++      0x7C00 /* A4 + (-B4) * B2.  */,
++      0x6CC8 /* A5 + (-B5) * B2.  */,
++      0x5DD7 /* A6 + (-B6) * B2.  */,
++      0xFC00 /* A7 + (-B7) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_static, hfloat, 16, 8) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */,
++      0x7C00 /* A4 + (-B4) * B3.  */,
++      0x684B /* A5 + (-B5) * B3.  */,
++      0x5AD0 /* A6 + (-B6) * B3.  */,
++      0xFC00 /* A7 + (-B7) * B3.  */ };
++
++/* Expected results for vfms_laneq.  */
++VECT_VAR_DECL (expected0_fms_laneq_static, hfloat, 16, 4) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_laneq_static, hfloat, 16, 4) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */ };
++
++VECT_VAR_DECL (expected4_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x5179 /* A0 + (-B0) * B4.  */,
++      0x4AF6 /* A1 + (-B1) * B4.  */,
++      0xCF91 /* A2 + (-B2) * B4.  */,
++      0xC334 /* A3 + (-B3) * B4.  */ };
++
++VECT_VAR_DECL (expected5_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x725C /* A0 + (-B0) * B5.  */,
++      0xEA41 /* A1 + (-B1) * B5.  */,
++      0x6CCA /* A2 + (-B2) * B5.  */,
++      0x6853 /* A3 + (-B3) * B5.  */ };
++
++VECT_VAR_DECL (expected6_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x62C7 /* A0 + (-B0) * B6.  */,
++      0xD9F2 /* A1 + (-B1) * B6.  */,
++      0x5C6C /* A2 + (-B2) * B6.  */,
++      0x584A /* A3 + (-B3) * B6.  */ };
++
++VECT_VAR_DECL (expected7_fms_laneq_static, hfloat, 16, 4) []
++  = { 0xFC00 /* A0 + (-B0) * B7.  */,
++      0x7C00 /* A1 + (-B1) * B7.  */,
++      0xFC00 /* A2 + (-B2) * B7.  */,
++      0xFC00 /* A3 + (-B3) * B7.  */ };
++
++/* Expected results for vfmsq_laneq.  */
++VECT_VAR_DECL (expected0_fms_laneq_static, hfloat, 16, 8) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */,
++      0x7C00 /* A4 + (-B4) * B0.  */,
++      0x724B /* A5 + (-B5) * B0.  */,
++      0x6286 /* A6 + (-B6) * B0.  */,
++      0xFC00 /* A7 + (-B7) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */,
++      0x7C00 /* A4 + (-B4) * B1.  */,
++      0xEA41 /* A5 + (-B5) * B1.  */,
++      0xD5DA /* A6 + (-B6) * B1.  */,
++      0x7C00 /* A7 + (-B7) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_laneq_static, hfloat, 16, 8) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */,
++      0x7C00 /* A4 + (-B4) * B2.  */,
++      0x6CC8 /* A5 + (-B5) * B2.  */,
++      0x5DD7 /* A6 + (-B6) * B2.  */,
++      0xFC00 /* A7 + (-B7) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */,
++      0x7C00 /* A4 + (-B4) * B3.  */,
++      0x684B /* A5 + (-B5) * B3.  */,
++      0x5AD0 /* A6 + (-B6) * B3.  */,
++      0xFC00 /* A7 + (-B7) * B3.  */ };
++
++VECT_VAR_DECL (expected4_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x5179 /* A0 + (-B0) * B4.  */,
++      0x4AF6 /* A1 + (-B1) * B4.  */,
++      0xCF91 /* A2 + (-B2) * B4.  */,
++      0xC334 /* A3 + (-B3) * B4.  */,
++      0x7C00 /* A4 + (-B4) * B4.  */,
++      0x674C /* A5 + (-B5) * B4.  */,
++      0x5A37 /* A6 + (-B6) * B4.  */,
++      0xFC00 /* A7 + (-B7) * B4.  */ };
++
++VECT_VAR_DECL (expected5_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x725C /* A0 + (-B0) * B5.  */,
++      0xEA41 /* A1 + (-B1) * B5.  */,
++      0x6CCA /* A2 + (-B2) * B5.  */,
++      0x6853 /* A3 + (-B3) * B5.  */,
++      0x7C00 /* A4 + (-B4) * B5.  */,
++      0xFC00 /* A5 + (-B5) * B5.  */,
++      0xF441 /* A6 + (-B6) * B5.  */,
++      0x7C00 /* A7 + (-B7) * B5.  */ };
++
++VECT_VAR_DECL (expected6_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x62C7 /* A0 + (-B0) * B6.  */,
++      0xD9F2 /* A1 + (-B1) * B6.  */,
++      0x5C6C /* A2 + (-B2) * B6.  */,
++      0x584A /* A3 + (-B3) * B6.  */,
++      0x7C00 /* A4 + (-B4) * B6.  */,
++      0xF447 /* A5 + (-B5) * B6.  */,
++      0xE330 /* A6 + (-B6) * B6.  */,
++      0x7C00 /* A7 + (-B7) * B6.  */ };
++
++VECT_VAR_DECL (expected7_fms_laneq_static, hfloat, 16, 8) []
++  = { 0xFC00 /* A0 + (-B0) * B7.  */,
++      0x7C00 /* A1 + (-B1) * B7.  */,
++      0xFC00 /* A2 + (-B2) * B7.  */,
++      0xFC00 /* A3 + (-B3) * B7.  */,
++      0x7C00 /* A4 + (-B4) * B7.  */,
++      0x7C00 /* A5 + (-B5) * B7.  */,
++      0x7C00 /* A6 + (-B6) * B7.  */,
++      0xFC00 /* A7 + (-B7) * B7.  */ };
++
++void exec_vfmas_lane_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VFMA_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A0, A1, A2, A3};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {B0, B1, B2, B3};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A0, A1, A2, A3, A4, A5, A6, A7};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {B0, B1, B2, B3, B4, B5, B6, B7};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMA_LANEQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_3, float, 16, 8);
++  VECT_VAR_DECL (buf_src_3, float, 16, 8) [] = {B0, B1, B2, B3, B4, B5, B6, B7};
++  VLOAD (vsrc_3, buf_src_3, q, float, f, 16, 8);
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected4_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected5_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected6_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected7_laneq_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected4_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected5_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected6_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected7_laneq_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMS_LANE (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_fms_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_LANE (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_fms_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMS_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected4_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected5_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected6_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected7_fms_laneq_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected4_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected5_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected6_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected7_fms_laneq_static, "");
++}
++
++int
++main (void)
++{
++  exec_vfmas_lane_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c
+@@ -0,0 +1,469 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define A1 FP16_C (-5.8)
++#define A2 FP16_C (-0.0)
++#define A3 FP16_C (10)
++#define A4 FP16_C (123412.43)
++#define A5 FP16_C (-5.8)
++#define A6 FP16_C (90.8)
++#define A7 FP16_C (24)
++
++#define B0 FP16_C (23.4)
++#define B1 FP16_C (-5.8)
++#define B2 FP16_C (8.9)
++#define B3 FP16_C (4.0)
++#define B4 FP16_C (3.4)
++#define B5 FP16_C (-550.8)
++#define B6 FP16_C (-31.8)
++#define B7 FP16_C (20000.0)
++
++/* Expected results for vfma_n.  */
++VECT_VAR_DECL (expected_fma0_static, hfloat, 16, 4) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */ };
++
++VECT_VAR_DECL (expected_fma1_static, hfloat, 16, 4) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */ };
++
++VECT_VAR_DECL (expected_fma2_static, hfloat, 16, 4) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */ };
++
++VECT_VAR_DECL (expected_fma3_static, hfloat, 16, 4) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */ };
++
++VECT_VAR_DECL (expected_fma0_static, hfloat, 16, 8) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */,
++      0x7C00 /* A4 + B4 * B0.  */,
++      0xF24D /* A5 + B5 * B0.  */,
++      0xE11B /* A6 + B6 * B0.  */,
++      0x7C00 /* A7 + B7 * B0.  */ };
++
++VECT_VAR_DECL (expected_fma1_static, hfloat, 16, 8) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */,
++      0x7C00 /* A4 + B4 * B1.  */,
++      0x6A3B /* A5 + B5 * B1.  */,
++      0x5C4D /* A6 + B6 * B1.  */,
++      0xFC00 /* A7 + B7 * B1.  */ };
++
++VECT_VAR_DECL (expected_fma2_static, hfloat, 16, 8) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */,
++      0x7C00 /* A4 + B4 * B2.  */,
++      0xECCB /* A5 + B5 * B2.  */,
++      0xDA01 /* A6 + B6 * B2.  */,
++      0x7C00 /* A7 + B7 * B2.  */ };
++
++VECT_VAR_DECL (expected_fma3_static, hfloat, 16, 8) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */,
++      0x7C00 /* A4 + B4 * B3.  */,
++      0xE851 /* A5 + B5 * B3.  */,
++      0xD08C /* A6 + B6 * B3.  */,
++      0x7C00 /* A7 + B7 * B3.  */ };
++
++VECT_VAR_DECL (expected_fma4_static, hfloat, 16, 8) []
++  = { 0x5A58 /* A0 + B0 * B4.  */,
++      0xCE62 /* A1 + B1 * B4.  */,
++      0x4F91 /* A2 + B2 * B4.  */,
++      0x4DE6 /* A3 + B3 * B4.  */,
++      0x7C00 /* A4 + B4 * B4.  */,
++      0xE757 /* A5 + B5 * B4.  */,
++      0xCC54 /* A6 + B6 * B4.  */,
++      0x7C00 /* A7 + B7 * B4.  */ };
++
++VECT_VAR_DECL (expected_fma5_static, hfloat, 16, 8) []
++  = { 0xF23D /* A0 + B0 * B5.  */,
++      0x6A3B /* A1 + B1 * B5.  */,
++      0xECCA /* A2 + B2 * B5.  */,
++      0xE849 /* A3 + B3 * B5.  */,
++      0x7C00 /* A4 + B4 * B5.  */,
++      0x7C00 /* A5 + B5 * B5.  */,
++      0x744D /* A6 + B6 * B5.  */,
++      0xFC00 /* A7 + B7 * B5.  */ };
++
++VECT_VAR_DECL (expected_fma6_static, hfloat, 16, 8) []
++  = { 0xE0DA /* A0 + B0 * B6.  */,
++      0x5995 /* A1 + B1 * B6.  */,
++      0xDC6C /* A2 + B2 * B6.  */,
++      0xD753 /* A3 + B3 * B6.  */,
++      0x7C00 /* A4 + B4 * B6.  */,
++      0x7447 /* A5 + B5 * B6.  */,
++      0x644E /* A6 + B6 * B6.  */,
++      0xFC00 /* A7 + B7 * B6.  */ };
++
++VECT_VAR_DECL (expected_fma7_static, hfloat, 16, 8) []
++  = { 0x7C00 /* A0 + B0 * B7.  */,
++      0xFC00 /* A1 + B1 * B7.  */,
++      0x7C00 /* A2 + B2 * B7.  */,
++      0x7C00 /* A3 + B3 * B7.  */,
++      0x7C00 /* A4 + B4 * B7.  */,
++      0xFC00 /* A5 + B5 * B7.  */,
++      0xFC00 /* A6 + B6 * B7.  */,
++      0x7C00 /* A7 + B7 * B7.  */ };
++
++/* Expected results for vfms_n.  */
++VECT_VAR_DECL (expected_fms0_static, hfloat, 16, 4) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */ };
++
++VECT_VAR_DECL (expected_fms1_static, hfloat, 16, 4) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */ };
++
++VECT_VAR_DECL (expected_fms2_static, hfloat, 16, 4) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */ };
++
++VECT_VAR_DECL (expected_fms3_static, hfloat, 16, 4) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */ };
++
++VECT_VAR_DECL (expected_fms0_static, hfloat, 16, 8) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */,
++      0x7C00 /* A4 + (-B4) * B0.  */,
++      0x724B /* A5 + (-B5) * B0.  */,
++      0x6286 /* A6 + (-B6) * B0.  */,
++      0xFC00 /* A7 + (-B7) * B0.  */ };
++
++VECT_VAR_DECL (expected_fms1_static, hfloat, 16, 8) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */,
++      0x7C00 /* A4 + (-B4) * B1.  */,
++      0xEA41 /* A5 + (-B5) * B1.  */,
++      0xD5DA /* A6 + (-B6) * B1.  */,
++      0x7C00 /* A7 + (-B7) * B1.  */ };
++
++VECT_VAR_DECL (expected_fms2_static, hfloat, 16, 8) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */,
++      0x7C00 /* A4 + (-B4) * B2.  */,
++      0x6CC8 /* A5 + (-B5) * B2.  */,
++      0x5DD7 /* A6 + (-B6) * B2.  */,
++      0xFC00 /* A7 + (-B7) * B2.  */ };
++
++VECT_VAR_DECL (expected_fms3_static, hfloat, 16, 8) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */,
++      0x7C00 /* A4 + (-B4) * B3.  */,
++      0x684B /* A5 + (-B5) * B3.  */,
++      0x5AD0 /* A6 + (-B6) * B3.  */,
++      0xFC00 /* A7 + (-B7) * B3.  */ };
++
++VECT_VAR_DECL (expected_fms4_static, hfloat, 16, 8) []
++  = { 0x5179 /* A0 + (-B0) * B4.  */,
++      0x4AF6 /* A1 + (-B1) * B4.  */,
++      0xCF91 /* A2 + (-B2) * B4.  */,
++      0xC334 /* A3 + (-B3) * B4.  */,
++      0x7C00 /* A4 + (-B4) * B4.  */,
++      0x674C /* A5 + (-B5) * B4.  */,
++      0x5A37 /* A6 + (-B6) * B4.  */,
++      0xFC00 /* A7 + (-B7) * B4.  */ };
++
++VECT_VAR_DECL (expected_fms5_static, hfloat, 16, 8) []
++  = { 0x725C /* A0 + (-B0) * B5.  */,
++      0xEA41 /* A1 + (-B1) * B5.  */,
++      0x6CCA /* A2 + (-B2) * B5.  */,
++      0x6853 /* A3 + (-B3) * B5.  */,
++      0x7C00 /* A4 + (-B4) * B5.  */,
++      0xFC00 /* A5 + (-B5) * B5.  */,
++      0xF441 /* A6 + (-B6) * B5.  */,
++      0x7C00 /* A7 + (-B7) * B5.  */ };
++
++VECT_VAR_DECL (expected_fms6_static, hfloat, 16, 8) []
++  = { 0x62C7 /* A0 + (-B0) * B6.  */,
++      0xD9F2 /* A1 + (-B1) * B6.  */,
++      0x5C6C /* A2 + (-B2) * B6.  */,
++      0x584A /* A3 + (-B3) * B6.  */,
++      0x7C00 /* A4 + (-B4) * B6.  */,
++      0xF447 /* A5 + (-B5) * B6.  */,
++      0xE330 /* A6 + (-B6) * B6.  */,
++      0x7C00 /* A7 + (-B7) * B6.  */ };
++
++VECT_VAR_DECL (expected_fms7_static, hfloat, 16, 8) []
++  = { 0xFC00 /* A0 + (-B0) * B7.  */,
++      0x7C00 /* A1 + (-B1) * B7.  */,
++      0xFC00 /* A2 + (-B2) * B7.  */,
++      0xFC00 /* A3 + (-B3) * B7.  */,
++      0x7C00 /* A4 + (-B4) * B7.  */,
++      0x7C00 /* A5 + (-B5) * B7.  */,
++      0x7C00 /* A6 + (-B6) * B7.  */,
++      0xFC00 /* A7 + (-B7) * B7.  */ };
++
++void exec_vfmas_n_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VFMA_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A0, A1, A2, A3};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {B0, B1, B2, B3};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B0);
++
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A0, A1, A2, A3, A4, A5, A6, A7};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {B0, B1, B2, B3, B4, B5, B6, B7};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma7_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMA_N (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B0);
++
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_N (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms7_static, "");
++}
++
++int
++main (void)
++{
++  exec_vfmas_n_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c
+@@ -0,0 +1,143 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define B0 FP16_C (-5.8)
++#define C0 FP16_C (-3.8)
++#define D0 FP16_C (10)
++
++#define A1 FP16_C (12.4)
++#define B1 FP16_C (-5.8)
++#define C1 FP16_C (90.8)
++#define D1 FP16_C (24)
++
++#define A2 FP16_C (23.4)
++#define B2 FP16_C (-5.8)
++#define C2 FP16_C (8.9)
++#define D2 FP16_C (4)
++
++#define E0 FP16_C (3.4)
++#define F0 FP16_C (-55.8)
++#define G0 FP16_C (-31.8)
++#define H0 FP16_C (2)
++
++#define E1 FP16_C (123.4)
++#define F1 FP16_C (-5.8)
++#define G1 FP16_C (-3.8)
++#define H1 FP16_C (102)
++
++#define E2 FP16_C (4.9)
++#define F2 FP16_C (-15.8)
++#define G2 FP16_C (39.8)
++#define H2 FP16_C (49)
++
++extern void abort ();
++
++float16_t src1[8] = { A0, B0, C0, D0, E0, F0, G0, H0 };
++float16_t src2[8] = { A1, B1, C1, D1, E1, F1, G1, H1 };
++VECT_VAR_DECL (src3, float, 16, 4) [] = { A2, B2, C2, D2 };
++VECT_VAR_DECL (src3, float, 16, 8) [] = { A2, B2, C2, D2, E2, F2, G2, H2 };
++
++/* Expected results for vfmah_lane_f16.  */
++uint16_t expected[4] = { 0x5E76 /* A0 + A1 * A2.  */,
++			 0x4EF6 /* B0 + B1 * B2.  */,
++			 0x6249 /* C0 + C1 * C2.  */,
++			 0x56A0 /* D0 + D1 * D2.  */ };
++
++/* Expected results for vfmah_laneq_f16.  */
++uint16_t expected_laneq[8] = { 0x5E76 /* A0 + A1 * A2.  */,
++			       0x4EF6 /* B0 + B1 * B2.  */,
++			       0x6249 /* C0 + C1 * C2.  */,
++			       0x56A0 /* D0 + D1 * D2.  */,
++			       0x60BF /* E0 + E1 * E2.  */,
++			       0x507A /* F0 + F1 * F2.  */,
++			       0xD9B9 /* G0 + G1 * G2.  */,
++			       0x6CE2 /* H0 + H1 * H2.  */ };
++
++/* Expected results for vfmsh_lane_f16.  */
++uint16_t expected_fms[4] = { 0xD937 /* A0 + -A1 * A2.  */,
++			     0xD0EE /* B0 + -B1 * B2.  */,
++			     0xE258 /* C0 + -C1 * C2.  */,
++			     0xD560 /* D0 + -D1 * D2.  */ };
++
++/* Expected results for vfmsh_laneq_f16.  */
++uint16_t expected_fms_laneq[8] = { 0xD937 /* A0 + -A1 * A2.  */,
++				   0xD0EE /* B0 + -B1 * B2.  */,
++				   0xE258 /* C0 + -C1 * C2.  */,
++				   0xD560 /* D0 + -D1 * D2.  */,
++				   0xE0B2 /* E0 + -E1 * E2.  */,
++				   0xD89C /* F0 + -F1 * F2.  */,
++				   0x5778 /* G0 + -G1 * G2.  */,
++				   0xECE1 /* H0 + -H1 * H2.  */ };
++
++void exec_vfmash_lane_f16 (void)
++{
++#define CHECK_LANE(N) \
++  ret = vfmah_lane_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc3, float, 16, 4);
++  VLOAD (vsrc3, src3, , float, f, 16, 4);
++  float16_t ret;
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N) \
++  ret = vfmah_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_laneq[N]) \
++	  abort ();
++
++  DECL_VARIABLE(vsrc3, float, 16, 8);
++  VLOAD (vsrc3, src3, q, float, f, 16, 8);
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N) \
++  ret = vfmsh_lane_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected_fms[N])\
++    abort ();
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N) \
++  ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_fms_laneq[N]) \
++	  abort ();
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++}
++
++int
++main (void)
++{
++  exec_vfmash_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c
+@@ -4,10 +4,17 @@
+ 
+ #ifdef __ARM_FEATURE_FMA
+ /* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xe206, 0xe204, 0xe202, 0xe200 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe455, 0xe454, 0xe453, 0xe452,
++					      0xe451, 0xe450, 0xe44f, 0xe44e };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc440ca3d, 0xc4408a3d };
+-VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc48a9eb8, 0xc48a7eb8, 0xc48a5eb8, 0xc48a3eb8 };
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc48a9eb8, 0xc48a7eb8,
++					   0xc48a5eb8, 0xc48a3eb8 };
+ #ifdef __aarch64__
+-VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0xc08a06e1532b8520, 0xc089fee1532b8520 };
++VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0xc08a06e1532b8520,
++					   0xc089fee1532b8520 };
+ #endif
+ 
+ #define TEST_MSG "VFMS/VFMSQ"
+@@ -44,6 +51,18 @@ void exec_vfms (void)
+   DECL_VARIABLE(VAR, float, 32, 4);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector3, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++
++  DECL_VARIABLE(vector1, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector3, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   DECL_VFMS_VAR(vector1);
+   DECL_VFMS_VAR(vector2);
+   DECL_VFMS_VAR(vector3);
+@@ -52,6 +71,10 @@ void exec_vfms (void)
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ #ifdef __aarch64__
+@@ -59,13 +82,21 @@ void exec_vfms (void)
+ #endif
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 9.3f);
++  VDUP(vector2, q, float, f, 16, 8, 29.7f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 9.3f);
+   VDUP(vector2, q, float, f, 32, 4, 29.7f);
+ #ifdef __aarch64__
+   VDUP(vector2, q, float, f, 64, 2, 15.8f);
+ #endif
+-  
++
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector3, , float, f, 16, 4, 81.2f);
++  VDUP(vector3, q, float, f, 16, 8, 36.8f);
++#endif
+   VDUP(vector3, , float, f, 32, 2, 81.2f);
+   VDUP(vector3, q, float, f, 32, 4, 36.8f);
+ #ifdef __aarch64__
+@@ -73,12 +104,20 @@ void exec_vfms (void)
+ #endif
+ 
+   /* Execute the tests.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VFMS(, float, f, 16, 4);
++  TEST_VFMS(q, float, f, 16, 8);
++#endif
+   TEST_VFMS(, float, f, 32, 2);
+   TEST_VFMS(q, float, f, 32, 4);
+ #ifdef __aarch64__
+   TEST_VFMS(q, float, f, 64, 2);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_VFMS_RESULTS (TEST_MSG, "");
+ }
+ #endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms_vfma_n.c
+@@ -0,0 +1,490 @@
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#if defined(__aarch64__) && defined(__ARM_FEATURE_FMA)
++
++#define A0 123.4f
++#define A1 -3.8f
++#define A2 -29.4f
++#define A3 (__builtin_inff ())
++#define A4 0.0f
++#define A5 24.0f
++#define A6 124.0f
++#define A7 1024.0f
++
++#define B0 -5.8f
++#define B1 -0.0f
++#define B2 -10.8f
++#define B3 10.0f
++#define B4 23.4f
++#define B5 -1234.8f
++#define B6 8.9f
++#define B7 4.0f
++
++#define E0 9.8f
++#define E1 -1024.0f
++#define E2 (-__builtin_inff ())
++#define E3 479.0f
++float32_t elem0 = E0;
++float32_t elem1 = E1;
++float32_t elem2 = E2;
++float32_t elem3 = E3;
++
++#define DA0 1231234.4
++#define DA1 -3.8
++#define DA2 -2980.4
++#define DA3 -5.8
++#define DA4 0.01123
++#define DA5 24.0
++#define DA6 124.12345
++#define DA7 1024.0
++
++#define DB0 -5.8
++#define DB1 (__builtin_inf ())
++#define DB2 -105.8
++#define DB3 10.0
++#define DB4 (-__builtin_inf ())
++#define DB5 -1234.8
++#define DB6 848.9
++#define DB7 44444.0
++
++#define DE0 9.8
++#define DE1 -1024.0
++#define DE2 105.8
++#define DE3 479.0
++float64_t delem0 = DE0;
++float64_t delem1 = DE1;
++float64_t delem2 = DE2;
++float64_t delem3 = DE3;
++
++/* Expected results for vfms_n.  */
++
++VECT_VAR_DECL(expectedfms0, float, 32, 2) [] = {A0 + -B0 * E0, A1 + -B1 * E0};
++VECT_VAR_DECL(expectedfms1, float, 32, 2) [] = {A2 + -B2 * E1, A3 + -B3 * E1};
++VECT_VAR_DECL(expectedfms2, float, 32, 2) [] = {A4 + -B4 * E2, A5 + -B5 * E2};
++VECT_VAR_DECL(expectedfms3, float, 32, 2) [] = {A6 + -B6 * E3, A7 + -B7 * E3};
++VECT_VAR_DECL(expectedfma0, float, 32, 2) [] = {A0 + B0 * E0, A1 + B1 * E0};
++VECT_VAR_DECL(expectedfma1, float, 32, 2) [] = {A2 + B2 * E1, A3 + B3 * E1};
++VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2};
++VECT_VAR_DECL(expectedfma3, float, 32, 2) [] = {A6 + B6 * E3, A7 + B7 * E3};
++
++hfloat32_t * VECT_VAR (expectedfms0_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms0, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfms1_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms1, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfms2_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms2, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfms3_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms3, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma0_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma0, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma1_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma1, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma2_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma3_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma3, float, 32, 2);
++
++
++VECT_VAR_DECL(expectedfms0, float, 32, 4) [] = {A0 + -B0 * E0, A1 + -B1 * E0,
++						A2 + -B2 * E0, A3 + -B3 * E0};
++VECT_VAR_DECL(expectedfms1, float, 32, 4) [] = {A4 + -B4 * E1, A5 + -B5 * E1,
++						A6 + -B6 * E1, A7 + -B7 * E1};
++VECT_VAR_DECL(expectedfms2, float, 32, 4) [] = {A0 + -B0 * E2, A2 + -B2 * E2,
++						A4 + -B4 * E2, A6 + -B6 * E2};
++VECT_VAR_DECL(expectedfms3, float, 32, 4) [] = {A1 + -B1 * E3, A3 + -B3 * E3,
++						A5 + -B5 * E3, A7 + -B7 * E3};
++VECT_VAR_DECL(expectedfma0, float, 32, 4) [] = {A0 + B0 * E0, A1 + B1 * E0,
++						A2 + B2 * E0, A3 + B3 * E0};
++VECT_VAR_DECL(expectedfma1, float, 32, 4) [] = {A4 + B4 * E1, A5 + B5 * E1,
++						A6 + B6 * E1, A7 + B7 * E1};
++VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2,
++						A4 + B4 * E2, A6 + B6 * E2};
++VECT_VAR_DECL(expectedfma3, float, 32, 4) [] = {A1 + B1 * E3, A3 + B3 * E3,
++						A5 + B5 * E3, A7 + B7 * E3};
++
++hfloat32_t * VECT_VAR (expectedfms0_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms0, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfms1_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms1, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfms2_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms2, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfms3_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms3, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma0_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma0, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma1_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma1, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma2_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma3_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma3, float, 32, 4);
++
++VECT_VAR_DECL(expectedfms0, float, 64, 2) [] = {DA0 + -DB0 * DE0,
++						DA1 + -DB1 * DE0};
++VECT_VAR_DECL(expectedfms1, float, 64, 2) [] = {DA2 + -DB2 * DE1,
++						DA3 + -DB3 * DE1};
++VECT_VAR_DECL(expectedfms2, float, 64, 2) [] = {DA4 + -DB4 * DE2,
++						DA5 + -DB5 * DE2};
++VECT_VAR_DECL(expectedfms3, float, 64, 2) [] = {DA6 + -DB6 * DE3,
++						DA7 + -DB7 * DE3};
++VECT_VAR_DECL(expectedfma0, float, 64, 2) [] = {DA0 + DB0 * DE0,
++						DA1 + DB1 * DE0};
++VECT_VAR_DECL(expectedfma1, float, 64, 2) [] = {DA2 + DB2 * DE1,
++						DA3 + DB3 * DE1};
++VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2,
++						DA5 + DB5 * DE2};
++VECT_VAR_DECL(expectedfma3, float, 64, 2) [] = {DA6 + DB6 * DE3,
++						DA7 + DB7 * DE3};
++hfloat64_t * VECT_VAR (expectedfms0_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms0, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfms1_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms1, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfms2_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms2, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfms3_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms3, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma0_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma0, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma1_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma1, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma2_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma3_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma3, float, 64, 2);
++
++VECT_VAR_DECL(expectedfms0, float, 64, 1) [] = {DA0 + -DB0 * DE0};
++VECT_VAR_DECL(expectedfms1, float, 64, 1) [] = {DA2 + -DB2 * DE1};
++VECT_VAR_DECL(expectedfms2, float, 64, 1) [] = {DA4 + -DB4 * DE2};
++VECT_VAR_DECL(expectedfms3, float, 64, 1) [] = {DA6 + -DB6 * DE3};
++VECT_VAR_DECL(expectedfma0, float, 64, 1) [] = {DA0 + DB0 * DE0};
++VECT_VAR_DECL(expectedfma1, float, 64, 1) [] = {DA2 + DB2 * DE1};
++VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2};
++VECT_VAR_DECL(expectedfma3, float, 64, 1) [] = {DA6 + DB6 * DE3};
++
++hfloat64_t * VECT_VAR (expectedfms0_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms0, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfms1_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms1, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfms2_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms2, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfms3_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms3, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma0_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma0, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma1_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma1, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma2_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma3_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma3, float, 64, 1);
++
++void exec_vfma_vfms_n (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VFMS_VFMA_N (FP32)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 32, 2);
++  DECL_VARIABLE(vsrc_2, float, 32, 2);
++  VECT_VAR_DECL (buf_src_1, float, 32, 2) [] = {A0, A1};
++  VECT_VAR_DECL (buf_src_2, float, 32, 2) [] = {B0, B1};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 32, 2);
++  DECL_VARIABLE (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem0);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem0);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 32, 2) [] = {A2, A3};
++  VECT_VAR_DECL (buf_src_4, float, 32, 2) [] = {B2, B3};
++  VLOAD (vsrc_1, buf_src_3, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_4, , float, f, 32, 2);
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem1);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem1);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 32, 2) [] = {A4, A5};
++  VECT_VAR_DECL (buf_src_6, float, 32, 2) [] = {B4, B5};
++  VLOAD (vsrc_1, buf_src_5, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_6, , float, f, 32, 2);
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem2);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem2);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 32, 2) [] = {A6, A7};
++  VECT_VAR_DECL (buf_src_8, float, 32, 2) [] = {B6, B7};
++  VLOAD (vsrc_1, buf_src_7, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_8, , float, f, 32, 2);
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem3);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem3);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_VFMAQ_N (FP32)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 32, 4);
++  DECL_VARIABLE(vsrc_2, float, 32, 4);
++  VECT_VAR_DECL (buf_src_1, float, 32, 4) [] = {A0, A1, A2, A3};
++  VECT_VAR_DECL (buf_src_2, float, 32, 4) [] = {B0, B1, B2, B3};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 32, 4);
++  DECL_VARIABLE (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem0);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem0);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 32, 4) [] = {A4, A5, A6, A7};
++  VECT_VAR_DECL (buf_src_4, float, 32, 4) [] = {B4, B5, B6, B7};
++  VLOAD (vsrc_1, buf_src_3, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_4, q, float, f, 32, 4);
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem1);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem1);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 32, 4) [] = {A0, A2, A4, A6};
++  VECT_VAR_DECL (buf_src_6, float, 32, 4) [] = {B0, B2, B4, B6};
++  VLOAD (vsrc_1, buf_src_5, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_6, q, float, f, 32, 4);
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem2);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem2);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 32, 4) [] = {A1, A3, A5, A7};
++  VECT_VAR_DECL (buf_src_8, float, 32, 4) [] = {B1, B3, B5, B7};
++  VLOAD (vsrc_1, buf_src_7, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_8, q, float, f, 32, 4);
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem3);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem3);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_VFMAQ_N (FP64)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 64, 2);
++  DECL_VARIABLE(vsrc_2, float, 64, 2);
++  VECT_VAR_DECL (buf_src_1, float, 64, 2) [] = {DA0, DA1};
++  VECT_VAR_DECL (buf_src_2, float, 64, 2) [] = {DB0, DB1};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 64, 2);
++  DECL_VARIABLE (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem0);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem0);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 64, 2) [] = {DA2, DA3};
++  VECT_VAR_DECL (buf_src_4, float, 64, 2) [] = {DB2, DB3};
++  VLOAD (vsrc_1, buf_src_3, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_4, q, float, f, 64, 2);
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem1);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem1);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 64, 2) [] = {DA4, DA5};
++  VECT_VAR_DECL (buf_src_6, float, 64, 2) [] = {DB4, DB5};
++  VLOAD (vsrc_1, buf_src_5, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_6, q, float, f, 64, 2);
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem2);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem2);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 64, 2) [] = {DA6, DA7};
++  VECT_VAR_DECL (buf_src_8, float, 64, 2) [] = {DB6, DB7};
++  VLOAD (vsrc_1, buf_src_7, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_8, q, float, f, 64, 2);
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem3);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem3);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMS_VFMA_N (FP64)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 64, 1);
++  DECL_VARIABLE(vsrc_2, float, 64, 1);
++  VECT_VAR_DECL (buf_src_1, float, 64, 1) [] = {DA0};
++  VECT_VAR_DECL (buf_src_2, float, 64, 1) [] = {DB0};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 64, 1);
++  DECL_VARIABLE (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem0);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem0);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 64, 1) [] = {DA2};
++  VECT_VAR_DECL (buf_src_4, float, 64, 1) [] = {DB2};
++  VLOAD (vsrc_1, buf_src_3, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_4, , float, f, 64, 1);
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem1);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem1);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 64, 1) [] = {DA4};
++  VECT_VAR_DECL (buf_src_6, float, 64, 1) [] = {DB4};
++  VLOAD (vsrc_1, buf_src_5, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_6, , float, f, 64, 1);
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem2);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem2);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 64, 1) [] = {DA6};
++  VECT_VAR_DECL (buf_src_8, float, 64, 1) [] = {DB6};
++  VLOAD (vsrc_1, buf_src_7, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_8, , float, f, 64, 1);
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem3);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem3);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma3_static, "");
++}
++#endif
++
++int
++main (void)
++{
++#if defined(__aarch64__) && defined(__ARM_FEATURE_FMA)
++  exec_vfma_vfms_n ();
++#endif
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x42af /* 3.341797 */,
++  0x5043 /* 34.093750 */,
++  0xccd2 /* -19.281250 */,
++  0x3712 /* 0.441895 */,
++  0x3acc /* 0.849609 */,
++  0x4848 /* 8.562500 */,
++  0xcc43 /* -17.046875 */,
++  0xd65c /* -101.750000 */,
++  0x4185 /* 2.759766 */,
++  0xcd39 /* -20.890625 */,
++  0xd45b /* -69.687500 */,
++  0x5241 /* 50.031250 */,
++  0xc675 /* -6.457031 */,
++  0x4d07 /* 20.109375 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VFMSH_F16"
++#define INSN_NAME vfmsh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "ternary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c
+@@ -63,8 +63,8 @@ void exec_vget_high (void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
+@@ -13,6 +13,7 @@ uint32_t   expected_u32  = 0xfffffff1;
+ uint64_t   expected_u64  = 0xfffffffffffffff0;
+ poly8_t    expected_p8   = 0xf6;
+ poly16_t   expected_p16  = 0xfff2;
++hfloat16_t expected_f16  = 0xcb80;
+ hfloat32_t expected_f32  = 0xc1700000;
+ 
+ int8_t     expectedq_s8  = 0xff;
+@@ -25,6 +26,7 @@ uint32_t   expectedq_u32 = 0xfffffff2;
+ uint64_t   expectedq_u64 = 0xfffffffffffffff1;
+ poly8_t    expectedq_p8  = 0xfe;
+ poly16_t   expectedq_p16 = 0xfff6;
++hfloat16_t expectedq_f16 = 0xca80;
+ hfloat32_t expectedq_f32 = 0xc1500000;
+ 
+ int error_found = 0;
+@@ -52,6 +54,12 @@ void exec_vget_lane (void)
+     uint32_t var_int32;
+     float32_t var_float32;
+   } var_int32_float32;
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  union {
++    uint16_t var_int16;
++    float16_t var_float16;
++  } var_int16_float16;
++#endif
+ 
+ #define TEST_VGET_LANE_FP(Q, T1, T2, W, N, L)				   \
+   VAR(var, T1, W) = vget##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), L); \
+@@ -81,10 +89,17 @@ void exec_vget_lane (void)
+   VAR_DECL(var, uint, 64);
+   VAR_DECL(var, poly, 8);
+   VAR_DECL(var, poly, 16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VAR_DECL(var, float, 16);
++#endif
+   VAR_DECL(var, float, 32);
+ 
+   /* Initialize input values.  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -99,6 +114,9 @@ void exec_vget_lane (void)
+   TEST_VGET_LANE(, uint, u, 64, 1, 0);
+   TEST_VGET_LANE(, poly, p, 8, 8, 6);
+   TEST_VGET_LANE(, poly, p, 16, 4, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VGET_LANE_FP(, float, f, 16, 4, 1);
++#endif
+   TEST_VGET_LANE_FP(, float, f, 32, 2, 1);
+ 
+   TEST_VGET_LANE(q, int, s, 8, 16, 15);
+@@ -111,6 +129,9 @@ void exec_vget_lane (void)
+   TEST_VGET_LANE(q, uint, u, 64, 2, 1);
+   TEST_VGET_LANE(q, poly, p, 8, 16, 14);
+   TEST_VGET_LANE(q, poly, p, 16, 8, 6);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VGET_LANE_FP(q, float, f, 16, 8, 3);
++#endif
+   TEST_VGET_LANE_FP(q, float, f, 32, 4, 3);
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c
+@@ -63,8 +63,8 @@ void exec_vget_low (void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
+ #endif
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x4x2_t
+ f_vld2_lane_f16 (float16_t * p, float16x4x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x8x2_t
+ f_vld2q_lane_f16 (float16_t * p, float16x8x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x4x3_t
+ f_vld3_lane_f16 (float16_t * p, float16x4x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x8x3_t
+ f_vld3q_lane_f16 (float16_t * p, float16x8x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x4x4_t
+ f_vld4_lane_f16 (float16_t * p, float16x4x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x8x4_t
+ f_vld4q_lane_f16 (float16_t * p, float16x8x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c
+@@ -528,8 +528,8 @@ void exec_vldX (void)
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+ 									\
+     CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment);		\
+@@ -538,8 +538,8 @@ void exec_vldX (void)
+     CHECK(test_name, uint, 8, 16, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment)
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
+@@ -270,8 +270,8 @@ void exec_vldX_dup (void)
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment)
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c
+@@ -451,14 +451,14 @@ void exec_vldX_lane (void)
+     CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+     CHECK(test_name, int, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, int, 32, 4, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment)
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
+@@ -7,6 +7,10 @@
+ 
+ #define HAS_FLOAT_VARIANT
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
+ /* Expected results.  */
+ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 				       0xf4, 0xf5, 0xf6, 0xf7 };
+@@ -16,6 +20,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 					0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcbc0, 0xcb80, 0xcb00, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4,
+ 					0xf4, 0xf5, 0xf6, 0xf7,
+@@ -33,10 +40,36 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3,
+ 					 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 					 0xfffffff2, 0xfffffff3 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcb40, 0xcb40, 0xcb00, 0xca80,
++					      0xca00, 0xc980, 0xc900, 0xc880 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000,
+ 					   0xc1600000, 0xc1500000 };
+ 
+ /* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c
+@@ -0,0 +1,34 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 123.4
++#define B -567.8
++#define C -34.8
++#define D 1024
++#define E 663.1
++#define F 169.1
++#define G -4.8
++#define H 77
++
++float16_t input_1[] = { A, B, C, D };
++float16_t input_2[] = { E, F, G, H };
++float16_t expected[] = { E, F, G, D };
++
++#define TEST_MSG "VMAXH_F16"
++#define INSN_NAME vmaxh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c
+@@ -0,0 +1,47 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define INSN_NAME vmaxnm
++#define TEST_MSG "VMAXNM/VMAXNMQ"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcbc0, 0xcb80, 0xcb00, 0xca80 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcb40, 0xcb40, 0xcb00, 0xca80,
++					      0xca00, 0xc980, 0xc900, 0xc880 };
++#endif
++
++/* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++#endif
++
++#include "binary_op_float.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4000 /* 2.000000 */,
++  0x5640 /* 100.000000 */,
++  0x4f80 /* 30.000000 */,
++  0x3666 /* 0.399902 */,
++  0x3800 /* 0.500000 */,
++  0x3d52 /* 1.330078 */,
++  0xc64d /* -6.300781 */,
++  0x4d00 /* 20.000000 */,
++  0x355d /* 0.335205 */,
++  0x409a /* 2.300781 */,
++  0x3c00 /* 1.000000 */,
++  0x4a91 /* 13.132812 */,
++  0x34f6 /* 0.310059 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VMAXNMH_F16"
++#define INSN_NAME vmaxnmh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (34.8)
++#define B0 FP16_C (__builtin_nanf (""))
++#define C0 FP16_C (-__builtin_nanf (""))
++#define D0 FP16_C (0.0)
++
++#define A1 FP16_C (1025.8)
++#define B1 FP16_C (13.4)
++#define C1 FP16_C (__builtin_nanf (""))
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (-__builtin_nanf (""))
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vmaxnmv.  */
++uint16_t expect = 0x505A /* A0.  */;
++uint16_t expect_alt = 0x6402 /* A1.  */;
++
++void exec_vmaxnmv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMAXNMV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMAXNMVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vmaxnmv_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define B0 FP16_C (-567.8)
++#define C0 FP16_C (34.8)
++#define D0 FP16_C (0.0)
++
++#define A1 FP16_C (1025.8)
++#define B1 FP16_C (13.4)
++#define C1 FP16_C (-567.8)
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (567.8)
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vmaxv.  */
++uint16_t expect = 0x57B6 /* A0.  */;
++uint16_t expect_alt = 0x6402 /* A1.  */;
++
++void exec_vmaxv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMAXV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMAXVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vmaxv_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
+@@ -7,6 +7,10 @@
+ 
+ #define HAS_FLOAT_VARIANT
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
+ /* Expected results.  */
+ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 				       0xf3, 0xf3, 0xf3, 0xf3 };
+@@ -16,6 +20,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					0xf3, 0xf3, 0xf3, 0xf3 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcbc0, 0xcbc0, 0xcbc0 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					0xf4, 0xf4, 0xf4, 0xf4,
+@@ -31,11 +38,41 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					 0xf9, 0xf9, 0xf9, 0xf9 };
+ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2,
+ 					 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, 0xcb40, 0xcb40,
++					      0xcb40, 0xcb40, 0xcb40, 0xcb40 };
++#endif
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					 0xfffffff1, 0xfffffff1 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 					   0xc1680000, 0xc1680000 };
+ /* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++#endif
+ VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c
+@@ -0,0 +1,34 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 123.4
++#define B -567.8
++#define C -34.8
++#define D 1024
++#define E 663.1
++#define F 169.1
++#define G -4.8
++#define H 77
++
++float16_t input_1[] = { A, B, C, D };
++float16_t input_2[] = { E, F, G, H };
++float16_t expected[] = { A, B, C, H };
++
++#define TEST_MSG "VMINH_F16"
++#define INSN_NAME vminh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c
+@@ -0,0 +1,51 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define INSN_NAME vminnm
++#define TEST_MSG "VMINNM/VMINMQ"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcbc0, 0xcbc0, 0xcbc0 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, 0xcb40, 0xcb40,
++					      0xcb40, 0xcb40, 0xcb40, 0xcb40 };
++#endif
++
++/* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++#endif
++
++#include "binary_op_float.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0xc454 /* -4.328125 */,
++  0x4233 /* 3.099609 */,
++  0x4d00 /* 20.000000 */,
++  0xa51f /* -0.020004 */,
++  0xc09a /* -2.300781 */,
++  0xc73b /* -7.230469 */,
++  0xc79a /* -7.601562 */,
++  0x34f6 /* 0.310059 */,
++  0xc73b /* -7.230469 */,
++  0x3800 /* 0.500000 */,
++  0xc79a /* -7.601562 */,
++  0x451a /* 5.101562 */,
++  0xc64d /* -6.300781 */,
++  0x3556 /* 0.333496 */,
++  0xfc00 /* -inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VMINNMH_F16"
++#define INSN_NAME vminnmh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (-567.8)
++#define B0 FP16_C (__builtin_nanf (""))
++#define C0 FP16_C (34.8)
++#define D0 FP16_C (-__builtin_nanf (""))
++
++#define A1 FP16_C (-567.8)
++#define B1 FP16_C (1025.8)
++#define C1 FP16_C (-__builtin_nanf (""))
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (__builtin_nanf (""))
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vminnmv.  */
++uint16_t expect = 0xE070 /* A0.  */;
++uint16_t expect_alt = 0xE070 /* A1.  */;
++
++void exec_vminnmv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMINNMV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMINNMVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vminnmv_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (-567.8)
++#define B0 FP16_C (123.4)
++#define C0 FP16_C (34.8)
++#define D0 FP16_C (0.0)
++
++#define A1 FP16_C (-567.8)
++#define B1 FP16_C (1025.8)
++#define C1 FP16_C (13.4)
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (567.8)
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vminv.  */
++uint16_t expect = 0xE070 /* A0.  */;
++uint16_t expect_alt = 0xE070 /* A1.  */;
++
++void exec_vminv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMINV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMINVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vminv_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
+@@ -35,11 +35,11 @@ void exec_vmovn (void)
+   TEST_VMOVN(uint, u, 32, 16, 4);
+   TEST_VMOVN(uint, u, 64, 32, 2);
+ 
+-  CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
+@@ -13,6 +13,10 @@ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffff9a0, 0xfffffa06 };
+ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc0, 0x84, 0x48, 0xc,
+ 					0xd0, 0x94, 0x58, 0x1c };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xe02a, 0xdfcf,
++					      0xdf4a, 0xdec4 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc4053333, 0xc3f9c000 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0x90, 0x7, 0x7e, 0xf5,
+ 					0x6c, 0xe3, 0x5a, 0xd1,
+@@ -34,13 +38,15 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0xca, 0x34, 0x9e,
+ 					 0xc8, 0x62, 0x9c, 0x36,
+ 					 0x30, 0x9a, 0x64, 0xce,
+ 					 0x98, 0x32, 0xcc, 0x66 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe63a, 0xe5d6, 0xe573, 0xe50f,
++					      0xe4ac, 0xe448, 0xe3c8, 0xe301 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4c73333, 0xc4bac000,
+ 					   0xc4ae4ccd, 0xc4a1d999 };
+ 
+-#ifndef INSN_NAME
+ #define INSN_NAME vmul
+ #define TEST_MSG "VMUL"
+-#endif
+ 
+ #define FNNAME1(NAME) exec_ ## NAME
+ #define FNNAME(NAME) FNNAME1(NAME)
+@@ -80,6 +86,17 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VMUL(poly, 8, 16);
+   DECL_VMUL(float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector1, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
+@@ -99,6 +116,10 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector1, buffer, q, uint, u, 32, 4);
+   VLOAD(vector1, buffer, q, poly, p, 8, 16);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+ 
+   /* Choose init value arbitrarily.  */
+   VDUP(vector2, , int, s, 8, 8, 0x11);
+@@ -117,6 +138,10 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 32, 4, 0xCC);
+   VDUP(vector2, q, poly, p, 8, 16, 0xAA);
+   VDUP(vector2, q, float, f, 32, 4, 99.6f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 33.3f);
++  VDUP(vector2, q, float, f, 16, 8, 99.6f);
++#endif
+ 
+   /* Execute the tests.  */
+   TEST_VMUL(INSN_NAME, , int, s, 8, 8);
+@@ -135,6 +160,10 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VMUL(INSN_NAME, q, uint, u, 32, 4);
+   TEST_VMUL(INSN_NAME, q, poly, p, 8, 16);
+   TEST_VMUL(INSN_NAME, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL(INSN_NAME, , float, f, 16, 4);
++  TEST_VMUL(INSN_NAME, q, float, f, 16, 8);
++#endif
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+@@ -142,7 +171,7 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+@@ -150,8 +179,12 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
+@@ -7,6 +7,9 @@ VECT_VAR_DECL(expected,int,16,4) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc };
+ VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffface0, 0xffffb212 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xddb3, 0xdd58, 0xdcfd, 0xdca1 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b66666, 0xc3ab0000 };
+ VECT_VAR_DECL(expected,int,16,8) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc,
+ 					0xffd0, 0xffd4, 0xffd8, 0xffdc };
+@@ -16,6 +19,10 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c,
+ 					 0xccd0, 0xd114, 0xd558, 0xd99c };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffface0, 0xffffb212,
+ 					 0xffffb744, 0xffffbc76 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xddb3, 0xdd58, 0xdcfd, 0xdca1,
++					      0xdc46, 0xdbd6, 0xdb20, 0xda69 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc3b66666, 0xc3ab0000,
+ 					   0xc39f9999, 0xc3943333 };
+ 
+@@ -45,11 +52,20 @@ void exec_vmul_lane (void)
+ 
+   DECL_VMUL(vector);
+   DECL_VMUL(vector_res);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+ 
+   DECL_VARIABLE(vector2, int, 16, 4);
+   DECL_VARIABLE(vector2, int, 32, 2);
+   DECL_VARIABLE(vector2, uint, 16, 4);
+   DECL_VARIABLE(vector2, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector2, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+ 
+   clean_results ();
+@@ -59,11 +75,17 @@ void exec_vmul_lane (void)
+   VLOAD(vector, buffer, , int, s, 32, 2);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, int, s, 16, 8);
+   VLOAD(vector, buffer, q, int, s, 32, 4);
+   VLOAD(vector, buffer, q, uint, u, 16, 8);
+   VLOAD(vector, buffer, q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Initialize vector2.  */
+@@ -71,6 +93,9 @@ void exec_vmul_lane (void)
+   VDUP(vector2, , int, s, 32, 2, 0x22);
+   VDUP(vector2, , uint, u, 16, 4, 0x444);
+   VDUP(vector2, , uint, u, 32, 2, 0x532);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 22.8f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 22.8f);
+ 
+   /* Choose lane arbitrarily.  */
+@@ -78,22 +103,34 @@ void exec_vmul_lane (void)
+   TEST_VMUL_LANE(, int, s, 32, 2, 2, 1);
+   TEST_VMUL_LANE(, uint, u, 16, 4, 4, 2);
+   TEST_VMUL_LANE(, uint, u, 32, 2, 2, 1);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_LANE(, float, f, 16, 4, 4, 1);
++#endif
+   TEST_VMUL_LANE(, float, f, 32, 2, 2, 1);
+   TEST_VMUL_LANE(q, int, s, 16, 8, 4, 2);
+   TEST_VMUL_LANE(q, int, s, 32, 4, 2, 0);
+   TEST_VMUL_LANE(q, uint, u, 16, 8, 4, 2);
+   TEST_VMUL_LANE(q, uint, u, 32, 4, 2, 1);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_LANE(q, float, f, 16, 8, 4, 0);
++#endif
+   TEST_VMUL_LANE(q, float, f, 32, 4, 2, 0);
+ 
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+ }
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c
+@@ -0,0 +1,454 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (-56.8)
++#define C FP16_C (-34.8)
++#define D FP16_C (12)
++#define E FP16_C (63.1)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (77)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++/* Expected results for vmul_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */ };
++
++/* Expected results for vmulq_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */,
++      0x5186 /* I * E.  */,
++      0xECCE /* J * E.  */,
++      0x6189 /* K * E.  */,
++      0x6E0A /* L * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0x5AB3 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0xD2BD /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */,
++      0x52BD /* I * H.  */,
++      0xEDDE /* J * H.  */,
++      0x62C1 /* K * H.  */,
++      0x6F5E /* L * H.  */ };
++
++/* Expected results for vmul_laneq.  */
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 4) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */ };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 4) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 4) []
++  = { 0x648F /* A * M.  */,
++      0xECD5 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0x6416 /* D * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 4) []
++  = { 0xD6B3 /* A * N.  */,
++      0x5F1A /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0xD600 /* D * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 4) []
++  = { 0xCB5E /* A * O.  */,
++      0x53CF /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0xCA99 /* D * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 4) []
++  = { 0xD810 /* A * P.  */,
++      0x604F /* B * P.  */,
++      0x5D47 /* C * P.  */,
++      0xD747 /* D * P.  */ };
++
++/* Expected results for vmulq_laneq.  */
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 8) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */,
++      0x5186 /* I * E.  */,
++      0xECCE /* J * E.  */,
++      0x6189 /* K * E.  */,
++      0x6E0A /* L * E.  */ };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0x5AB3 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0xD2BD /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 8) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */,
++      0x52BD /* I * H.  */,
++      0xEDDE /* J * H.  */,
++      0x62C1 /* K * H.  */,
++      0x6F5E /* L * H.  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 8) []
++  = { 0x648F /* A * M.  */,
++      0xECD5 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0x6416 /* D * M.  */,
++      0x53A0 /* I * M.  */,
++      0xEEA3 /* J * M.  */,
++      0x63A4 /* K * M.  */,
++      0x702B /* L * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 8) []
++  = { 0xD6B3 /* A * N.  */,
++      0x5F1A /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0xD600 /* D * N.  */,
++      0xC59A /* I * N.  */,
++      0x60E0 /* J * N.  */,
++      0xD59D /* K * N.  */,
++      0xE220 /* L * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 8) []
++  = { 0xCB5E /* A * O.  */,
++      0x53CF /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0xCA99 /* D * O.  */,
++      0xBA29 /* I * O.  */,
++      0x555C /* J * O.  */,
++      0xCA2C /* K * O.  */,
++      0xD6BC /* L * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 8) []
++  = { 0xD810 /* A * P.  */,
++      0x604F /* B * P.  */,
++      0x5D47 /* C * P.  */,
++      0xD747 /* D * P.  */,
++      0xC6CB /* I * P.  */,
++      0x61EA /* J * P.  */,
++      0xD6CF /* K * P.  */,
++      0xE36E /* L * P.  */ };
++
++void exec_vmul_lane_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMUL_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULQ_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMUL_LANEQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq7_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq7_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmul_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
+@@ -7,6 +7,9 @@ VECT_VAR_DECL(expected,int,16,4) [] = { 0xfef0, 0xff01, 0xff12, 0xff23 };
+ VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfcd0, 0xfd03, 0xfd36, 0xfd69 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffbc0, 0xfffffc04 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xdd93, 0xdd3a, 0xdce1, 0xdc87 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b26666, 0xc3a74000 };
+ VECT_VAR_DECL(expected,int,16,8) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf,
+ 					0xfc04, 0xfc59, 0xfcae, 0xfd03 };
+@@ -16,6 +19,10 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf890, 0xf907, 0xf97e, 0xf9f5,
+ 					 0xfa6c, 0xfae3, 0xfb5a, 0xfbd1 };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffff780, 0xfffff808,
+ 					 0xfffff890, 0xfffff918 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe58e, 0xe535, 0xe4dc, 0xe483,
++					      0xe42a, 0xe3a3, 0xe2f2, 0xe240 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4b1cccd, 0xc4a6b000,
+ 					   0xc49b9333, 0xc4907667 };
+ 
+@@ -50,6 +57,13 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VMUL(vector);
+   DECL_VMUL(vector_res);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   clean_results ();
+ 
+   /* Initialize vector from pre-initialized values.  */
+@@ -57,11 +71,17 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, , int, s, 32, 2);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, int, s, 16, 8);
+   VLOAD(vector, buffer, q, int, s, 32, 4);
+   VLOAD(vector, buffer, q, uint, u, 16, 8);
+   VLOAD(vector, buffer, q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Choose multiplier arbitrarily.  */
+@@ -69,22 +89,34 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VMUL_N(, int, s, 32, 2, 0x22);
+   TEST_VMUL_N(, uint, u, 16, 4, 0x33);
+   TEST_VMUL_N(, uint, u, 32, 2, 0x44);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_N(, float, f, 16, 4, 22.3f);
++#endif
+   TEST_VMUL_N(, float, f, 32, 2, 22.3f);
+   TEST_VMUL_N(q, int, s, 16, 8, 0x55);
+   TEST_VMUL_N(q, int, s, 32, 4, 0x66);
+   TEST_VMUL_N(q, uint, u, 16, 8, 0x77);
+   TEST_VMUL_N(q, uint, u, 32, 4, 0x88);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_N(q, float, f, 16, 8, 88.9f);
++#endif
+   TEST_VMUL_N(q, float, f, 32, 4, 88.9f);
+ 
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+ }
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0xc854 /* -8.656250 */,
++  0x5cd8 /* 310.000000 */,
++  0x60b0 /* 600.000000 */,
++  0xa019 /* -0.008003 */,
++  0xbc9a /* -1.150391 */,
++  0xc8cf /* -9.617188 */,
++  0x51fd /* 47.906250 */,
++  0x4634 /* 6.203125 */,
++  0xc0d9 /* -2.423828 */,
++  0x3c9a /* 1.150391 */,
++  0xc79a /* -7.601562 */,
++  0x5430 /* 67.000000 */,
++  0xbfd0 /* -1.953125 */,
++  0x46ac /* 6.671875 */,
++  0xfc00 /* -inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VMULH_F16"
++#define INSN_NAME vmulh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c
+@@ -0,0 +1,90 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (-56.8)
++#define C FP16_C (-34.8)
++#define D FP16_C (12)
++#define E FP16_C (63.1)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (77)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++extern void abort ();
++
++float16_t src1[8] = { A, B, C, D, I, J, K, L };
++VECT_VAR_DECL (src2, float, 16, 4) [] = { E, F, G, H };
++VECT_VAR_DECL (src2, float, 16, 8) [] = { E, F, G, H, M, N, O, P };
++
++/* Expected results for vmulh_lane.  */
++uint16_t expected[4] = { 0x629B /* A * E.  */, 0xE43D /* B * F.  */,
++			 0x5939 /* C * G.  */, 0x6338 /* D * H.  */ };
++
++
++/* Expected results for vmulh_lane.  */
++uint16_t expected_laneq[8] = { 0x629B /* A * E.  */,
++			       0xE43D /* B * F.  */,
++			       0x5939 /* C * G.  */,
++			       0x6338 /* D * H.  */,
++			       0x53A0 /* I * M.  */,
++			       0x60E0 /* J * N.  */,
++			       0xCA2C /* K * O.  */,
++			       0xE36E /* L * P.  */ };
++
++void exec_vmulh_lane_f16 (void)
++{
++#define CHECK_LANE(N)\
++  ret = vmulh_lane_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 4);
++  VLOAD (vsrc2, src2, , float, f, 16, 4);
++  float16_t ret;
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N)\
++  ret = vmulh_laneq_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_laneq[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 8);
++  VLOAD (vsrc2, src2, q, float, f, 16, 8);
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++}
++
++int
++main (void)
++{
++  exec_vmulh_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
+@@ -59,13 +59,13 @@ void exec_vmull (void)
+   TEST_VMULL(uint, u, 32, 64, 2);
+   TEST_VMULL(poly, p, 8, 16, 8);
+ 
+-  CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
++  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
+@@ -54,9 +54,9 @@ void exec_vmull_lane (void)
+   TEST_VMULL_LANE(uint, u, 32, 64, 2, 1);
+ 
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
++  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
++  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c
+@@ -0,0 +1,84 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (63.1)
++#define F FP16_C (0.0)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-__builtin_inff ())
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-0.0)
++#define O FP16_C (-1.1)
++#define P FP16_C (7)
++
++/* Expected results for vmulx.  */
++VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
++  = { 0x629B /* A * E.  */, 0x4000 /* FP16_C (2.0f).  */,
++      0x5939 /* C * G.  */, 0xC000 /* FP16_C (-2.0f).  */ };
++
++VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
++  = { 0x629B /* A * E.  */, 0x4000 /* FP16_C (2.0f).  */,
++      0x5939 /* C * G.  */, 0xC000 /* FP16_C (-2.0f).  */,
++      0x53A0 /* I * M.  */, 0x4000 /* FP16_C (2.0f).  */,
++      0xCA2C /* K * O.  */, 0x615C /* L * P.  */ };
++
++void exec_vmulx_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMULX (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmulx_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		 VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulxq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		  VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmulx_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c
+@@ -0,0 +1,452 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (-0.0)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (-__builtin_inff ())
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-0.0)
++
++/* Expected results for vmulx_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */ };
++
++/* Expected results for vmulxq_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * E.  */,
++      0x0000 /* J * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* L * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0xFC00 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0x7C00 /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* I * H.  */,
++      0x8000 /* J * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* L * H.  */};
++
++/* Expected results for vmulx_laneq.  */
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 4) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 4) []
++  = { 0x648F /* A * M.  */,
++      0x7C00 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0xFC00 /* D * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 4) []
++  = { 0xD6B3 /* A * N.  */,
++      0xFC00 /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0x7C00 /* D * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 4) []
++  = { 0xCB5E /* A * O.  */,
++      0xFC00 /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0x7C00 /* D * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * P.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * P.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * E.  */,
++      0x0000 /* J * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* L * E.  */  };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0xFC00 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0x7C00 /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 8) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* I * H.  */,
++      0x8000 /* J * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* L * H.  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 8) []
++  = { 0x648F /* A * M.  */,
++      0x7C00 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0xFC00 /* D * M.  */,
++      0x53A0 /* I * M.  */,
++      0xEEA3 /* J * M.  */,
++      0xFC00 /* K * M.  */,
++      0x702B /* L * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 8) []
++  = { 0xD6B3 /* A * N.  */,
++      0xFC00 /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0x7C00 /* D * N.  */,
++      0xC59A /* I * N.  */,
++      0x60E0 /* J * N.  */,
++      0x7C00 /* K * N.  */,
++      0xE220 /* L * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 8) []
++  = { 0xCB5E /* A * O.  */,
++      0xFC00 /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0x7C00 /* D * O.  */,
++      0xBA29 /* I * O.  */,
++      0x555C /* J * O.  */,
++      0x7C00 /* K * O.  */,
++      0xD6BC /* L * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * P.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * P.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * P.  */,
++      0x0000 /* J * P.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* L * P.  */ };
++
++void exec_vmulx_lane_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMULX_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULX_LANEQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq7_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq7_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmulx_lane_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c
+@@ -0,0 +1,177 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (-0.0)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++float16_t elemE = E;
++float16_t elemF = F;
++float16_t elemG = G;
++float16_t elemH = H;
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++/* Expected results for vmulx_n.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */ };
++
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * E.  */,
++      0x0000 /* J * E.  */,
++      0x8000 /* K * E.  */,
++      0x8000 /* L * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0x5AB3 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0xD2BD /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* I * H.  */,
++      0x8000 /* J * H.  */,
++      0x0000 /* K * H.  */,
++      0x0000 /* L * H.  */ };
++
++void exec_vmulx_n_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMULX_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE (vsrc_1, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemE);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemF);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemG);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemH);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE (vsrc_1, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemE);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemF);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemG);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemH);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmulx_n_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c
+@@ -0,0 +1,50 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 13.4
++#define B __builtin_inff ()
++#define C -34.8
++#define D -__builtin_inff ()
++#define E 63.1
++#define F 0.0
++#define G -4.8
++#define H 0.0
++
++#define I 0.7
++#define J -__builtin_inff ()
++#define K 11.23
++#define L 98
++#define M 87.1
++#define N -0.0
++#define O -1.1
++#define P 7
++
++float16_t input_1[] = { A, B, C, D, I, J, K, L };
++float16_t input_2[] = { E, F, G, H, M, N, O, P };
++uint16_t expected[] = { 0x629B /* A * E.  */,
++			0x4000 /* FP16_C (2.0f).  */,
++			0x5939 /* C * G.  */,
++			0xC000 /* FP16_C (-2.0f).  */,
++			0x53A0 /* I * M.  */,
++			0x4000 /* FP16_C (2.0f).  */,
++			0xCA2C /* K * O.  */,
++			0x615C /* L * P.  */ };
++
++#define TEST_MSG "VMULXH_F16"
++#define INSN_NAME vmulxh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c
+@@ -0,0 +1,91 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (63.1)
++#define F FP16_C (0.0)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-__builtin_inff ())
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-0.0)
++#define O FP16_C (-1.1)
++#define P FP16_C (7)
++
++extern void abort ();
++
++float16_t src1[8] = { A, B, C, D, I, J, K, L };
++VECT_VAR_DECL (src2, float, 16, 4) [] = { E, F, G, H };
++VECT_VAR_DECL (src2, float, 16, 8) [] = { E, F, G, H, M, N, O, P };
++
++/* Expected results for vmulxh_lane.  */
++uint16_t expected[4] = { 0x629B /* A * E.  */,
++			 0x4000 /* FP16_C (2.0f).  */,
++			 0x5939 /* C * G.  */,
++			 0xC000 /* FP16_C (-2.0f).  */ };
++
++/* Expected results for vmulxh_lane.  */
++uint16_t expected_laneq[8] = { 0x629B /* A * E.  */,
++			       0x4000 /* FP16_C (2.0f).  */,
++			       0x5939 /* C * G.  */,
++			       0xC000 /* FP16_C (-2.0f).  */,
++			       0x53A0 /* I * M.  */,
++			       0x4000 /* FP16_C (2.0f).  */,
++			       0xCA2C /* K * O.  */,
++			       0x615C /* L * P.  */ };
++
++void exec_vmulxh_lane_f16 (void)
++{
++#define CHECK_LANE(N)\
++  ret = vmulxh_lane_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 4);
++  VLOAD (vsrc2, src2, , float, f, 16, 4);
++  float16_t ret;
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N)\
++  ret = vmulxh_laneq_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_laneq[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 8);
++  VLOAD (vsrc2, src2, q, float, f, 16, 8);
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++}
++
++int
++main (void)
++{
++  exec_vmulxh_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
+@@ -120,14 +120,14 @@ FNNAME (INSN_NAME)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c
+@@ -21,24 +21,53 @@ VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd };
+ /* Expected results for float32 variants. Needs to be separated since
+    the generic test function does not test floating-point
+    versions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0xc09a, 0xc09a,
++						      0xc09a, 0xc09a };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0xc2cd, 0xc2cd,
++						      0xc2cd, 0xc2cd,
++						      0xc2cd, 0xc2cd,
++						      0xc2cd, 0xc2cd };
++#endif
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc0133333, 0xc0133333 };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc059999a, 0xc059999a,
+ 						   0xc059999a, 0xc059999a };
+ 
+ void exec_vneg_f32(void)
+ {
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 2.3f);
+   VDUP(vector, q, float, f, 32, 4, 3.4f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_UNARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_UNARY_OP(INSN_NAME, q, float, f, 16, 8);
++#endif
+   TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2);
+   TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
+@@ -0,0 +1,39 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] =
++{
++  0x8000 /* -0.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0xc233 /* -3.099609 */,
++  0xcd00 /* -20.000000 */,
++  0xb666 /* -0.399902 */,
++  0x409a /* 2.300781 */,
++  0xbd52 /* -1.330078 */,
++  0x479a /* 7.601562 */,
++  0xb4f6 /* -0.310059 */,
++  0xb55d /* -0.335205 */,
++  0xb800 /* -0.500000 */,
++  0xbc00 /* -1.000000 */,
++  0xca91 /* -13.132812 */,
++  0x464d /* 6.300781 */,
++  0xcd00 /* -20.000000 */,
++  0xfc00 /* -inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VNEGH_F16"
++#define INSN_NAME vnegh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
+@@ -21,6 +21,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector, uint, 8, 8);
+   DECL_VARIABLE(vector, uint, 16, 4);
+   DECL_VARIABLE(vector, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+ 
+   DECL_VARIABLE(vector_res, int, 8, 8);
+@@ -29,6 +32,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector_res, uint, 8, 8);
+   DECL_VARIABLE(vector_res, uint, 16, 4);
+   DECL_VARIABLE(vector_res, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+ 
+   clean_results ();
+@@ -40,6 +46,9 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, , uint, u, 8, 8);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+ 
+   /* Apply a binary operator named INSN_NAME.  */
+@@ -49,14 +58,20 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VPXXX(INSN_NAME, uint, u, 8, 8);
+   TEST_VPXXX(INSN_NAME, uint, u, 16, 4);
+   TEST_VPXXX(INSN_NAME, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VPXXX(INSN_NAME, float, f, 16, 4);
++#endif
+   TEST_VPXXX(INSN_NAME, float, f, 32, 2);
+ 
+-  CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
+@@ -14,6 +14,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 					0xe1, 0xe5, 0xe9, 0xed };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcfc0, 0xcec0, 0xcfc0, 0xcec0 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
+ 
+ #include "vpXXX.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
+@@ -15,6 +15,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 					0xf1, 0xf3, 0xf5, 0xf7 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcb80, 0xca80, 0xcb80, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+ 
+ #include "vpXXX.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
+@@ -15,6 +15,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 					0xf0, 0xf2, 0xf4, 0xf6 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, 0xcc00, 0xcb00 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+ 
+ #include "vpXXX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c
+@@ -0,0 +1,114 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (123.4)
++#define B FP16_C (__builtin_nanf ("")) /* NaN */
++#define C FP16_C (-34.8)
++#define D FP16_C (1024)
++#define E FP16_C (663.1)
++#define F FP16_C (169.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (-__builtin_nanf ("")) /* NaN */
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (101.23)
++#define L FP16_C (-1098)
++#define M FP16_C (870.1)
++#define N FP16_C (-8781)
++#define O FP16_C (__builtin_inff ()) /* +Inf */
++#define P FP16_C (-__builtin_inff ()) /* -Inf */
++
++
++/* Expected results for vpminnm.  */
++VECT_VAR_DECL (expected_min_static, hfloat, 16, 4) []
++  = { 0x57B6 /* A.  */, 0xD05A /* C.  */, 0x5949 /* F.  */, 0xC4CD /* G.  */ };
++
++VECT_VAR_DECL (expected_min_static, hfloat, 16, 8) []
++  = { 0x57B6 /* A.  */, 0xD05A /* C.  */, 0xD4E0 /* J.  */, 0xE44A /* L.  */,
++      0x5949 /* F.  */, 0xC4CD /* G.  */, 0xF04A /* N.  */, 0xFC00 /* P.  */ };
++
++/* expected_max results for vpmaxnm.  */
++VECT_VAR_DECL (expected_max_static, hfloat, 16, 4) []
++  = { 0x57B6 /* A.  */, 0x6400 /* D.  */, 0x612E /* E.  */, 0xC4CD /* G.  */ };
++
++VECT_VAR_DECL (expected_max_static, hfloat, 16, 8) []
++  = { 0x57B6 /* A.  */, 0x6400 /* D.  */, 0x399A /* I.  */, 0x5654 /* K.  */,
++      0x612E /* E.  */, 0xC4CD /* G.  */, 0x62CC /* M.  */, 0x7C00 /* O.  */ };
++
++void exec_vpminmaxnm_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VPMINNM (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vpminnm_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		   VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_min_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VPMINNMQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vpminnmq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		    VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_min_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VPMAXNM (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vpmaxnm_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		   VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_max_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VPMAXNMQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vpmaxnmq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		    VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_max_static, "");
++}
++
++int
++main (void)
++{
++  exec_vpminmaxnm_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c
+@@ -90,9 +90,9 @@ void vqabs_extra()
+   TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat_min_neg, MSG);
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 4, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 2, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_neg, MSG);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 4, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_neg, MSG);
+ }
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
+@@ -63,8 +63,8 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VQDMULL(int, s, 16, 32, 4, expected_cumulative_sat, "");
+   TEST_VQDMULL(int, s, 32, 64, 2, expected_cumulative_sat, "");
+ 
+-  CHECK (TEST_MSG, int, 32, 4, PRIx16, expected, "");
+-  CHECK (TEST_MSG, int, 64, 2, PRIx32, expected, "");
++  CHECK (TEST_MSG, int, 32, 4, PRIx32, expected, "");
++  CHECK (TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ 
+   VDUP(vector, , int, s, 16, 4, 0x8000);
+   VDUP(vector2, , int, s, 16, 4, 0x8000);
+@@ -75,8 +75,8 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VQDMULL(int, s, 16, 32, 4, expected_cumulative_sat2, TEST_MSG2);
+   TEST_VQDMULL(int, s, 32, 64, 2, expected_cumulative_sat2, TEST_MSG2);
+ 
+-  CHECK (TEST_MSG, int, 32, 4, PRIx16, expected2, TEST_MSG2);
+-  CHECK (TEST_MSG, int, 64, 2, PRIx32, expected2, TEST_MSG2);
++  CHECK (TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
++  CHECK (TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c
+@@ -90,9 +90,9 @@ void vqneg_extra()
+   TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat_min_neg, MSG);
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 4, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 2, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_neg, MSG);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 4, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_neg, MSG);
+ }
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqtbX.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqtbX.c
+@@ -318,13 +318,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl1, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL1Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl1q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl1q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl1q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl1q, "");
+ 
+   /* Check vqtbl2.  */
+   clean_results ();
+@@ -334,13 +334,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl2, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL2Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl2q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl2q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl2q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl2q, "");
+ 
+   /* Check vqtbl3.  */
+   clean_results ();
+@@ -350,13 +350,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl3, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL3Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl3q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl3q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl3q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl3q, "");
+ 
+   /* Check vqtbl4.  */
+   clean_results ();
+@@ -366,13 +366,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl4, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL4Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl4q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl4q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl4q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl4q, "");
+ 
+ 
+   /* Now test VQTBX.  */
+@@ -455,13 +455,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx1, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX1Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx1q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx1q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx1q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx1q, "");
+ 
+   /* Check vqtbx2.  */
+   clean_results ();
+@@ -471,13 +471,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx2, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX2Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx2q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx2q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx2q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx2q, "");
+ 
+   /* Check vqtbx3.  */
+   clean_results ();
+@@ -487,13 +487,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx3, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX3Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx3q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx3q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx3q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx3q, "");
+ 
+   /* Check vqtbx4.  */
+   clean_results ();
+@@ -503,13 +503,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx4, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX4Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx4q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx4q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx4q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx4q, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
+@@ -7,6 +7,14 @@
+ VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000,
+ 						  0xbf000000, 0xbf000000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834,
++						       0x3834, 0x3834 };
++VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018,
++						       0x2018, 0x2018,
++						       0x2018, 0x2018,
++						       0x2018, 0x2018 };
++#endif
+ VECT_VAR_DECL(expected_positive,hfloat,32,2) [] = { 0x3f068000, 0x3f068000 };
+ VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000,
+ 						    0x3c030000, 0x3c030000 };
+@@ -15,24 +23,56 @@ VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000,
+ VECT_VAR_DECL(expected_negative,uint,32,2) [] = { 0x80000000, 0x80000000 };
+ VECT_VAR_DECL(expected_negative,uint,32,4) [] = { 0xee800000, 0xee800000,
+ 						  0xee800000, 0xee800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_negative, hfloat, 16, 4) [] = { 0xae64, 0xae64,
++						       0xae64, 0xae64 };
++VECT_VAR_DECL(expected_negative, hfloat, 16, 8) [] = { 0xa018, 0xa018,
++						       0xa018, 0xa018,
++						       0xa018, 0xa018,
++						       0xa018, 0xa018 };
++#endif
+ VECT_VAR_DECL(expected_negative,hfloat,32,2) [] = { 0xbdcc8000, 0xbdcc8000 };
+ VECT_VAR_DECL(expected_negative,hfloat,32,4) [] = { 0xbc030000, 0xbc030000,
+ 						    0xbc030000, 0xbc030000 };
+ 
+ /* Expected results with FP special values (NaN, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						  0x0, 0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results with FP special values (zero, large value).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						  0x0, 0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7f800000, 0x7f800000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results with FP special values (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00};
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						  0x8000, 0x8000,
++						  0x8000, 0x8000,
++						  0x8000, 0x8000 };
++#endif
+ VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x80000000, 0x80000000,
+ 					       0x80000000, 0x80000000 };
+ 
+ /* Expected results with FP special large negative value.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp4, hfloat, 16, 4) [] = { 0x8000, 0x8000,
++						  0x8000, 0x8000 };
++#endif
+ VECT_VAR_DECL(expected_fp4,hfloat,32,2) [] = { 0x80000000, 0x80000000 };
+ 
+ #define TEST_MSG "VRECPE/VRECPEQ"
+@@ -50,11 +90,19 @@ void exec_vrecpe(void)
+   /* No need for 64 bits variants.  */
+   DECL_VARIABLE(vector, uint, 32, 2);
+   DECL_VARIABLE(vector, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
+   DECL_VARIABLE(vector_res, uint, 32, 2);
+   DECL_VARIABLE(vector_res, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+@@ -62,88 +110,165 @@ void exec_vrecpe(void)
+ 
+   /* Choose init value arbitrarily, positive.  */
+   VDUP(vector, , uint, u, 32, 2, 0x12345678);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 1.9f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 1.9f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, q, float, f, 16, 8, 125.0f);
++#endif
+   VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10);
+   VDUP(vector, q, float, f, 32, 4, 125.0f);
+ 
+   /* Apply the operator.  */
+   TEST_VRECPE(, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #define CMT " (positive input)"
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_positive, CMT);
+ 
+   /* Choose init value arbitrarily,negative.  */
+   VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -10.0f);
++#endif
+   VDUP(vector, , float, f, 32, 2, -10.0f);
+   VDUP(vector, q, uint, u, 32, 4, 0x89081234);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, q, float, f, 16, 8, -125.0f);
++#endif
+   VDUP(vector, q, float, f, 32, 4, -125.0f);
+ 
+   /* Apply the operator.  */
+   TEST_VRECPE(, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " (negative input)"
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_negative, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_negative, CMT);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_negative, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_negative, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_negative, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_negative, CMT);
+ 
+   /* Test FP variants with special input values (NaN, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector, q, float, f, 32, 4, HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NaN, infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+   /* Test FP variants with special input values (zero, large value).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 0.0f);
++  VDUP(vector, q, float, f, 16, 8, 8.97229e37f /*9.0e37f*/);
++#endif
+   VDUP(vector, , float, f, 32, 2, 0.0f);
+   VDUP(vector, q, float, f, 32, 4, 8.97229e37f /*9.0e37f*/);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (zero, large value)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ 
+   /* Test FP variants with special input values (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -0.0f);
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, -0.0f);
+   VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (-0, -infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+ 
+   /* Test FP variants with special input values (large negative value).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -9.0e37f);
++#endif
+   VDUP(vector, , float, f, 32, 2, -9.0e37f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+ 
+ #undef CMT
+ #define CMT " FP special (large negative value)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp4, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp4, CMT);
+ }
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 123.4
++#define B 567.8
++#define C 34.8
++#define D 1024
++#define E 663.1
++#define F 144.0
++#define G 4.8
++#define H 77
++
++#define RECP_A 0x2028 /* 1/A.  */
++#define RECP_B 0x1734 /* 1/B.  */
++#define RECP_C 0x275C /* 1/C.  */
++#define RECP_D 0x13FC /* 1/D.  */
++#define RECP_E 0x162C /* 1/E.  */
++#define RECP_F 0x1F18 /* 1/F.  */
++#define RECP_G 0x32A8 /* 1/G.  */
++#define RECP_H 0x22A4 /* 1/H.  */
++
++float16_t input[] = { A, B, C, D, E, F, G, H };
++uint16_t expected[] = { RECP_A, RECP_B, RECP_C, RECP_D,
++		        RECP_E, RECP_F, RECP_G, RECP_H };
++
++#define TEST_MSG "VRECPEH_F16"
++#define INSN_NAME vrecpeh_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
+@@ -4,22 +4,51 @@
+ #include <math.h>
+ 
+ /* Expected results with positive input.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xd70c, 0xd70c, 0xd70c, 0xd70c };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcedc, 0xcedc, 0xcedc, 0xcedc,
++					      0xcedc, 0xcedc, 0xcedc, 0xcedc };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2e19eb7, 0xc2e19eb7 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1db851f, 0xc1db851f,
+ 					   0xc1db851f, 0xc1db851f };
+ 
+ /* Expected results with FP special values (NaN).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ 
+ /* Expected results with FP special values (infinity, 0) and normal
+    values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x40000000, 0x40000000,
+ 					       0x40000000, 0x40000000 };
+ 
+ /* Expected results with FP special values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0x4000, 0x4000,
++						  0x4000, 0x4000 };
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000 };
++#endif
+ VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0x40000000, 0x40000000 };
+ VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x40000000, 0x40000000,
+ 					       0x40000000, 0x40000000 };
+@@ -38,74 +67,143 @@ void exec_vrecps(void)
+ 		    VECT_VAR(vector_res, T1, W, N))
+ 
+   /* No need for integer variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+   DECL_VARIABLE(vector2, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+   clean_results ();
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 12.9f);
++  VDUP(vector, q, float, f, 16, 8, 9.2f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 12.9f);
+   VDUP(vector, q, float, f, 32, 4, 9.2f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 8.9f);
++  VDUP(vector2, q, float, f, 16, 8, 3.2f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 8.9f);
+   VDUP(vector2, q, float, f, 32, 4, 3.2f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #define CMT " (positive input)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+ 
+ 
+   /* Test FP variants with special input values (NaN).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector2, q, float, f, 32, 4, NAN);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NaN)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+ 
+   /* Test FP variants with special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 3.2f); /* Restore a normal value.  */
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, q, float, f, 32, 4, 3.2f); /* Restore a normal value.  */
+ 
++
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (infinity, 0) and normal value"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ 
+ 
+   /* Test FP variants with only special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, , float, f, 16, 4, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, , float, f, 32, 2, 0.0f);
+   VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+ 
++
+   /* Apply the operator */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (infinity, 0)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c
+@@ -0,0 +1,50 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 12.4
++#define B -5.8
++#define C -3.8
++#define D 10
++#define E 66.1
++#define F 16.1
++#define G -4.8
++#define H -77
++
++#define I 0.7
++#define J -78
++#define K 10.23
++#define L 98
++#define M 87
++#define N -87.81
++#define O -1.1
++#define P 47.8
++
++float16_t input_1[] = { A, B, C, D, I, J, K, L };
++float16_t input_2[] = { E, F, G, H, M, N, O, P };
++uint16_t expected[] = { 0xE264 /* 2.0f - A * E.  */,
++			0x55F6 /* 2.0f - B * F.  */,
++			0xCC10 /* 2.0f - C * G.  */,
++			0x6208 /* 2.0f - D * H.  */,
++			0xD35D /* 2.0f - I * M.  */,
++			0xEEB0 /* 2.0f - J * N.  */,
++			0x4A9F /* 2.0f - K * O.  */,
++			0xEC93 /* 2.0f - L * P.  */ };
++
++#define TEST_MSG "VRECPSH_F16"
++#define INSN_NAME vrecpsh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c
+@@ -0,0 +1,32 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++
++float16_t input[] = { 123.4, 567.8, 34.8, 1024, 663.1, 144.0, 4.8, 77 };
++/*  Expected results are calculated by:
++  for (index = 0; index < 8; index++)
++    {
++      uint16_t src_cast = * (uint16_t *) &src[index];
++      * (uint16_t *) &expected[index] =
++	(src_cast & 0x8000) | (~src_cast & 0x7C00);
++    }  */
++uint16_t expected[8] = { 0x2800, 0x1C00, 0x2C00, 0x1800,
++			 0x1C00, 0x2400, 0x3800, 0x2800 };
++
++#define TEST_MSG "VRECPXH_F16"
++#define INSN_NAME vrecpxh_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+@@ -21,6 +21,8 @@ VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					    0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					    0xf2, 0xff, 0xf3, 0xff };
++VECT_VAR_DECL(expected_s8_10,int,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
++					     0x00, 0xcb, 0x80, 0xca };
+ 
+ /* Expected results for vreinterpret_s16_xx.  */
+ VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+@@ -32,6 +34,7 @@ VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+ VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+ VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_s16_10,int,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ 
+ /* Expected results for vreinterpret_s32_xx.  */
+ VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+@@ -43,6 +46,7 @@ VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfffffff0, 0xffffffff };
+ VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+ VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
++VECT_VAR_DECL(expected_s32_10,int,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
+ 
+ /* Expected results for vreinterpret_s64_xx.  */
+ VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+@@ -54,6 +58,7 @@ VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 0xfffffff1fffffff0 };
+ VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfffffffffffffff0 };
+ VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+ VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(expected_s64_10,int,64,1) [] = { 0xca80cb00cb80cc00 };
+ 
+ /* Expected results for vreinterpret_u8_xx.  */
+ VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+@@ -74,6 +79,8 @@ VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					     0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					     0xf2, 0xff, 0xf3, 0xff };
++VECT_VAR_DECL(expected_u8_10,uint,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
++					      0x00, 0xcb, 0x80, 0xca };
+ 
+ /* Expected results for vreinterpret_u16_xx.  */
+ VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+@@ -85,6 +92,7 @@ VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+ VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+ VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_u16_10,uint,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ 
+ /* Expected results for vreinterpret_u32_xx.  */
+ VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+@@ -96,6 +104,7 @@ VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+ VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
+ VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+ VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
++VECT_VAR_DECL(expected_u32_10,uint,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
+ 
+ /* Expected results for vreinterpret_u64_xx.  */
+ VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+@@ -107,6 +116,7 @@ VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+ VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfffffff1fffffff0 };
+ VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+ VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(expected_u64_10,uint,64,1) [] = { 0xca80cb00cb80cc00 };
+ 
+ /* Expected results for vreinterpret_p8_xx.  */
+ VECT_VAR_DECL(expected_p8_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+@@ -127,6 +137,8 @@ VECT_VAR_DECL(expected_p8_8,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 					     0xff, 0xff, 0xff, 0xff };
+ VECT_VAR_DECL(expected_p8_9,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					     0xf2, 0xff, 0xf3, 0xff };
++VECT_VAR_DECL(expected_p8_10,poly,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
++					      0x00, 0xcb, 0x80, 0xca };
+ 
+ /* Expected results for vreinterpret_p16_xx.  */
+ VECT_VAR_DECL(expected_p16_1,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+@@ -138,6 +150,7 @@ VECT_VAR_DECL(expected_p16_6,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+ VECT_VAR_DECL(expected_p16_7,poly,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+ VECT_VAR_DECL(expected_p16_8,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_p16_9,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_p16_10,poly,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ 
+ /* Expected results for vreinterpretq_s8_xx.  */
+ VECT_VAR_DECL(expected_q_s8_1,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+@@ -176,6 +189,10 @@ VECT_VAR_DECL(expected_q_s8_9,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					       0xf2, 0xff, 0xf3, 0xff,
+ 					       0xf4, 0xff, 0xf5, 0xff,
+ 					       0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_s8_10,int,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
++						0x00, 0xcb, 0x80, 0xca,
++						0x00, 0xca, 0x80, 0xc9,
++						0x00, 0xc9, 0x80, 0xc8 };
+ 
+ /* Expected results for vreinterpretq_s16_xx.  */
+ VECT_VAR_DECL(expected_q_s16_1,int,16,8) [] = { 0xf1f0, 0xf3f2,
+@@ -214,6 +231,10 @@ VECT_VAR_DECL(expected_q_s16_9,int,16,8) [] = { 0xfff0, 0xfff1,
+ 						0xfff2, 0xfff3,
+ 						0xfff4, 0xfff5,
+ 						0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_s16_10,int,16,8) [] = { 0xcc00, 0xcb80,
++						 0xcb00, 0xca80,
++						 0xca00, 0xc980,
++						 0xc900, 0xc880 };
+ 
+ /* Expected results for vreinterpretq_s32_xx.  */
+ VECT_VAR_DECL(expected_q_s32_1,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+@@ -234,6 +255,8 @@ VECT_VAR_DECL(expected_q_s32_8,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 						0xfbfaf9f8, 0xfffefdfc };
+ VECT_VAR_DECL(expected_q_s32_9,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 						0xfff5fff4, 0xfff7fff6 };
++VECT_VAR_DECL(expected_q_s32_10,int,32,4) [] = { 0xcb80cc00, 0xca80cb00,
++						 0xc980ca00, 0xc880c900 };
+ 
+ /* Expected results for vreinterpretq_s64_xx.  */
+ VECT_VAR_DECL(expected_q_s64_1,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+@@ -254,6 +277,8 @@ VECT_VAR_DECL(expected_q_s64_8,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 						0xfffefdfcfbfaf9f8 };
+ VECT_VAR_DECL(expected_q_s64_9,int,64,2) [] = { 0xfff3fff2fff1fff0,
+ 						0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(expected_q_s64_10,int,64,2) [] = { 0xca80cb00cb80cc00,
++						 0xc880c900c980ca00 };
+ 
+ /* Expected results for vreinterpretq_u8_xx.  */
+ VECT_VAR_DECL(expected_q_u8_1,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+@@ -292,6 +317,10 @@ VECT_VAR_DECL(expected_q_u8_9,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 						0xf2, 0xff, 0xf3, 0xff,
+ 						0xf4, 0xff, 0xf5, 0xff,
+ 						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_u8_10,uint,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
++						 0x00, 0xcb, 0x80, 0xca,
++						 0x00, 0xca, 0x80, 0xc9,
++						 0x00, 0xc9, 0x80, 0xc8 };
+ 
+ /* Expected results for vreinterpretq_u16_xx.  */
+ VECT_VAR_DECL(expected_q_u16_1,uint,16,8) [] = { 0xf1f0, 0xf3f2,
+@@ -330,6 +359,10 @@ VECT_VAR_DECL(expected_q_u16_9,uint,16,8) [] = { 0xfff0, 0xfff1,
+ 						 0xfff2, 0xfff3,
+ 						 0xfff4, 0xfff5,
+ 						 0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_u16_10,uint,16,8) [] = { 0xcc00, 0xcb80,
++						  0xcb00, 0xca80,
++						  0xca00, 0xc980,
++						  0xc900, 0xc880 };
+ 
+ /* Expected results for vreinterpretq_u32_xx.  */
+ VECT_VAR_DECL(expected_q_u32_1,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+@@ -350,6 +383,8 @@ VECT_VAR_DECL(expected_q_u32_8,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 						 0xfbfaf9f8, 0xfffefdfc };
+ VECT_VAR_DECL(expected_q_u32_9,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 						 0xfff5fff4, 0xfff7fff6 };
++VECT_VAR_DECL(expected_q_u32_10,uint,32,4) [] = { 0xcb80cc00, 0xca80cb00,
++						  0xc980ca00, 0xc880c900 };
+ 
+ /* Expected results for vreinterpretq_u64_xx.  */
+ VECT_VAR_DECL(expected_q_u64_1,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+@@ -370,6 +405,92 @@ VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 						0xfffefdfcfbfaf9f8 };
+ VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
+ 						 0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(expected_q_u64_10,uint,64,2) [] = { 0xca80cb00cb80cc00,
++						  0xc880c900c980ca00 };
++
++/* Expected results for vreinterpretq_p8_xx.  */
++VECT_VAR_DECL(expected_q_p8_1,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
++						0xf4, 0xf5, 0xf6, 0xf7,
++						0xf8, 0xf9, 0xfa, 0xfb,
++						0xfc, 0xfd, 0xfe, 0xff };
++VECT_VAR_DECL(expected_q_p8_2,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
++						0xf2, 0xff, 0xf3, 0xff,
++						0xf4, 0xff, 0xf5, 0xff,
++						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_p8_3,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xf2, 0xff, 0xff, 0xff,
++						0xf3, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_4,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_5,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
++						0xf4, 0xf5, 0xf6, 0xf7,
++						0xf8, 0xf9, 0xfa, 0xfb,
++						0xfc, 0xfd, 0xfe, 0xff };
++VECT_VAR_DECL(expected_q_p8_6,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
++						0xf2, 0xff, 0xf3, 0xff,
++						0xf4, 0xff, 0xf5, 0xff,
++						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_p8_7,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xf2, 0xff, 0xff, 0xff,
++						0xf3, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_8,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_9,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
++						0xf2, 0xff, 0xf3, 0xff,
++						0xf4, 0xff, 0xf5, 0xff,
++						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_p8_10,poly,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
++						 0x00, 0xcb, 0x80, 0xca,
++						 0x00, 0xca, 0x80, 0xc9,
++						 0x00, 0xc9, 0x80, 0xc8 };
++
++/* Expected results for vreinterpretq_p16_xx.  */
++VECT_VAR_DECL(expected_q_p16_1,poly,16,8) [] = { 0xf1f0, 0xf3f2,
++						 0xf5f4, 0xf7f6,
++						 0xf9f8, 0xfbfa,
++						 0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_p16_2,poly,16,8) [] = { 0xfff0, 0xfff1,
++						 0xfff2, 0xfff3,
++						 0xfff4, 0xfff5,
++						 0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_p16_3,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xfff1, 0xffff,
++						 0xfff2, 0xffff,
++						 0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_p16_4,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xffff, 0xffff,
++						 0xfff1, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_p16_5,poly,16,8) [] = { 0xf1f0, 0xf3f2,
++						 0xf5f4, 0xf7f6,
++						 0xf9f8, 0xfbfa,
++						 0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_p16_6,poly,16,8) [] = { 0xfff0, 0xfff1,
++						 0xfff2, 0xfff3,
++						 0xfff4, 0xfff5,
++						 0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_p16_7,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xfff1, 0xffff,
++						 0xfff2, 0xffff,
++						 0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_p16_8,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xffff, 0xffff,
++						 0xfff1, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_p16_9,poly,16,8) [] = { 0xf1f0, 0xf3f2,
++						 0xf5f4, 0xf7f6,
++						 0xf9f8, 0xfbfa,
++						 0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_p16_10,poly,16,8) [] = { 0xcc00, 0xcb80,
++						  0xcb00, 0xca80,
++						  0xca00, 0xc980,
++						  0xc900, 0xc880 };
+ 
+ /* Expected results for vreinterpret_f32_xx.  */
+ VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+@@ -382,6 +503,7 @@ VECT_VAR_DECL(expected_f32_7,hfloat,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_f32_8,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
+ VECT_VAR_DECL(expected_f32_9,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+ VECT_VAR_DECL(expected_f32_10,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
++VECT_VAR_DECL(expected_f32_11,hfloat,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
+ 
+ /* Expected results for vreinterpretq_f32_xx.  */
+ VECT_VAR_DECL(expected_q_f32_1,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+@@ -404,8 +526,10 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 						   0xfbfaf9f8, 0xfffefdfc };
+ VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 						    0xfff5fff4, 0xfff7fff6 };
++VECT_VAR_DECL(expected_q_f32_11,hfloat,32,4) [] = { 0xcb80cc00, 0xca80cb00,
++						    0xc980ca00, 0xc880c900 };
+ 
+-/* Expected results for vreinterpretq_xx_f32.  */
++/* Expected results for vreinterpret_xx_f32.  */
+ VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 						0x0, 0x0, 0x70, 0xc1 };
+ VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+@@ -419,6 +543,7 @@ VECT_VAR_DECL(expected_xx_f32_8,uint,64,1) [] = { 0xc1700000c1800000 };
+ VECT_VAR_DECL(expected_xx_f32_9,poly,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 						 0x0, 0x0, 0x70, 0xc1 };
+ VECT_VAR_DECL(expected_xx_f32_10,poly,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
++VECT_VAR_DECL(expected_xx_f32_11,hfloat,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+ 
+ /* Expected results for vreinterpretq_xx_f32.  */
+ VECT_VAR_DECL(expected_q_xx_f32_1,int,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
+@@ -447,6 +572,62 @@ VECT_VAR_DECL(expected_q_xx_f32_9,poly,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 						    0x0, 0x0, 0x50, 0xc1 };
+ VECT_VAR_DECL(expected_q_xx_f32_10,poly,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
+ 						     0x0, 0xc160, 0x0, 0xc150 };
++VECT_VAR_DECL(expected_q_xx_f32_11,hfloat,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
++						      0x0, 0xc160, 0x0, 0xc150 };
++
++/* Expected results for vreinterpret_f16_xx.  */
++VECT_VAR_DECL(expected_f16_1,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_f16_2,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_f16_3,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
++VECT_VAR_DECL(expected_f16_4,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(expected_f16_5,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_f16_6,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_f16_7,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
++VECT_VAR_DECL(expected_f16_8,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(expected_f16_9,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_f16_10,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++
++/* Expected results for vreinterpretq_f16_xx.  */
++VECT_VAR_DECL(expected_q_f16_1,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
++						   0xf5f4, 0xf7f6,
++						   0xf9f8, 0xfbfa,
++						   0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_f16_2,hfloat,16,8) [] = { 0xfff0, 0xfff1,
++						   0xfff2, 0xfff3,
++						   0xfff4, 0xfff5,
++						   0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_f16_3,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xfff1, 0xffff,
++						   0xfff2, 0xffff,
++						   0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_f16_4,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xffff, 0xffff,
++						   0xfff1, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_f16_5,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
++						   0xf5f4, 0xf7f6,
++						   0xf9f8, 0xfbfa,
++						   0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_f16_6,hfloat,16,8) [] = { 0xfff0, 0xfff1,
++						   0xfff2, 0xfff3,
++						   0xfff4, 0xfff5,
++						   0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_f16_7,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xfff1, 0xffff,
++						   0xfff2, 0xffff,
++						   0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_f16_8,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xffff, 0xffff,
++						   0xfff1, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_f16_9,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
++						   0xf5f4, 0xf7f6,
++						   0xf9f8, 0xfbfa,
++						   0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_f16_10,hfloat,16,8) [] = { 0xfff0, 0xfff1,
++						    0xfff2, 0xfff3,
++						    0xfff4, 0xfff5,
++						    0xfff6, 0xfff7 };
+ 
+ #define TEST_MSG "VREINTERPRET/VREINTERPRETQ"
+ 
+@@ -484,6 +665,10 @@ void exec_vreinterpret (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -497,6 +682,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 64, 1, expected_s8_7);
+   TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 8, 8, expected_s8_8);
+   TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 16, 4, expected_s8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 8, 8, float, f, 16, 4, expected_s8_10);
++#endif
+ 
+   /* vreinterpret_s16_xx.  */
+   TEST_VREINTERPRET(, int, s, 16, 4, int, s, 8, 8, expected_s16_1);
+@@ -508,6 +696,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 64, 1, expected_s16_7);
+   TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 8, 8, expected_s16_8);
+   TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 16, 4, expected_s16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 16, 4, float, f, 16, 4, expected_s16_10);
++#endif
+ 
+   /* vreinterpret_s32_xx.  */
+   TEST_VREINTERPRET(, int, s, 32, 2, int, s, 8, 8, expected_s32_1);
+@@ -519,6 +710,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 64, 1, expected_s32_7);
+   TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 8, 8, expected_s32_8);
+   TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 16, 4, expected_s32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 32, 2, float, f, 16, 4, expected_s32_10);
++#endif
+ 
+   /* vreinterpret_s64_xx.  */
+   TEST_VREINTERPRET(, int, s, 64, 1, int, s, 8, 8, expected_s64_1);
+@@ -530,6 +724,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 64, 1, expected_s64_7);
+   TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 8, 8, expected_s64_8);
+   TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 16, 4, expected_s64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 64, 1, float, f, 16, 4, expected_s64_10);
++#endif
+ 
+   /* vreinterpret_u8_xx.  */
+   TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 8, 8, expected_u8_1);
+@@ -541,6 +738,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 64, 1, expected_u8_7);
+   TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 8, 8, expected_u8_8);
+   TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 16, 4, expected_u8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 8, 8, float, f, 16, 4, expected_u8_10);
++#endif
+ 
+   /* vreinterpret_u16_xx.  */
+   TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 8, 8, expected_u16_1);
+@@ -552,6 +752,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 64, 1, expected_u16_7);
+   TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 8, 8, expected_u16_8);
+   TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 16, 4, expected_u16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 16, 4, float, f, 16, 4, expected_u16_10);
++#endif
+ 
+   /* vreinterpret_u32_xx.  */
+   TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 8, 8, expected_u32_1);
+@@ -563,6 +766,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 64, 1, expected_u32_7);
+   TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 8, 8, expected_u32_8);
+   TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 16, 4, expected_u32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 32, 2, float, f, 16, 4, expected_u32_10);
++#endif
+ 
+   /* vreinterpret_u64_xx.  */
+   TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 8, 8, expected_u64_1);
+@@ -574,6 +780,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 32, 2, expected_u64_7);
+   TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 8, 8, expected_u64_8);
+   TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 16, 4, expected_u64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 16, 4, expected_u64_10);
++#endif
+ 
+   /* vreinterpret_p8_xx.  */
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 8, 8, expected_p8_1);
+@@ -585,6 +794,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 32, 2, expected_p8_7);
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 64, 1, expected_p8_8);
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, poly, p, 16, 4, expected_p8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 16, 4, expected_p8_10);
++#endif
+ 
+   /* vreinterpret_p16_xx.  */
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 8, 8, expected_p16_1);
+@@ -596,6 +808,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 32, 2, expected_p16_7);
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 64, 1, expected_p16_8);
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, poly, p, 8, 8, expected_p16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 16, 4, expected_p16_10);
++#endif
+ 
+   /* vreinterpretq_s8_xx.  */
+   TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 16, 8, expected_q_s8_1);
+@@ -607,6 +822,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 64, 2, expected_q_s8_7);
+   TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 8, 16, expected_q_s8_8);
+   TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 16, 8, expected_q_s8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 16, 8, expected_q_s8_10);
++#endif
+ 
+   /* vreinterpretq_s16_xx.  */
+   TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 8, 16, expected_q_s16_1);
+@@ -618,6 +836,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 64, 2, expected_q_s16_7);
+   TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 8, 16, expected_q_s16_8);
+   TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 16, 8, expected_q_s16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 16, 8, float, f, 16, 8, expected_q_s16_10);
++#endif
+ 
+   /* vreinterpretq_s32_xx.  */
+   TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 8, 16, expected_q_s32_1);
+@@ -629,6 +850,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 64, 2, expected_q_s32_7);
+   TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 8, 16, expected_q_s32_8);
+   TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 16, 8, expected_q_s32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 32, 4, float, f, 16, 8, expected_q_s32_10);
++#endif
+ 
+   /* vreinterpretq_s64_xx.  */
+   TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 8, 16, expected_q_s64_1);
+@@ -640,6 +864,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 64, 2, expected_q_s64_7);
+   TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 8, 16, expected_q_s64_8);
+   TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 16, 8, expected_q_s64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 64, 2, float, f, 16, 8, expected_q_s64_10);
++#endif
+ 
+   /* vreinterpretq_u8_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 8, 16, expected_q_u8_1);
+@@ -651,6 +878,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 64, 2, expected_q_u8_7);
+   TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 8, 16, expected_q_u8_8);
+   TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 16, 8, expected_q_u8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 8, 16, float, f, 16, 8, expected_q_u8_10);
++#endif
+ 
+   /* vreinterpretq_u16_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 8, 16, expected_q_u16_1);
+@@ -662,6 +892,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 64, 2, expected_q_u16_7);
+   TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 8, 16, expected_q_u16_8);
+   TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 16, 8, expected_q_u16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 16, 8, float, f, 16, 8, expected_q_u16_10);
++#endif
+ 
+   /* vreinterpretq_u32_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 8, 16, expected_q_u32_1);
+@@ -673,6 +906,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 64, 2, expected_q_u32_7);
+   TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 8, 16, expected_q_u32_8);
+   TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 16, 8, expected_q_u32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 32, 4, float, f, 16, 8, expected_q_u32_10);
++#endif
+ 
+   /* vreinterpretq_u64_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 8, 16, expected_q_u64_1);
+@@ -684,6 +920,37 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 32, 4, expected_q_u64_7);
+   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
+   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 16, 8, expected_q_u64_10);
++#endif
++
++  /* vreinterpretq_p8_xx.  */
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 16, 8, expected_q_p8_2);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 32, 4, expected_q_p8_3);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 64, 2, expected_q_p8_4);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 8, 16, expected_q_p8_5);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 16, 8, expected_q_p8_6);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 16, 8, expected_q_p8_10);
++#endif
++
++  /* vreinterpretq_p16_xx.  */
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 16, 8, expected_q_p16_2);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 32, 4, expected_q_p16_3);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 64, 2, expected_q_p16_4);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 8, 16, expected_q_p16_5);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 16, 8, expected_q_p16_6);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 16, 8, expected_q_p16_10);
++#endif
+ 
+   /* vreinterpret_f32_xx.  */
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
+@@ -696,6 +963,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 64, 1, expected_f32_8);
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 8, 8, expected_f32_9);
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 16, 4, expected_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(, float, f, 32, 2, float, f, 16, 4, expected_f32_11);
++#endif
+ 
+   /* vreinterpretq_f32_xx.  */
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 8, 16, expected_q_f32_1);
+@@ -708,6 +978,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 64, 2, expected_q_f32_8);
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 8, 16, expected_q_f32_9);
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 16, 8, expected_q_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(q, float, f, 32, 4, float, f, 16, 8, expected_q_f32_11);
++#endif
+ 
+   /* vreinterpret_xx_f32.  */
+   TEST_VREINTERPRET(, int, s, 8, 8, float, f, 32, 2, expected_xx_f32_1);
+@@ -720,6 +993,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 32, 2, expected_xx_f32_8);
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 32, 2, expected_xx_f32_9);
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 32, 2, expected_xx_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, float, f, 32, 2, expected_xx_f32_11);
++#endif
+ 
+   /* vreinterpretq_xx_f32.  */
+   TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 32, 4, expected_q_xx_f32_1);
+@@ -732,6 +1008,33 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 32, 4, expected_q_xx_f32_8);
+   TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 32, 4, expected_q_xx_f32_9);
+   TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 32, 4, expected_q_xx_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, float, f, 32, 4, expected_q_xx_f32_11);
++
++  /* vreinterpret_f16_xx.  */
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 8, 8, expected_f16_1);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 16, 4, expected_f16_2);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 32, 2, expected_f16_3);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 64, 1, expected_f16_4);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 8, 8, expected_f16_5);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 16, 4, expected_f16_6);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 32, 2, expected_f16_7);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 64, 1, expected_f16_8);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 8, 8, expected_f16_9);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 16, 4, expected_f16_10);
++
++  /* vreinterpretq_f16_xx.  */
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 8, 16, expected_q_f16_1);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 16, 8, expected_q_f16_2);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 32, 4, expected_q_f16_3);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 64, 2, expected_q_f16_4);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 8, 16, expected_q_f16_5);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 16, 8, expected_q_f16_6);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 32, 4, expected_q_f16_7);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 64, 2, expected_q_f16_8);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 8, 16, expected_q_f16_9);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 16, 8, expected_q_f16_10);
++#endif
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
+@@ -0,0 +1,165 @@
++/* This file contains tests for the vreinterpret *p128 intrinsics.  */
++
++/* { dg-require-effective-target arm_crypto_ok { target { arm*-*-* } } } */
++/* { dg-add-options arm_crypto } */
++/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results: vreinterpretq_p128_*.  */
++VECT_VAR_DECL(vreint_expected_q_p128_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							  0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p128_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							   0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p128_s32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							   0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p128_s64,poly,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p128_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							  0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p128_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							   0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p128_u32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							   0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p128_u64,poly,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p128_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							  0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p128_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							   0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000,
++							   0xc1500000c1600000 };
++VECT_VAR_DECL(vreint_expected_q_p128_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
++							   0xc880c900c980ca00 };
++
++/* Expected results: vreinterpretq_*_p128.  */
++VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff,
++							 0xf1, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_s16_p128,int,16,8) [] = { 0xfff0, 0xffff,
++							  0xffff, 0xffff,
++							  0xfff1, 0xffff,
++							  0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_s32_p128,int,32,4) [] = { 0xfffffff0, 0xffffffff,
++							  0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_s64_p128,int,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_u8_p128,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff,
++							  0xf1, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_u16_p128,uint,16,8) [] = { 0xfff0, 0xffff,
++							   0xffff, 0xffff,
++							   0xfff1, 0xffff,
++							   0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_u32_p128,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
++							   0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_u64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p8_p128,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff,
++							  0xf1, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_p16_p128,poly,16,8) [] = { 0xfff0, 0xffff,
++							   0xffff, 0xffff,
++							   0xfff1, 0xffff,
++							   0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_p64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_f32_p128,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
++							     0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_f16_p128,hfloat,16,8) [] = { 0xfff0, 0xffff,
++							     0xffff, 0xffff,
++							     0xfff1, 0xffff,
++							     0xffff, 0xffff };
++
++int main (void)
++{
++  DECL_VARIABLE_128BITS_VARIANTS(vreint_vector);
++  DECL_VARIABLE_128BITS_VARIANTS(vreint_vector_res);
++
++  clean_results ();
++
++  TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
++  VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
++
++  /* vreinterpretq_p128_* tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRETQ_P128_*"
++
++  /* Since there is no way to store a poly128_t value, convert to
++     poly64x2_t before storing. This means that we are not able to
++     test vreinterpretq_p128* alone, and that errors in
++     vreinterpretq_p64_p128 could compensate for errors in
++     vreinterpretq_p128*.  */
++#define TEST_VREINTERPRET128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, poly, 64, 2) =  vreinterpretq_p64_p128(	\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS))); \
++  vst1##Q##_##T2##64(VECT_VAR(result, poly, 64, 2),			\
++                     VECT_VAR(vreint_vector_res, poly, 64, 2));		\
++  CHECK_POLY(TEST_MSG, T1, 64, 2, PRIx##64, EXPECTED, "");
++
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 8, 16, vreint_expected_q_p128_s8);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 16, 8, vreint_expected_q_p128_s16);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 32, 4, vreint_expected_q_p128_s32);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 64, 2, vreint_expected_q_p128_s64);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 8, 16, vreint_expected_q_p128_u8);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 16, 8, vreint_expected_q_p128_u16);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 32, 4, vreint_expected_q_p128_u32);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 16, 8, vreint_expected_q_p128_f16);
++#endif
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32);
++
++  /* vreinterpretq_*_p128 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRETQ_*_P128"
++
++  /* Since there is no way to load a poly128_t value, load a
++     poly64x2_t and convert it to poly128_t. This means that we are
++     not able to test vreinterpretq_*_p128 alone, and that errors in
++     vreinterpretq_p128_p64 could compensate for errors in
++     vreinterpretq_*_p128*.  */
++#define TEST_VREINTERPRET_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(				\
++  vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2)));		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++#define TEST_VREINTERPRET_FP_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(				\
++  vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2)));		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 8, 16, poly, p, 128, 1, vreint_expected_q_s8_p128);
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 16, 8, poly, p, 128, 1, vreint_expected_q_s16_p128);
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 32, 4, poly, p, 128, 1, vreint_expected_q_s32_p128);
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 64, 2, poly, p, 128, 1, vreint_expected_q_s64_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 8, 16, poly, p, 128, 1, vreint_expected_q_u8_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 16, 8, poly, p, 128, 1, vreint_expected_q_u16_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 32, 4, poly, p, 128, 1, vreint_expected_q_u32_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128);
++  TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128);
++  TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 16, 8, poly, p, 128, 1, vreint_expected_q_f16_p128);
++#endif
++  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128);
++
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
+@@ -0,0 +1,216 @@
++/* This file contains tests for the vreinterpret *p64 intrinsics.  */
++
++/* { dg-require-effective-target arm_crypto_ok { target { arm*-*-* } } } */
++/* { dg-add-options arm_crypto } */
++/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results: vreinterpret_p64_*.  */
++VECT_VAR_DECL(vreint_expected_p64_s8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
++VECT_VAR_DECL(vreint_expected_p64_s16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(vreint_expected_p64_s32,poly,64,1) [] = { 0xfffffff1fffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_s64,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_u8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
++VECT_VAR_DECL(vreint_expected_p64_u16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(vreint_expected_p64_u32,poly,64,1) [] = { 0xfffffff1fffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_u64,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_p8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
++VECT_VAR_DECL(vreint_expected_p64_p16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(vreint_expected_p64_f32,poly,64,1) [] = { 0xc1700000c1800000 };
++VECT_VAR_DECL(vreint_expected_p64_f16,poly,64,1) [] = { 0xca80cb00cb80cc00 };
++
++/* Expected results: vreinterpretq_p64_*.  */
++VECT_VAR_DECL(vreint_expected_q_p64_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							 0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p64_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							  0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p64_s32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							  0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p64_s64,poly,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p64_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							 0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p64_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							  0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p64_u32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							  0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p64_u64,poly,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p64_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							 0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p64_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							  0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p64_f32,poly,64,2) [] = { 0xc1700000c1800000,
++							  0xc1500000c1600000 };
++VECT_VAR_DECL(vreint_expected_q_p64_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
++							  0xc880c900c980ca00 };
++
++/* Expected results: vreinterpret_*_p64.  */
++VECT_VAR_DECL(vreint_expected_s8_p64,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
++						     0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_s16_p64,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_s32_p64,int,32,2) [] = { 0xfffffff0, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_s64_p64,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_u8_p64,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
++						      0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_u16_p64,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_u32_p64,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_u64_p64,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_p8_p64,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
++						      0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_p16_p64,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_f32_p64,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_f16_p64,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++
++/* Expected results: vreinterpretq_*_p64.  */
++VECT_VAR_DECL(vreint_expected_q_s8_p64,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							0xff, 0xff, 0xff, 0xff,
++							0xf1, 0xff, 0xff, 0xff,
++							0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_s16_p64,int,16,8) [] = { 0xfff0, 0xffff,
++							 0xffff, 0xffff,
++							 0xfff1, 0xffff,
++							 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_s32_p64,int,32,4) [] = { 0xfffffff0, 0xffffffff,
++							 0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_s64_p64,int,64,2) [] = { 0xfffffffffffffff0,
++							 0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_u8_p64,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff,
++							 0xf1, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_u16_p64,uint,16,8) [] = { 0xfff0, 0xffff,
++							  0xffff, 0xffff,
++							  0xfff1, 0xffff,
++							  0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_u32_p64,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
++							  0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_u64_p64,uint,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p8_p64,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff,
++							 0xf1, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_p16_p64,poly,16,8) [] = { 0xfff0, 0xffff,
++							  0xffff, 0xffff,
++							  0xfff1, 0xffff,
++							  0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_f32_p64,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
++							    0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_f16_p64,hfloat,16,8) [] = { 0xfff0, 0xffff,
++							    0xffff, 0xffff,
++							    0xfff1, 0xffff,
++							    0xffff, 0xffff };
++
++int main (void)
++{
++#define TEST_VREINTERPRET(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED)	\
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++#define TEST_VREINTERPRET_TO_POLY(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED)	\
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK_POLY(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++#define TEST_VREINTERPRET_FP(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++  DECL_VARIABLE_ALL_VARIANTS(vreint_vector);
++  DECL_VARIABLE_ALL_VARIANTS(vreint_vector_res);
++
++  clean_results ();
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
++  VLOAD(vreint_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vreint_vector, buffer, , float, f, 16, 4);
++  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vreint_vector, buffer, , float, f, 32, 2);
++  VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
++
++  /* vreinterpret_p64_* tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRET_P64_*"
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 8, 8, vreint_expected_p64_s8);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 16, 4, vreint_expected_p64_s16);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 32, 2, vreint_expected_p64_s32);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 64, 1, vreint_expected_p64_s64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 8, 8, vreint_expected_p64_u8);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 16, 4, vreint_expected_p64_u16);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 32, 2, vreint_expected_p64_u32);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, float, f, 16, 4, vreint_expected_p64_f16);
++#endif
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32);
++
++  /* vreinterpretq_p64_* tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRETQ_P64_*"
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 8, 16, vreint_expected_q_p64_s8);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 16, 8, vreint_expected_q_p64_s16);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 32, 4, vreint_expected_q_p64_s32);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 64, 2, vreint_expected_q_p64_s64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 8, 16, vreint_expected_q_p64_u8);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 16, 8, vreint_expected_q_p64_u16);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 32, 4, vreint_expected_q_p64_u32);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, float, f, 16, 8, vreint_expected_q_p64_f16);
++#endif
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32);
++
++  /* vreinterpret_*_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRET_*_P64"
++
++  TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 64, 1, vreint_expected_s8_p64);
++  TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 64, 1, vreint_expected_s16_p64);
++  TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 64, 1, vreint_expected_s32_p64);
++  TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 64, 1, vreint_expected_s64_p64);
++  TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 64, 1, vreint_expected_u8_p64);
++  TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 64, 1, vreint_expected_u16_p64);
++  TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 64, 1, vreint_expected_u32_p64);
++  TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 64, 1, vreint_expected_f16_p64);
++#endif
++  TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64);
++  TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64);
++  TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64);
++  TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 64, 2, vreint_expected_q_s32_p64);
++  TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 64, 2, vreint_expected_q_s64_p64);
++  TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 64, 2, vreint_expected_q_u8_p64);
++  TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 64, 2, vreint_expected_q_u16_p64);
++  TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 64, 2, vreint_expected_q_u32_p64);
++  TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 64, 2, vreint_expected_q_f16_p64);
++#endif
++  TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64);
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
+@@ -63,6 +63,10 @@ VECT_VAR_DECL(expected_vrev64,uint,32,2) [] = { 0xfffffff1, 0xfffffff0 };
+ VECT_VAR_DECL(expected_vrev64,poly,8,8) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 					       0xf3, 0xf2, 0xf1, 0xf0 };
+ VECT_VAR_DECL(expected_vrev64,poly,16,4) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected_vrev64, hfloat, 16, 4) [] = { 0xca80, 0xcb00,
++						      0xcb80, 0xcc00 };
++#endif
+ VECT_VAR_DECL(expected_vrev64,hfloat,32,2) [] = { 0xc1700000, 0xc1800000 };
+ VECT_VAR_DECL(expected_vrev64,int,8,16) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 					       0xf3, 0xf2, 0xf1, 0xf0,
+@@ -86,6 +90,12 @@ VECT_VAR_DECL(expected_vrev64,poly,8,16) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 						0xfb, 0xfa, 0xf9, 0xf8 };
+ VECT_VAR_DECL(expected_vrev64,poly,16,8) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0,
+ 						0xfff7, 0xfff6, 0xfff5, 0xfff4 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected_vrev64, hfloat, 16, 8) [] = { 0xca80, 0xcb00,
++						      0xcb80, 0xcc00,
++						      0xc880, 0xc900,
++						      0xc980, 0xca00 };
++#endif
+ VECT_VAR_DECL(expected_vrev64,hfloat,32,4) [] = { 0xc1700000, 0xc1800000,
+ 						  0xc1500000, 0xc1600000 };
+ 
+@@ -104,6 +114,10 @@ void exec_vrev (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD (vector, buffer, , float, f, 16, 4);
++  VLOAD (vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -118,10 +132,10 @@ void exec_vrev (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vrev16, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev16, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev16, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev16, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev16, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev16, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev16, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev16, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VREV32"
+@@ -142,14 +156,14 @@ void exec_vrev (void)
+   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev32, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev32, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev32, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VREV64"
+@@ -176,17 +190,23 @@ void exec_vrev (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev64, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev64, "");
+ 
++#if defined (FP16_SUPPORTED)
++  TEST_VREV (, float, f, 16, 4, 64);
++  TEST_VREV (q, float, f, 16, 8, 64);
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx32, expected_vrev64, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx32, expected_vrev64, "");
++#endif
+   TEST_VREV(, float, f, 32, 2, 64);
+   TEST_VREV(q, float, f, 32, 4, 64);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_vrev64, "");
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
+@@ -0,0 +1,24 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrnd
++#define TEST_MSG "VRND"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
+@@ -0,0 +1,63 @@
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++void FNNAME (INSN) (void)
++{
++  /* vector_res = vrndX (vector), then store the result.  */
++#define TEST_VRND2(INSN, Q, T1, T2, W, N)				\
++  VECT_VAR (vector_res, T1, W, N) =					\
++    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));			\
++    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),			\
++		       VECT_VAR (vector_res, T1, W, N))
++
++  /* Two auxliary macros are necessary to expand INSN.  */
++#define TEST_VRND1(INSN, Q, T1, T2, W, N)	\
++  TEST_VRND2 (INSN, Q, T1, T2, W, N)
++
++#define TEST_VRND(Q, T1, T2, W, N)		\
++  TEST_VRND1 (INSN, Q, T1, T2, W, N)
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
++  DECL_VARIABLE (vector, float, 32, 2);
++  DECL_VARIABLE (vector, float, 32, 4);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++  DECL_VARIABLE (vector_res, float, 32, 2);
++  DECL_VARIABLE (vector_res, float, 32, 4);
++
++  clean_results ();
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD (vector, buffer, , float, f, 16, 4);
++  VLOAD (vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD (vector, buffer, , float, f, 32, 2);
++  VLOAD (vector, buffer, q, float, f, 32, 4);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRND ( , float, f, 16, 4);
++  TEST_VRND (q, float, f, 16, 8);
++#endif
++  TEST_VRND ( , float, f, 32, 2);
++  TEST_VRND (q, float, f, 32, 4);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
++}
++
++int
++main (void)
++{
++  FNNAME (INSN) ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
+@@ -0,0 +1,25 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrnda
++#define TEST_MSG "VRNDA"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDAH_F16"
++#define INSN_NAME vrndah_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc700 /* -7.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDH_F16"
++#define INSN_NAME vrndh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c
+@@ -0,0 +1,71 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (123.4)
++#define RNDI_A 0x57B0 /* FP16_C (123).  */
++#define B FP16_C (-567.5)
++#define RNDI_B 0xE070 /* FP16_C (-568).  */
++#define C FP16_C (-34.8)
++#define RNDI_C 0xD060 /* FP16_C (-35).  */
++#define D FP16_C (1024)
++#define RNDI_D 0x6400 /* FP16_C (1024).  */
++#define E FP16_C (663.1)
++#define RNDI_E 0x612E /* FP16_C (663).  */
++#define F FP16_C (169.1)
++#define RNDI_F 0x5948 /* FP16_C (169).  */
++#define G FP16_C (-4.8)
++#define RNDI_G 0xC500 /* FP16_C (-5).  */
++#define H FP16_C (77.5)
++#define RNDI_H 0x54E0 /* FP16_C (78).  */
++
++/* Expected results for vrndi.  */
++VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
++  = { RNDI_A, RNDI_B, RNDI_C, RNDI_D };
++
++VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
++  = { RNDI_A, RNDI_B, RNDI_C, RNDI_D, RNDI_E, RNDI_F, RNDI_G, RNDI_H };
++
++void exec_vrndi_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VRNDI (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A, B, C, D};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vrndi_f16 (VECT_VAR (vsrc, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VRNDIQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A, B, C, D, E, F, G, H};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vrndiq_f16 (VECT_VAR (vsrc, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
++}
++
++int
++main (void)
++{
++  exec_vrndi_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDIH_F16"
++#define INSN_NAME vrndih_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
+@@ -0,0 +1,25 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndm
++#define TEST_MSG "VRNDM"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc200 /* -3.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc700 /* -7.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDMH_F16"
++#define INSN_NAME vrndmh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
+@@ -0,0 +1,25 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndn
++#define TEST_MSG "VRNDN"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDNH_F16"
++#define INSN_NAME vrndnh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
+@@ -0,0 +1,24 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndp
++#define TEST_MSG "VRNDP"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4400 /* 4.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc000 /* -2.000000 */,
++  0x4000 /* 2.000000 */,
++  0xc700 /* -7.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4b00 /* 14.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDPH_F16"
++#define INSN_NAME vrndph_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
+@@ -0,0 +1,24 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndx
++#define TEST_MSG "VRNDX"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDNH_F16"
++#define INSN_NAME vrndnh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
+@@ -7,6 +7,11 @@
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x9c800000, 0x9c800000,
+ 					 0x9c800000, 0x9c800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x324c, 0x324c, 0x324c, 0x324c };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x3380, 0x3380, 0x3380, 0x3380,
++					      0x3380, 0x3380, 0x3380, 0x3380 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x3e498000, 0x3e498000 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x3e700000, 0x3e700000,
+ 					   0x3e700000, 0x3e700000 };
+@@ -22,17 +27,39 @@ VECT_VAR_DECL(expected_2,uint,32,4) [] = { 0xed000000, 0xed000000,
+ 					   0xed000000, 0xed000000 };
+ 
+ /* Expected results with FP special inputs values (NaNs, ...).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
+ 					       0x7f800000, 0x7f800000 };
+ 
+ /* Expected results with FP special inputs values
+    (negative, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0,
++						  0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results with FP special inputs values
+    (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++#endif
+ VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+@@ -50,32 +77,60 @@ void exec_vrsqrte(void)
+ 		    VECT_VAR(vector_res, T1, W, N))
+ 
+   DECL_VARIABLE(vector, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
+   DECL_VARIABLE(vector_res, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+   clean_results ();
+ 
+   /* Choose init value arbitrarily.  */
+   VDUP(vector, , uint, u, 32, 2, 0x12345678);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 25.799999f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 25.799999f);
+   VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, q, float, f, 16, 8, 18.2f);
++#endif
+   VDUP(vector, q, float, f, 32, 4, 18.2f);
+ 
+   /* Apply the operator.  */
+   TEST_VRSQRTE(, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #define CMT ""
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+ 
+@@ -110,42 +165,78 @@ void exec_vrsqrte(void)
+ 
+ 
+   /* Test FP variants with special input values (NaNs, ...).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NaN, 0)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+ 
+   /* Test FP variants with special input values (negative, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -1.0f);
++  VDUP(vector, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, -1.0f);
+   VDUP(vector, q, float, f, 32, 4, HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (negative, infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ 
+   /* Test FP variants with special input values (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -0.0f);
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, -0.0f);
+   VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (-0, -infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c
+@@ -0,0 +1,30 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.4, 67.8, 34.8, 24.0, 66.1, 144.0, 4.8, 77.0 };
++uint16_t expected[] = { 0x2DC4 /* FP16_C (1/__builtin_sqrtf (123.4)).  */,
++			0x2FC8 /* FP16_C (1/__builtin_sqrtf (67.8)).  */,
++			0x316C /* FP16_C (1/__builtin_sqrtf (34.8)).  */,
++			0x3288 /* FP16_C (1/__builtin_sqrtf (24.0)).  */,
++			0x2FDC /* FP16_C (1/__builtin_sqrtf (66.1)).  */,
++			0x2D54 /* FP16_C (1/__builtin_sqrtf (144.0)).  */,
++			0x3750 /* FP16_C (1/__builtin_sqrtf (4.8)).  */,
++			0x2F48 /* FP16_C (1/__builtin_sqrtf (77.0)).  */ };
++
++#define TEST_MSG "VRSQRTEH_F16"
++#define INSN_NAME vrsqrteh_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
+@@ -4,22 +4,51 @@
+ #include <math.h>
+ 
+ /* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xd3cb, 0xd3cb, 0xd3cb, 0xd3cb };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xc726, 0xc726, 0xc726, 0xc726,
++					      0xc726, 0xc726, 0xc726, 0xc726 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2796b84, 0xc2796b84 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc0e4a3d8, 0xc0e4a3d8,
+ 					   0xc0e4a3d8, 0xc0e4a3d8 };
+ 
+ /* Expected results with input=NaN.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++#endif
+ VECT_VAR_DECL(expected_nan,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ 
+ /* Expected results with FP special inputs values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000,
+ 					       0x3fc00000, 0x3fc00000 };
+ 
+ /* Expected results with only FP special inputs values (infinity,
+    0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x3e00, 0x3e00,
++						  0x3e00, 0x3e00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x3fc00000, 0x3fc00000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000,
+ 					       0x3fc00000, 0x3fc00000 };
+@@ -38,75 +67,143 @@ void exec_vrsqrts(void)
+ 		    VECT_VAR(vector_res, T1, W, N))
+ 
+   /* No need for integer variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+   DECL_VARIABLE(vector2, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+   clean_results ();
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 12.9f);
++  VDUP(vector, q, float, f, 16, 8, 9.1f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 12.9f);
+   VDUP(vector, q, float, f, 32, 4, 9.1f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 9.9f);
++  VDUP(vector2, q, float, f, 16, 8, 1.9f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 9.9f);
+   VDUP(vector2, q, float, f, 32, 4, 1.9f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #define CMT ""
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+ 
+ 
+   /* Test FP variants with special input values (NaN).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector2, q, float, f, 32, 4, NAN);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NAN) and normal values"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_nan, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_nan, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, CMT);
+ 
+ 
+   /* Test FP variants with special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  /* Restore a normal value in vector2.  */
++  VDUP(vector2, q, float, f, 16, 8, 3.2f);
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   /* Restore a normal value in vector2.  */
+   VDUP(vector2, q, float, f, 32, 4, 3.2f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (infinity, 0) and normal values"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+ 
+   /* Test FP variants with only special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, , float, f, 16, 4, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, , float, f, 32, 2, -0.0f);
+   VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " only FP special (infinity, 0)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c
+@@ -0,0 +1,50 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 12.4
++#define B -5.8
++#define C -3.8
++#define D 10
++#define E 66.1
++#define F 16.1
++#define G -4.8
++#define H -77
++
++#define I 0.7
++#define J -78
++#define K 10.23
++#define L 98
++#define M 87
++#define N -87.81
++#define O -1.1
++#define P 47.8
++
++float16_t input_1[] = { A, B, C, D, I, J, K, L };
++float16_t input_2[] = { E, F, G, H, M, N, O, P };
++uint16_t expected[] = { 0xDE62 /* (3.0f + (-A) * E) / 2.0f.  */,
++			0x5206 /* (3.0f + (-B) * F) / 2.0f.  */,
++			0xC7A0 /* (3.0f + (-C) * G) / 2.0f.  */,
++			0x5E0A /* (3.0f + (-D) * H) / 2.0f.  */,
++			0xCF3D /* (3.0f + (-I) * M) / 2.0f.  */,
++			0xEAB0 /* (3.0f + (-J) * N) / 2.0f.  */,
++			0x471F /* (3.0f + (-K) * O) / 2.0f.  */,
++			0xE893 /* (3.0f + (-L) * P) / 2.0f.  */ };
++
++#define TEST_MSG "VRSQRTSH_F16"
++#define INSN_NAME vrsqrtsh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
+@@ -76,16 +76,16 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+ 
+ #ifdef EXTRA_TESTS
+   EXTRA_TESTS();
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
+@@ -101,10 +101,8 @@ VECT_VAR_DECL(expected_negative_shift,uint,64,2) [] = { 0x7ffffffffffffff,
+ 							0x7ffffffffffffff };
+ 
+ 
+-#ifndef INSN_NAME
+ #define INSN_NAME vshl
+ #define TEST_MSG "VSHL/VSHLQ"
+-#endif
+ 
+ #define FNNAME1(NAME) exec_ ## NAME
+ #define FNNAME(NAME) FNNAME1(NAME)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
+@@ -53,9 +53,17 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VSHUFFLE(float, 32, 4)
+ 
+   DECL_ALL_VSHUFFLE();
++#if defined (FP16_SUPPORTED)
++  DECL_VSHUFFLE (float, 16, 4);
++  DECL_VSHUFFLE (float, 16, 8);
++#endif
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD (vector1, buffer, , float, f, 16, 4);
++  VLOAD (vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ 
+@@ -68,6 +76,9 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, , uint, u, 32, 2, 0x77);
+   VDUP(vector2, , poly, p, 8, 8, 0x55);
+   VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
+   VDUP(vector2, , float, f, 32, 2, 33.6f);
+ 
+   VDUP(vector2, q, int, s, 8, 16, 0x11);
+@@ -78,8 +89,11 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 32, 4, 0x77);
+   VDUP(vector2, q, poly, p, 8, 16, 0x55);
+   VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, 33.8f);
+-  
++
+ #define TEST_ALL_VSHUFFLE(INSN)				\
+   TEST_VSHUFFLE(INSN, , int, s, 8, 8);			\
+   TEST_VSHUFFLE(INSN, , int, s, 16, 4);			\
+@@ -100,6 +114,10 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VSHUFFLE(INSN, q, poly, p, 16, 8);		\
+   TEST_VSHUFFLE(INSN, q, float, f, 32, 4)
+ 
++#define TEST_VSHUFFLE_FP16(INSN)		\
++  TEST_VSHUFFLE(INSN, , float, f, 16, 4);	\
++  TEST_VSHUFFLE(INSN, q, float, f, 16, 8);
++
+ #define TEST_ALL_EXTRA_CHUNKS()			\
+   TEST_EXTRA_CHUNK(int, 8, 8, 1);		\
+   TEST_EXTRA_CHUNK(int, 16, 4, 1);		\
+@@ -130,8 +148,8 @@ void FNNAME (INSN_NAME) (void)
+     CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+ 									\
+     CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment);		\
+@@ -140,20 +158,40 @@ void FNNAME (INSN_NAME) (void)
+     CHECK(test_name, uint, 8, 16, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment);	\
+-  }									\
++  }
++
++#define CHECK_RESULTS_VSHUFFLE_FP16(test_name,EXPECTED,comment)		\
++  {									\
++    CHECK_FP (test_name, float, 16, 4, PRIx16, EXPECTED, comment);	\
++    CHECK_FP (test_name, float, 16, 8, PRIx16, EXPECTED, comment);	\
++  }
+ 
+   clean_results ();
+ 
+   /* Execute the tests.  */
+   TEST_ALL_VSHUFFLE(INSN_NAME);
++#if defined (FP16_SUPPORTED)
++  TEST_VSHUFFLE_FP16 (INSN_NAME);
++#endif
+ 
+   CHECK_RESULTS_VSHUFFLE (TEST_MSG, expected0, "(chunk 0)");
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS_VSHUFFLE_FP16 (TEST_MSG, expected0, "(chunk 0)");
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS();
++#if defined (FP16_SUPPORTED)
++  TEST_EXTRA_CHUNK (float, 16, 4, 1);
++  TEST_EXTRA_CHUNK (float, 16, 8, 1);
++#endif
++
+   CHECK_RESULTS_VSHUFFLE (TEST_MSG, expected1, "(chunk 1)");
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS_VSHUFFLE_FP16 (TEST_MSG, expected1, "(chunk 1)");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
+@@ -161,14 +161,16 @@ void vsli_extra(void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shift, COMMENT);
++  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
++  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c
+@@ -0,0 +1,72 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (123.4)
++#define B FP16_C (567.8)
++#define C FP16_C (34.8)
++#define D FP16_C (1024)
++#define E FP16_C (663.1)
++#define F FP16_C (144.0)
++#define G FP16_C (4.8)
++#define H FP16_C (77)
++
++#define SQRT_A 0x498E /* FP16_C (__builtin_sqrtf (123.4)).  */
++#define SQRT_B 0x4DF5 /* FP16_C (__builtin_sqrtf (567.8)).  */
++#define SQRT_C 0x45E6 /* FP16_C (__builtin_sqrtf (34.8)).  */
++#define SQRT_D 0x5000 /* FP16_C (__builtin_sqrtf (1024)).  */
++#define SQRT_E 0x4E70 /* FP16_C (__builtin_sqrtf (663.1)).  */
++#define SQRT_F 0x4A00 /* FP16_C (__builtin_sqrtf (144.0)).  */
++#define SQRT_G 0x4062 /* FP16_C (__builtin_sqrtf (4.8)).  */
++#define SQRT_H 0x4863 /* FP16_C (__builtin_sqrtf (77)).  */
++
++/* Expected results for vsqrt.  */
++VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
++  = { SQRT_A, SQRT_B, SQRT_C, SQRT_D };
++
++VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
++  = { SQRT_A, SQRT_B, SQRT_C, SQRT_D, SQRT_E, SQRT_F, SQRT_G, SQRT_H };
++
++void exec_vsqrt_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VSQRT (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A, B, C, D};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vsqrt_f16 (VECT_VAR (vsrc, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VSQRTQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A, B, C, D, E, F, G, H};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vsqrtq_f16 (VECT_VAR (vsrc, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
++}
++
++int
++main (void)
++{
++  exec_vsqrt_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x3da8 /* 1.414062 */,
++  0x3f0b /* 1.760742 */,
++  0x4479 /* 4.472656 */,
++  0x390f /* 0.632324 */,
++  0x7e00 /* nan */,
++  0x3c9d /* 1.153320 */,
++  0x7e00 /* nan */,
++  0x3874 /* 0.556641 */,
++  0x38a2 /* 0.579102 */,
++  0x39a8 /* 0.707031 */,
++  0x3c00 /* 1.000000 */,
++  0x433f /* 3.623047 */,
++  0x7e00 /* nan */,
++  0x4479 /* 4.472656 */,
++  0x7c00 /* inf */,
++  0x7e00 /* nan */
++};
++
++#define TEST_MSG "VSQRTH_F16"
++#define INSN_NAME vsqrth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
+@@ -163,14 +163,14 @@ void vsri_extra(void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
+ }
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst2_lane_f16 (float16_t * p, float16x4x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst2q_lane_f16 (float16_t * p, float16x8x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst3_lane_f16 (float16_t * p, float16x4x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst3q_lane_f16 (float16_t * p, float16x8x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst4_lane_f16 (float16_t * p, float16x4x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst4q_lane_f16 (float16_t * p, float16x8x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
+@@ -14,6 +14,7 @@ VECT_VAR_DECL(expected_st2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_st2_0,poly,8,8) [] = { 0xf0, 0xf1, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_st2_0,int,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -24,6 +25,8 @@ VECT_VAR_DECL(expected_st2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					       0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 						 0x0, 0x0 };
+ 
+@@ -39,6 +42,7 @@ VECT_VAR_DECL(expected_st2_1,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -48,6 +52,8 @@ VECT_VAR_DECL(expected_st2_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st2_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst3, chunk 0.  */
+@@ -62,6 +68,7 @@ VECT_VAR_DECL(expected_st3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_st3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0 };
++VECT_VAR_DECL(expected_st3_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_st3_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -73,6 +80,8 @@ VECT_VAR_DECL(expected_st3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					       0xfffffff2, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 						 0xc1600000, 0x0 };
+ 
+@@ -88,6 +97,7 @@ VECT_VAR_DECL(expected_st3_1,uint,32,2) [] = { 0xfffffff2, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,hfloat,32,2) [] = { 0xc1600000, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -97,6 +107,8 @@ VECT_VAR_DECL(expected_st3_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st3_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst3, chunk 2.  */
+@@ -111,6 +123,7 @@ VECT_VAR_DECL(expected_st3_2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -120,6 +133,8 @@ VECT_VAR_DECL(expected_st3_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st3_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst4, chunk 0.  */
+@@ -134,6 +149,7 @@ VECT_VAR_DECL(expected_st4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_st4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_st4_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ VECT_VAR_DECL(expected_st4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_st4_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -145,6 +161,8 @@ VECT_VAR_DECL(expected_st4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					       0xfffffff2, 0xfffffff3 };
+ VECT_VAR_DECL(expected_st4_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 						 0xc1600000, 0xc1500000 };
+ 
+@@ -160,6 +178,7 @@ VECT_VAR_DECL(expected_st4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+ VECT_VAR_DECL(expected_st4_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
+ VECT_VAR_DECL(expected_st4_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -169,6 +188,8 @@ VECT_VAR_DECL(expected_st4_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st4_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst4, chunk 2.  */
+@@ -183,6 +204,7 @@ VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -192,6 +214,8 @@ VECT_VAR_DECL(expected_st4_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st4_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++					       0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst4, chunk 3.  */
+@@ -206,6 +230,7 @@ VECT_VAR_DECL(expected_st4_3,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_3,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -215,6 +240,8 @@ VECT_VAR_DECL(expected_st4_3,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st4_3,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_3,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Declare additional input buffers as needed.  */
+@@ -229,6 +256,9 @@ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 32, 2);
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 64, 2);
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 8, 2);
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 16, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 16, 2);
++#endif
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 32, 2);
+ 
+ /* Input buffers for vld3_lane.  */
+@@ -242,6 +272,9 @@ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 32, 3);
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 64, 3);
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 8, 3);
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 16, 3);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 16, 3);
++#endif
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 32, 3);
+ 
+ /* Input buffers for vld4_lane.  */
+@@ -255,6 +288,9 @@ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 32, 4);
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 64, 4);
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 8, 4);
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 16, 4);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 16, 4);
++#endif
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 32, 4);
+ 
+ void exec_vstX_lane (void)
+@@ -302,7 +338,7 @@ void exec_vstX_lane (void)
+ 
+   /* We need all variants in 64 bits, but there is no 64x2 variant,
+      nor 128 bits vectors of int8/uint8/poly8.  */
+-#define DECL_ALL_VSTX_LANE(X)			\
++#define DECL_ALL_VSTX_LANE_NO_FP16(X)		\
+   DECL_VSTX_LANE(int, 8, 8, X);			\
+   DECL_VSTX_LANE(int, 16, 4, X);		\
+   DECL_VSTX_LANE(int, 32, 2, X);		\
+@@ -319,11 +355,20 @@ void exec_vstX_lane (void)
+   DECL_VSTX_LANE(poly, 16, 8, X);		\
+   DECL_VSTX_LANE(float, 32, 4, X)
+ 
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++#define DECL_ALL_VSTX_LANE(X)		\
++  DECL_ALL_VSTX_LANE_NO_FP16(X);	\
++  DECL_VSTX_LANE(float, 16, 4, X);	\
++  DECL_VSTX_LANE(float, 16, 8, X)
++#else
++#define DECL_ALL_VSTX_LANE(X) DECL_ALL_VSTX_LANE_NO_FP16(X)
++#endif
++
+ #define DUMMY_ARRAY(V, T, W, N, L) VECT_VAR_DECL(V,T,W,N)[N*L]
+ 
+   /* Use the same lanes regardless of the size of the array (X), for
+      simplicity.  */
+-#define TEST_ALL_VSTX_LANE(X)			\
++#define TEST_ALL_VSTX_LANE_NO_FP16(X)		\
+   TEST_VSTX_LANE(, int, s, 8, 8, X, 7);		\
+   TEST_VSTX_LANE(, int, s, 16, 4, X, 2);	\
+   TEST_VSTX_LANE(, int, s, 32, 2, X, 0);	\
+@@ -340,7 +385,16 @@ void exec_vstX_lane (void)
+   TEST_VSTX_LANE(q, poly, p, 16, 8, X, 5);	\
+   TEST_VSTX_LANE(q, float, f, 32, 4, X, 2)
+ 
+-#define TEST_ALL_EXTRA_CHUNKS(X, Y)		\
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++#define TEST_ALL_VSTX_LANE(X)			\
++  TEST_ALL_VSTX_LANE_NO_FP16(X);		\
++  TEST_VSTX_LANE(, float, f, 16, 4, X, 2);	\
++  TEST_VSTX_LANE(q, float, f, 16, 8, X, 6)
++#else
++#define TEST_ALL_VSTX_LANE(X) TEST_ALL_VSTX_LANE_NO_FP16(X)
++#endif
++
++#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)	\
+   TEST_EXTRA_CHUNK(int, 8, 8, X, Y);		\
+   TEST_EXTRA_CHUNK(int, 16, 4, X, Y);		\
+   TEST_EXTRA_CHUNK(int, 32, 2, X, Y);		\
+@@ -357,6 +411,15 @@ void exec_vstX_lane (void)
+   TEST_EXTRA_CHUNK(poly, 16, 8, X, Y);		\
+   TEST_EXTRA_CHUNK(float, 32, 4, X, Y)
+ 
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++#define TEST_ALL_EXTRA_CHUNKS(X,Y)		\
++  TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y);		\
++  TEST_EXTRA_CHUNK(float, 16, 4, X, Y);		\
++  TEST_EXTRA_CHUNK(float, 16, 8, X, Y)
++#else
++#define TEST_ALL_EXTRA_CHUNKS(X,Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)
++#endif
++
+   /* Declare the temporary buffers / variables.  */
+   DECL_ALL_VSTX_LANE(2);
+   DECL_ALL_VSTX_LANE(3);
+@@ -371,12 +434,18 @@ void exec_vstX_lane (void)
+   DUMMY_ARRAY(buffer_src, uint, 32, 2, 4);
+   DUMMY_ARRAY(buffer_src, poly, 8, 8, 4);
+   DUMMY_ARRAY(buffer_src, poly, 16, 4, 4);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  DUMMY_ARRAY(buffer_src, float, 16, 4, 4);
++#endif
+   DUMMY_ARRAY(buffer_src, float, 32, 2, 4);
+   DUMMY_ARRAY(buffer_src, int, 16, 8, 4);
+   DUMMY_ARRAY(buffer_src, int, 32, 4, 4);
+   DUMMY_ARRAY(buffer_src, uint, 16, 8, 4);
+   DUMMY_ARRAY(buffer_src, uint, 32, 4, 4);
+   DUMMY_ARRAY(buffer_src, poly, 16, 8, 4);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  DUMMY_ARRAY(buffer_src, float, 16, 8, 4);
++#endif
+   DUMMY_ARRAY(buffer_src, float, 32, 4, 4);
+ 
+   /* Check vst2_lane/vst2q_lane.  */
+@@ -391,15 +460,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st2_0, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st2_0, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st2_0, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_0, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_0, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_0, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(2, 1);
+ #undef CMT
+@@ -410,15 +483,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st2_1, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st2_1, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st2_1, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_1, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_1, CMT);
++#endif
+ 
+ 
+   /* Check vst3_lane/vst3q_lane.  */
+@@ -435,15 +512,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_0, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_0, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_0, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_0, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_0, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_0, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(3, 1);
+ 
+@@ -455,15 +536,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_1, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_1, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_1, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_1, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_1, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(3, 2);
+ 
+@@ -475,15 +560,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_2, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_2, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_2, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_2, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_2, CMT);
++#endif
+ 
+ 
+   /* Check vst4_lane/vst4q_lane.  */
+@@ -500,15 +589,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_0, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_0, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_0, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_0, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_0, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_0, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(4, 1);
+ 
+@@ -520,15 +613,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_1, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_1, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_1, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_1, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_1, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(4, 2);
+ 
+@@ -540,15 +637,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_2, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_2, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_2, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(4, 3);
+ 
+@@ -560,15 +661,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_3, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_3, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_3, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_3, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_3, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_3, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_3, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_3, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_3, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_3, CMT);
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c
+@@ -44,6 +44,14 @@ VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffed,
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc00ccccd, 0xc00ccccd };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc00ccccc, 0xc00ccccc,
+ 						   0xc00ccccc, 0xc00ccccc };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0xc066, 0xc066,
++						      0xc066, 0xc066 };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0xc067, 0xc067,
++						      0xc067, 0xc067,
++						      0xc067, 0xc067,
++						      0xc067, 0xc067 };
++#endif
+ 
+ void exec_vsub_f32(void)
+ {
+@@ -67,4 +75,27 @@ void exec_vsub_f32(void)
+ 
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++
++  VDUP(vector, , float, f, 16, 4, 2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++
++  VDUP(vector2, , float, f, 16, 4, 4.5f);
++  VDUP(vector2, q, float, f, 16, 8, 5.6f);
++
++  TEST_BINARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0xbc00 /* -1.000000 */,
++  0xbc00 /* -1.000000 */,
++  0x4654 /* 6.328125 */,
++  0xd60e /* -96.875000 */,
++  0xc900 /* -10.000000 */,
++  0x36b8 /* 0.419922 */,
++  0xc19a /* -2.800781 */,
++  0x4848 /* 8.562500 */,
++  0xbd34 /* -1.300781 */,
++  0xccec /* -19.687500 */,
++  0x4791 /* 7.566406 */,
++  0xbf34 /* -1.800781 */,
++  0x484d /* 8.601562 */,
++  0x4804 /* 8.031250 */,
++  0xc69c /* -6.609375 */,
++  0x4ceb /* 19.671875 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VSUB_F16"
++#define INSN_NAME vsubh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
+@@ -167,7 +167,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl1, "");
+ 
+   /* Check vtbl2.  */
+   clean_results ();
+@@ -177,7 +177,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl2, "");
+ 
+   /* Check vtbl3.  */
+   clean_results ();
+@@ -187,7 +187,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl3, "");
+ 
+   /* Check vtbl4.  */
+   clean_results ();
+@@ -197,7 +197,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl4, "");
+ 
+ 
+   /* Now test VTBX.  */
+@@ -249,7 +249,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx1, "");
+ 
+   /* Check vtbx2.  */
+   clean_results ();
+@@ -259,7 +259,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx2, "");
+ 
+   /* Check vtbx3.  */
+   clean_results ();
+@@ -269,7 +269,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx3, "");
+ 
+   /* Check vtbx4.  */
+   clean_results ();
+@@ -279,7 +279,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx4, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
+@@ -15,6 +15,10 @@ VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 					 0xf2, 0xf3, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11,
+ 					 0xf2, 0xf3, 0x11, 0x11,
+@@ -36,6 +40,12 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 					  0xf6, 0xf7, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
+ 					  0xfff2, 0xfff3, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++						0x4b4d, 0x4b4d,
++						0xcb00, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 					    0x42073333, 0x42073333 };
+ 
+@@ -51,6 +61,10 @@ VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
+ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
+ 					 0xf6, 0xf7, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0xcb00, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf8, 0xf9, 0x11, 0x11,
+ 					 0xfa, 0xfb, 0x11, 0x11,
+@@ -72,6 +86,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
+ 					  0xfe, 0xff, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
+ 					  0xfff6, 0xfff7, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0xca00, 0xc980,
++						0x4b4d, 0x4b4d,
++						0xc900, 0xc880,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1600000, 0xc1500000,
+ 					    0x42073333, 0x42073333 };
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
+@@ -0,0 +1,263 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x11, 0xf2, 0x11,
++				       0xf4, 0x11, 0xf6, 0x11 };
++VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0x22, 0xfff2, 0x22 };
++VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
++VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					0xf4, 0x55, 0xf6, 0x55 };
++VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
++VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
++VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					0xf4, 0x55, 0xf6, 0x55 };
++VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
++VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0x4b4d,
++					       0xcb00, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0x11, 0xf2, 0x11,
++					0xf4, 0x11, 0xf6, 0x11,
++					0xf8, 0x11, 0xfa, 0x11,
++					0xfc, 0x11, 0xfe, 0x11 };
++VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0x22, 0xfff2, 0x22,
++					0xfff4, 0x22, 0xfff6, 0x22 };
++VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0x33,
++					0xfffffff2, 0x33 };
++VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
++					0x44 };
++VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					 0xf4, 0x55, 0xf6, 0x55,
++					 0xf8, 0x55, 0xfa, 0x55,
++					 0xfc, 0x55, 0xfe, 0x55 };
++VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
++					 0xfff4, 0x66, 0xfff6, 0x66 };
++VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0x77,
++					 0xfffffff2, 0x77 };
++VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
++					 0x88 };
++VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					 0xf4, 0x55, 0xf6, 0x55,
++					 0xf8, 0x55, 0xfa, 0x55,
++					 0xfc, 0x55, 0xfe, 0x55 };
++VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
++					 0xfff4, 0x66, 0xfff6, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0x4b4d,
++					       0xcb00, 0x4b4d,
++					       0xca00, 0x4b4d,
++					       0xc900, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0x42073333,
++					   0xc1600000, 0x42073333 };
++
++#define TEST_MSG "VTRN1"
++void exec_vtrn_half (void)
++{
++#define TEST_VTRN(PART, Q, T1, T2, W, N)		\
++  VECT_VAR(vector_res, T1, W, N) =			\
++    vtrn##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
++		       VECT_VAR(vector2, T1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_VTRN1(Q, T1, T2, W, N) TEST_VTRN(1, Q, T1, T2, W, N)
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector2);
++  DECL_VARIABLE(vector, float, 64, 2);
++  DECL_VARIABLE(vector2, float, 64, 2);
++
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++  DECL_VARIABLE(vector_res, float, 64, 2);
++
++  clean_results ();
++  /* We don't have vtrn1_T64x1, so set expected to the clean value.  */
++  CLEAN(expected, int, 64, 1);
++  CLEAN(expected, uint, 64, 1);
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++  VLOAD(vector, buffer, q, float, f, 64, 2);
++
++  /* Choose arbitrary initialization values.  */
++  VDUP(vector2, , int, s, 8, 8, 0x11);
++  VDUP(vector2, , int, s, 16, 4, 0x22);
++  VDUP(vector2, , int, s, 32, 2, 0x33);
++  VDUP(vector2, , uint, u, 8, 8, 0x55);
++  VDUP(vector2, , uint, u, 16, 4, 0x66);
++  VDUP(vector2, , uint, u, 32, 2, 0x77);
++  VDUP(vector2, , poly, p, 8, 8, 0x55);
++  VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
++  VDUP(vector2, , float, f, 32, 2, 33.6f);
++
++  VDUP(vector2, q, int, s, 8, 16, 0x11);
++  VDUP(vector2, q, int, s, 16, 8, 0x22);
++  VDUP(vector2, q, int, s, 32, 4, 0x33);
++  VDUP(vector2, q, int, s, 64, 2, 0x44);
++  VDUP(vector2, q, uint, u, 8, 16, 0x55);
++  VDUP(vector2, q, uint, u, 16, 8, 0x66);
++  VDUP(vector2, q, uint, u, 32, 4, 0x77);
++  VDUP(vector2, q, uint, u, 64, 2, 0x88);
++  VDUP(vector2, q, poly, p, 8, 16, 0x55);
++  VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
++  VDUP(vector2, q, float, f, 32, 4, 33.8f);
++  VDUP(vector2, q, float, f, 64, 2, 33.8f);
++
++  TEST_VTRN1(, int, s, 8, 8);
++  TEST_VTRN1(, int, s, 16, 4);
++  TEST_VTRN1(, int, s, 32, 2);
++  TEST_VTRN1(, uint, u, 8, 8);
++  TEST_VTRN1(, uint, u, 16, 4);
++  TEST_VTRN1(, uint, u, 32, 2);
++  TEST_VTRN1(, poly, p, 8, 8);
++  TEST_VTRN1(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN1(, float, f, 16, 4);
++#endif
++  TEST_VTRN1(, float, f, 32, 2);
++
++  TEST_VTRN1(q, int, s, 8, 16);
++  TEST_VTRN1(q, int, s, 16, 8);
++  TEST_VTRN1(q, int, s, 32, 4);
++  TEST_VTRN1(q, int, s, 64, 2);
++  TEST_VTRN1(q, uint, u, 8, 16);
++  TEST_VTRN1(q, uint, u, 16, 8);
++  TEST_VTRN1(q, uint, u, 32, 4);
++  TEST_VTRN1(q, uint, u, 64, 2);
++  TEST_VTRN1(q, poly, p, 8, 16);
++  TEST_VTRN1(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN1(q, float, f, 16, 8);
++#endif
++  TEST_VTRN1(q, float, f, 32, 4);
++  TEST_VTRN1(q, float, f, 64, 2);
++
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
++  CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#undef TEST_MSG
++#define TEST_MSG "VTRN2"
++
++#define TEST_VTRN2(Q, T1, T2, W, N) TEST_VTRN(2, Q, T1, T2, W, N)
++
++/* Expected results.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0x11, 0xf3, 0x11,
++					0xf5, 0x11, 0xf7, 0x11 };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff1, 0x22, 0xfff3, 0x22 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					 0xf5, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					 0xf5, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0x4b4d,
++						0xca80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0x11, 0xf3, 0x11,
++					 0xf5, 0x11, 0xf7, 0x11,
++					 0xf9, 0x11, 0xfb, 0x11,
++					 0xfd, 0x11, 0xff, 0x11 };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff1, 0x22, 0xfff3, 0x22,
++					 0xfff5, 0x22, 0xfff7, 0x22 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0x33,
++					 0xfffffff3, 0x33 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
++					 0x44 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					  0xf5, 0x55, 0xf7, 0x55,
++					  0xf9, 0x55, 0xfb, 0x55,
++					  0xfd, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
++					  0xfff5, 0x66, 0xfff7, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0x77,
++					  0xfffffff3, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
++					  0x88 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					  0xf5, 0x55, 0xf7, 0x55,
++					  0xf9, 0x55, 0xfb, 0x55,
++					  0xfd, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
++					  0xfff5, 0x66, 0xfff7, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb80, 0x4b4d,
++						0xca80, 0x4b4d,
++						0xc980, 0x4b4d,
++						0xc880, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0x42073333,
++					    0xc1500000, 0x42073333 };
++  clean_results ();
++  CLEAN(expected2, int, 64, 1);
++  CLEAN(expected2, uint, 64, 1);
++
++  TEST_VTRN2(, int, s, 8, 8);
++  TEST_VTRN2(, int, s, 16, 4);
++  TEST_VTRN2(, int, s, 32, 2);
++  TEST_VTRN2(, uint, u, 8, 8);
++  TEST_VTRN2(, uint, u, 16, 4);
++  TEST_VTRN2(, uint, u, 32, 2);
++  TEST_VTRN2(, poly, p, 8, 8);
++  TEST_VTRN2(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN2(, float, f, 16, 4);
++#endif
++  TEST_VTRN2(, float, f, 32, 2);
++
++  TEST_VTRN2(q, int, s, 8, 16);
++  TEST_VTRN2(q, int, s, 16, 8);
++  TEST_VTRN2(q, int, s, 32, 4);
++  TEST_VTRN2(q, int, s, 64, 2);
++  TEST_VTRN2(q, uint, u, 8, 16);
++  TEST_VTRN2(q, uint, u, 16, 8);
++  TEST_VTRN2(q, uint, u, 32, 4);
++  TEST_VTRN2(q, uint, u, 64, 2);
++  TEST_VTRN2(q, poly, p, 8, 16);
++  TEST_VTRN2(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN2(q, float, f, 16, 8);
++#endif
++  TEST_VTRN2(q, float, f, 32, 4);
++  TEST_VTRN2(q, float, f, 64, 2);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++}
++
++int main (void)
++{
++  exec_vtrn_half ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
+@@ -32,10 +32,21 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
+ VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
+ 						  0x0, 0xffffffff };
+ 
+-#ifndef INSN_NAME
++/* Expected results with poly input.  */
++VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
++					     0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
++					      0xff, 0xff, 0xff, 0xff,
++					      0xff, 0xff, 0xff, 0xff,
++					      0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_poly,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
++VECT_VAR_DECL(expected_poly,uint,16,8) [] = { 0x0, 0xffff,
++					      0x0, 0xffff,
++					      0xffff, 0xffff,
++					      0xffff, 0xffff };
++
+ #define INSN_NAME vtst
+ #define TEST_MSG "VTST/VTSTQ"
+-#endif
+ 
+ /* We can't use the standard ref_v_binary_op.c template because vtst
+    has no 64 bits variant, and outputs are always of uint type.  */
+@@ -73,12 +84,16 @@ FNNAME (INSN_NAME)
+   VDUP(vector2, , uint, u, 8, 8, 15);
+   VDUP(vector2, , uint, u, 16, 4, 5);
+   VDUP(vector2, , uint, u, 32, 2, 1);
++  VDUP(vector2, , poly, p, 8, 8, 15);
++  VDUP(vector2, , poly, p, 16, 4, 5);
+   VDUP(vector2, q, int, s, 8, 16, 15);
+   VDUP(vector2, q, int, s, 16, 8, 5);
+   VDUP(vector2, q, int, s, 32, 4, 1);
+   VDUP(vector2, q, uint, u, 8, 16, 15);
+   VDUP(vector2, q, uint, u, 16, 8, 5);
+   VDUP(vector2, q, uint, u, 32, 4, 1);
++  VDUP(vector2, q, poly, p, 8, 16, 15);
++  VDUP(vector2, q, poly, p, 16, 8, 5);
+ 
+ #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)	\
+   MACRO(VAR, , T1, T2, 8, 8);					\
+@@ -111,6 +126,18 @@ FNNAME (INSN_NAME)
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
++
++  /* Now, test the variants with poly8 and poly16 as input.  */
++#undef CMT
++#define CMT " (poly input)"
++  TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8);
++  TEST_BINARY_OP(INSN_NAME, , poly, p, 16, 4);
++  TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16);
++  TEST_BINARY_OP(INSN_NAME, q, poly, p, 16, 8);
++  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT);
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_poly, CMT);
++  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT);
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_poly, CMT);
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
+@@ -19,6 +19,10 @@ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					 0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1,
+ 					  0xfff2, 0xfff3 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++						0xcb00, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					 0xf4, 0xf5, 0xf6, 0xf7,
+@@ -48,6 +52,12 @@ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1,
+ 					  0xfff2, 0xfff3,
+ 					  0xfff4, 0xfff5,
+ 					  0xfff6, 0xfff7 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++						0xcb00, 0xca80,
++						0xca00, 0xc980,
++						0xc900, 0xc880 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 					    0xc1600000, 0xc1500000 };
+ 
+@@ -63,6 +73,10 @@ VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
+ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0x55, 0x55, 0x55, 0x55,
+ 					 0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0x11, 0x11, 0x11, 0x11,
+ 					 0x11, 0x11, 0x11, 0x11,
+@@ -84,6 +98,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0x55, 0x55, 0x55, 0x55,
+ 					  0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0x66, 0x66, 0x66, 0x66,
+ 					  0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0x42073333, 0x42073333,
+ 					    0x42073333, 0x42073333 };
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
+@@ -0,0 +1,259 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++				       0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0x22, 0x22 };
++VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
++VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0x66, 0x66 };
++VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
++VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff2, 0x66, 0x66 };
++VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb00,
++					       0x4b4d, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					0xf8, 0xfa, 0xfc, 0xfe,
++					0x11, 0x11, 0x11, 0x11,
++					0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
++					0x22, 0x22, 0x22, 0x22 };
++VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff2,
++					0x33, 0x33 };
++VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
++					0x44 };
++VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					 0xf8, 0xfa, 0xfc, 0xfe,
++					 0x55, 0x55, 0x55, 0x55,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
++					 0x66, 0x66, 0x66, 0x66 };
++VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff2, 0x77, 0x77 };
++VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
++					 0x88 };
++VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					 0xf8, 0xfa, 0xfc, 0xfe,
++					 0x55, 0x55, 0x55, 0x55,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
++					 0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb00, 0xca00, 0xc900,
++					       0x4b4d, 0x4b4d, 0x4b4d, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1600000,
++					   0x42073333, 0x42073333 };
++
++#define TEST_MSG "VUZP1"
++void exec_vuzp_half (void)
++{
++#define TEST_VUZP(PART, Q, T1, T2, W, N)		\
++  VECT_VAR(vector_res, T1, W, N) =			\
++    vuzp##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
++		       VECT_VAR(vector2, T1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_VUZP1(Q, T1, T2, W, N) TEST_VUZP(1, Q, T1, T2, W, N)
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector2);
++  DECL_VARIABLE(vector, float, 64, 2);
++  DECL_VARIABLE(vector2, float, 64, 2);
++
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++  DECL_VARIABLE(vector_res, float, 64, 2);
++
++  clean_results ();
++  /* We don't have vuzp1_T64x1, so set expected to the clean value.  */
++  CLEAN(expected, int, 64, 1);
++  CLEAN(expected, uint, 64, 1);
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++  VLOAD(vector, buffer, q, float, f, 64, 2);
++
++  /* Choose arbitrary initialization values.  */
++  VDUP(vector2, , int, s, 8, 8, 0x11);
++  VDUP(vector2, , int, s, 16, 4, 0x22);
++  VDUP(vector2, , int, s, 32, 2, 0x33);
++  VDUP(vector2, , uint, u, 8, 8, 0x55);
++  VDUP(vector2, , uint, u, 16, 4, 0x66);
++  VDUP(vector2, , uint, u, 32, 2, 0x77);
++  VDUP(vector2, , poly, p, 8, 8, 0x55);
++  VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
++  VDUP(vector2, , float, f, 32, 2, 33.6f);
++
++  VDUP(vector2, q, int, s, 8, 16, 0x11);
++  VDUP(vector2, q, int, s, 16, 8, 0x22);
++  VDUP(vector2, q, int, s, 32, 4, 0x33);
++  VDUP(vector2, q, int, s, 64, 2, 0x44);
++  VDUP(vector2, q, uint, u, 8, 16, 0x55);
++  VDUP(vector2, q, uint, u, 16, 8, 0x66);
++  VDUP(vector2, q, uint, u, 32, 4, 0x77);
++  VDUP(vector2, q, uint, u, 64, 2, 0x88);
++  VDUP(vector2, q, poly, p, 8, 16, 0x55);
++  VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
++  VDUP(vector2, q, float, f, 32, 4, 33.8f);
++  VDUP(vector2, q, float, f, 64, 2, 33.8f);
++
++  TEST_VUZP1(, int, s, 8, 8);
++  TEST_VUZP1(, int, s, 16, 4);
++  TEST_VUZP1(, int, s, 32, 2);
++  TEST_VUZP1(, uint, u, 8, 8);
++  TEST_VUZP1(, uint, u, 16, 4);
++  TEST_VUZP1(, uint, u, 32, 2);
++  TEST_VUZP1(, poly, p, 8, 8);
++  TEST_VUZP1(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP1(, float, f, 16, 4);
++#endif
++  TEST_VUZP1(, float, f, 32, 2);
++
++  TEST_VUZP1(q, int, s, 8, 16);
++  TEST_VUZP1(q, int, s, 16, 8);
++  TEST_VUZP1(q, int, s, 32, 4);
++  TEST_VUZP1(q, int, s, 64, 2);
++  TEST_VUZP1(q, uint, u, 8, 16);
++  TEST_VUZP1(q, uint, u, 16, 8);
++  TEST_VUZP1(q, uint, u, 32, 4);
++  TEST_VUZP1(q, uint, u, 64, 2);
++  TEST_VUZP1(q, poly, p, 8, 16);
++  TEST_VUZP1(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP1(q, float, f, 16, 8);
++#endif
++  TEST_VUZP1(q, float, f, 32, 4);
++  TEST_VUZP1(q, float, f, 64, 2);
++
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
++  CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#undef TEST_MSG
++#define TEST_MSG "VUZP2"
++
++#define TEST_VUZP2(Q, T1, T2, W, N) TEST_VUZP(2, Q, T1, T2, W, N)
++
++/* Expected results.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff1, 0xfff3, 0x22, 0x22 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff1, 0xfff3, 0x66, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff1, 0xfff3, 0x66, 0x66 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					 0xf9, 0xfb, 0xfd, 0xff,
++					 0x11, 0x11, 0x11, 0x11,
++					 0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
++					 0x22, 0x22, 0x22, 0x22 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff3,
++					 0x33, 0x33 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
++					 0x44 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					  0xf9, 0xfb, 0xfd, 0xff,
++					  0x55, 0x55, 0x55, 0x55,
++					  0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
++					  0x66, 0x66, 0x66, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0xfffffff3, 0x77, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
++					  0x88 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					  0xf9, 0xfb, 0xfd, 0xff,
++					  0x55, 0x55, 0x55, 0x55,
++					  0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
++					  0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb80, 0xca80, 0xc980, 0xc880,
++						0x4b4d, 0x4b4d, 0x4b4d, 0x4b4d
++					      };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
++					    0x42073333, 0x42073333 };
++
++  clean_results ();
++  CLEAN(expected2, int, 64, 1);
++  CLEAN(expected2, uint, 64, 1);
++
++  TEST_VUZP2(, int, s, 8, 8);
++  TEST_VUZP2(, int, s, 16, 4);
++  TEST_VUZP2(, int, s, 32, 2);
++  TEST_VUZP2(, uint, u, 8, 8);
++  TEST_VUZP2(, uint, u, 16, 4);
++  TEST_VUZP2(, uint, u, 32, 2);
++  TEST_VUZP2(, poly, p, 8, 8);
++  TEST_VUZP2(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP2(, float, f, 16, 4);
++#endif
++  TEST_VUZP2(, float, f, 32, 2);
++
++  TEST_VUZP2(q, int, s, 8, 16);
++  TEST_VUZP2(q, int, s, 16, 8);
++  TEST_VUZP2(q, int, s, 32, 4);
++  TEST_VUZP2(q, int, s, 64, 2);
++  TEST_VUZP2(q, uint, u, 8, 16);
++  TEST_VUZP2(q, uint, u, 16, 8);
++  TEST_VUZP2(q, uint, u, 32, 4);
++  TEST_VUZP2(q, uint, u, 64, 2);
++  TEST_VUZP2(q, poly, p, 8, 16);
++  TEST_VUZP2(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP2(q, float, f, 16, 8);
++#endif
++  TEST_VUZP2(q, float, f, 32, 4);
++  TEST_VUZP2(q, float, f, 64, 2);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++}
++
++int main (void)
++{
++  exec_vuzp_half ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
+@@ -18,6 +18,10 @@ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55,
+ 					 0xf1, 0xf5, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2,
+ 					  0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11,
+ 					 0xf1, 0xf9, 0x11, 0x11,
+@@ -41,6 +45,12 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf8, 0x55, 0x55,
+ 					  0xf3, 0xfb, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff4, 0x66, 0x66,
+ 					  0xfff1, 0xfff5, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xca00,
++						0x4b4d, 0x4b4d,
++						0xcb80, 0xc980,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1600000,
+ 					    0x42073333, 0x42073333 };
+ 
+@@ -59,6 +69,10 @@ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf2, 0xf6, 0x55, 0x55,
+ 					 0xf3, 0xf7, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff3,
+ 					  0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0xcb80, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf4, 0xfc, 0x11, 0x11,
+ 					 0xf5, 0xfd, 0x11, 0x11,
+@@ -82,6 +96,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf4, 0xfc, 0x55, 0x55,
+ 					  0xf7, 0xff, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff2, 0xfff6, 0x66, 0x66,
+ 					  0xfff3, 0xfff7, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0xcb00, 0xc900,
++						0x4b4d, 0x4b4d,
++						0xca80, 0xc880,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
+ 					    0x42073333, 0x42073333 };
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
+@@ -0,0 +1,263 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x11, 0xf1, 0x11,
++				       0xf2, 0x11, 0xf3, 0x11 };
++VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0x22, 0xfff1, 0x22 };
++VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
++VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					0xf2, 0x55, 0xf3, 0x55 };
++VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0x66, 0xfff1, 0x66 };
++VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
++VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					0xf2, 0x55, 0xf3, 0x55 };
++VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0x66, 0xfff1, 0x66 };
++VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0x4b4d,
++					       0xcb80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0x11, 0xf1, 0x11,
++					0xf2, 0x11, 0xf3, 0x11,
++					0xf4, 0x11, 0xf5, 0x11,
++					0xf6, 0x11, 0xf7, 0x11 };
++VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0x22, 0xfff1, 0x22,
++					0xfff2, 0x22, 0xfff3, 0x22 };
++VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0x33,
++					0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
++					0x44 };
++VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					 0xf2, 0x55, 0xf3, 0x55,
++					 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0x66, 0xfff1, 0x66,
++					 0xfff2, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0x77,
++					 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
++					 0x88 };
++VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					 0xf2, 0x55, 0xf3, 0x55,
++					 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0x66, 0xfff1, 0x66,
++					 0xfff2, 0x66, 0xfff3, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0x4b4d,
++					       0xcb80, 0x4b4d,
++					       0xcb00, 0x4b4d,
++					       0xca80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0x42073333,
++					   0xc1700000, 0x42073333 };
++
++#define TEST_MSG "VZIP1"
++void exec_vzip_half (void)
++{
++#define TEST_VZIP(PART, Q, T1, T2, W, N)		\
++  VECT_VAR(vector_res, T1, W, N) =			\
++    vzip##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
++		       VECT_VAR(vector2, T1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_VZIP1(Q, T1, T2, W, N) TEST_VZIP(1, Q, T1, T2, W, N)
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector2);
++  DECL_VARIABLE(vector, float, 64, 2);
++  DECL_VARIABLE(vector2, float, 64, 2);
++
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++  DECL_VARIABLE(vector_res, float, 64, 2);
++
++  clean_results ();
++  /* We don't have vzip1_T64x1, so set expected to the clean value.  */
++  CLEAN(expected, int, 64, 1);
++  CLEAN(expected, uint, 64, 1);
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++  VLOAD(vector, buffer, q, float, f, 64, 2);
++
++  /* Choose arbitrary initialization values.  */
++  VDUP(vector2, , int, s, 8, 8, 0x11);
++  VDUP(vector2, , int, s, 16, 4, 0x22);
++  VDUP(vector2, , int, s, 32, 2, 0x33);
++  VDUP(vector2, , uint, u, 8, 8, 0x55);
++  VDUP(vector2, , uint, u, 16, 4, 0x66);
++  VDUP(vector2, , uint, u, 32, 2, 0x77);
++  VDUP(vector2, , poly, p, 8, 8, 0x55);
++  VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
++  VDUP(vector2, , float, f, 32, 2, 33.6f);
++
++  VDUP(vector2, q, int, s, 8, 16, 0x11);
++  VDUP(vector2, q, int, s, 16, 8, 0x22);
++  VDUP(vector2, q, int, s, 32, 4, 0x33);
++  VDUP(vector2, q, int, s, 64, 2, 0x44);
++  VDUP(vector2, q, uint, u, 8, 16, 0x55);
++  VDUP(vector2, q, uint, u, 16, 8, 0x66);
++  VDUP(vector2, q, uint, u, 32, 4, 0x77);
++  VDUP(vector2, q, uint, u, 64, 2, 0x88);
++  VDUP(vector2, q, poly, p, 8, 16, 0x55);
++  VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
++  VDUP(vector2, q, float, f, 32, 4, 33.8f);
++  VDUP(vector2, q, float, f, 64, 2, 33.8f);
++
++  TEST_VZIP1(, int, s, 8, 8);
++  TEST_VZIP1(, int, s, 16, 4);
++  TEST_VZIP1(, int, s, 32, 2);
++  TEST_VZIP1(, uint, u, 8, 8);
++  TEST_VZIP1(, uint, u, 16, 4);
++  TEST_VZIP1(, uint, u, 32, 2);
++  TEST_VZIP1(, poly, p, 8, 8);
++  TEST_VZIP1(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP1(, float, f, 16, 4);
++#endif
++  TEST_VZIP1(, float, f, 32, 2);
++
++  TEST_VZIP1(q, int, s, 8, 16);
++  TEST_VZIP1(q, int, s, 16, 8);
++  TEST_VZIP1(q, int, s, 32, 4);
++  TEST_VZIP1(q, int, s, 64, 2);
++  TEST_VZIP1(q, uint, u, 8, 16);
++  TEST_VZIP1(q, uint, u, 16, 8);
++  TEST_VZIP1(q, uint, u, 32, 4);
++  TEST_VZIP1(q, uint, u, 64, 2);
++  TEST_VZIP1(q, poly, p, 8, 16);
++  TEST_VZIP1(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP1(q, float, f, 16, 8);
++#endif
++  TEST_VZIP1(q, float, f, 32, 4);
++  TEST_VZIP1(q, float, f, 64, 2);
++
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
++  CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#undef TEST_MSG
++#define TEST_MSG "VZIP2"
++
++#define TEST_VZIP2(Q, T1, T2, W, N) TEST_VZIP(2, Q, T1, T2, W, N)
++
++/* Expected results.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf4, 0x11, 0xf5, 0x11,
++					0xf6, 0x11, 0xf7, 0x11 };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff2, 0x22, 0xfff3, 0x22 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff2, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff2, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0x4b4d,
++						0xca80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf8, 0x11, 0xf9, 0x11,
++					 0xfa, 0x11, 0xfb, 0x11,
++					 0xfc, 0x11, 0xfd, 0x11,
++					 0xfe, 0x11, 0xff, 0x11 };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff4, 0x22, 0xfff5, 0x22,
++					 0xfff6, 0x22, 0xfff7, 0x22 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff2, 0x33,
++					 0xfffffff3, 0x33 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
++					 0x44 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf8, 0x55, 0xf9, 0x55,
++					  0xfa, 0x55, 0xfb, 0x55,
++					  0xfc, 0x55, 0xfd, 0x55,
++					  0xfe, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff4, 0x66, 0xfff5, 0x66,
++					  0xfff6, 0x66, 0xfff7, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff2, 0x77,
++					  0xfffffff3, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
++					  0x88 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf8, 0x55, 0xf9, 0x55,
++					  0xfa, 0x55, 0xfb, 0x55,
++					  0xfc, 0x55, 0xfd, 0x55,
++					  0xfe, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff4, 0x66, 0xfff5, 0x66,
++					  0xfff6, 0x66, 0xfff7, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xca00, 0x4b4d,
++						0xc980, 0x4b4d,
++						0xc900, 0x4b4d,
++						0xc880, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1600000, 0x42073333,
++					    0xc1500000, 0x42073333 };
++  clean_results ();
++  CLEAN(expected2, int, 64, 1);
++  CLEAN(expected2, uint, 64, 1);
++
++  TEST_VZIP2(, int, s, 8, 8);
++  TEST_VZIP2(, int, s, 16, 4);
++  TEST_VZIP2(, int, s, 32, 2);
++  TEST_VZIP2(, uint, u, 8, 8);
++  TEST_VZIP2(, uint, u, 16, 4);
++  TEST_VZIP2(, uint, u, 32, 2);
++  TEST_VZIP2(, poly, p, 8, 8);
++  TEST_VZIP2(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP2(, float, f, 16, 4);
++#endif
++  TEST_VZIP2(, float, f, 32, 2);
++
++  TEST_VZIP2(q, int, s, 8, 16);
++  TEST_VZIP2(q, int, s, 16, 8);
++  TEST_VZIP2(q, int, s, 32, 4);
++  TEST_VZIP2(q, int, s, 64, 2);
++  TEST_VZIP2(q, uint, u, 8, 16);
++  TEST_VZIP2(q, uint, u, 16, 8);
++  TEST_VZIP2(q, uint, u, 32, 4);
++  TEST_VZIP2(q, uint, u, 64, 2);
++  TEST_VZIP2(q, poly, p, 8, 16);
++  TEST_VZIP2(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP2(q, float, f, 16, 8);
++#endif
++  TEST_VZIP2(q, float, f, 32, 4);
++  TEST_VZIP2(q, float, f, 64, 2);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++}
++
++int main (void)
++{
++  exec_vzip_half ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ands_3.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int
++f9 (unsigned char x, int y)
++{
++  if (y > 1 && x == 0)
++    return 10;
++  return x;
++}
++
++/* { dg-final { scan-assembler "ands\t(x|w)\[0-9\]+,\[ \t\]*(x|w)\[0-9\]+,\[ \t\]*255" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=dummy" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "missing" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=cortex-a53+no" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "invalid feature" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=cortex-a53+dummy" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "missing" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=+dummy" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmaxmin.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmaxmin.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fno-inline -save-temps" } */
++/* { dg-options "-O2 -ftree-vectorize -fno-inline -fno-vect-cost-model -save-temps" } */
+ 
+ 
+ extern void abort (void);
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
+@@ -110,6 +110,6 @@ main (int argc, char **argv)
+ /* vfmaq_lane_f64.
+    vfma_laneq_f64.
+    vfmaq_laneq_f64.  */
+-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
++/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+ 
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
+@@ -111,6 +111,6 @@ main (int argc, char **argv)
+ /* vfmsq_lane_f64.
+    vfms_laneq_f64.
+    vfmsq_laneq_f64.  */
+-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
++/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+ 
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c
+@@ -8,4 +8,4 @@ foo (void)
+   bar (0.0);
+ }
+ 
+-/* { dg-final { scan-assembler "fmov\\td0, xzr" } } */
++/* { dg-final { scan-assembler "movi\\td0, #0" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c
+@@ -8,4 +8,4 @@ foo (void)
+   bar (0.0);
+ }
+ 
+-/* { dg-final { scan-assembler "fmov\\ts0, wzr" } } */
++/* { dg-final { scan-assembler "movi\\tv0\.2s, #0" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-save-temps -O2 -ftree-vectorize -fno-inline" } */
++/* { dg-options "-save-temps -O2 -ftree-vectorize -fno-inline -fno-vect-cost-model" } */
+ 
+ #define N 1024
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_subreg_1.c
+@@ -0,0 +1,30 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-ce1" } */
++
++/* Check that the inner if is transformed into CSELs.  */
++
++int
++foo (int *x, int *z, int a)
++{
++  int b = 0;
++  int c = 0;
++  int d = 0;
++  int i;
++
++  for (i = 0; i < a; i++)
++    {
++      if (x[i] < c)
++	{
++	  b = z[i];
++	  if (c < b)
++	    {
++	      c = b;
++	      d = i;
++	    }
++	}
++    }
++
++  return c + d;
++}
++
++/* { dg-final { scan-rtl-dump "if-conversion succeeded through noce_convert_multiple_sets" "ce1" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/ldp_stp_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/ldp_stp_1.c
+@@ -1,4 +1,4 @@
+-/* { dg-options "-O2" } */
++/* { dg-options "-O2 -mcpu=generic" } */
+ 
+ int arr[4][4];
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_1.c
+@@ -0,0 +1,20 @@
++/* { dg-options "-O2" } */
++
++/* Check that we can use a REG + IMM addressing mode when moving an unaligned
++   TImode value to and from memory.  */
++
++struct foo
++{
++  long long b;
++  __int128 a;
++} __attribute__ ((packed));
++
++void
++bar (struct foo *p, struct foo *q)
++{
++  p->a = q->a;
++}
++
++/* { dg-final { scan-assembler-not "add\tx\[0-9\]+, x\[0-9\]+" } } */
++/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr37780_1.c
+@@ -0,0 +1,46 @@
++/* Test that we can remove the conditional move due to CLZ
++   and CTZ being defined at zero.  */
++
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int
++fooctz (int i)
++{
++  return (i == 0) ? 32 : __builtin_ctz (i);
++}
++
++int
++fooctz2 (int i)
++{
++  return (i != 0) ? __builtin_ctz (i) : 32;
++}
++
++unsigned int
++fooctz3 (unsigned int i)
++{
++  return (i > 0) ?  __builtin_ctz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "rbit\t*" 3 } } */
++
++int
++fooclz (int i)
++{
++  return (i == 0) ? 32 : __builtin_clz (i);
++}
++
++int
++fooclz2 (int i)
++{
++  return (i != 0) ? __builtin_clz (i) : 32;
++}
++
++unsigned int
++fooclz3 (unsigned int i)
++{
++  return (i > 0) ? __builtin_clz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "clz\t" 6 } } */
++/* { dg-final { scan-assembler-not "cmp\t.*0" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr63874.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++/* { dg-skip-if "Not applicable for mcmodel=large" { aarch64*-*-* }  { "-mcmodel=large" } { "" } } */
++
++extern void __attribute__((weak)) foo_weakref (void);
++void __attribute__((weak, noinline)) bar (void)
++{
++ return;
++}
++void (*f) (void);
++void (*g) (void);
++
++int
++main (void)
++{
++ f = &foo_weakref;
++ g = &bar;
++ return 0;
++}
++
++/* { dg-final { scan-assembler-not "adr*foo_weakref" } } */
++/* { dg-final { scan-assembler-not "\\.(word|xword)\tbar" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c
+@@ -1,4 +1,4 @@
+-/* Test the `v[min|max]nm{q}_f*' AArch64 SIMD intrinsic.  */
++/* Test the `v[min|max]{nm}{q}_f*' AArch64 SIMD intrinsic.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2" } */
+@@ -18,6 +18,7 @@ extern void abort ();
+ int
+ main (int argc, char **argv)
+ {
++  /* v{min|max}nm_f32 normal.  */
+   float32x2_t f32x2_input1 = vdup_n_f32 (-1.0);
+   float32x2_t f32x2_input2 = vdup_n_f32 (0.0);
+   float32x2_t f32x2_exp_minnm  = vdup_n_f32 (-1.0);
+@@ -28,6 +29,7 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm);
+   CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm);
+ 
++  /* v{min|max}nm_f32 NaN.  */
+   f32x2_input1 = vdup_n_f32 (__builtin_nanf (""));
+   f32x2_input2 = vdup_n_f32 (1.0);
+   f32x2_exp_minnm  = vdup_n_f32 (1.0);
+@@ -38,6 +40,7 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm);
+   CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm);
+ 
++  /* v{min|max}nmq_f32 normal.  */
+   float32x4_t f32x4_input1 = vdupq_n_f32 (-1024.0);
+   float32x4_t f32x4_input2 = vdupq_n_f32 (77.0);
+   float32x4_t f32x4_exp_minnm  = vdupq_n_f32 (-1024.0);
+@@ -48,6 +51,7 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm);
+   CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm);
+ 
++  /* v{min|max}nmq_f32 NaN.  */
+   f32x4_input1 = vdupq_n_f32 (-__builtin_nanf (""));
+   f32x4_input2 = vdupq_n_f32 (-1.0);
+   f32x4_exp_minnm  = vdupq_n_f32 (-1.0);
+@@ -58,16 +62,57 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm);
+   CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm);
+ 
++  /* v{min|max}nm_f64 normal.  */
++  float64x1_t f64x1_input1 = vdup_n_f64 (1.23);
++  float64x1_t f64x1_input2 = vdup_n_f64 (4.56);
++  float64x1_t f64x1_exp_minnm  = vdup_n_f64 (1.23);
++  float64x1_t f64x1_exp_maxnm  = vdup_n_f64 (4.56);
++  float64x1_t f64x1_ret_minnm  = vminnm_f64 (f64x1_input1, f64x1_input2);
++  float64x1_t f64x1_ret_maxnm  = vmaxnm_f64 (f64x1_input1, f64x1_input2);
++  CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm);
++  CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm);
++
++  /* v{min|max}_f64 normal.  */
++  float64x1_t f64x1_exp_min  = vdup_n_f64 (1.23);
++  float64x1_t f64x1_exp_max  = vdup_n_f64 (4.56);
++  float64x1_t f64x1_ret_min  = vmin_f64 (f64x1_input1, f64x1_input2);
++  float64x1_t f64x1_ret_max  = vmax_f64 (f64x1_input1, f64x1_input2);
++  CHECK (uint64_t, 1, f64x1_ret_min, f64x1_exp_min);
++  CHECK (uint64_t, 1, f64x1_ret_max, f64x1_exp_max);
++
++  /* v{min|max}nmq_f64 normal.  */
+   float64x2_t f64x2_input1 = vdupq_n_f64 (1.23);
+   float64x2_t f64x2_input2 = vdupq_n_f64 (4.56);
+   float64x2_t f64x2_exp_minnm  = vdupq_n_f64 (1.23);
+   float64x2_t f64x2_exp_maxnm  = vdupq_n_f64 (4.56);
+   float64x2_t f64x2_ret_minnm  = vminnmq_f64 (f64x2_input1, f64x2_input2);
+   float64x2_t f64x2_ret_maxnm  = vmaxnmq_f64 (f64x2_input1, f64x2_input2);
+-
+   CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm);
+   CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm);
+ 
++  /* v{min|max}nm_f64 NaN.  */
++  f64x1_input1 = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_input2 = vdup_n_f64 (1.0);
++  f64x1_exp_minnm  = vdup_n_f64 (1.0);
++  f64x1_exp_maxnm  = vdup_n_f64 (1.0);
++  f64x1_ret_minnm  = vminnm_f64 (f64x1_input1, f64x1_input2);
++  f64x1_ret_maxnm  = vmaxnm_f64 (f64x1_input1, f64x1_input2);
++
++  CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm);
++  CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm);
++
++  /* v{min|max}_f64 NaN.  */
++  f64x1_input1 = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_input2 = vdup_n_f64 (1.0);
++  f64x1_exp_minnm  = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_exp_maxnm  = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_ret_minnm  = vmin_f64 (f64x1_input1, f64x1_input2);
++  f64x1_ret_maxnm  = vmax_f64 (f64x1_input1, f64x1_input2);
++
++  CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm);
++  CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm);
++
++  /* v{min|max}nmq_f64 NaN.  */
+   f64x2_input1 = vdupq_n_f64 (-__builtin_nan (""));
+   f64x2_input2 = vdupq_n_f64 (1.0);
+   f64x2_exp_minnm  = vdupq_n_f64 (1.0);
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vmul_elem_1.c
+@@ -0,0 +1,541 @@
++/* Test the vmul_n_f64 AArch64 SIMD intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-options "-O2 --save-temps" } */
++
++#include "arm_neon.h"
++
++extern void abort (void);
++
++#define A (132.4f)
++#define B (-0.0f)
++#define C (-34.8f)
++#define D (289.34f)
++float32_t expected2_1[2] = {A * A, B * A};
++float32_t expected2_2[2] = {A * B, B * B};
++float32_t expected4_1[4] = {A * A, B * A, C * A, D * A};
++float32_t expected4_2[4] = {A * B, B * B, C * B, D * B};
++float32_t expected4_3[4] = {A * C, B * C, C * C, D * C};
++float32_t expected4_4[4] = {A * D, B * D, C * D, D * D};
++float32_t _elemA = A;
++float32_t _elemB = B;
++float32_t _elemC = C;
++float32_t _elemD = D;
++
++#define AD (1234.5)
++#define BD (-0.0)
++#define CD (71.3)
++#define DD (-1024.4)
++float64_t expectedd2_1[2] = {AD * CD, BD * CD};
++float64_t expectedd2_2[2] = {AD * DD, BD * DD};
++float64_t _elemdC = CD;
++float64_t _elemdD = DD;
++
++
++#define AS (1024)
++#define BS (-31)
++#define CS (0)
++#define DS (655)
++int32_t expecteds2_1[2] = {AS * AS, BS * AS};
++int32_t expecteds2_2[2] = {AS * BS, BS * BS};
++int32_t expecteds4_1[4] = {AS * AS, BS * AS, CS * AS, DS * AS};
++int32_t expecteds4_2[4] = {AS * BS, BS * BS, CS * BS, DS * BS};
++int32_t expecteds4_3[4] = {AS * CS, BS * CS, CS * CS, DS * CS};
++int32_t expecteds4_4[4] = {AS * DS, BS * DS, CS * DS, DS * DS};
++int32_t _elemsA = AS;
++int32_t _elemsB = BS;
++int32_t _elemsC = CS;
++int32_t _elemsD = DS;
++
++#define AH ((int16_t) 0)
++#define BH ((int16_t) -32)
++#define CH ((int16_t) 102)
++#define DH ((int16_t) -51)
++#define EH ((int16_t) 71)
++#define FH ((int16_t) -91)
++#define GH ((int16_t) 48)
++#define HH ((int16_t) 255)
++int16_t expectedh4_1[4] = {AH * AH, BH * AH, CH * AH, DH * AH};
++int16_t expectedh4_2[4] = {AH * BH, BH * BH, CH * BH, DH * BH};
++int16_t expectedh4_3[4] = {AH * CH, BH * CH, CH * CH, DH * CH};
++int16_t expectedh4_4[4] = {AH * DH, BH * DH, CH * DH, DH * DH};
++int16_t expectedh8_1[8] = {AH * AH, BH * AH, CH * AH, DH * AH,
++			   EH * AH, FH * AH, GH * AH, HH * AH};
++int16_t expectedh8_2[8] = {AH * BH, BH * BH, CH * BH, DH * BH,
++			   EH * BH, FH * BH, GH * BH, HH * BH};
++int16_t expectedh8_3[8] = {AH * CH, BH * CH, CH * CH, DH * CH,
++			   EH * CH, FH * CH, GH * CH, HH * CH};
++int16_t expectedh8_4[8] = {AH * DH, BH * DH, CH * DH, DH * DH,
++			   EH * DH, FH * DH, GH * DH, HH * DH};
++int16_t expectedh8_5[8] = {AH * EH, BH * EH, CH * EH, DH * EH,
++			   EH * EH, FH * EH, GH * EH, HH * EH};
++int16_t expectedh8_6[8] = {AH * FH, BH * FH, CH * FH, DH * FH,
++			   EH * FH, FH * FH, GH * FH, HH * FH};
++int16_t expectedh8_7[8] = {AH * GH, BH * GH, CH * GH, DH * GH,
++			   EH * GH, FH * GH, GH * GH, HH * GH};
++int16_t expectedh8_8[8] = {AH * HH, BH * HH, CH * HH, DH * HH,
++			   EH * HH, FH * HH, GH * HH, HH * HH};
++int16_t _elemhA = AH;
++int16_t _elemhB = BH;
++int16_t _elemhC = CH;
++int16_t _elemhD = DH;
++int16_t _elemhE = EH;
++int16_t _elemhF = FH;
++int16_t _elemhG = GH;
++int16_t _elemhH = HH;
++
++#define AUS (1024)
++#define BUS (31)
++#define CUS (0)
++#define DUS (655)
++uint32_t expectedus2_1[2] = {AUS * AUS, BUS * AUS};
++uint32_t expectedus2_2[2] = {AUS * BUS, BUS * BUS};
++uint32_t expectedus4_1[4] = {AUS * AUS, BUS * AUS, CUS * AUS, DUS * AUS};
++uint32_t expectedus4_2[4] = {AUS * BUS, BUS * BUS, CUS * BUS, DUS * BUS};
++uint32_t expectedus4_3[4] = {AUS * CUS, BUS * CUS, CUS * CUS, DUS * CUS};
++uint32_t expectedus4_4[4] = {AUS * DUS, BUS * DUS, CUS * DUS, DUS * DUS};
++uint32_t _elemusA = AUS;
++uint32_t _elemusB = BUS;
++uint32_t _elemusC = CUS;
++uint32_t _elemusD = DUS;
++
++#define AUH ((uint16_t) 0)
++#define BUH ((uint16_t) 32)
++#define CUH ((uint16_t) 102)
++#define DUH ((uint16_t) 51)
++#define EUH ((uint16_t) 71)
++#define FUH ((uint16_t) 91)
++#define GUH ((uint16_t) 48)
++#define HUH ((uint16_t) 255)
++uint16_t expecteduh4_1[4] = {AUH * AUH, BUH * AUH, CUH * AUH, DUH * AUH};
++uint16_t expecteduh4_2[4] = {AUH * BUH, BUH * BUH, CUH * BUH, DUH * BUH};
++uint16_t expecteduh4_3[4] = {AUH * CUH, BUH * CUH, CUH * CUH, DUH * CUH};
++uint16_t expecteduh4_4[4] = {AUH * DUH, BUH * DUH, CUH * DUH, DUH * DUH};
++uint16_t expecteduh8_1[8] = {AUH * AUH, BUH * AUH, CUH * AUH, DUH * AUH,
++			     EUH * AUH, FUH * AUH, GUH * AUH, HUH * AUH};
++uint16_t expecteduh8_2[8] = {AUH * BUH, BUH * BUH, CUH * BUH, DUH * BUH,
++			     EUH * BUH, FUH * BUH, GUH * BUH, HUH * BUH};
++uint16_t expecteduh8_3[8] = {AUH * CUH, BUH * CUH, CUH * CUH, DUH * CUH,
++			     EUH * CUH, FUH * CUH, GUH * CUH, HUH * CUH};
++uint16_t expecteduh8_4[8] = {AUH * DUH, BUH * DUH, CUH * DUH, DUH * DUH,
++			     EUH * DUH, FUH * DUH, GUH * DUH, HUH * DUH};
++uint16_t expecteduh8_5[8] = {AUH * EUH, BUH * EUH, CUH * EUH, DUH * EUH,
++			     EUH * EUH, FUH * EUH, GUH * EUH, HUH * EUH};
++uint16_t expecteduh8_6[8] = {AUH * FUH, BUH * FUH, CUH * FUH, DUH * FUH,
++			     EUH * FUH, FUH * FUH, GUH * FUH, HUH * FUH};
++uint16_t expecteduh8_7[8] = {AUH * GUH, BUH * GUH, CUH * GUH, DUH * GUH,
++			     EUH * GUH, FUH * GUH, GUH * GUH, HUH * GUH};
++uint16_t expecteduh8_8[8] = {AUH * HUH, BUH * HUH, CUH * HUH, DUH * HUH,
++			     EUH * HUH, FUH * HUH, GUH * HUH, HUH * HUH};
++uint16_t _elemuhA = AUH;
++uint16_t _elemuhB = BUH;
++uint16_t _elemuhC = CUH;
++uint16_t _elemuhD = DUH;
++uint16_t _elemuhE = EUH;
++uint16_t _elemuhF = FUH;
++uint16_t _elemuhG = GUH;
++uint16_t _elemuhH = HUH;
++
++void
++check_v2sf (float32_t elemA, float32_t elemB)
++{
++  int32_t indx;
++  const float32_t vec32x2_buf[2] = {A, B};
++  float32x2_t vec32x2_src = vld1_f32 (vec32x2_buf);
++  float32_t vec32x2_res[2];
++
++  vst1_f32 (vec32x2_res, vmul_n_f32 (vec32x2_src, elemA));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint32_t *) &vec32x2_res[indx] != * (uint32_t *) &expected2_1[indx])
++      abort ();
++
++  vst1_f32 (vec32x2_res, vmul_n_f32 (vec32x2_src, elemB));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint32_t *) &vec32x2_res[indx] != * (uint32_t *) &expected2_2[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[0\\\]" 2 } } */
++}
++
++void
++check_v4sf (float32_t elemA, float32_t elemB, float32_t elemC, float32_t elemD)
++{
++  int32_t indx;
++  const float32_t vec32x4_buf[4] = {A, B, C, D};
++  float32x4_t vec32x4_src = vld1q_f32 (vec32x4_buf);
++  float32_t vec32x4_res[4];
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_1[indx])
++      abort ();
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_2[indx])
++      abort ();
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_3[indx])
++      abort ();
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_4[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" 4 } } */
++}
++
++void
++check_v2df (float64_t elemdC, float64_t elemdD)
++{
++  int32_t indx;
++  const float64_t vec64x2_buf[2] = {AD, BD};
++  float64x2_t vec64x2_src = vld1q_f64 (vec64x2_buf);
++  float64_t vec64x2_res[2];
++
++  vst1q_f64 (vec64x2_res, vmulq_n_f64 (vec64x2_src, elemdC));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint64_t *) &vec64x2_res[indx] != * (uint64_t *) &expectedd2_1[indx])
++      abort ();
++
++  vst1q_f64 (vec64x2_res, vmulq_n_f64 (vec64x2_src, elemdD));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint64_t *) &vec64x2_res[indx] != * (uint64_t *) &expectedd2_2[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[0\\\]" 2 } } */
++}
++
++void
++check_v2si (int32_t elemsA, int32_t elemsB)
++{
++  int32_t indx;
++  const int32_t vecs32x2_buf[2] = {AS, BS};
++  int32x2_t vecs32x2_src = vld1_s32 (vecs32x2_buf);
++  int32_t vecs32x2_res[2];
++
++  vst1_s32 (vecs32x2_res, vmul_n_s32 (vecs32x2_src, elemsA));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecs32x2_res[indx] != expecteds2_1[indx])
++      abort ();
++
++  vst1_s32 (vecs32x2_res, vmul_n_s32 (vecs32x2_src, elemsB));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecs32x2_res[indx] != expecteds2_2[indx])
++      abort ();
++}
++
++void
++check_v2si_unsigned (uint32_t elemusA, uint32_t elemusB)
++{
++  int indx;
++  const uint32_t vecus32x2_buf[2] = {AUS, BUS};
++  uint32x2_t vecus32x2_src = vld1_u32 (vecus32x2_buf);
++  uint32_t vecus32x2_res[2];
++
++  vst1_u32 (vecus32x2_res, vmul_n_u32 (vecus32x2_src, elemusA));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecus32x2_res[indx] != expectedus2_1[indx])
++      abort ();
++
++  vst1_u32 (vecus32x2_res, vmul_n_u32 (vecus32x2_src, elemusB));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecus32x2_res[indx] != expectedus2_2[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "\tmul\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[0\\\]" 4 } } */
++}
++
++void
++check_v4si (int32_t elemsA, int32_t elemsB, int32_t elemsC, int32_t elemsD)
++{
++  int32_t indx;
++  const int32_t vecs32x4_buf[4] = {AS, BS, CS, DS};
++  int32x4_t vecs32x4_src = vld1q_s32 (vecs32x4_buf);
++  int32_t vecs32x4_res[4];
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_1[indx])
++      abort ();
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_2[indx])
++      abort ();
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_3[indx])
++      abort ();
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_4[indx])
++      abort ();
++}
++
++void
++check_v4si_unsigned (uint32_t elemusA, uint32_t elemusB, uint32_t elemusC,
++		     uint32_t elemusD)
++{
++  int indx;
++  const uint32_t vecus32x4_buf[4] = {AUS, BUS, CUS, DUS};
++  uint32x4_t vecus32x4_src = vld1q_u32 (vecus32x4_buf);
++  uint32_t vecus32x4_res[4];
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_1[indx])
++      abort ();
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_2[indx])
++      abort ();
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_3[indx])
++      abort ();
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_4[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "\tmul\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" 8 } } */
++}
++
++
++void
++check_v4hi (int16_t elemhA, int16_t elemhB, int16_t elemhC, int16_t elemhD)
++{
++  int32_t indx;
++  const int16_t vech16x4_buf[4] = {AH, BH, CH, DH};
++  int16x4_t vech16x4_src = vld1_s16 (vech16x4_buf);
++  int16_t vech16x4_res[4];
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_1[indx])
++      abort ();
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_2[indx])
++      abort ();
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_3[indx])
++      abort ();
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_4[indx])
++      abort ();
++}
++
++void
++check_v4hi_unsigned (uint16_t elemuhA, uint16_t elemuhB, uint16_t elemuhC,
++		     uint16_t elemuhD)
++{
++  int indx;
++  const uint16_t vecuh16x4_buf[4] = {AUH, BUH, CUH, DUH};
++  uint16x4_t vecuh16x4_src = vld1_u16 (vecuh16x4_buf);
++  uint16_t vecuh16x4_res[4];
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_1[indx])
++      abort ();
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_2[indx])
++      abort ();
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_3[indx])
++      abort ();
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_4[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "mul\tv\[0-9\]+\.4h, v\[0-9\]+\.4h, v\[0-9\]+\.h\\\[0\\\]" 8 } } */
++}
++
++void
++check_v8hi (int16_t elemhA, int16_t elemhB, int16_t elemhC, int16_t elemhD,
++	    int16_t elemhE, int16_t elemhF, int16_t elemhG, int16_t elemhH)
++{
++  int32_t indx;
++  const int16_t vech16x8_buf[8] = {AH, BH, CH, DH, EH, FH, GH, HH};
++  int16x8_t vech16x8_src = vld1q_s16 (vech16x8_buf);
++  int16_t vech16x8_res[8];
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhA));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_1[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhB));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_2[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhC));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_3[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhD));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_4[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhE));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_5[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhF));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_6[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhG));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_7[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhH));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_8[indx])
++      abort ();
++}
++
++void
++check_v8hi_unsigned (uint16_t elemuhA, uint16_t elemuhB, uint16_t elemuhC,
++		     uint16_t elemuhD, uint16_t elemuhE, uint16_t elemuhF,
++		     uint16_t elemuhG, uint16_t elemuhH)
++{
++  int indx;
++  const uint16_t vecuh16x8_buf[8] = {AUH, BUH, CUH, DUH, EUH, FUH, GUH, HUH};
++  uint16x8_t vecuh16x8_src = vld1q_u16 (vecuh16x8_buf);
++  uint16_t vecuh16x8_res[8];
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhA));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_1[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhB));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_2[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhC));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_3[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhD));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_4[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhE));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_5[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhF));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_6[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhG));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_7[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhH));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_8[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "mul\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[0\\\]" 16 } } */
++}
++
++int
++main (void)
++{
++  check_v2sf (_elemA, _elemB);
++  check_v4sf (_elemA, _elemB, _elemC, _elemD);
++  check_v2df (_elemdC, _elemdD);
++  check_v2si (_elemsA, _elemsB);
++  check_v4si (_elemsA, _elemsB, _elemsC, _elemsD);
++  check_v4hi (_elemhA, _elemhB, _elemhC, _elemhD);
++  check_v8hi (_elemhA, _elemhB, _elemhC, _elemhD,
++	      _elemhE, _elemhF, _elemhG, _elemhH);
++  check_v2si_unsigned (_elemusA, _elemusB);
++  check_v4si_unsigned (_elemusA, _elemusB, _elemusC, _elemusD);
++  check_v4hi_unsigned (_elemuhA, _elemuhB, _elemuhC, _elemuhD);
++  check_v8hi_unsigned (_elemuhA, _elemuhB, _elemuhC, _elemuhD,
++		       _elemuhE, _elemuhF, _elemuhG, _elemuhH);
++
++  return 0;
++}
++
+--- a/src/gcc/testsuite/gcc.target/aarch64/store-pair-1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/store-pair-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2" } */
++/* { dg-options "-O2 -mcpu=generic" } */
+ 
+ int f(int *a, int b)
+ {
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/struct_return.c
+@@ -0,0 +1,31 @@
++/* Test the absence of a spurious move from x8 to x0 for functions
++   return structures.  */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++struct s
++{
++  long x;
++  long y;
++  long z;
++};
++
++struct s __attribute__((noinline))
++foo (long a, long d, long c)
++{
++  struct s b;
++  b.x = a;
++  b.y = d;
++  b.z = c;
++  return b;
++}
++
++int
++main (void)
++{
++  struct s x;
++  x = foo ( 10, 20, 30);
++  return x.x + x.y + x.z;
++}
++
++/* { dg-final { scan-assembler-not "mov\tx0, x8" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
+@@ -4,8 +4,7 @@
+      * total frame size > 512.
+        area except outgoing <= 512
+      * number of callee-saved reg >= 2.
+-     * Split stack adjustment into two subtractions.
+-       the first subtractions could be optimized into "stp !".  */
++     * Use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
+@@ -15,6 +14,6 @@
+ t_frame_pattern_outgoing (test10, 480, "x19", 24, a[8], a[9], a[10])
+ t_frame_run (test10)
+ 
+-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+-/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
++/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_12.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_12.c
+@@ -13,6 +13,6 @@ t_frame_run (test12)
+ 
+ /* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
+ 
+-/* Check epilogue using write-back.  */
+-/* { dg-final { scan-assembler-times "ldp\tx29, x30, \\\[sp\\\], \[0-9\]+" 3 } } */
++/* Check epilogue using no write-back.  */
++/* { dg-final { scan-assembler-times "ldp\tx29, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
+@@ -2,8 +2,7 @@
+      * without outgoing.
+      * total frame size > 512.
+      * number of callee-save reg >= 2.
+-     * split the stack adjustment into two substractions,
+-       the second could be optimized into "stp !".  */
++     * Use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 --save-temps" } */
+@@ -14,4 +13,4 @@ t_frame_pattern (test13, 700, )
+ t_frame_run (test13)
+ 
+ /* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
+-/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
++/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp\\\]" 1 } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
+@@ -3,8 +3,7 @@
+      * total frame size > 512.
+        area except outgoing <= 512
+      * number of callee-save reg >= 2.
+-     * split the stack adjustment into two substractions,
+-       the first could be optimized into "stp !".  */
++     * Use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 --save-temps" } */
+@@ -15,4 +14,4 @@ t_frame_pattern_outgoing (test15, 480, , 8, a[8])
+ t_frame_run (test15)
+ 
+ /* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
+-/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 3 } } */
++/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_16.c
+@@ -0,0 +1,25 @@
++/* Verify:
++     * with outgoing.
++     * single int register push.
++     * varargs and callee-save size >= 256
++     * Use 2 stack adjustments.  */
++
++/* { dg-do compile } */
++/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
++
++#define REP8(X) X,X,X,X,X,X,X,X
++#define REP64(X) REP8(REP8(X))
++
++void outgoing (__builtin_va_list, ...);
++
++double vararg_outgoing (int x1, ...)
++{
++  double a1 = x1, a2 = x1 * 2, a3 = x1 * 3, a4 = x1 * 4, a5 = x1 * 5, a6 = x1 * 6;
++  __builtin_va_list vl;
++  __builtin_va_start (vl, x1);
++  outgoing (vl, a1, a2, a3, a4, a5, a6, REP64 (1));
++  __builtin_va_end (vl);
++  return a1 + a2 + a3 + a4 + a5 + a6;
++}
++
++/* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 2 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_17.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++/* Test reuse of stack adjustment temporaries.  */
++
++void foo ();
++
++int reuse_mov (int i)
++{
++  int arr[1025];
++  return arr[i];
++}
++
++int no_reuse_mov (int i)
++{
++  int arr[1025];
++  foo ();
++  return arr[i];
++}
++
++/* { dg-final { scan-assembler-times "mov\tx16, \[0-9\]+" 3 } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
+@@ -3,8 +3,7 @@
+      * without outgoing.
+      * total frame size > 512.
+      * number of callee-saved reg == 1.
+-     * split stack adjustment into two subtractions.
+-       the second subtraction should use "str !".  */
++     * use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
+@@ -14,6 +13,7 @@
+ t_frame_pattern (test6, 700, )
+ t_frame_run (test6)
+ 
+-/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+-/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler-times "str\tx30, \\\[sp\\\]" 1 } } */
++/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\]" 2 } } */
++/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\]," 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
+@@ -3,8 +3,7 @@
+      * without outgoing.
+      * total frame size > 512.
+      * number of callee-saved reg == 2.
+-     * split stack adjustment into two subtractions.
+-       the second subtraction should use "stp !".  */
++     * use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
+@@ -14,6 +13,6 @@
+ t_frame_pattern (test7, 700, "x19")
+ t_frame_run (test7)
+ 
+-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+-/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp]" 1 } } */
++/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\]" 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
+@@ -12,6 +12,6 @@
+ t_frame_pattern_outgoing (test8, 700, , 8, a[8])
+ t_frame_run (test8)
+ 
+-/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 3 } } */
+-/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
++/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, \[0-9\]+\\\]" 1 } } */
++/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcpu=thunderx" } */
++
++struct ldp
++{
++  long long c;
++  int a, b;
++};
++
++
++int f(struct ldp *a)
++{
++  return a->a + a->b;
++}
++
++
++/* We know the alignement of a->a to be 8 byte aligned so it is profitable
++   to do ldp. */
++/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 1 } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcpu=thunderx" } */
++
++struct noldp
++{
++  int a, b;
++};
++
++
++int f(struct noldp *a)
++{
++  return a->a + a->b;
++}
++
++/* We know the alignement of a->a to be 4 byte aligned so it is not profitable
++   to do ldp. */
++/* { dg-final { scan-assembler-not "ldp\tw\[0-9\]+, w\[0-9\]" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL.  */
++
++long long
++f2 (long long x)
++{
++  return (x << 5) & 0xffffffff;
++}
++
++/* { dg-final { scan-assembler "lsl\tw" } } */
++/* { dg-final { scan-assembler-not "ubfiz\tx" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++/* Check that an X-reg UBFX can be simplified into a W-reg LSR.  */
++
++int
++f (unsigned long long x)
++{
++  x = (x >> 24) & 255;
++  return x + 1;
++}
++
++/* { dg-final { scan-assembler "lsr\tw" } } */
++/* { dg-final { scan-assembler-not "ubfx\tx" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/va_arg_1.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++int
++f (int a, ...)
++{
++  /* { dg-final { scan-assembler-not "str" } } */
++  return a;
++}
++
++/* { dg-final { cleanup-saved-temps } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/va_arg_2.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++int
++foo (char *fmt, ...)
++{
++  int d;
++  __builtin_va_list ap;
++
++  __builtin_va_start (ap, fmt);
++  d = __builtin_va_arg (ap, int);
++  __builtin_va_end (ap);
++
++  /* { dg-final { scan-assembler-not "x7" } } */
++  return d;
++}
++
++/* { dg-final { cleanup-saved-temps } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/va_arg_3.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++int d2i (double a);
++
++int
++foo (char *fmt, ...)
++{
++  int d, e;
++  double f, g;
++  __builtin_va_list ap;
++
++  __builtin_va_start (ap, fmt);
++  d = __builtin_va_arg (ap, int);
++  f = __builtin_va_arg (ap, double);
++  g = __builtin_va_arg (ap, double);
++  d += d2i (f);
++  d += d2i (g);
++  __builtin_va_end (ap);
++
++  /* { dg-final { scan-assembler-not "x7" } } */
++  /* { dg-final { scan-assembler-not "q7" } } */
++  return d;
++}
++
++/* { dg-final { cleanup-saved-temps } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
+@@ -1,6 +1,6 @@
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O3" } */
++/* { dg-options "-O3 -fno-vect-cost-model" } */
+ 
+ #define N 16
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O3 -save-temps -fno-inline" } */
++/* { dg-options "-O3 -save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ extern void abort ();
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ #define FTYPE double
+ #define ITYPE long
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ #define FTYPE double
+ #define ITYPE long
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ #define FTYPE double
+ #define ITYPE long
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c
+@@ -0,0 +1,86 @@
++/* { dg-do compile } */
++/* { dg-options "-O3" } */
++
++#include "arm_neon.h"
++
++#define BUILD_TEST(TYPE1, TYPE2, Q1, Q2, SUFFIX, INDEX1, INDEX2)	\
++TYPE1 __attribute__((noinline,noclone))					\
++test_copy##Q1##_lane##Q2##_##SUFFIX (TYPE1 a, TYPE2 b)			\
++{									\
++  return vcopy##Q1##_lane##Q2##_##SUFFIX (a, INDEX1, b, INDEX2);	\
++}
++
++/* vcopy_lane.  */
++BUILD_TEST (poly8x8_t, poly8x8_t, , , p8, 7, 6)
++BUILD_TEST (int8x8_t,  int8x8_t,  , , s8, 7, 6)
++BUILD_TEST (uint8x8_t, uint8x8_t, , , u8, 7, 6)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[6\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x4_t, , , p16, 3, 2)
++BUILD_TEST (int16x4_t,  int16x4_t,  , , s16, 3, 2)
++BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[2\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0)
++BUILD_TEST (int32x2_t,   int32x2_t,   , , s32, 1, 0)
++BUILD_TEST (uint32x2_t,  uint32x2_t,  , , u32, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */
++BUILD_TEST (int64x1_t,   int64x1_t,   , , s64, 0, 0)
++BUILD_TEST (uint64x1_t,  uint64x1_t,  , , u64, 0, 0)
++BUILD_TEST (float64x1_t, float64x1_t, , , f64, 0, 0)
++/* { dg-final { scan-assembler-times "fmov\\td0, d1" 3 } } */
++
++/* vcopy_laneq.  */
++
++BUILD_TEST (poly8x8_t, poly8x16_t, , q, p8, 7, 15)
++BUILD_TEST (int8x8_t,  int8x16_t,  , q, s8, 7, 15)
++BUILD_TEST (uint8x8_t, uint8x16_t, , q, u8, 7, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x8_t, , q, p16, 3, 7)
++BUILD_TEST (int16x4_t,  int16x8_t,  , q, s16, 3, 7)
++BUILD_TEST (uint16x4_t, uint16x8_t, , q, u16, 3, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x4_t, , q, f32, 1, 3)
++BUILD_TEST (int32x2_t,   int32x4_t,   , q, s32, 1, 3)
++BUILD_TEST (uint32x2_t,  uint32x4_t,  , q, u32, 1, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[3\\\]" 3 } } */
++BUILD_TEST (float64x1_t, float64x2_t, , q, f64, 0, 1)
++BUILD_TEST (int64x1_t,  int64x2_t,    , q, s64, 0, 1)
++BUILD_TEST (uint64x1_t, uint64x2_t,   , q, u64, 0, 1)
++/* XFAIL due to PR 71307.  */
++/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 { xfail *-*-* } } } */
++
++/* vcopyq_lane.  */
++BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7)
++BUILD_TEST (int8x16_t,  int8x8_t,  q, , s8, 15, 7)
++BUILD_TEST (uint8x16_t, uint8x8_t, q, , u8, 15, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[15\\\], v1.b\\\[7\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x4_t, q, , p16, 7, 3)
++BUILD_TEST (int16x8_t,  int16x4_t,  q, , s16, 7, 3)
++BUILD_TEST (uint16x8_t, uint16x4_t, q, , u16, 7, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[7\\\], v1.h\\\[3\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x2_t, q, , f32, 3, 1)
++BUILD_TEST (int32x4_t,   int32x2_t,   q, , s32, 3, 1)
++BUILD_TEST (uint32x4_t,  uint32x2_t,  q, , u32, 3, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[3\\\], v1.s\\\[1\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x1_t, q, , f64, 1, 0)
++BUILD_TEST (int64x2_t,   int64x1_t,   q, , s64, 1, 0)
++BUILD_TEST (uint64x2_t,  uint64x1_t,  q, , u64, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[0\\\]" 3 } } */
++
++/* vcopyq_laneq.  */
++
++BUILD_TEST (poly8x16_t, poly8x16_t, q, q, p8, 14, 15)
++BUILD_TEST (int8x16_t,  int8x16_t,  q, q, s8, 14, 15)
++BUILD_TEST (uint8x16_t, uint8x16_t, q, q, u8, 14, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[14\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x8_t, q, q, p16, 6, 7)
++BUILD_TEST (int16x8_t,  int16x8_t,  q, q, s16, 6, 7)
++BUILD_TEST (uint16x8_t, uint16x8_t, q, q, u16, 6, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[6\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x4_t, q, q, f32, 2, 3)
++BUILD_TEST (int32x4_t,   int32x4_t,   q, q, s32, 2, 3)
++BUILD_TEST (uint32x4_t,  uint32x4_t,  q, q, u32, 2, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[2\\\], v1.s\\\[3\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x2_t, q, q, f64, 1, 1)
++BUILD_TEST (int64x2_t,   int64x2_t,   q,  q, s64, 1, 1)
++BUILD_TEST (uint64x2_t,  uint64x2_t,  q, q, u64, 1, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[1\\\]" 3 } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect_ctz_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect_ctz_1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O3 -save-temps -fno-inline" } */
++/* { dg-options "-O3 -save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ extern void abort ();
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c
+@@ -0,0 +1,72 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++#include "arm_neon.h"
++
++#define BUILD_TEST(TYPE1, TYPE2, Q1, Q2, SUFFIX, INDEX1, INDEX2)	\
++TYPE1 __attribute__((noinline,noclone))				\
++test_copy##Q1##_lane##Q2##_##SUFFIX (TYPE1 a, TYPE2 b)			\
++{									\
++  return vset##Q1##_lane_##SUFFIX (vget##Q2##_lane_##SUFFIX (b, INDEX2),\
++				    a, INDEX1);				\
++}
++
++BUILD_TEST (poly8x8_t, poly8x8_t, , , p8, 7, 6)
++BUILD_TEST (int8x8_t,  int8x8_t,  , , s8, 7, 6)
++BUILD_TEST (uint8x8_t, uint8x8_t, , , u8, 7, 6)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[6\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x4_t, , , p16, 3, 2)
++BUILD_TEST (int16x4_t,  int16x4_t,  , , s16, 3, 2)
++BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[2\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0)
++BUILD_TEST (int32x2_t,   int32x2_t,   , , s32, 1, 0)
++BUILD_TEST (uint32x2_t,  uint32x2_t,  , , u32, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */
++
++BUILD_TEST (poly8x8_t, poly8x16_t, , q, p8, 7, 15)
++BUILD_TEST (int8x8_t,  int8x16_t,  , q, s8, 7, 15)
++BUILD_TEST (uint8x8_t, uint8x16_t, , q, u8, 7, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x8_t, , q, p16, 3, 7)
++BUILD_TEST (int16x4_t,  int16x8_t,  , q, s16, 3, 7)
++BUILD_TEST (uint16x4_t, uint16x8_t, , q, u16, 3, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x4_t, , q, f32, 1, 3)
++BUILD_TEST (int32x2_t,   int32x4_t,   , q, s32, 1, 3)
++BUILD_TEST (uint32x2_t,  uint32x4_t,  , q, u32, 1, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[3\\\]" 3 } } */
++
++BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7)
++BUILD_TEST (int8x16_t,  int8x8_t,  q, , s8, 15, 7)
++BUILD_TEST (uint8x16_t, uint8x8_t, q, , u8, 15, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[15\\\], v1.b\\\[7\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x4_t, q, , p16, 7, 3)
++BUILD_TEST (int16x8_t,  int16x4_t,  q, , s16, 7, 3)
++BUILD_TEST (uint16x8_t, uint16x4_t, q, , u16, 7, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[7\\\], v1.h\\\[3\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x2_t, q, , f32, 3, 1)
++BUILD_TEST (int32x4_t,   int32x2_t,   q, , s32, 3, 1)
++BUILD_TEST (uint32x4_t,  uint32x2_t,  q, , u32, 3, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[3\\\], v1.s\\\[1\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x1_t, q, , f64, 1, 0)
++BUILD_TEST (int64x2_t,   int64x1_t,   q, , s64, 1, 0)
++BUILD_TEST (uint64x2_t,  uint64x1_t,  q, , u64, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[0\\\]" 3 } } */
++
++BUILD_TEST (poly8x16_t, poly8x16_t, q, q, p8, 14, 15)
++BUILD_TEST (int8x16_t,  int8x16_t,  q, q, s8, 14, 15)
++BUILD_TEST (uint8x16_t, uint8x16_t, q, q, u8, 14, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[14\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x8_t, q, q, p16, 6, 7)
++BUILD_TEST (int16x8_t,  int16x8_t,  q, q, s16, 6, 7)
++BUILD_TEST (uint16x8_t, uint16x8_t, q, q, u16, 6, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[6\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x4_t, q, q, f32, 2, 3)
++BUILD_TEST (int32x4_t,   int32x4_t,   q, q, s32, 2, 3)
++BUILD_TEST (uint32x4_t,  uint32x4_t,  q, q, u32, 2, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[2\\\], v1.s\\\[3\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x2_t, q, q, f64, 1, 1)
++BUILD_TEST (int64x2_t,   int64x2_t,   q,  q, s64, 1, 1)
++BUILD_TEST (uint64x2_t,  uint64x2_t,  q, q, u64, 1, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[1\\\]" 3 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/vminmaxnm.c
+@@ -0,0 +1,37 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++#include "arm_neon.h"
++
++/* For each of these intrinsics, we map directly to an unspec in RTL.
++   We're just using the argument directly and returning the result, so we
++   can precisely specify the exact instruction pattern and register
++   allocations we expect.  */
++
++float64x1_t
++test_vmaxnm_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fmaxnm\td0, d0, d1" 1 } } */
++  return vmaxnm_f64 (a, b);
++}
++
++float64x1_t
++test_vminnm_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fminnm\td0, d0, d1" 1 } } */
++  return vminnm_f64 (a, b);
++}
++
++float64x1_t
++test_vmax_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fmax\td0, d0, d1" 1 } } */
++  return vmax_f64 (a, b);
++}
++
++float64x1_t
++test_vmin_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fmin\td0, d0, d1" 1 } } */
++  return vmin_f64 (a, b);
++}
+\ No newline at end of file
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
+@@ -0,0 +1,32 @@
++/* Test AAPCS layout (VFP variant for Neon types) */
++
++/* { dg-do run { target arm_eabi } } */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_neon_fp16_hw } */
++/* { dg-add-options arm_neon_fp16 } */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define NEON
++#define TESTFILE "neon-vect10.c"
++#include "neon-constants.h"
++
++#include "abitest.h"
++#else
++
++ARG (int32x4_t, i32x4_constvec2, Q0) /* D0, D1.  */
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 3.0f, S4 + 2) /* D2, Q1.  */
++#else
++ARG (__fp16, 3.0f, S4) /* D2, Q1.  */
++#endif
++ARG (int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12.  */
++ARG (double, 12.0, D3) /* Backfill this particular argument.  */
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 5.0f, S5 + 2) /* Backfill in S5.  */
++#else
++ARG (__fp16, 5.0f, S5) /* Backfill in S5.  */
++#endif
++ARG (int32x4x2_t, i32x4x2_constvec2, STACK)
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
+@@ -0,0 +1,24 @@
++/* Test AAPCS layout (VFP variant for Neon types) */
++
++/* { dg-do run { target arm_eabi } } */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_neon_fp16_hw } */
++/* { dg-add-options arm_neon_fp16 } */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define NEON
++#define TESTFILE "neon-vect9.c"
++#include "neon-constants.h"
++
++#include "abitest.h"
++#else
++
++ARG (int32x4_t, i32x4_constvec2, Q0) /* D0, D1.  */
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 3.0f, S4 + 2) /* D2, Q1 occupied.  */
++#else
++ARG (__fp16, 3.0f, S4) /* D2, Q1 occupied.  */
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
+@@ -0,0 +1,28 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp18.c"
++#include "abitest.h"
++
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (double, 4.0, D1)
++ARG (float, 2.0f, S4)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S5 + 2)
++#else
++ARG (__fp16, 1.0f, S5)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
+@@ -0,0 +1,30 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp19.c"
++
++__complex__ x = 1.0+2.0i;
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (__complex__ double, x, D1)
++ARG (float, 3.0f, S6)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 2.0f, S7 + 2)
++#else
++ARG (__fp16, 2.0f, S7)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
+@@ -0,0 +1,22 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp20.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++ARG (float, 1.0f, R0)
++ARG (double, 2.0, R2)
++ARG (float, 3.0f, STACK)
++ARG (__fp16, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
+@@ -0,0 +1,26 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp21.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, R0 + 2)
++#else
++ARG (__fp16, 1.0f, R0)
++#endif
++ARG (double, 2.0, R2)
++ARG (__fp16, 3.0f, STACK)
++ARG (float, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp22.c
+@@ -0,0 +1,28 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp22.c"
++#include "abitest.h"
++
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (double, 4.0, D1)
++ARG (float, 2.0f, S4)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S5 + 2)
++#else
++ARG (__fp16, 1.0f, S5)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp23.c
+@@ -0,0 +1,30 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp23.c"
++
++__complex__ x = 1.0+2.0i;
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (__complex__ double, x, D1)
++ARG (float, 3.0f, S6)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 2.0f, S7 + 2)
++#else
++ARG (__fp16, 2.0f, S7)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp24.c
+@@ -0,0 +1,21 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp24.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++ARG (float, 1.0f, R0)
++ARG (double, 2.0, R2)
++ARG (float, 3.0f, STACK)
++ARG (__fp16, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp25.c
+@@ -0,0 +1,25 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp25.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, R0 + 2)
++#else
++ARG (__fp16, 1.0f, R0)
++#endif
++ARG (double, 2.0, R2)
++ARG (__fp16, 3.0f, STACK)
++ARG (float, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c
+@@ -0,0 +1,8 @@
++/* { dg-require-effective-target arm_arch_v5_ok } */
++/* { dg-add-options arm_arch_v5 } */
++
++#if __ARM_ARCH_ISA_THUMB
++#error "__ARM_ARCH_ISA_THUMB defined for ARMv5"
++#endif
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c
+@@ -0,0 +1,105 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_ok }  */
++/* { dg-options "-O2 -ffast-math" }  */
++/* { dg-add-options arm_v8_2a_fp16_neon }  */
++
++/* Test instructions generated for half-precision arithmetic.  */
++
++typedef __fp16 float16_t;
++typedef __simd64_float16_t float16x4_t;
++typedef __simd128_float16_t float16x8_t;
++
++typedef short int16x4_t __attribute__ ((vector_size (8)));
++typedef short int int16x8_t  __attribute__ ((vector_size (16)));
++
++float16_t
++fp16_abs (float16_t a)
++{
++  return (a < 0) ? -a : a;
++}
++
++#define TEST_UNOP(NAME, OPERATOR, TY)		\
++  TY test_##NAME##_##TY (TY a)			\
++  {						\
++    return OPERATOR (a);			\
++  }
++
++#define TEST_BINOP(NAME, OPERATOR, TY)		\
++  TY test_##NAME##_##TY (TY a, TY b)		\
++  {						\
++    return a OPERATOR b;			\
++  }
++
++#define TEST_CMP(NAME, OPERATOR, RTY, TY)	\
++  RTY test_##NAME##_##TY (TY a, TY b)		\
++  {						\
++    return a OPERATOR b;			\
++  }
++
++/* Scalars.  */
++
++TEST_UNOP (neg, -, float16_t)
++TEST_UNOP (abs, fp16_abs, float16_t)
++
++TEST_BINOP (add, +, float16_t)
++TEST_BINOP (sub, -, float16_t)
++TEST_BINOP (mult, *, float16_t)
++TEST_BINOP (div, /, float16_t)
++
++TEST_CMP (equal, ==, int, float16_t)
++TEST_CMP (unequal, !=, int, float16_t)
++TEST_CMP (lessthan, <, int, float16_t)
++TEST_CMP (greaterthan, >, int, float16_t)
++TEST_CMP (lessthanequal, <=, int, float16_t)
++TEST_CMP (greaterthanqual, >=, int, float16_t)
++
++/* Vectors of size 4.  */
++
++TEST_UNOP (neg, -, float16x4_t)
++
++TEST_BINOP (add, +, float16x4_t)
++TEST_BINOP (sub, -, float16x4_t)
++TEST_BINOP (mult, *, float16x4_t)
++TEST_BINOP (div, /, float16x4_t)
++
++TEST_CMP (equal, ==, int16x4_t, float16x4_t)
++TEST_CMP (unequal, !=, int16x4_t, float16x4_t)
++TEST_CMP (lessthan, <, int16x4_t, float16x4_t)
++TEST_CMP (greaterthan, >, int16x4_t, float16x4_t)
++TEST_CMP (lessthanequal, <=, int16x4_t, float16x4_t)
++TEST_CMP (greaterthanqual, >=, int16x4_t, float16x4_t)
++
++/* Vectors of size 8.  */
++
++TEST_UNOP (neg, -, float16x8_t)
++
++TEST_BINOP (add, +, float16x8_t)
++TEST_BINOP (sub, -, float16x8_t)
++TEST_BINOP (mult, *, float16x8_t)
++TEST_BINOP (div, /, float16x8_t)
++
++TEST_CMP (equal, ==, int16x8_t, float16x8_t)
++TEST_CMP (unequal, !=, int16x8_t, float16x8_t)
++TEST_CMP (lessthan, <, int16x8_t, float16x8_t)
++TEST_CMP (greaterthan, >, int16x8_t, float16x8_t)
++TEST_CMP (lessthanequal, <=, int16x8_t, float16x8_t)
++TEST_CMP (greaterthanqual, >=, int16x8_t, float16x8_t)
++
++/* { dg-final { scan-assembler-times {vneg\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vneg\.f16\td[0-9]+, d[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vneg\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vabs\.f16\ts[0-9]+, s[0-9]+} 2 } }  */
++
++/* { dg-final { scan-assembler-times {vadd\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vsub\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vmul\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vdiv\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vcmp\.f32\ts[0-9]+, s[0-9]+} 26 } }  */
++/* { dg-final { scan-assembler-times {vcmpe\.f32\ts[0-9]+, s[0-9]+} 52 } }  */
++
++/* { dg-final { scan-assembler-not {vadd\.f32} } }  */
++/* { dg-final { scan-assembler-not {vsub\.f32} } }  */
++/* { dg-final { scan-assembler-not {vmul\.f32} } }  */
++/* { dg-final { scan-assembler-not {vdiv\.f32} } }  */
++/* { dg-final { scan-assembler-not {vcmp\.f16} } }  */
++/* { dg-final { scan-assembler-not {vcmpe\.f16} } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-conv-1.c
+@@ -0,0 +1,101 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++/* Test ARMv8.2 FP16 conversions.  */
++#include <arm_fp16.h>
++
++float
++f16_to_f32 (__fp16 a)
++{
++  return (float)a;
++}
++
++float
++f16_to_pf32 (__fp16* a)
++{
++  return (float)*a;
++}
++
++short
++f16_to_s16 (__fp16 a)
++{
++  return (short)a;
++}
++
++short
++pf16_to_s16 (__fp16* a)
++{
++  return (short)*a;
++}
++
++/* { dg-final { scan-assembler-times {vcvtb\.f32\.f16\ts[0-9]+, s[0-9]+} 4 } }  */
++
++__fp16
++f32_to_f16 (float a)
++{
++  return (__fp16)a;
++}
++
++void
++f32_to_pf16 (__fp16* x, float a)
++{
++  *x = (__fp16)a;
++}
++
++__fp16
++s16_to_f16 (short a)
++{
++  return (__fp16)a;
++}
++
++void
++s16_to_pf16 (__fp16* x, short a)
++{
++  *x = (__fp16)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvtb\.f16\.f32\ts[0-9]+, s[0-9]+} 4 } }  */
++
++float
++s16_to_f32 (short a)
++{
++  return (float)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+, s[0-9]+} 3 } }  */
++
++short
++f32_to_s16 (float a)
++{
++  return (short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+, s[0-9]+} 3 } }  */
++
++unsigned short
++f32_to_u16 (float a)
++{
++  return (unsigned short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.u32\.f32\ts[0-9]+, s[0-9]+} 1 } }  */
++
++short
++f64_to_s16 (double a)
++{
++  return (short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f64\ts[0-9]+, d[0-9]+} 1 } }  */
++
++unsigned short
++f64_to_u16 (double a)
++{
++  return (unsigned short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f64\ts[0-9]+, d[0-9]+} 1 } }  */
++
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c
+@@ -0,0 +1,165 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++__fp16
++test_load_1 (__fp16* a)
++{
++  return *a;
++}
++
++__fp16
++test_load_2 (__fp16* a, int i)
++{
++  return a[i];
++}
++
++/* { dg-final { scan-assembler-times {vld1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } }  */
++
++void
++test_store_1 (__fp16* a, __fp16 b)
++{
++  *a = b;
++}
++
++void
++test_store_2 (__fp16* a, int i, __fp16 b)
++{
++  a[i] = b;
++}
++
++/* { dg-final { scan-assembler-times {vst1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } }  */
++
++__fp16
++test_load_store_1 (__fp16* a, int i, __fp16* b)
++{
++  a[i] = b[i];
++}
++
++__fp16
++test_load_store_2 (__fp16* a, int i, __fp16* b)
++{
++  a[i] = b[i + 2];
++  return a[i];
++}
++/* { dg-final { scan-assembler-times {ldrh\tr[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {strh\tr[0-9]+} 2 } }  */
++
++__fp16
++test_select_1 (int sel, __fp16 a, __fp16 b)
++{
++  if (sel)
++    return a;
++  else
++    return b;
++}
++
++__fp16
++test_select_2 (int sel, __fp16 a, __fp16 b)
++{
++  return sel ? a : b;
++}
++
++__fp16
++test_select_3 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a == b) ? b : c;
++}
++
++__fp16
++test_select_4 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a != b) ? b : c;
++}
++
++__fp16
++test_select_5 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a < b) ? b : c;
++}
++
++__fp16
++test_select_6 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a <= b) ? b : c;
++}
++
++__fp16
++test_select_7 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a > b) ? b : c;
++}
++
++__fp16
++test_select_8 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a >= b) ? b : c;
++}
++
++/* { dg-final { scan-assembler-times {vseleq\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 4 } } */
++/* { dg-final { scan-assembler-times {vselgt\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vselge\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++/* { dg-final { scan-assembler-times {vmov\.f16\ts[0-9]+, r[0-9]+} 4 } }  */
++/* { dg-final { scan-assembler-times {vmov\.f16\tr[0-9]+, s[0-9]+} 4 } }  */
++
++int
++test_compare_1 (__fp16 a, __fp16 b)
++{
++  if (a == b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_ (__fp16 a, __fp16 b)
++{
++  if (a != b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_2 (__fp16 a, __fp16 b)
++{
++  if (a > b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_3 (__fp16 a, __fp16 b)
++{
++  if (a >= b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_4 (__fp16 a, __fp16 b)
++{
++  if (a < b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_5 (__fp16 a, __fp16 b)
++{
++  if (a <= b)
++    return -1;
++  else
++    return 0;
++}
++
++/* { dg-final { scan-assembler-not {vcmp\.f16} } }  */
++/* { dg-final { scan-assembler-not {vcmpe\.f16} } }  */
++
++/* { dg-final { scan-assembler-times {vcmp\.f32} 4 } }  */
++/* { dg-final { scan-assembler-times {vcmpe\.f32} 8 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c
+@@ -0,0 +1,490 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_neon }  */
++
++/* Test instructions generated for the FP16 vector intrinsics.  */
++
++#include <arm_neon.h>
++
++#define MSTRCAT(L, str)	L##str
++
++#define UNOP_TEST(insn)				\
++  float16x4_t					\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a)	\
++  {						\
++    return MSTRCAT (insn, _f16) (a);		\
++  }						\
++  float16x8_t					\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a)	\
++  {						\
++    return MSTRCAT (insn, q_f16) (a);		\
++  }
++
++#define BINOP_TEST(insn)					\
++  float16x4_t							\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a, float16x4_t b)	\
++  {								\
++    return MSTRCAT (insn, _f16) (a, b);				\
++  }								\
++  float16x8_t							\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a, float16x8_t b)	\
++  {								\
++    return MSTRCAT (insn, q_f16) (a, b);			\
++  }
++
++#define BINOP_LANE_TEST(insn, I)					\
++  float16x4_t								\
++  MSTRCAT (test_##insn##_lane, _16x4) (float16x4_t a, float16x4_t b)	\
++  {									\
++    return MSTRCAT (insn, _lane_f16) (a, b, I);				\
++  }									\
++  float16x8_t								\
++  MSTRCAT (test_##insn##_lane, _16x8) (float16x8_t a, float16x4_t b)	\
++  {									\
++    return MSTRCAT (insn, q_lane_f16) (a, b, I);			\
++  }
++
++#define BINOP_LANEQ_TEST(insn, I)					\
++  float16x4_t								\
++  MSTRCAT (test_##insn##_laneq, _16x4) (float16x4_t a, float16x8_t b)	\
++  {									\
++    return MSTRCAT (insn, _laneq_f16) (a, b, I);			\
++  }									\
++  float16x8_t								\
++  MSTRCAT (test_##insn##_laneq, _16x8) (float16x8_t a, float16x8_t b)	\
++  {									\
++    return MSTRCAT (insn, q_laneq_f16) (a, b, I);			\
++  }									\
++
++#define BINOP_N_TEST(insn)					\
++  float16x4_t							\
++  MSTRCAT (test_##insn##_n, _16x4) (float16x4_t a, float16_t b)	\
++  {								\
++    return MSTRCAT (insn, _n_f16) (a, b);			\
++  }								\
++  float16x8_t							\
++  MSTRCAT (test_##insn##_n, _16x8) (float16x8_t a, float16_t b)	\
++  {								\
++    return MSTRCAT (insn, q_n_f16) (a, b);			\
++  }
++
++#define TERNOP_TEST(insn)						\
++  float16_t								\
++  MSTRCAT (test_##insn, _16) (float16_t a, float16_t b, float16_t c)	\
++  {									\
++    return MSTRCAT (insn, h_f16) (a, b, c);				\
++  }									\
++  float16x4_t								\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a, float16x4_t b,		\
++			       float16x4_t c)				\
++  {									\
++    return MSTRCAT (insn, _f16) (a, b, c);				\
++  }									\
++  float16x8_t								\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a, float16x8_t b,		\
++			       float16x8_t c)				\
++  {									\
++    return MSTRCAT (insn, q_f16) (a, b, c);				\
++  }
++
++#define VCMP1_TEST(insn)			\
++  uint16x4_t					\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a)	\
++  {						\
++    return MSTRCAT (insn, _f16) (a);		\
++  }						\
++  uint16x8_t					\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a)	\
++  {						\
++    return MSTRCAT (insn, q_f16) (a);		\
++  }
++
++#define VCMP2_TEST(insn)					\
++  uint16x4_t							\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a, float16x4_t b)	\
++  {								\
++    return MSTRCAT (insn, _f16) (a, b);				\
++  }								\
++  uint16x8_t							\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a, float16x8_t b)	\
++  {								\
++    return MSTRCAT (insn, q_f16) (a, b);			\
++  }
++
++#define VCVT_TEST(insn, TY, TO, FR)			\
++  MSTRCAT (TO, 16x4_t)					\
++  MSTRCAT (test_##insn, TY) (MSTRCAT (FR, 16x4_t) a)	\
++  {							\
++    return MSTRCAT (insn, TY) (a);			\
++  }							\
++  MSTRCAT (TO, 16x8_t)					\
++  MSTRCAT (test_##insn##_q, TY) (MSTRCAT (FR, 16x8_t) a)	\
++  {							\
++    return MSTRCAT (insn, q##TY) (a);			\
++  }
++
++#define VCVT_N_TEST(insn, TY, TO, FR)			\
++  MSTRCAT (TO, 16x4_t)					\
++  MSTRCAT (test_##insn##_n, TY) (MSTRCAT (FR, 16x4_t) a)	\
++  {							\
++    return MSTRCAT (insn, _n##TY) (a, 1);		\
++  }							\
++  MSTRCAT (TO, 16x8_t)					\
++  MSTRCAT (test_##insn##_n_q, TY) (MSTRCAT (FR, 16x8_t) a)	\
++  {							\
++    return MSTRCAT (insn, q_n##TY) (a, 1);		\
++  }
++
++VCMP1_TEST (vceqz)
++/* { dg-final { scan-assembler-times {vceq\.f16\td[0-9]+, d[0-0]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vcgtz)
++/* { dg-final { scan-assembler-times {vcgt\.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vcgez)
++/* { dg-final { scan-assembler-times {vcge\.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vcge\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vcltz)
++/* { dg-final { scan-assembler-times {vclt.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vclt.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vclez)
++/* { dg-final { scan-assembler-times {vcle\.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vcle\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCVT_TEST (vcvt, _f16_s16, float, int)
++VCVT_N_TEST (vcvt, _f16_s16, float, int)
++/* { dg-final { scan-assembler-times {vcvt\.f16\.s16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.s16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.s16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.s16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvt, _f16_u16, float, uint)
++VCVT_N_TEST (vcvt, _f16_u16, float, uint)
++/* { dg-final { scan-assembler-times {vcvt\.f16\.u16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.u16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.u16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.u16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvt, _s16_f16, int, float)
++VCVT_N_TEST (vcvt, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvt\.s16\.f16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.s16\.f16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.s16\.f16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.s16\.f16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvt, _u16_f16, uint, float)
++VCVT_N_TEST (vcvt, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvt\.u16\.f16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.u16\.f16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.u16\.f16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.u16\.f16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvta, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvta\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvta\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvta, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvta\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvta\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtm, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvtm\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtm\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtm, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvtm\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtm\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtn, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvtn\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtn\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtn, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvtn\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtn\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtp, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvtp\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtp\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtp, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvtp\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtp\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++UNOP_TEST (vabs)
++/* { dg-final { scan-assembler-times {vabs\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vabs\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vneg)
++/* { dg-final { scan-assembler-times {vneg\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vneg\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrecpe)
++/* { dg-final { scan-assembler-times {vrecpe\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrecpe\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnd)
++/* { dg-final { scan-assembler-times {vrintz\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintz\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnda)
++/* { dg-final { scan-assembler-times {vrinta\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrinta\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndm)
++/* { dg-final { scan-assembler-times {vrintm\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintm\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndn)
++/* { dg-final { scan-assembler-times {vrintn\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintn\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndp)
++/* { dg-final { scan-assembler-times {vrintp\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintp\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndx)
++/* { dg-final { scan-assembler-times {vrintx\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintx\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrsqrte)
++/* { dg-final { scan-assembler-times {vrsqrte\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrsqrte\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vadd)
++/* { dg-final { scan-assembler-times {vadd\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vabd)
++/* { dg-final { scan-assembler-times {vabd\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vabd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcage)
++/* { dg-final { scan-assembler-times {vacge\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vacge\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcagt)
++/* { dg-final { scan-assembler-times {vacgt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vacgt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcale)
++/* { dg-final { scan-assembler-times {vacle\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vacle\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcalt)
++/* { dg-final { scan-assembler-times {vaclt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vaclt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vceq)
++/* { dg-final { scan-assembler-times {vceq\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcge)
++/* { dg-final { scan-assembler-times {vcge\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcge\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcgt)
++/* { dg-final { scan-assembler-times {vcgt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcgt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcle)
++/* { dg-final { scan-assembler-times {vcle\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcle\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vclt)
++/* { dg-final { scan-assembler-times {vclt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vclt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmax)
++/* { dg-final { scan-assembler-times {vmax\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vmax\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmin)
++/* { dg-final { scan-assembler-times {vmin\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vmin\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmaxnm)
++/* { dg-final { scan-assembler-times {vmaxnm\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vmaxnm\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vminnm)
++/* { dg-final { scan-assembler-times {vminnm\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vminnm\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmul)
++/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 3 } }
++   { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++BINOP_LANE_TEST (vmul, 2)
++/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+\[2\]} 1 } }
++   { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, d[0-9]+\[2\]} 1 } }  */
++BINOP_N_TEST (vmul)
++/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+\[0\]} 1 } }
++   { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, d[0-9]+\[0\]} 1 } }*/
++
++float16x4_t
++test_vpadd_16x4 (float16x4_t a, float16x4_t b)
++{
++  return vpadd_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vpadd\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } } */
++
++float16x4_t
++test_vpmax_16x4 (float16x4_t a, float16x4_t b)
++{
++  return vpmax_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vpmax\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } } */
++
++float16x4_t
++test_vpmin_16x4 (float16x4_t a, float16x4_t b)
++{
++  return vpmin_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vpmin\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } } */
++
++BINOP_TEST (vsub)
++/* { dg-final { scan-assembler-times {vsub\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vsub\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vrecps)
++/* { dg-final { scan-assembler-times {vrecps\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vrecps\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vrsqrts)
++/* { dg-final { scan-assembler-times {vrsqrts\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vrsqrts\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfma)
++/* { dg-final { scan-assembler-times {vfma\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vfma\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfms)
++/* { dg-final { scan-assembler-times {vfms\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vfms\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4_t
++test_vmov_n_f16 (float16_t a)
++{
++  return vmov_n_f16 (a);
++}
++
++float16x4_t
++test_vdup_n_f16 (float16_t a)
++{
++  return vdup_n_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, r[0-9]+} 2 } }  */
++
++float16x8_t
++test_vmovq_n_f16 (float16_t a)
++{
++  return vmovq_n_f16 (a);
++}
++
++float16x8_t
++test_vdupq_n_f16 (float16_t a)
++{
++  return vdupq_n_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, r[0-9]+} 2 } }  */
++
++float16x4_t
++test_vdup_lane_f16 (float16x4_t a)
++{
++  return vdup_lane_f16 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, d[0-9]+\[1\]} 1 } }  */
++
++float16x8_t
++test_vdupq_lane_f16 (float16x4_t a)
++{
++  return vdupq_lane_f16 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, d[0-9]+\[1\]} 1 } }  */
++
++float16x4_t
++test_vext_f16 (float16x4_t a, float16x4_t b)
++{
++  return vext_f16 (a, b, 1);
++}
++/* { dg-final { scan-assembler-times {vext\.16\td[0-9]+, d[0-9]+, d[0-9]+, #1} 1 } } */
++
++float16x8_t
++test_vextq_f16 (float16x8_t a, float16x8_t b)
++{
++  return vextq_f16 (a, b, 1);
++}
++/*   { dg-final { scan-assembler-times {vext\.16\tq[0-9]+, q[0-9]+, q[0-9]+, #1} 1 } }  */
++
++UNOP_TEST (vrev64)
++/* { dg-final { scan-assembler-times {vrev64\.16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrev64\.16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4_t
++test_vbsl16x4 (uint16x4_t a, float16x4_t b, float16x4_t c)
++{
++  return vbsl_f16 (a, b, c);
++}
++/* { dg-final { scan-assembler-times {vbsl\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8_t
++test_vbslq16x8 (uint16x8_t a, float16x8_t b, float16x8_t c)
++{
++  return vbslq_f16 (a, b, c);
++}
++/*{ dg-final { scan-assembler-times {vbsl\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4x2_t
++test_vzip16x4 (float16x4_t a, float16x4_t b)
++{
++  return vzip_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vzip\.16\td[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8x2_t
++test_vzipq16x8 (float16x8_t a, float16x8_t b)
++{
++  return vzipq_f16 (a, b);
++}
++/*{ dg-final { scan-assembler-times {vzip\.16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4x2_t
++test_vuzp16x4 (float16x4_t a, float16x4_t b)
++{
++  return vuzp_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vuzp\.16\td[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8x2_t
++test_vuzpq16x8 (float16x8_t a, float16x8_t b)
++{
++  return vuzpq_f16 (a, b);
++}
++/*{ dg-final { scan-assembler-times {vuzp\.16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4x2_t
++test_vtrn16x4 (float16x4_t a, float16x4_t b)
++{
++  return vtrn_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vtrn\.16\td[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8x2_t
++test_vtrnq16x8 (float16x8_t a, float16x8_t b)
++{
++  return vtrnq_f16 (a, b);
++}
++/*{ dg-final { scan-assembler-times {vtrn\.16\tq[0-9]+, q[0-9]+} 1 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-1.c
+@@ -0,0 +1,203 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++/* Test instructions generated for the FP16 scalar intrinsics.  */
++#include <arm_fp16.h>
++
++#define MSTRCAT(L, str)	L##str
++
++#define UNOP_TEST(insn)				\
++  float16_t					\
++  MSTRCAT (test_##insn, 16) (float16_t a)	\
++  {						\
++    return MSTRCAT (insn, h_f16) (a);		\
++  }
++
++#define BINOP_TEST(insn)				\
++  float16_t						\
++  MSTRCAT (test_##insn, 16) (float16_t a, float16_t b)	\
++  {							\
++    return MSTRCAT (insn, h_f16) (a, b);		\
++  }
++
++#define TERNOP_TEST(insn)						\
++  float16_t								\
++  MSTRCAT (test_##insn, 16) (float16_t a, float16_t b, float16_t c)	\
++  {									\
++    return MSTRCAT (insn, h_f16) (a, b, c);				\
++  }
++
++float16_t
++test_vcvth_f16_s32 (int32_t a)
++{
++  return vcvth_f16_s32 (a);
++}
++
++float16_t
++test_vcvth_n_f16_s32 (int32_t a)
++{
++  return vcvth_n_f16_s32 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vcvt\.f16\.s32\ts[0-9]+, s[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {vcvt\.f16\.s32\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++float16_t
++test_vcvth_f16_u32 (uint32_t a)
++{
++  return vcvth_f16_u32 (a);
++}
++
++float16_t
++test_vcvth_n_f16_u32 (uint32_t a)
++{
++  return vcvth_n_f16_u32 (a, 1);
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.f16\.u32\ts[0-9]+, s[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {vcvt\.f16\.u32\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++uint32_t
++test_vcvth_u32_f16 (float16_t a)
++{
++  return vcvth_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvt\.u32\.f16\ts[0-9]+, s[0-9]+} 2 } }  */
++
++uint32_t
++test_vcvth_n_u32_f16 (float16_t a)
++{
++  return vcvth_n_u32_f16 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vcvt\.u32\.f16\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++int32_t
++test_vcvth_s32_f16 (float16_t a)
++{
++  return vcvth_s32_f16 (a);
++}
++
++int32_t
++test_vcvth_n_s32_f16 (float16_t a)
++{
++  return vcvth_n_s32_f16 (a, 1);
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f16\ts[0-9]+, s[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f16\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++int32_t
++test_vcvtah_s32_f16 (float16_t a)
++{
++  return vcvtah_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvta\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++uint32_t
++test_vcvtah_u32_f16 (float16_t a)
++{
++  return vcvtah_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvta\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++int32_t
++test_vcvtmh_s32_f16 (float16_t a)
++{
++  return vcvtmh_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtm\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++uint32_t
++test_vcvtmh_u32_f16 (float16_t a)
++{
++  return vcvtmh_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtm\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++int32_t
++test_vcvtnh_s32_f16 (float16_t a)
++{
++  return vcvtnh_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtn\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++uint32_t
++test_vcvtnh_u32_f16 (float16_t a)
++{
++  return vcvtnh_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtn\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++int32_t
++test_vcvtph_s32_f16 (float16_t a)
++{
++  return vcvtph_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtp\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++uint32_t
++test_vcvtph_u32_f16 (float16_t a)
++{
++  return vcvtph_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtp\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++UNOP_TEST (vabs)
++/* { dg-final { scan-assembler-times {vabs\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vneg)
++/* { dg-final { scan-assembler-times {vneg\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnd)
++/* { dg-final { scan-assembler-times {vrintz\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndi)
++/* { dg-final { scan-assembler-times {vrintr\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnda)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndm)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndn)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndp)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndx)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vsqrt)
++/* { dg-final { scan-assembler-times {vsqrt\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vadd)
++/* { dg-final { scan-assembler-times {vadd\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vdiv)
++/* { dg-final { scan-assembler-times {vdiv\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vmaxnm)
++/* { dg-final { scan-assembler-times {vmaxnm\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vminnm)
++/* { dg-final { scan-assembler-times {vminnm\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vmul)
++/* { dg-final { scan-assembler-times {vmul\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vsub)
++/* { dg-final { scan-assembler-times {vsub\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfma)
++/* { dg-final { scan-assembler-times {vfma\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfms)
++/* { dg-final { scan-assembler-times {vfms\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-2.c
+@@ -0,0 +1,71 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2 -std=c11" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++/* Test compiler use of FP16 instructions.  */
++#include <arm_fp16.h>
++
++float16_t
++test_mov_imm_1 (float16_t a)
++{
++  return 1.0;
++}
++
++float16_t
++test_mov_imm_2 (float16_t a)
++{
++  float16_t b = 1.0;
++  return b;
++}
++
++float16_t
++test_vmov_imm_3 (float16_t a)
++{
++  float16_t b = 1.0;
++  return vaddh_f16 (a, b);
++}
++
++float16_t
++test_vmov_imm_4 (float16_t a)
++{
++  return vaddh_f16 (a, 1.0);
++}
++
++/* { dg-final { scan-assembler-times {vmov.f16\ts[0-9]+, #1\.0e\+0} 4 } }
++   { dg-final { scan-assembler-times {vadd.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 2 } } */
++
++float16_t
++test_vmla_1 (float16_t a, float16_t b, float16_t c)
++{
++  return vaddh_f16 (vmulh_f16 (a, b), c);
++}
++/* { dg-final { scan-assembler-times {vmla\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++float16_t
++test_vmla_2 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (vmulh_f16 (vnegh_f16 (a), b), c);
++}
++/* { dg-final { scan-assembler-times {vnmla\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
++
++float16_t
++test_vmls_1 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (c, vmulh_f16 (a, b));
++}
++
++float16_t
++test_vmls_2 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (a, vmulh_f16 (b, c));
++}
++/* { dg-final { scan-assembler-times {vmls\.f16} 2 } } */
++
++float16_t
++test_vnmls_1 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (vmulh_f16 (a, b), c);
++}
++/* { dg-final { scan-assembler-times {vnmls\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2 -fno-ipa-icf" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-comp-swap-release-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex" 4 } } */
++/* { dg-final { scan-assembler-times "stlex" 4 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2 -fno-ipa-icf" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-comp-swap-release-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex" 4 } } */
++/* { dg-final { scan-assembler-times "stlex" 4 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2 -fno-ipa-icf" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-comp-swap-release-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex" 4 } } */
++/* { dg-final { scan-assembler-times "stlex" 4 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2 -fno-ipa-icf" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-comp-swap-release-acquire.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex" 4 } } */
+-/* { dg-final { scan-assembler-times "stlex" 4 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-acq_rel.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-acq_rel.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-acq_rel.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-acq_rel.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-acquire.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-char.x"
++
++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-char.x"
++
++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-char.x"
++
++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-char.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-char.x"
+-
+-/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-1.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-consume.x"
++
++/* Scan for ldaex is a PR59448 consume workaround.  */
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-2.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-consume.x"
++
++/* Scan for ldaex is a PR59448 consume workaround.  */
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-consume.x"
++
++/* Scan for ldaex is a PR59448 consume workaround.  */
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-consume.c
++++ b/src//dev/null
+@@ -1,11 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-consume.x"
+-
+-/* Scan for ldaex is a PR59448 consume workaround.  */
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-int.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-int.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-int.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-int.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-relaxed.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-relaxed.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-relaxed.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-relaxed.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-release.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-release.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-release.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-release.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-release.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-seq_cst.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-seq_cst.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-seq_cst.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-seq_cst.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-short.x"
++
++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-short.x"
++
++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-short.x"
++
++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-short.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-short.x"
+-
+-/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/attr-fp16-arith-1.c
+@@ -0,0 +1,58 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_v8_2a_fp16_scalar } */
++
++/* Reset fpu to a value compatible with the next pragmas.  */
++#pragma GCC target ("fpu=vfp")
++
++#pragma GCC push_options
++#pragma GCC target ("fpu=fp-armv8")
++
++#ifndef __ARM_FEATURE_FP16_SCALAR_ARITHMETIC
++#error __ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined.
++#endif
++
++#pragma GCC push_options
++#pragma GCC target ("fpu=neon-fp-armv8")
++
++#ifndef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
++#error __ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined.
++#endif
++
++#ifndef __ARM_NEON
++#error __ARM_NEON not defined.
++#endif
++
++#if !defined (__ARM_FP) || !(__ARM_FP & 0x2)
++#error Invalid value for __ARM_FP
++#endif
++
++#include "arm_neon.h"
++
++float16_t
++foo (float16x4_t b)
++{
++  float16x4_t a = {2.0, 3.0, 4.0, 5.0};
++  float16x4_t res = vadd_f16 (a, b);
++
++  return res[0];
++}
++
++/* { dg-final { scan-assembler "vadd\\.f16\td\[0-9\]+, d\[0-9\]+" } } */
++
++#pragma GCC pop_options
++
++/* Check that the FP version is correctly reset to mfpu=fp-armv8.  */
++
++#if !defined (__ARM_FP) || !(__ARM_FP & 0x2)
++#error __ARM_FP should record FP16 support.
++#endif
++
++#pragma GCC pop_options
++
++/* Check that the FP version is correctly reset to mfpu=vfp.  */
++
++#if !defined (__ARM_FP) || (__ARM_FP & 0x2)
++#error Unexpected value for __ARM_FP.
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_saddl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long overflow_add (long x, long y)
++{
++  long r;
++
++  int ovr = __builtin_saddl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_saddll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long long overflow_add (long long x, long long y)
++{
++  long long r;
++
++  int ovr = __builtin_saddll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
++/* { dg-final { scan-assembler "adcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_ssubl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long overflow_sub (long x, long y)
++{
++  long r;
++
++  int ovr = __builtin_ssubl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_ssubll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long long overflow_sub (long long x, long long y)
++{
++  long long r;
++
++  int ovr = __builtin_ssubll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
++/* { dg-final { scan-assembler "sbcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_uaddl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long overflow_add (unsigned long x, unsigned long y)
++{
++  unsigned long r;
++
++  int ovr = __builtin_uaddl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_uaddll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long long overflow_add (unsigned long long x, unsigned long long y)
++{
++  unsigned long long r;
++
++  int ovr = __builtin_uaddll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
++/* { dg-final { scan-assembler "adcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_usubl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long overflow_sub (unsigned long x, unsigned long y)
++{
++  unsigned long r;
++
++  int ovr = __builtin_usubl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_usubll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long long overflow_sub (unsigned long long x, unsigned long long y)
++{
++  unsigned long long r;
++
++  int ovr = __builtin_usubll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
++/* { dg-final { scan-assembler "sbcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cbz.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile {target { arm_thumb2 || arm_thumb1_cbz_ok } } } */
++/* { dg-options "-O2" } */
++
++int
++foo (int a, int *b)
++{
++  if (a)
++    *b = 1;
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "cbz\\tr\\d" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-4.c
+@@ -0,0 +1,57 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int b:5;
++  unsigned int c:11, :0, d:8;
++  struct { unsigned int ee:2; } e;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++extern void foo (test_st st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #255" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #3" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-5.c
+@@ -0,0 +1,53 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8191" } } */
++/* { dg-final { scan-assembler "movt\tr4, 255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #2047" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-6.c
+@@ -0,0 +1,63 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int	b : 3;
++  unsigned int	c : 14;
++  unsigned int	d : 1;
++  struct {
++      unsigned int    ee  : 2;
++      unsigned short  ff  : 15;
++  } e;
++  unsigned char	g : 1;
++  unsigned char	  : 4;
++  unsigned char	h : 3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 1023" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #3" } } */
++/* { dg-final { scan-assembler "movt\tr4, 32767" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #255" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-7.c
+@@ -0,0 +1,54 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8191" } } */
++/* { dg-final { scan-assembler "movt\tr4, 255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #2047" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-8.c
+@@ -0,0 +1,57 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #1" } } */
++/* { dg-final { scan-assembler "movt\tr4, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 31" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-9.c
+@@ -0,0 +1,56 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  char a:3;
++} test_st3;
++
++typedef struct
++{
++  char a:3;
++} test_st2;
++
++typedef struct
++{
++  test_st2 st2;
++  test_st3 st3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #1799" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-and-union-1.c
+@@ -0,0 +1,96 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned short a :11;
++} test_st_4;
++
++typedef union
++{
++  char	      a;
++  test_st_4 st4;
++}test_un_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef struct
++{
++  unsigned char	  a :3;
++  unsigned int	  b :13;
++  test_un_2	  un2;
++} test_st_2;
++
++typedef union
++{
++  test_st_2 st2;
++  test_st_3 st3;
++}test_un_1;
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned char	  c :4;
++  test_un_1	  un1;
++} test_st_1;
++
++typedef union
++{
++  test_st_1 st1;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st_1;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st_1);
++
++int
++main (void)
++{
++  read_st_1 r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st1);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #7939" } } */
++/* { dg-final { scan-assembler "movt\tr4, 15" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 2047" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #1" } } */
++/* { dg-final { scan-assembler "movt\tr4, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 31" } } */
++/* { dg-final { scan-assembler "ands\tr3, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-11.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (int);
++
++int
++foo (int a)
++{
++  return bar (bar (a + 1));
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-13.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" } */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (1.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "movs\tr0, r4" } } */
++/* { dg-final { scan-assembler "\n\tmovs\tr1, r4" } } */
++/* { dg-final { scan-assembler-not "\n\tmovs\tr2, r4\n\tmovs\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-2.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "movs\tr1, r0" } } */
++/* { dg-final { scan-assembler "movs\tr2, r0" } } */
++/* { dg-final { scan-assembler "movs\tr3, r0" } } */
++/* { dg-final { scan-assembler "mov\tip, r0" } } */
++/* { dg-final { scan-assembler "mov\tlr, r0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq," } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-6.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Remember dont clear r0 and r1, because we are passing the double parameter
++ * for bar in them.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/softfp.c
+@@ -0,0 +1,29 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse -mfloat-abi=softfp" } */
++
++double __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++double
++foo (double a)
++{
++  return bar (1.0f, 2.0) + a;
++}
++
++float __attribute__ ((cmse_nonsecure_entry))
++baz (float a, double b)
++{
++  return (float) bar (a, b);
++}
++
++/* Make sure we are not using FP instructions, since ARMv8-M Baseline does not
++   support such instructions.  */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++/* { dg-final { scan-assembler-not "vmrs" } } */
++
++/* Just double checking that we are still doing cmse though.  */
++/* { dg-final { scan-assembler-not "vmrs" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/union-1.c
+@@ -0,0 +1,71 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8063" } } */
++/* { dg-final { scan-assembler "movt\tr4, 63" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #511" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/union-2.c
+@@ -0,0 +1,86 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++  test_st_3 st_3;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8191" } } */
++/* { dg-final { scan-assembler "movt\tr4, 63" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #511" } } */
++/* { dg-final { scan-assembler "movt\tr4, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 31" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c
+@@ -0,0 +1,39 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  unsigned short  a : 6;
++  unsigned char	  b : 3;
++  unsigned char	  c;
++  unsigned short  d : 8;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = 63u;
++  t.b = 7u;
++  t.c = 255u;
++  t.d = 255u;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != 63u
++      || t.b != 7u
++      || t.c != 255u
++      || t.d != 255u)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tr1, #1855" } } */
++/* { dg-final { scan-assembler "movt\tr1, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c
+@@ -0,0 +1,36 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  short	      a : 7;
++  signed char b : 3;
++  short	      c : 11;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = -64;
++  t.b = -4 ;
++  t.c = -1024;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != -64
++      || t.b != -4
++      || t.c != -1024)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tr1, #1919" } } */
++/* { dg-final { scan-assembler "movt\tr1, 2047" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c
+@@ -0,0 +1,37 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  short	      a;
++  signed char b : 2;
++  short		: 1;
++  signed char c : 3;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = -32768;
++  t.b = -2;
++  t.c = -4;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != -32768
++      || t.b != -2
++      || t.c != -4)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tr1, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr1, 63" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
+@@ -0,0 +1,106 @@
++/* { dg-do compile } */
++/* { dg-options "-Os -mcmse -fdump-rtl-expand" }  */
++
++#include <arm_cmse.h>
++
++extern int a;
++extern int bar (void);
++
++int foo (char * p)
++{
++  cmse_address_info_t cait;
++
++  cait = cmse_TT (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TT_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  cait = cmse_TTA (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TTA_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  cait = cmse_TTT (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TTT_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  cait = cmse_TTAT (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TTAT_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char), 0);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_MPU_UNPRIV);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_MPU_READWRITE);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_MPU_UNPRIV | CMSE_MPU_READ);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_AU_NONSECURE
++					 | CMSE_MPU_NONSECURE);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_NONSECURE | CMSE_MPU_UNPRIV);
++
++  p = (char *) cmse_check_pointed_object (p, CMSE_NONSECURE | CMSE_MPU_UNPRIV);
++
++  return a;
++}
++/* { dg-final { scan-assembler-times "\ttt " 2 } } */
++/* { dg-final { scan-assembler-times "ttt " 2 } } */
++/* { dg-final { scan-assembler-times "tta " 2 } } */
++/* { dg-final { scan-assembler-times "ttat " 2 } } */
++/* { dg-final { scan-assembler-times "bl.cmse_check_address_range" 7 } } */
++/* { dg-final { scan-assembler-not "cmse_check_pointed_object" } } */
++
++int __attribute__ ((cmse_nonsecure_entry))
++baz (void)
++{
++  return cmse_nonsecure_caller ();
++}
++
++typedef int __attribute__ ((cmse_nonsecure_call)) (int_nsfunc_t) (void);
++
++int default_callback (void)
++{
++  return 0;
++}
++
++int_nsfunc_t * fp = (int_nsfunc_t *) default_callback;
++
++void __attribute__ ((cmse_nonsecure_entry))
++qux (int_nsfunc_t * callback)
++{
++  fp = cmse_nsfptr_create (callback);
++}
++
++int call_callback (void)
++{
++  if (cmse_is_nsfptr (fp))
++      return fp ();
++  else
++    return default_callback ();
++}
++/* { dg-final { scan-assembler "baz:" } } */
++/* { dg-final { scan-assembler "__acle_se_baz:" } } */
++/* { dg-final { scan-assembler "qux:" } } */
++/* { dg-final { scan-assembler "__acle_se_qux:" } } */
++/* { dg-final { scan-assembler-not "\tcmse_nonsecure_caller" } } */
++/* { dg-final { scan-rtl-dump "and.*reg.*const_int 1" expand } } */
++/* { dg-final { scan-assembler "bic" } } */
++/* { dg-final { scan-assembler "push\t\{r4, r5, r6" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq" } } */
++/* { dg-final { scan-assembler-times "bl\\s+__gnu_cmse_nonsecure_call" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-10.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++
++void
++foo (void) {}
++
++/* { dg-final { scan-assembler-not "bxns" } } */
++/* { dg-final { scan-assembler "foo:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_foo:" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-12.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++#include <arm_cmse.h>
++
++char *
++foo (char * p)
++{
++  if (!cmse_is_nsfptr (p))
++    return cmse_nsfptr_create (p);
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler-not "cmse_is_nsfptr" } } */
++/* { dg-final { scan-assembler-not "cmse_nsfptr_create" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-14.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int foo (void)
++{
++  return bar ();
++}
++
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++/* { dg-final { scan-assembler-not "b\[^ y\n\]*\\s+bar" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-15.c
+@@ -0,0 +1,72 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++int __attribute__ ((cmse_nonsecure_call)) (*ns_foo) (void);
++int (*s_bar) (void);
++int __attribute__ ((cmse_nonsecure_call)) (**ns_foo2) (void);
++int (**s_bar2) (void);
++
++typedef int __attribute__ ((cmse_nonsecure_call)) ns_foo_t (void);
++typedef int s_bar_t (void);
++typedef int __attribute__ ((cmse_nonsecure_call)) (* ns_foo_ptr) (void);
++typedef int (*s_bar_ptr) (void);
++
++int nonsecure0 (ns_foo_t * ns_foo_p)
++{
++  return ns_foo_p ();
++}
++
++int nonsecure1 (ns_foo_t ** ns_foo_p)
++{
++  return (*ns_foo_p) ();
++}
++
++int nonsecure2 (ns_foo_ptr ns_foo_p)
++{
++  return ns_foo_p ();
++}
++int nonsecure3 (ns_foo_ptr * ns_foo_p)
++{
++  return (*ns_foo_p) ();
++}
++
++int secure0 (s_bar_t * s_bar_p)
++{
++  return s_bar_p ();
++}
++
++int secure1 (s_bar_t ** s_bar_p)
++{
++  return (*s_bar_p) ();
++}
++
++int secure2 (s_bar_ptr s_bar_p)
++{
++  return s_bar_p ();
++}
++
++int secure3 (s_bar_ptr * s_bar_p)
++{
++  return (*s_bar_p) ();
++}
++
++int nonsecure4 (void)
++{
++  return ns_foo ();
++}
++
++int nonsecure5 (void)
++{
++  return (*ns_foo2) ();
++}
++
++int secure4 (void)
++{
++  return s_bar ();
++}
++
++int secure5 (void)
++{
++  return (*s_bar2) ();
++}
++/* { dg-final { scan-assembler-times "bl\\s+__gnu_cmse_nonsecure_call" 6 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-3.c
+@@ -0,0 +1,45 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++
++struct span {
++  int a, b;
++};
++struct span2 {
++  float a, b, c, d;
++};
++
++union test_union
++{
++  long long a;
++  int b;
++  struct span2 c;
++} test_union;
++
++void __attribute__ ((cmse_nonsecure_entry))
++foo (long long a, int b, long long c) {} /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++void __attribute__ ((cmse_nonsecure_entry))
++bar (long long a, int b, struct span c) {} /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++void __attribute__ ((cmse_nonsecure_entry))
++baz (int a, ...) {} /* { dg-error "not available to functions with variable number of arguments" } */
++
++struct span __attribute__ ((cmse_nonsecure_entry))
++qux (void) { /* { dg-error "not available to functions that return value on the stack" } */
++  struct span ret = {0, 0};
++  return ret;
++}
++
++void __attribute__ ((cmse_nonsecure_entry))
++norf (struct span2 a) {}
++
++void __attribute__ ((cmse_nonsecure_entry))
++foo2 (long long a, int b, union test_union c) {} /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++typedef void __attribute__ ((cmse_nonsecure_call)) bar2 (long long a, int b, long long c); /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++typedef void __attribute__ ((cmse_nonsecure_call)) baz2 (long long a, int b, struct span c); /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++typedef struct span __attribute__ ((cmse_nonsecure_call)) qux2 (void); /* { dg-error "not available to functions that return value on the stack" } */
++
++typedef void __attribute__ ((cmse_nonsecure_call)) norf2 (int a, ...); /* { dg-error "not available to functions with variable number of arguments" } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-4.c
+@@ -0,0 +1,34 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++
++struct span {
++  int a, b;
++};
++
++extern int qux (void);
++
++void __attribute__ ((cmse_nonsecure_entry))
++foo (void) {}
++
++static void __attribute__ ((cmse_nonsecure_entry))
++bar (void) {} /* { dg-warning "has no effect on functions with static linkage" } */
++
++int __attribute__ ((cmse_nonsecure_entry))
++baz (void)
++{
++  return qux ();
++}
++
++void __attribute__ ((cmse_nonsecure_call))
++quux (void) {} /* { dg-warning "attribute only applies to base type of a function pointer" } */
++
++int __attribute__ ((cmse_nonsecure_call)) norf; /* { dg-warning "attribute only applies to base type of a function pointer" } */
++
++/* { dg-final { scan-assembler-times "bxns" 2 } } */
++/* { dg-final { scan-assembler "foo:" } } */
++/* { dg-final { scan-assembler "__acle_se_foo:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_bar:" } } */
++/* { dg-final { scan-assembler "baz:" } } */
++/* { dg-final { scan-assembler "__acle_se_baz:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_quux:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_norf:" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-9.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-skip-if "Testing exclusion of -mcmse" { arm-*-* } { "-mcmse" } { "" } }  */
++
++
++void __attribute__ ((cmse_nonsecure_call)) (*bar) (int); /* { dg-warning "attribute ignored without -mcmse option" } */
++typedef void __attribute__ ((cmse_nonsecure_call)) baz (int); /* { dg-warning "attribute ignored without -mcmse option" } */
++
++int __attribute__ ((cmse_nonsecure_entry))
++foo (int a, baz b)
++{ /* { dg-warning "attribute ignored without -mcmse option" } */
++  bar (a);
++  b (a);
++  return a + 1;
++}
++
++/* { dg-final { scan-assembler-not "bxns" } } */
++/* { dg-final { scan-assembler-not "blxns" } } */
++/* { dg-final { scan-assembler-not "bl\t__gnu_cmse_nonsecure_call" } } */
++/* { dg-final { scan-assembler "foo:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_foo:" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse.exp
+@@ -0,0 +1,72 @@
++#   Copyright (C) 1997-2016 Free Software Foundation, Inc.
++
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++# GCC testsuite for ARMv8-M Security Extensions using the `dg.exp' driver.
++
++# Load support procs.
++load_lib gcc-dg.exp
++
++# Exit immediately if the target does not support -mcmse.
++if ![check_effective_target_arm_cmse_ok] then {
++    return
++}
++
++# If a testcase doesn't have special options, use these.
++global DEFAULT_CFLAGS
++if ![info exists DEFAULT_CFLAGS] then {
++    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
++}
++
++# Initialize `dg'.
++dg-init
++
++set saved-dg-do-what-default ${dg-do-what-default}
++set dg-do-what-default "assemble"
++
++set saved-lto_torture_options ${LTO_TORTURE_OPTIONS}
++set LTO_TORTURE_OPTIONS ""
++
++# These are for both baseline and mainline.
++gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] \
++	"" $DEFAULT_CFLAGS
++
++if {[check_effective_target_arm_arch_v8m_base_ok]} then {
++    # Baseline only
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/baseline/*.c]] \
++	    "" $DEFAULT_CFLAGS
++}
++
++if {[check_effective_target_arm_arch_v8m_main_ok]} then {
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    # Mainline -mfloat-abi=soft
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/soft/*.c]] \
++	    "-mfloat-abi=soft" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/softfp/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/softfp-sp/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/hard/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/hard-sp/*.c]] \
++	    "" $DEFAULT_CFLAGS
++}
++
++set LTO_TORTURE_OPTIONS ${saved-lto_torture_options}
++set dg-do-what-default ${saved-dg-do-what-default}
++
++# All done.
++dg-finish
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-4.c
+@@ -0,0 +1,55 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int b:5;
++  unsigned int c:11, :0, d:8;
++  struct { unsigned int ee:2; } e;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++extern void foo (test_st st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #255" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #3" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-5.c
+@@ -0,0 +1,51 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #8191" } } */
++/* { dg-final { scan-assembler "movt\tip, 255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #2047" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-6.c
+@@ -0,0 +1,61 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int	b : 3;
++  unsigned int	c : 14;
++  unsigned int	d : 1;
++  struct {
++      unsigned int    ee  : 2;
++      unsigned short  ff  : 15;
++  } e;
++  unsigned char	g : 1;
++  unsigned char	  : 4;
++  unsigned char	h : 3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 1023" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #3" } } */
++/* { dg-final { scan-assembler "movt\tip, 32767" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #255" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-7.c
+@@ -0,0 +1,52 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++
++/* { dg-final { scan-assembler "movw\tip, #8191" } } */
++/* { dg-final { scan-assembler "movt\tip, 255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #2047" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-8.c
+@@ -0,0 +1,55 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, #255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #1" } } */
++/* { dg-final { scan-assembler "movt\tip, 65535" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 31" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-9.c
+@@ -0,0 +1,54 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  char a:3;
++} test_st3;
++
++typedef struct
++{
++  char a:3;
++} test_st2;
++
++typedef struct
++{
++  test_st2 st2;
++  test_st3 st3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #1799" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-and-union-1.c
+@@ -0,0 +1,94 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned short a :11;
++} test_st_4;
++
++typedef union
++{
++  char	      a;
++  test_st_4 st4;
++}test_un_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef struct
++{
++  unsigned char	  a :3;
++  unsigned int	  b :13;
++  test_un_2	  un2;
++} test_st_2;
++
++typedef union
++{
++  test_st_2 st2;
++  test_st_3 st3;
++}test_un_1;
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned char	  c :4;
++  test_un_1	  un1;
++} test_st_1;
++
++typedef union
++{
++  test_st_1 st1;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st_1;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st_1);
++
++int
++main (void)
++{
++  read_st_1 r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st1);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #7939" } } */
++/* { dg-final { scan-assembler "movt\tip, 15" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 2047" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #1" } } */
++/* { dg-final { scan-assembler "movt\tip, 65535" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 31" } } */
++/* { dg-final { scan-assembler "and\tr3, r3, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c
+@@ -0,0 +1,43 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (3.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts7, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts8, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts9, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts10, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts11, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts12, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts13, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts14, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts15, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c
+@@ -0,0 +1,45 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c
+@@ -0,0 +1,42 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts7, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts8, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts9, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts10, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts11, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts12, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts13, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts14, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts15, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c
+@@ -0,0 +1,41 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts7, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts8, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts9, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts10, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts11, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts12, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts13, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts14, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts15, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-13.c
+@@ -0,0 +1,38 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (3.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.64\td0, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.64\td1, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td7, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-5.c
+@@ -0,0 +1,38 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-7.c
+@@ -0,0 +1,34 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "vldr\.64\td0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td7, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-8.c
+@@ -0,0 +1,33 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vldr\.64\td0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td7, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-13.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (1.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-5.c
+@@ -0,0 +1,24 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-7.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-8.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c
+@@ -0,0 +1,46 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "__acle_se_foo:" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-13.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (1.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "\n\tmov\tr1, r4" } } */
++/* { dg-final { scan-assembler-not "\n\tmov\tr2, r4\n\tmov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-5.c
+@@ -0,0 +1,38 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "__acle_se_foo:" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-7.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-8.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/union-1.c
+@@ -0,0 +1,69 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #8063" } } */
++/* { dg-final { scan-assembler "movt\tip, 63" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #511" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/union-2.c
+@@ -0,0 +1,84 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++  test_st_3 st_3;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #8191" } } */
++/* { dg-final { scan-assembler "movt\tip, 63" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #511" } } */
++/* { dg-final { scan-assembler "movt\tip, 65535" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 31" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/struct-1.c
+@@ -0,0 +1,33 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = 255u;
++  t.b = 32767u;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != 255u || t.b != 32767u)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movs\tr1, #255" } } */
++/* { dg-final { scan-assembler "movt\tr1, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/data-rel-1.c
+@@ -0,0 +1,12 @@
++/* { dg-options "-fPIC -mno-pic-data-is-text-relative" } */
++/* { dg-final { scan-assembler-not "j-\\(.LPIC"  } } */
++/* { dg-final { scan-assembler-not "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
++/* { dg-final { scan-assembler "j\\(GOT\\)" } } */
++/* { dg-final { scan-assembler "(ldr|mov)\tr\[0-9\]+, \\\[?r9" } } */
++
++static int j;
++
++int *Foo ()
++{
++  return &j;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/data-rel-2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-fPIC -mno-pic-data-is-text-relative -mno-single-pic-base" } */
++/* { dg-final { scan-assembler-not "j-\\(.LPIC"  } } */
++/* { dg-final { scan-assembler "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
++/* { dg-final { scan-assembler "j\\(GOT\\)" } } */
++
++static int j;
++
++int *Foo ()
++{
++  return &j;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/data-rel-3.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-fPIC -mpic-data-is-text-relative" } */
++/* { dg-final { scan-assembler "j-\\(.LPIC"  } } */
++/* { dg-final { scan-assembler-not "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
++/* { dg-final { scan-assembler-not "j\\(GOT\\)" } } */
++
++static int j;
++
++int *Foo ()
++{
++  return &j;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_fp16_ieee } */
++
++/* Test __fp16 arguments and return value in registers (hard-float).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler {vmov(\.f16)?\tr[0-9]+, s[0-9]+} } }  */
++/* { dg-final { scan-assembler {vmov(\.f32)?\ts1, s0} } }  */
++/* { dg-final { scan-assembler {vmov(\.f16)?\ts0, r[0-9]+} } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-mfloat-abi=softfp -O2" }  */
++/* { dg-add-options arm_fp16_ieee } */
++/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
++
++/* Test __fp16 arguments and return value in registers (softfp).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } }  */
++/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } }  */
++/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_fp16_alternative } */
++
++/* Test __fp16 arguments and return value in registers (hard-float).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } }  */
++/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } }  */
++/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-mfloat-abi=softfp -O2" }  */
++/* { dg-add-options arm_fp16_alternative } */
++/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
++
++/* Test __fp16 arguments and return value in registers (softfp).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } }  */
++/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } }  */
++/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } }  */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ __fp16 xx = 0.0;
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
+ 
+ #include <math.h>
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
+ 
+ #include <math.h>
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ float xx __attribute__((mode(HF))) = 0.0;
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* This number is the maximum value representable in the alternative
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -pedantic" } */
+ 
+ /* This number overflows the range of the alternative encoding.  Since this
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_none_ok } */
+ /* { dg-options "-mfp16-format=none" } */
+ 
+ /* __fp16 type name is not recognized unless you explicitly enable it
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_none_ok } */
+ /* { dg-options "-mfp16-format=none" } */
+ 
+ /* mode(HF) attributes are not recognized unless you explicitly enable
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-param-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-param-1.c
+@@ -1,10 +1,14 @@
+ /* { dg-do compile } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot have parameters of type __fp16.  */
+-extern void f (__fp16);		/* { dg-error "parameters cannot have __fp16 type" } */
+-extern void (*pf) (__fp16);	/* { dg-error "parameters cannot have __fp16 type" } */
++/* Test that the ACLE macro is defined.  */
++#if __ARM_FP16_ARGS != 1
++#error Unexpected value for __ARM_FP16_ARGS
++#endif
++
++/* Test that __fp16 is supported as a parameter type.  */
++extern void f (__fp16);
++extern void (*pf) (__fp16);
+ 
+-/* These should be OK.  */
+ extern void g (__fp16 *);
+ extern void (*pg) (__fp16 *);
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-return-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-return-1.c
+@@ -1,10 +1,9 @@
+ /* { dg-do compile } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot return type __fp16.  */
+-extern __fp16 f (void);		/* { dg-error "cannot return __fp16" } */
+-extern __fp16 (*pf) (void);	/* { dg-error "cannot return __fp16" } */
++/* Test that __fp16 is supported as a return type.  */
++extern __fp16 f (void);
++extern __fp16 (*pf) (void);
+ 
+-/* These should be OK.  */
+ extern __fp16 *g (void);
+ extern __fp16 *(*pg) (void);
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c
+@@ -3,6 +3,7 @@
+    from double to __fp16.  */
+ 
+ /* { dg-do run } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include <stdlib.h>
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/movdi_movw.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile { target { arm_thumb2_ok || arm_thumb1_movt_ok } } } */
++/* { dg-options "-O2" } */
++
++long long
++movdi (int a)
++{
++  return 0xF0F0;
++}
++
++/* Accept r1 because big endian targets put the low bits in the highest
++   numbered register of a pair.  */
++/* { dg-final { scan-assembler-times "movw\tr\[01\], #61680" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/movhi_movw.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile { target { arm_thumb2_ok || arm_thumb1_movt_ok } } } */
++/* { dg-options "-O2" } */
++
++short
++movsi (void)
++{
++  return (short) 0x7070;
++}
++
++/* { dg-final { scan-assembler-times "movw\tr0, #28784" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/movsi_movw.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile { target { arm_thumb2_ok || arm_thumb1_movt_ok } } } */
++/* { dg-options "-O2" } */
++
++int
++movsi (void)
++{
++  return 0xF0F0;
++}
++
++/* { dg-final { scan-assembler-times "movw\tr0, #61680" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddws16.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++
++int
++t6 (int len, void * dummy, short * __restrict x)
++{
++  len = len & ~31;
++  int result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.s16" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddws32.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++int
++t6 (int len, void * dummy, int * __restrict x)
++{
++  len = len & ~31;
++  long long result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.s32" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddwu16.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++int
++t6 (int len, void * dummy, unsigned short * __restrict x)
++{
++  len = len & ~31;
++  unsigned int result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw.u16" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddwu32.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++int
++t6 (int len, void * dummy, unsigned int * __restrict x)
++{
++  len = len & ~31;
++  unsigned long long result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.u32" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddwu8.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++
++int
++t6 (int len, void * dummy, char * __restrict x)
++{
++  len = len & ~31;
++  unsigned short result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.u8" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/neon.exp
++++ b/src//dev/null
+@@ -1,35 +0,0 @@
+-# Copyright (C) 1997-2016 Free Software Foundation, Inc.
+-
+-# This program is free software; you can redistribute it and/or modify
+-# it under the terms of the GNU General Public License as published by
+-# the Free Software Foundation; either version 3 of the License, or
+-# (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with GCC; see the file COPYING3.  If not see
+-# <http://www.gnu.org/licenses/>.
+-
+-# GCC testsuite that uses the `dg.exp' driver.
+-
+-# Exit immediately if this isn't an ARM target.
+-if ![istarget arm*-*-*] then {
+-  return
+-}
+-
+-# Load support procs.
+-load_lib gcc-dg.exp
+-
+-# Initialize `dg'.
+-dg-init
+-
+-# Main loop.
+-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+-	"" ""
+-
+-# All done.
+-dg-finish
+--- a/src/gcc/testsuite/gcc.target/arm/neon/polytypes.c
++++ b/src//dev/null
+@@ -1,48 +0,0 @@
+-/* Check that NEON polynomial vector types are suitably incompatible with
+-   integer vector types of the same layout.  */
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-void s64_8 (int8x8_t a) {}
+-void u64_8 (uint8x8_t a) {}
+-void p64_8 (poly8x8_t a) {}
+-void s64_16 (int16x4_t a) {}
+-void u64_16 (uint16x4_t a) {}
+-void p64_16 (poly16x4_t a) {}
+-
+-void s128_8 (int8x16_t a) {}
+-void u128_8 (uint8x16_t a) {}
+-void p128_8 (poly8x16_t a) {}
+-void s128_16 (int16x8_t a) {}
+-void u128_16 (uint16x8_t a) {}
+-void p128_16 (poly16x8_t a) {}
+-
+-void foo ()
+-{
+-  poly8x8_t v64_8;
+-  poly16x4_t v64_16;
+-  poly8x16_t v128_8;
+-  poly16x8_t v128_16;
+-
+-  s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
+-  /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
+-  u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
+-  p64_8 (v64_8);
+-
+-  s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
+-  u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
+-  p64_16 (v64_16);
+-
+-  s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
+-  u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
+-  p128_8 (v128_8);
+-
+-  s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
+-  u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
+-  p128_16 (v128_16);
+-}
+-/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/pr51534.c
++++ b/src//dev/null
+@@ -1,83 +0,0 @@
+-/* Test the vector comparison intrinsics when comparing to immediate zero.
+-   */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-#define GEN_TEST(T, D, C, R) \
+-  R test_##C##_##T (T a) { return C (a, D (0)); }
+-
+-#define GEN_DOUBLE_TESTS(S, T, C) \
+-  GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
+-  GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) 
+-
+-#define GEN_QUAD_TESTS(S, T, C) \
+-  GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
+-  GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) 
+-
+-#define GEN_COND_TESTS(C) \
+-  GEN_DOUBLE_TESTS (8, int8x8_t, C) \
+-  GEN_DOUBLE_TESTS (16, int16x4_t, C) \
+-  GEN_DOUBLE_TESTS (32, int32x2_t, C) \
+-  GEN_QUAD_TESTS (8, int8x16_t, C) \
+-  GEN_QUAD_TESTS (16, int16x8_t, C) \
+-  GEN_QUAD_TESTS (32, int32x4_t, C)
+-
+-GEN_COND_TESTS(vcgt)
+-GEN_COND_TESTS(vcge)
+-GEN_COND_TESTS(vclt)
+-GEN_COND_TESTS(vcle)
+-GEN_COND_TESTS(vceq)
+-
+-/* Scan for expected outputs.  */
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-
+-/* And ensure we don't have unexpected output too.  */
+-/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ 	\]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
+-
+-/* Tidy up.  */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabals16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabals32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabals8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabals8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabalu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabalu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabalu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabalu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabalu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabalu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabas16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabas16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabas32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabas32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabas8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabas8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabau16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabau16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabau32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabau32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabau8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabau8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdlu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdlu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdlu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vabsq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vabsq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vabsq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vabsq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vabs_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vabs_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vabs_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vabs_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddlu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddlu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddlu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vadds64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vaddu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddws16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddws16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddws32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddws32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddws8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddws8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddwu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddwu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddwu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddwu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddwu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddwu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vands16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vands32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vands64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vands8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vandu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x8_t out_int16x8_t;
+-int16x8_t arg0_int16x8_t;
+-int16x8_t arg1_int16x8_t;
+-void test_vbicQs16 (void)
+-{
+-
+-  out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x4_t out_int32x4_t;
+-int32x4_t arg0_int32x4_t;
+-int32x4_t arg1_int32x4_t;
+-void test_vbicQs32 (void)
+-{
+-
+-  out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x2_t out_int64x2_t;
+-int64x2_t arg0_int64x2_t;
+-int64x2_t arg1_int64x2_t;
+-void test_vbicQs64 (void)
+-{
+-
+-  out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x16_t out_int8x16_t;
+-int8x16_t arg0_int8x16_t;
+-int8x16_t arg1_int8x16_t;
+-void test_vbicQs8 (void)
+-{
+-
+-  out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x8_t out_uint16x8_t;
+-uint16x8_t arg0_uint16x8_t;
+-uint16x8_t arg1_uint16x8_t;
+-void test_vbicQu16 (void)
+-{
+-
+-  out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x4_t out_uint32x4_t;
+-uint32x4_t arg0_uint32x4_t;
+-uint32x4_t arg1_uint32x4_t;
+-void test_vbicQu32 (void)
+-{
+-
+-  out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x2_t out_uint64x2_t;
+-uint64x2_t arg0_uint64x2_t;
+-uint64x2_t arg1_uint64x2_t;
+-void test_vbicQu64 (void)
+-{
+-
+-  out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x16_t out_uint8x16_t;
+-uint8x16_t arg0_uint8x16_t;
+-uint8x16_t arg1_uint8x16_t;
+-void test_vbicQu8 (void)
+-{
+-
+-  out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbics16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x4_t out_int16x4_t;
+-int16x4_t arg0_int16x4_t;
+-int16x4_t arg1_int16x4_t;
+-void test_vbics16 (void)
+-{
+-
+-  out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbics32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x2_t out_int32x2_t;
+-int32x2_t arg0_int32x2_t;
+-int32x2_t arg1_int32x2_t;
+-void test_vbics32 (void)
+-{
+-
+-  out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vbics64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x1_t out_int64x1_t;
+-int64x1_t arg0_int64x1_t;
+-int64x1_t arg1_int64x1_t;
+-void test_vbics64 (void)
+-{
+-
+-  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbics8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x8_t out_int8x8_t;
+-int8x8_t arg0_int8x8_t;
+-int8x8_t arg1_int8x8_t;
+-void test_vbics8 (void)
+-{
+-
+-  out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x4_t out_uint16x4_t;
+-uint16x4_t arg0_uint16x4_t;
+-uint16x4_t arg1_uint16x4_t;
+-void test_vbicu16 (void)
+-{
+-
+-  out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x2_t out_uint32x2_t;
+-uint32x2_t arg0_uint32x2_t;
+-uint32x2_t arg1_uint32x2_t;
+-void test_vbicu32 (void)
+-{
+-
+-  out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vbicu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x1_t out_uint64x1_t;
+-uint64x1_t arg0_uint64x1_t;
+-uint64x1_t arg1_uint64x1_t;
+-void test_vbicu64 (void)
+-{
+-
+-  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x8_t out_uint8x8_t;
+-uint8x8_t arg0_uint8x8_t;
+-uint8x8_t arg1_uint8x8_t;
+-void test_vbicu8 (void)
+-{
+-
+-  out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-  poly16x8_t arg2_poly16x8_t;
+-
+-  out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-  poly64x2_t arg2_poly64x2_t;
+-
+-  out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-  poly8x16_t arg2_poly8x16_t;
+-
+-  out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-  int64x2_t arg2_int64x2_t;
+-
+-  out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-  uint64x2_t arg2_uint64x2_t;
+-
+-  out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-  poly16x4_t arg2_poly16x4_t;
+-
+-  out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-  poly64x1_t arg2_poly64x1_t;
+-
+-  out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-  poly8x8_t arg2_poly8x8_t;
+-
+-  out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-  int64x1_t arg2_int64x1_t;
+-
+-  out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-  uint64x1_t arg2_uint64x1_t;
+-
+-  out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcageQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcageQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcagef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcagef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcagtQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcagtQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcagtf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcagtf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcaleQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcaleQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcalef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcalef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcaltQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcaltQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcaltf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcaltf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQp8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqp8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqs16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqs32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqs8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcequ16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcequ16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcequ32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcequ32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcequ8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcequ8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcges16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcges16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcges32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcges32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcges8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcges8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgts16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgts32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgts8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcles16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcles16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcles32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcles32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcles8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcles8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vclsq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vclsq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vclsq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vcls_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vcls_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vcls_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclts16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclts32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclts8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vclzq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vclzq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vclzq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vclz_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vclz_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vclz_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vclz_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vclz_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vclz_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vcntq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcnts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcnts8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vcnt_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinep64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_float32x2_t = vcreate_f32 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_poly16x4_t = vcreate_p16 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatep64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_poly64x1_t = vcreate_p64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_poly8x8_t = vcreate_p8 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int16x4_t = vcreate_s16 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int32x2_t = vcreate_s32 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int64x1_t = vcreate_s64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int8x8_t = vcreate_s8 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint16x4_t = vcreate_u16 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint32x2_t = vcreate_u32 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x1_t = vcreate_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint8x8_t = vcreate_u8 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_nf32_s32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_nf32_u32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_ns32_f32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_nu32_f32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQf32_s32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQf32_u32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQs32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQs32_f32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQu32_f32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_nf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_nf32_s32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_nf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_nf32_u32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_ns32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_ns32_f32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_nu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_nu32_f32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_fp16_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon_fp16 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf16_f32 (void)
+-{
+-  float16x4_t out_float16x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f16.f32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf32_f16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_fp16_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon_fp16 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf32_f16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float16x4_t arg0_float16x4_t;
+-
+-  out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.f16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf32_s32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf32_u32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvts32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvts32_f32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtu32_f32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanep64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_np64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64_t arg0_poly64_t;
+-
+-  out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanep64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x2_t = vdup_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_np64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64_t arg0_poly64_t;
+-
+-  out_poly64x1_t = vdup_n_p64 (arg0_poly64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x4_t = vdup_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x2_t = vdup_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x8_t = vdup_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
+-/* { dg-add-options arm_neon } */
+-
+-#define N 32
+-
+-int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+-float fa[N];
+-int ia[N];
+-
+-int convert()
+-{
+-  int i;
+-
+-  /* int -> float */
+-  for (i = 0; i < N; i++)
+-    fa[i] = (float) ib[i];
+-
+-  /* float -> int */
+-  for (i = 0; i < N; i++)
+-    ia[i] = (int) fa[i];
+-
+-  return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
+-/* { dg-add-options arm_neon } */
+-
+-#define N 32
+-
+-int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+-float fa[N];
+-int ia[N];
+-
+-int convert()
+-{
+-  int i;
+-
+-  /* int -> float */
+-  for (i = 0; i < N; i++)
+-    fa[i] = (float) ib[i];
+-
+-  /* float -> int */
+-  for (i = 0; i < N; i++)
+-    ia[i] = (int) fa[i];
+-
+-  return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veors16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veors32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `veors64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veors8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veoru16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veoru32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `veoru64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veoru8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmaQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmaQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vfmaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfma\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmaf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmaf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vfma_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfma\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vfmsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfms\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vfms_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfms\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* Check that NEON vector shifts support immediate values == size.  /*
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-uint16x8_t test_vshll_n_u8 (uint8x8_t a)
+-{
+-    return vshll_n_u8(a, 8);
+-}
+-
+-uint32x4_t test_vshll_n_u16 (uint16x4_t a)
+-{   
+-    return vshll_n_u16(a, 16);
+-}
+-
+-uint64x2_t test_vshll_n_u32 (uint32x2_t a)
+-{
+-    return vshll_n_u32(a, 32);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanef32 (void)
+-{
+-  float32_t out_float32_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanep16 (void)
+-{
+-  poly16_t out_poly16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanep8 (void)
+-{
+-  poly8_t out_poly8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes16 (void)
+-{
+-  int16_t out_int16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes32 (void)
+-{
+-  int32_t out_int32_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes64 (void)
+-{
+-  register int64_t out_int64_t asm ("r0");
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes8 (void)
+-{
+-  int8_t out_int8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu16 (void)
+-{
+-  uint16_t out_uint16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu32 (void)
+-{
+-  uint32_t out_uint32_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu64 (void)
+-{
+-  register uint64_t out_uint64_t asm ("r0");
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu8 (void)
+-{
+-  uint8_t out_uint8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x2_t = vget_high_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x4_t = vget_high_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x2_t = vget_high_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x1_t = vget_high_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x8_t = vget_high_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanef32 (void)
+-{
+-  float32_t out_float32_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanep16 (void)
+-{
+-  poly16_t out_poly16_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanep8 (void)
+-{
+-  poly8_t out_poly8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes16 (void)
+-{
+-  int16_t out_int16_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes32 (void)
+-{
+-  int32_t out_int32_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes64 (void)
+-{
+-  int64_t out_int64_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes8 (void)
+-{
+-  int8_t out_int8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu16 (void)
+-{
+-  uint16_t out_uint16_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu32 (void)
+-{
+-  uint32_t out_uint32_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu64 (void)
+-{
+-  uint64_t out_uint64_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu8 (void)
+-{
+-  uint8_t out_uint8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowf32 (void)
+-{
+-  register float32x2_t out_float32x2_t asm ("d18");
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x2_t = vget_low_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowp16 (void)
+-{
+-  register poly16x4_t out_poly16x4_t asm ("d18");
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lowp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowp8 (void)
+-{
+-  register poly8x8_t out_poly8x8_t asm ("d18");
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lows16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows16 (void)
+-{
+-  register int16x4_t out_int16x4_t asm ("d18");
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x4_t = vget_low_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lows32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows32 (void)
+-{
+-  register int32x2_t out_int32x2_t asm ("d18");
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x2_t = vget_low_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lows64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x1_t = vget_low_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lows8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows8 (void)
+-{
+-  register int8x8_t out_int8x8_t asm ("d18");
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x8_t = vget_low_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu16 (void)
+-{
+-  register uint16x4_t out_uint16x4_t asm ("d18");
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu32 (void)
+-{
+-  register uint32x2_t out_uint32x2_t asm ("d18");
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lowu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu8 (void)
+-{
+-  register uint8x8_t out_uint8x8_t asm ("d18");
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-
+-  out_float32x4_t = vld1q_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-
+-  out_poly16x8_t = vld1q_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-
+-  out_poly64x2_t = vld1q_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-
+-  out_poly8x16_t = vld1q_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-
+-  out_int16x8_t = vld1q_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-
+-  out_int32x4_t = vld1q_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-
+-  out_int64x2_t = vld1q_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-
+-  out_int8x16_t = vld1q_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-
+-  out_uint16x8_t = vld1q_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-
+-  out_uint32x4_t = vld1q_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-
+-  out_uint64x2_t = vld1q_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-
+-  out_uint8x16_t = vld1q_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanep64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-
+-  out_float32x4_t = vld1q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-
+-  out_poly16x8_t = vld1q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-
+-  out_poly64x2_t = vld1q_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-
+-  out_poly8x16_t = vld1q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-
+-  out_int16x8_t = vld1q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-
+-  out_int32x4_t = vld1q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-
+-  out_int64x2_t = vld1q_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-
+-  out_int8x16_t = vld1q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-
+-  out_uint16x8_t = vld1q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-
+-  out_uint32x4_t = vld1q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-
+-  out_uint64x2_t = vld1q_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-
+-  out_uint8x16_t = vld1q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-
+-  out_float32x2_t = vld1_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-
+-  out_poly16x4_t = vld1_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-
+-  out_poly64x1_t = vld1_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-
+-  out_poly8x8_t = vld1_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-
+-  out_int16x4_t = vld1_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-
+-  out_int32x2_t = vld1_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-
+-  out_int64x1_t = vld1_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-
+-  out_int8x8_t = vld1_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-
+-  out_uint16x4_t = vld1_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-
+-  out_uint32x2_t = vld1_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-
+-  out_uint64x1_t = vld1_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-
+-  out_uint8x8_t = vld1_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanep64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1f32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-
+-  out_float32x2_t = vld1_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1p16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-
+-  out_poly16x4_t = vld1_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1p64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-
+-  out_poly64x1_t = vld1_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-
+-  out_poly8x8_t = vld1_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-
+-  out_int16x4_t = vld1_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-
+-  out_int32x2_t = vld1_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-
+-  out_int64x1_t = vld1_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-
+-  out_int8x8_t = vld1_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-
+-  out_uint16x4_t = vld1_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-
+-  out_uint32x2_t = vld1_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-
+-  out_uint64x1_t = vld1_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-
+-  out_uint8x8_t = vld1_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanef32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4x2_t arg1_float32x4x2_t;
+-
+-  out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanep16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8x2_t arg1_poly16x8x2_t;
+-
+-  out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanes16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8x2_t arg1_int16x8x2_t;
+-
+-  out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanes32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4x2_t arg1_int32x4x2_t;
+-
+-  out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_laneu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8x2_t arg1_uint16x8x2_t;
+-
+-  out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_laneu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4x2_t arg1_uint32x4x2_t;
+-
+-  out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-
+-  out_float32x4x2_t = vld2q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-
+-  out_poly16x8x2_t = vld2q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-
+-  out_poly8x16x2_t = vld2q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-
+-  out_int16x8x2_t = vld2q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-
+-  out_int32x4x2_t = vld2q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-
+-  out_int8x16x2_t = vld2q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-
+-  out_uint16x8x2_t = vld2q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-
+-  out_uint32x4x2_t = vld2q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-
+-  out_uint8x16x2_t = vld2q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-
+-  out_float32x2x2_t = vld2_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-
+-  out_poly16x4x2_t = vld2_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupp64 (void)
+-{
+-  poly64x1x2_t out_poly64x1x2_t;
+-
+-  out_poly64x1x2_t = vld2_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-
+-  out_poly8x8x2_t = vld2_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-
+-  out_int16x4x2_t = vld2_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-
+-  out_int32x2x2_t = vld2_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups64 (void)
+-{
+-  int64x1x2_t out_int64x1x2_t;
+-
+-  out_int64x1x2_t = vld2_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-
+-  out_int8x8x2_t = vld2_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-
+-  out_uint16x4x2_t = vld2_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-
+-  out_uint32x2x2_t = vld2_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu64 (void)
+-{
+-  uint64x1x2_t out_uint64x1x2_t;
+-
+-  out_uint64x1x2_t = vld2_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-
+-  out_uint8x8x2_t = vld2_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanef32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2x2_t arg1_float32x2x2_t;
+-
+-  out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanep16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4x2_t arg1_poly16x4x2_t;
+-
+-  out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanep8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-
+-  out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanes16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4x2_t arg1_int16x4x2_t;
+-
+-  out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanes32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2x2_t arg1_int32x2x2_t;
+-
+-  out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanes8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-
+-  out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_laneu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4x2_t arg1_uint16x4x2_t;
+-
+-  out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_laneu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2x2_t arg1_uint32x2x2_t;
+-
+-  out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_laneu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-
+-  out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2f32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-
+-  out_float32x2x2_t = vld2_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2p16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-
+-  out_poly16x4x2_t = vld2_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2p64 (void)
+-{
+-  poly64x1x2_t out_poly64x1x2_t;
+-
+-  out_poly64x1x2_t = vld2_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2p8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-
+-  out_poly8x8x2_t = vld2_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-
+-  out_int16x4x2_t = vld2_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-
+-  out_int32x2x2_t = vld2_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s64 (void)
+-{
+-  int64x1x2_t out_int64x1x2_t;
+-
+-  out_int64x1x2_t = vld2_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-
+-  out_int8x8x2_t = vld2_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-
+-  out_uint16x4x2_t = vld2_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-
+-  out_uint32x2x2_t = vld2_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u64 (void)
+-{
+-  uint64x1x2_t out_uint64x1x2_t;
+-
+-  out_uint64x1x2_t = vld2_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-
+-  out_uint8x8x2_t = vld2_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanef32 (void)
+-{
+-  float32x4x3_t out_float32x4x3_t;
+-  float32x4x3_t arg1_float32x4x3_t;
+-
+-  out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanep16 (void)
+-{
+-  poly16x8x3_t out_poly16x8x3_t;
+-  poly16x8x3_t arg1_poly16x8x3_t;
+-
+-  out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanes16 (void)
+-{
+-  int16x8x3_t out_int16x8x3_t;
+-  int16x8x3_t arg1_int16x8x3_t;
+-
+-  out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanes32 (void)
+-{
+-  int32x4x3_t out_int32x4x3_t;
+-  int32x4x3_t arg1_int32x4x3_t;
+-
+-  out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_laneu16 (void)
+-{
+-  uint16x8x3_t out_uint16x8x3_t;
+-  uint16x8x3_t arg1_uint16x8x3_t;
+-
+-  out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_laneu32 (void)
+-{
+-  uint32x4x3_t out_uint32x4x3_t;
+-  uint32x4x3_t arg1_uint32x4x3_t;
+-
+-  out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qf32 (void)
+-{
+-  float32x4x3_t out_float32x4x3_t;
+-
+-  out_float32x4x3_t = vld3q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qp16 (void)
+-{
+-  poly16x8x3_t out_poly16x8x3_t;
+-
+-  out_poly16x8x3_t = vld3q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qp8 (void)
+-{
+-  poly8x16x3_t out_poly8x16x3_t;
+-
+-  out_poly8x16x3_t = vld3q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qs16 (void)
+-{
+-  int16x8x3_t out_int16x8x3_t;
+-
+-  out_int16x8x3_t = vld3q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qs32 (void)
+-{
+-  int32x4x3_t out_int32x4x3_t;
+-
+-  out_int32x4x3_t = vld3q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qs8 (void)
+-{
+-  int8x16x3_t out_int8x16x3_t;
+-
+-  out_int8x16x3_t = vld3q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qu16 (void)
+-{
+-  uint16x8x3_t out_uint16x8x3_t;
+-
+-  out_uint16x8x3_t = vld3q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qu32 (void)
+-{
+-  uint32x4x3_t out_uint32x4x3_t;
+-
+-  out_uint32x4x3_t = vld3q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qu8 (void)
+-{
+-  uint8x16x3_t out_uint8x16x3_t;
+-
+-  out_uint8x16x3_t = vld3q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupf32 (void)
+-{
+-  float32x2x3_t out_float32x2x3_t;
+-
+-  out_float32x2x3_t = vld3_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupp16 (void)
+-{
+-  poly16x4x3_t out_poly16x4x3_t;
+-
+-  out_poly16x4x3_t = vld3_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupp64 (void)
+-{
+-  poly64x1x3_t out_poly64x1x3_t;
+-
+-  out_poly64x1x3_t = vld3_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupp8 (void)
+-{
+-  poly8x8x3_t out_poly8x8x3_t;
+-
+-  out_poly8x8x3_t = vld3_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups16 (void)
+-{
+-  int16x4x3_t out_int16x4x3_t;
+-
+-  out_int16x4x3_t = vld3_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups32 (void)
+-{
+-  int32x2x3_t out_int32x2x3_t;
+-
+-  out_int32x2x3_t = vld3_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups64 (void)
+-{
+-  int64x1x3_t out_int64x1x3_t;
+-
+-  out_int64x1x3_t = vld3_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups8 (void)
+-{
+-  int8x8x3_t out_int8x8x3_t;
+-
+-  out_int8x8x3_t = vld3_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu16 (void)
+-{
+-  uint16x4x3_t out_uint16x4x3_t;
+-
+-  out_uint16x4x3_t = vld3_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu32 (void)
+-{
+-  uint32x2x3_t out_uint32x2x3_t;
+-
+-  out_uint32x2x3_t = vld3_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu64 (void)
+-{
+-  uint64x1x3_t out_uint64x1x3_t;
+-
+-  out_uint64x1x3_t = vld3_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu8 (void)
+-{
+-  uint8x8x3_t out_uint8x8x3_t;
+-
+-  out_uint8x8x3_t = vld3_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanef32 (void)
+-{
+-  float32x2x3_t out_float32x2x3_t;
+-  float32x2x3_t arg1_float32x2x3_t;
+-
+-  out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanep16 (void)
+-{
+-  poly16x4x3_t out_poly16x4x3_t;
+-  poly16x4x3_t arg1_poly16x4x3_t;
+-
+-  out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanep8 (void)
+-{
+-  poly8x8x3_t out_poly8x8x3_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-
+-  out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanes16 (void)
+-{
+-  int16x4x3_t out_int16x4x3_t;
+-  int16x4x3_t arg1_int16x4x3_t;
+-
+-  out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanes32 (void)
+-{
+-  int32x2x3_t out_int32x2x3_t;
+-  int32x2x3_t arg1_int32x2x3_t;
+-
+-  out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanes8 (void)
+-{
+-  int8x8x3_t out_int8x8x3_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-
+-  out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_laneu16 (void)
+-{
+-  uint16x4x3_t out_uint16x4x3_t;
+-  uint16x4x3_t arg1_uint16x4x3_t;
+-
+-  out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_laneu32 (void)
+-{
+-  uint32x2x3_t out_uint32x2x3_t;
+-  uint32x2x3_t arg1_uint32x2x3_t;
+-
+-  out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_laneu8 (void)
+-{
+-  uint8x8x3_t out_uint8x8x3_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-
+-  out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3f32 (void)
+-{
+-  float32x2x3_t out_float32x2x3_t;
+-
+-  out_float32x2x3_t = vld3_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3p16 (void)
+-{
+-  poly16x4x3_t out_poly16x4x3_t;
+-
+-  out_poly16x4x3_t = vld3_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3p64 (void)
+-{
+-  poly64x1x3_t out_poly64x1x3_t;
+-
+-  out_poly64x1x3_t = vld3_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3p8 (void)
+-{
+-  poly8x8x3_t out_poly8x8x3_t;
+-
+-  out_poly8x8x3_t = vld3_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s16 (void)
+-{
+-  int16x4x3_t out_int16x4x3_t;
+-
+-  out_int16x4x3_t = vld3_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s32 (void)
+-{
+-  int32x2x3_t out_int32x2x3_t;
+-
+-  out_int32x2x3_t = vld3_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s64 (void)
+-{
+-  int64x1x3_t out_int64x1x3_t;
+-
+-  out_int64x1x3_t = vld3_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s8 (void)
+-{
+-  int8x8x3_t out_int8x8x3_t;
+-
+-  out_int8x8x3_t = vld3_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u16 (void)
+-{
+-  uint16x4x3_t out_uint16x4x3_t;
+-
+-  out_uint16x4x3_t = vld3_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u32 (void)
+-{
+-  uint32x2x3_t out_uint32x2x3_t;
+-
+-  out_uint32x2x3_t = vld3_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u64 (void)
+-{
+-  uint64x1x3_t out_uint64x1x3_t;
+-
+-  out_uint64x1x3_t = vld3_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u8 (void)
+-{
+-  uint8x8x3_t out_uint8x8x3_t;
+-
+-  out_uint8x8x3_t = vld3_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanef32 (void)
+-{
+-  float32x4x4_t out_float32x4x4_t;
+-  float32x4x4_t arg1_float32x4x4_t;
+-
+-  out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanep16 (void)
+-{
+-  poly16x8x4_t out_poly16x8x4_t;
+-  poly16x8x4_t arg1_poly16x8x4_t;
+-
+-  out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanes16 (void)
+-{
+-  int16x8x4_t out_int16x8x4_t;
+-  int16x8x4_t arg1_int16x8x4_t;
+-
+-  out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanes32 (void)
+-{
+-  int32x4x4_t out_int32x4x4_t;
+-  int32x4x4_t arg1_int32x4x4_t;
+-
+-  out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_laneu16 (void)
+-{
+-  uint16x8x4_t out_uint16x8x4_t;
+-  uint16x8x4_t arg1_uint16x8x4_t;
+-
+-  out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_laneu32 (void)
+-{
+-  uint32x4x4_t out_uint32x4x4_t;
+-  uint32x4x4_t arg1_uint32x4x4_t;
+-
+-  out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qf32 (void)
+-{
+-  float32x4x4_t out_float32x4x4_t;
+-
+-  out_float32x4x4_t = vld4q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qp16 (void)
+-{
+-  poly16x8x4_t out_poly16x8x4_t;
+-
+-  out_poly16x8x4_t = vld4q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qp8 (void)
+-{
+-  poly8x16x4_t out_poly8x16x4_t;
+-
+-  out_poly8x16x4_t = vld4q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qs16 (void)
+-{
+-  int16x8x4_t out_int16x8x4_t;
+-
+-  out_int16x8x4_t = vld4q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qs32 (void)
+-{
+-  int32x4x4_t out_int32x4x4_t;
+-
+-  out_int32x4x4_t = vld4q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qs8 (void)
+-{
+-  int8x16x4_t out_int8x16x4_t;
+-
+-  out_int8x16x4_t = vld4q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qu16 (void)
+-{
+-  uint16x8x4_t out_uint16x8x4_t;
+-
+-  out_uint16x8x4_t = vld4q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qu32 (void)
+-{
+-  uint32x4x4_t out_uint32x4x4_t;
+-
+-  out_uint32x4x4_t = vld4q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qu8 (void)
+-{
+-  uint8x16x4_t out_uint8x16x4_t;
+-
+-  out_uint8x16x4_t = vld4q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupf32 (void)
+-{
+-  float32x2x4_t out_float32x2x4_t;
+-
+-  out_float32x2x4_t = vld4_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupp16 (void)
+-{
+-  poly16x4x4_t out_poly16x4x4_t;
+-
+-  out_poly16x4x4_t = vld4_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupp64 (void)
+-{
+-  poly64x1x4_t out_poly64x1x4_t;
+-
+-  out_poly64x1x4_t = vld4_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupp8 (void)
+-{
+-  poly8x8x4_t out_poly8x8x4_t;
+-
+-  out_poly8x8x4_t = vld4_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups16 (void)
+-{
+-  int16x4x4_t out_int16x4x4_t;
+-
+-  out_int16x4x4_t = vld4_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups32 (void)
+-{
+-  int32x2x4_t out_int32x2x4_t;
+-
+-  out_int32x2x4_t = vld4_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups64 (void)
+-{
+-  int64x1x4_t out_int64x1x4_t;
+-
+-  out_int64x1x4_t = vld4_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups8 (void)
+-{
+-  int8x8x4_t out_int8x8x4_t;
+-
+-  out_int8x8x4_t = vld4_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu16 (void)
+-{
+-  uint16x4x4_t out_uint16x4x4_t;
+-
+-  out_uint16x4x4_t = vld4_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu32 (void)
+-{
+-  uint32x2x4_t out_uint32x2x4_t;
+-
+-  out_uint32x2x4_t = vld4_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu64 (void)
+-{
+-  uint64x1x4_t out_uint64x1x4_t;
+-
+-  out_uint64x1x4_t = vld4_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu8 (void)
+-{
+-  uint8x8x4_t out_uint8x8x4_t;
+-
+-  out_uint8x8x4_t = vld4_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanef32 (void)
+-{
+-  float32x2x4_t out_float32x2x4_t;
+-  float32x2x4_t arg1_float32x2x4_t;
+-
+-  out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanep16 (void)
+-{
+-  poly16x4x4_t out_poly16x4x4_t;
+-  poly16x4x4_t arg1_poly16x4x4_t;
+-
+-  out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanep8 (void)
+-{
+-  poly8x8x4_t out_poly8x8x4_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-
+-  out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanes16 (void)
+-{
+-  int16x4x4_t out_int16x4x4_t;
+-  int16x4x4_t arg1_int16x4x4_t;
+-
+-  out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanes32 (void)
+-{
+-  int32x2x4_t out_int32x2x4_t;
+-  int32x2x4_t arg1_int32x2x4_t;
+-
+-  out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanes8 (void)
+-{
+-  int8x8x4_t out_int8x8x4_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-
+-  out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_laneu16 (void)
+-{
+-  uint16x4x4_t out_uint16x4x4_t;
+-  uint16x4x4_t arg1_uint16x4x4_t;
+-
+-  out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_laneu32 (void)
+-{
+-  uint32x2x4_t out_uint32x2x4_t;
+-  uint32x2x4_t arg1_uint32x2x4_t;
+-
+-  out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_laneu8 (void)
+-{
+-  uint8x8x4_t out_uint8x8x4_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-
+-  out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4f32 (void)
+-{
+-  float32x2x4_t out_float32x2x4_t;
+-
+-  out_float32x2x4_t = vld4_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4p16 (void)
+-{
+-  poly16x4x4_t out_poly16x4x4_t;
+-
+-  out_poly16x4x4_t = vld4_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4p64 (void)
+-{
+-  poly64x1x4_t out_poly64x1x4_t;
+-
+-  out_poly64x1x4_t = vld4_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4p8 (void)
+-{
+-  poly8x8x4_t out_poly8x8x4_t;
+-
+-  out_poly8x8x4_t = vld4_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s16 (void)
+-{
+-  int16x4x4_t out_int16x4x4_t;
+-
+-  out_int16x4x4_t = vld4_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s32 (void)
+-{
+-  int32x2x4_t out_int32x2x4_t;
+-
+-  out_int32x2x4_t = vld4_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s64 (void)
+-{
+-  int64x1x4_t out_int64x1x4_t;
+-
+-  out_int64x1x4_t = vld4_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s8 (void)
+-{
+-  int8x8x4_t out_int8x8x4_t;
+-
+-  out_int8x8x4_t = vld4_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u16 (void)
+-{
+-  uint16x4x4_t out_uint16x4x4_t;
+-
+-  out_uint16x4x4_t = vld4_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u32 (void)
+-{
+-  uint32x2x4_t out_uint32x2x4_t;
+-
+-  out_uint32x2x4_t = vld4_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u64 (void)
+-{
+-  uint64x1x4_t out_uint64x1x4_t;
+-
+-  out_uint64x1x4_t = vld4_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u8 (void)
+-{
+-  uint8x8x4_t out_uint8x8x4_t;
+-
+-  out_uint8x8x4_t = vld4_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmins16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmins16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmins32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmins32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmins8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmins8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_laneu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_laneu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlals16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlals32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlals8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlals8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlalu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlalu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlalu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlalu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlalu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlalu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlas16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlas16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlas32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlas32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlas8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlas8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlau16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlau16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlau32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlau32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlau8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlau8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_laneu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_laneu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlslu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlslu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlslu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlslu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlslu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlslu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmovQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmovQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmov_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmov_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovlu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovlu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovlu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32_t arg1_float32_t;
+-
+-  out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16_t arg1_uint16_t;
+-
+-  out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32_t arg1_uint32_t;
+-
+-  out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32_t arg1_float32_t;
+-
+-  out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16_t arg1_uint16_t;
+-
+-  out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32_t arg1_uint32_t;
+-
+-  out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_laneu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_laneu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16_t arg1_uint16_t;
+-
+-  out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32_t arg1_uint32_t;
+-
+-  out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullp8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmuls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmuls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmuls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmuls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmuls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmuls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x8_t out_int16x8_t;
+-int16x8_t arg0_int16x8_t;
+-int16x8_t arg1_int16x8_t;
+-void test_vornQs16 (void)
+-{
+-
+-  out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x4_t out_int32x4_t;
+-int32x4_t arg0_int32x4_t;
+-int32x4_t arg1_int32x4_t;
+-void test_vornQs32 (void)
+-{
+-
+-  out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x2_t out_int64x2_t;
+-int64x2_t arg0_int64x2_t;
+-int64x2_t arg1_int64x2_t;
+-void test_vornQs64 (void)
+-{
+-
+-  out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x16_t out_int8x16_t;
+-int8x16_t arg0_int8x16_t;
+-int8x16_t arg1_int8x16_t;
+-void test_vornQs8 (void)
+-{
+-
+-  out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x8_t out_uint16x8_t;
+-uint16x8_t arg0_uint16x8_t;
+-uint16x8_t arg1_uint16x8_t;
+-void test_vornQu16 (void)
+-{
+-
+-  out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x4_t out_uint32x4_t;
+-uint32x4_t arg0_uint32x4_t;
+-uint32x4_t arg1_uint32x4_t;
+-void test_vornQu32 (void)
+-{
+-
+-  out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x2_t out_uint64x2_t;
+-uint64x2_t arg0_uint64x2_t;
+-uint64x2_t arg1_uint64x2_t;
+-void test_vornQu64 (void)
+-{
+-
+-  out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x16_t out_uint8x16_t;
+-uint8x16_t arg0_uint8x16_t;
+-uint8x16_t arg1_uint8x16_t;
+-void test_vornQu8 (void)
+-{
+-
+-  out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x4_t out_int16x4_t;
+-int16x4_t arg0_int16x4_t;
+-int16x4_t arg1_int16x4_t;
+-void test_vorns16 (void)
+-{
+-
+-  out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x2_t out_int32x2_t;
+-int32x2_t arg0_int32x2_t;
+-int32x2_t arg1_int32x2_t;
+-void test_vorns32 (void)
+-{
+-
+-  out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vorns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x1_t out_int64x1_t;
+-int64x1_t arg0_int64x1_t;
+-int64x1_t arg1_int64x1_t;
+-void test_vorns64 (void)
+-{
+-
+-  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x8_t out_int8x8_t;
+-int8x8_t arg0_int8x8_t;
+-int8x8_t arg1_int8x8_t;
+-void test_vorns8 (void)
+-{
+-
+-  out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x4_t out_uint16x4_t;
+-uint16x4_t arg0_uint16x4_t;
+-uint16x4_t arg1_uint16x4_t;
+-void test_vornu16 (void)
+-{
+-
+-  out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x2_t out_uint32x2_t;
+-uint32x2_t arg0_uint32x2_t;
+-uint32x2_t arg1_uint32x2_t;
+-void test_vornu32 (void)
+-{
+-
+-  out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vornu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x1_t out_uint64x1_t;
+-uint64x1_t arg0_uint64x1_t;
+-uint64x1_t arg1_uint64x1_t;
+-void test_vornu64 (void)
+-{
+-
+-  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x8_t out_uint8x8_t;
+-uint8x8_t arg0_uint8x8_t;
+-uint8x8_t arg1_uint8x8_t;
+-void test_vornu8 (void)
+-{
+-
+-  out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vorrs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorru16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorru32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vorru64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorru8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQs16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQs32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQs8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadals16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadals32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadals8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadals8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalu16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalu32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalu8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQs16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQs32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQs8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddls16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddls32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddls8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlu16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlu32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlu8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmins16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmins16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmins32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmins32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmins8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmins8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrun_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrun_ns16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrun_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrun_ns32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrun_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrun_ns64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlals16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlals32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovuns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovuns16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovuns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovuns32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovuns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovuns64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrun_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrun_ns16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrun_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrun_ns32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrun_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrun_ns64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpeQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpeQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpeQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpeQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpeu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpeu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrecpsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrecpsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p128 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p64 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p8 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s64 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s8 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u64 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u8 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_f32 (void)
+-{
+-  poly128_t out_poly128_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_p16 (void)
+-{
+-  poly128_t out_poly128_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_p64 (void)
+-{
+-  poly128_t out_poly128_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_p8 (void)
+-{
+-  poly128_t out_poly128_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s16 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s32 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s64 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s8 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u16 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u32 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u64 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u8 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_f32 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_p128 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_p64 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_p8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s32 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s64 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u32 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u64 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_f32 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_p128 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_p16 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_p8 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s16 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s32 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s8 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u16 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u32 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u8 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_f32 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_p128 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_p16 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_p64 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s16 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s32 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s64 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u16 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u32 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u64 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_f32 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p128 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p64 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_s32 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_s64 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_s8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u32 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u64 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_f32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p128 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p64 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p8 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_s16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_s64 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_s8 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u64 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u8 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_f32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p128 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p16 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p8 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_s16 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_s32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_s8 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u16 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u8 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_f32 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p128 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p16 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p64 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_s16 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_s32 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_s64 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u16 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u32 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u64 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_f32 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p128 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p64 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s32 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s64 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_u32 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_u64 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_u8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_f32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p128 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p64 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p8 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s64 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s8 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_u16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_u64 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_u8 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_f32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p128 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p16 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p8 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s16 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s8 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_u16 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_u32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_u8 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_f32 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p128 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p16 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p64 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s16 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s32 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s64 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_u16 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_u32 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_u64 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_p16 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_p64 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_p8 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s16 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s64 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s8 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u16 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u64 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u8 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_f32 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_p64 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_p8 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s32 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s64 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s8 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u32 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u64 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u8 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_f32 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_p16 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_p8 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s16 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s32 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s8 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u16 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u32 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u8 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_f32 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_p16 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_p64 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s16 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s32 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s64 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u16 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u32 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u64 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_f32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_p16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_p64 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_p8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_s32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_s64 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_s8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u64 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_f32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_p16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_p64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_p8 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_s16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_s64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_s8 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u8 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_f32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_p16 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_p64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_p8 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_s16 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_s32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_s8 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u16 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u8 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_f32 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_p16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_p64 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_p8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_s16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_s32 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_s64 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u32 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u64 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_f32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_p16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_p64 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_p8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s64 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_u32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_u64 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_u8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_f32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_p16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_p64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_p8 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s8 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_u16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_u64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_u8 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_f32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_p16 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_p64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_p8 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s16 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s8 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_u16 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_u32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_u8 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_f32 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_p16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_p64 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_p8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s32 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s64 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_u16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_u32 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_u64 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32p16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32s16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32u16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64f32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64p16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64s16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64s32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64u16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64u32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndaf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndaf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrnda_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrinta\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndaq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndaqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndaq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrinta\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrnd_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintz\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndmf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndmf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrndm_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintm\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndmq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndmqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndmq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintm\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndnf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndnf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrndn_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintn\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndnq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndnqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndnq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintn\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndpf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndpf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrndp_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintp\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndpq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndpqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndpq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintp\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndqf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintz\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrteQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrteQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrteQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrteQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrtef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrtef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrteu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrteu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrsqrtsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrtsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrsqrtsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrtsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32_t arg0_float32_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16_t arg0_poly16_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8_t arg0_poly8_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16_t arg0_int16_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32_t arg0_int32_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64_t arg0_int64_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8_t arg0_int8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16_t arg0_uint16_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32_t arg0_uint32_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64_t arg0_uint64_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8_t arg0_uint8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32_t arg0_float32_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16_t arg0_poly16_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8_t arg0_poly8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16_t arg0_int16_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32_t arg0_int32_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vset_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64_t arg0_int64_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8_t arg0_int8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16_t arg0_uint16_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32_t arg0_uint32_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vset_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8_t arg0_uint8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_ns8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_nu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_np64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_np64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_np64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_np64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanep64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c
++++ b/src//dev/null
+@@ -1,25 +0,0 @@
+-/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+-
+-/* Detect ICE in the case of unaligned memory address.  */
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-unsigned char dummy_store[1000];
+-
+-void
+-foo (char* addr)
+-{
+-  uint8x16_t vdata = vld1q_u8 (addr);
+-  vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);
+-}
+-
+-uint64_t
+-bar (uint64x2_t vdata)
+-{
+-  vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);
+-  return vgetq_lane_u64 (vdata, 0);
+-}
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qp64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanep64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  vst1_p64 (arg0_poly64_t, arg1_poly64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x2_t arg1_float32x4x2_t;
+-
+-  vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x2_t arg1_poly16x8x2_t;
+-
+-  vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x2_t arg1_int16x8x2_t;
+-
+-  vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x2_t arg1_int32x4x2_t;
+-
+-  vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x2_t arg1_uint16x8x2_t;
+-
+-  vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x2_t arg1_uint32x4x2_t;
+-
+-  vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x2_t arg1_float32x4x2_t;
+-
+-  vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x2_t arg1_poly16x8x2_t;
+-
+-  vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16x2_t arg1_poly8x16x2_t;
+-
+-  vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x2_t arg1_int16x8x2_t;
+-
+-  vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x2_t arg1_int32x4x2_t;
+-
+-  vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16x2_t arg1_int8x16x2_t;
+-
+-  vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x2_t arg1_uint16x8x2_t;
+-
+-  vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x2_t arg1_uint32x4x2_t;
+-
+-  vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16x2_t arg1_uint8x16x2_t;
+-
+-  vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x2_t arg1_float32x2x2_t;
+-
+-  vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x2_t arg1_poly16x4x2_t;
+-
+-  vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-
+-  vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x2_t arg1_int16x4x2_t;
+-
+-  vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x2_t arg1_int32x2x2_t;
+-
+-  vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-
+-  vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x2_t arg1_uint16x4x2_t;
+-
+-  vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x2_t arg1_uint32x2x2_t;
+-
+-  vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-
+-  vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x2_t arg1_float32x2x2_t;
+-
+-  vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x2_t arg1_poly16x4x2_t;
+-
+-  vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1x2_t arg1_poly64x1x2_t;
+-
+-  vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-
+-  vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x2_t arg1_int16x4x2_t;
+-
+-  vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x2_t arg1_int32x2x2_t;
+-
+-  vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1x2_t arg1_int64x1x2_t;
+-
+-  vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-
+-  vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x2_t arg1_uint16x4x2_t;
+-
+-  vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x2_t arg1_uint32x2x2_t;
+-
+-  vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1x2_t arg1_uint64x1x2_t;
+-
+-  vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-
+-  vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x3_t arg1_float32x4x3_t;
+-
+-  vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x3_t arg1_poly16x8x3_t;
+-
+-  vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x3_t arg1_int16x8x3_t;
+-
+-  vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x3_t arg1_int32x4x3_t;
+-
+-  vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x3_t arg1_uint16x8x3_t;
+-
+-  vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x3_t arg1_uint32x4x3_t;
+-
+-  vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x3_t arg1_float32x4x3_t;
+-
+-  vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x3_t arg1_poly16x8x3_t;
+-
+-  vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16x3_t arg1_poly8x16x3_t;
+-
+-  vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x3_t arg1_int16x8x3_t;
+-
+-  vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x3_t arg1_int32x4x3_t;
+-
+-  vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16x3_t arg1_int8x16x3_t;
+-
+-  vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x3_t arg1_uint16x8x3_t;
+-
+-  vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x3_t arg1_uint32x4x3_t;
+-
+-  vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16x3_t arg1_uint8x16x3_t;
+-
+-  vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x3_t arg1_float32x2x3_t;
+-
+-  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x3_t arg1_poly16x4x3_t;
+-
+-  vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-
+-  vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x3_t arg1_int16x4x3_t;
+-
+-  vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x3_t arg1_int32x2x3_t;
+-
+-  vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-
+-  vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x3_t arg1_uint16x4x3_t;
+-
+-  vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x3_t arg1_uint32x2x3_t;
+-
+-  vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-
+-  vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x3_t arg1_float32x2x3_t;
+-
+-  vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x3_t arg1_poly16x4x3_t;
+-
+-  vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1x3_t arg1_poly64x1x3_t;
+-
+-  vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-
+-  vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x3_t arg1_int16x4x3_t;
+-
+-  vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x3_t arg1_int32x2x3_t;
+-
+-  vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1x3_t arg1_int64x1x3_t;
+-
+-  vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-
+-  vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x3_t arg1_uint16x4x3_t;
+-
+-  vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x3_t arg1_uint32x2x3_t;
+-
+-  vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1x3_t arg1_uint64x1x3_t;
+-
+-  vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-
+-  vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x4_t arg1_float32x4x4_t;
+-
+-  vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x4_t arg1_poly16x8x4_t;
+-
+-  vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x4_t arg1_int16x8x4_t;
+-
+-  vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x4_t arg1_int32x4x4_t;
+-
+-  vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x4_t arg1_uint16x8x4_t;
+-
+-  vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x4_t arg1_uint32x4x4_t;
+-
+-  vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x4_t arg1_float32x4x4_t;
+-
+-  vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x4_t arg1_poly16x8x4_t;
+-
+-  vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16x4_t arg1_poly8x16x4_t;
+-
+-  vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x4_t arg1_int16x8x4_t;
+-
+-  vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x4_t arg1_int32x4x4_t;
+-
+-  vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16x4_t arg1_int8x16x4_t;
+-
+-  vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x4_t arg1_uint16x8x4_t;
+-
+-  vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x4_t arg1_uint32x4x4_t;
+-
+-  vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16x4_t arg1_uint8x16x4_t;
+-
+-  vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x4_t arg1_float32x2x4_t;
+-
+-  vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x4_t arg1_poly16x4x4_t;
+-
+-  vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-
+-  vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x4_t arg1_int16x4x4_t;
+-
+-  vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x4_t arg1_int32x2x4_t;
+-
+-  vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-
+-  vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x4_t arg1_uint16x4x4_t;
+-
+-  vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x4_t arg1_uint32x2x4_t;
+-
+-  vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-
+-  vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x4_t arg1_float32x2x4_t;
+-
+-  vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x4_t arg1_poly16x4x4_t;
+-
+-  vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1x4_t arg1_poly64x1x4_t;
+-
+-  vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-
+-  vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x4_t arg1_int16x4x4_t;
+-
+-  vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x4_t arg1_int32x2x4_t;
+-
+-  vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1x4_t arg1_int64x1x4_t;
+-
+-  vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-
+-  vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x4_t arg1_uint16x4x4_t;
+-
+-  vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x4_t arg1_uint32x2x4_t;
+-
+-  vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1x4_t arg1_uint64x1x4_t;
+-
+-  vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-
+-  vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsublu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsublu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsublu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsublu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsublu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsublu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vsubs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vsubu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubws16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubws16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubws32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubws32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubws8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubws8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubwu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubwu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubwu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubwu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubwu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubwu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl1p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl1s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl1u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl2p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8x2_t arg0_poly8x8x2_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl2s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8x2_t arg0_int8x8x2_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl2u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8x2_t arg0_uint8x8x2_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl3p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8x3_t arg0_poly8x8x3_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl3s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8x3_t arg0_int8x8x3_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl3u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8x3_t arg0_uint8x8x3_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl4p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8x4_t arg0_poly8x8x4_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl4s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8x4_t arg0_int8x8x4_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl4u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8x4_t arg0_uint8x8x4_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx1p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx1s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx1u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx2p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx2s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx2u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx3p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx3s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx3u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx4p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx4s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx4u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrns16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrns32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrns8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQp8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstp8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtsts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtsts16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtsts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtsts32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtsts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtsts8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzps16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzps16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzps32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzps32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzps8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzps8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzips16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzips16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzips32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzips32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzips8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzips8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-1.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile } */
++/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-*} { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
++/* { dg-options "-march=armv6-m" } */
++
++/* Check that -mthumb is not needed when compiling for a Thumb-only target.  */
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-2.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile } */
++/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-*} { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
++/* { dg-options "-mcpu=cortex-m4" } */
++
++/* Check that -mthumb is not needed when compiling for a Thumb-only target.  */
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-3.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-skip-if "-mthumb given" { *-*-*} { "-mthumb" } } */
++/* { dg-options "-marm" } */
++/* { dg-error "target CPU does not support ARM mode" "missing error with -marm on Thumb-only targets" { target *-*-*} 0 } */
++
++/* Check that -marm gives an error when compiling for a Thumb-only target.  */
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/polytypes.c
+@@ -0,0 +1,48 @@
++/* Check that NEON polynomial vector types are suitably incompatible with
++   integer vector types of the same layout.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++void s64_8 (int8x8_t a) {}
++void u64_8 (uint8x8_t a) {}
++void p64_8 (poly8x8_t a) {}
++void s64_16 (int16x4_t a) {}
++void u64_16 (uint16x4_t a) {}
++void p64_16 (poly16x4_t a) {}
++
++void s128_8 (int8x16_t a) {}
++void u128_8 (uint8x16_t a) {}
++void p128_8 (poly8x16_t a) {}
++void s128_16 (int16x8_t a) {}
++void u128_16 (uint16x8_t a) {}
++void p128_16 (poly16x8_t a) {}
++
++void foo ()
++{
++  poly8x8_t v64_8;
++  poly16x4_t v64_16;
++  poly8x16_t v128_8;
++  poly16x8_t v128_16;
++
++  s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
++  /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
++  u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
++  p64_8 (v64_8);
++
++  s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
++  u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
++  p64_16 (v64_16);
++
++  s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
++  u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
++  p128_8 (v128_8);
++
++  s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
++  u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
++  p128_16 (v128_16);
++}
++/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pr37780_1.c
+@@ -0,0 +1,48 @@
++/* Test that we can remove the conditional move due to CLZ
++   being defined at zero.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v6t2_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v6t2 } */
++
++int
++fooctz (int i)
++{
++  return (i == 0) ? 32 : __builtin_ctz (i);
++}
++
++int
++fooctz2 (int i)
++{
++  return (i != 0) ? __builtin_ctz (i) : 32;
++}
++
++unsigned int
++fooctz3 (unsigned int i)
++{
++  return (i > 0) ?  __builtin_ctz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "rbit\t*" 3 } } */
++
++int
++fooclz (int i)
++{
++  return (i == 0) ? 32 : __builtin_clz (i);
++}
++
++int
++fooclz2 (int i)
++{
++  return (i != 0) ? __builtin_clz (i) : 32;
++}
++
++unsigned int
++fooclz3 (unsigned int i)
++{
++  return (i > 0) ? __builtin_clz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "clz\t" 6 } } */
++/* { dg-final { scan-assembler-not "cmp\t.*0" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/pr42574.c
++++ b/src/gcc/testsuite/gcc.target/arm/pr42574.c
+@@ -1,5 +1,5 @@
++/* { dg-do compile { target { arm_thumb1_ok && { ! arm_thumb1_movt_ok } } } } */
+ /* { dg-options "-mthumb -Os -fpic" }  */
+-/* { dg-require-effective-target arm_thumb1_ok } */
+ /* { dg-require-effective-target fpic } */
+ /* Make sure the address of glob.c is calculated only once and using
+    a logical shift for the offset (200<<1).  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pr51534.c
+@@ -0,0 +1,83 @@
++/* Test the vector comparison intrinsics when comparing to immediate zero.
++   */
++
++/* { dg-do assemble } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++#define GEN_TEST(T, D, C, R) \
++  R test_##C##_##T (T a) { return C (a, D (0)); }
++
++#define GEN_DOUBLE_TESTS(S, T, C) \
++  GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
++  GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) 
++
++#define GEN_QUAD_TESTS(S, T, C) \
++  GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
++  GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) 
++
++#define GEN_COND_TESTS(C) \
++  GEN_DOUBLE_TESTS (8, int8x8_t, C) \
++  GEN_DOUBLE_TESTS (16, int16x4_t, C) \
++  GEN_DOUBLE_TESTS (32, int32x2_t, C) \
++  GEN_QUAD_TESTS (8, int8x16_t, C) \
++  GEN_QUAD_TESTS (16, int16x8_t, C) \
++  GEN_QUAD_TESTS (32, int32x4_t, C)
++
++GEN_COND_TESTS(vcgt)
++GEN_COND_TESTS(vcge)
++GEN_COND_TESTS(vclt)
++GEN_COND_TESTS(vcle)
++GEN_COND_TESTS(vceq)
++
++/* Scan for expected outputs.  */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++
++/* And ensure we don't have unexpected output too.  */
++/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ 	\]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
++
++/* Tidy up.  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pr79145.c
+@@ -0,0 +1,16 @@
++/* { dg-do compile } */
++/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
++/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
++/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
++/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
++/* { dg-require-effective-target arm32 } */
++/* { dg-require-effective-target arm_iwmmxt_ok } */
++/* { dg-options "-mcpu=iwmmxt" } */
++
++int
++main (void)
++{
++  volatile long long t1;
++  t1 ^= 0x55;
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/short-vfp-1.c
+@@ -0,0 +1,45 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok }
++/* { dg-options "-mfpu=vfp" } */
++
++int
++test_sisf (float x)
++{
++  return (int)x;
++}
++
++short
++test_hisf (float x)
++{
++  return (short)x;
++}
++
++float
++test_sfsi (int x)
++{
++  return (float)x;
++}
++
++float
++test_sfhi (short x)
++{
++  return (float)x;
++}
++
++short
++test_hisi (int x)
++{
++  return (short)x;
++}
++
++int
++test_sihi (short x)
++{
++  return (int)x;
++}
++
++/* {dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vmaxnm_f32_1.c
+@@ -0,0 +1,159 @@
++/* Test the `vmaxnmf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {3,4};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != b1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2};
++  float32_t b1[] = {1,4};
++  float32_t e[] = {3,4};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vmaxnm returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vmaxnm returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2};
++  float32_t b1[] = {1,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__zero_both_args ()
++{
++  /* For 0 and -0, vmaxnm returns 0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0, 0.0};
++  float32_t b1[] = {-0.0, -0.0};
++  float32_t e[] = {0.0, 0.0};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) != 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__inf_both_args ()
++{
++  /* The max of inf and inf is inf.  The max of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf};
++  float32_t b1[] = {inf, -inf};
++  float32_t e[] = {inf, -inf};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {n,n};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vmaxnm_f32__regular_input1 ();
++  test_vmaxnm_f32__regular_input2 ();
++  test_vmaxnm_f32__quiet_NaN_one_arg ();
++  test_vmaxnm_f32__quiet_NaN_both_args ();
++  test_vmaxnm_f32__zero_both_args ();
++  test_vmaxnm_f32__inf_both_args ();
++  test_vmaxnm_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vmaxnm\.f32\t\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" 7 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vmaxnmq_f32_1.c
+@@ -0,0 +1,160 @@
++/* Test the `vmaxnmqf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2,5,6};
++  float32_t b1[] = {3,4,7,8};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != b1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2,7,6};
++  float32_t b1[] = {1,4,5,8};
++  float32_t e[] = {3,4,7,8};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vmaxnmq returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2,3,4};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vmaxnmq returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2,n,4};
++  float32_t b1[] = {1,n,3,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__zero_both_args ()
++{
++  /* For 0 and -0, vmaxnmq returns 0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0, 0.0, -0.0, -0.0};
++  float32_t b1[] = {-0.0, -0.0, 0.0, 0.0};
++  float32_t e[] = {0.0, 0.0, 0.0, 0.0};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) != 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__inf_both_args ()
++{
++  /* The max of inf and inf is inf.  The max of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf, inf, inf};
++  float32_t b1[] = {inf, -inf, -inf, -inf};
++  float32_t e[] = {inf, -inf, inf, inf};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n,n,n};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {n,n};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vmaxnmq_f32__regular_input1 ();
++  test_vmaxnmq_f32__regular_input2 ();
++  test_vmaxnmq_f32__quiet_NaN_one_arg ();
++  test_vmaxnmq_f32__quiet_NaN_both_args ();
++  test_vmaxnmq_f32__zero_both_args ();
++  test_vmaxnmq_f32__inf_both_args ();
++  test_vmaxnmq_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vmaxnm\.f32\t\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+\n" 7 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vminnm_f32_1.c
+@@ -0,0 +1,159 @@
++/* Test the `vminnmf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vminnm_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {3,4};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != a1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2};
++  float32_t b1[] = {1,4};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vminnm returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vminnm returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2};
++  float32_t b1[] = {1,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__zero_both_args ()
++{
++  /* For 0 and -0, vminnm returns -0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0,0.0};
++  float32_t b1[] = {-0.0, -0.0};
++  float32_t e[] = {-0.0, -0.0};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) == 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__inf_both_args ()
++{
++  /* The min of inf and inf is inf.  The min of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf};
++  float32_t b1[] = {inf, -inf};
++  float32_t e[] = {inf, -inf};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {n,n};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vminnm_f32__regular_input1 ();
++  test_vminnm_f32__regular_input2 ();
++  test_vminnm_f32__quiet_NaN_one_arg ();
++  test_vminnm_f32__quiet_NaN_both_args ();
++  test_vminnm_f32__zero_both_args ();
++  test_vminnm_f32__inf_both_args ();
++  test_vminnm_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vminnm\.f32\t\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" 7 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vminnmq_f32_1.c
+@@ -0,0 +1,159 @@
++/* Test the `vminnmqf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2,5,6};
++  float32_t b1[] = {3,4,7,8};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != a1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2,7,6};
++  float32_t b1[] = {1,4,5,8};
++  float32_t e[] = {1,2,5,6};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vminnmq returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2,3,4};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vminnmq returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2,n,4};
++  float32_t b1[] = {1,n,3,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__zero_both_args ()
++{
++  /* For 0 and -0, vminnmq returns -0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0, 0.0, -0.0, -0.0};
++  float32_t b1[] = {-0.0, -0.0, 0.0, 0.0};
++  float32_t e[] = {-0.0, -0.0, -0.0, -0.0};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) == 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__inf_both_args ()
++{
++  /* The min of inf and inf is inf.  The min of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf, inf, inf};
++  float32_t b1[] = {inf, -inf, -inf, -inf};
++  float32_t e[] = {inf, -inf, -inf, -inf};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n,n,n};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {n,n};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vminnmq_f32__regular_input1 ();
++  test_vminnmq_f32__regular_input2 ();
++  test_vminnmq_f32__quiet_NaN_one_arg ();
++  test_vminnmq_f32__quiet_NaN_both_args ();
++  test_vminnmq_f32__zero_both_args ();
++  test_vminnmq_f32__inf_both_args ();
++  test_vminnmq_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vminnm\.f32\t\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+\n" 7 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vect-vcvt.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
++/* { dg-add-options arm_neon } */
++
++#define N 32
++
++int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
++float fa[N];
++int ia[N];
++
++int convert()
++{
++  int i;
++
++  /* int -> float */
++  for (i = 0; i < N; i++)
++    fa[i] = (float) ib[i];
++
++  /* float -> int */
++  for (i = 0; i < N; i++)
++    ia[i] = (int) fa[i];
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vect-vcvtq.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
++/* { dg-add-options arm_neon } */
++
++#define N 32
++
++int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
++float fa[N];
++int ia[N];
++
++int convert()
++{
++  int i;
++
++  /* int -> float */
++  for (i = 0; i < N; i++)
++    fa[i] = (float) ib[i];
++
++  /* float -> int */
++  for (i = 0; i < N; i++)
++    ia[i] = (int) fa[i];
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vfp-shift-a2t2.c
+@@ -0,0 +1,27 @@
++/* Check that NEON vector shifts support immediate values == size.  /*
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-save-temps" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint16x8_t test_vshll_n_u8 (uint8x8_t a)
++{
++    return vshll_n_u8(a, 8);
++}
++
++uint32x4_t test_vshll_n_u16 (uint16x4_t a)
++{   
++    return vshll_n_u16(a, 16);
++}
++
++uint64x2_t test_vshll_n_u32 (uint32x2_t a)
++{
++    return vshll_n_u32(a, 32);
++}
++
++/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vst1Q_laneu64-1.c
+@@ -0,0 +1,25 @@
++/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
++
++/* Detect ICE in the case of unaligned memory address.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++unsigned char dummy_store[1000];
++
++void
++foo (unsigned char* addr)
++{
++  uint8x16_t vdata = vld1q_u8 (addr);
++  vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);
++}
++
++uint64_t
++bar (uint64x2_t vdata)
++{
++  vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);
++  return vgetq_lane_u64 (vdata, 0);
++}
+--- a/src/gcc/testsuite/lib/gcc-dg.exp
++++ b/src/gcc/testsuite/lib/gcc-dg.exp
+@@ -403,6 +403,7 @@ if { [info procs ${tool}_load] != [list] \
+ 	    switch [lindex $result 0] {
+ 		"pass" { set status "fail" }
+ 		"fail" { set status "pass" }
++		default { set status [lindex $result 0] }
+ 	    }
+ 	    set result [list $status [lindex $result 1]]
+ 	}
+--- a/src/gcc/testsuite/lib/target-supports.exp
++++ b/src/gcc/testsuite/lib/target-supports.exp
+@@ -2936,6 +2936,28 @@ proc add_options_for_arm_v8_1a_neon { flags } {
+     return "$flags $et_arm_v8_1a_neon_flags -march=armv8.1-a"
+ }
+ 
++# Add the options needed for ARMv8.2 with the scalar FP16 extension.
++# Also adds the ARMv8 FP options for ARM and for AArch64.
++
++proc add_options_for_arm_v8_2a_fp16_scalar { flags } {
++    if { ! [check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
++	return "$flags"
++    }
++    global et_arm_v8_2a_fp16_scalar_flags
++    return "$flags $et_arm_v8_2a_fp16_scalar_flags"
++}
++
++# Add the options needed for ARMv8.2 with the FP16 extension.  Also adds
++# the ARMv8 NEON options for ARM and for AArch64.
++
++proc add_options_for_arm_v8_2a_fp16_neon { flags } {
++    if { ! [check_effective_target_arm_v8_2a_fp16_neon_ok] } {
++	return "$flags"
++    }
++    global et_arm_v8_2a_fp16_neon_flags
++    return "$flags $et_arm_v8_2a_fp16_neon_flags"
++}
++
+ proc add_options_for_arm_crc { flags } {
+     if { ! [check_effective_target_arm_crc_ok] } {
+         return "$flags"
+@@ -3022,23 +3044,25 @@ proc check_effective_target_arm_crc_ok { } {
+ 
+ proc check_effective_target_arm_neon_fp16_ok_nocache { } {
+     global et_arm_neon_fp16_flags
++    global et_arm_neon_flags
+     set et_arm_neon_fp16_flags ""
+-    if { [check_effective_target_arm32] } {
++    if { [check_effective_target_arm32]
++	 && [check_effective_target_arm_neon_ok] } {
+ 	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
+ 		       "-mfpu=neon-fp16 -mfloat-abi=softfp"
+ 		       "-mfp16-format=ieee"
+ 		       "-mfloat-abi=softfp -mfp16-format=ieee"
+ 		       "-mfpu=neon-fp16 -mfp16-format=ieee"
+ 		       "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
+-	    if { [check_no_compiler_messages_nocache arm_neon_fp_16_ok object {
++	    if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
+ 		#include "arm_neon.h"
+ 		float16x4_t
+ 		foo (float32x4_t arg)
+ 		{
+                   return vcvt_f16_f32 (arg);
+ 		}
+-	    } "$flags"] } {
+-		set et_arm_neon_fp16_flags $flags
++	    } "$et_arm_neon_flags $flags"] } {
++		set et_arm_neon_fp16_flags [concat $et_arm_neon_flags $flags]
+ 		return 1
+ 	    }
+ 	}
+@@ -3075,6 +3099,65 @@ proc add_options_for_arm_neon_fp16 { flags } {
+     return "$flags $et_arm_neon_fp16_flags"
+ }
+ 
++# Return 1 if this is an ARM target supporting the FP16 alternative
++# format.  Some multilibs may be incompatible with the options needed.  Also
++# set et_arm_neon_fp16_flags to the best options to add.
++
++proc check_effective_target_arm_fp16_alternative_ok_nocache { } {
++    global et_arm_neon_fp16_flags
++    set et_arm_neon_fp16_flags ""
++    if { [check_effective_target_arm32] } {
++	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
++		       "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
++	    if { [check_no_compiler_messages_nocache \
++		      arm_fp16_alternative_ok object {
++		#if !defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++		#error __ARM_FP16_FORMAT_ALTERNATIVE not defined
++		#endif
++	    } "$flags -mfp16-format=alternative"] } {
++		set et_arm_neon_fp16_flags "$flags -mfp16-format=alternative"
++		return 1
++	    }
++	}
++    }
++
++    return 0
++}
++
++proc check_effective_target_arm_fp16_alternative_ok { } {
++    return [check_cached_effective_target arm_fp16_alternative_ok \
++		check_effective_target_arm_fp16_alternative_ok_nocache]
++}
++
++# Return 1 if this is an ARM target supports specifying the FP16 none
++# format.  Some multilibs may be incompatible with the options needed.
++
++proc check_effective_target_arm_fp16_none_ok_nocache { } {
++    if { [check_effective_target_arm32] } {
++	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
++		       "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
++	    if { [check_no_compiler_messages_nocache \
++		      arm_fp16_none_ok object {
++		#if defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++		#error __ARM_FP16_FORMAT_ALTERNATIVE defined
++		#endif
++		#if defined (__ARM_FP16_FORMAT_IEEE)
++		#error __ARM_FP16_FORMAT_IEEE defined
++		#endif
++	    } "$flags -mfp16-format=none"] } {
++		return 1
++	    }
++	}
++    }
++
++    return 0
++}
++
++proc check_effective_target_arm_fp16_none_ok { } {
++    return [check_cached_effective_target arm_fp16_none_ok \
++		check_effective_target_arm_fp16_none_ok_nocache]
++}
++
+ # Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
+ # -mfloat-abi=softfp or equivalent options.  Some multilibs may be
+ # incompatible with these options.  Also set et_arm_v8_neon_flags to the
+@@ -3117,8 +3200,10 @@ proc check_effective_target_arm_v8_neon_ok { } {
+ 
+ proc check_effective_target_arm_neonv2_ok_nocache { } {
+     global et_arm_neonv2_flags
++    global et_arm_neon_flags
+     set et_arm_neonv2_flags ""
+-    if { [check_effective_target_arm32] } {
++    if { [check_effective_target_arm32]
++	 && [check_effective_target_arm_neon_ok] } {
+ 	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
+ 	    if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
+ 		#include "arm_neon.h"
+@@ -3127,8 +3212,8 @@ proc check_effective_target_arm_neonv2_ok_nocache { } {
+                 {
+                   return vfma_f32 (a, b, c);
+                 }
+-	    } "$flags"] } {
+-		set et_arm_neonv2_flags $flags
++	    } "$et_arm_neon_flags $flags"] } {
++		set et_arm_neonv2_flags [concat $et_arm_neon_flags $flags]
+ 		return 1
+ 	    }
+ 	}
+@@ -3142,9 +3227,9 @@ proc check_effective_target_arm_neonv2_ok { } {
+ 		check_effective_target_arm_neonv2_ok_nocache]
+ }
+ 
+-# Add the options needed for NEON.  We need either -mfloat-abi=softfp
+-# or -mfloat-abi=hard, but if one is already specified by the
+-# multilib, use it.
++# Add the options needed for VFP FP16 support.  We need either
++# -mfloat-abi=softfp or -mfloat-abi=hard.  If one is already specified by
++# the multilib, use it.
+ 
+ proc add_options_for_arm_fp16 { flags } {
+     if { ! [check_effective_target_arm_fp16_ok] } {
+@@ -3154,9 +3239,32 @@ proc add_options_for_arm_fp16 { flags } {
+     return "$flags $et_arm_fp16_flags"
+ }
+ 
++# Add the options needed to enable support for IEEE format
++# half-precision support.  This is valid for ARM targets.
++
++proc add_options_for_arm_fp16_ieee { flags } {
++    if { ! [check_effective_target_arm_fp16_ok] } {
++	return "$flags"
++    }
++    global et_arm_fp16_flags
++    return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
++}
++
++# Add the options needed to enable support for ARM Alternative format
++# half-precision support.  This is valid for ARM targets.
++
++proc add_options_for_arm_fp16_alternative { flags } {
++    if { ! [check_effective_target_arm_fp16_ok] } {
++	return "$flags"
++    }
++    global et_arm_fp16_flags
++    return "$flags $et_arm_fp16_flags -mfp16-format=alternative"
++}
++
+ # Return 1 if this is an ARM target that can support a VFP fp16 variant.
+ # Skip multilibs that are incompatible with these options and set
+-# et_arm_fp16_flags to the best options to add.
++# et_arm_fp16_flags to the best options to add.  This test is valid for
++# ARM only.
+ 
+ proc check_effective_target_arm_fp16_ok_nocache { } {
+     global et_arm_fp16_flags
+@@ -3164,7 +3272,10 @@ proc check_effective_target_arm_fp16_ok_nocache { } {
+     if { ! [check_effective_target_arm32] } {
+ 	return 0;
+     }
+-    if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" "-mfpu=*fpv[1-9][0-9]*" } ]] {
++    if [check-flags \
++	    [list "" { *-*-* } { "-mfpu=*" } \
++		 { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
++		       "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
+ 	# Multilib flags would override -mfpu.
+ 	return 0
+     }
+@@ -3200,6 +3311,28 @@ proc check_effective_target_arm_fp16_ok { } {
+ 		check_effective_target_arm_fp16_ok_nocache]
+ }
+ 
++# Return 1 if the target supports executing VFP FP16 instructions, 0
++# otherwise.  This test is valid for ARM only.
++
++proc check_effective_target_arm_fp16_hw { } {
++    if {! [check_effective_target_arm_fp16_ok] } {
++	return 0
++    }
++    global et_arm_fp16_flags
++    check_runtime_nocache arm_fp16_hw {
++	int
++	main (int argc, char **argv)
++	{
++	  __fp16 a = 1.0;
++	  float r;
++	  asm ("vcvtb.f32.f16 %0, %1"
++	       : "=w" (r) : "w" (a)
++	       : /* No clobbers.  */);
++	  return (r == 1.0) ? 0 : 1;
++	}
++    } "$et_arm_fp16_flags -mfp16-format=ieee"
++}
++
+ # Creates a series of routines that return 1 if the given architecture
+ # can be selected and a routine to give the flags to select that architecture
+ # Note: Extra flags may be added to disable options from newer compilers
+@@ -3209,22 +3342,26 @@ proc check_effective_target_arm_fp16_ok { } {
+ # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
+ #        /* { dg-add-options arm_arch_v5 } */
+ #	 /* { dg-require-effective-target arm_arch_v5_multilib } */
+-foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__
+-				     v4t "-march=armv4t" __ARM_ARCH_4T__
+-				     v5 "-march=armv5 -marm" __ARM_ARCH_5__
+-				     v5t "-march=armv5t" __ARM_ARCH_5T__
+-				     v5te "-march=armv5te" __ARM_ARCH_5TE__
+-				     v6 "-march=armv6" __ARM_ARCH_6__
+-				     v6k "-march=armv6k" __ARM_ARCH_6K__
+-				     v6t2 "-march=armv6t2" __ARM_ARCH_6T2__
+-				     v6z "-march=armv6z" __ARM_ARCH_6Z__
+-				     v6m "-march=armv6-m -mthumb" __ARM_ARCH_6M__
+-				     v7a "-march=armv7-a" __ARM_ARCH_7A__
+-				     v7r "-march=armv7-r" __ARM_ARCH_7R__
+-				     v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__
+-				     v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__
+-				     v8a "-march=armv8-a" __ARM_ARCH_8A__
+-				     v8_1a "-march=armv8.1a" __ARM_ARCH_8A__ } {
++foreach { armfunc armflag armdef } {
++	v4 "-march=armv4 -marm" __ARM_ARCH_4__
++	v4t "-march=armv4t" __ARM_ARCH_4T__
++	v5 "-march=armv5 -marm" __ARM_ARCH_5__
++	v5t "-march=armv5t" __ARM_ARCH_5T__
++	v5te "-march=armv5te" __ARM_ARCH_5TE__
++	v6 "-march=armv6" __ARM_ARCH_6__
++	v6k "-march=armv6k" __ARM_ARCH_6K__
++	v6t2 "-march=armv6t2" __ARM_ARCH_6T2__
++	v6z "-march=armv6z" __ARM_ARCH_6Z__
++	v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
++	v7a "-march=armv7-a" __ARM_ARCH_7A__
++	v7r "-march=armv7-r" __ARM_ARCH_7R__
++	v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__
++	v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__
++	v8a "-march=armv8-a" __ARM_ARCH_8A__
++	v8_1a "-march=armv8.1a" __ARM_ARCH_8A__
++	v8_2a "-march=armv8.2a" __ARM_ARCH_8A__
++	v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft" __ARM_ARCH_8M_BASE__
++	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
+     eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
+ 	proc check_effective_target_arm_arch_FUNC_ok { } {
+ 	    if { [ string match "*-marm*" "FLAG" ] &&
+@@ -3352,15 +3489,60 @@ proc check_effective_target_arm_cortex_m { } {
+ 	return 0
+     }
+     return [check_no_compiler_messages arm_cortex_m assembly {
+-	#if !defined(__ARM_ARCH_7M__) \
+-            && !defined (__ARM_ARCH_7EM__) \
+-            && !defined (__ARM_ARCH_6M__)
+-	#error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__
++	#if defined(__ARM_ARCH_ISA_ARM)
++	#error __ARM_ARCH_ISA_ARM is defined
+ 	#endif
+ 	int i;
+     } "-mthumb"]
+ }
+ 
++# Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
++# used and MOVT/MOVW instructions to be available.
++
++proc check_effective_target_arm_thumb1_movt_ok {} {
++    if [check_effective_target_arm_thumb1_ok] {
++	return [check_no_compiler_messages arm_movt object {
++	    int
++	    foo (void)
++	    {
++	      asm ("movt r0, #42");
++	    }
++	} "-mthumb"]
++    } else {
++	return 0
++    }
++}
++
++# Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
++# used and CBZ and CBNZ instructions are available.
++
++proc check_effective_target_arm_thumb1_cbz_ok {} {
++    if [check_effective_target_arm_thumb1_ok] {
++	return [check_no_compiler_messages arm_movt object {
++	    int
++	    foo (void)
++	    {
++	      asm ("cbz r0, 2f\n2:");
++	    }
++	} "-mthumb"]
++    } else {
++	return 0
++    }
++}
++
++# Return 1 if this is an ARM target where ARMv8-M Security Extensions is
++# available.
++
++proc check_effective_target_arm_cmse_ok {} {
++    return [check_no_compiler_messages arm_cmse object {
++	int
++	foo (void)
++	{
++	  asm ("bxns r0");
++	}
++    } "-mcmse"];
++}
++
+ # Return 1 if this compilation turns on string_ops_prefer_neon on.
+ 
+ proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
+@@ -3436,6 +3618,76 @@ proc check_effective_target_arm_v8_1a_neon_ok { } {
+ 		check_effective_target_arm_v8_1a_neon_ok_nocache]
+ }
+ 
++# Return 1 if the target supports ARMv8.2 scalar FP16 arithmetic
++# instructions, 0 otherwise.  The test is valid for ARM and for AArch64.
++# Record the command line options needed.
++
++proc check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache { } {
++    global et_arm_v8_2a_fp16_scalar_flags
++    set et_arm_v8_2a_fp16_scalar_flags ""
++
++    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
++	return 0;
++    }
++
++    # Iterate through sets of options to find the compiler flags that
++    # need to be added to the -march option.
++    foreach flags {"" "-mfpu=fp-armv8" "-mfloat-abi=softfp" \
++		       "-mfpu=fp-armv8 -mfloat-abi=softfp"} {
++	if { [check_no_compiler_messages_nocache \
++		  arm_v8_2a_fp16_scalar_ok object {
++	    #if !defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
++	    #error "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined"
++	    #endif
++	} "$flags -march=armv8.2-a+fp16"] } {
++	    set et_arm_v8_2a_fp16_scalar_flags "$flags -march=armv8.2-a+fp16"
++	    return 1
++	}
++    }
++
++    return 0;
++}
++
++proc check_effective_target_arm_v8_2a_fp16_scalar_ok { } {
++    return [check_cached_effective_target arm_v8_2a_fp16_scalar_ok \
++		check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache]
++}
++
++# Return 1 if the target supports ARMv8.2 Adv.SIMD FP16 arithmetic
++# instructions, 0 otherwise.  The test is valid for ARM and for AArch64.
++# Record the command line options needed.
++
++proc check_effective_target_arm_v8_2a_fp16_neon_ok_nocache { } {
++    global et_arm_v8_2a_fp16_neon_flags
++    set et_arm_v8_2a_fp16_neon_flags ""
++
++    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
++	return 0;
++    }
++
++    # Iterate through sets of options to find the compiler flags that
++    # need to be added to the -march option.
++    foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
++		       "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
++	if { [check_no_compiler_messages_nocache \
++		  arm_v8_2a_fp16_neon_ok object {
++	    #if !defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++	    #error "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined"
++	    #endif
++	} "$flags -march=armv8.2-a+fp16"] } {
++	    set et_arm_v8_2a_fp16_neon_flags "$flags -march=armv8.2-a+fp16"
++	    return 1
++	}
++    }
++
++    return 0;
++}
++
++proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {
++    return [check_cached_effective_target arm_v8_2a_fp16_neon_ok \
++		check_effective_target_arm_v8_2a_fp16_neon_ok_nocache]
++}
++
+ # Return 1 if the target supports executing ARMv8 NEON instructions, 0
+ # otherwise.
+ 
+@@ -3445,11 +3697,17 @@ proc check_effective_target_arm_v8_neon_hw { } {
+ 	int
+ 	main (void)
+ 	{
+-	  float32x2_t a;
++	  float32x2_t a = { 1.0f, 2.0f };
++	  #ifdef __ARM_ARCH_ISA_A64
++	  asm ("frinta %0.2s, %1.2s"
++	      : "=w" (a)
++	      : "w" (a));
++	  #else
+ 	  asm ("vrinta.f32 %P0, %P1"
+ 	       : "=w" (a)
+ 	       : "0" (a));
+-	  return 0;
++	  #endif
++	  return a[0] == 2.0f;
+ 	}
+     } [add_options_for_arm_v8_neon ""]]
+ }
+@@ -3492,6 +3750,81 @@ proc check_effective_target_arm_v8_1a_neon_hw { } {
+     } [add_options_for_arm_v8_1a_neon ""]]
+ }
+ 
++# Return 1 if the target supports executing floating point instructions from
++# ARMv8.2 with the FP16 extension, 0 otherwise.  The test is valid for ARM and
++# for AArch64.
++
++proc check_effective_target_arm_v8_2a_fp16_scalar_hw { } {
++    if { ![check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
++	return 0;
++    }
++    return [check_runtime arm_v8_2a_fp16_scalar_hw_available {
++	int
++	main (void)
++	{
++	  __fp16 a = 1.0;
++	  __fp16 result;
++
++	  #ifdef __ARM_ARCH_ISA_A64
++
++	  asm ("fabs %h0, %h1"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #else
++
++	  asm ("vabs.f16 %0, %1"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #endif
++
++	  return (result == 1.0) ? 0 : 1;
++	}
++    } [add_options_for_arm_v8_2a_fp16_scalar ""]]
++}
++
++# Return 1 if the target supports executing Adv.SIMD instructions from ARMv8.2
++# with the FP16 extension, 0 otherwise.  The test is valid for ARM and for
++# AArch64.
++
++proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {
++    if { ![check_effective_target_arm_v8_2a_fp16_neon_ok] } {
++	return 0;
++    }
++    return [check_runtime arm_v8_2a_fp16_neon_hw_available {
++	int
++	main (void)
++	{
++	  #ifdef __ARM_ARCH_ISA_A64
++
++	  __Float16x4_t a = {1.0, -1.0, 1.0, -1.0};
++	  __Float16x4_t result;
++
++	  asm ("fabs %0.4h, %1.4h"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #else
++
++	  __simd64_float16_t a = {1.0, -1.0, 1.0, -1.0};
++	  __simd64_float16_t result;
++
++	  asm ("vabs.f16 %P0, %P1"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #endif
++
++	  return (result[0] == 1.0) ? 0 : 1;
++	}
++    } [add_options_for_arm_v8_2a_fp16_neon ""]]
++}
++
+ # Return 1 if this is a ARM target with NEON enabled.
+ 
+ proc check_effective_target_arm_neon { } {
+@@ -3526,6 +3859,25 @@ proc check_effective_target_arm_neonv2 { } {
+     }
+ }
+ 
++# Return 1 if this is an ARM target with load acquire and store release
++# instructions for 8-, 16- and 32-bit types.
++
++proc check_effective_target_arm_acq_rel { } {
++    return [check_no_compiler_messages arm_acq_rel object {
++	void
++	load_acquire_store_release (void)
++	{
++	  asm ("lda r0, [r1]\n\t"
++	       "stl r0, [r1]\n\t"
++	       "ldah r0, [r1]\n\t"
++	       "stlh r0, [r1]\n\t"
++	       "ldab r0, [r1]\n\t"
++	       "stlb r0, [r1]"
++	       : : : "r0", "memory");
++	}
++    }]
++}
++
+ # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
+ # the Loongson vector modes.
+ 
+@@ -4380,6 +4732,8 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
+         set et_vect_widen_sum_hi_to_si_pattern_saved 0
+         if { [istarget powerpc*-*-*]
+              || [istarget aarch64*-*-*]
++	     || ([istarget arm*-*-*] &&
++		 [check_effective_target_arm_neon_ok])
+              || [istarget ia64-*-*] } {
+             set et_vect_widen_sum_hi_to_si_pattern_saved 1
+         }
+@@ -5755,6 +6109,8 @@ proc check_effective_target_sync_int_long { } {
+ 	     || [istarget aarch64*-*-*]
+ 	     || [istarget alpha*-*-*] 
+ 	     || [istarget arm*-*-linux-*] 
++	     || ([istarget arm*-*-*]
++		 && [check_effective_target_arm_acq_rel])
+ 	     || [istarget bfin*-*linux*]
+ 	     || [istarget hppa*-*linux*]
+ 	     || [istarget s390*-*-*] 
+@@ -5788,6 +6144,8 @@ proc check_effective_target_sync_char_short { } {
+ 	     || [istarget i?86-*-*] || [istarget x86_64-*-*]
+ 	     || [istarget alpha*-*-*] 
+ 	     || [istarget arm*-*-linux-*] 
++	     || ([istarget arm*-*-*]
++		 && [check_effective_target_arm_acq_rel])
+ 	     || [istarget hppa*-*linux*]
+ 	     || [istarget s390*-*-*] 
+ 	     || [istarget powerpc*-*-*]
+--- a/src/gcc/tree-inline.c
++++ b/src/gcc/tree-inline.c
+@@ -244,6 +244,7 @@ remap_ssa_name (tree name, copy_body_data *id)
+       /* At least IPA points-to info can be directly transferred.  */
+       if (id->src_cfun->gimple_df
+ 	  && id->src_cfun->gimple_df->ipa_pta
++	  && POINTER_TYPE_P (TREE_TYPE (name))
+ 	  && (pi = SSA_NAME_PTR_INFO (name))
+ 	  && !pi->pt.anything)
+ 	{
+@@ -276,6 +277,7 @@ remap_ssa_name (tree name, copy_body_data *id)
+       /* At least IPA points-to info can be directly transferred.  */
+       if (id->src_cfun->gimple_df
+ 	  && id->src_cfun->gimple_df->ipa_pta
++	  && POINTER_TYPE_P (TREE_TYPE (name))
+ 	  && (pi = SSA_NAME_PTR_INFO (name))
+ 	  && !pi->pt.anything)
+ 	{
+--- a/src/gcc/tree-scalar-evolution.c
++++ b/src/gcc/tree-scalar-evolution.c
+@@ -1937,6 +1937,36 @@ interpret_rhs_expr (struct loop *loop, gimple *at_stmt,
+       res = chrec_convert (type, chrec1, at_stmt);
+       break;
+ 
++    case BIT_AND_EXPR:
++      /* Given int variable A, handle A&0xffff as (int)(unsigned short)A.
++	 If A is SCEV and its value is in the range of representable set
++	 of type unsigned short, the result expression is a (no-overflow)
++	 SCEV.  */
++      res = chrec_dont_know;
++      if (tree_fits_uhwi_p (rhs2))
++	{
++	  int precision;
++	  unsigned HOST_WIDE_INT val = tree_to_uhwi (rhs2);
++
++	  val ++;
++	  /* Skip if value of rhs2 wraps in unsigned HOST_WIDE_INT or
++	     it's not the maximum value of a smaller type than rhs1.  */
++	  if (val != 0
++	      && (precision = exact_log2 (val)) > 0
++	      && (unsigned) precision < TYPE_PRECISION (TREE_TYPE (rhs1)))
++	    {
++	      tree utype = build_nonstandard_integer_type (precision, 1);
++
++	      if (TYPE_PRECISION (utype) < TYPE_PRECISION (TREE_TYPE (rhs1)))
++		{
++		  chrec1 = analyze_scalar_evolution (loop, rhs1);
++		  chrec1 = chrec_convert (utype, chrec1, at_stmt);
++		  res = chrec_convert (TREE_TYPE (rhs1), chrec1, at_stmt);
++		}
++	    }
++	}
++      break;
++
+     default:
+       res = chrec_dont_know;
+       break;
+--- a/src/gcc/tree-ssa-address.c
++++ b/src/gcc/tree-ssa-address.c
+@@ -877,6 +877,10 @@ copy_ref_info (tree new_ref, tree old_ref)
+ 	      && TREE_CODE (old_ref) == MEM_REF
+ 	      && !(TREE_CODE (new_ref) == TARGET_MEM_REF
+ 		   && (TMR_INDEX2 (new_ref)
++		       /* TODO: Below conditions can be relaxed if TMR_INDEX
++			  is an indcution variable and its initial value and
++			  step are aligned.  */
++		       || (TMR_INDEX (new_ref) && !TMR_STEP (new_ref))
+ 		       || (TMR_STEP (new_ref)
+ 			   && (TREE_INT_CST_LOW (TMR_STEP (new_ref))
+ 			       < align)))))
+--- a/src/gcc/tree-ssa-ccp.c
++++ b/src/gcc/tree-ssa-ccp.c
+@@ -229,13 +229,12 @@ debug_lattice_value (ccp_prop_value_t val)
+   fprintf (stderr, "\n");
+ }
+ 
+-/* Extend NONZERO_BITS to a full mask, with the upper bits being set.  */
++/* Extend NONZERO_BITS to a full mask, based on sgn.  */ 
+ 
+ static widest_int
+-extend_mask (const wide_int &nonzero_bits)
++extend_mask (const wide_int &nonzero_bits, signop sgn)
+ {
+-  return (wi::mask <widest_int> (wi::get_precision (nonzero_bits), true)
+-	  | widest_int::from (nonzero_bits, UNSIGNED));
++  return widest_int::from (nonzero_bits, sgn); 
+ }
+ 
+ /* Compute a default value for variable VAR and store it in the
+@@ -284,7 +283,7 @@ get_default_value (tree var)
+ 		{
+ 		  val.lattice_val = CONSTANT;
+ 		  val.value = build_zero_cst (TREE_TYPE (var));
+-		  val.mask = extend_mask (nonzero_bits);
++		  val.mask = extend_mask (nonzero_bits, TYPE_SIGN (TREE_TYPE (var)));
+ 		}
+ 	    }
+ 	}
+@@ -1939,7 +1938,7 @@ evaluate_stmt (gimple *stmt)
+ 	    {
+ 	      val.lattice_val = CONSTANT;
+ 	      val.value = build_zero_cst (TREE_TYPE (lhs));
+-	      val.mask = extend_mask (nonzero_bits);
++	      val.mask = extend_mask (nonzero_bits, TYPE_SIGN (TREE_TYPE (lhs)));
+ 	      is_constant = true;
+ 	    }
+ 	  else
+@@ -1950,7 +1949,8 @@ evaluate_stmt (gimple *stmt)
+ 	      if (nonzero_bits == 0)
+ 		val.mask = 0;
+ 	      else
+-		val.mask = val.mask & extend_mask (nonzero_bits);
++		val.mask = val.mask & extend_mask (nonzero_bits,
++						   TYPE_SIGN (TREE_TYPE (lhs)));
+ 	    }
+ 	}
+     }
+--- a/src/gcc/tree-ssa-strlen.c
++++ b/src/gcc/tree-ssa-strlen.c
+@@ -2263,7 +2263,7 @@ public:
+ };
+ 
+ /* Callback for walk_dominator_tree.  Attempt to optimize various
+-   string ops by remembering string lenths pointed by pointer SSA_NAMEs.  */
++   string ops by remembering string lengths pointed by pointer SSA_NAMEs.  */
+ 
+ edge
+ strlen_dom_walker::before_dom_children (basic_block bb)
+--- a/src/gcc/tree-vect-data-refs.c
++++ b/src/gcc/tree-vect-data-refs.c
+@@ -2250,6 +2250,7 @@ vect_analyze_group_access_1 (struct data_reference *dr)
+ 	{
+ 	  GROUP_FIRST_ELEMENT (vinfo_for_stmt (stmt)) = stmt;
+ 	  GROUP_SIZE (vinfo_for_stmt (stmt)) = groupsize;
++	  GROUP_GAP (stmt_info) = groupsize - 1;
+ 	  if (dump_enabled_p ())
+ 	    {
+ 	      dump_printf_loc (MSG_NOTE, vect_location,
+--- a/src/gcc/tree-vect-loop-manip.c
++++ b/src/gcc/tree-vect-loop-manip.c
+@@ -40,6 +40,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "cfgloop.h"
+ #include "tree-scalar-evolution.h"
+ #include "tree-vectorizer.h"
++#include "tree-ssa-loop-ivopts.h"
+ 
+ /*************************************************************************
+   Simple Loop Peeling Utilities
+@@ -1594,10 +1595,26 @@ vect_can_advance_ivs_p (loop_vec_info loop_vinfo)
+         }
+ 
+       /* FORNOW: We do not transform initial conditions of IVs
++	 which evolution functions are not invariants in the loop.  */
++
++      if (!expr_invariant_in_loop_p (loop, evolution_part))
++	{
++	  if (dump_enabled_p ())
++	    dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
++			     "evolution not invariant in loop.\n");
++	  return false;
++	}
++
++      /* FORNOW: We do not transform initial conditions of IVs
+ 	 which evolution functions are a polynomial of degree >= 2.  */
+ 
+       if (tree_is_chrec (evolution_part))
+-	return false;
++	{
++	  if (dump_enabled_p ())
++	    dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
++			     "evolution is chrec.\n");
++	  return false;
++	}
+     }
+ 
+   return true;
+--- a/src/gcc/tree-vect-patterns.c
++++ b/src/gcc/tree-vect-patterns.c
+@@ -2136,32 +2136,313 @@ vect_recog_vector_vector_shift_pattern (vec<gimple *> *stmts,
+   return pattern_stmt;
+ }
+ 
+-/* Detect multiplication by constant which are postive or negatives of power 2,
+-   and convert them to shift patterns.
++/* Return true iff the target has a vector optab implementing the operation
++   CODE on type VECTYPE.  */
+ 
+-   Mult with constants that are postive power of two.
+-   type a_t;
+-   type b_t
+-   S1: b_t = a_t * n
++static bool
++target_has_vecop_for_code (tree_code code, tree vectype)
++{
++  optab voptab = optab_for_tree_code (code, vectype, optab_vector);
++  return voptab
++	 && optab_handler (voptab, TYPE_MODE (vectype)) != CODE_FOR_nothing;
++}
+ 
+-   or
++/* Verify that the target has optabs of VECTYPE to perform all the steps
++   needed by the multiplication-by-immediate synthesis algorithm described by
++   ALG and VAR.  If SYNTH_SHIFT_P is true ensure that vector addition is
++   present.  Return true iff the target supports all the steps.  */
++
++static bool
++target_supports_mult_synth_alg (struct algorithm *alg, mult_variant var,
++				 tree vectype, bool synth_shift_p)
++{
++  if (alg->op[0] != alg_zero && alg->op[0] != alg_m)
++    return false;
++
++  bool supports_vminus = target_has_vecop_for_code (MINUS_EXPR, vectype);
++  bool supports_vplus = target_has_vecop_for_code (PLUS_EXPR, vectype);
++
++  if (var == negate_variant
++      && !target_has_vecop_for_code (NEGATE_EXPR, vectype))
++    return false;
++
++  /* If we must synthesize shifts with additions make sure that vector
++     addition is available.  */
++  if ((var == add_variant || synth_shift_p) && !supports_vplus)
++    return false;
++
++  for (int i = 1; i < alg->ops; i++)
++    {
++      switch (alg->op[i])
++	{
++	case alg_shift:
++	  break;
++	case alg_add_t_m2:
++	case alg_add_t2_m:
++	case alg_add_factor:
++	  if (!supports_vplus)
++	    return false;
++	  break;
++	case alg_sub_t_m2:
++	case alg_sub_t2_m:
++	case alg_sub_factor:
++	  if (!supports_vminus)
++	    return false;
++	  break;
++	case alg_unknown:
++	case alg_m:
++	case alg_zero:
++	case alg_impossible:
++	  return false;
++	default:
++	  gcc_unreachable ();
++	}
++    }
++
++  return true;
++}
++
++/* Synthesize a left shift of OP by AMNT bits using a series of additions and
++   putting the final result in DEST.  Append all statements but the last into
++   VINFO.  Return the last statement.  */
++
++static gimple *
++synth_lshift_by_additions (tree dest, tree op, HOST_WIDE_INT amnt,
++			   stmt_vec_info vinfo)
++{
++  HOST_WIDE_INT i;
++  tree itype = TREE_TYPE (op);
++  tree prev_res = op;
++  gcc_assert (amnt >= 0);
++  for (i = 0; i < amnt; i++)
++    {
++      tree tmp_var = (i < amnt - 1) ? vect_recog_temp_ssa_var (itype, NULL)
++		      : dest;
++      gimple *stmt
++        = gimple_build_assign (tmp_var, PLUS_EXPR, prev_res, prev_res);
++      prev_res = tmp_var;
++      if (i < amnt - 1)
++	append_pattern_def_seq (vinfo, stmt);
++      else
++	return stmt;
++    }
++  gcc_unreachable ();
++  return NULL;
++}
++
++/* Helper for vect_synth_mult_by_constant.  Apply a binary operation
++   CODE to operands OP1 and OP2, creating a new temporary SSA var in
++   the process if necessary.  Append the resulting assignment statements
++   to the sequence in STMT_VINFO.  Return the SSA variable that holds the
++   result of the binary operation.  If SYNTH_SHIFT_P is true synthesize
++   left shifts using additions.  */
++
++static tree
++apply_binop_and_append_stmt (tree_code code, tree op1, tree op2,
++			     stmt_vec_info stmt_vinfo, bool synth_shift_p)
++{
++  if (integer_zerop (op2)
++      && (code == LSHIFT_EXPR
++	  || code == PLUS_EXPR))
++    {
++      gcc_assert (TREE_CODE (op1) == SSA_NAME);
++      return op1;
++    }
++
++  gimple *stmt;
++  tree itype = TREE_TYPE (op1);
++  tree tmp_var = vect_recog_temp_ssa_var (itype, NULL);
++
++  if (code == LSHIFT_EXPR
++      && synth_shift_p)
++    {
++      stmt = synth_lshift_by_additions (tmp_var, op1, TREE_INT_CST_LOW (op2),
++					 stmt_vinfo);
++      append_pattern_def_seq (stmt_vinfo, stmt);
++      return tmp_var;
++    }
++
++  stmt = gimple_build_assign (tmp_var, code, op1, op2);
++  append_pattern_def_seq (stmt_vinfo, stmt);
++  return tmp_var;
++}
++
++/* Synthesize a multiplication of OP by an INTEGER_CST VAL using shifts
++   and simple arithmetic operations to be vectorized.  Record the statements
++   produced in STMT_VINFO and return the last statement in the sequence or
++   NULL if it's not possible to synthesize such a multiplication.
++   This function mirrors the behavior of expand_mult_const in expmed.c but
++   works on tree-ssa form.  */
++
++static gimple *
++vect_synth_mult_by_constant (tree op, tree val,
++			     stmt_vec_info stmt_vinfo)
++{
++  tree itype = TREE_TYPE (op);
++  machine_mode mode = TYPE_MODE (itype);
++  struct algorithm alg;
++  mult_variant variant;
++  if (!tree_fits_shwi_p (val))
++    return NULL;
++
++  /* Multiplication synthesis by shifts, adds and subs can introduce
++     signed overflow where the original operation didn't.  Perform the
++     operations on an unsigned type and cast back to avoid this.
++     In the future we may want to relax this for synthesis algorithms
++     that we can prove do not cause unexpected overflow.  */
++  bool cast_to_unsigned_p = !TYPE_OVERFLOW_WRAPS (itype);
++
++  tree multtype = cast_to_unsigned_p ? unsigned_type_for (itype) : itype;
++
++  /* Targets that don't support vector shifts but support vector additions
++     can synthesize shifts that way.  */
++  bool synth_shift_p = !vect_supportable_shift (LSHIFT_EXPR, multtype);
++
++  HOST_WIDE_INT hwval = tree_to_shwi (val);
++  /* Use MAX_COST here as we don't want to limit the sequence on rtx costs.
++     The vectorizer's benefit analysis will decide whether it's beneficial
++     to do this.  */
++  bool possible = choose_mult_variant (mode, hwval, &alg,
++					&variant, MAX_COST);
++  if (!possible)
++    return NULL;
+ 
+-   Mult with constants that are negative power of two.
+-   S2: b_t = a_t * -n
++  tree vectype = get_vectype_for_scalar_type (multtype);
++
++  if (!vectype
++      || !target_supports_mult_synth_alg (&alg, variant,
++					   vectype, synth_shift_p))
++    return NULL;
++
++  tree accumulator;
++
++  /* Clear out the sequence of statements so we can populate it below.  */
++  STMT_VINFO_PATTERN_DEF_SEQ (stmt_vinfo) = NULL;
++  gimple *stmt = NULL;
++
++  if (cast_to_unsigned_p)
++    {
++      tree tmp_op = vect_recog_temp_ssa_var (multtype, NULL);
++      stmt = gimple_build_assign (tmp_op, CONVERT_EXPR, op);
++      append_pattern_def_seq (stmt_vinfo, stmt);
++      op = tmp_op;
++    }
++
++  if (alg.op[0] == alg_zero)
++    accumulator = build_int_cst (multtype, 0);
++  else
++    accumulator = op;
++
++  bool needs_fixup = (variant == negate_variant)
++		      || (variant == add_variant);
++
++  for (int i = 1; i < alg.ops; i++)
++    {
++      tree shft_log = build_int_cst (multtype, alg.log[i]);
++      tree accum_tmp = vect_recog_temp_ssa_var (multtype, NULL);
++      tree tmp_var = NULL_TREE;
++
++      switch (alg.op[i])
++	{
++	case alg_shift:
++	  if (synth_shift_p)
++	    stmt
++	      = synth_lshift_by_additions (accum_tmp, accumulator, alg.log[i],
++					    stmt_vinfo);
++	  else
++	    stmt = gimple_build_assign (accum_tmp, LSHIFT_EXPR, accumulator,
++					 shft_log);
++	  break;
++	case alg_add_t_m2:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, op, shft_log,
++					    stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, accumulator,
++				       tmp_var);
++	  break;
++	case alg_sub_t_m2:
++	  tmp_var = apply_binop_and_append_stmt (LSHIFT_EXPR, op,
++						  shft_log, stmt_vinfo,
++						  synth_shift_p);
++	  /* In some algorithms the first step involves zeroing the
++	     accumulator.  If subtracting from such an accumulator
++	     just emit the negation directly.  */
++	  if (integer_zerop (accumulator))
++	    stmt = gimple_build_assign (accum_tmp, NEGATE_EXPR, tmp_var);
++	  else
++	    stmt = gimple_build_assign (accum_tmp, MINUS_EXPR, accumulator,
++					tmp_var);
++	  break;
++	case alg_add_t2_m:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					   stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, tmp_var, op);
++	  break;
++	case alg_sub_t2_m:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					   stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, MINUS_EXPR, tmp_var, op);
++	  break;
++	case alg_add_factor:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					    stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, accumulator,
++				       tmp_var);
++	  break;
++	case alg_sub_factor:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					   stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, MINUS_EXPR, tmp_var,
++				      accumulator);
++	  break;
++	default:
++	  gcc_unreachable ();
++	}
++      /* We don't want to append the last stmt in the sequence to stmt_vinfo
++	 but rather return it directly.  */
++
++      if ((i < alg.ops - 1) || needs_fixup || cast_to_unsigned_p)
++	append_pattern_def_seq (stmt_vinfo, stmt);
++      accumulator = accum_tmp;
++    }
++  if (variant == negate_variant)
++    {
++      tree accum_tmp = vect_recog_temp_ssa_var (multtype, NULL);
++      stmt = gimple_build_assign (accum_tmp, NEGATE_EXPR, accumulator);
++      accumulator = accum_tmp;
++      if (cast_to_unsigned_p)
++	append_pattern_def_seq (stmt_vinfo, stmt);
++    }
++  else if (variant == add_variant)
++    {
++      tree accum_tmp = vect_recog_temp_ssa_var (multtype, NULL);
++      stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, accumulator, op);
++      accumulator = accum_tmp;
++      if (cast_to_unsigned_p)
++	append_pattern_def_seq (stmt_vinfo, stmt);
++    }
++  /* Move back to a signed if needed.  */
++  if (cast_to_unsigned_p)
++    {
++      tree accum_tmp = vect_recog_temp_ssa_var (itype, NULL);
++      stmt = gimple_build_assign (accum_tmp, CONVERT_EXPR, accumulator);
++    }
++
++  return stmt;
++}
++
++/* Detect multiplication by constant and convert it into a sequence of
++   shifts and additions, subtractions, negations.  We reuse the
++   choose_mult_variant algorithms from expmed.c
+ 
+    Input/Output:
+ 
+    STMTS: Contains a stmt from which the pattern search begins,
+-   i.e. the mult stmt.  Convert the mult operation to LSHIFT if
+-   constant operand is a power of 2.
+-   type a_t, b_t
+-   S1': b_t = a_t << log2 (n)
+-
+-   Convert the mult operation to LSHIFT and followed by a NEGATE
+-   if constant operand is a negative power of 2.
+-   type a_t, b_t, res_T;
+-   S2': b_t = a_t << log2 (n)
+-   S3': res_T  = - (b_t)
++   i.e. the mult stmt.
+ 
+  Output:
+ 
+@@ -2169,8 +2450,8 @@ vect_recog_vector_vector_shift_pattern (vec<gimple *> *stmts,
+ 
+   * TYPE_OUT: The type of the output of this pattern.
+ 
+-  * Return value: A new stmt that will be used to replace the multiplication
+-    S1 or S2 stmt.  */
++  * Return value: A new stmt that will be used to replace
++    the multiplication.  */
+ 
+ static gimple *
+ vect_recog_mult_pattern (vec<gimple *> *stmts,
+@@ -2178,11 +2459,8 @@ vect_recog_mult_pattern (vec<gimple *> *stmts,
+ {
+   gimple *last_stmt = stmts->pop ();
+   tree oprnd0, oprnd1, vectype, itype;
+-  gimple *pattern_stmt, *def_stmt;
+-  optab optab;
++  gimple *pattern_stmt;
+   stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
+-  int power2_val, power2_neg_val;
+-  tree shift;
+ 
+   if (!is_gimple_assign (last_stmt))
+     return NULL;
+@@ -2206,52 +2484,17 @@ vect_recog_mult_pattern (vec<gimple *> *stmts,
+ 
+   /* If the target can handle vectorized multiplication natively,
+      don't attempt to optimize this.  */
+-  optab = optab_for_tree_code (MULT_EXPR, vectype, optab_default);
+-  if (optab != unknown_optab)
++  optab mul_optab = optab_for_tree_code (MULT_EXPR, vectype, optab_default);
++  if (mul_optab != unknown_optab)
+     {
+       machine_mode vec_mode = TYPE_MODE (vectype);
+-      int icode = (int) optab_handler (optab, vec_mode);
++      int icode = (int) optab_handler (mul_optab, vec_mode);
+       if (icode != CODE_FOR_nothing)
+-	return NULL;
++       return NULL;
+     }
+ 
+-  /* If target cannot handle vector left shift then we cannot
+-     optimize and bail out.  */
+-  optab = optab_for_tree_code (LSHIFT_EXPR, vectype, optab_vector);
+-  if (!optab
+-      || optab_handler (optab, TYPE_MODE (vectype)) == CODE_FOR_nothing)
+-    return NULL;
+-
+-  power2_val = wi::exact_log2 (oprnd1);
+-  power2_neg_val = wi::exact_log2 (wi::neg (oprnd1));
+-
+-  /* Handle constant operands that are postive or negative powers of 2.  */
+-  if (power2_val != -1)
+-    {
+-      shift = build_int_cst (itype, power2_val);
+-      pattern_stmt
+-	= gimple_build_assign (vect_recog_temp_ssa_var (itype, NULL),
+-			       LSHIFT_EXPR, oprnd0, shift);
+-    }
+-  else if (power2_neg_val != -1)
+-    {
+-      /* If the target cannot handle vector NEGATE then we cannot
+-	 do the optimization.  */
+-      optab = optab_for_tree_code (NEGATE_EXPR, vectype, optab_vector);
+-      if (!optab
+-	  || optab_handler (optab, TYPE_MODE (vectype)) == CODE_FOR_nothing)
+-	return NULL;
+-
+-      shift = build_int_cst (itype, power2_neg_val);
+-      def_stmt
+-	= gimple_build_assign (vect_recog_temp_ssa_var (itype, NULL),
+-			       LSHIFT_EXPR, oprnd0, shift);
+-      new_pattern_def_seq (stmt_vinfo, def_stmt);
+-      pattern_stmt
+-	 = gimple_build_assign (vect_recog_temp_ssa_var (itype, NULL),
+-				NEGATE_EXPR, gimple_assign_lhs (def_stmt));
+-    }
+-  else
++  pattern_stmt = vect_synth_mult_by_constant (oprnd0, oprnd1, stmt_vinfo);
++  if (!pattern_stmt)
+     return NULL;
+ 
+   /* Pattern detected.  */
+--- a/src/gcc/tree-vect-stmts.c
++++ b/src/gcc/tree-vect-stmts.c
+@@ -6354,12 +6354,22 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+       gcc_assert (!nested_in_vect_loop && !STMT_VINFO_GATHER_SCATTER_P (stmt_info));
+ 
+       first_stmt = GROUP_FIRST_ELEMENT (stmt_info);
++      group_size = GROUP_SIZE (vinfo_for_stmt (first_stmt));
++
++      if (!slp
++	  && !PURE_SLP_STMT (stmt_info)
++	  && !STMT_VINFO_STRIDED_P (stmt_info))
++	{
++	  if (vect_load_lanes_supported (vectype, group_size))
++	    load_lanes_p = true;
++	  else if (!vect_grouped_load_supported (vectype, group_size))
++	    return false;
++	}
+ 
+       /* If this is single-element interleaving with an element distance
+          that leaves unused vector loads around punt - we at least create
+ 	 very sub-optimal code in that case (and blow up memory,
+ 	 see PR65518).  */
+-      bool force_peeling = false;
+       if (first_stmt == stmt
+ 	  && !GROUP_NEXT_ELEMENT (stmt_info))
+ 	{
+@@ -6373,7 +6383,7 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+ 	    }
+ 
+ 	  /* Single-element interleaving requires peeling for gaps.  */
+-	  force_peeling = true;
++	  gcc_assert (GROUP_GAP (stmt_info));
+ 	}
+ 
+       /* If there is a gap in the end of the group or the group size cannot
+@@ -6381,9 +6391,8 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+ 	 elements in the last iteration and thus need to peel that off.  */
+       if (loop_vinfo
+ 	  && ! STMT_VINFO_STRIDED_P (stmt_info)
+-	  && (force_peeling
+-	      || GROUP_GAP (vinfo_for_stmt (first_stmt)) != 0
+-	      || (!slp && vf % GROUP_SIZE (vinfo_for_stmt (first_stmt)) != 0)))
++	  && (GROUP_GAP (vinfo_for_stmt (first_stmt)) != 0
++	      || (!slp && !load_lanes_p && vf % group_size != 0)))
+ 	{
+ 	  if (dump_enabled_p ())
+ 	    dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
+@@ -6403,8 +6412,6 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+       if (slp && SLP_TREE_LOAD_PERMUTATION (slp_node).exists ())
+ 	slp_perm = true;
+ 
+-      group_size = GROUP_SIZE (vinfo_for_stmt (first_stmt));
+-
+       /* ???  The following is overly pessimistic (as well as the loop
+          case above) in the case we can statically determine the excess
+ 	 elements loaded are within the bounds of a decl that is accessed.
+@@ -6417,16 +6424,6 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+ 	  return false;
+ 	}
+ 
+-      if (!slp
+-	  && !PURE_SLP_STMT (stmt_info)
+-	  && !STMT_VINFO_STRIDED_P (stmt_info))
+-	{
+-	  if (vect_load_lanes_supported (vectype, group_size))
+-	    load_lanes_p = true;
+-	  else if (!vect_grouped_load_supported (vectype, group_size))
+-	    return false;
+-	}
+-
+       /* Invalidate assumptions made by dependence analysis when vectorization
+ 	 on the unrolled body effectively re-orders stmts.  */
+       if (!PURE_SLP_STMT (stmt_info)
+--- a/src/gcc/tree-vectorizer.c
++++ b/src/gcc/tree-vectorizer.c
+@@ -794,38 +794,142 @@ make_pass_slp_vectorize (gcc::context *ctxt)
+      This should involve global alignment analysis and in the future also
+      array padding.  */
+ 
++static unsigned get_vec_alignment_for_type (tree);
++static hash_map<tree, unsigned> *type_align_map;
++
++/* Return alignment of array's vector type corresponding to scalar type.
++   0 if no vector type exists.  */
++static unsigned
++get_vec_alignment_for_array_type (tree type) 
++{
++  gcc_assert (TREE_CODE (type) == ARRAY_TYPE);
++
++  tree vectype = get_vectype_for_scalar_type (strip_array_types (type));
++  if (!vectype
++      || !TYPE_SIZE (type)
++      || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST
++      || tree_int_cst_lt (TYPE_SIZE (type), TYPE_SIZE (vectype)))
++    return 0;
++
++  return TYPE_ALIGN (vectype);
++}
++
++/* Return alignment of field having maximum alignment of vector type
++   corresponding to it's scalar type. For now, we only consider fields whose
++   offset is a multiple of it's vector alignment.
++   0 if no suitable field is found.  */
++static unsigned
++get_vec_alignment_for_record_type (tree type) 
++{
++  gcc_assert (TREE_CODE (type) == RECORD_TYPE);
++
++  unsigned max_align = 0, alignment;
++  HOST_WIDE_INT offset;
++  tree offset_tree;
++
++  if (TYPE_PACKED (type))
++    return 0;
++
++  unsigned *slot = type_align_map->get (type);
++  if (slot)
++    return *slot;
++
++  for (tree field = first_field (type);
++       field != NULL_TREE;
++       field = DECL_CHAIN (field))
++    {
++      /* Skip if not FIELD_DECL or if alignment is set by user.  */ 
++      if (TREE_CODE (field) != FIELD_DECL
++	  || DECL_USER_ALIGN (field)
++	  || DECL_ARTIFICIAL (field))
++	continue;
++
++      /* We don't need to process the type further if offset is variable,
++	 since the offsets of remaining members will also be variable.  */
++      if (TREE_CODE (DECL_FIELD_OFFSET (field)) != INTEGER_CST
++	  || TREE_CODE (DECL_FIELD_BIT_OFFSET (field)) != INTEGER_CST)
++	break;
++
++      /* Similarly stop processing the type if offset_tree
++	 does not fit in unsigned HOST_WIDE_INT.  */
++      offset_tree = bit_position (field);
++      if (!tree_fits_uhwi_p (offset_tree))
++	break;
++
++      offset = tree_to_uhwi (offset_tree); 
++      alignment = get_vec_alignment_for_type (TREE_TYPE (field));
++
++      /* Get maximum alignment of vectorized field/array among those members
++	 whose offset is multiple of the vector alignment.  */ 
++      if (alignment
++	  && (offset % alignment == 0)
++	  && (alignment > max_align))
++	max_align = alignment;
++    }
++
++  type_align_map->put (type, max_align);
++  return max_align;
++}
++
++/* Return alignment of vector type corresponding to decl's scalar type
++   or 0 if it doesn't exist or the vector alignment is lesser than
++   decl's alignment.  */
++static unsigned
++get_vec_alignment_for_type (tree type)
++{
++  if (type == NULL_TREE)
++    return 0;
++
++  gcc_assert (TYPE_P (type));
++
++  static unsigned alignment = 0;
++  switch (TREE_CODE (type))
++    {
++      case ARRAY_TYPE:
++	alignment = get_vec_alignment_for_array_type (type);
++	break;
++      case RECORD_TYPE:
++	alignment = get_vec_alignment_for_record_type (type);
++	break;
++      default:
++	alignment = 0;
++	break;
++    }
++
++  return (alignment > TYPE_ALIGN (type)) ? alignment : 0;
++}
++
++/* Entry point to increase_alignment pass.  */
+ static unsigned int
+ increase_alignment (void)
+ {
+   varpool_node *vnode;
+ 
+   vect_location = UNKNOWN_LOCATION;
++  type_align_map = new hash_map<tree, unsigned>;
+ 
+   /* Increase the alignment of all global arrays for vectorization.  */
+   FOR_EACH_DEFINED_VARIABLE (vnode)
+     {
+-      tree vectype, decl = vnode->decl;
+-      tree t;
++      tree decl = vnode->decl;
+       unsigned int alignment;
+ 
+-      t = TREE_TYPE (decl);
+-      if (TREE_CODE (t) != ARRAY_TYPE)
+-        continue;
+-      vectype = get_vectype_for_scalar_type (strip_array_types (t));
+-      if (!vectype)
+-        continue;
+-      alignment = TYPE_ALIGN (vectype);
+-      if (DECL_ALIGN (decl) >= alignment)
+-        continue;
+-
+-      if (vect_can_force_dr_alignment_p (decl, alignment))
++      if ((decl_in_symtab_p (decl)
++	  && !symtab_node::get (decl)->can_increase_alignment_p ())
++	  || DECL_USER_ALIGN (decl) || DECL_ARTIFICIAL (decl))
++	continue;
++
++      alignment = get_vec_alignment_for_type (TREE_TYPE (decl));
++      if (alignment && vect_can_force_dr_alignment_p (decl, alignment))
+         {
+-	  vnode->increase_alignment (TYPE_ALIGN (vectype));
++	  vnode->increase_alignment (alignment);
+           dump_printf (MSG_NOTE, "Increasing alignment of decl: ");
+           dump_generic_expr (MSG_NOTE, TDF_SLIM, decl);
+           dump_printf (MSG_NOTE, "\n");
+         }
+     }
++
++  delete type_align_map;
+   return 0;
+ }
+ 
+--- a/src/gcc/tree-vrp.c
++++ b/src/gcc/tree-vrp.c
+@@ -3147,6 +3147,24 @@ extract_range_from_binary_expr_1 (value_range *vr,
+ 	  if (int_cst_range1 && tree_int_cst_sgn (vr1.min) >= 0)
+ 	    wmax = wi::min (wmax, vr1.max, TYPE_SIGN (expr_type));
+ 	  max = wide_int_to_tree (expr_type, wmax);
++	  cmp = compare_values (min, max);
++	  /* PR68217: In case of signed & sign-bit-CST should
++	     result in [-INF, 0] instead of [-INF, INF].  */
++	  if (cmp == -2 || cmp == 1)
++	    {
++	      wide_int sign_bit
++		= wi::set_bit_in_zero (TYPE_PRECISION (expr_type) - 1,
++				       TYPE_PRECISION (expr_type));
++	      if (!TYPE_UNSIGNED (expr_type)
++		  && ((value_range_constant_singleton (&vr0)
++		       && !wi::cmps (vr0.min, sign_bit))
++		      || (value_range_constant_singleton (&vr1)
++			  && !wi::cmps (vr1.min, sign_bit))))
++		{
++		  min = TYPE_MIN_VALUE (expr_type);
++		  max = build_int_cst (expr_type, 0);
++		}
++	    }
+ 	}
+       else if (code == BIT_IOR_EXPR)
+ 	{
+@@ -3841,7 +3859,8 @@ extract_range_basic (value_range *vr, gimple *stmt)
+ 	  arg = gimple_call_arg (stmt, 0);
+ 	  if (TREE_CODE (arg) == SSA_NAME
+ 	      && SSA_NAME_IS_DEFAULT_DEF (arg)
+-	      && TREE_CODE (SSA_NAME_VAR (arg)) == PARM_DECL)
++	      && TREE_CODE (SSA_NAME_VAR (arg)) == PARM_DECL
++	      && cfun->after_inlining)
+ 	    {
+ 	      set_value_range_to_null (vr, type);
+ 	      return;
+@@ -9917,6 +9936,40 @@ simplify_internal_call_using_ranges (gimple_stmt_iterator *gsi, gimple *stmt)
+   return true;
+ }
+ 
++/* Return true if VAR is a two-valued variable.  Set a and b with the
++   two-values when it is true.  Return false otherwise.  */
++
++static bool
++two_valued_val_range_p (tree var, tree *a, tree *b)
++{
++  value_range *vr = get_value_range (var);
++  if ((vr->type != VR_RANGE
++       && vr->type != VR_ANTI_RANGE)
++      || TREE_CODE (vr->min) != INTEGER_CST
++      || TREE_CODE (vr->max) != INTEGER_CST)
++    return false;
++
++  if (vr->type == VR_RANGE
++      && wi::sub (vr->max, vr->min) == 1)
++    {
++      *a = vr->min;
++      *b = vr->max;
++      return true;
++    }
++
++  /* ~[TYPE_MIN + 1, TYPE_MAX - 1] */
++  if (vr->type == VR_ANTI_RANGE
++      && wi::sub (vr->min, vrp_val_min (TREE_TYPE (var))) == 1
++      && wi::sub (vrp_val_max (TREE_TYPE (var)), vr->max) == 1)
++    {
++      *a = vrp_val_min (TREE_TYPE (var));
++      *b = vrp_val_max (TREE_TYPE (var));
++      return true;
++    }
++
++  return false;
++}
++
+ /* Simplify STMT using ranges if possible.  */
+ 
+ static bool
+@@ -9927,6 +9980,68 @@ simplify_stmt_using_ranges (gimple_stmt_iterator *gsi)
+     {
+       enum tree_code rhs_code = gimple_assign_rhs_code (stmt);
+       tree rhs1 = gimple_assign_rhs1 (stmt);
++      tree rhs2 = gimple_assign_rhs2 (stmt);
++      tree lhs = gimple_assign_lhs (stmt);
++      tree val1 = NULL_TREE, val2 = NULL_TREE;
++      use_operand_p use_p;
++      gimple *use_stmt;
++
++      /* Convert:
++	 LHS = CST BINOP VAR
++	 Where VAR is two-valued and LHS is used in GIMPLE_COND only
++	 To:
++	 LHS = VAR == VAL1 ? (CST BINOP VAL1) : (CST BINOP VAL2)
++
++	 Also handles:
++	 LHS = VAR BINOP CST
++	 Where VAR is two-valued and LHS is used in GIMPLE_COND only
++	 To:
++	 LHS = VAR == VAL1 ? (VAL1 BINOP CST) : (VAL2 BINOP CST) */
++
++      if (TREE_CODE_CLASS (rhs_code) == tcc_binary
++	  && INTEGRAL_TYPE_P (TREE_TYPE (lhs))
++	  && ((TREE_CODE (rhs1) == INTEGER_CST
++	       && TREE_CODE (rhs2) == SSA_NAME)
++	      || (TREE_CODE (rhs2) == INTEGER_CST
++		  && TREE_CODE (rhs1) == SSA_NAME))
++	  && single_imm_use (lhs, &use_p, &use_stmt)
++	  && gimple_code (use_stmt) == GIMPLE_COND)
++
++	{
++	  tree new_rhs1 = NULL_TREE;
++	  tree new_rhs2 = NULL_TREE;
++	  tree cmp_var = NULL_TREE;
++
++	  if (TREE_CODE (rhs2) == SSA_NAME
++	      && two_valued_val_range_p (rhs2, &val1, &val2))
++	    {
++	      /* Optimize RHS1 OP [VAL1, VAL2].  */
++	      new_rhs1 = int_const_binop (rhs_code, rhs1, val1);
++	      new_rhs2 = int_const_binop (rhs_code, rhs1, val2);
++	      cmp_var = rhs2;
++	    }
++	  else if (TREE_CODE (rhs1) == SSA_NAME
++		   && two_valued_val_range_p (rhs1, &val1, &val2))
++	    {
++	      /* Optimize [VAL1, VAL2] OP RHS2.  */
++	      new_rhs1 = int_const_binop (rhs_code, val1, rhs2);
++	      new_rhs2 = int_const_binop (rhs_code, val2, rhs2);
++	      cmp_var = rhs1;
++	    }
++
++	  /* If we could not find two-vals or the optimzation is invalid as
++	     in divide by zero, new_rhs1 / new_rhs will be NULL_TREE.  */
++	  if (new_rhs1 && new_rhs2)
++	    {
++	      tree cond = build2 (EQ_EXPR, TREE_TYPE (cmp_var), cmp_var, val1);
++	      gimple_assign_set_rhs_with_ops (gsi,
++					      COND_EXPR, cond,
++					      new_rhs1,
++					      new_rhs2);
++	      update_stmt (gsi_stmt (*gsi));
++	      return true;
++	    }
++	}
+ 
+       switch (rhs_code)
+ 	{
+--- a/src/gcc/tree.h
++++ b/src/gcc/tree.h
+@@ -4628,69 +4628,6 @@ extern void warn_deprecated_use (tree, tree);
+ extern void cache_integer_cst (tree);
+ extern const char *combined_fn_name (combined_fn);
+ 
+-/* Return the memory model from a host integer.  */
+-static inline enum memmodel
+-memmodel_from_int (unsigned HOST_WIDE_INT val)
+-{
+-  return (enum memmodel) (val & MEMMODEL_MASK);
+-}
+-
+-/* Return the base memory model from a host integer.  */
+-static inline enum memmodel
+-memmodel_base (unsigned HOST_WIDE_INT val)
+-{
+-  return (enum memmodel) (val & MEMMODEL_BASE_MASK);
+-}
+-
+-/* Return TRUE if the memory model is RELAXED.  */
+-static inline bool
+-is_mm_relaxed (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELAXED;
+-}
+-
+-/* Return TRUE if the memory model is CONSUME.  */
+-static inline bool
+-is_mm_consume (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_CONSUME;
+-}
+-
+-/* Return TRUE if the memory model is ACQUIRE.  */
+-static inline bool
+-is_mm_acquire (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQUIRE;
+-}
+-
+-/* Return TRUE if the memory model is RELEASE.  */
+-static inline bool
+-is_mm_release (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELEASE;
+-}
+-
+-/* Return TRUE if the memory model is ACQ_REL.  */
+-static inline bool
+-is_mm_acq_rel (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQ_REL;
+-}
+-
+-/* Return TRUE if the memory model is SEQ_CST.  */
+-static inline bool
+-is_mm_seq_cst (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_SEQ_CST;
+-}
+-
+-/* Return TRUE if the memory model is a SYNC variant.  */
+-static inline bool
+-is_mm_sync (enum memmodel model)
+-{
+-  return (model & MEMMODEL_SYNC);
+-}
+-
+ /* Compare and hash for any structure which begins with a canonical
+    pointer.  Assumes all pointers are interchangeable, which is sort
+    of already assumed by gcc elsewhere IIRC.  */
+--- a/src/gcc/tsan.c
++++ b/src/gcc/tsan.c
+@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "backend.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "tree-pass.h"
+ #include "ssa.h"
+--- a/src/gcc/varasm.c
++++ b/src/gcc/varasm.c
+@@ -6776,6 +6776,16 @@ default_use_anchors_for_symbol_p (const_rtx symbol)
+ 	 sections that should be marked as small in the section directive.  */
+       if (targetm.in_small_data_p (decl))
+ 	return false;
++
++      /* Don't use section anchors for decls that won't fit inside a single
++	 anchor range to reduce the amount of instructions required to refer
++	 to the entire declaration.  */
++      if (DECL_SIZE_UNIT (decl) == NULL_TREE
++	  || !tree_fits_uhwi_p (DECL_SIZE_UNIT (decl))
++	  || (tree_to_uhwi (DECL_SIZE_UNIT (decl))
++	      >= (unsigned HOST_WIDE_INT) targetm.max_anchor_offset))
++	return false;
++
+     }
+   return true;
+ }
+--- a/src/libcpp/expr.c
++++ b/src/libcpp/expr.c
+@@ -1073,7 +1073,7 @@ eval_token (cpp_reader *pfile, const cpp_token *token,
+ 	  result.low = 0;
+ 	  if (CPP_OPTION (pfile, warn_undef) && !pfile->state.skip_eval)
+ 	    cpp_warning_with_line (pfile, CPP_W_UNDEF, virtual_location, 0,
+-				   "\"%s\" is not defined",
++				   "\"%s\" is not defined, evaluates to 0",
+ 				   NODE_NAME (token->val.node.node));
+ 	}
+       break;
+--- a/src/libgcc/Makefile.in
++++ b/src/libgcc/Makefile.in
+@@ -414,8 +414,9 @@ lib2funcs = _muldi3 _negdi2 _lshrdi3 _ashldi3 _ashrdi3 _cmpdi2 _ucmpdi2	   \
+ 	    _negvsi2 _negvdi2 _ctors _ffssi2 _ffsdi2 _clz _clzsi2 _clzdi2  \
+ 	    _ctzsi2 _ctzdi2 _popcount_tab _popcountsi2 _popcountdi2	   \
+ 	    _paritysi2 _paritydi2 _powisf2 _powidf2 _powixf2 _powitf2	   \
+-	    _mulsc3 _muldc3 _mulxc3 _multc3 _divsc3 _divdc3 _divxc3	   \
+-	    _divtc3 _bswapsi2 _bswapdi2 _clrsbsi2 _clrsbdi2
++	    _mulhc3 _mulsc3 _muldc3 _mulxc3 _multc3 _divhc3 _divsc3	   \
++	    _divdc3 _divxc3 _divtc3 _bswapsi2 _bswapdi2 _clrsbsi2	   \
++	    _clrsbdi2
+ 
+ # The floating-point conversion routines that involve a single-word integer.
+ # XX stands for the integer mode.
+--- a/src/libgcc/config/arm/bpabi-v6m.S
++++ b/src/libgcc/config/arm/bpabi-v6m.S
+@@ -1,4 +1,5 @@
+-/* Miscellaneous BPABI functions.  ARMv6M implementation
++/* Miscellaneous BPABI functions.  Thumb-1 implementation, suitable for ARMv4T,
++   ARMv6-M and ARMv8-M Baseline like ISA variants.
+ 
+    Copyright (C) 2006-2016 Free Software Foundation, Inc.
+    Contributed by CodeSourcery.
+--- /dev/null
++++ b/src/libgcc/config/arm/cmse.c
+@@ -0,0 +1,108 @@
++/* ARMv8-M Security Extensions routines.
++   Copyright (C) 2015-2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by the
++   Free Software Foundation; either version 3, or (at your option) any
++   later version.
++
++   This file is distributed in the hope that it will be useful, but
++   WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   General Public License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++
++#if __ARM_FEATURE_CMSE & 1
++
++#include <arm_cmse.h>
++
++/* ARM intrinsic function to perform a permission check on a given
++   address range.  See ACLE changes for ARMv8-M.  */
++
++void *
++cmse_check_address_range (void *p, size_t size, int flags)
++{
++  cmse_address_info_t permb, perme;
++  char *pb = (char *) p, *pe;
++
++  /* Check if the range wraps around.  */
++  if (UINTPTR_MAX - (uintptr_t) p < size)
++    return NULL;
++
++  /* Check if an unknown flag is present.  */
++  int known = CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE | CMSE_MPU_READ;
++  int known_secure_level = CMSE_MPU_UNPRIV;
++#if __ARM_FEATURE_CMSE & 2
++  known |= CMSE_AU_NONSECURE | CMSE_MPU_NONSECURE;
++  known_secure_level |= CMSE_MPU_NONSECURE;
++#endif
++  if (flags & (~known))
++    return NULL;
++
++  /* Execute the right variant of the TT instructions.  */
++  pe = pb + size - 1;
++  const int singleCheck = (((uintptr_t) pb ^ (uintptr_t) pe) < 32);
++  switch (flags & known_secure_level)
++    {
++    case 0:
++      permb = cmse_TT (pb);
++      perme = singleCheck ? permb : cmse_TT (pe);
++      break;
++    case CMSE_MPU_UNPRIV:
++      permb = cmse_TTT (pb);
++      perme = singleCheck ? permb : cmse_TTT (pe);
++      break;
++#if __ARM_FEATURE_CMSE & 2
++    case CMSE_MPU_NONSECURE:
++      permb = cmse_TTA (pb);
++      perme = singleCheck ? permb : cmse_TTA (pe);
++      break;
++    case CMSE_MPU_UNPRIV | CMSE_MPU_NONSECURE:
++      permb = cmse_TTAT (pb);
++      perme = singleCheck ? permb : cmse_TTAT (pe);
++      break;
++#endif
++    default:
++      /* Invalid flag, eg.  CMSE_MPU_NONSECURE specified but
++	 __ARM_FEATURE_CMSE & 2 == 0.  */
++      return NULL;
++    }
++
++  /* Check that the range does not cross MPU, SAU, or IDAU boundaries.  */
++  if (permb.value != perme.value)
++    return NULL;
++
++  /* Check the permissions on the range.  */
++  switch (flags & (~known_secure_level))
++    {
++#if __ARM_FEATURE_CMSE & 2
++    case CMSE_MPU_READ | CMSE_MPU_READWRITE | CMSE_AU_NONSECURE:
++    case		 CMSE_MPU_READWRITE | CMSE_AU_NONSECURE:
++      return permb.flags.nonsecure_readwrite_ok	? p : NULL;
++    case CMSE_MPU_READ | CMSE_AU_NONSECURE:
++      return permb.flags.nonsecure_read_ok	? p : NULL;
++    case CMSE_AU_NONSECURE:
++      return permb.flags.secure			? NULL : p;
++#endif
++    case CMSE_MPU_READ | CMSE_MPU_READWRITE:
++    case		 CMSE_MPU_READWRITE:
++      return permb.flags.readwrite_ok		? p : NULL;
++    case CMSE_MPU_READ:
++      return permb.flags.read_ok		? p : NULL;
++    default:
++      return NULL;
++    }
++}
++
++
++#endif /* __ARM_FEATURE_CMSE & 1.  */
+--- /dev/null
++++ b/src/libgcc/config/arm/cmse_nonsecure_call.S
+@@ -0,0 +1,131 @@
++/* CMSE wrapper function used to save, clear and restore callee saved registers
++   for cmse_nonsecure_call's.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by the
++   Free Software Foundation; either version 3, or (at your option) any
++   later version.
++
++   This file is distributed in the hope that it will be useful, but
++   WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   General Public License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++.syntax unified
++.thumb
++.global __gnu_cmse_nonsecure_call
++__gnu_cmse_nonsecure_call:
++#if defined(__ARM_ARCH_8M_MAIN__)
++push	    {r5-r11,lr}
++mov	    r7, r4
++mov	    r8, r4
++mov	    r9, r4
++mov	    r10, r4
++mov	    r11, r4
++mov	    ip, r4
++
++/* Save and clear callee-saved registers only if we are dealing with hard float
++   ABI.  The unused caller-saved registers have already been cleared by GCC
++   generated code.  */
++#ifdef __ARM_PCS_VFP
++vpush.f64   {d8-d15}
++mov	    r5, #0
++vmov	    d8, r5, r5
++#if __ARM_FP & 0x04
++vmov	    s18, s19, r5, r5
++vmov	    s20, s21, r5, r5
++vmov	    s22, s23, r5, r5
++vmov	    s24, s25, r5, r5
++vmov	    s26, s27, r5, r5
++vmov	    s28, s29, r5, r5
++vmov	    s30, s31, r5, r5
++#elif __ARM_FP & 0x08
++vmov.f64    d9, d8
++vmov.f64    d10, d8
++vmov.f64    d11, d8
++vmov.f64    d12, d8
++vmov.f64    d13, d8
++vmov.f64    d14, d8
++vmov.f64    d15, d8
++#else
++#error "Half precision implementation not supported."
++#endif
++/* Clear the cumulative exception-status bits (0-4,7) and the
++   condition code bits (28-31) of the FPSCR.  */
++vmrs	    r5, fpscr
++movw	    r6, #65376
++movt	    r6, #4095
++ands	    r5, r6
++vmsr	    fpscr, r5
++
++/* We are not dealing with hard float ABI, so we can safely use the vlstm and
++   vlldm instructions without needing to preserve the registers used for
++   argument passing.  */
++#else
++sub	    sp, sp, #0x88 /* Reserve stack space to save all floating point
++			     registers, including FPSCR.  */
++vlstm	    sp		  /* Lazy store and clearance of d0-d16 and FPSCR.  */
++#endif /* __ARM_PCS_VFP */
++
++/* Make sure to clear the 'GE' bits of the APSR register if 32-bit SIMD
++   instructions are available.  */
++#if defined(__ARM_FEATURE_SIMD32)
++msr	    APSR_nzcvqg, r4
++#else
++msr	    APSR_nzcvq, r4
++#endif
++
++mov	    r5, r4
++mov	    r6, r4
++blxns	    r4
++
++#ifdef __ARM_PCS_VFP
++vpop.f64    {d8-d15}
++#else
++vlldm	    sp		  /* Lazy restore of d0-d16 and FPSCR.  */
++add	    sp, sp, #0x88 /* Free space used to save floating point registers.  */
++#endif /* __ARM_PCS_VFP */
++
++pop	    {r5-r11, pc}
++
++#elif defined (__ARM_ARCH_8M_BASE__)
++push	    {r5-r7, lr}
++mov	    r5, r8
++mov	    r6, r9
++mov	    r7, r10
++push	    {r5-r7}
++mov	    r5, r11
++push	    {r5}
++mov	    r5, r4
++mov	    r6, r4
++mov	    r7, r4
++mov	    r8, r4
++mov	    r9, r4
++mov	    r10, r4
++mov	    r11, r4
++mov	    ip, r4
++msr	    APSR_nzcvq, r4
++blxns	    r4
++pop	    {r5}
++mov	    r11, r5
++pop	    {r5-r7}
++mov	    r10, r7
++mov	    r9, r6
++mov	    r8, r5
++pop	    {r5-r7, pc}
++
++#else
++#error "This should only be used for armv8-m base- and mainline."
++#endif
+--- a/src/libgcc/config/arm/ieee754-df.S
++++ b/src/libgcc/config/arm/ieee754-df.S
+@@ -160,8 +160,8 @@ ARM_FUNC_ALIAS aeabi_dadd adddf3
+ 	teq	r4, r5
+ 	beq	LSYM(Lad_d)
+ 
+-@ CFI note: we're lucky that the branches to Lad_* that appear after this function
+-@ have a CFI state that's exactly the same as the one we're in at this
++@ CFI note: we're lucky that the branches to Lad_* that appear after this
++@ function have a CFI state that's exactly the same as the one we're in at this
+ @ point. Otherwise the CFI would change to a different state after the branch,
+ @ which would be disastrous for backtracing.
+ LSYM(Lad_x):
+@@ -507,11 +507,15 @@ ARM_FUNC_ALIAS aeabi_f2d extendsfdf2
+ 	eorne	xh, xh, #0x38000000	@ fixup exponent otherwise.
+ 	RETc(ne)			@ and return it.
+ 
+-	teq	r2, #0			@ if actually 0
+-	do_it	ne, e
+-	teqne	r3, #0xff000000		@ or INF or NAN
++	bics	r2, r2, #0xff000000	@ isolate mantissa
++	do_it	eq			@ if 0, that is ZERO or INF,
+ 	RETc(eq)			@ we are done already.
+ 
++	teq	r3, #0xff000000		@ check for NAN
++	do_it	eq, t
++	orreq	xh, xh, #0x00080000	@ change to quiet NAN
++	RETc(eq)			@ and return it.
++
+ 	@ value was denormalized.  We can normalize it now.
+ 	do_push	{r4, r5, lr}
+ 	.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+@@ -1158,8 +1162,8 @@ ARM_FUNC_ALIAS eqdf2 cmpdf2
+ 1:	str	ip, [sp, #-4]!
+ 	.cfi_adjust_cfa_offset 4        @ CFA is now sp + previousOffset + 4.
+ 	@ We're not adding CFI for ip as it's pushed into the stack
+-	@ only because @ it may be popped off later as a return value
+-	@ (i.e. we're not preserving @ it anyways).
++	@ only because it may be popped off later as a return value
++	@ (i.e. we're not preserving it anyways).
+ 
+ 	@ Trap any INF/NAN first.
+ 	mov	ip, xh, lsl #1
+@@ -1169,14 +1173,14 @@ ARM_FUNC_ALIAS eqdf2 cmpdf2
+ 	COND(mvn,s,ne)	ip, ip, asr #21
+ 	beq	3f
+ 	.cfi_remember_state
+-	@ Save the current CFI state. This is done because the branch
+-	@ is conditional, @ and if we don't take it we'll issue a
+-	@ .cfi_adjust_cfa_offset and return.  @ If we do take it,
+-	@ however, the .cfi_adjust_cfa_offset from the non-branch @ code
+-	@ will affect the branch code as well. To avoid this we'll
+-	@ restore @ the current state before executing the branch code.
+-
+-	@ Test for equality.  @ Note that 0.0 is equal to -0.0.
++	@ Save the current CFI state.  This is done because the branch
++	@ is conditional, and if we don't take it we'll issue a
++	@ .cfi_adjust_cfa_offset and return.  If we do take it,
++	@ however, the .cfi_adjust_cfa_offset from the non-branch code
++	@ will affect the branch code as well.  To avoid this we'll
++	@ restore the current state before executing the branch code.
++
++	@ Test for equality.  Note that 0.0 is equal to -0.0.
+ 2:	add	sp, sp, #4
+ 	.cfi_adjust_cfa_offset -4       @ CFA is now sp + previousOffset.
+ 
+--- a/src/libgcc/config/arm/lib1funcs.S
++++ b/src/libgcc/config/arm/lib1funcs.S
+@@ -108,7 +108,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ # define __ARM_ARCH__ 7
+ #endif
+ 
+-#if defined(__ARM_ARCH_8A__)
++#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
++	|| defined(__ARM_ARCH_8M_MAIN__)
+ # define __ARM_ARCH__ 8
+ #endif
+ 
+@@ -124,10 +125,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+      && !defined(__thumb2__)		\
+      && (!defined(__THUMB_INTERWORK__)	\
+ 	 || defined (__OPTIMIZE_SIZE__)	\
+-	 || defined(__ARM_ARCH_6M__)))
++	 || !__ARM_ARCH_ISA_ARM))
+ # define __prefer_thumb__
+ #endif
+ 
++#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
++#define NOT_ISA_TARGET_32BIT 1
++#endif
++
+ /* How to return from a function call depends on the architecture variant.  */
+ 
+ #if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__)
+@@ -305,35 +310,14 @@ LSYM(Lend_fde):
+ 
+ #ifdef __ARM_EABI__
+ .macro THUMB_LDIV0 name signed
+-#if defined(__ARM_ARCH_6M__)
+-	.ifc \signed, unsigned
+-	cmp	r0, #0
+-	beq	1f
+-	mov	r0, #0
+-	mvn	r0, r0		@ 0xffffffff
+-1:
+-	.else
+-	cmp	r0, #0
+-	beq	2f
+-	blt	3f
++#ifdef NOT_ISA_TARGET_32BIT
++
++	push	{r0, lr}
+ 	mov	r0, #0
+-	mvn	r0, r0
+-	lsr	r0, r0, #1	@ 0x7fffffff
+-	b	2f
+-3:	mov	r0, #0x80
+-	lsl	r0, r0, #24	@ 0x80000000
+-2:
+-	.endif
+-	push	{r0, r1, r2}
+-	ldr	r0, 4f
+-	adr	r1, 4f
+-	add	r0, r1
+-	str	r0, [sp, #8]
++	bl	SYM(__aeabi_idiv0)
+ 	@ We know we are not on armv4t, so pop pc is safe.
+-	pop	{r0, r1, pc}
+-	.align	2
+-4:
+-	.word	__aeabi_idiv0 - 4b
++	pop	{r1, pc}
++
+ #elif defined(__thumb2__)
+ 	.syntax unified
+ 	.ifc \signed, unsigned
+@@ -478,7 +462,7 @@ _L__\name:
+ 
+ #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */
+ 
+-#ifdef __ARM_ARCH_6M__
++#ifdef NOT_ISA_TARGET_32BIT
+ #define EQUIV .thumb_set
+ #else
+ .macro	ARM_FUNC_START name sp_section=
+@@ -510,7 +494,7 @@ SYM (__\name):
+ #endif
+ .endm
+ 
+-#ifndef __ARM_ARCH_6M__
++#ifndef NOT_ISA_TARGET_32BIT
+ .macro	ARM_FUNC_ALIAS new old
+ 	.globl	SYM (__\new)
+ 	EQUIV	SYM (__\new), SYM (__\old)
+@@ -945,7 +929,170 @@ LSYM(Lover7):
+ 	add	dividend, work
+   .endif
+ LSYM(Lgot_result):
+-.endm	
++.endm
++
++/* If performance is preferred, the following functions are provided.  */
++#if defined(__prefer_thumb__) && !defined(__OPTIMIZE_SIZE__)
++
++/* Branch to div(n), and jump to label if curbit is lo than divisior.  */
++.macro BranchToDiv n, label
++	lsr	curbit, dividend, \n
++	cmp	curbit, divisor
++	blo	\label
++.endm
++
++/* Body of div(n).  Shift the divisor in n bits and compare the divisor
++   and dividend.  Update the dividend as the substruction result.  */
++.macro DoDiv n
++	lsr	curbit, dividend, \n
++	cmp	curbit, divisor
++	bcc	1f
++	lsl	curbit, divisor, \n
++	sub	dividend, dividend, curbit
++
++1:	adc	result, result
++.endm
++
++/* The body of division with positive divisor.  Unless the divisor is very
++   big, shift it up in multiples of four bits, since this is the amount of
++   unwinding in the main division loop.  Continue shifting until the divisor
++   is larger than the dividend.  */
++.macro THUMB1_Div_Positive
++	mov	result, #0
++	BranchToDiv #1, LSYM(Lthumb1_div1)
++	BranchToDiv #4, LSYM(Lthumb1_div4)
++	BranchToDiv #8, LSYM(Lthumb1_div8)
++	BranchToDiv #12, LSYM(Lthumb1_div12)
++	BranchToDiv #16, LSYM(Lthumb1_div16)
++LSYM(Lthumb1_div_large_positive):
++	mov	result, #0xff
++	lsl	divisor, divisor, #8
++	rev	result, result
++	lsr	curbit, dividend, #16
++	cmp	curbit, divisor
++	blo	1f
++	asr	result, #8
++	lsl	divisor, divisor, #8
++	beq	LSYM(Ldivbyzero_waypoint)
++
++1:	lsr	curbit, dividend, #12
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div12)
++	b	LSYM(Lthumb1_div16)
++LSYM(Lthumb1_div_loop):
++	lsr	divisor, divisor, #8
++LSYM(Lthumb1_div16):
++	Dodiv	#15
++	Dodiv	#14
++	Dodiv	#13
++	Dodiv	#12
++LSYM(Lthumb1_div12):
++	Dodiv	#11
++	Dodiv	#10
++	Dodiv	#9
++	Dodiv	#8
++	bcs	LSYM(Lthumb1_div_loop)
++LSYM(Lthumb1_div8):
++	Dodiv	#7
++	Dodiv	#6
++	Dodiv	#5
++LSYM(Lthumb1_div5):
++	Dodiv	#4
++LSYM(Lthumb1_div4):
++	Dodiv	#3
++LSYM(Lthumb1_div3):
++	Dodiv	#2
++LSYM(Lthumb1_div2):
++	Dodiv	#1
++LSYM(Lthumb1_div1):
++	sub	divisor, dividend, divisor
++	bcs	1f
++	cpy	divisor, dividend
++
++1:	adc	result, result
++	cpy	dividend, result
++	RET
++
++LSYM(Ldivbyzero_waypoint):
++	b	LSYM(Ldiv0)
++.endm
++
++/* The body of division with negative divisor.  Similar with
++   THUMB1_Div_Positive except that the shift steps are in multiples
++   of six bits.  */
++.macro THUMB1_Div_Negative
++	lsr	result, divisor, #31
++	beq	1f
++	neg	divisor, divisor
++
++1:	asr	curbit, dividend, #32
++	bcc	2f
++	neg	dividend, dividend
++
++2:	eor	curbit, result
++	mov	result, #0
++	cpy	ip, curbit
++	BranchToDiv #4, LSYM(Lthumb1_div_negative4)
++	BranchToDiv #8, LSYM(Lthumb1_div_negative8)
++LSYM(Lthumb1_div_large):
++	mov	result, #0xfc
++	lsl	divisor, divisor, #6
++	rev	result, result
++	lsr	curbit, dividend, #8
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div_negative8)
++
++	lsl	divisor, divisor, #6
++	asr	result, result, #6
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div_negative8)
++
++	lsl	divisor, divisor, #6
++	asr	result, result, #6
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div_negative8)
++
++	lsl	divisor, divisor, #6
++	beq	LSYM(Ldivbyzero_negative)
++	asr	result, result, #6
++	b	LSYM(Lthumb1_div_negative8)
++LSYM(Lthumb1_div_negative_loop):
++	lsr	divisor, divisor, #6
++LSYM(Lthumb1_div_negative8):
++	DoDiv	#7
++	DoDiv	#6
++	DoDiv	#5
++	DoDiv	#4
++LSYM(Lthumb1_div_negative4):
++	DoDiv	#3
++	DoDiv	#2
++	bcs	LSYM(Lthumb1_div_negative_loop)
++	DoDiv	#1
++	sub	divisor, dividend, divisor
++	bcs	1f
++	cpy	divisor, dividend
++
++1:	cpy	curbit, ip
++	adc	result, result
++	asr	curbit, curbit, #1
++	cpy	dividend, result
++	bcc	2f
++	neg	dividend, dividend
++	cmp	curbit, #0
++
++2:	bpl	3f
++	neg	divisor, divisor
++
++3:	RET
++
++LSYM(Ldivbyzero_negative):
++	cpy	curbit, ip
++	asr	curbit, curbit, #1
++	bcc	LSYM(Ldiv0)
++	neg	dividend, dividend
++.endm
++#endif /* ARM Thumb version.  */
++
+ /* ------------------------------------------------------------------------ */
+ /*		Start of the Real Functions				    */
+ /* ------------------------------------------------------------------------ */
+@@ -955,6 +1102,7 @@ LSYM(Lgot_result):
+ 
+ 	FUNC_START udivsi3
+ 	FUNC_ALIAS aeabi_uidiv udivsi3
++#if defined(__OPTIMIZE_SIZE__)
+ 
+ 	cmp	divisor, #0
+ 	beq	LSYM(Ldiv0)
+@@ -972,6 +1120,14 @@ LSYM(udivsi3_skip_div0_test):
+ 	pop	{ work }
+ 	RET
+ 
++/* Implementation of aeabi_uidiv for ARMv6m.  This version is only
++   used in ARMv6-M when we need an efficient implementation.  */
++#else
++LSYM(udivsi3_skip_div0_test):
++	THUMB1_Div_Positive
++
++#endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ 
+ 	ARM_FUNC_START udivsi3
+@@ -1023,12 +1179,21 @@ LSYM(udivsi3_skip_div0_test):
+ FUNC_START aeabi_uidivmod
+ 	cmp	r1, #0
+ 	beq	LSYM(Ldiv0)
++# if defined(__OPTIMIZE_SIZE__)
+ 	push	{r0, r1, lr}
+ 	bl	LSYM(udivsi3_skip_div0_test)
+ 	POP	{r1, r2, r3}
+ 	mul	r2, r0
+ 	sub	r1, r1, r2
+ 	bx	r3
++# else
++	/* Both the quotient and remainder are calculated simultaneously
++	   in THUMB1_Div_Positive.  There is no need to calculate the
++	   remainder again here.  */
++	b	LSYM(udivsi3_skip_div0_test)
++	RET
++# endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ ARM_FUNC_START aeabi_uidivmod
+ 	cmp	r1, #0
+@@ -1054,7 +1219,7 @@ ARM_FUNC_START aeabi_uidivmod
+ /* ------------------------------------------------------------------------ */
+ #ifdef L_umodsi3
+ 
+-#ifdef __ARM_ARCH_EXT_IDIV__
++#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
+ 
+ 	ARM_FUNC_START umodsi3
+ 
+@@ -1084,7 +1249,7 @@ LSYM(Lover10):
+ 	RET
+ 	
+ #else  /* ARM version.  */
+-	
++
+ 	FUNC_START umodsi3
+ 
+ 	subs	r2, r1, #1			@ compare divisor with 1
+@@ -1109,8 +1274,9 @@ LSYM(Lover10):
+ 
+ #if defined(__prefer_thumb__)
+ 
+-	FUNC_START divsi3	
++	FUNC_START divsi3
+ 	FUNC_ALIAS aeabi_idiv divsi3
++#if defined(__OPTIMIZE_SIZE__)
+ 
+ 	cmp	divisor, #0
+ 	beq	LSYM(Ldiv0)
+@@ -1133,7 +1299,7 @@ LSYM(Lover11):
+ 	blo	LSYM(Lgot_result)
+ 
+ 	THUMB_DIV_MOD_BODY 0
+-	
++
+ 	mov	r0, result
+ 	mov	work, ip
+ 	cmp	work, #0
+@@ -1143,6 +1309,22 @@ LSYM(Lover12):
+ 	pop	{ work }
+ 	RET
+ 
++/* Implementation of aeabi_idiv for ARMv6m.  This version is only
++   used in ARMv6-M when we need an efficient implementation.  */
++#else
++LSYM(divsi3_skip_div0_test):
++	cpy	curbit, dividend
++	orr	curbit, divisor
++	bmi	LSYM(Lthumb1_div_negative)
++
++LSYM(Lthumb1_div_positive):
++	THUMB1_Div_Positive
++
++LSYM(Lthumb1_div_negative):
++	THUMB1_Div_Negative
++
++#endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ 
+ 	ARM_FUNC_START divsi3
+@@ -1154,8 +1336,8 @@ LSYM(Lover12):
+ 	RET
+ 
+ #else /* ARM/Thumb-2 version.  */
+-	
+-	ARM_FUNC_START divsi3	
++
++	ARM_FUNC_START divsi3
+ 	ARM_FUNC_ALIAS aeabi_idiv divsi3
+ 
+ 	cmp	r1, #0
+@@ -1209,12 +1391,21 @@ LSYM(divsi3_skip_div0_test):
+ FUNC_START aeabi_idivmod
+ 	cmp	r1, #0
+ 	beq	LSYM(Ldiv0)
++# if defined(__OPTIMIZE_SIZE__)
+ 	push	{r0, r1, lr}
+ 	bl	LSYM(divsi3_skip_div0_test)
+ 	POP	{r1, r2, r3}
+ 	mul	r2, r0
+ 	sub	r1, r1, r2
+ 	bx	r3
++# else
++	/* Both the quotient and remainder are calculated simultaneously
++	   in THUMB1_Div_Positive and THUMB1_Div_Negative.  There is no
++	   need to calculate the remainder again here.  */
++	b	LSYM(divsi3_skip_div0_test)
++	RET
++# endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ ARM_FUNC_START aeabi_idivmod
+ 	cmp 	r1, #0
+@@ -1240,7 +1431,7 @@ ARM_FUNC_START aeabi_idivmod
+ /* ------------------------------------------------------------------------ */
+ #ifdef L_modsi3
+ 
+-#if defined(__ARM_ARCH_EXT_IDIV__)
++#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
+ 
+ 	ARM_FUNC_START modsi3
+ 
+@@ -1508,14 +1699,15 @@ LSYM(Lover12):
+ 
+ #endif /* __symbian__ */
+ 
+-#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \
+-    || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
+-    || defined(__ARM_ARCH_5TEJ__)
++#if (__ARM_ARCH_ISA_THUMB == 2	\
++     || (__ARM_ARCH_ISA_ARM	\
++	 && (__ARM_ARCH__ > 5	\
++	     || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB))))
+ #define HAVE_ARM_CLZ 1
+ #endif
+ 
+ #ifdef L_clzsi2
+-#if defined(__ARM_ARCH_6M__)
++#ifdef NOT_ISA_TARGET_32BIT
+ FUNC_START clzsi2
+ 	mov	r1, #28
+ 	mov	r3, #1
+@@ -1576,7 +1768,7 @@ ARM_FUNC_START clzsi2
+ #ifdef L_clzdi2
+ #if !defined(HAVE_ARM_CLZ)
+ 
+-# if defined(__ARM_ARCH_6M__)
++# ifdef NOT_ISA_TARGET_32BIT
+ FUNC_START clzdi2
+ 	push	{r4, lr}
+ # else
+@@ -1601,7 +1793,7 @@ ARM_FUNC_START clzdi2
+ 	bl	__clzsi2
+ # endif
+ 2:
+-# if defined(__ARM_ARCH_6M__)
++# ifdef NOT_ISA_TARGET_32BIT
+ 	pop	{r4, pc}
+ # else
+ 	RETLDM	r4
+@@ -1623,7 +1815,7 @@ ARM_FUNC_START clzdi2
+ #endif /* L_clzdi2 */
+ 
+ #ifdef L_ctzsi2
+-#if defined(__ARM_ARCH_6M__)
++#ifdef NOT_ISA_TARGET_32BIT
+ FUNC_START ctzsi2
+ 	neg	r1, r0
+ 	and	r0, r0, r1
+@@ -1738,7 +1930,7 @@ ARM_FUNC_START ctzsi2
+ 
+ /* Don't bother with the old interworking routines for Thumb-2.  */
+ /* ??? Maybe only omit these on "m" variants.  */
+-#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__)
++#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM
+ 
+ #if defined L_interwork_call_via_rX
+ 
+@@ -1983,11 +2175,12 @@ LSYM(Lchange_\register):
+ .endm
+ 
+ #ifndef __symbian__
+-#ifndef __ARM_ARCH_6M__
++/* The condition here must match the one in gcc/config/arm/elf.h.  */
++#ifndef NOT_ISA_TARGET_32BIT
+ #include "ieee754-df.S"
+ #include "ieee754-sf.S"
+ #include "bpabi.S"
+-#else /* __ARM_ARCH_6M__ */
++#else /* NOT_ISA_TARGET_32BIT */
+ #include "bpabi-v6m.S"
+-#endif /* __ARM_ARCH_6M__ */
++#endif /* NOT_ISA_TARGET_32BIT */
+ #endif /* !__symbian__ */
+--- a/src/libgcc/config/arm/libunwind.S
++++ b/src/libgcc/config/arm/libunwind.S
+@@ -58,7 +58,7 @@
+ #endif
+ #endif
+ 
+-#ifdef __ARM_ARCH_6M__
++#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
+ 
+ /* r0 points to a 16-word block.  Upload these values to the actual core
+    state.  */
+@@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC
+ 	UNPREFIX \name
+ .endm
+ 
+-#else /* !__ARM_ARCH_6M__ */
++#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
+ 
+ /* r0 points to a 16-word block.  Upload these values to the actual core
+    state.  */
+@@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC
+ 	UNPREFIX \name
+ .endm
+ 
+-#endif /* !__ARM_ARCH_6M__ */
++#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
+ 
+ UNWIND_WRAPPER _Unwind_RaiseException 1
+ UNWIND_WRAPPER _Unwind_Resume 1
+--- a/src/libgcc/config/arm/t-arm
++++ b/src/libgcc/config/arm/t-arm
+@@ -1,3 +1,17 @@
+ LIB1ASMSRC = arm/lib1funcs.S
+ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \
+ 	_thumb1_case_uhi _thumb1_case_si
++
++HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E - </dev/null))
++ifneq ($(shell $(gcc_compile_bare) -E -mcmse - </dev/null 2>/dev/null),)
++CMSE_OPTS:=-mcmse
++endif
++
++ifdef HAVE_CMSE
++libgcc-objects += cmse.o cmse_nonsecure_call.o
++
++cmse.o: $(srcdir)/config/arm/cmse.c
++	$(gcc_compile) -c $(CMSE_OPTS) $<
++cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
++		       $(gcc_compile) -c $<
++endif
+--- a/src/libgcc/config/arm/t-softfp
++++ b/src/libgcc/config/arm/t-softfp
+@@ -1,2 +1,2 @@
+-softfp_wrap_start := '\#ifdef __ARM_ARCH_6M__'
++softfp_wrap_start := '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1'
+ softfp_wrap_end := '\#endif'
+--- a/src/libgcc/libgcc2.c
++++ b/src/libgcc/libgcc2.c
+@@ -1852,7 +1852,8 @@ NAME (TYPE x, int m)
+ 
+ #endif
+ 
+-#if ((defined(L_mulsc3) || defined(L_divsc3)) && LIBGCC2_HAS_SF_MODE) \
++#if((defined(L_mulhc3) || defined(L_divhc3)) && LIBGCC2_HAS_HF_MODE) \
++    || ((defined(L_mulsc3) || defined(L_divsc3)) && LIBGCC2_HAS_SF_MODE) \
+     || ((defined(L_muldc3) || defined(L_divdc3)) && LIBGCC2_HAS_DF_MODE) \
+     || ((defined(L_mulxc3) || defined(L_divxc3)) && LIBGCC2_HAS_XF_MODE) \
+     || ((defined(L_multc3) || defined(L_divtc3)) && LIBGCC2_HAS_TF_MODE)
+@@ -1861,7 +1862,13 @@ NAME (TYPE x, int m)
+ #undef double
+ #undef long
+ 
+-#if defined(L_mulsc3) || defined(L_divsc3)
++#if defined(L_mulhc3) || defined(L_divhc3)
++# define MTYPE	HFtype
++# define CTYPE	HCtype
++# define MODE	hc
++# define CEXT	__LIBGCC_HF_FUNC_EXT__
++# define NOTRUNC (!__LIBGCC_HF_EXCESS_PRECISION__)
++#elif defined(L_mulsc3) || defined(L_divsc3)
+ # define MTYPE	SFtype
+ # define CTYPE	SCtype
+ # define MODE	sc
+@@ -1922,7 +1929,7 @@ extern void *compile_type_assert[sizeof(INFINITY) == sizeof(MTYPE) ? 1 : -1];
+ # define TRUNC(x)	__asm__ ("" : "=m"(x) : "m"(x))
+ #endif
+ 
+-#if defined(L_mulsc3) || defined(L_muldc3) \
++#if defined(L_mulhc3) || defined(L_mulsc3) || defined(L_muldc3) \
+     || defined(L_mulxc3) || defined(L_multc3)
+ 
+ CTYPE
+@@ -1992,7 +1999,7 @@ CONCAT3(__mul,MODE,3) (MTYPE a, MTYPE b, MTYPE c, MTYPE d)
+ }
+ #endif /* complex multiply */
+ 
+-#if defined(L_divsc3) || defined(L_divdc3) \
++#if defined(L_divhc3) || defined(L_divsc3) || defined(L_divdc3) \
+     || defined(L_divxc3) || defined(L_divtc3)
+ 
+ CTYPE
+--- a/src/libgcc/libgcc2.h
++++ b/src/libgcc/libgcc2.h
+@@ -34,6 +34,12 @@ extern void __clear_cache (char *, char *);
+ extern void __eprintf (const char *, const char *, unsigned int, const char *)
+   __attribute__ ((__noreturn__));
+ 
++#ifdef __LIBGCC_HAS_HF_MODE__
++#define LIBGCC2_HAS_HF_MODE 1
++#else
++#define LIBGCC2_HAS_HF_MODE 0
++#endif
++
+ #ifdef __LIBGCC_HAS_SF_MODE__
+ #define LIBGCC2_HAS_SF_MODE 1
+ #else
+@@ -133,6 +139,10 @@ typedef unsigned int UTItype	__attribute__ ((mode (TI)));
+ #endif
+ #endif
+ 
++#if LIBGCC2_HAS_HF_MODE
++typedef		float HFtype	__attribute__ ((mode (HF)));
++typedef _Complex float HCtype	__attribute__ ((mode (HC)));
++#endif
+ #if LIBGCC2_HAS_SF_MODE
+ typedef 	float SFtype	__attribute__ ((mode (SF)));
+ typedef _Complex float SCtype	__attribute__ ((mode (SC)));
+@@ -424,6 +434,10 @@ extern SItype __negvsi2 (SItype);
+ #endif /* COMPAT_SIMODE_TRAPPING_ARITHMETIC */
+ 
+ #undef int
++#if LIBGCC2_HAS_HF_MODE
++extern HCtype __divhc3 (HFtype, HFtype, HFtype, HFtype);
++extern HCtype __mulhc3 (HFtype, HFtype, HFtype, HFtype);
++#endif
+ #if LIBGCC2_HAS_SF_MODE
+ extern DWtype __fixsfdi (SFtype);
+ extern SFtype __floatdisf (DWtype);
+--- a/src/libstdc++-v3/acinclude.m4
++++ b/src/libstdc++-v3/acinclude.m4
+@@ -632,10 +632,10 @@ dnl  baseline_dir
+ dnl  baseline_subdir_switch
+ dnl
+ AC_DEFUN([GLIBCXX_CONFIGURE_TESTSUITE], [
+-  if $GLIBCXX_IS_NATIVE ; then
+-    # Do checks for resource limit functions.
+-    GLIBCXX_CHECK_SETRLIMIT
++  # Do checks for resource limit functions.
++  GLIBCXX_CHECK_SETRLIMIT
+ 
++  if $GLIBCXX_IS_NATIVE ; then
+     # Look for setenv, so that extended locale tests can be performed.
+     GLIBCXX_CHECK_STDLIB_DECL_AND_LINKAGE_3(setenv)
+   fi
+--- a/src/libstdc++-v3/configure
++++ b/src/libstdc++-v3/configure
+@@ -79518,8 +79518,7 @@ $as_echo "$ac_cv_x86_rdrand" >&6; }
+ 
+ # This depends on GLIBCXX_ENABLE_SYMVERS and GLIBCXX_IS_NATIVE.
+ 
+-  if $GLIBCXX_IS_NATIVE ; then
+-    # Do checks for resource limit functions.
++  # Do checks for resource limit functions.
+ 
+   setrlimit_have_headers=yes
+   for ac_header in unistd.h sys/time.h sys/resource.h
+@@ -79748,6 +79747,7 @@ $as_echo "#define _GLIBCXX_RES_LIMITS 1" >>confdefs.h
+ $as_echo "$ac_res_limits" >&6; }
+ 
+ 
++  if $GLIBCXX_IS_NATIVE ; then
+     # Look for setenv, so that extended locale tests can be performed.
+ 
+   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for setenv declaration" >&5
+--- a/src/libstdc++-v3/testsuite/29_atomics/atomic/65913.cc
++++ b/src/libstdc++-v3/testsuite/29_atomics/atomic/65913.cc
+@@ -15,7 +15,8 @@
+ // with this library; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+-// { dg-do run { target x86_64-*-linux* powerpc*-*-linux* } }
++// { dg-do run }
++// { dg-require-atomic-builtins "" }
+ // { dg-options "-std=gnu++11 -O0" }
+ 
+ #include <atomic>
--- gcc-6-6.3.0.orig/debian/patches/gcc-multiarch.diff
+++ gcc-6-6.3.0/debian/patches/gcc-multiarch.diff
@@ -0,0 +1,210 @@
+# DP: - Remaining multiarch patches, not yet submitted upstream.
+# DP: - Add MULTIARCH_DIRNAME definitions for multilib configurations,
+# DP:   which are used for the non-multilib builds.
+
+2013-06-12  Matthias Klose  <doko@ubuntu.com>
+
+	* config/i386/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/i386/t-kfreebsd: Set MULTIARCH_DIRNAME.
+	* config.gcc (i[34567]86-*-linux* | x86_64-*-linux*): Prepend
+	i386/t-linux to $tmake_file;
+	set default ABI to N64 for mips64el.
+	* config/mips/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/rs6000/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/s390/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/sparc/t-linux64: Set MULTIARCH_DIRNAME.
+	* src/gcc/config/mips/mips.h: (/usr)/lib as default path.
+
+Index: b/src/gcc/config/sh/t-linux
+===================================================================
+--- a/src/gcc/config/sh/t-linux
++++ b/src/gcc/config/sh/t-linux
+@@ -1,2 +1,10 @@
+ MULTILIB_DIRNAMES= 
+ MULTILIB_MATCHES = 
++
++ifneq (,$(findstring sh4,$(target)))
++MULTILIB_OSDIRNAMES = .:sh4-linux-gnu sh4_nofpu-linux-gnu:sh4-linux-gnu
++MULTIARCH_DIRNAME = $(call if_multiarch,sh4-linux-gnu)
++else
++MULTILIB_OSDIRNAMES = .:sh3-linux-gnu sh3_nofpu-linux-gnu:sh3-linux-gnu
++MULTIARCH_DIRNAME = $(call if_multiarch,sh3-linux-gnu)
++endif
+Index: b/src/gcc/config/sparc/t-linux64
+===================================================================
+--- a/src/gcc/config/sparc/t-linux64
++++ b/src/gcc/config/sparc/t-linux64
+@@ -27,3 +27,5 @@ MULTILIB_OPTIONS = m64/m32
+ MULTILIB_DIRNAMES = 64 32
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:sparc64-linux-gnu)
+ MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:sparc-linux-gnu)
++
++MULTIARCH_DIRNAME = $(call if_multiarch,sparc$(if $(findstring 64,$(target)),64)-linux-gnu)
+Index: b/src/gcc/config/s390/t-linux64
+===================================================================
+--- a/src/gcc/config/s390/t-linux64
++++ b/src/gcc/config/s390/t-linux64
+@@ -9,3 +9,5 @@ MULTILIB_OPTIONS = m64/m31
+ MULTILIB_DIRNAMES = 64 32
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:s390x-linux-gnu)
+ MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:s390-linux-gnu)
++
++MULTIARCH_DIRNAME = $(call if_multiarch,s390$(if $(findstring s390x,$(target)),x)-linux-gnu)
+Index: b/src/gcc/config/rs6000/t-linux64
+===================================================================
+--- a/src/gcc/config/rs6000/t-linux64
++++ b/src/gcc/config/rs6000/t-linux64
+@@ -31,6 +31,8 @@ MULTILIB_EXTRA_OPTS :=
+ MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
+ MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
+ 
++MULTIARCH_DIRNAME = $(call if_multiarch,powerpc$(if $(findstring 64,$(target)),64)-linux-gnu)
++
+ rs6000-linux.o: $(srcdir)/config/rs6000/rs6000-linux.c
+ 	$(COMPILE) $<
+ 	$(POSTCOMPILE)
+Index: b/src/gcc/config/i386/t-linux64
+===================================================================
+--- a/src/gcc/config/i386/t-linux64
++++ b/src/gcc/config/i386/t-linux64
+@@ -36,3 +36,13 @@ MULTILIB_DIRNAMES   = $(patsubst m%, %,
+ MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu)
+ MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:i386-linux-gnu)
+ MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32)
++
++ifneq (,$(findstring x86_64,$(target)))
++  ifneq (,$(findstring biarchx32.h,$(tm_include_list)))
++  MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnux32)
++  else
++  MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnu)
++  endif
++else
++  MULTIARCH_DIRNAME = $(call if_multiarch,i386-linux-gnu)
++endif
+Index: b/src/gcc/config/i386/t-kfreebsd
+===================================================================
+--- a/src/gcc/config/i386/t-kfreebsd
++++ b/src/gcc/config/i386/t-kfreebsd
+@@ -1,5 +1,9 @@
+-MULTIARCH_DIRNAME = $(call if_multiarch,i386-kfreebsd-gnu)
++ifeq (,$(MULTIARCH_DIRNAME))
++  MULTIARCH_DIRNAME = $(call if_multiarch,i386-kfreebsd-gnu)
++endif
+ 
+ # MULTILIB_OSDIRNAMES are set in t-linux64.
+ KFREEBSD_OS = $(filter kfreebsd%, $(word 3, $(subst -, ,$(target))))
+ MULTILIB_OSDIRNAMES := $(filter-out mx32=%,$(subst linux,$(KFREEBSD_OS),$(MULTILIB_OSDIRNAMES)))
++
++MULTIARCH_DIRNAME := $(subst linux,$(KFREEBSD_OS),$(MULTIARCH_DIRNAME))
+Index: b/src/gcc/config/mips/t-linux64
+===================================================================
+--- a/src/gcc/config/mips/t-linux64
++++ b/src/gcc/config/mips/t-linux64
+@@ -18,9 +18,22 @@
+ 
+ MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64
+ MULTILIB_DIRNAMES = n32 32 64
++MIPS_R6 = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),r6)
++MIPS_32 = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),32)
++MIPS_ISA = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),isa)
+ MIPS_EL = $(if $(filter %el, $(firstword $(subst -, ,$(target)))),el)
+ MIPS_SOFT = $(if $(strip $(filter MASK_SOFT_FLOAT_ABI, $(target_cpu_default)) $(filter soft, $(with_float))),soft)
+ MULTILIB_OSDIRNAMES = \
+ 	../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
+ 	../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
+ 	../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++
++ifneq (,$(findstring abin32,$(target)))
++MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT))
++else
++ifneq (,$(findstring abi64,$(target)))
++MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++else
++MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT))
++endif
++endif
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -2085,6 +2085,11 @@ mips*-*-linux*)				# Linux MIPS, either
+ 			target_cpu_default=MASK_SOFT_FLOAT_ABI
+ 			enable_mips_multilibs="yes"
+ 			;;
++		mipsisa64r6*-*-linux-gnuabi64)
++			default_mips_abi=64
++			default_mips_arch=mips64r6
++			enable_mips_multilibs="yes"
++			;;
+ 		mipsisa64r6*-*-linux*)
+ 			default_mips_abi=n32
+ 			default_mips_arch=mips64r6
+@@ -2095,6 +2100,10 @@ mips*-*-linux*)				# Linux MIPS, either
+ 			default_mips_arch=mips64r2
+ 			enable_mips_multilibs="yes"
+ 			;;
++		mips64*-*-linux-gnuabi64 | mipsisa64*-*-linux-gnuabi64)
++			default_mips_abi=64
++			enable_mips_multilibs="yes"
++			;;
+ 		mips64*-*-linux* | mipsisa64*-*-linux*)
+ 			default_mips_abi=n32
+ 			enable_mips_multilibs="yes"
+@@ -4414,7 +4423,7 @@ case ${target} in
+ 	i[34567]86-*-darwin* | x86_64-*-darwin*)
+ 		;;
+ 	i[34567]86-*-linux* | x86_64-*-linux*)
+-		tmake_file="$tmake_file i386/t-linux"
++		tmake_file="i386/t-linux $tmake_file"
+ 		;;
+ 	i[34567]86-*-kfreebsd*-gnu | x86_64-*-kfreebsd*-gnu)
+ 		tmake_file="$tmake_file i386/t-kfreebsd"
+Index: b/src/gcc/config/aarch64/t-aarch64-linux
+===================================================================
+--- a/src/gcc/config/aarch64/t-aarch64-linux
++++ b/src/gcc/config/aarch64/t-aarch64-linux
+@@ -22,7 +22,7 @@ LIB1ASMSRC   = aarch64/lib1funcs.asm
+ LIB1ASMFUNCS = _aarch64_sync_cache_range
+ 
+ AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
+-MULTILIB_OSDIRNAMES = mabi.lp64=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
+-MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
++MULTILIB_OSDIRNAMES = mabi.lp64=../lib$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
++MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)_ilp32-linux-gnu)
+ 
+-MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32
++MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -3375,16 +3375,6 @@ struct GTY(())  machine_function {
+ #define PMODE_INSN(NAME, ARGS) \
+   (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
+ 
+-/* If we are *not* using multilibs and the default ABI is not ABI_32 we
+-   need to change these from /lib and /usr/lib.  */
+-#if MIPS_ABI_DEFAULT == ABI_N32
+-#define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
+-#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
+-#elif MIPS_ABI_DEFAULT == ABI_64
+-#define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
+-#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
+-#endif
+-
+ /* Load store bonding is not supported by micromips and fix_24k.  The
+    performance can be degraded for those targets.  Hence, do not bond for
+    micromips or fix_24k.  */
+Index: b/src/gcc/config/tilegx/t-tilegx
+===================================================================
+--- a/src/gcc/config/tilegx/t-tilegx
++++ b/src/gcc/config/tilegx/t-tilegx
+@@ -1,6 +1,7 @@
+ MULTILIB_OPTIONS = m64/m32
+ MULTILIB_DIRNAMES = 64 32
+-MULTILIB_OSDIRNAMES = ../lib ../lib32
++MULTILIB_OSDIRNAMES = ../lib$(call if_multiarch,:tilegx-linux-gnu) ../lib32$(call if_multiarch,:tilegx32-linux-gnu)
++MULTIARCH_DIRNAME = $(call if_multiarch,tilegx-linux-gnu)
+ 
+ LIBGCC = stmp-multilib
+ INSTALL_LIBGCC = install-multilib
--- gcc-6-6.3.0.orig/debian/patches/gcc-multilib-multiarch.diff
+++ gcc-6-6.3.0/debian/patches/gcc-multilib-multiarch.diff
@@ -0,0 +1,126 @@
+# DP: Don't auto-detect multilib osdirnames.
+
+Index: b/src/gcc/config/sparc/t-linux64
+===================================================================
+--- a/src/gcc/config/sparc/t-linux64
++++ b/src/gcc/config/sparc/t-linux64
+@@ -25,7 +25,12 @@
+ 
+ MULTILIB_OPTIONS = m64/m32
+ MULTILIB_DIRNAMES = 64 32
++ifneq (,$(findstring sparc64,$(target)))
++MULTILIB_OSDIRNAMES = ../lib$(call if_multiarch,:sparc64-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib32$(call if_multiarch,:sparc-linux-gnu)
++else
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:sparc64-linux-gnu)
+-MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:sparc-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib$(call if_multiarch,:sparc-linux-gnu)
++endif
+ 
+ MULTIARCH_DIRNAME = $(call if_multiarch,sparc$(if $(findstring 64,$(target)),64)-linux-gnu)
+Index: b/src/gcc/config/s390/t-linux64
+===================================================================
+--- a/src/gcc/config/s390/t-linux64
++++ b/src/gcc/config/s390/t-linux64
+@@ -7,7 +7,12 @@
+ 
+ MULTILIB_OPTIONS = m64/m31
+ MULTILIB_DIRNAMES = 64 32
++ifneq (,$(findstring s390x,$(target)))
++MULTILIB_OSDIRNAMES = ../lib$(call if_multiarch,:s390x-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib32$(call if_multiarch,:s390-linux-gnu)
++else
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:s390x-linux-gnu)
+-MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:s390-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib$(call if_multiarch,:s390-linux-gnu)
++endif
+ 
+ MULTIARCH_DIRNAME = $(call if_multiarch,s390$(if $(findstring s390x,$(target)),x)-linux-gnu)
+Index: b/src/gcc/config/rs6000/t-linux64
+===================================================================
+--- a/src/gcc/config/rs6000/t-linux64
++++ b/src/gcc/config/rs6000/t-linux64
+@@ -28,8 +28,13 @@
+ MULTILIB_OPTIONS    := m64/m32
+ MULTILIB_DIRNAMES   := 64 32
+ MULTILIB_EXTRA_OPTS := 
++ifneq (,$(findstring powerpc64,$(target)))
++MULTILIB_OSDIRNAMES := m64=../lib$(call if_multiarch,:powerpc64-linux-gnu)
++MULTILIB_OSDIRNAMES += m32=../lib32$(call if_multiarch,:powerpc-linux-gnu)
++else
+ MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
+-MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
++MULTILIB_OSDIRNAMES += m32=../lib$(call if_multiarch,:powerpc-linux-gnu)
++endif
+ 
+ MULTIARCH_DIRNAME = $(call if_multiarch,powerpc$(if $(findstring 64,$(target)),64)-linux-gnu)
+ 
+Index: b/src/gcc/config/i386/t-linux64
+===================================================================
+--- a/src/gcc/config/i386/t-linux64
++++ b/src/gcc/config/i386/t-linux64
+@@ -33,9 +33,19 @@
+ comma=,
+ MULTILIB_OPTIONS    = $(subst $(comma),/,$(TM_MULTILIB_CONFIG))
+ MULTILIB_DIRNAMES   = $(patsubst m%, %, $(subst /, ,$(MULTILIB_OPTIONS)))
++ifneq (,$(findstring gnux32,$(target)))
+ MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu)
+-MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:i386-linux-gnu)
++MULTILIB_OSDIRNAMES+= m32=../lib32$(call if_multiarch,:i386-linux-gnu)
++MULTILIB_OSDIRNAMES+= mx32=../lib$(call if_multiarch,:x86_64-linux-gnux32)
++else ifneq (,$(findstring x86_64,$(target)))
++MULTILIB_OSDIRNAMES = m64=../lib$(call if_multiarch,:x86_64-linux-gnu)
++MULTILIB_OSDIRNAMES+= m32=../lib32$(call if_multiarch,:i386-linux-gnu)
+ MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32)
++else
++MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu)
++MULTILIB_OSDIRNAMES+= m32=../lib$(call if_multiarch,:i386-linux-gnu)
++MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32)
++endif
+ 
+ ifneq (,$(findstring x86_64,$(target)))
+   ifneq (,$(findstring biarchx32.h,$(tm_include_list)))
+Index: b/src/gcc/config/mips/t-linux64
+===================================================================
+--- a/src/gcc/config/mips/t-linux64
++++ b/src/gcc/config/mips/t-linux64
+@@ -23,10 +23,23 @@ MIPS_32 = $(if $(findstring r6, $(firstw
+ MIPS_ISA = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),isa)
+ MIPS_EL = $(if $(filter %el, $(firstword $(subst -, ,$(target)))),el)
+ MIPS_SOFT = $(if $(strip $(filter MASK_SOFT_FLOAT_ABI, $(target_cpu_default)) $(filter soft, $(with_float))),soft)
++
++ifneq (,$(findstring gnuabi64,$(target)))
++MULTILIB_OSDIRNAMES = \
++        ../lib32$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
++        ../libo32$(call if_multiarch,:mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
++        ../lib$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++else ifneq (,$(findstring gnuabin32,$(target)))
++MULTILIB_OSDIRNAMES = \
++        ../lib$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
++        ../libo32$(call if_multiarch,:mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
++        ../lib64$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++else
+ MULTILIB_OSDIRNAMES = \
+-	../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
+-	../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
+-	../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++        ../lib32$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
++        ../lib$(call if_multiarch,:mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
++        ../lib64$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++endif
+ 
+ ifneq (,$(findstring abin32,$(target)))
+ MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT))
+Index: b/src/gcc/config/rs6000/t-linux
+===================================================================
+--- a/src/gcc/config/rs6000/t-linux
++++ b/src/gcc/config/rs6000/t-linux
+@@ -2,7 +2,7 @@
+ # or soft-float.
+ ifeq (,$(filter $(with_cpu),$(SOFT_FLOAT_CPUS))$(findstring soft,$(with_float)))
+ ifneq (,$(findstring powerpc64,$(target)))
+-MULTILIB_OSDIRNAMES := .=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
++MULTILIB_OSDIRNAMES := .=../lib$(call if_multiarch,:powerpc64-linux-gnu)
+ else
+ ifneq (,$(findstring spe,$(target)))
+ MULTIARCH_DIRNAME := powerpc-linux-gnuspe$(if $(findstring 8548,$(with_cpu)),,v1)
--- gcc-6-6.3.0.orig/debian/patches/gcc-target-include-asm.diff
+++ gcc-6-6.3.0/debian/patches/gcc-target-include-asm.diff
@@ -0,0 +1,15 @@
+# DP: Search $(builddir)/sys-include for the asm header files
+
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -3240,7 +3240,7 @@ fi
+ # being built; programs in there won't even run.
+ if test "${build}" = "${host}" && test -d ${srcdir}/gcc; then
+   # Search for pre-installed headers if nothing else fits.
+-  FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -B$(build_tooldir)/bin/ -B$(build_tooldir)/lib/ -isystem $(build_tooldir)/include -isystem $(build_tooldir)/sys-include'
++  FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -B$(build_tooldir)/bin/ -B$(build_tooldir)/lib/ -isystem $(build_tooldir)/include -isystem $(build_tooldir)/sys-include -isystem $(CURDIR)/sys-include'
+ fi
+ 
+ if test "x${use_gnu_ld}" = x &&
--- gcc-6-6.3.0.orig/debian/patches/gcc-textdomain.diff
+++ gcc-6-6.3.0/debian/patches/gcc-textdomain.diff
@@ -0,0 +1,96 @@
+# DP: Set gettext's domain and textdomain to the versioned package name.
+
+Index: b/src/gcc/intl.c
+===================================================================
+--- a/src/gcc/intl.c
++++ b/src/gcc/intl.c
+@@ -55,8 +55,8 @@ gcc_init_libintl (void)
+   setlocale (LC_ALL, "");
+ #endif
+ 
+-  (void) bindtextdomain ("gcc", LOCALEDIR);
+-  (void) textdomain ("gcc");
++  (void) bindtextdomain ("gcc-6", LOCALEDIR);
++  (void) textdomain ("gcc-6");
+ 
+   /* Opening quotation mark.  */
+   open_quote = _("`");
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -3995,8 +3995,8 @@ install-po:
+ 	  dir=$(localedir)/$$lang/LC_MESSAGES; \
+ 	  echo $(mkinstalldirs) $(DESTDIR)$$dir; \
+ 	  $(mkinstalldirs) $(DESTDIR)$$dir || exit 1; \
+-	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \
+-	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \
++	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-6.mo; \
++	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-6.mo; \
+ 	done
+ 
+ # Rule for regenerating the message template (gcc.pot).
+Index: b/src/libcpp/init.c
+===================================================================
+--- a/src/libcpp/init.c
++++ b/src/libcpp/init.c
+@@ -155,7 +155,7 @@ init_library (void)
+       init_trigraph_map ();
+ 
+ #ifdef ENABLE_NLS
+-       (void) bindtextdomain (PACKAGE, LOCALEDIR);
++       (void) bindtextdomain (PACKAGE PACKAGE_SUFFIX, LOCALEDIR);
+ #endif
+     }
+ }
+Index: b/src/libcpp/system.h
+===================================================================
+--- a/src/libcpp/system.h
++++ b/src/libcpp/system.h
+@@ -280,7 +280,7 @@ extern int errno;
+ #endif
+ 
+ #ifndef _
+-# define _(msgid) dgettext (PACKAGE, msgid)
++# define _(msgid) dgettext (PACKAGE PACKAGE_SUFFIX, msgid)
+ #endif
+ 
+ #ifndef N_
+Index: b/src/libcpp/Makefile.in
+===================================================================
+--- a/src/libcpp/Makefile.in
++++ b/src/libcpp/Makefile.in
+@@ -49,6 +49,7 @@ LDFLAGS = @LDFLAGS@
+ LIBICONV = @LIBICONV@
+ LIBINTL = @LIBINTL@
+ PACKAGE = @PACKAGE@
++PACKAGE_SUFFIX = -6
+ RANLIB = @RANLIB@
+ SHELL = @SHELL@
+ USED_CATALOGS = @USED_CATALOGS@
+@@ -72,10 +73,12 @@ depcomp = $(SHELL) $(srcdir)/../depcomp
+ 
+ INCLUDES = -I$(srcdir) -I. -I$(srcdir)/../include @INCINTL@ \
+ 	-I$(srcdir)/include
++DEBCPPFLAGS += -DPACKAGE_SUFFIX=\"$(strip $(PACKAGE_SUFFIX))\"
+ 
+-ALL_CFLAGS = $(CFLAGS) $(WARN_CFLAGS) $(INCLUDES) $(CPPFLAGS) $(PICFLAG)
++ALL_CFLAGS = $(CFLAGS) $(WARN_CFLAGS) $(INCLUDES) $(CPPFLAGS) $(PICFLAG) \
++	$(DEBCPPFLAGS)
+ ALL_CXXFLAGS = $(CXXFLAGS) $(WARN_CXXFLAGS) $(NOEXCEPTION_FLAGS) $(INCLUDES) \
+-	$(CPPFLAGS) $(PICFLAG)
++	$(CPPFLAGS) $(PICFLAG) $(DEBCPPFLAGS)
+ 
+ # The name of the compiler to use.
+ COMPILER = $(CXX)
+@@ -164,8 +167,8 @@ install-strip install: all installdirs
+ 	  else continue; \
+ 	  fi; \
+ 	  dir=$(localedir)/$$lang/LC_MESSAGES; \
+-	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE).mo; \
+-	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE).mo; \
++	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE)$(PACKAGE_SUFFIX).mo; \
++	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE)$(PACKAGE_SUFFIX).mo; \
+ 	done
+ 
+ mostlyclean:
--- gcc-6-6.3.0.orig/debian/patches/gccgo-issue16780.diff
+++ gcc-6-6.3.0/debian/patches/gccgo-issue16780.diff
@@ -0,0 +1,39 @@
+# DP: gccgo: Call default_file_start from s390_asm_file_start
+
+https://gcc.gnu.org/ml/gcc-patches/2016-08/msg01655.html
+
+gcc/
+
+2016-08-23  Ian Lance Taylor  <iant@golang.org>
+
+	* config/s390/s390.c (s390_asm_file_start): Call
+	default_file_start.
+
+gcc/testsuite/
+
+2016-08-23  Ian Lance Taylor  <iant@golang.org>
+
+	* gcc.target/s390/nolrl-1.c: Don't match the file name.
+
+Index: b/src/gcc/config/s390/s390.c
+===================================================================
+--- a/src/gcc/config/s390/s390.c
++++ b/src/gcc/config/s390/s390.c
+@@ -14973,6 +14973,7 @@ s390_vector_alignment (const_tree type)
+ static void
+ s390_asm_file_start (void)
+ {
++  default_file_start ();
+   s390_asm_output_machine_for_arch (asm_out_file);
+ }
+ #endif
+Index: b/src/gcc/testsuite/gcc.target/s390/nolrl-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nolrl-1.c
++++ b/src/gcc/testsuite/gcc.target/s390/nolrl-1.c
+@@ -16,4 +16,4 @@ bar ()
+     foo (z);
+ }
+ 
+-/* { dg-final { scan-assembler-not "lrl" } } */
++/* { dg-final { scan-assembler-not "\tlrl" } } */
--- gcc-6-6.3.0.orig/debian/patches/gccgo-version.diff
+++ gcc-6-6.3.0/debian/patches/gccgo-version.diff
@@ -0,0 +1,91 @@
+# DP: Omit the subminor number from the go libdir
+
+Index: b/src/gcc/go/Make-lang.in
+===================================================================
+--- a/src/gcc/go/Make-lang.in
++++ b/src/gcc/go/Make-lang.in
+@@ -219,7 +219,9 @@ go.stageprofile: stageprofile-start
+ go.stagefeedback: stagefeedback-start
+ 	-mv go/*$(objext) stagefeedback/go
+ 
+-CFLAGS-go/go-lang.o += -DDEFAULT_TARGET_VERSION=\"$(version)\" \
++short_version := $(shell echo $(version) | sed -r 's/([0-9]+).*/\1/')
++
++CFLAGS-go/go-lang.o += -DDEFAULT_TARGET_VERSION=\"$(short_version)\" \
+ 	-DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\"
+ 
+ GOINCLUDES = -I $(srcdir)/go -I $(srcdir)/go/gofrontend
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -498,14 +498,15 @@ SUFFIXES = .c .go .gox .o .obj .lo .a
+ @LIBGO_IS_RTEMS_TRUE@subdirs = testsuite
+ SUBDIRS = ${subdirs}
+ gcc_version := $(shell $(GOC) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
+ MAINT_CHARSET = latin1
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ toolexecdir = $(glibgo_toolexecdir)
+ toolexeclibdir = $(glibgo_toolexeclibdir)
+-toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(gcc_version)/$(target_alias)
+-libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(gcc_version)
++toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(short_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(short_version)
+ WARN_CFLAGS = $(WARN_FLAGS) $(WERROR)
+ 
+ # -I/-D flags to pass when compiling.
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -16,6 +16,7 @@ endif
+ SUBDIRS = ${subdirs}
+ 
+ gcc_version := $(shell $(GOC) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
+ 
+ MAINT_CHARSET = latin1
+ 
+@@ -25,8 +26,8 @@ STAMP = echo timestamp >
+ 
+ toolexecdir = $(glibgo_toolexecdir)
+ toolexeclibdir = $(glibgo_toolexeclibdir)
+-toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(gcc_version)/$(target_alias)
+-libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(gcc_version)
++toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(short_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(short_version)
+ 
+ LIBFFI = @LIBFFI@
+ LIBFFIINCS = @LIBFFIINCS@
+Index: b/src/gotools/Makefile.am
+===================================================================
+--- a/src/gotools/Makefile.am
++++ b/src/gotools/Makefile.am
+@@ -18,8 +18,9 @@
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ 
+ gcc_version := $(shell $(GCC_FOR_TARGET) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
+ 
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(short_version)
+ 
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+Index: b/src/gotools/Makefile.in
+===================================================================
+--- a/src/gotools/Makefile.in
++++ b/src/gotools/Makefile.in
+@@ -247,7 +247,8 @@ top_builddir = @top_builddir@
+ top_srcdir = @top_srcdir@
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ gcc_version := $(shell $(GCC_FOR_TARGET) -dumpversion)
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
++libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(short_version)
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
--- gcc-6-6.3.0.orig/debian/patches/gcj-arm-mode.diff
+++ gcc-6-6.3.0/debian/patches/gcj-arm-mode.diff
@@ -0,0 +1,33 @@
+# DP: For armhf, force arm mode instead of thumb mode
+
+--- a/src/libjava/configure.host
++++ b/src/libjava/configure.host
+@@ -66,6 +66,9 @@
+     ;;
+ esac
+ 
++# on armhf force arm mode
++libgcj_flags="${libgcj_flags} -marm"
++
+ AM_RUNTESTFLAGS= 
+ 
+ # Set any host dependent compiler flags.
+--- a/src/gcc/java/lang-specs.h
++++ b/src/gcc/java/lang-specs.h
+@@ -47,7 +47,7 @@
+     %{.class|.zip|.jar|!fsyntax-only:jc1				\
+       %{.java|fsaw-java-file:%U.jar -fsource-filename=%i %<ffilelist-file} \
+       %{.class|.zip|.jar|ffilelist-file|fcompile-resource*:%i}		\
+-      %(jc1) %(cc1_options) %{I*} %{!findirect-dispatch:-faux-classpath %U.zip} \
++      %(jc1) %(cc1_options) -marm %{I*} %{!findirect-dispatch:-faux-classpath %U.zip} \
+       %{MD:-MD_} %{MMD:-MMD_} %{M} %{MM} %{MA} %{MT*} %{MF*}\
+       %(invoke_as)}",
+       0, 0, 0},
+--- a/src/libjava/libgcj.spec.in
++++ b/src/libjava/libgcj.spec.in
+@@ -9,4 +9,4 @@
+ %rename lib liborig
+ *lib: @LD_START_STATIC_SPEC@ @LIBGCJ_SPEC@ @LD_FINISH_STATIC_SPEC@ @LIBMATHSPEC@ @LDLIBICONV@ @GCSPEC@ @THREADSPEC@ @ZLIBSPEC@ @SYSTEMSPEC@ %(libgcc) @LIBSTDCXXSPEC@ %(liborig)
+ 
+-*jc1: @HASH_SYNC_SPEC@ @DIVIDESPEC@ @CHECKREFSPEC@ @JC1GCSPEC@ @EXCEPTIONSPEC@ @BACKTRACESPEC@ @IEEESPEC@ @ATOMICSPEC@ @LIBGCJ_BC_SPEC@ -fkeep-inline-functions
++*jc1: @HASH_SYNC_SPEC@ @DIVIDESPEC@ @CHECKREFSPEC@ @JC1GCSPEC@ @EXCEPTIONSPEC@ @BACKTRACESPEC@ @IEEESPEC@ @ATOMICSPEC@ @LIBGCJ_BC_SPEC@ -fkeep-inline-functions -marm
--- gcc-6-6.3.0.orig/debian/patches/gdc-6-doc.diff
+++ gcc-6-6.3.0/debian/patches/gdc-6-doc.diff
@@ -0,0 +1,96 @@
+# DP: This implements D language support in the GCC back end, and adds
+# DP: relevant documentation about the GDC front end (documentation part).
+
+--- a/src/gcc/doc/frontends.texi
++++ b/src/gcc/doc/frontends.texi
+@@ -9,6 +9,7 @@
+ @cindex GNU Compiler Collection
+ @cindex GNU C Compiler
+ @cindex Ada
++@cindex D
+ @cindex Fortran
+ @cindex Go
+ @cindex Java
+@@ -17,7 +18,7 @@
+ GCC stands for ``GNU Compiler Collection''.  GCC is an integrated
+ distribution of compilers for several major programming languages.  These
+ languages currently include C, C++, Objective-C, Objective-C++, Java,
+-Fortran, Ada, and Go.
++Fortran, Ada, D and Go.
+ 
+ The abbreviation @dfn{GCC} has multiple meanings in common use.  The
+ current official meaning is ``GNU Compiler Collection'', which refers
+--- a/src/gcc/doc/install.texi
++++ b/src/gcc/doc/install.texi
+@@ -1547,12 +1547,12 @@ their runtime libraries should be built.  For a list of valid values for
+ grep ^language= */config-lang.in
+ @end smallexample
+ Currently, you can use any of the following:
+-@code{all}, @code{ada}, @code{c}, @code{c++}, @code{fortran},
++@code{all}, @code{ada}, @code{c}, @code{c++}, @code{d}, @code{fortran},
+ @code{go}, @code{java}, @code{jit}, @code{lto}, @code{objc}, @code{obj-c++}.
+ Building the Ada compiler has special requirements, see below.
+ If you do not pass this flag, or specify the option @code{all}, then all
+ default languages available in the @file{gcc} sub-tree will be configured.
+-Ada, Go, Jit, and Objective-C++ are not default languages.  LTO is not a
++Ada, D, Go, Jit, and Objective-C++ are not default languages.  LTO is not a
+ default language, but is built by default because @option{--enable-lto} is
+ enabled by default.  The other languages are default languages.
+ 
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -1269,6 +1269,15 @@ called @dfn{specs}.
+ Ada source code file containing a library unit body (a subprogram or
+ package body).  Such files are also called @dfn{bodies}.
+ 
++@item @var{file}.d
++D source code file.
++
++@item @var{file}.di
++D interface code file.
++
++@item @var{file}.dd
++D documentation code file.
++
+ @c GCC also knows about some suffixes for languages not yet included:
+ @c Pascal:
+ @c @var{file}.p
+@@ -1304,6 +1313,7 @@ objective-c  objective-c-header  objective-c-cpp-output
+ objective-c++ objective-c++-header objective-c++-cpp-output
+ assembler  assembler-with-cpp
+ ada
++d
+ f77  f77-cpp-input f95  f95-cpp-input
+ go
+ java
+--- a/src/gcc/doc/sourcebuild.texi
++++ b/src/gcc/doc/sourcebuild.texi
+@@ -109,6 +109,9 @@ The Objective-C and Objective-C++ runtime library.
+ @item libquadmath
+ The runtime support library for quad-precision math operations.
+ 
++@item libphobos
++The D standard runtime library.
++
+ @item libssp
+ The Stack protector runtime library.
+ 
+--- a/src/gcc/doc/standards.texi
++++ b/src/gcc/doc/standards.texi
+@@ -280,6 +280,16 @@ available online, see @uref{http://gcc.gnu.org/readings.html}
+ As of the GCC 4.7.1 release, GCC supports the Go 1 language standard,
+ described at @uref{http://golang.org/doc/go1.html}.
+ 
++@section D language
++
++The D language is under development as of this writing; see the
++@uref{http://dlang.org/@/language-reference.html, current language
++reference}.  At present the current major version of D is 2.0, and
++there is no way to describe the language supported by GCC in terms of
++a specific minor version.  In general GCC follows the D frontend
++releases closely, and any given GCC release will support the current
++language as of the date that the release was frozen.
++
+ @section References for Other Languages
+ 
+ @xref{Top, GNAT Reference Manual, About This Guide, gnat_rm,
--- gcc-6-6.3.0.orig/debian/patches/gdc-6.diff
+++ gcc-6-6.3.0/debian/patches/gdc-6.diff
@@ -0,0 +1,139 @@
+# DP: This implements D language support in the GCC back end, and adds
+# DP: relevant documentation about the GDC front end (code part).
+
+Index: b/src/gcc/config/darwin.h
+===================================================================
+--- a/src/gcc/config/darwin.h
++++ b/src/gcc/config/darwin.h
+@@ -49,6 +49,10 @@ see the files COPYING3 and COPYING.RUNTI
+ /* Suppress g++ attempt to link in the math library automatically. */
+ #define MATH_LIBRARY ""
+ 
++/* Suppress gdc attempt to link in the thread and time library automatically. */
++#define THREAD_LIBRARY ""
++#define TIME_LIBRARY ""
++
+ /* We have atexit.  */
+ 
+ #define HAVE_ATEXIT
+Index: b/src/gcc/config/i386/cygming.h
+===================================================================
+--- a/src/gcc/config/i386/cygming.h
++++ b/src/gcc/config/i386/cygming.h
+@@ -175,6 +175,10 @@ along with GCC; see the file COPYING3.
+ 
+ #undef MATH_LIBRARY
+ #define MATH_LIBRARY ""
++#undef THREAD_LIBRARY
++#define THREAD_LIBRARY ""
++#undef TIME_LIBRARY
++#define TIME_LIBRARY ""
+ 
+ #undef TARGET_LIBC_HAS_FUNCTION
+ #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
+Index: b/src/gcc/config/linux-android.h
+===================================================================
+--- a/src/gcc/config/linux-android.h
++++ b/src/gcc/config/linux-android.h
+@@ -57,3 +57,9 @@
+ 
+ #define ANDROID_ENDFILE_SPEC \
+   "%{shared: crtend_so%O%s;: crtend_android%O%s}"
++
++/* Suppress gdc attempt to link in the thread and time library automatically. */
++#if ANDROID_DEFAULT
++# define THREAD_LIBRARY ""
++# define TIME_LIBRARY ""
++#endif
+Index: b/src/gcc/config/rs6000/rs6000.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.c
++++ b/src/gcc/config/rs6000/rs6000.c
+@@ -28596,7 +28596,8 @@ rs6000_output_function_epilogue (FILE *f
+       if (lang_GNU_C ()
+ 	  || ! strcmp (language_string, "GNU GIMPLE")
+ 	  || ! strcmp (language_string, "GNU Go")
+-	  || ! strcmp (language_string, "libgccjit"))
++	  || ! strcmp (language_string, "libgccjit")
++	  || ! strcmp (language_string, "GNU D"))
+ 	i = 0;
+       else if (! strcmp (language_string, "GNU F77")
+ 	       || lang_GNU_Fortran ())
+Index: b/src/gcc/dwarf2out.c
+===================================================================
+--- a/src/gcc/dwarf2out.c
++++ b/src/gcc/dwarf2out.c
+@@ -4846,6 +4846,16 @@ is_ada (void)
+   return lang == DW_LANG_Ada95 || lang == DW_LANG_Ada83;
+ }
+ 
++/* Return TRUE if the language is D.  */
++
++static inline bool
++is_dlang (void)
++{
++  unsigned int lang = get_AT_unsigned (comp_unit_die (), DW_AT_language);
++
++  return lang == DW_LANG_D;
++}
++
+ /* Remove the specified attribute if present.  Return TRUE if removal
+    was successful.  */
+ 
+@@ -21949,6 +21959,8 @@ gen_compile_unit_die (const char *filena
+ 	language = DW_LANG_ObjC;
+       else if (strcmp (language_string, "GNU Objective-C++") == 0)
+ 	language = DW_LANG_ObjC_plus_plus;
++      else if (strcmp (language_string, "GNU D") == 0)
++	language = DW_LANG_D;
+       else if (dwarf_version >= 5 || !dwarf_strict)
+ 	{
+ 	  if (strcmp (language_string, "GNU Go") == 0)
+@@ -23401,7 +23413,7 @@ declare_in_namespace (tree thing, dw_die
+ 
+   if (ns_context != context_die)
+     {
+-      if (is_fortran ())
++      if (is_fortran () || is_dlang ())
+ 	return ns_context;
+       if (DECL_P (thing))
+ 	gen_decl_die (thing, NULL, NULL, ns_context);
+@@ -23424,7 +23436,7 @@ gen_namespace_die (tree decl, dw_die_ref
+     {
+       /* Output a real namespace or module.  */
+       context_die = setup_namespace_context (decl, comp_unit_die ());
+-      namespace_die = new_die (is_fortran ()
++      namespace_die = new_die (is_fortran () || is_dlang ()
+ 			       ? DW_TAG_module : DW_TAG_namespace,
+ 			       context_die, decl);
+       /* For Fortran modules defined in different CU don't add src coords.  */
+@@ -23491,7 +23503,7 @@ gen_decl_die (tree decl, tree origin, st
+       break;
+ 
+     case CONST_DECL:
+-      if (!is_fortran () && !is_ada ())
++      if (!is_fortran () && !is_ada () && !is_dlang ())
+ 	{
+ 	  /* The individual enumerators of an enum type get output when we output
+ 	     the Dwarf representation of the relevant enum type itself.  */
+@@ -24012,7 +24024,7 @@ dwarf2out_decl (tree decl)
+     case CONST_DECL:
+       if (debug_info_level <= DINFO_LEVEL_TERSE)
+ 	return;
+-      if (!is_fortran () && !is_ada ())
++      if (!is_fortran () && !is_ada () && !is_dlang ())
+ 	return;
+       if (TREE_STATIC (decl) && decl_function_context (decl))
+ 	context_die = lookup_decl_die (DECL_CONTEXT (decl));
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -1288,6 +1288,7 @@ static const struct compiler default_com
+   {".java", "#Java", 0, 0, 0}, {".class", "#Java", 0, 0, 0},
+   {".zip", "#Java", 0, 0, 0}, {".jar", "#Java", 0, 0, 0},
+   {".go", "#Go", 0, 1, 0},
++  {".d", "#D", 0, 1, 0}, {".dd", "#D", 0, 1, 0}, {".di", "#D", 0, 1, 0},
+   /* Next come the entries for C.  */
+   {".c", "@c", 0, 0, 1},
+   {"@c",
--- gcc-6-6.3.0.orig/debian/patches/gdc-base-version.diff
+++ gcc-6-6.3.0/debian/patches/gdc-base-version.diff
@@ -0,0 +1,27 @@
+# DP: Use the GCC base version for the D include dir name
+
+Index: b/src/libphobos/m4/druntime.m4
+===================================================================
+--- a/src/libphobos/m4/druntime.m4
++++ b/src/libphobos/m4/druntime.m4
+@@ -43,7 +43,7 @@ AC_DEFUN([DRUNTIME_INSTALL_DIRECTORIES],
+   AC_REQUIRE([AC_PROG_GDC])
+ 
+   AC_MSG_CHECKING([D GCC version])
+-  d_gcc_ver=`$GDC -dumpversion`
++  d_gcc_ver=`$GDC -dumpversion | sed 's/^\(@<:@0-9@:>@*\).*/\1/'`
+   AC_MSG_RESULT($d_gcc_ver)
+   AC_ARG_WITH([cross-host],
+     AC_HELP_STRING([--with-cross-host=HOST],
+Index: b/src/libphobos/configure.ac
+===================================================================
+--- a/src/libphobos/configure.ac
++++ b/src/libphobos/configure.ac
+@@ -53,6 +53,7 @@ m4_rename([_AC_ARG_VAR_PRECIOUS],[glibd_
+ m4_define([_AC_ARG_VAR_PRECIOUS],[])
+ AM_PROG_AS
+ AC_PROG_CC
++dnl dummy change to run autoreconf in this directory
+ AC_PROG_GDC
+ WITH_LOCAL_DRUNTIME([GDC_CHECK_COMPILE], [])
+ 
--- gcc-6-6.3.0.orig/debian/patches/gdc-config-ml.diff
+++ gcc-6-6.3.0/debian/patches/gdc-config-ml.diff
@@ -0,0 +1,55 @@
+# DP: config-ml.in: Add D support.
+
+2015-04-30  Matthias Klose  <doko@ubuntu.com>
+
+        * config-ml.in: Add D support: treat GDC and GDCFLAGS like other
+        compiler/flag environment variables.
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -525,6 +525,7 @@ multi-do:
+ 				GCJFLAGS="$(GCJFLAGS) $${flags}" \
+ 				GOCFLAGS="$(GOCFLAGS) $${flags}" \
+ 				CXXFLAGS="$(CXXFLAGS) $${flags}" \
++				DFLAGS="$(DFLAGS) $${flags}" \
+ 				LIBCFLAGS="$(LIBCFLAGS) $${flags}" \
+ 				LIBCXXFLAGS="$(LIBCXXFLAGS) $${flags}" \
+ 				LDFLAGS="$(LDFLAGS) $${flags}" \
+@@ -757,7 +758,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+         break
+       fi
+     done
+-    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags"'
++    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags" GDC="${GDC_}$flags"'
+ 
+     if [ "${with_target_subdir}" = "." ]; then
+ 	CC_=$CC' '
+@@ -766,6 +767,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	GCJ_=$GCJ' '
+ 	GFORTRAN_=$GFORTRAN' '
+ 	GOC_=$GOC' '
++	GDC_=$GDC' '
+     else
+ 	# Create a regular expression that matches any string as long
+ 	# as ML_POPDIR.
+@@ -842,6 +844,18 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  esac
+ 	done
+ 
++	GDC_=
++	for arg in ${GDC}; do
++	  case $arg in
++	  -[BIL]"${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  "${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  *)
++	    GDC_="${GDC_}${arg} " ;;
++	  esac
++	done
++
+ 	if test "x${LD_LIBRARY_PATH+set}" = xset; then
+ 	  LD_LIBRARY_PATH_=
+ 	  for arg in `echo "$LD_LIBRARY_PATH" | tr ':' ' '`; do
--- gcc-6-6.3.0.orig/debian/patches/gdc-cross-biarch.diff
+++ gcc-6-6.3.0/debian/patches/gdc-cross-biarch.diff
@@ -0,0 +1,13 @@
+# DP: Fix the location of target's libs in cross-build for biarch
+
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -891,6 +915,8 @@
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
--- gcc-6-6.3.0.orig/debian/patches/gdc-cross-install-location.diff
+++ gcc-6-6.3.0/debian/patches/gdc-cross-install-location.diff
@@ -0,0 +1,22 @@
+--- a/src/libphobos/configure.ac
++++ b/src/libphobos/configure.ac
+@@ -119,6 +119,8 @@
+ AC_SUBST([DRUNTIME_SOVERSION])
+ AC_SUBST([PHOBOS_SOVERSION])
+ 
++# trigger rebuild of the configure file
++
+ # Set default flags (after DRUNTIME_WERROR!)
+ if test -z "$DFLAGS"; then
+     DFLAGS="-Wall $WERROR_FLAG -g -frelease -O2"
+--- a/src/libphobos/m4/druntime.m4
++++ b/src/libphobos/m4/druntime.m4
+@@ -78,7 +78,7 @@ AC_DEFUN([DRUNTIME_INSTALL_DIRECTORIES],
+   AC_SUBST(toolexeclibdir)
+ 
+   # Default case for install directory for D sources files.
+-  gdc_include_dir='${libdir}/gcc/${target_alias}'/${d_gcc_ver}/include/d
++  gdc_include_dir='${libdir}/gcc-cross/${target_alias}'/${d_gcc_ver}/include/d
+   AC_SUBST(gdc_include_dir)
+ ])
+ 
--- gcc-6-6.3.0.orig/debian/patches/gdc-driver-nophobos.diff
+++ gcc-6-6.3.0/debian/patches/gdc-driver-nophobos.diff
@@ -0,0 +1,28 @@
+# DP: Modify gdc driver to have no libphobos by default.
+
+Index: b/src/gcc/d/d-lang.cc
+===================================================================
+--- a/src/gcc/d/d-lang.cc
++++ b/src/gcc/d/d-lang.cc
+@@ -198,7 +198,7 @@ static void
+ d_init_options_struct(gcc_options *opts)
+ {
+   // GCC options
+-  opts->x_flag_exceptions = 1;
++  opts->x_flag_exceptions = 0;
+ 
+   // Avoid range issues for complex multiply and divide.
+   opts->x_flag_complex_method = 2;
+Index: b/src/gcc/d/d-spec.c
+===================================================================
+--- a/src/gcc/d/d-spec.c
++++ b/src/gcc/d/d-spec.c
+@@ -62,7 +62,7 @@ static int library = 0;
+ 
+ /* If true, use the standard D runtime library when linking with
+    standard libraries. */
+-static bool need_phobos = true;
++static bool need_phobos = false;
+ 
+ void
+ lang_specific_driver (cl_decoded_option **in_decoded_options,
--- gcc-6-6.3.0.orig/debian/patches/gdc-frontend-posix.diff
+++ gcc-6-6.3.0/debian/patches/gdc-frontend-posix.diff
@@ -0,0 +1,15 @@
+# DP: Fix build of the D frontend on the Hurd and KFreeBSD.
+
+Index: b/src/gcc/d/dfrontend/object.h
+===================================================================
+--- a/src/gcc/d/dfrontend/object.h
++++ b/src/gcc/d/dfrontend/object.h
+@@ -10,7 +10,7 @@
+ #ifndef OBJECT_H
+ #define OBJECT_H
+ 
+-#define POSIX (__linux__ || __APPLE__ || __FreeBSD__ || __OpenBSD__ || __sun)
++#define POSIX (__linux__ || __GLIBC__ || __gnu_hurd__ || __APPLE__ || __FreeBSD__ || __OpenBSD__ || __sun)
+ 
+ #if __DMC__
+ #pragma once
--- gcc-6-6.3.0.orig/debian/patches/gdc-libphobos-build.diff
+++ gcc-6-6.3.0/debian/patches/gdc-libphobos-build.diff
@@ -0,0 +1,1301 @@
+# DP: This implements building of libphobos library in GCC.
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -513,6 +513,7 @@ multi-do:
+ 				exec_prefix="$(exec_prefix)" \
+ 				GCJFLAGS="$(GCJFLAGS) $${flags}" \
+ 				GOCFLAGS="$(GOCFLAGS) $${flags}" \
++				GDCFLAGS="$(GDCFLAGS) $${flags}" \
+ 				CXXFLAGS="$(CXXFLAGS) $${flags}" \
+ 				LIBCFLAGS="$(LIBCFLAGS) $${flags}" \
+ 				LIBCXXFLAGS="$(LIBCXXFLAGS) $${flags}" \
+@@ -746,7 +747,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+         break
+       fi
+     done
+-    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags"'
++    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags" GDC="${GDC_}$flags"'
+ 
+     if [ "${with_target_subdir}" = "." ]; then
+ 	CC_=$CC' '
+@@ -755,6 +756,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	GCJ_=$GCJ' '
+ 	GFORTRAN_=$GFORTRAN' '
+ 	GOC_=$GOC' '
++	GDC_=$GDC' '
+     else
+ 	# Create a regular expression that matches any string as long
+ 	# as ML_POPDIR.
+@@ -831,6 +833,18 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  esac
+ 	done
+ 
++	GDC_=
++	for arg in ${GDC}; do
++	  case $arg in
++	  -[BIL]"${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  "${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  *)
++	    GDC_="${GDC_}${arg} " ;;
++	  esac
++	done
++
+ 	if test "x${LD_LIBRARY_PATH+set}" = xset; then
+ 	  LD_LIBRARY_PATH_=
+ 	  for arg in `echo "$LD_LIBRARY_PATH" | tr ':' ' '`; do
+Index: b/src/config/multi.m4
+===================================================================
+--- a/src/config/multi.m4
++++ b/src/config/multi.m4
+@@ -65,4 +65,5 @@ CONFIG_SHELL=${CONFIG_SHELL-/bin/sh}
+ CC="$CC"
+ CXX="$CXX"
+ GFORTRAN="$GFORTRAN"
+-GCJ="$GCJ"])])dnl
++GCJ="$GCJ"
++GDC="$GDC"])])dnl
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -172,6 +172,8 @@ target_libraries="target-libgcc \
+ 		target-libssp \
+ 		target-libquadmath \
+ 		target-libgfortran \
++		target-zlib \
++		target-libphobos \
+ 		target-boehm-gc \
+ 		${libgcj} \
+ 		target-libobjc \
+@@ -1372,6 +1374,7 @@ if test "${build}" != "${host}" ; then
+   GCJ_FOR_BUILD=${GCJ_FOR_BUILD-gcj}
+   GFORTRAN_FOR_BUILD=${GFORTRAN_FOR_BUILD-gfortran}
+   GOC_FOR_BUILD=${GOC_FOR_BUILD-gccgo}
++  GDC_FOR_BUILD=${GDC_FOR_BUILD-gdc}
+   DLLTOOL_FOR_BUILD=${DLLTOOL_FOR_BUILD-dlltool}
+   LD_FOR_BUILD=${LD_FOR_BUILD-ld}
+   NM_FOR_BUILD=${NM_FOR_BUILD-nm}
+@@ -1386,6 +1389,7 @@ else
+   GCJ_FOR_BUILD="\$(GCJ)"
+   GFORTRAN_FOR_BUILD="\$(GFORTRAN)"
+   GOC_FOR_BUILD="\$(GOC)"
++  GDC_FOR_BUILD="\$(GDC)"
+   DLLTOOL_FOR_BUILD="\$(DLLTOOL)"
+   LD_FOR_BUILD="\$(LD)"
+   NM_FOR_BUILD="\$(NM)"
+@@ -3318,6 +3322,7 @@ AC_SUBST(DLLTOOL_FOR_BUILD)
+ AC_SUBST(GCJ_FOR_BUILD)
+ AC_SUBST(GFORTRAN_FOR_BUILD)
+ AC_SUBST(GOC_FOR_BUILD)
++AC_SUBST(GDC_FOR_BUILD)
+ AC_SUBST(LDFLAGS_FOR_BUILD)
+ AC_SUBST(LD_FOR_BUILD)
+ AC_SUBST(NM_FOR_BUILD)
+@@ -3428,6 +3433,7 @@ NCN_STRICT_CHECK_TARGET_TOOLS(GCC_FOR_TA
+ NCN_STRICT_CHECK_TARGET_TOOLS(GCJ_FOR_TARGET, gcj)
+ NCN_STRICT_CHECK_TARGET_TOOLS(GFORTRAN_FOR_TARGET, gfortran)
+ NCN_STRICT_CHECK_TARGET_TOOLS(GOC_FOR_TARGET, gccgo)
++NCN_STRICT_CHECK_TARGET_TOOLS(GDC_FOR_TARGET, gdc)
+ 
+ ACX_CHECK_INSTALLED_TARGET_TOOL(AR_FOR_TARGET, ar)
+ ACX_CHECK_INSTALLED_TARGET_TOOL(AS_FOR_TARGET, as)
+@@ -3463,6 +3469,8 @@ GCC_TARGET_TOOL(gfortran, GFORTRAN_FOR_T
+ 		[gcc/gfortran -B$$r/$(HOST_SUBDIR)/gcc/], fortran)
+ GCC_TARGET_TOOL(gccgo, GOC_FOR_TARGET, GOC,
+ 		[gcc/gccgo -B$$r/$(HOST_SUBDIR)/gcc/], go)
++GCC_TARGET_TOOL(gdc, GDC_FOR_TARGET, GDC,
++		[gcc/gdc -B$$r/$(HOST_SUBDIR)/gcc/], d)
+ GCC_TARGET_TOOL(ld, LD_FOR_TARGET, LD, [ld/ld-new])
+ GCC_TARGET_TOOL(lipo, LIPO_FOR_TARGET, LIPO)
+ GCC_TARGET_TOOL(nm, NM_FOR_TARGET, NM, [binutils/nm-new])
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -162,6 +162,7 @@ target_modules = { module= libquadmath;
+ target_modules = { module= libgfortran; };
+ target_modules = { module= libobjc; };
+ target_modules = { module= libgo; };
++target_modules = { module= libphobos; };
+ target_modules = { module= libtermcap; no_check=true;
+                    missing=mostlyclean;
+                    missing=clean;
+@@ -319,6 +320,7 @@ flags_to_pass = { flag= GCJ_FOR_TARGET ;
+ flags_to_pass = { flag= GFORTRAN_FOR_TARGET ; };
+ flags_to_pass = { flag= GOC_FOR_TARGET ; };
+ flags_to_pass = { flag= GOCFLAGS_FOR_TARGET ; };
++flags_to_pass = { flag= GDC_FOR_TARGET ; };
+ flags_to_pass = { flag= LD_FOR_TARGET ; };
+ flags_to_pass = { flag= LIPO_FOR_TARGET ; };
+ flags_to_pass = { flag= LDFLAGS_FOR_TARGET ; };
+@@ -596,6 +598,8 @@ dependencies = { module=configure-target
+ dependencies = { module=all-target-libgo; on=all-target-libbacktrace; };
+ dependencies = { module=all-target-libgo; on=all-target-libffi; };
+ dependencies = { module=all-target-libgo; on=all-target-libatomic; };
++dependencies = { module=configure-target-libphobos; on=configure-target-zlib; };
++dependencies = { module=all-target-libphobos; on=all-target-zlib; };
+ dependencies = { module=configure-target-libjava; on=configure-target-zlib; };
+ dependencies = { module=configure-target-libjava; on=configure-target-boehm-gc; };
+ dependencies = { module=configure-target-libjava; on=configure-target-libffi; };
+@@ -660,6 +664,8 @@ languages = { language=objc;	gcc-check-t
+ languages = { language=obj-c++;	gcc-check-target=check-obj-c++; };
+ languages = { language=go;	gcc-check-target=check-go;
+ 				lib-check-target=check-target-libgo; };
++languages = { language=d;	gcc-check-target=check-d;
++				lib-check-target=check-target-libphobos; };
+ 
+ // Toplevel bootstrap
+ bootstrap_stage = { id=1 ; };
+Index: b/src/Makefile.tpl
+===================================================================
+--- a/src/Makefile.tpl
++++ b/src/Makefile.tpl
+@@ -160,6 +160,7 @@ BUILD_EXPORTS = \
+ 	GFORTRAN="$(GFORTRAN_FOR_BUILD)"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_BUILD)"; export GOC; \
+ 	GOCFLAGS="$(GOCFLAGS_FOR_BUILD)"; export GOCFLAGS; \
++	GDC="$(GDC_FOR_BUILD)"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_BUILD)"; export DLLTOOL; \
+ 	LD="$(LD_FOR_BUILD)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"; export LDFLAGS; \
+@@ -197,6 +198,7 @@ HOST_EXPORTS = \
+ 	GCJ="$(GCJ)"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN)"; export GFORTRAN; \
+ 	GOC="$(GOC)"; export GOC; \
++	GDC="$(GDC)"; export GDC; \
+ 	AR="$(AR)"; export AR; \
+ 	AS="$(AS)"; export AS; \
+ 	CC_FOR_BUILD="$(CC_FOR_BUILD)"; export CC_FOR_BUILD; \
+@@ -285,6 +287,7 @@ BASE_TARGET_EXPORTS = \
+ 	GCJ="$(GCJ_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GOC; \
++	GDC="$(GDC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_TARGET)"; export DLLTOOL; \
+ 	LD="$(COMPILER_LD_FOR_TARGET)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_TARGET)"; export LDFLAGS; \
+@@ -353,6 +356,7 @@ DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
+ GCJ_FOR_BUILD = @GCJ_FOR_BUILD@
+ GFORTRAN_FOR_BUILD = @GFORTRAN_FOR_BUILD@
+ GOC_FOR_BUILD = @GOC_FOR_BUILD@
++GDC_FOR_BUILD = @GDC_FOR_BUILD@
+ LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
+ LD_FOR_BUILD = @LD_FOR_BUILD@
+ NM_FOR_BUILD = @NM_FOR_BUILD@
+@@ -483,6 +487,7 @@ RAW_CXX_FOR_TARGET=$(STAGE_CC_WRAPPER) @
+ GCJ_FOR_TARGET=$(STAGE_CC_WRAPPER) @GCJ_FOR_TARGET@
+ GFORTRAN_FOR_TARGET=$(STAGE_CC_WRAPPER) @GFORTRAN_FOR_TARGET@
+ GOC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GOC_FOR_TARGET@
++GDC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GDC_FOR_TARGET@
+ DLLTOOL_FOR_TARGET=@DLLTOOL_FOR_TARGET@
+ LD_FOR_TARGET=@LD_FOR_TARGET@
+ 
+@@ -609,6 +614,7 @@ EXTRA_HOST_FLAGS = \
+ 	'GCJ=$(GCJ)' \
+ 	'GFORTRAN=$(GFORTRAN)' \
+ 	'GOC=$(GOC)' \
++	'GDC=$(GDC)' \
+ 	'LD=$(LD)' \
+ 	'LIPO=$(LIPO)' \
+ 	'NM=$(NM)' \
+@@ -665,6 +671,7 @@ EXTRA_TARGET_FLAGS = \
+ 	'GFORTRAN=$$(GFORTRAN_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOC=$$(GOC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOCFLAGS=$$(GOCFLAGS_FOR_TARGET)' \
++	'GDC=$$(GDC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'LD=$(COMPILER_LD_FOR_TARGET)' \
+ 	'LDFLAGS=$$(LDFLAGS_FOR_TARGET)' \
+ 	'LIBCFLAGS=$$(LIBCFLAGS_FOR_TARGET)' \
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -157,6 +157,7 @@ BUILD_EXPORTS = \
+ 	GFORTRAN="$(GFORTRAN_FOR_BUILD)"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_BUILD)"; export GOC; \
+ 	GOCFLAGS="$(GOCFLAGS_FOR_BUILD)"; export GOCFLAGS; \
++	GDC="$(GDC_FOR_BUILD)"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_BUILD)"; export DLLTOOL; \
+ 	LD="$(LD_FOR_BUILD)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"; export LDFLAGS; \
+@@ -194,6 +195,7 @@ HOST_EXPORTS = \
+ 	GCJ="$(GCJ)"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN)"; export GFORTRAN; \
+ 	GOC="$(GOC)"; export GOC; \
++	GDC="$(GDC)"; export GDC; \
+ 	AR="$(AR)"; export AR; \
+ 	AS="$(AS)"; export AS; \
+ 	CC_FOR_BUILD="$(CC_FOR_BUILD)"; export CC_FOR_BUILD; \
+@@ -282,6 +284,7 @@ BASE_TARGET_EXPORTS = \
+ 	GCJ="$(GCJ_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GOC; \
++	GDC="$(GDC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_TARGET)"; export DLLTOOL; \
+ 	LD="$(COMPILER_LD_FOR_TARGET)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_TARGET)"; export LDFLAGS; \
+@@ -350,6 +353,7 @@ DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
+ GCJ_FOR_BUILD = @GCJ_FOR_BUILD@
+ GFORTRAN_FOR_BUILD = @GFORTRAN_FOR_BUILD@
+ GOC_FOR_BUILD = @GOC_FOR_BUILD@
++GDC_FOR_BUILD = @GDC_FOR_BUILD@
+ LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
+ LD_FOR_BUILD = @LD_FOR_BUILD@
+ NM_FOR_BUILD = @NM_FOR_BUILD@
+@@ -530,6 +534,7 @@ RAW_CXX_FOR_TARGET=$(STAGE_CC_WRAPPER) @
+ GCJ_FOR_TARGET=$(STAGE_CC_WRAPPER) @GCJ_FOR_TARGET@
+ GFORTRAN_FOR_TARGET=$(STAGE_CC_WRAPPER) @GFORTRAN_FOR_TARGET@
+ GOC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GOC_FOR_TARGET@
++GDC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GDC_FOR_TARGET@
+ DLLTOOL_FOR_TARGET=@DLLTOOL_FOR_TARGET@
+ LD_FOR_TARGET=@LD_FOR_TARGET@
+ 
+@@ -754,6 +759,7 @@ BASE_FLAGS_TO_PASS = \
+ 	"GFORTRAN_FOR_TARGET=$(GFORTRAN_FOR_TARGET)" \
+ 	"GOC_FOR_TARGET=$(GOC_FOR_TARGET)" \
+ 	"GOCFLAGS_FOR_TARGET=$(GOCFLAGS_FOR_TARGET)" \
++	"GDC_FOR_TARGET=$(GDC_FOR_TARGET)" \
+ 	"LD_FOR_TARGET=$(LD_FOR_TARGET)" \
+ 	"LIPO_FOR_TARGET=$(LIPO_FOR_TARGET)" \
+ 	"LDFLAGS_FOR_TARGET=$(LDFLAGS_FOR_TARGET)" \
+@@ -808,6 +814,7 @@ EXTRA_HOST_FLAGS = \
+ 	'GCJ=$(GCJ)' \
+ 	'GFORTRAN=$(GFORTRAN)' \
+ 	'GOC=$(GOC)' \
++	'GDC=$(GDC)' \
+ 	'LD=$(LD)' \
+ 	'LIPO=$(LIPO)' \
+ 	'NM=$(NM)' \
+@@ -864,6 +871,7 @@ EXTRA_TARGET_FLAGS = \
+ 	'GFORTRAN=$$(GFORTRAN_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOC=$$(GOC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOCFLAGS=$$(GOCFLAGS_FOR_TARGET)' \
++	'GDC=$$(GDC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'LD=$(COMPILER_LD_FOR_TARGET)' \
+ 	'LDFLAGS=$$(LDFLAGS_FOR_TARGET)' \
+ 	'LIBCFLAGS=$$(LIBCFLAGS_FOR_TARGET)' \
+@@ -966,6 +974,7 @@ configure-target:  \
+     maybe-configure-target-libgfortran \
+     maybe-configure-target-libobjc \
+     maybe-configure-target-libgo \
++    maybe-configure-target-libphobos \
+     maybe-configure-target-libtermcap \
+     maybe-configure-target-winsup \
+     maybe-configure-target-libgloss \
+@@ -1137,6 +1146,7 @@ all-target: maybe-all-target-libquadmath
+ all-target: maybe-all-target-libgfortran
+ all-target: maybe-all-target-libobjc
+ all-target: maybe-all-target-libgo
++all-target: maybe-all-target-libphobos
+ all-target: maybe-all-target-libtermcap
+ all-target: maybe-all-target-winsup
+ all-target: maybe-all-target-libgloss
+@@ -1235,6 +1245,7 @@ info-target: maybe-info-target-libquadma
+ info-target: maybe-info-target-libgfortran
+ info-target: maybe-info-target-libobjc
+ info-target: maybe-info-target-libgo
++info-target: maybe-info-target-libphobos
+ info-target: maybe-info-target-libtermcap
+ info-target: maybe-info-target-winsup
+ info-target: maybe-info-target-libgloss
+@@ -1326,6 +1337,7 @@ dvi-target: maybe-dvi-target-libquadmath
+ dvi-target: maybe-dvi-target-libgfortran
+ dvi-target: maybe-dvi-target-libobjc
+ dvi-target: maybe-dvi-target-libgo
++dvi-target: maybe-dvi-target-libphobos
+ dvi-target: maybe-dvi-target-libtermcap
+ dvi-target: maybe-dvi-target-winsup
+ dvi-target: maybe-dvi-target-libgloss
+@@ -1417,6 +1429,7 @@ pdf-target: maybe-pdf-target-libquadmath
+ pdf-target: maybe-pdf-target-libgfortran
+ pdf-target: maybe-pdf-target-libobjc
+ pdf-target: maybe-pdf-target-libgo
++pdf-target: maybe-pdf-target-libphobos
+ pdf-target: maybe-pdf-target-libtermcap
+ pdf-target: maybe-pdf-target-winsup
+ pdf-target: maybe-pdf-target-libgloss
+@@ -1508,6 +1521,7 @@ html-target: maybe-html-target-libquadma
+ html-target: maybe-html-target-libgfortran
+ html-target: maybe-html-target-libobjc
+ html-target: maybe-html-target-libgo
++html-target: maybe-html-target-libphobos
+ html-target: maybe-html-target-libtermcap
+ html-target: maybe-html-target-winsup
+ html-target: maybe-html-target-libgloss
+@@ -1599,6 +1613,7 @@ TAGS-target: maybe-TAGS-target-libquadma
+ TAGS-target: maybe-TAGS-target-libgfortran
+ TAGS-target: maybe-TAGS-target-libobjc
+ TAGS-target: maybe-TAGS-target-libgo
++TAGS-target: maybe-TAGS-target-libphobos
+ TAGS-target: maybe-TAGS-target-libtermcap
+ TAGS-target: maybe-TAGS-target-winsup
+ TAGS-target: maybe-TAGS-target-libgloss
+@@ -1690,6 +1705,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-libgfortran
+ install-info-target: maybe-install-info-target-libobjc
+ install-info-target: maybe-install-info-target-libgo
++install-info-target: maybe-install-info-target-libphobos
+ install-info-target: maybe-install-info-target-libtermcap
+ install-info-target: maybe-install-info-target-winsup
+ install-info-target: maybe-install-info-target-libgloss
+@@ -1781,6 +1797,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-libgfortran
+ install-pdf-target: maybe-install-pdf-target-libobjc
+ install-pdf-target: maybe-install-pdf-target-libgo
++install-pdf-target: maybe-install-pdf-target-libphobos
+ install-pdf-target: maybe-install-pdf-target-libtermcap
+ install-pdf-target: maybe-install-pdf-target-winsup
+ install-pdf-target: maybe-install-pdf-target-libgloss
+@@ -1872,6 +1889,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-libgfortran
+ install-html-target: maybe-install-html-target-libobjc
+ install-html-target: maybe-install-html-target-libgo
++install-html-target: maybe-install-html-target-libphobos
+ install-html-target: maybe-install-html-target-libtermcap
+ install-html-target: maybe-install-html-target-winsup
+ install-html-target: maybe-install-html-target-libgloss
+@@ -1963,6 +1981,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-libgfortran
+ installcheck-target: maybe-installcheck-target-libobjc
+ installcheck-target: maybe-installcheck-target-libgo
++installcheck-target: maybe-installcheck-target-libphobos
+ installcheck-target: maybe-installcheck-target-libtermcap
+ installcheck-target: maybe-installcheck-target-winsup
+ installcheck-target: maybe-installcheck-target-libgloss
+@@ -2054,6 +2073,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-libgfortran
+ mostlyclean-target: maybe-mostlyclean-target-libobjc
+ mostlyclean-target: maybe-mostlyclean-target-libgo
++mostlyclean-target: maybe-mostlyclean-target-libphobos
+ mostlyclean-target: maybe-mostlyclean-target-libtermcap
+ mostlyclean-target: maybe-mostlyclean-target-winsup
+ mostlyclean-target: maybe-mostlyclean-target-libgloss
+@@ -2145,6 +2165,7 @@ clean-target: maybe-clean-target-libquad
+ clean-target: maybe-clean-target-libgfortran
+ clean-target: maybe-clean-target-libobjc
+ clean-target: maybe-clean-target-libgo
++clean-target: maybe-clean-target-libphobos
+ clean-target: maybe-clean-target-libtermcap
+ clean-target: maybe-clean-target-winsup
+ clean-target: maybe-clean-target-libgloss
+@@ -2236,6 +2257,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-libgfortran
+ distclean-target: maybe-distclean-target-libobjc
+ distclean-target: maybe-distclean-target-libgo
++distclean-target: maybe-distclean-target-libphobos
+ distclean-target: maybe-distclean-target-libtermcap
+ distclean-target: maybe-distclean-target-winsup
+ distclean-target: maybe-distclean-target-libgloss
+@@ -2327,6 +2349,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-libgfortran
+ maintainer-clean-target: maybe-maintainer-clean-target-libobjc
+ maintainer-clean-target: maybe-maintainer-clean-target-libgo
++maintainer-clean-target: maybe-maintainer-clean-target-libphobos
+ maintainer-clean-target: maybe-maintainer-clean-target-libtermcap
+ maintainer-clean-target: maybe-maintainer-clean-target-winsup
+ maintainer-clean-target: maybe-maintainer-clean-target-libgloss
+@@ -2474,6 +2497,7 @@ check-target:  \
+     maybe-check-target-libgfortran \
+     maybe-check-target-libobjc \
+     maybe-check-target-libgo \
++    maybe-check-target-libphobos \
+     maybe-check-target-libtermcap \
+     maybe-check-target-winsup \
+     maybe-check-target-libgloss \
+@@ -2661,6 +2685,7 @@ install-target:  \
+     maybe-install-target-libgfortran \
+     maybe-install-target-libobjc \
+     maybe-install-target-libgo \
++    maybe-install-target-libphobos \
+     maybe-install-target-libtermcap \
+     maybe-install-target-winsup \
+     maybe-install-target-libgloss \
+@@ -2772,6 +2797,7 @@ install-strip-target:  \
+     maybe-install-strip-target-libgfortran \
+     maybe-install-strip-target-libobjc \
+     maybe-install-strip-target-libgo \
++    maybe-install-strip-target-libphobos \
+     maybe-install-strip-target-libtermcap \
+     maybe-install-strip-target-winsup \
+     maybe-install-strip-target-libgloss \
+@@ -41722,6 +41748,464 @@ maintainer-clean-target-libgo:
+ 
+ 
+ 
++.PHONY: configure-target-libphobos maybe-configure-target-libphobos
++maybe-configure-target-libphobos:
++@if gcc-bootstrap
++configure-target-libphobos: stage_current
++@endif gcc-bootstrap
++@if target-libphobos
++maybe-configure-target-libphobos: configure-target-libphobos
++configure-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libphobos..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libphobos; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libphobos/multilib.tmp 2> /dev/null; \
++	if test -r $(TARGET_SUBDIR)/libphobos/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libphobos/multilib.tmp $(TARGET_SUBDIR)/libphobos/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libphobos/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libphobos/Makefile; \
++	    mv $(TARGET_SUBDIR)/libphobos/multilib.tmp $(TARGET_SUBDIR)/libphobos/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libphobos/multilib.tmp $(TARGET_SUBDIR)/libphobos/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libphobos/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libphobos; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libphobos; \
++	cd "$(TARGET_SUBDIR)/libphobos" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libphobos/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libphobos; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libphobos
++
++
++
++
++
++.PHONY: all-target-libphobos maybe-all-target-libphobos
++maybe-all-target-libphobos:
++@if gcc-bootstrap
++all-target-libphobos: stage_current
++@endif gcc-bootstrap
++@if target-libphobos
++TARGET-target-libphobos=all
++maybe-all-target-libphobos: all-target-libphobos
++all-target-libphobos: configure-target-libphobos
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libphobos))
++@endif target-libphobos
++
++
++
++
++
++.PHONY: check-target-libphobos maybe-check-target-libphobos
++maybe-check-target-libphobos:
++@if target-libphobos
++maybe-check-target-libphobos: check-target-libphobos
++
++check-target-libphobos:
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)   check)
++
++@endif target-libphobos
++
++.PHONY: install-target-libphobos maybe-install-target-libphobos
++maybe-install-target-libphobos:
++@if target-libphobos
++maybe-install-target-libphobos: install-target-libphobos
++
++install-target-libphobos: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++
++@endif target-libphobos
++
++.PHONY: install-strip-target-libphobos maybe-install-strip-target-libphobos
++maybe-install-strip-target-libphobos:
++@if target-libphobos
++maybe-install-strip-target-libphobos: install-strip-target-libphobos
++
++install-strip-target-libphobos: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++
++@endif target-libphobos
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libphobos info-target-libphobos
++maybe-info-target-libphobos:
++@if target-libphobos
++maybe-info-target-libphobos: info-target-libphobos
++
++info-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing info in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           info) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-dvi-target-libphobos dvi-target-libphobos
++maybe-dvi-target-libphobos:
++@if target-libphobos
++maybe-dvi-target-libphobos: dvi-target-libphobos
++
++dvi-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing dvi in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           dvi) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-pdf-target-libphobos pdf-target-libphobos
++maybe-pdf-target-libphobos:
++@if target-libphobos
++maybe-pdf-target-libphobos: pdf-target-libphobos
++
++pdf-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-html-target-libphobos html-target-libphobos
++maybe-html-target-libphobos:
++@if target-libphobos
++maybe-html-target-libphobos: html-target-libphobos
++
++html-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing html in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           html) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-TAGS-target-libphobos TAGS-target-libphobos
++maybe-TAGS-target-libphobos:
++@if target-libphobos
++maybe-TAGS-target-libphobos: TAGS-target-libphobos
++
++TAGS-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing TAGS in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           TAGS) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-install-info-target-libphobos install-info-target-libphobos
++maybe-install-info-target-libphobos:
++@if target-libphobos
++maybe-install-info-target-libphobos: install-info-target-libphobos
++
++install-info-target-libphobos: \
++    configure-target-libphobos \
++    info-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-info in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-info) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-install-pdf-target-libphobos install-pdf-target-libphobos
++maybe-install-pdf-target-libphobos:
++@if target-libphobos
++maybe-install-pdf-target-libphobos: install-pdf-target-libphobos
++
++install-pdf-target-libphobos: \
++    configure-target-libphobos \
++    pdf-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-install-html-target-libphobos install-html-target-libphobos
++maybe-install-html-target-libphobos:
++@if target-libphobos
++maybe-install-html-target-libphobos: install-html-target-libphobos
++
++install-html-target-libphobos: \
++    configure-target-libphobos \
++    html-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-installcheck-target-libphobos installcheck-target-libphobos
++maybe-installcheck-target-libphobos:
++@if target-libphobos
++maybe-installcheck-target-libphobos: installcheck-target-libphobos
++
++installcheck-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing installcheck in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           installcheck) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-mostlyclean-target-libphobos mostlyclean-target-libphobos
++maybe-mostlyclean-target-libphobos:
++@if target-libphobos
++maybe-mostlyclean-target-libphobos: mostlyclean-target-libphobos
++
++mostlyclean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-clean-target-libphobos clean-target-libphobos
++maybe-clean-target-libphobos:
++@if target-libphobos
++maybe-clean-target-libphobos: clean-target-libphobos
++
++clean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-distclean-target-libphobos distclean-target-libphobos
++maybe-distclean-target-libphobos:
++@if target-libphobos
++maybe-distclean-target-libphobos: distclean-target-libphobos
++
++distclean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-maintainer-clean-target-libphobos maintainer-clean-target-libphobos
++maybe-maintainer-clean-target-libphobos:
++@if target-libphobos
++maybe-maintainer-clean-target-libphobos: maintainer-clean-target-libphobos
++
++maintainer-clean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libphobos
++
++
++
++
++
+ .PHONY: configure-target-libtermcap maybe-configure-target-libtermcap
+ maybe-configure-target-libtermcap:
+ @if gcc-bootstrap
+@@ -46107,8 +46591,8 @@ configure-target-libada-sjlj:
+ 	@r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	echo "Checking multilib configuration for libada-sjlj..."; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
+-	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp 2> /dev/null ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp 2> /dev/null; \
+ 	if test -r $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
+ 	  if cmp -s $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
+ 	    rm -f $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp; \
+@@ -46120,7 +46604,7 @@ configure-target-libada-sjlj:
+ 	  mv $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; \
+ 	fi; \
+ 	test ! -f $(TARGET_SUBDIR)/libada-sjlj/Makefile || exit 0; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj; \
+ 	$(NORMAL_TARGET_EXPORTS)  \
+ 	echo Configuring in $(TARGET_SUBDIR)/libada-sjlj; \
+ 	cd "$(TARGET_SUBDIR)/libada-sjlj" || exit 1; \
+@@ -46225,11 +46709,11 @@ maybe-pdf-target-libada-sjlj: pdf-target
+ pdf-target-libada-sjlj: \
+     configure-target-libada-sjlj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46282,11 +46766,11 @@ install-pdf-target-libada-sjlj: \
+     configure-target-libada-sjlj \
+     pdf-target-libada-sjlj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46309,11 +46793,11 @@ install-html-target-libada-sjlj: \
+     configure-target-libada-sjlj \
+     html-target-libada-sjlj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-html in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46344,11 +46828,11 @@ maybe-mostlyclean-target-libada-sjlj: mo
+ 
+ mostlyclean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46369,11 +46853,11 @@ maybe-clean-target-libada-sjlj: clean-ta
+ 
+ clean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing clean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46394,11 +46878,11 @@ maybe-distclean-target-libada-sjlj: dist
+ 
+ distclean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing distclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46419,11 +46903,11 @@ maybe-maintainer-clean-target-libada-sjl
+ 
+ maintainer-clean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46453,8 +46937,8 @@ configure-target-libgnatvsn:
+ 	@r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	echo "Checking multilib configuration for libgnatvsn..."; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
+-	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp 2> /dev/null ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp 2> /dev/null; \
+ 	if test -r $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
+ 	  if cmp -s $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
+ 	    rm -f $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp; \
+@@ -46466,7 +46950,7 @@ configure-target-libgnatvsn:
+ 	  mv $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; \
+ 	fi; \
+ 	test ! -f $(TARGET_SUBDIR)/libgnatvsn/Makefile || exit 0; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn; \
+ 	$(NORMAL_TARGET_EXPORTS)  \
+ 	echo Configuring in $(TARGET_SUBDIR)/libgnatvsn; \
+ 	cd "$(TARGET_SUBDIR)/libgnatvsn" || exit 1; \
+@@ -46581,11 +47065,11 @@ maybe-pdf-target-libgnatvsn: pdf-target-
+ pdf-target-libgnatvsn: \
+     configure-target-libgnatvsn 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46638,11 +47122,11 @@ install-pdf-target-libgnatvsn: \
+     configure-target-libgnatvsn \
+     pdf-target-libgnatvsn 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46665,11 +47149,11 @@ install-html-target-libgnatvsn: \
+     configure-target-libgnatvsn \
+     html-target-libgnatvsn 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46700,11 +47184,11 @@ maybe-mostlyclean-target-libgnatvsn: mos
+ 
+ mostlyclean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46725,11 +47209,11 @@ maybe-clean-target-libgnatvsn: clean-tar
+ 
+ clean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46750,11 +47234,11 @@ maybe-distclean-target-libgnatvsn: distc
+ 
+ distclean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46775,11 +47259,11 @@ maybe-maintainer-clean-target-libgnatvsn
+ 
+ maintainer-clean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46809,8 +47293,8 @@ configure-target-libgnatprj:
+ 	@r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	echo "Checking multilib configuration for libgnatprj..."; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
+-	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatprj/multilib.tmp 2> /dev/null ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatprj/multilib.tmp 2> /dev/null; \
+ 	if test -r $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
+ 	  if cmp -s $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
+ 	    rm -f $(TARGET_SUBDIR)/libgnatprj/multilib.tmp; \
+@@ -46822,7 +47306,7 @@ configure-target-libgnatprj:
+ 	  mv $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; \
+ 	fi; \
+ 	test ! -f $(TARGET_SUBDIR)/libgnatprj/Makefile || exit 0; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj; \
+ 	$(NORMAL_TARGET_EXPORTS)  \
+ 	echo Configuring in $(TARGET_SUBDIR)/libgnatprj; \
+ 	cd "$(TARGET_SUBDIR)/libgnatprj" || exit 1; \
+@@ -46937,11 +47421,11 @@ maybe-pdf-target-libgnatprj: pdf-target-
+ pdf-target-libgnatprj: \
+     configure-target-libgnatprj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46994,11 +47478,11 @@ install-pdf-target-libgnatprj: \
+     configure-target-libgnatprj \
+     pdf-target-libgnatprj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47021,11 +47505,11 @@ install-html-target-libgnatprj: \
+     configure-target-libgnatprj \
+     html-target-libgnatprj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47056,11 +47540,11 @@ maybe-mostlyclean-target-libgnatprj: mos
+ 
+ mostlyclean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47081,11 +47565,11 @@ maybe-clean-target-libgnatprj: clean-tar
+ 
+ clean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47106,11 +47590,11 @@ maybe-distclean-target-libgnatprj: distc
+ 
+ distclean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47131,11 +47615,11 @@ maybe-maintainer-clean-target-libgnatprj
+ 
+ maintainer-clean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -49141,6 +49625,14 @@ check-gcc-go:
+ 	(cd gcc && $(MAKE) $(GCC_FLAGS_TO_PASS) check-go);
+ check-go: check-gcc-go check-target-libgo
+ 
++.PHONY: check-gcc-d check-d
++check-gcc-d:
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(HOST_EXPORTS) \
++	(cd gcc && $(MAKE) $(GCC_FLAGS_TO_PASS) check-d);
++check-d: check-gcc-d check-target-libphobos
++
+ 
+ # The gcc part of install-no-fixedincludes, which relies on an intimate
+ # knowledge of how a number of gcc internal targets (inter)operate.  Delegate.
+@@ -51347,6 +51839,7 @@ configure-target-libquadmath: stage_last
+ configure-target-libgfortran: stage_last
+ configure-target-libobjc: stage_last
+ configure-target-libgo: stage_last
++configure-target-libphobos: stage_last
+ configure-target-libtermcap: stage_last
+ configure-target-winsup: stage_last
+ configure-target-libgloss: stage_last
+@@ -51385,6 +51878,7 @@ configure-target-libquadmath: maybe-all-
+ configure-target-libgfortran: maybe-all-gcc
+ configure-target-libobjc: maybe-all-gcc
+ configure-target-libgo: maybe-all-gcc
++configure-target-libphobos: maybe-all-gcc
+ configure-target-libtermcap: maybe-all-gcc
+ configure-target-winsup: maybe-all-gcc
+ configure-target-libgloss: maybe-all-gcc
+@@ -52246,6 +52740,8 @@ configure-target-libgo: maybe-all-target
+ all-target-libgo: maybe-all-target-libbacktrace
+ all-target-libgo: maybe-all-target-libffi
+ all-target-libgo: maybe-all-target-libatomic
++configure-target-libphobos: maybe-configure-target-zlib
++all-target-libphobos: maybe-all-target-zlib
+ configure-target-libjava: maybe-configure-target-zlib
+ configure-target-libjava: maybe-configure-target-boehm-gc
+ configure-target-libjava: maybe-configure-target-libffi
+@@ -52364,6 +52860,7 @@ configure-target-libquadmath: maybe-all-
+ configure-target-libgfortran: maybe-all-target-libgcc
+ configure-target-libobjc: maybe-all-target-libgcc
+ configure-target-libgo: maybe-all-target-libgcc
++configure-target-libphobos: maybe-all-target-libgcc
+ configure-target-libtermcap: maybe-all-target-libgcc
+ configure-target-winsup: maybe-all-target-libgcc
+ configure-target-libgloss: maybe-all-target-libgcc
+@@ -52411,6 +52908,8 @@ configure-target-libobjc: maybe-all-targ
+ 
+ configure-target-libgo: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libphobos: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libtermcap: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-winsup: maybe-all-target-newlib maybe-all-target-libgloss
--- gcc-6-6.3.0.orig/debian/patches/gdc-multiarch.diff
+++ gcc-6-6.3.0/debian/patches/gdc-multiarch.diff
@@ -0,0 +1,17 @@
+# DP: Set the D target include directory to a multiarch location.
+
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -61,7 +61,11 @@
+ 	$(D_DMD_H)
+ 
+ 
+-gcc_d_target_include_dir=$(gcc_d_include_dir)/$(target_noncanonical)
++ifneq (,$(MULTIARCH_DIRNAME))
++  gcc_d_target_include_dir = /usr/include/$(MULTIARCH_DIRNAME)/d/$(version)
++else
++  gcc_d_target_include_dir=$(gcc_d_include_dir)/$(target_noncanonical)
++endif
+ 
+ # Name of phobos library
+ D_LIBPHOBOS = -DLIBPHOBOS=\"gphobos2\"
--- gcc-6-6.3.0.orig/debian/patches/gdc-profiledbuild.diff
+++ gcc-6-6.3.0/debian/patches/gdc-profiledbuild.diff
@@ -0,0 +1,19 @@
+# DP: Don't build gdc build tools idgen and impcnvgen with profiling flags
+
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -97,6 +97,14 @@
+ d/impcvgen: d/impcnvgen.dmdgen.o
+ 	+$(LINKER_FOR_BUILD) $(BUILD_LINKER_FLAGS) $(BUILD_LDFLAGS) -o $@ $^
+ 
++d/idgen.dmdgen.o: d/dfrontend/idgen.c
++	$(filter-out -fprofile-%,$(DMD_COMPILE)) $(D_INCLUDES) $<
++	$(POSTCOMPILE)
++
++d/impcnvgen.dmdgen.o: $(srcdir)/d/dfrontend/impcnvgen.c
++	$(filter-out -fprofile-%,$(DMDGEN_COMPILE)) $(D_INCLUDES) $<
++	$(POSTCOMPILE)
++
+ # Generated sources.
+ d/id.c: d/idgen
+ 	cd d && ./idgen
--- gcc-6-6.3.0.orig/debian/patches/gdc-texinfo.diff
+++ gcc-6-6.3.0/debian/patches/gdc-texinfo.diff
@@ -0,0 +1,55 @@
+# DP: Add macros for the gdc texinfo documentation.
+
+Index: b/src/gcc/d/gdc.texi
+===================================================================
+--- a/src/gcc/d/gdc.texi
++++ b/src/gcc/d/gdc.texi
+@@ -43,6 +43,22 @@ man page gfdl(7).
+ @insertcopying
+ @end ifinfo
+ 
++@macro versionsubtitle
++@ifclear DEVELOPMENT
++@subtitle For @sc{gcc} version @value{version-GCC}
++@end ifclear
++@ifset DEVELOPMENT
++@subtitle For @sc{gcc} version @value{version-GCC} (pre-release)
++@end ifset
++@ifset VERSION_PACKAGE
++@sp 1
++@subtitle @value{VERSION_PACKAGE}
++@end ifset
++@c Even if there are no authors, the second titlepage line should be
++@c forced to the bottom of the page.
++@vskip 0pt plus 1filll
++@end macro
++
+ @titlepage
+ @title The GNU D Compiler
+ @versionsubtitle
+@@ -138,6 +154,25 @@ remainder.
+ 
+ @c man end
+ 
++@macro gcctabopt{body}
++@code{\body\}
++@end macro
++@macro gccoptlist{body}
++@smallexample
++\body\
++@end smallexample
++@end macro
++@c Makeinfo handles the above macro OK, TeX needs manual line breaks;
++@c they get lost at some point in handling the macro.  But if @macro is
++@c used here rather than @alias, it produces double line breaks.
++@iftex
++@alias gol = *
++@end iftex
++@ifnottex
++@macro gol
++@end macro
++@end ifnottex
++
+ @c man begin OPTIONS gdc
+ 
+ @table @gcctabopt
--- gcc-6-6.3.0.orig/debian/patches/gdc-updates.diff
+++ gcc-6-6.3.0/debian/patches/gdc-updates.diff
@@ -0,0 +1,26 @@
+# DP: gdc updates up to 20160115.
+
+	* Make-lang.in (d-warn): Filter out -Wmissing-format-attribute.
+
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -51,7 +51,7 @@
+ 	cp gdc$(exeext) gdc-cross$(exeext)
+ 
+ # Filter out pedantic and virtual overload warnings.
+-d-warn = $(filter-out -pedantic -Woverloaded-virtual, $(STRICT_WARN))
++d-warn = $(filter-out -pedantic -Woverloaded-virtual -Wmissing-format-attribute, $(STRICT_WARN))
+ 
+ # D Frontend has slightly relaxed warnings compared to rest of GDC.
+ DMD_WARN_CXXFLAGS = -Wno-deprecated -Wstrict-aliasing -Wuninitialized
+--- a/src/libphobos/src/std/internal/math/gammafunction.d
++++ b/src/libphobos/src/std/internal/math/gammafunction.d
+@@ -420,7 +420,7 @@
+         if ( p == q )
+             return real.infinity;
+         int intpart = cast(int)(p);
+-        real sgngam = 1;
++        real sgngam = 1.0L;
+         if ( (intpart & 1) == 0 )
+             sgngam = -1;
+         z = q - p;
--- gcc-6-6.3.0.orig/debian/patches/gdc-versym-cpu.diff
+++ gcc-6-6.3.0/debian/patches/gdc-versym-cpu.diff
@@ -0,0 +1,382 @@
+# DP: Implements D CPU version conditions.
+
+This implements the following versions:
+* D_HardFloat
+* D_SoftFloat
+
+for all supported architectures. And these where appropriate:
+* ARM
+** ARM_Thumb
+** ARM_HardFloat
+** ARM_SoftFloat
+** ARM_SoftFP
+* AArch64
+* Alpha
+** Alpha_SoftFloat
+** Alpha_HardFloat
+* X86
+* X86_64
+** D_X32
+* IA64
+* MIPS32
+* MIPS64
+** MIPS_O32
+** MIPS_O64
+** MIPS_N32
+** MIPS_N64
+** MIPS_EABI
+** MIPS_HardFloat
+** MIPS_SoftFloat
+* HPPA
+* HPPA64
+* PPC
+* PPC64
+** PPC_HardFloat
+** PPC_SoftFloat
+* S390
+* S390X
+* SH
+* SH64
+* SPARC
+* SPARC64
+* SPARC_V8Plus
+** SPARC_HardFloat
+** SPARC_SoftFloat
+
+Index: b/src/gcc/config/aarch64/aarch64.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.h
++++ b/src/gcc/config/aarch64/aarch64.h
+@@ -26,6 +26,14 @@
+ #define TARGET_CPU_CPP_BUILTINS()	\
+   aarch64_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++      builtin_define ("AArch64");			\
++      builtin_define ("D_HardFloat");			\
++    } while (0)
++
+ 
+ 
+ #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
+Index: b/src/gcc/config/alpha/alpha.h
+===================================================================
+--- a/src/gcc/config/alpha/alpha.h
++++ b/src/gcc/config/alpha/alpha.h
+@@ -72,6 +72,23 @@ along with GCC; see the file COPYING3.
+ 	SUBTARGET_LANGUAGE_CPP_BUILTINS();		\
+ } while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++	builtin_define ("Alpha");			\
++	if (TARGET_SOFT_FP)				\
++	  {						\
++	    builtin_define ("D_SoftFloat");		\
++	    builtin_define ("Alpha_SoftFloat");		\
++	  }						\
++	else						\
++	  {						\
++	    builtin_define ("D_HardFloat");		\
++	    builtin_define ("Alpha_HardFloat");		\
++	  }						\
++} while (0)
++
+ #ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS
+ #define SUBTARGET_LANGUAGE_CPP_BUILTINS()		\
+   do							\
+Index: b/src/gcc/config/arm/arm.h
+===================================================================
+--- a/src/gcc/config/arm/arm.h
++++ b/src/gcc/config/arm/arm.h
+@@ -47,6 +47,31 @@ extern char arm_arch_name[];
+ /* Target CPU builtins.  */
+ #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++	builtin_define ("ARM");				\
++							\
++	if (TARGET_THUMB || TARGET_THUMB2)		\
++	  builtin_define ("ARM_Thumb");			\
++							\
++	if (TARGET_HARD_FLOAT_ABI)			\
++	  builtin_define ("ARM_HardFloat");		\
++	else						\
++	  {						\
++	    if(TARGET_SOFT_FLOAT)			\
++	      builtin_define ("ARM_SoftFloat");		\
++	    else if(TARGET_HARD_FLOAT)			\
++	      builtin_define ("ARM_SoftFP");		\
++	  }						\
++							\
++	if(TARGET_SOFT_FLOAT)				\
++	  builtin_define ("D_SoftFloat");		\
++	else if(TARGET_HARD_FLOAT)			\
++	  builtin_define ("D_HardFloat");		\
++    } while (0)
++
+ #include "config/arm/arm-opts.h"
+ 
+ enum target_cpus
+Index: b/src/gcc/config/i386/i386.h
+===================================================================
+--- a/src/gcc/config/i386/i386.h
++++ b/src/gcc/config/i386/i386.h
+@@ -662,6 +662,24 @@ extern const char *host_detect_local_cpu
+ /* Target CPU builtins.  */
+ #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++  do {						\
++    if (TARGET_64BIT)				\
++    {						\
++      builtin_define("X86_64");			\
++      if (TARGET_X32)				\
++        builtin_define("D_X32");		\
++    }						\
++    else					\
++      builtin_define("X86");			\
++						\
++    if (TARGET_80387)				\
++      builtin_define("D_HardFloat");		\
++    else					\
++      builtin_define("D_SoftFloat");		\
++  } while (0)
++
+ /* Target Pragmas.  */
+ #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
+ 
+Index: b/src/gcc/config/ia64/ia64.h
+===================================================================
+--- a/src/gcc/config/ia64/ia64.h
++++ b/src/gcc/config/ia64/ia64.h
+@@ -40,6 +40,13 @@ do {						\
+ 	  builtin_define("__BIG_ENDIAN__");	\
+ } while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++do {						\
++	builtin_define ("IA64");		\
++	builtin_define ("D_HardFloat");		\
++} while (0)
++
+ #ifndef SUBTARGET_EXTRA_SPECS
+ #define SUBTARGET_EXTRA_SPECS
+ #endif
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -622,6 +622,54 @@ struct mips_cpu_info {
+     }									\
+   while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()						\
++  do									\
++  {									\
++    if (TARGET_64BIT)							\
++      builtin_define("MIPS64");						\
++    else								\
++      builtin_define("MIPS32");						\
++									\
++    switch (mips_abi)							\
++    {									\
++      case ABI_32:							\
++	builtin_define("MIPS_O32");					\
++	break;								\
++									\
++      case ABI_O64:							\
++	builtin_define("MIPS_O64");					\
++	break;								\
++									\
++      case ABI_N32:							\
++	builtin_define("MIPS_N32");					\
++	break;								\
++									\
++      case ABI_64:							\
++	builtin_define("MIPS_N64");					\
++	break;								\
++									\
++      case ABI_EABI:							\
++	builtin_define("MIPS_EABI");					\
++	break;								\
++									\
++      default:								\
++	gcc_unreachable();						\
++    }									\
++									\
++    if (TARGET_HARD_FLOAT_ABI)						\
++    {									\
++      builtin_define("MIPS_HardFloat");					\
++      builtin_define("D_HardFloat");					\
++    }									\
++    else if (TARGET_SOFT_FLOAT_ABI)					\
++    {									\
++      builtin_define("MIPS_SoftFloat");					\
++      builtin_define("D_SoftFloat");					\
++    }									\
++  }									\
++  while (0)
++
+ /* Default target_flags if no switches are specified  */
+ 
+ #ifndef TARGET_DEFAULT
+Index: b/src/gcc/config/pa/pa.h
+===================================================================
+--- a/src/gcc/config/pa/pa.h
++++ b/src/gcc/config/pa/pa.h
+@@ -185,6 +185,20 @@ do {								\
+        builtin_define("_PA_RISC1_0");				\
+ } while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()					\
++do {								\
++     if(TARGET_64BIT)						\
++       builtin_define("HPPA64");				\
++     else							\
++       builtin_define("HPPA");					\
++								\
++     if(TARGET_SOFT_FLOAT)					\
++       builtin_define ("D_SoftFloat");				\
++     else							\
++       builtin_define ("D_HardFloat");				\
++} while (0)
++
+ /* An old set of OS defines for various BSD-like systems.  */
+ #define TARGET_OS_CPP_BUILTINS()				\
+   do								\
+Index: b/src/gcc/config/rs6000/rs6000.h
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.h
++++ b/src/gcc/config/rs6000/rs6000.h
+@@ -802,6 +802,28 @@ extern unsigned char rs6000_recip_bits[]
+ #define TARGET_CPU_CPP_BUILTINS() \
+   rs6000_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++  do						\
++    {						\
++      if (TARGET_64BIT)				\
++	builtin_define ("PPC64");		\
++      else					\
++	builtin_define ("PPC");			\
++						\
++      if (TARGET_HARD_FLOAT)			\
++	{					\
++	  builtin_define ("PPC_HardFloat");	\
++	  builtin_define ("D_HardFloat");	\
++	}					\
++      else if (TARGET_SOFT_FLOAT)		\
++	{					\
++	  builtin_define ("PPC_SoftFloat");	\
++	  builtin_define ("D_SoftFloat");	\
++	}					\
++    }						\
++  while (0)
++
+ /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
+    we're compiling for.  Some configurations may need to override it.  */
+ #define RS6000_CPU_CPP_ENDIAN_BUILTINS()	\
+Index: b/src/gcc/config/s390/s390.h
+===================================================================
+--- a/src/gcc/config/s390/s390.h
++++ b/src/gcc/config/s390/s390.h
+@@ -177,6 +177,22 @@ enum processor_flags
+ /* Target CPU builtins.  */
+ #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++      if (TARGET_64BIT)					\
++        builtin_define ("S390X");			\
++      else						\
++        builtin_define ("S390");			\
++							\
++      if(TARGET_SOFT_FLOAT)				\
++        builtin_define ("D_SoftFloat");			\
++      else if(TARGET_HARD_FLOAT)			\
++        builtin_define ("D_HardFloat");			\
++    }							\
++  while (0)
++
+ #ifdef DEFAULT_TARGET_64BIT
+ #define TARGET_DEFAULT     (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP	\
+                             | MASK_OPT_HTM | MASK_OPT_VX)
+Index: b/src/gcc/config/sh/sh.h
+===================================================================
+--- a/src/gcc/config/sh/sh.h
++++ b/src/gcc/config/sh/sh.h
+@@ -31,6 +31,22 @@ extern int code_for_indirect_jump_scratc
+ 
+ #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++  do						\
++    {						\
++      if (TARGET_SHMEDIA64)			\
++	builtin_define ("SH64");		\
++      else					\
++	builtin_define ("SH");			\
++						\
++      if (TARGET_FPU_ANY)			\
++	builtin_define ("D_HardFloat");		\
++      else					\
++	builtin_define ("D_SoftFloat");		\
++    }						\
++  while (0)
++
+ /* Value should be nonzero if functions must have frame pointers.
+    Zero means the frame pointer need not be set up (and parms may be accessed
+    via the stack pointer) in functions that seem suitable.  */
+Index: b/src/gcc/config/sparc/sparc.h
+===================================================================
+--- a/src/gcc/config/sparc/sparc.h
++++ b/src/gcc/config/sparc/sparc.h
+@@ -27,6 +27,31 @@ along with GCC; see the file COPYING3.
+ 
+ #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++do						\
++    {						\
++      if (TARGET_64BIT)				\
++	builtin_define ("SPARC64");		\
++      else					\
++	builtin_define ("SPARC");		\
++						\
++      if(TARGET_V8PLUS)				\
++	builtin_define ("SPARC_V8Plus");	\
++						\
++      if(TARGET_FPU)				\
++	{					\
++	  builtin_define ("D_HardFloat");	\
++	  builtin_define ("SPARC_HardFloat");	\
++	}					\
++      else					\
++	{					\
++	  builtin_define ("D_SoftFloat");	\
++	  builtin_define ("SPARC_SoftFloat");	\
++	}					\
++    }						\
++  while (0)
++
+ /* Specify this in a cover file to provide bi-architecture (32/64) support.  */
+ /* #define SPARC_BI_ARCH */
+ 
--- gcc-6-6.3.0.orig/debian/patches/gdc-versym-os.diff
+++ gcc-6-6.3.0/debian/patches/gdc-versym-os.diff
@@ -0,0 +1,430 @@
+# DP: Implements D OS version conditions.
+
+This implements the following official versions:
+* Windows
+** Win32
+** Win64
+** Cygwin
+** MinGW
+* linux
+* OSX
+* FreeBSD
+* OpenBSD
+* NetBSD
+* Solaris
+* Posix
+* AIX
+* SysV4
+* Hurd
+* Android
+
+These gdc specific versions are also implemented:
+* GNU_MinGW64 (for mingw-w64)
+* GNU_OpenSolaris (for opensolaris)
+* GNU_GLibc (implemented for linux & bsd & opensolaris)
+* GNU_UCLibc (implemented for linux)
+* GNU_Bionic (implemented for linux)
+
+These official OS versions are not implemented:
+* DragonFlyBSD
+* BSD (other BSDs)
+* Haiku
+* SkyOS
+* SysV3
+
+Index: b/src/gcc/config/alpha/linux.h
+===================================================================
+--- a/src/gcc/config/alpha/linux.h
++++ b/src/gcc/config/alpha/linux.h
+@@ -33,6 +33,16 @@ along with GCC; see the file COPYING3.
+ 	  builtin_define ("_GNU_SOURCE");			\
+     } while (0)
+ 
++#undef TARGET_OS_D_BUILTINS 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	if (OPTION_GLIBC)					\
++	  builtin_define ("GNU_GLibc");				\
++								\
++	builtin_define ("linux");				\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ #undef LIB_SPEC
+ #define LIB_SPEC \
+   "%{pthread:-lpthread} \
+Index: b/src/gcc/config/arm/linux-eabi.h
+===================================================================
+--- a/src/gcc/config/arm/linux-eabi.h
++++ b/src/gcc/config/arm/linux-eabi.h
+@@ -30,6 +30,15 @@
+     }						\
+   while (false)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS() 			\
++  do 						\
++    {						\
++      TARGET_GENERIC_LINUX_OS_D_BUILTINS();	\
++      ANDROID_TARGET_OS_D_BUILTINS();		\
++    }						\
++  while (false)
++
+ /* We default to a soft-float ABI so that binaries can run on all
+    target hardware.  If you override this to use the hard-float ABI then
+    change the setting of GLIBC_DYNAMIC_LINKER_DEFAULT as well.  */
+Index: b/src/gcc/config/darwin.h
+===================================================================
+--- a/src/gcc/config/darwin.h
++++ b/src/gcc/config/darwin.h
+@@ -977,4 +977,10 @@ extern void darwin_driver_init (unsigned
+ #define DEF_LD64 LD64_VERSION
+ #endif
+ 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	builtin_define ("OSX");					\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ #endif /* CONFIG_DARWIN_H */
+Index: b/src/gcc/config/freebsd.h
+===================================================================
+--- a/src/gcc/config/freebsd.h
++++ b/src/gcc/config/freebsd.h
+@@ -32,6 +32,13 @@ along with GCC; see the file COPYING3.
+ #undef  TARGET_OS_CPP_BUILTINS
+ #define TARGET_OS_CPP_BUILTINS() FBSD_TARGET_OS_CPP_BUILTINS()
+ 
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	builtin_define ("FreeBSD");				\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ #undef  CPP_SPEC
+ #define CPP_SPEC FBSD_CPP_SPEC
+ 
+Index: b/src/gcc/config/gnu.h
+===================================================================
+--- a/src/gcc/config/gnu.h
++++ b/src/gcc/config/gnu.h
+@@ -31,3 +31,11 @@ along with GCC.  If not, see <http://www
+ 	builtin_assert ("system=unix");		\
+ 	builtin_assert ("system=posix");	\
+     } while (0)
++
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++								\
++	builtin_define ("Hurd");				\
++	builtin_define ("Posix");				\
++    } while (0)
+Index: b/src/gcc/config/i386/cygwin.h
+===================================================================
+--- a/src/gcc/config/i386/cygwin.h
++++ b/src/gcc/config/i386/cygwin.h
+@@ -29,6 +29,13 @@ along with GCC; see the file COPYING3.
+     }								\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++      builtin_define ("Windows");				\
++      builtin_define ("Cygwin");				\
++      builtin_define ("Posix");					\
++    } while (0)
++
+ #undef CPP_SPEC
+ #define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE} \
+   %{!ansi:-Dunix} \
+Index: b/src/gcc/config/i386/linux-common.h
+===================================================================
+--- a/src/gcc/config/i386/linux-common.h
++++ b/src/gcc/config/i386/linux-common.h
+@@ -27,6 +27,15 @@ along with GCC; see the file COPYING3.
+     }                                          \
+   while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS() 			\
++  do 						\
++    {						\
++      TARGET_GENERIC_LINUX_OS_D_BUILTINS();	\
++      ANDROID_TARGET_OS_D_BUILTINS();		\
++    }						\
++  while (0)
++
+ #undef CC1_SPEC
+ #define CC1_SPEC \
+   LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC, \
+Index: b/src/gcc/config/i386/mingw-w64.h
+===================================================================
+--- a/src/gcc/config/i386/mingw-w64.h
++++ b/src/gcc/config/i386/mingw-w64.h
+@@ -89,3 +89,10 @@ along with GCC; see the file COPYING3.
+   %{static:-Bstatic} %{!static:-Bdynamic} \
+   %{shared|mdll: " SUB_LINK_ENTRY " --enable-auto-image-base} \
+   %(shared_libgcc_undefs)"
++
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++      TARGET_GENERIC_MINGW_OS_D_BUILTINS();			\
++      builtin_define ("GNU_MinGW64");				\
++    } while (0)
+Index: b/src/gcc/config/i386/mingw32.h
+===================================================================
+--- a/src/gcc/config/i386/mingw32.h
++++ b/src/gcc/config/i386/mingw32.h
+@@ -53,6 +53,18 @@ along with GCC; see the file COPYING3.
+     }								\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS() TARGET_GENERIC_MINGW_OS_D_BUILTINS()
++#define TARGET_GENERIC_MINGW_OS_D_BUILTINS()			\
++    do {							\
++      builtin_define ("Windows");				\
++      builtin_define ("MinGW");					\
++								\
++      if (TARGET_64BIT && ix86_abi == MS_ABI)			\
++	  builtin_define ("Win64");				\
++      else if (!TARGET_64BIT)					\
++        builtin_define ("Win32");				\
++    } while (0)
++
+ #ifndef TARGET_USE_PTHREAD_BY_DEFAULT
+ #define SPEC_PTHREAD1 "pthread"
+ #define SPEC_PTHREAD2 "!no-pthread"
+Index: b/src/gcc/config/kfreebsd-gnu.h
+===================================================================
+--- a/src/gcc/config/kfreebsd-gnu.h
++++ b/src/gcc/config/kfreebsd-gnu.h
+@@ -29,6 +29,14 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	builtin_define ("FreeBSD");				\
++	builtin_define ("Posix");				\
++	builtin_define ("GNU_GLibc");				\
++    } while (0)
++
+ #define GNU_USER_DYNAMIC_LINKER        GLIBC_DYNAMIC_LINKER
+ #define GNU_USER_DYNAMIC_LINKER32      GLIBC_DYNAMIC_LINKER32
+ #define GNU_USER_DYNAMIC_LINKER64      GLIBC_DYNAMIC_LINKER64
+Index: b/src/gcc/config/knetbsd-gnu.h
+===================================================================
+--- a/src/gcc/config/knetbsd-gnu.h
++++ b/src/gcc/config/knetbsd-gnu.h
+@@ -30,6 +30,16 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("NetBSD");		\
++      builtin_define ("Posix");			\
++      builtin_define ("GNU_GLibc");		\
++    }						\
++  while (0)
++
+ 
+ #undef GNU_USER_DYNAMIC_LINKER
+ #define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+Index: b/src/gcc/config/kopensolaris-gnu.h
+===================================================================
+--- a/src/gcc/config/kopensolaris-gnu.h
++++ b/src/gcc/config/kopensolaris-gnu.h
+@@ -30,5 +30,15 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()				\
++  do							\
++    {							\
++	builtin_define ("Solaris");			\
++	builtin_define ("Posix");			\
++	builtin_define ("GNU_OpenSolaris");		\
++	builtin_define ("GNU_GLibc");			\
++    }							\
++  while (0)
++
+ #undef GNU_USER_DYNAMIC_LINKER
+ #define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+Index: b/src/gcc/config/linux-android.h
+===================================================================
+--- a/src/gcc/config/linux-android.h
++++ b/src/gcc/config/linux-android.h
+@@ -25,6 +25,12 @@
+ 	  builtin_define ("__ANDROID__");			\
+     } while (0)
+ 
++#define ANDROID_TARGET_OS_D_BUILTINS()				\
++    do {							\
++	if (TARGET_ANDROID)					\
++	  builtin_define ("Android");				\
++    } while (0)
++
+ #if ANDROID_DEFAULT
+ # define NOANDROID "mno-android"
+ #else
+Index: b/src/gcc/config/linux.h
+===================================================================
+--- a/src/gcc/config/linux.h
++++ b/src/gcc/config/linux.h
+@@ -53,6 +53,28 @@ see the files COPYING3 and COPYING.RUNTI
+ 	builtin_assert ("system=posix");			\
+     } while (0)
+ 
++#define TARGET_OS_D_BUILTINS() TARGET_GENERIC_LINUX_OS_D_BUILTINS()
++#define TARGET_GENERIC_LINUX_OS_D_BUILTINS()			\
++    do {							\
++	if (OPTION_GLIBC)					\
++	  {							\
++	    builtin_define ("GNU_GLibc");			\
++	    builtin_define ("CRuntime_Glibc");			\
++	  }							\
++	else if (OPTION_UCLIBC)					\
++	  {							\
++	    builtin_define ("GNU_UCLibc");			\
++	  }							\
++	else if (OPTION_BIONIC)					\
++	  {							\
++	    builtin_define ("GNU_Bionic");			\
++	    builtin_define ("CRuntime_Bionic");			\
++	  }							\
++								\
++	builtin_define ("linux");				\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+    uClibc or Bionic or musl is the default C library and whether
+    -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+Index: b/src/gcc/config/mips/linux-common.h
+===================================================================
+--- a/src/gcc/config/mips/linux-common.h
++++ b/src/gcc/config/mips/linux-common.h
+@@ -27,6 +27,15 @@ along with GCC; see the file COPYING3.
+     ANDROID_TARGET_OS_CPP_BUILTINS();				\
+   } while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS() 			\
++  do 						\
++    {						\
++      TARGET_GENERIC_LINUX_OS_D_BUILTINS();	\
++      ANDROID_TARGET_OS_D_BUILTINS();		\
++    }						\
++  while (0)
++
+ #undef  LINK_SPEC
+ #define LINK_SPEC							\
+   LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LINK_SPEC,			\
+Index: b/src/gcc/config/netbsd.h
+===================================================================
+--- a/src/gcc/config/netbsd.h
++++ b/src/gcc/config/netbsd.h
+@@ -29,6 +29,14 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("NetBSD");		\
++      builtin_define ("Posix");			\
++    }						\
++  while (0)
++
+ /* CPP_SPEC parts common to all NetBSD targets.  */
+ #define NETBSD_CPP_SPEC				\
+   "%{posix:-D_POSIX_SOURCE} \
+Index: b/src/gcc/config/openbsd.h
+===================================================================
+--- a/src/gcc/config/openbsd.h
++++ b/src/gcc/config/openbsd.h
+@@ -84,6 +84,14 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("OpenBSD");		\
++      builtin_define ("Posix");			\
++    }						\
++  while (0)
++
+ /* TARGET_OS_CPP_BUILTINS() common to all OpenBSD ELF targets.  */
+ #define OPENBSD_OS_CPP_BUILTINS_ELF()		\
+   do						\
+Index: b/src/gcc/config/rs6000/aix.h
+===================================================================
+--- a/src/gcc/config/rs6000/aix.h
++++ b/src/gcc/config/rs6000/aix.h
+@@ -129,6 +129,13 @@
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++								\
++	builtin_define ("AIX");					\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ /* Define appropriate architecture macros for preprocessor depending on
+    target switches.  */
+ 
+Index: b/src/gcc/config/rs6000/linux.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux.h
++++ b/src/gcc/config/rs6000/linux.h
+@@ -57,6 +57,17 @@
+     }						\
+   while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("linux");			\
++      builtin_define ("Posix");			\
++      if (OPTION_GLIBC)				\
++	builtin_define ("GNU_GLibc");		\
++    }						\
++  while (0)
++
+ #undef	CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
+ 
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -391,6 +391,17 @@ extern int dot_symbols;
+     }							\
+   while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()				\
++  do							\
++    {							\
++      builtin_define ("linux");				\
++      builtin_define ("Posix");				\
++      if (OPTION_GLIBC)					\
++	builtin_define ("GNU_GLibc");			\
++    }							\
++  while (0)
++
+ #undef  CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux) %(include_extra)"
+ 
--- gcc-6-6.3.0.orig/debian/patches/go-testsuite.diff
+++ gcc-6-6.3.0/debian/patches/go-testsuite.diff
@@ -0,0 +1,21 @@
+# DP: Skip Go testcase on AArch64 which hangs on the buildds.
+
+Index: b/src/gcc/testsuite/go.test/go-test.exp
+===================================================================
+--- a/src/gcc/testsuite/go.test/go-test.exp
++++ b/src/gcc/testsuite/go.test/go-test.exp
+@@ -404,6 +404,14 @@ proc go-gc-tests { } {
+ 	    continue
+ 	}
+ 
++	# Hangs on the buildds
++	if { [istarget "aarch64*-*-*"] } {
++	    if { [string match "*go.test/test/chan/select5.go" $test] } {
++		untested $test
++		continue
++	    }
++	}
++
+ 	if { [file tail $test] == "init1.go" } {
+ 	    # This tests whether GC runs during init, which for gccgo
+ 	    # it currently does not.
--- gcc-6-6.3.0.orig/debian/patches/gotools-configury.diff
+++ gcc-6-6.3.0/debian/patches/gotools-configury.diff
@@ -0,0 +1,19 @@
+# DP: Fix gotools cross build.
+
+	* Makefile.am: Use GOC configured in configure.ac for cross builds.
+	* configure.ac: Fix NATIVE conditional.
+	* Makefile.in, configure: Regenerate.
+
+Index: b/src/gotools/configure.ac
+===================================================================
+--- a/src/gotools/configure.ac
++++ b/src/gotools/configure.ac
+@@ -46,7 +46,7 @@ AC_PROG_INSTALL
+ AC_PROG_CC
+ AC_PROG_GO
+ 
+-AM_CONDITIONAL(NATIVE, test "$cross_compiling" = no)
++AM_CONDITIONAL(NATIVE, test "$host" = "$target")
+ 
+ dnl Test for -lsocket and -lnsl.  Copied from libjava/configure.ac.
+ AC_CACHE_CHECK([for socket libraries], gotools_cv_lib_sockets,
--- gcc-6-6.3.0.orig/debian/patches/hurd-changes.diff
+++ gcc-6-6.3.0/debian/patches/hurd-changes.diff
@@ -0,0 +1,20 @@
+# DP: Traditional GNU systems don't have a /usr directory.  However, Debian
+# DP: systems do, and we support both having a /usr -> . symlink, and having a
+# DP: /usr directory like the other ports.  So this patch should NOT go
+# DP: upstream.
+
+---
+ config.gcc |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/gcc/config.gcc	(révision 182461)
++++ b/src/gcc/config.gcc	(copie de travail)
+@@ -583,7 +583,7 @@
+     *-*-linux* | frv-*-*linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu | *-*-kopensolaris*-gnu)
+       :;;
+     *-*-gnu*)
+-      native_system_header_dir=/include
++      # native_system_header_dir=/include
+       ;;
+   esac
+   # glibc / uclibc / bionic switch.
--- gcc-6-6.3.0.orig/debian/patches/ignore-pie-specs-when-not-enabled.diff
+++ gcc-6-6.3.0/debian/patches/ignore-pie-specs-when-not-enabled.diff
@@ -0,0 +1,56 @@
+# DP: Ignore dpkg's pie specs when pie is not enabled.
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -3715,6 +3715,36 @@ handle_foffload_option (const char *arg)
+     }
+ }
+ 
++static bool ignore_pie_specs_when_not_enabled(const char *envvar,
++					      const char *specname)
++{
++  const char *envval = secure_getenv(envvar);
++  char *hardening;
++  bool ignore;
++
++  if (strstr (specname, "/pie-compile.specs") == NULL
++      && strstr (specname, "/pie-link.specs") == NULL)
++    return false;
++  if (envval == NULL || strstr (envval, "hardening=") == NULL)
++    return true;
++  ignore = true;
++  hardening = (char *) xmalloc (strlen(envval) + 1);
++  strcpy (hardening, strstr (envval, "hardening="));
++  if (strchr (hardening, ' '))
++    *strchr (hardening, ' ') = '\0';
++  if (strstr(hardening, "+all"))
++    {
++      if (strstr(hardening, "-pie") == NULL)
++	ignore = false;
++    }
++  else if (strstr(hardening, "+pie"))
++    {
++      ignore = false;
++    }
++  free (hardening);
++  return ignore;
++}
++
+ /* Handle a driver option; arguments and return value as for
+    handle_option.  */
+ 
+@@ -3989,6 +4019,12 @@ driver_handle_option (struct gcc_options
+       break;
+ 
+     case OPT_specs_:
++      if (ignore_pie_specs_when_not_enabled("DEB_BUILD_MAINT_OPTIONS", arg)
++	  && ignore_pie_specs_when_not_enabled("DEB_BUILD_OPTIONS", arg))
++	{
++	  inform (0, "pie specs %s ignored when pie is not enabled", arg);
++	  return true;
++	}
+       {
+ 	struct user_specs *user = XNEW (struct user_specs);
+ 
--- gcc-6-6.3.0.orig/debian/patches/kfreebsd-unwind.diff
+++ gcc-6-6.3.0/debian/patches/kfreebsd-unwind.diff
@@ -0,0 +1,53 @@
+# DP: DWARF2 EH unwinding support for AMD x86-64 and x86 KFreeBSD.
+
+Index: b/src/libgcc/config.host
+===================================================================
+--- a/src/libgcc/config.host
++++ b/src/libgcc/config.host
+@@ -620,7 +620,12 @@ i[34567]86-*-linux*)
+ 	tm_file="${tm_file} i386/elf-lib.h"
+ 	md_unwind_header=i386/linux-unwind.h
+ 	;;
+-i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i[34567]86-*-gnu* | i[34567]86-*-kopensolaris*-gnu)
++i[34567]86-*-kfreebsd*-gnu)
++	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
++	tmake_file="${tmake_file} i386/t-crtpc i386/t-crtfm i386/t-crtstuff t-dfprules"
++	md_unwind_header=i386/freebsd-unwind.h
++	;;
++i[34567]86-*-knetbsd*-gnu | i[34567]86-*-gnu* | i[34567]86-*-kopensolaris*-gnu)
+ 	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
+ 	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
+ 	tm_file="${tm_file} i386/elf-lib.h"
+@@ -631,7 +636,12 @@ x86_64-*-linux*)
+ 	tm_file="${tm_file} i386/elf-lib.h"
+ 	md_unwind_header=i386/linux-unwind.h
+ 	;;
+-x86_64-*-kfreebsd*-gnu | x86_64-*-knetbsd*-gnu)
++x86_64-*-kfreebsd*-gnu)
++	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
++	tmake_file="${tmake_file} i386/t-crtpc i386/t-crtfm i386/t-crtstuff t-dfprules"
++	md_unwind_header=i386/freebsd-unwind.h
++	;;
++x86_64-*-knetbsd*-gnu)
+ 	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
+ 	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
+ 	tm_file="${tm_file} i386/elf-lib.h"
+Index: b/src/libgcc/config/i386/freebsd-unwind.h
+===================================================================
+--- a/src/libgcc/config/i386/freebsd-unwind.h
++++ b/src/libgcc/config/i386/freebsd-unwind.h
+@@ -26,6 +26,8 @@ see the files COPYING3 and COPYING.RUNTI
+ /* Do code reading to identify a signal frame, and set the frame
+    state data appropriately.  See unwind-dw2.c for the structs. */
+ 
++#ifndef inhibit_libc
++
+ #include <sys/types.h>
+ #include <signal.h>
+ #include <sys/ucontext.h>
+@@ -171,3 +173,5 @@ x86_freebsd_fallback_frame_state
+   return _URC_NO_REASON;
+ }
+ #endif /* ifdef __x86_64__  */
++
++#endif /* ifndef inhibit_libc */
--- gcc-6-6.3.0.orig/debian/patches/libasan-sparc.diff
+++ gcc-6-6.3.0/debian/patches/libasan-sparc.diff
@@ -0,0 +1,163 @@
+# DP: Re-apply sanitizer patch for sparc, dropped upstream
+
+# don't remove, this is regularly overwritten, see PR sanitizer/63958.
+
+libsanitizer/
+
+2014-10-14  David S. Miller  <davem@davemloft.net>
+
+	* sanitizer_common/sanitizer_platform_limits_linux.cc (time_t):
+	Define at __kernel_time_t, as needed for sparc.
+	(struct __old_kernel_stat): Don't check if __sparc__ is defined.
+	* libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+	(__sanitizer): Define struct___old_kernel_stat_sz,
+	struct_kernel_stat_sz, and struct_kernel_stat64_sz for sparc.
+	(__sanitizer_ipc_perm): Adjust for sparc targets.
+	(__sanitizer_shmid_ds): Likewsie.
+	(__sanitizer_sigaction): Likewsie.
+	(IOC_SIZE): Likewsie.
+
+Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	(revision 216223)
++++ a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	(revision 216224)
+@@ -72,6 +72,14 @@
+   const unsigned struct_kernel_stat_sz = 144;
+   #endif
+   const unsigned struct_kernel_stat64_sz = 104;
++#elif defined(__sparc__) && defined(__arch64__)
++  const unsigned struct___old_kernel_stat_sz = 0;
++  const unsigned struct_kernel_stat_sz = 104;
++  const unsigned struct_kernel_stat64_sz = 144;
++#elif defined(__sparc__) && !defined(__arch64__)
++  const unsigned struct___old_kernel_stat_sz = 0;
++  const unsigned struct_kernel_stat_sz = 64;
++  const unsigned struct_kernel_stat64_sz = 104;
+ #endif
+   struct __sanitizer_perf_event_attr {
+     unsigned type;
+@@ -94,7 +102,7 @@
+ 
+ #if defined(__powerpc64__)
+   const unsigned struct___old_kernel_stat_sz = 0;
+-#else
++#elif !defined(__sparc__)
+   const unsigned struct___old_kernel_stat_sz = 32;
+ #endif
+ 
+@@ -173,6 +181,18 @@
+     unsigned short __pad1;
+     unsigned long __unused1;
+     unsigned long __unused2;
++#elif defined(__sparc__)
++# if defined(__arch64__)
++    unsigned mode;
++    unsigned short __pad1;
++# else
++    unsigned short __pad1;
++    unsigned short mode;
++    unsigned short __pad2;
++# endif
++    unsigned short __seq;
++    unsigned long long __unused1;
++    unsigned long long __unused2;
+ #else
+     unsigned short mode;
+     unsigned short __pad1;
+@@ -190,6 +210,26 @@
+ 
+   struct __sanitizer_shmid_ds {
+     __sanitizer_ipc_perm shm_perm;
++  #if defined(__sparc__)
++  # if !defined(__arch64__)
++    u32 __pad1;
++  # endif
++    long shm_atime;
++  # if !defined(__arch64__)
++    u32 __pad2;
++  # endif
++    long shm_dtime;
++  # if !defined(__arch64__)
++    u32 __pad3;
++  # endif
++    long shm_ctime;
++    uptr shm_segsz;
++    int shm_cpid;
++    int shm_lpid;
++    unsigned long shm_nattch;
++    unsigned long __glibc_reserved1;
++    unsigned long __glibc_reserved2;
++  #else    
+   #ifndef __powerpc__
+     uptr shm_segsz;
+   #elif !defined(__powerpc64__)
+@@ -227,6 +267,7 @@
+     uptr __unused4;
+     uptr __unused5;
+   #endif
++#endif
+   };
+ #elif SANITIZER_FREEBSD
+   struct __sanitizer_ipc_perm {
+@@ -523,9 +564,13 @@
+ #else
+     __sanitizer_sigset_t sa_mask;
+ #ifndef __mips__
++#if defined(__sparc__)
++    unsigned long sa_flags;
++#else
+     int sa_flags;
+ #endif
+ #endif
++#endif
+ #if SANITIZER_LINUX
+     void (*sa_restorer)();
+ #endif
+@@ -745,7 +790,7 @@
+ 
+ #define IOC_NRBITS 8
+ #define IOC_TYPEBITS 8
+-#if defined(__powerpc__) || defined(__powerpc64__) || defined(__mips__)
++#if defined(__powerpc__) || defined(__powerpc64__) || defined(__mips__) || defined(__sparc__)
+ #define IOC_SIZEBITS 13
+ #define IOC_DIRBITS 3
+ #define IOC_NONE 1U
+@@ -775,7 +820,17 @@
+ #define IOC_DIR(nr) (((nr) >> IOC_DIRSHIFT) & IOC_DIRMASK)
+ #define IOC_TYPE(nr) (((nr) >> IOC_TYPESHIFT) & IOC_TYPEMASK)
+ #define IOC_NR(nr) (((nr) >> IOC_NRSHIFT) & IOC_NRMASK)
++
++#if defined(__sparc__)
++// In sparc the 14 bits SIZE field overlaps with the
++// least significant bit of DIR, so either IOC_READ or
++// IOC_WRITE shall be 1 in order to get a non-zero SIZE.
++# define IOC_SIZE(nr)                       \
++  ((((((nr) >> 29) & 0x7) & (4U|2U)) == 0)? \
++   0 : (((nr) >> 16) & 0x3fff))
++#else
+ #define IOC_SIZE(nr) (((nr) >> IOC_SIZESHIFT) & IOC_SIZEMASK)
++#endif
+ 
+   extern unsigned struct_arpreq_sz;
+   extern unsigned struct_ifreq_sz;
+Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc	(revision 216223)
++++ a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc	(revision 216224)
+@@ -36,6 +36,7 @@
+ #define uid_t __kernel_uid_t
+ #define gid_t __kernel_gid_t
+ #define off_t __kernel_off_t
++#define time_t __kernel_time_t
+ // This header seems to contain the definitions of _kernel_ stat* structs.
+ #include <asm/stat.h>
+ #undef ino_t
+@@ -60,7 +61,7 @@
+ }  // namespace __sanitizer
+ 
+ #if !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__aarch64__)\
+-                            && !defined(__mips__)
++                            && !defined(__mips__) && !defined(__sparc__)
+ COMPILER_CHECK(struct___old_kernel_stat_sz == sizeof(struct __old_kernel_stat));
+ #endif
+ 
--- gcc-6-6.3.0.orig/debian/patches/libcc1-compiler-name.diff
+++ gcc-6-6.3.0/debian/patches/libcc1-compiler-name.diff
@@ -0,0 +1,24 @@
+# DP: Don't add the configured prefix to libcc1's compiler name.
+
+--- a/src/libcc1/Makefile.am
++++ b/src/libcc1/Makefile.am
+@@ -49,7 +49,7 @@
+ # Put this in a header so we don't run sed for each compilation.  This
+ # is also simpler to debug as one can easily see the constant.
+ compiler-name.h: Makefile
+-	echo "#define COMPILER_NAME \"`echo gcc | sed '$(transform)'`\"" > $@
++	echo "#define COMPILER_NAME \"`echo gcc-6`\"" > $@
+ 
+ 
+ shared_source = callbacks.cc callbacks.hh connection.cc connection.hh \
+--- a/src/libcc1/Makefile.in
++++ b/src/libcc1/Makefile.in
+@@ -674,7 +674,7 @@
+ # Put this in a header so we don't run sed for each compilation.  This
+ # is also simpler to debug as one can easily see the constant.
+ compiler-name.h: Makefile
+-	echo "#define COMPILER_NAME \"`echo gcc | sed '$(transform)'`\"" > $@
++	echo "#define COMPILER_NAME \"`echo gcc-6`\"" > $@
+ 
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
--- gcc-6-6.3.0.orig/debian/patches/libcilkrts-targets.diff
+++ gcc-6-6.3.0/debian/patches/libcilkrts-targets.diff
@@ -0,0 +1,21 @@
+# DP: Disable libcilkrts on KFreeBSD and the Hurd. See #734973.
+
+Index: b/src/libcilkrts/configure.tgt
+===================================================================
+--- a/src/libcilkrts/configure.tgt
++++ b/src/libcilkrts/configure.tgt
+@@ -44,3 +44,14 @@ esac
+ 
+ # Disable libcilkrts on non POSIX hosted systems.
+ . ${srcdir}/../config/target-posix
++
++# Disable libcilkrts on KFreeBSD and the Hurd.
++if test x$enable_libcilkrts = x ; then
++    case "${target}" in
++    *-*-linux*)
++        ;;
++    *-*-gnu* | *-*-k*bsd*-gnu)
++        UNSUPPORTED=1
++        ;;
++    esac
++fi
--- gcc-6-6.3.0.orig/debian/patches/libffi-mips.diff
+++ gcc-6-6.3.0/debian/patches/libffi-mips.diff
@@ -0,0 +1,703 @@
+# DP: Backport Mips go closure support, taken from libffi issue #197.
+
+--- a/src/libffi/src/mips/ffi.c
++++ b/src/libffi/src/mips/ffi.c
+@@ -581,14 +581,15 @@ ffi_status ffi_prep_cif_machdep(ffi_cif *cif)
+ /* Low level routine for calling O32 functions */
+ extern int ffi_call_O32(void (*)(char *, extended_cif *, int, int), 
+ 			extended_cif *, unsigned, 
+-			unsigned, unsigned *, void (*)(void));
++			unsigned, unsigned *, void (*)(void), void *closure);
+ 
+ /* Low level routine for calling N32 functions */
+ extern int ffi_call_N32(void (*)(char *, extended_cif *, int, int), 
+ 			extended_cif *, unsigned, 
+-			unsigned, void *, void (*)(void));
++			unsigned, void *, void (*)(void), void *closure);
+ 
+-void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
++void ffi_call_int(ffi_cif *cif, void (*fn)(void), void *rvalue, 
++	      void **avalue, void *closure)
+ {
+   extended_cif ecif;
+ 
+@@ -610,7 +611,7 @@ void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
+     case FFI_O32:
+     case FFI_O32_SOFT_FLOAT:
+       ffi_call_O32(ffi_prep_args, &ecif, cif->bytes, 
+-		   cif->flags, ecif.rvalue, fn);
++		   cif->flags, ecif.rvalue, fn, closure);
+       break;
+ #endif
+ 
+@@ -642,7 +643,7 @@ void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
+ #endif
+ 	  }
+         ffi_call_N32(ffi_prep_args, &ecif, cif->bytes,
+-                     cif->flags, rvalue_copy, fn);
++                     cif->flags, rvalue_copy, fn, closure);
+         if (copy_rvalue)
+           memcpy(ecif.rvalue, rvalue_copy + copy_offset, cif->rtype->size);
+       }
+@@ -655,11 +656,27 @@ void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
+     }
+ }
+ 
++void
++ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
++{
++  ffi_call_int (cif, fn, rvalue, avalue, NULL);
++}
++
++void
++ffi_call_go (ffi_cif *cif, void (*fn)(void), void *rvalue,
++	     void **avalue, void *closure)
++{
++  ffi_call_int (cif, fn, rvalue, avalue, closure);
++}
++
++
+ #if FFI_CLOSURES
+ #if defined(FFI_MIPS_O32)
+ extern void ffi_closure_O32(void);
++extern void ffi_go_closure_O32(void);
+ #else
+ extern void ffi_closure_N32(void);
++extern void ffi_go_closure_N32(void);
+ #endif /* FFI_MIPS_O32 */
+ 
+ ffi_status
+@@ -762,17 +779,17 @@ ffi_prep_closure_loc (ffi_closure *closure,
+  * Based on the similar routine for sparc.
+  */
+ int
+-ffi_closure_mips_inner_O32 (ffi_closure *closure,
++ffi_closure_mips_inner_O32 (ffi_cif *cif,
++                            void (*fun)(ffi_cif*, void*, void**, void*),
++			    void *user_data,
+ 			    void *rvalue, ffi_arg *ar,
+ 			    double *fpr)
+ {
+-  ffi_cif *cif;
+   void **avaluep;
+   ffi_arg *avalue;
+   ffi_type **arg_types;
+   int i, avn, argn, seen_int;
+ 
+-  cif = closure->cif;
+   avalue = alloca (cif->nargs * sizeof (ffi_arg));
+   avaluep = alloca (cif->nargs * sizeof (ffi_arg));
+ 
+@@ -840,7 +857,7 @@ ffi_closure_mips_inner_O32 (ffi_closure *closure,
+     }
+ 
+   /* Invoke the closure. */
+-  (closure->fun) (cif, rvalue, avaluep, closure->user_data);
++  fun(cif, rvalue, avaluep, user_data);
+ 
+   if (cif->abi == FFI_O32_SOFT_FLOAT)
+     {
+@@ -916,11 +933,12 @@ copy_struct_N32(char *target, unsigned offset, ffi_abi abi, ffi_type *type,
+  *
+  */
+ int
+-ffi_closure_mips_inner_N32 (ffi_closure *closure,
++ffi_closure_mips_inner_N32 (ffi_cif *cif, 
++			    void (*fun)(ffi_cif*, void*, void**, void*),
++                            void *user_data,
+ 			    void *rvalue, ffi_arg *ar,
+ 			    ffi_arg *fpr)
+ {
+-  ffi_cif *cif;
+   void **avaluep;
+   ffi_arg *avalue;
+   ffi_type **arg_types;
+@@ -928,7 +946,6 @@ ffi_closure_mips_inner_N32 (ffi_closure *closure,
+   int soft_float;
+   ffi_arg *argp;
+ 
+-  cif = closure->cif;
+   soft_float = cif->abi == FFI_N64_SOFT_FLOAT
+     || cif->abi == FFI_N32_SOFT_FLOAT;
+   avalue = alloca (cif->nargs * sizeof (ffi_arg));
+@@ -1040,11 +1057,49 @@ ffi_closure_mips_inner_N32 (ffi_closure *closure,
+     }
+ 
+   /* Invoke the closure. */
+-  (closure->fun) (cif, rvalue, avaluep, closure->user_data);
++  fun (cif, rvalue, avaluep, user_data);
+ 
+   return cif->flags >> (FFI_FLAG_BITS * 8);
+ }
+ 
+ #endif /* FFI_MIPS_N32 */
+ 
++#if defined(FFI_MIPS_O32)
++extern void ffi_closure_O32(void);
++extern void ffi_go_closure_O32(void);
++#else
++extern void ffi_closure_N32(void);
++extern void ffi_go_closure_N32(void);
++#endif /* FFI_MIPS_O32 */
++
++ffi_status
++ffi_prep_go_closure (ffi_go_closure* closure, ffi_cif* cif,
++		     void (*fun)(ffi_cif*,void*,void**,void*))
++{
++  void * fn;
++
++#if defined(FFI_MIPS_O32)
++  if (cif->abi != FFI_O32 && cif->abi != FFI_O32_SOFT_FLOAT)
++    return FFI_BAD_ABI;
++  fn = ffi_go_closure_O32;
++#else
++#if _MIPS_SIM ==_ABIN32
++  if (cif->abi != FFI_N32
++      && cif->abi != FFI_N32_SOFT_FLOAT)
++    return FFI_BAD_ABI;
++#else
++  if (cif->abi != FFI_N64
++      && cif->abi != FFI_N64_SOFT_FLOAT)
++    return FFI_BAD_ABI;
++#endif
++  fn = ffi_go_closure_N32;
++#endif /* FFI_MIPS_O32 */
++
++  closure->tramp = (void *)fn;
++  closure->cif = cif;
++  closure->fun = fun;
++
++  return FFI_OK;
++}
++
+ #endif /* FFI_CLOSURES */
+--- a/src/libffi/src/mips/ffitarget.h
++++ b/src/libffi/src/mips/ffitarget.h
+@@ -231,12 +231,14 @@ typedef enum ffi_abi {
+ 
+ #if defined(FFI_MIPS_O32)
+ #define FFI_CLOSURES 1
++#define FFI_GO_CLOSURES 1
+ #define FFI_TRAMPOLINE_SIZE 20
+ #else
+ /* N32/N64. */
+ # define FFI_CLOSURES 1
++#define FFI_GO_CLOSURES 1
+ #if _MIPS_SIM==_ABI64
+-#define FFI_TRAMPOLINE_SIZE 52
++#define FFI_TRAMPOLINE_SIZE 56
+ #else
+ #define FFI_TRAMPOLINE_SIZE 20
+ #endif
+--- a/src/libffi/src/mips/n32.S
++++ b/src/libffi/src/mips/n32.S
+@@ -37,8 +37,12 @@
+ #define flags	 a3
+ #define raddr    a4
+ #define fn       a5
++#define closure  a6
+ 
+-#define SIZEOF_FRAME	( 8 * FFI_SIZEOF_ARG )
++/* Note: to keep stack 16 byte aligned we need even number slots 
++   used 9 slots here
++*/
++#define SIZEOF_FRAME	( 10 * FFI_SIZEOF_ARG )
+ 
+ #ifdef __GNUC__
+ 	.abicalls
+@@ -49,24 +53,25 @@
+ 	.globl	ffi_call_N32
+ 	.ent	ffi_call_N32
+ ffi_call_N32:	
+-.LFB3:
++.LFB0:
+ 	.frame	$fp, SIZEOF_FRAME, ra
+ 	.mask	0xc0000000,-FFI_SIZEOF_ARG
+ 	.fmask	0x00000000,0
+ 
+ 	# Prologue
+ 	SUBU	$sp, SIZEOF_FRAME			# Frame size
+-.LCFI0:
++.LCFI00:
+ 	REG_S	$fp, SIZEOF_FRAME - 2*FFI_SIZEOF_ARG($sp)	# Save frame pointer
+ 	REG_S	ra, SIZEOF_FRAME - 1*FFI_SIZEOF_ARG($sp)	# Save return address
+-.LCFI1:
++.LCFI01:
+ 	move	$fp, $sp
+-.LCFI3:
++.LCFI02:
+ 	move	t9, callback	# callback function pointer
+ 	REG_S	bytes, 2*FFI_SIZEOF_ARG($fp) # bytes
+ 	REG_S	flags, 3*FFI_SIZEOF_ARG($fp) # flags
+ 	REG_S	raddr, 4*FFI_SIZEOF_ARG($fp) # raddr
+ 	REG_S	fn,    5*FFI_SIZEOF_ARG($fp) # fn
++	REG_S	closure, 6*FFI_SIZEOF_ARG($fp) # closure
+ 
+ 	# Allocate at least 4 words in the argstack
+ 	move	v0, bytes
+@@ -198,6 +203,9 @@ callit:
+ 	# Load the function pointer
+ 	REG_L	t9, 5*FFI_SIZEOF_ARG($fp)
+ 
++	# install the static chain(t7=$15)
++	REG_L	t7, 6*FFI_SIZEOF_ARG($fp)
++
+ 	# If the return value pointer is NULL, assume no return value.
+ 	REG_L	t5, 4*FFI_SIZEOF_ARG($fp)
+ 	beqz	t5, noretval
+@@ -346,7 +354,7 @@ epilogue:
+ 	ADDU	$sp, SIZEOF_FRAME		      # Fix stack pointer
+ 	j	ra
+ 
+-.LFE3:
++.LFE0:
+ 	.end	ffi_call_N32
+ 
+ /* ffi_closure_N32. Expects address of the passed-in ffi_closure in t0
+@@ -406,6 +414,41 @@ epilogue:
+ #define GP_OFF2		(0  * FFI_SIZEOF_ARG)
+ 
+ 	.align	2
++	.globl	ffi_go_closure_N32
++	.ent	ffi_go_closure_N32
++ffi_go_closure_N32:
++.LFB1:
++	.frame	$sp, SIZEOF_FRAME2, ra
++	.mask	0x90000000,-(SIZEOF_FRAME2 - RA_OFF2)
++	.fmask	0x00000000,0
++	SUBU	$sp, SIZEOF_FRAME2
++.LCFI10:
++	.cpsetup t9, GP_OFF2, ffi_go_closure_N32
++	REG_S	ra, RA_OFF2($sp)	# Save return address
++.LCFI11:
++
++	REG_S	a0, A0_OFF2($sp)
++	REG_S	a1, A1_OFF2($sp)
++	REG_S	a2, A2_OFF2($sp)
++	REG_S	a3, A3_OFF2($sp)
++	REG_S	a4, A4_OFF2($sp)
++	REG_S	a5, A5_OFF2($sp)
++
++	# Call ffi_closure_mips_inner_N32 to do the real work.
++	LA	t9, ffi_closure_mips_inner_N32
++	REG_L	a0, 8($15)   # cif
++	REG_L	a1, 16($15) # fun
++	move	a2, t7                     # userdata=closure
++	ADDU	a3, $sp, V0_OFF2           # rvalue
++	ADDU	a4, $sp, A0_OFF2           # ar
++	ADDU	a5, $sp, F12_OFF2          # fpr
++
++	b	$do_closure
++
++.LFE1:	
++	.end	ffi_go_closure_N32
++
++	.align	2
+ 	.globl	ffi_closure_N32
+ 	.ent	ffi_closure_N32
+ ffi_closure_N32:
+@@ -414,18 +457,29 @@ ffi_closure_N32:
+ 	.mask	0x90000000,-(SIZEOF_FRAME2 - RA_OFF2)
+ 	.fmask	0x00000000,0
+ 	SUBU	$sp, SIZEOF_FRAME2
+-.LCFI5:
++.LCFI20:
+ 	.cpsetup t9, GP_OFF2, ffi_closure_N32
+ 	REG_S	ra, RA_OFF2($sp)	# Save return address
+-.LCFI6:
+-	# Store all possible argument registers. If there are more than
+-	# fit in registers, then they were stored on the stack.
++.LCFI21:
+ 	REG_S	a0, A0_OFF2($sp)
+ 	REG_S	a1, A1_OFF2($sp)
+ 	REG_S	a2, A2_OFF2($sp)
+ 	REG_S	a3, A3_OFF2($sp)
+ 	REG_S	a4, A4_OFF2($sp)
+ 	REG_S	a5, A5_OFF2($sp)
++
++	# Call ffi_closure_mips_inner_N32 to do the real work.
++	LA	t9, ffi_closure_mips_inner_N32
++	REG_L	a0, 56($12)   # cif
++	REG_L	a1, 64($12)   # fun
++	REG_L	a2, 72($12) # user_data
++	ADDU	a3, $sp, V0_OFF2
++	ADDU	a4, $sp, A0_OFF2
++	ADDU	a5, $sp, F12_OFF2
++
++$do_closure:
++	# Store all possible argument registers. If there are more than
++	# fit in registers, then they were stored on the stack.
+ 	REG_S	a6, A6_OFF2($sp)
+ 	REG_S	a7, A7_OFF2($sp)
+ 
+@@ -439,12 +493,6 @@ ffi_closure_N32:
+ 	s.d	$f18, F18_OFF2($sp)
+ 	s.d	$f19, F19_OFF2($sp)
+ 
+-	# Call ffi_closure_mips_inner_N32 to do the real work.
+-	LA	t9, ffi_closure_mips_inner_N32
+-	move	a0, $12	 # Pointer to the ffi_closure
+-	ADDU	a1, $sp, V0_OFF2
+-	ADDU	a2, $sp, A0_OFF2
+-	ADDU	a3, $sp, F12_OFF2
+ 	jalr	t9
+ 
+ 	# Return flags are in v0
+@@ -531,46 +579,66 @@ cls_epilogue:
+         .align  EH_FRAME_ALIGN
+ .LECIE1:
+ 
+-.LSFDE1:
+-        .4byte  .LEFDE1-.LASFDE1	# length.
+-.LASFDE1:
+-        .4byte  .LASFDE1-.Lframe1	# CIE_pointer.
+-        FDE_ADDR_BYTES  .LFB3		# initial_location.
+-        FDE_ADDR_BYTES  .LFE3-.LFB3	# address_range.
++.LSFDE0:
++        .4byte  .LEFDE0-.LASFDE0	# length.
++.LASFDE0:
++        .4byte  .LASFDE0-.Lframe1	# CIE_pointer.
++        FDE_ADDR_BYTES  .LFB0		# initial_location.
++        FDE_ADDR_BYTES  .LFE0-.LFB0	# address_range.
+         .byte   0x4			# DW_CFA_advance_loc4
+-        .4byte  .LCFI0-.LFB3		# to .LCFI0
++        .4byte  .LCFI00-.LFB0		# to .LCFI00
+         .byte   0xe			# DW_CFA_def_cfa_offset
+         .uleb128 SIZEOF_FRAME		# adjust stack.by SIZEOF_FRAME
+         .byte   0x4			# DW_CFA_advance_loc4
+-        .4byte  .LCFI1-.LCFI0		# to .LCFI1
++        .4byte  .LCFI01-.LCFI00		# to .LCFI01
+         .byte   0x9e			# DW_CFA_offset of $fp
+         .uleb128 2*FFI_SIZEOF_ARG/4	# 
+         .byte   0x9f			# DW_CFA_offset of ra
+         .uleb128 1*FFI_SIZEOF_ARG/4	# 
+         .byte   0x4			# DW_CFA_advance_loc4
+-        .4byte  .LCFI3-.LCFI1		# to .LCFI3
++        .4byte  .LCFI02-.LCFI01		# to .LCFI02
+         .byte   0xd			# DW_CFA_def_cfa_register
+         .uleb128 0x1e			# in $fp
+         .align  EH_FRAME_ALIGN
++.LEFDE0:
++
++.LSFDE1:
++	.4byte	.LEFDE1-.LASFDE1	# length
++.LASFDE1:
++	.4byte	.LASFDE1-.Lframe1	# CIE_pointer.
++	FDE_ADDR_BYTES	.LFB1		# initial_location.
++	FDE_ADDR_BYTES	.LFE1-.LFB1	# address_range.
++	.byte	0x4			# DW_CFA_advance_loc4
++	.4byte	.LCFI10-.LFB1		# to .LCFI10
++	.byte	0xe			# DW_CFA_def_cfa_offset
++	.uleb128 SIZEOF_FRAME2		# adjust stack.by SIZEOF_FRAME
++	.byte	0x4			# DW_CFA_advance_loc4
++	.4byte	.LCFI11-.LCFI10		# to .LCFI11
++	.byte	0x9c			# DW_CFA_offset of $gp ($28)
++	.uleb128 (SIZEOF_FRAME2 - GP_OFF2)/4
++	.byte	0x9f			# DW_CFA_offset of ra ($31)
++	.uleb128 (SIZEOF_FRAME2 - RA_OFF2)/4
++	.align	EH_FRAME_ALIGN
+ .LEFDE1:
+-.LSFDE3:
+-	.4byte	.LEFDE3-.LASFDE3	# length
+-.LASFDE3:
+-	.4byte	.LASFDE3-.Lframe1	# CIE_pointer.
++
++.LSFDE2:
++	.4byte	.LEFDE2-.LASFDE2	# length
++.LASFDE2:
++	.4byte	.LASFDE2-.Lframe1	# CIE_pointer.
+ 	FDE_ADDR_BYTES	.LFB2		# initial_location.
+ 	FDE_ADDR_BYTES	.LFE2-.LFB2	# address_range.
+ 	.byte	0x4			# DW_CFA_advance_loc4
+-	.4byte	.LCFI5-.LFB2		# to .LCFI5
++	.4byte	.LCFI20-.LFB2		# to .LCFI20
+ 	.byte	0xe			# DW_CFA_def_cfa_offset
+ 	.uleb128 SIZEOF_FRAME2		# adjust stack.by SIZEOF_FRAME
+ 	.byte	0x4			# DW_CFA_advance_loc4
+-	.4byte	.LCFI6-.LCFI5		# to .LCFI6
++	.4byte	.LCFI21-.LCFI20		# to .LCFI21
+ 	.byte	0x9c			# DW_CFA_offset of $gp ($28)
+ 	.uleb128 (SIZEOF_FRAME2 - GP_OFF2)/4
+ 	.byte	0x9f			# DW_CFA_offset of ra ($31)
+ 	.uleb128 (SIZEOF_FRAME2 - RA_OFF2)/4
+ 	.align	EH_FRAME_ALIGN
+-.LEFDE3:
++.LEFDE2:
+ #endif /* __GNUC__ */	
+ 	
+ #endif
+--- a/src/libffi/src/mips/o32.S
++++ b/src/libffi/src/mips/o32.S
+@@ -50,14 +50,14 @@ ffi_call_O32:
+ $LFB0:
+ 	# Prologue
+ 	SUBU	$sp, SIZEOF_FRAME	# Frame size
+-$LCFI0:
++$LCFI00:
+ 	REG_S	$fp, FP_OFF($sp)	# Save frame pointer
+-$LCFI1:
++$LCFI01:
+ 	REG_S	ra, RA_OFF($sp)		# Save return address
+-$LCFI2:
++$LCFI02:
+ 	move	$fp, $sp
+ 
+-$LCFI3:
++$LCFI03:
+ 	move	t9, callback		# callback function pointer
+ 	REG_S	flags, A3_OFF($fp)	# flags
+ 
+@@ -132,6 +132,9 @@ pass_f_d:
+ 	l.d	$f14, 2*FFI_SIZEOF_ARG($sp)	# passing double and float
+ 
+ call_it:	
++	# Load the static chain pointer
++	REG_L	t7, SIZEOF_FRAME + 6*FFI_SIZEOF_ARG($fp)
++
+ 	# Load the function pointer
+ 	REG_L	t9, SIZEOF_FRAME + 5*FFI_SIZEOF_ARG($fp)
+ 
+@@ -204,13 +207,15 @@ $LFE0:
+ 	-8 - f14 (le low, be high)
+ 	-9 - f12 (le high, be low)
+        -10 - f12 (le low, be high)
+-       -11 - Called function a3 save
+-       -12 - Called function a2 save
+-       -13 - Called function a1 save
+-       -14 - Called function a0 save, our sp and fp point here
++       -11 - Called function a5 save
++       -12 - Called function a4 save
++       -13 - Called function a3 save
++       -14 - Called function a2 save
++       -15 - Called function a1 save
++       -16 - Called function a0 save, our sp and fp point here
+ 	 */
+ 	
+-#define SIZEOF_FRAME2	(14 * FFI_SIZEOF_ARG)
++#define SIZEOF_FRAME2	(16 * FFI_SIZEOF_ARG)
+ #define A3_OFF2		(SIZEOF_FRAME2 + 3 * FFI_SIZEOF_ARG)
+ #define A2_OFF2		(SIZEOF_FRAME2 + 2 * FFI_SIZEOF_ARG)
+ #define A1_OFF2		(SIZEOF_FRAME2 + 1 * FFI_SIZEOF_ARG)
+@@ -225,13 +230,71 @@ $LFE0:
+ #define FA_1_0_OFF2	(SIZEOF_FRAME2 - 8 * FFI_SIZEOF_ARG)
+ #define FA_0_1_OFF2	(SIZEOF_FRAME2 - 9 * FFI_SIZEOF_ARG)
+ #define FA_0_0_OFF2	(SIZEOF_FRAME2 - 10 * FFI_SIZEOF_ARG)
++#define CALLED_A5_OFF2  (SIZEOF_FRAME2 - 11 * FFI_SIZEOF_ARG)
++#define CALLED_A4_OFF2  (SIZEOF_FRAME2 - 12 * FFI_SIZEOF_ARG)
+ 
+ 	.text
++
++	.align	2
++	.globl	ffi_go_closure_O32
++	.ent	ffi_go_closure_O32
++ffi_go_closure_O32:
++$LFB1:
++	# Prologue
++	.frame	$fp, SIZEOF_FRAME2, ra
++	.set	noreorder
++	.cpload	t9
++	.set	reorder
++	SUBU	$sp, SIZEOF_FRAME2
++	.cprestore GP_OFF2
++$LCFI10:
++
++	REG_S	$16, S0_OFF2($sp)	 # Save s0
++	REG_S	$fp, FP_OFF2($sp)	 # Save frame pointer
++	REG_S	ra, RA_OFF2($sp)	 # Save return address
++$LCFI11:
++
++	move	$fp, $sp
++$LCFI12:
++
++	REG_S	a0, A0_OFF2($fp)
++	REG_S	a1, A1_OFF2($fp)
++	REG_S	a2, A2_OFF2($fp)
++	REG_S	a3, A3_OFF2($fp)
++
++	# Load ABI enum to s0
++	REG_L	$16, 4($15)	# cif 
++	REG_L	$16, 0($16)	# abi is first member.
++
++	li	$13, 1		# FFI_O32
++	bne	$16, $13, 1f	# Skip fp save if FFI_O32_SOFT_FLOAT
++	
++	# Store all possible float/double registers.
++	s.d	$f12, FA_0_0_OFF2($fp)
++	s.d	$f14, FA_1_0_OFF2($fp)
++1:
++	# prepare arguments for ffi_closure_mips_inner_O32
++	REG_L	a0, 4($15)	 # cif 
++	REG_L	a1, 8($15)	 # fun
++	move	a2, $15		 # user_data = go closure
++	addu	a3, $fp, V0_OFF2 # rvalue
++
++	addu	t9, $fp, A0_OFF2 # ar
++	REG_S   t9, CALLED_A4_OFF2($fp)
++
++	addu	t9, $fp, FA_0_0_OFF2 #fpr
++	REG_S   t9, CALLED_A5_OFF2($fp)
++
++	b $do_closure
++
++$LFE1:
++	.end ffi_go_closure_O32
++
+ 	.align	2
+ 	.globl	ffi_closure_O32
+ 	.ent	ffi_closure_O32
+ ffi_closure_O32:
+-$LFB1:
++$LFB2:
+ 	# Prologue
+ 	.frame	$fp, SIZEOF_FRAME2, ra
+ 	.set	noreorder
+@@ -239,14 +302,14 @@ $LFB1:
+ 	.set	reorder
+ 	SUBU	$sp, SIZEOF_FRAME2
+ 	.cprestore GP_OFF2
+-$LCFI4:
++$LCFI20:
+ 	REG_S	$16, S0_OFF2($sp)	 # Save s0
+ 	REG_S	$fp, FP_OFF2($sp)	 # Save frame pointer
+ 	REG_S	ra, RA_OFF2($sp)	 # Save return address
+-$LCFI6:
++$LCFI21:
+ 	move	$fp, $sp
+ 
+-$LCFI7:
++$LCFI22:
+ 	# Store all possible argument registers. If there are more than
+ 	# four arguments, then they are stored above where we put a3.
+ 	REG_S	a0, A0_OFF2($fp)
+@@ -265,12 +328,21 @@ $LCFI7:
+ 	s.d	$f12, FA_0_0_OFF2($fp)
+ 	s.d	$f14, FA_1_0_OFF2($fp)
+ 1:	
+-	# Call ffi_closure_mips_inner_O32 to do the work.
++	# prepare arguments for ffi_closure_mips_inner_O32
++	REG_L	a0, 20($12)	 # cif pointer follows tramp.
++	REG_L	a1, 24($12)	 # fun
++	REG_L	a2, 28($12)	 # user_data
++	addu	a3, $fp, V0_OFF2 # rvalue
++
++	addu	t9, $fp, A0_OFF2 # ar
++	REG_S   t9, CALLED_A4_OFF2($fp)
++
++	addu	t9, $fp, FA_0_0_OFF2 #fpr
++	REG_S   t9, CALLED_A5_OFF2($fp)
++
++$do_closure:
+ 	la	t9, ffi_closure_mips_inner_O32
+-	move	a0, $12	 # Pointer to the ffi_closure
+-	addu	a1, $fp, V0_OFF2
+-	addu	a2, $fp, A0_OFF2
+-	addu	a3, $fp, FA_0_0_OFF2
++	# Call ffi_closure_mips_inner_O32 to do the work.
+ 	jalr	t9
+ 
+ 	# Load the return value into the appropriate register.
+@@ -300,7 +372,7 @@ closure_done:
+ 	REG_L	ra,  RA_OFF2($sp)	 # Restore return address
+ 	ADDU	$sp, SIZEOF_FRAME2
+ 	j	ra
+-$LFE1:
++$LFE2:
+ 	.end	ffi_closure_O32
+ 
+ /* DWARF-2 unwind info. */
+@@ -322,6 +394,7 @@ $LSCIE0:
+ 	.uleb128 0x0
+ 	.align	2
+ $LECIE0:
++
+ $LSFDE0:
+ 	.4byte	$LEFDE0-$LASFDE0	 # FDE Length
+ $LASFDE0:
+@@ -330,11 +403,11 @@ $LASFDE0:
+ 	.4byte	$LFE0-$LFB0	 # FDE address range
+ 	.uleb128 0x0	 # Augmentation size
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI0-$LFB0
++	.4byte	$LCFI00-$LFB0
+ 	.byte	0xe	 # DW_CFA_def_cfa_offset
+ 	.uleb128 0x18
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI2-$LCFI0
++	.4byte	$LCFI01-$LCFI00
+ 	.byte	0x11	 # DW_CFA_offset_extended_sf
+ 	.uleb128 0x1e	 # $fp
+ 	.sleb128 -2	 # SIZEOF_FRAME2 - 2*FFI_SIZEOF_ARG($sp)
+@@ -342,12 +415,13 @@ $LASFDE0:
+ 	.uleb128 0x1f	 # $ra
+ 	.sleb128 -1	 # SIZEOF_FRAME2 - 1*FFI_SIZEOF_ARG($sp)
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI3-$LCFI2
++	.4byte	$LCFI02-$LCFI01
+ 	.byte	0xc	 # DW_CFA_def_cfa
+ 	.uleb128 0x1e
+ 	.uleb128 0x18
+ 	.align	2
+ $LEFDE0:
++
+ $LSFDE1:
+ 	.4byte	$LEFDE1-$LASFDE1	 # FDE Length
+ $LASFDE1:
+@@ -356,11 +430,11 @@ $LASFDE1:
+ 	.4byte	$LFE1-$LFB1	 # FDE address range
+ 	.uleb128 0x0	 # Augmentation size
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI4-$LFB1
++	.4byte	$LCFI10-$LFB1
+ 	.byte	0xe	 # DW_CFA_def_cfa_offset
+-	.uleb128 0x38
++	.uleb128 SIZEOF_FRAME2
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI6-$LCFI4
++	.4byte	$LCFI11-$LCFI10
+ 	.byte	0x11	 # DW_CFA_offset_extended_sf
+ 	.uleb128 0x10	 # $16
+ 	.sleb128 -3	 # SIZEOF_FRAME2 - 3*FFI_SIZEOF_ARG($sp)
+@@ -371,11 +445,41 @@ $LASFDE1:
+ 	.uleb128 0x1f	 # $ra
+ 	.sleb128 -1	 # SIZEOF_FRAME2 - 1*FFI_SIZEOF_ARG($sp)
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI7-$LCFI6
++	.4byte	$LCFI12-$LCFI11
+ 	.byte	0xc	 # DW_CFA_def_cfa
+ 	.uleb128 0x1e
+-	.uleb128 0x38
++	.uleb128 SIZEOF_FRAME2
+ 	.align	2
+ $LEFDE1:
+ 
++$LSFDE2:
++	.4byte	$LEFDE2-$LASFDE2	 # FDE Length
++$LASFDE2:
++	.4byte	$LASFDE2-$Lframe0	 # FDE CIE offset
++	.4byte	$LFB2	 # FDE initial location
++	.4byte	$LFE2-$LFB2	 # FDE address range
++	.uleb128 0x0	 # Augmentation size
++	.byte	0x4	 # DW_CFA_advance_loc4
++	.4byte	$LCFI20-$LFB2
++	.byte	0xe	 # DW_CFA_def_cfa_offset
++	.uleb128 SIZEOF_FRAME2
++	.byte	0x4	 # DW_CFA_advance_loc4
++	.4byte	$LCFI21-$LCFI20
++	.byte	0x11	 # DW_CFA_offset_extended_sf
++	.uleb128 0x10	 # $16
++	.sleb128 -3	 # SIZEOF_FRAME2 - 3*FFI_SIZEOF_ARG($sp)
++	.byte	0x11	 # DW_CFA_offset_extended_sf
++	.uleb128 0x1e	 # $fp
++	.sleb128 -2	 # SIZEOF_FRAME2 - 2*FFI_SIZEOF_ARG($sp)
++	.byte	0x11	 # DW_CFA_offset_extended_sf
++	.uleb128 0x1f	 # $ra
++	.sleb128 -1	 # SIZEOF_FRAME2 - 1*FFI_SIZEOF_ARG($sp)
++	.byte	0x4	 # DW_CFA_advance_loc4
++	.4byte	$LCFI22-$LCFI21
++	.byte	0xc	 # DW_CFA_def_cfa
++	.uleb128 0x1e
++	.uleb128 SIZEOF_FRAME2
++	.align	2
++$LEFDE2:
++
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/libffi-pax.diff
+++ gcc-6-6.3.0/debian/patches/libffi-pax.diff
@@ -0,0 +1,161 @@
+From 757876336c183f5b20b6620d674cc9817fd0d280 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Stefan=20B=C3=BChler?= <buehler@cert.uni-stuttgart.de>
+Date: Wed, 7 Sep 2016 15:50:54 +0200
+Subject: [PATCH 2/2] always check for PaX MPROTECT on linux, make EMUTRAMP
+ experimental
+
+- ffi_prep_closure_loc doesn't necessarily generate trampolines recognized by
+  PaX EMUTRAMP handler; there is no way to check before, and it isn't working
+on x86-64 right now -> experimental
+- if MPROTECT is enabled use the same workaround as is used for SELinux (double
+  mmap())
+---
+ configure.ac   | 11 +++++++---
+ src/closures.c | 68 +++++++++++++++++++++++++++++++++++++++-------------------
+ 2 files changed, 54 insertions(+), 25 deletions(-)
+
+--- a/src/libffi/configure.ac
++++ b/src/libffi/configure.ac
+@@ -177,12 +177,17 @@
+     ;;
+ esac
+ 
+-# On PaX enable kernels that have MPROTECT enable we can't use PROT_EXEC.
++# On PaX enable kernels that have MPROTECT enable we can't use PROT_EXEC;
++# if EMUTRAMP is active too ffi could try mapping without PROT_EXEC,
++# but the kernel needs to recognize the trampoline generated by ffi.
++# Otherwise fallback to double mmap trick.
+ AC_ARG_ENABLE(pax_emutramp,
+-  [  --enable-pax_emutramp       enable pax emulated trampolines, for we can't use PROT_EXEC],
++  [  --enable-pax_emutramp       enable pax emulated trampolines (experimental)],
+   if test "$enable_pax_emutramp" = "yes"; then
++    AC_MSG_WARN([EMUTRAMP is experimental only.  Use --enable-pax_emutramp=experimental to enforce.])
++  elif test "$enable_pax_emutramp" = "experimental"; then
+     AC_DEFINE(FFI_MMAP_EXEC_EMUTRAMP_PAX, 1,
+-      [Define this if you want to enable pax emulated trampolines])
++      [Define this if you want to enable pax emulated trampolines (experimental)])
+   fi)
+ 
+ FFI_EXEC_TRAMPOLINE_TABLE=0
+--- a/src/libffi/src/closures.c
++++ b/src/libffi/src/closures.c
+@@ -53,14 +53,18 @@
+ # endif
+ #endif
+ 
+-#if FFI_MMAP_EXEC_WRIT && !defined FFI_MMAP_EXEC_SELINUX
+-# ifdef __linux__
++#if FFI_MMAP_EXEC_WRIT && defined __linux__
++# if !defined FFI_MMAP_EXEC_SELINUX
+ /* When defined to 1 check for SELinux and if SELinux is active,
+    don't attempt PROT_EXEC|PROT_WRITE mapping at all, as that
+    might cause audit messages.  */
+ #  define FFI_MMAP_EXEC_SELINUX 1
+-# endif
+-#endif
++# endif /* !defined FFI_MMAP_EXEC_SELINUX */
++# if !defined FFI_MMAP_PAX
++/* Also check for PaX MPROTECT */
++#  define FFI_MMAP_PAX 1
++# endif /* !defined FFI_MMAP_PAX */
++#endif /* FFI_MMAP_EXEC_WRIT && defined __linux__ */
+ 
+ #if FFI_CLOSURES
+ 
+@@ -172,14 +176,18 @@
+ 
+ #endif /* !FFI_MMAP_EXEC_SELINUX */
+ 
+-/* On PaX enable kernels that have MPROTECT enable we can't use PROT_EXEC. */
+-#ifdef FFI_MMAP_EXEC_EMUTRAMP_PAX
++/* On PaX enable kernels that have MPROTECT enabled we can't use PROT_EXEC. */
++#if defined FFI_MMAP_PAX
+ #include <stdlib.h>
+ 
+-static int emutramp_enabled = -1;
++enum {
++  PAX_MPROTECT = (1 << 0),
++  PAX_EMUTRAMP = (1 << 1),
++};
++static int cached_pax_flags = -1;
+ 
+ static int
+-emutramp_enabled_check (void)
++pax_flags_check (void)
+ {
+   char *buf = NULL;
+   size_t len = 0;
+@@ -193,9 +201,10 @@
+   while (getline (&buf, &len, f) != -1)
+     if (!strncmp (buf, "PaX:", 4))
+       {
+-        char emutramp;
+-        if (sscanf (buf, "%*s %*c%c", &emutramp) == 1)
+-          ret = (emutramp == 'E');
++        if (NULL != strchr (buf + 4, 'M'))
++          ret |= PAX_MPROTECT;
++        if (NULL != strchr (buf + 4, 'E'))
++          ret |= PAX_EMUTRAMP;
+         break;
+       }
+   free (buf);
+@@ -203,9 +212,13 @@
+   return ret;
+ }
+ 
+-#define is_emutramp_enabled() (emutramp_enabled >= 0 ? emutramp_enabled \
+-                               : (emutramp_enabled = emutramp_enabled_check ()))
+-#endif /* FFI_MMAP_EXEC_EMUTRAMP_PAX */
++#define get_pax_flags() (cached_pax_flags >= 0 ? cached_pax_flags \
++                               : (cached_pax_flags = pax_flags_check ()))
++#define has_pax_flags(flags) ((flags) == ((flags) & get_pax_flags ()))
++#define is_mprotect_enabled() (has_pax_flags (PAX_MPROTECT))
++#define is_emutramp_enabled() (has_pax_flags (PAX_EMUTRAMP))
++
++#endif /* defined FFI_MMAP_PAX */
+ 
+ #elif defined (__CYGWIN__) || defined(__INTERIX)
+ 
+@@ -216,9 +229,10 @@
+ 
+ #endif /* !defined(X86_WIN32) && !defined(X86_WIN64) */
+ 
+-#ifndef FFI_MMAP_EXEC_EMUTRAMP_PAX
+-#define is_emutramp_enabled() 0
+-#endif /* FFI_MMAP_EXEC_EMUTRAMP_PAX */
++#if !defined FFI_MMAP_PAX
++# define is_mprotect_enabled() 0
++# define is_emutramp_enabled() 0
++#endif /* !defined FFI_MMAP_PAX */
+ 
+ /* Declare all functions defined in dlmalloc.c as static.  */
+ static void *dlmalloc(size_t);
+@@ -525,13 +539,23 @@
+   printf ("mapping in %zi\n", length);
+ #endif
+ 
+-  if (execfd == -1 && is_emutramp_enabled ())
++  /* -1 != execfd hints that we already decided to use dlmmap_locked
++     last time.  */
++  if (execfd == -1 && is_mprotect_enabled ())
+     {
+-      ptr = mmap (start, length, prot & ~PROT_EXEC, flags, fd, offset);
+-      return ptr;
++#ifdef FFI_MMAP_EXEC_EMUTRAMP_PAX
++      if (is_emutramp_enabled ())
++        {
++          /* emutramp requires the kernel recognizing the trampoline pattern
++             generated by ffi_prep_closure_loc; there is no way to test
++             in advance whether this will work, so this is experimental.  */
++          ptr = mmap (start, length, prot & ~PROT_EXEC, flags, fd, offset);
++          return ptr;
++        }
++#endif
++      /* fallback to dlmmap_locked.  */
+     }
+-
+-  if (execfd == -1 && !is_selinux_enabled ())
++  else if (execfd == -1 && !is_selinux_enabled ())
+     {
+       ptr = mmap (start, length, prot | PROT_EXEC, flags, fd, offset);
+ 
--- gcc-6-6.3.0.orig/debian/patches/libffi-race-condition.diff
+++ gcc-6-6.3.0/debian/patches/libffi-race-condition.diff
@@ -0,0 +1,33 @@
+From 48d2e46528fb6e621d95a7fa194069fd136b712d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Stefan=20B=C3=BChler?= <buehler@cert.uni-stuttgart.de>
+Date: Wed, 7 Sep 2016 15:49:48 +0200
+Subject: [PATCH 1/2] dlmmap_locked always needs locking as it always modifies
+ execsize
+
+---
+ src/closures.c | 13 ++++---------
+ 1 file changed, 4 insertions(+), 9 deletions(-)
+
+--- a/src/libffi/src/closures.c
++++ b/src/libffi/src/closures.c
+@@ -568,16 +568,11 @@
+ 	 MREMAP_DUP and prot at this point.  */
+     }
+ 
+-  if (execsize == 0 || execfd == -1)
+-    {
+-      pthread_mutex_lock (&open_temp_exec_file_mutex);
+-      ptr = dlmmap_locked (start, length, prot, flags, offset);
+-      pthread_mutex_unlock (&open_temp_exec_file_mutex);
++  pthread_mutex_lock (&open_temp_exec_file_mutex);
++  ptr = dlmmap_locked (start, length, prot, flags, offset);
++  pthread_mutex_unlock (&open_temp_exec_file_mutex);
+ 
+-      return ptr;
+-    }
+-
+-  return dlmmap_locked (start, length, prot, flags, offset);
++  return ptr;
+ }
+ 
+ /* Release memory at the given address, as well as the corresponding
--- gcc-6-6.3.0.orig/debian/patches/libffi-ro-eh_frame_sect.diff
+++ gcc-6-6.3.0/debian/patches/libffi-ro-eh_frame_sect.diff
@@ -0,0 +1,15 @@
+# DP: PR libffi/47248, force a read only eh frame section.
+
+Index: b/src/libffi/configure.ac
+===================================================================
+--- a/src/libffi/configure.ac
++++ b/src/libffi/configure.ac
+@@ -275,6 +275,8 @@ if test "x$GCC" = "xyes"; then
+   		libffi_cv_hidden_visibility_attribute=yes
+   	    fi
+   	fi
++	# FIXME: see PR libffi/47248
++	libffi_cv_ro_eh_frame=yes
+   	rm -f conftest.*
+       ])
+   if test $libffi_cv_hidden_visibility_attribute = yes; then
--- gcc-6-6.3.0.orig/debian/patches/libgnatprj-cross-hack.diff
+++ gcc-6-6.3.0/debian/patches/libgnatprj-cross-hack.diff
@@ -0,0 +1,66 @@
+This is a gross hack to cross build libgnatprj without having the
+gmp.h header for the target architecture.  Are libgnatvsn and libgnatprj
+really target libraries, or host libraries? The odd thing is that
+the gnat cross build tools are not linked against these two libraries.
+
+Index: b/src/gcc/wide-int.h
+===================================================================
+--- a/src/gcc/wide-int.h
++++ b/src/gcc/wide-int.h
+@@ -3106,8 +3106,10 @@ namespace wi
+   wide_int from_buffer (const unsigned char *, unsigned int);
+ 
+ #ifndef GENERATOR_FILE
++#ifndef LIBGNATPRJ_CROSS_HACK
+   void to_mpz (const wide_int_ref &, mpz_t, signop);
+ #endif
++#endif
+ 
+   wide_int mask (unsigned int, bool, unsigned int);
+   wide_int shifted_mask (unsigned int, unsigned int, bool, unsigned int);
+Index: b/src/gcc/system.h
+===================================================================
+--- a/src/gcc/system.h
++++ b/src/gcc/system.h
+@@ -678,8 +678,10 @@ extern int vsnprintf (char *, size_t, co
+ 
+ /* Do not introduce a gmp.h dependency on the build system.  */
+ #ifndef GENERATOR_FILE
++#ifndef LIBGNATPRJ_CROSS_HACK
+ #include <gmp.h>
+ #endif
++#endif
+ 
+ /* Get libiberty declarations.  */
+ #include "libiberty.h"
+Index: b/src/libgnatprj/Makefile.in
+===================================================================
+--- a/src/libgnatprj/Makefile.in
++++ b/src/libgnatprj/Makefile.in
+@@ -37,7 +37,7 @@ TOOLS_TARGET_PAIRS := @TOOLS_TARGET_PAIR
+ LN_S := @LN_S@
+ 
+ ifneq (@build@,@host@)
+-   CFLAGS += -b @host@
++   override CFLAGS += -DLIBGNATPRJ_CROSS_HACK
+ endif
+ 
+ .PHONY: libgnatprj install
+Index: b/src/gcc/double-int.h
+===================================================================
+--- a/src/gcc/double-int.h
++++ b/src/gcc/double-int.h
+@@ -429,11 +429,13 @@ double_int::popcount () const
+ 
+ 
+ #ifndef GENERATOR_FILE
++#ifndef LIBGNATPRJ_CROSS_HACK
+ /* Conversion to and from GMP integer representations.  */
+ 
+ void mpz_set_double_int (mpz_t, double_int, bool);
+ double_int mpz_get_double_int (const_tree, mpz_t, bool);
+ #endif
++#endif
+ 
+ namespace wi
+ {
--- gcc-6-6.3.0.orig/debian/patches/libgnatprj-link.diff
+++ gcc-6-6.3.0/debian/patches/libgnatprj-link.diff
@@ -0,0 +1,21 @@
+# DP: Don't link libgnatprj using --no-allow-shlib-undefined on older releases.
+
+in precise:
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `_rtld_global@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `_dl_argv@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `_rtld_global_ro@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `__libc_enable_secure@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `__tls_get_addr@GLIBC_2.3'
+collect2: error: ld returned 1 exit status
+
+--- a/src/libgnatprj/Makefile.in
++++ b/src/libgnatprj/Makefile.in
+@@ -74,7 +74,7 @@
+ 
+ libgnatprj.so.$(LIB_VERSION): $(addprefix obj-shared/,$(OBJECTS))
+ 	: # Make libgnatprj.so
+-	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ -Wl,--no-allow-shlib-undefined \
++	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ \
+ 	   $^ $(addprefix ../libiberty/pic/,$(LIBIBERTY_OBJECTS)) \
+ 	   -L../gcc/ada/rts -lgnat-$(LIB_VERSION) \
+ 	   -L../libgnatvsn -lgnatvsn
--- gcc-6-6.3.0.orig/debian/patches/libgo-add-getrandom-mips-sparc.diff
+++ gcc-6-6.3.0/debian/patches/libgo-add-getrandom-mips-sparc.diff
@@ -0,0 +1,67 @@
+# DP: Backport r240457 from trunk
+
+internal/syscall/unix: add getrandom syscall for MIPS and SPARC
+
+Reviewed-on: https://go-review.googlesource.com/29678
+
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipso32.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_mipso32.go	(nonexistent)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipso32.go	(revision 240457)
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build mipso32
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 4353
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go	(nonexistent)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go	(revision 240457)
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build sparc sparc64
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 347
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_mips64x.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_mips64x.go	(revision 240456)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_mips64x.go	(revision 240457)
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build mips64 mips64le
++// +build mips64 mips64le mipsn64 mipso64
+ 
+ package unix
+ 
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipsn32.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_mipsn32.go	(nonexistent)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipsn32.go	(revision 240457)
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build mipsn32
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 6317
--- gcc-6-6.3.0.orig/debian/patches/libgo-elf-relocations-sparc64.diff
+++ gcc-6-6.3.0/debian/patches/libgo-elf-relocations-sparc64.diff
@@ -0,0 +1,106 @@
+# DP: Backport r241051 from trunk
+# DP: src/libgo/go/debug/elf/testdata/go-relocation-test-gcc620-sparc64.obj is
+# DP: encoded in debian/go-relocation-test-gcc620-sparc64.obj.uue and is
+# DP: decoded at patch time.
+
+debug/elf: add sparc64 relocations
+
+This is a backport of https://go-review.googlesource.com/30870.
+
+Reviewed-on: https://go-review.googlesource.com/30916
+
+Index: b/src/libgo/go/debug/elf/file_test.go
+===================================================================
+--- a/src/libgo/go/debug/elf/file_test.go
++++ b/src/libgo/go/debug/elf/file_test.go
+@@ -473,6 +473,25 @@ var relocationTests = []relocationTest{
+ 		},
+ 	},
+ 	{
++		"testdata/go-relocation-test-gcc620-sparc64.obj",
++		[]relocationTestEntry{
++			{0, &dwarf.Entry{
++				Offset:   0xb,
++				Tag:      dwarf.TagCompileUnit,
++				Children: true,
++				Field: []dwarf.Field{
++					{Attr: dwarf.AttrProducer, Val: "GNU C11 6.2.0 20160914 -mcpu=v9 -g -fstack-protector-strong", Class: dwarf.ClassString},
++					{Attr: dwarf.AttrLanguage, Val: int64(12), Class: dwarf.ClassConstant},
++					{Attr: dwarf.AttrName, Val: "hello.c", Class: dwarf.ClassString},
++					{Attr: dwarf.AttrCompDir, Val: "/tmp", Class: dwarf.ClassString},
++					{Attr: dwarf.AttrLowpc, Val: uint64(0x0), Class: dwarf.ClassAddress},
++					{Attr: dwarf.AttrHighpc, Val: int64(0x2c), Class: dwarf.ClassConstant},
++					{Attr: dwarf.AttrStmtList, Val: int64(0), Class: dwarf.ClassLinePtr},
++				},
++			}},
++		},
++	},
++	{
+ 		"testdata/go-relocation-test-gcc493-mips64le.obj",
+ 		[]relocationTestEntry{
+ 			{0, &dwarf.Entry{
+Index: b/src/libgo/go/debug/elf/file.go
+===================================================================
+--- a/src/libgo/go/debug/elf/file.go
++++ b/src/libgo/go/debug/elf/file.go
+@@ -598,6 +598,8 @@ func (f *File) applyRelocations(dst []by
+ 		return f.applyRelocationsMIPS64(dst, rels)
+ 	case f.Class == ELFCLASS64 && f.Machine == EM_S390:
+ 		return f.applyRelocationsS390x(dst, rels)
++	case f.Class == ELFCLASS64 && f.Machine == EM_SPARCV9:
++		return f.applyRelocationsSPARC64(dst, rels)
+ 	default:
+ 		return errors.New("applyRelocations: not implemented")
+ 	}
+@@ -951,6 +953,51 @@ func (f *File) applyRelocationsS390x(dst
+ 		}
+ 	}
+ 
++	return nil
++}
++
++func (f *File) applyRelocationsSPARC64(dst []byte, rels []byte) error {
++	// 24 is the size of Rela64.
++	if len(rels)%24 != 0 {
++		return errors.New("length of relocation section is not a multiple of 24")
++	}
++
++	symbols, _, err := f.getSymbols(SHT_SYMTAB)
++	if err != nil {
++		return err
++	}
++
++	b := bytes.NewReader(rels)
++	var rela Rela64
++
++	for b.Len() > 0 {
++		binary.Read(b, f.ByteOrder, &rela)
++		symNo := rela.Info >> 32
++		t := R_SPARC(rela.Info & 0xffff)
++
++		if symNo == 0 || symNo > uint64(len(symbols)) {
++			continue
++		}
++		sym := &symbols[symNo-1]
++		if SymType(sym.Info&0xf) != STT_SECTION {
++			// We don't handle non-section relocations for now.
++			continue
++		}
++
++		switch t {
++		case R_SPARC_64, R_SPARC_UA64:
++			if rela.Off+8 >= uint64(len(dst)) || rela.Addend < 0 {
++				continue
++			}
++			f.ByteOrder.PutUint64(dst[rela.Off:rela.Off+8], uint64(rela.Addend))
++		case R_SPARC_32, R_SPARC_UA32:
++			if rela.Off+4 >= uint64(len(dst)) || rela.Addend < 0 {
++				continue
++			}
++			f.ByteOrder.PutUint32(dst[rela.Off:rela.Off+4], uint32(rela.Addend))
++		}
++	}
++
+ 	return nil
+ }
+ 
--- gcc-6-6.3.0.orig/debian/patches/libgo-fix-getrandom-clone-sparc64.diff
+++ gcc-6-6.3.0/debian/patches/libgo-fix-getrandom-clone-sparc64.diff
@@ -0,0 +1,343 @@
+# DP: Backport r241072 from trunk
+
+syscall, internal/syscall/unix: Fix getrandom, clone on sparc64
+
+Since sparc is a valid architecture, the name of
+getrandom_linux_sparc.go means that it will be ignored on sparc64,
+even though it's whitelisted with a +build line.
+
+On SPARC, clone has a unique return value convention which requires
+some inline assembly to convert it to the normal convention.
+
+Reviewed-on: https://go-review.googlesource.com/30873
+
+Index: b/src/libgo/mksysinfo.sh
+===================================================================
+--- a/src/libgo/mksysinfo.sh
++++ b/src/libgo/mksysinfo.sh
+@@ -603,8 +603,10 @@ fi
+ sizeof_long=`grep '^const ___SIZEOF_LONG__ = ' gen-sysinfo.go | sed -e 's/.*= //'`
+ if test "$sizeof_long" = "4"; then
+   echo "type _C_long int32" >> ${OUT}
++  echo "type _C_ulong uint32" >> ${OUT}
+ elif test "$sizeof_long" = "8"; then
+   echo "type _C_long int64" >> ${OUT}
++  echo "type _C_ulong uint64" >> ${OUT}
+ else
+   echo 1>&2 "mksysinfo.sh: could not determine size of long (got $sizeof_long)"
+   exit 1
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
+@@ -1,11 +0,0 @@
+-// Copyright 2016 The Go Authors. All rights reserved.
+-// Use of this source code is governed by a BSD-style
+-// license that can be found in the LICENSE file.
+-
+-// +build sparc sparc64
+-
+-package unix
+-
+-// Linux getrandom system call number.
+-// See GetRandom in getrandom_linux.go.
+-const randomTrap uintptr = 347
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparcx.go
+===================================================================
+--- /dev/null
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparcx.go
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build sparc sparc64
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 347
+Index: b/src/libgo/go/syscall/clone_linux.c
+===================================================================
+--- /dev/null
++++ b/src/libgo/go/syscall/clone_linux.c
+@@ -0,0 +1,100 @@
++/* clone_linux.c -- consistent wrapper around Linux clone syscall
++
++   Copyright 2016 The Go Authors. All rights reserved.
++   Use of this source code is governed by a BSD-style
++   license that can be found in the LICENSE file.  */
++
++#include <errno.h>
++#include <asm/ptrace.h>
++#include <sys/syscall.h>
++
++#include "runtime.h"
++
++long rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs) __asm__ (GOSYM_PREFIX "syscall.rawClone");
++
++long
++rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs)
++{
++#if defined(__arc__) || defined(__aarch64__) || defined(__arm__) || defined(__mips__) || defined(__hppa__) || defined(__powerpc__) || defined(__score__) || defined(__i386__) || defined(__xtensa__)
++  // CLONE_BACKWARDS
++  return syscall(__NR_clone, flags, child_stack, ptid, regs, ctid);
++#elif defined(__s390__) || defined(__cris__)
++  // CLONE_BACKWARDS2
++  return syscall(__NR_clone, child_stack, flags, ptid, ctid, regs);
++#elif defined(__microblaze__)
++  // CLONE_BACKWARDS3
++  return syscall(__NR_clone, flags, child_stack, 0, ptid, ctid, regs);
++#elif defined(__sparc__)
++
++  /* SPARC has a unique return value convention:
++
++     Parent -->  %o0 == child's  pid, %o1 == 0
++     Child  -->  %o0 == parent's pid, %o1 == 1
++
++     Translate this to look like a normal clone.  */
++
++# if defined(__arch64__)
++
++#  define SYSCALL_STRING						\
++	"ta	0x6d;"							\
++	"bcc,pt	%%xcc, 1f;"						\
++	" mov	0, %%g1;"						\
++	"sub	%%g0, %%o0, %%o0;"					\
++	"mov	1, %%g1;"						\
++	"1:"
++
++#  define SYSCALL_CLOBBERS						\
++	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",			\
++	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
++	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",		\
++	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",		\
++	"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",		\
++	"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",		\
++	"cc", "memory"
++
++# else /* __arch64__ */
++
++#  define SYSCALL_STRING						\
++	"ta	0x10;"							\
++	"bcc	1f;"							\
++	" mov	0, %%g1;"						\
++	"sub	%%g0, %%o0, %%o0;"					\
++	"mov	1, %%g1;"						\
++	"1:"
++
++#  define SYSCALL_CLOBBERS						\
++	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",			\
++	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
++	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",		\
++	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",		\
++	"cc", "memory"
++
++# endif /* __arch64__ */
++
++  register long o0 __asm__ ("o0") = (long)flags;
++  register long o1 __asm__ ("o1") = (long)child_stack;
++  register long o2 __asm__ ("o2") = (long)ptid;
++  register long o3 __asm__ ("o3") = (long)ctid;
++  register long o4 __asm__ ("o4") = (long)regs;
++  register long g1 __asm__ ("g1") = __NR_clone;
++
++  __asm __volatile (SYSCALL_STRING :
++		    "=r" (g1), "=r" (o0), "=r" (o1) :
++		    "0" (g1), "1" (o0), "2" (o1),
++		    "r" (o2), "r" (o3), "r" (o4) :
++		    SYSCALL_CLOBBERS);
++
++  if (__builtin_expect(g1 != 0, 0))
++    {
++      errno = -o0;
++      o0 = -1L;
++    }
++  else
++    o0 &= (o1 - 1);
++
++  return o0;
++
++#else
++  return syscall(__NR_clone, flags, child_stack, ptid, ctid, regs);
++#endif
++}
+Index: b/src/libgo/go/syscall/exec_linux.go
+===================================================================
+--- a/src/libgo/go/syscall/exec_linux.go
++++ b/src/libgo/go/syscall/exec_linux.go
+@@ -7,7 +7,6 @@
+ package syscall
+ 
+ import (
+-	"runtime"
+ 	"unsafe"
+ )
+ 
+@@ -48,6 +47,9 @@ type SysProcAttr struct {
+ func runtime_BeforeFork()
+ func runtime_AfterFork()
+ 
++// Implemented in clone_linux.c
++func rawClone(flags _C_ulong, child_stack *byte, ptid *Pid_t, ctid *Pid_t, regs unsafe.Pointer) _C_long
++
+ // Fork, dup fd onto 0..len(fd), and exec(argv0, argvv, envv) in child.
+ // If a dup or exec fails, write the errno error to pipe.
+ // (Pipe is close-on-exec so if exec succeeds, it will be closed.)
+@@ -63,6 +65,7 @@ func forkAndExecInChild(argv0 *byte, arg
+ 	// declarations require heap allocation (e.g., err1).
+ 	var (
+ 		r1     uintptr
++		r2     _C_long
+ 		err1   Errno
+ 		err2   Errno
+ 		nextfd int
+@@ -97,20 +100,16 @@ func forkAndExecInChild(argv0 *byte, arg
+ 	// About to call fork.
+ 	// No more allocation or calls of non-assembly functions.
+ 	runtime_BeforeFork()
+-	if runtime.GOARCH == "s390x" || runtime.GOARCH == "s390" {
+-		r1, _, err1 = RawSyscall6(SYS_CLONE, 0, uintptr(SIGCHLD)|sys.Cloneflags, 0, 0, 0, 0)
+-	} else {
+-		r1, _, err1 = RawSyscall6(SYS_CLONE, uintptr(SIGCHLD)|sys.Cloneflags, 0, 0, 0, 0, 0)
+-	}
+-	if err1 != 0 {
++	r2 = rawClone(_C_ulong(uintptr(SIGCHLD)|sys.Cloneflags), nil, nil, nil, unsafe.Pointer(nil))
++	if r2 < 0 {
+ 		runtime_AfterFork()
+-		return 0, err1
++		return 0, GetErrno()
+ 	}
+ 
+-	if r1 != 0 {
++	if r2 != 0 {
+ 		// parent; return PID
+ 		runtime_AfterFork()
+-		pid = int(r1)
++		pid = int(r2)
+ 
+ 		if sys.UidMappings != nil || sys.GidMappings != nil {
+ 			Close(p[0])
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -2145,6 +2145,12 @@ else
+ os_lib_inotify_lo =
+ endif
+ 
++if LIBGO_IS_LINUX
++syscall_lib_clone_lo = syscall/clone_linux.lo
++else
++syscall_lib_clone_lo =
++endif
++
+ libgo_go_objs = \
+ 	bufio.lo \
+ 	bytes.lo \
+@@ -2175,6 +2181,7 @@ libgo_go_objs = \
+ 	strings/index.lo \
+ 	sync.lo \
+ 	syscall.lo \
++	$(syscall_lib_clone_lo) \
+ 	syscall/errno.lo \
+ 	syscall/signame.lo \
+ 	syscall/wait.lo \
+@@ -3820,6 +3827,9 @@ syscall.lo.dep: $(go_syscall_files)
+ 	$(BUILDDEPS)
+ syscall.lo: $(go_syscall_files)
+ 	$(BUILDPACKAGE)
++syscall/clone_linux.lo: go/syscall/clone_linux.c
++	@$(MKDIR_P) syscall
++	$(LTCOMPILE) -c -o $@ $<
+ syscall/errno.lo: go/syscall/errno.c
+ 	@$(MKDIR_P) syscall
+ 	$(LTCOMPILE) -c -o $@ $<
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -173,15 +173,16 @@ am__objects_3 = $(am__objects_2)
+ am_libnetgo_a_OBJECTS = $(am__objects_3)
+ libnetgo_a_OBJECTS = $(am_libnetgo_a_OBJECTS)
+ LTLIBRARIES = $(toolexeclib_LTLIBRARIES)
+-am__DEPENDENCIES_1 =
+-am__DEPENDENCIES_2 = bufio.lo bytes.lo bytes/index.lo crypto.lo \
++@LIBGO_IS_LINUX_TRUE@am__DEPENDENCIES_1 = syscall/clone_linux.lo
++am__DEPENDENCIES_2 =
++am__DEPENDENCIES_3 = bufio.lo bytes.lo bytes/index.lo crypto.lo \
+ 	encoding.lo errors.lo expvar.lo flag.lo fmt.lo hash.lo html.lo \
+ 	image.lo io.lo log.lo math.lo mime.lo net.lo os.lo path.lo \
+ 	reflect-go.lo reflect/makefunc_ffi_c.lo regexp.lo \
+ 	runtime-go.lo sort.lo strconv.lo strings.lo strings/index.lo \
+-	sync.lo syscall.lo syscall/errno.lo syscall/signame.lo \
+-	syscall/wait.lo testing.lo time-go.lo unicode.lo \
+-	archive/tar.lo archive/zip.lo compress/bzip2.lo \
++	sync.lo syscall.lo $(am__DEPENDENCIES_1) syscall/errno.lo \
++	syscall/signame.lo syscall/wait.lo testing.lo time-go.lo \
++	unicode.lo archive/tar.lo archive/zip.lo compress/bzip2.lo \
+ 	compress/flate.lo compress/gzip.lo compress/lzw.lo \
+ 	compress/zlib.lo container/heap.lo container/list.lo \
+ 	container/ring.lo crypto/aes.lo crypto/cipher.lo crypto/des.lo \
+@@ -213,18 +214,18 @@ am__DEPENDENCIES_2 = bufio.lo bytes.lo b
+ 	math/rand.lo mime/multipart.lo mime/quotedprintable.lo \
+ 	net/http.lo net/internal/socktest.lo net/mail.lo net/rpc.lo \
+ 	net/smtp.lo net/textproto.lo net/url.lo old/regexp.lo \
+-	old/template.lo os/exec.lo $(am__DEPENDENCIES_1) os/signal.lo \
++	old/template.lo os/exec.lo $(am__DEPENDENCIES_2) os/signal.lo \
+ 	os/user.lo path/filepath.lo regexp/syntax.lo \
+ 	net/rpc/jsonrpc.lo runtime/debug.lo runtime/pprof.lo \
+ 	sync/atomic.lo sync/atomic_c.lo text/scanner.lo \
+ 	text/tabwriter.lo text/template.lo text/template/parse.lo \
+ 	testing/iotest.lo testing/quick.lo unicode/utf16.lo \
+ 	unicode/utf8.lo
+-am__DEPENDENCIES_3 = $(am__DEPENDENCIES_2) \
+-	../libbacktrace/libbacktrace.la $(am__DEPENDENCIES_1) \
+-	$(am__DEPENDENCIES_1) $(am__DEPENDENCIES_1) \
+-	$(am__DEPENDENCIES_1) $(am__DEPENDENCIES_1)
+-libgo_llgo_la_DEPENDENCIES = $(am__DEPENDENCIES_3)
++am__DEPENDENCIES_4 = $(am__DEPENDENCIES_3) \
++	../libbacktrace/libbacktrace.la $(am__DEPENDENCIES_2) \
++	$(am__DEPENDENCIES_2) $(am__DEPENDENCIES_2) \
++	$(am__DEPENDENCIES_2) $(am__DEPENDENCIES_2)
++libgo_llgo_la_DEPENDENCIES = $(am__DEPENDENCIES_4)
+ @LIBGO_IS_LINUX_FALSE@am__objects_4 = lock_sema.lo thread-sema.lo
+ @LIBGO_IS_LINUX_TRUE@am__objects_4 = lock_futex.lo thread-linux.lo
+ @HAVE_SYS_MMAN_H_FALSE@am__objects_5 = mem_posix_memalign.lo
+@@ -276,7 +277,7 @@ libgo_llgo_la_LINK = $(LIBTOOL) --tag=CC
+ 	$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
+ 	$(libgo_llgo_la_LDFLAGS) $(LDFLAGS) -o $@
+ @GOC_IS_LLGO_TRUE@am_libgo_llgo_la_rpath = -rpath $(toolexeclibdir)
+-libgo_la_DEPENDENCIES = $(am__DEPENDENCIES_3)
++libgo_la_DEPENDENCIES = $(am__DEPENDENCIES_4)
+ am_libgo_la_OBJECTS = $(am__objects_9)
+ libgo_la_OBJECTS = $(am_libgo_la_OBJECTS)
+ libgo_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
+@@ -2156,6 +2157,8 @@ go_syscall_test_files = \
+ 
+ # os_lib_inotify_lo = os/inotify.lo
+ @LIBGO_IS_LINUX_TRUE@os_lib_inotify_lo = 
++@LIBGO_IS_LINUX_FALSE@syscall_lib_clone_lo = 
++@LIBGO_IS_LINUX_TRUE@syscall_lib_clone_lo = syscall/clone_linux.lo
+ libgo_go_objs = \
+ 	bufio.lo \
+ 	bytes.lo \
+@@ -2186,6 +2189,7 @@ libgo_go_objs = \
+ 	strings/index.lo \
+ 	sync.lo \
+ 	syscall.lo \
++	$(syscall_lib_clone_lo) \
+ 	syscall/errno.lo \
+ 	syscall/signame.lo \
+ 	syscall/wait.lo \
+@@ -6197,6 +6201,9 @@ syscall.lo.dep: $(go_syscall_files)
+ 	$(BUILDDEPS)
+ syscall.lo: $(go_syscall_files)
+ 	$(BUILDPACKAGE)
++syscall/clone_linux.lo: go/syscall/clone_linux.c
++	@$(MKDIR_P) syscall
++	$(LTCOMPILE) -c -o $@ $<
+ syscall/errno.lo: go/syscall/errno.c
+ 	@$(MKDIR_P) syscall
+ 	$(LTCOMPILE) -c -o $@ $<
--- gcc-6-6.3.0.orig/debian/patches/libgo-rawClone-no-pt_regs.diff
+++ gcc-6-6.3.0/debian/patches/libgo-rawClone-no-pt_regs.diff
@@ -0,0 +1,33 @@
+# DP: Backport r241084 from trunk
+
+syscall: don't use pt_regs in clone_linux.c
+
+It's unnecessary and it reportedly breaks the build on arm64 GNU/Linux.
+
+Reviewed-on: https://go-review.googlesource.com/30978
+
+Index: b/src/libgo/go/syscall/clone_linux.c
+===================================================================
+--- a/src/libgo/go/syscall/clone_linux.c	(revision 241083)
++++ b/src/libgo/go/syscall/clone_linux.c	(revision 241084)
+@@ -5,18 +5,17 @@
+    license that can be found in the LICENSE file.  */
+ 
+ #include <errno.h>
+-#include <asm/ptrace.h>
+ #include <sys/syscall.h>
+ 
+ #include "runtime.h"
+ 
+ long rawClone (unsigned long flags, void *child_stack, void *ptid,
+-	       void *ctid, struct pt_regs *regs)
++	       void *ctid, void *regs)
+   __asm__ (GOSYM_PREFIX "syscall.rawClone")
+   __attribute__ ((no_split_stack));
+ 
+ long
+-rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs)
++rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, void *regs)
+ {
+ #if defined(__arc__) || defined(__aarch64__) || defined(__arm__) || defined(__mips__) || defined(__hppa__) || defined(__powerpc__) || defined(__score__) || defined(__i386__) || defined(__xtensa__)
+   // CLONE_BACKWARDS
--- gcc-6-6.3.0.orig/debian/patches/libgo-rawClone-no_split_stack.diff
+++ gcc-6-6.3.0/debian/patches/libgo-rawClone-no_split_stack.diff
@@ -0,0 +1,22 @@
+# DP: Backport r241171 from trunk
+
+syscall: mark rawClone as no_split_stack
+
+Reviewed-on: https://go-review.googlesource.com/30955
+
+Index: b/src/libgo/go/syscall/clone_linux.c
+===================================================================
+--- a/src/libgo/go/syscall/clone_linux.c	(revision 241071)
++++ b/src/libgo/go/syscall/clone_linux.c	(revision 241072)
+@@ -10,7 +10,10 @@
+ 
+ #include "runtime.h"
+ 
+-long rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs) __asm__ (GOSYM_PREFIX "syscall.rawClone");
++long rawClone (unsigned long flags, void *child_stack, void *ptid,
++	       void *ctid, struct pt_regs *regs)
++  __asm__ (GOSYM_PREFIX "syscall.rawClone")
++  __attribute__ ((no_split_stack));
+ 
+ long
+ rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs)
--- gcc-6-6.3.0.orig/debian/patches/libgo-revert-timeout-exp.diff
+++ gcc-6-6.3.0/debian/patches/libgo-revert-timeout-exp.diff
@@ -0,0 +1,12 @@
+Index: b/src/libgo/testsuite/lib/libgo.exp
+===================================================================
+--- a/src/libgo/testsuite/lib/libgo.exp
++++ b/src/libgo/testsuite/lib/libgo.exp
+@@ -46,7 +46,6 @@ load_gcc_lib wrapper.exp
+ load_gcc_lib target-supports.exp
+ load_gcc_lib target-utils.exp
+ load_gcc_lib gcc-defs.exp
+-load_gcc_lib timeout.exp
+ load_gcc_lib go.exp
+ 
+ proc libgo_init { args } {
--- gcc-6-6.3.0.orig/debian/patches/libgo-setcontext-config.diff
+++ gcc-6-6.3.0/debian/patches/libgo-setcontext-config.diff
@@ -0,0 +1,21 @@
+# DP: libgo: Overwrite the setcontext_clobbers_tls check on mips*
+
+Index: b/src/libgo/configure.ac
+===================================================================
+--- a/src/libgo/configure.ac
++++ b/src/libgo/configure.ac
+@@ -785,6 +785,14 @@ main ()
+ CFLAGS="$CFLAGS_hold"
+ LIBS="$LIBS_hold"
+ ])
++dnl overwrite for the mips* 64bit multilibs, fails on some buildds
++if test "$libgo_cv_lib_setcontext_clobbers_tls" = "yes"; then
++  case "$target" in
++  mips*-linux-*)
++    AC_MSG_WARN([FIXME: overwrite setcontext_clobbers_tls for $target:$ptr_type_size])
++    libgo_cv_lib_setcontext_clobbers_tls=no ;;
++  esac
++fi
+ if test "$libgo_cv_lib_setcontext_clobbers_tls" = "yes"; then
+   AC_DEFINE(SETCONTEXT_CLOBBERS_TLS, 1,
+ 	    [Define if setcontext clobbers TLS variables])
--- gcc-6-6.3.0.orig/debian/patches/libgo-testsuite.diff
+++ gcc-6-6.3.0/debian/patches/libgo-testsuite.diff
@@ -0,0 +1,52 @@
+# DP: Only run the libgo testsuite for flags configured in RUNTESTFLAGS
+
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -2387,6 +2387,12 @@ CHECK = \
+ 	export LD_LIBRARY_PATH; \
+ 	$(MKDIR_P) $(@D); \
+ 	rm -f $@-testsum $@-testlog; \
++	run_check=yes; \
++	MULTILIBDIR="$(MULTILIBDIR)"; \
++	case "$$MULTILIBDIR" in /64|/x32) \
++	  echo "$$RUNTESTFLAGS" | grep -q "$${MULTILIBDIR\#/*}" || run_check=; \
++	esac; \
++	if test "$$run_check" = "yes"; then \
+ 	if test "$(USE_DEJAGNU)" = "yes"; then \
+ 	  $(SHELL) $(srcdir)/testsuite/gotest --goarch=$(GOARCH) --goos=$(GOOS) --dejagnu=yes --basedir=$(srcdir) --srcdir=$(srcdir)/go/$(@D) --pkgpath="$(@D)" --pkgfiles="$(go_$(subst /,_,$(@D))_files)" --testname="$(@D)" $(GOTESTFLAGS) $(go_$(subst /,_,$(@D))_test_files); \
+ 	elif test "$(GOBENCH)" != ""; then \
+@@ -2402,6 +2408,7 @@ CHECK = \
+ 	    echo "FAIL: $(@D)" > $@-testsum; \
+ 	    exit 1; \
+ 	  fi; \
++	fi; \
+ 	fi
+ 
+ # Build all packages before checking any.
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -2394,6 +2394,12 @@ CHECK = \
+ 	export LD_LIBRARY_PATH; \
+ 	$(MKDIR_P) $(@D); \
+ 	rm -f $@-testsum $@-testlog; \
++	run_check=yes; \
++	MULTILIBDIR="$(MULTILIBDIR)"; \
++	case "$$MULTILIBDIR" in /64|/x32) \
++	  echo "$$RUNTESTFLAGS" | grep -q "$${MULTILIBDIR\#/*}" || run_check=; \
++	esac; \
++	if test "$$run_check" = "yes"; then \
+ 	if test "$(USE_DEJAGNU)" = "yes"; then \
+ 	  $(SHELL) $(srcdir)/testsuite/gotest --goarch=$(GOARCH) --goos=$(GOOS) --dejagnu=yes --basedir=$(srcdir) --srcdir=$(srcdir)/go/$(@D) --pkgpath="$(@D)" --pkgfiles="$(go_$(subst /,_,$(@D))_files)" --testname="$(@D)" $(GOTESTFLAGS) $(go_$(subst /,_,$(@D))_test_files); \
+ 	elif test "$(GOBENCH)" != ""; then \
+@@ -2409,6 +2415,7 @@ CHECK = \
+ 	    echo "FAIL: $(@D)" > $@-testsum; \
+ 	    exit 1; \
+ 	  fi; \
++	fi; \
+ 	fi
+ 
+ 
--- gcc-6-6.3.0.orig/debian/patches/libgomp-kfreebsd-testsuite.diff
+++ gcc-6-6.3.0/debian/patches/libgomp-kfreebsd-testsuite.diff
@@ -0,0 +1,16 @@
+# DP: Disable lock-2.c test on kfreebsd-*
+
+Index: b/src/libgomp/testsuite/libgomp.c/lock-2.c
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c/lock-2.c
++++ b/src/libgomp/testsuite/libgomp.c/lock-2.c
+@@ -4,6 +4,9 @@
+ int
+ main (void)
+ {
++#ifdef __FreeBSD_kernel__
++  return 1;
++#endif
+   int l = 0;
+   omp_nest_lock_t lock;
+   omp_init_nest_lock (&lock);
--- gcc-6-6.3.0.orig/debian/patches/libgomp-omp_h-multilib.diff
+++ gcc-6-6.3.0/debian/patches/libgomp-omp_h-multilib.diff
@@ -0,0 +1,28 @@
+# DP: Fix up omp.h for multilibs.
+
+2008-06-09  Jakub Jelinek  <jakub@redhat.com>
+
+	* omp.h.in (omp_nest_lock_t): Fix up for Linux multilibs.
+
+2015-03-25  Matthias Klose  <doko@ubuntu.com>
+
+	* omp.h.in (omp_nest_lock_t): Limit the fix Linux.
+
+Index: b/src/libgomp/omp.h.in
+===================================================================
+--- a/src/libgomp/omp.h.in
++++ b/src/libgomp/omp.h.in
+@@ -40,8 +40,13 @@ typedef struct
+ 
+ typedef struct
+ {
++#if defined(__linux__)
++  unsigned char _x[8 + sizeof (void *)] 
++    __attribute__((__aligned__(sizeof (void *))));
++#else
+   unsigned char _x[@OMP_NEST_LOCK_SIZE@] 
+     __attribute__((__aligned__(@OMP_NEST_LOCK_ALIGN@)));
++#endif
+ } omp_nest_lock_t;
+ #endif
+ 
--- gcc-6-6.3.0.orig/debian/patches/libiberty-updates.diff
+++ gcc-6-6.3.0/debian/patches/libiberty-updates.diff
@@ -0,0 +1,2647 @@
+# DP: libiberty updates, taken from the trunk 20161108
+
+2016-11-30  David Malcolm  <dmalcolm@redhat.com>
+
+	PR c/78498
+	* strndup.c (strlen): Delete decl.
+	(strnlen): Add decl.
+	(strndup): Call strnlen rather than strlen.
+	* xstrndup.c (xstrndup): Likewise.
+
+2016-11-29  Nathan Sidwell  <nathan@acm.org>
+
+	* cp-demangle.c (d_print_comp_inner): Fix parameter indentation.
+
+2016-11-03  David Tolnay <dtolnay@gmail.com>
+	    Mark Wielaard  <mark@klomp.org>
+
+	* Makefile.in (CFILES): Add rust-demangle.c.
+	(REQUIRED_OFILES): Add rust-demangle.o.
+	* cplus-dem.c (libiberty_demanglers): Add rust_demangling case.
+	(cplus_demangle): Handle RUST_DEMANGLING.
+	(rust_demangle): New function.
+	* rust-demangle.c: New file.
+	* testsuite/Makefile.in (really-check): Add check-rust-demangle.
+	(check-rust-demangle): New rule.
+	* testsuite/rust-demangle-expected: New file.
+
+2016-11-15  Mark Wielaard  <mark@klomp.org>
+
+	* cp-demangle.c (d_expression_1): Make sure third expression
+	exists for ?: and fold expressions.
+	* testsuite/demangle-expected: Add examples of strings that could
+	crash the demangler because of missing expression.
+
+2016-11-14  Mark Wielaard  <mark@klomp.org>
+
+	* cplus-dem.c (demangle_signature): After 'H', template function,
+	no success and don't advance position if end of string reached.
+	(demangle_template): After 'z', template name, return zero on
+	premature end of string.
+	(gnu_special): Guard strchr against searching for zero characters.
+	(do_type): If member, only advance mangled string when 'F' found.
+	* testsuite/demangle-expected: Add examples of strings that could
+	crash the demangler by reading past end of input.
+
+2016-11-06  Mark Wielaard  <mark@klomp.org>
+
+	* configure.ac (ac_libiberty_warn_cflags): Add -Wshadow=local.
+	* configure: Regenerated.
+
+2016-11-07  Jason Merrill  <jason@redhat.com>
+
+	* cp-demangle.c (is_fnqual_component_type): New.
+	(d_encoding, d_print_comp_inner, d_print_mod_list): Use it.
+	(FNQUAL_COMPONENT_CASE): New.
+	(d_make_comp, has_return_type, d_print_comp_inner)
+	(d_print_function_type): Use it.
+	(next_is_type_qual): New.
+	(d_cv_qualifiers, d_print_mod): Handle noexcept and throw-spec.
+
+2016-11-02  Mark Wielaard  <mjw@redhat.com>
+
+	* cplus-dem.c (demangle_signature): Move fall through comment.
+	(demangle_fund_type): Add fall through comment between 'G' and 'I'.
+	* hashtab.c (iterative_hash): Add fall through comments.
+	* regex.c (regex_compile): Add Fall through comment after '+'/'?'.
+	(byte_re_match_2_internal): Add Fall through comment after jump_n.
+	Change "Note fall through" to "Fall through".
+	(common_op_match_null_string_p): Return false after set_number_at
+	instead of fall through.
+
+2016-11-01  Jason Merrill  <jason@redhat.com>
+
+	* cp-demangle.c (d_ctor_dtor_name): Handle inheriting constructor.
+
+2016-10-31  Mark Wielaard  <mjw@redhat.com>
+
+	* cplus-dem.c (ada_demangle): Initialize demangled to NULL and
+	XDELETEVEC demangled when unknown.
+
+2016-09-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	* pex-win32.c (argv_to_cmdline): Quote zero-length parameters.
+	* testsuite/test-pexecute.c (main): Insert check for zero-length parameters.
+
+2016-09-10  Mark Wielaard  <mjw@redhat.com>
+
+	* cp-demangle.c (d_substitution): Change struct demangle_component
+	variable name from c to dc.
+
+2016-08-12  Marek Polacek  <polacek@redhat.com>
+
+	PR c/7652
+	* cp-demangle.c (d_print_mod): Add FALLTHRU.
+
+2016-08-04  Marcel Böhme  <boehme.marcel@gmail.com>
+
+	PR c++/71696
+	* cplus-dem.c: Prevent infinite recursion when there is a cycle
+	in the referencing of remembered mangled types.
+	(work_stuff): New stack to keep track of the remembered mangled
+	types that are currently being processed.
+	(push_processed_type): New method to push currently processed
+	remembered type onto the stack.
+	(pop_processed_type): New method to pop currently processed
+	remembered type from the stack.
+	(work_stuff_copy_to_from): Copy values of new variables.
+	(delete_non_B_K_work_stuff): Free stack memory.
+	(demangle_args): Push/Pop currently processed remembered type.
+	(do_type): Do not demangle a cyclic reference and push/pop
+	referenced remembered type.
+
+2016-07-29  Aldy Hernandez  <aldyh@redhat.com>
+
+	* make-relative-prefix.c (make_relative_prefix_1): Fall back to
+	malloc if alloca argument is greater than MAX_ALLOCA_SIZE.
+
+2016-07-15  Jason Merrill  <jason@redhat.com>
+
+	* cp-demangle.c (cplus_demangle_operators): Add f[lrLR].
+	(d_expression_1): Handle them.
+	(d_maybe_print_fold_expression): New.
+	(d_print_comp_inner): Use it.
+	(d_index_template_argument): Handle negative index.
+
+	* cp-demangle.c (cplus_demangle_operators): Add sP and sZ.
+	(d_print_comp_inner): Handle them.
+	(d_template_args_1): Split out from d_template_args.
+	(d_args_length): New.
+
+2016-07-13  Marcel Böhme  <boehme.marcel@gmail.com>
+
+	PR c++/70926
+	* cplus-dem.c: Handle large values and overflow when demangling
+	length variables.
+	(demangle_template_value_parm): Read only until end of mangled string.
+	(do_hpacc_template_literal): Likewise.
+	(do_type): Handle overflow when demangling array indices.
+
+2016-06-12  Brooks Moses  <bmoses@google.com>
+
+	* cp-demangle.c (cplus_demangle_print_callback): Avoid zero-length
+	  VLAs.
+
+2016-05-31  Alan Modra  <amodra@gmail.com>
+
+	* xmemdup.c (xmemdup): Use xmalloc rather than xcalloc.
+
+2016-05-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/70498
+	* cp-demangle.c (d_expression_1): Formatting fix.
+
+2016-05-18  Artemiy Volkov  <artemiyv@acm.org>
+
+	* cplus-dem.c (enum type_kind_t): Add tk_rvalue_reference
+	constant.
+	(demangle_template_value_parm): Handle tk_rvalue_reference
+	type kind.
+	(do_type): Support 'O' type id (rvalue references).
+
+	* testsuite/demangle-expected: Add tests.
+
+Index: b/src/libiberty/argv.c
+===================================================================
+--- a/src/libiberty/argv.c
++++ b/src/libiberty/argv.c
+@@ -35,6 +35,13 @@ Boston, MA 02110-1301, USA.  */
+ #include <string.h>
+ #include <stdlib.h>
+ #include <stdio.h>
++#include <sys/types.h>
++#ifdef HAVE_UNISTD_H
++#include <unistd.h>
++#endif
++#if HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
+ 
+ #ifndef NULL
+ #define NULL 0
+@@ -387,6 +394,9 @@ expandargv (int *argcp, char ***argvp)
+       char **file_argv;
+       /* The number of options read from the response file, if any.  */
+       size_t file_argc;
++#ifdef S_ISDIR
++      struct stat sb;
++#endif
+       /* We are only interested in options of the form "@file".  */
+       filename = (*argvp)[i];
+       if (filename[0] != '@')
+@@ -397,6 +407,15 @@ expandargv (int *argcp, char ***argvp)
+ 	  fprintf (stderr, "%s: error: too many @-files encountered\n", (*argvp)[0]);
+ 	  xexit (1);
+ 	}
++#ifdef S_ISDIR
++      if (stat (filename+1, &sb) < 0)
++	continue;
++      if (S_ISDIR(sb.st_mode))
++	{
++	  fprintf (stderr, "%s: error: @-file refers to a directory\n", (*argvp)[0]);
++	  xexit (1);
++	}
++#endif
+       /* Read the contents of the file.  */
+       f = fopen (++filename, "r");
+       if (!f)
+Index: b/src/libiberty/ChangeLog
+===================================================================
+--- a/src/libiberty/ChangeLog
++++ b/src/libiberty/ChangeLog
+@@ -22,11 +22,126 @@
+ 	printing.
+ 	* testsuite/demangle-expected: Add lambda auto mangling cases. 
+ 
+-2016-08-22  Release Manager
++2016-12-06  DJ Delorie  <dj@redhat.com>
+ 
+-	* GCC 6.2.0 released.
++	* argv.c (expandargv): Check for directories passed as @-files.
+ 
+-2016-07-21  Jason Merrill  <jason@redhat.com>
++2016-11-30  David Malcolm  <dmalcolm@redhat.com>
++
++	PR c/78498
++	* strndup.c (strlen): Delete decl.
++	(strnlen): Add decl.
++	(strndup): Call strnlen rather than strlen.
++	* xstrndup.c (xstrndup): Likewise.
++
++2016-11-29  Nathan Sidwell  <nathan@acm.org>
++
++	* cp-demangle.c (d_print_comp_inner): Fix parameter indentation.
++
++2016-11-03  David Tolnay <dtolnay@gmail.com>
++	    Mark Wielaard  <mark@klomp.org>
++
++	* Makefile.in (CFILES): Add rust-demangle.c.
++	(REQUIRED_OFILES): Add rust-demangle.o.
++	* cplus-dem.c (libiberty_demanglers): Add rust_demangling case.
++	(cplus_demangle): Handle RUST_DEMANGLING.
++	(rust_demangle): New function.
++	* rust-demangle.c: New file.
++	* testsuite/Makefile.in (really-check): Add check-rust-demangle.
++	(check-rust-demangle): New rule.
++	* testsuite/rust-demangle-expected: New file.
++
++2016-11-15  Mark Wielaard  <mark@klomp.org>
++
++	* cp-demangle.c (d_expression_1): Make sure third expression
++	exists for ?: and fold expressions.
++	* testsuite/demangle-expected: Add examples of strings that could
++	crash the demangler because of missing expression.
++
++2016-11-14  Mark Wielaard  <mark@klomp.org>
++
++	* cplus-dem.c (demangle_signature): After 'H', template function,
++	no success and don't advance position if end of string reached.
++	(demangle_template): After 'z', template name, return zero on
++	premature end of string.
++	(gnu_special): Guard strchr against searching for zero characters.
++	(do_type): If member, only advance mangled string when 'F' found.
++	* testsuite/demangle-expected: Add examples of strings that could
++	crash the demangler by reading past end of input.
++
++2016-11-06  Mark Wielaard  <mark@klomp.org>
++
++	* configure.ac (ac_libiberty_warn_cflags): Add -Wshadow=local.
++	* configure: Regenerated.
++
++2016-11-07  Jason Merrill  <jason@redhat.com>
++
++	* cp-demangle.c (is_fnqual_component_type): New.
++	(d_encoding, d_print_comp_inner, d_print_mod_list): Use it.
++	(FNQUAL_COMPONENT_CASE): New.
++	(d_make_comp, has_return_type, d_print_comp_inner)
++	(d_print_function_type): Use it.
++	(next_is_type_qual): New.
++	(d_cv_qualifiers, d_print_mod): Handle noexcept and throw-spec.
++
++2016-11-02  Mark Wielaard  <mjw@redhat.com>
++
++	* cplus-dem.c (demangle_signature): Move fall through comment.
++	(demangle_fund_type): Add fall through comment between 'G' and 'I'.
++	* hashtab.c (iterative_hash): Add fall through comments.
++	* regex.c (regex_compile): Add Fall through comment after '+'/'?'.
++	(byte_re_match_2_internal): Add Fall through comment after jump_n.
++	Change "Note fall through" to "Fall through".
++	(common_op_match_null_string_p): Return false after set_number_at
++	instead of fall through.
++
++2016-11-01  Jason Merrill  <jason@redhat.com>
++
++	* cp-demangle.c (d_ctor_dtor_name): Handle inheriting constructor.
++
++2016-10-31  Mark Wielaard  <mjw@redhat.com>
++
++	* cplus-dem.c (ada_demangle): Initialize demangled to NULL and
++	XDELETEVEC demangled when unknown.
++
++2016-09-19  Andrew Stubbs  <ams@codesourcery.com>
++
++	* pex-win32.c (argv_to_cmdline): Quote zero-length parameters.
++	* testsuite/test-pexecute.c (main): Insert check for zero-length parameters.
++
++2016-09-10  Mark Wielaard  <mjw@redhat.com>
++
++	* cp-demangle.c (d_substitution): Change struct demangle_component
++	variable name from c to dc.
++
++2016-08-12  Marek Polacek  <polacek@redhat.com>
++
++	PR c/7652
++	* cp-demangle.c (d_print_mod): Add FALLTHRU.
++
++2016-08-04  Marcel Böhme  <boehme.marcel@gmail.com>
++
++	PR c++/71696
++	* cplus-dem.c: Prevent infinite recursion when there is a cycle
++	in the referencing of remembered mangled types.
++	(work_stuff): New stack to keep track of the remembered mangled
++	types that are currently being processed.
++	(push_processed_type): New method to push currently processed
++	remembered type onto the stack.
++	(pop_processed_type): New method to pop currently processed
++	remembered type from the stack.
++	(work_stuff_copy_to_from): Copy values of new variables.
++	(delete_non_B_K_work_stuff): Free stack memory.
++	(demangle_args): Push/Pop currently processed remembered type.
++	(do_type): Do not demangle a cyclic reference and push/pop
++	referenced remembered type.
++
++2016-07-29  Aldy Hernandez  <aldyh@redhat.com>
++
++	* make-relative-prefix.c (make_relative_prefix_1): Fall back to
++	malloc if alloca argument is greater than MAX_ALLOCA_SIZE.
++
++2016-07-15  Jason Merrill  <jason@redhat.com>
+ 
+ 	* cp-demangle.c (cplus_demangle_operators): Add f[lrLR].
+ 	(d_expression_1): Handle them.
+@@ -39,15 +154,40 @@
+ 	(d_template_args_1): Split out from d_template_args.
+ 	(d_args_length): New.
+ 
+-2016-05-19  Jakub Jelinek  <jakub@redhat.com>
++2016-07-13  Marcel Böhme  <boehme.marcel@gmail.com>
++
++	PR c++/70926
++	* cplus-dem.c: Handle large values and overflow when demangling
++	length variables.
++	(demangle_template_value_parm): Read only until end of mangled string.
++	(do_hpacc_template_literal): Likewise.
++	(do_type): Handle overflow when demangling array indices.
++
++2016-06-12  Brooks Moses  <bmoses@google.com>
++
++	* cp-demangle.c (cplus_demangle_print_callback): Avoid zero-length
++	  VLAs.
+ 
+-	Backported from mainline
+-	2016-05-19  Jakub Jelinek  <jakub@redhat.com>
++2016-05-31  Alan Modra  <amodra@gmail.com>
++
++	* xmemdup.c (xmemdup): Use xmalloc rather than xcalloc.
++
++2016-05-19  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR c++/70498
+ 	* cp-demangle.c (d_expression_1): Formatting fix.
+ 
+-	2016-05-02  Marcel Böhme  <boehme.marcel@gmail.com>
++2016-05-18  Artemiy Volkov  <artemiyv@acm.org>
++
++	* cplus-dem.c (enum type_kind_t): Add tk_rvalue_reference
++	constant.
++	(demangle_template_value_parm): Handle tk_rvalue_reference
++	type kind.
++	(do_type): Support 'O' type id (rvalue references).
++
++	* testsuite/demangle-expected: Add tests.
++
++2016-05-02  Marcel Böhme  <boehme.marcel@gmail.com>
+ 
+ 	PR c++/70498
+ 	* cp-demangle.c: Parse numbers as integer instead of long to avoid
+@@ -66,9 +206,9 @@
+ 	(d_unnamed_type): Likewise.
+ 	* testsuite/demangle-expected: Add regression test cases.
+ 
+-2016-04-27  Release Manager
++2016-04-30  Oleg Endo  <olegendo@gcc.gnu.org>
+ 
+-	* GCC 6.1.0 released.
++	* configure: Remove SH5 support.
+ 
+ 2016-04-08  Marcel Böhme  <boehme.marcel@gmail.com>
+ 
+@@ -141,8 +281,6 @@
+ 
+ 	PR other/61321
+ 	PR other/61233
+-	* demangle.h (enum demangle_component_type)
+-	<DEMANGLE_COMPONENT_CONVERSION>: New value.
+ 	* cp-demangle.c (d_demangle_callback, d_make_comp): Handle
+ 	DEMANGLE_COMPONENT_CONVERSION.
+ 	(is_ctor_dtor_or_conversion): Handle DEMANGLE_COMPONENT_CONVERSION
+@@ -729,11 +867,11 @@
+ 2013-05-31  Matt Burgess <matthew@linuxfromscratch.org>
+ 
+ 	PR other/56780
+-	* libiberty/configure.ac: Move test for --enable-install-libiberty
++	* configure.ac: Move test for --enable-install-libiberty
+ 	outside of the 'with_target_subdir' test so that it actually gets
+ 	run.  Add output messages to show the test result.
+-	* libiberty/configure: Regenerate.
+-	* libiberty/Makefile.in (install_to_libdir): Place the
++	* configure: Regenerate.
++	* Makefile.in (install_to_libdir): Place the
+ 	installation of the libiberty library in the same guard as that
+ 	used for the headers to prevent it being installed unless
+ 	requested via --enable-install-libiberty.
+@@ -1533,7 +1671,6 @@
+ 	Daniel Jacobowitz  <dan@codesourcery.com>
+ 	Pedro Alves  <pedro@codesourcery.com>
+ 
+-	libiberty/
+ 	* argv.c (consume_whitespace): New function.
+ 	(only_whitespace): New function.
+ 	(buildargv): Always use ISSPACE by calling consume_whitespace.
+@@ -1734,8 +1871,8 @@
+ 
+ 2009-04-07  Arnaud Patard <apatard@mandriva.com>
+ 
+-	* libiberty/configure.ac: Fix Linux/MIPS matching rule.
+-	* libiberty/configure: Regenerate.
++	* configure.ac: Fix Linux/MIPS matching rule.
++	* configure: Regenerate.
+ 
+ 2009-03-27  Ian Lance Taylor  <iant@google.com>
+ 
+@@ -1898,8 +2035,8 @@
+ 
+ 2008-04-21  Aurelien Jarno  <aurelien@aurel32.net>
+ 
+-	* libiberty/configure.ac: use -fPIC on Linux/MIPS hosts.
+-	* libiberty/configure: Regenerate.
++	* configure.ac: use -fPIC on Linux/MIPS hosts.
++	* configure: Regenerate.
+ 
+ 2008-04-18  Kris Van Hees <kris.van.hees@oracle.com>
+ 
+@@ -3677,7 +3814,7 @@
+ 
+ 2003-12-15  Brendan Kehoe  <brendan@zen.org>
+ 
+-	* libiberty/Makefile.in (floatformat.o): Add dependency on
++	* Makefile.in (floatformat.o): Add dependency on
+ 	config.h to accompany change of 2003-12-03.
+ 
+ 2003-12-15  Ian Lance Taylor  <ian@wasabisystems.com>
+@@ -4373,7 +4510,7 @@
+ 
+ 2002-10-06  Andreas Jaeger  <aj@suse.de>
+ 
+-	* libiberty/cplus-dem.c (ada_demangle): Get rid of unneeded
++	* cplus-dem.c (ada_demangle): Get rid of unneeded
+ 	variable and of strict-aliasing warning.
+ 	(grow_vect): Use char as first parameter.
+ 
+@@ -4641,7 +4778,7 @@
+ 
+ 2002-01-31  Adam Megacz  <adam@xwt.org>
+ 
+-	* gcc/libiberty/configure.in: Treat mingw the same as cywin
++	* configure.in: Treat mingw the same as cywin
+ 	wrt HAVE_SYS_ERRLIST.
+ 
+ 2002-01-30  Phil Edwards  <pme@gcc.gnu.org>
+@@ -5149,8 +5286,8 @@ Tue Aug 21 12:35:04 2001  Christopher Fa
+ 2001-03-10  Neil Booth  <neil@daikokuya.demon.co.uk>
+ 	    John David Anglin  <dave@hiauly1.hia.nrc.ca>
+ 
+-	* libiberty/lbasename.c: New file.
+-	* libiberty/Makefile.in: Update for lbasename.
++	* lbasename.c: New file.
++	* Makefile.in: Update for lbasename.
+ 
+ 2001-03-06  Zack Weinberg  <zackw@stanford.edu>
+ 
+@@ -5523,13 +5660,13 @@ Tue Aug 21 12:35:04 2001  Christopher Fa
+ 
+ 2000-08-24  Greg McGary  <greg@mcgary.org>
+ 
+-	* libiberty/random.c (end_ptr): Revert previous change.
++	* random.c (end_ptr): Revert previous change.
+ 
+ 2000-08-24  Greg McGary  <greg@mcgary.org>
+ 
+-	* libiberty/cplus-dem.c (cplus_demangle_opname, cplus_mangle_opname,
++	* cplus-dem.c (cplus_demangle_opname, cplus_mangle_opname,
+ 	demangle_expression, demangle_function_name): Use ARRAY_SIZE.
+-	* libiberty/random.c (end_ptr): Likewise.
++	* random.c (end_ptr): Likewise.
+ 
+ 2000-08-23  Alex Samuel  <samuel@codesourcery.com>
+ 
+Index: b/src/libiberty/configure
+===================================================================
+--- a/src/libiberty/configure
++++ b/src/libiberty/configure
+@@ -4398,7 +4398,8 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu
+ ac_libiberty_warn_cflags=
+ save_CFLAGS="$CFLAGS"
+ for real_option in -W -Wall -Wwrite-strings -Wc++-compat \
+-			  -Wstrict-prototypes; do
++			  -Wstrict-prototypes \
++			  -Wshadow=local; do
+   # Do the check with the no- prefix removed since gcc silently
+   # accepts any -Wno-* option on purpose
+   case $real_option in
+@@ -5145,8 +5146,7 @@ case "${host}" in
+ 	PICFLAG=-fpic
+ 	;;
+     # FIXME: Simplify to sh*-*-netbsd*?
+-    sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
+-      sh64-*-netbsd* | sh64l*-*-netbsd*)
++    sh-*-netbsdelf* | shl*-*-netbsdelf*)
+ 	PICFLAG=-fpic
+ 	;;
+     # Default to -fPIC unless specified otherwise.
+Index: b/src/libiberty/configure.ac
+===================================================================
+--- a/src/libiberty/configure.ac
++++ b/src/libiberty/configure.ac
+@@ -160,7 +160,8 @@ AC_SYS_LARGEFILE
+ AC_PROG_CPP_WERROR
+ 
+ ACX_PROG_CC_WARNING_OPTS([-W -Wall -Wwrite-strings -Wc++-compat \
+-			  -Wstrict-prototypes], [ac_libiberty_warn_cflags])
++			  -Wstrict-prototypes \
++			  -Wshadow=local], [ac_libiberty_warn_cflags])
+ ACX_PROG_CC_WARNING_ALMOST_PEDANTIC([], [ac_libiberty_warn_cflags])
+ 
+ AC_PROG_CC_C_O
+Index: b/src/libiberty/cp-demangle.c
+===================================================================
+--- a/src/libiberty/cp-demangle.c
++++ b/src/libiberty/cp-demangle.c
+@@ -439,6 +439,8 @@ static struct demangle_component *d_oper
+ 
+ static struct demangle_component *d_special_name (struct d_info *);
+ 
++static struct demangle_component *d_parmlist (struct d_info *);
++
+ static int d_call_offset (struct d_info *, int);
+ 
+ static struct demangle_component *d_ctor_dtor_name (struct d_info *);
+@@ -562,6 +564,32 @@ static int d_demangle_callback (const ch
+                                 demangle_callbackref, void *);
+ static char *d_demangle (const char *, int, size_t *);
+ 
++/* True iff TYPE is a demangling component representing a
++   function-type-qualifier.  */
++
++static int
++is_fnqual_component_type (enum demangle_component_type type)
++{
++  return (type == DEMANGLE_COMPONENT_RESTRICT_THIS
++	  || type == DEMANGLE_COMPONENT_VOLATILE_THIS
++	  || type == DEMANGLE_COMPONENT_CONST_THIS
++	  || type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS
++	  || type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
++	  || type == DEMANGLE_COMPONENT_NOEXCEPT
++	  || type == DEMANGLE_COMPONENT_THROW_SPEC
++	  || type == DEMANGLE_COMPONENT_REFERENCE_THIS);
++}
++
++#define FNQUAL_COMPONENT_CASE				\
++    case DEMANGLE_COMPONENT_RESTRICT_THIS:		\
++    case DEMANGLE_COMPONENT_VOLATILE_THIS:		\
++    case DEMANGLE_COMPONENT_CONST_THIS:			\
++    case DEMANGLE_COMPONENT_REFERENCE_THIS:		\
++    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:	\
++    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:		\
++    case DEMANGLE_COMPONENT_NOEXCEPT:			\
++    case DEMANGLE_COMPONENT_THROW_SPEC
++
+ #ifdef CP_DEMANGLE_DEBUG
+ 
+ static void
+@@ -987,14 +1015,9 @@ d_make_comp (struct d_info *di, enum dem
+     case DEMANGLE_COMPONENT_RESTRICT:
+     case DEMANGLE_COMPONENT_VOLATILE:
+     case DEMANGLE_COMPONENT_CONST:
+-    case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-    case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-    case DEMANGLE_COMPONENT_CONST_THIS:
+-    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+-    case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_ARGLIST:
+     case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST:
++    FNQUAL_COMPONENT_CASE:
+       break;
+ 
+       /* Other types should not be seen here.  */
+@@ -1228,12 +1251,7 @@ has_return_type (struct demangle_compone
+       return 0;
+     case DEMANGLE_COMPONENT_TEMPLATE:
+       return ! is_ctor_dtor_or_conversion (d_left (dc));
+-    case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-    case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-    case DEMANGLE_COMPONENT_CONST_THIS:
+-    case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++    FNQUAL_COMPONENT_CASE:
+       return has_return_type (d_left (dc));
+     }
+ }
+@@ -1290,13 +1308,12 @@ d_encoding (struct d_info *di, int top_l
+ 	  while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+ 		 || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+ 		 || dc->type == DEMANGLE_COMPONENT_CONST_THIS
+-		 || dc->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+ 		 || dc->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+ 		 || dc->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
+ 	    dc = d_left (dc);
+ 
+ 	  /* If the top level is a DEMANGLE_COMPONENT_LOCAL_NAME, then
+-	     there may be CV-qualifiers on its right argument which
++	     there may be function-qualifiers on its right argument which
+ 	     really apply here; this happens when parsing a class
+ 	     which is local to a function.  */
+ 	  if (dc->type == DEMANGLE_COMPONENT_LOCAL_NAME)
+@@ -1304,12 +1321,7 @@ d_encoding (struct d_info *di, int top_l
+ 	      struct demangle_component *dcr;
+ 
+ 	      dcr = d_right (dc);
+-	      while (dcr->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_CONST_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-		     || dcr->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
++	      while (is_fnqual_component_type (dcr->type))
+ 		dcr = d_left (dcr);
+ 	      dc->u.s_binary.right = dcr;
+ 	    }
+@@ -2171,6 +2183,13 @@ d_ctor_dtor_name (struct d_info *di)
+     case 'C':
+       {
+ 	enum gnu_v3_ctor_kinds kind;
++	int inheriting = 0;
++
++	if (d_peek_next_char (di) == 'I')
++	  {
++	    inheriting = 1;
++	    d_advance (di, 1);
++	  }
+ 
+ 	switch (d_peek_next_char (di))
+ 	  {
+@@ -2192,7 +2211,12 @@ d_ctor_dtor_name (struct d_info *di)
+ 	  default:
+ 	    return NULL;
+ 	  }
++
+ 	d_advance (di, 2);
++
++	if (inheriting)
++	  cplus_demangle_type (di);
++
+ 	return d_make_ctor (di, kind, di->last_name);
+       }
+ 
+@@ -2230,6 +2254,24 @@ d_ctor_dtor_name (struct d_info *di)
+     }
+ }
+ 
++/* True iff we're looking at an order-insensitive type-qualifier, including
++   function-type-qualifiers.  */
++
++static int
++next_is_type_qual (struct d_info *di)
++{
++  char peek = d_peek_char (di);
++  if (peek == 'r' || peek == 'V' || peek == 'K')
++    return 1;
++  if (peek == 'D')
++    {
++      peek = d_peek_next_char (di);
++      if (peek == 'x' || peek == 'o' || peek == 'O' || peek == 'w')
++	return 1;
++    }
++  return 0;
++}
++
+ /* <type> ::= <builtin-type>
+           ::= <function-type>
+           ::= <class-enum-type>
+@@ -2315,9 +2357,7 @@ cplus_demangle_type (struct d_info *di)
+      __vector, and it treats it as order-sensitive when mangling
+      names.  */
+ 
+-  peek = d_peek_char (di);
+-  if (peek == 'r' || peek == 'V' || peek == 'K'
+-      || (peek == 'D' && d_peek_next_char (di) == 'x'))
++  if (next_is_type_qual (di))
+     {
+       struct demangle_component **pret;
+ 
+@@ -2352,6 +2392,7 @@ cplus_demangle_type (struct d_info *di)
+ 
+   can_subst = 1;
+ 
++  peek = d_peek_char (di);
+   switch (peek)
+     {
+     case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'g':
+@@ -2643,10 +2684,10 @@ d_cv_qualifiers (struct d_info *di,
+ 
+   pstart = pret;
+   peek = d_peek_char (di);
+-  while (peek == 'r' || peek == 'V' || peek == 'K'
+-	 || (peek == 'D' && d_peek_next_char (di) == 'x'))
++  while (next_is_type_qual (di))
+     {
+       enum demangle_component_type t;
++      struct demangle_component *right = NULL;
+ 
+       d_advance (di, 1);
+       if (peek == 'r')
+@@ -2672,12 +2713,41 @@ d_cv_qualifiers (struct d_info *di,
+ 	}
+       else
+ 	{
+-	  t = DEMANGLE_COMPONENT_TRANSACTION_SAFE;
+-	  di->expansion += sizeof "transaction_safe";
+-	  d_advance (di, 1);
++	  peek = d_next_char (di);
++	  if (peek == 'x')
++	    {
++	      t = DEMANGLE_COMPONENT_TRANSACTION_SAFE;
++	      di->expansion += sizeof "transaction_safe";
++	    }
++	  else if (peek == 'o'
++		   || peek == 'O')
++	    {
++	      t = DEMANGLE_COMPONENT_NOEXCEPT;
++	      di->expansion += sizeof "noexcept";
++	      if (peek == 'O')
++		{
++		  right = d_expression (di);
++		  if (right == NULL)
++		    return NULL;
++		  if (! d_check_char (di, 'E'))
++		    return NULL;
++		}
++	    }
++	  else if (peek == 'w')
++	    {
++	      t = DEMANGLE_COMPONENT_THROW_SPEC;
++	      di->expansion += sizeof "throw";
++	      right = d_parmlist (di);
++	      if (right == NULL)
++		return NULL;
++	      if (! d_check_char (di, 'E'))
++		return NULL;
++	    }
++	  else
++	    return NULL;
+ 	}
+ 
+-      *pret = d_make_comp (di, t, NULL, NULL);
++      *pret = d_make_comp (di, t, NULL, right);
+       if (*pret == NULL)
+ 	return NULL;
+       pret = &d_left (*pret);
+@@ -3352,6 +3422,8 @@ d_expression_1 (struct d_info *di)
+ 		first = d_expression_1 (di);
+ 		second = d_expression_1 (di);
+ 		third = d_expression_1 (di);
++		if (third == NULL)
++		  return NULL;
+ 	      }
+ 	    else if (code[0] == 'f')
+ 	      {
+@@ -3359,6 +3431,8 @@ d_expression_1 (struct d_info *di)
+ 		first = d_operator_name (di);
+ 		second = d_expression_1 (di);
+ 		third = d_expression_1 (di);
++		if (third == NULL)
++		  return NULL;
+ 	      }
+ 	    else if (code[0] == 'n')
+ 	      {
+@@ -3776,7 +3850,7 @@ d_substitution (struct d_info *di, int p
+ 	    {
+ 	      const char *s;
+ 	      int len;
+-	      struct demangle_component *c;
++	      struct demangle_component *dc;
+ 
+ 	      if (p->set_last_name != NULL)
+ 		di->last_name = d_make_sub (di, p->set_last_name,
+@@ -3792,15 +3866,15 @@ d_substitution (struct d_info *di, int p
+ 		  len = p->simple_len;
+ 		}
+ 	      di->expansion += len;
+-	      c = d_make_sub (di, s, len);
++	      dc = d_make_sub (di, s, len);
+ 	      if (d_peek_char (di) == 'B')
+ 		{
+ 		  /* If there are ABI tags on the abbreviation, it becomes
+ 		     a substitution candidate.  */
+-		  c = d_abi_tags (di, c);
+-		  d_add_substitution (di, c);
++		  dc = d_abi_tags (di, dc);
++		  d_add_substitution (di, dc);
+ 		}
+-	      return c;
++	      return dc;
+ 	    }
+ 	}
+ 
+@@ -3968,6 +4042,8 @@ d_count_templates_scopes (int *num_templ
+     case DEMANGLE_COMPONENT_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++    case DEMANGLE_COMPONENT_NOEXCEPT:
++    case DEMANGLE_COMPONENT_THROW_SPEC:
+     case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
+     case DEMANGLE_COMPONENT_POINTER:
+     case DEMANGLE_COMPONENT_COMPLEX:
+@@ -4163,8 +4239,12 @@ cplus_demangle_print_callback (int optio
+ 
+   {
+ #ifdef CP_DYNAMIC_ARRAYS
+-    __extension__ struct d_saved_scope scopes[dpi.num_saved_scopes];
+-    __extension__ struct d_print_template temps[dpi.num_copy_templates];
++    /* Avoid zero-length VLAs, which are prohibited by the C99 standard
++       and flagged as errors by Address Sanitizer.  */
++    __extension__ struct d_saved_scope scopes[(dpi.num_saved_scopes > 0)
++                                              ? dpi.num_saved_scopes : 1];
++    __extension__ struct d_print_template temps[(dpi.num_copy_templates > 0)
++                                                ? dpi.num_copy_templates : 1];
+ 
+     dpi.saved_scopes = scopes;
+     dpi.copy_templates = temps;
+@@ -4492,7 +4572,7 @@ d_maybe_print_fold_expression (struct d_
+ 
+ static void
+ d_print_comp_inner (struct d_print_info *dpi, int options,
+-		  const struct demangle_component *dc)
++		    const struct demangle_component *dc)
+ {
+   /* Magic variable to let reference smashing skip over the next modifier
+      without needing to modify *dc.  */
+@@ -4579,12 +4659,7 @@ d_print_comp_inner (struct d_print_info
+ 	    adpm[i].templates = dpi->templates;
+ 	    ++i;
+ 
+-	    if (typed_name->type != DEMANGLE_COMPONENT_RESTRICT_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_VOLATILE_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_CONST_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-		&& typed_name->type != DEMANGLE_COMPONENT_REFERENCE_THIS)
++	    if (!is_fnqual_component_type (typed_name->type))
+ 	      break;
+ 
+ 	    typed_name = d_left (typed_name);
+@@ -4621,13 +4696,7 @@ d_print_comp_inner (struct d_print_info
+ 		d_print_error (dpi);
+ 		return;
+ 	      }
+-	    while (local_name->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_CONST_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-		   || (local_name->type
+-		       == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS))
++	    while (is_fnqual_component_type (local_name->type))
+ 	      {
+ 		if (i >= sizeof adpm / sizeof adpm[0])
+ 		  {
+@@ -4961,16 +5030,11 @@ d_print_comp_inner (struct d_print_info
+       }
+       /* Fall through.  */
+ 
+-    case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-    case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-    case DEMANGLE_COMPONENT_CONST_THIS:
+-    case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
+     case DEMANGLE_COMPONENT_POINTER:
+     case DEMANGLE_COMPONENT_COMPLEX:
+     case DEMANGLE_COMPONENT_IMAGINARY:
+-    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++    FNQUAL_COMPONENT_CASE:
+     modifier:
+       {
+ 	/* We keep a list of modifiers on the stack.  */
+@@ -5679,13 +5743,7 @@ d_print_mod_list (struct d_print_info *d
+ 
+   if (mods->printed
+       || (! suffix
+-	  && (mods->mod->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_CONST_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-	      || (mods->mod->type
+-		  == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS))))
++	  && (is_fnqual_component_type (mods->mod->type))))
+     {
+       d_print_mod_list (dpi, options, mods->next, suffix);
+       return;
+@@ -5738,12 +5796,7 @@ d_print_mod_list (struct d_print_info *d
+ 	  dc = dc->u.s_unary_num.sub;
+ 	}
+ 
+-      while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_CONST_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-	     || dc->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
++      while (is_fnqual_component_type (dc->type))
+ 	dc = d_left (dc);
+ 
+       d_print_comp (dpi, options, dc);
+@@ -5782,6 +5835,24 @@ d_print_mod (struct d_print_info *dpi, i
+     case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+       d_append_string (dpi, " transaction_safe");
+       return;
++    case DEMANGLE_COMPONENT_NOEXCEPT:
++      d_append_string (dpi, " noexcept");
++      if (d_right (mod))
++	{
++	  d_append_char (dpi, '(');
++	  d_print_comp (dpi, options, d_right (mod));
++	  d_append_char (dpi, ')');
++	}
++      return;
++    case DEMANGLE_COMPONENT_THROW_SPEC:
++      d_append_string (dpi, " throw");
++      if (d_right (mod))
++	{
++	  d_append_char (dpi, '(');
++	  d_print_comp (dpi, options, d_right (mod));
++	  d_append_char (dpi, ')');
++	}
++      return;
+     case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
+       d_append_char (dpi, ' ');
+       d_print_comp (dpi, options, d_right (mod));
+@@ -5794,11 +5865,13 @@ d_print_mod (struct d_print_info *dpi, i
+     case DEMANGLE_COMPONENT_REFERENCE_THIS:
+       /* For the ref-qualifier, put a space before the &.  */
+       d_append_char (dpi, ' ');
++      /* FALLTHRU */
+     case DEMANGLE_COMPONENT_REFERENCE:
+       d_append_char (dpi, '&');
+       return;
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+       d_append_char (dpi, ' ');
++      /* FALLTHRU */
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
+       d_append_string (dpi, "&&");
+       return;
+@@ -5867,12 +5940,7 @@ d_print_function_type (struct d_print_in
+ 	  need_space = 1;
+ 	  need_paren = 1;
+ 	  break;
+-	case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-	case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-	case DEMANGLE_COMPONENT_CONST_THIS:
+-	case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-	case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+-	case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++	FNQUAL_COMPONENT_CASE:
+ 	  break;
+ 	default:
+ 	  break;
+@@ -6414,7 +6482,6 @@ is_ctor_or_dtor (const char *mangled,
+ 	  case DEMANGLE_COMPONENT_CONST_THIS:
+ 	  case DEMANGLE_COMPONENT_REFERENCE_THIS:
+ 	  case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+-	  case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+ 	  default:
+ 	    dc = NULL;
+ 	    break;
+Index: b/src/libiberty/cplus-dem.c
+===================================================================
+--- a/src/libiberty/cplus-dem.c
++++ b/src/libiberty/cplus-dem.c
+@@ -144,6 +144,9 @@ struct work_stuff
+   string* previous_argument; /* The last function argument demangled.  */
+   int nrepeats;         /* The number of times to repeat the previous
+ 			   argument.  */
++  int *proctypevec;     /* Indices of currently processed remembered typevecs.  */
++  int proctypevec_size;
++  int nproctypes;
+ };
+ 
+ #define PRINT_ANSI_QUALIFIERS (work -> options & DMGL_ANSI)
+@@ -244,6 +247,7 @@ typedef enum type_kind_t
+   tk_none,
+   tk_pointer,
+   tk_reference,
++  tk_rvalue_reference,
+   tk_integral,
+   tk_bool,
+   tk_char,
+@@ -319,6 +323,12 @@ const struct demangler_engine libiberty_
+   }
+   ,
+   {
++    RUST_DEMANGLING_STYLE_STRING,
++    rust_demangling,
++    "Rust style demangling"
++  }
++  ,
++  {
+     NULL, unknown_demangling, NULL
+   }
+ };
+@@ -435,6 +445,10 @@ iterate_demangle_function (struct work_s
+ 
+ static void remember_type (struct work_stuff *, const char *, int);
+ 
++static void push_processed_type (struct work_stuff *, int);
++
++static void pop_processed_type (struct work_stuff *);
++
+ static void remember_Btype (struct work_stuff *, const char *, int, int);
+ 
+ static int register_Btype (struct work_stuff *);
+@@ -866,10 +880,26 @@ cplus_demangle (const char *mangled, int
+     work->options |= (int) current_demangling_style & DMGL_STYLE_MASK;
+ 
+   /* The V3 ABI demangling is implemented elsewhere.  */
+-  if (GNU_V3_DEMANGLING || AUTO_DEMANGLING)
++  if (GNU_V3_DEMANGLING || RUST_DEMANGLING || AUTO_DEMANGLING)
+     {
+       ret = cplus_demangle_v3 (mangled, work->options);
+-      if (ret || GNU_V3_DEMANGLING)
++      if (GNU_V3_DEMANGLING)
++	return ret;
++
++      if (ret)
++	{
++	  /* Rust symbols are GNU_V3 mangled plus some extra subtitutions.
++	     The subtitutions are always smaller, so do in place changes.  */
++	  if (rust_is_mangled (ret))
++	    rust_demangle_sym (ret);
++	  else if (RUST_DEMANGLING)
++	    {
++	      free (ret);
++	      ret = NULL;
++	    }
++	}
++
++      if (ret || RUST_DEMANGLING)
+ 	return ret;
+     }
+ 
+@@ -895,6 +925,27 @@ cplus_demangle (const char *mangled, int
+   return (ret);
+ }
+ 
++char *
++rust_demangle (const char *mangled, int options)
++{
++  /* Rust symbols are GNU_V3 mangled plus some extra subtitutions.  */
++  char *ret = cplus_demangle_v3 (mangled, options);
++
++  /* The Rust subtitutions are always smaller, so do in place changes.  */
++  if (ret != NULL)
++    {
++      if (rust_is_mangled (ret))
++	rust_demangle_sym (ret);
++      else
++	{
++	  free (ret);
++	  ret = NULL;
++	}
++    }
++
++  return ret;
++}
++
+ /* Demangle ada names.  The encoding is documented in gcc/ada/exp_dbug.ads.  */
+ 
+ char *
+@@ -903,7 +954,7 @@ ada_demangle (const char *mangled, int o
+   int len0;
+   const char* p;
+   char *d;
+-  char *demangled;
++  char *demangled = NULL;
+   
+   /* Discard leading _ada_, which is used for library level subprograms.  */
+   if (strncmp (mangled, "_ada_", 5) == 0)
+@@ -1148,6 +1199,7 @@ ada_demangle (const char *mangled, int o
+   return demangled;
+ 
+  unknown:
++  XDELETEVEC (demangled);
+   len0 = strlen (mangled);
+   demangled = XNEWVEC (char, len0 + 3);
+ 
+@@ -1301,6 +1353,10 @@ work_stuff_copy_to_from (struct work_stu
+       memcpy (to->btypevec[i], from->btypevec[i], len);
+     }
+ 
++  if (from->proctypevec)
++    to->proctypevec =
++      XDUPVEC (int, from->proctypevec, from->proctypevec_size);
++
+   if (from->ntmpl_args)
+     to->tmpl_argvec = XNEWVEC (char *, from->ntmpl_args);
+ 
+@@ -1329,11 +1385,17 @@ delete_non_B_K_work_stuff (struct work_s
+   /* Discard the remembered types, if any.  */
+ 
+   forget_types (work);
+-  if (work -> typevec != NULL)
++  if (work->typevec != NULL)
++    {
++      free ((char *) work->typevec);
++      work->typevec = NULL;
++      work->typevec_size = 0;
++    }
++  if (work->proctypevec != NULL)
+     {
+-      free ((char *) work -> typevec);
+-      work -> typevec = NULL;
+-      work -> typevec_size = 0;
++      free (work->proctypevec);
++      work->proctypevec = NULL;
++      work->proctypevec_size = 0;
+     }
+   if (work->tmpl_argvec)
+     {
+@@ -1635,12 +1697,13 @@ demangle_signature (struct work_stuff *w
+ 					   0);
+ 	      if (!(work->constructor & 1))
+ 		expect_return_type = 1;
+-	      (*mangled)++;
++	      if (!**mangled)
++		success = 0;
++	      else
++	        (*mangled)++;
+ 	      break;
+ 	    }
+-	  else
+-	    /* fall through */
+-	    {;}
++	  /* fall through */
+ 
+ 	default:
+ 	  if (AUTO_DEMANGLING || GNU_DEMANGLING)
+@@ -2042,7 +2105,8 @@ demangle_template_value_parm (struct wor
+     }
+   else if (tk == tk_real)
+     success = demangle_real_value (work, mangled, s);
+-  else if (tk == tk_pointer || tk == tk_reference)
++  else if (tk == tk_pointer || tk == tk_reference
++	   || tk == tk_rvalue_reference)
+     {
+       if (**mangled == 'Q')
+ 	success = demangle_qualified (work, mangled, s,
+@@ -2051,7 +2115,8 @@ demangle_template_value_parm (struct wor
+       else
+ 	{
+ 	  int symbol_len  = consume_count (mangled);
+-	  if (symbol_len == -1)
++	  if (symbol_len == -1
++	      || symbol_len > (long) strlen (*mangled))
+ 	    return -1;
+ 	  if (symbol_len == 0)
+ 	    string_appendn (s, "0", 1);
+@@ -2114,6 +2179,8 @@ demangle_template (struct work_stuff *wo
+ 	{
+ 	  int idx;
+ 	  (*mangled)++;
++	  if (**mangled == '\0')
++	    return (0);
+ 	  (*mangled)++;
+ 
+ 	  idx = consume_count_with_underscores (mangled);
+@@ -2958,7 +3025,7 @@ gnu_special (struct work_stuff *work, co
+   int success = 1;
+   const char *p;
+ 
+-  if ((*mangled)[0] == '_'
++  if ((*mangled)[0] == '_' && (*mangled)[1] != '\0'
+       && strchr (cplus_markers, (*mangled)[1]) != NULL
+       && (*mangled)[2] == '_')
+     {
+@@ -2972,7 +3039,7 @@ gnu_special (struct work_stuff *work, co
+ 		&& (*mangled)[3] == 't'
+ 		&& (*mangled)[4] == '_')
+ 	       || ((*mangled)[1] == 'v'
+-		   && (*mangled)[2] == 't'
++		   && (*mangled)[2] == 't' && (*mangled)[3] != '\0'
+ 		   && strchr (cplus_markers, (*mangled)[3]) != NULL)))
+     {
+       /* Found a GNU style virtual table, get past "_vt<CPLUS_MARKER>"
+@@ -3552,6 +3619,8 @@ static int
+ do_type (struct work_stuff *work, const char **mangled, string *result)
+ {
+   int n;
++  int i;
++  int is_proctypevec;
+   int done;
+   int success;
+   string decl;
+@@ -3564,6 +3633,7 @@ do_type (struct work_stuff *work, const
+ 
+   done = 0;
+   success = 1;
++  is_proctypevec = 0;
+   while (success && !done)
+     {
+       int member;
+@@ -3588,6 +3658,14 @@ do_type (struct work_stuff *work, const
+ 	    tk = tk_reference;
+ 	  break;
+ 
++	  /* An rvalue reference type */
++	case 'O':
++	  (*mangled)++;
++	  string_prepend (&decl, "&&");
++	  if (tk == tk_none)
++	    tk = tk_rvalue_reference;
++	  break;
++
+ 	  /* An array */
+ 	case 'A':
+ 	  {
+@@ -3611,13 +3689,20 @@ do_type (struct work_stuff *work, const
+ 	/* A back reference to a previously seen type */
+ 	case 'T':
+ 	  (*mangled)++;
+-	  if (!get_count (mangled, &n) || n >= work -> ntypes)
++	  if (!get_count (mangled, &n) || n < 0 || n >= work -> ntypes)
+ 	    {
+ 	      success = 0;
+ 	    }
+ 	  else
+-	    {
+-	      remembered_type = work -> typevec[n];
++	    for (i = 0; i < work->nproctypes; i++)
++	      if (work -> proctypevec [i] == n)
++	        success = 0;
++
++	  if (success)
++	    {    
++	      is_proctypevec = 1;
++	      push_processed_type (work, n);
++	      remembered_type = work->typevec[n];
+ 	      mangled = &remembered_type;
+ 	    }
+ 	  break;
+@@ -3645,7 +3730,6 @@ do_type (struct work_stuff *work, const
+ 	  break;
+ 
+ 	case 'M':
+-	case 'O':
+ 	  {
+ 	    type_quals = TYPE_UNQUALIFIED;
+ 
+@@ -3725,11 +3809,12 @@ do_type (struct work_stuff *work, const
+ 		    break;
+ 		  }
+ 
+-		if (*(*mangled)++ != 'F')
++		if (*(*mangled) != 'F')
+ 		  {
+ 		    success = 0;
+ 		    break;
+ 		  }
++		(*mangled)++;
+ 	      }
+ 	    if ((member && !demangle_nested_args (work, mangled, &decl))
+ 		|| **mangled != '_')
+@@ -3789,7 +3874,7 @@ do_type (struct work_stuff *work, const
+     /* A back reference to a previously seen squangled type */
+     case 'B':
+       (*mangled)++;
+-      if (!get_count (mangled, &n) || n >= work -> numb)
++      if (!get_count (mangled, &n) || n < 0 || n >= work -> numb)
+ 	success = 0;
+       else
+ 	string_append (result, work->btypevec[n]);
+@@ -3840,6 +3925,9 @@ do_type (struct work_stuff *work, const
+     string_delete (result);
+   string_delete (&decl);
+ 
++  if (is_proctypevec)
++    pop_processed_type (work); 
++
+   if (success)
+     /* Assume an integral type, if we're not sure.  */
+     return (int) ((tk == tk_none) ? tk_integral : tk);
+@@ -3983,6 +4071,7 @@ demangle_fund_type (struct work_stuff *w
+ 	  success = 0;
+ 	  break;
+ 	}
++      /* fall through */
+     case 'I':
+       (*mangled)++;
+       if (**mangled == '_')
+@@ -4130,7 +4219,8 @@ do_hpacc_template_literal (struct work_s
+ 
+   literal_len = consume_count (mangled);
+ 
+-  if (literal_len <= 0)
++  if (literal_len <= 0
++      || literal_len > (long) strlen (*mangled))
+     return 0;
+ 
+   /* Literal parameters are names of arrays, functions, etc.  and the
+@@ -4252,6 +4342,41 @@ do_arg (struct work_stuff *work, const c
+ }
+ 
+ static void
++push_processed_type (struct work_stuff *work, int typevec_index)
++{
++  if (work->nproctypes >= work->proctypevec_size)
++    {
++      if (!work->proctypevec_size)
++	{
++	  work->proctypevec_size = 4;
++	  work->proctypevec = XNEWVEC (int, work->proctypevec_size);
++	}
++      else 
++	{
++	  if (work->proctypevec_size < 16)
++	    /* Double when small.  */
++	    work->proctypevec_size *= 2;
++	  else
++	    {
++	      /* Grow slower when large.  */
++	      if (work->proctypevec_size > (INT_MAX / 3) * 2)
++                xmalloc_failed (INT_MAX);
++              work->proctypevec_size = (work->proctypevec_size * 3 / 2);
++	    }   
++          work->proctypevec
++            = XRESIZEVEC (int, work->proctypevec, work->proctypevec_size);
++	}
++    }
++    work->proctypevec [work->nproctypes++] = typevec_index;
++}
++
++static void
++pop_processed_type (struct work_stuff *work)
++{
++  work->nproctypes--;
++}
++
++static void
+ remember_type (struct work_stuff *work, const char *start, int len)
+ {
+   char *tem;
+@@ -4515,10 +4640,13 @@ demangle_args (struct work_stuff *work,
+ 		{
+ 		  string_append (declp, ", ");
+ 		}
++	      push_processed_type (work, t);  
+ 	      if (!do_arg (work, &tem, &arg))
+ 		{
++		  pop_processed_type (work);
+ 		  return (0);
+ 		}
++	      pop_processed_type (work);
+ 	      if (PRINT_ARG_TYPES)
+ 		{
+ 		  string_appends (declp, &arg);
+Index: b/src/libiberty/hashtab.c
+===================================================================
+--- a/src/libiberty/hashtab.c
++++ b/src/libiberty/hashtab.c
+@@ -962,17 +962,17 @@ iterative_hash (const PTR k_in /* the ke
+   c += length;
+   switch(len)              /* all the case statements fall through */
+     {
+-    case 11: c+=((hashval_t)k[10]<<24);
+-    case 10: c+=((hashval_t)k[9]<<16);
+-    case 9 : c+=((hashval_t)k[8]<<8);
++    case 11: c+=((hashval_t)k[10]<<24);	/* fall through */
++    case 10: c+=((hashval_t)k[9]<<16);	/* fall through */
++    case 9 : c+=((hashval_t)k[8]<<8);	/* fall through */
+       /* the first byte of c is reserved for the length */
+-    case 8 : b+=((hashval_t)k[7]<<24);
+-    case 7 : b+=((hashval_t)k[6]<<16);
+-    case 6 : b+=((hashval_t)k[5]<<8);
+-    case 5 : b+=k[4];
+-    case 4 : a+=((hashval_t)k[3]<<24);
+-    case 3 : a+=((hashval_t)k[2]<<16);
+-    case 2 : a+=((hashval_t)k[1]<<8);
++    case 8 : b+=((hashval_t)k[7]<<24);	/* fall through */
++    case 7 : b+=((hashval_t)k[6]<<16);	/* fall through */
++    case 6 : b+=((hashval_t)k[5]<<8);	/* fall through */
++    case 5 : b+=k[4];			/* fall through */
++    case 4 : a+=((hashval_t)k[3]<<24);	/* fall through */
++    case 3 : a+=((hashval_t)k[2]<<16);	/* fall through */
++    case 2 : a+=((hashval_t)k[1]<<8);	/* fall through */
+     case 1 : a+=k[0];
+       /* case 0: nothing left to add */
+     }
+Index: b/src/libiberty/Makefile.in
+===================================================================
+--- a/src/libiberty/Makefile.in
++++ b/src/libiberty/Makefile.in
+@@ -146,6 +146,7 @@ CFILES = alloca.c argv.c asprintf.c atex
+ 	 pex-unix.c pex-win32.c						\
+          physmem.c putenv.c						\
+ 	random.c regex.c rename.c rindex.c				\
++	rust-demangle.c							\
+ 	safe-ctype.c setenv.c setproctitle.c sha1.c sigsetmask.c        \
+ 	 simple-object.c simple-object-coff.c simple-object-elf.c	\
+ 	 simple-object-mach-o.c simple-object-xcoff.c			\
+@@ -183,6 +184,7 @@ REQUIRED_OFILES =							\
+ 	./partition.$(objext) ./pexecute.$(objext) ./physmem.$(objext)	\
+ 	./pex-common.$(objext) ./pex-one.$(objext)			\
+ 	./@pexecute@.$(objext) ./vprintf-support.$(objext)		\
++	./rust-demangle.$(objext)					\
+ 	./safe-ctype.$(objext)						\
+ 	./simple-object.$(objext) ./simple-object-coff.$(objext)	\
+ 	./simple-object-elf.$(objext) ./simple-object-mach-o.$(objext)	\
+@@ -1188,6 +1190,17 @@ $(CONFIGURED_OFILES): stamp-picdir stamp
+ 	else true; fi
+ 	$(COMPILE.c) $(srcdir)/rindex.c $(OUTPUT_OPTION)
+ 
++./rust-demangle.$(objext): $(srcdir)/rust-demangle.c config.h \
++	$(INCDIR)/ansidecl.h $(INCDIR)/demangle.h $(INCDIR)/libiberty.h \
++	$(INCDIR)/safe-ctype.h
++	if [ x"$(PICFLAG)" != x ]; then \
++	  $(COMPILE.c) $(PICFLAG) $(srcdir)/rust-demangle.c -o pic/$@; \
++	else true; fi
++	if [ x"$(NOASANFLAG)" != x ]; then \
++	  $(COMPILE.c) $(PICFLAG) $(NOASANFLAG) $(srcdir)/rust-demangle.c -o noasan/$@; \
++	else true; fi
++	$(COMPILE.c) $(srcdir)/rust-demangle.c $(OUTPUT_OPTION)
++
+ ./safe-ctype.$(objext): $(srcdir)/safe-ctype.c $(INCDIR)/ansidecl.h \
+ 	$(INCDIR)/safe-ctype.h
+ 	if [ x"$(PICFLAG)" != x ]; then \
+Index: b/src/libiberty/make-relative-prefix.c
+===================================================================
+--- a/src/libiberty/make-relative-prefix.c
++++ b/src/libiberty/make-relative-prefix.c
+@@ -233,6 +233,7 @@ make_relative_prefix_1 (const char *prog
+   int i, n, common;
+   int needed_len;
+   char *ret = NULL, *ptr, *full_progname;
++  char *alloc_ptr = NULL;
+ 
+   if (progname == NULL || bin_prefix == NULL || prefix == NULL)
+     return NULL;
+@@ -256,7 +257,10 @@ make_relative_prefix_1 (const char *prog
+ #ifdef HAVE_HOST_EXECUTABLE_SUFFIX
+ 	  len += strlen (HOST_EXECUTABLE_SUFFIX);
+ #endif
+-	  nstore = (char *) alloca (len);
++	  if (len < MAX_ALLOCA_SIZE)
++	    nstore = (char *) alloca (len);
++	  else
++	    alloc_ptr = nstore = (char *) malloc (len);
+ 
+ 	  startp = endp = temp;
+ 	  while (1)
+@@ -312,12 +316,12 @@ make_relative_prefix_1 (const char *prog
+   else
+     full_progname = strdup (progname);
+   if (full_progname == NULL)
+-    return NULL;
++    goto bailout;
+ 
+   prog_dirs = split_directories (full_progname, &prog_num);
+   free (full_progname);
+   if (prog_dirs == NULL)
+-    return NULL;
++    goto bailout;
+ 
+   bin_dirs = split_directories (bin_prefix, &bin_num);
+   if (bin_dirs == NULL)
+@@ -395,6 +399,7 @@ make_relative_prefix_1 (const char *prog
+   free_split_directories (prog_dirs);
+   free_split_directories (bin_dirs);
+   free_split_directories (prefix_dirs);
++  free (alloc_ptr);
+ 
+   return ret;
+ }
+Index: b/src/libiberty/pex-win32.c
+===================================================================
+--- a/src/libiberty/pex-win32.c
++++ b/src/libiberty/pex-win32.c
+@@ -370,6 +370,8 @@ argv_to_cmdline (char *const *argv)
+ 	      cmdline_len++;
+ 	    }
+ 	}
++      if (j == 0)
++	needs_quotes = 1;
+       /* Trailing backslashes also need to be escaped because they will be
+          followed by the terminating quote.  */
+       if (needs_quotes)
+@@ -394,6 +396,8 @@ argv_to_cmdline (char *const *argv)
+               break;
+             }
+         }
++      if (j == 0)
++	needs_quotes = 1;
+ 
+       if (needs_quotes)
+         {
+Index: b/src/libiberty/regex.c
+===================================================================
+--- a/src/libiberty/regex.c
++++ b/src/libiberty/regex.c
+@@ -2493,6 +2493,7 @@ PREFIX(regex_compile) (const char *ARG_P
+           if ((syntax & RE_BK_PLUS_QM)
+               || (syntax & RE_LIMITED_OPS))
+             goto normal_char;
++	  /* Fall through.  */
+         handle_plus:
+         case '*':
+           /* If there is no previous pattern... */
+@@ -6697,6 +6698,7 @@ byte_re_match_2_internal (struct re_patt
+                 {
+                   case jump_n:
+ 		    is_a_jump_n = true;
++		    /* Fall through.  */
+                   case pop_failure_jump:
+ 		  case maybe_pop_jump:
+ 		  case jump:
+@@ -7125,7 +7127,7 @@ byte_re_match_2_internal (struct re_patt
+               DEBUG_PRINT1 ("  Match => jump.\n");
+ 	      goto unconditional_jump;
+ 	    }
+-        /* Note fall through.  */
++        /* Fall through.  */
+ 
+ 
+ 	/* The end of a simple repeat has a pop_failure_jump back to
+@@ -7150,7 +7152,7 @@ byte_re_match_2_internal (struct re_patt
+                                dummy_low_reg, dummy_high_reg,
+                                reg_dummy, reg_dummy, reg_info_dummy);
+           }
+-	  /* Note fall through.  */
++	  /* Fall through.  */
+ 
+ 	unconditional_jump:
+ #ifdef _LIBC
+@@ -7453,6 +7455,7 @@ byte_re_match_2_internal (struct re_patt
+                 {
+                 case jump_n:
+                   is_a_jump_n = true;
++		  /* Fall through.  */
+                 case maybe_pop_jump:
+                 case pop_failure_jump:
+                 case jump:
+@@ -7718,6 +7721,7 @@ PREFIX(common_op_match_null_string_p) (U
+ 
+     case set_number_at:
+       p1 += 2 * OFFSET_ADDRESS_SIZE;
++      return false;
+ 
+     default:
+       /* All other opcodes mean we cannot match the empty string.  */
+Index: b/src/libiberty/rust-demangle.c
+===================================================================
+--- /dev/null
++++ b/src/libiberty/rust-demangle.c
+@@ -0,0 +1,348 @@
++/* Demangler for the Rust programming language
++   Copyright 2016 Free Software Foundation, Inc.
++   Written by David Tolnay (dtolnay@gmail.com).
++
++This file is part of the libiberty library.
++Libiberty is free software; you can redistribute it and/or
++modify it under the terms of the GNU Library General Public
++License as published by the Free Software Foundation; either
++version 2 of the License, or (at your option) any later version.
++
++In addition to the permissions in the GNU Library General Public
++License, the Free Software Foundation gives you unlimited permission
++to link the compiled version of this file into combinations with other
++programs, and to distribute those combinations without any restriction
++coming from the use of this file.  (The Library Public License
++restrictions do apply in other respects; for example, they cover
++modification of the file, and distribution when not linked into a
++combined executable.)
++
++Libiberty is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++Library General Public License for more details.
++
++You should have received a copy of the GNU Library General Public
++License along with libiberty; see the file COPYING.LIB.
++If not, see <http://www.gnu.org/licenses/>.  */
++
++
++#ifdef HAVE_CONFIG_H
++#include "config.h"
++#endif
++
++#include "safe-ctype.h"
++
++#include <sys/types.h>
++#include <string.h>
++#include <stdio.h>
++
++#ifdef HAVE_STRING_H
++#include <string.h>
++#else
++extern size_t strlen(const char *s);
++extern int strncmp(const char *s1, const char *s2, size_t n);
++extern void *memset(void *s, int c, size_t n);
++#endif
++
++#include <demangle.h>
++#include "libiberty.h"
++
++
++/* Mangled Rust symbols look like this:
++     _$LT$std..sys..fd..FileDesc$u20$as$u20$core..ops..Drop$GT$::drop::hc68340e1baa4987a
++
++   The original symbol is:
++     <std::sys::fd::FileDesc as core::ops::Drop>::drop
++
++   The last component of the path is a 64-bit hash in lowercase hex,
++   prefixed with "h". Rust does not have a global namespace between
++   crates, an illusion which Rust maintains by using the hash to
++   distinguish things that would otherwise have the same symbol.
++
++   Any path component not starting with a XID_Start character is
++   prefixed with "_".
++
++   The following escape sequences are used:
++
++   ","  =>  $C$
++   "@"  =>  $SP$
++   "*"  =>  $BP$
++   "&"  =>  $RF$
++   "<"  =>  $LT$
++   ">"  =>  $GT$
++   "("  =>  $LP$
++   ")"  =>  $RP$
++   " "  =>  $u20$
++   "\"" =>  $u22$
++   "'"  =>  $u27$
++   "+"  =>  $u2b$
++   ";"  =>  $u3b$
++   "["  =>  $u5b$
++   "]"  =>  $u5d$
++   "{"  =>  $u7b$
++   "}"  =>  $u7d$
++   "~"  =>  $u7e$
++
++   A double ".." means "::" and a single "." means "-".
++
++   The only characters allowed in the mangled symbol are a-zA-Z0-9 and _.:$  */
++
++static const char *hash_prefix = "::h";
++static const size_t hash_prefix_len = 3;
++static const size_t hash_len = 16;
++
++static int is_prefixed_hash (const char *start);
++static int looks_like_rust (const char *sym, size_t len);
++static int unescape (const char **in, char **out, const char *seq, char value);
++
++/* INPUT: sym: symbol that has been through C++ (gnu v3) demangling
++
++   This function looks for the following indicators:
++
++   1. The hash must consist of "h" followed by 16 lowercase hex digits.
++
++   2. As a sanity check, the hash must use between 5 and 15 of the 16
++      possible hex digits. This is true of 99.9998% of hashes so once
++      in your life you may see a false negative. The point is to
++      notice path components that could be Rust hashes but are
++      probably not, like "haaaaaaaaaaaaaaaa". In this case a false
++      positive (non-Rust symbol has an important path component
++      removed because it looks like a Rust hash) is worse than a false
++      negative (the rare Rust symbol is not demangled) so this sets
++      the balance in favor of false negatives.
++
++   3. There must be no characters other than a-zA-Z0-9 and _.:$
++
++   4. There must be no unrecognized $-sign sequences.
++
++   5. There must be no sequence of three or more dots in a row ("...").  */
++
++int
++rust_is_mangled (const char *sym)
++{
++  size_t len, len_without_hash;
++
++  if (!sym)
++    return 0;
++
++  len = strlen (sym);
++  if (len <= hash_prefix_len + hash_len)
++    /* Not long enough to contain "::h" + hash + something else */
++    return 0;
++
++  len_without_hash = len - (hash_prefix_len + hash_len);
++  if (!is_prefixed_hash (sym + len_without_hash))
++    return 0;
++
++  return looks_like_rust (sym, len_without_hash);
++}
++
++/* A hash is the prefix "::h" followed by 16 lowercase hex digits. The
++   hex digits must comprise between 5 and 15 (inclusive) distinct
++   digits.  */
++
++static int
++is_prefixed_hash (const char *str)
++{
++  const char *end;
++  char seen[16];
++  size_t i;
++  int count;
++
++  if (strncmp (str, hash_prefix, hash_prefix_len))
++    return 0;
++  str += hash_prefix_len;
++
++  memset (seen, 0, sizeof(seen));
++  for (end = str + hash_len; str < end; str++)
++    if (*str >= '0' && *str <= '9')
++      seen[*str - '0'] = 1;
++    else if (*str >= 'a' && *str <= 'f')
++      seen[*str - 'a' + 10] = 1;
++    else
++      return 0;
++
++  /* Count how many distinct digits seen */
++  count = 0;
++  for (i = 0; i < 16; i++)
++    if (seen[i])
++      count++;
++
++  return count >= 5 && count <= 15;
++}
++
++static int
++looks_like_rust (const char *str, size_t len)
++{
++  const char *end = str + len;
++
++  while (str < end)
++    switch (*str)
++      {
++      case '$':
++	if (!strncmp (str, "$C$", 3))
++	  str += 3;
++	else if (!strncmp (str, "$SP$", 4)
++		 || !strncmp (str, "$BP$", 4)
++		 || !strncmp (str, "$RF$", 4)
++		 || !strncmp (str, "$LT$", 4)
++		 || !strncmp (str, "$GT$", 4)
++		 || !strncmp (str, "$LP$", 4)
++		 || !strncmp (str, "$RP$", 4))
++	  str += 4;
++	else if (!strncmp (str, "$u20$", 5)
++		 || !strncmp (str, "$u22$", 5)
++		 || !strncmp (str, "$u27$", 5)
++		 || !strncmp (str, "$u2b$", 5)
++		 || !strncmp (str, "$u3b$", 5)
++		 || !strncmp (str, "$u5b$", 5)
++		 || !strncmp (str, "$u5d$", 5)
++		 || !strncmp (str, "$u7b$", 5)
++		 || !strncmp (str, "$u7d$", 5)
++		 || !strncmp (str, "$u7e$", 5))
++	  str += 5;
++	else
++	  return 0;
++	break;
++      case '.':
++	/* Do not allow three or more consecutive dots */
++	if (!strncmp (str, "...", 3))
++	  return 0;
++	/* Fall through */
++      case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
++      case 'g': case 'h': case 'i': case 'j': case 'k': case 'l':
++      case 'm': case 'n': case 'o': case 'p': case 'q': case 'r':
++      case 's': case 't': case 'u': case 'v': case 'w': case 'x':
++      case 'y': case 'z':
++      case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
++      case 'G': case 'H': case 'I': case 'J': case 'K': case 'L':
++      case 'M': case 'N': case 'O': case 'P': case 'Q': case 'R':
++      case 'S': case 'T': case 'U': case 'V': case 'W': case 'X':
++      case 'Y': case 'Z':
++      case '0': case '1': case '2': case '3': case '4': case '5':
++      case '6': case '7': case '8': case '9':
++      case '_':
++      case ':':
++	str++;
++	break;
++      default:
++	return 0;
++      }
++
++  return 1;
++}
++
++/*
++  INPUT: sym: symbol for which rust_is_mangled(sym) returned 1.
++
++  The input is demangled in-place because the mangled name is always
++  longer than the demangled one.  */
++
++void
++rust_demangle_sym (char *sym)
++{
++  const char *in;
++  char *out;
++  const char *end;
++
++  if (!sym)
++    return;
++
++  in = sym;
++  out = sym;
++  end = sym + strlen (sym) - (hash_prefix_len + hash_len);
++
++  while (in < end)
++    switch (*in)
++      {
++      case '$':
++	if (!(unescape (&in, &out, "$C$", ',')
++	      || unescape (&in, &out, "$SP$", '@')
++	      || unescape (&in, &out, "$BP$", '*')
++	      || unescape (&in, &out, "$RF$", '&')
++	      || unescape (&in, &out, "$LT$", '<')
++	      || unescape (&in, &out, "$GT$", '>')
++	      || unescape (&in, &out, "$LP$", '(')
++	      || unescape (&in, &out, "$RP$", ')')
++	      || unescape (&in, &out, "$u20$", ' ')
++	      || unescape (&in, &out, "$u22$", '\"')
++	      || unescape (&in, &out, "$u27$", '\'')
++	      || unescape (&in, &out, "$u2b$", '+')
++	      || unescape (&in, &out, "$u3b$", ';')
++	      || unescape (&in, &out, "$u5b$", '[')
++	      || unescape (&in, &out, "$u5d$", ']')
++	      || unescape (&in, &out, "$u7b$", '{')
++	      || unescape (&in, &out, "$u7d$", '}')
++	      || unescape (&in, &out, "$u7e$", '~'))) {
++	  /* unexpected escape sequence, not looks_like_rust. */
++	  goto fail;
++	}
++	break;
++      case '_':
++	/* If this is the start of a path component and the next
++	   character is an escape sequence, ignore the underscore. The
++	   mangler inserts an underscore to make sure the path
++	   component begins with a XID_Start character. */
++	if ((in == sym || in[-1] == ':') && in[1] == '$')
++	  in++;
++	else
++	  *out++ = *in++;
++	break;
++      case '.':
++	if (in[1] == '.')
++	  {
++	    /* ".." becomes "::" */
++	    *out++ = ':';
++	    *out++ = ':';
++	    in += 2;
++	  }
++	else
++	  {
++	    /* "." becomes "-" */
++	    *out++ = '-';
++	    in++;
++	  }
++	break;
++      case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
++      case 'g': case 'h': case 'i': case 'j': case 'k': case 'l':
++      case 'm': case 'n': case 'o': case 'p': case 'q': case 'r':
++      case 's': case 't': case 'u': case 'v': case 'w': case 'x':
++      case 'y': case 'z':
++      case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
++      case 'G': case 'H': case 'I': case 'J': case 'K': case 'L':
++      case 'M': case 'N': case 'O': case 'P': case 'Q': case 'R':
++      case 'S': case 'T': case 'U': case 'V': case 'W': case 'X':
++      case 'Y': case 'Z':
++      case '0': case '1': case '2': case '3': case '4': case '5':
++      case '6': case '7': case '8': case '9':
++      case ':':
++	*out++ = *in++;
++	break;
++      default:
++	/* unexpected character in symbol, not looks_like_rust.  */
++	goto fail;
++      }
++  goto done;
++
++fail:
++  *out++ = '?'; /* This is pretty lame, but it's hard to do better. */
++done:
++  *out = '\0';
++}
++
++static int
++unescape (const char **in, char **out, const char *seq, char value)
++{
++  size_t len = strlen (seq);
++
++  if (strncmp (*in, seq, len))
++    return 0;
++
++  **out = value;
++
++  *in += len;
++  *out += 1;
++
++  return 1;
++}
+Index: b/src/libiberty/strndup.c
+===================================================================
+--- a/src/libiberty/strndup.c
++++ b/src/libiberty/strndup.c
+@@ -33,7 +33,7 @@ memory was available.  The result is alw
+ #include "ansidecl.h"
+ #include <stddef.h>
+ 
+-extern size_t	strlen (const char*);
++extern size_t	strnlen (const char *s, size_t maxlen);
+ extern PTR	malloc (size_t);
+ extern PTR	memcpy (PTR, const PTR, size_t);
+ 
+@@ -41,10 +41,7 @@ char *
+ strndup (const char *s, size_t n)
+ {
+   char *result;
+-  size_t len = strlen (s);
+-
+-  if (n < len)
+-    len = n;
++  size_t len = strnlen (s, n);
+ 
+   result = (char *) malloc (len + 1);
+   if (!result)
+Index: b/src/libiberty/testsuite/demangle-expected
+===================================================================
+--- a/src/libiberty/testsuite/demangle-expected
++++ b/src/libiberty/testsuite/demangle-expected
+@@ -31,6 +31,11 @@ ArrowLine::ArrowheadIntersects(Arrowhead
+ ArrowLine::ArrowheadIntersects
+ #
+ --format=gnu --no-params
++ArrowheadIntersects__9ArrowLineP9ArrowheadO6BoxObjP7Graphic
++ArrowLine::ArrowheadIntersects(Arrowhead *, BoxObj &&, Graphic *)
++ArrowLine::ArrowheadIntersects
++#
++--format=gnu --no-params
+ AtEnd__13ivRubberGroup
+ ivRubberGroup::AtEnd(void)
+ ivRubberGroup::AtEnd
+@@ -51,6 +56,11 @@ TextCode::CoreConstDecls(ostream &)
+ TextCode::CoreConstDecls
+ #
+ --format=gnu --no-params
++CoreConstDecls__8TextCodeO7ostream
++TextCode::CoreConstDecls(ostream &&)
++TextCode::CoreConstDecls
++#
++--format=gnu --no-params
+ Detach__8StateVarP12StateVarView
+ StateVar::Detach(StateVarView *)
+ StateVar::Detach
+@@ -66,21 +76,41 @@ RelateManip::Effect(ivEvent &)
+ RelateManip::Effect
+ #
+ --format=gnu --no-params
++Effect__11RelateManipO7ivEvent
++RelateManip::Effect(ivEvent &&)
++RelateManip::Effect
++#
++--format=gnu --no-params
+ FindFixed__FRP4CNetP4CNet
+ FindFixed(CNet *&, CNet *)
+ FindFixed
+ #
+ --format=gnu --no-params
++FindFixed__FOP4CNetP4CNet
++FindFixed(CNet *&&, CNet *)
++FindFixed
++#
++--format=gnu --no-params
+ Fix48_abort__FR8twolongs
+ Fix48_abort(twolongs &)
+ Fix48_abort
+ #
+ --format=gnu --no-params
++Fix48_abort__FO8twolongs
++Fix48_abort(twolongs &&)
++Fix48_abort
++#
++--format=gnu --no-params
+ GetBarInfo__15iv2_6_VScrollerP13ivPerspectiveRiT2
+ iv2_6_VScroller::GetBarInfo(ivPerspective *, int &, int &)
+ iv2_6_VScroller::GetBarInfo
+ #
+ --format=gnu --no-params
++GetBarInfo__15iv2_6_VScrollerP13ivPerspectiveOiT2
++iv2_6_VScroller::GetBarInfo(ivPerspective *, int &&, int &&)
++iv2_6_VScroller::GetBarInfo
++#
++--format=gnu --no-params
+ GetBgColor__C9ivPainter
+ ivPainter::GetBgColor(void) const
+ ivPainter::GetBgColor
+@@ -986,11 +1016,21 @@ List<VHDLEntity>::Pix::Pix(List<VHDLEnti
+ List<VHDLEntity>::Pix::Pix
+ #
+ --format=gnu --no-params
++__Q2t4List1Z10VHDLEntity3PixOCQ2t4List1Z10VHDLEntity3Pix
++List<VHDLEntity>::Pix::Pix(List<VHDLEntity>::Pix const &&)
++List<VHDLEntity>::Pix::Pix
++#
++--format=gnu --no-params
+ __Q2t4List1Z10VHDLEntity7elementRC10VHDLEntityPT0
+ List<VHDLEntity>::element::element(VHDLEntity const &, List<VHDLEntity>::element *)
+ List<VHDLEntity>::element::element
+ #
+ --format=gnu --no-params
++__Q2t4List1Z10VHDLEntity7elementOC10VHDLEntityPT0
++List<VHDLEntity>::element::element(VHDLEntity const &&, List<VHDLEntity>::element *)
++List<VHDLEntity>::element::element
++#
++--format=gnu --no-params
+ __Q2t4List1Z10VHDLEntity7elementRCQ2t4List1Z10VHDLEntity7element
+ List<VHDLEntity>::element::element(List<VHDLEntity>::element const &)
+ List<VHDLEntity>::element::element
+@@ -1036,6 +1076,11 @@ PixX<VHDLLibrary, VHDLLibraryRep, List<V
+ PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> >::PixX
+ #
+ --format=gnu --no-params
++__t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntityOCt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity
++PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> >::PixX(PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> > const &&)
++PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> >::PixX
++#
++--format=gnu --no-params
+ nextE__C11VHDLLibraryRt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity
+ VHDLLibrary::nextE(PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> > &) const
+ VHDLLibrary::nextE
+@@ -1261,6 +1306,11 @@ smanip_int::smanip_int(ios &(*)(ios &, i
+ smanip_int::smanip_int
+ #
+ --format=lucid --no-params
++__ct__10smanip_intFPFO3iosi_O3iosi
++smanip_int::smanip_int(ios &&(*)(ios &&, int), int)
++smanip_int::smanip_int
++#
++--format=lucid --no-params
+ __ct__11fstreambaseFi
+ fstreambase::fstreambase(int)
+ fstreambase::fstreambase
+@@ -1281,6 +1331,11 @@ smanip_long::smanip_long(ios &(*)(ios &,
+ smanip_long::smanip_long
+ #
+ --format=lucid --no-params
++__ct__11smanip_longFPFO3iosl_O3iosl
++smanip_long::smanip_long(ios &&(*)(ios &&, long), long)
++smanip_long::smanip_long
++#
++--format=lucid --no-params
+ __ct__11stdiostreamFP4FILE
+ stdiostream::stdiostream(FILE *)
+ stdiostream::stdiostream
+@@ -1321,6 +1376,11 @@ foo::foo(foo &)
+ foo::foo
+ #
+ --format=lucid --no-params
++__ct__3fooFO3foo
++foo::foo(foo &&)
++foo::foo
++#
++--format=lucid --no-params
+ __ct__3fooFi
+ foo::foo(int)
+ foo::foo
+@@ -1336,6 +1396,11 @@ foo::foo(int, foo &, int, foo &, int, fo
+ foo::foo
+ #
+ --format=lucid --no-params
++__ct__3fooFiO3fooT1T2T1T2
++foo::foo(int, foo &&, int, foo &&, int, foo &&)
++foo::foo
++#
++--format=lucid --no-params
+ __ct__3iosFP9streambuf
+ ios::ios(streambuf *)
+ ios::ios
+@@ -1811,6 +1876,11 @@ foo(int, foo &, int, foo &, int, foo &)
+ foo
+ #
+ --format=lucid --no-params
++foo__FiO3fooT1T2T1T2
++foo(int, foo &&, int, foo &&, int, foo &&)
++foo
++#
++--format=lucid --no-params
+ foo___3barFl
+ bar::foo_(long)
+ bar::foo_
+@@ -2561,6 +2631,11 @@ DListNode<RLabel &>::DListNode(RLabel &,
+ DListNode<RLabel &>::DListNode
+ #
+ --format=arm --no-params
++__ct__25DListNode__pt__9_O6RLabelFO6RLabelP25DListNode__pt__9_O6RLabelT2
++DListNode<RLabel &&>::DListNode(RLabel &&, DListNode<RLabel &&> *, DListNode<RLabel &&> *)
++DListNode<RLabel &&>::DListNode
++#
++--format=arm --no-params
+ bar__3fooFiT16FooBar
+ foo::bar(int, int, FooBar)
+ foo::bar
+@@ -2991,6 +3066,11 @@ DListNode<RLabel &>::DListNode(RLabel &,
+ DListNode<RLabel &>::DListNode
+ #
+ --format=hp --no-params
++__ct__9DListNodeXTO6RLabel__FO6RLabelP9DListNodeXTO6RLabel_T2
++DListNode<RLabel &&>::DListNode(RLabel &&, DListNode<RLabel &&> *, DListNode<RLabel &&> *)
++DListNode<RLabel &&>::DListNode
++#
++--format=hp --no-params
+ elem__6vectorXTiUP34__Fi
+ vector<int,34U>::elem(int)
+ vector<int,34U>::elem
+@@ -3021,16 +3101,31 @@ vector<int,-67,4000U,short &>::elem(int)
+ vector<int,-67,4000U,short &>::elem
+ #
+ --format=hp --no-params
++elem__6vectorXTiSN67UP4000TOs__Fi
++vector<int,-67,4000U,short &&>::elem(int)
++vector<int,-67,4000U,short &&>::elem
++#
++--format=hp --no-params
+ elem__6vectorXTiSN67TRdTFPv_i__Fi
+ vector<int,-67,double &,int (void *)>::elem(int)
+ vector<int,-67,double &,int (void *)>::elem
+ #
+ --format=hp --no-params
++elem__6vectorXTiSN67TOdTFPv_i__Fi
++vector<int,-67,double &&,int (void *)>::elem(int)
++vector<int,-67,double &&,int (void *)>::elem
++#
++--format=hp --no-params
+ X__6vectorXTiSN67TdTPvUP5TRs
+ vector<int,-67,double,void *,5U,short &>::X
+ vector<int,-67,double,void *,5U,short &>::X
+ #
+ --format=hp --no-params
++X__6vectorXTiSN67TdTPvUP5TOs
++vector<int,-67,double,void *,5U,short &&>::X
++vector<int,-67,double,void *,5U,short &&>::X
++#
++--format=hp --no-params
+ elem__6vectorXTiA3foo__Fi
+ vector<int,&foo>::elem(int)
+ vector<int,&foo>::elem
+@@ -3071,6 +3166,11 @@ Spec<int,int &,int>::spec(int *)
+ Spec<int,int &,int>::spec
+ #
+ --format=hp --no-params
++spec__17Spec<#1,#1.&&,#1>XTiTOiTi_FPi
++Spec<int,int &&,int>::spec(int *)
++Spec<int,int &&,int>::spec
++#
++--format=hp --no-params
+ add__XTc_FcT1
+ add<char>(char, char)
+ add<char>
+@@ -3101,6 +3201,11 @@ C<Test, Test::output> call<Test>(Test &)
+ C<Test, Test::output> call<Test>
+ #
+ --format=gnu --no-params
++call__H1Z4Test_OX01_t1C2ZX01PMX01FPX01i_vQ2X016output
++C<Test, Test::output> call<Test>(Test &&)
++C<Test, Test::output> call<Test>
++#
++--format=gnu --no-params
+ fn__FPQ21n1cPMQ21n1cFPQ21n1c_i
+ fn(n::c *, int (n::c::*)(n::c *))
+ fn
+@@ -3126,6 +3231,11 @@ int foo<TA<int const &, NA<9> > >(TA<int
+ int foo<TA<int const &, NA<9> > >
+ #
+ --format=gnu --no-params
++foo__H1Zt2TA2ZOCiZt2NA1Ui9_X01_i
++int foo<TA<int const &&, NA<9> > >(TA<int const &&, NA<9> >)
++int foo<TA<int const &&, NA<9> > >
++#
++--format=gnu --no-params
+ foo__H1Zt2TA2ZcZt2NA1Ui20_X01_i
+ int foo<TA<char, NA<20> > >(TA<char, NA<20> >)
+ int foo<TA<char, NA<20> > >
+@@ -3402,6 +3512,11 @@ int* const volatile restrict _far
+ _Z3fooILi2EEvRAplT_Li1E_i
+ void foo<2>(int (&) [(2)+(1)])
+ foo<2>
++#
++--format=gnu-v3 --no-params
++_Z3fooILi2EEvOAplT_Li1E_i
++void foo<2>(int (&&) [(2)+(1)])
++foo<2>
+ # 
+ --format=gnu-v3 --no-params
+ _Z1fM1AKFvvE
+@@ -4462,6 +4577,66 @@ __vt_90000000000cafebabe
+ 
+ _Z80800000000000000000000
+ _Z80800000000000000000000
++#
++# Tests write access violation PR70926
++
++0__Ot2m02R5T0000500000
++0__Ot2m02R5T0000500000
++#
++
++0__GT50000000000_
++0__GT50000000000_
++#
++
++__t2m05B500000000000000000_
++__t2m05B500000000000000000_
++#
++# Tests stack overflow PR71696
++
++__10%0__S4_0T0T0
++%0<>::%0(%0<>)
++
++# Inheriting constructor
++_ZN1DCI11BEi
++D::B(int)
++
++# exception-specification (C++17)
++_Z1fIvJiELb0EEvPDOT1_EFT_DpT0_E
++void f<void, int, false>(void (*)(int) noexcept(false))
++
++_Z1fIvJiELb0EEvPDoFT_DpT0_E
++void f<void, int, false>(void (*)(int) noexcept)
++
++_Z1fIvJiELb0EEvPDwiEFT_DpT0_E
++void f<void, int, false>(void (*)(int) throw(int))
++
++# Could crash
++_
++_
++
++# Could crash
++_vt
++_vt
++
++# Could crash
++_$_1Acitz
++_$_1Acitz
++
++# Could crash
++_$_H1R
++_$_H1R
++
++# Could crash
++_Q8ccQ4M2e.
++_Q8ccQ4M2e.
++
++# fold-expression with missing third component could crash.
++_Z12binary_rightIJLi1ELi2ELi3EEEv1AIXfRplT_LiEEE
++_Z12binary_rightIJLi1ELi2ELi3EEEv1AIXfRplT_LiEEE
++
++# ?: expression with missing third component could crash.
++AquT_quT_4mxautouT_4mxxx
++AquT_quT_4mxautouT_4mxxx
+ 
+ # pr c++/78252 generic lambda mangling uses template parms, and leads
+ # to unbounded recursion if not dealt with properly
+Index: b/src/libiberty/testsuite/Makefile.in
+===================================================================
+--- a/src/libiberty/testsuite/Makefile.in
++++ b/src/libiberty/testsuite/Makefile.in
+@@ -45,8 +45,8 @@ all:
+ # CHECK is set to "really_check" or the empty string by configure.
+ check: @CHECK@
+ 
+-really-check: check-cplus-dem check-d-demangle check-pexecute check-expandargv \
+-		check-strtol
++really-check: check-cplus-dem check-d-demangle check-rust-demangle \
++		check-pexecute check-expandargv check-strtol
+ 
+ # Run some tests of the demangler.
+ check-cplus-dem: test-demangle $(srcdir)/demangle-expected
+@@ -55,6 +55,9 @@ check-cplus-dem: test-demangle $(srcdir)
+ check-d-demangle: test-demangle $(srcdir)/d-demangle-expected
+ 	./test-demangle < $(srcdir)/d-demangle-expected
+ 
++check-rust-demangle: test-demangle $(srcdir)/rust-demangle-expected
++	./test-demangle < $(srcdir)/rust-demangle-expected
++
+ # Check the pexecute code.
+ check-pexecute: test-pexecute
+ 	./test-pexecute
+Index: b/src/libiberty/testsuite/rust-demangle-expected
+===================================================================
+--- /dev/null
++++ b/src/libiberty/testsuite/rust-demangle-expected
+@@ -0,0 +1,161 @@
++# This file holds test cases for the Rust demangler.
++# Each test case looks like this:
++#  options
++#  input to be demangled
++#  expected output
++#
++# See demangle-expected for documentation of supported options.
++#
++# A line starting with `#' is ignored.
++# However, blank lines in this file are NOT ignored.
++#
++############
++#
++# Coverage Tests
++#
++#
++# Demangles as rust symbol.
++--format=rust
++_ZN4main4main17he714a2e23ed7db23E
++main::main
++# Also demangles as c++ gnu v3 mangled symbol. But with extra Rust hash.
++--format=gnu-v3
++_ZN4main4main17he714a2e23ed7db23E
++main::main::he714a2e23ed7db23
++# But auto should demangle fully gnu-v3 -> rust -> demangled, not partially.
++--format=auto
++_ZN4main4main17he714a2e23ed7db23E
++main::main
++# Hash is exactly 16 hex chars. Not more.
++--format=auto
++_ZN4main4main18h1e714a2e23ed7db23E
++main::main::h1e714a2e23ed7db23
++# Not less.
++--format=auto
++_ZN4main4main16h714a2e23ed7db23E
++main::main::h714a2e23ed7db23
++# And not non-hex.
++--format=auto
++_ZN4main4main17he714a2e23ed7db2gE
++main::main::he714a2e23ed7db2g
++# $XX$ substitutions should not contain just numbers.
++--format=auto
++_ZN4main4$99$17he714a2e23ed7db23E
++main::$99$::he714a2e23ed7db23
++# _ at start of path should be removed.
++# ".." translates to "::" "$GT$" to ">" and "$LT$" to "<".
++--format=rust
++_ZN71_$LT$Test$u20$$u2b$$u20$$u27$static$u20$as$u20$foo..Bar$LT$Test$GT$$GT$3bar17h930b740aa94f1d3aE
++<Test + 'static as foo::Bar<Test>>::bar
++#
++--format=rust
++_ZN54_$LT$I$u20$as$u20$core..iter..traits..IntoIterator$GT$9into_iter17h8581507801fb8615E
++<I as core::iter::traits::IntoIterator>::into_iter
++#
++--format=rust
++_ZN10parse_tsan4main17hdbbfdf1c6a7e27d9E
++parse_tsan::main
++#
++--format=rust
++_ZN65_$LT$std..env..Args$u20$as$u20$core..iter..iterator..Iterator$GT$4next17h420a7c8d0c7eef40E
++<std::env::Args as core::iter::iterator::Iterator>::next
++#
++--format=rust
++_ZN4core3str9from_utf817hdcea28871313776dE
++core::str::from_utf8
++#
++--format=rust
++_ZN4core3mem7size_of17h18bde9bb8c22e2cfE
++core::mem::size_of
++#
++--format=rust
++_ZN5alloc4heap8allocate17hd55c03e6cb81d924E
++alloc::heap::allocate
++#
++--format=rust
++_ZN4core3ptr8null_mut17h736cce09ca0ac11aE
++core::ptr::null_mut
++#
++--format=rust
++_ZN4core3ptr31_$LT$impl$u20$$BP$mut$u20$T$GT$7is_null17h7f9de798bc3f0879E
++core::ptr::<impl *mut T>::is_null
++#
++--format=rust
++_ZN40_$LT$alloc..raw_vec..RawVec$LT$T$GT$$GT$6double17h4166e2b47539e1ffE
++<alloc::raw_vec::RawVec<T>>::double
++#
++--format=rust
++_ZN39_$LT$collections..vec..Vec$LT$T$GT$$GT$4push17hd4b6b23c1b88141aE
++<collections::vec::Vec<T>>::push
++#
++--format=rust
++_ZN70_$LT$collections..vec..Vec$LT$T$GT$$u20$as$u20$core..ops..DerefMut$GT$9deref_mut17hf299b860dc5a831cE
++<collections::vec::Vec<T> as core::ops::DerefMut>::deref_mut
++#
++--format=rust
++_ZN63_$LT$core..ptr..Unique$LT$T$GT$$u20$as$u20$core..ops..Deref$GT$5deref17hc784b4a166cb5e5cE
++<core::ptr::Unique<T> as core::ops::Deref>::deref
++#
++--format=rust
++_ZN40_$LT$alloc..raw_vec..RawVec$LT$T$GT$$GT$3ptr17h7570b6e9070b693bE
++<alloc::raw_vec::RawVec<T>>::ptr
++#
++--format=rust
++_ZN4core3ptr31_$LT$impl$u20$$BP$mut$u20$T$GT$7is_null17h0f3228f343444ac8E
++core::ptr::<impl *mut T>::is_null
++#
++--format=rust
++_ZN53_$LT$$u5b$T$u5d$$u20$as$u20$core..slice..SliceExt$GT$10as_mut_ptr17h153241df1c7d1666E
++<[T] as core::slice::SliceExt>::as_mut_ptr
++#
++--format=rust
++_ZN11collections5slice29_$LT$impl$u20$$u5b$T$u5d$$GT$10as_mut_ptr17hf12a6d0409938c96E
++collections::slice::<impl [T]>::as_mut_ptr
++#
++--format=rust
++_ZN4core3ptr5write17h651fe53ec860e780E
++core::ptr::write
++#
++--format=rust
++_ZN65_$LT$std..env..Args$u20$as$u20$core..iter..iterator..Iterator$GT$4next17h420a7c8d0c7eef40E
++<std::env::Args as core::iter::iterator::Iterator>::next
++#
++--format=rust
++_ZN54_$LT$I$u20$as$u20$core..iter..traits..IntoIterator$GT$9into_iter17he06cb713aae5b465E
++<I as core::iter::traits::IntoIterator>::into_iter
++#
++--format=rust
++_ZN71_$LT$collections..vec..IntoIter$LT$T$GT$$u20$as$u20$core..ops..Drop$GT$4drop17hf7f23304ebe62eedE
++<collections::vec::IntoIter<T> as core::ops::Drop>::drop
++#
++--format=rust
++_ZN86_$LT$collections..vec..IntoIter$LT$T$GT$$u20$as$u20$core..iter..iterator..Iterator$GT$4next17h04b3fbf148c39713E
++<collections::vec::IntoIter<T> as core::iter::iterator::Iterator>::next
++#
++--format=rust
++_ZN75_$LT$$RF$$u27$a$u20$mut$u20$I$u20$as$u20$core..iter..iterator..Iterator$GT$4next17ha050492063e0fd20E
++<&'a mut I as core::iter::iterator::Iterator>::next
++# Different hashes are OK, they are just stripped.
++--format=rust
++_ZN13drop_contents17hfe3c0a68c8ad1c74E
++drop_contents
++#
++--format=rust
++_ZN13drop_contents17h48cb59bef15bb555E
++drop_contents
++#
++--format=rust
++_ZN4core3mem7size_of17h900b33157bf58f26E
++core::mem::size_of
++#
++--format=rust
++_ZN67_$LT$alloc..raw_vec..RawVec$LT$T$GT$$u20$as$u20$core..ops..Drop$GT$4drop17h96a5cf6e94807905E
++<alloc::raw_vec::RawVec<T> as core::ops::Drop>::drop
++#
++--format=rust
++_ZN68_$LT$core..nonzero..NonZero$LT$T$GT$$u20$as$u20$core..ops..Deref$GT$5deref17hc49056f882aa46dbE
++<core::nonzero::NonZero<T> as core::ops::Deref>::deref
++#
++--format=rust
++_ZN63_$LT$core..ptr..Unique$LT$T$GT$$u20$as$u20$core..ops..Deref$GT$5deref17h19f2ad4920655e85E
++<core::ptr::Unique<T> as core::ops::Deref>::deref
+Index: b/src/libiberty/testsuite/test-pexecute.c
+===================================================================
+--- a/src/libiberty/testsuite/test-pexecute.c
++++ b/src/libiberty/testsuite/test-pexecute.c
+@@ -285,6 +285,20 @@ main (int argc, char **argv)
+     ERROR ("echo exit status failed");
+   pex_free (pex1);
+ 
++  /* Check empty parameters don't get lost.  */
++  pex1 = TEST_PEX_INIT (PEX_USE_PIPES, "temp");
++  subargv[1] = "echo";
++  subargv[2] = "foo";
++  subargv[3] = "";
++  subargv[4] = "bar";
++  subargv[5] = NULL;
++  TEST_PEX_RUN (pex1, 0, "./test-pexecute", subargv, NULL, NULL);
++  e = TEST_PEX_READ_OUTPUT (pex1);
++  CHECK_LINE (e, "foo  bar");  /* Two spaces!  */
++  if (TEST_PEX_GET_STATUS_1 (pex1) != 0)
++    ERROR ("echo exit status failed");
++  pex_free (pex1);
++
+   pex1 = TEST_PEX_INIT (PEX_USE_PIPES, "temp");
+   subargv[1] = "echo";
+   subargv[2] = "bar";
+Index: b/src/libiberty/xmemdup.c
+===================================================================
+--- a/src/libiberty/xmemdup.c
++++ b/src/libiberty/xmemdup.c
+@@ -1,4 +1,4 @@
+-/* xmemdup.c -- Duplicate a memory buffer, using xcalloc.
++/* xmemdup.c -- Duplicate a memory buffer, using xmalloc.
+    This trivial function is in the public domain.
+    Jeff Garzik, September 1999.  */
+ 
+@@ -34,6 +34,8 @@ allocated, the remaining memory is zeroe
+ PTR
+ xmemdup (const PTR input, size_t copy_size, size_t alloc_size)
+ {
+-  PTR output = xcalloc (1, alloc_size);
++  PTR output = xmalloc (alloc_size);
++  if (alloc_size > copy_size)
++    memset ((char *) output + copy_size, 0, alloc_size - copy_size);
+   return (PTR) memcpy (output, input, copy_size);
+ }
+Index: b/src/libiberty/xstrndup.c
+===================================================================
+--- a/src/libiberty/xstrndup.c
++++ b/src/libiberty/xstrndup.c
+@@ -48,10 +48,7 @@ char *
+ xstrndup (const char *s, size_t n)
+ {
+   char *result;
+-  size_t len = strlen (s);
+-
+-  if (n < len)
+-    len = n;
++  size_t len = strnlen (s, n);
+ 
+   result = XNEWVEC (char, len + 1);
+ 
+Index: b/src/include/libiberty.h
+===================================================================
+--- a/src/include/libiberty.h
++++ b/src/include/libiberty.h
+@@ -397,6 +397,17 @@ extern void hex_init (void);
+ /* Save files used for communication between processes.  */
+ #define PEX_SAVE_TEMPS		0x4
+ 
++/* Max number of alloca bytes per call before we must switch to malloc.
++
++   ?? Swiped from gnulib's regex_internal.h header.  Is this actually
++   the case?  This number seems arbitrary, though sane.
++
++   The OS usually guarantees only one guard page at the bottom of the stack,
++   and a page size can be as small as 4096 bytes.  So we cannot safely
++   allocate anything larger than 4096 bytes.  Also care for the possibility
++   of a few compiler-allocated temporary stack slots.  */
++#define MAX_ALLOCA_SIZE	4032
++
+ /* Prepare to execute one or more programs, with standard output of
+    each program fed to standard input of the next.
+    FLAGS	As above.
+Index: b/src/include/demangle.h
+===================================================================
+--- a/src/include/demangle.h
++++ b/src/include/demangle.h
+@@ -63,9 +63,10 @@ extern "C" {
+ #define DMGL_GNU_V3	 (1 << 14)
+ #define DMGL_GNAT	 (1 << 15)
+ #define DMGL_DLANG	 (1 << 16)
++#define DMGL_RUST	 (1 << 17)	/* Rust wraps GNU_V3 style mangling.  */
+ 
+ /* If none of these are set, use 'current_demangling_style' as the default. */
+-#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG)
++#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG|DMGL_RUST)
+ 
+ /* Enumeration of possible demangling styles.
+ 
+@@ -88,7 +89,8 @@ extern enum demangling_styles
+   gnu_v3_demangling = DMGL_GNU_V3,
+   java_demangling = DMGL_JAVA,
+   gnat_demangling = DMGL_GNAT,
+-  dlang_demangling = DMGL_DLANG
++  dlang_demangling = DMGL_DLANG,
++  rust_demangling = DMGL_RUST
+ } current_demangling_style;
+ 
+ /* Define string names for the various demangling styles. */
+@@ -104,6 +106,7 @@ extern enum demangling_styles
+ #define JAVA_DEMANGLING_STYLE_STRING          "java"
+ #define GNAT_DEMANGLING_STYLE_STRING          "gnat"
+ #define DLANG_DEMANGLING_STYLE_STRING         "dlang"
++#define RUST_DEMANGLING_STYLE_STRING          "rust"
+ 
+ /* Some macros to test what demangling style is active. */
+ 
+@@ -118,6 +121,7 @@ extern enum demangling_styles
+ #define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA)
+ #define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT)
+ #define DLANG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_DLANG)
++#define RUST_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_RUST)
+ 
+ /* Provide information about the available demangle styles. This code is
+    pulled from gdb into libiberty because it is useful to binutils also.  */
+@@ -175,6 +179,27 @@ ada_demangle (const char *mangled, int o
+ extern char *
+ dlang_demangle (const char *mangled, int options);
+ 
++/* Returns non-zero iff MANGLED is a rust mangled symbol.  MANGLED must
++   already have been demangled through cplus_demangle_v3.  If this function
++   returns non-zero then MANGLED can be demangled (in-place) using
++   RUST_DEMANGLE_SYM.  */
++extern int
++rust_is_mangled (const char *mangled);
++
++/* Demangles SYM (in-place) if RUST_IS_MANGLED returned non-zero for SYM.
++   If RUST_IS_MANGLED returned zero for SYM then RUST_DEMANGLE_SYM might
++   replace characters that cannot be demangled with '?' and might truncate
++   SYM.  After calling RUST_DEMANGLE_SYM SYM might be shorter, but never
++   larger.  */
++extern void
++rust_demangle_sym (char *sym);
++
++/* Demangles MANGLED if it was GNU_V3 and then RUST mangled, otherwise
++   returns NULL. Uses CPLUS_DEMANGLE_V3, RUST_IS_MANGLED and
++   RUST_DEMANGLE_SYM.  Returns a new string that is owned by the caller.  */
++extern char *
++rust_demangle (const char *mangled, int options);
++
+ enum gnu_v3_ctor_kinds {
+   gnu_v3_complete_object_ctor = 1,
+   gnu_v3_base_object_ctor,
+@@ -449,7 +474,9 @@ enum demangle_component_type
+   /* A transaction-safe function type.  */
+   DEMANGLE_COMPONENT_TRANSACTION_SAFE,
+   /* A cloned function.  */
+-  DEMANGLE_COMPONENT_CLONE
++  DEMANGLE_COMPONENT_CLONE,
++  DEMANGLE_COMPONENT_NOEXCEPT,
++  DEMANGLE_COMPONENT_THROW_SPEC
+ };
+ 
+ /* Types which are only used internally.  */
--- gcc-6-6.3.0.orig/debian/patches/libitm-no-fortify-source.diff
+++ gcc-6-6.3.0/debian/patches/libitm-no-fortify-source.diff
@@ -0,0 +1,19 @@
+# DP: Build libitm with -U_FORTIFY_SOURCE on x86 and x86_64.
+
+Index: b/src/libitm/configure.tgt
+===================================================================
+--- a/src/libitm/configure.tgt
++++ b/src/libitm/configure.tgt
+@@ -119,6 +119,12 @@ case "${target_cpu}" in
+ 	;;
+ esac
+ 
++# FIXME: ftbfs with -D_FORTIFY_SOURCE (error: invalid use of '__builtin_va_arg_pack ())
++case "${target}" in
++  *-*-linux*)
++	XCFLAGS="${XCFLAGS} -U_FORTIFY_SOURCE"
++esac
++
+ # For the benefit of top-level configure, determine if the cpu is supported.
+ test -d ${srcdir}/config/$ARCH || UNSUPPORTED=1
+ 
--- gcc-6-6.3.0.orig/debian/patches/libjava-armel-unwind.diff
+++ gcc-6-6.3.0/debian/patches/libjava-armel-unwind.diff
@@ -0,0 +1,19 @@
+# DP: On armel, apply kludge to fix unwinder infinitely looping 'til it runs out
+# DP: of memory (http://gcc.gnu.org/ml/java/2008-06/msg00010.html).
+
+---
+ libjava/stacktrace.cc |    3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+--- a/src/libjava/stacktrace.cc
++++ b/src/libjava/stacktrace.cc
+@@ -115,6 +115,9 @@ _Jv_StackTrace::UnwindTraceFn (struct _Unwind_Context *context, void *state_ptr)
+   // Check if the trace buffer needs to be extended.
+   if (pos == state->length)
+     {
++      // http://gcc.gnu.org/ml/java/2008-06/msg00010.html
++      return _URC_END_OF_STACK;
++
+       int newLength = state->length * 2;
+       void *newFrames = _Jv_AllocBytes (newLength * sizeof(_Jv_StackFrame));
+       memcpy (newFrames, state->frames, state->length * sizeof(_Jv_StackFrame));      
--- gcc-6-6.3.0.orig/debian/patches/libjava-disable-plugin.diff
+++ gcc-6-6.3.0/debian/patches/libjava-disable-plugin.diff
@@ -0,0 +1,15 @@
+# DP: Don't build the gcjwebplugin, even when configured with --enable-plugin
+
+Index: b/src/libjava/configure.ac
+===================================================================
+--- a/src/libjava/configure.ac
++++ b/src/libjava/configure.ac
+@@ -70,6 +70,8 @@ AC_ARG_ENABLE(browser-plugin,
+      esac],
+     [browser_plugin_enabled=no]
+ )
++# FIXME: don't build the plugin, this option collides with GCC plugin support
++plugin_enabled=no
+ 
+ AC_ARG_ENABLE(gconf-peer,
+   AS_HELP_STRING([--enable-gconf-peer],
--- gcc-6-6.3.0.orig/debian/patches/libjava-fixed-symlinks.diff
+++ gcc-6-6.3.0/debian/patches/libjava-fixed-symlinks.diff
@@ -0,0 +1,28 @@
+# DP: Remove unneed '..' elements from symlinks in JAVA_HOME
+
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -836,7 +836,7 @@ if CREATE_JAVA_HOME
+ 	$(mkinstalldirs) $(DESTDIR)$(SDK_INCLUDE_DIR)/$(OS)
+ 	relative() { \
+ 	  $(PERL) -e 'use File::Spec; \
+-	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2; \
++	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2 | sed -r 's,(bin|lib)[^/]*/\.\./,,'; \
+ 	}; \
+ 	RELATIVE=$$(relative $(DESTDIR)$(bindir) $(DESTDIR)$(SDK_BIN_DIR)); \
+ 	ln -sf $$RELATIVE/`echo gij | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'` \
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -12552,7 +12552,7 @@ install-data-local:
+ @CREATE_JAVA_HOME_TRUE@	$(mkinstalldirs) $(DESTDIR)$(SDK_INCLUDE_DIR)/$(OS)
+ @CREATE_JAVA_HOME_TRUE@	relative() { \
+ @CREATE_JAVA_HOME_TRUE@	  $(PERL) -e 'use File::Spec; \
+-@CREATE_JAVA_HOME_TRUE@	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2; \
++@CREATE_JAVA_HOME_TRUE@	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2 | sed -r 's,(bin|lib)[^/]*/\.\./,,'; \
+ @CREATE_JAVA_HOME_TRUE@	}; \
+ @CREATE_JAVA_HOME_TRUE@	RELATIVE=$$(relative $(DESTDIR)$(bindir) $(DESTDIR)$(SDK_BIN_DIR)); \
+ @CREATE_JAVA_HOME_TRUE@	ln -sf $$RELATIVE/`echo gij | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'` \
--- gcc-6-6.3.0.orig/debian/patches/libjava-jnipath.diff
+++ gcc-6-6.3.0/debian/patches/libjava-jnipath.diff
@@ -0,0 +1,129 @@
+# DP: - Add /usr/lib/jni and /usr/lib/<multiarch>/jni to java.library.path.
+# DP: - When running the i386 binaries on amd64, look in
+# DP: - /usr/lib32/gcj-x.y and /usr/lib32/jni instead.
+
+Index: b/src/libjava/configure.ac
+===================================================================
+--- a/src/libjava/configure.ac
++++ b/src/libjava/configure.ac
+@@ -1475,6 +1475,9 @@ AC_CHECK_SIZEOF(void *)
+ 
+ AC_C_BIGENDIAN
+ 
++MULTIARCH_DIR=$(dpkg-architecture -qDEB_HOST_MULTIARCH 2>/dev/null || true)
++AC_SUBST(MULTIARCH_DIR)
++
+ ZLIBS=
+ SYS_ZLIBS=
+ ZINCS=
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -364,6 +364,7 @@ AM_CXXFLAGS = \
+ 	$(WARNINGS) \
+ 	-D_GNU_SOURCE \
+ 	-DPREFIX="\"$(prefix)\"" \
++	-DMULTIARCH_DIR="\"$(MULTIARCH_DIR)\"" \
+ 	-DTOOLEXECLIBDIR="\"$(toolexeclibdir)\"" \
+         -DJAVA_HOME="\"$(JAVA_HOME_DIR)\"" \
+         -DBOOT_CLASS_PATH="\"$(BOOT_CLASS_PATH_DIR)\"" \
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -667,6 +667,7 @@ MAINT = @MAINT@
+ MAKE = @MAKE@
+ MAKEINFO = @MAKEINFO@
+ MKDIR_P = @MKDIR_P@
++MULTIARCH_DIR = @MULTIARCH_DIR@
+ NM = nm
+ NMEDIT = @NMEDIT@
+ OBJDUMP = @OBJDUMP@
+@@ -1050,6 +1051,7 @@ AM_CXXFLAGS = \
+ 	$(WARNINGS) \
+ 	-D_GNU_SOURCE \
+ 	-DPREFIX="\"$(prefix)\"" \
++	-DMULTIARCH_DIR="\"$(MULTIARCH_DIR)\"" \
+ 	-DTOOLEXECLIBDIR="\"$(toolexeclibdir)\"" \
+         -DJAVA_HOME="\"$(JAVA_HOME_DIR)\"" \
+         -DBOOT_CLASS_PATH="\"$(BOOT_CLASS_PATH_DIR)\"" \
+Index: b/src/libjava/gnu/classpath/natSystemProperties.cc
+===================================================================
+--- a/src/libjava/gnu/classpath/natSystemProperties.cc
++++ b/src/libjava/gnu/classpath/natSystemProperties.cc
+@@ -141,6 +141,44 @@ PrependVersionedLibdir (::java::lang::St
+   return retval;
+ }
+ 
++static char*
++AppendJniLibdir (char *path, struct utsname *u)
++{
++  char* retval;
++  const char* jnilibdir = "/usr/lib/jni";
++#ifdef MULTIARCH_DIR
++  const char* jnilibdir2 = "/usr/lib/" MULTIARCH_DIR "/jni";
++  jsize len2 = strlen (jnilibdir2) + 2;
++#else
++  jsize len2 = 0;
++#endif
++
++#if defined(__linux__) && defined (__i386__)
++  if (! strcmp ("x86_64", u->machine))
++    jnilibdir = "/usr/lib32/jni";
++#endif
++
++  if (path)
++    {
++      jsize total = strlen (path)
++	+ (sizeof (PATH_SEPARATOR) - 1) + strlen (jnilibdir) +len2 + 1;
++      retval = (char*) _Jv_Malloc (total);
++      strcpy (retval, path);
++      strcat (retval, PATH_SEPARATOR);
++      strcat (retval, jnilibdir);
++    }
++  else
++    {
++      retval = (char*) _Jv_Malloc (strlen (jnilibdir) + len2 + 1);
++      strcpy (retval, jnilibdir);
++    }
++#ifdef MULTIARCH_DIR
++  strcat (retval, PATH_SEPARATOR);
++  strcat (retval, jnilibdir2);
++#endif
++  return retval;
++}
++
+ void
+ gnu::classpath::SystemProperties::insertSystemProperties (::java::util::Properties *newprops)
+ {
+@@ -373,8 +411,13 @@ gnu::classpath::SystemProperties::insert
+       // Prepend GCJ_VERSIONED_LIBDIR to the module load path so that
+       // libgcj will find its own JNI libraries, like libgtkpeer.so.
+       char* val = PrependVersionedLibdir (path);
+-      _Jv_SetDLLSearchPath (val);
++
++      // Append jnilibdir
++      char* val2 = AppendJniLibdir (val, &u);
++
++      _Jv_SetDLLSearchPath (val2);
+       _Jv_Free (val);
++      _Jv_Free (val2);
+     }
+   else
+     {
+@@ -382,9 +425,12 @@ gnu::classpath::SystemProperties::insert
+ #ifdef USE_LTDL
+       char *libpath = getenv (LTDL_SHLIBPATH_VAR);
+       char* val = _Jv_PrependVersionedLibdir (libpath);
+-      SET ("java.library.path", val);
+-      _Jv_SetDLLSearchPath (val);
++      // Append jnilibdir
++      char* val2 = AppendJniLibdir (val, &u);
++      SET ("java.library.path", val2);
++      _Jv_SetDLLSearchPath (val2);
+       _Jv_Free (val);
++      _Jv_Free (val2);
+ #else
+       SET ("java.library.path", "");
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/libjava-mips64el.diff
+++ gcc-6-6.3.0/debian/patches/libjava-mips64el.diff
@@ -0,0 +1,58 @@
+2016-07-13  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* java/lang/reflect/natVMProxy.cc (unbox): Use ffi_arg for
+	integer return types smaller than a word.
+
+2016-07-13  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* interpret-run.cc: Use ffi_arg for FFI integer return types.
+
+--- a/src/libjava/interpret-run.cc
++++ b/src/libjava/interpret-run.cc
+@@ -1838,7 +1838,7 @@ details.  */
+       return;
+ 
+     insn_ireturn:
+-      *(jint *) retp = POPI ();
++      *(ffi_arg *) retp = POPI ();
+       return;
+ 
+     insn_return:
+--- a/src/libjava/java/lang/reflect/natVMProxy.cc
++++ b/src/libjava/java/lang/reflect/natVMProxy.cc
+@@ -272,17 +272,17 @@ unbox (jobject o, jclass klass, void *rvalue, FFI_TYPE type)
+   if (klass == JvPrimClass (byte))
+     {
+       _Jv_CheckCast (&Byte::class$, o);
+-      *(jbyte*)rvalue = ((Byte*)o)->byteValue();
++      *(ffi_arg*)rvalue = ((Byte*)o)->byteValue();
+     }
+   else if (klass == JvPrimClass (short))
+     {
+       _Jv_CheckCast (&Short::class$, o);
+-      *(jshort*)rvalue = ((Short*)o)->shortValue();
++      *(ffi_arg*)rvalue = ((Short*)o)->shortValue();
+     }
+   else if (klass == JvPrimClass (int))
+     {
+       _Jv_CheckCast (&Integer::class$, o);
+-      *(jint*)rvalue = ((Integer*)o)->intValue();
++      *(ffi_arg*)rvalue = ((Integer*)o)->intValue();
+     }
+   else if (klass == JvPrimClass (long))
+     {
+@@ -302,12 +302,12 @@ unbox (jobject o, jclass klass, void *rvalue, FFI_TYPE type)
+   else if (klass == JvPrimClass (boolean))
+     {
+       _Jv_CheckCast (&Boolean::class$, o);
+-      *(jboolean*)rvalue = ((Boolean*)o)->booleanValue();
++      *(ffi_arg*)rvalue = ((Boolean*)o)->booleanValue();
+     }
+   else if (klass == JvPrimClass (char))
+     {
+       _Jv_CheckCast (&Character::class$, o);
+-      *(jchar*)rvalue = ((Character*)o)->charValue();
++      *(ffi_arg*)rvalue = ((Character*)o)->charValue();
+     }
+   else
+     JvFail ("Bad ffi type in proxy");
--- gcc-6-6.3.0.orig/debian/patches/libjava-multiarch.diff
+++ gcc-6-6.3.0/debian/patches/libjava-multiarch.diff
@@ -0,0 +1,82 @@
+# DP: Install libjava libraries to multiarch location
+
+Index: b/src/libjava/configure.ac
+===================================================================
+--- a/src/libjava/configure.ac
++++ b/src/libjava/configure.ac
+@@ -1535,6 +1535,10 @@ case ${version_specific_libs} in
+       .) toolexeclibdir=$toolexecmainlibdir ;; # Avoid trailing /.
+       *) toolexeclibdir=$toolexecmainlibdir/$multi_os_directory ;;
+     esac
++    multiarch=`$CC -print-multiarch`
++    if test -n "$multiarch"; then
++        toolexeclibdir=$toolexecmainlibdir/$multiarch
++    fi
+     ;;
+ esac
+ AC_SUBST(toolexecdir)
+@@ -1552,6 +1556,10 @@ AC_DEFINE_UNQUOTED(GCJVERSION, "$GCJVERS
+ # libraries are found.
+ gcjsubdir=gcj-$gcjversion-$libgcj_soversion
+ dbexecdir='$(toolexeclibdir)/'$gcjsubdir
++multiarch=`$CC -print-multiarch`
++if test -n "$multiarch"; then
++    dbexecdir='$(libdir)/'$multiarch/$gcjsubdir
++fi
+ AC_SUBST(dbexecdir)
+ AC_SUBST(gcjsubdir)
+ 
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -373,7 +373,7 @@ AM_CXXFLAGS = \
+ 	-DGCJ_VERSIONED_LIBDIR="\"$(dbexecdir)\"" \
+ 	-DPATH_SEPARATOR="\"$(CLASSPATH_SEPARATOR)\"" \
+ 	-DECJ_JAR_FILE="\"$(ECJ_JAR)\"" \
+-	-DLIBGCJ_DEFAULT_DATABASE="\"$(dbexecdir)/$(db_name)\"" \
++	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-6/$(db_name)\"" \
+ 	-DLIBGCJ_DEFAULT_DATABASE_PATH_TAIL="\"$(db_pathtail)\""
+ 
+ AM_GCJFLAGS = \
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -1060,7 +1060,7 @@ AM_CXXFLAGS = \
+ 	-DGCJ_VERSIONED_LIBDIR="\"$(dbexecdir)\"" \
+ 	-DPATH_SEPARATOR="\"$(CLASSPATH_SEPARATOR)\"" \
+ 	-DECJ_JAR_FILE="\"$(ECJ_JAR)\"" \
+-	-DLIBGCJ_DEFAULT_DATABASE="\"$(dbexecdir)/$(db_name)\"" \
++	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-6/$(db_name)\"" \
+ 	-DLIBGCJ_DEFAULT_DATABASE_PATH_TAIL="\"$(db_pathtail)\""
+ 
+ AM_GCJFLAGS = \
+Index: b/src/libjava/classpath/m4/acinclude.m4
+===================================================================
+--- a/src/libjava/classpath/m4/acinclude.m4
++++ b/src/libjava/classpath/m4/acinclude.m4
+@@ -276,6 +276,10 @@ AC_DEFUN([CLASSPATH_TOOLEXECLIBDIR],
+       esac
+       ;;
+   esac
++  multiarch=`$CC -print-multiarch`
++  if test -n "$multiarch"; then
++    toolexeclibdir=${libdir}/${multiarch}
++  fi
+   AC_SUBST(toolexecdir)
+   AC_SUBST(toolexecmainlibdir)
+   AC_SUBST(toolexeclibdir)
+Index: b/src/libjava/classpath/configure.ac
+===================================================================
+--- a/src/libjava/classpath/configure.ac
++++ b/src/libjava/classpath/configure.ac
+@@ -16,6 +16,8 @@ dnl END GCJ LOCAL
+ 
+ AC_CANONICAL_TARGET
+ 
++dnl dummy change to run autoconf
++
+ dnl GCJ LOCAL
+ AC_ARG_ENABLE(java-maintainer-mode,
+ 	AS_HELP_STRING([--enable-java-maintainer-mode],
--- gcc-6-6.3.0.orig/debian/patches/libjava-nobiarch-check.diff
+++ gcc-6-6.3.0/debian/patches/libjava-nobiarch-check.diff
@@ -0,0 +1,27 @@
+# DP: For biarch builds, disable the testsuite for the non-default architecture
+# DP: for runtime libraries, which are not built by default (libjava).
+
+---
+ libjava/testsuite/Makefile.in |    4 +++-
+ 2 files changed, 25 insertions(+), 1 deletions(-)
+
+Index: b/src/libjava/testsuite/Makefile.in
+===================================================================
+--- a/src/libjava/testsuite/Makefile.in
++++ b/src/libjava/testsuite/Makefile.in
+@@ -406,12 +406,14 @@ CTAGS:
+ 
+ 
+ check-DEJAGNU: site.exp
++	runtestflags="`echo '$(RUNTESTFLAGS)' | sed -r 's/,-m(32|64|x32)//g;s/,-mabi=(n32|64)//g'`"; \
++	case "$$runtestflags" in *\\{\\}) runtestflags=; esac; \
+ 	srcdir='$(srcdir)'; export srcdir; \
+ 	EXPECT=$(EXPECT); export EXPECT; \
+ 	runtest=$(RUNTEST); \
+ 	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+ 	  exit_status=0; l='$(DEJATOOL)'; for tool in $$l; do \
+-	    if $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \
++	    if $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $$runtestflags; \
+ 	    then :; else exit_status=1; fi; \
+ 	  done; \
+ 	else echo "WARNING: could not find \`runtest'" 1>&2; :;\
--- gcc-6-6.3.0.orig/debian/patches/libjava-rpath.diff
+++ gcc-6-6.3.0/debian/patches/libjava-rpath.diff
@@ -0,0 +1,29 @@
+# DP: - Link ecjx with -rpath $(dbexecdir)
+
+---
+ libjava/Makefile.am |    2 +-
+ libjava/Makefile.in |    2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -888,7 +888,7 @@ else !ENABLE_SHARED
+ ecjx_LDFLAGS = $(ECJX_BASE_FLAGS) $(ECJ_BUILD_JAR) -fbootclasspath=$(BOOTCLASSPATH)
+ endif !ENABLE_SHARED
+ 
+-ecjx_LDADD = -L$(here)/.libs $(extra_ldflags)
++ecjx_LDADD = -L$(here)/.libs $(extra_ldflags) -rpath $(dbexecdir)
+ ecjx_DEPENDENCIES = libgcj.la libgcj.spec
+ if USE_LIBGCJ_BC
+ ecjx_DEPENDENCIES += libgcj_bc.la
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -8360,7 +8360,7 @@ ECJX_BASE_FLAGS = -findirect-dispatch \
+ @NATIVE_FALSE@ecjx_LDFLAGS = $(ECJX_BASE_FLAGS) $(ECJ_BUILD_JAR)
+ @NATIVE_FALSE@ecjx_LDADD = 
+ @NATIVE_TRUE@ecjx_LDADD = -L$(here)/.libs $(extra_ldflags) \
+-@NATIVE_TRUE@	$(am__append_21)
++@NATIVE_TRUE@	$(am__append_21) -rpath $(dbexecdir)
+ @NATIVE_FALSE@ecjx_DEPENDENCIES = 
+ @NATIVE_TRUE@ecjx_DEPENDENCIES = libgcj.la libgcj.spec \
+ @NATIVE_TRUE@	$(am__append_20)
--- gcc-6-6.3.0.orig/debian/patches/libjava-sjlj.diff
+++ gcc-6-6.3.0/debian/patches/libjava-sjlj.diff
@@ -0,0 +1,40 @@
+# DP: Don't try to use _Unwind_Backtrace on SJLJ targets.
+# DP: See bug #387875, #388505, GCC PR 29206.
+
+---
+ libjava/sysdep/generic/backtrace.h |   17 +++++++++++++++++
+ 1 files changed, 17 insertions(+), 0 deletions(-)
+
+Index: b/src/libjava/sysdep/generic/backtrace.h
+===================================================================
+--- a/src/libjava/sysdep/generic/backtrace.h
++++ b/src/libjava/sysdep/generic/backtrace.h
+@@ -13,6 +13,20 @@ details.  */
+ 
+ #include <java-stack.h>
+ 
++#ifdef SJLJ_EXCEPTIONS
++
++#undef _Unwind_GetIPInfo
++#define _Unwind_GetIPInfo(ctx,ip_before_insn) \
++  (abort (), (void) (ctx), *ip_before_insn = 1, 0)
++
++#undef _Unwind_GetRegionStart
++#define _Unwind_GetRegionStart(ctx) \
++  (abort (), (void) (ctx), 0)
++
++#undef _Unwind_Backtrace
++#define _Unwind_Backtrace(trace_fn,state_ptr) \
++  (fallback_backtrace (trace_fn, state_ptr))
++
+ /* Unwind through the call stack calling TRACE_FN with STATE for every stack
+    frame.  Returns the reason why the unwinding was stopped.  */
+ _Unwind_Reason_Code
+@@ -20,4 +34,7 @@ fallback_backtrace (_Unwind_Trace_Fn, _J
+ {
+   return _URC_NO_REASON;
+ }
++
++#endif /* SJLJ_EXCEPTIONS */
++
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/libjava-stacktrace.diff
+++ gcc-6-6.3.0/debian/patches/libjava-stacktrace.diff
@@ -0,0 +1,52 @@
+# DP: libgcj: Lookup source file name and line number in separated
+# DP: debug files found in /usr/lib/debug
+
+---
+ libjava/stacktrace.cc |   27 +++++++++++++++++++++++++++
+ 1 files changed, 27 insertions(+), 0 deletions(-)
+
+Index: b/src/libjava/stacktrace.cc
+===================================================================
+--- a/src/libjava/stacktrace.cc
++++ b/src/libjava/stacktrace.cc
+@@ -17,6 +17,11 @@ details.  */
+ #include <java-stack.h>
+ 
+ #include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++#ifdef HAVE_UNISTD_H
++#include <unistd.h>
++#endif
+ 
+ #include <java/lang/Boolean.h>
+ #include <java/lang/Class.h>
+@@ -260,6 +265,28 @@ _Jv_StackTrace::getLineNumberForFrame(_J
+       finder->lookup (binaryName, (jlong) offset);
+       *sourceFileName = finder->getSourceFile();
+       *lineNum = finder->getLineNum();
++      if (*lineNum == -1 && info.file_name[0] == '/')
++	{
++	  const char *debugPrefix = "/usr/lib/debug";
++	  char *debugPath = (char *) malloc (strlen(debugPrefix)
++					     + strlen(info.file_name)
++					     + 2);
++
++	  if (debugPath)
++	    {
++	      strcpy (debugPath, debugPrefix);
++	      strcat (debugPath, info.file_name);
++	      //printf ("%s: 0x%x\n", debugPath, offset);
++	      if (!access (debugPath, R_OK))
++		{
++		  binaryName = JvNewStringUTF (debugPath);
++		  finder->lookup (binaryName, (jlong) offset);
++		  *sourceFileName = finder->getSourceFile();
++		  *lineNum = finder->getLineNum();
++		}
++	      free (debugPath);
++	    }
++	}
+       if (*lineNum == -1 && NameFinder::showRaw())
+         {
+           gnu::gcj::runtime::StringBuffer *t =
--- gcc-6-6.3.0.orig/debian/patches/libjit-ldflags.diff
+++ gcc-6-6.3.0/debian/patches/libjit-ldflags.diff
@@ -0,0 +1,13 @@
+Index: b/src/gcc/jit/Make-lang.in
+===================================================================
+--- a/src/gcc/jit/Make-lang.in
++++ b/src/gcc/jit/Make-lang.in
+@@ -86,7 +86,7 @@ $(LIBGCCJIT_FILENAME): $(jit_OBJS) \
+ 	     $(CPPLIB) $(LIBDECNUMBER) $(LIBS) $(BACKENDLIBS) \
+ 	     $(EXTRA_GCC_OBJS) \
+ 	     -Wl,--version-script=$(srcdir)/jit/libgccjit.map \
+-	     -Wl,-soname,$(LIBGCCJIT_SONAME)
++	     -Wl,-soname,$(LIBGCCJIT_SONAME) $(LDFLAGS)
+ 
+ $(LIBGCCJIT_SONAME_SYMLINK): $(LIBGCCJIT_FILENAME)
+ 	ln -sf $(LIBGCCJIT_FILENAME) $(LIBGCCJIT_SONAME_SYMLINK)
--- gcc-6-6.3.0.orig/debian/patches/libobjc-system-gc.diff
+++ gcc-6-6.3.0/debian/patches/libobjc-system-gc.diff
@@ -0,0 +1,822 @@
+# DP: Build the GC enabled libobjc using the system libgc when available
+
+<toplevel>
+
+2016-11-19  Matthias Klose  <doko@ubuntu.com>
+
+	* configure.ac: Include pkg.m4, check for bdw-gc pkg-config module.
+	* configure: Regenerate.
+
+config/
+
+2016-11-19  Matthias Klose  <doko@ubuntu.com>
+
+	* pkg.m4: New file.
+
+libobjc/
+
+2016-11-19  Matthias Klose  <doko@ubuntu.com>
+
+	* configure.ac (--enable-objc-gc): Allow to configure with a
+	system provided boehm-gc.
+	* configure: Regenerate.
+	* Makefile.in (OBJC_BOEHM_GC_LIBS): Get value from configure.
+	* gc.c: Optionally include system boehm-gc headers.
+	* memory.c: Likewise
+	* objects.c: Likewise
+
+Index: b/src/config/pkg.m4
+===================================================================
+--- /dev/null
++++ b/src/config/pkg.m4
+@@ -0,0 +1,550 @@
++dnl pkg.m4 - Macros to locate and utilise pkg-config.   -*- Autoconf -*-
++dnl serial 11 (pkg-config-0.29)
++dnl
++dnl Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
++dnl Copyright © 2012-2015 Dan Nicholson <dbn.lists@gmail.com>
++dnl
++dnl This program is free software; you can redistribute it and/or modify
++dnl it under the terms of the GNU General Public License as published by
++dnl the Free Software Foundation; either version 2 of the License, or
++dnl (at your option) any later version.
++dnl
++dnl This program is distributed in the hope that it will be useful, but
++dnl WITHOUT ANY WARRANTY; without even the implied warranty of
++dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++dnl General Public License for more details.
++dnl
++dnl You should have received a copy of the GNU General Public License
++dnl along with this program; if not, write to the Free Software
++dnl Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++dnl 02111-1307, USA.
++dnl
++dnl As a special exception to the GNU General Public License, if you
++dnl distribute this file as part of a program that contains a
++dnl configuration script generated by Autoconf, you may include it under
++dnl the same distribution terms that you use for the rest of that
++dnl program.
++
++dnl PKG_PREREQ(MIN-VERSION)
++dnl -----------------------
++dnl Since: 0.29
++dnl
++dnl Verify that the version of the pkg-config macros are at least
++dnl MIN-VERSION. Unlike PKG_PROG_PKG_CONFIG, which checks the user's
++dnl installed version of pkg-config, this checks the developer's version
++dnl of pkg.m4 when generating configure.
++dnl
++dnl To ensure that this macro is defined, also add:
++dnl m4_ifndef([PKG_PREREQ],
++dnl     [m4_fatal([must install pkg-config 0.29 or later before running autoconf/autogen])])
++dnl
++dnl See the "Since" comment for each macro you use to see what version
++dnl of the macros you require.
++m4_defun([PKG_PREREQ],
++[m4_define([PKG_MACROS_VERSION], [0.29])
++m4_if(m4_version_compare(PKG_MACROS_VERSION, [$1]), -1,
++    [m4_fatal([pkg.m4 version $1 or higher is required but ]PKG_MACROS_VERSION[ found])])
++])dnl PKG_PREREQ
++
++dnl PKG_PROG_PKG_CONFIG([MIN-VERSION])
++dnl ----------------------------------
++dnl Since: 0.16
++dnl
++dnl Search for the pkg-config tool and set the PKG_CONFIG variable to
++dnl first found in the path. Checks that the version of pkg-config found
++dnl is at least MIN-VERSION. If MIN-VERSION is not specified, 0.9.0 is
++dnl used since that's the first version where most current features of
++dnl pkg-config existed.
++AC_DEFUN([PKG_PROG_PKG_CONFIG],
++[m4_pattern_forbid([^_?PKG_[A-Z_]+$])
++m4_pattern_allow([^PKG_CONFIG(_(PATH|LIBDIR|SYSROOT_DIR|ALLOW_SYSTEM_(CFLAGS|LIBS)))?$])
++m4_pattern_allow([^PKG_CONFIG_(DISABLE_UNINSTALLED|TOP_BUILD_DIR|DEBUG_SPEW)$])
++AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility])
++AC_ARG_VAR([PKG_CONFIG_PATH], [directories to add to pkg-config's search path])
++AC_ARG_VAR([PKG_CONFIG_LIBDIR], [path overriding pkg-config's built-in search path])
++
++if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
++	AC_PATH_TOOL([PKG_CONFIG], [pkg-config])
++fi
++if test -n "$PKG_CONFIG"; then
++	_pkg_min_version=m4_default([$1], [0.9.0])
++	AC_MSG_CHECKING([pkg-config is at least version $_pkg_min_version])
++	if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then
++		AC_MSG_RESULT([yes])
++	else
++		AC_MSG_RESULT([no])
++		PKG_CONFIG=""
++	fi
++fi[]dnl
++])dnl PKG_PROG_PKG_CONFIG
++
++dnl PKG_CHECK_EXISTS(MODULES, [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------------------------------
++dnl Since: 0.18
++dnl
++dnl Check to see whether a particular set of modules exists. Similar to
++dnl PKG_CHECK_MODULES(), but does not set variables or print errors.
++dnl
++dnl Please remember that m4 expands AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++dnl only at the first occurence in configure.ac, so if the first place
++dnl it's called might be skipped (such as if it is within an "if", you
++dnl have to call PKG_CHECK_EXISTS manually
++AC_DEFUN([PKG_CHECK_EXISTS],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++if test -n "$PKG_CONFIG" && \
++    AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then
++  m4_default([$2], [:])
++m4_ifvaln([$3], [else
++  $3])dnl
++fi])
++
++dnl _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES])
++dnl ---------------------------------------------
++dnl Internal wrapper calling pkg-config via PKG_CONFIG and setting
++dnl pkg_failed based on the result.
++m4_define([_PKG_CONFIG],
++[if test -n "$$1"; then
++    pkg_cv_[]$1="$$1"
++ elif test -n "$PKG_CONFIG"; then
++    PKG_CHECK_EXISTS([$3],
++                     [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`
++		      test "x$?" != "x0" && pkg_failed=yes ],
++		     [pkg_failed=yes])
++ else
++    pkg_failed=untried
++fi[]dnl
++])dnl _PKG_CONFIG
++
++dnl _PKG_SHORT_ERRORS_SUPPORTED
++dnl ---------------------------
++dnl Internal check to see if pkg-config supports short errors.
++AC_DEFUN([_PKG_SHORT_ERRORS_SUPPORTED],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
++        _pkg_short_errors_supported=yes
++else
++        _pkg_short_errors_supported=no
++fi[]dnl
++])dnl _PKG_SHORT_ERRORS_SUPPORTED
++
++
++dnl PKG_CHECK_MODULES(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl --------------------------------------------------------------
++dnl Since: 0.4.0
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES might not happen, you should be sure to include an
++dnl explicit call to PKG_PROG_PKG_CONFIG in your configure.ac
++AC_DEFUN([PKG_CHECK_MODULES],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl
++AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl
++
++pkg_failed=no
++AC_MSG_CHECKING([for $1])
++
++_PKG_CONFIG([$1][_CFLAGS], [cflags], [$2])
++_PKG_CONFIG([$1][_LIBS], [libs], [$2])
++
++m4_define([_PKG_TEXT], [Alternatively, you may set the environment variables $1[]_CFLAGS
++and $1[]_LIBS to avoid the need to call pkg-config.
++See the pkg-config man page for more details.])
++
++if test $pkg_failed = yes; then
++   	AC_MSG_RESULT([no])
++        _PKG_SHORT_ERRORS_SUPPORTED
++        if test $_pkg_short_errors_supported = yes; then
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "$2" 2>&1`
++        else 
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "$2" 2>&1`
++        fi
++	# Put the nasty error message in config.log where it belongs
++	echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD
++
++	m4_default([$4], [AC_MSG_ERROR(
++[Package requirements ($2) were not met:
++
++$$1_PKG_ERRORS
++
++Consider adjusting the PKG_CONFIG_PATH environment variable if you
++installed software in a non-standard prefix.
++
++_PKG_TEXT])[]dnl
++        ])
++elif test $pkg_failed = untried; then
++     	AC_MSG_RESULT([no])
++	m4_default([$4], [AC_MSG_FAILURE(
++[The pkg-config script could not be found or is too old.  Make sure it
++is in your PATH or set the PKG_CONFIG environment variable to the full
++path to pkg-config.
++
++_PKG_TEXT
++
++To get pkg-config, see <http://pkg-config.freedesktop.org/>.])[]dnl
++        ])
++else
++	$1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS
++	$1[]_LIBS=$pkg_cv_[]$1[]_LIBS
++        AC_MSG_RESULT([yes])
++	$3
++fi[]dnl
++])dnl PKG_CHECK_MODULES
++
++
++dnl PKG_CHECK_MODULES_STATIC(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl ---------------------------------------------------------------------
++dnl Since: 0.29
++dnl
++dnl Checks for existence of MODULES and gathers its build flags with
++dnl static libraries enabled. Sets VARIABLE-PREFIX_CFLAGS from --cflags
++dnl and VARIABLE-PREFIX_LIBS from --libs.
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES_STATIC might not happen, you should be sure to
++dnl include an explicit call to PKG_PROG_PKG_CONFIG in your
++dnl configure.ac.
++AC_DEFUN([PKG_CHECK_MODULES_STATIC],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++_save_PKG_CONFIG=$PKG_CONFIG
++PKG_CONFIG="$PKG_CONFIG --static"
++PKG_CHECK_MODULES($@)
++PKG_CONFIG=$_save_PKG_CONFIG[]dnl
++])dnl PKG_CHECK_MODULES_STATIC
++
++
++dnl PKG_INSTALLDIR([DIRECTORY])
++dnl -------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable pkgconfigdir as the location where a module
++dnl should install pkg-config .pc files. By default the directory is
++dnl $libdir/pkgconfig, but the default can be changed by passing
++dnl DIRECTORY. The user can override through the --with-pkgconfigdir
++dnl parameter.
++AC_DEFUN([PKG_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${libdir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([pkgconfigdir],
++    [AS_HELP_STRING([--with-pkgconfigdir], pkg_description)],,
++    [with_pkgconfigdir=]pkg_default)
++AC_SUBST([pkgconfigdir], [$with_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_INSTALLDIR
++
++
++dnl PKG_NOARCH_INSTALLDIR([DIRECTORY])
++dnl --------------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable noarch_pkgconfigdir as the location where a
++dnl module should install arch-independent pkg-config .pc files. By
++dnl default the directory is $datadir/pkgconfig, but the default can be
++dnl changed by passing DIRECTORY. The user can override through the
++dnl --with-noarch-pkgconfigdir parameter.
++AC_DEFUN([PKG_NOARCH_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${datadir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config arch-independent installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([noarch-pkgconfigdir],
++    [AS_HELP_STRING([--with-noarch-pkgconfigdir], pkg_description)],,
++    [with_noarch_pkgconfigdir=]pkg_default)
++AC_SUBST([noarch_pkgconfigdir], [$with_noarch_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_NOARCH_INSTALLDIR
++
++
++dnl PKG_CHECK_VAR(VARIABLE, MODULE, CONFIG-VARIABLE,
++dnl [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------
++dnl Since: 0.28
++dnl
++dnl Retrieves the value of the pkg-config variable for the given module.
++AC_DEFUN([PKG_CHECK_VAR],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1], [value of $3 for $2, overriding pkg-config])dnl
++
++_PKG_CONFIG([$1], [variable="][$3]["], [$2])
++AS_VAR_COPY([$1], [pkg_cv_][$1])
++
++AS_VAR_IF([$1], [""], [$5], [$4])dnl
++])dnl PKG_CHECK_VAR
++dnl pkg.m4 - Macros to locate and utilise pkg-config.   -*- Autoconf -*-
++dnl serial 11 (pkg-config-0.29)
++dnl
++dnl Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
++dnl Copyright © 2012-2015 Dan Nicholson <dbn.lists@gmail.com>
++dnl
++dnl This program is free software; you can redistribute it and/or modify
++dnl it under the terms of the GNU General Public License as published by
++dnl the Free Software Foundation; either version 2 of the License, or
++dnl (at your option) any later version.
++dnl
++dnl This program is distributed in the hope that it will be useful, but
++dnl WITHOUT ANY WARRANTY; without even the implied warranty of
++dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++dnl General Public License for more details.
++dnl
++dnl You should have received a copy of the GNU General Public License
++dnl along with this program; if not, write to the Free Software
++dnl Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++dnl 02111-1307, USA.
++dnl
++dnl As a special exception to the GNU General Public License, if you
++dnl distribute this file as part of a program that contains a
++dnl configuration script generated by Autoconf, you may include it under
++dnl the same distribution terms that you use for the rest of that
++dnl program.
++
++dnl PKG_PREREQ(MIN-VERSION)
++dnl -----------------------
++dnl Since: 0.29
++dnl
++dnl Verify that the version of the pkg-config macros are at least
++dnl MIN-VERSION. Unlike PKG_PROG_PKG_CONFIG, which checks the user's
++dnl installed version of pkg-config, this checks the developer's version
++dnl of pkg.m4 when generating configure.
++dnl
++dnl To ensure that this macro is defined, also add:
++dnl m4_ifndef([PKG_PREREQ],
++dnl     [m4_fatal([must install pkg-config 0.29 or later before running autoconf/autogen])])
++dnl
++dnl See the "Since" comment for each macro you use to see what version
++dnl of the macros you require.
++m4_defun([PKG_PREREQ],
++[m4_define([PKG_MACROS_VERSION], [0.29])
++m4_if(m4_version_compare(PKG_MACROS_VERSION, [$1]), -1,
++    [m4_fatal([pkg.m4 version $1 or higher is required but ]PKG_MACROS_VERSION[ found])])
++])dnl PKG_PREREQ
++
++dnl PKG_PROG_PKG_CONFIG([MIN-VERSION])
++dnl ----------------------------------
++dnl Since: 0.16
++dnl
++dnl Search for the pkg-config tool and set the PKG_CONFIG variable to
++dnl first found in the path. Checks that the version of pkg-config found
++dnl is at least MIN-VERSION. If MIN-VERSION is not specified, 0.9.0 is
++dnl used since that's the first version where most current features of
++dnl pkg-config existed.
++AC_DEFUN([PKG_PROG_PKG_CONFIG],
++[m4_pattern_forbid([^_?PKG_[A-Z_]+$])
++m4_pattern_allow([^PKG_CONFIG(_(PATH|LIBDIR|SYSROOT_DIR|ALLOW_SYSTEM_(CFLAGS|LIBS)))?$])
++m4_pattern_allow([^PKG_CONFIG_(DISABLE_UNINSTALLED|TOP_BUILD_DIR|DEBUG_SPEW)$])
++AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility])
++AC_ARG_VAR([PKG_CONFIG_PATH], [directories to add to pkg-config's search path])
++AC_ARG_VAR([PKG_CONFIG_LIBDIR], [path overriding pkg-config's built-in search path])
++
++if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
++	AC_PATH_TOOL([PKG_CONFIG], [pkg-config])
++fi
++if test -n "$PKG_CONFIG"; then
++	_pkg_min_version=m4_default([$1], [0.9.0])
++	AC_MSG_CHECKING([pkg-config is at least version $_pkg_min_version])
++	if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then
++		AC_MSG_RESULT([yes])
++	else
++		AC_MSG_RESULT([no])
++		PKG_CONFIG=""
++	fi
++fi[]dnl
++])dnl PKG_PROG_PKG_CONFIG
++
++dnl PKG_CHECK_EXISTS(MODULES, [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------------------------------
++dnl Since: 0.18
++dnl
++dnl Check to see whether a particular set of modules exists. Similar to
++dnl PKG_CHECK_MODULES(), but does not set variables or print errors.
++dnl
++dnl Please remember that m4 expands AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++dnl only at the first occurence in configure.ac, so if the first place
++dnl it's called might be skipped (such as if it is within an "if", you
++dnl have to call PKG_CHECK_EXISTS manually
++AC_DEFUN([PKG_CHECK_EXISTS],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++if test -n "$PKG_CONFIG" && \
++    AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then
++  m4_default([$2], [:])
++m4_ifvaln([$3], [else
++  $3])dnl
++fi])
++
++dnl _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES])
++dnl ---------------------------------------------
++dnl Internal wrapper calling pkg-config via PKG_CONFIG and setting
++dnl pkg_failed based on the result.
++m4_define([_PKG_CONFIG],
++[if test -n "$$1"; then
++    pkg_cv_[]$1="$$1"
++ elif test -n "$PKG_CONFIG"; then
++    PKG_CHECK_EXISTS([$3],
++                     [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`
++		      test "x$?" != "x0" && pkg_failed=yes ],
++		     [pkg_failed=yes])
++ else
++    pkg_failed=untried
++fi[]dnl
++])dnl _PKG_CONFIG
++
++dnl _PKG_SHORT_ERRORS_SUPPORTED
++dnl ---------------------------
++dnl Internal check to see if pkg-config supports short errors.
++AC_DEFUN([_PKG_SHORT_ERRORS_SUPPORTED],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
++        _pkg_short_errors_supported=yes
++else
++        _pkg_short_errors_supported=no
++fi[]dnl
++])dnl _PKG_SHORT_ERRORS_SUPPORTED
++
++
++dnl PKG_CHECK_MODULES(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl --------------------------------------------------------------
++dnl Since: 0.4.0
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES might not happen, you should be sure to include an
++dnl explicit call to PKG_PROG_PKG_CONFIG in your configure.ac
++AC_DEFUN([PKG_CHECK_MODULES],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl
++AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl
++
++pkg_failed=no
++AC_MSG_CHECKING([for $1])
++
++_PKG_CONFIG([$1][_CFLAGS], [cflags], [$2])
++_PKG_CONFIG([$1][_LIBS], [libs], [$2])
++
++m4_define([_PKG_TEXT], [Alternatively, you may set the environment variables $1[]_CFLAGS
++and $1[]_LIBS to avoid the need to call pkg-config.
++See the pkg-config man page for more details.])
++
++if test $pkg_failed = yes; then
++   	AC_MSG_RESULT([no])
++        _PKG_SHORT_ERRORS_SUPPORTED
++        if test $_pkg_short_errors_supported = yes; then
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "$2" 2>&1`
++        else 
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "$2" 2>&1`
++        fi
++	# Put the nasty error message in config.log where it belongs
++	echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD
++
++	m4_default([$4], [AC_MSG_ERROR(
++[Package requirements ($2) were not met:
++
++$$1_PKG_ERRORS
++
++Consider adjusting the PKG_CONFIG_PATH environment variable if you
++installed software in a non-standard prefix.
++
++_PKG_TEXT])[]dnl
++        ])
++elif test $pkg_failed = untried; then
++     	AC_MSG_RESULT([no])
++	m4_default([$4], [AC_MSG_FAILURE(
++[The pkg-config script could not be found or is too old.  Make sure it
++is in your PATH or set the PKG_CONFIG environment variable to the full
++path to pkg-config.
++
++_PKG_TEXT
++
++To get pkg-config, see <http://pkg-config.freedesktop.org/>.])[]dnl
++        ])
++else
++	$1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS
++	$1[]_LIBS=$pkg_cv_[]$1[]_LIBS
++        AC_MSG_RESULT([yes])
++	$3
++fi[]dnl
++])dnl PKG_CHECK_MODULES
++
++
++dnl PKG_CHECK_MODULES_STATIC(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl ---------------------------------------------------------------------
++dnl Since: 0.29
++dnl
++dnl Checks for existence of MODULES and gathers its build flags with
++dnl static libraries enabled. Sets VARIABLE-PREFIX_CFLAGS from --cflags
++dnl and VARIABLE-PREFIX_LIBS from --libs.
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES_STATIC might not happen, you should be sure to
++dnl include an explicit call to PKG_PROG_PKG_CONFIG in your
++dnl configure.ac.
++AC_DEFUN([PKG_CHECK_MODULES_STATIC],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++_save_PKG_CONFIG=$PKG_CONFIG
++PKG_CONFIG="$PKG_CONFIG --static"
++PKG_CHECK_MODULES($@)
++PKG_CONFIG=$_save_PKG_CONFIG[]dnl
++])dnl PKG_CHECK_MODULES_STATIC
++
++
++dnl PKG_INSTALLDIR([DIRECTORY])
++dnl -------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable pkgconfigdir as the location where a module
++dnl should install pkg-config .pc files. By default the directory is
++dnl $libdir/pkgconfig, but the default can be changed by passing
++dnl DIRECTORY. The user can override through the --with-pkgconfigdir
++dnl parameter.
++AC_DEFUN([PKG_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${libdir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([pkgconfigdir],
++    [AS_HELP_STRING([--with-pkgconfigdir], pkg_description)],,
++    [with_pkgconfigdir=]pkg_default)
++AC_SUBST([pkgconfigdir], [$with_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_INSTALLDIR
++
++
++dnl PKG_NOARCH_INSTALLDIR([DIRECTORY])
++dnl --------------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable noarch_pkgconfigdir as the location where a
++dnl module should install arch-independent pkg-config .pc files. By
++dnl default the directory is $datadir/pkgconfig, but the default can be
++dnl changed by passing DIRECTORY. The user can override through the
++dnl --with-noarch-pkgconfigdir parameter.
++AC_DEFUN([PKG_NOARCH_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${datadir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config arch-independent installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([noarch-pkgconfigdir],
++    [AS_HELP_STRING([--with-noarch-pkgconfigdir], pkg_description)],,
++    [with_noarch_pkgconfigdir=]pkg_default)
++AC_SUBST([noarch_pkgconfigdir], [$with_noarch_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_NOARCH_INSTALLDIR
++
++
++dnl PKG_CHECK_VAR(VARIABLE, MODULE, CONFIG-VARIABLE,
++dnl [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------
++dnl Since: 0.28
++dnl
++dnl Retrieves the value of the pkg-config variable for the given module.
++AC_DEFUN([PKG_CHECK_VAR],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1], [value of $3 for $2, overriding pkg-config])dnl
++
++_PKG_CONFIG([$1], [variable="][$3]["], [$2])
++AS_VAR_COPY([$1], [pkg_cv_][$1])
++
++AS_VAR_IF([$1], [""], [$5], [$4])dnl
++])dnl PKG_CHECK_VAR
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -29,6 +29,7 @@ m4_include([ltsugar.m4])
+ m4_include([ltversion.m4])
+ m4_include([lt~obsolete.m4])
+ m4_include([config/isl.m4])
++m4_include([config/pkg.m4])
+ 
+ AC_INIT(move-if-change)
+ AC_PREREQ(2.64)
+@@ -2169,14 +2170,20 @@ AC_ARG_ENABLE(objc-gc,
+ 		[enable use of Boehm's garbage collector with the
+ 		 GNU Objective-C runtime])],
+ [case ,${enable_languages},:${enable_objc_gc}:${noconfigdirs} in
+-  *,objc,*:*:yes:*target-boehm-gc*)
++  *,objc,*:*:yes:*target-boehm-gc*|*,objc,*:*:auto:*target-boehm-gc*|*,objc,*:*:system:*target-boehm-gc*)
+     AC_MSG_ERROR([Boehm's garbage collector was requested yet not supported in this configuration])
++esac
++case ,${enable_languages},:${enable_objc_gc} in
++  *,objc,*:auto|*,objc,*:system)
++    PKG_CHECK_EXISTS(bdw-gc,
++      AC_MSG_RESULT([found]),
++      AC_MSG_ERROR([bdw-gc pkg-config module not found]))
+     ;;
+ esac])
+ 
+ # Make sure we only build Boehm's garbage collector if required.
+ case ,${enable_languages},:${enable_objc_gc} in
+-  *,objc,*:yes)
++  *,objc,*:yes|*,objc,*:auto)
+     # Keep target-boehm-gc if requested for Objective-C.
+     ;;
+   *)
+Index: b/src/libobjc/Makefile.in
+===================================================================
+--- a/src/libobjc/Makefile.in
++++ b/src/libobjc/Makefile.in
+@@ -95,7 +95,7 @@ LIBTOOL_CLEAN   = $(LIBTOOL) --mode=clea
+ OBJC_GCFLAGS=@OBJC_GCFLAGS@
+ OBJC_BOEHM_GC=@OBJC_BOEHM_GC@
+ OBJC_BOEHM_GC_INCLUDES=@OBJC_BOEHM_GC_INCLUDES@
+-OBJC_BOEHM_GC_LIBS=../boehm-gc/libgcjgc_convenience.la $(thread_libs_and_flags)
++OBJC_BOEHM_GC_LIBS=@OBJC_BOEHM_GC_LIBS@
+ 
+ INCLUDES = -I$(srcdir)/$(MULTISRCTOP)../gcc \
+   -I$(srcdir)/$(MULTISRCTOP)../gcc/config \
+Index: b/src/libobjc/configure.ac
+===================================================================
+--- a/src/libobjc/configure.ac
++++ b/src/libobjc/configure.ac
+@@ -18,6 +18,8 @@
+ #along with GCC; see the file COPYING3.  If not see
+ #<http://www.gnu.org/licenses/>.
+ 
++m4_include([../config/pkg.m4])
++
+ AC_PREREQ(2.64)
+ AC_INIT(package-unused, version-unused,, libobjc)
+ AC_CONFIG_SRCDIR([objc/objc.h])
+@@ -57,26 +59,6 @@ AC_ARG_ENABLE(version-specific-runtime-l
+ [version_specific_libs=no])
+ AC_MSG_RESULT($version_specific_libs)
+ 
+-AC_ARG_ENABLE(objc-gc,
+-[  --enable-objc-gc       enable the use of Boehm's garbage collector with
+-                          the GNU Objective-C runtime.],
+-[case $enable_objc_gc in
+-  no)
+-    OBJC_GCFLAGS=''
+-    OBJC_BOEHM_GC=''
+-    OBJC_BOEHM_GC_INCLUDES=''
+-    ;;
+-  *)
+-    OBJC_GCFLAGS='-DOBJC_WITH_GC=1'
+-    OBJC_BOEHM_GC='libobjc_gc$(libsuffix).la'
+-    OBJC_BOEHM_GC_INCLUDES='-I$(top_srcdir)/../boehm-gc/include -I../boehm-gc/include'
+-    ;;
+-esac],
+-[OBJC_GCFLAGS=''; OBJC_BOEHM_GC=''; OBJC_BOEHM_GC_INCLUDES=''])
+-AC_SUBST(OBJC_GCFLAGS)
+-AC_SUBST(OBJC_BOEHM_GC)
+-AC_SUBST(OBJC_BOEHM_GC_INCLUDES)
+-
+ # -----------
+ # Directories
+ # -----------
+@@ -214,6 +196,87 @@ GCC_CHECK_TLS
+ 
+ gt_BITFIELD_TYPE_MATTERS
+ 
++# -----------
++# boehm-gc
++# -----------
++
++AC_ARG_ENABLE(objc-gc,
++[  --enable-objc-gc       enable the use of Boehm's garbage collector with
++                          the GNU Objective-C runtime. Valid values are
++                          yes, no, system or auto],
++[case $enable_objc_gc in
++  no)
++    use_boehm_gc=no
++    ;;
++  auto|system)
++    PKG_CHECK_MODULES(BDW_GC, bdw-gc >= 7)
++    AC_MSG_CHECKING([for system boehm-gc])
++    save_CFLAGS=$CFLAGS
++    save_LIBS=$LIBS
++    CFLAGS="$CFLAGS $BDW_GC_CFLAGS"
++    LIBS="$LIBS $BDW_GC_LIBS"
++    dnl the link test is not good enough for ARM32 multilib detection,
++    dnl first check to link, then to run
++    AC_LINK_IFELSE(
++      [AC_LANG_PROGRAM([#include <gc/gc.h>],[GC_init()])],
++      [
++        AC_RUN_IFELSE([AC_LANG_SOURCE([[
++          #include <gc/gc.h>
++          int main() {
++            GC_init();
++            return 0;
++          }
++          ]])],
++          [system_boehm_gc_found=yes],
++          [system_boehm_gc_found=no],
++          dnl assume no system boehm-gc for cross builds ...
++          [system_boehm_gc_found=no]
++        )
++      ],
++      [system_boehm_gc_found=no])
++    CFLAGS=$save_CFLAGS
++    LIBS=$save_LIBS
++    if test x$enable_objc_gc = xsystem && test x$system_boehm_gc_found = xno; then
++      AC_MSG_ERROR([system boehm-gc required but not found])
++    elif test x$system_boehm_gc_found = xno; then
++      use_boehm_gc=internal
++      AC_MSG_RESULT([not found, falling back to internal boehm-gc])
++    else
++      use_boehm_gc=system
++      AC_MSG_RESULT([found])
++    fi
++    ;;
++  *)
++    use_boehm_gc=internal
++    ;;
++esac],
++[use_boehm_gc=no])
++
++case "$use_boehm_gc" in
++  internal)
++    OBJC_GCFLAGS='-DOBJC_WITH_GC=1'
++    OBJC_BOEHM_GC='libobjc_gc$(libsuffix).la'
++    OBJC_BOEHM_GC_INCLUDES='-I$(top_srcdir)/../boehm-gc/include -I../boehm-gc/include'
++    OBJC_BOEHM_GC_LIBS='../boehm-gc/libgcjgc_convenience.la $(thread_libs_and_flags)'
++    ;;
++  system)
++    OBJC_GCFLAGS='-DOBJC_WITH_GC=1 -DSYSTEM_BOEHM_GC=1'
++    OBJC_BOEHM_GC='libobjc_gc$(libsuffix).la'
++    OBJC_BOEHM_GC_INCLUDES=$BDW_GC_CFLAGS
++    OBJC_BOEHM_GC_LIBS=$BDW_GC_LIBS
++    ;;
++  *)
++    OBJC_GCFLAGS=''
++    OBJC_BOEHM_GC=''
++    OBJC_BOEHM_GC_INCLUDES=''
++    OBJC_BOEHM_GC_LIBS=''
++    ;;
++esac
++AC_SUBST(OBJC_GCFLAGS)
++AC_SUBST(OBJC_BOEHM_GC)
++AC_SUBST(OBJC_BOEHM_GC_INCLUDES)
++AC_SUBST(OBJC_BOEHM_GC_LIBS)
++
+ # ------
+ # Output
+ # ------
+Index: b/src/libobjc/gc.c
+===================================================================
+--- a/src/libobjc/gc.c
++++ b/src/libobjc/gc.c
+@@ -36,7 +36,11 @@ see the files COPYING3 and COPYING.RUNTI
+ #include "objc/runtime.h"
+ #include "objc-private/module-abi-8.h"
+ 
++#if SYSTEM_BOEHM_GC
++#include <gc/gc.h>
++#else
+ #include <gc.h>
++#endif
+ #include <limits.h>
+ 
+ /* gc_typed.h uses the following but doesn't declare them */
+@@ -44,7 +48,11 @@ typedef GC_word word;
+ typedef GC_signed_word signed_word;
+ #define BITS_PER_WORD (CHAR_BIT * sizeof (word))
+ 
++#if SYSTEM_BOEHM_GC
++#include <gc/gc_typed.h>
++#else
+ #include <gc_typed.h>
++#endif
+ 
+ /* The following functions set up in `mask` the corresponding pointers.
+    The offset is incremented with the size of the type.  */
+Index: b/src/libobjc/memory.c
+===================================================================
+--- a/src/libobjc/memory.c
++++ b/src/libobjc/memory.c
+@@ -41,7 +41,11 @@ see the files COPYING3 and COPYING.RUNTI
+ #include "objc/runtime.h"
+ 
+ #if OBJC_WITH_GC
++#if SYSTEM_BOEHM_GC
++#include <gc/gc.h>
++#else
+ #include <gc.h>
++#endif
+ 
+ void *
+ objc_malloc (size_t size)
+Index: b/src/libobjc/objects.c
+===================================================================
+--- a/src/libobjc/objects.c
++++ b/src/libobjc/objects.c
+@@ -31,8 +31,13 @@ see the files COPYING3 and COPYING.RUNTI
+ #include <string.h>                     /* For memcpy()  */
+ 
+ #if OBJC_WITH_GC
+-# include <gc.h>
+-# include <gc_typed.h>
++# if SYSTEM_BOEHM_GC
++#  include <gc/gc.h>
++#  include <gc/gc_typed.h>
++# else
++#  include <gc.h>
++#  include <gc_typed.h>
++# endif
+ #endif
+ 
+ /* FIXME: The semantics of extraBytes are not really clear.  */
--- gcc-6-6.3.0.orig/debian/patches/libphobos-zlib.diff
+++ gcc-6-6.3.0/debian/patches/libphobos-zlib.diff
@@ -0,0 +1,74 @@
+# DP: Build zlib in any case to have a fall back for missing libz multilibs
+
+Index: b/src/libphobos/configure.ac
+===================================================================
+--- a/src/libphobos/configure.ac
++++ b/src/libphobos/configure.ac
+@@ -104,6 +104,7 @@ WITH_LOCAL_DRUNTIME([
+ 
+ DRUNTIME_LIBBACKTRACE_SETUP
+ DRUNTIME_INSTALL_DIRECTORIES
++dnl fake change to regenerate the configure file
+ 
+ # Add dependencies for libgphobos.spec file
+ LIBS="$LIBS $LIBADD_DLOPEN"
+Index: b/src/libphobos/m4/druntime/libraries.m4
+===================================================================
+--- a/src/libphobos/m4/druntime/libraries.m4
++++ b/src/libphobos/m4/druntime/libraries.m4
+@@ -39,18 +39,44 @@ AC_DEFUN([DRUNTIME_LIBRARIES_ZLIB],
+ [
+   AC_ARG_WITH(target-system-zlib,
+     AS_HELP_STRING([--with-target-system-zlib],
+-                   [use installed libz (default: no)]))
++                   [use installed libz (default: no)]),
++     [system_zlib=yes],[system_zlib=no])
+ 
+-  system_zlib=false
+-  AS_IF([test "x$with_target_system_zlib" = "xyes"], [
+-    AC_CHECK_LIB([z], [deflate], [
+-      system_zlib=yes
+-      ], [
+-      AC_MSG_ERROR([System zlib not found])])
+-  ], [
+-    AC_MSG_CHECKING([for zlib])
+-    AC_MSG_RESULT([just compiled])
+-  ])
++  AC_MSG_CHECKING([for system zlib])
++  save_LIBS=$LIBS
++  LIBS="$LIBS -lz"
++  dnl the link test is not good enough for ARM32 multilib detection,
++  dnl first check to link, then to run
++  AC_LANG_PUSH(C)
++  AC_LINK_IFELSE(
++    [AC_LANG_PROGRAM([#include <zlib.h>],[gzopen("none", "rb")])],
++    [
++      AC_RUN_IFELSE([AC_LANG_SOURCE([[
++        #include <zlib.h>
++        int main() {
++          gzFile file = gzopen("none", "rb");
++          return 0;
++        }
++        ]])],
++        [system_zlib_found=yes],
++        [system_zlib_found=no],
++        dnl no system zlib for cross builds ...
++        [system_zlib_found=no]
++      )
++    ],
++    [system_zlib_found=no])
++  LIBS=$save_LIBS
++  if test x$system_zlib = xyes; then
++    if test x$system_zlib_found = xyes; then
++      AC_MSG_RESULT([found])
++    else
++      AC_MSG_RESULT([not found, disabled])
++      system_zlib=no
++    fi
++  else
++    AC_MSG_RESULT([not enabled])
++  fi
++  AC_LANG_POP
+ 
+   AM_CONDITIONAL([DRUNTIME_ZLIB_SYSTEM], [test "$with_target_system_zlib" = yes])
+ ])
--- gcc-6-6.3.0.orig/debian/patches/libstdc++-doclink.diff
+++ gcc-6-6.3.0/debian/patches/libstdc++-doclink.diff
@@ -0,0 +1,75 @@
+# DP: adjust hrefs to point to the local documentation
+
+---
+ libstdc++-v3/doc/doxygen/mainpage.html |   10 +++++-----
+ 1 files changed, 5 insertions(+), 5 deletions(-)
+
+Index: b/src/libstdc++-v3/doc/doxygen/mainpage.html
+===================================================================
+--- a/src/libstdc++-v3/doc/doxygen/mainpage.html
++++ b/src/libstdc++-v3/doc/doxygen/mainpage.html
+@@ -27,10 +27,10 @@
+ <p class="smallertext">Generated on @DATE@.</p>
+ 
+ <p>There are two types of documentation for libstdc++.  One is the
+-   distribution documentation, which can be read online
+-   <a href="http://gcc.gnu.org/onlinedocs/libstdc++/index.html">here</a>
+-   or offline from the file doc/html/index.html in the library source
+-   directory.
++   distribution documentation, which can be read
++   <a href="../index.html">offline in the documentation directory</a>
++   or
++   <a href="http://gcc.gnu.org/onlinedocs/libstdc++/index.html">online</a>.
+ </p>
+ 
+ <p>The other type is the source documentation, of which this is the first page.
+@@ -81,9 +81,10 @@
+   This style guide can also be viewed on the <a href="http://gcc.gnu.org/onlinedocs/libstdc++/manual/bk01apas04.html">web</a>.
+ 
+ <h2>License, Copyright, and Other Lawyerly Verbosity</h2>
+-<p>The libstdc++ documentation is released under
+-   <a href="http://gcc.gnu.org/onlinedocs/libstdc++/manual/bk01pt01ch01s02.html">
+-   these terms</a>.
++<p>The libstdc++ documentation is released under these terms
++   (<a href="../manual/license.html">read offline</a> or
++    <a href="http://gcc.gnu.org/onlinedocs/libstdc++/manual/license.html">read online</a>.
++   ).
+ </p>
+ <p>Part of the generated documentation involved comments and notes from
+    SGI, who says we gotta say this:
+Index: b/src/libstdc++-v3/doc/html/api.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/api.html
++++ b/src/libstdc++-v3/doc/html/api.html
+@@ -20,6 +20,8 @@
+   member functions for the library classes, finding out what is in a
+   particular include file, looking at inheritance diagrams, etc.
+ </p><p>
++<a class="link" href="user/index.html">The API documentation, rendered into HTML, can be viewed offline.</a>
++</p><p>
+   The API documentation, rendered into HTML, can be viewed online
+   <a class="link" href="http://gcc.gnu.org/onlinedocs/" target="_top">for each GCC release</a>
+   and
+@@ -38,4 +40,4 @@
+ </p><p>
+   In addition, a rendered set of man pages are available in the same
+   location specified above. Start with C++Intro(3).
+-</p></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="bk02.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="bk02.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="bk03.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> </td></tr></table></div></body></html>
+\ No newline at end of file
++</p></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="bk02.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="bk02.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="bk03.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> </td></tr></table></div></body></html>
+Index: b/src/libstdc++-v3/doc/xml/api.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/api.xml
++++ b/src/libstdc++-v3/doc/xml/api.xml
+@@ -40,6 +40,11 @@
+ </para>
+ 
+ <para>
++  <ulink url="user/index.html">The source-level documentation for this release can be viewed offline.
++  </ulink>
++</para>
++
++<para>
+   The API documentation, rendered into HTML, can be viewed online
+   <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/onlinedocs/">for each GCC release</link>
+   and
--- gcc-6-6.3.0.orig/debian/patches/libstdc++-functexcept.diff
+++ gcc-6-6.3.0/debian/patches/libstdc++-functexcept.diff
@@ -0,0 +1,17 @@
+# DP: PR libstdc++/66145, std::ios_base::failure objects thrown from libstdc++.so use old ABI
+# DP: Just build src/c++11/functexcept.cc using the new ABI. It will break
+# DP: code, which will be handled in the archive by adding Breaks for the
+# DP: affected packages.  Third party code using such code will need a rebuild.
+
+--- a/src/libstdc++-v3/src/c++11/functexcept.cc
++++ b/src/libstdc++-v3/src/c++11/functexcept.cc
+@@ -20,9 +20,6 @@
+ // see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ // <http://www.gnu.org/licenses/>.
+ 
+-// We don't want to change the type thrown by __throw_ios_failure (yet?)
+-#define _GLIBCXX_USE_CXX11_ABI 0
+-
+ #include <bits/functexcept.h>
+ #include <cstdlib>
+ #include <exception>
--- gcc-6-6.3.0.orig/debian/patches/libstdc++-man-3cxx.diff
+++ gcc-6-6.3.0/debian/patches/libstdc++-man-3cxx.diff
@@ -0,0 +1,67 @@
+# DP: Install libstdc++ man pages with suffix .3cxx instead of .3
+
+Index: b/src/libstdc++-v3/doc/doxygen/user.cfg.in
+===================================================================
+--- a/src/libstdc++-v3/doc/doxygen/user.cfg.in
++++ b/src/libstdc++-v3/doc/doxygen/user.cfg.in
+@@ -1968,7 +1968,7 @@ MAN_OUTPUT             = man
+ # The default value is: .3.
+ # This tag requires that the tag GENERATE_MAN is set to YES.
+ 
+-MAN_EXTENSION          = .3
++MAN_EXTENSION          = .3cxx
+ 
+ # If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+ # will generate one additional man file for each entity documented in the real
+Index: b/src/libstdc++-v3/scripts/run_doxygen
+===================================================================
+--- a/src/libstdc++-v3/scripts/run_doxygen
++++ b/src/libstdc++-v3/scripts/run_doxygen
+@@ -243,6 +243,9 @@ fi
+ if $do_man; then
+ echo ::
+ echo :: Fixing up the man pages...
++mkdir -p $outdir/man/man3
++mv $outdir/man/man3cxx/* $outdir/man/man3/
++rmdir $outdir/man/man3cxx
+ cd $outdir/man/man3
+ 
+ # File names with embedded spaces (EVIL!) need to be....?  renamed or removed?
+@@ -264,7 +267,7 @@ rm -f *.h.3 *.hpp.3 *config* *.cc.3 *.tc
+ # and I'm off getting coffee then anyhow, so I didn't care enough to make
+ # this super-fast.
+ g++ ${srcdir}/doc/doxygen/stdheader.cc -o ./stdheader
+-problematic=`egrep -l '#include <.*_.*>' [a-z]*.3`
++problematic=`egrep -l '#include <.*_.*>' [a-z]*.3 [a-z]*.3cxx`
+ for f in $problematic; do
+     # this is also slow, but safe and easy to debug
+     oldh=`sed -n '/fC#include </s/.*<\(.*\)>.*/\1/p' $f`
+@@ -277,7 +280,7 @@ rm stdheader
+ # Some of the pages for generated modules have text that confuses certain
+ # implementations of man(1), e.g. on GNU/Linux.  We need to have another
+ # top-level *roff tag to /stop/ the .SH NAME entry.
+-problematic=`egrep --files-without-match '^\.SH SYNOPSIS' [A-Z]*.3`
++problematic=`egrep --files-without-match '^\.SH SYNOPSIS' [A-Z]*.3cxx`
+ #problematic='Containers.3 Sequences.3 Assoc_containers.3 Iterator_types.3'
+ 
+ for f in $problematic; do
+@@ -291,7 +294,7 @@ a\
+ done
+ 
+ # Also, break this (generated) line up.  It's ugly as sin.
+-problematic=`grep -l '[^^]Definition at line' *.3`
++problematic=`grep -l '[^^]Definition at line' *.3 *.3cxx`
+ for f in $problematic; do
+     sed 's/Definition at line/\
+ .PP\
+@@ -408,8 +411,8 @@ for f in ios streambuf istream ostream i
+ 	 istringstream ostringstream stringstream filebuf ifstream \
+ 	 ofstream fstream string;
+ do
+-    echo ".so man3/std::basic_${f}.3" > std::${f}.3
+-    echo ".so man3/std::basic_${f}.3" > std::w${f}.3
++    echo ".so man3/std::basic_${f}.3cxx" > std::${f}.3cxx
++    echo ".so man3/std::basic_${f}.3cxx" > std::w${f}.3cxx
+ done
+ 
+ echo ::
--- gcc-6-6.3.0.orig/debian/patches/libstdc++-no-testsuite.diff
+++ gcc-6-6.3.0/debian/patches/libstdc++-no-testsuite.diff
@@ -0,0 +1,12 @@
+# DP: Don't run the libstdc++ testsuite on arm, hppa and mipsel (timeouts on the buildds)
+
+--- a/src/libstdc++-v3/testsuite/Makefile.in
++++ b/src/libstdc++-v3/testsuite/Makefile.in
+@@ -567,6 +567,7 @@
+ 
+ # Run the testsuite in normal mode.
+ check-DEJAGNU $(check_DEJAGNU_normal_targets): check-DEJAGNU%: site.exp
++	case "$(target)" in arm*|hppa*|mipsel*) exit 0;; esac; \
+ 	$(if $*,@)AR="$(AR)"; export AR; \
+ 	RANLIB="$(RANLIB)"; export RANLIB; \
+ 	if [ -z "$*" ] && [ "$(filter -j, $(MFLAGS))" = "-j" ]; then \
--- gcc-6-6.3.0.orig/debian/patches/libstdc++-nothumb-check.diff
+++ gcc-6-6.3.0/debian/patches/libstdc++-nothumb-check.diff
@@ -0,0 +1,38 @@
+# DP: Don't run the libstdc++-v3 testsuite in thumb mode on armel
+
+Index: testsuite/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/testsuite/Makefile.in	(revision 156820)
++++ b/src/libstdc++-v3/testsuite/Makefile.in	(working copy)
+@@ -583,6 +583,8 @@
+ 	srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \
+ 	EXPECT=$(EXPECT); export EXPECT; \
+ 	runtest=$(RUNTEST); \
++	runtestflags="`echo '$(RUNTESTFLAGS)' | sed 's/,-marm/-marm/'`"; \
++	case "$$runtestflags" in *\\{\\}) runtestflags=; esac; \
+ 	if [ -z "$$runtest" ]; then runtest=runtest; fi; \
+ 	tool=libstdc++; \
+ 	dirs=; \
+@@ -590,7 +592,7 @@
+ 	  normal0) \
+ 	    if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+ 	      $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+-			$(RUNTESTFLAGS) abi.exp; \
++			$$runtestflags abi.exp; \
+ 	    else echo "WARNING: could not find \`runtest'" 1>&2; :;\
+ 	    fi; \
+ 	    dirs="`cd $$srcdir; echo [013-9][0-9]_*/* [abep]*/*`";; \
+@@ -605,11 +607,11 @@
+ 	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+ 	  if [ -n "$$dirs" ]; then \
+ 	    $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+-		    $(RUNTESTFLAGS) \
++		    $$runtestflags \
+ 		    "conformance.exp=`echo $$dirs | sed 's/ /* /g;s/$$/*/'`"; \
+ 	  else \
+ 	    $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+-		    $(RUNTESTFLAGS); \
++		    $$runtestflags; \
+ 	  fi; \
+ 	else echo "WARNING: could not find \`runtest'" 1>&2; :;\
+ 	fi
--- gcc-6-6.3.0.orig/debian/patches/libstdc++-pic.diff
+++ gcc-6-6.3.0/debian/patches/libstdc++-pic.diff
@@ -0,0 +1,95 @@
+# DP: Build and install libstdc++_pic.a library.
+
+Index: b/src/libstdc++-v3/src/Makefile.am
+===================================================================
+--- a/src/libstdc++-v3/src/Makefile.am
++++ b/src/libstdc++-v3/src/Makefile.am
+@@ -311,10 +311,12 @@ if GLIBCXX_BUILD_DEBUG
+ STAMP_DEBUG = build-debug
+ STAMP_INSTALL_DEBUG = install-debug
+ CLEAN_DEBUG = debug
++STAMP_INSTALL_PIC = install-pic
+ else
+ STAMP_DEBUG =
+ STAMP_INSTALL_DEBUG =
+ CLEAN_DEBUG =
++STAMP_INSTALL_PIC =
+ endif
+ 
+ # Build a debug variant.
+@@ -349,6 +351,7 @@ build-debug: stamp-debug
+ 	  mv Makefile Makefile.tmp; \
+ 	  sed -e 's,all-local: all-once,all-local:,' \
+ 	      -e 's,install-data-local: install-data-once,install-data-local:,' \
++	      -e 's,install-exec-local:.*,install-exec-local:,' \
+ 	      -e '/vpath/!s,src/c,src/debug/c,' \
+ 	  < Makefile.tmp > Makefile ; \
+ 	  rm -f Makefile.tmp ; \
+@@ -359,3 +362,8 @@ build-debug: stamp-debug
+ install-debug: build-debug
+ 	(cd ${debugdir} && $(MAKE) CXXFLAGS='$(DEBUG_FLAGS)' \
+ 	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install) ;
++
++install-exec-local: $(STAMP_INSTALL_PIC)
++$(STAMP_INSTALL_PIC):
++	$(MKDIR_P) $(DESTDIR)$(toolexeclibdir)
++	$(INSTALL_DATA) .libs/libstdc++convenience.a $(DESTDIR)$(toolexeclibdir)/libstdc++_pic.a
+Index: b/src/libstdc++-v3/src/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/src/Makefile.in
++++ b/src/libstdc++-v3/src/Makefile.in
+@@ -531,6 +531,8 @@ CXXLINK = \
+ @GLIBCXX_BUILD_DEBUG_TRUE@STAMP_INSTALL_DEBUG = install-debug
+ @GLIBCXX_BUILD_DEBUG_FALSE@CLEAN_DEBUG = 
+ @GLIBCXX_BUILD_DEBUG_TRUE@CLEAN_DEBUG = debug
++@GLIBCXX_BUILD_DEBUG_FALSE@STAMP_INSTALL_PIC = 
++@GLIBCXX_BUILD_DEBUG_TRUE@STAMP_INSTALL_PIC = install-pic
+ 
+ # Build a debug variant.
+ # Take care to fix all possibly-relative paths.
+@@ -829,7 +831,7 @@ install-dvi: install-dvi-recursive
+ 
+ install-dvi-am:
+ 
+-install-exec-am: install-toolexeclibLTLIBRARIES
++install-exec-am: install-exec-local install-toolexeclibLTLIBRARIES
+ 
+ install-html: install-html-recursive
+ 
+@@ -880,11 +882,11 @@ uninstall-am: uninstall-toolexeclibLTLIB
+ 	distclean-libtool distclean-tags dvi dvi-am html html-am info \
+ 	info-am install install-am install-data install-data-am \
+ 	install-data-local install-dvi install-dvi-am install-exec \
+-	install-exec-am install-html install-html-am install-info \
+-	install-info-am install-man install-pdf install-pdf-am \
+-	install-ps install-ps-am install-strip \
+-	install-toolexeclibLTLIBRARIES installcheck installcheck-am \
+-	installdirs installdirs-am maintainer-clean \
++	install-exec-am install-exec-local install-html \
++	install-html-am install-info install-info-am install-man \
++	install-pdf install-pdf-am install-ps install-ps-am \
++	install-strip install-toolexeclibLTLIBRARIES installcheck \
++	installcheck-am installdirs installdirs-am maintainer-clean \
+ 	maintainer-clean-generic mostlyclean mostlyclean-compile \
+ 	mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
+ 	tags tags-recursive uninstall uninstall-am \
+@@ -1017,6 +1019,7 @@ build-debug: stamp-debug
+ 	  mv Makefile Makefile.tmp; \
+ 	  sed -e 's,all-local: all-once,all-local:,' \
+ 	      -e 's,install-data-local: install-data-once,install-data-local:,' \
++	      -e 's,install-exec-local:.*,install-exec-local:,' \
+ 	      -e '/vpath/!s,src/c,src/debug/c,' \
+ 	  < Makefile.tmp > Makefile ; \
+ 	  rm -f Makefile.tmp ; \
+@@ -1028,6 +1031,11 @@ install-debug: build-debug
+ 	(cd ${debugdir} && $(MAKE) CXXFLAGS='$(DEBUG_FLAGS)' \
+ 	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install) ;
+ 
++install-exec-local: $(STAMP_INSTALL_PIC)
++$(STAMP_INSTALL_PIC):
++	$(MKDIR_P) $(DESTDIR)$(toolexeclibdir)
++	$(INSTALL_DATA) .libs/libstdc++convenience.a $(DESTDIR)$(toolexeclibdir)/libstdc++_pic.a
++
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
+ .NOEXPORT:
--- gcc-6-6.3.0.orig/debian/patches/libstdc++-test-installed.diff
+++ gcc-6-6.3.0/debian/patches/libstdc++-test-installed.diff
@@ -0,0 +1,78 @@
+# DP: Add support to run the libstdc++-v3 testsuite using the
+# DP: installed shared libraries.
+
+Index: b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
+===================================================================
+--- a/src/libstdc++-v3/testsuite/lib/libstdc++.exp
++++ b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
+@@ -37,6 +37,12 @@
+ # the last thing before testing begins.  This can be defined in, e.g.,
+ # ~/.dejagnurc or $DEJAGNU.
+ 
++set test_installed 0
++if [info exists env(TEST_INSTALLED)] {
++    verbose -log "test installed libstdc++-v3"
++    set test_installed 1
++}
++
+ proc load_gcc_lib { filename } {
+     global srcdir loaded_libs
+ 
+@@ -101,6 +107,7 @@ proc libstdc++_init { testfile } {
+     global tool_timeout
+     global DEFAULT_CXXFLAGS
+     global STATIC_LIBCXXFLAGS
++    global test_installed
+ 
+     # We set LC_ALL and LANG to C so that we get the same error
+     # messages as expected.
+@@ -120,6 +127,9 @@ proc libstdc++_init { testfile } {
+ 
+     set blddir [lookfor_file [get_multilibs] libstdc++-v3]
+     set flags_file "${blddir}/scripts/testsuite_flags"
++    if {$test_installed} {
++      set flags_file "${blddir}/scripts/testsuite_flags.installed"
++    }
+     set shlib_ext [get_shlib_extension]
+     v3track flags_file 2
+ 
+@@ -151,7 +161,11 @@ proc libstdc++_init { testfile } {
+ 
+     # Locate libgcc.a so we don't need to account for different values of
+     # SHLIB_EXT on different platforms
+-    set gccdir [lookfor_file $tool_root_dir gcc/libgcc.a]
++    if {$test_installed} {
++	set gccdir ""
++    } else {
++	set gccdir [lookfor_file $tool_root_dir gcc/libgcc.a]
++    }
+     if {$gccdir != ""} {
+         set gccdir [file dirname $gccdir]
+ 	append ld_library_path_tmp ":${gccdir}"
+@@ -160,7 +174,11 @@ proc libstdc++_init { testfile } {
+ 
+     # Locate libgomp. This is only required for parallel mode.
+     set v3-libgomp 0
+-    set libgompdir [lookfor_file $blddir/../libgomp .libs/libgomp.$shlib_ext]
++    if {$test_installed} {
++	set libgompdir ""
++    } else {
++	set libgompdir [lookfor_file $blddir/../libgomp .libs/libgomp.$shlib_ext]
++    }
+     if {$libgompdir != ""} {
+ 	set v3-libgomp 1
+         set libgompdir [file dirname $libgompdir]
+@@ -182,7 +200,12 @@ proc libstdc++_init { testfile } {
+ 
+     # Locate libstdc++ shared library. (ie libstdc++.so.)
+     set v3-sharedlib 0
+-    set sharedlibdir [lookfor_file $blddir src/.libs/libstdc++.$shlib_ext]
++    if {$test_installed} {
++	set sharedlibdir ""
++	set v3-sharedlib 1
++    } else {
++	set sharedlibdir [lookfor_file $blddir src/.libs/libstdc++.$shlib_ext]
++    }
+     if {$sharedlibdir != ""} {
+ 	if { ([string match "*-*-linux*" $target_triplet]
+ 	      || [string match "*-*-gnu*" $target_triplet])
--- gcc-6-6.3.0.orig/debian/patches/link-libs.diff
+++ gcc-6-6.3.0/debian/patches/link-libs.diff
@@ -0,0 +1,170 @@
+#DP: Link libraries with -01.
+
+---
+ gcc/config/t-slibgcc-elf-ver |    1 +
+ libffi/Makefile.am           |    2 +-
+ libffi/Makefile.in           |    2 +-
+ libgfortran/Makefile.am      |    2 +-
+ libgfortran/Makefile.in      |    2 +-
+ libjava/Makefile.am          |    2 +-
+ libjava/Makefile.in          |    2 +-
+ libmudflap/Makefile.am       |    4 ++--
+ libmudflap/Makefile.in       |    4 ++--
+ libobjc/Makefile.in          |    2 ++
+ libstdc++-v3/src/Makefile.am |    1 +
+ libstdc++-v3/src/Makefile.in |    1 +
+ 12 files changed, 15 insertions(+), 10 deletions(-)
+
+--- a/src/gcc/config/t-slibgcc-elf-ver.orig	2009-09-10
++++ b/src/gcc/config/t-slibgcc-elf-ver	2009-12-22
+@@ -35,6 +35,7 @@
+ SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
+ 	-Wl,--soname=$(SHLIB_SONAME) \
+ 	-Wl,--version-script=$(SHLIB_MAP) \
++	-Wl,-O1 \
+ 	-o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ \
+ 	$(SHLIB_OBJS) $(SHLIB_LC) && \
+ 	rm -f $(SHLIB_DIR)/$(SHLIB_SOLINK) && \
+--- a/src/libffi/Makefile.am.orig	2009-08-23
++++ b/src/libffi/Makefile.am	2009-12-22
+@@ -164,7 +164,7 @@
+ 
+ LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS))
+ 
+-libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS)
++libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -Wl,-O1
+ 
+ AM_CPPFLAGS = -I. -I$(top_srcdir)/include -Iinclude -I$(top_srcdir)/src
+ AM_CCASFLAGS = $(AM_CPPFLAGS)
+--- a/src/libffi/Makefile.in.orig	2009-12-07
++++ b/src/libffi/Makefile.in	2009-12-22
+@@ -468,7 +468,7 @@
+ nodist_libffi_convenience_la_SOURCES = $(nodist_libffi_la_SOURCES)
+ AM_CFLAGS = -Wall -g -fexceptions
+ LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS))
+-libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS)
++libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -Wl,-O1
+ AM_CPPFLAGS = -I. -I$(top_srcdir)/include -Iinclude -I$(top_srcdir)/src
+ AM_CCASFLAGS = $(AM_CPPFLAGS)
+ all: fficonfig.h
+--- a/src/libgfortran/Makefile.am.orig	2009-12-01
++++ b/src/libgfortran/Makefile.am	2009-12-22
+@@ -18,7 +18,7 @@
+ 
+ toolexeclib_LTLIBRARIES = libgfortran.la
+ libgfortran_la_LINK = $(LINK) $(libgfortran_la_LDFLAGS)
+-libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg)
++libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) -Wl,-O1
+ 
+ myexeclib_LTLIBRARIES = libgfortranbegin.la
+ myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+--- a/src/libgfortran/Makefile.in.orig	2009-12-07
++++ b/src/libgfortran/Makefile.in	2009-12-22
+@@ -976,7 +976,7 @@
+ 
+ toolexeclib_LTLIBRARIES = libgfortran.la
+ libgfortran_la_LINK = $(LINK) $(libgfortran_la_LDFLAGS)
+-libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg)
++libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) -Wl,-O1
+ myexeclib_LTLIBRARIES = libgfortranbegin.la
+ myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+ libgfortranbegin_la_SOURCES = fmain.c
+--- a/src/libjava/Makefile.am.orig	2009-12-21
++++ b/src/libjava/Makefile.am	2009-12-22
+@@ -299,7 +299,7 @@
+ GCJ_FOR_ECJX = @GCJ_FOR_ECJX@
+ GCJ_FOR_ECJX_LINK = $(GCJ_FOR_ECJX) -o $@
+ LIBLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXX) -L$(here) \
+-	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -o $@
++	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -Wl,-O1 -o $@
+ CXXLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXXLD) \
+ 	  $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LTLDFLAGS) -o $@
+ 
+--- a/src/libjava/Makefile.in.orig	2009-12-21
++++ b/src/libjava/Makefile.in	2009-12-22
+@@ -1073,7 +1073,7 @@
+ 
+ GCJ_FOR_ECJX_LINK = $(GCJ_FOR_ECJX) -o $@
+ LIBLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXX) -L$(here) \
+-	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -o $@
++	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -Wl,-O1 -o $@
+ 
+ CXXLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXXLD) \
+ 	  $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LTLDFLAGS) -o $@
+--- a/src/libmudflap/Makefile.am.orig	2009-08-23
++++ b/src/libmudflap/Makefile.am	2009-12-22
+@@ -34,7 +34,7 @@
+ 	mf-hooks2.c
+ libmudflap_la_LIBADD = 
+ libmudflap_la_DEPENDENCIES = $(libmudflap_la_LIBADD)
+-libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ 
+ 
+ libmudflapth_la_SOURCES = \
+@@ -46,7 +46,7 @@
+ libmudflapth_la_CFLAGS = -DLIBMUDFLAPTH
+ libmudflapth_la_LIBADD =
+ libmudflapth_la_DEPENDENCIES = $(libmudflapth_la_LIBADD)
+-libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ 
+ 
+ # XXX hack alert
+--- a/src/libmudflap/Makefile.in.orig	2009-12-07
++++ b/src/libmudflap/Makefile.in	2009-12-22
+@@ -320,7 +320,7 @@
+ 
+ libmudflap_la_LIBADD = 
+ libmudflap_la_DEPENDENCIES = $(libmudflap_la_LIBADD)
+-libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ libmudflapth_la_SOURCES = \
+ 	mf-runtime.c \
+ 	mf-heuristics.c \
+@@ -331,7 +331,7 @@
+ libmudflapth_la_CFLAGS = -DLIBMUDFLAPTH
+ libmudflapth_la_LIBADD = 
+ libmudflapth_la_DEPENDENCIES = $(libmudflapth_la_LIBADD)
+-libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ 
+ # XXX hack alert
+ # From libffi/Makefile.am
+--- a/src/libobjc/Makefile.in.orig	2009-08-23
++++ b/src/libobjc/Makefile.in	2009-12-22
+@@ -282,12 +282,14 @@
+ libobjc$(libsuffix).la: $(OBJS)
+ 	$(LIBTOOL_LINK) $(CC) -o $@ $(OBJS) \
+ 		-rpath $(toolexeclibdir) \
++		-Wl,-O1 \
+ 		-version-info $(LIBOBJC_VERSION) $(extra_ldflags_libobjc) \
+ 		$(LTLDFLAGS)
+ 
+ libobjc_gc$(libsuffix).la: $(OBJS_GC)
+ 	$(LIBTOOL_LINK) $(CC) -o $@ $(OBJS_GC) $(OBJC_BOEHM_GC_LIBS) \
+ 		-rpath $(toolexeclibdir) \
++		-Wl,-O1 \
+ 		-version-info $(LIBOBJC_GC_VERSION) $(extra_ldflags_libobjc) \
+ 		$(LTLDFLAGS)
+ 
+--- a/src/libstdc++-v3/src/Makefile.am.orig	2009-12-21
++++ b/src/libstdc++-v3/src/Makefile.am	2009-12-22
+@@ -207,6 +207,7 @@
+ 	$(top_builddir)/libsupc++/libsupc++convenience.la
+ 
+ libstdc___la_LDFLAGS = \
++	-Wl,-O1 \
+ 	-version-info $(libtool_VERSION) ${version_arg} -lm 
+ 
+ libstdc___la_LINK = $(CXXLINK) $(libstdc___la_LDFLAGS)
+--- a/src/libstdc++-v3/src/Makefile.in.orig	2009-12-21
++++ b/src/libstdc++-v3/src/Makefile.in	2009-12-22
+@@ -444,6 +444,7 @@
+ 	$(top_builddir)/libsupc++/libsupc++convenience.la
+ 
+ libstdc___la_LDFLAGS = \
++	-Wl,-O1 \
+ 	-version-info $(libtool_VERSION) ${version_arg} -lm 
+ 
+ libstdc___la_LINK = $(CXXLINK) $(libstdc___la_LDFLAGS)
--- gcc-6-6.3.0.orig/debian/patches/m68k-revert-pr45144.diff
+++ gcc-6-6.3.0/debian/patches/m68k-revert-pr45144.diff
@@ -0,0 +1,20 @@
+[revert the minor PR45144 missed-optimization fix because it
+ results in miscompilation of gnat on m68k with gcc-4.6 and 4.5;
+ with gcc-4.7 other changes mask the issue <mikpe@it.uu.se>]
+
+	PR ada/48835
+
+Index: b/src/gcc/tree-sra.c
+===================================================================
+--- a/src/gcc/tree-sra.c
++++ b/src/gcc/tree-sra.c
+@@ -927,9 +927,6 @@ scalarizable_type_p (tree type)
+ 	{
+ 	  tree ft = TREE_TYPE (fld);
+ 
+-	  if (DECL_BIT_FIELD (fld))
+-	    return false;
+-
+ 	  if (!is_gimple_reg_type (ft)
+ 	      && !scalarizable_type_p (ft))
+ 	    return false;
--- gcc-6-6.3.0.orig/debian/patches/mips-loongson3a-use-fused-madd.d.diff
+++ gcc-6-6.3.0/debian/patches/mips-loongson3a-use-fused-madd.d.diff
@@ -0,0 +1,39 @@
+From 04877b8f39eff7bc35ff4d3bcdd8196ec1449c43 Mon Sep 17 00:00:00 2001
+From: mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu, 19 Jan 2017 16:26:32 +0000
+Subject: [PATCH] MIPS: Make loongson3a use fused madd.d
+
+gcc/
+	* config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
+	TARGET_LOONGSON_3A.
+	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244641 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/ChangeLog          | 6 ++++++
+ gcc/config/mips/mips.h | 6 ++++--
+ 2 files changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/src/gcc/config/mips/mips.h b/src/gcc/config/mips/mips.h
+index 4205589af45..81032c9f94c 100644
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -1066,11 +1066,13 @@ struct mips_cpu_info {
+ 
+ /* ISA has 4 operand fused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_FUSED_MADD4	TARGET_MIPS8000
++#define ISA_HAS_FUSED_MADD4	(TARGET_MIPS8000 || TARGET_LOONGSON_3A)
+ 
+ /* ISA has 4 operand unfused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4 && !TARGET_MIPS8000)
++#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4				\
++				 && !TARGET_MIPS8000			\
++				 && !TARGET_LOONGSON_3A)
+ 
+ /* ISA has 3 operand r6 fused madd instructions of the form
+    'c = c [+-] (a * b)'.  */
+-- 
+2.11.0
+
--- gcc-6-6.3.0.orig/debian/patches/mips-madd4.diff
+++ gcc-6-6.3.0/debian/patches/mips-madd4.diff
@@ -0,0 +1,307 @@
+From eb5c0cb6c16d435f6797cd934ceaac73ac7db52c Mon Sep 17 00:00:00 2001
+From: clm <clm@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Fri, 20 Jan 2017 01:05:25 +0000
+Subject: [PATCH] gcc/ 2017-01-19  Matthew Fortune 
+ <matthew.fortune@imgtec.com> 	    Yunqiang Su  <yunqiang.su@imgtec.com>
+
+	* config.gcc (supported_defaults): Add madd4.
+	(with_madd4): Add validation.
+	(all_defaults): Add madd4.
+	* config/mips/mips.opt (mmadd4): New option.
+	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
+	mmadd4.
+	(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
+	__mips_no_madd4.
+	(ISA_HAS_UNFUSED_MADD4): Gate with mips_madd4.
+	(ISA_HAS_FUSED_MADD4): Likewise.
+	* gcc/doc/invoke.texi (-mmadd4): Document the new option.
+	* gcc/doc/install.texi (--with-madd4): Document the new option.
+
+gcc/testsuite/
+2017-01-19  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* gcc.target/mips/madd4-1.c: New file.
+	* gcc.target/mips/madd4-2.c: Likewise.
+	* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
+	HAS_MADD4.
+	(mips_option_groups): Add -m[no-]madd4.
+	(mips-dg-init): Detect default -mno-madd4.
+	(mips-dg-options): Handle HAS_MADD4 arch upgrade/downgrade.
+	* gcc.target/mips/mips-ps-type.c: Add -mmadd4 test option.
+	* gcc.target/mips/mips-ps-type-2.c: Likewise.
+	* gcc.target/mips/nmadd-1.c: Likewise.
+	* gcc.target/mips/nmadd-2.c: Likewise.
+	* gcc.target/mips/nmadd-3.c: Likewise.
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244676 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/ChangeLog                                  | 16 ++++++++++++++++
+ gcc/config.gcc                                 | 19 +++++++++++++++++--
+ gcc/config/mips/mips.h                         | 12 +++++++++---
+ gcc/config/mips/mips.opt                       |  4 ++++
+ gcc/doc/install.texi                           | 14 ++++++++++++++
+ gcc/doc/invoke.texi                            |  8 +++++++-
+ gcc/testsuite/ChangeLog                        | 15 +++++++++++++++
+ gcc/testsuite/gcc.target/mips/madd4-1.c        | 14 ++++++++++++++
+ gcc/testsuite/gcc.target/mips/madd4-2.c        | 14 ++++++++++++++
+ gcc/testsuite/gcc.target/mips/mips-ps-type-2.c |  2 +-
+ gcc/testsuite/gcc.target/mips/mips-ps-type.c   |  2 +-
+ gcc/testsuite/gcc.target/mips/mips.exp         | 12 +++++++++++-
+ gcc/testsuite/gcc.target/mips/nmadd-1.c        |  2 +-
+ gcc/testsuite/gcc.target/mips/nmadd-2.c        |  2 +-
+ gcc/testsuite/gcc.target/mips/nmadd-3.c        |  2 +-
+ 15 files changed, 126 insertions(+), 12 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/mips/madd4-1.c
+ create mode 100644 gcc/testsuite/gcc.target/mips/madd4-2.c
+
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -3987,7 +3987,7 @@ case "${target}" in
+ 		;;
+ 
+ 	mips*-*-*)
+-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1"
++		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 madd4"
+ 
+ 		case ${with_float} in
+ 		"" | soft | hard)
+@@ -4125,6 +4125,21 @@ case "${target}" in
+ 			exit 1
+ 			;;
+ 		esac
++
++		case ${with_madd4} in
++		yes)
++			with_madd4=madd4
++			;;
++		no)
++			with_madd4=no-madd4
++			;;
++		"")
++			;;
++		*)
++			echo "Unknown madd4 type used in --with-madd4" 1>&2
++			exit 1
++			;;
++		esac
+ 		;;
+ 
+ 	nds32*-*-*)
+@@ -4558,7 +4573,7 @@ case ${target} in
+ esac
+ 
+ t=
+-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1"
++all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4"
+ for option in $all_defaults
+ do
+ 	eval "val=\$with_"`echo $option | sed s/-/_/g`
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -621,6 +621,8 @@ struct mips_cpu_info {
+ 	builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE");		\
+       if (!ISA_HAS_LXC1_SXC1)						\
+ 	builtin_define ("__mips_no_lxc1_sxc1");				\
++      if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4)		\
++	builtin_define ("__mips_no_madd4");				\
+     }									\
+   while (0)
+ 
+@@ -898,7 +900,8 @@ struct mips_cpu_info {
+   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
+   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
+   {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },			\
+-  {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" } \
++  {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
++  {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
+ 
+ /* A spec that infers the:
+    -mnan=2008 setting from a -mips argument,
+@@ -1089,11 +1092,14 @@ struct mips_cpu_info {
+ 
+ /* ISA has 4 operand fused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_FUSED_MADD4	(TARGET_MIPS8000 || TARGET_LOONGSON_3A)
++#define ISA_HAS_FUSED_MADD4	(mips_madd4				\
++				 && (TARGET_MIPS8000			\
++				     || TARGET_LOONGSON_3A))
+ 
+ /* ISA has 4 operand unfused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4				\
++#define ISA_HAS_UNFUSED_MADD4	(mips_madd4				\
++				 && ISA_HAS_FP4				\
+ 				 && !TARGET_MIPS8000			\
+ 				 && !TARGET_LOONGSON_3A)
+ 
+Index: b/src/gcc/config/mips/mips.opt
+===================================================================
+--- a/src/gcc/config/mips/mips.opt
++++ b/src/gcc/config/mips/mips.opt
+@@ -388,6 +388,10 @@ mlxc1-sxc1
+ Target Report Var(mips_lxc1_sxc1) Init(1)
+ Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
+ 
++mmadd4
++Target Report Var(mips_madd4) Init(1)
++Use 4-operand madd.s/madd.d and related instructions where applicable.
++
+ mtune=
+ Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
+ -mtune=PROCESSOR	Optimize the output for PROCESSOR.
+Index: b/src/gcc/testsuite/gcc.target/mips/madd4-1.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/madd4-1.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-ffast-math -mno-madd4 (HAS_MADD4) -mhard-float" } */
++/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
++/* { dg-final { scan-assembler-not "\tmadd.s\t" } } */
++
++#ifndef __mips_no_madd4
++#error missing definition of __mips_no_madd4
++#endif
++
++NOMIPS16 float
++madd4 (float f, float g, float h)
++{
++  return (f * g) + h;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/madd4-2.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/madd4-2.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-ffast-math -mmadd4 (HAS_MADD4) -mhard-float" } */
++/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
++/* { dg-final { scan-assembler "\tmadd.s\t" } } */
++
++#ifdef __mips_no_madd4
++#error unexpected definition of __mips_no_madd4
++#endif
++
++NOMIPS16 float
++madd4 (float f, float g, float h)
++{
++  return (f * g) + h;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
++++ b/src/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
+@@ -1,7 +1,7 @@
+ /* Test v2sf calculations.  The nmadd and nmsub patterns need
+    -ffinite-math-only.  */
+ /* { dg-do compile } */
+-/* { dg-options "(HAS_MADDPS) -mgp32 -mpaired-single -ffinite-math-only forbid_cpu=octeon.*" } */
++/* { dg-options "(HAS_MADDPS) -mmadd4 -mgp32 -mpaired-single -ffinite-math-only forbid_cpu=octeon.*" } */
+ /* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */
+ /* { dg-final { scan-assembler "\tmov.ps\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/mips-ps-type.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips-ps-type.c
++++ b/src/gcc/testsuite/gcc.target/mips/mips-ps-type.c
+@@ -1,7 +1,7 @@
+ /* Test v2sf calculations.  The nmadd and nmsub patterns need
+    -ffinite-math-only.  */
+ /* { dg-do compile } */ 
+-/* { dg-options "-mpaired-single -mgp64 -ffinite-math-only forbid_cpu=octeon.*" } */
++/* { dg-options "-mpaired-single -mmadd4 -mgp64 -ffinite-math-only forbid_cpu=octeon.*" } */
+ /* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */
+ /* { dg-final { scan-assembler "\tmov.ps\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/mips.exp
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips.exp
++++ b/src/gcc/testsuite/gcc.target/mips/mips.exp
+@@ -256,6 +256,7 @@ set mips_option_groups {
+     ldc "HAS_LDC"
+     movn "HAS_MOVN"
+     madd "HAS_MADD"
++    madd4_ghost "HAS_MADD4"
+     maddps "HAS_MADDPS"
+     lsa "(|!)HAS_LSA"
+     lxc1 "HAS_LXC1"
+@@ -283,6 +284,7 @@ foreach option {
+     local-sdata
+     long-calls
+     lxc1-sxc1
++    madd4
+     paired-single
+     plt
+     shared
+@@ -822,6 +824,12 @@ proc mips-dg-init {} {
+ 	    "-mlxc1-sxc1"
+ 	    #endif
+ 
++	    #ifdef __mips_no_madd4
++	    "-mno-madd4"
++	    #else
++	    "-mmadd4"
++	    #endif
++
+ 	    #ifdef __mips_synci
+ 	    "-msynci",
+ 	    #else
+@@ -1132,6 +1140,7 @@ proc mips-dg-options { args } {
+ 	#
+ 	} elseif { $isa < 4
+ +		   && ([mips_have_test_option_p options "HAS_LXC1"]
+++		       || [mips_have_test_option_p options "HAS_MADD4"]
+ +		       || [mips_have_test_option_p options "HAS_MOVN"]) } {
+ 	    mips_make_test_option options "-mips4"
+         # We need MIPS III or higher for:
+@@ -1174,8 +1183,9 @@ proc mips-dg-options { args } {
+ 		       || [mips_have_test_option_p options "-mfix-r10000"]
+ 		       || [mips_have_test_option_p options "NOT_HAS_DMUL"]
+ 		       || [mips_have_test_option_p options "HAS_LXC1"]
+-		       || [mips_have_test_option_p options "HAS_MOVN"]
+ 		       || [mips_have_test_option_p options "HAS_MADD"]
++		       || [mips_have_test_option_p options "HAS_MADD4"]
++		       || [mips_have_test_option_p options "HAS_MOVN"]
+ 		       || [mips_have_test_option_p options "-mpaired-single"]
+ 		       || [mips_have_test_option_p options "-mnan=legacy"]
+ 		       || [mips_have_test_option_p options "-mabs=legacy"]
+Index: b/src/gcc/testsuite/gcc.target/mips/nmadd-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/nmadd-1.c
++++ b/src/gcc/testsuite/gcc.target/mips/nmadd-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-ffast-math isa=4 -mhard-float" } */
++/* { dg-options "-ffast-math -mmadd4 isa=4 -mhard-float" } */
+ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tnmadd.s\t" } } */
+ /* { dg-final { scan-assembler "\tnmadd.d\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/nmadd-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/nmadd-2.c
++++ b/src/gcc/testsuite/gcc.target/mips/nmadd-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-fno-fast-math -ffinite-math-only isa=4 -mhard-float" } */
++/* { dg-options "-fno-fast-math -ffinite-math-only -mmadd4 isa=4 -mhard-float" } */
+ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tnmadd.s\t" } } */
+ /* { dg-final { scan-assembler "\tnmadd.d\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/nmadd-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/nmadd-3.c
++++ b/src/gcc/testsuite/gcc.target/mips/nmadd-3.c
+@@ -1,7 +1,7 @@
+ /* The same code as nmadd-2.c, but compiled with -fno-finite-math-only.
+    We can't use nmadd and nmsub in that case.  */
+ /* { dg-do compile } */
+-/* { dg-options "-fno-fast-math -fno-finite-math-only isa=4 -mhard-float" } */
++/* { dg-options "-fno-fast-math -fno-finite-math-only -mmadd4 isa=4 -mhard-float" } */
+ /* { dg-final { scan-assembler-not "\tnmadd" } } */
+ /* { dg-final { scan-assembler-not "\tnmsub" } } */
+ 
--- gcc-6-6.3.0.orig/debian/patches/mips-pr78176-add-mlxc1-sxc1.diff
+++ gcc-6-6.3.0/debian/patches/mips-pr78176-add-mlxc1-sxc1.diff
@@ -0,0 +1,321 @@
+From fccc4b5408942b92bc00bc053f4da9af2109557c Mon Sep 17 00:00:00 2001
+From: mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu, 19 Jan 2017 16:05:59 +0000
+Subject: [PATCH] MIPS: PR target/78176 add -mlxc1-sxc1.
+
+gcc/
+
+	PR target/78176
+	* config.gcc (supported_defaults): Add lxc1-sxc1.
+	(with_lxc1_sxc1): Add validation.
+	(all_defaults): Add lxc1-sxc1.
+	* config/mips/mips.opt (mlxc1-sxc1): New option.
+	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
+	mlxc1-sxc1.
+	(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
+	__mips_no_lxc1_sxc1.
+	(ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1.
+	* gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option.
+	* doc/install.texi (--with-lxc1-sxc1): Document the new option.
+
+gcc/testsuite/
+
+	* gcc.target/mips/lxc1-sxc1-1.c: New file.
+	* gcc.target/mips/lxc1-sxc1-2.c: Likewise.
+	* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
+	HAS_LXC1.
+	(mips_option_groups): Add -m[no-]lxc1-sxc1.
+	(mips-dg-init): Detect default -mno-lxc1-sxc1.
+	(mips-dg-options): Handle HAS_LXC1 arch upgrade/downgrade.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244640 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/ChangeLog                               | 15 ++++++++
+ gcc/config.gcc                              | 19 ++++++++-
+ gcc/config/mips/mips.h                      |  8 +++-
+ gcc/config/mips/mips.opt                    |  4 ++
+ gcc/doc/install.texi                        | 19 +++++++++
+ gcc/doc/invoke.texi                         |  6 +++
+ gcc/testsuite/ChangeLog                     | 11 ++++++
+ gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c | 60 +++++++++++++++++++++++++++++
+ gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c | 60 +++++++++++++++++++++++++++++
+ gcc/testsuite/gcc.target/mips/mips.exp      | 12 +++++-
+ 10 files changed, 209 insertions(+), 5 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c
+ create mode 100644 gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c
+
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -3987,7 +3987,7 @@ case "${target}" in
+ 		;;
+ 
+ 	mips*-*-*)
+-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
++		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1"
+ 
+ 		case ${with_float} in
+ 		"" | soft | hard)
+@@ -4110,6 +4110,21 @@ case "${target}" in
+ 			exit 1
+ 			;;
+ 		esac
++
++		case ${with_lxc1_sxc1} in
++		yes)
++			with_lxc1_sxc1=lxc1-sxc1
++			;;
++		no)
++			with_lxc1_sxc1=no-lxc1-sxc1
++			;;
++		"")
++			;;
++		*)
++			echo "Unknown lxc1-sxc1 type used in --with-lxc1-sxc1" 1>&2
++			exit 1
++			;;
++		esac
+ 		;;
+ 
+ 	nds32*-*-*)
+@@ -4543,7 +4558,7 @@ case ${target} in
+ esac
+ 
+ t=
+-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls"
++all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1"
+ for option in $all_defaults
+ do
+ 	eval "val=\$with_"`echo $option | sed s/-/_/g`
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -619,6 +619,8 @@ struct mips_cpu_info {
+ 									\
+       if (TARGET_CACHE_BUILTIN)						\
+ 	builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE");		\
++      if (!ISA_HAS_LXC1_SXC1)						\
++	builtin_define ("__mips_no_lxc1_sxc1");				\
+     }									\
+   while (0)
+ 
+@@ -895,7 +897,8 @@ struct mips_cpu_info {
+   {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
+   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
+   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
+-  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
++  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },			\
++  {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" } \
+ 
+ /* A spec that infers the:
+    -mnan=2008 setting from a -mips argument,
+@@ -1059,7 +1062,8 @@ struct mips_cpu_info {
+ 
+ /* ISA has floating-point indexed load and store instructions
+    (LWXC1, LDXC1, SWXC1 and SDXC1).  */
+-#define ISA_HAS_LXC1_SXC1	ISA_HAS_FP4
++#define ISA_HAS_LXC1_SXC1	(ISA_HAS_FP4				\
++				 && mips_lxc1_sxc1)
+ 
+ /* ISA has paired-single instructions.  */
+ #define ISA_HAS_PAIRED_SINGLE	((ISA_MIPS64				\
+Index: b/src/gcc/config/mips/mips.opt
+===================================================================
+--- a/src/gcc/config/mips/mips.opt
++++ b/src/gcc/config/mips/mips.opt
+@@ -384,6 +384,10 @@ mlra
+ Target Report Var(mips_lra_flag) Init(1) Save
+ Use LRA instead of reload.
+ 
++mlxc1-sxc1
++Target Report Var(mips_lxc1_sxc1) Init(1)
++Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
++
+ mtune=
+ Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
+ -mtune=PROCESSOR	Optimize the output for PROCESSOR.
+Index: b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c
+@@ -0,0 +1,60 @@
++/* { dg-options "(HAS_LXC1) -mno-lxc1-sxc1" } */
++/* { dg-final { scan-assembler-not "\tldxc1\t" } } */
++/* { dg-final { scan-assembler-not "\tsdxc1\t" } } */
++
++#ifndef __mips_no_lxc1_sxc1
++#error missing definition of __mips_no_lxc1_sxc1
++#endif
++
++double ldexp(double x, int exp);
++
++typedef struct
++{
++  double** rows;
++} d_mat_struct;
++
++typedef d_mat_struct d_mat_t[1];
++
++#define d_mat_entry(mat,i,j) (*((mat)->rows[i] + (j)))
++
++double __attribute__((noinline))
++ldxc1_test (int kappa, int zeros, double ctt, int* expo, d_mat_t r, double* s)
++{
++  int kappa2 = kappa;
++  double tmp = 0.0;
++
++  do
++    {
++      kappa--;
++      if (kappa > zeros + 1)
++	{
++	  tmp = d_mat_entry(r, kappa - 1, kappa - 1) * ctt;
++	  tmp = ldexp(tmp, (expo[kappa - 1] - expo[kappa2]));
++	}
++    }
++  while ((kappa >= zeros + 2) && (s[kappa - 1] <= tmp));
++
++  return tmp;
++}
++
++#define SIZE 20
++
++int main(void)
++{
++  int kappa = SIZE - 1;
++  int zeros = 1;
++  double ctt = 2;
++
++  int expo[SIZE] = {0};
++  double s[SIZE] = {0};
++  double rows_data[SIZE][SIZE] = {0};
++  double* rows[SIZE];
++
++  for (int i = 0; i < SIZE; i++)
++    rows[i] = rows_data[i];
++
++  d_mat_t r = { rows };
++
++  ldxc1_test(kappa, zeros, ctt, expo, r, s);
++  return 0;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c
+@@ -0,0 +1,60 @@
++/* { dg-options "(HAS_LXC1) -mlxc1-sxc1" } */
++/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
++/* { dg-final { scan-assembler "\tldxc1\t" } } */
++
++#ifdef __mips_no_lxc1_sxc1
++#error unexpected definition of __mips_no_lxc1_sxc1
++#endif
++
++double ldexp(double x, int exp);
++
++typedef struct
++{
++  double** rows;
++} d_mat_struct;
++
++typedef d_mat_struct d_mat_t[1];
++
++#define d_mat_entry(mat,i,j) (*((mat)->rows[i] + (j)))
++
++double __attribute__((noinline))
++ldxc1_test (int kappa, int zeros, double ctt, int* expo, d_mat_t r, double* s)
++{
++  int kappa2 = kappa;
++  double tmp = 0.0;
++
++  do
++    {
++      kappa--;
++      if (kappa > zeros + 1)
++	{
++	  tmp = d_mat_entry(r, kappa - 1, kappa - 1) * ctt;
++	  tmp = ldexp(tmp, (expo[kappa - 1] - expo[kappa2]));
++	}
++    }
++  while ((kappa >= zeros + 2) && (s[kappa - 1] <= tmp));
++
++  return tmp;
++}
++
++#define SIZE 20
++
++int main(void)
++{
++  int kappa = SIZE - 1;
++  int zeros = 1;
++  double ctt = 2;
++
++  int expo[SIZE] = {0};
++  double s[SIZE] = {0};
++  double rows_data[SIZE][SIZE] = {0};
++  double* rows[SIZE];
++
++  for (int i = 0; i < SIZE; i++)
++    rows[i] = rows_data[i];
++
++  d_mat_t r = { rows };
++
++  ldxc1_test(kappa, zeros, ctt, expo, r, s);
++  return 0;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/mips.exp
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips.exp
++++ b/src/gcc/testsuite/gcc.target/mips/mips.exp
+@@ -258,6 +258,7 @@ set mips_option_groups {
+     madd "HAS_MADD"
+     maddps "HAS_MADDPS"
+     lsa "(|!)HAS_LSA"
++    lxc1 "HAS_LXC1"
+     section_start "-Wl,--section-start=.*"
+     frame-header "-mframe-header-opt|-mno-frame-header-opt"
+     stack-protector "-fstack-protector"
+@@ -281,6 +282,7 @@ foreach option {
+     gpopt
+     local-sdata
+     long-calls
++    lxc1-sxc1
+     paired-single
+     plt
+     shared
+@@ -814,6 +816,12 @@ proc mips-dg-init {} {
+ 	    "-mno-smartmips",
+ 	    #endif
+ 
++	    #ifdef __mips_no_lxc1_sxc1
++	    "-mno-lxc1-sxc1",
++	    #else
++	    "-mlxc1-sxc1"
++	    #endif
++
+ 	    #ifdef __mips_synci
+ 	    "-msynci",
+ 	    #else
+@@ -1122,8 +1130,9 @@ proc mips-dg-options { args } {
+         # We need MIPS IV or higher for:
+ 	#
+ 	#
+-	} elseif { $isa < 3
+-		   && [mips_have_test_option_p options "HAS_MOVN"] } {
++	} elseif { $isa < 4
+++		   && ([mips_have_test_option_p options "HAS_LXC1"]
+++		       || [mips_have_test_option_p options "HAS_MOVN"]) } {
+ 	    mips_make_test_option options "-mips4"
+         # We need MIPS III or higher for:
+ 	#
+@@ -1164,6 +1173,7 @@ proc mips-dg-options { args } {
+ 		       || [mips_have_test_option_p options "-mfp32"]
+ 		       || [mips_have_test_option_p options "-mfix-r10000"]
+ 		       || [mips_have_test_option_p options "NOT_HAS_DMUL"]
++		       || [mips_have_test_option_p options "HAS_LXC1"]
+ 		       || [mips_have_test_option_p options "HAS_MOVN"]
+ 		       || [mips_have_test_option_p options "HAS_MADD"]
+ 		       || [mips_have_test_option_p options "-mpaired-single"]
--- gcc-6-6.3.0.orig/debian/patches/note-gnu-stack.diff
+++ gcc-6-6.3.0/debian/patches/note-gnu-stack.diff
@@ -0,0 +1,186 @@
+# DP: Add .note.GNU-stack sections for gcc's crt files, libffi and boehm-gc
+# DP: Taken from FC.
+
+gcc/
+
+2004-09-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/rs6000/ppc-asm.h: Add .note.GNU-stack section also
+	on ppc64-linux.
+
+	* config/ia64/lib1funcs.asm: Add .note.GNU-stack section on
+	ia64-linux.
+	* config/ia64/crtbegin.asm: Likewise.
+	* config/ia64/crtend.asm: Likewise.
+	* config/ia64/crti.asm: Likewise.
+	* config/ia64/crtn.asm: Likewise.
+
+2004-05-14  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/ia64/linux.h (TARGET_ASM_FILE_END): Define.
+
+boehm-gc/
+
+2005-02-08  Jakub Jelinek  <jakub@redhat.com>
+
+	* ia64_save_regs_in_stack.s: Moved to...
+	* ia64_save_regs_in_stack.S: ... this.  Add .note.GNU-stack
+	on Linux.
+
+libffi/
+
+2007-05-11  Daniel Jacobowitz  <dan@debian.org>
+
+	* src/arm/sysv.S: Fix ARM comment marker.
+
+2005-02-08  Jakub Jelinek  <jakub@redhat.com>
+
+	* src/alpha/osf.S: Add .note.GNU-stack on Linux.
+	* src/s390/sysv.S: Likewise.
+	* src/powerpc/linux64.S: Likewise.
+	* src/powerpc/linux64_closure.S: Likewise.
+	* src/powerpc/ppc_closure.S: Likewise.
+	* src/powerpc/sysv.S: Likewise.
+	* src/x86/unix64.S: Likewise.
+	* src/x86/sysv.S: Likewise.
+	* src/sparc/v8.S: Likewise.
+	* src/sparc/v9.S: Likewise.
+	* src/m68k/sysv.S: Likewise.
+	* src/ia64/unix.S: Likewise.
+	* src/arm/sysv.S: Likewise.
+
+---
+ boehm-gc/ia64_save_regs_in_stack.S   |   15 +++++++++++++++
+ boehm-gc/ia64_save_regs_in_stack.s   |   12 ------------
+ gcc/config/ia64/linux.h              |    3 +++
+ gcc/config/rs6000/ppc-asm.h          |    2 +-
+ libgcc/config/ia64/crtbegin.S        |    4 ++++
+ libgcc/config/ia64/crtend.S          |    4 ++++
+ libgcc/config/ia64/crti.S            |    4 ++++
+ libgcc/config/ia64/crtn.S            |    4 ++++
+ libgcc/config/ia64/lib1funcs.S       |    4 ++++
+ 9 files changed, 39 insertions(+), 13 deletions(-)
+
+Index: b/src/boehm-gc/ia64_save_regs_in_stack.s
+===================================================================
+--- a/src/boehm-gc/ia64_save_regs_in_stack.s
++++ /dev/null
+@@ -1,12 +0,0 @@
+-        .text
+-        .align 16
+-        .global GC_save_regs_in_stack
+-        .proc GC_save_regs_in_stack
+-GC_save_regs_in_stack:
+-        .body
+-        flushrs
+-        ;;
+-        mov r8=ar.bsp
+-        br.ret.sptk.few rp
+-        .endp GC_save_regs_in_stack
+-
+Index: b/src/boehm-gc/ia64_save_regs_in_stack.S
+===================================================================
+--- /dev/null
++++ b/src/boehm-gc/ia64_save_regs_in_stack.S
+@@ -0,0 +1,15 @@
++        .text
++        .align 16
++        .global GC_save_regs_in_stack
++        .proc GC_save_regs_in_stack
++GC_save_regs_in_stack:
++        .body
++        flushrs
++        ;;
++        mov r8=ar.bsp
++        br.ret.sptk.few rp
++        .endp GC_save_regs_in_stack
++
++#ifdef __linux__
++	.section .note.GNU-stack,"",@progbits
++#endif
+Index: b/src/libgcc/config/ia64/crtbegin.S
+===================================================================
+--- a/src/libgcc/config/ia64/crtbegin.S
++++ b/src/libgcc/config/ia64/crtbegin.S
+@@ -252,3 +252,7 @@ __do_jv_register_classes:
+ .weak __cxa_finalize
+ #endif
+ .weak _Jv_RegisterClasses
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/crtend.S
+===================================================================
+--- a/src/libgcc/config/ia64/crtend.S
++++ b/src/libgcc/config/ia64/crtend.S
+@@ -119,3 +119,7 @@ __do_global_ctors_aux:
+ 
+ 	br.ret.sptk.many rp
+ 	.endp __do_global_ctors_aux
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/crti.S
+===================================================================
+--- a/src/libgcc/config/ia64/crti.S
++++ b/src/libgcc/config/ia64/crti.S
+@@ -51,3 +51,7 @@ _fini:
+ 	.body
+ 
+ # end of crti.S
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/crtn.S
+===================================================================
+--- a/src/libgcc/config/ia64/crtn.S
++++ b/src/libgcc/config/ia64/crtn.S
+@@ -41,3 +41,7 @@
+ 	br.ret.sptk.many b0
+ 
+ # end of crtn.S
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/lib1funcs.S
+===================================================================
+--- a/src/libgcc/config/ia64/lib1funcs.S
++++ b/src/libgcc/config/ia64/lib1funcs.S
+@@ -793,3 +793,7 @@ __floattitf:
+ 	.endp __floattitf
+ #endif
+ #endif
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -79,5 +79,8 @@ do {						\
+ #undef TARGET_INIT_LIBFUNCS
+ #define TARGET_INIT_LIBFUNCS ia64_soft_fp_init_libfuncs
+ 
++#undef TARGET_ASM_FILE_END
++#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
++
+ /* Define this to be nonzero if static stack checking is supported.  */
+ #define STACK_CHECK_STATIC_BUILTIN 1
+Index: b/src/gcc/config/rs6000/ppc-asm.h
+===================================================================
+--- a/src/gcc/config/rs6000/ppc-asm.h
++++ b/src/gcc/config/rs6000/ppc-asm.h
+@@ -375,7 +375,7 @@ GLUE(.L,name): \
+ #endif
+ #endif
+ 
+-#if defined __linux__ && !defined __powerpc64__
++#if defined __linux__
+ 	.section .note.GNU-stack
+ 	.previous
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/powerpc_nofprs.diff
+++ gcc-6-6.3.0/debian/patches/powerpc_nofprs.diff
@@ -0,0 +1,75 @@
+--- a/src/libgcc/config/rs6000/crtsavfpr.S
++++ b/src/libgcc/config/rs6000/crtsavfpr.S
+@@ -33,6 +33,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ /* Routines for saving floating point registers, called by the compiler.  */
+ /* Called with r11 pointing to the stack header word of the caller of the */
+@@ -79,3 +80,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtresfpr.S
++++ b/src/libgcc/config/rs6000/crtresfpr.S
+@@ -33,6 +33,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ /* Routines for restoring floating point registers, called by the compiler.  */
+ /* Called with r11 pointing to the stack header word of the caller of the */
+@@ -79,3 +80,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtresxfpr.S
++++ b/src/libgcc/config/rs6000/crtresxfpr.S
+@@ -33,6 +33,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ /* Routines for restoring floating point registers, called by the compiler.  */
+ /* Called with r11 pointing to the stack header word of the caller of the */
+@@ -124,3 +125,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtsavevr.S	2013-03-13 22:25:25.802681336 +0000
++++ b/src/libgcc/config/rs6000/crtsavevr.S	2013-03-13 22:26:21.054695066 +0000
+@@ -24,6 +24,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ #undef __ALTIVEC__
+ #define __ALTIVEC__ 1
+@@ -85,3 +86,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtrestvr.S	2013-03-13 22:25:28.394681980 +0000
++++ b/src/libgcc/config/rs6000/crtrestvr.S	2013-03-13 22:26:21.058695067 +0000
+@@ -24,6 +24,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ #undef __ALTIVEC__
+ #define __ALTIVEC__ 1
+@@ -85,3 +86,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
--- gcc-6-6.3.0.orig/debian/patches/powerpc_remove_many.diff
+++ gcc-6-6.3.0/debian/patches/powerpc_remove_many.diff
@@ -0,0 +1,32 @@
+# DP: Subject: [PATCH] remove -many on __SPE__ target
+# DP: this helps to to detect opcodes which are not part of the current
+# DP: CPU because without -many gas won't touch them. This currently could
+# DP: break the kernel build as the 603 on steroids cpus use performance
+# DP: counter opcodes which are not available on the steroid less 603 core.
+
+--- a/src/gcc/config/rs6000/rs6000.h
++++ b/src/gcc/config/rs6000/rs6000.h
+@@ -98,6 +98,12 @@
+ #define ASM_CPU_476_SPEC "-mpower4"
+ #endif
+ 
++#ifndef __SPE__
++#define ASM_CPU_SPU_MANY_NOT_SPE "-many"
++#else
++#define ASM_CPU_SPU_MANY_NOT_SPE
++#endif
++
+ /* Common ASM definitions used by ASM_SPEC among the various targets for
+    handling -mcpu=xxx switches.  There is a parallel list in driver-rs6000.c to
+    provide the default assembler options if the user uses -mcpu=native, so if
+@@ -170,7 +176,8 @@
+ %{mcpu=e500mc64: -me500mc64} \
+ %{maltivec: -maltivec} \
+ %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
+ %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
+--many"
++" \
++ASM_CPU_SPU_MANY_NOT_SPE
+ 
+ #define CPP_DEFAULT_SPEC ""
+ 
--- gcc-6-6.3.0.orig/debian/patches/pr39491.diff
+++ gcc-6-6.3.0/debian/patches/pr39491.diff
@@ -0,0 +1,132 @@
+# DP: Proposed patch for PR libstdc++/39491.
+
+2009-04-16  Benjamin Kosnik  <bkoz@redhat.com>
+
+	* src/math_stubs_long_double.cc (__signbitl): Add for hppa linux only.
+
+Index: a/src/libstdc++-v3/src/math_stubs_long_double.cc
+===================================================================
+--- a/src/libstdc++-v3/src/math_stubs_long_double.cc	(revision 146216)
++++ b/src/libstdc++-v3/src/math_stubs_long_double.cc	(working copy)
+@@ -213,4 +221,111 @@
+     return tanh((double) x);
+   }
+ #endif
++
++  // From libmath/signbitl.c
++  // XXX ABI mistakenly exported
++#if defined (__hppa__) && defined (__linux__)
++# include <endian.h>
++# include <float.h>
++
++typedef unsigned int U_int32_t __attribute ((mode (SI)));
++typedef int Int32_t __attribute ((mode (SI)));
++typedef unsigned int U_int64_t __attribute ((mode (DI)));
++typedef int Int64_t __attribute ((mode (DI)));
++
++#if BYTE_ORDER == BIG_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    unsigned int sign_exponent:16;
++    unsigned int empty:16;
++    U_int32_t msw;
++    U_int32_t lsw;
++  } parts;
++} ieee_long_double_shape_type;
++#endif
++#if BYTE_ORDER == LITTLE_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    U_int32_t lsw;
++    U_int32_t msw;
++    unsigned int sign_exponent:16;
++    unsigned int empty:16;
++  } parts;
++} ieee_long_double_shape_type;
++#endif
++
++/* Get int from the exponent of a long double.  */
++#define GET_LDOUBLE_EXP(exp,d)                                  \
++do {                                                            \
++  ieee_long_double_shape_type ge_u;                             \
++  ge_u.value = (d);                                             \
++  (exp) = ge_u.parts.sign_exponent;                             \
++} while (0)
++
++#if BYTE_ORDER == BIG_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    U_int64_t msw;
++    U_int64_t lsw;
++  } parts64;
++  struct
++  {
++    U_int32_t w0, w1, w2, w3;
++  } parts32;
++} ieee_quad_double_shape_type;
++#endif
++
++#if BYTE_ORDER == LITTLE_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    U_int64_t lsw;
++    U_int64_t msw;
++  } parts64;
++  struct
++  {
++    U_int32_t w3, w2, w1, w0;
++  } parts32;
++} ieee_quad_double_shape_type;
++#endif
++
++/* Get most significant 64 bit int from a quad long double.  */
++#define GET_LDOUBLE_MSW64(msw,d)				\
++do {								\
++  ieee_quad_double_shape_type qw_u;				\
++  qw_u.value = (d);						\
++  (msw) = qw_u.parts64.msw;					\
++} while (0)
++
++int
++__signbitl (long double x)
++{
++#if LDBL_MANT_DIG == 113
++  Int64_t msw;
++
++  GET_LDOUBLE_MSW64 (msw, x);
++  return msw < 0;
++#else
++  Int32_t e;
++
++  GET_LDOUBLE_EXP (e, x);
++  return e & 0x8000;
++#endif
++}
++#endif
++
++#ifndef _GLIBCXX_HAVE___SIGNBITL
++
++#endif
+ } // extern "C"
+--- a/src/libstdc++-v3/config/abi/pre/gnu.ver~	2009-04-10 01:23:07.000000000 +0200
++++ b/src/libstdc++-v3/config/abi/pre/gnu.ver	2009-04-21 16:24:24.000000000 +0200
+@@ -635,6 +635,7 @@
+     sqrtf;
+     sqrtl;
+     copysignf;
++    __signbitl;
+ 
+    # GLIBCXX_ABI compatibility only.
+     # std::string
--- gcc-6-6.3.0.orig/debian/patches/pr47818.diff
+++ gcc-6-6.3.0/debian/patches/pr47818.diff
@@ -0,0 +1,24 @@
+# DP: Fix PR ada/47818: Pragma Assert is rejected with No_Implementation_Pragmas restriction.
+
+Index: b/src/gcc/ada/sem_prag.adb
+===================================================================
+--- a/src/gcc/ada/sem_prag.adb
++++ b/src/gcc/ada/sem_prag.adb
+@@ -16306,7 +16306,16 @@ package body Sem_Prag is
+             Type_Id : Node_Id;
+ 
+          begin
+-            GNAT_Pragma;
++            --  This could be a rewritten pragma Assert. If it is the case
++            --  then don't check restrictions, because they are different for
++            --  pragma Assert and were already checked.
++
++            if Nkind (Original_Node (N)) /= N_Pragma
++              or else Pragma_Name (Original_Node (N)) /= Name_Assert
++            then
++               GNAT_Pragma;
++            end if;
++
+             Check_At_Least_N_Arguments (2);
+             Check_At_Most_N_Arguments  (3);
+             Check_Optional_Identifier (Arg1, Name_Entity);
--- gcc-6-6.3.0.orig/debian/patches/pr64735-headers.diff
+++ gcc-6-6.3.0/debian/patches/pr64735-headers.diff
@@ -0,0 +1,60 @@
+--- a/src/libstdc++-v3/include/std/future
++++ b/src/libstdc++-v3/include/std/future
+@@ -183,7 +183,7 @@
+     async(_Fn&& __fn, _Args&&... __args);
+ 
+ #if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) \
+-  && (ATOMIC_INT_LOCK_FREE > 1)
++  && ((ATOMIC_INT_LOCK_FREE > 1) || (defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP)))
+ 
+   /// Base class and enclosing scope.
+   struct __future_base
+--- a/src/libstdc++-v3/libsupc++/exception_ptr.h
++++ b/src/libstdc++-v3/libsupc++/exception_ptr.h
+@@ -36,9 +36,11 @@
+ #include <bits/c++config.h>
+ #include <bits/exception_defines.h>
+ 
++#if !(defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP))
+ #if ATOMIC_INT_LOCK_FREE < 2
+ #  error This platform does not support exception propagation.
+ #endif
++#endif
+ 
+ extern "C++" {
+ 
+--- a/src/libstdc++-v3/libsupc++/nested_exception.h
++++ b/src/libstdc++-v3/libsupc++/nested_exception.h
+@@ -39,9 +39,11 @@
+ #include <bits/c++config.h>
+ #include <bits/move.h>
+ 
++#if !(defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP))
+ #if ATOMIC_INT_LOCK_FREE < 2
+ #  error This platform does not support exception propagation.
+ #endif
++#endif
+ 
+ extern "C++" {
+ 
+--- a/src/libstdc++-v3/libsupc++/exception
++++ b/src/libstdc++-v3/libsupc++/exception
+@@ -35,7 +35,9 @@
+ #pragma GCC visibility push(default)
+ 
+ #include <bits/c++config.h>
++#if !(defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP))
+ #include <bits/atomic_lockfree_defines.h>
++#endif
+ 
+ extern "C++" {
+ 
+@@ -166,7 +168,7 @@
+ 
+ #pragma GCC visibility pop
+ 
+-#if (__cplusplus >= 201103L) && (ATOMIC_INT_LOCK_FREE > 1)
++#if (__cplusplus >= 201103L) && ((ATOMIC_INT_LOCK_FREE > 1) || (defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP)))
+ #include <bits/exception_ptr.h>
+ #include <bits/nested_exception.h>
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/pr64735.diff
+++ gcc-6-6.3.0/debian/patches/pr64735.diff
@@ -0,0 +1,1610 @@
+# DP: Proposed patch for PR libstdc++/64735
+
+commit e81e908deb699886e65cb4d614f6a0a1cf54662f
+Author: Jonathan Wakely <jwakely@redhat.com>
+Date:   Fri Dec 16 15:22:21 2016 +0000
+
+    PR64735 support exception propagation without atomics
+    
+    2016-11-09  Pauli Nieminen  <suokkos@gmail.com>
+    	    Jonathan Wakely  <jwakely@redhat.com>
+    
+    	PR libstdc++/64735
+    	* include/std/future: Remove check for ATOMIC_INT_LOCK_FREE
+    	* libsupc++/eh_atomics.h: New file for internal use only.
+    	(__eh_atomic_inc, __eh_atomic_dec): New.
+    	* libsupc++/eh_ptr.cc (exception_ptr::_M_addref)
+    	(exception_ptr::_M_release) (__gxx_dependent_exception_cleanup)
+    	(rethrow_exception): Use eh_atomics.h reference counting helpers.
+    	* libsupc++/eh_throw.cc (__gxx_exception_cleanup): Likewise.
+    	* libsupc++/eh_tm.cc (free_any_cxa_exception): Likewise.
+    	* libsupc++/exception: Remove check for ATOMIC_INT_LOCK_FREE.
+    	* libsupc++/exception_ptr.h: Likewise.
+    	* libsupc++/guard.cc: Include header for ATOMIC_INT_LOCK_FREE macro.
+    	* libsupc++/nested_exception.cc: Remove check for
+    	ATOMIC_INT_LOCK_FREE.
+    	* libsupc++/nested_exception.h: Likewise.
+    	* src/c++11/future.cc: Likewise.
+    	* testsuite/18_support/exception_ptr/*: Remove atomic builtins checks.
+    	* testsuite/18_support/nested_exception/*: Likewise.
+    	* testsuite/30_threads/async/*: Likewise.
+    	* testsuite/30_threads/future/*: Likewise.
+    	* testsuite/30_threads/headers/future/types_std_c++0x.cc: Likewise.
+    	* testsuite/30_threads/packaged_task/*: Likewise.
+    	* testsuite/30_threads/promise/*: Likewise.
+    	* testsuite/30_threads/shared_future/*: Likewise.
+
+#Index: b/src/libstdc++-v3/include/std/future
+#===================================================================
+#--- a/src/libstdc++-v3/include/std/future
+#+++ b/src/libstdc++-v3/include/std/future
+#@@ -182,8 +182,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+#     future<__async_result_of<_Fn, _Args...>>
+#     async(_Fn&& __fn, _Args&&... __args);
+# 
+#-#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) \
+#-  && (ATOMIC_INT_LOCK_FREE > 1)
+#+#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1)
+# 
+#   /// Base class and enclosing scope.
+#   struct __future_base
+#@@ -1745,7 +1744,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+# 
+# #endif // _GLIBCXX_ASYNC_ABI_COMPAT
+# #endif // _GLIBCXX_HAS_GTHREADS && _GLIBCXX_USE_C99_STDINT_TR1
+#-       // && ATOMIC_INT_LOCK_FREE
+# 
+#   // @} group futures
+# _GLIBCXX_END_NAMESPACE_VERSION
+Index: b/src/libstdc++-v3/libsupc++/eh_atomics.h
+===================================================================
+--- /dev/null
++++ b/src/libstdc++-v3/libsupc++/eh_atomics.h
+@@ -0,0 +1,84 @@
++// Exception Handling support header for -*- C++ -*-
++
++// Copyright (C) 2016 Free Software Foundation, Inc.
++//
++// This file is part of GCC.
++//
++// GCC is free software; you can redistribute it and/or modify
++// it under the terms of the GNU General Public License as published by
++// the Free Software Foundation; either version 3, or (at your option)
++// any later version.
++//
++// GCC is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++//
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++/** @file eh_atomics.h
++ *  This is an internal header file, included by library source files.
++ *  Do not attempt to use it directly.
++ */
++
++#ifndef _EH_ATOMICS_H
++#define _EH_ATOMICS_H 1
++
++#include <bits/c++config.h>
++#include <bits/atomic_word.h>
++#include <bits/atomic_lockfree_defines.h>
++#if ATOMIC_INT_LOCK_FREE <= 1
++# include <ext/atomicity.h>
++#endif
++
++#pragma GCC visibility push(default)
++extern "C++" {
++namespace __gnu_cxx
++{
++  void
++  __eh_atomic_inc (_Atomic_word* __count) __attribute__((always_inline));
++
++  bool
++  __eh_atomic_dec (_Atomic_word* __count) __attribute__((always_inline));
++
++  // Increments the count.
++  inline void
++  __eh_atomic_inc (_Atomic_word* __count)
++  {
++#if ATOMIC_INT_LOCK_FREE > 1
++    __atomic_add_fetch (__count, 1, __ATOMIC_ACQ_REL);
++#else
++    _GLIBCXX_SYNCHRONIZATION_HAPPENS_BEFORE (__count);
++    __gnu_cxx::__atomic_add_dispatch (__count, 1);
++    _GLIBCXX_SYNCHRONIZATION_HAPPENS_AFTER (__count);
++#endif
++  }
++
++  // Decrements the count and returns true if it reached zero.
++  inline bool
++  __eh_atomic_dec (_Atomic_word* __count)
++  {
++#if ATOMIC_INT_LOCK_FREE > 1
++    return __atomic_sub_fetch (__count, 1, __ATOMIC_ACQ_REL) == 0;
++#else
++    _GLIBCXX_SYNCHRONIZATION_HAPPENS_BEFORE (__count);
++    if (__gnu_cxx::__exchange_and_add_dispatch (__count, -1) == 1)
++      {
++	_GLIBCXX_SYNCHRONIZATION_HAPPENS_AFTER (__count);
++	return true;
++      }
++    return false;
++#endif
++  }
++} // namespace __gnu_cxx
++}
++#pragma GCC visibility pop
++
++#endif // _EH_ATOMICS_H
+Index: b/src/libstdc++-v3/libsupc++/eh_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/eh_ptr.cc
++++ b/src/libstdc++-v3/libsupc++/eh_ptr.cc
+@@ -23,9 +23,7 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include <bits/c++config.h>
+-#include <bits/atomic_lockfree_defines.h>
+-
+-#if ATOMIC_INT_LOCK_FREE > 1
++#include "eh_atomics.h"
+ 
+ #define _GLIBCXX_EH_PTR_COMPAT
+ 
+@@ -103,7 +101,7 @@ std::__exception_ptr::exception_ptr::_M_
+     {
+       __cxa_refcounted_exception *eh =
+ 	__get_refcounted_exception_header_from_obj (_M_exception_object);
+-      __atomic_add_fetch (&eh->referenceCount, 1, __ATOMIC_ACQ_REL);
++      __gnu_cxx::__eh_atomic_inc (&eh->referenceCount);
+     }
+ }
+ 
+@@ -115,7 +113,7 @@ std::__exception_ptr::exception_ptr::_M_
+     {
+       __cxa_refcounted_exception *eh =
+ 	__get_refcounted_exception_header_from_obj (_M_exception_object);
+-      if (__atomic_sub_fetch (&eh->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
++      if (__gnu_cxx::__eh_atomic_dec (&eh->referenceCount))
+         {
+ 	  if (eh->exc.exceptionDestructor)
+ 	    eh->exc.exceptionDestructor (_M_exception_object);
+@@ -219,7 +217,7 @@ __gxx_dependent_exception_cleanup(_Unwin
+ 
+   __cxa_free_dependent_exception (dep);
+ 
+-  if (__atomic_sub_fetch (&header->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
++  if (__gnu_cxx::__eh_atomic_dec (&header->referenceCount))
+     {
+       if (header->exc.exceptionDestructor)
+ 	header->exc.exceptionDestructor (header + 1);
+@@ -238,7 +236,7 @@ std::rethrow_exception(std::exception_pt
+ 
+   __cxa_dependent_exception *dep = __cxa_allocate_dependent_exception ();
+   dep->primaryException = obj;
+-  __atomic_add_fetch (&eh->referenceCount, 1,  __ATOMIC_ACQ_REL);
++  __gnu_cxx::__eh_atomic_inc (&eh->referenceCount);
+ 
+   dep->unexpectedHandler = get_unexpected ();
+   dep->terminateHandler = get_terminate ();
+@@ -260,5 +258,3 @@ std::rethrow_exception(std::exception_pt
+ }
+ 
+ #undef _GLIBCXX_EH_PTR_COMPAT
+-
+-#endif
+Index: b/src/libstdc++-v3/libsupc++/eh_throw.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/eh_throw.cc
++++ b/src/libstdc++-v3/libsupc++/eh_throw.cc
+@@ -24,6 +24,7 @@
+ 
+ #include <bits/c++config.h>
+ #include "unwind-cxx.h"
++#include "eh_atomics.h"
+ 
+ using namespace __cxxabiv1;
+ 
+@@ -42,17 +43,13 @@ __gxx_exception_cleanup (_Unwind_Reason_
+   if (code != _URC_FOREIGN_EXCEPTION_CAUGHT && code != _URC_NO_REASON)
+     __terminate (header->exc.terminateHandler);
+ 
+-#if ATOMIC_INT_LOCK_FREE > 1
+-  if (__atomic_sub_fetch (&header->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
++  if (__gnu_cxx::__eh_atomic_dec (&header->referenceCount))
+     {
+-#endif
+       if (header->exc.exceptionDestructor)
+ 	header->exc.exceptionDestructor (header + 1);
+ 
+       __cxa_free_exception (header + 1);
+-#if ATOMIC_INT_LOCK_FREE > 1
+     }
+-#endif
+ }
+ 
+ 
+Index: b/src/libstdc++-v3/libsupc++/eh_tm.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/eh_tm.cc
++++ b/src/libstdc++-v3/libsupc++/eh_tm.cc
+@@ -24,6 +24,7 @@
+ 
+ #include <cstdlib>
+ #include "unwind-cxx.h"
++#include "eh_atomics.h"
+ 
+ using namespace __cxxabiv1;
+ 
+@@ -45,9 +46,7 @@ free_any_cxa_exception (_Unwind_Exceptio
+       __cxa_free_dependent_exception (dep);
+     }
+ 
+-#if __GCC_ATOMIC_INT_LOCK_FREE > 1
+-  if (__atomic_sub_fetch (&h->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
+-#endif
++  if (__gnu_cxx::__eh_atomic_dec (&h->referenceCount))
+     __cxa_free_exception (h + 1);
+ }
+ 
+#Index: b/src/libstdc++-v3/libsupc++/exception
+#===================================================================
+#--- a/src/libstdc++-v3/libsupc++/exception
+#+++ b/src/libstdc++-v3/libsupc++/exception
+#@@ -35,7 +35,6 @@
+# #pragma GCC visibility push(default)
+# 
+# #include <bits/c++config.h>
+#-#include <bits/atomic_lockfree_defines.h>
+# 
+# extern "C++" {
+# 
+#@@ -166,7 +165,7 @@ _GLIBCXX_END_NAMESPACE_VERSION
+# 
+# #pragma GCC visibility pop
+# 
+#-#if (__cplusplus >= 201103L) && (ATOMIC_INT_LOCK_FREE > 1)
+#+#if (__cplusplus >= 201103L)
+# #include <bits/exception_ptr.h>
+# #include <bits/nested_exception.h>
+# #endif
+#Index: b/src/libstdc++-v3/libsupc++/exception_ptr.h
+#===================================================================
+#--- a/src/libstdc++-v3/libsupc++/exception_ptr.h
+#+++ b/src/libstdc++-v3/libsupc++/exception_ptr.h
+#@@ -36,10 +36,6 @@
+# #include <bits/c++config.h>
+# #include <bits/exception_defines.h>
+# 
+#-#if ATOMIC_INT_LOCK_FREE < 2
+#-#  error This platform does not support exception propagation.
+#-#endif
+#-
+# extern "C++" {
+# 
+# namespace std 
+Index: b/src/libstdc++-v3/libsupc++/guard.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/guard.cc
++++ b/src/libstdc++-v3/libsupc++/guard.cc
+@@ -30,6 +30,7 @@
+ #include <new>
+ #include <ext/atomicity.h>
+ #include <ext/concurrence.h>
++#include <bits/atomic_lockfree_defines.h>
+ #if defined(__GTHREADS) && defined(__GTHREAD_HAS_COND) \
+   && (ATOMIC_INT_LOCK_FREE > 1) && defined(_GLIBCXX_HAVE_LINUX_FUTEX)
+ # include <climits>
+Index: b/src/libstdc++-v3/libsupc++/nested_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/nested_exception.cc
++++ b/src/libstdc++-v3/libsupc++/nested_exception.cc
+@@ -25,7 +25,5 @@
+ 
+ namespace std 
+ {
+-#if ATOMIC_INT_LOCK_FREE > 1
+   nested_exception::~nested_exception() noexcept = default;
+-#endif
+ } // namespace std
+#Index: b/src/libstdc++-v3/libsupc++/nested_exception.h
+#===================================================================
+#--- a/src/libstdc++-v3/libsupc++/nested_exception.h
+#+++ b/src/libstdc++-v3/libsupc++/nested_exception.h
+#@@ -39,10 +39,6 @@
+# #include <bits/c++config.h>
+# #include <bits/move.h>
+# 
+#-#if ATOMIC_INT_LOCK_FREE < 2
+#-#  error This platform does not support exception propagation.
+#-#endif
+#-
+# extern "C++" {
+# 
+# namespace std
+Index: b/src/libstdc++-v3/src/c++11/future.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/future.cc
++++ b/src/libstdc++-v3/src/c++11/future.cc
+@@ -78,8 +78,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+   const char*
+   future_error::what() const noexcept { return logic_error::what(); }
+ 
+-#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) \
+-  && (ATOMIC_INT_LOCK_FREE > 1)
++#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1)
+   __future_base::_Result_base::_Result_base() = default;
+ 
+   __future_base::_Result_base::~_Result_base() = default;
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/40296.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/40296.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/40296.cc
+@@ -1,6 +1,5 @@
+ // { dg-do compile }
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-terminate.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-terminate.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-terminate.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-unexpected.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-unexpected.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-unexpected.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/62258.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/62258.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/62258.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2015-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/64241.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/64241.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/64241.cc
+@@ -16,7 +16,6 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ // { dg-options "-std=gnu++11 -fno-exceptions -O0" }
+-// { dg-require-atomic-builtins "" }
+ 
+ #include <exception>
+ #include <testsuite_hooks.h>
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/current_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/current_exception.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/current_exception.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // 2008-05-25  Sebastian Redl  <sebastian.redl@getdesigned.at>
+ 
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/lifespan.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/lifespan.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/lifespan.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // 2008-05-25  Sebastian Redl  <sebastian.redl@getdesigned.at>
+ 
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/make_exception_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/make_exception_ptr.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/make_exception_ptr.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/move.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/move.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements_neg.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements_neg.cc
+@@ -1,6 +1,5 @@
+ // { dg-do compile }
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/rethrow_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/rethrow_exception.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/rethrow_exception.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // 2008-05-25  Sebastian Redl  <sebastian.redl@getdesigned.at>
+ 
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/51438.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/51438.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/51438.cc
+@@ -1,6 +1,5 @@
+ // { dg-do compile }
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/62154.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/62154.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/62154.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/cons.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/cons.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/cons.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/nested_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/nested_ptr.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/nested_ptr.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_if_nested.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_if_nested.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_if_nested.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_nested.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_nested.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_nested.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/throw_with_nested.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/throw_with_nested.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/throw_with_nested.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/42819.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/42819.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/42819.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/49668.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/49668.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/49668.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/54297.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/54297.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/54297.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ // { dg-require-sleep "" }
+ 
+ // Copyright (C) 2012-2016 Free Software Foundation, Inc.
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/any.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/any.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/any.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/async.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/async.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/async.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/except.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/except.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/except.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/forced_unwind.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/forced_unwind.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/forced_unwind.cc
+@@ -2,7 +2,6 @@
+ // { dg-options " -std=gnu++11 -pthread" { target *-*-linux* *-*-gnu* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/launch.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/launch.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/launch.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/lwg2021.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/lwg2021.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/lwg2021.cc
+@@ -21,7 +21,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // LWG 2021. Further incorrect usages of result_of
+ // Arguments to result_of should use decay.
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/sync.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/sync.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/sync.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/assign_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/assign_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/assign_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/constexpr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/constexpr.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/constexpr.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11 -fno-inline -g0" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ // { dg-final { scan-assembler-not "_ZNSt6futureIvEC2Ev" } }
+ // { dg-final { scan-assembler-not "_ZNSt6futureIiEC2Ev" } }
+ 
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/copy_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/copy_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/copy_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/default.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/default.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/default.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/headers/future/types_std_c++0x.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/headers/future/types_std_c++0x.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/headers/future/types_std_c++0x.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" } 
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/56492.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/56492.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/56492.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2013-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc2.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/forced_unwind.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/forced_unwind.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/forced_unwind.cc
+@@ -2,7 +2,6 @@
+ // { dg-options " -std=gnu++11 -pthread" { target *-*-linux* *-*-gnu* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/at_thread_exit.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/at_thread_exit.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/at_thread_exit.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/uses_allocator.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/uses_allocator.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/uses_allocator.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/60966.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/60966.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/60966.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/69106.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/69106.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/69106.cc
+@@ -19,7 +19,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ #include <future>
+ 
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/1.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/1.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/1.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc2.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc_min.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc_min.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc_min.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/assign_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/assign_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/assign_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/copy_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/copy_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/copy_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/uses_allocator.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/uses_allocator.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/uses_allocator.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/assign.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/constexpr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/constexpr.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/constexpr.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11 -fno-inline -g0" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ // { dg-final { scan-assembler-not "_ZNSt13shared_futureIvEC2Ev" } }
+ // { dg-final { scan-assembler-not "_ZNSt13shared_futureIiEC2Ev" } }
+ 
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/copy.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/copy.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/copy.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/default.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/default.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/default.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move_assign.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
--- gcc-6-6.3.0.orig/debian/patches/pr65618.diff
+++ gcc-6-6.3.0/debian/patches/pr65618.diff
@@ -0,0 +1,16 @@
+# DP: Proposed patch for PR rtl-optimization/65618
+
+--- a/src/gcc/emit-rtl.c	
++++ a/src/gcc/emit-rtl.c	
+@@ -3742,6 +3742,11 @@ try_split (rtx pat, rtx_insn *trial, int last)
+ 		   next = NEXT_INSN (next))
+ 		if (NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
+ 		  {
++		    /* Advance after to the next instruction if it is about to
++		       be removed */
++		    if (after == next)
++		      after = NEXT_INSN(after);
++
+ 		    remove_insn (next);
+ 		    add_insn_after (next, insn, NULL);
+ 		    break;
--- gcc-6-6.3.0.orig/debian/patches/pr66368.diff
+++ gcc-6-6.3.0/debian/patches/pr66368.diff
@@ -0,0 +1,26 @@
+# DP: PR go/66368, build libgo with -fno-stack-protector
+
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -42,6 +42,7 @@ AM_CPPFLAGS = -I $(srcdir)/runtime $(LIB
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ 
+ AM_CFLAGS = -fexceptions -fnon-call-exceptions -fplan9-extensions \
++	-fno-stack-protector \
+ 	$(SPLIT_STACK) $(WARN_CFLAGS) \
+ 	$(STRINGOPS_FLAG) $(OSCFLAGS) \
+ 	-I $(srcdir)/../libgcc -I $(srcdir)/../libbacktrace \
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -513,6 +513,7 @@ WARN_CFLAGS = $(WARN_FLAGS) $(WERROR)
+ AM_CPPFLAGS = -I $(srcdir)/runtime $(LIBFFIINCS) $(PTHREAD_CFLAGS)
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ AM_CFLAGS = -fexceptions -fnon-call-exceptions -fplan9-extensions \
++	-fno-stack-protector \
+ 	$(SPLIT_STACK) $(WARN_CFLAGS) \
+ 	$(STRINGOPS_FLAG) $(OSCFLAGS) \
+ 	-I $(srcdir)/../libgcc -I $(srcdir)/../libbacktrace \
--- gcc-6-6.3.0.orig/debian/patches/pr67590.diff
+++ gcc-6-6.3.0/debian/patches/pr67590.diff
@@ -0,0 +1,38 @@
+# DP: Fix PR67590, setting objdump macro.
+
+Index: b/src/libcc1/configure.ac
+===================================================================
+--- a/src/libcc1/configure.ac
++++ b/src/libcc1/configure.ac
+@@ -64,6 +64,31 @@ if test "$GXX" = yes; then
+ fi
+ AC_SUBST(libsuffix)
+ 
++# Figure out what objdump we will be using.
++AS_VAR_SET_IF(gcc_cv_objdump,, [
++if test -f $gcc_cv_binutils_srcdir/configure.ac \
++     && test -f ../binutils/Makefile \
++     && test x$build = x$host; then
++	# Single tree build which includes binutils.
++	gcc_cv_objdump=../binutils/objdump$build_exeext
++elif test -x objdump$build_exeext; then
++	gcc_cv_objdump=./objdump$build_exeext
++elif ( set dummy $OBJDUMP_FOR_TARGET; test -x $[2] ); then
++        gcc_cv_objdump="$OBJDUMP_FOR_TARGET"
++else
++        AC_PATH_PROG(gcc_cv_objdump, $OBJDUMP_FOR_TARGET)
++fi])
++
++AC_MSG_CHECKING(what objdump to use)
++if test "$gcc_cv_objdump" = ../binutils/objdump$build_exeext; then
++	# Single tree build which includes binutils.
++	AC_MSG_RESULT(newly built objdump)
++elif test x$gcc_cv_objdump = x; then
++	AC_MSG_RESULT(not found)
++else
++	AC_MSG_RESULT($gcc_cv_objdump)
++fi
++
+ dnl Test for -lsocket and -lnsl.  Copied from libgo/configure.ac.
+ AC_CACHE_CHECK([for socket libraries], libcc1_cv_lib_sockets,
+   [libcc1_cv_lib_sockets=
--- gcc-6-6.3.0.orig/debian/patches/pr67899.diff
+++ gcc-6-6.3.0/debian/patches/pr67899.diff
@@ -0,0 +1,31 @@
+# DP: Proposed patch for PR sanitizer/67899
+
+Index: b/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
++++ b/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+@@ -606,11 +606,10 @@ namespace __sanitizer {
+ #else
+     __sanitizer_sigset_t sa_mask;
+ #ifndef __mips__
+-#if defined(__sparc__)
+-    unsigned long sa_flags;
+-#else
+-    int sa_flags;
++#if defined(__sparc__) && defined(__arch64__)
++    int __pad;
+ #endif
++    int sa_flags;
+ #endif
+ #endif
+ #if SANITIZER_LINUX
+@@ -640,7 +639,8 @@ namespace __sanitizer {
+       void (*handler)(int signo);
+       void (*sigaction)(int signo, void *info, void *ctx);
+     };
+-    unsigned long sa_flags;
++    int __pad;
++    int sa_flags;
+     void (*sa_restorer)(void);
+     __sanitizer_kernel_sigset_t sa_mask;
+   };
--- gcc-6-6.3.0.orig/debian/patches/pr77267.diff
+++ gcc-6-6.3.0/debian/patches/pr77267.diff
@@ -0,0 +1,109 @@
+# DP: Fix PR target/77267 (x86), taken from the trunk.
+
+gcc/
+
+2016-09-10  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+
+	PR target/77267
+	* config.in: Regenerate.
+	* config/i386/linux-common.h (MPX_LD_AS_NEEDED_GUARD_PUSH):
+	New macro.
+	(MPX_LD_AS_NEEDED_GUARD_PUSH): Ditto.
+	(LIBMPXWRAPPERS_SPEC): Remove "--no-whole-archive" from
+	static-libmpxwrappers case.
+	(LIBMPX_SPEC): Add guards with MPX_LD_AS_NEEDED_GUARD_PUSH and
+	MPX_LD_AS_NEEDED_GUARD_POP.
+	* configure: Regenerate.
+	* configure.ac (HAVE_LD_PUSHPOPSTATE_SUPPORT): New variable.
+	defined if linker support "--push-state"/"--pop-state".
+
+ 
+Index: b/src/gcc/config.in
+===================================================================
+--- a/src/gcc/config.in
++++ b/src/gcc/config.in
+@@ -1525,6 +1525,12 @@
+ #endif
+ 
+ 
++/* Define if your linker supports --push-state/--pop-state */
++#ifndef USED_FOR_TARGET
++#undef HAVE_LD_PUSHPOPSTATE_SUPPORT
++#endif
++
++
+ /* Define if your linker links a mix of read-only and read-write sections into
+    a read-write section. */
+ #ifndef USED_FOR_TARGET
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -6219,6 +6219,27 @@ if test x"$ld_bndplt_support" = xyes; th
+ fi
+ AC_MSG_RESULT($ld_bndplt_support)
+ 
++# Check linker supports '--push-state'/'--pop-state'
++ld_pushpopstate_support=no
++AC_MSG_CHECKING(linker --push-state/--pop-state options)
++if test x"$ld_is_gold" = xno; then
++  if test $in_tree_ld = yes ; then
++    if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 25 -o "$gcc_cv_gld_major_version" -gt 2; then
++      ld_pushpopstate_support=yes
++    fi
++  elif test x$gcc_cv_ld != x; then
++    # Check if linker supports --push-state/--pop-state options
++    if $gcc_cv_ld --help 2>/dev/null | grep -- '--push-state' > /dev/null; then
++      ld_pushpopstate_support=yes
++    fi
++  fi
++fi
++if test x"$ld_pushpopstate_support" = xyes; then
++  AC_DEFINE(HAVE_LD_PUSHPOPSTATE_SUPPORT, 1,
++	[Define if your linker supports --push-state/--pop-state])
++fi
++AC_MSG_RESULT($ld_pushpopstate_support)
++
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+ 
+Index: b/src/gcc/config/i386/linux-common.h
+===================================================================
+--- a/src/gcc/config/i386/linux-common.h
++++ b/src/gcc/config/i386/linux-common.h
+@@ -79,13 +79,23 @@ along with GCC; see the file COPYING3.
+ #endif
+ #endif
+ 
++#ifdef HAVE_LD_PUSHPOPSTATE_SUPPORT
++#define MPX_LD_AS_NEEDED_GUARD_PUSH "--push-state --no-as-needed"
++#define MPX_LD_AS_NEEDED_GUARD_POP "--pop-state"
++#else
++#define MPX_LD_AS_NEEDED_GUARD_PUSH ""
++#define MPX_LD_AS_NEEDED_GUARD_POP ""
++#endif
++
+ #ifndef LIBMPX_SPEC
+ #if defined(HAVE_LD_STATIC_DYNAMIC)
+ #define LIBMPX_SPEC "\
+ %{mmpx:%{fcheck-pointer-bounds:\
+     %{static:--whole-archive -lmpx --no-whole-archive" LIBMPX_LIBS "}\
+     %{!static:%{static-libmpx:" LD_STATIC_OPTION " --whole-archive}\
+-    -lmpx %{static-libmpx:--no-whole-archive " LD_DYNAMIC_OPTION \
++    %{!static-libmpx:" MPX_LD_AS_NEEDED_GUARD_PUSH "} -lmpx \
++    %{!static-libmpx:" MPX_LD_AS_NEEDED_GUARD_POP "} \
++    %{static-libmpx:--no-whole-archive " LD_DYNAMIC_OPTION \
+     LIBMPX_LIBS "}}}}"
+ #else
+ #define LIBMPX_SPEC "\
+@@ -98,8 +108,8 @@ along with GCC; see the file COPYING3.
+ #define LIBMPXWRAPPERS_SPEC "\
+ %{mmpx:%{fcheck-pointer-bounds:%{!fno-chkp-use-wrappers:\
+     %{static:-lmpxwrappers}\
+-    %{!static:%{static-libmpxwrappers:" LD_STATIC_OPTION " --whole-archive}\
+-    -lmpxwrappers %{static-libmpxwrappers:--no-whole-archive "\
++    %{!static:%{static-libmpxwrappers:" LD_STATIC_OPTION "}\
++    -lmpxwrappers %{static-libmpxwrappers: "\
+     LD_DYNAMIC_OPTION "}}}}}"
+ #else
+ #define LIBMPXWRAPPERS_SPEC "\
--- gcc-6-6.3.0.orig/debian/patches/pr78774.diff
+++ gcc-6-6.3.0/debian/patches/pr78774.diff
@@ -0,0 +1,48 @@
+# DP: Fix PR c++/78774, proposed for the gcc-6-branch
+
+PR c++/78774 - [6/7 Regression] ICE in constexpr string literals and templates
+
+gcc/cp/ChangeLog:
+
+	PR c++/78774
+	* pt.c (convert_template_argument): Avoid assuming operand type
+	is non-null since that of SCOPE_REF is not.
+
+gcc/testsuite/ChangeLog:
+
+	PR c++/78774
+	* g++.dg/cpp1y/pr78774.C: New test.
+
+Index: b/src/gcc/cp/pt.c
+===================================================================
+--- a/src/gcc/cp/pt.c
++++ b/src/gcc/cp/pt.c
+@@ -7281,9 +7281,11 @@ convert_template_argument (tree parm,
+           /* Reject template arguments that are references to built-in
+              functions with no library fallbacks.  */
+           const_tree inner = TREE_OPERAND (val, 0);
+-          if (TREE_CODE (TREE_TYPE (inner)) == REFERENCE_TYPE
+-              && TREE_CODE (TREE_TYPE (TREE_TYPE (inner))) == FUNCTION_TYPE
+-              && TREE_CODE (TREE_TYPE (inner)) == REFERENCE_TYPE
++	  const_tree innertype = TREE_TYPE (inner);
++          if (innertype
++	      && TREE_CODE (innertype) == REFERENCE_TYPE
++              && TREE_CODE (TREE_TYPE (innertype)) == FUNCTION_TYPE
++              && TREE_CODE (innertype) == REFERENCE_TYPE
+               && 0 < TREE_OPERAND_LENGTH (inner)
+               && reject_gcc_builtin (TREE_OPERAND (inner, 0)))
+               return error_mark_node;
+Index: b/src/gcc/testsuite/g++.dg/cpp1y/pr78774.C
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/g++.dg/cpp1y/pr78774.C
+@@ -0,0 +1,9 @@
++// PR c++/78774 - [6/7 Regression] ICE in constexpr string literals and
++// templates
++// { dg-do compile { target c++14 } }
++
++template <int> struct ops {
++  template <int> struct A;
++  template <int *Ptr> using explode = typename A<*Ptr>::join;
++};
++template <typename Ts> typename ops<'\0'>::explode<Ts::join>::type a;
--- gcc-6-6.3.0.orig/debian/patches/rename-info-files.diff
+++ gcc-6-6.3.0/debian/patches/rename-info-files.diff
@@ -0,0 +1,842 @@
+# DP: Allow transformations on info file names. Reference the
+# DP: transformed info file names in the texinfo files.
+
+
+2004-02-17  Matthias Klose  <doko@debian.org>
+
+gcc/ChangeLog:
+	* Makefile.in: Allow transformations on info file names.
+	Define MAKEINFODEFS, macros to pass transformated info file
+	names to makeinfo.
+	* doc/cpp.texi: Use macros defined in MAKEINFODEFS for references.
+	* doc/cppinternals.texi: Likewise.
+	* doc/extend.texi: Likewise.
+	* doc/gcc.texi: Likewise.
+	* doc/gccint.texi: Likewise.
+	* doc/invoke.texi: Likewise.
+	* doc/libgcc.texi: Likewise.
+	* doc/makefile.texi: Likewise.
+	* doc/passes.texi: Likewise.
+	* doc/sourcebuild.texi: Likewise.
+	* doc/standards.texi: Likewise.
+	* doc/trouble.texi: Likewise.
+
+gcc/fortran/ChangeLog:
+	* Make-lang.in: Allow transformations on info file names.
+	Pass macros of transformated info file defined in MAKEINFODEFS
+	names to makeinfo.
+	* gfortran.texi: Use macros defined in MAKEINFODEFS for references.
+
+gcc/java/ChangeLog:
+	* Make-lang.in: Allow transformations on info file names.
+	Pass macros of transformated info file defined in MAKEINFODEFS
+
+Index: b/src/gcc/fortran/gfortran.texi
+===================================================================
+--- a/src/gcc/fortran/gfortran.texi
++++ b/src/gcc/fortran/gfortran.texi
+@@ -101,7 +101,7 @@ Texts being (a) (see below), and with th
+ @ifinfo
+ @dircategory Software development
+ @direntry
+-* gfortran: (gfortran).                  The GNU Fortran Compiler.
++* @value{fngfortran}: (@value{fngfortran}).                  The GNU Fortran Compiler.
+ @end direntry
+ This file documents the use and the internals of
+ the GNU Fortran compiler, (@command{gfortran}).
+Index: b/src/gcc/fortran/Make-lang.in
+===================================================================
+--- a/src/gcc/fortran/Make-lang.in
++++ b/src/gcc/fortran/Make-lang.in
+@@ -114,7 +114,8 @@ fortran.tags: force
+ 	cd $(srcdir)/fortran; etags -o TAGS.sub *.c *.h; \
+ 	etags --include TAGS.sub --include ../TAGS.sub
+ 
+-fortran.info: doc/gfortran.info doc/gfc-internals.info
++INFO_FORTRAN_NAME = $(shell echo gfortran|sed '$(program_transform_name)')
++fortran.info: doc/$(INFO_FORTRAN_NAME).info
+ fortran.dvi: doc/gfortran.dvi doc/gfc-internals.dvi
+ 
+ F95_HTMLFILES = $(build_htmldir)/gfortran
+@@ -181,10 +182,10 @@ GFORTRAN_TEXI = \
+   $(srcdir)/doc/include/gcc-common.texi \
+   gcc-vers.texi
+ 
+-doc/gfortran.info: $(GFORTRAN_TEXI)
++doc/$(INFO_FORTRAN_NAME).info: $(GFORTRAN_TEXI)
+ 	if [ x$(BUILD_INFO) = xinfo ]; then \
+ 	  rm -f doc/gfortran.info-*; \
+-	  $(MAKEINFO) -I $(srcdir)/doc/include -I $(srcdir)/fortran \
++	  $(MAKEINFO) $(MAKEINFODEFS) -I $(srcdir)/doc/include -I $(srcdir)/fortran \
+ 	    -o $@ $<; \
+ 	else true; fi
+ 
+@@ -249,7 +250,7 @@ fortran.install-common: install-finclude
+ 
+ fortran.install-plugin:
+ 
+-fortran.install-info: $(DESTDIR)$(infodir)/gfortran.info
++fortran.install-info: $(DESTDIR)$(infodir)/$(INFO_FORTRAN_NAME).info
+ 
+ fortran.install-man: $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext)
+ 
+@@ -267,7 +268,7 @@ fortran.uninstall:
+ 	rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_INSTALL_NAME)$(exeext); \
+ 	rm -rf $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext); \
+ 	rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_TARGET_INSTALL_NAME)$(exeext); \
+-	rm -rf $(DESTDIR)$(infodir)/gfortran.info*
++	rm -rf $(DESTDIR)$(infodir)/$(INFO_FORTRAN_NAME).info*
+ 
+ #
+ # Clean hooks:
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -2880,8 +2880,32 @@ install-no-fixedincludes:
+ 
+ doc: $(BUILD_INFO) $(GENERATED_MANPAGES)
+ 
+-INFOFILES = doc/cpp.info doc/gcc.info doc/gccint.info \
+-            doc/gccinstall.info doc/cppinternals.info
++INFO_CPP_NAME = $(shell echo cpp|sed '$(program_transform_name)')
++INFO_GCC_NAME = $(shell echo gcc|sed '$(program_transform_name)')
++INFO_GXX_NAME = $(shell echo g++|sed '$(program_transform_name)')
++INFO_GCCINT_NAME = $(shell echo gccint|sed '$(program_transform_name)')
++INFO_GCCINSTALL_NAME = $(shell echo gccinstall|sed '$(program_transform_name)')
++INFO_CPPINT_NAME = $(shell echo cppinternals|sed '$(program_transform_name)')
++
++INFO_FORTRAN_NAME = $(shell echo gfortran|sed '$(program_transform_name)')
++INFO_GCJ_NAME = $(shell echo gcj|sed '$(program_transform_name)')
++INFO_GCCGO_NAME = $(shell echo gccgo|sed '$(program_transform_name)')
++
++INFOFILES = doc/$(INFO_CPP_NAME).info doc/$(INFO_GCC_NAME).info \
++            doc/$(INFO_GCCINT_NAME).info \
++            doc/$(INFO_GCCINSTALL_NAME).info doc/$(INFO_CPPINT_NAME).info
++
++MAKEINFODEFS = -D 'fncpp $(INFO_CPP_NAME)' \
++               -D 'fngcc $(INFO_GCC_NAME)' \
++               -D 'fngcov $(INFO_GCC_NAME)' \
++               -D 'fngcovtool $(INFO_GCC_NAME)' \
++               -D 'fngxx $(INFO_GXX_NAME)' \
++               -D 'fngccint $(INFO_GCCINT_NAME)' \
++               -D 'fngccinstall $(INFO_GCCINSTALL_NAME)' \
++               -D 'fncppint $(INFO_CPPINT_NAME)' \
++               -D 'fngfortran $(INFO_FORTRAN_NAME)' \
++               -D 'fngcj $(INFO_GCJ_NAME)' \
++               -D 'fngccgo $(INFO_GCCGO_NAME)'
+ 
+ info: $(INFOFILES) lang.info @GENINSRC@ srcinfo lang.srcinfo
+ 
+@@ -2928,7 +2952,19 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+ 	if [ -n "$(PKGVERSION)" ]; then \
+ 	  echo "@set VERSION_PACKAGE $(PKGVERSION)" >> $@T; \
+ 	fi
+-	echo "@set BUGURL $(BUGURL_TEXI)" >> $@T; \
++	echo "@set BUGURL $(BUGURL_TEXI)" >> $@T
++	( \
++	  echo '@set fncpp $(INFO_CPP_NAME)'; \
++	  echo '@set fngcc $(INFO_GCC_NAME)'; \
++	  echo '@set fngcov $(INFO_GCC_NAME)'; \
++	  echo '@set fngxx $(INFO_GXX_NAME)'; \
++	  echo '@set fngccint $(INFO_GCCINT_NAME)'; \
++	  echo '@set fngccinstall $(INFO_GCCINSTALL_NAME)'; \
++	  echo '@set fncppint $(INFO_CPPINT_NAME)'; \
++	  echo '@set fngfortran $(INFO_FORTRAN_NAME)'; \
++	  echo '@set fngcj $(INFO_GCJ_NAME)'; \
++	  echo '@set fngccgo $(INFO_GCCGO_NAME)'; \
++	) >> $@T
+ 	mv -f $@T $@
+ 
+ 
+@@ -2936,21 +2972,41 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+ # patterns.  To use them, put each of the specific targets with its
+ # specific dependencies but no build commands.
+ 
+-doc/cpp.info: $(TEXI_CPP_FILES)
+-doc/gcc.info: $(TEXI_GCC_FILES)
+-doc/gccint.info: $(TEXI_GCCINT_FILES)
+-doc/cppinternals.info: $(TEXI_CPPINT_FILES)
+-
++# Generic entry to handle info files, which are not renamed (currently Ada)
+ doc/%.info: %.texi
+ 	if [ x$(BUILD_INFO) = xinfo ]; then \
+ 		$(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \
+ 			-I $(gcc_docdir)/include -o $@ $<; \
+ 	fi
+ 
++doc/$(INFO_CPP_NAME).info: $(TEXI_CPP_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
++doc/$(INFO_GCC_NAME).info: $(TEXI_GCC_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
++doc/$(INFO_GCCINT_NAME).info: $(TEXI_GCCINT_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
++doc/$(INFO_CPPINT_NAME).info: $(TEXI_CPPINT_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
+ # Duplicate entry to handle renaming of gccinstall.info
+-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)
++doc/$(INFO_GCCINSTALL_NAME).info: $(TEXI_GCCINSTALL_FILES)
+ 	if [ x$(BUILD_INFO) = xinfo ]; then \
+-		$(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
+ 			-I $(gcc_docdir)/include -o $@ $<; \
+ 	fi
+ 
+@@ -3346,11 +3402,11 @@ install-driver: installdirs xgcc$(exeext
+ # $(INSTALL_DATA) might be a relative pathname, so we can't cd into srcdir
+ # to do the install.
+ install-info:: doc installdirs \
+-	$(DESTDIR)$(infodir)/cpp.info \
+-	$(DESTDIR)$(infodir)/gcc.info \
+-	$(DESTDIR)$(infodir)/cppinternals.info \
+-	$(DESTDIR)$(infodir)/gccinstall.info \
+-	$(DESTDIR)$(infodir)/gccint.info \
++	$(DESTDIR)$(infodir)/$(INFO_CPP_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_GCC_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_CPPINT_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_GCCINSTALL_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_GCCINT_NAME).info \
+ 	lang.install-info
+ 
+ $(DESTDIR)$(infodir)/%.info: doc/%.info installdirs
+@@ -3404,6 +3460,7 @@ install-man: lang.install-man \
+ 	$(DESTDIR)$(man1dir)/$(GCC_INSTALL_NAME)$(man1ext) \
+ 	$(DESTDIR)$(man1dir)/$(CPP_INSTALL_NAME)$(man1ext) \
+ 	$(DESTDIR)$(man1dir)/$(GCOV_INSTALL_NAME)$(man1ext) \
++	$(DESTDIR)$(man1dir)/$(GCOV_TOOL_INSTALL_NAME)$(man1ext) \
+ 	$(DESTDIR)$(man7dir)/fsf-funding$(man7ext) \
+ 	$(DESTDIR)$(man7dir)/gfdl$(man7ext) \
+ 	$(DESTDIR)$(man7dir)/gpl$(man7ext)
+@@ -3564,8 +3621,11 @@ uninstall: lang.uninstall
+ 	-rm -rf $(DESTDIR)$(bindir)/$(GCOV_INSTALL_NAME)$(exeext)
+ 	-rm -rf $(DESTDIR)$(man1dir)/$(GCC_INSTALL_NAME)$(man1ext)
+ 	-rm -rf $(DESTDIR)$(man1dir)/cpp$(man1ext)
+-	-rm -f $(DESTDIR)$(infodir)/cpp.info* $(DESTDIR)$(infodir)/gcc.info*
+-	-rm -f $(DESTDIR)$(infodir)/cppinternals.info* $(DESTDIR)$(infodir)/gccint.info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_CPP_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_GCC_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_CPPINT_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_GCCINT_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_GCCINSTALL_NAME).info*
+ 	for i in ar nm ranlib ; do \
+ 	  install_name=`echo gcc-$$i|sed '$(program_transform_name)'`$(exeext) ;\
+ 	  target_install_name=$(target_noncanonical)-`echo gcc-$$i|sed '$(program_transform_name)'`$(exeext) ; \
+Index: b/src/gcc/java/gcj.texi
+===================================================================
+--- a/src/gcc/java/gcj.texi
++++ b/src/gcc/java/gcj.texi
+@@ -55,25 +55,25 @@ man page gfdl(7).
+ @format
+ @dircategory Software development
+ @direntry
+-* Gcj: (gcj).               Ahead-of-time compiler for the Java language
++* @value{fngcj}: (@value{fngcj}).               Ahead-of-time compiler for the Java language
+ @end direntry
+ 
+ @dircategory Individual utilities
+ @direntry
+-* jcf-dump: (gcj)Invoking jcf-dump.
++* jcf-dump: (@value{fngcj}) Invoking jcf-dump.
+                             Print information about Java class files
+-* gij: (gcj)Invoking gij.   GNU interpreter for Java bytecode
+-* gcj-dbtool: (gcj)Invoking gcj-dbtool.
++* gij: (@value{fngcj}) Invoking gij.   GNU interpreter for Java bytecode
++* gcj-dbtool: (@value{fngcj}) Invoking gcj-dbtool.
+                             Tool for manipulating class file databases.
+-* jv-convert: (gcj)Invoking jv-convert.
++* jv-convert: (@value{fngcj}) Invoking jv-convert.
+                             Convert file from one encoding to another
+-* grmic: (gcj)Invoking grmic.
++* grmic: (@value{fngcj}) Invoking grmic.
+                             Generate stubs for Remote Method Invocation.
+-* gc-analyze: (gcj)Invoking gc-analyze.
++* gc-analyze: (@value{fngcj}) Invoking gc-analyze.
+                             Analyze Garbage Collector (GC) memory dumps.
+-* aot-compile: (gcj)Invoking aot-compile.
++* aot-compile: (@value{fngcj})Invoking aot-compile.
+                             Compile bytecode to native and generate databases.
+-* rebuild-gcj-db: (gcj)Invoking rebuild-gcj-db.
++* rebuild-gcj-db: (@value{fngcj})Invoking rebuild-gcj-db.
+                             Merge the per-solib databases made by aot-compile
+                             into one system-wide database.
+ @end direntry
+@@ -159,7 +159,7 @@ and the Info entries for @file{gcj} and
+ 
+ As @command{gcj} is just another front end to @command{gcc}, it supports many
+ of the same options as gcc.  @xref{Option Summary, , Option Summary,
+-gcc, Using the GNU Compiler Collection (GCC)}.  This manual only documents the
++@value{fngcc}, Using the GNU Compiler Collection (GCC)}.  This manual only documents the
+ options specific to @command{gcj}.
+ 
+ @c man end
+Index: b/src/gcc/java/Make-lang.in
+===================================================================
+--- a/src/gcc/java/Make-lang.in
++++ b/src/gcc/java/Make-lang.in
+@@ -122,9 +122,10 @@ java.tags: force
+ 	etags --include TAGS.sub --include ../TAGS.sub
+ 
+ 
+-java.info: doc/gcj.info
++INFO_GCJ_NAME = $(shell echo gcj|sed '$(program_transform_name)')
++java.info: doc/$(INFO_GCJ_NAME).info
+ 
+-java.srcinfo: doc/gcj.info
++java.srcinfo: doc/$(INFO_GCJ_NAME).info
+ 	-cp -p $^ $(srcdir)/doc
+ 
+ java.dvi: doc/gcj.dvi
+@@ -190,7 +191,7 @@ java.uninstall:
+ 	-rm -rf $(DESTDIR)$(man1dir)/aot-compile$(man1ext)
+ 	-rm -rf $(DESTDIR)$(man1dir)/rebuild-gcj-db$(man1ext)
+ 
+-java.install-info: $(DESTDIR)$(infodir)/gcj.info
++java.install-info: $(DESTDIR)$(infodir)/$(INFO_GCJ_NAME).info
+ 
+ java.install-pdf: $(JAVA_PDFFILES)
+ 	@$(NORMAL_INSTALL)
+@@ -273,10 +274,10 @@ TEXI_JAVA_FILES = java/gcj.texi $(gcc_do
+ 	 gcc-vers.texi
+ 
+ # Documentation
+-doc/gcj.info: $(TEXI_JAVA_FILES)
++doc/$(INFO_GCJ_NAME).info: $(TEXI_JAVA_FILES)
+ 	if test "x$(BUILD_INFO)" = xinfo; then \
+-	  rm -f doc/gcj.info*; \
+-	  $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
++	  rm -f doc/$(INFO_GCJ_NAME).info*; \
++	  $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
+ 		-I $(gcc_docdir)/include -o $@ $<; \
+ 	else true; fi
+ 
+Index: b/src/gcc/ada/gnat-style.texi
+===================================================================
+--- a/src/gcc/ada/gnat-style.texi
++++ b/src/gcc/ada/gnat-style.texi
+@@ -31,7 +31,7 @@ Texts.  A copy of the license is include
+ 
+ @dircategory Software development
+ @direntry
+-* gnat-style: (gnat-style).      GNAT Coding Style
++* gnat-style: (gnat-style-6).      GNAT Coding Style
+ @end direntry
+ 
+ @macro syntax{element}
+Index: b/src/gcc/ada/gnat_rm.texi
+===================================================================
+--- a/src/gcc/ada/gnat_rm.texi
++++ b/src/gcc/ada/gnat_rm.texi
+@@ -12,7 +12,7 @@
+ @finalout
+ @dircategory GNU Ada Tools 
+ @direntry
+-* gnat_rm: (gnat_rm.info). gnat_rm
++* GNAT Reference Manual: (gnat_rm-6).  Reference Manual for GNU Ada tools.
+ @end direntry
+ 
+ @definfoenclose strong,`,'
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -11188,7 +11188,7 @@ One of the standard libraries bypassed b
+ @option{-nodefaultlibs} is @file{libgcc.a}, a library of internal subroutines
+ which GCC uses to overcome shortcomings of particular machines, or special
+ needs for some languages.
+-(@xref{Interface,,Interfacing to GCC Output,gccint,GNU Compiler
++(@xref{Interface,,Interfacing to GCC Output,@value{fngccint},GNU Compiler
+ Collection (GCC) Internals},
+ for more discussion of @file{libgcc.a}.)
+ In most cases, you need @file{libgcc.a} even when you want to avoid
+@@ -11197,7 +11197,7 @@ or @option{-nodefaultlibs} you should us
+ This ensures that you have no unresolved references to internal GCC
+ library subroutines.
+ (An example of such an internal subroutine is @code{__main}, used to ensure C++
+-constructors are called; @pxref{Collect2,,@code{collect2}, gccint,
++constructors are called; @pxref{Collect2,,@code{collect2}, @value{fngccint},
+ GNU Compiler Collection (GCC) Internals}.)
+ 
+ @item -pie
+@@ -23994,7 +23994,7 @@ Note that you can also specify places to
+ @option{-B}, @option{-I} and @option{-L} (@pxref{Directory Options}).  These
+ take precedence over places specified using environment variables, which
+ in turn take precedence over those specified by the configuration of GCC@.
+-@xref{Driver,, Controlling the Compilation Driver @file{gcc}, gccint,
++@xref{Driver,, Controlling the Compilation Driver @file{gcc}, @value{fngccint},
+ GNU Compiler Collection (GCC) Internals}.
+ 
+ @table @env
+@@ -24154,7 +24154,7 @@ the headers it contains change.
+ 
+ A precompiled header file is searched for when @code{#include} is
+ seen in the compilation.  As it searches for the included file
+-(@pxref{Search Path,,Search Path,cpp,The C Preprocessor}) the
++(@pxref{Search Path,,Search Path,@value{fncpp},The C Preprocessor}) the
+ compiler looks for a precompiled header in each directory just before it
+ looks for the include file in that directory.  The name searched for is
+ the name specified in the @code{#include} with @samp{.gch} appended.  If
+Index: b/src/gcc/doc/extend.texi
+===================================================================
+--- a/src/gcc/doc/extend.texi
++++ b/src/gcc/doc/extend.texi
+@@ -18396,7 +18396,7 @@ want to write code that checks whether t
+ test for the GNU compiler the same way as for C programs: check for a
+ predefined macro @code{__GNUC__}.  You can also use @code{__GNUG__} to
+ test specifically for GNU C++ (@pxref{Common Predefined Macros,,
+-Predefined Macros,cpp,The GNU C Preprocessor}).
++Predefined Macros,@value{fncpp},The GNU C Preprocessor}).
+ 
+ @menu
+ * C++ Volatiles::       What constitutes an access to a volatile object.
+Index: b/src/gcc/doc/standards.texi
+===================================================================
+--- a/src/gcc/doc/standards.texi
++++ b/src/gcc/doc/standards.texi
+@@ -286,8 +286,8 @@ described at @uref{http://golang.org/doc
+ GNAT Reference Manual}, for information on standard
+ conformance and compatibility of the Ada compiler.
+ 
+-@xref{Standards,,Standards, gfortran, The GNU Fortran Compiler}, for details
++@xref{Standards,,Standards, @value{fngfortran}, The GNU Fortran Compiler}, for details
+ of standards supported by GNU Fortran.
+ 
+-@xref{Compatibility,,Compatibility with the Java Platform, gcj, GNU gcj},
++@xref{Compatibility,,Compatibility with the Java Platform, @value{fngcj}, GNU gcj},
+ for details of compatibility between @command{gcj} and the Java Platform.
+Index: b/src/gcc/doc/libgcc.texi
+===================================================================
+--- a/src/gcc/doc/libgcc.texi
++++ b/src/gcc/doc/libgcc.texi
+@@ -24,7 +24,7 @@ that needs them.
+ GCC will also generate calls to C library routines, such as
+ @code{memcpy} and @code{memset}, in some cases.  The set of routines
+ that GCC may possibly use is documented in @ref{Other
+-Builtins,,,gcc, Using the GNU Compiler Collection (GCC)}.
++Builtins,,,@value{fngcc}, Using the GNU Compiler Collection (GCC)}.
+ 
+ These routines take arguments and return values of a specific machine
+ mode, not a specific C type.  @xref{Machine Modes}, for an explanation
+Index: b/src/gcc/doc/gccint.texi
+===================================================================
+--- a/src/gcc/doc/gccint.texi
++++ b/src/gcc/doc/gccint.texi
+@@ -49,7 +49,7 @@ Texts being (a) (see below), and with th
+ @ifnottex
+ @dircategory Software development
+ @direntry
+-* gccint: (gccint).            Internals of the GNU Compiler Collection.
++* @value{fngccint}: (@value{fngccint}).            Internals of the GNU Compiler Collection.
+ @end direntry
+ This file documents the internals of the GNU compilers.
+ @sp 1
+@@ -81,7 +81,7 @@ write front ends for new languages.  It
+ @value{VERSION_PACKAGE}
+ @end ifset
+ version @value{version-GCC}.  The use of the GNU compilers is documented in a
+-separate manual.  @xref{Top,, Introduction, gcc, Using the GNU
++separate manual.  @xref{Top,, Introduction, @value{fngcc}, Using the GNU
+ Compiler Collection (GCC)}.
+ 
+ This manual is mainly a reference manual rather than a tutorial.  It
+Index: b/src/gcc/doc/cpp.texi
+===================================================================
+--- a/src/gcc/doc/cpp.texi
++++ b/src/gcc/doc/cpp.texi
+@@ -50,7 +50,7 @@ This manual contains no Invariant Sectio
+ @ifinfo
+ @dircategory Software development
+ @direntry
+-* Cpp: (cpp).                  The GNU C preprocessor.
++* @value{fncpp}: (@value{fncpp}).                  The GNU C preprocessor.
+ @end direntry
+ @end ifinfo
+ 
+Index: b/src/gcc/doc/gcc.texi
+===================================================================
+--- a/src/gcc/doc/gcc.texi
++++ b/src/gcc/doc/gcc.texi
+@@ -63,10 +63,10 @@ Texts being (a) (see below), and with th
+ @ifnottex
+ @dircategory Software development
+ @direntry
+-* gcc: (gcc).                  The GNU Compiler Collection.
+-* g++: (gcc).                  The GNU C++ compiler.
+-* gcov: (gcc) Gcov.            @command{gcov}---a test coverage program.
+-* gcov-tool: (gcc) Gcov-tool.  @command{gcov-tool}---an offline gcda profile processing program.
++* @value{fngcc}: (@value{fngcc}).                  The GNU Compiler Collection.
++* @value{fngxx}: (@value{fngcc}).                  The GNU C++ compiler.
++* @value{fngcov}: (@value{fngcc}) Gcov.            @command{gcov}---a test coverage program.
++* @value{fngcovtool}: (@value{fngcc}) Gcov.            @command{gcov-tool}---an offline gcda profile processing program.
+ @end direntry
+ This file documents the use of the GNU compilers.
+ @sp 1
+@@ -126,7 +126,7 @@ version @value{version-GCC}.
+ The internals of the GNU compilers, including how to port them to new
+ targets and some information about how to write front ends for new
+ languages, are documented in a separate manual.  @xref{Top,,
+-Introduction, gccint, GNU Compiler Collection (GCC) Internals}.
++Introduction, @value{fngccint}, GNU Compiler Collection (GCC) Internals}.
+ 
+ @menu
+ * G++ and GCC::     You can compile C or C++ programs.
+Index: b/src/gcc/doc/makefile.texi
+===================================================================
+--- a/src/gcc/doc/makefile.texi
++++ b/src/gcc/doc/makefile.texi
+@@ -139,7 +139,7 @@ regardless of how it itself was compiled
+ Builds a compiler with profiling feedback information.  In this case,
+ the second and third stages are named @samp{profile} and @samp{feedback},
+ respectively.  For more information, see
+-@ref{Building,,Building with profile feedback,gccinstall,Installing GCC}.
++@ref{Building,,Building with profile feedback,@value{fngccinstall},Installing GCC}.
+ 
+ @item restrap
+ Restart a bootstrap, so that everything that was not built with
+Index: b/src/gcc/doc/install.texi
+===================================================================
+--- a/src/gcc/doc/install.texi
++++ b/src/gcc/doc/install.texi
+@@ -94,7 +94,7 @@ Free Documentation License}''.
+ @end ifinfo
+ @dircategory Software development
+ @direntry
+-* gccinstall: (gccinstall).    Installing the GNU Compiler Collection.
++* @value{fngccinstall}: (@value{fngccinstall}).    Installing the GNU Compiler Collection.
+ @end direntry
+ 
+ @c Part 3 Titlepage and Copyright
+Index: b/src/gcc/doc/cppinternals.texi
+===================================================================
+--- a/src/gcc/doc/cppinternals.texi
++++ b/src/gcc/doc/cppinternals.texi
+@@ -7,7 +7,7 @@
+ @ifinfo
+ @dircategory Software development
+ @direntry
+-* Cpplib: (cppinternals).      Cpplib internals.
++* @value{fncppint}: (@value{fncppint}).      Cpplib internals.
+ @end direntry
+ @end ifinfo
+ 
+Index: b/src/libgomp/libgomp.texi
+===================================================================
+--- a/src/libgomp/libgomp.texi
++++ b/src/libgomp/libgomp.texi
+@@ -31,7 +31,7 @@ texts being (a) (see below), and with th
+ @ifinfo
+ @dircategory GNU Libraries
+ @direntry
+-* libgomp: (libgomp).          GNU Offloading and Multi Processing Runtime Library.
++* @value{fnlibgomp}: (@value{fnlibgomp}).          GNU Offloading and Multi Processing Runtime Library.
+ @end direntry
+ 
+ This manual documents libgomp, the GNU Offloading and Multi Processing
+Index: b/src/libgomp/Makefile.in
+===================================================================
+--- a/src/libgomp/Makefile.in
++++ b/src/libgomp/Makefile.in
+@@ -445,7 +445,8 @@ info_TEXINFOS = libgomp.texi
+ 
+ # AM_CONDITIONAL on configure check ACX_CHECK_PROG_VER([MAKEINFO])
+ @BUILD_INFO_TRUE@STAMP_BUILD_INFO = stamp-build-info
+-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libgomp.info
++INFO_LIBGOMP_NAME = $(shell echo libgomp|sed '$(program_transform_name)')
++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBGOMP_NAME).info
+ MAINTAINERCLEANFILES = $(srcdir)/libgomp.info
+ all: config.h
+ 	$(MAKE) $(AM_MAKEFLAGS) all-recursive
+@@ -1235,15 +1236,16 @@ env.lo: libgomp_f.h
+ env.o: libgomp_f.h
+ 
+ all-local: $(STAMP_GENINSRC)
+-
+-stamp-geninsrc: libgomp.info
+-	cp -p $(top_builddir)/libgomp.info $(srcdir)/libgomp.info
++stamp-geninsrc: $(INFO_LIBGOMP_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.info
+ 	@touch $@
+ 
+-libgomp.info: $(STAMP_BUILD_INFO)
++libgomp.info: $(INFO_LIBGOMP_NAME).info
++	[ "$(INFO_LIBGOMP_NAME).info" = libgomp.info ] || cp $(INFO_LIBGOMP_NAME).info libgomp.info
++$(INFO_LIBGOMP_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libgomp.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libgomp.info $(srcdir)/libgomp.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -D 'fnlibgomp $(INFO_LIBGOMP_NAME)' -I $(srcdir) -o $(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.texi
+ 	@touch $@
+ 
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+Index: b/src/libgomp/Makefile.am
+===================================================================
+--- a/src/libgomp/Makefile.am
++++ b/src/libgomp/Makefile.am
+@@ -125,16 +125,19 @@ endif
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libgomp.info
+-	cp -p $(top_builddir)/libgomp.info $(srcdir)/libgomp.info
++INFO_LIBGOMP_NAME = $(shell echo libgomp|sed '$(program_transform_name)')
++stamp-geninsrc: $(INFO_LIBGOMP_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.info
+ 	@touch $@
+ 
+-libgomp.info: $(STAMP_BUILD_INFO)
++libgomp.info: $(INFO_LIBGOMP_NAME).info
++	cp $(INFO_LIBGOMP_NAME).info libgomp.info
++$(INFO_LIBGOMP_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libgomp.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libgomp.info $(srcdir)/libgomp.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -D 'fnlibgomp $(INFO_LIBGOMP_NAME)' -I $(srcdir) -o $(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.texi
+ 	@touch $@
+ 
+ 
+-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libgomp.info
++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBGOMP_NAME).info
+ MAINTAINERCLEANFILES = $(srcdir)/libgomp.info
+Index: b/src/libitm/libitm.texi
+===================================================================
+--- a/src/libitm/libitm.texi
++++ b/src/libitm/libitm.texi
+@@ -20,7 +20,7 @@ Free Documentation License''.
+ @ifinfo
+ @dircategory GNU Libraries
+ @direntry
+-* libitm: (libitm).                    GNU Transactional Memory Library
++* @value{fnlibitm}: (@value{fnlibitm}).                    GNU Transactional Memory Library
+ @end direntry
+ 
+ This manual documents the GNU Transactional Memory Library.
+Index: b/src/libitm/Makefile.am
+===================================================================
+--- a/src/libitm/Makefile.am
++++ b/src/libitm/Makefile.am
+@@ -107,14 +107,17 @@ endif
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libitm.info
+-	cp -p $(top_builddir)/libitm.info $(srcdir)/libitm.info
++INFO_LIBITM_NAME = $(shell echo libitm|sed '$(program_transform_name)')
++stamp-geninsrc: $(INFO_LIBITM_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBITM_NAME).info $(srcdir)/libitm.info
+ 	@touch $@
+ 
+-libitm.info: $(STAMP_BUILD_INFO)
++libitm.info: $(INFO_LIBITM_NAME).info
++       cp $(INFO_LIBITM_NAME).info libitm.info
++$(INFO_LIBITM_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libitm.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libitm.info $(srcdir)/libitm.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -D 'fnlibitm $(INFO_LIBITM_NAME)'-o $(INFO_LIBITM_NAME).info $(srcdir)/libitm.texi
+ 	@touch $@
+ 
+ 
+Index: b/src/libitm/Makefile.in
+===================================================================
+--- a/src/libitm/Makefile.in
++++ b/src/libitm/Makefile.in
+@@ -1057,14 +1057,17 @@ vpath % $(strip $(search_path))
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libitm.info
+-	cp -p $(top_builddir)/libitm.info $(srcdir)/libitm.info
++INFO_LIBITM_NAME = $(shell echo libitm|sed '$(program_transform_name)')
++stamp-geninsrc: $(INFO_LIBITM_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBITM_NAME).info $(srcdir)/libitm.info
+ 	@touch $@
+ 
+-libitm.info: $(STAMP_BUILD_INFO)
++libitm.info: $(INFO_LIBITM_NAME).info
++	cp $(INFO_LIBITM_NAME).info libitm.info
++$(INFO_LIBITM_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libitm.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libitm.info $(srcdir)/libitm.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -D 'fnlibitm $(INFO_LIBITM_NAME)' -o $(INFO_LIBITM_NAME).info $(srcdir)/libitm.texi
+ 	@touch $@
+ 
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+Index: b/src/gcc/go/Make-lang.in
+===================================================================
+--- a/src/gcc/go/Make-lang.in
++++ b/src/gcc/go/Make-lang.in
+@@ -85,10 +85,11 @@ GO_TEXI_FILES = \
+ 	$(gcc_docdir)/include/gcc-common.texi \
+ 	gcc-vers.texi
+ 
+-doc/gccgo.info: $(GO_TEXI_FILES)
++INFO_GCCGO_NAME = $(shell echo gccgo|sed '$(program_transform_name)')
++doc/$(INFO_GCCGO_NAME).info: $(GO_TEXI_FILES)
+ 	if test "x$(BUILD_INFO)" = xinfo; then \
+-	  rm -f doc/gccgo.info*; \
+-	  $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
++	  rm -f doc/$(INFO_GCCGO_NAME).info*; \
++	  $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
+ 		-I $(gcc_docdir)/include -o $@ $<; \
+ 	else true; fi
+ 
+@@ -114,7 +115,7 @@ gccgo.pod: go/gccgo.texi
+ go.all.cross: gccgo-cross$(exeext)
+ go.start.encap: gccgo$(exeext)
+ go.rest.encap:
+-go.info: doc/gccgo.info
++go.info: doc/$(INFO_GCCGO_NAME).info
+ go.dvi: doc/gccgo.dvi
+ go.pdf: doc/gccgo.pdf
+ go.html: $(build_htmldir)/go/index.html
+@@ -150,7 +151,7 @@ go.install-common: installdirs
+ 
+ go.install-plugin:
+ 
+-go.install-info: $(DESTDIR)$(infodir)/gccgo.info
++go.install-info: $(DESTDIR)$(infodir)/$(INFO_GCCGO_NAME).info
+ 
+ go.install-pdf: doc/gccgo.pdf
+ 	@$(NORMAL_INSTALL)
+@@ -190,7 +191,7 @@ go.uninstall:
+ 	rm -rf $(DESTDIR)$(bindir)/$(GCCGO_INSTALL_NAME)$(exeext)
+ 	rm -rf $(DESTDIR)$(man1dir)/$(GCCGO_INSTALL_NAME)$(man1ext)
+ 	rm -rf $(DESTDIR)$(bindir)/$(GCCGO_TARGET_INSTALL_NAME)$(exeext)
+-	rm -rf $(DESTDIR)$(infodir)/gccgo.info*
++	rm -rf $(DESTDIR)$(infodir)/$(INFO_GCCGO_NAME).info*
+ 
+ # Clean hooks.
+ 
+Index: b/src/gcc/go/gccgo.texi
+===================================================================
+--- a/src/gcc/go/gccgo.texi
++++ b/src/gcc/go/gccgo.texi
+@@ -50,7 +50,7 @@ man page gfdl(7).
+ @format
+ @dircategory Software development
+ @direntry
+-* Gccgo: (gccgo).           A GCC-based compiler for the Go language
++* @value{fngccgo}: (@value{fngccgo}).           A GCC-based compiler for the Go language
+ @end direntry
+ @end format
+ 
+@@ -123,7 +123,7 @@ and the Info entries for @file{gccgo} an
+ 
+ The @command{gccgo} command is a frontend to @command{gcc} and
+ supports many of the same options.  @xref{Option Summary, , Option
+-Summary, gcc, Using the GNU Compiler Collection (GCC)}.  This manual
++Summary, @value{fngcc}, Using the GNU Compiler Collection (GCC)}.  This manual
+ only documents the options specific to @command{gccgo}.
+ 
+ The @command{gccgo} command may be used to compile Go source code into
+Index: b/src/libquadmath/libquadmath.texi
+===================================================================
+--- a/src/libquadmath/libquadmath.texi
++++ b/src/libquadmath/libquadmath.texi
+@@ -25,7 +25,7 @@ copy and modify this GNU manual.
+ @ifinfo
+ @dircategory GNU Libraries
+ @direntry
+-* libquadmath: (libquadmath).                  GCC Quad-Precision Math Library
++* @value{fnlibquadmath}: (@value{fnlibquadmath}).                  GCC Quad-Precision Math Library
+ @end direntry
+ 
+ This manual documents the GCC Quad-Precision Math Library API.
+Index: b/src/libquadmath/Makefile.am
+===================================================================
+--- a/src/libquadmath/Makefile.am
++++ b/src/libquadmath/Makefile.am
+@@ -133,22 +133,24 @@ endif
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libquadmath.info
+-	cp -p $(top_builddir)/libquadmath.info $(srcdir)/libquadmath.info
++INFO_LIBQMATH_NAME = $(shell echo libquadmath|sed '$(program_transform_name)')
++
++stamp-geninsrc: $(INFO_LIBQMATH_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBQMATH_NAME).info $(srcdir)/libquadmath.info
+ 	@touch $@
+ 
+ stamp-build-info: libquadmath.texi $(libquadmath_TEXINFOS)
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libquadmath.info $(srcdir)/libquadmath.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o $(INFO_LIBQMATH_NAME).info $(srcdir)/libquadmath.texi
+ 	@touch $@
+ 
+-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libquadmath.info
+-MAINTAINERCLEANFILES = $(srcdir)/libquadmath.info
++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBQMATH_NAME).info
++MAINTAINERCLEANFILES = $(srcdir)/$(INFO_LIBQMATH_NAME).info
+ 
+ endif BUILD_LIBQUADMATH
+ 
+ # Unconditionally override this target, so that automake's definition
+ # does not wrongly interfere.
+-libquadmath.info: $(STAMP_BUILD_INFO)
++$(INFO_LIBQMATH_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ 
+ # Automake Documentation:
+Index: b/src/libquadmath/Makefile.in
+===================================================================
+--- a/src/libquadmath/Makefile.in
++++ b/src/libquadmath/Makefile.in
+@@ -169,7 +169,8 @@ MULTIDIRS =
+ MULTISUBDIR = 
+ MULTIDO = true
+ MULTICLEAN = true
+-INFO_DEPS = libquadmath.info
++INFO_LIBQMATH_NAME = $(shell echo libquadmath|sed '$(program_transform_name)')
++INFO_DEPS = $(INFO_LIBQMATH_NAME).info
+ am__TEXINFO_TEX_DIR = $(srcdir)/../gcc/doc/include
+ DVIS = libquadmath.dvi
+ PDFS = libquadmath.pdf
+@@ -406,8 +407,8 @@ AUTOMAKE_OPTIONS = 1.8 foreign
+ 
+ # AM_CONDITIONAL on configure check ACX_CHECK_PROG_VER([MAKEINFO])
+ @BUILD_INFO_TRUE@@BUILD_LIBQUADMATH_TRUE@STAMP_BUILD_INFO = stamp-build-info
+-@BUILD_LIBQUADMATH_TRUE@CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libquadmath.info
+-@BUILD_LIBQUADMATH_TRUE@MAINTAINERCLEANFILES = $(srcdir)/libquadmath.info
++@BUILD_LIBQUADMATH_TRUE@CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBQMATH_NAME).info
++@BUILD_LIBQUADMATH_TRUE@MAINTAINERCLEANFILES = $(srcdir)/$(INFO_LIBQMATH_NAME).info
+ 
+ # Automake Documentation:
+ # If your package has Texinfo files in many directories, you can use the
+@@ -1466,17 +1467,17 @@ uninstall-am: uninstall-dvi-am uninstall
+ 
+ @BUILD_LIBQUADMATH_TRUE@all-local: $(STAMP_GENINSRC)
+ 
+-@BUILD_LIBQUADMATH_TRUE@stamp-geninsrc: libquadmath.info
+-@BUILD_LIBQUADMATH_TRUE@	cp -p $(top_builddir)/libquadmath.info $(srcdir)/libquadmath.info
++@BUILD_LIBQUADMATH_TRUE@stamp-geninsrc: $(INFO_LIBQMATH_NAME).info
++@BUILD_LIBQUADMATH_TRUE@	cp -p $(top_builddir)/$(INFO_LIBQMATH_NAME).info $(srcdir)/$(INFO_LIBQMATH_NAME).info
+ @BUILD_LIBQUADMATH_TRUE@	@touch $@
+ 
+ @BUILD_LIBQUADMATH_TRUE@stamp-build-info: libquadmath.texi $(libquadmath_TEXINFOS)
+-@BUILD_LIBQUADMATH_TRUE@	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libquadmath.info $(srcdir)/libquadmath.texi
++@BUILD_LIBQUADMATH_TRUE@	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o $(INFO_LIBQMATH_NAME).info $(srcdir)/libquadmath.texi
+ @BUILD_LIBQUADMATH_TRUE@	@touch $@
+ 
+ # Unconditionally override this target, so that automake's definition
+ # does not wrongly interfere.
+-libquadmath.info: $(STAMP_BUILD_INFO)
++$(INFO_LIBQMATH_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ libquadmath-vers.texi:
+ 	echo "@set BUGURL $(REPORT_BUGS_TEXI)" > $@
--- gcc-6-6.3.0.orig/debian/patches/skip-bootstrap-multilib.diff
+++ gcc-6-6.3.0/debian/patches/skip-bootstrap-multilib.diff
@@ -0,0 +1,49 @@
+# DP: Skip non-default multilib and libstdc++-v3 debug builds in bootstrap builds
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -479,6 +479,17 @@ esac
+ # Tests like `if [ -n "$multidirs" ]' require it.
+ multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'`
+ 
++# stage1 and stage2 builds of the non-default multilib configurations
++# are not needed; skip these to save some build time.
++if [ -f ../../stage_final ] && [ -f ../../stage_current ]; then
++    stage_final=`cat ../../stage_final`
++    stage_current=`cat ../../stage_current`
++    if [ "$stage_current" != "$stage_final" ]; then
++	echo "Skip `basename $ml_realsrcdir` non-default multilibs for bootstrap stage $stage_current"
++	multidirs=
++    fi
++fi
++
+ # Add code to library's top level makefile to handle building the multilib
+ # subdirs.
+ 
+Index: b/src/libstdc++-v3/acinclude.m4
+===================================================================
+--- a/src/libstdc++-v3/acinclude.m4
++++ b/src/libstdc++-v3/acinclude.m4
+@@ -2901,7 +2901,20 @@ dnl
+ AC_DEFUN([GLIBCXX_ENABLE_DEBUG], [
+   AC_MSG_CHECKING([for additional debug build])
+   GLIBCXX_ENABLE(libstdcxx-debug,$1,,[build extra debug library])
++  if test x$enable_libstdcxx_debug = xyes; then
++    if test -f $toplevel_builddir/../stage_final && test -f $toplevel_builddir/../stage_current; then
++      stage_final=`cat $toplevel_builddir/../stage_final`
++      stage_current=`cat $toplevel_builddir/../stage_current`
++      if test x$stage_current != x$stage_final ; then
++	skip_debug_build=yes
++	enable_libstdcxx_debug=no
++      fi
++    fi
++  fi
+   AC_MSG_RESULT($enable_libstdcxx_debug)
++  if test x$skip_debug_build = xyes ; then
++    AC_MSG_NOTICE([Skip libstdc++-v3 debug build for bootstrap stage $stage_current])
++  fi
+   GLIBCXX_CONDITIONAL(GLIBCXX_BUILD_DEBUG, test $enable_libstdcxx_debug = yes)
+ ])
+ 
--- gcc-6-6.3.0.orig/debian/patches/sparc64-biarch-long-double-128.diff
+++ gcc-6-6.3.0/debian/patches/sparc64-biarch-long-double-128.diff
@@ -0,0 +1,35 @@
+# DP: Fix --with-long-double-128 for sparc32 when defaulting to 64-bit.
+
+On sparc, the --with-long-double-128 option doesn't change anything for
+a 64-bit compiler, as it always default to 128-bit long doubles. For
+a 32/64-bit compiler defaulting to 32-bit this correctly control the
+size of long double of the 32-bit compiler, however for a 32/64-bit
+compiler defaulting to 64-bit, the built-in specs force the 
+-mlong-double-64 option. This makes the option useless in this case.
+
+The patch below fixes that by removing the -mlong-double-64 from the
+built-in spec, using the default instead.
+
+Changelog gcc/
+
+2013-12-04  Aurelien Jarno  <aurelien@aurel32.net>
+
+	* config/sparc/linux64.h (CC1_SPEC): When defaulting to 64-bit,
+	don't force -mlong-double-64 when -m32 or -mv8plus is given.
+
+Index: b/src/gcc/config/sparc/linux64.h
+===================================================================
+--- a/src/gcc/config/sparc/linux64.h
++++ b/src/gcc/config/sparc/linux64.h
+@@ -154,9 +154,9 @@ extern const char *host_detect_local_cpu
+ #else
+ #define CC1_SPEC "%{profile:-p} \
+ %{m32:%{m64:%emay not use both -m32 and -m64}} \
+-%{m32:-mptr32 -mno-stack-bias %{!mlong-double-128:-mlong-double-64} \
++%{m32:-mptr32 -mno-stack-bias \
+   %{!mcpu*:-mcpu=cypress}} \
+-%{mv8plus:-mptr32 -mno-stack-bias %{!mlong-double-128:-mlong-double-64} \
++%{mv8plus:-mptr32 -mno-stack-bias \
+   %{!mcpu*:-mcpu=v9}} \
+ %{!m32:%{!mcpu*:-mcpu=ultrasparc}} \
+ %{!mno-vis:%{!m32:%{!mcpu=v9:-mvis}}} \
--- gcc-6-6.3.0.orig/debian/patches/src_gcc_config_i386_gnu.h.diff
+++ gcc-6-6.3.0/debian/patches/src_gcc_config_i386_gnu.h.diff
@@ -0,0 +1,25 @@
+Index: gcc-6-6.2.1-4.1/src/gcc/config/i386/gnu.h
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/gcc/config/i386/gnu.h
++++ gcc-6-6.2.1-4.1/src/gcc/config/i386/gnu.h
+@@ -37,11 +37,14 @@ along with GCC.  If not, see <http://www
+ 
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+ 
+-/* Not supported yet.  */
+-# undef TARGET_THREAD_SSP_OFFSET
+-
+-/* Not supported yet.  */
+-# undef TARGET_CAN_SPLIT_STACK
+-# undef TARGET_THREAD_SPLIT_STACK_OFFSET
++/* i386 glibc provides __stack_chk_guard in %gs:0x14.  */
++#define TARGET_THREAD_SSP_OFFSET        0x14
+ 
++/* We only build the -fsplit-stack support in libgcc if the
++   assembler has full support for the CFI directives.  */
++#if HAVE_GAS_CFI_PERSONALITY_DIRECTIVE
++#define TARGET_CAN_SPLIT_STACK
++#endif
++/* We steal the last transactional memory word.  */
++#define TARGET_THREAD_SPLIT_STACK_OFFSET 0x30
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_Makefile.am.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_Makefile.am.diff
@@ -0,0 +1,281 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/Makefile.am
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/Makefile.am
++++ gcc-6-6.2.1-4.1/src/libgo/Makefile.am
+@@ -419,6 +419,9 @@ else
+ if LIBGO_IS_NETBSD
+ runtime_getncpu_file = runtime/getncpu-bsd.c
+ else
++if LIBGO_IS_GNU
++runtime_getncpu_file = runtime/getncpu-gnu.c
++else
+ runtime_getncpu_file = runtime/getncpu-none.c
+ endif
+ endif
+@@ -426,6 +429,7 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ runtime_netpoll_files = runtime/netpoll_epoll.c
+@@ -433,9 +437,13 @@ else
+ if LIBGO_IS_SOLARIS
+ runtime_netpoll_files = runtime/netpoll_select.c
+ else
++if LIBGO_IS_GNU
++runtime_netpoll_files = runtime/netpoll_select.c
++else
+ runtime_netpoll_files = runtime/netpoll_kqueue.c
+ endif
+ endif
++endif
+ 
+ runtime_files = \
+ 	runtime/go-append.c \
+@@ -744,6 +752,14 @@ go_net_sockoptip_file = go/net/sockoptip
+ go_net_cgo_sock_file = go/net/cgo_sockold.go
+ go_net_cgo_res_file = go/net/cgo_resnew.go
+ else
++if LIBGO_IS_GNU
++go_net_cgo_file = go/net/cgo_linux.go
++go_net_sock_file = go/net/sock_gnu.go
++go_net_sockopt_file = go/net/sockopt_gnu.go
++go_net_sockoptip_file = go/net/sockoptip_gnu.go go/net/sockoptip_posix.go
++go_net_cgo_sock_file = go/net/cgo_socknew.go
++go_net_cgo_res_file = go/net/cgo_resnew.go
++else
+ go_net_cgo_file = go/net/cgo_bsd.go
+ go_net_sock_file = go/net/sock_bsd.go
+ go_net_sockopt_file = go/net/sockopt_bsd.go
+@@ -755,6 +771,7 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ go_net_sendfile_file = go/net/sendfile_linux.go
+@@ -768,11 +785,15 @@ else
+ if LIBGO_IS_SOLARIS
+ go_net_sendfile_file = go/net/sendfile_solaris.go
+ else
++if LIBGO_IS_GNU
++go_net_sendfile_file = go/net/sendfile_gnu.go
++else
+ go_net_sendfile_file = go/net/sendfile_stub.go
+ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ go_net_interface_file = go/net/interface_linux.go
+@@ -794,9 +815,13 @@ else
+ if LIBGO_IS_FREEBSD
+ go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ else
++if LIBGO_IS_GNU
++go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
++else
+ go_net_cloexec_file = go/net/sys_cloexec.go
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_OPENBSD
+ go_net_tcpsockopt_file = go/net/tcpsockopt_openbsd.go
+@@ -889,9 +914,13 @@ else
+ if LIBGO_IS_LINUX
+ go_os_dir_file = go/os/dir_largefile.go
+ else
++if LIBGO_IS_GNU
++go_os_dir_file = go/os/dir_largefile.go
++else
+ go_os_dir_file = go/os/dir_regfile.go
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_DARWIN
+ go_os_getwd_file = go/os/getwd_darwin.go
+@@ -911,11 +940,15 @@ else
+ if LIBGO_IS_RTEMS
+ go_os_sys_file = go/os/sys_uname.go
+ else
++if LIBGO_IS_GNU
++go_os_sys_file = go/os/sys_uname.go
++else
+ go_os_sys_file = go/os/sys_bsd.go
+ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_FREEBSD
+ go_os_cloexec_file = go/os/sys_freebsd.go
+@@ -937,6 +970,9 @@ else
+ if LIBGO_IS_LINUX
+ go_os_stat_file = go/os/stat_atim.go
+ else
++if LIBGO_IS_GNU
++go_os_stat_file = go/os/stat_atim.go
++else
+ if LIBGO_IS_OPENBSD
+ go_os_stat_file = go/os/stat_atim.go
+ else
+@@ -960,12 +996,17 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ go_os_pipe_file = go/os/pipe_linux.go
+ else
++if LIBGO_IS_GNU
++go_os_pipe_file = go/os/pipe_linux.go
++else
+ go_os_pipe_file = go/os/pipe_bsd.go
+ endif
++endif
+ 
+ if LIBGO_IS_DARWIN
+ go_os_sticky_file = go/os/sticky_bsd.go
+@@ -1158,6 +1199,9 @@ go_unicode_files = \
+ if LIBGO_IS_LINUX
+ archive_tar_atim_file = go/archive/tar/stat_atim.go
+ endif
++if LIBGO_IS_GNU
++archive_tar_atim_file = go/archive/tar/stat_atim.go
++endif
+ if LIBGO_IS_OPENBSD
+ archive_tar_atim_file = go/archive/tar/stat_atim.go
+ endif
+@@ -1322,6 +1366,9 @@ else
+ if LIBGO_IS_DARWIN
+ go_crypto_x509_root_file = go/crypto/x509/root_darwin.go
+ else
++if LIBGO_IS_GNU
++go_crypto_x509_root_file = go/crypto/x509/root_linux.go
++else
+ go_crypto_x509_root_file =
+ endif
+ endif
+@@ -1330,6 +1377,7 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ go_crypto_x509_files = \
+ 	go/crypto/x509/cert_pool.go \
+@@ -1857,10 +1905,15 @@ if LIBGO_IS_LINUX
+ syscall_exec_file = go/syscall/exec_unix.go
+ syscall_exec_os_file = go/syscall/exec_linux.go
+ else
++if LIBGO_IS_GNU
++syscall_exec_file = go/syscall/exec_unix.go
++syscall_exec_os_file = go/syscall/exec_bsd.go
++else
+ syscall_exec_file = go/syscall/exec_unix.go
+ syscall_exec_os_file = go/syscall/exec_bsd.go
+ endif
+ endif
++endif
+ 
+ # Define Wait4.
+ if LIBGO_IS_RTEMS
+@@ -1894,6 +1947,9 @@ else
+ if LIBGO_IS_RTEMS
+ syscall_errstr_file = go/syscall/errstr_linux.go
+ else
++if LIBGO_IS_GNU
++syscall_errstr_file = go/syscall/errstr_linux.go
++else
+ if HAVE_STRERROR_R
+ syscall_errstr_file = go/syscall/errstr.go
+ else
+@@ -1901,12 +1957,16 @@ syscall_errstr_file = go/syscall/errstr_
+ endif
+ endif
+ endif
++endif
+ 
+ # Declare libc functions that vary for largefile systems.
+ if LIBGO_IS_LINUX
+ # Always use lseek64 on GNU/Linux.
+ syscall_size_file = go/syscall/libcall_posix_largefile.go
+ else # !LIBGO_IS_LINUX
++if LIBGO_IS_GNU
++syscall_size_file = go/syscall/libcall_posix_largefile.go
++else # !LIBGO_IS_LINUX && !LIBGO_IS_GNU
+ if LIBGO_IS_SOLARIS
+ if LIBGO_IS_386
+ # Use lseek64 on 32-bit Solaris/x86.
+@@ -1924,6 +1984,7 @@ else # !LIBGO_IS_LINUX && !LIBGO_IS_SOLA
+ # Use lseek by default.
+ syscall_size_file = go/syscall/libcall_posix_regfile.go
+ endif # !LIBGO_IS_SOLARIS
++endif # !LIBGO_IS_LINUX && !LIBGO_IS_GNU
+ endif # !LIBGO_IS_LINUX
+ 
+ # Define socket sizes and types.
+@@ -1946,10 +2007,14 @@ else
+ if LIBGO_IS_IRIX
+ syscall_socket_file = go/syscall/socket_irix.go
+ else
++if LIBGO_IS_GNU
++syscall_socket_file = go/syscall/socket_gnu.go
++else
+ syscall_socket_file = go/syscall/socket_bsd.go
+ endif
+ endif
+ endif
++endif
+ 
+ # Define socket functions.
+ if LIBGO_IS_SOLARIS
+@@ -2028,11 +2093,20 @@ else
+ syscall_os_file = go/syscall/libcall_bsd.go
+ endif
+ 
++# GNU/Hurd specific library calls support.
++if LIBGO_IS_GNU
++syscall_libcall_file = go/syscall/libcall_posix-1.go
++syscall_os_test_file = go/syscall/syscall_gnu_test.go
++else
++syscall_libcall_file = go/syscall/libcall_posix.go
++syscall_os_test_file = go/syscall/syscall_unix_test.go
++endif
++
+ go_base_syscall_files = \
+ 	go/syscall/env_unix.go \
+ 	go/syscall/syscall_errno.go \
+ 	go/syscall/libcall_support.go \
+-	go/syscall/libcall_posix.go \
++	$(syscall_libcall_file) \
+ 	go/syscall/msan0.go \
+ 	go/syscall/socket.go \
+ 	go/syscall/sockcmsg_unix.go \
+@@ -2078,7 +2152,7 @@ go_syscall_test_files = \
+ 	go/syscall/export_unix_test.go \
+ 	go/syscall/mmap_unix_test.go \
+ 	go/syscall/syscall_test.go \
+-	go/syscall/syscall_unix_test.go
++	$(syscall_os_test_file)
+ 
+ libcalls.go: s-libcalls; @true
+ s-libcalls: libcalls-list go/syscall/mksyscall.awk $(go_base_syscall_files)
+@@ -4431,7 +4505,7 @@ mostlyclean-local:
+ 	find . -name '*-testsum' -print | xargs rm -f
+ 	find . -name '*-testlog' -print | xargs rm -f
+ 
+-CLEANFILES = *.go *.gox goc2c *.c s-version libgo.sum libgo.log
++CLEANFILES = *.go *.gox goc2c *.c s-* libgo.sum libgo.log
+ 
+ clean-local:
+ 	find . -name '*.la' -print | xargs $(LIBTOOL) --mode=clean rm -f
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_Makefile.in.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_Makefile.in.diff
@@ -0,0 +1,475 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/Makefile.in
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/Makefile.in
++++ gcc-6-6.2.1-4.1/src/libgo/Makefile.in
+@@ -230,11 +230,13 @@ libgo_llgo_la_DEPENDENCIES = $(am__DEPEN
+ @LIBGO_IS_LINUX_TRUE@am__objects_4 = lock_futex.lo thread-linux.lo
+ @HAVE_SYS_MMAN_H_FALSE@am__objects_5 = mem_posix_memalign.lo
+ @HAVE_SYS_MMAN_H_TRUE@am__objects_5 = mem.lo
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_6 = netpoll_kqueue.lo
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_6 = netpoll_kqueue.lo
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_6 = netpoll_select.lo
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@am__objects_6 = netpoll_select.lo
+ @LIBGO_IS_LINUX_TRUE@am__objects_6 = netpoll_epoll.lo
+ @LIBGO_IS_RTEMS_TRUE@am__objects_7 = rtems-task-variable-add.lo
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-none.lo
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-none.lo
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-gnu.lo
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-bsd.lo
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-bsd.lo
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@am__objects_8 = getncpu-solaris.lo
+@@ -300,10 +302,10 @@ LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLF
+ SOURCES = $(libgobegin_llgo_a_SOURCES) $(libgobegin_a_SOURCES) \
+ 	$(libgolibbegin_a_SOURCES) $(libnetgo_a_SOURCES) \
+ 	$(libgo_llgo_la_SOURCES) $(libgo_la_SOURCES)
+-MULTISRCTOP = 
+-MULTIBUILDTOP = 
+-MULTIDIRS = 
+-MULTISUBDIR = 
++MULTISRCTOP =
++MULTIBUILDTOP =
++MULTIDIRS =
++MULTISUBDIR =
+ MULTIDO = true
+ MULTICLEAN = true
+ RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+@@ -523,7 +525,7 @@ AM_CFLAGS = -fexceptions -fnon-call-exce
+ @USING_SPLIT_STACK_TRUE@AM_LDFLAGS = -XCClinker $(SPLIT_STACK)
+ 
+ # Multilib support.
+-MAKEOVERRIDES = 
++MAKEOVERRIDES =
+ 
+ # Work around what appears to be a GNU make  handling MAKEFLAGS
+ # values defined in terms of make variables, as is the case for CC and
+@@ -818,18 +820,20 @@ toolexeclibgounicode_DATA = \
+ 
+ @HAVE_SYS_MMAN_H_FALSE@runtime_mem_file = runtime/mem_posix_memalign.c
+ @HAVE_SYS_MMAN_H_TRUE@runtime_mem_file = runtime/mem.c
+-@LIBGO_IS_RTEMS_FALSE@rtems_task_variable_add_file = 
++@LIBGO_IS_RTEMS_FALSE@rtems_task_variable_add_file =
+ @LIBGO_IS_RTEMS_TRUE@rtems_task_variable_add_file = runtime/rtems-task-variable-add.c
+ @LIBGO_IS_LINUX_FALSE@runtime_lock_files = runtime/lock_sema.c runtime/thread-sema.c
+ @LIBGO_IS_LINUX_TRUE@runtime_lock_files = runtime/lock_futex.c runtime/thread-linux.c
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-none.c
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-none.c
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-gnu.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-bsd.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-bsd.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@runtime_getncpu_file = runtime/getncpu-solaris.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@runtime_getncpu_file = runtime/getncpu-irix.c
+ @LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_LINUX_FALSE@runtime_getncpu_file = runtime/getncpu-bsd.c
+ @LIBGO_IS_LINUX_TRUE@runtime_getncpu_file = runtime/getncpu-linux.c
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_netpoll_files = runtime/netpoll_kqueue.c
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_netpoll_files = runtime/netpoll_kqueue.c
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_netpoll_files = runtime/netpoll_select.c
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@runtime_netpoll_files = runtime/netpoll_select.c
+ @LIBGO_IS_LINUX_TRUE@runtime_netpoll_files = runtime/netpoll_epoll.c
+ runtime_files = \
+@@ -1036,7 +1040,7 @@ go_math_files = \
+ 	go/math/tanh.go \
+ 	go/math/unsafe.go
+ 
+-@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file = 
++@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file =
+ @LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file = go/mime/type_dragonfly.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file = go/mime/type_freebsd.go
+ @LIBGO_IS_OPENBSD_TRUE@go_mime_type_file = go/mime/type_openbsd.go
+@@ -1048,43 +1052,50 @@ go_mime_files = \
+ 	go/mime/type_unix.go \
+ 	$(go_mime_type_file)
+ 
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_linux.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_netbsd.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_bsd.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_cgo_file = go/net/cgo_solaris.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cgo_file = go/net/cgo_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cgo_file = go/net/cgo_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_gnu.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sock_file = go/net/sock_stub.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sock_file = go/net/sock_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_net_sock_file = go/net/sock_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_gnu.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sockopt_file = go/net/sockopt_solaris.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sockopt_file = go/net/sockopt_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_net_sockopt_file = go/net/sockopt_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_gnu.go go/net/sockoptip_posix.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sockoptip_file = go/net/sockoptip_stub.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sockoptip_file = go/net/sockoptip_linux.go go/net/sockoptip_posix.go
+ @LIBGO_IS_LINUX_TRUE@go_net_sockoptip_file = go/net/sockoptip_linux.go go/net/sockoptip_posix.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resold.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cgo_res_file = go/net/cgo_resnew.go
+-@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sendfile_file = go/net/sendfile_stub.go
++@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sendfile_file = go/net/sendfile_stub.go
++@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sendfile_file = go/net/sendfile_gnu.go
+ @LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sendfile_file = go/net/sendfile_solaris.go
+ @LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_sendfile_file = go/net/sendfile_dragonfly.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sendfile_file = go/net/sendfile_freebsd.go
+@@ -1093,7 +1104,8 @@ go_mime_files = \
+ @LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@go_net_interface_file = go/net/interface_dragonfly.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@go_net_interface_file = go/net/interface_netbsd.go
+ @LIBGO_IS_LINUX_TRUE@go_net_interface_file = go/net/interface_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sys_cloexec.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sys_cloexec.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_tcpsockopt_file = go/net/tcpsockopt_unix.go
+@@ -1163,11 +1175,13 @@ go_netgo_files = \
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_FALSE@go_os_dir_file = go/os/dir_regfile.go
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_TRUE@go_os_dir_file = go/os/dir_largefile.go
+ @LIBGO_IS_386_TRUE@@LIBGO_IS_SOLARIS_TRUE@go_os_dir_file = go/os/dir_largefile.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_regfile.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_regfile.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_largefile.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_largefile.go
+-@LIBGO_IS_DARWIN_FALSE@go_os_getwd_file = 
++@LIBGO_IS_DARWIN_FALSE@go_os_getwd_file =
+ @LIBGO_IS_DARWIN_TRUE@go_os_getwd_file = go/os/getwd_darwin.go
+-@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_uname.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_uname.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_uname.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_os_sys_file = go/os/sys_uname.go
+@@ -1177,14 +1191,16 @@ go_netgo_files = \
+ @LIBGO_IS_FREEBSD_TRUE@go_os_cloexec_file = go/os/sys_freebsd.go
+ @HAVE_STAT_TIMESPEC_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_os_stat_file = go/os/stat_solaris.go
+ @HAVE_STAT_TIMESPEC_TRUE@@LIBGO_IS_SOLARIS_TRUE@go_os_stat_file = go/os/stat_atim.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_dragonfly.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
+-@LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_dragonfly.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
++@LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
+-@LIBGO_IS_LINUX_FALSE@go_os_pipe_file = go/os/pipe_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@go_os_pipe_file = go/os/pipe_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@go_os_pipe_file = go/os/pipe_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_os_pipe_file = go/os/pipe_linux.go
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sticky_file = go/os/sticky_notbsd.go
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_os_sticky_file = go/os/sticky_bsd.go
+@@ -1328,6 +1344,7 @@ go_unicode_files = \
+ 
+ @LIBGO_IS_DARWIN_TRUE@archive_tar_atim_file = go/archive/tar/stat_atimespec.go
+ @LIBGO_IS_FREEBSD_TRUE@archive_tar_atim_file = go/archive/tar/stat_atimespec.go
++@LIBGO_IS_GNU_TRUE@archive_tar_atim_file = go/archive/tar/stat_atim.go
+ @LIBGO_IS_LINUX_TRUE@archive_tar_atim_file = go/archive/tar/stat_atim.go
+ @LIBGO_IS_NETBSD_TRUE@archive_tar_atim_file = go/archive/tar/stat_atimespec.go
+ @LIBGO_IS_OPENBSD_TRUE@archive_tar_atim_file = go/archive/tar/stat_atim.go
+@@ -1421,7 +1438,7 @@ go_crypto_md5_files = \
+ 	go/crypto/md5/md5block.go \
+ 	go/crypto/md5/md5block_generic.go
+ 
+-@LIBGO_IS_LINUX_FALSE@crypto_rand_file = 
++@LIBGO_IS_LINUX_FALSE@crypto_rand_file =
+ @LIBGO_IS_LINUX_TRUE@crypto_rand_file = go/crypto/rand/rand_linux.go
+ go_crypto_rand_files = \
+ 	go/crypto/rand/eagain.go \
+@@ -1468,7 +1485,8 @@ go_crypto_tls_files = \
+ 	go/crypto/tls/ticket.go \
+ 	go/crypto/tls/tls.go
+ 
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = 
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file =
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_linux.go
+ @LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_darwin.go
+ @LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_bsd.go
+ @LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_bsd.go
+@@ -1772,7 +1790,7 @@ go_internal_singleflight_files = \
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_ARM_TRUE@@LIBGO_IS_LINUX_TRUE@@LIBGO_IS_X86_64_FALSE@internal_syscall_unix_getrandom_files = go/internal/syscall/unix/getrandom_linux.go go/internal/syscall/unix/getrandom_linux_arm.go
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_LINUX_TRUE@@LIBGO_IS_X86_64_TRUE@internal_syscall_unix_getrandom_files = go/internal/syscall/unix/getrandom_linux.go go/internal/syscall/unix/getrandom_linux_amd64.go
+ @LIBGO_IS_386_TRUE@@LIBGO_IS_LINUX_TRUE@internal_syscall_unix_getrandom_files = go/internal/syscall/unix/getrandom_linux.go go/internal/syscall/unix/getrandom_linux_386.go
+-@LIBGO_IS_LINUX_FALSE@internal_syscall_unix_getrandom_files = 
++@LIBGO_IS_LINUX_FALSE@internal_syscall_unix_getrandom_files =
+ go_internal_syscall_unix_files = \
+ 	go/internal/syscall/unix/dummy.go \
+ 	$(internal_syscall_unix_getrandom_files)
+@@ -1904,7 +1922,7 @@ go_net_http_internal_files = \
+ 	go/net/http/internal/chunked.go \
+ 	go/net/http/internal/testcert.go
+ 
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_internal_socktest_sys = 
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_internal_socktest_sys =
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_internal_socktest_sys = go/net/internal/socktest/sys_cloexec.go
+ @LIBGO_IS_LINUX_TRUE@go_net_internal_socktest_sys = go/net/internal/socktest/sys_cloexec.go
+ go_net_internal_socktest_files = \
+@@ -2012,52 +2030,57 @@ go_unicode_utf8_files = \
+ 
+ # Define Syscall and Syscall6.
+ @LIBGO_IS_RTEMS_TRUE@syscall_syscall_file = go/syscall/syscall_stubs.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
+ 
+ # Define ForkExec and Exec.
+ @LIBGO_IS_RTEMS_TRUE@syscall_exec_file = go/syscall/exec_stubs.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_bsd.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_linux.go
+-@LIBGO_IS_RTEMS_TRUE@syscall_exec_os_file = 
++@LIBGO_IS_RTEMS_TRUE@syscall_exec_os_file =
+ @HAVE_WAIT4_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_wait_file = go/syscall/libcall_waitpid.go
+ @HAVE_WAIT4_TRUE@@LIBGO_IS_RTEMS_FALSE@syscall_wait_file = go/syscall/libcall_wait4.go
+ 
+ # Define Wait4.
+-@LIBGO_IS_RTEMS_TRUE@syscall_wait_file = 
++@LIBGO_IS_RTEMS_TRUE@syscall_wait_file =
+ @LIBGO_IS_RTEMS_FALSE@syscall_wait_c_file = go/syscall/wait.c
+ 
+ # Support for pulling apart wait status.
+-@LIBGO_IS_RTEMS_TRUE@syscall_wait_c_file = 
++@LIBGO_IS_RTEMS_TRUE@syscall_wait_c_file =
+ @LIBGO_IS_RTEMS_FALSE@syscall_sleep_file = go/syscall/sleep_select.go
+ 
+ # Define Sleep.
+ @LIBGO_IS_RTEMS_TRUE@syscall_sleep_file = go/syscall/sleep_rtems.go
+-@HAVE_STRERROR_R_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr_nor.go
+-@HAVE_STRERROR_R_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr.go
++@HAVE_STRERROR_R_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr_nor.go
++@HAVE_STRERROR_R_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr_linux.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_TRUE@syscall_errstr_file = go/syscall/errstr_linux.go
+ 
+ # Define Errstr.
+ @LIBGO_IS_LINUX_TRUE@syscall_errstr_file = go/syscall/errstr_linux.go
+ # Use lseek on 64-bit Solaris.
+-@LIBGO_IS_386_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
++@LIBGO_IS_386_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
+ # Use lseek64 on 32-bit Solaris/SPARC.
+-@LIBGO_IS_386_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
++@LIBGO_IS_386_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+ # Use lseek64 on 32-bit Solaris/x86.
+-@LIBGO_IS_386_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
++@LIBGO_IS_386_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+ # Use lseek by default.
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+ 
+ # Declare libc functions that vary for largefile systems.
+ # Always use lseek64 on GNU/Linux.
+ @LIBGO_IS_LINUX_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+-@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_gnu.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_irix.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@syscall_socket_file = go/syscall/socket_solaris.go
+ 
+ # Define socket sizes and types.
+ @LIBGO_IS_LINUX_TRUE@syscall_socket_file = go/syscall/socket_linux.go epoll.go
+-@LIBGO_IS_LINUX_FALSE@syscall_socket_type_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_socket_type_file =
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_PPC64LE_FALSE@@LIBGO_IS_PPC64_FALSE@syscall_socket_type_file = go/syscall/socket_linux_type.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_PPC64LE_FALSE@@LIBGO_IS_PPC64_TRUE@syscall_socket_type_file = go/syscall/socket_linux_ppc64x_type.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_PPC64LE_TRUE@syscall_socket_type_file = go/syscall/socket_linux_ppc64x_type.go
+@@ -2069,42 +2092,48 @@ go_unicode_utf8_files = \
+ 
+ # Support for uname.
+ # 32-bit Solaris 2/x86 needs _nuname, handled in libcall_solaris_386.go.
+-@LIBGO_IS_386_TRUE@@LIBGO_IS_SOLARIS_TRUE@syscall_uname_file = 
++@LIBGO_IS_386_TRUE@@LIBGO_IS_SOLARIS_TRUE@syscall_uname_file =
+ @LIBGO_IS_SOLARIS_FALSE@syscall_uname_file = go/syscall/libcall_uname.go
+-@LIBGO_IS_LINUX_FALSE@syscall_sockcmsg_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_sockcmsg_file =
+ 
+ # GNU/Linux specific socket control messages.
+ @LIBGO_IS_LINUX_TRUE@syscall_sockcmsg_file = go/syscall/sockcmsg_linux.go
+-@LIBGO_IS_LINUX_FALSE@syscall_netlink_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_netlink_file =
+ 
+ # Support for netlink sockets and messages.
+ @LIBGO_IS_LINUX_TRUE@syscall_netlink_file = go/syscall/netlink_linux.go
+-@LIBGO_IS_LINUX_FALSE@syscall_lsf_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_lsf_file =
+ 
+ # GNU/Linux specific socket filters.
+ @LIBGO_IS_LINUX_TRUE@syscall_lsf_file = go/syscall/lsf_linux.go
+ @LIBGO_IS_ARM64_FALSE@@LIBGO_IS_LINUX_TRUE@syscall_ustat_file = go/syscall/libcall_linux_ustat.go
+ 
+ # GNU/Linux specific ustat support.
+-@LIBGO_IS_ARM64_TRUE@@LIBGO_IS_LINUX_TRUE@syscall_ustat_file = 
+-@LIBGO_IS_LINUX_FALSE@syscall_ustat_file = 
++@LIBGO_IS_ARM64_TRUE@@LIBGO_IS_LINUX_TRUE@syscall_ustat_file =
++@LIBGO_IS_LINUX_FALSE@syscall_ustat_file =
+ @LIBGO_IS_LINUX_FALSE@syscall_utimesnano_file = go/syscall/libcall_posix_utimesnano.go
+ 
+ # GNU/Linux specific utimesnano support.
+ @LIBGO_IS_LINUX_TRUE@syscall_utimesnano_file = go/syscall/libcall_linux_utimesnano.go
+-@LIBGO_IS_LINUX_FALSE@syscall_creds_test_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_creds_test_file =
+ 
+ # Test files.
+ @LIBGO_IS_LINUX_TRUE@syscall_creds_test_file = go/syscall/creds_test.go
+-@LIBGO_IS_LINUX_FALSE@syscall_exec_test_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_exec_test_file =
+ @LIBGO_IS_LINUX_TRUE@syscall_exec_test_file = go/syscall/exec_linux_test.go go/syscall/syscall_linux_test.go
+ @LIBGO_IS_LINUX_FALSE@syscall_os_file = go/syscall/libcall_bsd.go
+-@LIBGO_IS_LINUX_TRUE@syscall_os_file = 
++@LIBGO_IS_LINUX_TRUE@syscall_os_file =
++@LIBGO_IS_GNU_FALSE@syscall_libcall_file = go/syscall/libcall_posix.go
++
++# GNU/Hurd specific library calls support.
++@LIBGO_IS_GNU_TRUE@syscall_libcall_file = go/syscall/libcall_posix-1.go
++@LIBGO_IS_GNU_FALSE@syscall_os_test_file = go/syscall/syscall_unix_test.go
++@LIBGO_IS_GNU_TRUE@syscall_os_test_file = go/syscall/syscall_gnu_test.go
+ go_base_syscall_files = \
+ 	go/syscall/env_unix.go \
+ 	go/syscall/syscall_errno.go \
+ 	go/syscall/libcall_support.go \
+-	go/syscall/libcall_posix.go \
++	$(syscall_libcall_file) \
+ 	go/syscall/msan0.go \
+ 	go/syscall/socket.go \
+ 	go/syscall/sockcmsg_unix.go \
+@@ -2151,13 +2180,13 @@ go_syscall_test_files = \
+ 	go/syscall/export_unix_test.go \
+ 	go/syscall/mmap_unix_test.go \
+ 	go/syscall/syscall_test.go \
+-	go/syscall/syscall_unix_test.go
++	$(syscall_os_test_file)
+ 
+-@LIBGO_IS_LINUX_FALSE@os_lib_inotify_lo = 
++@LIBGO_IS_LINUX_FALSE@os_lib_inotify_lo =
+ 
+ # os_lib_inotify_lo = os/inotify.lo
+-@LIBGO_IS_LINUX_TRUE@os_lib_inotify_lo = 
+-@LIBGO_IS_LINUX_FALSE@syscall_lib_clone_lo = 
++@LIBGO_IS_LINUX_TRUE@os_lib_inotify_lo =
++@LIBGO_IS_LINUX_FALSE@syscall_lib_clone_lo =
+ @LIBGO_IS_LINUX_TRUE@syscall_lib_clone_lo = syscall/clone_linux.lo
+ libgo_go_objs = \
+ 	bufio.lo \
+@@ -2380,8 +2409,8 @@ BUILDNETGO = \
+ 	files=`echo $^ | sed -e 's/[^ ]*\.gox//g'`; \
+ 	$(GOCOMPILE) -I . -c -fPIC -fgo-pkgpath=net -o $@ $$files
+ 
+-GOTESTFLAGS = 
+-GOBENCH = 
++GOTESTFLAGS =
++GOBENCH =
+ 
+ # Check a package.
+ CHECK = \
+@@ -2586,7 +2615,7 @@ TEST_PACKAGES = \
+ 	unicode/utf8/check
+ 
+ MOSTLYCLEAN_FILES = libgo.head libgo.sum.sep libgo.log.sep
+-CLEANFILES = *.go *.gox goc2c *.c s-version libgo.sum libgo.log
++CLEANFILES = *.go *.gox goc2c *.c s-* libgo.sum libgo.log
+ all: config.h
+ 	$(MAKE) $(AM_MAKEFLAGS) all-recursive
+ 
+@@ -2634,7 +2663,7 @@ config.h: stamp-h1
+ stamp-h1: $(srcdir)/config.h.in $(top_builddir)/config.status
+ 	@rm -f stamp-h1
+ 	cd $(top_builddir) && $(SHELL) ./config.status config.h
+-$(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) 
++$(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ 	($(am__cd) $(top_srcdir) && $(AUTOHEADER))
+ 	rm -f stamp-h1
+ 	touch $@
+@@ -2672,19 +2701,19 @@ uninstall-toolexeclibLIBRARIES:
+ 
+ clean-toolexeclibLIBRARIES:
+ 	-test -z "$(toolexeclib_LIBRARIES)" || rm -f $(toolexeclib_LIBRARIES)
+-libgobegin-llgo.a: $(libgobegin_llgo_a_OBJECTS) $(libgobegin_llgo_a_DEPENDENCIES) $(EXTRA_libgobegin_llgo_a_DEPENDENCIES) 
++libgobegin-llgo.a: $(libgobegin_llgo_a_OBJECTS) $(libgobegin_llgo_a_DEPENDENCIES) $(EXTRA_libgobegin_llgo_a_DEPENDENCIES)
+ 	-rm -f libgobegin-llgo.a
+ 	$(libgobegin_llgo_a_AR) libgobegin-llgo.a $(libgobegin_llgo_a_OBJECTS) $(libgobegin_llgo_a_LIBADD)
+ 	$(RANLIB) libgobegin-llgo.a
+-libgobegin.a: $(libgobegin_a_OBJECTS) $(libgobegin_a_DEPENDENCIES) $(EXTRA_libgobegin_a_DEPENDENCIES) 
++libgobegin.a: $(libgobegin_a_OBJECTS) $(libgobegin_a_DEPENDENCIES) $(EXTRA_libgobegin_a_DEPENDENCIES)
+ 	-rm -f libgobegin.a
+ 	$(libgobegin_a_AR) libgobegin.a $(libgobegin_a_OBJECTS) $(libgobegin_a_LIBADD)
+ 	$(RANLIB) libgobegin.a
+-libgolibbegin.a: $(libgolibbegin_a_OBJECTS) $(libgolibbegin_a_DEPENDENCIES) $(EXTRA_libgolibbegin_a_DEPENDENCIES) 
++libgolibbegin.a: $(libgolibbegin_a_OBJECTS) $(libgolibbegin_a_DEPENDENCIES) $(EXTRA_libgolibbegin_a_DEPENDENCIES)
+ 	-rm -f libgolibbegin.a
+ 	$(libgolibbegin_a_AR) libgolibbegin.a $(libgolibbegin_a_OBJECTS) $(libgolibbegin_a_LIBADD)
+ 	$(RANLIB) libgolibbegin.a
+-libnetgo.a: $(libnetgo_a_OBJECTS) $(libnetgo_a_DEPENDENCIES) $(EXTRA_libnetgo_a_DEPENDENCIES) 
++libnetgo.a: $(libnetgo_a_OBJECTS) $(libnetgo_a_DEPENDENCIES) $(EXTRA_libnetgo_a_DEPENDENCIES)
+ 	-rm -f libnetgo.a
+ 	$(libnetgo_a_AR) libnetgo.a $(libnetgo_a_OBJECTS) $(libnetgo_a_LIBADD)
+ 	$(RANLIB) libnetgo.a
+@@ -2720,9 +2749,9 @@ clean-toolexeclibLTLIBRARIES:
+ 	  echo "rm -f \"$${dir}/so_locations\""; \
+ 	  rm -f "$${dir}/so_locations"; \
+ 	done
+-libgo-llgo.la: $(libgo_llgo_la_OBJECTS) $(libgo_llgo_la_DEPENDENCIES) $(EXTRA_libgo_llgo_la_DEPENDENCIES) 
++libgo-llgo.la: $(libgo_llgo_la_OBJECTS) $(libgo_llgo_la_DEPENDENCIES) $(EXTRA_libgo_llgo_la_DEPENDENCIES)
+ 	$(libgo_llgo_la_LINK) $(am_libgo_llgo_la_rpath) $(libgo_llgo_la_OBJECTS) $(libgo_llgo_la_LIBADD) $(LIBS)
+-libgo.la: $(libgo_la_OBJECTS) $(libgo_la_DEPENDENCIES) $(EXTRA_libgo_la_DEPENDENCIES) 
++libgo.la: $(libgo_la_OBJECTS) $(libgo_la_DEPENDENCIES) $(EXTRA_libgo_la_DEPENDENCIES)
+ 	$(libgo_la_LINK) $(am_libgo_la_rpath) $(libgo_la_OBJECTS) $(libgo_la_LIBADD) $(LIBS)
+ 
+ mostlyclean-compile:
+@@ -2735,6 +2764,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpuprof.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/env_posix.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-bsd.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-gnu.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-irix.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-linux.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-none.Plo@am__quote@
+@@ -3561,6 +3591,13 @@ getncpu-none.lo: runtime/getncpu-none.c
+ @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ @am__fastdepCC_FALSE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o getncpu-none.lo `test -f 'runtime/getncpu-none.c' || echo '$(srcdir)/'`runtime/getncpu-none.c
+ 
++getncpu-gnu.lo: runtime/getncpu-gnu.c
++@am__fastdepCC_TRUE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT getncpu-gnu.lo -MD -MP -MF $(DEPDIR)/getncpu-gnu.Tpo -c -o getncpu-gnu.lo `test -f 'runtime/getncpu-gnu.c' || echo '$(srcdir)/'`runtime/getncpu-gnu.c
++@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/getncpu-gnu.Tpo $(DEPDIR)/getncpu-gnu.Plo
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='runtime/getncpu-gnu.c' object='getncpu-gnu.lo' libtool=yes @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o getncpu-gnu.lo `test -f 'runtime/getncpu-gnu.c' || echo '$(srcdir)/'`runtime/getncpu-gnu.c
++
+ getncpu-bsd.lo: runtime/getncpu-bsd.c
+ @am__fastdepCC_TRUE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT getncpu-bsd.lo -MD -MP -MF $(DEPDIR)/getncpu-bsd.Tpo -c -o getncpu-bsd.lo `test -f 'runtime/getncpu-bsd.c' || echo '$(srcdir)/'`runtime/getncpu-bsd.c
+ @am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/getncpu-bsd.Tpo $(DEPDIR)/getncpu-bsd.Plo
+@@ -6307,7 +6344,7 @@ crypto/des.gox: crypto/des.lo
+ 	$(BUILDGOX)
+ crypto/dsa.gox: crypto/dsa.lo
+ 	$(BUILDGOX)
+-crypto/ecdsa.gox: crypto/ecdsa.lo	
++crypto/ecdsa.gox: crypto/ecdsa.lo
+ 	$(BUILDGOX)
+ crypto/elliptic.gox: crypto/elliptic.lo
+ 	$(BUILDGOX)
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_configure.ac.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_configure.ac.diff
@@ -0,0 +1,28 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/configure.ac
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/configure.ac
++++ gcc-6-6.2.1-4.1/src/libgo/configure.ac
+@@ -151,6 +151,7 @@ is_openbsd=no
+ is_dragonfly=no
+ is_rtems=no
+ is_solaris=no
++is_gnu=no
+ GOOS=unknown
+ case ${host} in
+   *-*-darwin*)   is_darwin=yes;  GOOS=darwin ;;
+@@ -162,6 +163,7 @@ case ${host} in
+   *-*-dragonfly*) is_dragonfly=yes; GOOS=dragonfly ;;
+   *-*-rtems*)    is_rtems=yes;   GOOS=rtems ;;
+   *-*-solaris2*) is_solaris=yes; GOOS=solaris ;;
++  *-*-gnu*)      is_gnu=yes;     GOOS=gnu ;;
+ esac
+ AM_CONDITIONAL(LIBGO_IS_DARWIN, test $is_darwin = yes)
+ AM_CONDITIONAL(LIBGO_IS_FREEBSD, test $is_freebsd = yes)
+@@ -172,6 +174,7 @@ AM_CONDITIONAL(LIBGO_IS_OPENBSD, test $i
+ AM_CONDITIONAL(LIBGO_IS_DRAGONFLY, test $is_dragonfly = yes)
+ AM_CONDITIONAL(LIBGO_IS_RTEMS, test $is_rtems = yes)
+ AM_CONDITIONAL(LIBGO_IS_SOLARIS, test $is_solaris = yes)
++AM_CONDITIONAL(LIBGO_IS_GNU, test $is_gnu = yes)
+ AC_SUBST(GOOS)
+ 
+ dnl Test whether we need to use DejaGNU or whether we can use the
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_net_sendfile_gnu.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_net_sendfile_gnu.go.diff
@@ -0,0 +1,84 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sendfile_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sendfile_gnu.go
+@@ -0,0 +1,79 @@
++// Copyright 2011 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++package net
++
++import (
++	"io"
++	"os"
++	"syscall"
++)
++
++// maxSendfileSize is the largest chunk size we ask the kernel to copy
++// at a time.
++const maxSendfileSize int = 4 << 20
++
++// sendFile copies the contents of r to c using the sendfile
++// system call to minimize copies.
++//
++// if handled == true, sendFile returns the number of bytes copied and any
++// non-EOF error.
++//
++// if handled == false, sendFile performed no work.
++func sendFile(c *netFD, r io.Reader) (written int64, err error, handled bool) {
++	var remain int64 = 1 << 62 // by default, copy until EOF
++
++	lr, ok := r.(*io.LimitedReader)
++	if ok {
++		remain, r = lr.N, lr.R
++		if remain <= 0 {
++			return 0, nil, true
++		}
++	}
++	f, ok := r.(*os.File)
++	if !ok {
++		return 0, nil, false
++	}
++
++	if err := c.writeLock(); err != nil {
++		return 0, err, true
++	}
++	defer c.writeUnlock()
++
++	dst := c.sysfd
++	src := int(f.Fd())
++	for remain > 0 {
++		n := maxSendfileSize
++		if int64(n) > remain {
++			n = int(remain)
++		}
++		n, err1 := syscall.Sendfile(dst, src, nil, n)
++		if n > 0 {
++			written += int64(n)
++			remain -= int64(n)
++		}
++		if n == 0 && err1 == nil {
++			break
++		}
++		if err1 == syscall.EAGAIN {
++			if err1 = c.pd.WaitWrite(); err1 == nil {
++				continue
++			}
++		}
++		if err1 != nil {
++			// This includes syscall.ENOSYS (no kernel
++			// support) and syscall.EINVAL (fd types which
++			// don't implement sendfile)
++			err = err1
++			break
++		}
++	}
++	if lr != nil {
++		lr.N = remain
++	}
++	if err != nil {
++		err = os.NewSyscallError("sendfile", err)
++	}
++	return written, err, written > 0
++}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_net_sock_gnu.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_net_sock_gnu.go.diff
@@ -0,0 +1,19 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sock_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sock_gnu.go
+@@ -0,0 +1,14 @@
++// Copyright 2014 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package net
++
++import "syscall"
++
++func maxListenerBacklog() int {
++       // From /usr/include/i386-gnu/bits/socket.h
++       return syscall.SOMAXCONN
++}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_net_sockopt_gnu.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_net_sockopt_gnu.go.diff
@@ -0,0 +1,50 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_gnu.go
+@@ -0,0 +1,45 @@
++// Copyright 2011 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package net
++
++import (
++	"os"
++	"syscall"
++)
++
++func setDefaultSockopts(s, family, sotype int, ipv6only bool) error {
++	if family == syscall.AF_INET6 && sotype != syscall.SOCK_RAW {
++		// Allow both IP versions even if the OS default
++		// is otherwise.  Note that some operating systems
++		// never admit this option.
++		syscall.SetsockoptInt(s, syscall.IPPROTO_IPV6, syscall.IPV6_V6ONLY, boolint(ipv6only))
++	}
++	// Allow broadcast.
++	return os.NewSyscallError("setsockopt", syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_BROADCAST, 1))
++}
++
++func setDefaultListenerSockopts(s int) error {
++	// Allow reuse of recently-used addresses.
++	return os.NewSyscallError("setsockopt", syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_REUSEADDR, 1))
++}
++
++func setDefaultMulticastSockopts(s int) error {
++	// Allow multicast UDP and raw IP datagram sockets to listen
++	// concurrently across multiple listeners.
++	if err := syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_REUSEADDR, 1); err != nil {
++		return os.NewSyscallError("setsockopt", err)
++	}
++	// Allow reuse of recently-used ports.
++	// This option is supported only in descendants of 4.4BSD,
++	// to make an effective multicast application that requires
++	// quick draw possible.
++	// Not supported on GNU/Hurd
++	//if syscall.SO_REUSEPORT != 0 {
++	//	return os.NewSyscallError("setsockopt", syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_REUSEPORT, 1))
++	//}
++	return nil
++}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_net_sockoptip_gnu.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_net_sockoptip_gnu.go.diff
@@ -0,0 +1,35 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_gnu.go
+@@ -0,0 +1,30 @@
++// Copyright 2011 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package net
++
++import (
++	"os"
++	"syscall"
++)
++
++func setIPv4MulticastInterface(fd *netFD, ifi *Interface) error {
++	ip, err := interfaceToIPv4Addr(ifi)
++	if err != nil {
++		return os.NewSyscallError("setsockopt", err)
++	}
++	var a [4]byte
++	copy(a[:], ip.To4())
++	if err := fd.incref(); err != nil {
++		return err
++	}
++	defer fd.decref()
++	return os.NewSyscallError("setsockopt", syscall.SetsockoptInet4Addr(fd.sysfd, syscall.IPPROTO_IP, syscall.IP_MULTICAST_IF, a))
++}
++
++func setIPv4MulticastLoopback(fd *netFD, v bool) error {
++	return syscall.ENOPROTOOPT
++}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_os_os_test.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_os_os_test.go.diff
@@ -0,0 +1,15 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/os_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/os_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/os_test.go
+@@ -1192,8 +1192,9 @@ func TestSeek(t *testing.T) {
+ 	for i, tt := range tests {
+ 		off, err := f.Seek(tt.in, tt.whence)
+ 		if off != tt.out || err != nil {
+-			if e, ok := err.(*PathError); ok && e.Err == syscall.EINVAL && tt.out > 1<<32 {
++			if e, ok := err.(*PathError); ok && e.Err == syscall.EINVAL || e.Err == syscall.EFBIG && tt.out > 1<<32 {
+ 				// Reiserfs rejects the big seeks.
++				// GNU rejects the big seeks, returns EFBIG
+ 				// https://golang.org/issue/91
+ 				break
+ 			}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_syscall_libcall_gnu.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_syscall_libcall_gnu.go.diff
@@ -0,0 +1,190 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu.go
+@@ -0,0 +1,185 @@
++// Copyright 2014 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// GNU/Hurd library calls.
++
++package syscall
++
++import "unsafe"
++
++//sys   Openat(dirfd int, path string, flags int, mode uint32) (fd int, err error)
++//__go_openat(dirfd _C_int, path *byte, flags _C_int, mode Mode_t) _C_int
++
++//sys   futimesat(dirfd int, path *byte, times *[2]Timeval) (err error)
++//futimesat(dirfd _C_int, path *byte, times *[2]Timeval) _C_int
++func Futimesat(dirfd int, path string, tv []Timeval) (err error) {
++	if len(tv) != 2 {
++		return EINVAL
++	}
++	return futimesat(dirfd, StringBytePtr(path), (*[2]Timeval)(unsafe.Pointer(&tv[0])))
++}
++
++func Futimes(fd int, tv []Timeval) (err error) {
++	// Believe it or not, this is the best we can do on GNU/Linux
++	// (and is what glibc does).
++	return Utimes("/proc/self/fd/"+itoa(fd), tv)
++}
++
++//sys   ptrace(request int, pid int, addr uintptr, data uintptr) (err error)
++//ptrace(request _C_int, pid Pid_t, addr *byte, data *byte) _C_long
++
++// Dummy function
++func raw_ptrace(request int, pid int, addr *byte, data *byte) Errno {
++	return ENOSYS
++}
++
++//sys   accept4(fd int, sa *RawSockaddrAny, len *Socklen_t, flags int) (nfd int, err error)
++//accept4(fd _C_int, sa *RawSockaddrAny, len *Socklen_t, flags _C_int) _C_int
++
++func Accept4(fd int, flags int) (nfd int, sa Sockaddr, err error) {
++	var rsa RawSockaddrAny
++	var len Socklen_t = SizeofSockaddrAny
++	nfd, err = accept4(fd, &rsa, &len, flags)
++	if err != nil {
++		return -1, nil, err
++	}
++	sa, err = anyToSockaddr(&rsa)
++	if err != nil {
++		Close(nfd)
++		return -1, nil, err
++	}
++	return nfd, sa, nil
++}
++
++///INCLUDE?
++///sys   Acct(path string) (err error)
++///acct(path *byte) _C_int
++
++//sysnb Dup3(oldfd int, newfd int, flags int) (err error)
++//dup3(oldfd _C_int, newfd _C_int, flags _C_int) _C_int
++
++//sys   Faccessat(dirfd int, path string, mode uint32, flags int) (err error)
++//faccessat(dirfd _C_int, pathname *byte, mode _C_int, flags _C_int) _C_int
++
++//sys   Fallocate(fd int, mode uint32, off int64, len int64) (err error)
++//fallocate(fd _C_int, mode _C_int, offset Offset_t, len Offset_t) _C_int
++
++//sys   Fchmodat(dirfd int, path string, mode uint32, flags int) (err error)
++//fchmodat(dirfd _C_int, pathname *byte, mode Mode_t, flags _C_int) _C_int
++
++//sys   Fchownat(dirfd int, path string, uid int, gid int, flags int) (err error)
++//fchownat(dirfd _C_int, path *byte, owner Uid_t, group Gid_t, flags _C_int) _C_int
++
++//sys   Flock(fd int, how int) (err error)
++//flock(fd _C_int, how _C_int) _C_int
++
++//sys   Fstatfs(fd int, buf *Statfs_t) (err error)
++//fstatfs(fd _C_int, buf *Statfs_t) _C_int
++
++func Getdents(fd int, buf []byte) (n int, err error) {
++	var p *byte
++	if len(buf) > 0 {
++		p = &buf[0]
++	} else {
++		p = (*byte)(unsafe.Pointer(&_zero))
++	}
++	s := SYS_GETDENTS64
++	if s == 0 {
++		s = SYS_GETDENTS
++	}
++	r1, _, errno := Syscall(uintptr(s), uintptr(fd), uintptr(unsafe.Pointer(p)), uintptr(len(buf)))
++	n = int(r1)
++	if n < 0 {
++		err = errno
++	}
++	return
++}
++
++func clen(n []byte) int {
++	for i := 0; i < len(n); i++ {
++		if n[i] == 0 {
++			return i
++		}
++	}
++	return len(n)
++}
++
++func ReadDirent(fd int, buf []byte) (n int, err error) {
++	return Getdents(fd, buf)
++}
++
++func ParseDirent(buf []byte, max int, names []string) (consumed int, count int, newnames []string) {
++	origlen := len(buf)
++	count = 0
++	for max != 0 && len(buf) > 0 {
++		dirent := (*Dirent)(unsafe.Pointer(&buf[0]))
++		buf = buf[dirent.Reclen:]
++		if dirent.Ino == 0 { // File absent in directory.
++			continue
++		}
++		bytes := (*[10000]byte)(unsafe.Pointer(&dirent.Name[0]))
++		var name = string(bytes[0:clen(bytes[:])])
++		if name == "." || name == ".." { // Useless names
++			continue
++		}
++		max--
++		count++
++		names = append(names, name)
++	}
++	return origlen - len(buf), count, names
++}
++
++///INCLUDE??
++///sys   Getxattr(path string, attr string, dest []byte) (sz int, err error)
++///getxattr(path *byte, attr *byte, buf *byte, count Size_t) Ssize_t
++
++///INCLUDE??
++///sys   Listxattr(path string, dest []byte) (sz int, err error)
++///listxattr(path *byte, list *byte, size Size_t) Ssize_t
++
++//sys   Mkdirat(dirfd int, path string, mode uint32) (err error)
++//mkdirat(dirfd _C_int, path *byte, mode Mode_t) _C_int
++
++//sys   Mknodat(dirfd int, path string, mode uint32, dev int) (err error)
++//mknodat(dirfd _C_int, path *byte, mode Mode_t, dev _dev_t) _C_int
++
++//sysnb pipe2(p *[2]_C_int, flags int) (err error)
++//pipe2(p *[2]_C_int, flags _C_int) _C_int
++func Pipe2(p []int, flags int) (err error) {
++	if len(p) != 2 {
++		return EINVAL
++	}
++	var pp [2]_C_int
++	err = pipe2(&pp, flags)
++	p[0] = int(pp[0])
++	p[1] = int(pp[1])
++	return
++}
++
++///INCLUDE??
++///sys   Removexattr(path string, attr string) (err error)
++///removexattr(path *byte, name *byte) _C_int
++
++///INCLUDE??
++///sys   Renameat(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)
++///renameat(olddirfd _C_int, oldpath *byte, newdirfd _C_int, newpath *byte) _C_int
++
++//INCLUDE??
++///sys   Setxattr(path string, attr string, data []byte, flags int) (err error)
++///setxattr(path *byte, name *byte, value *byte, size Size_t, flags _C_int) _C_int
++
++//sys   SyncFileRange(fd int, off int64, n int64, flags int) (err error)
++//sync_file_range(fd _C_int, off Offset_t, n Offset_t, flags _C_uint) _C_int
++
++//INCLUDE??
++///sysnb Sysinfo(info *Sysinfo_t) (err error)
++///sysinfo(info *Sysinfo_t) _C_int
++
++//func Unlinkat(dirfd int, path string) (err error) {
++//	return unlinkat(dirfd, path, 0)
++//}
++
++///INCLUDE??
++///sys   Ustat(dev int, ubuf *Ustat_t) (err error)
++///ustat(dev _dev_t, ubuf *Ustat_t) _C_int
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_syscall_libcall_gnu_386.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_syscall_libcall_gnu_386.go.diff
@@ -0,0 +1,15 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu_386.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu_386.go
+@@ -0,0 +1,10 @@
++// Copyright 2012 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// GNU/Hurd library calls 386 specific.
++
++package syscall
++
++//sys	Ioperm(from int, num int, on int) (err error)
++//ioperm(from _C_long, num _C_long, on _C_int) _C_int
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_syscall_libcall_posix-1.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_syscall_libcall_posix-1.go.diff
@@ -0,0 +1,398 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_posix-1.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_posix-1.go
+@@ -0,0 +1,393 @@
++// Copyright 2011 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// POSIX library calls.
++// Removed the mount call for GNU/Hurd, it exists but use translators.
++// Functionality is not the same as descibed in Linux <sys/mount.h>
++// Removed the mlockall/munlockall calls for GNU/Hurd, not yet implemented.
++// Removed the madvise call for GNU/Hurd, not yet implemented.
++// This file is compiled as ordinary Go code,
++// but it is also input to mksyscall,
++// which parses the //sys lines and generates library call stubs.
++// Note that sometimes we use a lowercase //sys name and
++// wrap it in our own nicer implementation.
++
++package syscall
++
++import "unsafe"
++
++/*
++ * Wrapped
++ */
++
++//sysnb	pipe(p *[2]_C_int) (err error)
++//pipe(p *[2]_C_int) _C_int
++func Pipe(p []int) (err error) {
++	if len(p) != 2 {
++		return EINVAL
++	}
++	var pp [2]_C_int
++	err = pipe(&pp)
++	p[0] = int(pp[0])
++	p[1] = int(pp[1])
++	return
++}
++
++//sys	utimes(path string, times *[2]Timeval) (err error)
++//utimes(path *byte, times *[2]Timeval) _C_int
++func Utimes(path string, tv []Timeval) (err error) {
++	if len(tv) != 2 {
++		return EINVAL
++	}
++	return utimes(path, (*[2]Timeval)(unsafe.Pointer(&tv[0])))
++}
++
++//sys	getcwd(buf *byte, size Size_t) (err error)
++//getcwd(buf *byte, size Size_t) *byte
++
++const ImplementsGetwd = true
++
++func Getwd() (ret string, err error) {
++	for len := Size_t(4096); ; len *= 2 {
++		b := make([]byte, len)
++		err := getcwd(&b[0], len)
++		if err == nil {
++			i := 0
++			for b[i] != 0 {
++				i++
++			}
++			return string(b[0:i]), nil
++		}
++		if err != ERANGE {
++			return "", err
++		}
++	}
++}
++
++func Getcwd(buf []byte) (n int, err error) {
++	err = getcwd(&buf[0], Size_t(len(buf)))
++	if err == nil {
++		i := 0
++		for buf[i] != 0 {
++			i++
++		}
++		n = i + 1
++	}
++	return
++}
++
++//sysnb	getgroups(size int, list *Gid_t) (nn int, err error)
++//getgroups(size _C_int, list *Gid_t) _C_int
++
++func Getgroups() (gids []int, err error) {
++	n, err := getgroups(0, nil)
++	if err != nil {
++		return nil, err
++	}
++	if n == 0 {
++		return nil, nil
++	}
++
++	// Sanity check group count.  Max is 1<<16 on GNU/Linux.
++	if n < 0 || n > 1<<20 {
++		return nil, EINVAL
++	}
++
++	a := make([]Gid_t, n)
++	n, err = getgroups(n, &a[0])
++	if err != nil {
++		return nil, err
++	}
++	gids = make([]int, n)
++	for i, v := range a[0:n] {
++		gids[i] = int(v)
++	}
++	return
++}
++
++//sysnb	setgroups(n int, list *Gid_t) (err error)
++//setgroups(n Size_t, list *Gid_t) _C_int
++
++func Setgroups(gids []int) (err error) {
++	if len(gids) == 0 {
++		return setgroups(0, nil)
++	}
++
++	a := make([]Gid_t, len(gids))
++	for i, v := range gids {
++		a[i] = Gid_t(v)
++	}
++	return setgroups(len(a), &a[0])
++}
++
++type WaitStatus uint32
++
++// The WaitStatus methods are implemented in C, to pick up the macros
++// #defines in <sys/wait.h>.
++
++func (w WaitStatus) Exited() bool
++func (w WaitStatus) Signaled() bool
++func (w WaitStatus) Stopped() bool
++func (w WaitStatus) Continued() bool
++func (w WaitStatus) CoreDump() bool
++func (w WaitStatus) ExitStatus() int
++func (w WaitStatus) Signal() Signal
++func (w WaitStatus) StopSignal() Signal
++func (w WaitStatus) TrapCause() int
++
++//sys	Mkfifo(path string, mode uint32) (err error)
++//mkfifo(path *byte, mode Mode_t) _C_int
++
++//sys	Select(nfd int, r *FdSet, w *FdSet, e *FdSet, timeout *Timeval) (n int, err error)
++//select(nfd _C_int, r *FdSet, w *FdSet, e *FdSet, timeout *Timeval) _C_int
++
++const nfdbits = int(unsafe.Sizeof(fds_bits_type(0)) * 8)
++
++type FdSet struct {
++	Bits [(FD_SETSIZE + nfdbits - 1) / nfdbits]fds_bits_type
++}
++
++func FDSet(fd int, set *FdSet) {
++	set.Bits[fd/nfdbits] |= (1 << (uint)(fd%nfdbits))
++}
++
++func FDClr(fd int, set *FdSet) {
++	set.Bits[fd/nfdbits] &^= (1 << (uint)(fd%nfdbits))
++}
++
++func FDIsSet(fd int, set *FdSet) bool {
++	if set.Bits[fd/nfdbits]&(1<<(uint)(fd%nfdbits)) != 0 {
++		return true
++	} else {
++		return false
++	}
++}
++
++func FDZero(set *FdSet) {
++	for i := range set.Bits {
++		set.Bits[i] = 0
++	}
++}
++
++//sys	Access(path string, mode uint32) (err error)
++//access(path *byte, mode _C_int) _C_int
++
++//sys	Chdir(path string) (err error)
++//chdir(path *byte) _C_int
++
++//sys	Chmod(path string, mode uint32) (err error)
++//chmod(path *byte, mode Mode_t) _C_int
++
++//sys	Chown(path string, uid int, gid int) (err error)
++//chown(path *byte, uid Uid_t, gid Gid_t) _C_int
++
++//sys	Chroot(path string) (err error)
++//chroot(path *byte) _C_int
++
++//sys	Close(fd int) (err error)
++//close(fd _C_int) _C_int
++
++//sys	Creat(path string, mode uint32) (fd int, err error)
++//creat(path *byte, mode Mode_t) _C_int
++
++//sysnb	Dup(oldfd int) (fd int, err error)
++//dup(oldfd _C_int) _C_int
++
++//sysnb	Dup2(oldfd int, newfd int) (err error)
++//dup2(oldfd _C_int, newfd _C_int) _C_int
++
++//sys	Exit(code int)
++//exit(code _C_int)
++
++//sys	Fchdir(fd int) (err error)
++//fchdir(fd _C_int) _C_int
++
++//sys	Fchmod(fd int, mode uint32) (err error)
++//fchmod(fd _C_int, mode Mode_t) _C_int
++
++//sys	Fchown(fd int, uid int, gid int) (err error)
++//fchown(fd _C_int, uid Uid_t, gid Gid_t) _C_int
++
++//sys	fcntl(fd int, cmd int, arg int) (val int, err error)
++//__go_fcntl(fd _C_int, cmd _C_int, arg _C_int) _C_int
++
++//sys	FcntlFlock(fd uintptr, cmd int, lk *Flock_t) (err error)
++//__go_fcntl_flock(fd _C_int, cmd _C_int, arg *Flock_t) _C_int
++
++//sys	Fdatasync(fd int) (err error)
++//fdatasync(fd _C_int) _C_int
++
++//sys	Fsync(fd int) (err error)
++//fsync(fd _C_int) _C_int
++
++//sysnb Getegid() (egid int)
++//getegid() Gid_t
++
++//sysnb Geteuid() (euid int)
++//geteuid() Uid_t
++
++//sysnb Getgid() (gid int)
++//getgid() Gid_t
++
++//sysnb	Getpagesize() (pagesize int)
++//getpagesize() _C_int
++
++//sysnb	Getpgid(pid int) (pgid int, err error)
++//getpgid(pid Pid_t) Pid_t
++
++//sysnb	Getpgrp() (pid int)
++//getpgrp() Pid_t
++
++//sysnb	Getpid() (pid int)
++//getpid() Pid_t
++
++//sysnb	Getppid() (ppid int)
++//getppid() Pid_t
++
++//sys Getpriority(which int, who int) (prio int, err error)
++//getpriority(which _C_int, who _C_int) _C_int
++
++//sysnb	Getrusage(who int, rusage *Rusage) (err error)
++//getrusage(who _C_int, rusage *Rusage) _C_int
++
++//sysnb	gettimeofday(tv *Timeval, tz *byte) (err error)
++//gettimeofday(tv *Timeval, tz *byte) _C_int
++func Gettimeofday(tv *Timeval) (err error) {
++	return gettimeofday(tv, nil)
++}
++
++//sysnb Getuid() (uid int)
++//getuid() Uid_t
++
++//sysnb	Kill(pid int, sig Signal) (err error)
++//kill(pid Pid_t, sig _C_int) _C_int
++
++//sys	Lchown(path string, uid int, gid int) (err error)
++//lchown(path *byte, uid Uid_t, gid Gid_t) _C_int
++
++//sys	Link(oldpath string, newpath string) (err error)
++//link(oldpath *byte, newpath *byte) _C_int
++
++//sys	Mkdir(path string, mode uint32) (err error)
++//mkdir(path *byte, mode Mode_t) _C_int
++
++//sys	Mknod(path string, mode uint32, dev int) (err error)
++//mknod(path *byte, mode Mode_t, dev _dev_t) _C_int
++
++//sys	Nanosleep(time *Timespec, leftover *Timespec) (err error)
++//nanosleep(time *Timespec, leftover *Timespec) _C_int
++
++//sys	Pause() (err error)
++//pause() _C_int
++
++//sys	read(fd int, p []byte) (n int, err error)
++//read(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	readlen(fd int, p *byte, np int) (n int, err error)
++//read(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	Readlink(path string, buf []byte) (n int, err error)
++//readlink(path *byte, buf *byte, bufsiz Size_t) Ssize_t
++
++//sys	Rename(oldpath string, newpath string) (err error)
++//rename(oldpath *byte, newpath *byte) _C_int
++
++//sys	Rmdir(path string) (err error)
++//rmdir(path *byte) _C_int
++
++//sys	Setdomainname(p []byte) (err error)
++//setdomainname(name *byte, len Size_t) _C_int
++
++//sys	Sethostname(p []byte) (err error)
++//sethostname(name *byte, len Size_t) _C_int
++
++//sysnb	Setgid(gid int) (err error)
++//setgid(gid Gid_t) _C_int
++
++//sysnb Setregid(rgid int, egid int) (err error)
++//setregid(rgid Gid_t, egid Gid_t) _C_int
++
++//sysnb	Setpgid(pid int, pgid int) (err error)
++//setpgid(pid Pid_t, pgid Pid_t) _C_int
++
++//sys Setpriority(which int, who int, prio int) (err error)
++//setpriority(which _C_int, who _C_int, prio _C_int) _C_int
++
++//sysnb	Setreuid(ruid int, euid int) (err error)
++//setreuid(ruid Uid_t, euid Uid_t) _C_int
++
++//sysnb	Setsid() (pid int, err error)
++//setsid() Pid_t
++
++//sysnb	settimeofday(tv *Timeval, tz *byte) (err error)
++//settimeofday(tv *Timeval, tz *byte) _C_int
++
++func Settimeofday(tv *Timeval) (err error) {
++	return settimeofday(tv, nil)
++}
++
++//sysnb	Setuid(uid int) (err error)
++//setuid(uid Uid_t) _C_int
++
++//sys	Symlink(oldpath string, newpath string) (err error)
++//symlink(oldpath *byte, newpath *byte) _C_int
++
++//sys	Sync()
++//sync()
++
++//sysnb	Time(t *Time_t) (tt Time_t, err error)
++//time(t *Time_t) Time_t
++
++//sysnb	Times(tms *Tms) (ticks uintptr, err error)
++//times(tms *Tms) _clock_t
++
++//sysnb	Umask(mask int) (oldmask int)
++//umask(mask Mode_t) Mode_t
++
++//sys	Unlink(path string) (err error)
++//unlink(path *byte) _C_int
++
++//sys	Utime(path string, buf *Utimbuf) (err error)
++//utime(path *byte, buf *Utimbuf) _C_int
++
++//sys	write(fd int, p []byte) (n int, err error)
++//write(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	writelen(fd int, p *byte, np int) (n int, err error)
++//write(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	munmap(addr uintptr, length uintptr) (err error)
++//munmap(addr *byte, length Size_t) _C_int
++
++//sys	Mprotect(b []byte, prot int) (err error)
++//mprotect(addr *byte, len Size_t, prot _C_int) _C_int
++
++//sys	Mlock(b []byte) (err error)
++//mlock(addr *byte, len Size_t) _C_int
++
++//sys	Munlock(b []byte) (err error)
++//munlock(addr *byte, len Size_t) _C_int
++
++func TimespecToNsec(ts Timespec) int64 { return int64(ts.Sec)*1e9 + int64(ts.Nsec) }
++
++func NsecToTimespec(nsec int64) (ts Timespec) {
++	ts.Sec = Timespec_sec_t(nsec / 1e9)
++	ts.Nsec = Timespec_nsec_t(nsec % 1e9)
++	return
++}
++
++func TimevalToNsec(tv Timeval) int64 { return int64(tv.Sec)*1e9 + int64(tv.Usec)*1e3 }
++
++func NsecToTimeval(nsec int64) (tv Timeval) {
++	nsec += 999 // round up to microsecond
++	tv.Sec = Timeval_sec_t(nsec / 1e9)
++	tv.Usec = Timeval_usec_t(nsec % 1e9 / 1e3)
++	return
++}
++
++//sysnb	Tcgetattr(fd int, p *Termios) (err error)
++//tcgetattr(fd _C_int, p *Termios) _C_int
++
++//sys	Tcsetattr(fd int, actions int, p *Termios) (err error)
++//tcsetattr(fd _C_int, actions _C_int, p *Termios) _C_int
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_syscall_socket_gnu.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_syscall_socket_gnu.go.diff
@@ -0,0 +1,93 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/socket_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/socket_gnu.go
+@@ -0,0 +1,88 @@
++// socket_gnu.go -- Socket handling specific to GNU/Hurd.
++
++// Copyright 2010 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++package syscall
++
++import "unsafe"
++
++const SizeofSockaddrInet4 = 16
++const SizeofSockaddrInet6 = 28
++const SizeofSockaddrUnix = 110
++
++type RawSockaddrInet4 struct {
++	Len    uint8
++	Family uint8
++	Port   uint16
++	Addr   [4]byte /* in_addr */
++	Zero   [8]uint8
++}
++
++func (sa *RawSockaddrInet4) setLen() Socklen_t {
++	sa.Len = SizeofSockaddrInet4
++	return SizeofSockaddrInet4
++}
++
++type RawSockaddrInet6 struct {
++	Len      uint8
++	Family   uint8
++	Port     uint16
++	Flowinfo uint32
++	Addr     [16]byte /* in6_addr */
++	Scope_id uint32
++}
++
++func (sa *RawSockaddrInet6) setLen() Socklen_t {
++	sa.Len = SizeofSockaddrInet6
++	return SizeofSockaddrInet6
++}
++
++type RawSockaddrUnix struct {
++	Len    uint8
++	Family uint8
++	Path   [108]int8
++}
++
++func (sa *RawSockaddrUnix) setLen(n int) {
++	sa.Len = uint8(3 + n) // 2 for Family, Len; 1 for NUL.
++}
++
++func (sa *RawSockaddrUnix) getLen() (int, error) {
++	if sa.Len < 3 || sa.Len > SizeofSockaddrUnix {
++		return 0, EINVAL
++	}
++	// Assume path ends at NUL.
++	n := 0
++	for n < len(sa.Path) && sa.Path[n] != 0 {
++		n++
++	}
++	return n, nil
++}
++
++func (sa *RawSockaddrUnix) adjustAbstract(sl Socklen_t) Socklen_t {
++	return sl
++}
++
++type RawSockaddr struct {
++	Len    uint8
++	Family uint8
++	Data   [14]int8
++}
++
++// BindToDevice binds the socket associated with fd to device.
++func BindToDevice(fd int, device string) (err error) {
++	return ENOSYS
++}
++
++func anyToSockaddrOS(rsa *RawSockaddrAny) (Sockaddr, error) {
++	return nil, EAFNOSUPPORT
++}
++
++func GetsockoptIPv6MTUInfo(fd, level, opt int) (*IPv6MTUInfo, error) {
++	var value IPv6MTUInfo
++	vallen := Socklen_t(SizeofIPv6MTUInfo)
++	err := getsockopt(fd, level, opt, unsafe.Pointer(&value), &vallen)
++	return &value, err
++}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_syscall_syscall_gnu_test.go.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_syscall_syscall_gnu_test.go.diff
@@ -0,0 +1,361 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_gnu_test.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_gnu_test.go
+@@ -0,0 +1,356 @@
++// Copyright 2013 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package syscall_test
++
++import (
++	"flag"
++	"fmt"
++	"internal/testenv"
++	"io/ioutil"
++	"net"
++	"os"
++	"os/exec"
++	"path/filepath"
++	"runtime"
++	"syscall"
++	"testing"
++	"time"
++)
++
++// Tests that below functions, structures and constants are consistent
++// on all Unix-like systems.
++func _() {
++	// program scheduling priority functions and constants
++	var (
++		_ func(int, int, int) error   = syscall.Setpriority
++		_ func(int, int) (int, error) = syscall.Getpriority
++	)
++	const (
++		_ int = syscall.PRIO_USER
++		_ int = syscall.PRIO_PROCESS
++		_ int = syscall.PRIO_PGRP
++	)
++
++	// termios constants
++	const (
++		_ int = syscall.TCIFLUSH
++		_ int = syscall.TCIOFLUSH
++		_ int = syscall.TCOFLUSH
++	)
++
++	// fcntl file locking structure and constants
++	var (
++		_ = syscall.Flock_t{
++			Type:   int32(0),
++			Whence: int32(0),
++			Start:  int64(0),
++			Len:    int64(0),
++			Pid:    int32(0),
++		}
++	)
++	const (
++		_ = syscall.F_GETLK
++		_ = syscall.F_SETLK
++		_ = syscall.F_SETLKW
++	)
++}
++
++// TestFcntlFlock tests whether the file locking structure matches
++// the calling convention of each kernel.
++// On some Linux systems, glibc uses another set of values for the
++// commands and translates them to the correct value that the kernel
++// expects just before the actual fcntl syscall. As Go uses raw
++// syscalls directly, it must use the real value, not the glibc value.
++// Thus this test also verifies that the Flock_t structure can be
++// roundtripped with F_SETLK and F_GETLK.
++func TestFcntlFlock(t *testing.T) {
++	if runtime.GOOS == "darwin" && (runtime.GOARCH == "arm" || runtime.GOARCH == "arm64") {
++		t.Skip("skipping; no child processes allowed on iOS")
++	}
++	flock := syscall.Flock_t{
++		Type:  syscall.F_WRLCK,
++		Start: 31415, Len: 271828, Whence: 1,
++	}
++	if os.Getenv("GO_WANT_HELPER_PROCESS") == "" {
++		// parent
++		name := filepath.Join(os.TempDir(), "TestFcntlFlock")
++		fd, err := syscall.Open(name, syscall.O_CREAT|syscall.O_RDWR|syscall.O_CLOEXEC, 0)
++		if err != nil {
++			t.Fatalf("Open failed: %v", err)
++		}
++		defer syscall.Unlink(name)
++		defer syscall.Close(fd)
++		if err := syscall.Ftruncate(fd, 1<<20); err != nil {
++			t.Fatalf("Ftruncate(1<<20) failed: %v", err)
++		}
++		if err := syscall.FcntlFlock(uintptr(fd), syscall.F_SETLK, &flock); err != nil {
++			t.Fatalf("FcntlFlock(F_SETLK) failed: %v", err)
++		}
++		cmd := exec.Command(os.Args[0], "-test.run=^TestFcntlFlock$")
++		cmd.Env = append(os.Environ(), "GO_WANT_HELPER_PROCESS=1")
++		cmd.ExtraFiles = []*os.File{os.NewFile(uintptr(fd), name)}
++		out, err := cmd.CombinedOutput()
++		if len(out) > 0 || err != nil {
++			t.Fatalf("child process: %q, %v", out, err)
++		}
++	} else {
++		// child
++		got := flock
++		// make sure the child lock is conflicting with the parent lock
++		got.Start--
++		got.Len++
++		if err := syscall.FcntlFlock(3, syscall.F_GETLK, &got); err != nil {
++			t.Fatalf("FcntlFlock(F_GETLK) failed: %v", err)
++		}
++		flock.Pid = int32(syscall.Getppid())
++		// Linux kernel always set Whence to 0
++		flock.Whence = 0
++		if got.Type == flock.Type && got.Start == flock.Start && got.Len == flock.Len && got.Pid == flock.Pid && got.Whence == flock.Whence {
++			os.Exit(0)
++		}
++		t.Fatalf("FcntlFlock got %v, want %v", got, flock)
++	}
++}
++
++// TestPassFD tests passing a file descriptor over a Unix socket.
++//
++// This test involved both a parent and child process. The parent
++// process is invoked as a normal test, with "go test", which then
++// runs the child process by running the current test binary with args
++// "-test.run=^TestPassFD$" and an environment variable used to signal
++// that the test should become the child process instead.
++func TestPassFD(t *testing.T) {
++	switch runtime.GOOS {
++	case "dragonfly":
++		// TODO(jsing): Figure out why sendmsg is returning EINVAL.
++		t.Skip("skipping test on dragonfly")
++	case "solaris":
++		// TODO(aram): Figure out why ReadMsgUnix is returning empty message.
++		t.Skip("skipping test on solaris, see issue 7402")
++	}
++
++	testenv.MustHaveExec(t)
++
++	if os.Getenv("GO_WANT_HELPER_PROCESS") == "1" {
++		passFDChild()
++		return
++	}
++
++	tempDir, err := ioutil.TempDir("", "TestPassFD")
++	if err != nil {
++		t.Fatal(err)
++	}
++	defer os.RemoveAll(tempDir)
++
++	fds, err := syscall.Socketpair(syscall.AF_LOCAL, syscall.SOCK_STREAM, 0)
++	if err != nil {
++		t.Fatalf("Socketpair: %v", err)
++	}
++	defer syscall.Close(fds[0])
++	defer syscall.Close(fds[1])
++	writeFile := os.NewFile(uintptr(fds[0]), "child-writes")
++	readFile := os.NewFile(uintptr(fds[1]), "parent-reads")
++	defer writeFile.Close()
++	defer readFile.Close()
++
++	cmd := exec.Command(os.Args[0], "-test.run=^TestPassFD$", "--", tempDir)
++	cmd.Env = append(os.Environ(), "GO_WANT_HELPER_PROCESS=1")
++	cmd.ExtraFiles = []*os.File{writeFile}
++
++	out, err := cmd.CombinedOutput()
++	if len(out) > 0 || err != nil {
++		t.Fatalf("child process: %q, %v", out, err)
++	}
++
++	c, err := net.FileConn(readFile)
++	if err != nil {
++		t.Fatalf("FileConn: %v", err)
++	}
++	defer c.Close()
++
++	uc, ok := c.(*net.UnixConn)
++	if !ok {
++		t.Fatalf("unexpected FileConn type; expected UnixConn, got %T", c)
++	}
++
++	buf := make([]byte, 32) // expect 1 byte
++	oob := make([]byte, 32) // expect 24 bytes
++	closeUnix := time.AfterFunc(5*time.Second, func() {
++		t.Logf("timeout reading from unix socket")
++		uc.Close()
++	})
++	_, oobn, _, _, err := uc.ReadMsgUnix(buf, oob)
++	closeUnix.Stop()
++
++	scms, err := syscall.ParseSocketControlMessage(oob[:oobn])
++	if err != nil {
++		t.Fatalf("ParseSocketControlMessage: %v", err)
++	}
++	if len(scms) != 1 {
++		t.Fatalf("expected 1 SocketControlMessage; got scms = %#v", scms)
++	}
++	scm := scms[0]
++	gotFds, err := syscall.ParseUnixRights(&scm)
++	if err != nil {
++		t.Fatalf("syscall.ParseUnixRights: %v", err)
++	}
++	if len(gotFds) != 1 {
++		t.Fatalf("wanted 1 fd; got %#v", gotFds)
++	}
++
++	f := os.NewFile(uintptr(gotFds[0]), "fd-from-child")
++	defer f.Close()
++
++	got, err := ioutil.ReadAll(f)
++	want := "Hello from child process!\n"
++	if string(got) != want {
++		t.Errorf("child process ReadAll: %q, %v; want %q", got, err, want)
++	}
++}
++
++// passFDChild is the child process used by TestPassFD.
++func passFDChild() {
++	defer os.Exit(0)
++
++	// Look for our fd. It should be fd 3, but we work around an fd leak
++	// bug here (https://golang.org/issue/2603) to let it be elsewhere.
++	var uc *net.UnixConn
++	for fd := uintptr(3); fd <= 10; fd++ {
++		f := os.NewFile(fd, "unix-conn")
++		var ok bool
++		netc, _ := net.FileConn(f)
++		uc, ok = netc.(*net.UnixConn)
++		if ok {
++			break
++		}
++	}
++	if uc == nil {
++		fmt.Println("failed to find unix fd")
++		return
++	}
++
++	// Make a file f to send to our parent process on uc.
++	// We make it in tempDir, which our parent will clean up.
++	flag.Parse()
++	tempDir := flag.Arg(0)
++	f, err := ioutil.TempFile(tempDir, "")
++	if err != nil {
++		fmt.Printf("TempFile: %v", err)
++		return
++	}
++
++	f.Write([]byte("Hello from child process!\n"))
++	f.Seek(0, 0)
++
++	rights := syscall.UnixRights(int(f.Fd()))
++	dummyByte := []byte("x")
++	n, oobn, err := uc.WriteMsgUnix(dummyByte, rights, nil)
++	if err != nil {
++		fmt.Printf("WriteMsgUnix: %v", err)
++		return
++	}
++	if n != 1 || oobn != len(rights) {
++		fmt.Printf("WriteMsgUnix = %d, %d; want 1, %d", n, oobn, len(rights))
++		return
++	}
++}
++
++// TestUnixRightsRoundtrip tests that UnixRights, ParseSocketControlMessage,
++// and ParseUnixRights are able to successfully round-trip lists of file descriptors.
++func TestUnixRightsRoundtrip(t *testing.T) {
++	testCases := [...][][]int{
++		{{42}},
++		{{1, 2}},
++		{{3, 4, 5}},
++		{{}},
++		{{1, 2}, {3, 4, 5}, {}, {7}},
++	}
++	for _, testCase := range testCases {
++		b := []byte{}
++		var n int
++		for _, fds := range testCase {
++			// Last assignment to n wins
++			n = len(b) + syscall.CmsgLen(4*len(fds))
++			b = append(b, syscall.UnixRights(fds...)...)
++		}
++		// Truncate b
++		b = b[:n]
++
++		scms, err := syscall.ParseSocketControlMessage(b)
++		if err != nil {
++			t.Fatalf("ParseSocketControlMessage: %v", err)
++		}
++		if len(scms) != len(testCase) {
++			t.Fatalf("expected %v SocketControlMessage; got scms = %#v", len(testCase), scms)
++		}
++		for i, scm := range scms {
++			gotFds, err := syscall.ParseUnixRights(&scm)
++			if err != nil {
++				t.Fatalf("ParseUnixRights: %v", err)
++			}
++			wantFds := testCase[i]
++			if len(gotFds) != len(wantFds) {
++				t.Fatalf("expected %v fds, got %#v", len(wantFds), gotFds)
++			}
++			for j, fd := range gotFds {
++				if fd != wantFds[j] {
++					t.Fatalf("expected fd %v, got %v", wantFds[j], fd)
++				}
++			}
++		}
++	}
++}
++
++func TestRlimit(t *testing.T) {
++	var rlimit, zero syscall.Rlimit
++	err := syscall.Getrlimit(syscall.RLIMIT_NOFILE, &rlimit)
++	if err != nil {
++		t.Fatalf("Getrlimit: save failed: %v", err)
++	}
++	if zero == rlimit {
++		t.Fatalf("Getrlimit: save failed: got zero value %#v", rlimit)
++	}
++	set := rlimit
++	set.Cur = set.Max - 1
++	err = syscall.Setrlimit(syscall.RLIMIT_NOFILE, &set)
++	if err != nil {
++		t.Fatalf("Setrlimit: set failed: %#v %v", set, err)
++	}
++	var get syscall.Rlimit
++	err = syscall.Getrlimit(syscall.RLIMIT_NOFILE, &get)
++	if err != nil {
++		t.Fatalf("Getrlimit: get failed: %v", err)
++	}
++	set = rlimit
++	set.Cur = set.Max - 1
++	if set != get {
++		// Seems like Darwin requires some privilege to
++		// increase the soft limit of rlimit sandbox, though
++		// Setrlimit never reports an error.
++		switch runtime.GOOS {
++		case "darwin":
++		default:
++			t.Fatalf("Rlimit: change failed: wanted %#v got %#v", set, get)
++		}
++	}
++	err = syscall.Setrlimit(syscall.RLIMIT_NOFILE, &rlimit)
++	if err != nil {
++		t.Fatalf("Setrlimit: restore failed: %#v %v", rlimit, err)
++	}
++}
++
++func TestSeekFailure(t *testing.T) {
++	_, err := syscall.Seek(-1, 0, 0)
++	if err == nil {
++		t.Fatalf("Seek(-1, 0, 0) did not fail")
++	}
++	str := err.Error() // used to crash on Linux
++	t.Logf("Seek: %v", str)
++	if str == "" {
++		t.Fatalf("Seek(-1, 0, 0) return error with empty message")
++	}
++}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_go_syscall_wait.c.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_go_syscall_wait.c.diff
@@ -0,0 +1,14 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/wait.c
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/wait.c
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/wait.c
+@@ -8,6 +8,9 @@
+    OS-independent.  */
+ 
+ #include <stdint.h>
++#ifndef WCONTINUED
++#define WCONTINUED 0
++#endif
+ #include <sys/wait.h>
+ 
+ #include "runtime.h"
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_mksysinfo.sh.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_mksysinfo.sh.diff
@@ -0,0 +1,42 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/mksysinfo.sh
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/mksysinfo.sh
++++ gcc-6-6.2.1-4.1/src/libgo/mksysinfo.sh
+@@ -304,6 +304,13 @@ echo '#include <errno.h>' | ${CC} -x c -
+   egrep '#define E[A-Z0-9_]+ ' | \
+   sed -e 's/^#define \(E[A-Z0-9_]*\) .*$/const \1 = Errno(_\1)/' >> ${OUT}
+ 
++# Special treatment of EWOULDBLOCK for GNU/Hurd
++# /usr/include/bits/errno.h: #define EWOULDBLOCK EAGAIN
++if egrep 'define EWOULDBLOCK EAGAIN' gen-sysinfo.go > /dev/null 2>&1; then
++  egrep '^const EWOULDBLOCK = Errno(_EWOULDBLOCK)' ${OUT} | \
++    sed -i -e 's/_EWOULDBLOCK/_EAGAIN/' ${OUT}
++fi
++
+ # The O_xxx flags.
+ egrep '^const _(O|F|FD)_' gen-sysinfo.go | \
+   sed -e 's/^\(const \)_\([^= ]*\)\(.*\)$/\1\2 = _\2/' >> ${OUT}
+@@ -319,6 +326,11 @@ if ! grep '^const F_DUPFD_CLOEXEC' ${OUT
+   echo "const F_DUPFD_CLOEXEC = 0" >> ${OUT}
+ fi
+ 
++# Special treatment of SYS_IOCTL for GNU/Hurd
++if ! grep '^const SYS_IOCTL' ${OUT} > /dev/null 2>&1; then
++  echo "const SYS_IOCTL = 0" >> ${OUT}
++fi
++
+ # These flags can be lost on i386 GNU/Linux when using
+ # -D_FILE_OFFSET_BITS=64, because we see "#define F_SETLK F_SETLK64"
+ # before we see the definition of F_SETLK64.
+@@ -676,6 +688,11 @@ grep '^type _tms ' gen-sysinfo.go | \
+ 
+ # The stat type.
+ # Prefer largefile variant if available.
++# Special treatment of st_dev for GNU/Hurd
++# /usr/include/i386-gnu/bits/stat.h: #define st_dev st_fsid
++if grep 'define st_dev st_fsid' gen-sysinfo.go > /dev/null 2>&1; then
++  sed -i -e 's/; st_fsid/; st_dev/' gen-sysinfo.go
++fi
+ stat=`grep '^type _stat64 ' gen-sysinfo.go || true`
+ if test "$stat" != ""; then
+   grep '^type _stat64 ' gen-sysinfo.go
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_runtime_getncpu-gnu.c.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_runtime_getncpu-gnu.c.diff
@@ -0,0 +1,21 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/runtime/getncpu-gnu.c
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/runtime/getncpu-gnu.c
+@@ -0,0 +1,16 @@
++// Copyright 2012 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++#include <unistd.h>
++
++#include "runtime.h"
++#include "defs.h"
++
++int32
++getproccount(void)
++{
++	int32 n;
++	n = (int32)sysconf(_SC_NPROCESSORS_ONLN);
++	return n > 1 ? n : 1;
++}
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_runtime_go-caller.c.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_runtime_go-caller.c.diff
@@ -0,0 +1,14 @@
+Index: gcc/src/libgo/runtime/go-caller.c
+===================================================================
+--- gcc/src/libgo/runtime/go-caller.c	(révision 235086)
++++ gcc/src/libgo/runtime/go-caller.c	(copie de travail)
+@@ -93,7 +93,7 @@
+ 	 argv[0] (http://gcc.gnu.org/PR61895).  It would be nice to
+ 	 have a better check for whether this file is the real
+ 	 executable.  */
+-      if (stat (filename, &s) < 0 || s.st_size < 1024)
++      if (filename != NULL && (stat (filename, &s) < 0 || s.st_size < 1024))
+ 	filename = NULL;
+ 
+       back_state = backtrace_create_state (filename, 1, error_callback, NULL);
+
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_runtime_netpoll.goc.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_runtime_netpoll.goc.diff
@@ -0,0 +1,31 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll.goc
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/runtime/netpoll.goc
++++ gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll.goc
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd gnu linux nacl netbsd openbsd solaris windows
+ 
+ package net
+ 
+@@ -98,7 +98,7 @@ func runtime_pollServerInit() {
+ 	runtime_netpollinit();
+ }
+ 
+-func runtime_pollOpen(fd uintptr) (pd *PollDesc, errno int) {
++func runtime_pollOpen(fd uintptr) (pd *PollDesc, errno1 int) {
+ 	pd = allocPollDesc();
+ 	runtime_lock(pd);
+ 	if(pd->wg != nil && pd->wg != READY)
+@@ -114,7 +114,7 @@ func runtime_pollOpen(fd uintptr) (pd *P
+ 	pd->wd = 0;
+ 	runtime_unlock(pd);
+ 
+-	errno = runtime_netpollopen(fd, pd);
++	errno1 = runtime_netpollopen(fd, pd);
+ }
+ 
+ func runtime_pollClose(pd *PollDesc) {
--- gcc-6-6.3.0.orig/debian/patches/src_libgo_testsuite_gotest.diff
+++ gcc-6-6.3.0/debian/patches/src_libgo_testsuite_gotest.diff
@@ -0,0 +1,17 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/testsuite/gotest
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/testsuite/gotest
++++ gcc-6-6.2.1-4.1/src/libgo/testsuite/gotest
+@@ -618,7 +618,11 @@ xno)
+ 		wait $pid
+ 		status=$?
+ 		if ! test -f gotest-timeout; then
+-		    sleeppid=`ps -o pid,ppid,comm | grep " $alarmpid " | grep sleep | sed -e 's/ *\([0-9]*\) .*$/\1/'`
++		    if test "$goos" = "gnu"; then
++			sleeppid=`ps -o pid,ppid | grep " $alarmpid " | grep sleep | sed -e 's/ *\([0-9]*\) .*$/\1/'`
++		    else
++			sleeppid=`ps -o pid,ppid,comm | grep " $alarmpid " | grep sleep | sed -e 's/ *\([0-9]*\) .*$/\1/'`
++		    fi
+ 		    kill $alarmpid
+ 		    wait $alarmpid
+ 		    if test "$sleeppid" != ""; then
--- gcc-6-6.3.0.orig/debian/patches/svn-class-updates.diff
+++ gcc-6-6.3.0/debian/patches/svn-class-updates.diff
@@ -0,0 +1,27 @@
+# DP: updated class files from the 4.8 branch upto yyyymmdd.
+
+dir=gcc-4_8-branch
+dir=/scratch/packages/gcc/svn/gcc-4_8-branch
+tag=gcc_4_8_0_release
+branch=gcc-4_8-branch
+
+tmplist=files$$
+
+svn diff --summarize \
+        svn://gcc.gnu.org/svn/gcc/tags/$tag \
+        svn://gcc.gnu.org/svn/gcc/branches/$branch \
+    | grep '\.class$' > $tmplist
+
+sed -n '/^[AM].*\.class$/s,.*/'$tag'/\(.*\),\1,p' $tmplist \
+    > neworchanged.list
+sed -n '/^[D].*\.class$/s,.*/'$tag'/\(.*\),\1,p' $tmplist \
+    > removed.list
+sed -n '/^[^ADM].*\.class$/s,.*/'$tag'/\(.*\),\1,p' $tmplist \
+    > unknown.list
+
+echo "new or changed: $(wc -l neworchanged.list | cut '-d ' -f1), removed $(wc -l removed.list | cut '-d ' -f1): , unknown: $(wc -l unknown.list | cut '-d ' -f1)"
+tar -c -J -f java-class-files.tar.xz -C $dir -T neworchanged.list
+uuencode java-class-files.tar.xz java-class-files.tar.xz > java-class-files.tar.xz.uue
+
+rm -f $tmplist neworchanged.list removed.list unknown.list
+
--- gcc-6-6.3.0.orig/debian/patches/svn-doc-updates.diff
+++ gcc-6-6.3.0/debian/patches/svn-doc-updates.diff
@@ -0,0 +1,6 @@
+# DP: updates from the 6 branch upto 2016xxyy (documentation).
+
+svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_6_1_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-5-branch \
+	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
+	| awk '/^Index:.*\.texi/ {skip=0; print; next} /^Index:/ {skip=1; next} skip==0'
+
--- gcc-6-6.3.0.orig/debian/patches/svn-updates.diff
+++ gcc-6-6.3.0/debian/patches/svn-updates.diff
@@ -0,0 +1,57498 @@
+# DP: updates from the 6 branch upto 20170316 (r246188).
+
+last_update()
+{
+	cat > ${dir}LAST_UPDATED <EOF
+Thu Mar 16 10:56:04 CET 2017
+Thu Mar 16 09:56:04 UTC 2017 (revision 246188)
+EOF
+}
+
+LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_6_3_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-6-branch \
+	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
+	| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'
+
+Index: libgomp/ChangeLog
+===================================================================
+--- a/src/libgomp/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/libgomp/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,16 @@
++2017-01-10  Thomas Schwinge  <thomas@codesourcery.com>
++
++	Backport trunk r239125:
++	2016-08-04  Thomas Schwinge  <thomas@codesourcery.com>
++
++	* testsuite/libgomp.oacc-c-c++-common/crash-1.c: Make it a "link"
++	test, and don't hardcode -O0.
++
++	Backport trunk r239086:
++	2016-08-03  Nathan Sidwell  <nathan@codesourcery.com>
++
++	* testsuite/libgomp.oacc-c-c++-common/crash-1.c: New.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: libgomp/testsuite/libgomp.oacc-c-c++-common/crash-1.c
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.oacc-c-c++-common/crash-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/libgomp/testsuite/libgomp.oacc-c-c++-common/crash-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,27 @@
++/* { dg-do link } */
++
++/* For -O0, ICEd in nvptx backend due to unexpected frame size.  */
++#pragma acc routine worker
++void
++worker_matmul (int *c, int i)
++{
++  int j;
++
++#pragma acc loop
++  for (j = 0; j < 4; j++)
++    c[j] = j;
++}
++
++
++int
++main ()
++{
++  int c[4];
++
++#pragma acc parallel 
++  {
++    worker_matmul (c, 0);
++  }
++  
++  return 0;
++}
+Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cc
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cc	(.../branches/gcc-6-branch)
+@@ -21,11 +21,6 @@
+ #ifdef _FILE_OFFSET_BITS
+ #undef _FILE_OFFSET_BITS
+ #endif
+-#if SANITIZER_FREEBSD
+-#define _WANT_RTENTRY
+-#include <sys/param.h>
+-#include <sys/socketvar.h>
+-#endif
+ #include <arpa/inet.h>
+ #include <dirent.h>
+ #include <errno.h>
+@@ -411,6 +406,7 @@
+   unsigned struct_input_absinfo_sz = sizeof(struct input_absinfo);
+   unsigned struct_input_id_sz = sizeof(struct input_id);
+   unsigned struct_mtpos_sz = sizeof(struct mtpos);
++  unsigned struct_rtentry_sz = sizeof(struct rtentry);
+   unsigned struct_termio_sz = sizeof(struct termio);
+   unsigned struct_vt_consize_sz = sizeof(struct vt_consize);
+   unsigned struct_vt_sizes_sz = sizeof(struct vt_sizes);
+@@ -430,7 +426,6 @@
+   unsigned struct_midi_info_sz = sizeof(struct midi_info);
+   unsigned struct_mtget_sz = sizeof(struct mtget);
+   unsigned struct_mtop_sz = sizeof(struct mtop);
+-  unsigned struct_rtentry_sz = sizeof(struct rtentry);
+   unsigned struct_sbi_instrument_sz = sizeof(struct sbi_instrument);
+   unsigned struct_seq_event_rec_sz = sizeof(struct seq_event_rec);
+   unsigned struct_synth_info_sz = sizeof(struct synth_info);
+Index: libsanitizer/ChangeLog
+===================================================================
+--- a/src/libsanitizer/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/libsanitizer/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,12 @@
++2017-02-17  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	Backported from mainline
++	2017-02-16  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	PR sanitizer/79562
++	* sanitizer_common/sanitizer_platform_limits_posix.cc: Cherry-pick
++	upstream r294806.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: libstdc++-v3/configure
+===================================================================
+--- a/src/libstdc++-v3/configure	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/configure	(.../branches/gcc-6-branch)
+@@ -18385,6 +18385,7 @@
+ 
+           cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
++#define _GLIBCXX_INCLUDE_NEXT_C_HEADERS
+ #include <math.h>
+              #undef isnan
+              namespace std {
+Index: libstdc++-v3/python/libstdcxx/v6/xmethods.py
+===================================================================
+--- a/src/libstdc++-v3/python/libstdcxx/v6/xmethods.py	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/python/libstdcxx/v6/xmethods.py	(.../branches/gcc-6-branch)
+@@ -565,8 +565,14 @@
+ # Xmethods for std::unique_ptr
+ 
+ class UniquePtrGetWorker(gdb.xmethod.XMethodWorker):
++    "Implements std::unique_ptr<T>::get() and std::unique_ptr<T>::operator->()"
++
+     def __init__(self, elem_type):
+-        self._elem_type = elem_type
++        self._is_array = elem_type.code == gdb.TYPE_CODE_ARRAY
++        if self._is_array:
++            self._elem_type = elem_type.target()
++        else:
++            self._elem_type = elem_type
+ 
+     def get_arg_types(self):
+         return None
+@@ -574,10 +580,16 @@
+     def get_result_type(self, obj):
+         return self._elem_type.pointer()
+ 
++    def _supports(self, method_name):
++        "operator-> is not supported for unique_ptr<T[]>"
++        return method_name == 'get' or not self._is_array
++
+     def __call__(self, obj):
+         return obj['_M_t']['_M_head_impl']
+ 
+ class UniquePtrDerefWorker(UniquePtrGetWorker):
++    "Implements std::unique_ptr<T>::operator*()"
++
+     def __init__(self, elem_type):
+         UniquePtrGetWorker.__init__(self, elem_type)
+ 
+@@ -584,9 +596,32 @@
+     def get_result_type(self, obj):
+         return self._elem_type
+ 
++    def _supports(self, method_name):
++        "operator* is not supported for unique_ptr<T[]>"
++        return not self._is_array
++
+     def __call__(self, obj):
+         return UniquePtrGetWorker.__call__(self, obj).dereference()
+ 
++class UniquePtrSubscriptWorker(UniquePtrGetWorker):
++    "Implements std::unique_ptr<T>::operator[](size_t)"
++
++    def __init__(self, elem_type):
++        UniquePtrGetWorker.__init__(self, elem_type)
++
++    def get_arg_types(self):
++        return get_std_size_type()
++
++    def get_result_type(self, obj, index):
++        return self._elem_type
++
++    def _supports(self, method_name):
++        "operator[] is only supported for unique_ptr<T[]>"
++        return self._is_array
++
++    def __call__(self, obj, index):
++        return UniquePtrGetWorker.__call__(self, obj)[index]
++
+ class UniquePtrMethodsMatcher(gdb.xmethod.XMethodMatcher):
+     def __init__(self):
+         gdb.xmethod.XMethodMatcher.__init__(self,
+@@ -595,6 +630,7 @@
+             'get': LibStdCxxXMethod('get', UniquePtrGetWorker),
+             'operator->': LibStdCxxXMethod('operator->', UniquePtrGetWorker),
+             'operator*': LibStdCxxXMethod('operator*', UniquePtrDerefWorker),
++            'operator[]': LibStdCxxXMethod('operator[]', UniquePtrSubscriptWorker),
+         }
+         self.methods = [self._method_dict[m] for m in self._method_dict]
+ 
+@@ -604,6 +640,112 @@
+         method = self._method_dict.get(method_name)
+         if method is None or not method.enabled:
+             return None
++        worker = method.worker_class(class_type.template_argument(0))
++        if worker._supports(method_name):
++            return worker
++        return None
++
++# Xmethods for std::shared_ptr
++
++class SharedPtrGetWorker(gdb.xmethod.XMethodWorker):
++    "Implements std::shared_ptr<T>::get() and std::shared_ptr<T>::operator->()"
++
++    def __init__(self, elem_type):
++        self._is_array = elem_type.code == gdb.TYPE_CODE_ARRAY
++        if self._is_array:
++            self._elem_type = elem_type.target()
++        else:
++            self._elem_type = elem_type
++
++    def get_arg_types(self):
++        return None
++
++    def get_result_type(self, obj):
++        return self._elem_type.pointer()
++
++    def __call__(self, obj):
++        return obj['_M_ptr']
++
++class SharedPtrDerefWorker(SharedPtrGetWorker):
++    "Implements std::shared_ptr<T>::operator*()"
++
++    def __init__(self, elem_type):
++        SharedPtrGetWorker.__init__(self, elem_type)
++
++    def get_result_type(self, obj):
++        return self._elem_type
++
++    def __call__(self, obj):
++        return SharedPtrGetWorker.__call__(self, obj).dereference()
++
++class SharedPtrSubscriptWorker(SharedPtrGetWorker):
++    "Implements std::shared_ptr<T>::operator[](size_t)"
++
++    def __init__(self, elem_type):
++        SharedPtrGetWorker.__init__(self, elem_type)
++
++    def get_arg_types(self):
++        return get_std_size_type()
++
++    def get_result_type(self, obj, index):
++        return self._elem_type
++
++    def __call__(self, obj, index):
++        # Check bounds if _elem_type is an array of known bound
++        m = re.match('.*\[(\d+)]$', str(self._elem_type))
++        if m and index >= int(m.group(1)):
++            raise IndexError('shared_ptr<%s> index "%d" should not be >= %d.' %
++                             (self._elem_type, int(index), int(m.group(1))))
++        return SharedPtrGetWorker.__call__(self, obj)[index]
++
++class SharedPtrUseCountWorker(gdb.xmethod.XMethodWorker):
++    "Implements std::shared_ptr<T>::use_count()"
++
++    def __init__(self, elem_type):
++        SharedPtrUseCountWorker.__init__(self, elem_type)
++
++    def get_arg_types(self):
++        return None
++
++    def get_result_type(self, obj):
++        return gdb.lookup_type('long')
++
++    def __call__(self, obj):
++        refcounts = ['_M_refcount']['_M_pi']
++        return refcounts['_M_use_count'] if refcounts else 0
++
++class SharedPtrUniqueWorker(SharedPtrUseCountWorker):
++    "Implements std::shared_ptr<T>::unique()"
++
++    def __init__(self, elem_type):
++        SharedPtrUseCountWorker.__init__(self, elem_type)
++
++    def get_result_type(self, obj):
++        return gdb.lookup_type('bool')
++
++    def __call__(self, obj):
++        return SharedPtrUseCountWorker.__call__(self, obj) == 1
++
++class SharedPtrMethodsMatcher(gdb.xmethod.XMethodMatcher):
++    def __init__(self):
++        gdb.xmethod.XMethodMatcher.__init__(self,
++                                            matcher_name_prefix + 'shared_ptr')
++        self._method_dict = {
++            'get': LibStdCxxXMethod('get', SharedPtrGetWorker),
++            'operator->': LibStdCxxXMethod('operator->', SharedPtrGetWorker),
++            'operator*': LibStdCxxXMethod('operator*', SharedPtrDerefWorker),
++            'operator[]': LibStdCxxXMethod('operator[]', SharedPtrSubscriptWorker),
++            'use_count': LibStdCxxXMethod('use_count', SharedPtrUseCountWorker),
++            'unique': LibStdCxxXMethod('unique', SharedPtrUniqueWorker),
++        }
++        self.methods = [self._method_dict[m] for m in self._method_dict]
++
++    def match(self, class_type, method_name):
++        if not re.match('^std::shared_ptr<.*>$', class_type.tag):
++            return None
++        method = self._method_dict.get(method_name)
++        if method is None or not method.enabled:
++            return None
+         return method.worker_class(class_type.template_argument(0))
+ 
+ def register_libstdcxx_xmethods(locus):
+@@ -629,3 +771,4 @@
+     gdb.xmethod.register_xmethod_matcher(
+         locus, AssociativeContainerMethodsMatcher('unordered_multimap'))
+     gdb.xmethod.register_xmethod_matcher(locus, UniquePtrMethodsMatcher())
++    gdb.xmethod.register_xmethod_matcher(locus, SharedPtrMethodsMatcher())
+Index: libstdc++-v3/python/libstdcxx/v6/printers.py
+===================================================================
+--- a/src/libstdc++-v3/python/libstdcxx/v6/printers.py	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/python/libstdcxx/v6/printers.py	(.../branches/gcc-6-branch)
+@@ -127,8 +127,8 @@
+ 
+     def to_string (self):
+         v = self.val['_M_t']['_M_head_impl']
+-        return ('std::unique_ptr<%s> containing %s' % (str(v.type.target()),
+-                                                       str(v)))
++        return 'std::unique_ptr<%s> containing %s' % (str(v.type.target()),
++                                                      str(v))
+ 
+ def get_value_from_list_node(node):
+     """Returns the value held in an _List_node<_Val>"""
+@@ -191,10 +191,12 @@
+         self.typename = typename
+ 
+     def to_string(self):
++        if not self.val['_M_node']:
++            return 'non-dereferenceable iterator for std::list'
+         nodetype = find_type(self.val.type, '_Node')
+         nodetype = nodetype.strip_typedefs().pointer()
+         node = self.val['_M_node'].cast(nodetype).dereference()
+-        return get_value_from_list_node(node)
++        return str(get_value_from_list_node(node))
+ 
+ class StdSlistPrinter:
+     "Print a __gnu_cxx::slist"
+@@ -237,9 +239,11 @@
+         self.val = val
+ 
+     def to_string(self):
++        if not self.val['_M_node']:
++            return 'non-dereferenceable iterator for __gnu_cxx::slist'
+         nodetype = find_type(self.val.type, '_Node')
+         nodetype = nodetype.strip_typedefs().pointer()
+-        return self.val['_M_node'].cast(nodetype).dereference()['_M_data']
++        return str(self.val['_M_node'].cast(nodetype).dereference()['_M_data'])
+ 
+ class StdVectorPrinter:
+     "Print a std::vector"
+@@ -324,7 +328,9 @@
+         self.val = val
+ 
+     def to_string(self):
+-        return self.val['_M_current'].dereference()
++        if not self.val['_M_current']:
++            return 'non-dereferenceable iterator for std::vector'
++        return str(self.val['_M_current'].dereference())
+ 
+ class StdTuplePrinter:
+     "Print a std::tuple"
+@@ -419,6 +425,11 @@
+         return None
+ 
+ class RbtreeIterator(Iterator):
++    """
++    Turn an RB-tree-based container (std::map, std::set etc.) into
++    a Python iterable object.
++    """
++
+     def __init__(self, rbtree):
+         self.size = rbtree['_M_t']['_M_impl']['_M_node_count']
+         self.node = rbtree['_M_t']['_M_impl']['_M_header']['_M_left']
+@@ -472,7 +483,7 @@
+ # std::map::iterator), and has nothing to do with the RbtreeIterator
+ # class above.
+ class StdRbtreeIteratorPrinter:
+-    "Print std::map::iterator"
++    "Print std::map::iterator, std::set::iterator, etc."
+ 
+     def __init__ (self, typename, val):
+         self.val = val
+@@ -481,8 +492,10 @@
+         self.link_type = nodetype.strip_typedefs().pointer()
+ 
+     def to_string (self):
++        if not self.val['_M_node']:
++            return 'non-dereferenceable iterator for associative container'
+         node = self.val['_M_node'].cast(self.link_type).dereference()
+-        return get_value_from_Rb_tree_node(node)
++        return str(get_value_from_Rb_tree_node(node))
+ 
+ class StdDebugIteratorPrinter:
+     "Print a debug enabled version of an iterator"
+@@ -494,7 +507,7 @@
+     # and return the wrapped iterator value.
+     def to_string (self):
+         itype = self.val.type.template_argument(0)
+-        return self.val.cast(itype)
++        return str(self.val.cast(itype))
+ 
+ class StdMapPrinter:
+     "Print a std::map or std::multimap"
+@@ -687,7 +700,9 @@
+         self.val = val
+ 
+     def to_string(self):
+-        return self.val['_M_cur'].dereference()
++        if not self.val['_M_cur']:
++            return 'non-dereferenceable iterator for std::deque'
++        return str(self.val['_M_cur'].dereference())
+ 
+ class StdStringPrinter:
+     "Print a std::basic_string of some kind"
+@@ -873,8 +888,8 @@
+ 
+     def to_string(self):
+         if self.val['_M_impl']['_M_head']['_M_next'] == 0:
+-            return 'empty %s' % (self.typename)
+-        return '%s' % (self.typename)
++            return 'empty %s' % self.typename
++        return '%s' % self.typename
+ 
+ class SingleObjContainerPrinter(object):
+     "Base class for printers of containers of single objects"
+@@ -975,9 +990,10 @@
+ 
+     def to_string (self):
+         if self.contained_value is None:
+-            return self.typename + " [no contained value]"
++            return "%s [no contained value]" % self.typename
+         if hasattr (self.visualizer, 'children'):
+-            return self.typename + " containing " + self.visualizer.to_string ()
++            return "%s containing %s" % (self.typename,
++                                         self.visualizer.to_string())
+         return self.typename
+ 
+ class StdExpStringViewPrinter:
+@@ -1133,7 +1149,8 @@
+ libstdcxx_printer = None
+ 
+ class TemplateTypePrinter(object):
+-    r"""A type printer for class templates.
++    r"""
++    A type printer for class templates.
+ 
+     Recognizes type names that match a regular expression.
+     Replaces them with a formatted string which can use replacement field
+Index: libstdc++-v3/src/c++11/cxx11-shim_facets.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/cxx11-shim_facets.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/src/c++11/cxx11-shim_facets.cc	(.../branches/gcc-6-branch)
+@@ -226,8 +226,14 @@
+ 
+   namespace // unnamed
+   {
++    struct __shim_accessor : facet
++    {
++      using facet::__shim;  // Redeclare protected member as public.
++    };
++    using __shim = __shim_accessor::__shim;
++
+     template<typename _CharT>
+-      struct numpunct_shim : std::numpunct<_CharT>, facet::__shim
++      struct numpunct_shim : std::numpunct<_CharT>, __shim
+       {
+ 	typedef typename numpunct<_CharT>::__cache_type __cache_type;
+ 
+@@ -251,7 +257,7 @@
+       };
+ 
+     template<typename _CharT>
+-      struct collate_shim : std::collate<_CharT>, facet::__shim
++      struct collate_shim : std::collate<_CharT>, __shim
+       {
+ 	typedef basic_string<_CharT>	string_type;
+ 
+@@ -276,7 +282,7 @@
+       };
+ 
+     template<typename _CharT>
+-      struct time_get_shim : std::time_get<_CharT>, facet::__shim
++      struct time_get_shim : std::time_get<_CharT>, __shim
+       {
+ 	typedef typename std::time_get<_CharT>::iter_type iter_type;
+ 	typedef typename std::time_get<_CharT>::char_type char_type;
+@@ -330,7 +336,7 @@
+       };
+ 
+     template<typename _CharT, bool _Intl>
+-      struct moneypunct_shim : std::moneypunct<_CharT, _Intl>, facet::__shim
++      struct moneypunct_shim : std::moneypunct<_CharT, _Intl>, __shim
+       {
+ 	typedef typename moneypunct<_CharT, _Intl>::__cache_type __cache_type;
+ 
+@@ -357,7 +363,7 @@
+       };
+ 
+     template<typename _CharT>
+-      struct money_get_shim : std::money_get<_CharT>, facet::__shim
++      struct money_get_shim : std::money_get<_CharT>, __shim
+       {
+ 	typedef typename std::money_get<_CharT>::iter_type iter_type;
+ 	typedef typename std::money_get<_CharT>::char_type char_type;
+@@ -398,7 +404,7 @@
+       };
+ 
+     template<typename _CharT>
+-      struct money_put_shim : std::money_put<_CharT>, facet::__shim
++      struct money_put_shim : std::money_put<_CharT>, __shim
+       {
+ 	typedef typename std::money_put<_CharT>::iter_type iter_type;
+ 	typedef typename std::money_put<_CharT>::char_type char_type;
+@@ -427,7 +433,7 @@
+       };
+ 
+     template<typename _CharT>
+-      struct messages_shim : std::messages<_CharT>, facet::__shim
++      struct messages_shim : std::messages<_CharT>, __shim
+       {
+ 	typedef messages_base::catalog  catalog;
+ 	typedef basic_string<_CharT>	string_type;
+Index: libstdc++-v3/doc/xml/faq.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/faq.xml	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/doc/xml/faq.xml	(.../branches/gcc-6-branch)
+@@ -1230,7 +1230,7 @@
+     details than for C, and most CPU designers (for good reasons elaborated
+     below) have not stepped up to publish C++ ABIs.  Such an ABI has been
+     defined for the Itanium architecture (see
+-    <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://www.codesourcery.com/cxx-abi/">C++
++    <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://mentorembedded.github.io/cxx-abi/">C++
+     ABI for Itanium</link>) and that is used by G++ and other compilers
+     as the de facto standard ABI on many common architectures (including x86).
+     G++ can also use the ARM architecture's EABI, for embedded
+Index: libstdc++-v3/doc/xml/manual/abi.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/manual/abi.xml	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/doc/xml/manual/abi.xml	(.../branches/gcc-6-branch)
+@@ -42,7 +42,7 @@
+   virtual functions, etc. These details are defined as the compiler
+   Application Binary Interface, or ABI. The GNU C++ compiler uses an
+   industry-standard C++ ABI starting with version 3. Details can be
+-  found in the <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://mentorembedded.github.com/cxx-abi/abi.html">ABI
++  found in the <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://mentorembedded.github.io/cxx-abi/abi.html">ABI
+   specification</link>.
+ </para>
+ 
+@@ -736,7 +736,7 @@
+ the way the compiler deals with this class in by-value return
+ statements or parameters: instead of passing instances of this
+ class in registers, the compiler will be forced to use memory. See the
+-section on <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://mentorembedded.github.com/cxx-abi/abi.html#calls">Function
++section on <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://mentorembedded.github.io/cxx-abi/abi.html#calls">Function
+ Calling Conventions and APIs</link>
+  of the C++ ABI documentation for further details.
+ </para></listitem>
+@@ -1094,7 +1094,7 @@
+     <biblioentry xml:id="biblio.cxxabi">
+       <title>
+ 	<link xmlns:xlink="http://www.w3.org/1999/xlink"
+-	      xlink:href="http://www.codesourcery.com/cxx-abi/">
++	      xlink:href="http://mentorembedded.github.io/cxx-abi/">
+ 	  C++ ABI Summary
+ 	</link>
+       </title>
+Index: libstdc++-v3/include/std/tuple
+===================================================================
+--- a/src/libstdc++-v3/include/std/tuple	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/std/tuple	(.../branches/gcc-6-branch)
+@@ -923,7 +923,9 @@
+         enable_if<_TMC::template
+                     _MoveConstructibleTuple<_U1, _U2>()
+                   && _TMC::template
+-                    _ImplicitlyMoveConvertibleTuple<_U1, _U2>(),
++                    _ImplicitlyMoveConvertibleTuple<_U1, _U2>()
++	          && !is_same<typename decay<_U1>::type,
++			      allocator_arg_t>::value,
+ 	bool>::type = true>
+         constexpr tuple(_U1&& __a1, _U2&& __a2)
+ 	: _Inherited(std::forward<_U1>(__a1), std::forward<_U2>(__a2)) { }
+@@ -932,7 +934,9 @@
+         enable_if<_TMC::template
+                     _MoveConstructibleTuple<_U1, _U2>()
+                   && !_TMC::template
+-                    _ImplicitlyMoveConvertibleTuple<_U1, _U2>(),
++                    _ImplicitlyMoveConvertibleTuple<_U1, _U2>()
++	          && !is_same<typename decay<_U1>::type,
++			      allocator_arg_t>::value,
+ 	bool>::type = false>
+         explicit constexpr tuple(_U1&& __a1, _U2&& __a2)
+ 	: _Inherited(std::forward<_U1>(__a1), std::forward<_U2>(__a2)) { }
+Index: libstdc++-v3/include/std/thread
+===================================================================
+--- a/src/libstdc++-v3/include/std/thread	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/std/thread	(.../branches/gcc-6-branch)
+@@ -119,6 +119,7 @@
+     // 2097.  packaged_task constructors should be constrained
+     thread(thread&) = delete;
+     thread(const thread&) = delete;
++    thread(const thread&&) = delete;
+ 
+     thread(thread&& __t) noexcept
+     { swap(__t); }
+Index: libstdc++-v3/include/std/type_traits
+===================================================================
+--- a/src/libstdc++-v3/include/std/type_traits	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/std/type_traits	(.../branches/gcc-6-branch)
+@@ -2576,12 +2576,6 @@
+     using __detected_or_t
+       = typename __detected_or<_Default, _Op, _Args...>::type;
+ 
+-  // _Op<_Args...> if that is a valid type, otherwise _Default<_Args...>.
+-  template<template<typename...> class _Default,
+-	   template<typename...> class _Op, typename... _Args>
+-    using __detected_or_t_ =
+-      __detected_or_t<_Default<_Args...>, _Op, _Args...>;
+-
+   /// @} group metaprogramming
+ 
+   /**
+Index: libstdc++-v3/include/std/memory
+===================================================================
+--- a/src/libstdc++-v3/include/std/memory	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/std/memory	(.../branches/gcc-6-branch)
+@@ -133,9 +133,9 @@
+ inline void
+ declare_reachable(void*) { }
+ 
+-template <class T>
+-  inline T*
+-  undeclare_reachable(T* __p) { return __p; }
++template <typename _Tp>
++  inline _Tp*
++  undeclare_reachable(_Tp* __p) { return __p; }
+ 
+ inline void
+ declare_no_pointers(char*, size_t) { }
+Index: libstdc++-v3/include/std/atomic
+===================================================================
+--- a/src/libstdc++-v3/include/std/atomic	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/std/atomic	(.../branches/gcc-6-branch)
+@@ -230,35 +230,39 @@
+ 
+       _Tp
+       load(memory_order __m = memory_order_seq_cst) const noexcept
+-      { 
+-        _Tp tmp;
+-	__atomic_load(&_M_i, &tmp, __m);
+-	return tmp;
++      {
++	alignas(_Tp) unsigned char __buf[sizeof(_Tp)];
++	_Tp* __ptr = reinterpret_cast<_Tp*>(__buf);
++	__atomic_load(&_M_i, __ptr, __m);
++	return *__ptr;
+       }
+ 
+       _Tp
+       load(memory_order __m = memory_order_seq_cst) const volatile noexcept
+-      { 
+-        _Tp tmp;
+-	__atomic_load(&_M_i, &tmp, __m);
+-	return tmp;
++      {
++        alignas(_Tp) unsigned char __buf[sizeof(_Tp)];
++	_Tp* __ptr = reinterpret_cast<_Tp*>(__buf);
++	__atomic_load(&_M_i, __ptr, __m);
++	return *__ptr;
+       }
+ 
+       _Tp
+       exchange(_Tp __i, memory_order __m = memory_order_seq_cst) noexcept
+-      { 
+-        _Tp tmp;
+-	__atomic_exchange(&_M_i, &__i, &tmp, __m);
+-	return tmp;
++      {
++        alignas(_Tp) unsigned char __buf[sizeof(_Tp)];
++	_Tp* __ptr = reinterpret_cast<_Tp*>(__buf);
++	__atomic_exchange(&_M_i, &__i, __ptr, __m);
++	return *__ptr;
+       }
+ 
+       _Tp
+       exchange(_Tp __i, 
+ 	       memory_order __m = memory_order_seq_cst) volatile noexcept
+-      { 
+-        _Tp tmp;
+-	__atomic_exchange(&_M_i, &__i, &tmp, __m);
+-	return tmp;
++      {
++        alignas(_Tp) unsigned char __buf[sizeof(_Tp)];
++	_Tp* __ptr = reinterpret_cast<_Tp*>(__buf);
++	__atomic_exchange(&_M_i, &__i, __ptr, __m);
++	return *__ptr;
+       }
+ 
+       bool
+Index: libstdc++-v3/include/experimental/any
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/any	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/experimental/any	(.../branches/gcc-6-branch)
+@@ -425,7 +425,10 @@
+   template<typename _Tp>
+     void* __any_caster(const any* __any)
+     {
+-      if (__any->_M_manager != &any::_Manager<decay_t<_Tp>>::_S_manage)
++      struct _None { };
++      using _Up = decay_t<_Tp>;
++      using _Vp = conditional_t<is_copy_constructible<_Up>::value, _Up, _None>;
++      if (__any->_M_manager != &any::_Manager<_Vp>::_S_manage)
+ 	return nullptr;
+       any::_Arg __arg;
+       __any->_M_manager(any::_Op_access, __any, &__arg);
+Index: libstdc++-v3/include/experimental/memory
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/memory	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/experimental/memory	(.../branches/gcc-6-branch)
+@@ -124,9 +124,9 @@
+       constexpr __pointer
+       release() noexcept
+       {
+-	__pointer tmp = get();
++	__pointer __tmp = get();
+ 	reset();
+-	return tmp;
++	return __tmp;
+       }
+ 
+       constexpr void
+Index: libstdc++-v3/include/experimental/array
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/array	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/experimental/array	(.../branches/gcc-6-branch)
+@@ -69,9 +69,9 @@
+ template <typename _Dest = void, typename... _Types>
+   constexpr auto
+   make_array(_Types&&... __t)
+-    -> array<conditional_t<is_void_v<_Dest>,
+-                           common_type_t<_Types...>,
+-                           _Dest>,
++    -> array<typename conditional_t<is_void_v<_Dest>,
++				    common_type<_Types...>,
++				    common_type<_Dest>>::type,
+              sizeof...(_Types)>
+   {
+     static_assert(__or_<
+@@ -80,13 +80,12 @@
+                   ::value,
+                   "make_array cannot be used without an explicit target type "
+                   "if any of the types given is a reference_wrapper");
+-    return {{forward<_Types>(__t)...}};
++    return {{ std::forward<_Types>(__t)... }};
+   }
+ 
+ template <typename _Tp, size_t _Nm, size_t... _Idx>
+   constexpr array<remove_cv_t<_Tp>, _Nm>
+-  __to_array(_Tp (&__a)[_Nm],
+-             index_sequence<_Idx...>)
++  __to_array(_Tp (&__a)[_Nm], index_sequence<_Idx...>)
+   {
+     return {{__a[_Idx]...}};
+   }
+@@ -94,6 +93,7 @@
+ template <typename _Tp, size_t _Nm>
+   constexpr array<remove_cv_t<_Tp>, _Nm>
+   to_array(_Tp (&__a)[_Nm])
++  noexcept(is_nothrow_constructible<remove_cv_t<_Tp>, _Tp&>::value)
+   {
+     return __to_array(__a, make_index_sequence<_Nm>{});
+   }
+Index: libstdc++-v3/include/ext/pointer.h
+===================================================================
+--- a/src/libstdc++-v3/include/ext/pointer.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/ext/pointer.h	(.../branches/gcc-6-branch)
+@@ -449,9 +449,9 @@
+       inline _Pointer_adapter 
+       operator++(int)
+       {
+-        _Pointer_adapter tmp(*this);
++        _Pointer_adapter __tmp(*this);
+         _Storage_policy::set(_Storage_policy::get() + 1);
+-        return tmp;
++        return __tmp;
+       }
+   
+       inline _Pointer_adapter& 
+@@ -464,9 +464,9 @@
+       inline _Pointer_adapter
+       operator--(int) 
+       {
+-        _Pointer_adapter tmp(*this);
++        _Pointer_adapter __tmp(*this);
+         _Storage_policy::set(_Storage_policy::get() - 1);
+-        return tmp;
++        return __tmp;
+       }
+   
+     }; // class _Pointer_adapter
+Index: libstdc++-v3/include/bits/stl_map.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/stl_map.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/stl_map.h	(.../branches/gcc-6-branch)
+@@ -1129,7 +1129,7 @@
+       template<typename _Kt>
+ 	auto
+ 	count(const _Kt& __x) const -> decltype(_M_t._M_count_tr(__x))
+-	{ return _M_t._M_find_tr(__x) == _M_t.end() ? 0 : 1; }
++	{ return _M_t._M_count_tr(__x); }
+ #endif
+       //@}
+ 
+@@ -1153,8 +1153,8 @@
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return iterator(_M_t._M_lower_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -1178,8 +1178,8 @@
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(const_iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return const_iterator(_M_t._M_lower_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -1198,8 +1198,8 @@
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return iterator(_M_t._M_upper_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -1218,8 +1218,8 @@
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(const_iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return const_iterator(_M_t._M_upper_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -1247,8 +1247,8 @@
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x)
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)))
++	{ return pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -1276,8 +1276,12 @@
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x) const
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<const_iterator, const_iterator>(
++	      _M_t._M_equal_range_tr(__x)))
++	{
++	  return pair<const_iterator, const_iterator>(
++	      _M_t._M_equal_range_tr(__x));
++	}
+ #endif
+       //@}
+ 
+Index: libstdc++-v3/include/bits/locale_classes.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/locale_classes.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/locale_classes.h	(.../branches/gcc-6-branch)
+@@ -461,10 +461,11 @@
+ 	}
+     }
+ 
+-    class __shim;
+-
+     const facet* _M_sso_shim(const id*) const;
+     const facet* _M_cow_shim(const id*) const;
++
++  protected:
++    class __shim; // For internal use only.
+   };
+ 
+ 
+Index: libstdc++-v3/include/bits/stl_set.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/stl_set.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/stl_set.h	(.../branches/gcc-6-branch)
+@@ -670,7 +670,7 @@
+ 	auto
+ 	count(const _Kt& __x) const
+ 	-> decltype(_M_t._M_count_tr(__x))
+-	{ return _M_t._M_find_tr(__x) == _M_t.end() ? 0 : 1; }
++	{ return _M_t._M_count_tr(__x); }
+ #endif
+       //@}
+ 
+@@ -735,14 +735,14 @@
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return iterator(_M_t._M_lower_bound_tr(__x)); }
+ 
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(const_iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return const_iterator(_M_t._M_lower_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -765,14 +765,14 @@
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return iterator(_M_t._M_upper_bound_tr(__x)); }
+ 
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return const_iterator(_M_t._M_upper_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -804,14 +804,14 @@
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x)
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)))
++	{ return pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)); }
+ 
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x) const
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)))
++	{ return pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)); }
+ #endif
+       //@}
+ 
+Index: libstdc++-v3/include/bits/basic_string.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/basic_string.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/basic_string.h	(.../branches/gcc-6-branch)
+@@ -570,10 +570,25 @@
+ 	    if (!_Alloc_traits::_S_always_equal() && !_M_is_local()
+ 		&& _M_get_allocator() != __str._M_get_allocator())
+ 	      {
+-		// replacement allocator cannot free existing storage
+-		_M_destroy(_M_allocated_capacity);
+-		_M_data(_M_local_data());
+-		_M_set_length(0);
++		// Propagating allocator cannot free existing storage so must
++		// deallocate it before replacing current allocator.
++		if (__str.size() <= _S_local_capacity)
++		  {
++		    _M_destroy(_M_allocated_capacity);
++		    _M_data(_M_local_data());
++		    _M_set_length(0);
++		  }
++		else
++		  {
++		    const auto __len = __str.size();
++		    auto __alloc = __str._M_get_allocator();
++		    // If this allocation throws there are no effects:
++		    auto __ptr = _Alloc_traits::allocate(__alloc, __len + 1);
++		    _M_destroy(_M_allocated_capacity);
++		    _M_data(__ptr);
++		    _M_capacity(__len);
++		    _M_set_length(__len);
++		  }
+ 	      }
+ 	    std::__alloc_on_copy(_M_get_allocator(), __str._M_get_allocator());
+ 	  }
+Index: libstdc++-v3/include/bits/stl_multimap.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/stl_multimap.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/stl_multimap.h	(.../branches/gcc-6-branch)
+@@ -822,8 +822,8 @@
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return iterator(_M_t._M_lower_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -847,8 +847,8 @@
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(const_iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return const_iterator(_M_t._M_lower_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -867,8 +867,8 @@
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return iterator(_M_t._M_upper_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -887,8 +887,8 @@
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(const_iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return const_iterator(_M_t._M_upper_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -914,8 +914,8 @@
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x)
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)))
++	{ return pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -941,8 +941,12 @@
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x) const
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<const_iterator, const_iterator>(
++	      _M_t._M_equal_range_tr(__x)))
++	{
++	  return pair<const_iterator, const_iterator>(
++	      _M_t._M_equal_range_tr(__x));
++	}
+ #endif
+       //@}
+ 
+Index: libstdc++-v3/include/bits/ios_base.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/ios_base.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/ios_base.h	(.../branches/gcc-6-branch)
+@@ -207,12 +207,12 @@
+   const error_category& iostream_category() noexcept;
+ 
+   inline error_code
+-  make_error_code(io_errc e) noexcept
+-  { return error_code(static_cast<int>(e), iostream_category()); }
++  make_error_code(io_errc __e) noexcept
++  { return error_code(static_cast<int>(__e), iostream_category()); }
+ 
+   inline error_condition
+-  make_error_condition(io_errc e) noexcept
+-  { return error_condition(static_cast<int>(e), iostream_category()); }
++  make_error_condition(io_errc __e) noexcept
++  { return error_condition(static_cast<int>(__e), iostream_category()); }
+ #endif
+ 
+   // 27.4.2  Class ios_base
+Index: libstdc++-v3/include/bits/predefined_ops.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/predefined_ops.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/predefined_ops.h	(.../branches/gcc-6-branch)
+@@ -24,7 +24,7 @@
+ 
+ /** @file predefined_ops.h
+  *  This is an internal header file, included by other library headers.
+- *  You should not attempt to use it directly.
++ *  You should not attempt to use it directly. @headername{algorithm}
+  */
+ 
+ #ifndef _GLIBCXX_PREDEFINED_OPS_H
+@@ -42,6 +42,7 @@
+       operator()(_Iterator1 __it1, _Iterator2 __it2) const
+       { return *__it1 < *__it2; }
+   };
++
+   _GLIBCXX14_CONSTEXPR
+   inline _Iter_less_iter
+   __iter_less_iter()
+@@ -53,7 +54,7 @@
+       bool
+       operator()(_Iterator __it, _Value& __val) const
+       { return *__it < __val; }
+-    };
++  };
+ 
+   inline _Iter_less_val
+   __iter_less_val()
+@@ -69,7 +70,7 @@
+       bool
+       operator()(_Value& __val, _Iterator __it) const
+       { return __val < *__it; }
+-    };
++  };
+ 
+   inline _Val_less_iter
+   __val_less_iter()
+@@ -85,7 +86,7 @@
+       bool
+       operator()(_Iterator1 __it1, _Iterator2 __it2) const
+       { return *__it1 == *__it2; }
+-    };
++  };
+ 
+   inline _Iter_equal_to_iter
+   __iter_equal_to_iter()
+@@ -97,7 +98,7 @@
+       bool
+       operator()(_Iterator __it, _Value& __val) const
+       { return *__it == __val; }
+-    };
++  };
+ 
+   inline _Iter_equal_to_val
+   __iter_equal_to_val()
+@@ -111,7 +112,8 @@
+     struct _Iter_comp_iter
+     {
+       _Compare _M_comp;
+-      _GLIBCXX14_CONSTEXPR
++
++      explicit _GLIBCXX14_CONSTEXPR
+       _Iter_comp_iter(_Compare __comp)
+ 	: _M_comp(__comp)
+       { }
+@@ -134,6 +136,7 @@
+     {
+       _Compare _M_comp;
+ 
++      explicit
+       _Iter_comp_val(_Compare __comp)
+ 	: _M_comp(__comp)
+       { }
+@@ -159,6 +162,7 @@
+     {
+       _Compare _M_comp;
+ 
++      explicit
+       _Val_comp_iter(_Compare __comp)
+ 	: _M_comp(__comp)
+       { }
+@@ -184,6 +188,7 @@
+     {
+       _Value& _M_value;
+ 
++      explicit
+       _Iter_equals_val(_Value& __value)
+ 	: _M_value(__value)
+       { }
+@@ -202,16 +207,17 @@
+   template<typename _Iterator1>
+     struct _Iter_equals_iter
+     {
+-      typename std::iterator_traits<_Iterator1>::reference _M_ref;
++      _Iterator1 _M_it1;
+ 
++      explicit
+       _Iter_equals_iter(_Iterator1 __it1)
+-	: _M_ref(*__it1)
++	: _M_it1(__it1)
+       { }
+ 
+       template<typename _Iterator2>
+ 	bool
+ 	operator()(_Iterator2 __it2)
+-	{ return *__it2 == _M_ref; }
++	{ return *__it2 == *_M_it1; }
+     };
+ 
+   template<typename _Iterator>
+@@ -224,6 +230,7 @@
+     {
+       _Predicate _M_pred;
+ 
++      explicit
+       _Iter_pred(_Predicate __pred)
+ 	: _M_pred(__pred)
+       { }
+@@ -264,16 +271,16 @@
+     struct _Iter_comp_to_iter
+     {
+       _Compare _M_comp;
+-      typename std::iterator_traits<_Iterator1>::reference _M_ref;
++      _Iterator1 _M_it1;
+ 
+       _Iter_comp_to_iter(_Compare __comp, _Iterator1 __it1)
+-	: _M_comp(__comp), _M_ref(*__it1)
++	: _M_comp(__comp), _M_it1(__it1)
+       { }
+ 
+       template<typename _Iterator2>
+ 	bool
+ 	operator()(_Iterator2 __it2)
+-	{ return bool(_M_comp(*__it2, _M_ref)); }
++	{ return bool(_M_comp(*__it2, *_M_it1)); }
+     };
+ 
+   template<typename _Compare, typename _Iterator>
+@@ -286,6 +293,7 @@
+     {
+       _Predicate _M_pred;
+ 
++      explicit
+       _Iter_negate(_Predicate __pred)
+ 	: _M_pred(__pred)
+       { }
+Index: libstdc++-v3/include/bits/stl_multiset.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/stl_multiset.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/stl_multiset.h	(.../branches/gcc-6-branch)
+@@ -716,14 +716,14 @@
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return iterator(_M_t._M_lower_bound_tr(__x)); }
+ 
+       template<typename _Kt>
+ 	auto
+ 	lower_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_lower_bound_tr(__x))
+-	{ return _M_t._M_lower_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_lower_bound_tr(__x)))
++	{ return iterator(_M_t._M_lower_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -746,14 +746,14 @@
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x)
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return iterator(_M_t._M_upper_bound_tr(__x)); }
+ 
+       template<typename _Kt>
+ 	auto
+ 	upper_bound(const _Kt& __x) const
+-	-> decltype(_M_t._M_upper_bound_tr(__x))
+-	{ return _M_t._M_upper_bound_tr(__x); }
++	-> decltype(iterator(_M_t._M_upper_bound_tr(__x)))
++	{ return iterator(_M_t._M_upper_bound_tr(__x)); }
+ #endif
+       //@}
+ 
+@@ -785,14 +785,14 @@
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x)
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)))
++	{ return pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)); }
+ 
+       template<typename _Kt>
+ 	auto
+ 	equal_range(const _Kt& __x) const
+-	-> decltype(_M_t._M_equal_range_tr(__x))
+-	{ return _M_t._M_equal_range_tr(__x); }
++	-> decltype(pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)))
++	{ return pair<iterator, iterator>(_M_t._M_equal_range_tr(__x)); }
+ #endif
+       //@}
+ 
+Index: libstdc++-v3/include/bits/mask_array.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/mask_array.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/mask_array.h	(.../branches/gcc-6-branch)
+@@ -136,8 +136,8 @@
+     };
+ 
+   template<typename _Tp>
+-    inline mask_array<_Tp>::mask_array(const mask_array<_Tp>& a)
+-    : _M_sz(a._M_sz), _M_mask(a._M_mask), _M_array(a._M_array) {}
++    inline mask_array<_Tp>::mask_array(const mask_array<_Tp>& __a)
++    : _M_sz(__a._M_sz), _M_mask(__a._M_mask), _M_array(__a._M_array) {}
+ 
+   template<typename _Tp>
+     inline
+Index: libstdc++-v3/include/bits/ptr_traits.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/ptr_traits.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/ptr_traits.h	(.../branches/gcc-6-branch)
+@@ -56,7 +56,7 @@
+   // Given Template<T, ...> and U return Template<U, ...>, otherwise invalid.
+   template<typename _Tp, typename _Up>
+     struct __replace_first_arg
+-    { using type = __undefined; };
++    { };
+ 
+   template<template<typename, typename...> class _Template, typename _Up,
+            typename _Tp, typename... _Types>
+@@ -84,8 +84,12 @@
+       template<typename _Tp>
+ 	using __difference_type = typename _Tp::difference_type;
+ 
++      template<typename _Tp, typename _Up, typename = void>
++	struct __rebind : __replace_first_arg<_Tp, _Up> { };
++
+       template<typename _Tp, typename _Up>
+-	using __rebind = typename _Tp::template rebind<_Up>;
++	struct __rebind<_Tp, _Up, __void_t<typename _Tp::template rebind<_Up>>>
++	{ using type = typename _Tp::template rebind<_Up>; };
+ 
+     public:
+       /// The pointer type.
+@@ -93,7 +97,7 @@
+ 
+       /// The type pointed to.
+       using element_type
+-	= __detected_or_t_<__get_first_arg_t, __element_type, _Ptr>;
++	= __detected_or_t<__get_first_arg_t<_Ptr>, __element_type, _Ptr>;
+ 
+       /// The type used to represent the difference between two pointers.
+       using difference_type
+@@ -101,8 +105,7 @@
+ 
+       /// A pointer to a different type.
+       template<typename _Up>
+-        using rebind
+-	  = __detected_or_t_<__replace_first_arg_t, __rebind, _Ptr, _Up>;
++        using rebind = typename __rebind<_Ptr, _Up>::type;
+ 
+       static _Ptr
+       pointer_to(__make_not_void<element_type>& __e)
+@@ -110,8 +113,6 @@
+ 
+       static_assert(!is_same<element_type, __undefined>::value,
+ 	  "pointer type defines element_type or is like SomePointer<T, Args>");
+-      static_assert(!is_same<rebind<element_type>, __undefined>::value,
+-	  "pointer type defines rebind<U> or is like SomePointer<T, Args>");
+     };
+ 
+   /**
+Index: libstdc++-v3/include/bits/slice_array.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/slice_array.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/slice_array.h	(.../branches/gcc-6-branch)
+@@ -204,8 +204,8 @@
+ 
+   template<typename _Tp>
+     inline
+-    slice_array<_Tp>::slice_array(const slice_array<_Tp>& a)
+-    : _M_sz(a._M_sz), _M_stride(a._M_stride), _M_array(a._M_array) {}
++    slice_array<_Tp>::slice_array(const slice_array<_Tp>& __a)
++    : _M_sz(__a._M_sz), _M_stride(__a._M_stride), _M_array(__a._M_array) {}
+ 
+   //    template<typename _Tp>
+   //    inline slice_array<_Tp>::~slice_array () {}
+Index: libstdc++-v3/include/bits/list.tcc
+===================================================================
+--- a/src/libstdc++-v3/include/bits/list.tcc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/list.tcc	(.../branches/gcc-6-branch)
+@@ -380,26 +380,36 @@
+       // 300. list::merge() specification incomplete
+       if (this != std::__addressof(__x))
+ 	{
+-	  _M_check_equal_allocators(__x); 
++	  _M_check_equal_allocators(__x);
+ 
+ 	  iterator __first1 = begin();
+ 	  iterator __last1 = end();
+ 	  iterator __first2 = __x.begin();
+ 	  iterator __last2 = __x.end();
+-	  while (__first1 != __last1 && __first2 != __last2)
+-	    if (*__first2 < *__first1)
+-	      {
+-		iterator __next = __first2;
+-		_M_transfer(__first1, __first2, ++__next);
+-		__first2 = __next;
+-	      }
+-	    else
+-	      ++__first1;
+-	  if (__first2 != __last2)
+-	    _M_transfer(__last1, __first2, __last2);
++	  const size_t __orig_size = __x.size();
++	  __try {
++	    while (__first1 != __last1 && __first2 != __last2)
++	      if (*__first2 < *__first1)
++		{
++		  iterator __next = __first2;
++		  _M_transfer(__first1, __first2, ++__next);
++		  __first2 = __next;
++		}
++	      else
++		++__first1;
++	    if (__first2 != __last2)
++	      _M_transfer(__last1, __first2, __last2);
+ 
+-	  this->_M_inc_size(__x._M_get_size());
+-	  __x._M_set_size(0);
++	    this->_M_inc_size(__x._M_get_size());
++	    __x._M_set_size(0);
++	  }
++	  __catch(...)
++	    {
++	      const size_t __dist = std::distance(__first2, __last2);
++	      this->_M_inc_size(__orig_size - __dist);
++	      __x._M_set_size(__dist);
++	      __throw_exception_again;
++	    }
+ 	}
+     }
+ 
+@@ -423,20 +433,31 @@
+ 	    iterator __last1 = end();
+ 	    iterator __first2 = __x.begin();
+ 	    iterator __last2 = __x.end();
+-	    while (__first1 != __last1 && __first2 != __last2)
+-	      if (__comp(*__first2, *__first1))
+-		{
+-		  iterator __next = __first2;
+-		  _M_transfer(__first1, __first2, ++__next);
+-		  __first2 = __next;
+-		}
+-	      else
+-		++__first1;
+-	    if (__first2 != __last2)
+-	      _M_transfer(__last1, __first2, __last2);
++	    const size_t __orig_size = __x.size();
++	    __try
++	      {
++		while (__first1 != __last1 && __first2 != __last2)
++		  if (__comp(*__first2, *__first1))
++		    {
++		      iterator __next = __first2;
++		      _M_transfer(__first1, __first2, ++__next);
++		      __first2 = __next;
++		    }
++		  else
++		    ++__first1;
++		if (__first2 != __last2)
++		  _M_transfer(__last1, __first2, __last2);
+ 
+-	    this->_M_inc_size(__x._M_get_size());
+-	    __x._M_set_size(0);
++		this->_M_inc_size(__x._M_get_size());
++		__x._M_set_size(0);
++	      }
++	    __catch(...)
++	      {
++		const size_t __dist = std::distance(__first2, __last2);
++		this->_M_inc_size(__orig_size - __dist);
++		__x._M_set_size(__dist);
++		__throw_exception_again;
++	      }
+ 	  }
+       }
+ 
+Index: libstdc++-v3/include/bits/regex.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/regex.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/regex.h	(.../branches/gcc-6-branch)
+@@ -2672,9 +2672,9 @@
+ 			   initializer_list<int>,
+ 			   regex_constants::match_flag_type =
+ 			   regex_constants::match_default) = delete;
+-      template <std::size_t N>
++      template <std::size_t _Nm>
+ 	regex_token_iterator(_Bi_iter, _Bi_iter, const regex_type&&,
+-			     const int (&)[N],
++			     const int (&)[_Nm],
+ 			     regex_constants::match_flag_type =
+ 			     regex_constants::match_default) = delete;
+ 
+Index: libstdc++-v3/include/bits/alloc_traits.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/alloc_traits.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/alloc_traits.h	(.../branches/gcc-6-branch)
+@@ -44,9 +44,14 @@
+ 
+   struct __allocator_traits_base
+   {
+-    template<typename _Alloc, typename _Up>
+-      using __rebind = typename _Alloc::template rebind<_Up>::other;
++    template<typename _Tp, typename _Up, typename = void>
++      struct __rebind : __replace_first_arg<_Tp, _Up> { };
+ 
++    template<typename _Tp, typename _Up>
++      struct __rebind<_Tp, _Up,
++		      __void_t<typename _Tp::template rebind<_Up>::other>>
++      { using type = typename _Tp::template rebind<_Up>::other; };
++
+   protected:
+     template<typename _Tp>
+       using __pointer = typename _Tp::pointer;
+@@ -57,10 +62,6 @@
+     template<typename _Tp>
+       using __cv_pointer = typename _Tp::const_void_pointer;
+     template<typename _Tp>
+-      using __diff_type = typename _Tp::difference_type;
+-    template<typename _Tp>
+-      using __size_type = typename _Tp::size_type;
+-    template<typename _Tp>
+       using __pocca = typename _Tp::propagate_on_container_copy_assignment;
+     template<typename _Tp>
+       using __pocma = typename _Tp::propagate_on_container_move_assignment;
+@@ -71,9 +72,8 @@
+   };
+ 
+   template<typename _Alloc, typename _Up>
+-    using __alloc_rebind = __detected_or_t_<__replace_first_arg_t,
+-					    __allocator_traits_base::__rebind,
+-					    _Alloc, _Up>;
++    using __alloc_rebind
++      = typename __allocator_traits_base::template __rebind<_Alloc, _Up>::type;
+ 
+   /**
+    * @brief  Uniform interface to all allocator types.
+@@ -94,6 +94,38 @@
+       */
+       using pointer = __detected_or_t<value_type*, __pointer, _Alloc>;
+ 
++    private:
++      // Select _Func<_Alloc> or pointer_traits<pointer>::rebind<_Tp>
++      template<template<typename> class _Func, typename _Tp, typename = void>
++	struct _Ptr
++	{
++	  using type = typename pointer_traits<pointer>::template rebind<_Tp>;
++	};
++
++      template<template<typename> class _Func, typename _Tp>
++	struct _Ptr<_Func, _Tp, __void_t<_Func<_Alloc>>>
++	{
++	  using type = _Func<_Alloc>;
++	};
++
++      // Select _A2::difference_type or pointer_traits<_Ptr>::difference_type
++      template<typename _A2, typename _PtrT, typename = void>
++	struct _Diff
++	{ using type = typename pointer_traits<_PtrT>::difference_type; };
++
++      template<typename _A2, typename _PtrT>
++	struct _Diff<_A2, _PtrT, __void_t<typename _A2::difference_type>>
++	{ using type = typename _A2::difference_type; };
++
++      // Select _A2::size_type or make_unsigned<_DiffT>::type
++      template<typename _A2, typename _DiffT, typename = void>
++	struct _Size : make_unsigned<_DiffT> { };
++
++      template<typename _A2, typename _DiffT>
++	struct _Size<_A2, _DiffT, __void_t<typename _A2::size_type>>
++	{ using type = typename _A2::size_type; };
++
++    public:
+       /**
+        * @brief   The allocator's const pointer type.
+        *
+@@ -100,9 +132,7 @@
+        * @c Alloc::const_pointer if that type exists, otherwise
+        * <tt> pointer_traits<pointer>::rebind<const value_type> </tt>
+       */
+-      using const_pointer
+-	= __detected_or_t<__ptr_rebind<pointer, const value_type>,
+-			  __c_pointer, _Alloc>;
++      using const_pointer = typename _Ptr<__c_pointer, const value_type>::type;
+ 
+       /**
+        * @brief   The allocator's void pointer type.
+@@ -110,8 +140,7 @@
+        * @c Alloc::void_pointer if that type exists, otherwise
+        * <tt> pointer_traits<pointer>::rebind<void> </tt>
+       */
+-      using void_pointer
+-	= __detected_or_t<__ptr_rebind<pointer, void>, __v_pointer, _Alloc>;
++      using void_pointer = typename _Ptr<__v_pointer, void>::type;
+ 
+       /**
+        * @brief   The allocator's const void pointer type.
+@@ -119,9 +148,7 @@
+        * @c Alloc::const_void_pointer if that type exists, otherwise
+        * <tt> pointer_traits<pointer>::rebind<const void> </tt>
+       */
+-      using const_void_pointer
+-	= __detected_or_t<__ptr_rebind<pointer, const void>, __cv_pointer,
+-			  _Alloc>;
++      using const_void_pointer = typename _Ptr<__cv_pointer, const void>::type;
+ 
+       /**
+        * @brief   The allocator's difference type
+@@ -129,9 +156,7 @@
+        * @c Alloc::difference_type if that type exists, otherwise
+        * <tt> pointer_traits<pointer>::difference_type </tt>
+       */
+-      using difference_type
+-	= __detected_or_t<typename pointer_traits<pointer>::difference_type,
+-			  __diff_type, _Alloc>;
++      using difference_type = typename _Diff<_Alloc, pointer>::type;
+ 
+       /**
+        * @brief   The allocator's size type
+@@ -139,9 +164,7 @@
+        * @c Alloc::size_type if that type exists, otherwise
+        * <tt> make_unsigned<difference_type>::type </tt>
+       */
+-      using size_type
+-	= __detected_or_t<typename make_unsigned<difference_type>::type,
+-			  __size_type, _Alloc>;
++      using size_type = typename _Size<_Alloc, difference_type>::type;
+ 
+       /**
+        * @brief   How the allocator is propagated on copy assignment
+@@ -184,9 +207,6 @@
+       template<typename _Tp>
+ 	using rebind_traits = allocator_traits<rebind_alloc<_Tp>>;
+ 
+-      static_assert(!is_same<rebind_alloc<value_type>, __undefined>::value,
+-	  "allocator defines rebind or is like Alloc<T, Args>");
+-
+     private:
+       template<typename _Alloc2>
+ 	static auto
+Index: libstdc++-v3/libsupc++/nested_exception.h
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/nested_exception.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/libsupc++/nested_exception.h	(.../branches/gcc-6-branch)
+@@ -115,7 +115,7 @@
+     inline void
+     throw_with_nested(_Tp&& __t)
+     {
+-      using _Up = typename remove_reference<_Tp>::type;
++      using _Up = typename decay<_Tp>::type;
+       using _CopyConstructible
+ 	= __and_<is_copy_constructible<_Up>, is_move_constructible<_Up>>;
+       static_assert(_CopyConstructible::value,
+Index: libstdc++-v3/ChangeLog
+===================================================================
+--- a/src/libstdc++-v3/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,277 @@
++2017-03-14  Jonathan Wakely  <jwakely@redhat.com>
++
++	* testsuite/17_intro/names.cc: Undefine macros that clash with
++	identifiers in AIX system headers.
++
++2017-03-13  Ville Voutilainen  <ville.voutilainen@gmail.com>
++
++	PR libstdc++/80034
++	* include/bits/list.tcc (merge(list&&)): Use const for the size_t
++	in the function and in the catch-block, qualify uses of std::distance.
++	(merge(list&&, _StrictWeakOrdering)): Likewise.
++	* testsuite/23_containers/list/operations/80034.cc: New.
++
++2017-03-10  George Lander  <george.lander@arm.com>
++
++	* acinclude.m4 (glibcxx_cv_obsolete_isnan): Define
++	_GLIBCXX_INCLUDE_NEXT_C_HEADERS before including math.h.
++	* configure: Regenerate.
++
++2017-03-02  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/79789
++	* include/bits/ios_base.h (make_error_code, make_error_condition):
++	Likewise.
++	* include/bits/mask_array.h (mask_array): Likewise.
++	* include/bits/regex.h (regex_token_iterator): Likewise.
++	* include/bits/slice_array.h (slice_array): Likewise.
++	* include/std/memory (undeclare_no_pointers): Likewise.
++	* testsuite/17_intro/names.cc: New test.
++
++2017-02-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/79114
++	* testsuite/18_support/nested_exception/79114.cc: Add dg-require.
++
++	Backport from mainline
++	2016-12-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/59170
++	* python/libstdcxx/v6/printers.py (StdListIteratorPrinter.to_string)
++	(StdSlistIteratorPrinter.to_string, StdVectorIteratorPrinter.to_string)
++	(StdRbtreeIteratorPrinter.to_string)
++	(StdDequeIteratorPrinter.to_string): Add check for value-initialized
++	iterators.
++	* testsuite/libstdc++-prettyprinters/simple.cc: Test them.
++	* testsuite/libstdc++-prettyprinters/simple11.cc: Likewise.
++
++	Backport from mainline
++	2016-12-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/59161
++	* python/libstdcxx/v6/printers.py (StdListIteratorPrinter.to_string)
++	(StdSlistIteratorPrinter.to_string, StdVectorIteratorPrinter.to_string)
++	(StdRbtreeIteratorPrinter.to_string, StdDequeIteratorPrinter.to_string)
++	(StdDebugIteratorPrinter.to_string): Return string instead of
++	gdb.Value.
++	* testsuite/libstdc++-prettyprinters/59161.cc: New test.
++
++	Backport from mainline
++	2016-12-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	* python/libstdcxx/v6/printers.py (UniquePointerPrinter.to_string):
++	Remove redundant parentheses.
++	(RbtreeIterator, StdRbtreeIteratorPrinter): Add docstrings.
++	(StdForwardListPrinter.to_string): Remove redundant parentheses.
++	(StdExpOptionalPrinter.to_string): Use string formatting instead of
++	concatenation.
++	(TemplateTypePrinter): Adjust whitespace.
++
++	Backport from mainline
++	2016-12-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	* python/libstdcxx/v6/xmethods.py (UniquePtrGetWorker.__init__): Use
++	correct element type for unique_ptr<T[]>.
++	(UniquePtrGetWorker._supports, UniquePtrDerefWorker._supports): New
++	functions to disable unsupported operators for unique_ptr<T[]>.
++	(UniquePtrSubscriptWorker): New worker for operator[].
++	(UniquePtrMethodsMatcher.__init__): Register UniquePtrSubscriptWorker.
++	(UniquePtrMethodsMatcher.match): Call _supports on the chosen worker.
++	(SharedPtrGetWorker, SharedPtrDerefWorker, SharedPtrSubscriptWorker)
++	(SharedPtrUseCountWorker, SharedPtrUniqueWorker): New workers.
++	(SharedPtrMethodsMatcher): New matcher for shared_ptr.
++	(register_libstdcxx_xmethods): Register SharedPtrMethodsMatcher.
++	* testsuite/libstdc++-xmethods/unique_ptr.cc: Test arrays.
++	* testsuite/libstdc++-xmethods/shared_ptr.cc: New test.
++
++2017-02-14  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-01-20  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/72792
++	* include/bits/alloc_traits.h (__allocator_traits_base::__diff_type)
++	(__allocator_traits_base::__size_type): Remove.
++	(allocator_traits::_Ptr): New class template to detect const and void
++	pointer types without instantiating pointer_traits::rebind
++	unnecessarily.
++	(allocator_traits::_Diff): Likewise for detecting difference_type.
++	(allocator_traits::_Size): New class template to detect size_type
++	without instantiating make_unsigned unnecessarily.
++	* include/bits/ptr_traits.h (pointer_traits::element_type): Use
++	__detected_or_t instead of __detected_or_t_.
++	* include/std/type_traits (__detected_or_t_): Remove.
++	* testsuite/20_util/allocator_traits/members/pointers.cc: New test.
++
++	Backport from mainline
++	2017-01-20  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/72792
++	PR libstdc++/72793
++	* include/bits/alloc_traits.h (__allocator_traits_base::__rebind):
++	Replace with class template using void_t.
++	(__alloc_rebind): Define in terms of
++	__allocator_traits_base::__rebind.
++	(allocator_traits): Remove unconditional static_assert for
++	rebind_alloc.
++	* include/bits/ptr_traits.h (__replace_first_arg): Remove type member.
++	(pointer_traits::__rebind): Replace with class template using void_t.
++	(pointer_traits::rebind): Define in terms of __rebind.
++	(pointer_traits): Remove unconditional static_assert for rebind.
++	* testsuite/20_util/allocator_traits/members/rebind_alloc.cc: New test.
++	* testsuite/20_util/pointer_traits/rebind.cc: New test.
++
++	Backport from mainline
++	2017-01-20  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/69321
++	* include/experimental/any (__any_caster): Avoid instantiating
++	manager function for types that can't be stored in any.
++	* testsuite/experimental/any/misc/any_cast.cc: Test non-copyable type.
++
++	Backport from mainline
++	2017-01-18  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/69301
++	* include/std/atomic (atomic<T>::load, atomic<T>::exchange): Use
++	aligned buffer instead of default-initialized variable.
++	* testsuite/29_atomics/atomic/69301.cc: New test.
++	* include/experimental/memory (observer_ptr::release): Use reserved
++	name.
++	* include/ext/pointer.h (_Pointer_adapter::operator++(int))
++	(_Pointer_adapter::operator--(int)): Likewise.
++
++	Backport from mainline
++	2017-01-17  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/79114
++	* libsupc++/nested_exception.h (throw_with_nested): Use decay instead
++	of remove_reference.
++	* testsuite/18_support/nested_exception/79114.cc: New test.
++
++	Backport from mainline
++	2017-01-16  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/78702
++	* include/bits/locale_classes.h (locale::facet::__shim): Change from
++	private to protected.
++	* src/c++11/cxx11-shim_facets.cc (__shim_accessor): Define helper to
++	make locale::facet::__shim accessible.
++
++	Backport from mainline
++	2017-01-11  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/78134
++	* include/bits/stl_map.h (map::lower_bound, map::upper_bound)
++	(map::equal_range): Fix return type of heterogeneous overloads.
++	* include/bits/stl_multimap.h (multimap::lower_bound)
++	(multimap::upper_bound, multimap::equal_range): Likewise.
++	* include/bits/stl_multiset.h (multiset::lower_bound)
++	(multiset::upper_bound, multiset::equal_range): Likewise.
++	* include/bits/stl_set.h (set::lower_bound, set::upper_bound)
++	(set::equal_range): Likewise.
++	* testsuite/23_containers/map/operations/2.cc: Check return types.
++	* testsuite/23_containers/multimap/operations/2.cc: Likewise.
++	* testsuite/23_containers/multiset/operations/2.cc: Likewise.
++	* testsuite/23_containers/set/operations/2.cc: Likewise.
++
++	Backport from mainline
++	2017-01-11  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/78273
++	* include/bits/stl_map.h (map::count<_Kt>(const _Kt&)): Don't assume
++	the heterogeneous comparison can only find one match.
++	* include/bits/stl_set.h (set::count<_Kt>(const _Kt&)): Likewise.
++	* testsuite/23_containers/map/operations/2.cc: Test count works with
++	comparison function that just partitions rather than sorting.
++	* testsuite/23_containers/set/operations/2.cc: Likewise.
++
++2017-02-01  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/78346
++	* include/bits/predefined_ops.h (_Iter_equals_iter): Store iterator
++	not its referent.
++	(_Iter_comp_to_iter): Likewise.
++	* testsuite/25_algorithms/search/78346.cc: New test.
++
++	PR libstdc++/79195
++	* include/experimental/array (make_array): Use common_type<_Dest>
++	and delay instantiation of common_type until after conditional_t.
++	Qualify std::forward call.
++	(to_array): Add exception specification.
++	* testsuite/experimental/array/make_array.cc: Test argument types
++	without a common type.
++
++	PR libstdc++/79254
++	* include/bits/basic_string.h [_GLIBCXX_USE_CXX11_ABI]
++	(basic_string::operator=(const basic_string&)): If source object is
++	small just deallocate, otherwise perform new allocation before
++	making any changes.
++	* testsuite/21_strings/basic_string/allocator/wchar_t/copy_assign.cc:
++	Test exception-safety of copy assignment when allocator propagates.
++	* testsuite/21_strings/basic_string/allocator/char/copy_assign.cc:
++	Likewise.
++	* testsuite/util/testsuite_allocator.h (uneq_allocator::swap): Make
++	std::swap visible.
++
++2017-01-22  Gerald Pfeifer  <gerald@pfeifer.com>
++
++	Backport from mainline
++	2017-01-01  Gerald Pfeifer  <gerald@pfeifer.com>
++
++	* doc/xml/faq.xml: Update address of C++ ABI link.
++	* doc/xml/manual/abi.xml: Ditto.
++	
++2017-01-16  Ville Voutilainen  <ville.voutilainen@gmail.com>
++
++	Backport from mainline
++	2017-01-16  Ville Voutilainen  <ville.voutilainen@gmail.com>
++
++	PR libstdc++/78389
++	* include/bits/list.tcc (merge(list&&)): Fix backwards size adjustments.
++	(merge(list&&, _StrictWeakOrdering)): Likewise.
++	* testsuite/23_containers/list/operations/78389.cc: Add
++	better test for the sizes.
++
++2017-01-15  Ville Voutilainen  <ville.voutilainen@gmail.com>
++
++	Backport from mainline
++        2017-01-13  Ville Voutilainen  <ville.voutilainen@gmail.com>
++
++	PR libstdc++/78389
++	* include/bits/list.tcc (merge(list&&)):
++	Adjust list sizes if the comparator throws.
++	(merge(list&&, _StrictWeakOrdering)): Likewise.
++	* testsuite/23_containers/list/operations/78389.cc: New.
++
++2017-01-15  Ville Voutilainen  <ville.voutilainen@gmail.com>
++
++	Backport from mainline
++        2016-12-19  Ville Voutilainen  <ville.voutilainen@gmail.com>
++
++	Make the perfect-forwarding constructor of a two-element tuple
++	sfinae away when the first argument is an allocator_arg.
++	* include/std/tuple (tuple(_U1&&, _U2&&)): Constrain.
++	* testsuite/20_util/tuple/cons/allocator_with_any.cc: New.
++
++2017-01-06  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-01-03  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/78956
++	* include/std/thread (thread(const thread&&)): Add deleted
++	constructor.
++	* testsuite/30_threads/thread/cons/lwg2097.cc: New test.
++
++2017-01-06  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/78991
++	* include/bits/predefined_ops.h (_Iter_comp_iter, _Iter_comp_val)
++	(_Val_comp_iter, _Iter_equals_val, _Iter_pred, _Iter_comp_to_val)
++	(_Iter_comp_to_iter, _Iter_negate): Make constructors explicit.
++	* testsuite/25_algorithms/sort/78991.cc: New test.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: libstdc++-v3/testsuite/25_algorithms/search/78346.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/25_algorithms/search/78346.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/25_algorithms/search/78346.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,118 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++11 } }
++
++#include <algorithm>
++#include <testsuite_hooks.h>
++
++bool values[100];
++
++unsigned next_id()
++{
++  static unsigned counter = 0;
++  VERIFY(counter < 100);
++  return counter++;
++}
++
++struct value
++{
++  int val;
++  const unsigned id;
++
++  value(int i = 0) : val(i), id(next_id()) { values[id] = true; }
++  value(const value& v) : val(v.val), id(next_id()) { values[id] = true; }
++  value& operator=(const value& v) { val = v.val; return *this; }
++  ~value() { values[id] = false; }
++};
++
++bool operator<(const value& lhs, const value& rhs)
++{
++  if (!values[lhs.id])
++    throw lhs.id;
++  if (!values[rhs.id])
++    throw rhs.id;
++  return lhs.val < rhs.val;
++}
++
++bool operator==(const value& lhs, const value& rhs)
++{
++  if (!values[lhs.id])
++    throw lhs.id;
++  if (!values[rhs.id])
++    throw rhs.id;
++  return lhs.val == rhs.val;
++}
++
++// A forward iterator that fails to meet the requirement that for any
++// two dereferenceable forward iterators, a == b implies &*a == &*b
++struct stashing_iterator
++{
++  typedef std::forward_iterator_tag iterator_category;
++  typedef value value_type;
++  typedef value_type const* pointer;
++  typedef value_type const& reference;
++  typedef std::ptrdiff_t difference_type;
++
++  stashing_iterator() : ptr(), stashed() { }
++  stashing_iterator(pointer p) : ptr(p), stashed() { stash(); }
++  stashing_iterator(const stashing_iterator&) = default;
++  stashing_iterator& operator=(const stashing_iterator&) = default;
++
++  stashing_iterator& operator++()
++  {
++    ++ptr;
++    stash();
++    return *this;
++  }
++
++  stashing_iterator operator++(int)
++  {
++    stashing_iterator i = *this;
++    ++*this;
++    return i;
++  }
++
++  reference operator*() const { return stashed; }
++  pointer operator->() const { return &**this; }
++
++  bool operator==(const stashing_iterator& i) const { return ptr == i.ptr; }
++  bool operator!=(const stashing_iterator& i) const { return !(*this == i); }
++
++private:
++  void stash()
++  {
++    if (ptr)
++      stashed = *ptr;
++  }
++
++  pointer ptr;
++  value_type stashed;
++};
++
++void
++test01()
++{
++  value s[] = { 0, 1, 2, 3, 4, 5 };
++  std::search(s, s+6, stashing_iterator(s), stashing_iterator(s+4));
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/25_algorithms/sort/78991.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/25_algorithms/sort/78991.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/25_algorithms/sort/78991.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,40 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++14 } }
++
++// PR 78991
++// This failed to compile with Clang because the result_of expression causes
++// instantiation of _Iter_comp_iter::operator() outside the immediate context.
++
++#include <algorithm>
++
++struct function
++{
++  function() = default;
++
++  template<typename F, typename = std::result_of_t<F&(int, int)>>
++    function(F) { }
++
++  bool operator()(int x, int y) const { return x < y; }
++};
++
++int main()
++{
++  int a[2]{ 2, 1 };
++  std::sort(a, a+2, function{});
++}
+Index: libstdc++-v3/testsuite/18_support/nested_exception/79114.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/79114.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/79114.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++// { dg-require-atomic-builtins "" }
++
++#include <exception>
++
++void
++test01()
++{
++  std::throw_with_nested("");
++  std::throw_with_nested(test01);
++}
+Index: libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple11.cc	(.../branches/gcc-6-branch)
+@@ -30,6 +30,7 @@
+ #include <list>
+ #include <map>
+ #include <set>
++#include <vector>
+ #include <ext/slist>
+ 
+ int
+@@ -53,6 +54,9 @@
+   std::deque<std::string>::iterator deqiter = deq.begin();
+ // { dg-final { note-test deqiter {"one"} } }
+ 
++  std::deque<int>::iterator deqiter0;
++// { dg-final { note-test deqiter0 {non-dereferenceable iterator for std::deque} } }
++
+   std::list<std::string> lst;
+   lst.push_back("one");
+   lst.push_back("two");
+@@ -66,6 +70,9 @@
+   tem = *lstciter;
+ // { dg-final { note-test lstciter {"one"}} }
+ 
++  std::list<int>::iterator lstiter0;
++// { dg-final { note-test lstiter0 {non-dereferenceable iterator for std::list} } }
++
+   std::map<std::string, int> mp;
+   mp["zardoz"] = 23;
+ // { dg-final { note-test mp {std::map with 1 elements = {["zardoz"] = 23}} } }
+@@ -73,6 +80,9 @@
+   std::map<std::string, int>::iterator mpiter = mp.begin();
+ // { dg-final { note-test mpiter {{first = "zardoz", second = 23}} } }
+ 
++  std::map<std::string, int>::iterator mpiter0;
++// { dg-final { note-test mpiter0 {non-dereferenceable iterator for associative container} } }
++
+   // PR 67440
+   const std::set<int> const_intset = {2, 3};
+ // { dg-final { note-test const_intset {std::set with 2 elements = {[0] = 2, [1] = 3}} } }
+@@ -85,6 +95,20 @@
+   std::set<std::string>::const_iterator spciter = sp.begin();
+ // { dg-final { note-test spciter {"barrel"} } }
+ 
++  std::set<int>::iterator spiter0;
++// { dg-final { note-test spiter0 {non-dereferenceable iterator for associative container} } }
++
++  std::vector<int> v;
++  v.push_back(1);
++  v.push_back(2);
++  v.erase(v.begin());
++// { dg-final { note-test v {std::vector of length 1, capacity 2 = {2}} } }
++  std::vector<int>::iterator viter3 = v.begin();
++// { dg-final { note-test viter3 {2} } }
++
++  std::vector<int>::iterator viter0;
++// { dg-final { note-test viter0 {non-dereferenceable iterator for std::vector} } }
++
+   __gnu_cxx::slist<int> sll;
+   sll.push_front(23);
+   sll.push_front(47);
+@@ -93,6 +117,9 @@
+   __gnu_cxx::slist<int>::iterator slliter = sll.begin();
+ // { dg-final { note-test slliter {47} } }
+ 
++  __gnu_cxx::slist<int>::iterator slliter0;
++// { dg-final { note-test slliter0 {non-dereferenceable iterator for __gnu_cxx::slist} } }
++
+   std::cout << "\n";
+   return 0;			// Mark SPOT
+ }
+Index: libstdc++-v3/testsuite/libstdc++-prettyprinters/59161.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/libstdc++-prettyprinters/59161.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/libstdc++-prettyprinters/59161.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,70 @@
++// { dg-do run }
++// { dg-options "-g -O0" }
++
++// Copyright (C) 2011-2016 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <deque>
++#include <list>
++#include <ext/slist>
++#include <set>
++#include <vector>
++#include <debug/vector>
++#include <iostream>
++
++struct C {
++  C(int& i) : ref(i) { }
++  int& ref;
++  bool operator<(const C& c) const { return ref < c.ref; }
++};
++
++int main()
++{
++  int i = 1;
++  C c(i);
++
++  std::deque<C> d;
++  d.push_back(c);
++  std::deque<C>::iterator diter = d.begin();
++// { dg-final { regexp-test diter {ref = @0x.*} } }
++
++  std::list<C> l;
++  l.push_back(c);
++  std::list<C>::iterator liter = l.begin();
++  // Need to ensure the list<C>::iterator::_Node typedef is in the debuginfo:
++  int tmp __attribute__((unused)) = (*liter).ref;
++// { dg-final { regexp-test liter {ref = @0x.*} } }
++
++  __gnu_cxx::slist<C> sl;
++  sl.push_front(c);
++  __gnu_cxx::slist<C>::iterator sliter = sl.begin();
++// { dg-final { regexp-test sliter {ref = @0x.*} } }
++
++  std::set<C> s;
++  s.insert(c);
++  std::set<C>::iterator siter = s.begin();
++// { dg-final { regexp-test siter {ref = @0x.*} } }
++
++  std::vector<C> v;
++  v.push_back(c);
++  std::vector<C>::iterator viter = v.begin();
++// { dg-final { regexp-test viter {ref = @0x.*} } }
++
++  std::cout << "\n";
++  return 0;			// Mark SPOT
++}
++// { dg-final { gdb-test SPOT } }
+Index: libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/libstdc++-prettyprinters/simple.cc	(.../branches/gcc-6-branch)
+@@ -30,6 +30,7 @@
+ #include <list>
+ #include <map>
+ #include <set>
++#include <vector>
+ #include <ext/slist>
+ 
+ int
+@@ -50,6 +51,9 @@
+   deq.push_back("two");
+ // { dg-final { note-test deq {std::deque with 2 elements = {"one", "two"}} } }
+ 
++  std::deque<int>::iterator deqiter0;
++// { dg-final { note-test deqiter0 {non-dereferenceable iterator for std::deque} } }
++
+   std::deque<std::string>::iterator deqiter = deq.begin();
+ // { dg-final { note-test deqiter {"one"} } }
+ 
+@@ -58,6 +62,9 @@
+   lst.push_back("two");
+ // { dg-final { note-test lst {std::list = {[0] = "one", [1] = "two"}} } }
+ 
++  std::list<int>::iterator lstiter0;
++// { dg-final { note-test lstiter0 {non-dereferenceable iterator for std::list} } }
++
+   std::list<std::string>::iterator lstiter = lst.begin();
+   tem = *lstiter;
+ // { dg-final { note-test lstiter {"one"}} }
+@@ -73,6 +80,9 @@
+   std::map<std::string, int>::iterator mpiter = mp.begin();
+ // { dg-final { note-test mpiter {{first = "zardoz", second = 23}} } }
+ 
++  std::map<std::string, int>::iterator mpiter0;
++// { dg-final { note-test mpiter0 {non-dereferenceable iterator for associative container} } }
++
+   // PR 67440
+   std::set<int> intset;
+   intset.insert(2);
+@@ -88,6 +98,20 @@
+   std::set<std::string>::const_iterator spciter = sp.begin();
+ // { dg-final { note-test spciter {"barrel"} } }
+ 
++  std::set<int>::iterator spiter0;
++// { dg-final { note-test spiter0 {non-dereferenceable iterator for associative container} } }
++
++  std::vector<int> v;
++  v.push_back(1);
++  v.push_back(2);
++  v.erase(v.begin());
++// { dg-final { note-test v {std::vector of length 1, capacity 2 = {2}} } }
++  std::vector<int>::iterator viter3 = v.begin();
++// { dg-final { note-test viter3 {2} } }
++
++  std::vector<int>::iterator viter0;
++// { dg-final { note-test viter0 {non-dereferenceable iterator for std::vector} } }
++
+   __gnu_cxx::slist<int> sll;
+   sll.push_front(23);
+   sll.push_front(47);
+@@ -96,6 +120,9 @@
+   __gnu_cxx::slist<int>::iterator slliter = sll.begin();
+ // { dg-final { note-test slliter {47} } }
+ 
++  __gnu_cxx::slist<int>::iterator slliter0;
++// { dg-final { note-test slliter0 {non-dereferenceable iterator for __gnu_cxx::slist} } }
++
+   std::cout << "\n";
+   return 0;			// Mark SPOT
+ }
+Index: libstdc++-v3/testsuite/30_threads/thread/cons/lwg2097.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/lwg2097.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/lwg2097.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,29 @@
++// { dg-do compile { target c++11 } }
++// { dg-require-cstdint "" }
++// { dg-require-gthreads "" }
++
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <thread>
++
++using std::thread;
++using std::is_constructible;
++
++static_assert( !is_constructible<thread, thread&>::value, "" );
++static_assert( !is_constructible<thread, const thread&>::value, "" );
++static_assert( !is_constructible<thread, const thread>::value, "" );
+Index: libstdc++-v3/testsuite/29_atomics/atomic/69301.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/29_atomics/atomic/69301.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/29_atomics/atomic/69301.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,57 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++11 } }
++// { dg-require-atomic-builtins "" }
++
++#include <atomic>
++#include <testsuite_hooks.h>
++
++struct NonDefaultConstructible
++{
++  NonDefaultConstructible(int i) : val(i) { }
++  int val;
++};
++
++template class std::atomic<NonDefaultConstructible>;
++
++void
++test01()
++{
++  std::atomic<NonDefaultConstructible> a(1);
++  const auto n1 = a.exchange(2);
++  VERIFY( n1.val == 1 );
++  const auto n2 = a.load();
++  VERIFY( n2.val == 2 );
++}
++
++void
++test02()
++{
++  volatile std::atomic<NonDefaultConstructible> a(1);
++  const auto n1 = a.exchange(2);
++  VERIFY( n1.val == 1 );
++  const auto n2 = a.load();
++  VERIFY( n2.val == 2 );
++}
++
++int
++main()
++{
++  test01();
++  test02();
++}
+Index: libstdc++-v3/testsuite/23_containers/multimap/operations/2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/multimap/operations/2.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/multimap/operations/2.cc	(.../branches/gcc-6-branch)
+@@ -53,7 +53,7 @@
+   cit = cx.find(2L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ 
+   static_assert(std::is_same<decltype(it), test_type::iterator>::value,
+       "find returns iterator");
+@@ -76,7 +76,7 @@
+   cn = cx.count(2L);
+   VERIFY( cn == 0 );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ }
+ 
+ void
+@@ -94,7 +94,12 @@
+   cit = cx.lower_bound(2L);
+   VERIFY( cit != cx.end() && cit->second == '4' );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "lower_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const lower_bound returns const_iterator");
+ }
+ 
+ void
+@@ -112,7 +117,12 @@
+   cit = cx.upper_bound(3L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "upper_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const upper_bound returns const_iterator");
+ }
+ 
+ void
+@@ -131,7 +141,14 @@
+   cit = cx.equal_range(2L);
+   VERIFY( cit.first == cit.second && cit.first != cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  using pair = std::pair<test_type::iterator, test_type::iterator>;
++  static_assert(std::is_same<decltype(it), pair>::value,
++      "equal_range returns pair<iterator, iterator>");
++  using cpair = std::pair<test_type::const_iterator, test_type::const_iterator>;
++  static_assert(std::is_same<decltype(cit), cpair>::value,
++      "const equal_range returns pair<const_iterator, const_iterator>");
+ }
+ 
+ 
+Index: libstdc++-v3/testsuite/23_containers/set/operations/2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/set/operations/2.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/set/operations/2.cc	(.../branches/gcc-6-branch)
+@@ -53,7 +53,7 @@
+   cit = cx.find(2L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ 
+   static_assert(std::is_same<decltype(it), test_type::iterator>::value,
+       "find returns iterator");
+@@ -76,7 +76,7 @@
+   cn = cx.count(2L);
+   VERIFY( cn == 0 );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ }
+ 
+ void
+@@ -94,7 +94,12 @@
+   cit = cx.lower_bound(2L);
+   VERIFY( cit != cx.end() && *cit == 3 );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "lower_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const lower_bound returns const_iterator");
+ }
+ 
+ void
+@@ -112,7 +117,12 @@
+   cit = cx.upper_bound(5L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "upper_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const upper_bound returns const_iterator");
+ }
+ 
+ void
+@@ -130,7 +140,14 @@
+   cit = cx.equal_range(2L);
+   VERIFY( cit.first == cit.second && cit.first != cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  using pair = std::pair<test_type::iterator, test_type::iterator>;
++  static_assert(std::is_same<decltype(it), pair>::value,
++      "equal_range returns pair<iterator, iterator>");
++  using cpair = std::pair<test_type::const_iterator, test_type::const_iterator>;
++  static_assert(std::is_same<decltype(cit), cpair>::value,
++      "const equal_range returns pair<const_iterator, const_iterator>");
+ }
+ 
+ void
+@@ -150,6 +167,28 @@
+   s.find(i);
+ }
+ 
++void
++test07()
++{
++  // PR libstdc++/78273
++
++  struct C {
++    bool operator()(int l, int r) const { return l < r; }
++
++    struct Partition { };
++
++    bool operator()(int l, Partition) const { return l < 2; }
++    bool operator()(Partition, int r) const { return 4 < r; }
++
++    using is_transparent = void;
++  };
++
++  std::set<int, C> s{ 1, 2, 3, 4, 5 };
++
++  auto n = s.count(C::Partition{});
++  VERIFY( n == 3 );
++}
++
+ int
+ main()
+ {
+@@ -159,4 +198,5 @@
+   test04();
+   test05();
+   test06();
++  test07();
+ }
+Index: libstdc++-v3/testsuite/23_containers/multiset/operations/2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/multiset/operations/2.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/multiset/operations/2.cc	(.../branches/gcc-6-branch)
+@@ -53,7 +53,7 @@
+   cit = cx.find(2L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ 
+   static_assert(std::is_same<decltype(it), test_type::iterator>::value,
+       "find returns iterator");
+@@ -76,7 +76,7 @@
+   cn = cx.count(2L);
+   VERIFY( cn == 0 );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ }
+ 
+ void
+@@ -94,7 +94,12 @@
+   cit = cx.lower_bound(2L);
+   VERIFY( cit != cx.end() && *cit == 3 );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "lower_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const lower_bound returns const_iterator");
+ }
+ 
+ void
+@@ -112,7 +117,12 @@
+   cit = cx.upper_bound(5L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "upper_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const upper_bound returns const_iterator");
+ }
+ 
+ void
+@@ -131,7 +141,14 @@
+   cit = cx.equal_range(2L);
+   VERIFY( cit.first == cit.second && cit.first != cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  using pair = std::pair<test_type::iterator, test_type::iterator>;
++  static_assert(std::is_same<decltype(it), pair>::value,
++      "equal_range returns pair<iterator, iterator>");
++  using cpair = std::pair<test_type::const_iterator, test_type::const_iterator>;
++  static_assert(std::is_same<decltype(cit), cpair>::value,
++      "const equal_range returns pair<const_iterator, const_iterator>");
+ }
+ 
+ 
+Index: libstdc++-v3/testsuite/23_containers/list/operations/80034.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/list/operations/80034.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/list/operations/80034.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,32 @@
++// { dg-do compile }
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <list>
++
++namespace X {
++  struct Y { };
++  bool operator<(Y, Y) { return false; }
++  template<typename T>
++    void distance(T, T) { }
++}
++
++int main()
++{
++  std::list<X::Y> l;
++  l.sort();
++}
+Index: libstdc++-v3/testsuite/23_containers/list/operations/78389.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/list/operations/78389.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/list/operations/78389.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,74 @@
++// { dg-do run { target c++11 } }
++
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// 23.2.2.4 list operations [lib.list.ops]
++
++#include <testsuite_hooks.h>
++
++#include <list>
++
++struct ThrowingComparator
++{
++    unsigned int throw_after = 0;
++    unsigned int count = 0;
++    bool operator()(int, int) {
++        if (++count >= throw_after) {
++            throw 666;
++        }
++        return true;
++    }
++};
++
++struct X
++{
++  X() = default;
++  X(int) {}
++};
++
++unsigned int throw_after_X = 0;
++unsigned int count_X = 0;
++
++bool operator<(const X&, const X&) {
++  if (++count_X >= throw_after_X) {
++    throw 666;
++  }
++  return true;
++}
++
++
++int main()
++{
++    std::list<int> a{1, 2, 3, 4};
++    std::list<int> b{5, 6, 7, 8, 9, 10, 11, 12};
++    try {
++        a.merge(b, ThrowingComparator{4});
++    } catch (...) {
++    }
++    VERIFY(a.size() == std::distance(a.begin(), a.end()) &&
++	   b.size() == std::distance(b.begin(), b.end()));
++    std::list<X> ax{1, 2, 3, 4};
++    std::list<X> bx{5, 6, 7, 8, 9, 10, 11, 12};
++    throw_after_X = 4;
++    try {
++        ax.merge(bx);
++    } catch (...) {
++    }
++    VERIFY(ax.size() == std::distance(ax.begin(), ax.end()) &&
++	   bx.size() == std::distance(bx.begin(), bx.end()));
++}
+Index: libstdc++-v3/testsuite/23_containers/map/operations/2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/map/operations/2.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/map/operations/2.cc	(.../branches/gcc-6-branch)
+@@ -53,7 +53,7 @@
+   cit = cx.find(2L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ 
+   static_assert(std::is_same<decltype(it), test_type::iterator>::value,
+       "find returns iterator");
+@@ -76,7 +76,7 @@
+   cn = cx.count(2L);
+   VERIFY( cn == 0 );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
+ }
+ 
+ void
+@@ -94,7 +94,12 @@
+   cit = cx.lower_bound(2L);
+   VERIFY( cit != cx.end() && cit->second == '4' );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "lower_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const lower_bound returns const_iterator");
+ }
+ 
+ void
+@@ -112,7 +117,12 @@
+   cit = cx.upper_bound(3L);
+   VERIFY( cit == cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  static_assert(std::is_same<decltype(it), test_type::iterator>::value,
++      "upper_bound returns iterator");
++  static_assert(std::is_same<decltype(cit), test_type::const_iterator>::value,
++      "const upper_bound returns const_iterator");
+ }
+ 
+ void
+@@ -130,10 +140,38 @@
+   cit = cx.equal_range(2L);
+   VERIFY( cit.first == cit.second && cit.first != cx.end() );
+ 
+-  VERIFY( Cmp::count == 0);
++  VERIFY( Cmp::count == 0 );
++
++  using pair = std::pair<test_type::iterator, test_type::iterator>;
++  static_assert(std::is_same<decltype(it), pair>::value,
++      "equal_range returns pair<iterator, iterator>");
++  using cpair = std::pair<test_type::const_iterator, test_type::const_iterator>;
++  static_assert(std::is_same<decltype(cit), cpair>::value,
++      "const equal_range returns pair<const_iterator, const_iterator>");
+ }
+ 
++void
++test06()
++{
++  // PR libstdc++/78273
+ 
++  struct C {
++    bool operator()(int l, int r) const { return l < r; }
++
++    struct Partition { };
++
++    bool operator()(int l, Partition) const { return l < 2; }
++    bool operator()(Partition, int r) const { return 4 < r; }
++
++    using is_transparent = void;
++  };
++
++  std::map<int, int, C> m{ {1,0}, {2,0}, {3,0}, {4, 0}, {5, 0} };
++
++  auto n = m.count(C::Partition{});
++  VERIFY( n == 3 );
++}
++
+ int
+ main()
+ {
+@@ -142,4 +180,5 @@
+   test03();
+   test04();
+   test05();
++  test06();
+ }
+Index: libstdc++-v3/testsuite/21_strings/basic_string/allocator/wchar_t/copy_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/21_strings/basic_string/allocator/wchar_t/copy_assign.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/21_strings/basic_string/allocator/wchar_t/copy_assign.cc	(.../branches/gcc-6-branch)
+@@ -1,4 +1,4 @@
+-// Copyright (C) 2015-2016 Free Software Foundation, Inc.
++// Copyright (C) 2015-2017 Free Software Foundation, Inc.
+ //
+ // This file is part of the GNU ISO C++ Library.  This library is free
+ // software; you can redistribute it and/or modify it under the
+@@ -20,6 +20,7 @@
+ #include <string>
+ #include <testsuite_hooks.h>
+ #include <testsuite_allocator.h>
++#include <ext/throw_allocator.h>
+  
+ #if _GLIBCXX_USE_CXX11_ABI
+ using C = wchar_t;
+@@ -100,10 +101,44 @@
+   VERIFY(1 == v5.get_allocator().get_personality());
+ }
+ 
++void test03()
++{
++  // PR libstdc++/79254
++  using throw_alloc = __gnu_cxx::throw_allocator_limit<C>;
++  typedef propagating_allocator<C, true, throw_alloc> alloc_type;
++  typedef std::basic_string<C, traits, alloc_type> test_type;
++  alloc_type a1(1), a2(2);
++  throw_alloc::set_limit(2); // Throw on third allocation (during assignment).
++  const C* s1 = L"a string that is longer than a small string";
++  const C* s2 = L"another string that is longer than a small string";
++  test_type v1(s1, a1);
++  test_type v2(s2, a2);
++  bool caught = false;
++  try {
++    v1 = v2;
++  } catch (__gnu_cxx::forced_error&) {
++    caught = true;
++  }
++  VERIFY( caught );
++  VERIFY( v1 == s1 );
++  VERIFY( v1.get_allocator() == a1 );
++
++  throw_alloc::set_limit(1); // Allow one more allocation (and no more).
++  test_type v3(s1, a1);
++  // No allocation when allocators are equal and capacity is sufficient:
++  VERIFY( v1.capacity() >= v3.size() );
++  v1 = v3;
++  // No allocation when the contents fit in the small-string buffer:
++  v2 = L"sso";
++  v1 = v2;
++  VERIFY( v1.get_allocator() == a2 );
++}
++
+ int main()
+ {
+   test01();
+   test02();
++  test03();
+   return 0;
+ }
+ #else
+Index: libstdc++-v3/testsuite/21_strings/basic_string/allocator/char/copy_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/21_strings/basic_string/allocator/char/copy_assign.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/21_strings/basic_string/allocator/char/copy_assign.cc	(.../branches/gcc-6-branch)
+@@ -1,4 +1,4 @@
+-// Copyright (C) 2015-2016 Free Software Foundation, Inc.
++// Copyright (C) 2015-2017 Free Software Foundation, Inc.
+ //
+ // This file is part of the GNU ISO C++ Library.  This library is free
+ // software; you can redistribute it and/or modify it under the
+@@ -20,6 +20,7 @@
+ #include <string>
+ #include <testsuite_hooks.h>
+ #include <testsuite_allocator.h>
++#include <ext/throw_allocator.h>
+  
+ #if _GLIBCXX_USE_CXX11_ABI
+ using C = char;
+@@ -100,10 +101,44 @@
+   VERIFY(1 == v5.get_allocator().get_personality());
+ }
+ 
++void test03()
++{
++  // PR libstdc++/79254
++  using throw_alloc = __gnu_cxx::throw_allocator_limit<C>;
++  typedef propagating_allocator<C, true, throw_alloc> alloc_type;
++  typedef std::basic_string<C, traits, alloc_type> test_type;
++  alloc_type a1(1), a2(2);
++  throw_alloc::set_limit(2); // Throw on third allocation (during assignment).
++  const C* s1 = "a string that is longer than a small string";
++  const C* s2 = "another string that is longer than a small string";
++  test_type v1(s1, a1);
++  test_type v2(s2, a2);
++  bool caught = false;
++  try {
++    v1 = v2;
++  } catch (__gnu_cxx::forced_error&) {
++    caught = true;
++  }
++  VERIFY( caught );
++  VERIFY( v1 == s1 );
++  VERIFY( v1.get_allocator() == a1 );
++
++  throw_alloc::set_limit(1); // Allow one more allocation (and no more).
++  test_type v3(s1, a1);
++  // No allocation when allocators are equal and capacity is sufficient:
++  VERIFY( v1.capacity() >= v3.size() );
++  v1 = v3;
++  // No allocation when the contents fit in the small-string buffer:
++  v2 = "sso";
++  v1 = v2;
++  VERIFY( v1.get_allocator() == a2 );
++}
++
+ int main()
+ {
+   test01();
+   test02();
++  test03();
+   return 0;
+ }
+ #else
+Index: libstdc++-v3/testsuite/experimental/any/misc/any_cast.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/any/misc/any_cast.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/any/misc/any_cast.cc	(.../branches/gcc-6-branch)
+@@ -106,9 +106,22 @@
+   MoveDeleted&& md3 = any_cast<MoveDeleted&&>(any(std::move(md)));
+ }
+ 
++void test04()
++{
++  // PR libstdc++/69321
++  struct noncopyable {
++    noncopyable(noncopyable const&) = delete;
++  };
++
++  any a;
++  auto p = any_cast<noncopyable>(&a);
++  VERIFY( p == nullptr );
++}
++
+ int main()
+ {
+   test01();
+   test02();
+   test03();
++  test04();
+ }
+Index: libstdc++-v3/testsuite/experimental/array/make_array.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/array/make_array.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/array/make_array.cc	(.../branches/gcc-6-branch)
+@@ -1,7 +1,6 @@
+-// { dg-options "-std=gnu++14" }
+-// { dg-do compile }
++// { dg-do compile { target c++14 } }
+ 
+-// Copyright (C) 2015-2016 Free Software Foundation, Inc.
++// Copyright (C) 2015-2017 Free Software Foundation, Inc.
+ //
+ // This file is part of the GNU ISO C++ Library.  This library is free
+ // software; you can redistribute it and/or modify it under the
+@@ -19,6 +18,7 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include <experimental/array>
++#include <functional> // for std::ref and std::reference_wrapper
+ 
+ struct MoveOnly
+ {
+@@ -27,7 +27,7 @@
+   MoveOnly& operator=(MoveOnly&&) = default;
+ };
+ 
+-int main()
++void test01()
+ {
+   char x[42];
+   std::array<char, 42> y = std::experimental::to_array(x);
+@@ -45,3 +45,13 @@
+     = std::experimental::make_array(1,2L, 3);
+   constexpr std::array<MoveOnly, 1> zzz2 = std::experimental::make_array(MoveOnly{});
+ }
++
++void test02()
++{
++  // PR libstdc++/79195
++  struct A {};
++  struct B : A {};
++  struct C : A {};
++  auto arr = std::experimental::make_array<A>(B{}, C{});
++  static_assert(std::is_same<decltype(arr), std::array<A, 2>>::value, "");
++}
+Index: libstdc++-v3/testsuite/17_intro/names.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/17_intro/names.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/17_intro/names.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,110 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile }
++
++// Define macros for some common variables names that we must not use for
++// naming variables, parameters etc. in the library.
++#define tmp (
++#define A (
++#define B (
++#define C (
++#define D (
++#define E (
++#define F (
++#define G (
++#define H (
++#define I (
++#define J (
++#define K (
++#define L (
++#define M (
++#define N (
++#define O (
++#define P (
++#define Q (
++#define R (
++#define S (
++#define T (
++#define U (
++#define V (
++#define W (
++#define X (
++#define Y (
++#define Z (
++#if __cplusplus >= 201103L
++// <random> defines member functions called a() and b()
++#else
++#define a (
++#define b (
++#endif
++// <queue> and <stack> defined data members called c
++#define d (
++#define e (
++#define f (
++#define g (
++#if __cplusplus >= 201402L
++// <chrono> defines operator ""h in C++14
++// <complex> defines operator ""i in C++14
++#else
++#define h (
++#define i (
++#endif
++#define j (
++#if __cplusplus >= 201103L
++// <random> defines member functions called k()
++#else
++#define k (
++#endif
++#define l (
++#if __cplusplus >= 201103L
++// <random> defines member functions called m() and n()
++#else
++#define m (
++#define n (
++#endif
++#define o (
++#if __cplusplus >= 201103L
++// <random> defines member functions called p()
++#else
++#define p (
++#endif
++#define q (
++#define r (
++#if __cplusplus >= 201103L
++// <random> defines member functions called s() and t()
++// <chrono> and <string> define operator ""s in C++14
++#else
++#define s (
++#define t (
++#endif
++#define u (
++#define v (
++#define w (
++#define x (
++#define y (
++#define z (
++
++#ifdef _AIX
++// See https://gcc.gnu.org/ml/libstdc++/2017-03/msg00015.html
++#undef f
++#undef r
++#undef x
++#undef y
++#endif
++
++#include <bits/stdc++.h>
+Index: libstdc++-v3/testsuite/libstdc++-xmethods/shared_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/libstdc++-xmethods/shared_ptr.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/libstdc++-xmethods/shared_ptr.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,52 @@
++// { dg-do run { target c++11 } }
++// { dg-options "-g -O0" }
++
++// Copyright (C) 2016 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <memory>
++
++struct x_struct
++{
++  int y;
++};
++
++int
++main ()
++{
++  std::shared_ptr<int> p(new int(10));
++
++  std::shared_ptr<x_struct> q(new x_struct{23});
++
++// { dg-final { note-test *p 10 } }
++// { dg-final { regexp-test p.get() 0x.* } }
++
++// { dg-final { whatis-test *p int } }
++// { dg-final { whatis-test p.get() "int \*" } }
++
++// { dg-final { note-test *q {\{y = 23\}} } }
++// { dg-final { regexp-test q.get() 0x.* } }
++// { dg-final { note-test q->y 23 } }
++
++// { dg-final { whatis-test *q x_struct } }
++// { dg-final { whatis-test q.get() "x_struct \*" } }
++// { dg-final { whatis-test q->y int } }
++
++  return 0;  // Mark SPOT
++}
++
++// { dg-final { gdb-test SPOT {} 1 } }
+Index: libstdc++-v3/testsuite/libstdc++-xmethods/unique_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/libstdc++-xmethods/unique_ptr.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/libstdc++-xmethods/unique_ptr.cc	(.../branches/gcc-6-branch)
+@@ -28,14 +28,12 @@
+ int
+ main ()
+ {
+-  int *i = new int;
+-  *i = 10;
+-  std::unique_ptr<int> p(i);
++  std::unique_ptr<int> p(new int(10));
+ 
+-  x_struct *x = new x_struct;
+-  x->y = 23;
+-  std::unique_ptr<x_struct> q(x);
++  std::unique_ptr<x_struct> q(new x_struct{23});
+ 
++  std::unique_ptr<x_struct[]> r(new x_struct[2]{ {46}, {69} });
++
+ // { dg-final { note-test *p 10 } }
+ // { dg-final { regexp-test p.get() 0x.* } }
+ 
+@@ -50,6 +48,15 @@
+ // { dg-final { whatis-test q.get() "x_struct \*" } }
+ // { dg-final { whatis-test q->y int } }
+ 
++// { dg-final { note-test r\[1] {\{y = 69\}} } }
++// { dg-final { regexp-test r.get() 0x.* } }
++// { dg-final { note-test r\[1].y 69 } }
++
++// { dg-final { whatis-test r\[1] x_struct } }
++// { dg-final { whatis-test r.get() "x_struct \*" } }
++// { dg-final { whatis-test r\[1].y int } }
++
++
+   return 0;  // Mark SPOT
+ }
+ 
+Index: libstdc++-v3/testsuite/util/testsuite_allocator.h
+===================================================================
+--- a/src/libstdc++-v3/testsuite/util/testsuite_allocator.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/util/testsuite_allocator.h	(.../branches/gcc-6-branch)
+@@ -287,7 +287,7 @@
+ 
+       Alloc& base() { return *this; }
+       const Alloc& base() const  { return *this; }
+-      void swap_base(Alloc& b) { swap(b, this->base()); }
++      void swap_base(Alloc& b) { using std::swap; swap(b, this->base()); }
+ 
+     public:
+       typedef typename check_consistent_alloc_value_type<Tp, Alloc>::value_type
+Index: libstdc++-v3/testsuite/20_util/allocator_traits/members/rebind_alloc.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/allocator_traits/members/rebind_alloc.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/allocator_traits/members/rebind_alloc.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,81 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++
++#include <memory>
++
++using std::is_same;
++
++template<typename T, typename U>
++  using Rebind = typename std::allocator_traits<T>::template rebind_alloc<U>;
++
++template<typename T>
++  struct HasRebind {
++    using value_type = T;
++    template<typename U> struct rebind { using other = std::allocator<U>; };
++  };
++
++static_assert(is_same<Rebind<HasRebind<int>, long>,
++		      std::allocator<long>>::value,
++	      "nested alias template is used");
++
++template<typename T>
++  struct NoRebind0 {
++    using value_type = T;
++  };
++
++static_assert(is_same<Rebind<NoRebind0<int>, long>,
++		      NoRebind0<long>>::value,
++	      "first template argument is replaced");
++
++template<typename T, typename>
++  struct NoRebind1 {
++    using value_type = T;
++  };
++
++static_assert(is_same<Rebind<NoRebind1<int, void>, long>,
++		      NoRebind1<long, void>>::value,
++	      "first template argument is replaced");
++
++template<typename T, typename, typename>
++  struct NoRebind2 {
++    using value_type = T;
++  };
++
++static_assert(is_same<Rebind<NoRebind2<int, void, void>, long>,
++		      NoRebind2<long, void, void>>::value,
++	      "first template argument is replaced");
++
++template<typename T, typename...>
++  struct NoRebindN {
++    using value_type = T;
++  };
++
++static_assert(is_same<Rebind<NoRebindN<int>, long>,
++		      NoRebindN<long>>::value,
++	      "first template argument is replaced");
++static_assert(is_same<Rebind<NoRebindN<int, void>, long>,
++		      NoRebindN<long, void>>::value,
++	      "first template argument is replaced");
++
++template<typename T, int = 0>
++  struct CannotRebind {
++    using value_type = T;
++  };
++// PR libstdc++/72792 specialization of allocator_traits is still well-formed:
++std::allocator_traits<CannotRebind<int>>::value_type v;
+Index: libstdc++-v3/testsuite/20_util/allocator_traits/members/pointers.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/allocator_traits/members/pointers.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/allocator_traits/members/pointers.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,52 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++
++#include <memory>
++
++// Non-type template param means pointer_traits::rebind can't be instantiated.
++template<typename T, int = 0>
++  struct Pointer
++  {
++    using element_type = T;
++    Pointer(T* p = nullptr) : ptr(p) { }
++    T* ptr;
++  };
++
++template<typename T>
++  struct Alloc
++  {
++    using value_type = T;
++    using pointer = Pointer<T>;
++    using const_pointer = Pointer<const T>;
++    using void_pointer = Pointer<void>;
++    using const_void_pointer = Pointer<const void>;
++
++    pointer allocate(std::size_t n)
++    { return std::allocator<T>().allocate(n); }
++
++    void allocate(pointer p, std::size_t n)
++    { return std::allocator<T>().deallocate(p, n); }
++  };
++
++// The nested pointer types in Alloc should be found without attempting to
++// instantiate pointer_traits::rebind (which would fail):
++std::allocator_traits<Alloc<int>>::pointer p;
++std::allocator_traits<Alloc<int>>::const_pointer cp;
++std::allocator_traits<Alloc<int>>::void_pointer vp;
++std::allocator_traits<Alloc<int>>::const_void_pointer cvp;
+Index: libstdc++-v3/testsuite/20_util/pointer_traits/rebind.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/pointer_traits/rebind.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/pointer_traits/rebind.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,68 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++
++#include <memory>
++
++using std::is_same;
++
++template<typename T, typename U>
++  using Rebind = typename std::pointer_traits<T>::template rebind<U>;
++
++template<typename T>
++  struct HasRebind {
++    template<typename U> using rebind = U*;
++  };
++
++static_assert(is_same<Rebind<HasRebind<int>, long>,
++		      long*>::value,
++	      "nested alias template is used");
++
++template<typename T> struct NoRebind0 { };
++
++static_assert(is_same<Rebind<NoRebind0<int>, long>,
++		      NoRebind0<long>>::value,
++	      "first template argument is replaced");
++
++template<typename T, typename> struct NoRebind1 { };
++
++static_assert(is_same<Rebind<NoRebind1<int, void>, long>,
++		      NoRebind1<long, void>>::value,
++	      "first template argument is replaced");
++
++template<typename T, typename, typename> struct NoRebind2 { };
++
++static_assert(is_same<Rebind<NoRebind2<int, void, void>, long>,
++		      NoRebind2<long, void, void>>::value,
++	      "first template argument is replaced");
++
++template<typename T, typename...> struct NoRebindN { };
++
++static_assert(is_same<Rebind<NoRebindN<int>, long>,
++		      NoRebindN<long>>::value,
++	      "first template argument is replaced");
++static_assert(is_same<Rebind<NoRebindN<int, void>, long>,
++		      NoRebindN<long, void>>::value,
++	      "first template argument is replaced");
++
++template<typename T, int = 0>
++  struct CannotRebind {
++    using element_type = T;
++  };
++// PR libstdc++/72793 specialization of pointer_traits is still well-formed:
++std::pointer_traits<CannotRebind<int>>::element_type e;
+Index: libstdc++-v3/testsuite/20_util/tuple/cons/allocator_with_any.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/tuple/cons/allocator_with_any.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/tuple/cons/allocator_with_any.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,42 @@
++// { dg-do run { target c++14 } }
++
++// Copyright (C) 2016 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++
++// NOTE: This makes use of the fact that we know how moveable
++// is implemented on tuple.  If the implementation changed
++// this test may begin to fail.
++
++#include <tuple>
++#include <experimental/any>
++#include <testsuite_hooks.h>
++
++using std::experimental::any;
++
++void test01()
++{
++    std::tuple<any, any> t(std::allocator_arg,
++			   std::allocator<any>{});
++    VERIFY(std::get<0>(t).empty());
++    VERIFY(std::get<1>(t).empty());
++}
++
++int main()
++{
++    test01();
++}
+Index: libstdc++-v3/acinclude.m4
+===================================================================
+--- a/src/libstdc++-v3/acinclude.m4	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/acinclude.m4	(.../branches/gcc-6-branch)
+@@ -2304,7 +2304,8 @@
+       AC_MSG_CHECKING([for obsolete isnan function in <math.h>])
+         AC_CACHE_VAL(glibcxx_cv_obsolete_isnan, [
+           AC_COMPILE_IFELSE([AC_LANG_SOURCE(
+-            [#include <math.h>
++            [#define _GLIBCXX_INCLUDE_NEXT_C_HEADERS
++             #include <math.h>
+              #undef isnan
+              namespace std {
+                using ::isnan;
+Index: configure.ac
+===================================================================
+--- a/src/configure.ac	(.../tags/gcc_6_3_0_release)
++++ b/src/configure.ac	(.../branches/gcc-6-branch)
+@@ -819,6 +819,9 @@
+   *-*-vxworks*)
+     noconfigdirs="$noconfigdirs ${libgcj}"
+     ;;
++  aarch64*-*-freebsd*)
++    noconfigdirs="$noconfigdirs ${libgcj}"
++    ;;
+   alpha*-*-*vms*)
+     noconfigdirs="$noconfigdirs ${libgcj}"
+     ;;
+Index: ChangeLog
+===================================================================
+--- a/src/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,11 @@
++2017-01-09  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	Backport from mainline
++	2016-10-10  Andreas Tobler <andreast@gcc.gnu.org>
++
++	* configure.ac: Add aarch64-*-freebsd*.
++	* configure: Regenerate.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: libatomic/ChangeLog
+===================================================================
+--- a/src/libatomic/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/libatomic/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,11 @@
++2017-02-07  Szabolcs Nagy  <szabolcs.nagy@arm.com>
++
++	Backport from mainline:
++	2017-01-30  Szabolcs Nagy  <szabolcs.nagy@arm.com>
++
++	PR target/78945
++	* config/arm/exch_n.c (libat_exchange): Check __ARM_FEATURE_SIMD32.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: libatomic/config/arm/exch_n.c
+===================================================================
+--- a/src/libatomic/config/arm/exch_n.c	(.../tags/gcc_6_3_0_release)
++++ b/src/libatomic/config/arm/exch_n.c	(.../branches/gcc-6-branch)
+@@ -29,7 +29,7 @@
+ /* When using STREX to implement sub-word exchange, we can do much better
+    than the compiler by using the APSR.GE and APSR.C flags.  */
+ 
+-#if !DONE && HAVE_STREX && !HAVE_STREXBH && N == 2
++#if !DONE && __ARM_FEATURE_SIMD32 && HAVE_STREX && !HAVE_STREXBH && N == 2
+ UTYPE
+ SIZE(libat_exchange) (UTYPE *mptr, UTYPE newval, int smodel)
+ {
+@@ -79,7 +79,7 @@
+ #endif /* !HAVE_STREXBH && N == 2 */
+ 
+ 
+-#if !DONE && HAVE_STREX && !HAVE_STREXBH && N == 1
++#if !DONE && __ARM_FEATURE_SIMD32 && HAVE_STREX && !HAVE_STREXBH && N == 1
+ UTYPE
+ SIZE(libat_exchange) (UTYPE *mptr, UTYPE newval, int smodel)
+ {
+Index: config/ax_check_define.m4
+===================================================================
+--- a/src/config/ax_check_define.m4	(.../tags/gcc_6_3_0_release)
++++ b/src/config/ax_check_define.m4	(.../branches/gcc-6-branch)
+@@ -0,0 +1,92 @@
++# ===========================================================================
++#      http://www.gnu.org/software/autoconf-archive/ax_check_define.html
++# ===========================================================================
++#
++# SYNOPSIS
++#
++#   AC_CHECK_DEFINE([symbol], [ACTION-IF-FOUND], [ACTION-IF-NOT])
++#   AX_CHECK_DEFINE([includes],[symbol], [ACTION-IF-FOUND], [ACTION-IF-NOT])
++#
++# DESCRIPTION
++#
++#   Complements AC_CHECK_FUNC but it does not check for a function but for a
++#   define to exist. Consider a usage like:
++#
++#    AC_CHECK_DEFINE(__STRICT_ANSI__, CFLAGS="$CFLAGS -D_XOPEN_SOURCE=500")
++#
++# LICENSE
++#
++#   Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de>
++#
++#   This program is free software; you can redistribute it and/or modify it
++#   under the terms of the GNU General Public License as published by the
++#   Free Software Foundation; either version 3 of the License, or (at your
++#   option) any later version.
++#
++#   This program is distributed in the hope that it will be useful, but
++#   WITHOUT ANY WARRANTY; without even the implied warranty of
++#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
++#   Public License for more details.
++#
++#   You should have received a copy of the GNU General Public License along
++#   with this program. If not, see <http://www.gnu.org/licenses/>.
++#
++#   As a special exception, the respective Autoconf Macro's copyright owner
++#   gives unlimited permission to copy, distribute and modify the configure
++#   scripts that are the output of Autoconf when processing the Macro. You
++#   need not follow the terms of the GNU General Public License when using
++#   or distributing such scripts, even though portions of the text of the
++#   Macro appear in them. The GNU General Public License (GPL) does govern
++#   all other use of the material that constitutes the Autoconf Macro.
++#
++#   This special exception to the GPL applies to versions of the Autoconf
++#   Macro released by the Autoconf Archive. When you make and distribute a
++#   modified version of the Autoconf Macro, you may extend this special
++#   exception to the GPL to apply to your modified version as well.
++
++#serial 8
++
++AU_ALIAS([AC_CHECK_DEFINED], [AC_CHECK_DEFINE])
++AC_DEFUN([AC_CHECK_DEFINE],[
++AS_VAR_PUSHDEF([ac_var],[ac_cv_defined_$1])dnl
++AC_CACHE_CHECK([for $1 defined], ac_var,
++AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
++  #ifdef $1
++  int ok;
++  #else
++  choke me
++  #endif
++]])],[AS_VAR_SET(ac_var, yes)],[AS_VAR_SET(ac_var, no)]))
++AS_IF([test AS_VAR_GET(ac_var) != "no"], [$2], [$3])dnl
++AS_VAR_POPDEF([ac_var])dnl
++])
++
++AU_ALIAS([AX_CHECK_DEFINED], [AX_CHECK_DEFINE])
++AC_DEFUN([AX_CHECK_DEFINE],[
++AS_VAR_PUSHDEF([ac_var],[ac_cv_defined_$2_$1])dnl
++AC_CACHE_CHECK([for $2 defined in $1], ac_var,
++AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include <$1>]], [[
++  #ifdef $2
++  int ok;
++  #else
++  choke me
++  #endif
++]])],[AS_VAR_SET(ac_var, yes)],[AS_VAR_SET(ac_var, no)]))
++AS_IF([test AS_VAR_GET(ac_var) != "no"], [$3], [$4])dnl
++AS_VAR_POPDEF([ac_var])dnl
++])
++
++AC_DEFUN([AX_CHECK_FUNC],
++[AS_VAR_PUSHDEF([ac_var], [ac_cv_func_$2])dnl
++AC_CACHE_CHECK([for $2], ac_var,
++dnl AC_LANG_FUNC_LINK_TRY
++[AC_LINK_IFELSE([AC_LANG_PROGRAM([$1
++                #undef $2
++                char $2 ();],[
++                char (*f) () = $2;
++                return f != $2; ])],
++                [AS_VAR_SET(ac_var, yes)],
++                [AS_VAR_SET(ac_var, no)])])
++AS_IF([test AS_VAR_GET(ac_var) = yes], [$3], [$4])dnl
++AS_VAR_POPDEF([ac_var])dnl
++])# AC_CHECK_FUNC
+Index: config/ChangeLog
+===================================================================
+--- a/src/config/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/config/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,8 @@
++2017-01-24  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/78478
++	* ax_check_define.m4: New file.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: configure
+===================================================================
+--- a/src/configure	(.../tags/gcc_6_3_0_release)
++++ b/src/configure	(.../branches/gcc-6-branch)
+@@ -3483,6 +3483,9 @@
+   *-*-vxworks*)
+     noconfigdirs="$noconfigdirs ${libgcj}"
+     ;;
++  aarch64*-*-freebsd*)
++    noconfigdirs="$noconfigdirs ${libgcj}"
++    ;;
+   alpha*-*-*vms*)
+     noconfigdirs="$noconfigdirs ${libgcj}"
+     ;;
+Index: libgcc/config.host
+===================================================================
+--- a/src/libgcc/config.host	(.../tags/gcc_6_3_0_release)
++++ b/src/libgcc/config.host	(.../branches/gcc-6-branch)
+@@ -333,6 +333,11 @@
+ 	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+ 	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
+ 	;;
++aarch64*-*-freebsd*)
++	extra_parts="$extra_parts crtfastmath.o"
++	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
++	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
++	;;
+ aarch64*-*-linux*)
+ 	extra_parts="$extra_parts crtfastmath.o"
+ 	md_unwind_header=aarch64/linux-unwind.h
+Index: libgcc/ChangeLog
+===================================================================
+--- a/src/libgcc/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/libgcc/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,10 @@
++2017-01-09  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	Backport from mainline
++	2016-10-10  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	* config.host: Add support for aarch64-*-freebsd*.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/tree-vrp.c
+===================================================================
+--- a/src/gcc/tree-vrp.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-vrp.c	(.../branches/gcc-6-branch)
+@@ -2651,8 +2651,17 @@
+ 	    min = build_symbolic_expr (expr_type, sym_min_op0,
+ 				       neg_min_op0, min);
+ 	  else if (sym_min_op1)
+-	    min = build_symbolic_expr (expr_type, sym_min_op1,
+-				       neg_min_op1 ^ minus_p, min);
++	    {
++	      /* We may not negate if that might introduce
++		 undefined overflow.  */
++	      if (! minus_p
++		  || neg_min_op1
++		  || TYPE_OVERFLOW_WRAPS (expr_type))
++		min = build_symbolic_expr (expr_type, sym_min_op1,
++					   neg_min_op1 ^ minus_p, min);
++	      else
++		min = NULL_TREE;
++	    }
+ 
+ 	  /* Likewise for the upper bound.  */
+ 	  if (sym_max_op0 == sym_max_op1)
+@@ -2661,8 +2670,17 @@
+ 	    max = build_symbolic_expr (expr_type, sym_max_op0,
+ 				       neg_max_op0, max);
+ 	  else if (sym_max_op1)
+-	    max = build_symbolic_expr (expr_type, sym_max_op1,
+-				       neg_max_op1 ^ minus_p, max);
++	    {
++	      /* We may not negate if that might introduce
++		 undefined overflow.  */
++	      if (! minus_p
++		  || neg_max_op1
++		  || TYPE_OVERFLOW_WRAPS (expr_type))
++		max = build_symbolic_expr (expr_type, sym_max_op1,
++					   neg_max_op1 ^ minus_p, max);
++	      else
++		max = NULL_TREE;
++	    }
+ 	}
+       else
+ 	{
+@@ -7057,8 +7075,7 @@
+ static enum ssa_prop_result
+ vrp_visit_assignment_or_call (gimple *stmt, tree *output_p)
+ {
+-  tree def, lhs;
+-  ssa_op_iter iter;
++  tree lhs;
+   enum gimple_code code = gimple_code (stmt);
+   lhs = gimple_get_lhs (stmt);
+ 
+@@ -7175,8 +7192,7 @@
+       }
+ 
+   /* Every other statement produces no useful ranges.  */
+-  FOR_EACH_SSA_TREE_OPERAND (def, stmt, iter, SSA_OP_DEF)
+-    set_value_range_to_varying (get_value_range (def));
++  set_defs_to_varying (stmt);
+ 
+   return SSA_PROP_VARYING;
+ }
+Index: gcc/c-family/c-opts.c
+===================================================================
+--- a/src/gcc/c-family/c-opts.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/c-family/c-opts.c	(.../branches/gcc-6-branch)
+@@ -742,8 +742,13 @@
+       in_fnames[0] = "";
+     }
+   else if (strcmp (in_fnames[0], "-") == 0)
+-    in_fnames[0] = "";
++    {
++      if (pch_file)
++	error ("cannot use %<-%> as input filename for a precompiled header");
+ 
++      in_fnames[0] = "";
++    }
++
+   if (out_fname == NULL || !strcmp (out_fname, "-"))
+     out_fname = "";
+ 
+Index: gcc/c-family/ChangeLog
+===================================================================
+--- a/src/gcc/c-family/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/c-family/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,28 @@
++2017-03-14  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/79962
++	PR c++/79984
++	* c-common.c (handle_nonnull_attribute): Save the result of default
++	conversion to the attribute list.
++
++2017-03-14  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-03-02  Richard Biener  <rguenther@suse.de>
++
++	PR c/79756
++	* c-common.c (c_common_mark_addressable_vec): Look through
++	C_MAYBE_CONST_EXPR.
++
++2017-01-10  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-05  Martin Liska  <mliska@suse.cz>
++
++	PR pch/78970
++	* c-opts.c (c_common_post_options): Reject '-' filename for a precompiled
++	header.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/c-family/c-common.c
+===================================================================
+--- a/src/gcc/c-family/c-common.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/c-family/c-common.c	(.../branches/gcc-6-branch)
+@@ -9061,7 +9061,7 @@
+       tree arg = TREE_VALUE (args);
+       if (arg && TREE_CODE (arg) != IDENTIFIER_NODE
+ 	  && TREE_CODE (arg) != FUNCTION_DECL)
+-	arg = default_conversion (arg);
++	TREE_VALUE (args) = arg = default_conversion (arg);
+ 
+       if (!get_nonnull_operand (arg, &arg_num))
+ 	{
+@@ -10677,6 +10677,8 @@
+ void 
+ c_common_mark_addressable_vec (tree t)
+ {   
++  if (TREE_CODE (t) == C_MAYBE_CONST_EXPR)
++    t = C_MAYBE_CONST_EXPR_EXPR (t);
+   while (handled_component_p (t))
+     t = TREE_OPERAND (t, 0);
+   if (!VAR_P (t)
+Index: gcc/ipa-polymorphic-call.c
+===================================================================
+--- a/src/gcc/ipa-polymorphic-call.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ipa-polymorphic-call.c	(.../branches/gcc-6-branch)
+@@ -463,13 +463,13 @@
+   /* Check that type is within range.  */
+   if (offset < 0)
+     return false;
+-  if (TYPE_SIZE (outer_type) && TYPE_SIZE (otr_type)
+-      && TREE_CODE (TYPE_SIZE (outer_type)) == INTEGER_CST
+-      && TREE_CODE (TYPE_SIZE (otr_type)) == INTEGER_CST
+-      && wi::ltu_p (wi::to_offset (TYPE_SIZE (outer_type)),
+-		    (wi::to_offset (TYPE_SIZE (otr_type)) + offset)))
+-    return false;
+ 
++  /* PR ipa/71207
++     As OUTER_TYPE can be a type which has a diamond virtual inheritance,
++     it's not necessary that INNER_TYPE will fit within OUTER_TYPE with
++     a given offset.  It can happen that INNER_TYPE also contains a base object,
++     however it would point to the same instance in the OUTER_TYPE.  */
++
+   context.offset = offset;
+   context.outer_type = TYPE_MAIN_VARIANT (outer_type);
+   context.maybe_derived_type = false;
+Index: gcc/c/ChangeLog
+===================================================================
+--- a/src/gcc/c/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/c/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,18 @@
++2017-02-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-02-09  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/79431
++	* c-parser.c (c_parser_omp_declare_target): Don't invoke
++	symtab_node::get on automatic variables.
++
++2016-12-21  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/77767
++	* c-decl.c (grokdeclarator): If *expr is non-NULL, append expression
++	to *expr instead of overwriting it.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/c/c-parser.c
+===================================================================
+--- a/src/gcc/c/c-parser.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/c/c-parser.c	(.../branches/gcc-6-branch)
+@@ -15180,7 +15180,7 @@
+   if (context != pragma_stmt && context != pragma_compound)
+     {
+       c_parser_error (parser, "expected declaration specifiers");
+-      c_parser_skip_until_found (parser, CPP_PRAGMA_EOL, NULL);
++      c_parser_skip_to_pragma_eol (parser, false);
+       return false;
+     }
+ 
+@@ -16560,8 +16560,11 @@
+ 	}
+       if (!at1)
+ 	{
++	  DECL_ATTRIBUTES (t) = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (t));
++	  if (TREE_CODE (t) != FUNCTION_DECL && !is_global_var (t))
++	    continue;
++
+ 	  symtab_node *node = symtab_node::get (t);
+-	  DECL_ATTRIBUTES (t) = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (t));
+ 	  if (node != NULL)
+ 	    {
+ 	      node->offloadable = 1;
+Index: gcc/c/c-decl.c
+===================================================================
+--- a/src/gcc/c/c-decl.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/c/c-decl.c	(.../branches/gcc-6-branch)
+@@ -5400,11 +5400,21 @@
+   if (TREE_CODE (type) == ERROR_MARK)
+     return error_mark_node;
+   if (expr == NULL)
+-    expr = &expr_dummy;
++    {
++      expr = &expr_dummy;
++      expr_dummy = NULL_TREE;
++    }
+   if (expr_const_operands == NULL)
+     expr_const_operands = &expr_const_operands_dummy;
+ 
+-  *expr = declspecs->expr;
++  if (declspecs->expr)
++    {
++      if (*expr)
++	*expr = build2 (COMPOUND_EXPR, TREE_TYPE (declspecs->expr), *expr,
++			declspecs->expr);
++      else
++	*expr = declspecs->expr;
++    }
+   *expr_const_operands = declspecs->expr_const_operands;
+ 
+   if (decl_context == FUNCDEF)
+Index: gcc/DATESTAMP
+===================================================================
+--- a/src/gcc/DATESTAMP	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/DATESTAMP	(.../branches/gcc-6-branch)
+@@ -1 +1 @@
+-20161221
++20170316
+Index: gcc/postreload.c
+===================================================================
+--- a/src/gcc/postreload.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/postreload.c	(.../branches/gcc-6-branch)
+@@ -93,6 +93,11 @@
+   basic_block insn_bb = BLOCK_FOR_INSN (insn);
+   unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
+ 
++  /* If NO_FUNCTION_CSE has been set by the target, then we should not try
++     to cse function calls.  */
++  if (NO_FUNCTION_CSE && CALL_P (insn))
++    return false;
++
+   if (GET_CODE (body) == SET)
+     {
+       int count = 0;
+Index: gcc/value-prof.c
+===================================================================
+--- a/src/gcc/value-prof.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/value-prof.c	(.../branches/gcc-6-branch)
+@@ -1376,7 +1376,13 @@
+   gimple_call_set_fndecl (dcall_stmt, direct_call->decl);
+   dflags = flags_from_decl_or_type (direct_call->decl);
+   if ((dflags & ECF_NORETURN) != 0)
+-    gimple_call_set_lhs (dcall_stmt, NULL_TREE);
++    {
++      tree lhs = gimple_call_lhs (dcall_stmt);
++      if (lhs
++          && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (lhs))) == INTEGER_CST
++          && !TREE_ADDRESSABLE (TREE_TYPE (lhs)))
++	gimple_call_set_lhs (dcall_stmt, NULL_TREE);
++    }
+   gsi_insert_before (&gsi, dcall_stmt, GSI_SAME_STMT);
+ 
+   /* Fix CFG. */
+Index: gcc/tree-ssa-strlen.c
+===================================================================
+--- a/src/gcc/tree-ssa-strlen.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-ssa-strlen.c	(.../branches/gcc-6-branch)
+@@ -1834,6 +1834,9 @@
+ {
+   gimple *stmt = gsi_stmt (*gsi);
+   tree lhs = gimple_call_lhs (stmt);
++  if (lhs == NULL_TREE)
++    return;
++
+   gcc_assert (get_stridx (lhs) == 0);
+   int idx = new_stridx (lhs);
+   tree length = NULL_TREE;
+Index: gcc/tree.c
+===================================================================
+--- a/src/gcc/tree.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree.c	(.../branches/gcc-6-branch)
+@@ -1675,13 +1675,8 @@
+ bool
+ cst_and_fits_in_hwi (const_tree x)
+ {
+-  if (TREE_CODE (x) != INTEGER_CST)
+-    return false;
+-
+-  if (TYPE_PRECISION (TREE_TYPE (x)) > HOST_BITS_PER_WIDE_INT)
+-    return false;
+-
+-  return TREE_INT_CST_NUNITS (x) == 1;
++  return (TREE_CODE (x) == INTEGER_CST
++	  && (tree_fits_shwi_p (x) || tree_fits_uhwi_p (x)));
+ }
+ 
+ /* Build a newly constructed VECTOR_CST node of length LEN.  */
+Index: gcc/internal-fn.c
+===================================================================
+--- a/src/gcc/internal-fn.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/internal-fn.c	(.../branches/gcc-6-branch)
+@@ -1271,8 +1271,8 @@
+ 	  res = expand_expr_real_2 (&ops, NULL_RTX, wmode, EXPAND_NORMAL);
+ 	  rtx hipart = expand_shift (RSHIFT_EXPR, wmode, res, prec,
+ 				     NULL_RTX, uns);
+-	  hipart = gen_lowpart (mode, hipart);
+-	  res = gen_lowpart (mode, res);
++	  hipart = convert_modes (mode, wmode, hipart, uns);
++	  res = convert_modes (mode, wmode, res, uns);
+ 	  if (uns)
+ 	    /* For the unsigned multiplication, there was overflow if
+ 	       HIPART is non-zero.  */
+@@ -1305,8 +1305,8 @@
+ 	  unsigned int hprec = GET_MODE_PRECISION (hmode);
+ 	  rtx hipart0 = expand_shift (RSHIFT_EXPR, mode, op0, hprec,
+ 				      NULL_RTX, uns);
+-	  hipart0 = gen_lowpart (hmode, hipart0);
+-	  rtx lopart0 = gen_lowpart (hmode, op0);
++	  hipart0 = convert_modes (hmode, mode, hipart0, uns);
++	  rtx lopart0 = convert_modes (hmode, mode, op0, uns);
+ 	  rtx signbit0 = const0_rtx;
+ 	  if (!uns)
+ 	    signbit0 = expand_shift (RSHIFT_EXPR, hmode, lopart0, hprec - 1,
+@@ -1313,8 +1313,8 @@
+ 				     NULL_RTX, 0);
+ 	  rtx hipart1 = expand_shift (RSHIFT_EXPR, mode, op1, hprec,
+ 				      NULL_RTX, uns);
+-	  hipart1 = gen_lowpart (hmode, hipart1);
+-	  rtx lopart1 = gen_lowpart (hmode, op1);
++	  hipart1 = convert_modes (hmode, mode, hipart1, uns);
++	  rtx lopart1 = convert_modes (hmode, mode, op1, uns);
+ 	  rtx signbit1 = const0_rtx;
+ 	  if (!uns)
+ 	    signbit1 = expand_shift (RSHIFT_EXPR, hmode, lopart1, hprec - 1,
+@@ -1505,11 +1505,12 @@
+ 	     if (loxhi >> (bitsize / 2) == 0		 (if uns).  */
+ 	  rtx hipartloxhi = expand_shift (RSHIFT_EXPR, mode, loxhi, hprec,
+ 					  NULL_RTX, 0);
+-	  hipartloxhi = gen_lowpart (hmode, hipartloxhi);
++	  hipartloxhi = convert_modes (hmode, mode, hipartloxhi, 0);
+ 	  rtx signbitloxhi = const0_rtx;
+ 	  if (!uns)
+ 	    signbitloxhi = expand_shift (RSHIFT_EXPR, hmode,
+-					 gen_lowpart (hmode, loxhi),
++					 convert_modes (hmode, mode,
++							loxhi, 0),
+ 					 hprec - 1, NULL_RTX, 0);
+ 
+ 	  do_compare_rtx_and_jump (signbitloxhi, hipartloxhi, NE, true, hmode,
+@@ -1519,7 +1520,8 @@
+ 	  /* res = (loxhi << (bitsize / 2)) | (hmode) lo0xlo1;  */
+ 	  rtx loxhishifted = expand_shift (LSHIFT_EXPR, mode, loxhi, hprec,
+ 					   NULL_RTX, 1);
+-	  tem = convert_modes (mode, hmode, gen_lowpart (hmode, lo0xlo1), 1);
++	  tem = convert_modes (mode, hmode,
++			       convert_modes (hmode, mode, lo0xlo1, 1), 1);
+ 
+ 	  tem = expand_simple_binop (mode, IOR, loxhishifted, tem, res,
+ 				     1, OPTAB_DIRECT);
+Index: gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/gcc.c	(.../branches/gcc-6-branch)
+@@ -1919,6 +1919,9 @@
+ /* Was the option -o passed.  */
+ static int have_o = 0;
+ 
++/* Was the option -E passed.  */
++static int have_E = 0;
++
+ /* Pointer to output file name passed in with -o. */
+ static const char *output_file = 0;
+ 
+@@ -4031,6 +4034,10 @@
+       validated = true;
+       break;
+ 
++    case OPT_E:
++      have_E = true;
++      break;
++
+     case OPT_x:
+       spec_lang = arg;
+       if (!strcmp (spec_lang, "none"))
+@@ -7692,6 +7699,17 @@
+ 	  {
+ 	    for (int j = 0; sanitizer_opts[j].name != NULL; ++j)
+ 	      {
++		struct cl_option optb;
++		/* -fsanitize=all is not valid, only -fno-sanitize=all.
++		   So don't register the positive misspelling candidates
++		   for it.  */
++		if (sanitizer_opts[j].flag == ~0U && i == OPT_fsanitize_)
++		  {
++		    optb = *option;
++		    optb.opt_text = opt_text = "-fno-sanitize=";
++		    optb.cl_reject_negative = true;
++		    option = &optb;
++		  }
+ 		/* Get one arg at a time e.g. "-fsanitize=address".  */
+ 		char *with_arg = concat (opt_text,
+ 					 sanitizer_opts[j].name,
+@@ -8273,8 +8291,18 @@
+     {
+       for (cp = compilers + n_compilers - 1; cp >= compilers; cp--)
+ 	if (cp->suffix[0] == '@' && !strcmp (cp->suffix + 1, language))
+-	  return cp;
++	  {
++	    if (name != NULL && strcmp (name, "-") == 0
++		&& (strcmp (cp->suffix, "@c-header") == 0
++		    || strcmp (cp->suffix, "@c++-header") == 0)
++		&& !have_E)
++	      fatal_error (input_location,
++			   "cannot use %<-%> as input filename for a "
++			   "precompiled header");
+ 
++	    return cp;
++	  }
++
+       error ("language %s not recognized", language);
+       return 0;
+     }
+Index: gcc/fold-const.c
+===================================================================
+--- a/src/gcc/fold-const.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fold-const.c	(.../branches/gcc-6-branch)
+@@ -143,6 +143,7 @@
+ static tree fold_convert_const (enum tree_code, tree, tree);
+ static tree fold_view_convert_expr (tree, tree);
+ static bool vec_cst_ctor_to_array (tree, tree *);
++static tree fold_negate_expr (location_t, tree);
+ 
+ 
+ /* Return EXPR_LOCATION of T if it is not UNKNOWN_LOCATION.
+@@ -530,7 +531,7 @@
+    returned.  */
+ 
+ static tree
+-fold_negate_expr (location_t loc, tree t)
++fold_negate_expr_1 (location_t loc, tree t)
+ {
+   tree type = TREE_TYPE (t);
+   tree tem;
+@@ -541,7 +542,7 @@
+     case BIT_NOT_EXPR:
+       if (INTEGRAL_TYPE_P (type))
+         return fold_build2_loc (loc, PLUS_EXPR, type, TREE_OPERAND (t, 0),
+-                            build_one_cst (type));
++				build_one_cst (type));
+       break;
+ 
+     case INTEGER_CST:
+@@ -589,14 +590,14 @@
+     case COMPLEX_EXPR:
+       if (negate_expr_p (t))
+ 	return fold_build2_loc (loc, COMPLEX_EXPR, type,
+-			    fold_negate_expr (loc, TREE_OPERAND (t, 0)),
+-			    fold_negate_expr (loc, TREE_OPERAND (t, 1)));
++				fold_negate_expr (loc, TREE_OPERAND (t, 0)),
++				fold_negate_expr (loc, TREE_OPERAND (t, 1)));
+       break;
+ 
+     case CONJ_EXPR:
+       if (negate_expr_p (t))
+ 	return fold_build1_loc (loc, CONJ_EXPR, type,
+-			    fold_negate_expr (loc, TREE_OPERAND (t, 0)));
++				fold_negate_expr (loc, TREE_OPERAND (t, 0)));
+       break;
+ 
+     case NEGATE_EXPR:
+@@ -615,7 +616,7 @@
+ 	    {
+ 	      tem = negate_expr (TREE_OPERAND (t, 1));
+ 	      return fold_build2_loc (loc, MINUS_EXPR, type,
+-				  tem, TREE_OPERAND (t, 0));
++				      tem, TREE_OPERAND (t, 0));
+ 	    }
+ 
+ 	  /* -(A + B) -> (-A) - B.  */
+@@ -623,7 +624,7 @@
+ 	    {
+ 	      tem = negate_expr (TREE_OPERAND (t, 0));
+ 	      return fold_build2_loc (loc, MINUS_EXPR, type,
+-				  tem, TREE_OPERAND (t, 1));
++				      tem, TREE_OPERAND (t, 1));
+ 	    }
+ 	}
+       break;
+@@ -634,7 +635,7 @@
+ 	  && !HONOR_SIGNED_ZEROS (element_mode (type))
+ 	  && reorder_operands_p (TREE_OPERAND (t, 0), TREE_OPERAND (t, 1)))
+ 	return fold_build2_loc (loc, MINUS_EXPR, type,
+-			    TREE_OPERAND (t, 1), TREE_OPERAND (t, 0));
++				TREE_OPERAND (t, 1), TREE_OPERAND (t, 0));
+       break;
+ 
+     case MULT_EXPR:
+@@ -649,11 +650,11 @@
+ 	  tem = TREE_OPERAND (t, 1);
+ 	  if (negate_expr_p (tem))
+ 	    return fold_build2_loc (loc, TREE_CODE (t), type,
+-				TREE_OPERAND (t, 0), negate_expr (tem));
++				    TREE_OPERAND (t, 0), negate_expr (tem));
+ 	  tem = TREE_OPERAND (t, 0);
+ 	  if (negate_expr_p (tem))
+ 	    return fold_build2_loc (loc, TREE_CODE (t), type,
+-				negate_expr (tem), TREE_OPERAND (t, 1));
++				    negate_expr (tem), TREE_OPERAND (t, 1));
+ 	}
+       break;
+ 
+@@ -726,6 +727,19 @@
+   return NULL_TREE;
+ }
+ 
++/* A wrapper for fold_negate_expr_1.  */
++
++static tree
++fold_negate_expr (location_t loc, tree t)
++{
++  tree type = TREE_TYPE (t);
++  STRIP_SIGN_NOPS (t);
++  tree tem = fold_negate_expr_1 (loc, t);
++  if (tem == NULL_TREE)
++    return NULL_TREE;
++  return fold_convert_loc (loc, type, tem);
++}
++
+ /* Like fold_negate_expr, but return a NEGATE_EXPR tree, if T can not be
+    negated in a simpler way.  Also allow for T to be NULL_TREE, in which case
+    return NULL_TREE. */
+Index: gcc/omp-low.c
+===================================================================
+--- a/src/gcc/omp-low.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/omp-low.c	(.../branches/gcc-6-branch)
+@@ -19225,7 +19225,9 @@
+ static oacc_loop *
+ oacc_loop_discovery ()
+ {
+-  basic_block bb;
++  /* Clear basic block flags, in particular BB_VISITED which we're going to use
++     in the following.  */
++  clear_bb_flags ();
+   
+   oacc_loop *top = new_oacc_loop_outer (current_function_decl);
+   oacc_loop_discover_walk (top, ENTRY_BLOCK_PTR_FOR_FN (cfun));
+@@ -19234,9 +19236,8 @@
+      that diagnostics come out in an unsurprising order.  */
+   top = oacc_loop_sibling_nreverse (top);
+ 
+-  /* Reset the visited flags.  */
+-  FOR_ALL_BB_FN (bb, cfun)
+-    bb->flags &= ~BB_VISITED;
++  /* Clear basic block flags again.  */
++  clear_bb_flags ();
+ 
+   return top;
+ }
+@@ -19889,7 +19890,9 @@
+ {
+   tree t = *tp;
+ 
+-  if (TREE_CODE (t) == VAR_DECL && DECL_HAS_VALUE_EXPR_P (t)
++  if (TREE_CODE (t) == VAR_DECL
++      && DECL_HAS_VALUE_EXPR_P (t)
++      && is_global_var (t)
+       && lookup_attribute ("omp declare target link", DECL_ATTRIBUTES (t)))
+     {
+       *walk_subtrees = 0;
+Index: gcc/ipa-inline-transform.c
+===================================================================
+--- a/src/gcc/ipa-inline-transform.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ipa-inline-transform.c	(.../branches/gcc-6-branch)
+@@ -324,6 +324,8 @@
+   if (DECL_FUNCTION_PERSONALITY (callee->decl))
+     DECL_FUNCTION_PERSONALITY (to->decl)
+       = DECL_FUNCTION_PERSONALITY (callee->decl);
++
++  bool reload_optimization_node = false;
+   if (!opt_for_fn (callee->decl, flag_strict_aliasing)
+       && opt_for_fn (to->decl, flag_strict_aliasing))
+     {
+@@ -336,8 +338,13 @@
+ 		 to->name (), to->order);
+       DECL_FUNCTION_SPECIFIC_OPTIMIZATION (to->decl)
+ 	 = build_optimization_node (&opts);
++      reload_optimization_node = true;
+     }
+ 
++  /* Reload global optimization flags.  */
++  if (reload_optimization_node && DECL_STRUCT_FUNCTION (to->decl) == cfun)
++    set_cfun (cfun, true);
++
+   /* If aliases are involved, redirect edge to the actual destination and
+      possibly remove the aliases.  */
+   if (e->callee != callee)
+Index: gcc/tree-ssa-sccvn.c
+===================================================================
+--- a/src/gcc/tree-ssa-sccvn.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-ssa-sccvn.c	(.../branches/gcc-6-branch)
+@@ -1817,14 +1817,34 @@
+ 				    buffer, sizeof (buffer));
+ 	  if (len > 0)
+ 	    {
+-	      tree val = native_interpret_expr (vr->type,
++	      tree type = vr->type;
++	      /* Make sure to interpret in a type that has a range
++	         covering the whole access size.  */
++	      if (INTEGRAL_TYPE_P (vr->type)
++		  && ref->size != TYPE_PRECISION (vr->type))
++		type = build_nonstandard_integer_type (ref->size,
++						       TYPE_UNSIGNED (type));
++	      tree val = native_interpret_expr (type,
+ 						buffer
+ 						+ ((offset - offset2)
+ 						   / BITS_PER_UNIT),
+ 						ref->size / BITS_PER_UNIT);
++	      /* If we chop off bits because the types precision doesn't
++		 match the memory access size this is ok when optimizing
++		 reads but not when called from the DSE code during
++		 elimination.  */
++	      if (val
++		  && type != vr->type)
++		{
++		  if (! int_fits_type_p (val, vr->type))
++		    val = NULL_TREE;
++		  else
++		    val = fold_convert (vr->type, val);
++		}
++
+ 	      if (val)
+ 		return vn_reference_lookup_or_insert_for_pieces
+-		         (vuse, vr->set, vr->type, vr->operands, val);
++			 (vuse, vr->set, vr->type, vr->operands, val);
+ 	    }
+ 	}
+     }
+@@ -4735,6 +4755,7 @@
+   walker.walk (ENTRY_BLOCK_PTR_FOR_FN (cfun));
+   if (walker.fail)
+     {
++      scc_vn_restore_ssa_info ();
+       free_scc_vn ();
+       return false;
+     }
+Index: gcc/cgraphunit.c
+===================================================================
+--- a/src/gcc/cgraphunit.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cgraphunit.c	(.../branches/gcc-6-branch)
+@@ -1193,8 +1193,16 @@
+ 	     at looking at optimized away DECLs, since
+ 	     late_global_decl will subsequently be called from the
+ 	     contents of the now pruned symbol table.  */
+-	  if (!decl_function_context (node->decl))
+-	    (*debug_hooks->late_global_decl) (node->decl);
++	  if (VAR_P (node->decl)
++	      && !decl_function_context (node->decl))
++	    {
++	      /* We are reclaiming totally unreachable code and variables
++	         so they effectively appear as readonly.  Show that to
++	         the debug machinery.  */
++	      TREE_READONLY (node->decl) = 1;
++	      node->definition = false;
++	      (*debug_hooks->late_global_decl) (node->decl);
++	    }
+ 
+ 	  node->remove ();
+ 	  continue;
+Index: gcc/ChangeLog
+===================================================================
+--- a/src/gcc/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,862 @@
++2017-03-16  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-02-28  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79732
++	* tree-inline.c (expand_call_inline): Handle anonymous
++	SSA lhs properly when inlining a function without return
++	value.
++
++2017-03-15  Matthias Klose  <doko@ubuntu.com>
++
++	Backport from mainline
++	2017-03-14  Martin Liska  <mliska@suse.cz>
++
++	* Makefile.in: Install gcov-dump.
++
++2017-03-15  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/80019
++	* config/i386/i386.c (ix86_vector_duplicate_value): Create
++	subreg of inner mode for values already in registers.
++
++2017-03-14  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-02-28  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
++
++	PR target/79752
++        * config/rs6000/rs6000.md (peephole2 for udiv/umod): Should emit
++        udiv rather than div since input pattern is unsigned.
++
++2017-03-14  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2016-05-02  Jakub Jelinek  <jakub@redhat.com>
++
++	PR middle-end/80004
++	PR target/49244
++	* gimple.c (gimple_builtin_call_types_compatible_p): Allow
++	char/short arguments promoted to int because of promote_prototypes.
++
++	2017-03-09  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79977
++	* graphite-scop-detection.c (scop_detection::merge_sese):
++	Handle the case of extra exits to blocks dominating the entry.
++
++	2017-03-09  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/79971
++	* gimple-expr.c (useless_type_conversion_p): Preserve
++	TYPE_SATURATING for fixed-point types.
++
++	2017-02-22  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79666
++	* tree-vrp.c (extract_range_from_binary_expr_1): Make sure
++	to not symbolically negate if that may introduce undefined
++	overflow.
++
++	2017-02-17  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/79576
++	* params.def (max-ssa-name-query-depth): Limit to 10.
++
++2017-03-07  Uros Bizjak  <ubizjak@gmail.com>
++
++	Backport from mainline
++	2017-03-07  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	* config/i386/i386.c (ix86_local_alignment): Align most aggregates
++	of 16 bytes and more to 16 bytes, not those of 16 bits and more.
++
++2017-03-06  John David Anglin  <danglin@gcc.gnu.org>
++
++	PR target/77850
++	* config/pa/pa-64.h (PAD_VARARGS_DOWN): Don't pad down complex and
++	vector types.
++
++2017-03-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2017-03-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/79439
++	* config/rs6000/predicates.md (current_file_function_operand): Do
++	not allow self calls to be local if the function is replaceable.
++
++2017-03-02  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/79514
++	* config/i386/i386.md (*pushxf_rounded): New insn_and_split pattern.
++
++2017-03-01  Pat Haugen  <pthaugen@us.ibm.com>
++
++	Backport from mainline:
++	2017-02-27  Pat Haugen  <pthaugen@us.ibm.com>
++
++	PR target/79544
++	* rs6000/rs6000-c.c (struct altivec_builtin_types): Use VSRAD for
++	arithmetic shift of unsigned V2DI.
++
++2017-03-01  Martin Jambor  <mjambor@suse.cz>
++
++	Backport from mainline
++	2017-02-21  Martin Jambor  <mjambor@suse.cz>
++
++	PR lto/79579
++	* ipa-prop.c (ipa_prop_write_jump_functions): Bail out if no edges
++	have been analyzed.
++
++2017-02-28  Eric Botcazou  <ebotcazou@adacore.com>
++
++	PR target/79749
++	* config/sparc/sparc.c (sparc_frame_pointer_required): Add missing
++	condition on optimize for the leaf function test.
++
++2017-02-22  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-02-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/79261
++	* config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add
++	support for CODE_FOR_vsx_xxpermdi_v2d[fi]_be.
++	* config/rs6000/rs6000.md (reload_gpr_from_vsx<mode>): Call
++	generator for vsx_xxpermdi_<mode>_be.
++	* config/rs6000/vsx.md (vsx_xxpermdi_<mode>): Remove logic to
++	force big-endian semantics.
++	(vsx_xxpermdi_<mode>_be): New define_expand with same
++	implementation as previous version of vsx_xxpermdi_<mode>.
++
++2017-02-20  Marek Polacek  <polacek@redhat.com>
++
++	Backport from mainline
++	2017-02-20  Marek Polacek  <polacek@redhat.com>
++
++	PR middle-end/79537
++	* gimplify.c (gimplify_expr): Handle unused *&&L;.
++
++	PR sanitizer/79558
++	* ubsan.c (ubsan_type_descriptor): Check if TYPE_MAX_VALUE is null.
++
++2017-02-20  Marek Polacek  <polacek@redhat.com>
++
++	Backport from mainline
++	2017-02-17  Marek Polacek  <polacek@redhat.com>
++
++	PR middle-end/79536
++	* fold-const.c (fold_negate_expr_1): Renamed from fold_negate_expr.
++	(fold_negate_expr): New wrapper.
++
++2017-02-17  Carl Love  <cel@us.ibm.com>
++
++	Backport from mainline commit r245460 on 2017-02-14
++
++	PR 79545
++	* config/rs6000/rs6000.c: Add case statement entry to make the xvcvuxdsp
++	built-in argument unsigned.
++	* config/rs6000/vsx.md: Fix the source and return operand types so they
++	match the instruction definitions from the ISA document.  Fix typo
++	in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
++	statement.
++
++2017-01-17  Julia Koval  <julia.koval@intel.com>
++
++	PR target/76731
++	* config/i386/avx512fintrin.h
++	(_mm512_i32gather_ps): Change __addr type to void const*.
++	(_mm512_mask_i32gather_ps): Ditto.
++	(_mm512_i32gather_pd): Ditto.
++	(_mm512_mask_i32gather_pd): Ditto.
++	(_mm512_i64gather_ps): Ditto.
++	(_mm512_mask_i64gather_ps): Ditto.
++	(_mm512_i64gather_pd): Ditto.
++	(_mm512_mask_i64gather_pd): Ditto.
++	(_mm512_i32gather_epi32): Ditto.
++	(_mm512_mask_i32gather_epi32): Ditto.
++	(_mm512_i32gather_epi64): Ditto.
++	(_mm512_mask_i32gather_epi64): Ditto.
++	(_mm512_i64gather_epi32): Ditto.
++	(_mm512_mask_i64gather_epi32): Ditto.
++	(_mm512_i64gather_epi64): Ditto.
++	(_mm512_mask_i64gather_epi64): Ditto.
++	(_mm512_i32scatter_ps): Change __addr type to void*.
++	(_mm512_mask_i32scatter_ps): Ditto.
++	(_mm512_i32scatter_pd): Ditto.
++	(_mm512_mask_i32scatter_pd): Ditto.
++	(_mm512_i64scatter_ps): Ditto.
++	(_mm512_mask_i64scatter_ps): Ditto.
++	(_mm512_i64scatter_pd): Ditto.
++	(_mm512_mask_i64scatter_pd): Ditto.
++	(_mm512_i32scatter_epi32): Ditto.
++	(_mm512_mask_i32scatter_epi32): Ditto.
++	(_mm512_i32scatter_epi64): Ditto.
++	(_mm512_mask_i32scatter_epi64): Ditto.
++	(_mm512_i64scatter_epi32): Ditto.
++	(_mm512_mask_i64scatter_epi32): Ditto.
++	(_mm512_i64scatter_epi64): Ditto.
++	(_mm512_mask_i64scatter_epi64): Ditto.
++	* config/i386/avx512pfintrin.h
++	(_mm512_mask_prefetch_i32gather_pd): Change addr type to void const*.
++	(_mm512_mask_prefetch_i32gather_ps): Ditto.
++	(_mm512_mask_prefetch_i64gather_pd): Ditto.
++	(_mm512_mask_prefetch_i64gather_ps): Ditto.
++	(_mm512_prefetch_i32scatter_pd): Change addr type to void*.
++	(_mm512_prefetch_i32scatter_ps): Ditto.
++	(_mm512_mask_prefetch_i32scatter_pd): Ditto.
++	(_mm512_mask_prefetch_i32scatter_ps): Ditto.
++	(_mm512_prefetch_i64scatter_pd): Ditto.
++	(_mm512_prefetch_i64scatter_ps): Ditto.
++	(_mm512_mask_prefetch_i64scatter_pd): Ditto.
++	(_mm512_mask_prefetch_i64scatter_ps): Ditto.
++	* config/i386/avx512vlintrin.h
++	(_mm256_mmask_i32gather_ps): Change __addr type to void const*.
++	(_mm_mmask_i32gather_ps): Ditto.
++	(_mm256_mmask_i32gather_pd): Ditto.
++	(_mm_mmask_i32gather_pd): Ditto.
++	(_mm256_mmask_i64gather_ps): Ditto.
++	(_mm_mmask_i64gather_ps): Ditto.
++	(_mm256_mmask_i64gather_pd): Ditto.
++	(_mm_mmask_i64gather_pd): Ditto.
++	(_mm256_mmask_i32gather_epi32): Ditto.
++	(_mm_mmask_i32gather_epi32): Ditto.
++	(_mm256_mmask_i32gather_epi64): Ditto.
++	(_mm_mmask_i32gather_epi64): Ditto.
++	(_mm256_mmask_i64gather_epi32): Ditto.
++	(_mm_mmask_i64gather_epi32): Ditto.
++	(_mm256_mmask_i64gather_epi64): Ditto.
++	(_mm_mmask_i64gather_epi64): Ditto.
++	(_mm256_i32scatter_ps): Change __addr type to void*.
++	(_mm256_mask_i32scatter_ps): Ditto.
++	(_mm_i32scatter_ps): Ditto.
++	(_mm_mask_i32scatter_ps): Ditto.
++	(_mm256_i32scatter_pd): Ditto.
++	(_mm256_mask_i32scatter_pd): Ditto.
++	(_mm_i32scatter_pd): Ditto.
++	(_mm_mask_i32scatter_pd): Ditto.
++	(_mm256_i64scatter_ps): Ditto.
++	(_mm256_mask_i64scatter_ps): Ditto.
++	(_mm_i64scatter_ps): Ditto.
++	(_mm_mask_i64scatter_ps): Ditto.
++	(_mm256_i64scatter_pd): Ditto.
++	(_mm256_mask_i64scatter_pd): Ditto.
++	(_mm_i64scatter_pd): Ditto.
++	(_mm_mask_i64scatter_pd): Ditto.
++	(_mm256_i32scatter_epi32): Ditto.
++	(_mm256_mask_i32scatter_epi32): Ditto.
++	(_mm_i32scatter_epi32): Ditto.
++	(_mm_mask_i32scatter_epi32): Ditto.
++	(_mm256_i32scatter_epi64): Ditto.
++	(_mm256_mask_i32scatter_epi64): Ditto.
++	(_mm_i32scatter_epi64): Ditto.
++	(_mm_mask_i32scatter_epi64): Ditto.
++	(_mm256_i64scatter_epi32): Ditto.
++	(_mm256_mask_i64scatter_epi32): Ditto.
++	(_mm_i64scatter_epi32): Ditto.
++	(_mm_mask_i64scatter_epi32): Ditto.
++	(_mm256_i64scatter_epi64): Ditto.
++	(_mm256_mask_i64scatter_epi64): Ditto.
++	(_mm_i64scatter_epi64): Ditto.
++	(_mm_mask_i64scatter_epi64): Ditto.
++	* config/i386/i386-builtin-types.def (V16SF_V16SF_PCFLOAT_V16SI_HI_INT)
++	(V8DF_V8DF_PCDOUBLE_V8SI_QI_INT, V8SF_V8SF_PCFLOAT_V8DI_QI_INT)
++	(V8DF_V8DF_PCDOUBLE_V8DI_QI_INT, V16SI_V16SI_PCINT_V16SI_HI_INT)
++	(V8DI_V8DI_PCINT64_V8SI_QI_INT, V8SI_V8SI_PCINT_V8DI_QI_INT)
++	(V8DI_V8DI_PCINT64_V8DI_QI_INT, V2DF_V2DF_PCDOUBLE_V4SI_QI_INT)
++	(V4DF_V4DF_PCDOUBLE_V4SI_QI_INT, V2DF_V2DF_PCDOUBLE_V2DI_QI_INT)
++	(V4DF_V4DF_PCDOUBLE_V4DI_QI_INT, V4SF_V4SF_PCFLOAT_V4SI_QI_INT)
++	(V8SF_V8SF_PCFLOAT_V8SI_QI_INT, V4SF_V4SF_PCFLOAT_V2DI_QI_INT)
++	(V4SF_V4SF_PCFLOAT_V4DI_QI_INT, V2DI_V2DI_PCINT64_V4SI_QI_INT)
++	(V4DI_V4DI_PCINT64_V4SI_QI_INT, V2DI_V2DI_PCINT64_V2DI_QI_INT)
++	(V4DI_V4DI_PCINT64_V4DI_QI_INT, V4SI_V4SI_PCINT_V4SI_QI_INT)
++	(V8SI_V8SI_PCINT_V8SI_QI_INT, V4SI_V4SI_PCINT_V2DI_QI_INT)
++	(V4SI_V4SI_PCINT_V4DI_QI_INT, VOID_PFLOAT_HI_V16SI_V16SF_INT)
++	(VOID_PFLOAT_QI_V8SI_V8SF_INT, VOID_PFLOAT_QI_V4SI_V4SF_INT)
++	(VOID_PDOUBLE_QI_V8SI_V8DF_INT, VOID_PDOUBLE_QI_V4SI_V4DF_INT)
++	(VOID_PDOUBLE_QI_V4SI_V2DF_INT, VOID_PFLOAT_QI_V8DI_V8SF_INT)
++	(VOID_PFLOAT_QI_V4DI_V4SF_INT, VOID_PFLOAT_QI_V2DI_V4SF_INT)
++	(VOID_PDOUBLE_QI_V8DI_V8DF_INT, VOID_PDOUBLE_QI_V4DI_V4DF_INT)
++	(VOID_PDOUBLE_QI_V2DI_V2DF_INT, VOID_PINT_HI_V16SI_V16SI_INT)
++	(VOID_PINT_QI_V8SI_V8SI_INT, VOID_PINT_QI_V4SI_V4SI_INT)
++	(VOID_PLONGLONG_QI_V8SI_V8DI_INT, VOID_PLONGLONG_QI_V4SI_V4DI_INT)
++	(VOID_PLONGLONG_QI_V4SI_V2DI_INT, VOID_PINT_QI_V8DI_V8SI_INT)
++	(VOID_PINT_QI_V4DI_V4SI_INT, VOID_PINT_QI_V2DI_V4SI_INT)
++	(VOID_PLONGLONG_QI_V8DI_V8DI_INT, VOID_QI_V8SI_PCINT64_INT_INT)
++	(VOID_PLONGLONG_QI_V4DI_V4DI_INT, VOID_PLONGLONG_QI_V2DI_V2DI_INT)
++	(VOID_HI_V16SI_PCINT_INT_INT, VOID_QI_V8DI_PCINT64_INT_INT)
++	(VOID_QI_V8DI_PCINT_INT_INT): Remove.
++	(V16SF_V16SF_PCVOID_V16SI_HI_INT,  V8DF_V8DF_PCVOID_V8SI_QI_INT)
++	(V8SF_V8SF_PCVOID_V8DI_QI_INT, V8DF_V8DF_PCVOID_V8DI_QI_INT)
++	(V16SI_V16SI_PCVOID_V16SI_HI_INT, V8DI_V8DI_PCVOID_V8SI_QI_INT)
++	(V8SI_V8SI_PCVOID_V8DI_QI_INT, V8DI_V8DI_PCVOID_V8DI_QI_INT)
++	(VOID_PVOID_HI_V16SI_V16SF_INT, VOID_PVOID_QI_V8SI_V8DF_INT)
++	(VOID_PVOID_QI_V8DI_V8SF_INT, VOID_PVOID_QI_V8DI_V8DF_INT)
++	(VOID_PVOID_HI_V16SI_V16SI_INT, VOID_PVOID_QI_V8SI_V8DI_INT)
++	(VOID_PVOID_QI_V8DI_V8SI_INT, VOID_PVOID_QI_V8DI_V8DI_INT)
++	(V2DF_V2DF_PCVOID_V4SI_QI_INT, V4DF_V4DF_PCVOID_V4SI_QI_INT)
++	(V2DF_V2DF_PCVOID_V2DI_QI_INT, V4DF_V4DF_PCVOID_V4DI_QI_INT
++	(V4SF_V4SF_PCVOID_V4SI_QI_INT, V8SF_V8SF_PCVOID_V8SI_QI_INT)
++	(V4SF_V4SF_PCVOID_V2DI_QI_INT, V4SF_V4SF_PCVOID_V4DI_QI_INT)
++	(V2DI_V2DI_PCVOID_V4SI_QI_INT, V4DI_V4DI_PCVOID_V4SI_QI_INT)
++	(V2DI_V2DI_PCVOID_V2DI_QI_INT, V4DI_V4DI_PCVOID_V4DI_QI_INT)
++	(V4SI_V4SI_PCVOID_V4SI_QI_INT, V8SI_V8SI_PCVOID_V8SI_QI_INT)
++	(V4SI_V4SI_PCVOID_V2DI_QI_INT, V4SI_V4SI_PCVOID_V4DI_QI_INT)
++	(VOID_PVOID_QI_V8SI_V8SF_INT, VOID_PVOID_QI_V4SI_V4SF_INT)
++	(VOID_PVOID_QI_V4SI_V4DF_INT, VOID_PVOID_QI_V4SI_V2DF_INT)
++	(VOID_PVOID_QI_V4DI_V4SF_INT, VOID_PVOID_QI_V2DI_V4SF_INT)
++	(VOID_PVOID_QI_V4DI_V4DF_INT, VOID_PVOID_QI_V2DI_V2DF_INT)
++	(VOID_PVOID_QI_V8SI_V8SI_INT, VOID_PVOID_QI_V4SI_V4SI_INT)
++	(VOID_PVOID_QI_V4SI_V4DI_INT, VOID_PVOID_QI_V4SI_V2DI_INT)
++	(VOID_PVOID_QI_V4DI_V4SI_INT, VOID_PVOID_QI_V2DI_V4SI_INT)
++	(VOID_PVOID_QI_V4DI_V4DI_INT, VOID_PVOID_QI_V2DI_V2DI_INT)
++	(VOID_QI_V8SI_PCVOID_INT_INT, VOID_HI_V16SI_PCVOID_INT_INT)
++	(VOID_QI_V8DI_PCVOID_INT_INT): Add.
++	* config/i386/i386.c (ix86_init_mmx_sse_builtins): Adjust builtin
++	definitions accordingly.
++
++2017-02-16  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-02-09  Marek Polacek  <polacek@redhat.com>
++
++	PR c/79428
++	* c-parser.c (c_parser_omp_ordered): Call c_parser_skip_to_pragma_eol
++	instead of c_parser_skip_until_found.
++
++2017-02-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-02-10  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/79411
++	* tree-ssa-reassoc.c (is_reassociable_op): Return false if
++	stmt operands are SSA_NAMEs used in abnormal phis.
++	(can_reassociate_p): Return false if op is SSA_NAME used in abnormal
++	phis.
++
++	2017-02-09  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/79431
++	* gimplify.c (gimplify_adjust_omp_clauses): Ignore
++	"omp declare target link" attribute unless is_global_var.
++	* omp-low.c (find_link_var_op): Likewise.
++
++	2017-02-07  Jakub Jelinek  <jakub@redhat.com>
++		    Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/79399
++	* ira-int.h (struct target_ira_int): Change x_max_struct_costs_size
++	type from int to size_t.
++	* ira-costs.c (struct_costs_size): Change type from int to size_t.
++
++	2017-02-04  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/79338
++	* tree-parloops.c (gather_scalar_reductions): Don't call
++	vect_analyze_loop_form for loop->inner before destroying loop's
++	loop_vinfo.
++
++	2017-02-02  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/79197
++	* config/rs6000/rs6000.md (*fixuns_trunc<mode>di2_fctiduz): Rename to ...
++	(fixuns_trunc<mode>di2): ... this, remove previous expander.  Put all
++	conditions on a single line.
++
++	2017-01-31  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/79267
++	* value-prof.c (gimple_ic): Only drop lhs for noreturn calls
++	if should_remove_lhs_p is true.
++
++	2017-01-17  Kito Cheng  <kito.cheng@gmail.com>
++		    Kuan-Lin Chen  <kuanlinchentw@gmail.com>
++
++	PR target/79079
++	* internal-fn.c (expand_mul_overflow): Use convert_modes instead of
++	gen_lowpart.
++
++2017-02-14  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/79495
++	* config/i386/i386.md (*movxf_internal): Add (o,rC) alternative.
++
++2017-02-14  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-02-13  Martin Liska  <mliska@suse.cz>
++
++	PR c/79471
++	* calls.c (expand_call): Replace XALLOCAVEC with XCNEWVEC.
++
++2017-02-13  Gerald Pfeifer  <gerald@pfeifer.com>
++
++	Backport from mainline
++	2016-12-11  Roger Pau Monné  <roger.pau@citrix.com>
++
++	* config/i386/x86-64.h: Append --32 to the assembler options when
++	-m16 is used on non-glibc systems as well.
++
++2017-02-08  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR translation/79397
++	* config/rs6000/rs6000.opt (maltivec=le, maltivec=be): Fix spelling
++	of AltiVec.
++
++2017-02-08  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-02-08  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/71824
++	* graphite-scop-detection.c (scop_detection::build_scop_breadth):
++	Check all loops contained in the merged region.
++
++	2017-02-01  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/71824
++	* graphite-scop-detection.c (scop_detection::build_scop_breadth):
++	Verify the loops are valid in the merged SESE region.
++	(scop_detection::can_represent_loop_1): Check analyzing the
++	evolution of the number of iterations in the region succeeds.
++
++	2017-01-31  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/77318
++	* graphite-sese-to-poly.c (extract_affine): Fix assert.
++	(create_pw_aff_from_tree): Take loop parameter.
++	(add_condition_to_pbb): Pass loop of the condition to
++	create_pw_aff_from_tree.
++
++2017-02-06  Dominique d'Humieres  <dominiq@lps.ens.fr>
++
++	PR target/71017
++	* config/i386/cpuid.h: Fix undefined behavior.
++
++2017-02-03  Carl Love  <cel@us.ibm.com>
++
++	Backport of two commits from mainline, r244943 and r244904,
++	dated 017-01-26 and 2017-01-25 respectively
++
++	* config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order
++	of entries for ALTIVEC_BUILTIN_VEC_PACKS.  Remove bogus entries
++	for P8V_BUILTIN_VEC_VGBBD.
++
++2017-02-03  Walter Lee  <walt@tilera.com>
++
++	Backport from mainline
++	2017-02-03  Walter Lee  <walt@tilera.com>
++
++	PR target/78862
++	* config/tilegx/tilegx.md (tilegx_expand_prologue): Add blockage
++	after initial stackframe link reg save.
++	* config/tilepro/tilepro.md (tilepro_expand_prologue): Likewise.
++
++2017-02-03  Maxim Ostapenko  <m.ostapenko@samsung.com>
++
++	PR lto/79061
++	* asan.c (asan_add_global): Force has_dynamic_init to zero in LTO mode.
++
++2017-01-31  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/79268
++	* config/rs6000/altivec.h (vec_xl): Revise #define.
++	(vec_xst): Likewise.
++
++2017-01-26  Eric Botcazou  <ebotcazou@adacore.com>
++
++	Backport from mainline
++	2017-01-10  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* expr.c (store_field): In the bitfield case, fetch the return value
++	from the registers before applying a single big-endian adjustment.
++	Always do a final load for a BLKmode value not larger than a word.
++
++	2017-01-09  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* expr.c (store_field): In the bitfield case, if the value comes from
++	a function call and is of an aggregate type returned in registers, do
++	not modify the field mode; extract the value in all cases if the mode
++	is BLKmode and the size is not larger than a word.
++
++2017-01-26  Richard Biener  <rguenther@suse.de>
++
++	* tree-vrp.c (vrp_visit_assignment_or_call): Use set_defs_to_varying.
++
++	Backport from mainline
++	2016-01-10  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79034
++	* tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
++	Propagate out degenerate PHIs in the joiner.
++
++	2016-12-13  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/78742
++	* tree.c (cst_and_fits_in_hwi): Look if the actual value fits.
++	* tree-object-size.c (compute_builtin_object_size): Use
++	tree_fits_shwi_p.
++	* tree-data-ref.c (initialize_matrix_A): Remove excess assert.
++
++2017-01-26  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2016-09-03  Kirill Yukhin  <kirill.yukhin@intel.com>
++
++	* ubsan.c (ubsan_use_new_style_p): Fix check for empty string.
++
++2017-01-24  Eric Botcazou  <ebotcazou@adacore.com>
++
++	PR target/77439
++	* config/arm/arm.c (arm_function_ok_for_sibcall): Add back restriction
++	for long calls with APCS frame and VFP.
++
++2017-01-24  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/78478
++	Revert:
++	2013-11-05  Uros Bizjak  <ubizjak@gmail.com>
++
++	* config/i386/rtemself.h (LONG_DOUBLE_TYPE_SIZE): New define.
++
++2017-01-23  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-20  Martin Liska  <mliska@suse.cz>
++
++	PR lto/69188
++	* tree-profile.c (init_ic_make_global_vars): Do not call
++	finalize_decl.
++	(gimple_init_gcov_profiler): Likewise.
++
++2017-01-21  Gerald Pfeifer  <gerald@pfeifer.com>
++
++	Backport from mainline
++	2016-12-29  Gerald Pfeifer  <gerald@pfeifer.com>
++
++	* doc/extend.texi (Cilk Plus Builtins): cilkplus.org now uses
++	https by default.
++	* doc/passes.texi (Cilk Plus Transformation): Ditto.
++	* doc/generic.texi (Statements for C++): Ditto, and use @uref.
++
++2017-01-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	* config/rs6000/rs6000.c (rtx_is_swappable_p): Change
++	UNSPEC_VSX__XXSPLTD to require special splat handling.
++
++2017-01-20  Wilco Dijkstra  <wdijkstr@arm.com>
++
++	Backport from mainline
++	PR target/77455
++	* config/aarch64/aarch64.md (eh_return): Remove pattern and splitter.
++	* config/aarch64/aarch64.h (AARCH64_EH_STACKADJ_REGNUM): Remove.
++	(EH_RETURN_HANDLER_RTX): New define.
++	* config/aarch64/aarch64.c (aarch64_frame_pointer_required):
++	Force frame pointer in EH return functions.
++	(aarch64_expand_epilogue): Add barrier for eh_return.
++	(aarch64_final_eh_return_addr): Remove.
++	(aarch64_eh_return_handler_rtx): New function.
++	* config/aarch64/aarch64-protos.h (aarch64_final_eh_return_addr):
++	Remove.
++	(aarch64_eh_return_handler_rtx): New prototype.
++
++2017-01-20  Richard Earnshaw  <rearnsha@arm.com>
++
++	Backported from mainline
++	2017-01-19  Richard Earnshaw  <rearnsha@arm.com>
++
++	PR rtl-optimization/79121
++	* expr.c (expand_expr_real_2, case LSHIFT_EXPR): Look at the signedness
++	of the inner type when shifting an extended value.
++
++2017-01-20  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-13  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/79043
++	* function.c (set_cfun): Add new argument force.
++	* function.h (set_cfun): Likewise.
++	* ipa-inline-transform.c (inline_call): Use the function when
++	strict alising from is dropped for function we inline to.
++
++2017-01-20  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-17  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/71207
++	* ipa-polymorphic-call.c (contains_type_p): Fix wrong
++	assumption and add comment.
++
++2017-01-19  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/72488
++	* tree-ssa-sccvn.c (run_scc_vn): When we abort the VN make
++	sure to restore SSA info.
++
++2017-01-17  Jakub Jelinek  <jakub@redhat.com>
++
++	PR debug/78839
++	* dwarf2out.c (field_byte_offset): Restore the
++	PCC_BITFIELD_TYPE_MATTERS behavior for INTEGER_CST DECL_FIELD_OFFSET
++	and DECL_FIELD_BIT_OFFSET.  Use fold_build2 instead of build2 + fold.
++	(analyze_variants_discr, gen_variant_part): Use fold_build2 instead
++	of build2 + fold.
++
++2017-01-17  Thomas Preud'homme  <thomas.preudhomme@arm.com>
++
++	Backport from mainline
++	2016-12-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>
++
++	PR rtl-optimization/78617
++	* lra-remat.c (do_remat): Initialize live_hard_regs from live in
++	registers, also setting hard registers mapped to pseudo registers.
++
++2017-01-13  Christophe Lyon  <christophe.lyon@linaro.org>
++
++	Backport from mainline r244320.
++	2017-01-11  Christophe Lyon  <christophe.lyon@linaro.org>
++
++	PR target/78253
++	* config/arm/arm.c (legitimize_pic_address): Handle reference to
++	weak symbol.
++	(arm_assemble_integer): Likewise.
++
++2017-01-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/79044
++	* config/rs6000/rs6000.c (insn_is_swappable_p): Mark
++	element-reversing loads and stores as not swappable.
++
++2017-01-11  Uros Bizjak  <ubizjak@gmail.com>
++
++	* config/i386/i386.c (memory_address_length): Increase len
++	only when rip_relative_addr_p returns false.
++
++2017-01-11  Maxim Ostapenko  <m.ostapenko@samsung.com>
++
++	Backport from mainline
++	2017-01-11  Maxim Ostapenko  <m.ostapenko@samsung.com>
++
++	PR lto/79042
++	* lto-cgraph.c (lto_output_varpool_node): Pack dynamically_initialized
++	bit.
++	(input_varpool_node): Unpack dynamically_initialized bit.
++	* lto-streamer.h (LTO_minor_version): Bump version.
++
++2017-01-10  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2016-12-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/78900
++	* config/rs6000/rs6000.c (rs6000_split_signbit): Change some
++	assertions.  Add support for doing the signbit if the IEEE 128-bit
++	floating point value is in a GPR.
++	* config/rs6000/rs6000.md (Fsignbit): Delete.
++	(signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa".
++	Update the length attribute if the value is in a GPR.
++	(signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate
++	the sign or zero extension instruction, since the value is always
++	0/1.
++	(signbit<mode>2_dm2): Delete using <Fsignbit>.
++
++2017-01-10  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-09  Martin Liska  <mliska@suse.cz>
++
++	PR pch/78970
++	* gcc.c (driver_handle_option): Handle OPT_E and set
++	have_E.
++	(lookup_compiler): Do not show error message with have_E.
++
++2017-01-10  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-05  Martin Liska  <mliska@suse.cz>
++
++	PR pch/78970
++	* gcc.c (lookup_compiler): Reject '-' filename for a precompiled
++	header.
++
++2017-01-10  Thomas Schwinge  <thomas@codesourcery.com>
++
++	PR tree-optimization/78024
++	* omp-low.c (oacc_loop_discovery): Call clear_bb_flags.
++
++	Backport trunk r239086:
++	2016-08-03  Nathan Sidwell  <nathan@codesourcery.com>
++
++	* config/nvptx/nvptx.c (nvptx_declare_function_name): Round frame
++	size to DImode boundary.
++	(nvptx_propagate): Likewise.
++
++2017-01-10  Chung-Ju Wu  <jasonwucj@gmail.com>
++
++	Backport from mainline
++	2016-04-28  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR target/70668
++	* config/nds32/nds32.md (casesi): Don't access the operands array
++	out of bounds.
++
++2017-01-09  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	Backport from mainline
++	2016-10-10  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	* config.gcc: Add aarch64-*-freebsd* support.
++	* config.host: Likewise.
++	* config/aarch64/aarch64-freebsd.h: New file.
++	* config/aarch64/t-aarch64-freebsd: Ditto.
++
++2017-01-09  Bill Seurer  <seurer@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2016-12-21  Bill Seurer  <seurer@linux.vnet.ibm.com>
++
++	PR sanitizer/65479
++	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
++	-fasynchronous-unwind-tables option when -fsanitize=address is
++	specified.
++
++2017-01-09  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	Backport from mainline
++	2016-09-19  Richard Biener  <rguenther@suse.de>
++
++	* dwarf2out.c (dwarf2out_late_global_decl): When being during the
++	early debug phase do not add locations but only const value
++	attributes.
++
++	Backport from mainline
++	2016-10-20  Richard Biener  <rguenther@suse.de>
++
++	* cgraphunit.c (analyze_functions): Set node->definition to
++	false to signal symbol removal to debug_hooks->late_global_decl.
++
++2017-01-09  Andre Vieira <andre.simoesdiasvieira@arm.com>
++
++	Backport from mainline
++	2016-12-09  Andre Vieira <andre.simoesdiasvieira@arm.com>
++
++	PR rtl-optimization/78255
++	* gcc/postreload.c (reload_cse_simplify): Do not CSE a function if
++	NO_FUNCTION_CSE is true.
++
++2017-01-06  Wilco Dijkstra  <wdijkstr@arm.com>
++
++	Backport from mainline
++	2016-10-25  Wilco Dijkstra  <wdijkstr@arm.com>
++
++	PR target/78041
++	* config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants.
++	Remove partial overlap check for shift by 1.
++	(ashldi3_neon): Likewise.
++
++2017-01-05  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++
++	Backport from mainline
++	2016-07-22  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++
++	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
++	comments to explain why certain error messages make mention of
++	undocumented options.
++	(rs6000_invalid_builtin): Change error messages to replace mention
++	of undocumented options with mention of the -mcpu=power9 option
++	that enables those undocumented options.
++	* config/rs6000/rs6000.h: Add macro definition of MASK_FLOAT128
++	and change the macro definition of RS6000_BTM_FLOAT128 to correct
++	an error that was discovered during the development of this patch.
++	* config/rs6000/rs6000.opt: Add the Undocumented qualifier to the
++	mpower9-fusion, mpower9-vector, mpower9-dform, and mmodulo entries.
++	* doc/extend.texi (PowerPC AltiVec Built-in Functions): Modify
++	descriptions of built-in functions so that they depend on
++	-mcpu=power9 instead of on the corresponding undocumented flags.
++	* doc/invoke.texi (Option Summary):  Remove all mention of newly
++	undocumented flags.
++	(IBM RS/6000 and PowerPC Options): Likewise.
++	* doc/md.texi (Constraints for Particuliar Machines): Remove all
++	mention of newly undocumented flags.
++
++2017-01-05  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2016-12-22  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	* varasm.c (build_constant_desc): Use the alignment of the var
++	decl instead of the original expression.
++
++2017-01-04  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2016-05-11  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/71055
++	* tree-ssa-sccvn.c (vn_reference_lookup_3): When native-interpreting
++	sth with precision not equal to access size verify we don't chop
++	off bits.
++
++2017-01-03  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-21  Jakub Jelinek  <jakub@redhat.com>
++		    Martin Liska  <mliska@suse.cz>
++
++	PR driver/78863
++	* gcc.c (driver::build_option_suggestions): Do not add
++	-fsanitize=all as a suggestion candidate.
++
++2017-01-03  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-22  Martin Liska  <mliska@suse.cz>
++
++	PR tree-optimization/78886
++	* tree-ssa-strlen.c (handle_builtin_malloc): Return when LHS
++	is equal to NULL.
++
++2017-01-03  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-13  Martin Liska  <mliska@suse.cz>
++
++	PR tree-optimization/78428
++	* expr.c (store_constructor_field): Add new arguments to the
++	function.
++	(store_constructor): Set up bitregion_end and add
++	gcc_unreachable to fields that have either non-constant size
++	or (and) offset.
++
++2016-12-27  Jakub Jelinek  <jakub@redhat.com>
++
++	PR translation/78922
++	* config/i386/stringop.opt: Remove.
++
++2016-12-21  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2016-12-13  Jakub Jelinek  <jakub@redhat.com>
++
++	PR ipa/77905
++	* ipa-pure-const.c (cdtor_p): Return true for
++	DECL_STATIC_{CON,DE}STRUCTOR even when it is
++	DECL_LOOPING_CONST_OR_PURE_P.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+@@ -68,11 +931,11 @@
+ 	Backport from mainline
+ 	2016-11-07  Bernd Schmidt  <bschmidt@redhat.com>
+ 
+-        PR rtl-optimization/77309
+-        * combine.c (make_compound_operation): Allow EQ for IN_CODE, and
+-        don't assume an equality comparison for plain COMPARE.
+-        (simplify_comparison): Pass a more accurate code to
+-        make_compound_operation.
++	PR rtl-optimization/77309
++	* combine.c (make_compound_operation): Allow EQ for IN_CODE, and
++	don't assume an equality comparison for plain COMPARE.
++	(simplify_comparison): Pass a more accurate code to
++	make_compound_operation.
+ 
+ 2016-12-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
+ 
+Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c	(.../branches/gcc-6-branch)
+@@ -1,230 +0,0 @@
+-/* { dg-do compile { target { powerpc64-*-* } } } */
+-/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+-/* { dg-options "-mcpu=power9 -O0" } */
+-/* { dg-require-effective-target powerpc_p9vector_ok } */
+-/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
+-/* { dg-final { scan-assembler-times "lxvx" 40 } } */
+-/* { dg-final { scan-assembler-times "stxvx" 40 } } */
+-
+-#include <altivec.h>
+-
+-extern vector double vd, *vdp;
+-extern vector signed long long vsll, *vsllp;
+-extern vector unsigned long long vull, *vullp;
+-extern vector float vf, *vfp;
+-extern vector signed int vsi, *vsip;
+-extern vector unsigned int vui, *vuip;
+-extern vector signed short vss, *vssp;
+-extern vector unsigned short vus, *vusp;
+-extern vector signed char vsc, *vscp;
+-extern vector unsigned char vuc, *vucp;
+-extern double *dp;
+-extern signed long long *sllp;
+-extern unsigned long long *ullp;
+-extern float *fp;
+-extern signed int *sip;
+-extern unsigned int *uip;
+-extern signed short *ssp;
+-extern unsigned short *usp;
+-extern signed char *scp;
+-extern unsigned char *ucp;
+-
+-void foo0 (void)
+-{
+-  vd = vec_xl (0, vdp);
+-}
+-
+-void foo1 (void)
+-{
+-  vsll = vec_xl (0, vsllp);
+-}
+-
+-void foo2 (void)
+-{
+-  vull = vec_xl (0, vullp);
+-}
+-
+-void foo3 (void)
+-{
+-  vf = vec_xl (0, vfp);
+-}
+-
+-void foo4 (void)
+-{
+-  vsi = vec_xl (0, vsip);
+-}
+-
+-void foo5 (void)
+-{
+-  vui = vec_xl (0, vuip);
+-}
+-
+-void foo6 (void)
+-{
+-  vss = vec_xl (0, vssp);
+-}
+-
+-void foo7 (void)
+-{
+-  vus = vec_xl (0, vusp);
+-}
+-
+-void foo8 (void)
+-{
+-  vsc = vec_xl (0, vscp);
+-}
+-
+-void foo9 (void)
+-{
+-  vuc = vec_xl (0, vucp);
+-}
+-
+-void foo10 (void)
+-{
+-  vec_xst (vd, 0, vdp);
+-}
+-
+-void foo11 (void)
+-{
+-  vec_xst (vsll, 0, vsllp);
+-}
+-
+-void foo12 (void)
+-{
+-  vec_xst (vull, 0, vullp);
+-}
+-
+-void foo13 (void)
+-{
+-  vec_xst (vf, 0, vfp);
+-}
+-
+-void foo14 (void)
+-{
+-  vec_xst (vsi, 0, vsip);
+-}
+-
+-void foo15 (void)
+-{
+-  vec_xst (vui, 0, vuip);
+-}
+-
+-void foo16 (void)
+-{
+-  vec_xst (vss, 0, vssp);
+-}
+-
+-void foo17 (void)
+-{
+-  vec_xst (vus, 0, vusp);
+-}
+-
+-void foo18 (void)
+-{
+-  vec_xst (vsc, 0, vscp);
+-}
+-
+-void foo19 (void)
+-{
+-  vec_xst (vuc, 0, vucp);
+-}
+-
+-void foo20 (void)
+-{
+-  vd = vec_xl (0, dp);
+-}
+-
+-void foo21 (void)
+-{
+-  vsll = vec_xl (0, sllp);
+-}
+-
+-void foo22 (void)
+-{
+-  vull = vec_xl (0, ullp);
+-}
+-
+-void foo23 (void)
+-{
+-  vf = vec_xl (0, fp);
+-}
+-
+-void foo24 (void)
+-{
+-  vsi = vec_xl (0, sip);
+-}
+-
+-void foo25 (void)
+-{
+-  vui = vec_xl (0, uip);
+-}
+-
+-void foo26 (void)
+-{
+-  vss = vec_xl (0, ssp);
+-}
+-
+-void foo27 (void)
+-{
+-  vus = vec_xl (0, usp);
+-}
+-
+-void foo28 (void)
+-{
+-  vsc = vec_xl (0, scp);
+-}
+-
+-void foo29 (void)
+-{
+-  vuc = vec_xl (0, ucp);
+-}
+-
+-void foo30 (void)
+-{
+-  vec_xst (vd, 0, dp);
+-}
+-
+-void foo31 (void)
+-{
+-  vec_xst (vsll, 0, sllp);
+-}
+-
+-void foo32 (void)
+-{
+-  vec_xst (vull, 0, ullp);
+-}
+-
+-void foo33 (void)
+-{
+-  vec_xst (vf, 0, fp);
+-}
+-
+-void foo34 (void)
+-{
+-  vec_xst (vsi, 0, sip);
+-}
+-
+-void foo35 (void)
+-{
+-  vec_xst (vui, 0, uip);
+-}
+-
+-void foo36 (void)
+-{
+-  vec_xst (vss, 0, ssp);
+-}
+-
+-void foo37 (void)
+-{
+-  vec_xst (vus, 0, usp);
+-}
+-
+-void foo38 (void)
+-{
+-  vec_xst (vsc, 0, scp);
+-}
+-
+-void foo39 (void)
+-{
+-  vec_xst (vuc, 0, ucp);
+-}
+Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-1.c	(.../branches/gcc-6-branch)
+@@ -1,143 +0,0 @@
+-/* { dg-do compile { target { powerpc64le*-*-* } } } */
+-/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+-/* { dg-options "-mcpu=power8 -O0" } */
+-/* { dg-final { scan-assembler-times "lxvd2x" 18 } } */
+-/* { dg-final { scan-assembler-times "lxvw4x" 6 } } */
+-/* { dg-final { scan-assembler-times "stxvd2x" 18 } } */
+-/* { dg-final { scan-assembler-times "stxvw4x" 6 } } */
+-/* { dg-final { scan-assembler-times "xxpermdi" 24 } } */
+-
+-#include <altivec.h>
+-
+-extern vector double vd, *vdp;
+-extern vector signed long long vsll, *vsllp;
+-extern vector unsigned long long vull, *vullp;
+-extern vector float vf, *vfp;
+-extern vector signed int vsi, *vsip;
+-extern vector unsigned int vui, *vuip;
+-extern double *dp;
+-extern signed long long *sllp;
+-extern unsigned long long *ullp;
+-extern float *fp;
+-extern signed int *sip;
+-extern unsigned int *uip;
+-
+-void foo0 (void)
+-{
+-  vd = vec_xl (0, vdp);
+-}
+-
+-void foo1 (void)
+-{
+-  vsll = vec_xl (0, vsllp);
+-}
+-
+-void foo2 (void)
+-{
+-  vull = vec_xl (0, vullp);
+-}
+-
+-void foo3 (void)
+-{
+-  vf = vec_xl (0, vfp);
+-}
+-
+-void foo4 (void)
+-{
+-  vsi = vec_xl (0, vsip);
+-}
+-
+-void foo5 (void)
+-{
+-  vui = vec_xl (0, vuip);
+-}
+-
+-void foo6 (void)
+-{
+-  vec_xst (vd, 0, vdp);
+-}
+-
+-void foo7 (void)
+-{
+-  vec_xst (vsll, 0, vsllp);
+-}
+-
+-void foo8 (void)
+-{
+-  vec_xst (vull, 0, vullp);
+-}
+-
+-void foo9 (void)
+-{
+-  vec_xst (vf, 0, vfp);
+-}
+-
+-void foo10 (void)
+-{
+-  vec_xst (vsi, 0, vsip);
+-}
+-
+-void foo11 (void)
+-{
+-  vec_xst (vui, 0, vuip);
+-}
+-
+-void foo20 (void)
+-{
+-  vd = vec_xl (0, dp);
+-}
+-
+-void foo21 (void)
+-{
+-  vsll = vec_xl (0, sllp);
+-}
+-
+-void foo22 (void)
+-{
+-  vull = vec_xl (0, ullp);
+-}
+-
+-void foo23 (void)
+-{
+-  vf = vec_xl (0, fp);
+-}
+-
+-void foo24 (void)
+-{
+-  vsi = vec_xl (0, sip);
+-}
+-
+-void foo25 (void)
+-{
+-  vui = vec_xl (0, uip);
+-}
+-
+-void foo26 (void)
+-{
+-  vec_xst (vd, 0, dp);
+-}
+-
+-void foo27 (void)
+-{
+-  vec_xst (vsll, 0, sllp);
+-}
+-
+-void foo28 (void)
+-{
+-  vec_xst (vull, 0, ullp);
+-}
+-
+-void foo29 (void)
+-{
+-  vec_xst (vf, 0, fp);
+-}
+-
+-void foo30 (void)
+-{
+-  vec_xst (vsi, 0, sip);
+-}
+-
+-void foo31 (void)
+-{
+-  vec_xst (vui, 0, uip);
+-}
+Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c	(.../branches/gcc-6-branch)
+@@ -1,236 +0,0 @@
+-/* { dg-do compile { target { powerpc64le*-*-* } } } */
+-/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+-/* { dg-options "-mcpu=power9 -O0" } */
+-/* { dg-require-effective-target powerpc_p9vector_ok } */
+-/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
+-/* { dg-final { scan-assembler-times "lxvd2x" 6 } } */
+-/* { dg-final { scan-assembler-times "lxvw4x" 6 } } */
+-/* { dg-final { scan-assembler-times "lxvh8x" 4 } } */
+-/* { dg-final { scan-assembler-times "lxvb16x" 4 } } */
+-/* { dg-final { scan-assembler-times "stxvd2x" 6 } } */
+-/* { dg-final { scan-assembler-times "stxvw4x" 6 } } */
+-/* { dg-final { scan-assembler-times "stxvh8x" 4 } } */
+-/* { dg-final { scan-assembler-times "stxvb16x" 4 } } */
+-
+-#include <altivec.h>
+-
+-extern vector double vd, *vdp;
+-extern vector signed long long vsll, *vsllp;
+-extern vector unsigned long long vull, *vullp;
+-extern vector float vf, *vfp;
+-extern vector signed int vsi, *vsip;
+-extern vector unsigned int vui, *vuip;
+-extern vector signed short vss, *vssp;
+-extern vector unsigned short vus, *vusp;
+-extern vector signed char vsc, *vscp;
+-extern vector unsigned char vuc, *vucp;
+-extern double *dp;
+-extern signed long long *sllp;
+-extern unsigned long long *ullp;
+-extern float *fp;
+-extern signed int *sip;
+-extern unsigned int *uip;
+-extern signed short *ssp;
+-extern unsigned short *usp;
+-extern signed char *scp;
+-extern unsigned char *ucp;
+-
+-void foo0 (void)
+-{
+-  vd = vec_xl (0, vdp);
+-}
+-
+-void foo1 (void)
+-{
+-  vsll = vec_xl (0, vsllp);
+-}
+-
+-void foo2 (void)
+-{
+-  vull = vec_xl (0, vullp);
+-}
+-
+-void foo3 (void)
+-{
+-  vf = vec_xl (0, vfp);
+-}
+-
+-void foo4 (void)
+-{
+-  vsi = vec_xl (0, vsip);
+-}
+-
+-void foo5 (void)
+-{
+-  vui = vec_xl (0, vuip);
+-}
+-
+-void foo6 (void)
+-{
+-  vss = vec_xl (0, vssp);
+-}
+-
+-void foo7 (void)
+-{
+-  vus = vec_xl (0, vusp);
+-}
+-
+-void foo8 (void)
+-{
+-  vsc = vec_xl (0, vscp);
+-}
+-
+-void foo9 (void)
+-{
+-  vuc = vec_xl (0, vucp);
+-}
+-
+-void foo10 (void)
+-{
+-  vec_xst (vd, 0, vdp);
+-}
+-
+-void foo11 (void)
+-{
+-  vec_xst (vsll, 0, vsllp);
+-}
+-
+-void foo12 (void)
+-{
+-  vec_xst (vull, 0, vullp);
+-}
+-
+-void foo13 (void)
+-{
+-  vec_xst (vf, 0, vfp);
+-}
+-
+-void foo14 (void)
+-{
+-  vec_xst (vsi, 0, vsip);
+-}
+-
+-void foo15 (void)
+-{
+-  vec_xst (vui, 0, vuip);
+-}
+-
+-void foo16 (void)
+-{
+-  vec_xst (vss, 0, vssp);
+-}
+-
+-void foo17 (void)
+-{
+-  vec_xst (vus, 0, vusp);
+-}
+-
+-void foo18 (void)
+-{
+-  vec_xst (vsc, 0, vscp);
+-}
+-
+-void foo19 (void)
+-{
+-  vec_xst (vuc, 0, vucp);
+-}
+-
+-void foo20 (void)
+-{
+-  vd = vec_xl (0, dp);
+-}
+-
+-void foo21 (void)
+-{
+-  vsll = vec_xl (0, sllp);
+-}
+-
+-void foo22 (void)
+-{
+-  vull = vec_xl (0, ullp);
+-}
+-
+-void foo23 (void)
+-{
+-  vf = vec_xl (0, fp);
+-}
+-
+-void foo24 (void)
+-{
+-  vsi = vec_xl (0, sip);
+-}
+-
+-void foo25 (void)
+-{
+-  vui = vec_xl (0, uip);
+-}
+-
+-void foo26 (void)
+-{
+-  vss = vec_xl (0, ssp);
+-}
+-
+-void foo27 (void)
+-{
+-  vus = vec_xl (0, usp);
+-}
+-
+-void foo28 (void)
+-{
+-  vsc = vec_xl (0, scp);
+-}
+-
+-void foo29 (void)
+-{
+-  vuc = vec_xl (0, ucp);
+-}
+-
+-void foo30 (void)
+-{
+-  vec_xst (vd, 0, dp);
+-}
+-
+-void foo31 (void)
+-{
+-  vec_xst (vsll, 0, sllp);
+-}
+-
+-void foo32 (void)
+-{
+-  vec_xst (vull, 0, ullp);
+-}
+-
+-void foo33 (void)
+-{
+-  vec_xst (vf, 0, fp);
+-}
+-
+-void foo34 (void)
+-{
+-  vec_xst (vsi, 0, sip);
+-}
+-
+-void foo35 (void)
+-{
+-  vec_xst (vui, 0, uip);
+-}
+-
+-void foo36 (void)
+-{
+-  vec_xst (vss, 0, ssp);
+-}
+-
+-void foo37 (void)
+-{
+-  vec_xst (vus, 0, usp);
+-}
+-
+-void foo38 (void)
+-{
+-  vec_xst (vsc, 0, scp);
+-}
+-
+-void foo39 (void)
+-{
+-  vec_xst (vuc, 0, ucp);
+-}
+Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-3.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-3.c	(.../branches/gcc-6-branch)
+@@ -1,142 +0,0 @@
+-/* { dg-do compile { target { powerpc64-*-* } } } */
+-/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+-/* { dg-options "-mcpu=power8 -O0" } */
+-/* { dg-final { scan-assembler-times "lxvd2x" 16 } } */
+-/* { dg-final { scan-assembler-times "lxvw4x" 8 } } */
+-/* { dg-final { scan-assembler-times "stxvd2x" 16 } } */
+-/* { dg-final { scan-assembler-times "stxvw4x" 8 } } */
+-
+-#include <altivec.h>
+-
+-extern vector double vd, *vdp;
+-extern vector signed long long vsll, *vsllp;
+-extern vector unsigned long long vull, *vullp;
+-extern vector float vf, *vfp;
+-extern vector signed int vsi, *vsip;
+-extern vector unsigned int vui, *vuip;
+-extern double *dp;
+-extern signed long long *sllp;
+-extern unsigned long long *ullp;
+-extern float *fp;
+-extern signed int *sip;
+-extern unsigned int *uip;
+-
+-void foo0 (void)
+-{
+-  vd = vec_xl (0, vdp);
+-}
+-
+-void foo1 (void)
+-{
+-  vsll = vec_xl (0, vsllp);
+-}
+-
+-void foo2 (void)
+-{
+-  vull = vec_xl (0, vullp);
+-}
+-
+-void foo3 (void)
+-{
+-  vf = vec_xl (0, vfp);
+-}
+-
+-void foo4 (void)
+-{
+-  vsi = vec_xl (0, vsip);
+-}
+-
+-void foo5 (void)
+-{
+-  vui = vec_xl (0, vuip);
+-}
+-
+-void foo6 (void)
+-{
+-  vec_xst (vd, 0, vdp);
+-}
+-
+-void foo7 (void)
+-{
+-  vec_xst (vsll, 0, vsllp);
+-}
+-
+-void foo8 (void)
+-{
+-  vec_xst (vull, 0, vullp);
+-}
+-
+-void foo9 (void)
+-{
+-  vec_xst (vf, 0, vfp);
+-}
+-
+-void foo10 (void)
+-{
+-  vec_xst (vsi, 0, vsip);
+-}
+-
+-void foo11 (void)
+-{
+-  vec_xst (vui, 0, vuip);
+-}
+-
+-void foo20 (void)
+-{
+-  vd = vec_xl (0, dp);
+-}
+-
+-void foo21 (void)
+-{
+-  vsll = vec_xl (0, sllp);
+-}
+-
+-void foo22 (void)
+-{
+-  vull = vec_xl (0, ullp);
+-}
+-
+-void foo23 (void)
+-{
+-  vf = vec_xl (0, fp);
+-}
+-
+-void foo24 (void)
+-{
+-  vsi = vec_xl (0, sip);
+-}
+-
+-void foo25 (void)
+-{
+-  vui = vec_xl (0, uip);
+-}
+-
+-void foo26 (void)
+-{
+-  vec_xst (vd, 0, dp);
+-}
+-
+-void foo27 (void)
+-{
+-  vec_xst (vsll, 0, sllp);
+-}
+-
+-void foo28 (void)
+-{
+-  vec_xst (vull, 0, ullp);
+-}
+-
+-void foo29 (void)
+-{
+-  vec_xst (vf, 0, fp);
+-}
+-
+-void foo30 (void)
+-{
+-  vec_xst (vsi, 0, sip);
+-}
+-
+-void foo31 (void)
+-{
+-  vec_xst (vui, 0, uip);
+-}
+Index: gcc/testsuite/gcc.target/powerpc/pr79268.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79268.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79268.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-*-aix* } } */
++/* { dg-options "-mcpu=power8 -O3 " } */
++
++/* Verify that vec_xl and vec_xst accept vector pixel parameters.  */
++
++/* Test case to resolve PR79268.  */
++
++#include <altivec.h>
++
++vector pixel a;
++
++vector pixel
++pr79268 (vector pixel *x)
++{
++  vec_xst (a, 0, x);
++  return vec_xl (0, x);
++}
+Index: gcc/testsuite/gcc.target/powerpc/pr79439.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79439.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79439.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,29 @@
++/* { dg-do compile { target { powerpc64*-*-linux* && lp64 } } } */
++/* { dg-options "-O2 -fpic" } */
++
++/* On the Linux 64-bit ABIs, we should not eliminate NOP in the 'rec' call if
++   -fpic is used because rec can be interposed at link time (since it is
++   external), and the recursive call should call the interposed function.  The
++   Linux 32-bit ABIs do not require NOPs after the BL instruction.  */
++
++int f (void);
++
++void
++g (void)
++{
++}
++
++int
++rec (int a)
++{
++  int ret = 0;
++  if (a > 10 && f ())
++    ret += rec (a - 1);
++  g ();
++  return a + ret;
++}
++
++/* { dg-final { scan-assembler-times {\mbl f\M}   1 } } */
++/* { dg-final { scan-assembler-times {\mbl g\M}   2 } } */
++/* { dg-final { scan-assembler-times {\mbl rec\M} 1 } } */
++/* { dg-final { scan-assembler-times {\mnop\M}    4 } } */
+Index: gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target powerpc_p8vector_ok } */
++/* { dg-options "-mcpu=power8" } */
++
++#include <altivec.h>
++
++vector signed int
++test_vsi_packs_vsll_vsll (vector signed long long x,
++                          vector signed long long y)
++{
++  return vec_packs (x, y);
++}
++
++vector unsigned int
++test_vui_packs_vull_vull (vector unsigned long long x,
++                          vector unsigned long long y)
++{
++  return vec_packs (x, y);
++}
++
++/* Expected test results:
++     test_vsi_packs_vsll_vsll                  1 vpksdss
++     test_vui_packs_vull_vull                  1 vpkudus */
++
++/* { dg-final { scan-assembler-times "vpksdss"  1 } } */
++/* { dg-final { scan-assembler-times "vpkudus"  1 } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr79197.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79197.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79197.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* PR target/79197 */
++/* { dg-do compile } */
++/* { dg-options "-O0 -mno-popcntd" } */
++
++unsigned a;
++
++void
++foo (void)
++{
++  a = *(double *) (__UINTPTR_TYPE__) 0x400000;
++}
+Index: gcc/testsuite/gcc.target/powerpc/vec-xxpermdi.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vec-xxpermdi.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vec-xxpermdi.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,68 @@
++/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
++/* { dg-options "-O2 -mvsx" } */
++
++/* Added for PR79261 to test that vec_xxpermdi works correctly for
++   both BE and LE targets.  */
++
++#include <altivec.h>
++void abort (void);
++
++vector double vdx = { 0.0, 1.0 };
++vector double vdy = { 2.0, 3.0 };
++vector double vdz;
++
++vector signed long long vsllx = { 0, 1 };
++vector signed long long vslly = { 2, 3 };
++vector signed long long vsllz;
++
++vector float vfx = { 0.0, 1.0, 2.0, 3.0 };
++vector float vfy = { 4.0, 5.0, 6.0, 7.0 };
++vector float vfz;
++
++vector signed int vsix = { 0, 1, 2, 3 };
++vector signed int vsiy = { 4, 5, 6, 7 };
++vector signed int vsiz;
++
++vector signed short vssx = { 0, 1, 2, 3, 4, 5, 6, 7 };
++vector signed short vssy = { 8, 9, 10, 11, 12, 13, 14, 15 };
++vector signed short vssz;
++
++vector signed char vscx = { 0, 1, 2, 3, 4, 5, 6, 7,
++			    8, 9, 10, 11, 12, 13, 14, 15 };
++vector signed char vscy = { 16, 17, 18, 19, 20, 21, 22, 23,
++			    24, 25, 26, 27, 28, 29, 30, 31 };
++vector signed char vscz;
++
++int
++main ()
++{
++  vdz = vec_xxpermdi (vdx, vdy, 0b01);
++  if (vdz[0] != 0.0 || vdz[1] != 3.0)
++    abort ();
++
++  vsllz = vec_xxpermdi (vsllx, vslly, 0b10);
++  if (vsllz[0] != 1 || vsllz[1] != 2)
++    abort ();
++
++  vfz = vec_xxpermdi (vfx, vfy, 0b01);
++  if (vfz[0] != 0.0 || vfz[1] != 1.0 || vfz[2] != 6.0 || vfz[3] != 7.0)
++    abort ();
++
++  vsiz = vec_xxpermdi (vsix, vsiy, 0b10);
++  if (vsiz[0] != 2 || vsiz[1] != 3 || vsiz[2] != 4 || vsiz[3] != 5)
++    abort ();
++
++  vssz = vec_xxpermdi (vssx, vssy, 0b00);
++  if (vssz[0] != 0 || vssz[1] != 1 || vssz[2] != 2 || vssz[3] != 3
++      || vssz[4] != 8 || vssz[5] != 9 || vssz[6] != 10 || vssz[7] != 11)
++    abort ();
++
++  vscz = vec_xxpermdi (vscx, vscy, 0b11);
++  if (vscz[0] != 8 || vscz[1] != 9 || vscz[2] != 10 || vscz[3] != 11
++      || vscz[4] != 12 || vscz[5] != 13 || vscz[6] != 14 || vscz[7] != 15
++      || vscz[8] != 24 || vscz[9] != 25 || vscz[10] != 26 || vscz[11] != 27
++      || vscz[12] != 28 || vscz[13] != 29 || vscz[14] != 30 || vscz[15] != 31)
++    abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c	(.../branches/gcc-6-branch)
+@@ -35,6 +35,8 @@
+ /* { dg-final { scan-assembler "xvcmpgesp" } } */
+ /* { dg-final { scan-assembler "xxsldwi" } } */
+ /* { dg-final { scan-assembler-not "call" } } */
++/* { dg-final { scan-assembler "xvcvsxdsp" } } */
++/* { dg-final { scan-assembler "xvcvuxdsp" } } */
+ 
+ extern __vector int si[][4];
+ extern __vector short ss[][4];
+@@ -50,7 +52,9 @@
+ #ifdef __VSX__
+ extern __vector double d[][4];
+ extern __vector long sl[][4];
++extern __vector long long sll[][4];
+ extern __vector unsigned long ul[][4];
++extern __vector unsigned long long ull[][4];
+ extern __vector __bool long bl[][4];
+ #endif
+ 
+@@ -211,3 +215,22 @@
+   d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
+   return i;
+ }
++
++int do_xvcvsxdsp (void)
++{
++  int i = 0;
++
++  f[i][0] = __builtin_vsx_xvcvsxdsp (sll[i][1]); i++;
++
++  return i;
++}
++
++int do_xvcvuxdsp (void)
++{
++  int i = 0;
++
++  f[i][0] = __builtin_vsx_xvcvuxdsp (ull[i][1]); i++;
++
++  return i;
++}
++
+Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++/* { dg-do compile { target { powerpc64le-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
++/* { dg-options "-mcpu=power8 -O3 " } */
++/* { dg-final { scan-assembler-times "lxvw4x" 2 } } */
++/* { dg-final { scan-assembler "stxvw4x" } } */
++/* { dg-final { scan-assembler-not "xxpermdi" } } */
++
++/* Verify that swap optimization does not interfere with element-reversing
++   loads and stores.  */
++
++/* Test case to resolve PR79044.  */
++
++#include <altivec.h>
++
++void pr79044 (float *x, float *y, float *z)
++{
++  vector float a = __builtin_vec_xl (0, x);
++  vector float b = __builtin_vec_xl (0, y);
++  vector float c = __builtin_vec_mul (a, b);
++  __builtin_vec_xst (c, 0, z);
++}
+Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,36 @@
++/* { dg-do compile { target { powerpc64le-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
++/* { dg-options "-mcpu=power8 -O3 " } */
++/* { dg-final { scan-assembler-times "lxvd2x" 2 } } */
++/* { dg-final { scan-assembler-times "stxvd2x" 1 } } */
++/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */
++
++/* Verify that swap optimization works correctly for a VSX direct splat.
++   The three xxpermdi's that are generated correspond to two splats
++   and the __builtin_vsx_xxpermdi.  */
++
++int printf (const char *__restrict __format, ...);
++typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
++
++double s1[] = {2134.3343, 6678.346};
++double s2[] = {41124.234, 6678.346};
++long long dd[] = {1, 2}, d[2];
++union{long long l[2]; double d[2];} e;
++
++void
++foo ()
++{
++  __m128d source1, source2, dest;
++  __m128d a, b, c;
++
++  e.d[1] = s1[1];
++  e.l[0] = !__builtin_isunordered(s1[0], s2[0]) 
++    && s1[0] == s2[0] ? -1 : 0;
++  source1 = __builtin_vec_vsx_ld (0, s1);
++  source2 = __builtin_vec_vsx_ld (0, s2);
++  a = __builtin_vec_splat (source1, 0);
++  b = __builtin_vec_splat (source2, 0);
++  c = (__m128d)__builtin_vec_cmpeq (a, b);
++  dest = __builtin_vsx_xxpermdi (source1, c, 1);
++  *(__m128d *)d = dest;
++}
+Index: gcc/testsuite/gcc.target/powerpc/pr79544.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79544.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79544.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-require-effective-target powerpc_p8vector_ok } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
++/* { dg-options "-mcpu=power8 -O2" } */
++
++#include <altivec.h>
++
++vector unsigned long long
++test_sra (vector unsigned long long x, vector unsigned long long y)
++{
++  return vec_sra (x, y);
++}
++
++vector unsigned long long
++test_vsrad (vector unsigned long long x, vector unsigned long long y)
++{
++  return vec_vsrad (x, y);
++}
++
++/* { dg-final { scan-assembler-times {\mvsrad\M} 2 } } */
++
+Index: gcc/testsuite/gcc.target/arm/pr78255-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/pr78255-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/pr78255-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,57 @@
++/* { dg-do run } */
++/* { dg-options "-O2" }  */
++
++#include <string.h>
++
++struct table_s
++    {
++    void (*fun0)
++        ( void );
++    void (*fun1)
++        ( void );
++    void (*fun2)
++        ( void );
++    void (*fun3)
++        ( void );
++    void (*fun4)
++        ( void );
++    void (*fun5)
++        ( void );
++    void (*fun6)
++        ( void );
++    void (*fun7)
++        ( void );
++    } table;
++
++void callback0(){__asm("mov r0, r0 \n\t");}
++void callback1(){__asm("mov r0, r0 \n\t");}
++void callback2(){__asm("mov r0, r0 \n\t");}
++void callback3(){__asm("mov r0, r0 \n\t");}
++void callback4(){__asm("mov r0, r0 \n\t");}
++
++void test (void) {
++    memset(&table, 0, sizeof table);
++
++    asm volatile ("" : : : "r3");
++
++    table.fun0 = callback0;
++    table.fun1 = callback1;
++    table.fun2 = callback2;
++    table.fun3 = callback3;
++    table.fun4 = callback4;
++    table.fun0();
++}
++
++void foo (void)
++{
++  __builtin_abort ();
++}
++
++int main (void)
++{
++  unsigned long p = (unsigned long) &foo;
++  asm volatile ("mov r3, %0" : : "r" (p));
++  test ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/arm/vfp-longcall-apcs.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/vfp-longcall-apcs.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/vfp-longcall-apcs.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,32 @@
++/* { dg-do run } */
++/* { dg-options "-mapcs-frame -O -foptimize-sibling-calls -ffunction-sections" } */
++
++extern void abort (void);
++
++static __attribute__((noclone, noinline, long_call))
++int foo (int a, int b, int c, int d, double i)
++{
++  return a;
++}
++
++static __attribute__((noclone, noinline))
++double baz (double i)
++{
++  return i;
++}
++
++static __attribute__((noclone, noinline))
++int bar (int a, int b, int c, int d, double i, double j)
++{
++  double l = baz (i) * j;
++  return foo (a, b, c, d, l);
++}
++
++int
++main (void)
++{
++  if (bar (0, 0, 0, 0, 0.0, 0.0) != 0)
++    abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/arm/pr78255-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/pr78255-2.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/pr78255-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++
++extern int bar (void *);
++
++int
++foo (void)
++{
++  return bar ((void*)bar);
++}
++
++/* { dg-final { scan-assembler "bl?\\s+bar" } } */
+Index: gcc/testsuite/gcc.target/arm/pr78041.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/pr78041.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/pr78041.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-fno-inline -mthumb -O1 -mfpu=neon -w" } */
++
++extern void abort (void);
++
++register long long x asm ("r1");
++
++long long f (void)
++{
++  return x << 5;
++}
++
++int main ()
++{
++  x = 0x0100000001;
++  if (f () != 0x2000000020)
++    abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/s390/litpool-str-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/litpool-str-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/litpool-str-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++/* Make sure strings are recognized as being accessible through larl.
++   This requires the symbol ref alignment properly propagated to
++   encode_section_info.  */
++
++/* { dg-do compile } */
++/* { dg-options "-march=z900 -O2 -fpic" } */
++
++
++extern void foo(const char*, const char*, const char*);
++
++void bar(int i)
++{
++  const char t1[10] = "test";
++  const char t2[10] = "test2";
++  const char t3[2][10] = {
++       "foofoofoo",
++       "barbarbar",
++    };
++  foo(t1, t2, t3[i]);
++}
++
++/* { dg-final { scan-assembler-not "GOTOFF" } } */
+Index: gcc/testsuite/gcc.target/sparc/20170228-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/sparc/20170228-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/sparc/20170228-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++/* PR target/79749 */
++/* Reported by Rainer Orth <ro@gcc.gnu.org> */
++
++/* { dg-do run } */
++/* { dg-options "-fomit-frame-pointer" } */
++
++extern void abort (void);
++
++int foo (int x1, int x2, int x3, int x4, int x5, int x6, int x7)
++{
++  return x7;
++}
++
++int main (void)
++{
++  if (foo (100, 200, 300, 400, 500, 600, 700) != 700)
++    abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/aarch64/pr78255.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/pr78255.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr78255.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcmodel=tiny" } */
++
++extern int bar (void *);
++
++int
++foo (void)
++{
++  return bar ((void *)bar);
++}
++
++/* { dg-final { scan-assembler "b\\s+bar" } } */
+Index: gcc/testsuite/gcc.target/aarch64/eh_return.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/eh_return.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/eh_return.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,82 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -fno-inline" } */
++
++#include <stdlib.h>
++#include <stdio.h>
++
++int val, test, failed;
++
++int main (void);
++
++void
++eh0 (void *p)
++{
++  val = (int)(long)p & 7;
++  if (val)
++    abort ();
++}
++
++void
++eh1 (void *p, int x)
++{
++  void *q = __builtin_alloca (x);
++  eh0 (q);
++  __builtin_eh_return (0, p);
++}
++
++void
++eh2a (int a,int b,int c,int d,int e,int f,int g,int h, void *p)
++{
++  val = a + b + c + d + e + f + g + h +  (int)(long)p & 7;
++}
++
++void
++eh2 (void *p)
++{
++  eh2a (val, val, val, val, val, val, val, val, p);
++  __builtin_eh_return (0, p);
++}
++
++
++void
++continuation (void)
++{
++  test++;
++  main ();
++}
++
++void
++fail (void)
++{
++  failed = 1;
++  printf ("failed\n");
++  continuation ();
++}
++
++void
++do_test1 (void)
++{
++  if (!val)
++    eh1 (continuation, 100);
++  fail ();
++}
++
++void
++do_test2 (void)
++{
++  if (!val)
++    eh2 (continuation);
++  fail ();
++}
++
++int
++main (void)
++{
++  if (test == 0)
++    do_test1 ();
++  if (test == 1)
++    do_test2 ();
++  if (failed || test != 2)
++    exit (1);
++  exit (0);
++}
+Index: gcc/testsuite/gcc.target/i386/pr49095.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr49095.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr49095.c	(.../branches/gcc-6-branch)
+@@ -1,7 +1,7 @@
+ /* PR rtl-optimization/49095 */
+ /* { dg-do compile } */
+-/* { dg-options "-Os" } */
+-/* { dg-options "-Os -mregparm=2" { target ia32 } } */
++/* { dg-options "-Os -fno-shrink-wrap" } */
++/* { dg-additional-options "-mregparm=2" { target ia32 } } */
+ 
+ void foo (void *);
+ 
+@@ -70,5 +70,4 @@
+ G (int)
+ G (long)
+ 
+-/* See PR61225 for the XFAIL.  */
+-/* { dg-final { scan-assembler-not "test\[lq\]" { xfail { ia32 } } } } */
++/* { dg-final { scan-assembler-not "test\[lq\]" } } */
+Index: gcc/testsuite/gcc.target/i386/pr79514.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr79514.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr79514.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++/* PR target/79514 */
++/* { dg-do compile } */
++/* { dg-options "-m96bit-long-double" } */
++
++extern void bar (long double);
++
++extern long double x;
++
++void foo (void)
++{
++  bar (x);
++}
+Index: gcc/testsuite/gcc.target/i386/pr80019.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr80019.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr80019.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++/* PR target/80019 */
++/* { dg-do compile } */
++/* { dg-options "-O2 -mxop -mavx2" } */
++
++typedef char v16qi __attribute__ ((vector_size (16)));
++
++extern v16qi b, c;
++
++void
++foo (int e)
++{
++  b = c << e;
++}
+Index: gcc/testsuite/gcc.target/i386/pr79495.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr79495.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr79495.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* PR target/79495 */
++/* { dg-do compile } */
++/* { dg-options "-O2 -msoft-float" } */
++
++long double dnan = 1.0l/0.0l - 1.0l/0.0l;
++long double x = 1.0l;
++void fn1 (void)
++{
++  if (dnan != x)
++    x = 1.0;
++}
+Index: gcc/testsuite/g++.old-deja/g++.abi/vtable2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.abi/vtable2.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.old-deja/g++.abi/vtable2.C	(.../branches/gcc-6-branch)
+@@ -142,10 +142,24 @@
+ #define INC_VDATA(A,N)	((A) += 2*(N))
+ #endif
+ #else
++// HPPA uses function pointers but they point to function descriptors.
++#if defined __hppa__
++#ifdef __hpux__
++#ifdef _LP64
++#define CMP_VPTR(A, B)	(*(unsigned long *)(*(A)+16) == *(unsigned long *)((unsigned long)(B)+16))
++#else
+ #define CMP_VPTR(A, B)	(*(A) == (ptrdiff_t)(B))
++#endif /* _LP64 */
++#else
++extern "C" { unsigned int __canonicalize_funcptr_for_compare (void*); }
++#define CMP_VPTR(A, B) (__canonicalize_funcptr_for_compare(*(void **)A) == __canonicalize_funcptr_for_compare((void *)B))
++#endif /* __hpux__ */
++#else
++#define CMP_VPTR(A, B)	(*(A) == (ptrdiff_t)(B))
++#endif /* __hppa__ */
+ #define INC_VPTR(A)	((A) += 1)
+ #define INC_VDATA(A,N)	((A) += (N))
+-#endif
++#endif /* __ia64__ */
+ 
+ int main ()
+ {
+Index: gcc/testsuite/gfortran.dg/gomp/pr78866-1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/gomp/pr78866-1.f90	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/gomp/pr78866-1.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++! PR fortran/78866
++! { dg-do compile }
++
++subroutine pr78866(x)
++  integer :: x(*)
++!$omp target map(x)			! { dg-error "Assumed size array" }
++  x(1) = 1
++!$omp end target
++!$omp target data map(tofrom: x)	! { dg-error "Assumed size array" }
++!$omp target update to(x)		! { dg-error "Assumed size array" }
++!$omp target update from(x)		! { dg-error "Assumed size array" }
++!$omp end target data
++!$omp target map(x(:23))		! { dg-bogus "Assumed size array" }
++  x(1) = 1
++!$omp end target
++!$omp target map(x(:))			! { dg-error "upper bound of assumed size array section" }
++  x(1) = 1				! { dg-error "not a proper array section" "" { target *-*-* } .-1 }
++!$omp end target
++end
+Index: gcc/testsuite/gfortran.dg/gomp/pr78866-2.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/gomp/pr78866-2.f90	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/gomp/pr78866-2.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++! PR fortran/78866
++! { dg-do compile }
++
++subroutine pr78866(x)
++  integer :: x(*)
++!$omp target		! { dg-error "implicit mapping of assumed size array" }
++  x(1) = 1
++!$omp end target
++end
+Index: gcc/testsuite/gfortran.dg/gomp/map-1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/gomp/map-1.f90	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/gomp/map-1.f90	(.../branches/gcc-6-branch)
+@@ -70,7 +70,7 @@
+   ! { dg-error "Rightmost upper bound of assumed size array section not specified" "" { target *-*-* } 68 }
+   ! { dg-error "'aas' in MAP clause at \\\(1\\\) is not a proper array section" "" { target *-*-* } 68 }
+ 
+-  !$omp target map(aas) ! { dg-error "The upper bound in the last dimension must appear" "" { xfail *-*-* } }
++  !$omp target map(aas) ! { dg-error "Assumed size array" }
+   !$omp end target
+ 
+   !$omp target map(aas(5:7))
+Index: gcc/testsuite/gfortran.dg/coarray_event_1.f08
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/coarray_event_1.f08	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/coarray_event_1.f08	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++! { dg-do compile }
++! { dg-options "-fcoarray=lib -lcaf_single" }
++
++! Check that pr70696 is really fixed.
++
++  use iso_fortran_env
++  type(event_type) :: x[*]
++
++  ! exchange must not be called or the link problem before the patch
++  ! does not occur.
++contains
++  subroutine exchange
++    event post (x[1])
++  end subroutine
++end 
+Index: gcc/testsuite/gfortran.dg/submodule_22.f08
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/submodule_22.f08	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/submodule_22.f08	(.../branches/gcc-6-branch)
+@@ -0,0 +1,47 @@
++! { dg-do compile }
++!
++! Test the fix for PR78474.
++!
++! Contributed by Nicholas Brearly  <nick.brealey@cobham.com>
++!
++module mtop
++  implicit none
++  real :: r
++  interface
++    module subroutine sub1()
++    end subroutine
++  end interface
++  interface
++    module subroutine sub2()
++    end subroutine
++  end interface
++  interface
++    module subroutine sub3()
++    end subroutine
++  end interface
++end module mtop
++
++submodule (mtop) submod
++  implicit none
++  real :: s
++contains
++  module subroutine sub1
++    r = 0.0
++  end subroutine sub1
++end
++
++submodule (mtop:submod) subsubmod
++contains
++  module subroutine sub2
++    r = 1.0
++    s = 1.0
++  end subroutine sub2
++end
++
++submodule (mtop:submod:subsubmod) subsubsubmod ! { dg-error "Syntax error in SUBMODULE statement" }
++contains
++  module subroutine sub3
++    r = 2.0
++    s = 2.0
++  end subroutine sub3
++end
+Index: gcc/testsuite/gfortran.dg/submodule_21.f08
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/submodule_21.f08	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/submodule_21.f08	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++! { dg-do compile }
++!
++! Test the fix for PR78331.
++!
++! Reported on https://groups.google.com/forum/#!topic/comp.lang.fortran/NFCF9brKksg
++!
++MODULE MainModule
++END MODULE MainModule
++
++SUBMODULE (MainModule) MySub1
++  IMPLICIT NONE
++  INTEGER, PARAMETER :: a = 17
++END SUBMODULE MySub1
++
++PROGRAM MyProg
++  USE MainModule
++  WRITE(*,*) a
++END PROGRAM MyProg
++! { dg-excess-errors "does not contain a MODULE PROCEDURE" }
+Index: gcc/testsuite/gfortran.dg/fimplicit_none_2.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/fimplicit_none_2.f90	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/fimplicit_none_2.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++! { dg-do compile }
++! { dg-options "-fimplicit-none" }
++! PR fortran/78239 - used to ICE
++program p
++   character(*), parameter :: z(2) = [character(n) :: 'x', 'y'] ! { dg-error "Scalar INTEGER expression expected" }
++end
+Index: gcc/testsuite/gfortran.dg/coarray_43.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/coarray_43.f90	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/coarray_43.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++! { dg-do link }
++! { dg-options "-fcoarray=lib -lcaf_single" }
++
++program coarray_43
++  implicit none
++  integer, parameter :: STR_LEN = 50
++  character(len=STR_LEN) :: str[*]
++  integer :: pos
++  write(str,"(2(a,i2))") "Greetings from image ",this_image()," of ",num_images()
++  block
++    pos = scan(str[5], set="123456789")
++  end block
++end program
+Index: gcc/testsuite/gfortran.dg/fimplicit_none_1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/fimplicit_none_1.f90	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/fimplicit_none_1.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++! { dg-do compile }
++! { dg-options "-fimplicit-none" }
++subroutine s(n) ! { dg-error "has no IMPLICIT type" }
++   character(n) :: c  ! { dg-error "Scalar INTEGER expression expected" }
++   c = 'c' ! { dg-error "has no IMPLICIT type" }
++end
+Index: gcc/testsuite/gfortran.dg/coarray/event_3.f08
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/coarray/event_3.f08	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/coarray/event_3.f08	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++! { dg-do run }
++!
++! Check PR fortran/70696 is fixed.
++
++program global_event
++  use iso_fortran_env , only : event_type
++  implicit none
++  type(event_type) :: x[*]
++  
++  call exchange
++  contains
++    subroutine exchange
++      integer :: cnt
++      event post(x[1])
++      event post(x[1])
++      call event_query(x, cnt)
++      if (cnt /= 2) error stop 1
++      event wait(x, until_count=2)
++    end subroutine
++end 
+Index: gcc/testsuite/gfortran.dg/coarray/event_4.f08
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/coarray/event_4.f08	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/coarray/event_4.f08	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++! { dg-do run }
++!
++! Check that pr 70697 is fixed.
++
++program event_4
++  use iso_fortran_env
++  integer :: nc(1)
++  type(event_type) done[*]
++  nc(1) = 1
++  event post(done[1])
++  event wait(done,until_count=nc(1))
++end
+Index: gcc/testsuite/gcc.c-torture/execute/pr79121.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr79121.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr79121.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,34 @@
++extern void abort (void);
++
++__attribute__ ((noinline, noclone)) unsigned long long f1 (int x)
++{
++  return ((unsigned long long) x) << 4;
++}
++
++__attribute__ ((noinline, noclone)) long long f2 (unsigned x)
++{
++  return ((long long) x) << 4;
++}
++
++__attribute__ ((noinline, noclone)) unsigned long long f3 (unsigned x)
++{
++  return ((unsigned long long) x) << 4;
++}
++
++__attribute__ ((noinline, noclone)) long long f4 (int x)
++{
++  return ((long long) x) << 4;
++}
++
++int main ()
++{
++  if (f1 (0xf0000000) != 0xffffffff00000000)
++    abort ();
++  if (f2 (0xf0000000) != 0xf00000000)
++    abort ();
++  if (f3 (0xf0000000) != 0xf00000000)
++    abort ();
++  if (f4 (0xf0000000) != 0xffffffff00000000)
++    abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr79043.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr79043.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr79043.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++/* PR ipa/78791 */
++
++int val;
++
++int *ptr = &val;
++float *ptr2 = &val;
++
++static
++__attribute__((always_inline, optimize ("-fno-strict-aliasing")))
++typepun ()
++{
++  *ptr2=0;
++}
++
++main()
++{
++  *ptr=1;
++  typepun ();
++  if (*ptr)
++    __builtin_abort ();
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr77767.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr77767.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr77767.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++/* PR c/77767 */
++
++void
++foo (int a, int b[a++], int c, int d[c++])
++{
++  if (a != 2 || c != 2)
++    __builtin_abort ();
++}
++
++int
++main ()
++{
++  int e[10];
++  foo (1, e, 1, e);
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr78617.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr78617.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr78617.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,25 @@
++int a = 0;
++int d = 1;
++int f = 1;
++
++int fn1() {
++  return a || 1 >> a;
++}
++
++int fn2(int p1, int p2) {
++  return p2 >= 2 ? p1 : p1 >> 1;
++}
++
++int fn3(int p1) {
++  return d ^ p1;
++}
++
++int fn4(int p1, int p2) {
++  return fn3(!d > fn2((f = fn1() - 1000) || p2, p1));
++}
++
++int main() {
++  if (fn4(0, 0) != 1)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/compile/pr79197.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/compile/pr79197.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr79197.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++/* PR target/79197 */
++
++unsigned long b;
++
++unsigned long
++foo (float *a, float *x)
++{
++  __builtin_memcpy (a, x, sizeof (float));
++  return *a;
++}
+Index: gcc/testsuite/gcc.c-torture/compile/pr79411.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/compile/pr79411.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr79411.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++/* PR tree-optimization/79411 */
++
++typedef struct __jmp_buf_tag { char buf[1024]; } jmp_buf[1];
++extern int setjmp (jmp_buf);
++extern int bar (unsigned int *);
++extern jmp_buf *baz (void);
++struct C { int c1; unsigned int c2, c3, c4; };
++
++void
++foo (struct C *x, const int *y, unsigned int *z, unsigned int e, unsigned int g)
++{
++  unsigned int d = 0;
++  unsigned long f;
++  setjmp (*baz ());
++  f = 1 + d;
++  if ((x->c1 || x->c2) && g && (!e || d >= 8))
++    d = 16;
++  else
++    d = 8;
++  if ((!x->c3 && !x->c4 || *y == 0) && !e && bar (z))
++    *z = 1 + f;
++}
+Index: gcc/testsuite/gnat.dg/array28.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array28.adb	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array28.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++-- { dg-do run }
++-- { dg-options "-O" }
++
++with Array28_Pkg; use Array28_Pkg;
++
++procedure Array28 is
++
++  function Get return Outer_type is
++    Ret : Outer_Type;
++  begin
++    Ret (Inner_Type'Range) := F;
++    return Ret;
++  end;
++
++  A : Outer_Type := Get;
++  B : Inner_Type := A (Inner_Type'Range);
++
++begin
++  if B /= "12345" then
++    raise Program_Error;
++  end if;
++end;
+Index: gcc/testsuite/gnat.dg/opt63.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/opt63.adb	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/opt63.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++-- { dg-do compile }
++-- { dg-options "-O -gnatws" }
++
++procedure Opt63 is
++
++   type T_MOD is mod 2**32;
++   subtype T_INDEX is T_MOD range 3_000_000_000 .. 4_000_000_000;
++   type T_ARRAY is array(T_INDEX range <>) of INTEGER;
++
++   function Build_Crash(First : T_INDEX; Length : NATURAL) return T_ARRAY is
++      R : T_ARRAY(First .. T_Index'Val (T_Index'Pos (First) + Length))
++             := (others => -1); -- Crash here
++   begin
++      return R;
++   end;
++
++begin
++   null;
++end;
+Index: gcc/testsuite/gnat.dg/array26_pkg.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array26_pkg.adb	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array26_pkg.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++package body Array26_Pkg is
++
++  function F return Inner_Type is
++  begin
++    return "123";
++  end;
++
++end Array26_Pkg;
+Index: gcc/testsuite/gnat.dg/array26_pkg.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array26_pkg.ads	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array26_pkg.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++package Array26_Pkg is
++
++  subtype Outer_Type is String (1 .. 4);
++  subtype Inner_Type is String (1 .. 3);
++
++  function F return Inner_Type;
++
++end Array26_Pkg;
+Index: gcc/testsuite/gnat.dg/array27_pkg.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array27_pkg.adb	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array27_pkg.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++package body Array27_Pkg is
++
++  function F return Inner_Type is
++  begin
++    return "123";
++  end;
++
++end Array27_Pkg;
+Index: gcc/testsuite/gnat.dg/array27_pkg.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array27_pkg.ads	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array27_pkg.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++package Array27_Pkg is
++
++  subtype Outer_Type is String (1 .. 8);
++  subtype Inner_Type is String (1 .. 3);
++
++  function F return Inner_Type;
++
++end Array27_Pkg;
+Index: gcc/testsuite/gnat.dg/array26.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array26.adb	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array26.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++-- { dg-do run }
++-- { dg-options "-O" }
++
++with Array26_Pkg; use Array26_Pkg;
++
++procedure Array26 is
++
++  function Get return Outer_type is
++    Ret : Outer_Type;
++  begin
++    Ret (Inner_Type'Range) := F;
++    return Ret;
++  end;
++
++  A : Outer_Type := Get;
++  B : Inner_Type := A (Inner_Type'Range);
++
++begin
++  if B /= "123" then
++    raise Program_Error;
++  end if;
++end;
+Index: gcc/testsuite/gnat.dg/array27.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array27.adb	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array27.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++-- { dg-do run }
++-- { dg-options "-O" }
++
++with Array27_Pkg; use Array27_Pkg;
++
++procedure Array27 is
++
++  function Get return Outer_type is
++    Ret : Outer_Type;
++  begin
++    Ret (Inner_Type'Range) := F;
++    return Ret;
++  end;
++
++  A : Outer_Type := Get;
++  B : Inner_Type := A (Inner_Type'Range);
++
++begin
++    if B /= "123" then
++    raise Program_Error;
++  end if;
++end;
+Index: gcc/testsuite/gnat.dg/array28_pkg.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array28_pkg.adb	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array28_pkg.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++package body Array28_Pkg is
++
++  function F return Inner_Type is
++  begin
++    return "12345";
++  end;
++
++end Array28_Pkg;
+Index: gcc/testsuite/gnat.dg/array28_pkg.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array28_pkg.ads	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array28_pkg.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++package Array28_Pkg is
++
++  subtype Outer_Type is String (1 .. 8);
++  subtype Inner_Type is String (1 .. 5);
++
++  function F return Inner_Type;
++
++end Array28_Pkg;
+Index: gcc/testsuite/gcc.dg/vector-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/vector-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/vector-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* { dg-do compile } */
++/* { dg-options "-std=gnu90" } */
++
++typedef int V __attribute__ ((vector_size(4)));
++void fn1 ()
++{
++  (V){(1,0)}[0] = 0;
++}
+Index: gcc/testsuite/gcc.dg/goacc/loop-processing-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/goacc/loop-processing-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/goacc/loop-processing-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++/* Make sure that OpenACC loop processing happens.  */
++/* { dg-additional-options "-O2 -fdump-tree-oaccdevlow" } */
++
++extern int place ();
++
++void vector_1 (int *ary, int size)
++{
++#pragma acc parallel num_workers (32) vector_length(32) copy(ary[0:size]) firstprivate (size)
++  {
++#pragma acc loop gang
++    for (int jx = 0; jx < 1; jx++)
++#pragma acc loop auto
++      for (int ix = 0; ix < size; ix++)
++	ary[ix] = place ();
++  }
++}
++
++/* { dg-final { scan-tree-dump "OpenACC loops.*Loop 0\\\(0\\\).*Loop 14\\\(1\\\).*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, 0, 1, 20\\\);.*Head-0:.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, 0, 1, 20\\\);.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, \\\.data_dep\\\.\[0-9_\]+, 0\\\);.*Tail-0:.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, \\\.data_dep\\\.\[0-9_\]+, 1\\\);.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, \\\.data_dep\\\.\[0-9_\]+, 0\\\);.*Loop 6\\\(4\\\).*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, 0, 1, 6\\\);.*Head-0:.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, 0, 1, 6\\\);.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, \\\.data_dep\\\.\[0-9_\]+, 2\\\);.*Tail-0:.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, \\\.data_dep\\\.\[0-9_\]+, 1\\\);.*\\\.data_dep\\\.\[0-9_\]+ = UNIQUE \\\(\[0-9\]+, \\\.data_dep\\\.\[0-9_\]+, 2\\\);" "oaccdevlow" } } */
+Index: gcc/testsuite/gcc.dg/spellcheck-options-13.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/spellcheck-options-13.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/spellcheck-options-13.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++/* PR driver/78863.  */
++
++/* { dg-do compile } */
++/* { dg-options "-fsanitize" } */
++/* { dg-error "unrecognized command line option .-fsanitize..$" "" { target *-*-* } 0 } */
+Index: gcc/testsuite/gcc.dg/fixed-point/pr79971.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/fixed-point/pr79971.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/fixed-point/pr79971.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O3" } */
++
++void
++a ()
++{
++  unsigned _Accum b;
++  for (b = 0.1; b; b += 0.1uk)
++    {
++      _Sat unsigned _Accum b;
++      for (b = 0; b <= 0.8; b = 0.1)
++	;
++    }
++}
+Index: gcc/testsuite/gcc.dg/graphite/pr71824-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/graphite/pr71824-2.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/graphite/pr71824-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,34 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -floop-nest-optimize" } */
++
++typedef struct { float x1; } bx;
++typedef struct {
++    int w;
++    short o;
++} T2P;
++T2P a;
++int b;
++void fn2();
++void fn3(bx*,short);
++void fn1() {
++    unsigned i = 0;
++    int c;
++    bx *d;
++    bx **h;
++    if (b == 0) {
++	fn2();
++	return;
++    }
++    for (; c; c++)
++      for (; i < 100; i++) {
++	  d = h[i];
++	  d->x1 = a.w;
++      }
++    for (; i < 100; i++) {
++	d = h[i];
++	d->x1 = a.w;
++    }
++    if (a.o)
++      for (; b;)
++	fn3(d, a.o);
++}
+Index: gcc/testsuite/gcc.dg/graphite/pr71824-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/graphite/pr71824-3.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/graphite/pr71824-3.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -ftree-loop-distribution -floop-nest-optimize" } */
++
++struct
++{
++  int bz;
++} od, ka[2];
++
++int fw;
++
++void
++pc (void)
++{
++  for (od.bz = 0; od.bz < 2; ++od.bz)
++    {
++      ++fw;
++      ka[0] = ka[1];
++    }
++}
+Index: gcc/testsuite/gcc.dg/graphite/pr71824.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/graphite/pr71824.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/graphite/pr71824.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -floop-nest-optimize" } */
++
++int a, b, d;
++int **c;
++int fn1() {
++    while (a)
++      if (d) {
++	  int e = -d;
++	  for (; b < e; b++)
++	    c[b] = &a;
++      } else {
++	  for (; b; b++)
++	    c[b] = &b;
++	  d = 0;
++      }
++}
+Index: gcc/testsuite/gcc.dg/graphite/pr79977.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/graphite/pr79977.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/graphite/pr79977.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -floop-nest-optimize" } */
++
++int uo[3];
++int di;
++
++void
++i7 (int mp)
++{
++  int l4;
++
++wh:
++  while (l4 > 1)
++    {
++      for (di = 0; di < 2; ++di)
++	uo[di] = 0;
++
++      for (di = 0; di < 3; ++di)
++	{
++	  uo[di] = 0;
++	  if (mp != 0)
++	    goto wh;
++	}
++
++      --l4;
++    }
++}
+Index: gcc/testsuite/gcc.dg/comp-goto-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/comp-goto-4.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/comp-goto-4.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++/* PR middle-end/79537 */
++/* { dg-do compile } */
++/* { dg-options "" } */
++/* { dg-require-effective-target indirect_jumps } */
++/* { dg-require-effective-target label_values } */
++
++void
++f (void)
++{
++L:
++  *&&L;
++}
++
++void
++f2 (void)
++{
++   void *p;
++L:
++   p = &&L;
++   *p; /* { dg-warning "dereferencing 'void \\*' pointer" } */
++}
+Index: gcc/testsuite/gcc.dg/lto/pr69188_0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr69188_0.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr69188_0.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* PR ipa/69188 */
++/* { dg-lto-do link } */
++/* { dg-lto-options { { -flto -O0 -fprofile-generate } } } */
++/* { dg-require-profiling "-fprofile-generate" } */
++
++void fn1(void)
++{
++}
+Index: gcc/testsuite/gcc.dg/lto/pr50199_0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr50199_0.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr50199_0.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* PR middle-end/50199 */
++/* { dg-lto-options {{-O2 -flto -fno-merge-constants --param=lto-min-partition=1}} } */
++
++__attribute__ ((noinline)) const char *
++foo (const char *x)
++{
++  return x;
++}
++
++int
++main ()
++{
++  const char *a = "ab";
++  if (a != foo (a))
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/lto/pr69188_1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr69188_1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr69188_1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++/* PR ipa/69188 */
++/* { dg-options "-flto -O1 -fprofile-generate" } */
++
++extern void fn1(void);
++
++int main() {
++  fn1();
++  return 0;
++}
++
+Index: gcc/testsuite/gcc.dg/torture/pr79536.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr79536.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr79536.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++
++typedef int A;
++int
++fn1 (A x, A y)
++{
++  if ((x + (x - y) * 1i) != -(-x + (y - x) * 1i))
++    return 1;
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/torture/pr71055.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr71055.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr71055.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++/* { dg-do run } */
++
++extern void abort (void);
++union U { int i; _Bool b; char c; };
++void __attribute__((noinline,noclone))
++foo (union U *u)
++{
++  if (u->c != 0)
++    abort ();
++}
++int main()
++{
++  union U u;
++  u.i = 10;
++  u.b = 0;
++  foo (&u);
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/torture/pr79666.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr79666.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr79666.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,30 @@
++/* { dg-do run } */
++
++struct
++{
++  unsigned a:6;
++} b;
++
++int c, e, g = 7;
++signed char d, f = 6, h = -10;
++
++void fn1 ()
++{
++  for (; c < 9; c++)
++    {
++      if (f)
++	g = ~(~0 / (g ^ e));
++      b.a = ~0;
++      d = ~((h ^ b.a) & 132 & (~(f && g) | (d && 1)));
++      e = ~0;
++      if (d < 127 || f < 1)
++	continue;
++      g = 0;
++    }
++}
++
++int main ()
++{
++  fn1 ();
++  return 0; 
++}
+Index: gcc/testsuite/gcc.dg/torture/pr78742.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr78742.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr78742.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target int128 } */
++
++void foo();
++
++void func()
++{
++  int m;
++
++  int tab[m];
++
++  __int128 j;
++  for(; j; j++)
++    {
++      tab[j] = 0;
++      tab[j+1] = 0;
++    }
++
++  foo();
++}
+Index: gcc/testsuite/gcc.dg/torture/pr79732.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr79732.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr79732.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++/* { dg-do link } */
++
++int bar () __attribute__ ((alias ("foo")));
++void foo () { }
++int main () { return bar(); }
+Index: gcc/testsuite/gcc.dg/tree-ssa/pr78886.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr78886.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr78886.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++void *malloc(unsigned long x);
++
++void foo(void)
++{
++ volatile int i;
++ malloc(1);
++ i;
++}
+Index: gcc/testsuite/gcc.dg/tree-ssa/pr78428.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr78428.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr78428.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,27 @@
++/* PR tree-optimization/78428.  */
++/* { dg-options "-O2" } */
++/* { dg-do run } */
++
++struct S0
++{
++  int f2;
++  int f3:16;
++  int f4:18;
++} ;
++
++int a = 5;
++struct S0 b = { 3, 0, 0 };
++static struct S0 global[2] = { { 77, 0, 78 }, { 77, 0, 78 } };
++
++int main ()
++{
++  volatile struct S0 *j;
++  for (; a;)
++    {
++      __builtin_printf ("", b.f2);
++      j = &b;
++      *j = global[1];
++      a--;
++    }
++  return 0;
++}
+Index: gcc/testsuite/ChangeLog
+===================================================================
+--- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,543 @@
++2017-03-16  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-02-28  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79732
++	* gcc.dg/torture/pr79732.c: New testcase.
++
++2017-03-15  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/80019
++	* gcc.target/i386/pr80019.c: New test.
++
++2017-03-15  Marek Polacek  <polacek@redhat.com>
++
++	Backported from mainline
++	2016-12-14  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/72775
++	* g++.dg/ext/flexary12.C: Adjust dg-error.
++	* g++.dg/ext/flexary20.C: New.
++	* g++.dg/ext/flexary21.C: New.
++
++2017-03-14  Marek Polacek  <polacek@redhat.com>
++
++	Backported from mainline
++	2017-03-09  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/79900 - ICE in strip_typedefs
++	* g++.dg/warn/Wpadded-1.C: New test.
++
++	PR c++/79687
++	* g++.dg/expr/ptrmem8.C: New test.
++	* g++.dg/expr/ptrmem9.C: New test.
++
++	Backported from mainline
++	2017-01-31  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/79264
++	* g++.dg/cpp1y/pr61636-1.C: Augment.
++
++	Backported from mainline
++	2017-01-17  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/61636
++	* g++.dg/cpp1y/pr61636-1.C: New.
++	* g++.dg/cpp1y/pr61636-2.C: New.
++	* g++.dg/cpp1y/pr61636-3.C: New.
++
++2017-03-14  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/79962
++	PR c++/79984
++	* c-c++-common/nonnull-3.c: New test.
++	* g++.dg/warn/Wnonnull3.C: New test.
++
++2017-03-14  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-03-09  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79977
++	* gcc.dg/graphite/pr79977.c: New testcase.
++
++	2017-03-09  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/79971
++	* gcc.dg/fixed-point/pr79971.c: New testcase.
++
++	2017-03-02  Richard Biener  <rguenther@suse.de>
++
++	PR c/79756
++	* gcc.dg/vector-1.c: New testcase.
++
++	2017-02-22  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79666
++	* gcc.dg/torture/pr79666.c: New testcase.
++
++2017-03-07  Marek Polacek  <polacek@redhat.com>
++
++	Backported from mainline
++	2017-03-06  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/79796 - ICE with NSDMI and this pointer
++	* g++.dg/cpp0x/nsdmi13.C: New test.
++
++2017-03-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2017-03-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/79439
++	* gcc.target/powerpc/pr79439.c: New test.
++
++2017-03-02  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/79514
++	* gcc.target/i386/pr79514.c: New test.
++
++2017-03-01  Pat Haugen  <pthaugen@us.ibm.com>
++
++	Backport from mainline:
++	2017-03-01  Pat Haugen  <pthaugen@us.ibm.com>
++
++	* gcc.target/powerpc/pr79544.c: Add test for vec_vsrad and fix up
++	scan string.
++
++	2017-02-27  Pat Haugen  <pthaugen@us.ibm.com>
++
++	PR target/79544
++	* gcc.target/powerpc/pr79544.c: New.
++
++2017-02-28  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc.target/sparc/20170228-1.c: New test.
++
++2017-02-25  Paul Thomas  <pault@gcc.gnu.org>
++
++	PR fortran/78474
++	* gfortran.dg/submodule_22.f08: New test.
++
++	PR fortran/78331
++	* gfortran.dg/submodule_21.f08: New test.
++
++2017-02-24  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gnat.dg/opt63.adb: New test.
++
++2017-02-23  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/79268
++	* gcc.target/powerpc/pr79268.c: Enable for BE targets also.
++
++2017-02-22  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-02-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/79261
++	* gcc.target/powerpc/vec-xxpermdi.c: New file.
++
++2017-02-20  Marek Polacek  <polacek@redhat.com>
++
++	Backport from mainline
++	2017-02-20  Marek Polacek  <polacek@redhat.com>
++
++	PR middle-end/79537
++	* gcc.dg/comp-goto-4.c: New.
++
++	PR sanitizer/79558
++	* c-c++-common/ubsan/bounds-14.c: New test.
++
++2017-02-20  Marek Polacek  <polacek@redhat.com>
++
++	Backport from mainline
++	2017-02-17  Marek Polacek  <polacek@redhat.com>
++
++	PR middle-end/79536
++	* gcc.dg/torture/pr79536.c: New test.
++
++2017-01-17  Carl Love  <cel@us.ibm.com>
++
++	Backport from mainline commit r245460 on 2017-02-14
++
++	PR 79545
++	* gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
++	xvcvsxdsp and xvcvuxdsp instructions.
++
++2017-02-16  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-02-09  Marek Polacek  <polacek@redhat.com>
++
++	PR c/79428
++	* c-c++-common/cilk-plus/CK/pr79428-4.c: New test.
++	* c-c++-common/cilk-plus/CK/pr79428-7.c: New test.
++	* c-c++-common/gomp/pr79428-2.c: New test.
++	* c-c++-common/gomp/pr79428-5.c: New test.
++	* c-c++-common/gomp/pr79428-6.c: New test.
++	* c-c++-common/pr79428-3.c: New test.
++
++2017-02-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-02-10  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/79411
++	* gcc.c-torture/compile/pr79411.c: New test.
++
++	2017-02-09  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/79429
++	* c-c++-common/gomp/pr79429.c: New test.
++	* g++.dg/gomp/pr79429.C: New test.
++
++	PR c/79431
++	* c-c++-common/gomp/pr79431.c: New test.
++
++	2017-02-06  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/79377
++	* g++.dg/lookup/pr79377.C: New test.
++
++	2017-02-02  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/79197
++	* gcc.target/powerpc/pr79197.c: New test.
++	* gcc.c-torture/compile/pr79197.c: New test.
++
++	2017-01-31  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/79267
++	* g++.dg/opt/pr79267.C: New test.
++
++2017-02-14  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/79495
++	* gcc.target/i386/pr79495.c: New test.
++
++	PR middle-end/61225
++	* gcc.target/i386/pr49095.c: Add -fno-shrink-wrap to dg-options.
++	Use dg-additional-options for ia32 target.  Remove XFAIL.
++
++2017-02-13  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/79296
++	* g++.dg/cpp0x/pr79296.C: New.
++
++2017-02-08  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-02-08  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/71824
++	PR tree-optimization/79409
++	* gcc.dg/graphite/pr71824-3.c: New testcase.
++
++	2017-02-08  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/71824
++	* gcc.dg/graphite/pr71824-2.c: New testcase.
++
++	2017-02-01  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/71824
++	* gcc.dg/graphite/pr71824.c: New testcase.
++
++2017-02-03  Carl Love  <cel@us.ibm.com>
++
++	* gcc.target/powerpc/builtins-3-p8.c:  Add new testfile for missing
++	vec_packs built-in tests.
++
++2017-02-03  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-27  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/65484
++	* g++.dg/vect/pr36648.cc: Modify to reflect that the loop is not
++	vectorized on POWER unless hardware misaligned loads are
++	available.
++
++2017-01-31  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/79268
++	* gcc.target/powerpc/pr79268.c: New file.
++	* gcc.target/powerpc/vsx-elemrev-1.c: Delete file.
++	* gcc.target/powerpc/vsx-elemrev-2.c: Likewise.
++	* gcc.target/powerpc/vsx-elemrev-3.c: Likewise.
++	* gcc.target/powerpc/vsx-elemrev-4.c: Likewise.
++
++2017-01-29  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	Backport from trunk
++	2017-01-13  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	PR fortran/70697
++	* gfortran.dg/coarray/event_4.f08: New test.
++
++2017-01-29  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	Backport from trunk
++	2017-01-19  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	PR fortran/70696
++	* gfortran.dg/coarray_43.f90: New test.
++
++	2017-01-18  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	PR fortran/70696
++	* gfortran.dg/coarray_event_1.f08: New test.
++
++	2017-01-13  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	PR fortran/70696
++	* gfortran.dg/coarray/event_3.f08: New test.
++
++2017-01-28  John David Anglin  <danglin@gcc.gnu.org>
++
++	PR testsuite/70583
++	* g++.old-deja/g++.abi/vtable2.C: Adjust CMP_VPTR define on hppa.
++
++2017-01-26  Eric Botcazou  <ebotcazou@adacore.com>
++
++	2017-01-09  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* g++.dg/opt/call2.C: New test.
++	* g++.dg/opt/call3.C: Likewise.
++	* gnat.dg/array26.adb: New test.
++	* gnat.dg/array26_pkg.ad[sb]: New helper.
++	* gnat.dg/array27.adb: New test.
++	* gnat.dg/array27_pkg.ad[sb]: New helper.
++	* gnat.dg/array28.adb: New test.
++	* gnat.dg/array28_pkg.ad[sb]: New helper.
++
++2017-01-26  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2016-01-10  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/79034
++	* g++.dg/torture/pr79034.C: New testcase.
++
++	2016-12-13  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/78742
++	* gcc.dg/torture/pr78742.c: New testcase.
++
++2017-01-24  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc.target/arm/vfp-longcall-apcs.c: New test.
++
++2017-01-23  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-01-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	* gcc.dg/lto/pr69188_0.c: Require profiling support for testcase.
++
++2017-01-23  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-20  Martin Liska  <mliska@suse.cz>
++
++	PR lto/69188
++	* gcc.dg/lto/pr69188_0.c: New test.
++	* gcc.dg/lto/pr69188_1.c: New test.
++
++2017-01-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	* gcc.target/powerpc/swaps-p8-27.c: New.
++
++2017-01-20  Wilco Dijkstra  <wdijkstr@arm.com>
++
++	Backport from mainline
++	PR target/77455
++	* gcc.target/aarch64/eh_return.c: New test.
++
++2017-01-20  Marek Polacek  <polacek@redhat.com>
++
++	Backported from mainline
++	2017-01-04  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/77545
++	PR c++/77284
++	* g++.dg/cpp0x/range-for32.C: New test.
++	* g++.dg/cpp0x/range-for33.C: New test.
++
++2017-01-20  Richard Earnshaw  <rearnsha@arm.com>
++
++	Backported from mainline
++	2017-01-19  Richard Earnshaw  <rearnsha@arm.com>
++
++	PR rtl-optimization/79121
++	* gcc.c-torture/execute/pr79121.c: New test.
++
++2017-01-20  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-13  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/79043
++	* gcc.c-torture/execute/pr79043.c: New test.
++
++2017-01-20  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-01-17  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/71207
++	* g++.dg/ipa/pr71207.C: New test.
++
++2017-01-17  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-01-11  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/78341
++	* g++.dg/cpp0x/pr78341.C: New test.
++
++	PR middle-end/50199
++	* gcc.dg/lto/pr50199_0.c: New test.
++
++	2017-01-04  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/78949
++	* c-c++-common/Wunused-var-16.c: New test.
++
++	PR c++/78693
++	* g++.dg/cpp0x/pr78693.C: New test.
++
++	PR c++/71182
++	* g++.dg/cpp0x/pr71182.C: New test.
++
++	2016-12-21  Jakub Jelinek  <jakub@redhat.com>
++
++	PR fortran/78866
++	* gfortran.dg/gomp/map-1.f90: Add expected error.
++	* gfortran.dg/gomp/pr78866-1.f90: New test.
++	* gfortran.dg/gomp/pr78866-2.f90: New test.
++
++2017-01-17  Thomas Preud'homme  <thomas.preudhomme@arm.com>
++
++	Backport from mainline
++	2016-12-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>
++
++	PR rtl-optimization/78617
++	* gcc.c-torture/execute/pr78617.c: New test.
++
++2017-01-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/79044
++	* gcc.target/powerpc/swaps-p8-26.c: New.
++
++2017-01-11  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/77812
++	* g++.dg/pr77812.C: New.
++
++2017-01-10  Thomas Schwinge  <thomas@codesourcery.com>
++
++	Backport from trunk r241334:
++	2016-10-19  Thomas Schwinge  <thomas@codesourcery.com>
++
++	PR tree-optimization/78024
++	* gcc.dg/goacc/loop-processing-1.c: New file.
++
++2017-01-09  Andre Vieira <andre.simoesdiasvieira@arm.com>
++
++	Backport from mainline
++	2016-12-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>
++
++	* gcc.target/arm/pr78255-2.c: Fix to work for targets
++	that do not optimize for tailcall.
++
++2017-01-09  Andre Vieira <andre.simoesdiasvieira@arm.com>
++
++	Backport from mainline
++	2016-12-09  Andre Vieira <andre.simoesdiasvieira@arm.com>
++
++	PR rtl-optimization/78255
++	* gcc.target/aarch64/pr78255.c: New.
++	* gcc.target/arm/pr78255-1.c: New.
++	* gcc.target/arm/pr78255-2.c: New.
++
++2017-01-06  Wilco Dijkstra  <wdijkstr@arm.com>
++
++	Backport from mainline
++	2016-10-25  Wilco Dijkstra  <wdijkstr@arm.com>
++
++	PR target/78041
++	* gcc.target/arm/pr78041.c: New test.
++
++2017-01-05  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2016-12-22  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	* gcc.target/s390/litpool-str-1.c: New test.
++
++2017-01-04  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2016-05-11  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/71055
++	* gcc.dg/torture/pr71055.c: New testcase.
++
++2017-01-03  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-21  Martin Liska  <mliska@suse.cz>
++
++	PR driver/78863
++	* gcc.dg/spellcheck-options-13.c: New test.
++
++2017-01-03  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-22  Martin Liska  <mliska@suse.cz>
++
++	PR tree-optimization/78886
++	* gcc.dg/tree-ssa/pr78886.c: New test.
++
++2017-01-03  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-13  Martin Liska  <mliska@suse.cz>
++
++	PR tree-optimization/78428
++	* gcc.dg/tree-ssa/pr78428.c: New test.
++
++2016-12-22  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/78239
++	* gfortran.dg/fimplicit_none_1.f90:  New test.
++	* gfortran.dg/fimplicit_none_2.f90:  New test.
++
++2016-12-21  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/77767
++	* gcc.c-torture/execute/pr77767.c: New test.
++
++	Backported from mainline
++	2016-12-13  Jakub Jelinek  <jakub@redhat.com>
++
++	PR ipa/77905
++	* g++.dg/ipa/pr77905.C: New test.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+@@ -46,8 +586,8 @@
+ 	Backport from mainline
+ 	2016-11-07  Bernd Schmidt  <bschmidt@redhat.com>
+ 
+-        PR rtl-optimization/77309
+-        * gcc.dg/torture/pr77309.c: New test.
++	PR rtl-optimization/77309
++	* gcc.dg/torture/pr77309.c: New test.
+ 
+ 2016-12-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
+ 
+@@ -456,7 +996,7 @@
+ 	* g++.dg/torture/pr77822.C: New test.
+ 
+ 2016-11-20  Harald Anlauf  <anlauf@gmx.de>
+- 
++
+ 	PR fortran/69741
+ 	* gfortran.dg/forall_18.f90: New testcase.
+ 
+Index: gcc/testsuite/g++.dg/opt/call3.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/call3.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/call3.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,33 @@
++// { dg-do run }
++// { dg-options "-O" }
++
++struct Foo
++{
++  Foo() : a(1), c('a') {}
++  short int a;
++  char c;
++};
++
++static Foo copy_foo(Foo) __attribute__((noinline, noclone));
++
++static Foo copy_foo(Foo A)
++{
++  return A;
++}
++
++struct Bar : Foo
++{
++  Bar(Foo t) : Foo(copy_foo(t)) {}
++};
++
++Foo F;
++
++int main (void)
++{
++  Bar B (F);
++
++  if (B.a != 1 || B.c != 'a')
++    __builtin_abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/g++.dg/opt/declone3.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/declone3.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/declone3.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++// PR c++/79176
++// { dg-do compile { target c++11 } }
++// { dg-options "-flto -Os" }
++
++struct A {};
++struct Object {
++  virtual bool m_fn1();
++  virtual ~Object();
++};
++struct Item : Object, virtual A {
++  ~Item() {
++    [] {};
++  }
++  bool m_fn1();
++};
++bool Item::m_fn1() {}
+Index: gcc/testsuite/g++.dg/opt/pr79267.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/pr79267.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/pr79267.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,69 @@
++// PR tree-optimization/79267
++// { dg-do compile }
++// { dg-options "-O3" }
++
++struct A { A (int); };
++struct B
++{
++  virtual void av () = 0;
++  void aw ();
++  void h () { av (); aw (); }
++};
++template <class T> struct G : B
++{
++  T ba;
++  G (int, T) : ba (0) {}
++  void av () { ba (0); }
++};
++struct I
++{
++  B *bc;
++  template <class j, class T> I (j, T) try { G<T> (0, 0); } catch (...) {}
++  ~I () { bc->h (); }
++};
++template <class M> struct C { typedef M *i; };
++template <class M> struct J
++{
++  J ();
++  template <class O, class T> J (O, T p2) : be (0, p2) {}
++  typename C<M>::i operator-> ();
++  I be;
++};
++struct H : A { H () : A (0) {} };
++struct D { J<int> d; void q (); };
++template <typename = int> class bs;
++int z;
++
++void
++foo (int p1, int *, int)
++{
++  if (p1 == 0)
++    throw H ();
++}
++
++D bar ();
++template <typename T> struct L
++{
++  struct K { K (int); void operator() (int *) { bar ().q (); } };
++  static J<T> bp () { bq (0); }
++  template <typename br> static void bq (br) { J<T> (0, K (0)); }
++};
++struct F
++{
++  virtual J<int> x (int) { foo (0, 0, 0); J<bs<> > (L<bs<> >::bp ()); }
++};
++
++void
++baz ()
++{
++  if (z)
++    {
++      J<F> d, e;
++      d->x (0);
++      e->x (0);
++    }
++  J<F> v, i, j;
++  v->x (0);
++  i->x (0);
++  j->x (0);
++}
+Index: gcc/testsuite/g++.dg/opt/call2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/call2.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/call2.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,34 @@
++// { dg-do run }
++// { dg-options "-O" }
++
++struct Foo
++{
++  Foo() : a(1), b(1), c('a') {}
++  int a;
++  int b;
++  char c;
++};
++
++static Foo copy_foo(Foo) __attribute__((noinline, noclone));
++
++static Foo copy_foo(Foo A)
++{
++  return A;
++}
++
++struct Bar : Foo
++{
++  Bar(Foo t) : Foo(copy_foo(t)) {}
++};
++
++Foo F;
++
++int main (void)
++{
++  Bar B (F);
++
++  if (B.a != 1 || B.b != 1 || B.c != 'a')
++    __builtin_abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/g++.dg/pr77812.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/pr77812.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/pr77812.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++// PR77812
++// struct-stat hack failure when first overload is a template
++
++enum f {};
++
++template <typename>
++void f ()
++{
++}
++enum f F;
++
++struct g {};
++
++template <typename>
++void g ()
++{
++}
++struct g G;
+Index: gcc/testsuite/g++.dg/cpp0x/pr78693.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/pr78693.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/pr78693.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,31 @@
++// PR c++/78693
++// { dg-do compile { target c++11 } }
++
++template <class T>
++void
++foo (T t)
++{
++  auto i = t, j = 1;		// { dg-bogus "inconsistent deduction" }
++}
++
++template <class T>
++void
++bar (T t)
++{
++  auto i = 1, j = t, k = 2;	// { dg-bogus "inconsistent deduction" }
++}
++
++template <class T, class U>
++void
++foo (T t, U u)
++{
++  auto i = t, j = u;		// { dg-bogus "inconsistent deduction" }
++}
++
++void
++foo ()
++{
++  foo (0);
++  bar (0);
++  foo (1, 2);
++}
+Index: gcc/testsuite/g++.dg/cpp0x/pr78341.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/pr78341.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/pr78341.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,4 @@
++// PR c++/78341
++// { dg-do compile { target c++11 } }
++
++alignas (alignas double // { dg-error "" }
+Index: gcc/testsuite/g++.dg/cpp0x/pr71182.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/pr71182.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/pr71182.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++// PR c++/71182
++// { dg-do compile { target c++11 } }
++
++class A {
++  template <typename> void As();
++};
++template <typename T> class B : A {
++  void f() {
++    A *g ;
++    g ? g->As<T>() : nullptr;
++  }
++};
+Index: gcc/testsuite/g++.dg/cpp0x/nsdmi13.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/nsdmi13.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/nsdmi13.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++// PR c++/79796
++// { dg-do compile { target c++11 } }
++
++struct A
++{
++  A* p = this;
++};
++
++void foo()
++{
++  A a;
++  a = A({});
++}
+Index: gcc/testsuite/g++.dg/cpp0x/range-for32.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/range-for32.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/range-for32.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++// PR c++/77545
++// { dg-do compile { target c++11 } }
++// { dg-options "-Wno-pedantic" }
++
++template < typename T > struct A
++{
++  A ();
++  ~A ();
++  T t;
++};
++
++void f (A < int > a)
++{
++  for (auto x : (A<int>[]) { a })
++    ;
++}
+Index: gcc/testsuite/g++.dg/cpp0x/pr79296.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/pr79296.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/pr79296.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++// { dg-require-effective-target lto }
++// { dg-additional-options "-flto" }
++// { dg-do compile { target c++11 } }
++
++// PR 79296 ICE mangling local class of localized instantiation
++
++struct X {
++  template <typename T> X (T const *) {
++    struct Z {};
++  }
++};
++
++void Baz ()
++{
++  struct Y { } y;
++
++  0, X (&y);
++}
+Index: gcc/testsuite/g++.dg/cpp0x/range-for33.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/range-for33.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/range-for33.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++// PR c++/77284
++// { dg-do compile { target c++11 } }
++
++#include <initializer_list>
++
++struct A
++{
++  ~A () {}
++};
++
++void foo (A & v)
++{
++  for (A a : { v }) {};
++}
+Index: gcc/testsuite/g++.dg/torture/pr79034.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr79034.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr79034.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,52 @@
++/* { dg-do compile } */
++
++extern "C" {
++    float sqrtf(float);
++}
++
++class T {
++public:
++    float floats[1];
++
++    inline float length() const {
++	return sqrtf(floats[0]);
++    }
++};
++
++void destruct(void *);
++
++class Container {
++
++    T Ts[1];
++
++public:
++    ~Container() {
++	destruct((void *)Ts);
++    }
++
++    T& operator[](int n) {
++	return Ts[0];
++    }
++};
++
++void fill(Container&);
++
++void doit()
++{
++  Container data;
++  float max = 10;
++
++  int i, j, k;
++
++  for (i = 0; i < 10; i++) {
++      for (j = 1; j < 10; j++) {
++	  if (max < 5)
++	    break;
++	  fill( data);
++	  max = data[0].length();
++	  for (k = 1; k < j; k++) {
++	      max = 5;
++	  }
++      }
++  }
++}
+Index: gcc/testsuite/g++.dg/ipa/pr77905.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ipa/pr77905.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/ipa/pr77905.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++// PR ipa/77905
++// { dg-do compile }
++// { dg-options "-O2" }
++
++struct A {
++  A(int);
++};
++struct B : A {
++  B();
++} A;
++struct C : virtual A {
++  C(int);
++};
++A::A(int x) {
++  if (x)
++    A(0);
++}
++
++B::B() : A(1) {}
++
++C::C(int) : A(1) {}
+Index: gcc/testsuite/g++.dg/ipa/pr71207.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ipa/pr71207.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/ipa/pr71207.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,42 @@
++/* PR ipa/71207 */
++/* { dg-do run } */
++
++class Class1
++{
++public:
++  Class1() {};
++  virtual ~Class1() {};
++
++protected:
++  unsigned Field1;
++};
++
++class Class2 : public virtual Class1
++{
++};
++
++class Class3 : public virtual Class1
++{
++public:
++  virtual void Method1() = 0;
++
++  void Method2()
++  {
++    Method1();
++  }
++};
++
++class Class4 : public Class2, public virtual Class3
++{
++public:
++  Class4() {};
++  virtual void Method1() {};
++};
++
++int main()
++{
++  Class4 var1;
++  var1.Method2();
++
++  return 0;
++}
+Index: gcc/testsuite/g++.dg/cpp1y/pr61636-1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/pr61636-1.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/pr61636-1.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,36 @@
++// PR c++/61636
++// PR c++/79264
++// { dg-do compile { target c++14 } }
++
++// ICE because we figure this capture too late.
++
++struct Base
++{
++  void Bar (int);
++};
++
++struct A : Base {
++  void b ();
++  void Foo (int);
++  using Base::Bar;
++  template <typename T> void Baz (T);
++};
++
++void A::b() {
++
++  auto lam = [&](auto asdf) { Foo (asdf); };
++
++  lam (0);
++
++  auto lam1 = [&](auto asdf) { Bar (asdf); };
++
++  lam1 (0);
++
++  auto lam2 = [&](auto asdf) { Baz (asdf); };
++
++  lam2 (0);
++
++  auto lam3 = [&](auto asdf) { Baz<int> (asdf); };
++
++  lam3 (0);
++}
+Index: gcc/testsuite/g++.dg/cpp1y/constexpr-union1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/constexpr-union1.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/constexpr-union1.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++// PR c++/78897
++// { dg-do compile { target c++14 } }
++
++struct Optional {
++  constexpr Optional() : _dummy{} { _value = 1; }
++  union {
++    int _dummy;
++    int _value;
++  };
++};
++Optional opt{};
+Index: gcc/testsuite/g++.dg/cpp1y/pr61636-2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/pr61636-2.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/pr61636-2.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,72 @@
++// PR c++/61636
++// { dg-do run { target c++14 } }
++
++// Check we don't capture this (too) unnecessarily
++
++struct A {
++  int b ();
++  void f (int) {}
++  static void f (double) {}
++
++  static void g (int) {}
++  static void g (double) {}
++};
++
++struct O {
++  void x (int) {}
++  static void x (double) {}
++};
++
++namespace N {
++  void y (double) {}
++}
++
++int Check (bool expect, unsigned size)
++{
++  return (expect ? sizeof (void *) : 1) != size;
++}
++
++int A::b() {
++  int r = 0;
++
++  // one of the functions is non-static
++  auto l0 = [&](auto z) { f (z); };
++  r += Check (true, sizeof l0);
++  l0(0.0); // doesn't need this capture for A::f(double), but too late
++  l0 (0); // Needs this capture for A::f(int)
++
++  // no fn is non-static.
++  auto l00 = [&](auto z) { g (z); };
++  r += Check (false, sizeof l00);
++  l00(0.0); 
++  l00 (0);
++
++  // sizeof isn't an evaluation context, so no this capture
++  auto l1 = [&](auto z) { sizeof (f (z), 1); };
++  r += Check (false, sizeof l1);
++  l1(0.0); l1 (0); 
++
++  auto l2 = [&](auto) { f (2.4); };
++  auto l3 = [&](auto) { f (0); };
++  l2(0); l3(0); l2(0.0); l3 (0.0);
++  r += Check (false, sizeof l2);
++  r += Check (true, sizeof l3);
++
++  auto l4 = [&](auto) { O::x (2.4); };
++  auto l5 = [&](auto) { N::y (2.4); };
++  auto l6 = [&](auto) { };
++  l4(0); l5(0); l6(0);
++  l4(0.0); l5(0.0); l6(0.0);
++  r += Check (false, sizeof l4);
++  r += Check (false, sizeof l5);
++  r += Check (false, sizeof l6);
++
++  return r;
++}
++
++int main ()
++{
++  A a;
++
++  return a.b () ? 1 : 0;
++}
+Index: gcc/testsuite/g++.dg/cpp1y/pr61636-3.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/pr61636-3.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/pr61636-3.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,25 @@
++// PR c++/61636
++// { dg-do compile { target c++14 } }
++// permissiveness doesn't make this permitted
++// { dg-additional-options "-fpermissive" }
++
++// ICE because we attempt to use dependent Foo during error recovery
++// and die with an unexpected this capture need.
++
++template <typename T> struct Base
++{
++  void Foo (int);
++};
++
++template <typename T> struct A : Base<T> {
++  void b ();
++};
++
++template <typename T> void A<T>::b() {
++
++  auto lam = [&](auto asdf) { Foo (asdf); }; // { dg-error "not declared" }
++
++  lam (T(0));
++}
++
++template void A<int>::b ();
+Index: gcc/testsuite/g++.dg/ext/flexary21.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ext/flexary21.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/ext/flexary21.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++// PR c++/72775
++// { dg-do compile { target c++11 } }
++// { dg-options -Wno-pedantic }
++
++struct S {
++  int i;
++  char a[];
++  S () : a("bob") {} // { dg-error "member initializer for flexible array member" }
++};
++
++struct T {
++  int i;
++  char a[] = "bob";
++  T () : a("bob") {} // { dg-error "member initializer for flexible array member" }
++};
+Index: gcc/testsuite/g++.dg/ext/flexary20.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ext/flexary20.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/ext/flexary20.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,49 @@
++// PR c++/72775
++// { dg-do compile { target c++11 } }
++// { dg-options -Wno-pedantic }
++
++struct S {
++  int i;
++  char a[] = "foo";
++  S () {} // { dg-error "member initializer for flexible array member" }
++};
++
++struct T { // { dg-error "member initializer for flexible array member" }
++  int i;
++  char a[] = "foo";
++};
++
++struct U {
++  int i;
++  char a[] = "foo";
++  U ();
++};
++
++U::U() {} // { dg-error "member initializer for flexible array member" }
++
++int
++main ()
++{
++  struct T t;
++}
++
++struct V {
++  int i;
++  struct W { // { dg-error "member initializer for flexible array member" }
++    int j;
++    char a[] = "foo";
++  } w;
++  V () {}
++};
++
++template <class T>
++struct X { // { dg-error "member initializer for flexible array member" }
++  int i;
++  T a[] = "foo";
++};
++
++void
++fn ()
++{
++  struct X<char> x;
++}
+Index: gcc/testsuite/g++.dg/ext/flexary12.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ext/flexary12.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/ext/flexary12.C	(.../branches/gcc-6-branch)
+@@ -44,7 +44,7 @@
+   D ();
+ };
+ 
+-D::D ():
++D::D ():    // { dg-error "member initializer for flexible array member" }
+   a ("c")   // { dg-error "incompatible types in assignment of .const char \\\[2\\\]. to .int \\\[\\\]." }
+ { }
+ 
+Index: gcc/testsuite/g++.dg/vect/pr36648.cc
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/vect/pr36648.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/vect/pr36648.cc	(.../branches/gcc-6-branch)
+@@ -17,7 +17,12 @@
+ 
+ int main() { }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { !  vect_no_align } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_no_align } } } } */
++/* On older powerpc hardware (POWER7 and earlier), the default flag
++   -mno-allow-movmisalign prevents vectorization.  On POWER8 and later,
++   when vect_hw_misalign is true, vectorization occurs.  For other
++   targets, ! vect_no_align is a sufficient test.  */
+ 
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { { !  vect_no_align } && { ! powerpc*-*-* } } || { powerpc*-*-* && vect_hw_misalign } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { { { ! vect_no_align } && { ! powerpc*-*-* } } || { powerpc*-*-* && vect_hw_misalign } } } } } */
+ 
++
+Index: gcc/testsuite/g++.dg/lookup/pr79377.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/lookup/pr79377.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/lookup/pr79377.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,36 @@
++// PR c++/79377
++// { dg-do run }
++// { dg-options "-fpermissive" }
++
++struct A
++{
++  A () : a (0) {}
++  A& operator++ () { ++a; ++c; return *this; }
++  int a;
++  static int c;
++};
++
++int A::c = 0;
++
++template <typename>
++void
++foo (A& a)
++{
++  a++;		// { dg-warning "trying prefix operator instead" }
++  if (A::c != 3 || a.a != 3) __builtin_abort ();
++  ++a;
++  if (A::c != 4 || a.a != 4) __builtin_abort ();
++}
++
++int
++main ()
++{
++  A a;
++  if (A::c != 0 || a.a != 0) __builtin_abort ();
++  ++a;
++  if (A::c != 1 || a.a != 1) __builtin_abort ();
++  a++;		// { dg-warning "trying prefix operator instead" }
++  if (A::c != 2 || a.a != 2) __builtin_abort ();
++  foo<int> (a);
++  if (A::c != 4 || a.a != 4) __builtin_abort ();
++}
+Index: gcc/testsuite/g++.dg/expr/ptrmem9.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/expr/ptrmem9.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/expr/ptrmem9.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++// PR c++/79687
++// { dg-do run }
++
++struct A
++{
++  char c;
++};
++
++int main()
++{
++  static char A::* p1 = &A::c;
++  char A::* const q1 = p1;
++
++  char A::* p2 = &A::c;
++  static char A::* const q2 = p2;
++
++  A a;
++  return (&(a.*q1) - &a.c) || (&(a.*q2) - &a.c);
++}
+Index: gcc/testsuite/g++.dg/expr/ptrmem8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/expr/ptrmem8.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/expr/ptrmem8.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++// PR c++/79687
++// { dg-do run }
++
++struct A
++{
++  char c;
++};
++
++int main()
++{
++  char A::* p = &A::c;
++  static char A::* const q = p;
++  A a;
++  return &(a.*q) - &a.c;
++}
+Index: gcc/testsuite/g++.dg/gomp/pr79429.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/gomp/pr79429.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/gomp/pr79429.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++// PR c++/79429
++
++#pragma omp ordered // { dg-error "expected declaration specifiers" }
+Index: gcc/testsuite/g++.dg/warn/Wnonnull3.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/warn/Wnonnull3.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/warn/Wnonnull3.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++// PR c++/79962
++// { dg-options "-Wnonnull" }
++
++template <class T>
++__attribute__ ((__nonnull__ (T::i))) void f (typename T::U) { }
++
++struct S1 { enum { i = 1 }; typedef void* U; };
++struct S2 { static const int i = 1; typedef void* U; };
++
++void
++g ()
++{
++  f<S1>(0); // { dg-warning "null argument where non-null required" }
++  f<S2>(0); // { dg-warning "null argument where non-null required" }
++}
+Index: gcc/testsuite/g++.dg/warn/Wpadded-1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/warn/Wpadded-1.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/warn/Wpadded-1.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++// PR c++/79900 - ICE in strip_typedefs
++// { dg-do compile }
++// { dg-options "-Wpadded" }
++
++template <class> struct A;
++template <typename> struct B { // { dg-warning "padding struct size to alignment boundary" }
++  long long _M_off;
++  char _M_state;
++};
++template <> struct A<char> { typedef B<int> pos_type; };
++enum _Ios_Openmode {};
++struct C {
++  typedef _Ios_Openmode openmode;
++};
++template <typename, typename _Traits> struct D {
++  typedef typename _Traits::pos_type pos_type;
++  pos_type m_fn1(pos_type, C::openmode);
++};
++template class D<char, A<char> >;
++template <typename _CharT, typename _Traits>
++typename D<_CharT, _Traits>::pos_type D<_CharT, _Traits>::m_fn1(pos_type x,
++                                                                C::openmode) { return x; }
+Index: gcc/testsuite/g++.dg/template/bitfield3.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/template/bitfield3.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/template/bitfield3.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++// PR c++/78908
++
++struct A { int a : 1; };
++struct F { int foo (A const &); };
++template <typename> struct O : F { int foo (A const &); };
++struct S {} b;
++template <typename L, typename T> int operator<< (L, T) { return (T) 123; }
++template <typename T> int O<T>::foo (A const &x) { return b << x.a; }
++
++int
++main ()
++{
++  A a = { 0 };
++  O<int> o;
++  if (o.foo (a) != 123)
++    __builtin_abort ();
++  signed char d = 2;
++  if ((b << d) != 123)
++    __builtin_abort ();
++}
+Index: gcc/testsuite/c-c++-common/ubsan/bounds-14.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/ubsan/bounds-14.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/ubsan/bounds-14.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++/* PR sanitizer/79558 */
++/* { dg-do compile } */
++/* { dg-options "-fsanitize=bounds" } */
++
++void
++fn1 (int n)
++{
++  int i, j;
++  int x[2][0];
++  for (i = 0; i < n; i++)
++    for (j = 0; j < n; j++)
++      x[i][j] = 5;
++}
+Index: gcc/testsuite/c-c++-common/cilk-plus/CK/pr79428-4.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/cilk-plus/CK/pr79428-4.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/cilk-plus/CK/pr79428-4.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++/* PR c/79428 */
++/* { dg-options "-fcilkplus" } */
++#pragma cilk grainsize /* { dg-error "must be inside a function" } */
+Index: gcc/testsuite/c-c++-common/cilk-plus/CK/pr79428-7.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/cilk-plus/CK/pr79428-7.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/cilk-plus/CK/pr79428-7.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++/* PR c/79428 */
++/* { dg-options "-fcilkplus" } */
++#pragma simd /* { dg-error "must be inside a function" } */
+Index: gcc/testsuite/c-c++-common/Wunused-var-16.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/Wunused-var-16.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/Wunused-var-16.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++/* PR c++/78949 */
++/* { dg-do compile } */
++/* { dg-options "-Wunused" } */
++
++typedef unsigned char V __attribute__((vector_size(16)));
++V v;
++
++void
++foo ()
++{
++  V y = {};
++  V x = {};	// { dg-bogus "set but not used" }
++  y &= ~x;
++  v = y;
++}
+Index: gcc/testsuite/c-c++-common/nonnull-3.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/nonnull-3.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/nonnull-3.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* PR c++/79984 */
++/* { dg-do compile } */
++/* { dg-options "-Wnonnull-compare" } */
++
++enum { r = 1 };
++
++__attribute__ ((nonnull (r))) int
++f (int *p)
++{
++  return p == 0; /* { dg-warning "nonnull argument 'p' compared to NULL" } */
++}
+Index: gcc/testsuite/c-c++-common/pr79428-3.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/pr79428-3.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/pr79428-3.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++/* PR c/79428 */
++int i;
++#pragma GCC pch_preprocess /* { dg-error "'#pragma GCC pch_preprocess' must be first" } */
+Index: gcc/testsuite/c-c++-common/gomp/pr79428-5.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/gomp/pr79428-5.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/gomp/pr79428-5.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++/* PR c/79428 */
++/* { dg-options "-fopenmp" } */
++#pragma omp ordered /* { dg-error "expected declaration specifiers before end of line" } */
+Index: gcc/testsuite/c-c++-common/gomp/pr79431.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/gomp/pr79431.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/gomp/pr79431.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* PR c/79431 */
++
++void
++foo (void)
++{
++  int a;
++  #pragma omp declare target (a)
++}
+Index: gcc/testsuite/c-c++-common/gomp/pr79428-2.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/gomp/pr79428-2.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/gomp/pr79428-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++/* PR c/79428 */
++/* { dg-options "-fopenmp" } */
++void
++foo ()
++{
++#pragma omp sections
++#pragma omp section /* { dg-error "'#pragma omp section' may only be used in '#pragma omp sections' construct|not allowed|expected" } */
+Index: gcc/testsuite/c-c++-common/gomp/pr79429.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/gomp/pr79429.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/gomp/pr79429.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++/* PR c++/79429 */
++
++#pragma omp target /* { dg-error "expected declaration specifiers" } */
+Index: gcc/testsuite/c-c++-common/gomp/pr79428-6.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/gomp/pr79428-6.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/c-c++-common/gomp/pr79428-6.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++/* PR c/79428 */
++/* { dg-options "-fopenmp" } */
++#pragma omp target /* { dg-error "expected declaration specifiers before end of line" } */
+Index: gcc/cp/typeck.c
+===================================================================
+--- a/src/gcc/cp/typeck.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/typeck.c	(.../branches/gcc-6-branch)
+@@ -5848,6 +5848,8 @@
+ 	errstring = _("wrong type argument to bit-complement");
+       else if (!noconvert && CP_INTEGRAL_TYPE_P (TREE_TYPE (arg)))
+ 	arg = cp_perform_integral_promotions (arg, complain);
++      else if (!noconvert && VECTOR_TYPE_P (TREE_TYPE (arg)))
++	arg = mark_rvalue_use (arg);
+       break;
+ 
+     case ABS_EXPR:
+Index: gcc/cp/init.c
+===================================================================
+--- a/src/gcc/cp/init.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/init.c	(.../branches/gcc-6-branch)
+@@ -796,6 +796,14 @@
+ 	   in that case.  */
+ 	init = build_x_compound_expr_from_list (init, ELK_MEM_INIT,
+ 						tf_warning_or_error);
++      if (TREE_CODE (type) == ARRAY_TYPE
++	  && TYPE_DOMAIN (type) == NULL_TREE
++	  && init != NULL_TREE)
++	{
++	  error_at (DECL_SOURCE_LOCATION (current_function_decl),
++		    "member initializer for flexible array member");
++	  inform (DECL_SOURCE_LOCATION (member), "%q#D initialized", member);
++	}
+ 
+       if (init)
+ 	finish_expr_stmt (cp_build_modify_expr (decl, INIT_EXPR, init,
+@@ -2110,6 +2118,13 @@
+       if (TREE_CODE (init) == CONSTRUCTOR
+ 	  && !DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (decl))
+ 	break;
++      /* If the variable has a dynamic initializer, don't use its
++	 DECL_INITIAL which doesn't reflect the real value.  */
++      if (VAR_P (decl)
++	  && TREE_STATIC (decl)
++	  && !DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (decl)
++	  && DECL_NONTRIVIALLY_INITIALIZED_P (decl))
++	break;
+       decl = unshare_expr (init);
+     }
+   return decl;
+Index: gcc/cp/constexpr.c
+===================================================================
+--- a/src/gcc/cp/constexpr.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/constexpr.c	(.../branches/gcc-6-branch)
+@@ -3239,6 +3239,11 @@
+ 	  tree fields = TYPE_FIELDS (DECL_CONTEXT (index));
+ 	  unsigned HOST_WIDE_INT idx;
+ 
++	  if (code == UNION_TYPE && CONSTRUCTOR_NELTS (*valp)
++	      && CONSTRUCTOR_ELT (*valp, 0)->index != index)
++	    /* Changing active member.  */
++	    vec_safe_truncate (CONSTRUCTOR_ELTS (*valp), 0);
++
+ 	  for (idx = 0;
+ 	       vec_safe_iterate (CONSTRUCTOR_ELTS (*valp), idx, &cep);
+ 	       idx++, fields = DECL_CHAIN (fields))
+@@ -5295,6 +5300,7 @@
+       /* We can see these in statement-expressions.  */
+       return true;
+ 
++    case CLEANUP_STMT:
+     case EMPTY_CLASS_EXPR:
+       return false;
+ 
+Index: gcc/cp/tree.c
+===================================================================
+--- a/src/gcc/cp/tree.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/tree.c	(.../branches/gcc-6-branch)
+@@ -1463,29 +1463,40 @@
+ 	result = TYPE_MAIN_VARIANT (t);
+     }
+   gcc_assert (!typedef_variant_p (result));
+-  if (TYPE_USER_ALIGN (t) != TYPE_USER_ALIGN (result)
+-      || TYPE_ALIGN (t) != TYPE_ALIGN (result))
++
++  if (COMPLETE_TYPE_P (result) && !COMPLETE_TYPE_P (t))
++  /* If RESULT is complete and T isn't, it's likely the case that T
++     is a variant of RESULT which hasn't been updated yet.  Skip the
++     attribute handling.  */;
++  else
+     {
+-      gcc_assert (TYPE_USER_ALIGN (t));
+-      if (remove_attributes)
+-	*remove_attributes = true;
+-      else
++      if (TYPE_USER_ALIGN (t) != TYPE_USER_ALIGN (result)
++	  || TYPE_ALIGN (t) != TYPE_ALIGN (result))
+ 	{
+-	  if (TYPE_ALIGN (t) == TYPE_ALIGN (result))
+-	    result = build_variant_type_copy (result);
++	  gcc_assert (TYPE_USER_ALIGN (t));
++	  if (remove_attributes)
++	    *remove_attributes = true;
+ 	  else
+-	    result = build_aligned_type (result, TYPE_ALIGN (t));
+-	  TYPE_USER_ALIGN (result) = true;
++	    {
++	      if (TYPE_ALIGN (t) == TYPE_ALIGN (result))
++		result = build_variant_type_copy (result);
++	      else
++		result = build_aligned_type (result, TYPE_ALIGN (t));
++	      TYPE_USER_ALIGN (result) = true;
++	    }
+ 	}
++
++      if (TYPE_ATTRIBUTES (t))
++	{
++	  if (remove_attributes)
++	    result = apply_identity_attributes (result, TYPE_ATTRIBUTES (t),
++						remove_attributes);
++	  else
++	    result = cp_build_type_attribute_variant (result,
++						      TYPE_ATTRIBUTES (t));
++	}
+     }
+-  if (TYPE_ATTRIBUTES (t))
+-    {
+-      if (remove_attributes)
+-	result = apply_identity_attributes (result, TYPE_ATTRIBUTES (t),
+-					    remove_attributes);
+-      else
+-	result = cp_build_type_attribute_variant (result, TYPE_ATTRIBUTES (t));
+-    }
++
+   return cp_build_qualified_type (result, cp_type_quals (t));
+ }
+ 
+@@ -2775,7 +2786,7 @@
+ 
+   t = make_node (code);
+   length = TREE_CODE_LENGTH (code);
+-  TREE_TYPE (t) = TREE_TYPE (non_dep);
++  TREE_TYPE (t) = unlowered_expr_type (non_dep);
+   TREE_SIDE_EFFECTS (t) = TREE_SIDE_EFFECTS (non_dep);
+ 
+   for (i = 0; i < length; i++)
+@@ -2830,8 +2841,10 @@
+   nargs = call_expr_nargs (non_dep);
+ 
+   expected_nargs = cp_tree_code_length (op);
+-  if (op == POSTINCREMENT_EXPR
+-      || op == POSTDECREMENT_EXPR)
++  if ((op == POSTINCREMENT_EXPR
++       || op == POSTDECREMENT_EXPR)
++      /* With -fpermissive non_dep could be operator++().  */
++      && (!flag_permissive || nargs != expected_nargs))
+     expected_nargs += 1;
+   gcc_assert (nargs == expected_nargs);
+ 
+@@ -4146,6 +4159,14 @@
+   if (TREE_PUBLIC (decl))
+     return lk_external;
+ 
++  /* maybe_thunk_body clears TREE_PUBLIC on the maybe-in-charge 'tor variants,
++     check one of the "clones" for the real linkage.  */
++  if ((DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (decl)
++       || DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (decl))
++      && DECL_CHAIN (decl)
++      && DECL_CLONED_FUNCTION (DECL_CHAIN (decl)))
++    return decl_linkage (DECL_CHAIN (decl));
++
+   if (TREE_CODE (decl) == NAMESPACE_DECL)
+     return lk_external;
+ 
+Index: gcc/cp/ChangeLog
+===================================================================
+--- a/src/gcc/cp/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,140 @@
++2017-03-15  Marek Polacek  <polacek@redhat.com>
++
++	Backported from mainline
++	2016-12-14  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/72775
++	* init.c (perform_member_init): Diagnose member initializer for
++	flexible array member. 
++
++2017-03-14  Marek Polacek  <polacek@redhat.com>
++
++	Backported from mainline
++	2017-03-09  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/79900 - ICE in strip_typedefs
++	* tree.c (strip_typedefs): Skip the attribute handling if T is
++	a variant type which hasn't been updated yet.
++
++	PR c++/79687
++	* init.c (constant_value_1): Break if the variable has a dynamic
++	initializer.
++
++	Backported from mainline
++	2017-01-31  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/79264
++	* lambda.c (maybe_generic_this_capture): Deal with template-id-exprs.
++	* semantics.c (finish_member_declaration): Assert class is being
++	defined.
++
++	Backported from mainline
++	2017-01-17  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/61636
++	* cp-tree.h (maybe_generic_this_capture): Declare.
++	* lambda.c (resolvable_dummy_lambda): New, broken out of ...
++	(maybe_resolve_dummy): ... here.  Call it.
++	(maybe_generic_this_capture): New.
++	* parser.c (cp_parser_postfix_expression): Speculatively capture
++	this in generic lambda in unresolved member function call.
++	* pt.c (tsubst_copy_and_build): Force hard error from failed
++	member function lookup in generic lambda.
++
++2017-03-07  Marek Polacek  <polacek@redhat.com>
++
++	Backported from mainline
++	2017-03-06  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/79796 - ICE with NSDMI and this pointer
++	* call.c (build_over_call): Handle NSDMI with a 'this' by calling
++	replace_placeholders.
++
++2017-02-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-02-09  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/79429
++	* parser.c (cp_parser_omp_ordered): Don't check for non-pragma_stmt
++	non-pragma_compound context here.
++	(cp_parser_omp_target): Likewise.
++	(cp_parser_pragma): Don't call push_omp_privatization_clauses and
++	parsing for ordered and target omp pragmas in non-pragma_stmt
++	non-pragma_compound contexts.
++
++	PR c/79431
++	* parser.c (cp_parser_oacc_declare): Formatting fix.
++	(cp_parser_omp_declare_target): Don't invoke symtab_node::get on
++	automatic variables.
++
++	2017-02-06  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/79377
++	* tree.c (build_min_non_dep_op_overload): For POST{INC,DEC}REMENT_EXPR
++	allow one fewer than expected arguments if flag_permissive.
++
++2017-02-13  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/79296 - ICE mangling localized template instantiation
++	* decl2.c (determine_visibility): Use template fn context for
++	local class instantiations.
++
++2017-02-11  Jason Merrill  <jason@redhat.com>
++
++	PR c++/78908 - template ops and bitfields
++	* tree.c (build_min_non_dep): Use unlowered_expr_type.
++
++2017-02-10  Jason Merrill  <jason@redhat.com>
++
++	PR c++/78897 - constexpr union
++	* constexpr.c (cxx_eval_store_expression): A store to a union member
++	erases a previous store to another member.
++
++2017-01-26  Jason Merrill  <jason@redhat.com>
++
++	PR c++/79176 - lambda ICE with -flto -Os
++	* decl2.c (vague_linkage_p): Handle decloned 'tors.
++	* tree.c (decl_linkage): Likewise.
++
++2017-01-20  Marek Polacek  <polacek@redhat.com>
++	
++	Backported from mainline
++	2017-01-04  Marek Polacek  <polacek@redhat.com>
++
++	PR c++/77545
++	PR c++/77284
++	* constexpr.c (potential_constant_expression_1): Handle CLEANUP_STMT.
++
++2017-01-17  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-01-11  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/78341
++	* parser.c (cp_parser_std_attribute_spec): Remove over-eager
++	assertion.  Formatting fix.
++
++	2017-01-04  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/78949
++	* typeck.c (cp_build_unary_op): Call mark_rvalue_use on arg if it has
++	vector type.
++
++	PR c++/78693
++	* parser.c (cp_parser_simple_declaration): Only complain about
++	inconsistent auto deduction if auto_result doesn't use auto.
++
++	PR c++/71182
++	* parser.c (cp_lexer_previous_token): Use vec_safe_address in the
++	assertion, as lexer->buffer may be NULL.
++
++2017-01-11  Nathan Sidwell  <nathan@acm.org>
++
++	PR c++/77812
++	* name-lookup.c (set_namespace_binding_1): An overload of 1 decl
++	is a new overload.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/cp/pt.c
+===================================================================
+--- a/src/gcc/cp/pt.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/pt.c	(.../branches/gcc-6-branch)
+@@ -16613,19 +16613,34 @@
+ 
+ 		if (unq != function)
+ 		  {
+-		    tree fn = unq;
+-		    if (INDIRECT_REF_P (fn))
+-		      fn = TREE_OPERAND (fn, 0);
+-		    if (TREE_CODE (fn) == COMPONENT_REF)
+-		      fn = TREE_OPERAND (fn, 1);
+-		    if (is_overloaded_fn (fn))
+-		      fn = get_first_fn (fn);
+-		    if (permerror (EXPR_LOC_OR_LOC (t, input_location),
+-				   "%qD was not declared in this scope, "
+-				   "and no declarations were found by "
+-				   "argument-dependent lookup at the point "
+-				   "of instantiation", function))
++		    /* In a lambda fn, we have to be careful to not
++		       introduce new this captures.  Legacy code can't
++		       be using lambdas anyway, so it's ok to be
++		       stricter.  */
++		    bool in_lambda = (current_class_type
++				      && LAMBDA_TYPE_P (current_class_type));
++		    char const *msg = "%qD was not declared in this scope, "
++		      "and no declarations were found by "
++		      "argument-dependent lookup at the point "
++		      "of instantiation";
++
++		    bool diag = true;
++		    if (in_lambda)
++		      error_at (EXPR_LOC_OR_LOC (t, input_location),
++				msg, function);
++		    else
++		      diag = permerror (EXPR_LOC_OR_LOC (t, input_location),
++					msg, function);
++		    if (diag)
+ 		      {
++			tree fn = unq;
++			if (INDIRECT_REF_P (fn))
++			  fn = TREE_OPERAND (fn, 0);
++			if (TREE_CODE (fn) == COMPONENT_REF)
++			  fn = TREE_OPERAND (fn, 1);
++			if (is_overloaded_fn (fn))
++			  fn = get_first_fn (fn);
++
+ 			if (!DECL_P (fn))
+ 			  /* Can't say anything more.  */;
+ 			else if (DECL_CLASS_SCOPE_P (fn))
+@@ -16648,7 +16663,13 @@
+ 			  inform (DECL_SOURCE_LOCATION (fn),
+ 				  "%qD declared here, later in the "
+ 				  "translation unit", fn);
++			if (in_lambda)
++			  {
++			    release_tree_vector (call_args);
++			    RETURN (error_mark_node);
++			  }
+ 		      }
++
+ 		    function = unq;
+ 		  }
+ 	      }
+Index: gcc/cp/semantics.c
+===================================================================
+--- a/src/gcc/cp/semantics.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/semantics.c	(.../branches/gcc-6-branch)
+@@ -2965,6 +2965,12 @@
+   /* We should see only one DECL at a time.  */
+   gcc_assert (DECL_CHAIN (decl) == NULL_TREE);
+ 
++  /* Don't add decls after definition.  */
++  gcc_assert (TYPE_BEING_DEFINED (current_class_type)
++	      /* We can add lambda types when late parsing default
++		 arguments.  */
++	      || LAMBDA_TYPE_P (TREE_TYPE (decl)));
++
+   /* Set up access control for DECL.  */
+   TREE_PRIVATE (decl)
+     = (current_access_specifier == access_private_node);
+Index: gcc/cp/decl2.c
+===================================================================
+--- a/src/gcc/cp/decl2.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/decl2.c	(.../branches/gcc-6-branch)
+@@ -1875,6 +1875,14 @@
+ {
+   if (!TREE_PUBLIC (decl))
+     {
++      /* maybe_thunk_body clears TREE_PUBLIC on the maybe-in-charge 'tor
++	 variants, check one of the "clones" for the real linkage.  */
++      if ((DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (decl)
++	   || DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (decl))
++	  && DECL_CHAIN (decl)
++	  && DECL_CLONED_FUNCTION (DECL_CHAIN (decl)))
++	return vague_linkage_p (DECL_CHAIN (decl));
++
+       gcc_checking_assert (!DECL_COMDAT (decl));
+       return false;
+     }
+@@ -2272,11 +2280,6 @@
+ void
+ determine_visibility (tree decl)
+ {
+-  tree class_type = NULL_TREE;
+-  bool use_template;
+-  bool orig_visibility_specified;
+-  enum symbol_visibility orig_visibility;
+-
+   /* Remember that all decls get VISIBILITY_DEFAULT when built.  */
+ 
+   /* Only relevant for names with external linkage.  */
+@@ -2288,25 +2291,28 @@
+      maybe_clone_body.  */
+   gcc_assert (!DECL_CLONED_FUNCTION_P (decl));
+ 
+-  orig_visibility_specified = DECL_VISIBILITY_SPECIFIED (decl);
+-  orig_visibility = DECL_VISIBILITY (decl);
++  bool orig_visibility_specified = DECL_VISIBILITY_SPECIFIED (decl);
++  enum symbol_visibility orig_visibility = DECL_VISIBILITY (decl);
+ 
++  /* The decl may be a template instantiation, which could influence
++     visibilty.  */
++  tree template_decl = NULL_TREE;
+   if (TREE_CODE (decl) == TYPE_DECL)
+     {
+       if (CLASS_TYPE_P (TREE_TYPE (decl)))
+-	use_template = CLASSTYPE_USE_TEMPLATE (TREE_TYPE (decl));
++	{
++	  if (CLASSTYPE_USE_TEMPLATE (TREE_TYPE (decl)))
++	    template_decl = decl;
++	}
+       else if (TYPE_TEMPLATE_INFO (TREE_TYPE (decl)))
+-	use_template = 1;
+-      else
+-	use_template = 0;
++	template_decl = decl;
+     }
+-  else if (DECL_LANG_SPECIFIC (decl))
+-    use_template = DECL_USE_TEMPLATE (decl);
+-  else
+-    use_template = 0;
++  else if (DECL_LANG_SPECIFIC (decl) && DECL_USE_TEMPLATE (decl))
++    template_decl = decl;
+ 
+   /* If DECL is a member of a class, visibility specifiers on the
+      class can influence the visibility of the DECL.  */
++  tree class_type = NULL_TREE;
+   if (DECL_CLASS_SCOPE_P (decl))
+     class_type = DECL_CONTEXT (decl);
+   else
+@@ -2349,8 +2355,11 @@
+ 	    }
+ 
+ 	  /* Local classes in templates have CLASSTYPE_USE_TEMPLATE set,
+-	     but have no TEMPLATE_INFO, so don't try to check it.  */
+-	  use_template = 0;
++	     but have no TEMPLATE_INFO.  Their containing template
++	     function does, and the local class could be constrained
++	     by that.  */
++	  if (template_decl)
++	    template_decl = fn;
+ 	}
+       else if (VAR_P (decl) && DECL_TINFO_P (decl)
+ 	       && flag_visibility_ms_compat)
+@@ -2380,7 +2389,7 @@
+ 	      && !CLASSTYPE_VISIBILITY_SPECIFIED (TREE_TYPE (DECL_NAME (decl))))
+ 	    targetm.cxx.determine_class_data_visibility (decl);
+ 	}
+-      else if (use_template)
++      else if (template_decl)
+ 	/* Template instantiations and specializations get visibility based
+ 	   on their template unless they override it with an attribute.  */;
+       else if (! DECL_VISIBILITY_SPECIFIED (decl))
+@@ -2397,11 +2406,11 @@
+ 	}
+     }
+ 
+-  if (use_template)
++  if (template_decl)
+     {
+       /* If the specialization doesn't specify visibility, use the
+ 	 visibility from the template.  */
+-      tree tinfo = get_template_info (decl);
++      tree tinfo = get_template_info (template_decl);
+       tree args = TI_ARGS (tinfo);
+       tree attribs = (TREE_CODE (decl) == TYPE_DECL
+ 		      ? TYPE_ATTRIBUTES (TREE_TYPE (decl))
+Index: gcc/cp/parser.c
+===================================================================
+--- a/src/gcc/cp/parser.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/parser.c	(.../branches/gcc-6-branch)
+@@ -762,7 +762,7 @@
+   /* Skip past purged tokens.  */
+   while (tp->purged_p)
+     {
+-      gcc_assert (tp != lexer->buffer->address ());
++      gcc_assert (tp != vec_safe_address (lexer->buffer));
+       tp--;
+     }
+ 
+@@ -6867,6 +6867,7 @@
+ 			|| type_dependent_expression_p (fn)
+ 			|| any_type_dependent_arguments_p (args)))
+ 		  {
++		    maybe_generic_this_capture (instance, fn);
+ 		    postfix_expression
+ 		      = build_nt_call_vec (postfix_expression, args);
+ 		    release_tree_vector (args);
+@@ -12406,9 +12407,11 @@
+       if (cp_parser_error_occurred (parser))
+ 	goto done;
+ 
+-      if (auto_result)
++      if (auto_result
++	  && (!processing_template_decl || !type_uses_auto (auto_result)))
+ 	{
+-	  if (last_type && last_type != error_mark_node
++	  if (last_type
++	      && last_type != error_mark_node
+ 	      && !same_type_p (auto_result, last_type))
+ 	    {
+ 	      /* If the list of declarators contains more than one declarator,
+@@ -24140,11 +24143,7 @@
+ 
+       if (!cp_parser_parse_definitely (parser))
+ 	{
+-	  gcc_assert (alignas_expr == error_mark_node
+-		      || alignas_expr == NULL_TREE);
+-
+-	  alignas_expr =
+-	    cp_parser_assignment_expression (parser);
++	  alignas_expr = cp_parser_assignment_expression (parser);
+ 	  if (alignas_expr == error_mark_node)
+ 	    cp_parser_skip_to_end_of_statement (parser);
+ 	  if (alignas_expr == NULL_TREE
+@@ -34060,13 +34059,6 @@
+ {
+   location_t loc = pragma_tok->location;
+ 
+-  if (context != pragma_stmt && context != pragma_compound)
+-    {
+-      cp_parser_error (parser, "expected declaration specifiers");
+-      cp_parser_skip_to_pragma_eol (parser, pragma_tok);
+-      return false;
+-    }
+-
+   if (cp_lexer_next_token_is (parser->lexer, CPP_NAME))
+     {
+       tree id = cp_lexer_peek_token (parser->lexer)->u.value;
+@@ -34959,13 +34951,6 @@
+ {
+   tree *pc = NULL, stmt;
+ 
+-  if (context != pragma_stmt && context != pragma_compound)
+-    {
+-      cp_parser_error (parser, "expected declaration specifiers");
+-      cp_parser_skip_to_pragma_eol (parser, pragma_tok);
+-      return false;
+-    }
+-
+   if (cp_lexer_next_token_is (parser->lexer, CPP_NAME))
+     {
+       tree id = cp_lexer_peek_token (parser->lexer)->u.value;
+@@ -35347,7 +35332,7 @@
+ 	    id = get_identifier ("omp declare target");
+ 
+ 	  DECL_ATTRIBUTES (decl)
+-			   = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (decl));
++	    = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (decl));
+ 	  if (global_bindings_p ())
+ 	    {
+ 	      symtab_node *node = symtab_node::get (decl);
+@@ -35887,8 +35872,11 @@
+ 	}
+       if (!at1)
+ 	{
++	  DECL_ATTRIBUTES (t) = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (t));
++	  if (TREE_CODE (t) != FUNCTION_DECL && !is_global_var (t))
++	    continue;
++
+ 	  symtab_node *node = symtab_node::get (t);
+-	  DECL_ATTRIBUTES (t) = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (t));
+ 	  if (node != NULL)
+ 	    {
+ 	      node->offloadable = 1;
+@@ -37404,6 +37392,8 @@
+       return true;
+ 
+     case PRAGMA_OMP_ORDERED:
++      if (context != pragma_stmt && context != pragma_compound)
++	goto bad_stmt;
+       stmt = push_omp_privatization_clauses (false);
+       ret = cp_parser_omp_ordered (parser, pragma_tok, context, if_p);
+       pop_omp_privatization_clauses (stmt);
+@@ -37410,6 +37400,8 @@
+       return ret;
+ 
+     case PRAGMA_OMP_TARGET:
++      if (context != pragma_stmt && context != pragma_compound)
++	goto bad_stmt;
+       stmt = push_omp_privatization_clauses (false);
+       ret = cp_parser_omp_target (parser, pragma_tok, context, if_p);
+       pop_omp_privatization_clauses (stmt);
+Index: gcc/cp/call.c
+===================================================================
+--- a/src/gcc/cp/call.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/call.c	(.../branches/gcc-6-branch)
+@@ -7667,6 +7667,9 @@
+ 	{
+ 	  arg = cp_build_indirect_ref (arg, RO_NULL, complain);
+ 	  val = build2 (MODIFY_EXPR, TREE_TYPE (to), to, arg);
++	  if (cxx_dialect >= cxx14)
++	    /* Handle NSDMI that refer to the object being initialized.  */
++	    replace_placeholders (arg, to);
+ 	}
+       else
+ 	{
+Index: gcc/cp/lambda.c
+===================================================================
+--- a/src/gcc/cp/lambda.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/lambda.c	(.../branches/gcc-6-branch)
+@@ -746,16 +746,14 @@
+   return result;
+ }
+ 
+-/* We don't want to capture 'this' until we know we need it, i.e. after
+-   overload resolution has chosen a non-static member function.  At that
+-   point we call this function to turn a dummy object into a use of the
+-   'this' capture.  */
++/* Return the current LAMBDA_EXPR, if this is a resolvable dummy
++   object.  NULL otherwise..  */
+ 
+-tree
+-maybe_resolve_dummy (tree object, bool add_capture_p)
++static tree
++resolvable_dummy_lambda (tree object)
+ {
+   if (!is_dummy_object (object))
+-    return object;
++    return NULL_TREE;
+ 
+   tree type = TYPE_MAIN_VARIANT (TREE_TYPE (object));
+   gcc_assert (!TYPE_PTR_P (type));
+@@ -765,18 +763,63 @@
+       && LAMBDA_TYPE_P (current_class_type)
+       && lambda_function (current_class_type)
+       && DERIVED_FROM_P (type, current_nonlambda_class_type ()))
+-    {
+-      /* In a lambda, need to go through 'this' capture.  */
+-      tree lam = CLASSTYPE_LAMBDA_EXPR (current_class_type);
+-      tree cap = lambda_expr_this_capture (lam, add_capture_p);
+-      if (cap && cap != error_mark_node)
++    return CLASSTYPE_LAMBDA_EXPR (current_class_type);
++
++  return NULL_TREE;
++}
++
++/* We don't want to capture 'this' until we know we need it, i.e. after
++   overload resolution has chosen a non-static member function.  At that
++   point we call this function to turn a dummy object into a use of the
++   'this' capture.  */
++
++tree
++maybe_resolve_dummy (tree object, bool add_capture_p)
++{
++  if (tree lam = resolvable_dummy_lambda (object))
++    if (tree cap = lambda_expr_this_capture (lam, add_capture_p))
++      if (cap != error_mark_node)
+ 	object = build_x_indirect_ref (EXPR_LOCATION (object), cap,
+ 				       RO_NULL, tf_warning_or_error);
+-    }
+ 
+   return object;
+ }
+ 
++/* When parsing a generic lambda containing an argument-dependent
++   member function call we defer overload resolution to instantiation
++   time.  But we have to know now whether to capture this or not.
++   Do that if FNS contains any non-static fns.
++   The std doesn't anticipate this case, but I expect this to be the
++   outcome of discussion.  */
++
++void
++maybe_generic_this_capture (tree object, tree fns)
++{
++  if (tree lam = resolvable_dummy_lambda (object))
++    if (!LAMBDA_EXPR_THIS_CAPTURE (lam))
++      {
++	/* We've not yet captured, so look at the function set of
++	   interest.  */
++	if (BASELINK_P (fns))
++	  fns = BASELINK_FUNCTIONS (fns);
++	bool id_expr = TREE_CODE (fns) == TEMPLATE_ID_EXPR;
++	if (id_expr)
++	  fns = TREE_OPERAND (fns, 0);
++	for (; fns; fns = OVL_NEXT (fns))
++	  {
++	    tree fn = OVL_CURRENT (fns);
++
++	    if ((!id_expr || TREE_CODE (fn) == TEMPLATE_DECL)
++		&& DECL_NONSTATIC_MEMBER_FUNCTION_P (fn))
++	      {
++		/* Found a non-static member.  Capture this.  */
++		lambda_expr_this_capture (lam, true);
++		break;
++	      }
++	  }
++      }
++}
++
+ /* Returns the innermost non-lambda function.  */
+ 
+ tree
+Index: gcc/cp/cp-tree.h
+===================================================================
+--- a/src/gcc/cp/cp-tree.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/cp-tree.h	(.../branches/gcc-6-branch)
+@@ -6447,6 +6447,7 @@
+ extern bool is_normal_capture_proxy             (tree);
+ extern void register_capture_members		(tree);
+ extern tree lambda_expr_this_capture            (tree, bool);
++extern void maybe_generic_this_capture		(tree, tree);
+ extern tree maybe_resolve_dummy			(tree, bool);
+ extern tree current_nonlambda_function		(void);
+ extern tree nonlambda_method_basetype		(void);
+Index: gcc/cp/name-lookup.c
+===================================================================
+--- a/src/gcc/cp/name-lookup.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/name-lookup.c	(.../branches/gcc-6-branch)
+@@ -3470,7 +3470,12 @@
+   if (scope == NULL_TREE)
+     scope = global_namespace;
+   b = binding_for_name (NAMESPACE_LEVEL (scope), name);
+-  if (!b->value || TREE_CODE (val) == OVERLOAD || val == error_mark_node)
++  if (!b->value
++      /* For templates and using we create a single element OVERLOAD.
++	 Look for the chain to know whether this is really augmenting
++	 an existing overload.  */
++      || (TREE_CODE (val) == OVERLOAD && OVL_CHAIN (val))
++      || val == error_mark_node)
+     b->value = val;
+   else
+     supplement_binding (b, val);
+Index: gcc/lto-cgraph.c
+===================================================================
+--- a/src/gcc/lto-cgraph.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/lto-cgraph.c	(.../branches/gcc-6-branch)
+@@ -623,6 +623,7 @@
+     }
+   bp_pack_value (&bp, node->tls_model, 3);
+   bp_pack_value (&bp, node->used_by_single_function, 1);
++  bp_pack_value (&bp, node->dynamically_initialized, 1);
+   bp_pack_value (&bp, node->need_bounds_init, 1);
+   streamer_write_bitpack (&bp);
+ 
+@@ -1397,6 +1398,7 @@
+     node->alias_target = get_alias_symbol (node->decl);
+   node->tls_model = (enum tls_model)bp_unpack_value (&bp, 3);
+   node->used_by_single_function = (enum tls_model)bp_unpack_value (&bp, 1);
++  node->dynamically_initialized = bp_unpack_value (&bp, 1);
+   node->need_bounds_init = bp_unpack_value (&bp, 1);
+   group = read_identifier (ib);
+   if (group)
+Index: gcc/tree-call-cdce.c
+===================================================================
+--- a/src/gcc/tree-call-cdce.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-call-cdce.c	(.../branches/gcc-6-branch)
+@@ -805,7 +805,18 @@
+       if (EDGE_COUNT (join_tgt_in_edge_from_call->dest->preds) > 1)
+ 	join_tgt_bb = split_edge (join_tgt_in_edge_from_call);
+       else
+-	join_tgt_bb = join_tgt_in_edge_from_call->dest;
++	{
++	  join_tgt_bb = join_tgt_in_edge_from_call->dest;
++	  /* We may have degenerate PHIs in the destination.  Propagate
++	     those out.  */
++	  for (gphi_iterator i = gsi_start_phis (join_tgt_bb); !gsi_end_p (i);)
++	    {
++	      gphi *phi = i.phi ();
++	      replace_uses_by (gimple_phi_result (phi),
++			       gimple_phi_arg_def (phi, 0));
++	      remove_phi_node (&i, true);
++	    }
++	}
+     }
+   else
+     {
+Index: gcc/ipa-pure-const.c
+===================================================================
+--- a/src/gcc/ipa-pure-const.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ipa-pure-const.c	(.../branches/gcc-6-branch)
+@@ -1160,7 +1160,8 @@
+ cdtor_p (cgraph_node *n, void *)
+ {
+   if (DECL_STATIC_CONSTRUCTOR (n->decl) || DECL_STATIC_DESTRUCTOR (n->decl))
+-    return !TREE_READONLY (n->decl) && !DECL_PURE_P (n->decl);
++    return ((!TREE_READONLY (n->decl) && !DECL_PURE_P (n->decl))
++	    || DECL_LOOPING_CONST_OR_PURE_P (n->decl));
+   return false;
+ }
+ 
+Index: gcc/ira-int.h
+===================================================================
+--- a/src/gcc/ira-int.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ira-int.h	(.../branches/gcc-6-branch)
+@@ -782,7 +782,7 @@
+ 
+   /* Initialized once.  It is a maximal possible size of the allocated
+      struct costs.  */
+-  int x_max_struct_costs_size;
++  size_t x_max_struct_costs_size;
+ 
+   /* Allocated and initialized once, and used to initialize cost values
+      for each insn.  */
+Index: gcc/dwarf2out.c
+===================================================================
+--- a/src/gcc/dwarf2out.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/dwarf2out.c	(.../branches/gcc-6-branch)
+@@ -16615,10 +16615,6 @@
+ field_byte_offset (const_tree decl, struct vlr_context *ctx,
+ 		   HOST_WIDE_INT *cst_offset)
+ {
+-  offset_int object_offset_in_bits;
+-  offset_int object_offset_in_bytes;
+-  offset_int bitpos_int;
+-  bool is_byte_offset_cst, is_bit_offset_cst;
+   tree tree_result;
+   dw_loc_list_ref loc_result;
+ 
+@@ -16629,12 +16625,9 @@
+   else
+     gcc_assert (TREE_CODE (decl) == FIELD_DECL);
+ 
+-  is_bit_offset_cst = TREE_CODE (DECL_FIELD_BIT_OFFSET (decl)) != INTEGER_CST;
+-  is_byte_offset_cst = TREE_CODE (DECL_FIELD_OFFSET (decl)) != INTEGER_CST;
+-
+   /* We cannot handle variable bit offsets at the moment, so abort if it's the
+      case.  */
+-  if (is_bit_offset_cst)
++  if (TREE_CODE (DECL_FIELD_BIT_OFFSET (decl)) != INTEGER_CST)
+     return NULL;
+ 
+ #ifdef PCC_BITFIELD_TYPE_MATTERS
+@@ -16641,8 +16634,12 @@
+   /* We used to handle only constant offsets in all cases.  Now, we handle
+      properly dynamic byte offsets only when PCC bitfield type doesn't
+      matter.  */
+-  if (PCC_BITFIELD_TYPE_MATTERS && is_byte_offset_cst && is_bit_offset_cst)
++  if (PCC_BITFIELD_TYPE_MATTERS
++      && TREE_CODE (DECL_FIELD_OFFSET (decl)) == INTEGER_CST)
+     {
++      offset_int object_offset_in_bits;
++      offset_int object_offset_in_bytes;
++      offset_int bitpos_int;
+       tree type;
+       tree field_size_tree;
+       offset_int deepest_bitpos;
+@@ -16737,13 +16734,23 @@
+ 	  object_offset_in_bits
+ 	    = round_up_to_align (object_offset_in_bits, decl_align_in_bits);
+ 	}
++
++      object_offset_in_bytes
++	= wi::lrshift (object_offset_in_bits, LOG2_BITS_PER_UNIT);
++      if (ctx->variant_part_offset == NULL_TREE)
++	{
++	  *cst_offset = object_offset_in_bytes.to_shwi ();
++	  return NULL;
++	}
++      tree_result = wide_int_to_tree (sizetype, object_offset_in_bytes);
+     }
++  else
+ #endif /* PCC_BITFIELD_TYPE_MATTERS */
++    tree_result = byte_position (decl);
+ 
+-  tree_result = byte_position (decl);
+   if (ctx->variant_part_offset != NULL_TREE)
+-    tree_result = fold (build2 (PLUS_EXPR, TREE_TYPE (tree_result),
+-				ctx->variant_part_offset, tree_result));
++    tree_result = fold_build2 (PLUS_EXPR, TREE_TYPE (tree_result),
++			       ctx->variant_part_offset, tree_result);
+ 
+   /* If the byte offset is a constant, it's simplier to handle a native
+      constant rather than a DWARF expression.  */
+@@ -22221,14 +22228,12 @@
+ 
+ 	      if (!lower_cst_included)
+ 		lower_cst
+-		  = fold (build2 (PLUS_EXPR, TREE_TYPE (lower_cst),
+-				  lower_cst,
+-				  build_int_cst (TREE_TYPE (lower_cst), 1)));
++		  = fold_build2 (PLUS_EXPR, TREE_TYPE (lower_cst), lower_cst,
++				 build_int_cst (TREE_TYPE (lower_cst), 1));
+ 	      if (!upper_cst_included)
+ 		upper_cst
+-		  = fold (build2 (MINUS_EXPR, TREE_TYPE (upper_cst),
+-				  upper_cst,
+-				  build_int_cst (TREE_TYPE (upper_cst), 1)));
++		  = fold_build2 (MINUS_EXPR, TREE_TYPE (upper_cst), upper_cst,
++				 build_int_cst (TREE_TYPE (upper_cst), 1));
+ 
+ 	      if (!get_discr_value (lower_cst,
+ 				    &new_node->dw_discr_lower_bound)
+@@ -22397,8 +22402,8 @@
+ 		 we recurse.  */
+ 
+ 	      vlr_sub_ctx.variant_part_offset
+-	        = fold (build2 (PLUS_EXPR, TREE_TYPE (variant_part_offset),
+-				variant_part_offset, byte_position (member)));
++		= fold_build2 (PLUS_EXPR, TREE_TYPE (variant_part_offset),
++			       variant_part_offset, byte_position (member));
+ 	      gen_variant_part (member, &vlr_sub_ctx, variant_die);
+ 	    }
+ 	  else
+@@ -23752,7 +23757,16 @@
+     {
+       dw_die_ref die = lookup_decl_die (decl);
+       if (die)
+-	add_location_or_const_value_attribute (die, decl, false);
++        {
++          /* We get called via the symtab code invoking late_global_decl
++             for symbols that are optimized out.  Do not add locations
++             for those.  */
++          varpool_node *node = varpool_node::get (decl);
++          if (! node || ! node->definition)
++            tree_add_const_value_attribute_for_decl (die, decl);
++          else
++            add_location_or_const_value_attribute (die, decl, false);
++        }
+     }
+ }
+ 
+Index: gcc/expr.c
+===================================================================
+--- a/src/gcc/expr.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/expr.c	(.../branches/gcc-6-branch)
+@@ -120,7 +120,8 @@
+ static rtx_insn *compress_float_constant (rtx, rtx);
+ static rtx get_subtarget (rtx);
+ static void store_constructor_field (rtx, unsigned HOST_WIDE_INT,
+-				     HOST_WIDE_INT, machine_mode,
++				     HOST_WIDE_INT, unsigned HOST_WIDE_INT,
++				     unsigned HOST_WIDE_INT, machine_mode,
+ 				     tree, int, alias_set_type, bool);
+ static void store_constructor (tree, rtx, int, HOST_WIDE_INT, bool);
+ static rtx store_field (rtx, HOST_WIDE_INT, HOST_WIDE_INT,
+@@ -5932,7 +5933,10 @@
+ 
+ static void
+ store_constructor_field (rtx target, unsigned HOST_WIDE_INT bitsize,
+-			 HOST_WIDE_INT bitpos, machine_mode mode,
++			 HOST_WIDE_INT bitpos,
++			 unsigned HOST_WIDE_INT bitregion_start,
++			 unsigned HOST_WIDE_INT bitregion_end,
++			 machine_mode mode,
+ 			 tree exp, int cleared,
+ 			 alias_set_type alias_set, bool reverse)
+ {
+@@ -5967,8 +5971,8 @@
+ 			 reverse);
+     }
+   else
+-    store_field (target, bitsize, bitpos, 0, 0, mode, exp, alias_set, false,
+-		 reverse);
++    store_field (target, bitsize, bitpos, bitregion_start, bitregion_end, mode,
++		 exp, alias_set, false, reverse);
+ }
+ 
+ 
+@@ -6003,6 +6007,7 @@
+ {
+   tree type = TREE_TYPE (exp);
+   HOST_WIDE_INT exp_size = int_size_in_bytes (type);
++  HOST_WIDE_INT bitregion_end = size > 0 ? size * BITS_PER_UNIT - 1 : 0;
+ 
+   switch (TREE_CODE (type))
+     {
+@@ -6081,7 +6086,7 @@
+ 	    if (tree_fits_uhwi_p (DECL_SIZE (field)))
+ 	      bitsize = tree_to_uhwi (DECL_SIZE (field));
+ 	    else
+-	      bitsize = -1;
++	      gcc_unreachable ();
+ 
+ 	    mode = DECL_MODE (field);
+ 	    if (DECL_BIT_FIELD (field))
+@@ -6092,32 +6097,11 @@
+ 		&& tree_fits_shwi_p (bit_position (field)))
+ 	      {
+ 		bitpos = int_bit_position (field);
+-		offset = 0;
++		offset = NULL_TREE;
+ 	      }
+ 	    else
+-	      bitpos = tree_to_shwi (DECL_FIELD_BIT_OFFSET (field));
++	      gcc_unreachable ();
+ 
+-	    if (offset)
+-	      {
+-	        machine_mode address_mode;
+-		rtx offset_rtx;
+-
+-		offset
+-		  = SUBSTITUTE_PLACEHOLDER_IN_EXPR (offset,
+-						    make_tree (TREE_TYPE (exp),
+-							       target));
+-
+-		offset_rtx = expand_normal (offset);
+-		gcc_assert (MEM_P (to_rtx));
+-
+-		address_mode = get_address_mode (to_rtx);
+-		if (GET_MODE (offset_rtx) != address_mode)
+-		  offset_rtx = convert_to_mode (address_mode, offset_rtx, 0);
+-
+-		to_rtx = offset_address (to_rtx, offset_rtx,
+-					 highest_pow2_factor (offset));
+-	      }
+-
+ 	    /* If this initializes a field that is smaller than a
+ 	       word, at the start of a word, try to widen it to a full
+ 	       word.  This special case allows us to output C++ member
+@@ -6164,7 +6148,8 @@
+ 		MEM_KEEP_ALIAS_SET_P (to_rtx) = 1;
+ 	      }
+ 
+-	    store_constructor_field (to_rtx, bitsize, bitpos, mode,
++	    store_constructor_field (to_rtx, bitsize, bitpos,
++				     0, bitregion_end, mode,
+ 				     value, cleared,
+ 				     get_alias_set (TREE_TYPE (field)),
+ 				     reverse);
+@@ -6324,7 +6309,8 @@
+ 			  }
+ 
+ 			store_constructor_field
+-			  (target, bitsize, bitpos, mode, value, cleared,
++			  (target, bitsize, bitpos, 0, bitregion_end,
++			   mode, value, cleared,
+ 			   get_alias_set (elttype), reverse);
+ 		      }
+ 		  }
+@@ -6427,7 +6413,8 @@
+ 		    target = copy_rtx (target);
+ 		    MEM_KEEP_ALIAS_SET_P (target) = 1;
+ 		  }
+-		store_constructor_field (target, bitsize, bitpos, mode, value,
++		store_constructor_field (target, bitsize, bitpos, 0,
++					 bitregion_end, mode, value,
+ 					 cleared, get_alias_set (elttype),
+ 					 reverse);
+ 	      }
+@@ -6561,7 +6548,8 @@
+ 		  ? TYPE_MODE (TREE_TYPE (value))
+ 		  : eltmode;
+ 		bitpos = eltpos * elt_size;
+-		store_constructor_field (target, bitsize, bitpos, value_mode,
++		store_constructor_field (target, bitsize, bitpos, 0,
++					 bitregion_end, value_mode,
+ 					 value, cleared, alias, reverse);
+ 	      }
+ 	  }
+@@ -6700,13 +6688,36 @@
+ 
+       temp = expand_normal (exp);
+ 
+-      /* If the value has a record type and an integral mode then, if BITSIZE
+-	 is narrower than this mode and this is for big-endian data, we must
+-	 first put the value into the low-order bits.  Moreover, the field may
+-	 be not aligned on a byte boundary; in this case, if it has reverse
+-	 storage order, it needs to be accessed as a scalar field with reverse
+-	 storage order and we must first put the value into target order.  */
+-      if (TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE
++      /* Handle calls that return values in multiple non-contiguous locations.
++	 The Irix 6 ABI has examples of this.  */
++      if (GET_CODE (temp) == PARALLEL)
++	{
++	  HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
++	  machine_mode temp_mode
++	    = smallest_mode_for_size (size * BITS_PER_UNIT, MODE_INT);
++	  rtx temp_target = gen_reg_rtx (temp_mode);
++	  emit_group_store (temp_target, temp, TREE_TYPE (exp), size);
++	  temp = temp_target;
++	}
++
++      /* Handle calls that return BLKmode values in registers.  */
++      else if (mode == BLKmode && REG_P (temp) && TREE_CODE (exp) == CALL_EXPR)
++	{
++	  rtx temp_target = gen_reg_rtx (GET_MODE (temp));
++	  copy_blkmode_from_reg (temp_target, temp, TREE_TYPE (exp));
++	  temp = temp_target;
++	}
++
++      /* If the value has aggregate type and an integral mode then, if BITSIZE
++	 is narrower than this mode and this is for big-endian data, we first
++	 need to put the value into the low-order bits for store_bit_field,
++	 except when MODE is BLKmode and BITSIZE larger than the word size
++	 (see the handling of fields larger than a word in store_bit_field).
++	 Moreover, the field may be not aligned on a byte boundary; in this
++	 case, if it has reverse storage order, it needs to be accessed as a
++	 scalar field with reverse storage order and we must first put the
++	 value into target order.  */
++      if (AGGREGATE_TYPE_P (TREE_TYPE (exp))
+ 	  && GET_MODE_CLASS (GET_MODE (temp)) == MODE_INT)
+ 	{
+ 	  HOST_WIDE_INT size = GET_MODE_BITSIZE (GET_MODE (temp));
+@@ -6717,7 +6728,8 @@
+ 	    temp = flip_storage_order (GET_MODE (temp), temp);
+ 
+ 	  if (bitsize < size
+-	      && reverse ? !BYTES_BIG_ENDIAN : BYTES_BIG_ENDIAN)
++	      && reverse ? !BYTES_BIG_ENDIAN : BYTES_BIG_ENDIAN
++	      && !(mode == BLKmode && bitsize > BITS_PER_WORD))
+ 	    temp = expand_shift (RSHIFT_EXPR, GET_MODE (temp), temp,
+ 				 size - bitsize, NULL_RTX, 1);
+ 	}
+@@ -6727,12 +6739,10 @@
+ 	  && mode != TYPE_MODE (TREE_TYPE (exp)))
+ 	temp = convert_modes (mode, TYPE_MODE (TREE_TYPE (exp)), temp, 1);
+ 
+-      /* If TEMP is not a PARALLEL (see below) and its mode and that of TARGET
+-	 are both BLKmode, both must be in memory and BITPOS must be aligned
+-	 on a byte boundary.  If so, we simply do a block copy.  Likewise for
+-	 a BLKmode-like TARGET.  */
+-      if (GET_CODE (temp) != PARALLEL
+-	  && GET_MODE (temp) == BLKmode
++      /* If the mode of TEMP and TARGET is BLKmode, both must be in memory
++	 and BITPOS must be aligned on a byte boundary.  If so, we simply do
++	 a block copy.  Likewise for a BLKmode-like TARGET.  */
++      if (GET_MODE (temp) == BLKmode
+ 	  && (GET_MODE (target) == BLKmode
+ 	      || (MEM_P (target)
+ 		  && GET_MODE_CLASS (GET_MODE (target)) == MODE_INT
+@@ -6751,39 +6761,14 @@
+ 	  return const0_rtx;
+ 	}
+ 
+-      /* Handle calls that return values in multiple non-contiguous locations.
+-	 The Irix 6 ABI has examples of this.  */
+-      if (GET_CODE (temp) == PARALLEL)
++      /* If the mode of TEMP is still BLKmode and BITSIZE not larger than the
++	 word size, we need to load the value (see again store_bit_field).  */
++      if (GET_MODE (temp) == BLKmode && bitsize <= BITS_PER_WORD)
+ 	{
+-	  HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
+-	  rtx temp_target;
+-	  if (mode == BLKmode || mode == VOIDmode)
+-	    mode = smallest_mode_for_size (size * BITS_PER_UNIT, MODE_INT);
+-	  temp_target = gen_reg_rtx (mode);
+-	  emit_group_store (temp_target, temp, TREE_TYPE (exp), size);
+-	  temp = temp_target;
++	  machine_mode temp_mode = smallest_mode_for_size (bitsize, MODE_INT);
++	  temp = extract_bit_field (temp, bitsize, 0, 1, NULL_RTX, temp_mode,
++				    temp_mode, false);
+ 	}
+-      else if (mode == BLKmode)
+-	{
+-	  /* Handle calls that return BLKmode values in registers.  */
+-	  if (REG_P (temp) && TREE_CODE (exp) == CALL_EXPR)
+-	    {
+-	      rtx temp_target = gen_reg_rtx (GET_MODE (temp));
+-	      copy_blkmode_from_reg (temp_target, temp, TREE_TYPE (exp));
+-	      temp = temp_target;
+-	    }
+-	  else
+-	    {
+-	      HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
+-	      rtx temp_target;
+-	      mode = smallest_mode_for_size (size * BITS_PER_UNIT, MODE_INT);
+-	      temp_target = gen_reg_rtx (mode);
+-	      temp_target
+-	        = extract_bit_field (temp, size * BITS_PER_UNIT, 0, 1,
+-				     temp_target, mode, mode, false);
+-	      temp = temp_target;
+-	    }
+-	}
+ 
+       /* Store the value in the bitfield.  */
+       store_bit_field (target, bitsize, bitpos,
+@@ -8941,9 +8926,9 @@
+ 
+ 	/* Left shift optimization when shifting across word_size boundary.
+ 
+-	   If mode == GET_MODE_WIDER_MODE (word_mode), then normally there isn't
+-	   native instruction to support this wide mode left shift.  Given below
+-	   scenario:
++	   If mode == GET_MODE_WIDER_MODE (word_mode), then normally
++	   there isn't native instruction to support this wide mode
++	   left shift.  Given below scenario:
+ 
+ 	    Type A = (Type) B  << C
+ 
+@@ -8952,10 +8937,11 @@
+ 
+ 			 | word_size |
+ 
+-	   If the shift amount C caused we shift B to across the word size
+-	   boundary, i.e part of B shifted into high half of destination
+-	   register, and part of B remains in the low half, then GCC will use
+-	   the following left shift expand logic:
++	   If the shift amount C caused we shift B to across the word
++	   size boundary, i.e part of B shifted into high half of
++	   destination register, and part of B remains in the low
++	   half, then GCC will use the following left shift expand
++	   logic:
+ 
+ 	   1. Initialize dest_low to B.
+ 	   2. Initialize every bit of dest_high to the sign bit of B.
+@@ -8965,20 +8951,30 @@
+ 	   5. Logic right shift D by (word_size - C).
+ 	   6. Or the result of 4 and 5 to finalize dest_high.
+ 
+-	   While, by checking gimple statements, if operand B is coming from
+-	   signed extension, then we can simplify above expand logic into:
++	   While, by checking gimple statements, if operand B is
++	   coming from signed extension, then we can simplify above
++	   expand logic into:
+ 
+ 	      1. dest_high = src_low >> (word_size - C).
+ 	      2. dest_low = src_low << C.
+ 
+-	   We can use one arithmetic right shift to finish all the purpose of
+-	   steps 2, 4, 5, 6, thus we reduce the steps needed from 6 into 2.  */
++	   We can use one arithmetic right shift to finish all the
++	   purpose of steps 2, 4, 5, 6, thus we reduce the steps
++	   needed from 6 into 2.
+ 
++	   The case is similar for zero extension, except that we
++	   initialize dest_high to zero rather than copies of the sign
++	   bit from B.  Furthermore, we need to use a logical right shift
++	   in this case.
++
++	   The choice of sign-extension versus zero-extension is
++	   determined entirely by whether or not B is signed and is
++	   independent of the current setting of unsignedp.  */
++
+ 	temp = NULL_RTX;
+ 	if (code == LSHIFT_EXPR
+ 	    && target
+ 	    && REG_P (target)
+-	    && ! unsignedp
+ 	    && mode == GET_MODE_WIDER_MODE (word_mode)
+ 	    && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode)
+ 	    && TREE_CONSTANT (treeop1)
+@@ -8999,6 +8995,8 @@
+ 		    rtx_insn *seq, *seq_old;
+ 		    unsigned int high_off = subreg_highpart_offset (word_mode,
+ 								    mode);
++		    bool extend_unsigned
++		      = TYPE_UNSIGNED (TREE_TYPE (gimple_assign_rhs1 (def)));
+ 		    rtx low = lowpart_subreg (word_mode, op0, mode);
+ 		    rtx dest_low = lowpart_subreg (word_mode, target, mode);
+ 		    rtx dest_high = simplify_gen_subreg (word_mode, target,
+@@ -9010,7 +9008,8 @@
+ 		    start_sequence ();
+ 		    /* dest_high = src_low >> (word_size - C).  */
+ 		    temp = expand_variable_shift (RSHIFT_EXPR, word_mode, low,
+-						  rshift, dest_high, unsignedp);
++						  rshift, dest_high,
++						  extend_unsigned);
+ 		    if (temp != dest_high)
+ 		      emit_move_insn (dest_high, temp);
+ 
+Index: gcc/go/gofrontend/expressions.h
+===================================================================
+--- a/src/gcc/go/gofrontend/expressions.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/go/gofrontend/expressions.h	(.../branches/gcc-6-branch)
+@@ -1633,10 +1633,11 @@
+   }
+ 
+   // Apply unary opcode OP to UNC, setting NC.  Return true if this
+-  // could be done, false if not.  Issue errors for overflow.
++  // could be done, false if not.  On overflow, issues an error and
++  // sets *ISSUED_ERROR.
+   static bool
+   eval_constant(Operator op, const Numeric_constant* unc,
+-		Location, Numeric_constant* nc);
++		Location, Numeric_constant* nc, bool *issued_error);
+ 
+   static Expression*
+   do_import(Import*);
+@@ -1755,11 +1756,11 @@
+ 
+   // Apply binary opcode OP to LEFT_NC and RIGHT_NC, setting NC.
+   // Return true if this could be done, false if not.  Issue errors at
+-  // LOCATION as appropriate.
++  // LOCATION as appropriate, and sets *ISSUED_ERROR if it did.
+   static bool
+   eval_constant(Operator op, Numeric_constant* left_nc,
+ 		Numeric_constant* right_nc, Location location,
+-		Numeric_constant* nc);
++		Numeric_constant* nc, bool* issued_error);
+ 
+   // Compare constants LEFT_NC and RIGHT_NC according to OP, setting
+   // *RESULT.  Return true if this could be done, false if not.  Issue
+Index: gcc/go/gofrontend/types.cc
+===================================================================
+--- a/src/gcc/go/gofrontend/types.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/go/gofrontend/types.cc	(.../branches/gcc-6-branch)
+@@ -2175,11 +2175,26 @@
+       is_common = true;
+     }
+ 
++  // The current garbage collector requires that the GC symbol be
++  // aligned to at least a four byte boundary.  See the use of PRECISE
++  // and LOOP in libgo/runtime/mgc0.c.
++  int64_t align;
++  if (!sym_init->type()->backend_type_align(gogo, &align))
++    go_assert(saw_errors());
++  if (align < 4)
++    align = 4;
++  else
++    {
++      // Use default alignment.
++      align = 0;
++    }
++
+   // Since we are building the GC symbol in this package, we must create the
+   // variable before converting the initializer to its backend representation
+   // because the initializer may refer to the GC symbol for this type.
+   this->gc_symbol_var_ =
+-    gogo->backend()->implicit_variable(sym_name, sym_btype, false, true, is_common, 0);
++    gogo->backend()->implicit_variable(sym_name, sym_btype, false, true,
++                                       is_common, align);
+   if (phash != NULL)
+     *phash = this->gc_symbol_var_;
+ 
+Index: gcc/go/gofrontend/expressions.cc
+===================================================================
+--- a/src/gcc/go/gofrontend/expressions.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/go/gofrontend/expressions.cc	(.../branches/gcc-6-branch)
+@@ -3639,8 +3639,12 @@
+       if (expr->numeric_constant_value(&nc))
+ 	{
+ 	  Numeric_constant result;
+-	  if (Unary_expression::eval_constant(op, &nc, loc, &result))
++	  bool issued_error;
++	  if (Unary_expression::eval_constant(op, &nc, loc, &result,
++					      &issued_error))
+ 	    return result.expression(loc);
++	  else if (issued_error)
++	    return Expression::make_error(this->location());
+ 	}
+     }
+ 
+@@ -3747,12 +3751,15 @@
+ }
+ 
+ // Apply unary opcode OP to UNC, setting NC.  Return true if this
+-// could be done, false if not.  Issue errors for overflow.
++// could be done, false if not.  On overflow, issues an error and sets
++// *ISSUED_ERROR.
+ 
+ bool
+ Unary_expression::eval_constant(Operator op, const Numeric_constant* unc,
+-				Location location, Numeric_constant* nc)
++				Location location, Numeric_constant* nc,
++				bool* issued_error)
+ {
++  *issued_error = false;
+   switch (op)
+     {
+     case OPERATOR_PLUS:
+@@ -3897,7 +3904,12 @@
+   mpz_clear(uval);
+   mpz_clear(val);
+ 
+-  return nc->set_type(unc->type(), true, location);
++  if (!nc->set_type(unc->type(), true, location))
++    {
++      *issued_error = true;
++      return false;
++    }
++  return true;
+ }
+ 
+ // Return the integral constant value of a unary expression, if it has one.
+@@ -3908,8 +3920,9 @@
+   Numeric_constant unc;
+   if (!this->expr_->numeric_constant_value(&unc))
+     return false;
++  bool issued_error;
+   return Unary_expression::eval_constant(this->op_, &unc, this->location(),
+-					 nc);
++					 nc, &issued_error);
+ }
+ 
+ // Return the type of a unary expression.
+@@ -4539,13 +4552,15 @@
+ 
+ // Apply binary opcode OP to LEFT_NC and RIGHT_NC, setting NC.  Return
+ // true if this could be done, false if not.  Issue errors at LOCATION
+-// as appropriate.
++// as appropriate, and sets *ISSUED_ERROR if it did.
+ 
+ bool
+ Binary_expression::eval_constant(Operator op, Numeric_constant* left_nc,
+ 				 Numeric_constant* right_nc,
+-				 Location location, Numeric_constant* nc)
++				 Location location, Numeric_constant* nc,
++				 bool* issued_error)
+ {
++  *issued_error = false;
+   switch (op)
+     {
+     case OPERATOR_OROR:
+@@ -4594,7 +4609,11 @@
+     r = Binary_expression::eval_integer(op, left_nc, right_nc, location, nc);
+ 
+   if (r)
+-    r = nc->set_type(type, true, location);
++    {
++      r = nc->set_type(type, true, location);
++      if (!r)
++	*issued_error = true;
++    }
+ 
+   return r;
+ }
+@@ -4917,9 +4936,15 @@
+ 	else
+ 	  {
+ 	    Numeric_constant nc;
++	    bool issued_error;
+ 	    if (!Binary_expression::eval_constant(op, &left_nc, &right_nc,
+-						  location, &nc))
++						  location, &nc,
++						  &issued_error))
++	      {
++		if (issued_error)
++		  return Expression::make_error(location);
+                 return this;
++	      }
+ 	    return nc.expression(location);
+ 	  }
+       }
+@@ -5254,8 +5279,9 @@
+   Numeric_constant right_nc;
+   if (!this->right_->numeric_constant_value(&right_nc))
+     return false;
++  bool issued_error;
+   return Binary_expression::eval_constant(this->op_, &left_nc, &right_nc,
+-					  this->location(), nc);
++					  this->location(), nc, &issued_error);
+ }
+ 
+ // Note that the value is being discarded.
+@@ -5354,8 +5380,13 @@
+ 
+   Type_context subcontext(*context);
+ 
+-  if (is_comparison)
++  if (is_constant_expr)
+     {
++      subcontext.type = NULL;
++      subcontext.may_be_abstract = true;
++    }
++  else if (is_comparison)
++    {
+       // In a comparison, the context does not determine the types of
+       // the operands.
+       subcontext.type = NULL;
+@@ -5396,8 +5427,7 @@
+ 	subcontext.type = subcontext.type->make_non_abstract_type();
+     }
+ 
+-  if (!is_constant_expr)
+-    this->left_->determine_type(&subcontext);
++  this->left_->determine_type(&subcontext);
+ 
+   if (is_shift_op)
+     {
+@@ -5417,8 +5447,7 @@
+       subcontext.may_be_abstract = false;
+     }
+ 
+-  if (!is_constant_expr)
+-    this->right_->determine_type(&subcontext);
++  this->right_->determine_type(&subcontext);
+ 
+   if (is_comparison)
+     {
+Index: gcc/tree-parloops.c
+===================================================================
+--- a/src/gcc/tree-parloops.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-parloops.c	(.../branches/gcc-6-branch)
+@@ -2511,8 +2511,8 @@
+ {
+   gphi_iterator gsi;
+   loop_vec_info simple_loop_info;
+-  loop_vec_info simple_inner_loop_info = NULL;
+-  bool allow_double_reduc = true;
++  auto_vec<gphi *, 4> double_reduc_phis;
++  auto_vec<gimple *, 4> double_reduc_stmts;
+ 
+   if (!stmt_vec_info_vec.exists ())
+     init_stmt_vec_info_vec ();
+@@ -2542,44 +2542,56 @@
+ 
+       if (double_reduc)
+ 	{
+-	  if (!allow_double_reduc
+-	      || loop->inner->inner != NULL)
++	  if (loop->inner->inner != NULL)
+ 	    continue;
+ 
+-	  if (!simple_inner_loop_info)
+-	    {
+-	      simple_inner_loop_info = vect_analyze_loop_form (loop->inner);
+-	      if (!simple_inner_loop_info)
+-		{
+-		  allow_double_reduc = false;
+-		  continue;
+-		}
+-	    }
+-
+-	  use_operand_p use_p;
+-	  gimple *inner_stmt;
+-	  bool single_use_p = single_imm_use (res, &use_p, &inner_stmt);
+-	  gcc_assert (single_use_p);
+-	  if (gimple_code (inner_stmt) != GIMPLE_PHI)
+-	    continue;
+-	  gphi *inner_phi = as_a <gphi *> (inner_stmt);
+-	  if (simple_iv (loop->inner, loop->inner, PHI_RESULT (inner_phi),
+-			 &iv, true))
+-	    continue;
+-
+-	  gimple *inner_reduc_stmt
+-	    = vect_force_simple_reduction (simple_inner_loop_info, inner_phi,
+-					   true, &double_reduc, true);
+-	  gcc_assert (!double_reduc);
+-	  if (inner_reduc_stmt == NULL)
+-	    continue;
++	  double_reduc_phis.safe_push (phi);
++	  double_reduc_stmts.safe_push (reduc_stmt);
++	  continue;
+ 	}
+ 
+       build_new_reduction (reduction_list, reduc_stmt, phi);
+     }
+   destroy_loop_vec_info (simple_loop_info, true);
+-  destroy_loop_vec_info (simple_inner_loop_info, true);
+ 
++  if (!double_reduc_phis.is_empty ())
++    {
++      simple_loop_info = vect_analyze_loop_form (loop->inner);
++      if (simple_loop_info)
++	{
++	  gphi *phi;
++	  unsigned int i;
++
++	  FOR_EACH_VEC_ELT (double_reduc_phis, i, phi)
++	    {
++	      affine_iv iv;
++	      tree res = PHI_RESULT (phi);
++	      bool double_reduc;
++
++	      use_operand_p use_p;
++	      gimple *inner_stmt;
++	      bool single_use_p = single_imm_use (res, &use_p, &inner_stmt);
++	      gcc_assert (single_use_p);
++	      if (gimple_code (inner_stmt) != GIMPLE_PHI)
++		continue;
++	      gphi *inner_phi = as_a <gphi *> (inner_stmt);
++	      if (simple_iv (loop->inner, loop->inner, PHI_RESULT (inner_phi),
++			     &iv, true))
++		continue;
++
++	      gimple *inner_reduc_stmt
++		= vect_force_simple_reduction (simple_loop_info, inner_phi,
++					       true, &double_reduc, true);
++	      gcc_assert (!double_reduc);
++	      if (inner_reduc_stmt == NULL)
++		continue;
++
++	      build_new_reduction (reduction_list, double_reduc_stmts[i], phi);
++	    }
++	  destroy_loop_vec_info (simple_loop_info, true);
++	}
++    }
++
+  gather_done:
+   /* Release the claim on gimple_uid.  */
+   free_stmt_vec_info_vec ();
+Index: gcc/ada/socket.c
+===================================================================
+--- a/src/gcc/ada/socket.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ada/socket.c	(.../branches/gcc-6-branch)
+@@ -202,7 +202,7 @@
+   struct hostent *rh;
+   int ri;
+ 
+-#if defined(__linux__) || defined(__GLIBC__)
++#if defined(__linux__) || defined(__GLIBC__) || defined(__rtems__)
+   (void) gethostbyaddr_r (addr, len, type, ret, buf, buflen, &rh, h_errnop);
+ #else
+   rh = gethostbyaddr_r (addr, len, type, ret, buf, buflen, h_errnop);
+Index: gcc/ada/system-linux-ppc.ads
+===================================================================
+--- a/src/gcc/ada/system-linux-ppc.ads	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ada/system-linux-ppc.ads	(.../branches/gcc-6-branch)
+@@ -7,7 +7,7 @@
+ --                                 S p e c                                  --
+ --                         (GNU-Linux/PPC Version)                          --
+ --                                                                          --
+---          Copyright (C) 1992-2016, Free Software Foundation, Inc.         --
++--          Copyright (C) 1992-2017, Free Software Foundation, Inc.         --
+ --                                                                          --
+ -- This specification is derived from the Ada Reference Manual for use with --
+ -- GNAT. The copyright notice above, and the license provisions that follow --
+@@ -89,7 +89,8 @@
+    --  Other System-Dependent Declarations
+ 
+    type Bit_Order is (High_Order_First, Low_Order_First);
+-   Default_Bit_Order : constant Bit_Order := High_Order_First;
++   Default_Bit_Order : constant Bit_Order :=
++                         Bit_Order'Val (Standard'Default_Bit_Order);
+    pragma Warnings (Off, Default_Bit_Order); -- kill constant condition warning
+ 
+    --  Priority-related Declarations (RM D.1)
+Index: gcc/ada/ChangeLog
+===================================================================
+--- a/src/gcc/ada/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ada/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,40 @@
++2017-03-08  Thanassis Tsiodras  <ttsiodras@gmail.com>
++
++	PR ada/79903
++	* socket.c (__gnat_gethostbyaddr): Add missing test for __rtems__.
++
++2017-03-08  Eric Botcazou  <ebotcazou@adacore.com>
++
++	PR ada/79945
++	* system-linux-ppc.ads (Default_Bit_Order): Use Standard's setting.
++
++2017-02-24  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/decl.c (gnat_to_gnu_field): Do not remove the wrapper
++	around a justified modular type if it doesn't have the same scalar
++	storage order as the enclosing record type.
++
++2017-02-24  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/trans.c (gnat_to_gnu): Do not apply special handling
++	of boolean rvalues to function calls.
++
++2017-02-24  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/utils.c (fold_bit_position): New function.
++	(rest_of_record_type_compilation): Call it instead of bit_position to
++	compute the field position and remove the call to remove_conversions.
++	(compute_related_constant): Factor out the multiplication in both
++	operands, if any, and streamline the final test.
++
++2017-02-24  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/trans.c (return_value_ok_for_nrv_p): Add sanity check.
++
++2017-02-12  John Marino  <gnugcc@marino.st>
++
++	* gcc-interface/Makefile.in: Support aarch64-freebsd.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/ada/gcc-interface/utils.c
+===================================================================
+--- a/src/gcc/ada/gcc-interface/utils.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ada/gcc-interface/utils.c	(.../branches/gcc-6-branch)
+@@ -238,6 +238,7 @@
+   hash_table<pad_type_hasher> *pad_type_hash_table;
+ 
+ static tree merge_sizes (tree, tree, tree, bool, bool);
++static tree fold_bit_position (const_tree);
+ static tree compute_related_constant (tree, tree);
+ static tree split_plus (tree, tree *);
+ static tree float_type_for_precision (int, machine_mode);
+@@ -2021,15 +2022,11 @@
+ 	{
+ 	  tree field_type = TREE_TYPE (old_field);
+ 	  tree field_name = DECL_NAME (old_field);
+-	  tree curpos = bit_position (old_field);
++	  tree curpos = fold_bit_position (old_field);
+ 	  tree pos, new_field;
+ 	  bool var = false;
+ 	  unsigned int align = 0;
+ 
+-	  /* We're going to do some pattern matching below so remove as many
+-	     conversions as possible.  */
+-	  curpos = remove_conversions (curpos, true);
+-
+ 	  /* See how the position was modified from the last position.
+ 
+ 	     There are two basic cases we support: a value was added
+@@ -2126,7 +2123,7 @@
+ 	     is when there are other components at fixed positions after
+ 	     it (meaning there was a rep clause for every field) and we
+ 	     want to be able to encode them.  */
+-	  last_pos = size_binop (PLUS_EXPR, bit_position (old_field),
++	  last_pos = size_binop (PLUS_EXPR, curpos,
+ 				 (TREE_CODE (TREE_TYPE (old_field))
+ 				  == QUAL_UNION_TYPE)
+ 				 ? bitsize_zero_node
+@@ -2181,6 +2178,23 @@
+   return new_size;
+ }
+ 
++/* Return the bit position of FIELD, in bits from the start of the record,
++   and fold it as much as possible.  This is a tree of type bitsizetype.  */
++
++static tree
++fold_bit_position (const_tree field)
++{
++  tree offset = DECL_FIELD_OFFSET (field);
++  if (TREE_CODE (offset) == MULT_EXPR || TREE_CODE (offset) == PLUS_EXPR)
++    offset = size_binop (TREE_CODE (offset),
++			 fold_convert (bitsizetype, TREE_OPERAND (offset, 0)),
++			 fold_convert (bitsizetype, TREE_OPERAND (offset, 1)));
++  else
++    offset = fold_convert (bitsizetype, offset);
++  return size_binop (PLUS_EXPR, DECL_FIELD_BIT_OFFSET (field),
++ 		     size_binop (MULT_EXPR, offset, bitsize_unit_node));
++}
++
+ /* Utility function of above to see if OP0 and OP1, both of SIZETYPE, are
+    related by the addition of a constant.  Return that constant if so.  */
+ 
+@@ -2187,17 +2201,28 @@
+ static tree
+ compute_related_constant (tree op0, tree op1)
+ {
+-  tree op0_var, op1_var;
+-  tree op0_con = split_plus (op0, &op0_var);
+-  tree op1_con = split_plus (op1, &op1_var);
+-  tree result = size_binop (MINUS_EXPR, op0_con, op1_con);
++  tree factor, op0_var, op1_var, op0_cst, op1_cst, result;
+ 
++  if (TREE_CODE (op0) == MULT_EXPR
++      && TREE_CODE (op1) == MULT_EXPR
++      && TREE_CODE (TREE_OPERAND (op0, 1)) == INTEGER_CST
++      && TREE_OPERAND (op1, 1) == TREE_OPERAND (op0, 1))
++    {
++      factor = TREE_OPERAND (op0, 1);
++      op0 = TREE_OPERAND (op0, 0);
++      op1 = TREE_OPERAND (op1, 0);
++    }
++  else
++    factor = NULL_TREE;
++
++  op0_cst = split_plus (op0, &op0_var);
++  op1_cst = split_plus (op1, &op1_var);
++  result = size_binop (MINUS_EXPR, op0_cst, op1_cst);
++
+   if (operand_equal_p (op0_var, op1_var, 0))
+-    return result;
+-  else if (operand_equal_p (op0, size_binop (PLUS_EXPR, op1_var, result), 0))
+-    return result;
+-  else
+-    return 0;
++    return factor ? size_binop (MULT_EXPR, factor, result) : result;
++
++  return NULL_TREE;
+ }
+ 
+ /* Utility function of above to split a tree OP which may be a sum, into a
+Index: gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ada/gcc-interface/Makefile.in	(.../branches/gcc-6-branch)
+@@ -1475,6 +1475,34 @@
+   LIBRARY_VERSION := $(LIB_VERSION)
+ endif
+ 
++# aarch64 FreeBSD
++ifeq ($(strip $(filter-out %aarch64 freebsd%,$(target_cpu) $(target_os))),)
++  LIBGNAT_TARGET_PAIRS = \
++  a-intnam.ads<a-intnam-freebsd.ads \
++  s-inmaop.adb<s-inmaop-posix.adb \
++  s-intman.adb<s-intman-posix.adb \
++  s-mudido.adb<s-mudido-affinity.adb \
++  s-osinte.adb<s-osinte-freebsd.adb \
++  s-osinte.ads<s-osinte-freebsd.ads \
++  s-osprim.adb<s-osprim-posix.adb \
++  s-taprop.adb<s-taprop-posix.adb \
++  s-taspri.ads<s-taspri-posix.ads \
++  s-tpopsp.adb<s-tpopsp-posix.adb \
++  $(ATOMICS_TARGET_PAIRS) \
++  $(ATOMICS_BUILTINS_TARGET_PAIRS) \
++  system.ads<system-freebsd-x86_64.ads
++
++  TOOLS_TARGET_PAIRS = \
++  mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb
++  GNATLIB_SHARED = gnatlib-shared-dual
++
++  EH_MECHANISM=-gcc
++  THREADSLIB= -lpthread
++  GMEM_LIB = gmemlib
++  LIBRARY_VERSION := $(LIB_VERSION)
++  MISCLIB = -lutil
++endif
++
+ # x86 FreeBSD
+ ifeq ($(strip $(filter-out %86 freebsd%,$(target_cpu) $(target_os))),)
+   LIBGNAT_TARGET_PAIRS = \
+Index: gcc/ada/gcc-interface/decl.c
+===================================================================
+--- a/src/gcc/ada/gcc-interface/decl.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ada/gcc-interface/decl.c	(.../branches/gcc-6-branch)
+@@ -6685,6 +6685,7 @@
+ gnat_to_gnu_field (Entity_Id gnat_field, tree gnu_record_type, int packed,
+ 		   bool definition, bool debug_info_p)
+ {
++  const Entity_Id gnat_record_type = Underlying_Type (Scope (gnat_field));
+   const Entity_Id gnat_field_type = Etype (gnat_field);
+   const bool is_aliased
+     = Is_Aliased (gnat_field);
+@@ -6771,8 +6772,7 @@
+   if (Present (Component_Clause (gnat_field)))
+     {
+       Node_Id gnat_clause = Component_Clause (gnat_field);
+-      Entity_Id gnat_parent
+-	= Parent_Subtype (Underlying_Type (Scope (gnat_field)));
++      Entity_Id gnat_parent = Parent_Subtype (gnat_record_type);
+ 
+       gnu_pos = UI_To_gnu (Component_Bit_Offset (gnat_field), bitsizetype);
+       gnu_size = validate_size (Esize (gnat_field), gnu_field_type,
+@@ -6891,7 +6891,7 @@
+ 
+   /* If the record has rep clauses and this is the tag field, make a rep
+      clause for it as well.  */
+-  else if (Has_Specified_Layout (Scope (gnat_field))
++  else if (Has_Specified_Layout (gnat_record_type)
+ 	   && Chars (gnat_field) == Name_uTag)
+     {
+       gnu_pos = bitsize_zero_node;
+@@ -6928,11 +6928,14 @@
+       /* If the field's type is justified modular, we would need to remove
+ 	 the wrapper to (better) meet the layout requirements.  However we
+ 	 can do so only if the field is not aliased to preserve the unique
+-	 layout and if the prescribed size is not greater than that of the
+-	 packed array to preserve the justification.  */
++	 layout, if it has the same storage order as the enclosing record
++	 and if the prescribed size is not greater than that of the packed
++	 array to preserve the justification.  */
+       if (!needs_strict_alignment
+ 	  && TREE_CODE (gnu_field_type) == RECORD_TYPE
+ 	  && TYPE_JUSTIFIED_MODULAR_P (gnu_field_type)
++	  && TYPE_REVERSE_STORAGE_ORDER (gnu_field_type)
++	     == Reverse_Storage_Order (gnat_record_type)
+ 	  && tree_int_cst_compare (gnu_size, TYPE_ADA_SIZE (gnu_field_type))
+ 	       <= 0)
+ 	gnu_field_type = TREE_TYPE (TYPE_FIELDS (gnu_field_type));
+Index: gcc/ada/gcc-interface/trans.c
+===================================================================
+--- a/src/gcc/ada/gcc-interface/trans.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ada/gcc-interface/trans.c	(.../branches/gcc-6-branch)
+@@ -3600,9 +3600,16 @@
+   if (TREE_ADDRESSABLE (ret_val))
+     return false;
+ 
++  /* For the constrained case, test for overalignment.  */
+   if (ret_obj && DECL_ALIGN (ret_val) > DECL_ALIGN (ret_obj))
+     return false;
+ 
++  /* For the unconstrained case, test for bogus initialization.  */
++  if (!ret_obj
++      && DECL_INITIAL (ret_val)
++      && TREE_CODE (DECL_INITIAL (ret_val)) == NULL_EXPR)
++    return false;
++
+   return true;
+ }
+ 
+@@ -7696,7 +7703,6 @@
+       && (kind == N_Identifier
+ 	  || kind == N_Expanded_Name
+ 	  || kind == N_Explicit_Dereference
+-	  || kind == N_Function_Call
+ 	  || kind == N_Indexed_Component
+ 	  || kind == N_Selected_Component)
+       && TREE_CODE (get_base_type (gnu_result_type)) == BOOLEAN_TYPE
+Index: gcc/asan.c
+===================================================================
+--- a/src/gcc/asan.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/asan.c	(.../branches/gcc-6-branch)
+@@ -2275,7 +2275,11 @@
+   CONSTRUCTOR_APPEND_ELT (vinner, NULL_TREE,
+ 			  fold_convert (const_ptr_type_node, module_name_cst));
+   varpool_node *vnode = varpool_node::get (decl);
+-  int has_dynamic_init = vnode ? vnode->dynamically_initialized : 0;
++  int has_dynamic_init = 0;
++  /* FIXME: Enable initialization order fiasco detection in LTO mode once
++     proper fix for PR 79061 will be applied.  */
++  if (!in_lto_p)
++    has_dynamic_init = vnode ? vnode->dynamically_initialized : 0;
+   CONSTRUCTOR_APPEND_ELT (vinner, NULL_TREE,
+ 			  build_int_cst (uptr, has_dynamic_init));
+   tree locptr = NULL_TREE;
+Index: gcc/lra-remat.c
+===================================================================
+--- a/src/gcc/lra-remat.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/lra-remat.c	(.../branches/gcc-6-branch)
+@@ -1116,6 +1116,7 @@
+ static bool
+ do_remat (void)
+ {
++  unsigned regno;
+   rtx_insn *insn;
+   basic_block bb;
+   bitmap_head avail_cands;
+@@ -1123,12 +1124,21 @@
+   bool changed_p = false;
+   /* Living hard regs and hard registers of living pseudos.  */
+   HARD_REG_SET live_hard_regs;
++  bitmap_iterator bi;
+ 
+   bitmap_initialize (&avail_cands, &reg_obstack);
+   bitmap_initialize (&active_cands, &reg_obstack);
+   FOR_EACH_BB_FN (bb, cfun)
+     {
+-      REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_out (bb));
++      CLEAR_HARD_REG_SET (live_hard_regs);
++      EXECUTE_IF_SET_IN_BITMAP (df_get_live_in (bb), 0, regno, bi)
++	{
++	  int hard_regno = regno < FIRST_PSEUDO_REGISTER
++			   ? regno
++			   : reg_renumber[regno];
++	  if (hard_regno >= 0)
++	    SET_HARD_REG_BIT (live_hard_regs, hard_regno);
++	}
+       bitmap_and (&avail_cands, &get_remat_bb_data (bb)->avin_cands,
+ 		  &get_remat_bb_data (bb)->livein_cands);
+       /* Activating insns are always in the same block as their corresponding
+Index: gcc/fortran/openmp.c
+===================================================================
+--- a/src/gcc/fortran/openmp.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/openmp.c	(.../branches/gcc-6-branch)
+@@ -3530,6 +3530,11 @@
+ 		    else
+ 		      resolve_oacc_data_clauses (n->sym, n->where, name);
+ 		  }
++		else if (list != OMP_CLAUSE_DEPEND
++			 && n->sym->as
++			 && n->sym->as->type == AS_ASSUMED_SIZE)
++		  gfc_error ("Assumed size array %qs in %s clause at %L",
++			     n->sym->name, name, &n->where);
+ 	      }
+ 
+ 	    if (list != OMP_LIST_DEPEND)
+Index: gcc/fortran/trans-expr.c
+===================================================================
+--- a/src/gcc/fortran/trans-expr.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/trans-expr.c	(.../branches/gcc-6-branch)
+@@ -1898,8 +1898,11 @@
+ 		     &expr->where);
+     }
+ 
+-  caf_decl = expr->symtree->n.sym->backend_decl;
+-  gcc_assert (caf_decl);
++  /* Make sure the backend_decl is present before accessing it.  */
++  caf_decl = expr->symtree->n.sym->backend_decl == NULL_TREE
++      ? gfc_get_symbol_decl (expr->symtree->n.sym)
++      : expr->symtree->n.sym->backend_decl;
++
+   if (expr->symtree->n.sym->ts.type == BT_CLASS)
+     caf_decl = gfc_class_data_get (caf_decl);
+   if (expr->symtree->n.sym->attr.codimension)
+Index: gcc/fortran/decl.c
+===================================================================
+--- a/src/gcc/fortran/decl.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/decl.c	(.../branches/gcc-6-branch)
+@@ -922,7 +922,8 @@
+ 
+       if (!t && e->ts.type == BT_UNKNOWN
+ 	  && e->symtree->n.sym->attr.untyped == 1
+-	  && (e->symtree->n.sym->ns->seen_implicit_none == 1
++	  && (flag_implicit_none
++	      || e->symtree->n.sym->ns->seen_implicit_none == 1
+ 	      || e->symtree->n.sym->ns->parent->seen_implicit_none == 1))
+ 	{
+ 	  gfc_free_expr (e);
+Index: gcc/fortran/trans-openmp.c
+===================================================================
+--- a/src/gcc/fortran/trans-openmp.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/trans-openmp.c	(.../branches/gcc-6-branch)
+@@ -37,6 +37,11 @@
+ #include "arith.h"
+ #include "omp-low.h"
+ #include "gomp-constants.h"
++#undef GCC_DIAG_STYLE
++#define GCC_DIAG_STYLE __gcc_tdiag__
++#include "diagnostic-core.h"
++#undef GCC_DIAG_STYLE
++#define GCC_DIAG_STYLE __gcc_gfc__
+ 
+ int ompws_flags;
+ 
+@@ -1028,6 +1033,21 @@
+     return;
+ 
+   tree decl = OMP_CLAUSE_DECL (c);
++
++  /* Assumed-size arrays can't be mapped implicitly, they have to be
++     mapped explicitly using array sections.  */
++  if (TREE_CODE (decl) == PARM_DECL
++      && GFC_ARRAY_TYPE_P (TREE_TYPE (decl))
++      && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (decl)) == GFC_ARRAY_UNKNOWN
++      && GFC_TYPE_ARRAY_UBOUND (TREE_TYPE (decl),
++				GFC_TYPE_ARRAY_RANK (TREE_TYPE (decl)) - 1)
++	 == NULL)
++    {
++      error_at (OMP_CLAUSE_LOCATION (c),
++		"implicit mapping of assumed size array %qD", decl);
++      return;
++    }
++
+   tree c2 = NULL_TREE, c3 = NULL_TREE, c4 = NULL_TREE;
+   if (POINTER_TYPE_P (TREE_TYPE (decl)))
+     {
+Index: gcc/fortran/ChangeLog
+===================================================================
+--- a/src/gcc/fortran/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,67 @@
++2017-03-14  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-03-06  Richard Biener  <rguenther@suse.de>
++
++	PR fortran/79894
++	* trans.c (gfc_add_modify_loc): Weaken assert.
++
++2017-02-25  Paul Thomas  <pault@gcc.gnu.org>
++
++	PR fortran/78474
++	* module.c (gfc_match_submodule): If there is more than one
++	colon, it is a syntax error.
++
++	PR fortran/78331
++	* module.c (gfc_use_module): If an smod file does not exist it
++	is either because the module does not have a module procedure
++	interface or there is an error in the module.
++
++2017-02-07  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	* trans-types.c	(gfc_get_int_kind_from_width_isofortranen):  Choose
++	REAL type with the widest precision if two (or more) have the same
++	storage size.
++
++2017-01-29  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	Backported from trunk
++	2017-01-13  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	PR fortran/70697
++	* resolve.c (resolve_lock_unlock_event): Resolve the expression for
++	event's until_count.
++
++2017-01-29  Andre Vehreschild  <vehre@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/70696
++	* trans-expr.c (gfc_get_tree_for_caf_expr): Ensure the backend_decl
++	is valid before accessing it.  Remove unnecessary assert.
++	* trans-decl.c (gfc_build_qualified_array): Add static tokens to the
++	parent function's scope only, when the decl-context is not the
++	translation unit.
++
++2017-01-17  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2016-12-21  Jakub Jelinek  <jakub@redhat.com>
++
++	PR fortran/78866
++	* openmp.c (resolve_omp_clauses): Diagnose assumed size arrays in
++	OpenMP map, to and from clauses.
++	* trans-openmp.c: Include diagnostic-core.h, temporarily redefining
++	GCC_DIAG_STYLE to __gcc_tdiag__.
++	(gfc_omp_finish_clause): Diagnose implicitly mapped assumed size
++	arrays.
++
++2016-12-22  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/78239
++	* decl.c (char_len_param_value): Also check for -fimplicit-none
++	when determining if implicit none is in force.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/fortran/module.c
+===================================================================
+--- a/src/gcc/fortran/module.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/module.c	(.../branches/gcc-6-branch)
+@@ -740,6 +740,7 @@
+   match m;
+   char name[GFC_MAX_SYMBOL_LEN + 1];
+   gfc_use_list *use_list;
++  bool seen_colon = false;
+ 
+   if (!gfc_notify_std (GFC_STD_F2008, "SUBMODULE declaration at %C"))
+     return MATCH_ERROR;
+@@ -772,7 +773,7 @@
+ 	}
+       else
+ 	{
+-	module_list = use_list;
++	  module_list = use_list;
+ 	  use_list->module_name = gfc_get_string (name);
+ 	  use_list->submodule_name = use_list->module_name;
+ 	}
+@@ -780,8 +781,11 @@
+       if (gfc_match_char (')') == MATCH_YES)
+ 	break;
+ 
+-      if (gfc_match_char (':') != MATCH_YES)
++      if (gfc_match_char (':') != MATCH_YES
++	  || seen_colon)
+ 	goto syntax;
++
++      seen_colon = true;
+     }
+ 
+   m = gfc_match (" %s%t", &gfc_new_block);
+@@ -6917,8 +6921,17 @@
+     }
+ 
+   if (module_fp == NULL)
+-    gfc_fatal_error ("Can't open module file %qs for reading at %C: %s",
+-		     filename, xstrerror (errno));
++    {
++      if (gfc_state_stack->state != COMP_SUBMODULE
++	  && module->submodule_name == NULL)
++	gfc_fatal_error ("Can't open module file %qs for reading at %C: %s",
++			 filename, xstrerror (errno));
++      else
++	gfc_fatal_error ("Module file %qs has not been generated, either "
++			 "because the module does not contain a MODULE "
++			 "PROCEDURE or there is an error in the module.",
++			 filename);
++    }
+ 
+   /* Check that we haven't already USEd an intrinsic module with the
+      same name.  */
+Index: gcc/fortran/trans.c
+===================================================================
+--- a/src/gcc/fortran/trans.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/trans.c	(.../branches/gcc-6-branch)
+@@ -151,11 +151,11 @@
+   tree t1, t2;
+   t1 = TREE_TYPE (rhs);
+   t2 = TREE_TYPE (lhs);
+-  /* Make sure that the types of the rhs and the lhs are the same
++  /* Make sure that the types of the rhs and the lhs are compatible
+      for scalar assignments.  We should probably have something
+      similar for aggregates, but right now removing that check just
+      breaks everything.  */
+-  gcc_checking_assert (t1 == t2
++  gcc_checking_assert (TYPE_MAIN_VARIANT (t1) == TYPE_MAIN_VARIANT (t2)
+ 		       || AGGREGATE_TYPE_P (TREE_TYPE (lhs)));
+ 
+   tmp = fold_build2_loc (loc, MODIFY_EXPR, void_type_node, lhs,
+Index: gcc/fortran/trans-types.c
+===================================================================
+--- a/src/gcc/fortran/trans-types.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/trans-types.c	(.../branches/gcc-6-branch)
+@@ -234,27 +234,42 @@
+   return -1;
+ }
+ 
+-/* Get the kind number corresponding to a real of given storage size,
+-   following the required return values for ISO_FORTRAN_ENV REAL* constants:
+-   -2 is returned if we support a kind of larger size, -1 otherwise.  */
++
++/* Get the kind number corresponding to a real of a given storage size.
++   If two real's have the same storage size, then choose the real with
++   the largest precision.  If a kind type is unavailable and a real
++   exists with wider storage, then return -2; otherwise, return -1.  */
++
+ int
+ gfc_get_real_kind_from_width_isofortranenv (int size)
+ {
+-  int i;
++  int digits, i, kind;
+ 
+   size /= 8;
+ 
++  kind = -1;
++  digits = 0;
++
+   /* Look for a kind with matching storage size.  */
+   for (i = 0; gfc_real_kinds[i].kind != 0; i++)
+     if (int_size_in_bytes (gfc_get_real_type (gfc_real_kinds[i].kind)) == size)
+-      return gfc_real_kinds[i].kind;
++      {
++	if (gfc_real_kinds[i].digits > digits)
++	  {
++	    digits = gfc_real_kinds[i].digits;
++	    kind = gfc_real_kinds[i].kind;
++	  }
++      }
+ 
++  if (kind != -1)
++    return kind;
++
+   /* Look for a kind with larger storage size.  */
+   for (i = 0; gfc_real_kinds[i].kind != 0; i++)
+     if (int_size_in_bytes (gfc_get_real_type (gfc_real_kinds[i].kind)) > size)
+-      return -2;
++      kind = -2;
+ 
+-  return -1;
++  return kind;
+ }
+ 
+ 
+Index: gcc/fortran/resolve.c
+===================================================================
+--- a/src/gcc/fortran/resolve.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/resolve.c	(.../branches/gcc-6-branch)
+@@ -8840,10 +8840,13 @@
+     return;
+ 
+   /* Check for EVENT WAIT the UNTIL_COUNT.  */
+-  if (code->op == EXEC_EVENT_WAIT && code->expr4
+-      && (code->expr4->ts.type != BT_INTEGER || code->expr4->rank != 0))
+-    gfc_error ("UNTIL_COUNT= argument at %L must be a scalar INTEGER "
+-	       "expression", &code->expr4->where);
++  if (code->op == EXEC_EVENT_WAIT && code->expr4)
++    {
++      if (!gfc_resolve_expr (code->expr4) || code->expr4->ts.type != BT_INTEGER
++	  || code->expr4->rank != 0)
++	gfc_error ("UNTIL_COUNT= argument at %L must be a scalar INTEGER "
++		   "expression", &code->expr4->where);
++    }
+ }
+ 
+ 
+Index: gcc/fortran/trans-decl.c
+===================================================================
+--- a/src/gcc/fortran/trans-decl.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/fortran/trans-decl.c	(.../branches/gcc-6-branch)
+@@ -887,6 +887,10 @@
+ 	  DECL_CONTEXT (token) = sym->ns->proc_name->backend_decl;
+ 	  gfc_module_add_decl (cur_module, token);
+ 	}
++      else if (sym->attr.host_assoc
++	       && TREE_CODE (DECL_CONTEXT (current_function_decl))
++	       != TRANSLATION_UNIT_DECL)
++	gfc_add_decl_to_parent_function (token);
+       else
+ 	gfc_add_decl_to_function (token);
+     }
+Index: gcc/function.c
+===================================================================
+--- a/src/gcc/function.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/function.c	(.../branches/gcc-6-branch)
+@@ -4800,9 +4800,9 @@
+ /* cfun should never be set directly; use this function.  */
+ 
+ void
+-set_cfun (struct function *new_cfun)
++set_cfun (struct function *new_cfun, bool force)
+ {
+-  if (cfun != new_cfun)
++  if (cfun != new_cfun || force)
+     {
+       cfun = new_cfun;
+       invoke_set_current_function_hook (new_cfun ? new_cfun->decl : NULL_TREE);
+Index: gcc/function.h
+===================================================================
+--- a/src/gcc/function.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/function.h	(.../branches/gcc-6-branch)
+@@ -606,7 +606,7 @@
+ extern void number_blocks (tree);
+ 
+ /* cfun shouldn't be set directly; use one of these functions instead.  */
+-extern void set_cfun (struct function *new_cfun);
++extern void set_cfun (struct function *new_cfun, bool force = false);
+ extern void push_cfun (struct function *new_cfun);
+ extern void pop_cfun (void);
+ 
+Index: gcc/tree-data-ref.c
+===================================================================
+--- a/src/gcc/tree-data-ref.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-data-ref.c	(.../branches/gcc-6-branch)
+@@ -2112,8 +2112,6 @@
+   switch (TREE_CODE (chrec))
+     {
+     case POLYNOMIAL_CHREC:
+-      gcc_assert (TREE_CODE (CHREC_RIGHT (chrec)) == INTEGER_CST);
+-
+       A[index][0] = mult * int_cst_value (CHREC_RIGHT (chrec));
+       return initialize_matrix_A (A, CHREC_LEFT (chrec), index + 1, mult);
+ 
+Index: gcc/gimplify.c
+===================================================================
+--- a/src/gcc/gimplify.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/gimplify.c	(.../branches/gcc-6-branch)
+@@ -8136,8 +8136,9 @@
+ 	  if ((ctx->region_type & ORT_TARGET) != 0
+ 	      && !(n->value & GOVD_SEEN)
+ 	      && GOMP_MAP_ALWAYS_P (OMP_CLAUSE_MAP_KIND (c)) == 0
+-	      && !lookup_attribute ("omp declare target link",
+-				    DECL_ATTRIBUTES (decl)))
++	      && (!is_global_var (decl)
++		  || !lookup_attribute ("omp declare target link",
++					DECL_ATTRIBUTES (decl))))
+ 	    {
+ 	      remove = true;
+ 	      /* For struct element mapping, if struct is never referenced
+@@ -11156,8 +11157,11 @@
+   if (fallback == fb_none && *expr_p && !is_gimple_stmt (*expr_p))
+     {
+       /* We aren't looking for a value, and we don't have a valid
+-	 statement.  If it doesn't have side-effects, throw it away.  */
+-      if (!TREE_SIDE_EFFECTS (*expr_p))
++	 statement.  If it doesn't have side-effects, throw it away.
++	 We can also get here with code such as "*&&L;", where L is
++	 a LABEL_DECL that is marked as FORCED_LABEL.  */
++      if (TREE_CODE (*expr_p) == LABEL_DECL
++	  || !TREE_SIDE_EFFECTS (*expr_p))
+ 	*expr_p = NULL;
+       else if (!TREE_THIS_VOLATILE (*expr_p))
+ 	{
+Index: gcc/graphite-scop-detection.c
+===================================================================
+--- a/src/gcc/graphite-scop-detection.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/graphite-scop-detection.c	(.../branches/gcc-6-branch)
+@@ -817,6 +817,25 @@
+ 	 != loop_depth (exit->dest->loop_father))
+     return invalid_sese;
+ 
++  /* For now we just bail out when there is a loop exit in the region
++     that is not also the exit of the region.  We could enlarge the
++     region to cover the loop that region exits to.  See PR79977.  */
++  if (loop_outer (entry->src->loop_father))
++    {
++      vec<edge> exits = get_loop_exit_edges (entry->src->loop_father);
++      for (unsigned i = 0; i < exits.length (); ++i)
++	{
++	  if (exits[i] != exit
++	      && bb_in_region (exits[i]->src, entry->dest, exit->src))
++	    {
++	      DEBUG_PRINT (dp << "[scop-detection-fail] cannot merge seses.\n");
++	      exits.release ();
++	      return invalid_sese;
++	    }
++	}
++      exits.release ();
++    }
++
+   /* For now we just want to bail out when exit does not post-dominate entry.
+      TODO: We might just add a basic_block at the exit to make exit
+      post-dominate entry (the entire region).  */
+@@ -905,7 +924,19 @@
+ 
+   sese_l combined = merge_sese (s1, s2);
+ 
++  /* Combining adjacent loops may add unrelated loops into the
++     region so we have to check all sub-loops of the outer loop
++     that are in the combined region.  */
+   if (combined)
++    for (l = loop_outer (loop)->inner; l; l = l->next)
++      if (bb_in_sese_p (l->header, combined)
++	  && ! loop_is_valid_in_scop (l, combined))
++	{
++	  combined = invalid_sese;
++	  break;
++	}
++
++  if (combined)
+     s1 = combined;
+   else
+     add_scop (s2);
+@@ -931,6 +962,8 @@
+     && niter_desc.control.no_overflow
+     && (niter = number_of_latch_executions (loop))
+     && !chrec_contains_undetermined (niter)
++    && !chrec_contains_undetermined (scalar_evolution_in_region (scop,
++								 loop, niter))
+     && graphite_can_represent_expr (scop, loop, niter);
+ }
+ 
+Index: gcc/calls.c
+===================================================================
+--- a/src/gcc/calls.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/calls.c	(.../branches/gcc-6-branch)
+@@ -2695,8 +2695,7 @@
+     n_named_args = num_actuals;
+ 
+   /* Make a vector to hold all the information about each arg.  */
+-  args = XALLOCAVEC (struct arg_data, num_actuals);
+-  memset (args, 0, num_actuals * sizeof (struct arg_data));
++  args = XCNEWVEC (struct arg_data, num_actuals);
+ 
+   /* Build up entries in the ARGS array, compute the size of the
+      arguments into ARGS_SIZE, etc.  */
+@@ -3710,6 +3709,7 @@
+   currently_expanding_call--;
+ 
+   free (stack_usage_map_buf);
++  free (args);
+ 
+   /* Join result with returned bounds so caller may use them if needed.  */
+   target = chkp_join_splitted_slot (target, valbnd);
+Index: gcc/ubsan.c
+===================================================================
+--- a/src/gcc/ubsan.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ubsan.c	(.../branches/gcc-6-branch)
+@@ -408,7 +408,9 @@
+ 	{
+ 	  pp_left_bracket (&pretty_name);
+ 	  tree dom = TYPE_DOMAIN (t);
+-	  if (dom && TREE_CODE (TYPE_MAX_VALUE (dom)) == INTEGER_CST)
++	  if (dom != NULL_TREE
++	      && TYPE_MAX_VALUE (dom) != NULL_TREE
++	      && TREE_CODE (TYPE_MAX_VALUE (dom)) == INTEGER_CST)
+ 	    {
+ 	      if (tree_fits_uhwi_p (TYPE_MAX_VALUE (dom))
+ 		  && tree_to_uhwi (TYPE_MAX_VALUE (dom)) + 1 != 0)
+@@ -1471,7 +1473,7 @@
+ 
+   expanded_location xloc = expand_location (loc);
+   if (xloc.file == NULL || strncmp (xloc.file, "\1", 2) == 0
+-      || xloc.file == '\0' || xloc.file[0] == '\xff'
++      || xloc.file[0] == '\0' || xloc.file[0] == '\xff'
+       || xloc.file[1] == '\xff')
+     return false;
+ 
+Index: gcc/lto/ChangeLog
+===================================================================
+--- a/src/gcc/lto/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/lto/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,12 @@
++2017-01-17  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-01-11  Jakub Jelinek  <jakub@redhat.com>
++
++	PR middle-end/50199
++	* lto-lang.c (lto_post_options): Force flag_merge_constants = 1
++	if it was 0.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/lto/lto-lang.c
+===================================================================
+--- a/src/gcc/lto/lto-lang.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/lto/lto-lang.c	(.../branches/gcc-6-branch)
+@@ -852,6 +852,12 @@
+      support.  */
+   flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+ 
++  /* When partitioning, we can tear appart STRING_CSTs uses from the same
++     TU into multiple partitions.  Without constant merging the constants
++     might not be equal at runtime.  See PR50199.  */
++  if (!flag_merge_constants)
++    flag_merge_constants = 1;
++
+   /* Initialize the compiler back end.  */
+   return false;
+ }
+Index: gcc/ipa-prop.c
+===================================================================
+--- a/src/gcc/ipa-prop.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ipa-prop.c	(.../branches/gcc-6-branch)
+@@ -4745,7 +4745,7 @@
+   lto_symtab_encoder_iterator lsei;
+   lto_symtab_encoder_t encoder;
+ 
+-  if (!ipa_node_params_sum)
++  if (!ipa_node_params_sum || !ipa_edge_args_vector)
+     return;
+ 
+   ob = create_output_block (LTO_section_jump_functions);
+Index: gcc/po/exgettext
+===================================================================
+--- a/src/gcc/po/exgettext	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/po/exgettext	(.../branches/gcc-6-branch)
+@@ -237,6 +237,8 @@
+     field = 0
+     while (getline < file) {
+ 	if (/^[ \t]*(;|$)/ || !/^[^ \t]/) {
++	    if (field > 2)
++		printf("_(\"%s\")\n", line)
+ 	    field = 0
+ 	} else {
+ 	    if ((field == 1) && /MissingArgError/) {
+@@ -275,12 +277,15 @@
+ 	    if (field == 2) {
+ 		line = $0
+ 		printf("#line %d \"%s\"\n", lineno, file)
+-		printf("_(\"%s\")\n", line)
++	    } else if (field > 2) {
++		line = line " " $0
+ 	    }
+ 	    field++;
+ 	}
+ 	lineno++;
+     }
++    if (field > 2)
++	printf("_(\"%s\")\n", line)
+   }') >> $emsg
+ 
+ # Run the xgettext commands, with temporary added as a file to scan.
+Index: gcc/po/es.po
+===================================================================
+--- a/src/gcc/po/es.po	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/po/es.po	(.../branches/gcc-6-branch)
+@@ -16,7 +16,7 @@
+ # demangled       - mutilado
+ # hardware        - hardware
+ # hotness         - calentura
+-# insns           - TBD
++# insns           - instrucciones  #: config/frv/frv.opt:126
+ # instruction     - instrucción
+ # iv optimization - optimización iv
+ # omp (OpenMP)    - omp
+@@ -36,7 +36,7 @@
+ "Project-Id-Version: gcc 6.2.0\n"
+ "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
+ "POT-Creation-Date: 2016-08-19 21:03+0000\n"
+-"PO-Revision-Date: 2016-12-15 01:25+0100\n"
++"PO-Revision-Date: 2016-12-31 09:29+0100\n"
+ "Last-Translator: Antonio Ceballos <aceballos@gmail.com>\n"
+ "Language-Team: Spanish <es@tp.org.es>\n"
+ "Language: es\n"
+@@ -11633,140 +11633,94 @@
+ msgstr "Usa instrucciones high de multiplicación para la parte high de la multiplicación 32x32."
+ 
+ #: config/microblaze/microblaze.opt:104
+-#, fuzzy
+-#| msgid "Use hardware floating point conversion instructions"
+ msgid "Use hardware floating point conversion instructions."
+ msgstr "Usa instrucciones de conversión de coma flotante de hardware."
+ 
+ #: config/microblaze/microblaze.opt:108
+-#, fuzzy
+-#| msgid "Use hardware floating point square root instruction"
+ msgid "Use hardware floating point square root instruction."
+ msgstr "Usa instrucciones de raíz cuadrada de coma flotante de hardware."
+ 
+ #: config/microblaze/microblaze.opt:112
+-#, fuzzy
+-#| msgid "Description for mxl-mode-executable"
+ msgid "Description for mxl-mode-executable."
+ msgstr "Descripción para mxl-mode-executable."
+ 
+ #: config/microblaze/microblaze.opt:116
+-#, fuzzy
+-#| msgid "Description for mxl-mode-xmdstub"
+ msgid "Description for mxl-mode-xmdstub."
+ msgstr "Descripción para mxl-mode-xmdstub."
+ 
+ #: config/microblaze/microblaze.opt:120
+-#, fuzzy
+-#| msgid "Description for mxl-mode-bootstrap"
+ msgid "Description for mxl-mode-bootstrap."
+ msgstr "Descripción para mxl-mode-bootstrap."
+ 
+ #: config/microblaze/microblaze.opt:124
+-#, fuzzy
+-#| msgid "Description for mxl-mode-novectors"
+ msgid "Description for mxl-mode-novectors."
+ msgstr "Descripción para mxl-mode-novectors."
+ 
+ #: config/microblaze/microblaze.opt:128
+-#, fuzzy
+-#| msgid "Use hardware quad FP instructions"
+ msgid "Use hardware prefetch instruction"
+-msgstr "Usa instrucciones de FP quad de hardware"
++msgstr "Usa instrucciones de precargado de hardware"
+ 
+ #: config/vax/vax.opt:23 config/vax/vax.opt:27
+-#, fuzzy
+-#| msgid "Target DFLOAT double precision code"
+ msgid "Target DFLOAT double precision code."
+ msgstr "Apunta a código DFLOAT de doble precisión."
+ 
+ #: config/vax/vax.opt:31 config/vax/vax.opt:35
+-#, fuzzy
+-#| msgid "Generate GFLOAT double precision code"
+ msgid "Generate GFLOAT double precision code."
+ msgstr "Genera código GFLOAT de doble precisión."
+ 
+ #: config/vax/vax.opt:39
+-#, fuzzy
+-#| msgid "Generate code for GNU assembler (gas)"
+ msgid "Generate code for GNU assembler (gas)."
+ msgstr "Genera código para el ensamblador de GNU (gas)."
+ 
+ #: config/vax/vax.opt:43
+-#, fuzzy
+-#| msgid "Generate code for UNIX assembler"
+ msgid "Generate code for UNIX assembler."
+ msgstr "Genera código para el ensamblador UNIX."
+ 
+ #: config/vax/vax.opt:47
+-#, fuzzy
+-#| msgid "Use VAXC structure conventions"
+ msgid "Use VAXC structure conventions."
+-msgstr "Usa convenciones de estructura VAXC."
++msgstr "Usa los convenios de estructura VAXC."
+ 
+ #: config/vax/vax.opt:51
+-#, fuzzy
+-#| msgid "Use new adddi3/subdi3 patterns"
+ msgid "Use new adddi3/subdi3 patterns."
+-msgstr "Usa patrones nuevos adddi3/subdi3."
++msgstr "Usa los patrones nuevos adddi3/subdi3."
+ 
+ #: config/frv/frv.opt:30
+-#, fuzzy
+-#| msgid "Use 4 media accumulators"
+ msgid "Use 4 media accumulators."
+ msgstr "Usa 4 acumuladores de medios."
+ 
+ #: config/frv/frv.opt:34
+-#, fuzzy
+-#| msgid "Use 8 media accumulators"
+ msgid "Use 8 media accumulators."
+ msgstr "Usa 8 acumuladores de medios."
+ 
+ #: config/frv/frv.opt:38
+-#, fuzzy
+-#| msgid "Enable label alignment optimizations"
+ msgid "Enable label alignment optimizations."
+ msgstr "Activa las optimizaciones de alineación de etiquetas."
+ 
+ #: config/frv/frv.opt:42
+-#, fuzzy
+-#| msgid "Dynamically allocate cc registers"
+ msgid "Dynamically allocate cc registers."
+ msgstr "Asigna dinámicamente los registros cc."
+ 
+ #: config/frv/frv.opt:49
+-#, fuzzy
+-#| msgid "Set the cost of branches"
+ msgid "Set the cost of branches."
+ msgstr "Establece el costo de las ramificaciones."
+ 
+ #: config/frv/frv.opt:53
+-#, fuzzy
+-#| msgid "Enable conditional execution other than moves/scc"
+ msgid "Enable conditional execution other than moves/scc."
+ msgstr "Activa la ejecución condicional en lugar de moves/scc."
+ 
+ #: config/frv/frv.opt:57
+-#, fuzzy
+-#| msgid "Change the maximum length of conditionally-executed sequences"
+ msgid "Change the maximum length of conditionally-executed sequences."
+ msgstr "Cambia la longitud máxima de las secuencias ejecutadas condicionalmente."
+ 
+ #: config/frv/frv.opt:61
+-#, fuzzy
+-#| msgid "Change the number of temporary registers that are available to conditionally-executed sequences"
+ msgid "Change the number of temporary registers that are available to conditionally-executed sequences."
+ msgstr "Cambia el número de registros temporales disponibles para secuencias ejecutadas condicionalmente."
+ 
+ #: config/frv/frv.opt:65
+-#, fuzzy
+-#| msgid "Enable conditional moves"
+ msgid "Enable conditional moves."
+ msgstr "Activa moves condicionales."
+ 
+ #: config/frv/frv.opt:69
+-#, fuzzy
+-#| msgid "Set the target CPU type"
+ msgid "Set the target CPU type."
+ msgstr "Especifica el tipo del CPU destino."
+ 
+@@ -11775,296 +11729,204 @@
+ msgstr "CPUs FR-V conocidos (para usar con la opción -mcpu=):"
+ 
+ #: config/frv/frv.opt:122
+-#, fuzzy
+-#| msgid "Use fp double instructions"
+ msgid "Use fp double instructions."
+ msgstr "Usa instrucciones fp double."
+ 
+ #: config/frv/frv.opt:126
+-#, fuzzy
+-#| msgid "Change the ABI to allow double word insns"
+ msgid "Change the ABI to allow double word insns."
+ msgstr "Cambia la ABI para permitir instrucciones double word."
+ 
+ #: config/frv/frv.opt:134
+-#, fuzzy
+-#| msgid "Just use icc0/fcc0"
+ msgid "Just use icc0/fcc0."
+ msgstr "Usa solamente icc0/fcc0."
+ 
+ #: config/frv/frv.opt:138
+-#, fuzzy
+-#| msgid "Only use 32 FPRs"
+ msgid "Only use 32 FPRs."
+ msgstr "Usa solamente 32 FPRs."
+ 
+ #: config/frv/frv.opt:142
+-#, fuzzy
+-#| msgid "Use 64 FPRs"
+ msgid "Use 64 FPRs."
+ msgstr "Usa 64 FPRs."
+ 
+ #: config/frv/frv.opt:146
+-#, fuzzy
+-#| msgid "Only use 32 GPRs"
+ msgid "Only use 32 GPRs."
+ msgstr "Usa solamente 32 GPRs."
+ 
+ #: config/frv/frv.opt:150
+-#, fuzzy
+-#| msgid "Use 64 GPRs"
+ msgid "Use 64 GPRs."
+ msgstr "Usa 64 GPRs."
+ 
+ #: config/frv/frv.opt:154
+-#, fuzzy
+-#| msgid "Enable use of GPREL for read-only data in FDPIC"
+ msgid "Enable use of GPREL for read-only data in FDPIC."
+ msgstr "Activa el uso de GPREL para datos de sólo lectura en FDPIC."
+ 
+ #: config/frv/frv.opt:166
+-#, fuzzy
+-#| msgid "Enable PIC support for building libraries"
+ msgid "Enable PIC support for building libraries."
+ msgstr "Activa el soporte PIC para construir bibliotecas."
+ 
+ #: config/frv/frv.opt:170
+-#, fuzzy
+-#| msgid "Follow the EABI linkage requirements"
+ msgid "Follow the EABI linkage requirements."
+ msgstr "Sigue los requerimientos de enlace de EABI."
+ 
+ #: config/frv/frv.opt:174
+-#, fuzzy
+-#| msgid "Disallow direct calls to global functions"
+ msgid "Disallow direct calls to global functions."
+-msgstr "Desactiva las llamdas directas a funciones globales."
++msgstr "Desactiva las llamadas directas a funciones globales."
+ 
+ #: config/frv/frv.opt:178
+-#, fuzzy
+-#| msgid "Use media instructions"
+ msgid "Use media instructions."
+ msgstr "Usa instrucciones de medios."
+ 
+ #: config/frv/frv.opt:182
+-#, fuzzy
+-#| msgid "Use multiply add/subtract instructions"
+ msgid "Use multiply add/subtract instructions."
+ msgstr "Usa instrucciones acumular/sustraer de multiplicar."
+ 
+ #: config/frv/frv.opt:186
+-#, fuzzy
+-#| msgid "Enable optimizing &&/|| in conditional execution"
+ msgid "Enable optimizing &&/|| in conditional execution."
+ msgstr "Activa la optimización &&/|| en la ejecución condicional."
+ 
+ #: config/frv/frv.opt:190
+-#, fuzzy
+-#| msgid "Enable nested conditional execution optimizations"
+ msgid "Enable nested conditional execution optimizations."
+ msgstr "Activa las optimizaciones de ejecución condicional anidada."
+ 
+ #: config/frv/frv.opt:195
+-#, fuzzy
+-#| msgid "Do not mark ABI switches in e_flags"
+ msgid "Do not mark ABI switches in e_flags."
+ msgstr "No marca las opciones ABI en e_flags."
+ 
+ #: config/frv/frv.opt:199
+-#, fuzzy
+-#| msgid "Remove redundant membars"
+ msgid "Remove redundant membars."
+ msgstr "Remueve miembros redundantes."
+ 
+ #: config/frv/frv.opt:203
+-#, fuzzy
+-#| msgid "Pack VLIW instructions"
+ msgid "Pack VLIW instructions."
+ msgstr "Empaca las instrucciones VLIW."
+ 
+ #: config/frv/frv.opt:207
+-#, fuzzy
+-#| msgid "Enable setting GPRs to the result of comparisons"
+ msgid "Enable setting GPRs to the result of comparisons."
+ msgstr "Permite establecer los GPRs al resultado de las comparaciones."
+ 
+ #: config/frv/frv.opt:211
+-#, fuzzy
+-#| msgid "Change the amount of scheduler lookahead"
+ msgid "Change the amount of scheduler lookahead."
+ msgstr "Cambia la cantidad de vista hacia adelante del planificador."
+ 
+ #: config/frv/frv.opt:219
+-#, fuzzy
+-#| msgid "Assume a large TLS segment"
+ msgid "Assume a large TLS segment."
+ msgstr "Asume un segmento TLS grande."
+ 
+ #: config/frv/frv.opt:223
+-#, fuzzy
+-#| msgid "Do not assume a large TLS segment"
+ msgid "Do not assume a large TLS segment."
+ msgstr "No asume un segmento TLS grande."
+ 
+ #: config/frv/frv.opt:228
+-#, fuzzy
+-#| msgid "Cause gas to print tomcat statistics"
+ msgid "Cause gas to print tomcat statistics."
+ msgstr "Causa que gas muestre estadísticas de tomcat."
+ 
+ #: config/frv/frv.opt:233
+-#, fuzzy
+-#| msgid "Link with the library-pic libraries"
+ msgid "Link with the library-pic libraries."
+ msgstr "Enlaza con las bibliotecas de pic de biblioteca."
+ 
+ #: config/frv/frv.opt:237
+-#, fuzzy
+-#| msgid "Allow branches to be packed with other instructions"
+ msgid "Allow branches to be packed with other instructions."
+ msgstr "Permite que las ramificaciones se empaquen con otras instrucciones."
+ 
+ #: config/mn10300/mn10300.opt:30
+-#, fuzzy
+-#| msgid "Target the AM33 processor"
+ msgid "Target the AM33 processor."
+ msgstr "Apunta al procesador AM33."
+ 
+ #: config/mn10300/mn10300.opt:34
+-#, fuzzy
+-#| msgid "Target the AM33/2.0 processor"
+ msgid "Target the AM33/2.0 processor."
+ msgstr "Apunta al procesador AM33/2.0."
+ 
+ #: config/mn10300/mn10300.opt:38
+-#, fuzzy
+-#| msgid "Target the AM34 processor"
+ msgid "Target the AM34 processor."
+ msgstr "Apunta al procesador AM34."
+ 
+ #: config/mn10300/mn10300.opt:46
+-#, fuzzy
+-#| msgid "Work around hardware multiply bug"
+ msgid "Work around hardware multiply bug."
+ msgstr "Evita el error de multiplicación de hardware."
+ 
+ #: config/mn10300/mn10300.opt:55
+-#, fuzzy
+-#| msgid "Enable linker relaxations"
+ msgid "Enable linker relaxations."
+ msgstr "Activa la relajación del enlazador."
+ 
+ #: config/mn10300/mn10300.opt:59
+-#, fuzzy
+-#| msgid "Return pointers in both a0 and d0"
+ msgid "Return pointers in both a0 and d0."
+ msgstr "Devuelve punteros tanto en a0 como en d0."
+ 
+ #: config/mn10300/mn10300.opt:63
+-#, fuzzy
+-#| msgid "Allow gcc to generate LIW instructions"
+ msgid "Allow gcc to generate LIW instructions."
+ msgstr "Permite a gcc generar instrucciones LIW."
+ 
+ #: config/mn10300/mn10300.opt:67
+-#, fuzzy
+-#| msgid "Allow gcc to generate the SETLB and Lcc instructions"
+ msgid "Allow gcc to generate the SETLB and Lcc instructions."
+ msgstr "Permite a gcc generar las instrucciones SETLB y Lcc."
+ 
+ #: config/nds32/nds32.opt:26
+-#, fuzzy
+-#| msgid "Generate code in big endian mode"
+ msgid "Generate code in big-endian mode."
+ msgstr "Genera código en modo big endian."
+ 
+ #: config/nds32/nds32.opt:30
+-#, fuzzy
+-#| msgid "Generate code in little endian mode"
+ msgid "Generate code in little-endian mode."
+ msgstr "Genera código en modo little endian."
+ 
+ #: config/nds32/nds32.opt:34
+-#, fuzzy
+-#| msgid "Reschedule instructions before register allocation"
+ msgid "Use reduced-set registers for register allocation."
+-msgstr "Recalendariza las instrucciones antes del alojamiento de registros."
++msgstr "Usa un juego reducido de registros para asignación de registros."
+ 
+ #: config/nds32/nds32.opt:38
+-#, fuzzy
+-#| msgid "Reschedule instructions before register allocation"
+ msgid "Use full-set registers for register allocation."
+-msgstr "Recalendariza las instrucciones antes del alojamiento de registros."
++msgstr "Usa el juego completo de registros para asignación de registros."
+ 
+ #: config/nds32/nds32.opt:42
+-#, fuzzy
+-#| msgid "enable conditional move instruction usage."
+ msgid "Generate conditional move instructions."
+-msgstr "activa el uso de la instrucción move condicional."
++msgstr "Genera instrucciones move condicionales."
+ 
+ #: config/nds32/nds32.opt:46
+-#, fuzzy
+-#| msgid "Generate bit instructions"
+ msgid "Generate performance extension instructions."
+-msgstr "Genera instrucciones bit."
++msgstr "Genera instrucciones de extensión del rendimiento."
+ 
+ #: config/nds32/nds32.opt:50
+-#, fuzzy
+-#| msgid "Generate isel instructions"
+ msgid "Generate v3 push25/pop25 instructions."
+-msgstr "Genera instrucciones isel."
++msgstr "Genera instrucciones v3 push25/pop25."
+ 
+ #: config/nds32/nds32.opt:54
+-#, fuzzy
+-#| msgid "Generate bit instructions"
+ msgid "Generate 16-bit instructions."
+-msgstr "Genera instrucciones bit."
++msgstr "Genera instrucciones de 16 bits."
+ 
+ #: config/nds32/nds32.opt:58
+ msgid "Specify the size of each interrupt vector, which must be 4 or 16."
+-msgstr ""
++msgstr "Especifica el tamaño de cada vector de interrupciones, que ha de ser 4 o 16."
+ 
+ #: config/nds32/nds32.opt:62
+ msgid "Specify the size of each cache block, which must be a power of 2 between 4 and 512."
+-msgstr ""
++msgstr "Especifica el tamaño de cada bloque de caché, que ha de ser potencia de 2 entre 4 y 512."
+ 
+ #: config/nds32/nds32.opt:70
+-#, fuzzy
+-#| msgid "Known ARM architectures (for use with the -march= option):"
+ msgid "Known arch types (for use with the -march= option):"
+-msgstr "Arquitecturas ARM conocidas (para usar con la opción -march=):"
++msgstr "Tipos de arquitectura conocidos (para usar con la opción -march=):"
+ 
+ #: config/nds32/nds32.opt:83
+ msgid "Specify the address generation strategy for code model."
+-msgstr ""
++msgstr "Especifica la estrategia de generación de direcciones para modelo de código."
+ 
+ #: config/nds32/nds32.opt:87
+-#, fuzzy
+-#| msgid "Known code models (for use with the -mcmodel= option):"
+ msgid "Known cmodel types (for use with the -mcmodel= option):"
+-msgstr "Modelos de código conocidos (para uso con la opción -mcmodel=):"
++msgstr "Tipos de modelos de código conocidos (para uso con la opción -mcmodel=):"
+ 
+ #: config/nds32/nds32.opt:100
+-#, fuzzy
+-#| msgid "Warn when all constructors and destructors are private"
+ msgid "Enable constructor/destructor feature."
+-msgstr "Avisa cuando todos los constructores y destructores son privados."
++msgstr "Activa la opción constructor/destructor."
+ 
+ #: config/nds32/nds32.opt:104
+-#, fuzzy
+-#| msgid "Generate isel instructions"
+ msgid "Guide linker to relax instructions."
+-msgstr "Genera instrucciones isel."
++msgstr "Guía al enlazador para que relaje las instrucciones."
+ 
+ #: config/iq2000/iq2000.opt:31
+-#, fuzzy
+-#| msgid "Specify CPU for code generation purposes"
+ msgid "Specify CPU for code generation purposes."
+-msgstr "Especifica el CPU para propósitos de generación de código."
++msgstr "Especifica la CPU para propósitos de generación de código."
+ 
+ #: config/iq2000/iq2000.opt:47
+ msgid "Specify CPU for scheduling purposes."
+-msgstr "Especifica el CPU para propósitos de planificación."
++msgstr "Especifica la CPU para propósitos de planificación."
+ 
+ #: config/iq2000/iq2000.opt:51
+ msgid "Known IQ2000 CPUs (for use with the -mcpu= option):"
+@@ -12071,20 +11933,14 @@
+ msgstr "CPUs IQ2000 conocidos (para uso con la opción -mcpu=):"
+ 
+ #: config/iq2000/iq2000.opt:61 config/mips/mips.opt:142
+-#, fuzzy
+-#| msgid "Use ROM instead of RAM"
+ msgid "Use ROM instead of RAM."
+ msgstr "Usa la ROM en lugar de la RAM."
+ 
+ #: config/iq2000/iq2000.opt:70
+-#, fuzzy
+-#| msgid "No default crt0.o"
+ msgid "No default crt0.o."
+-msgstr "No define a crt0.o por defecto."
++msgstr "Sin crt0.o predeterminada."
+ 
+ #: config/iq2000/iq2000.opt:74 config/mips/mips.opt:393
+-#, fuzzy
+-#| msgid "Put uninitialized constants in ROM (needs -membedded-data)"
+ msgid "Put uninitialized constants in ROM (needs -membedded-data)."
+ msgstr "Pone las constantes sin inicializar en ROM (necesita -membedded-data)."
+ 
+@@ -12093,136 +11949,96 @@
+ msgstr "ISAs C6X conocidas (para uso con la opción -march=):"
+ 
+ #: config/c6x/c6x.opt:46
+-#, fuzzy
+-#| msgid "Valid arguments for the -msdata= option"
+ msgid "Valid arguments for the -msdata= option."
+ msgstr "Argumentos válidos para la opción -msdata=."
+ 
+ #: config/c6x/c6x.opt:59
+-#, fuzzy
+-#| msgid "Compile for the DSBT shared library ABI"
+ msgid "Compile for the DSBT shared library ABI."
+ msgstr "Compila para la ABI de biblioteca compartida DSBT."
+ 
+ #: config/cris/linux.opt:27
+-#, fuzzy
+-#| msgid "Together with -fpic and -fPIC, do not use GOTPLT references"
+ msgid "Together with -fpic and -fPIC, do not use GOTPLT references."
+ msgstr "Junto con -fpic y -fPIC, no utiliza referencias GOTPLT."
+ 
+ #: config/cris/cris.opt:45
+-#, fuzzy
+-#| msgid "Work around bug in multiplication instruction"
+ msgid "Work around bug in multiplication instruction."
+ msgstr "Evita el error en la instrucción de multiplicación."
+ 
+ #: config/cris/cris.opt:51
+-#, fuzzy
+-#| msgid "Compile for ETRAX 4 (CRIS v3)"
+ msgid "Compile for ETRAX 4 (CRIS v3)."
+ msgstr "Compila para ETRAX 4 (CRIS v3)."
+ 
+ #: config/cris/cris.opt:56
+-#, fuzzy
+-#| msgid "Compile for ETRAX 100 (CRIS v8)"
+ msgid "Compile for ETRAX 100 (CRIS v8)."
+ msgstr "Compila para ETRAX 100 (CRIS v8)."
+ 
+ #: config/cris/cris.opt:64
+-#, fuzzy
+-#| msgid "Emit verbose debug information in assembly code"
+ msgid "Emit verbose debug information in assembly code."
+ msgstr "Emite información de depuración detallada en el código ensamblador."
+ 
+ #: config/cris/cris.opt:71
+-#, fuzzy
+-#| msgid "Do not use condition codes from normal instructions"
+ msgid "Do not use condition codes from normal instructions."
+ msgstr "No usa códigos de condición para las instrucciones normales."
+ 
+ #: config/cris/cris.opt:80
+-#, fuzzy
+-#| msgid "Do not emit addressing modes with side-effect assignment"
+ msgid "Do not emit addressing modes with side-effect assignment."
+ msgstr "No emite modos de direccionamiento con asignaciones colaterales."
+ 
+ #: config/cris/cris.opt:89
+-#, fuzzy
+-#| msgid "Do not tune stack alignment"
+ msgid "Do not tune stack alignment."
+ msgstr "No ajusta la alineación de la pila."
+ 
+ #: config/cris/cris.opt:98
+-#, fuzzy
+-#| msgid "Do not tune writable data alignment"
+ msgid "Do not tune writable data alignment."
+ msgstr "No ajusta la alineación de los datos modificables."
+ 
+ #: config/cris/cris.opt:107
+-#, fuzzy
+-#| msgid "Do not tune code and read-only data alignment"
+ msgid "Do not tune code and read-only data alignment."
+ msgstr "No ajusta la alineación del código y de datos de sólo lectura."
+ 
+ #: config/cris/cris.opt:116
+-#, fuzzy
+-#| msgid "Align code and data to 32 bits"
+ msgid "Align code and data to 32 bits."
+ msgstr "Alinea código y datos a 32 bits."
+ 
+ #: config/cris/cris.opt:133
+-#, fuzzy
+-#| msgid "Don't align items in code or data"
+ msgid "Don't align items in code or data."
+ msgstr "No alinea los elementos en el código o los datos."
+ 
+ #: config/cris/cris.opt:142
+-#, fuzzy
+-#| msgid "Do not emit function prologue or epilogue"
+ msgid "Do not emit function prologue or epilogue."
+ msgstr "No emite el prólogo o epílogo de funciones."
+ 
+ #: config/cris/cris.opt:149
+-#, fuzzy
+-#| msgid "Use the most feature-enabling options allowed by other options"
+ msgid "Use the most feature-enabling options allowed by other options."
+ msgstr "Usa la mayor cantidad de características permitidas por otras opciones."
+ 
+ #: config/cris/cris.opt:158
+-#, fuzzy
+-#| msgid "Override -mbest-lib-options"
+ msgid "Override -mbest-lib-options."
+ msgstr "Anula -mbest-lib-options."
+ 
+ #: config/cris/cris.opt:165
+-#, fuzzy
+-#| msgid "-march=ARCH\tGenerate code for the specified chip or CPU version"
+ msgid "-march=ARCH\tGenerate code for the specified chip or CPU version."
+ msgstr "-march=ARQ\tGenera código para el chip o la versión de CPU especificados."
+ 
+ #: config/cris/cris.opt:169
+-#, fuzzy
+-#| msgid "-mtune=ARCH\tTune alignment for the specified chip or CPU version"
+ msgid "-mtune=ARCH\tTune alignment for the specified chip or CPU version."
+ msgstr "-mtune=ARQ\tAjusta la alineación para el chip o la versión de CPU especificados."
+ 
+ #: config/cris/cris.opt:173
+-#, fuzzy
+-#| msgid "-mmax-stackframe=SIZE\tWarn when a stackframe is larger than the specified size"
+ msgid "-mmax-stackframe=SIZE\tWarn when a stackframe is larger than the specified size."
+ msgstr "-mmax-stackframe=TAM\tAvisa cuando un marco de pila es más grande que el tamaño especificado."
+ 
+ #: config/cris/cris.opt:180
+ msgid "Emit traps as \"break 8\", default for CRIS v3 and up.  If disabled, calls to abort() are used."
+-msgstr ""
++msgstr "Emite traps como \"break 8\", predeterminado para CRIS v3 y superior.  Si está desactivado, se usan llamadas a abort()."
+ 
+ #: config/cris/cris.opt:184
+ msgid "Emit checks causing \"break 8\" instructions to execute when applying atomic builtins on misaligned memory."
+-msgstr ""
++msgstr "Emite comprobaciones haciendo que las instrucciones \"break 8\" se ejecuten cuando se aplican funciones internas atómicas sobre memoria desalineada."
+ 
+ #: config/cris/cris.opt:188
+ msgid "Handle atomic builtins that may be applied to unaligned data by calling library functions. Overrides -mtrap-unaligned-atomic."
+-msgstr ""
++msgstr "Maneja las funciones internas atómicas que pueden aplicarse a datos desalineados mediante llamadas a funciones de biblioteca. Anula -mtrap-unaligned-atomic."
+ 
+ #: config/sh/superh.opt:6
+ msgid "Board name [and memory region]."
+@@ -12233,116 +12049,78 @@
+ msgstr "Nombre del entorno de ejecución."
+ 
+ #: config/sh/sh.opt:48
+-#, fuzzy
+-#| msgid "Generate SH1 code"
+ msgid "Generate SH1 code."
+ msgstr "Genera código SH1."
+ 
+ #: config/sh/sh.opt:52
+-#, fuzzy
+-#| msgid "Generate SH2 code"
+ msgid "Generate SH2 code."
+ msgstr "Genera código SH2."
+ 
+ #: config/sh/sh.opt:56
+-#, fuzzy
+-#| msgid "Generate default double-precision SH2a-FPU code"
+ msgid "Generate default double-precision SH2a-FPU code."
+ msgstr "Genera código FPU de SH2a de doble precisión por defecto."
+ 
+ #: config/sh/sh.opt:60
+-#, fuzzy
+-#| msgid "Generate SH2a FPU-less code"
+ msgid "Generate SH2a FPU-less code."
+ msgstr "Genera código SH2a sin FPU."
+ 
+ #: config/sh/sh.opt:64
+-#, fuzzy
+-#| msgid "Generate default single-precision SH2a-FPU code"
+ msgid "Generate default single-precision SH2a-FPU code."
+ msgstr "Genera código FPU de SH2a de precisión simple."
+ 
+ #: config/sh/sh.opt:68
+-#, fuzzy
+-#| msgid "Generate only single-precision SH2a-FPU code"
+ msgid "Generate only single-precision SH2a-FPU code."
+ msgstr "Genera solamente código FPU de SH2a de precisión simple."
+ 
+ #: config/sh/sh.opt:72
+-#, fuzzy
+-#| msgid "Generate SH2e code"
+ msgid "Generate SH2e code."
+ msgstr "Genera código SH2e."
+ 
+ #: config/sh/sh.opt:76
+-#, fuzzy
+-#| msgid "Generate SH3 code"
+ msgid "Generate SH3 code."
+ msgstr "Genera código SH3."
+ 
+ #: config/sh/sh.opt:80
+-#, fuzzy
+-#| msgid "Generate SH3e code"
+ msgid "Generate SH3e code."
+ msgstr "Genera código SH3e."
+ 
+ #: config/sh/sh.opt:84
+-#, fuzzy
+-#| msgid "Generate SH4 code"
+ msgid "Generate SH4 code."
+ msgstr "Genera código SH4."
+ 
+ #: config/sh/sh.opt:88
+-#, fuzzy
+-#| msgid "Generate SH4-100 code"
+ msgid "Generate SH4-100 code."
+ msgstr "Genera código SH4-100."
+ 
+ #: config/sh/sh.opt:92
+-#, fuzzy
+-#| msgid "Generate SH4-200 code"
+ msgid "Generate SH4-200 code."
+ msgstr "Genera código SH4-200."
+ 
+ #: config/sh/sh.opt:98
+-#, fuzzy
+-#| msgid "Generate SH4-300 code"
+ msgid "Generate SH4-300 code."
+ msgstr "Genera código SH4-300."
+ 
+ #: config/sh/sh.opt:102
+-#, fuzzy
+-#| msgid "Generate SH4 FPU-less code"
+ msgid "Generate SH4 FPU-less code."
+ msgstr "Genera código SH4 sin FPU."
+ 
+ #: config/sh/sh.opt:106
+-#, fuzzy
+-#| msgid "Generate SH4-100 FPU-less code"
+ msgid "Generate SH4-100 FPU-less code."
+ msgstr "Genera código SH4-100 sin FPU."
+ 
+ #: config/sh/sh.opt:110
+-#, fuzzy
+-#| msgid "Generate SH4-200 FPU-less code"
+ msgid "Generate SH4-200 FPU-less code."
+ msgstr "Genera código SH4-200 sin FPU."
+ 
+ #: config/sh/sh.opt:114
+-#, fuzzy
+-#| msgid "Generate SH4-300 FPU-less code"
+ msgid "Generate SH4-300 FPU-less code."
+ msgstr "Genera código SH4-300 sin FPU."
+ 
+ #: config/sh/sh.opt:118
+-#, fuzzy
+-#| msgid "Generate code for SH4 340 series (MMU/FPU-less)"
+ msgid "Generate code for SH4 340 series (MMU/FPU-less)."
+ msgstr "Genera código para SH4 series 340 (sin MMU/FPU)."
+ 
+ #: config/sh/sh.opt:123
+-#, fuzzy
+-#| msgid "Generate code for SH4 400 series (MMU/FPU-less)"
+ msgid "Generate code for SH4 400 series (MMU/FPU-less)."
+ msgstr "Genera código para SH4 series 400 (sin MMU/FPU)."
+ 
+@@ -12351,156 +12129,107 @@
+ msgstr "Genera código para SH4 series 500 (sin FPU)."
+ 
+ #: config/sh/sh.opt:133
+-#, fuzzy
+-#| msgid "Generate default single-precision SH4 code"
+ msgid "Generate default single-precision SH4 code."
+ msgstr "Genera código SH4 de precisión simple por defecto."
+ 
+ #: config/sh/sh.opt:137
+-#, fuzzy
+-#| msgid "Generate default single-precision SH4-100 code"
+ msgid "Generate default single-precision SH4-100 code."
+ msgstr "Genera código SH4-100 de precisión simple por defecto."
+ 
+ #: config/sh/sh.opt:141
+-#, fuzzy
+-#| msgid "Generate default single-precision SH4-200 code"
+ msgid "Generate default single-precision SH4-200 code."
+ msgstr "Genera código SH4-200 de precisión simple por defecto."
+ 
+ #: config/sh/sh.opt:145
+-#, fuzzy
+-#| msgid "Generate default single-precision SH4-300 code"
+ msgid "Generate default single-precision SH4-300 code."
+ msgstr "Genera código SH4-300 de precisión simple por defecto."
+ 
+ #: config/sh/sh.opt:149
+-#, fuzzy
+-#| msgid "Generate only single-precision SH4 code"
+ msgid "Generate only single-precision SH4 code."
+ msgstr "Genera código SH4 solamente de precisión simple."
+ 
+ #: config/sh/sh.opt:153
+-#, fuzzy
+-#| msgid "Generate only single-precision SH4-100 code"
+ msgid "Generate only single-precision SH4-100 code."
+ msgstr "Genera código SH4-100 solamente de precisión simple."
+ 
+ #: config/sh/sh.opt:157
+-#, fuzzy
+-#| msgid "Generate only single-precision SH4-200 code"
+ msgid "Generate only single-precision SH4-200 code."
+ msgstr "Genera código SH4-200 solamente de precisión simple."
+ 
+ #: config/sh/sh.opt:161
+-#, fuzzy
+-#| msgid "Generate only single-precision SH4-300 code"
+ msgid "Generate only single-precision SH4-300 code."
+ msgstr "Genera código SH4-300 solamente de precisión simple."
+ 
+ #: config/sh/sh.opt:165
+-#, fuzzy
+-#| msgid "Generate SH4a code"
+ msgid "Generate SH4a code."
+ msgstr "Genera código SH4a."
+ 
+ #: config/sh/sh.opt:169
+-#, fuzzy
+-#| msgid "Generate SH4a FPU-less code"
+ msgid "Generate SH4a FPU-less code."
+ msgstr "Genera código SH4a sin FPU."
+ 
+ #: config/sh/sh.opt:173
+-#, fuzzy
+-#| msgid "Generate default single-precision SH4a code"
+ msgid "Generate default single-precision SH4a code."
+ msgstr "Genera código SH4a de precisión simple por defecto."
+ 
+ #: config/sh/sh.opt:177
+-#, fuzzy
+-#| msgid "Generate only single-precision SH4a code"
+ msgid "Generate only single-precision SH4a code."
+ msgstr "Genera código SH4a solamente de precisión simple."
+ 
+ #: config/sh/sh.opt:181
+-#, fuzzy
+-#| msgid "Generate SH4al-dsp code"
+ msgid "Generate SH4al-dsp code."
+ msgstr "Genera código SH4al-dsp."
+ 
+ #: config/sh/sh.opt:185
+-#, fuzzy
+-#| msgid "Generate 32-bit SHmedia code"
+ msgid "Generate 32-bit SHmedia code."
+ msgstr "Genera código SHmedia de 32-bit."
+ 
+ #: config/sh/sh.opt:189
+-#, fuzzy
+-#| msgid "Generate 32-bit FPU-less SHmedia code"
+ msgid "Generate 32-bit FPU-less SHmedia code."
+ msgstr "Genera código SHmedia de 32-bit sin FPU."
+ 
+ #: config/sh/sh.opt:193
+-#, fuzzy
+-#| msgid "Generate 64-bit SHmedia code"
+ msgid "Generate 64-bit SHmedia code."
+ msgstr "Genera código SHmedia de 64-bit."
+ 
+ #: config/sh/sh.opt:197
+-#, fuzzy
+-#| msgid "Generate 64-bit FPU-less SHmedia code"
+ msgid "Generate 64-bit FPU-less SHmedia code."
+ msgstr "Genera código SHmedia de 64-bit sin FPU."
+ 
+ #: config/sh/sh.opt:201
+-#, fuzzy
+-#| msgid "Generate SHcompact code"
+ msgid "Generate SHcompact code."
+ msgstr "Genera código SHcompact."
+ 
+ #: config/sh/sh.opt:205
+-#, fuzzy
+-#| msgid "Generate FPU-less SHcompact code"
+ msgid "Generate FPU-less SHcompact code."
+ msgstr "Genera código SHcompact sin FPU."
+ 
+ #: config/sh/sh.opt:217
+-#, fuzzy
+-#| msgid "Generate code in big endian mode"
+ msgid "Generate code in big endian mode."
+ msgstr "Genera código en modo big endian."
+ 
+ #: config/sh/sh.opt:221
+-#, fuzzy
+-#| msgid "Generate 32-bit offsets in switch tables"
+ msgid "Generate 32-bit offsets in switch tables."
+ msgstr "Genera desplazamientos de 32-bit en las tablas de switch."
+ 
+ #: config/sh/sh.opt:225
+-#, fuzzy
+-#| msgid "Generate bit instructions"
+ msgid "Generate bit instructions."
+-msgstr "Genera instrucciones bit."
++msgstr "Genera instrucciones de bit."
+ 
+ #: config/sh/sh.opt:229
+-#, fuzzy
+-#| msgid "Cost to assume for a branch insn"
+ msgid "Cost to assume for a branch insn."
+ msgstr "Costo de asumir una ramificación de insn."
+ 
+ #: config/sh/sh.opt:233
+ msgid "Assume that zero displacement conditional branches are fast."
+-msgstr ""
++msgstr "Asume que las ramificaciones condicionales con desplazamiento cero son rápidas."
+ 
+ #: config/sh/sh.opt:236 config/sh/sh.opt:240
+-#, fuzzy, c-format
+-#| msgid "Deprecated.  This switch has no effect"
++#, c-format
+ msgid "%qs is deprecated and has no effect"
+-msgstr "Obsoleto.  Esta opción no tiene efecto"
++msgstr "%qs está obsoleto y no tiene ningún efecto"
+ 
+ #: config/sh/sh.opt:237
+-#, fuzzy
+-#| msgid "Enable cbranchdi4 pattern"
+ msgid "Enable cbranchdi4 pattern."
+ msgstr "Activa el patrón cbranchdi4."
+ 
+@@ -12510,37 +12239,27 @@
+ 
+ #: config/sh/sh.opt:245
+ msgid "Force the usage of delay slots for conditional branches."
+-msgstr ""
++msgstr "Fuerza el uso de ranuras de retardo para las ramificaciones condicionales."
+ 
+ #: config/sh/sh.opt:249
+-#, fuzzy
+-#| msgid "Enable SH5 cut2 workaround"
+ msgid "Enable SH5 cut2 workaround."
+ msgstr "Permite evitar cut2 en SH5."
+ 
+ #: config/sh/sh.opt:253
+-#, fuzzy
+-#| msgid "Align doubles at 64-bit boundaries"
+ msgid "Align doubles at 64-bit boundaries."
+ msgstr "Alinea doubles en límites de 64-bit."
+ 
+ #: config/sh/sh.opt:257
+-#, fuzzy
+-#| msgid "Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table"
+ msgid "Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table."
+-msgstr "Estrategia de división, uno de: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table."
++msgstr "Estrategia de división, una de las siguientes: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table."
+ 
+ #: config/sh/sh.opt:261
+-#, fuzzy
+-#| msgid "Specify name for 32 bit signed division function"
+ msgid "Specify name for 32 bit signed division function."
+ msgstr "Especifica un nombre para la función de división de 32 bit con signo."
+ 
+ #: config/sh/sh.opt:265
+-#, fuzzy
+-#| msgid "Generate LP64 code"
+ msgid "Generate ELF FDPIC code."
+-msgstr "Genera código LP64."
++msgstr "Genera código ELF FDPIC."
+ 
+ #: config/sh/sh.opt:269
+ msgid "Enable the use of 64-bit floating point registers in fmov instructions.  See -mdalign if 64-bit alignment is required."
+@@ -12547,68 +12266,46 @@
+ msgstr "Activa el uso de registros de coma flotante de 64-bit en instrucciones. fmov.  Vea -mdalign si se requiere alineación de 64-bit."
+ 
+ #: config/sh/sh.opt:277
+-#, fuzzy
+-#| msgid "Cost to assume for gettr insn"
+ msgid "Cost to assume for gettr insn."
+ msgstr "Costo de asumir la instrucción gettr."
+ 
+ #: config/sh/sh.opt:281 config/sh/sh.opt:331
+-#, fuzzy
+-#| msgid "Follow Renesas (formerly Hitachi) / SuperH calling conventions"
+ msgid "Follow Renesas (formerly Hitachi) / SuperH calling conventions."
+ msgstr "Sigue las convenciones de llamada Renesas (anteriormente Hitachi) / SuperH."
+ 
+ #: config/sh/sh.opt:285
+-#, fuzzy
+-#| msgid "Increase the IEEE compliance for floating-point comparisons"
+ msgid "Increase the IEEE compliance for floating-point comparisons."
+ msgstr "Incrementa el cumplimiento con IEEE para las comparaciones de coma flotante."
+ 
+ #: config/sh/sh.opt:289
+-#, fuzzy
+-#| msgid "Enable the use of the indexed addressing mode for SHmedia32/SHcompact"
+ msgid "Enable the use of the indexed addressing mode for SHmedia32/SHcompact."
+-msgstr "Permite el uso del modo de direccionamiento indizado para SHmedia32/SHcompact."
++msgstr "Permite el uso del modo de direccionamiento indexado para SHmedia32/SHcompact."
+ 
+ #: config/sh/sh.opt:293
+-#, fuzzy
+-#| msgid "inline code to invalidate instruction cache entries after setting up nested function trampolines"
+ msgid "inline code to invalidate instruction cache entries after setting up nested function trampolines."
+ msgstr "Código inline para invalidar las entradas de caché de instruciones después de establecerer los trampolines de funciones anidadas."
+ 
+ #: config/sh/sh.opt:297
+-#, fuzzy
+-#| msgid "Assume symbols might be invalid"
+ msgid "Assume symbols might be invalid."
+ msgstr "Asume que los símbolos pueden ser no válidos."
+ 
+ #: config/sh/sh.opt:301 config/arc/arc.opt:209
+-#, fuzzy
+-#| msgid "Annotate assembler instructions with estimated addresses"
+ msgid "Annotate assembler instructions with estimated addresses."
+ msgstr "Anota las instrucciones de ensamblador con direcciones estimadas."
+ 
+ #: config/sh/sh.opt:305
+-#, fuzzy
+-#| msgid "Generate code in little endian mode"
+ msgid "Generate code in little endian mode."
+ msgstr "Genera código en modo little endian."
+ 
+ #: config/sh/sh.opt:309
+-#, fuzzy
+-#| msgid "Mark MAC register as call-clobbered"
+ msgid "Mark MAC register as call-clobbered."
+ msgstr "Marca los registros MAC como sobreescritos por llamada."
+ 
+ #: config/sh/sh.opt:315
+-#, fuzzy
+-#| msgid "Make structs a multiple of 4 bytes (warning: ABI altered)"
+ msgid "Make structs a multiple of 4 bytes (warning: ABI altered)."
+-msgstr "Marca los structs como un múltiplo de 4 bytes (aviso: se altera la ABI)."
++msgstr "Construye los structs como un múltiplo de 4 bytes (aviso: se altera la ABI)."
+ 
+ #: config/sh/sh.opt:319
+-#, fuzzy
+-#| msgid "Emit function-calls using global offset table when generating PIC"
+ msgid "Emit function-calls using global offset table when generating PIC."
+ msgstr "Emite llamadas a función usando la tabla de desplazamiento global al generar PIC."
+ 
+@@ -12617,34 +12314,26 @@
+ msgstr "Asume que las instrucciones pt* no capturarán"
+ 
+ #: config/sh/sh.opt:327
+-#, fuzzy
+-#| msgid "Shorten address references during linking"
+ msgid "Shorten address references during linking."
+ msgstr "Abrevia las referencias de direcciones durante el enlace."
+ 
+ #: config/sh/sh.opt:335
+ msgid "Deprecated.  Use -matomic= instead to select the atomic model."
+-msgstr ""
++msgstr "Obsoleta.  Utilice -matomic= en su lugar para seleccionar el modelo atómico."
+ 
+ #: config/sh/sh.opt:339
+-#, fuzzy
+-#| msgid "Generate code for built-in atomic operations"
+ msgid "Specify the model for atomic operations."
+-msgstr "Genera código para operaciones atómicas internas."
++msgstr "Especifica el modelo para operaciones atómicas."
+ 
+ #: config/sh/sh.opt:343
+ msgid "Use tas.b instruction for __atomic_test_and_set."
+-msgstr ""
++msgstr "Usa la instrucción tas.b para __atomic_test_and_set."
+ 
+ #: config/sh/sh.opt:347
+-#, fuzzy
+-#| msgid "Deprecated.  Use -Os instead"
+ msgid "Deprecated.  Use -Os instead."
+ msgstr "Obsoleto. Utilice en su lugar -Os."
+ 
+ #: config/sh/sh.opt:351
+-#, fuzzy
+-#| msgid "Cost to assume for a multiply insn"
+ msgid "Cost to assume for a multiply insn."
+ msgstr "Costo de asumir una instrucción multiply."
+ 
+@@ -12657,198 +12346,134 @@
+ msgstr "Pretende que una ramificación-alrededor-de-un-movimiento es un movimiento condicional."
+ 
+ #: config/sh/sh.opt:365
+-#, fuzzy
+-#| msgid "Enable the use of the short load instructions"
+ msgid "Enable the use of the fsca instruction."
+-msgstr "Activa el uso de las instrucciones short load."
++msgstr "Activa el uso de la instrucción fsca."
+ 
+ #: config/sh/sh.opt:369
+-#, fuzzy
+-#| msgid "Enable the use of the short load instructions"
+ msgid "Enable the use of the fsrra instruction."
+-msgstr "Activa el uso de las instrucciones short load."
++msgstr "Activa el uso de la instrucción fsrra."
+ 
+ #: config/sh/sh.opt:373
+ msgid "Use LRA instead of reload (transitional)."
+-msgstr ""
++msgstr "Usa LRA en lugar de reload (transicional)."
+ 
+ #: config/fr30/fr30.opt:23
+-#, fuzzy
+-#| msgid "Assume small address space"
+ msgid "Assume small address space."
+ msgstr "Asume espacio de direcciones small."
+ 
+ #: config/mep/mep.opt:23
+-#, fuzzy
+-#| msgid "Enable absolute difference instructions"
+ msgid "Enable absolute difference instructions."
+ msgstr "Activa las instrucciones de diferencia absoluta."
+ 
+ #: config/mep/mep.opt:27
+-#, fuzzy
+-#| msgid "Enable all optional instructions"
+ msgid "Enable all optional instructions."
+ msgstr "Activa todas las instrucciones opcionales."
+ 
+ #: config/mep/mep.opt:31
+-#, fuzzy
+-#| msgid "Enable average instructions"
+ msgid "Enable average instructions."
+ msgstr "Activa las instrucciones promedio."
+ 
+ #: config/mep/mep.opt:35
+-#, fuzzy
+-#| msgid "Variables this size and smaller go in the based section. (default 0)"
+ msgid "Variables this size and smaller go in the based section. (default 0)."
+ msgstr "Las variables de este tamaño y menores van en la sección basada. (por defecto 0)."
+ 
+ #: config/mep/mep.opt:39
+-#, fuzzy
+-#| msgid "Enable bit manipulation instructions"
+ msgid "Enable bit manipulation instructions."
+ msgstr "Activa las instrucciones de manipulación de bits."
+ 
+ #: config/mep/mep.opt:43
+-#, fuzzy
+-#| msgid "Section to put all const variables in (tiny, near, far) (no default)"
+ msgid "Section to put all const variables in (tiny, near, far) (no default)."
+ msgstr "Sección para poner todas las variables const en (tiny, near, far) (sin valor por defecto)."
+ 
+ #: config/mep/mep.opt:47
+-#, fuzzy
+-#| msgid "Enable clip instructions"
+ msgid "Enable clip instructions."
+ msgstr "Activa las instrucciones clip."
+ 
+ #: config/mep/mep.opt:51
+-#, fuzzy
+-#| msgid "Configuration name"
+ msgid "Configuration name."
+ msgstr "Nombre de configuración."
+ 
+ #: config/mep/mep.opt:55
+-#, fuzzy
+-#| msgid "Enable MeP Coprocessor"
+ msgid "Enable MeP Coprocessor."
+ msgstr "Habilita el Coprocesador MeP."
+ 
+ #: config/mep/mep.opt:59
+-#, fuzzy
+-#| msgid "Enable MeP Coprocessor with 32-bit registers"
+ msgid "Enable MeP Coprocessor with 32-bit registers."
+ msgstr "Habilita el Coprocesador MeP con registros de 32-bit."
+ 
+ #: config/mep/mep.opt:63
+-#, fuzzy
+-#| msgid "Enable MeP Coprocessor with 64-bit registers"
+ msgid "Enable MeP Coprocessor with 64-bit registers."
+ msgstr "Habilita el Coprocesador MeP con registros de 64-bit."
+ 
+ #: config/mep/mep.opt:67
+-#, fuzzy
+-#| msgid "Enable IVC2 scheduling"
+ msgid "Enable IVC2 scheduling."
+ msgstr "Activa la planificación IVC2."
+ 
+ #: config/mep/mep.opt:71
+-#, fuzzy
+-#| msgid "Const variables default to the near section"
+ msgid "Const variables default to the near section."
+-msgstr "Las variables cons van por defecto a la sección near."
++msgstr "Las variables const van por defecto a la sección near."
+ 
+ #: config/mep/mep.opt:78
+-#, fuzzy
+-#| msgid "Enable 32-bit divide instructions"
+ msgid "Enable 32-bit divide instructions."
+ msgstr "Activa las instrucciones divide de 32-bit."
+ 
+ #: config/mep/mep.opt:93
+-#, fuzzy
+-#| msgid "__io vars are volatile by default"
+ msgid "__io vars are volatile by default."
+ msgstr "__io vars son volatile por defecto."
+ 
+ #: config/mep/mep.opt:97
+-#, fuzzy
+-#| msgid "All variables default to the far section"
+ msgid "All variables default to the far section."
+ msgstr "Todas las variables van por defecto a la sección far."
+ 
+ #: config/mep/mep.opt:101
+-#, fuzzy
+-#| msgid "Enable leading zero instructions"
+ msgid "Enable leading zero instructions."
+ msgstr "Activa las instrucciones con ceros al inicio."
+ 
+ #: config/mep/mep.opt:108
+-#, fuzzy
+-#| msgid "All variables default to the near section"
+ msgid "All variables default to the near section."
+ msgstr "Todas las variables van por defecto a la sección near."
+ 
+ #: config/mep/mep.opt:112
+-#, fuzzy
+-#| msgid "Enable min/max instructions"
+ msgid "Enable min/max instructions."
+ msgstr "Activa las instrucciones min/max."
+ 
+ #: config/mep/mep.opt:116
+-#, fuzzy
+-#| msgid "Enable 32-bit multiply instructions"
+ msgid "Enable 32-bit multiply instructions."
+ msgstr "Activa las instrucciones multiply de 32-bit."
+ 
+ #: config/mep/mep.opt:120
+-#, fuzzy
+-#| msgid "Disable all optional instructions"
+ msgid "Disable all optional instructions."
+ msgstr "Desactiva todas las instrucciones opcionales."
+ 
+ #: config/mep/mep.opt:127
+-#, fuzzy
+-#| msgid "Allow gcc to use the repeat/erepeat instructions"
+ msgid "Allow gcc to use the repeat/erepeat instructions."
+ msgstr "Permite a gcc usar las instrucciones repeat/erepeat."
+ 
+ #: config/mep/mep.opt:131
+-#, fuzzy
+-#| msgid "All variables default to the tiny section"
+ msgid "All variables default to the tiny section."
+ msgstr "Todas las variables van por defecto a la sección tiny."
+ 
+ #: config/mep/mep.opt:135
+-#, fuzzy
+-#| msgid "Enable saturation instructions"
+ msgid "Enable saturation instructions."
+ msgstr "Activa las instrucciones de saturación."
+ 
+ #: config/mep/mep.opt:139
+-#, fuzzy
+-#| msgid "Use sdram version of runtime"
+ msgid "Use sdram version of runtime."
+ msgstr "Usa la versión sdram de tiempo de ejecución."
+ 
+ #: config/mep/mep.opt:147
+-#, fuzzy
+-#| msgid "Use simulator runtime without vectors"
+ msgid "Use simulator runtime without vectors."
+ msgstr "Usa el simulador de tiempo de ejecución sin vectores."
+ 
+ #: config/mep/mep.opt:151
+-#, fuzzy
+-#| msgid "All functions default to the far section"
+ msgid "All functions default to the far section."
+ msgstr "Todas las funciones van por defecto en la sección far."
+ 
+ #: config/mep/mep.opt:155
+-#, fuzzy
+-#| msgid "Variables this size and smaller go in the tiny section. (default 4)"
+ msgid "Variables this size and smaller go in the tiny section. (default 4)."
+ msgstr "Las variables de este tamaño y menores van en la sección tiny. (por defecto 4)."
+ 
+ #: config/mips/mips.opt:32
+-#, fuzzy
+-#| msgid "-mabi=ABI\tGenerate code that conforms to the given ABI"
+ msgid "-mabi=ABI\tGenerate code that conforms to the given ABI."
+ msgstr "-mabi=ABI\tGenera código que cumpla con la ABI dada."
+ 
+@@ -12857,58 +12482,40 @@
+ msgstr "ABIs MIPS conocidos (para uso con la opción -mabi=):"
+ 
+ #: config/mips/mips.opt:55
+-#, fuzzy
+-#| msgid "Generate code that can be used in SVR4-style dynamic objects"
+ msgid "Generate code that can be used in SVR4-style dynamic objects."
+ msgstr "Genera código que se pueda usar en objetos dinámicos de estilo SVR4."
+ 
+ #: config/mips/mips.opt:59
+-#, fuzzy
+-#| msgid "Use PMC-style 'mad' instructions"
+ msgid "Use PMC-style 'mad' instructions."
+ msgstr "Usa instrucciones 'mad' de estilo PMC."
+ 
+ #: config/mips/mips.opt:63
+-#, fuzzy
+-#| msgid "Use multiply add/subtract instructions"
+ msgid "Use integer madd/msub instructions."
+-msgstr "Usa instrucciones acumular/sustraer de multiplicar."
++msgstr "Usa instrucciones madd/msub de enteros."
+ 
+ #: config/mips/mips.opt:67
+-#, fuzzy
+-#| msgid "-march=ISA\tGenerate code for the given ISA"
+ msgid "-march=ISA\tGenerate code for the given ISA."
+ msgstr "-march=ISA\tGenera código para el ISA dado."
+ 
+ #: config/mips/mips.opt:71
+-#, fuzzy
+-#| msgid "-mbranch-cost=COST\tSet the cost of branches to roughly COST instructions"
+ msgid "-mbranch-cost=COST\tSet the cost of branches to roughly COST instructions."
+ msgstr "-mbranch-cost=COSTO\tEstablece el costo de las ramificaciones aproximadamente a COSTO instrucciones."
+ 
+ #: config/mips/mips.opt:75
+-#, fuzzy
+-#| msgid "Use Branch Likely instructions, overriding the architecture default"
+ msgid "Use Branch Likely instructions, overriding the architecture default."
+-msgstr "Usa instrucciones Branch Likely, sobreponiendo el valor por defecto para la arquitectura."
++msgstr "Usa instrucciones Branch Likely, anulando el valor predeterminado de la arquitectura."
+ 
+ #: config/mips/mips.opt:79
+-#, fuzzy
+-#| msgid "Switch on/off MIPS16 ASE on alternating functions for compiler testing"
+ msgid "Switch on/off MIPS16 ASE on alternating functions for compiler testing."
+-msgstr "Activa/desactiva el ASE de MIPS16 en funciones alternates para pruebas del compilador."
++msgstr "Activa/desactiva el ASE de MIPS16 en funciones alternantes para pruebas del compilador."
+ 
+ #: config/mips/mips.opt:83
+-#, fuzzy
+-#| msgid "Trap on integer divide by zero"
+ msgid "Trap on integer divide by zero."
+ msgstr "Atrapa la división entera por cero."
+ 
+ #: config/mips/mips.opt:87
+-#, fuzzy
+-#| msgid "-mcode-readable=SETTING\tSpecify when instructions are allowed to access code"
+ msgid "-mcode-readable=SETTING\tSpecify when instructions are allowed to access code."
+-msgstr "-mcode-readable=OPCIÓN\tEspecifica cuando se permite que las instrucciones accedan código."
++msgstr "-mcode-readable=OPCIÓN\tEspecifica cuándo se permite que las instrucciones accedan al código."
+ 
+ #: config/mips/mips.opt:91
+ msgid "Valid arguments to -mcode-readable=:"
+@@ -12915,314 +12522,214 @@
+ msgstr "Argumentos válidos para -fcode-readable=:"
+ 
+ #: config/mips/mips.opt:104
+-#, fuzzy
+-#| msgid "Use branch-and-break sequences to check for integer divide by zero"
+ msgid "Use branch-and-break sequences to check for integer divide by zero."
+ msgstr "Usa secuencias ramifica-y-para para revisar la división entera por cero."
+ 
+ #: config/mips/mips.opt:108
+-#, fuzzy
+-#| msgid "Use trap instructions to check for integer divide by zero"
+ msgid "Use trap instructions to check for integer divide by zero."
+ msgstr "Usa instrucciones trap para revisar la división entera por cero."
+ 
+ #: config/mips/mips.opt:112
+-#, fuzzy
+-#| msgid "Allow the use of MDMX instructions"
+ msgid "Allow the use of MDMX instructions."
+ msgstr "Permite el uso de las instrucciones MDMX."
+ 
+ #: config/mips/mips.opt:116
+-#, fuzzy
+-#| msgid "Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations"
+ msgid "Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations."
+ msgstr "Permite que las instrucciones de coma flotante de hardware cubran tanto operaciones de 32-bit como de 64-bit."
+ 
+ #: config/mips/mips.opt:120
+-#, fuzzy
+-#| msgid "Use MIPS-DSP instructions"
+ msgid "Use MIPS-DSP instructions."
+ msgstr "Usa instrucciones MIPS-DSP."
+ 
+ #: config/mips/mips.opt:124
+-#, fuzzy
+-#| msgid "Use MIPS-DSP REV 2 instructions"
+ msgid "Use MIPS-DSP REV 2 instructions."
+ msgstr "Usa instrucciones MIPS-DSP REV 2."
+ 
+ #: config/mips/mips.opt:146
+-#, fuzzy
+-#| msgid "Use the bit-field instructions"
+ msgid "Use Enhanced Virtual Addressing instructions."
+-msgstr "Usa las instrucciones de campos de bit."
++msgstr "Usa las instrucciones de direccionamiento virtual mejorado."
+ 
+ #: config/mips/mips.opt:150
+-#, fuzzy
+-#| msgid "Use NewABI-style %reloc() assembly operators"
+ msgid "Use NewABI-style %reloc() assembly operators."
+ msgstr "Usa los operadores de ensamblador %reloc() del estilo NewABI."
+ 
+ #: config/mips/mips.opt:154
+-#, fuzzy
+-#| msgid "Use -G for data that is not defined by the current object"
+ msgid "Use -G for data that is not defined by the current object."
+ msgstr "Usa -G para los datos que están definidos por el objeto actual."
+ 
+ #: config/mips/mips.opt:158
+-#, fuzzy
+-#| msgid "Work around certain 24K errata"
+ msgid "Work around certain 24K errata."
+-msgstr "Evita errores de ciertos 24K."
++msgstr "Evita ciertos errores de 24K."
+ 
+ #: config/mips/mips.opt:162
+-#, fuzzy
+-#| msgid "Work around certain R4000 errata"
+ msgid "Work around certain R4000 errata."
+-msgstr "Evita errores de ciertos R4000."
++msgstr "Evita ciertos errores de R4000."
+ 
+ #: config/mips/mips.opt:166
+-#, fuzzy
+-#| msgid "Work around certain R4400 errata"
+ msgid "Work around certain R4400 errata."
+-msgstr "Evita errores de ciertos R4400."
++msgstr "Evita ciertos errores de R4400."
+ 
+ #: config/mips/mips.opt:170
+-#, fuzzy
+-#| msgid "Work around certain R4000 errata"
+ msgid "Work around certain RM7000 errata."
+-msgstr "Evita errores de ciertos R4000."
++msgstr "Evita ciertos errores de R4000."
+ 
+ #: config/mips/mips.opt:174
+-#, fuzzy
+-#| msgid "Work around certain R10000 errata"
+ msgid "Work around certain R10000 errata."
+-msgstr "Evita errores de ciertos R10000."
++msgstr "Evita ciertos errores de R10000."
+ 
+ #: config/mips/mips.opt:178
+-#, fuzzy
+-#| msgid "Work around errata for early SB-1 revision 2 cores"
+ msgid "Work around errata for early SB-1 revision 2 cores."
+ msgstr "Evita los errores para núcleos tempranos SB-1 revisión 2."
+ 
+ #: config/mips/mips.opt:182
+-#, fuzzy
+-#| msgid "Work around certain VR4120 errata"
+ msgid "Work around certain VR4120 errata."
+-msgstr "Evita errores de ciertos VR4120."
++msgstr "Evita ciertos errores de VR4120."
+ 
+ #: config/mips/mips.opt:186
+-#, fuzzy
+-#| msgid "Work around VR4130 mflo/mfhi errata"
+ msgid "Work around VR4130 mflo/mfhi errata."
+ msgstr "Evita el error mflo/mfhi del VR4130."
+ 
+ #: config/mips/mips.opt:190
+-#, fuzzy
+-#| msgid "Work around an early 4300 hardware bug"
+ msgid "Work around an early 4300 hardware bug."
+ msgstr "Evita el error de hardware de los primeros 4300."
+ 
+ #: config/mips/mips.opt:194
+-#, fuzzy
+-#| msgid "FP exceptions are enabled"
+ msgid "FP exceptions are enabled."
+ msgstr "Las excepciones FP están activadas."
+ 
+ #: config/mips/mips.opt:198
+-#, fuzzy
+-#| msgid "Use 32-bit floating-point registers"
+ msgid "Use 32-bit floating-point registers."
+ msgstr "Usa los registros de coma flotante de 32-bit."
+ 
+ #: config/mips/mips.opt:202
+ msgid "Conform to the o32 FPXX ABI."
+-msgstr ""
++msgstr "Conforma al o32 FPXX ABI."
+ 
+ #: config/mips/mips.opt:206
+-#, fuzzy
+-#| msgid "Use 64-bit floating-point registers"
+ msgid "Use 64-bit floating-point registers."
+ msgstr "Usa los registros de coma flotante de 64-bit."
+ 
+ #: config/mips/mips.opt:210
+-#, fuzzy
+-#| msgid "-mflush-func=FUNC\tUse FUNC to flush the cache before calling stack trampolines"
+ msgid "-mflush-func=FUNC\tUse FUNC to flush the cache before calling stack trampolines."
+ msgstr "-mflush-func=FUNC\tUsa FUNC para vaciar el caché antes de llamar a los trampolines de pila."
+ 
+ #: config/mips/mips.opt:214
+ msgid "-mabs=MODE\tSelect the IEEE 754 ABS/NEG instruction execution mode."
+-msgstr ""
++msgstr "-mabs=MODO\tSelecciona el modo de ejecución de instrucciones IEEE 754 ABS/NEG."
+ 
+ #: config/mips/mips.opt:218
+ msgid "-mnan=ENCODING\tSelect the IEEE 754 NaN data encoding."
+-msgstr ""
++msgstr "-mnan=CODIFICACIÓN\tSelecciona la codificación de datos IEEE 754 NaN."
+ 
+ #: config/mips/mips.opt:222
+-#, fuzzy
+-#| msgid "Known MIPS CPUs (for use with the -march= and -mtune= options):"
+ msgid "Known MIPS IEEE 754 settings (for use with the -mabs= and -mnan= options):"
+-msgstr "CPUs MIPS conocidos (para uso con las opciones -march= y -mtune=):"
++msgstr "Configuración de lso MIPS IEEE 754 conocidos (para uso con las opciones -mabs= y -mnan=):"
+ 
+ #: config/mips/mips.opt:232
+-#, fuzzy
+-#| msgid "Use 32-bit general registers"
+ msgid "Use 32-bit general registers."
+ msgstr "Usa los registros generales de 32-bit."
+ 
+ #: config/mips/mips.opt:236
+-#, fuzzy
+-#| msgid "Use 64-bit general registers"
+ msgid "Use 64-bit general registers."
+ msgstr "Usa los registros generales de 64-bit."
+ 
+ #: config/mips/mips.opt:240
+-#, fuzzy
+-#| msgid "Use GP-relative addressing to access small data"
+ msgid "Use GP-relative addressing to access small data."
+ msgstr "Usa el direccionamiento relativo al GP para acceder a datos small."
+ 
+ #: config/mips/mips.opt:244
+-#, fuzzy
+-#| msgid "When generating -mabicalls code, allow executables to use PLTs and copy relocations"
+ msgid "When generating -mabicalls code, allow executables to use PLTs and copy relocations."
+ msgstr "Al generar código -mabicalls, permite que los ejecutables usen PLTs y copien reubicaciones."
+ 
+ #: config/mips/mips.opt:248
+-#, fuzzy
+-#| msgid "Allow the use of hardware floating-point ABI and instructions"
+ msgid "Allow the use of hardware floating-point ABI and instructions."
+ msgstr "Permite el uso de la ABI y las instrucciones de coma flotante de hardware."
+ 
+ #: config/mips/mips.opt:252
+-#, fuzzy
+-#| msgid "Generate code that can be safely linked with MIPS16 code."
+ msgid "Generate code that is link-compatible with MIPS16 and microMIPS code."
+-msgstr "Genera código que se puede enlazar sin problemas con código MIPS16."
++msgstr "Genera código que se puede enlazar con código MIPS16 microMIPS."
+ 
+ #: config/mips/mips.opt:256
+-#, fuzzy
+-#| msgid "Does nothing. Preserved for backward compatibility."
+ msgid "An alias for minterlink-compressed provided for backward-compatibility."
+-msgstr "No hace nada. Preservado por compatibilidad hacia atrás."
++msgstr "Sinónimo de minterlink-compressed, preservado por compatibilidad hacia atrás."
+ 
+ #: config/mips/mips.opt:260
+-#, fuzzy
+-#| msgid "-mipsN\tGenerate code for ISA level N"
+ msgid "-mipsN\tGenerate code for ISA level N."
+ msgstr "-mipsN\tGenera código para ISA nivel N."
+ 
+ #: config/mips/mips.opt:264
+-#, fuzzy
+-#| msgid "Generate MIPS16 code"
+ msgid "Generate MIPS16 code."
+ msgstr "Genera código MIPS16."
+ 
+ #: config/mips/mips.opt:268
+-#, fuzzy
+-#| msgid "Use MIPS-3D instructions"
+ msgid "Use MIPS-3D instructions."
+ msgstr "Usa instrucciones MIPS-3D."
+ 
+ #: config/mips/mips.opt:272
+-#, fuzzy
+-#| msgid "Use ll, sc and sync instructions"
+ msgid "Use ll, sc and sync instructions."
+ msgstr "Usa las instrucciones ll, sc y sync."
+ 
+ #: config/mips/mips.opt:276
+-#, fuzzy
+-#| msgid "Use -G for object-local data"
+ msgid "Use -G for object-local data."
+ msgstr "Usa -G para los datos del objeto local."
+ 
+ #: config/mips/mips.opt:280
+-#, fuzzy
+-#| msgid "Use indirect calls"
+ msgid "Use indirect calls."
+ msgstr "Usa llamadas indirectas."
+ 
+ #: config/mips/mips.opt:284
+-#, fuzzy
+-#| msgid "Use a 32-bit long type"
+ msgid "Use a 32-bit long type."
+ msgstr "Usa un tipo long de 32-bit."
+ 
+ #: config/mips/mips.opt:288
+-#, fuzzy
+-#| msgid "Use a 64-bit long type"
+ msgid "Use a 64-bit long type."
+ msgstr "Usa un tipo long de 64-bit."
+ 
+ #: config/mips/mips.opt:292
+-#, fuzzy
+-#| msgid "Pass the address of the ra save location to _mcount in $12"
+ msgid "Pass the address of the ra save location to _mcount in $12."
+ msgstr "Pasa la dirección de la ubicación de ra save a _mcount en $12."
+ 
+ #: config/mips/mips.opt:296
+-#, fuzzy
+-#| msgid "Don't optimize block moves"
+ msgid "Don't optimize block moves."
+ msgstr "No optimiza los movimientos de bloques."
+ 
+ #: config/mips/mips.opt:300
+-#, fuzzy
+-#| msgid "Use SmartMIPS instructions"
+ msgid "Use microMIPS instructions."
+-msgstr "Usa instrucciones SmartMIPS."
++msgstr "Usa instrucciones microMIPS."
+ 
+ #: config/mips/mips.opt:304
+-#, fuzzy
+-#| msgid "Allow the use of MT instructions"
+ msgid "Allow the use of MT instructions."
+ msgstr "Permite el uso de las instrucciones MT."
+ 
+ #: config/mips/mips.opt:308
+-#, fuzzy
+-#| msgid "Prevent the use of all floating-point operations"
+ msgid "Prevent the use of all floating-point operations."
+ msgstr "Previene el uso de todas las instrucciones de coma flotante."
+ 
+ #: config/mips/mips.opt:312
+-#, fuzzy
+-#| msgid "Use MIPS-3D instructions"
+ msgid "Use MCU instructions."
+-msgstr "Usa instrucciones MIPS-3D."
++msgstr "Usa instrucciones MCU."
+ 
+ #: config/mips/mips.opt:316
+-#, fuzzy
+-#| msgid "Do not use a cache-flushing function before calling stack trampolines"
+ msgid "Do not use a cache-flushing function before calling stack trampolines."
+ msgstr "No usa una función que vacíe el caché antes de llamar los trampolines de pila."
+ 
+ #: config/mips/mips.opt:320
+-#, fuzzy
+-#| msgid "Do not use MDMX instructions"
+ msgid "Do not use MDMX instructions."
+ msgstr "No usa instrucciones MDMX."
+ 
+ #: config/mips/mips.opt:324
+-#, fuzzy
+-#| msgid "Generate normal-mode code"
+ msgid "Generate normal-mode code."
+ msgstr "Genera código normal-mode."
+ 
+ #: config/mips/mips.opt:328
+-#, fuzzy
+-#| msgid "Do not use MIPS-3D instructions"
+ msgid "Do not use MIPS-3D instructions."
+ msgstr "No usa instrucciones MIPS-3D."
+ 
+ #: config/mips/mips.opt:332
+-#, fuzzy
+-#| msgid "Use paired-single floating-point instructions"
+ msgid "Use paired-single floating-point instructions."
+ msgstr "Usa instrucciones apareadas-sencillas de coma flotante."
+ 
+ #: config/mips/mips.opt:336
+-#, fuzzy
+-#| msgid "-mr10k-cache-barrier=SETTING\tSpecify when r10k cache barriers should be inserted"
+ msgid "-mr10k-cache-barrier=SETTING\tSpecify when r10k cache barriers should be inserted."
+ msgstr "-mr10k-cache-barrier=OPCIÓN\tEspecifica cuando se deben insertar las barreras de caché de r10k."
+ 
+@@ -13231,94 +12738,64 @@
+ msgstr "Argumentos válidos para -mr10k-cache-barrier=:"
+ 
+ #: config/mips/mips.opt:353
+-#, fuzzy
+-#| msgid "Try to allow the linker to turn PIC calls into direct calls"
+ msgid "Try to allow the linker to turn PIC calls into direct calls."
+ msgstr "Trata de permitir que el enlazador convierta las llamadas PIC a llamadas directas."
+ 
+ #: config/mips/mips.opt:357
+-#, fuzzy
+-#| msgid "When generating -mabicalls code, make the code suitable for use in shared libraries"
+ msgid "When generating -mabicalls code, make the code suitable for use in shared libraries."
+ msgstr "Al generar código -mabicalls, hace que el código sea adecuado para su uso en bibliotecas compartidas."
+ 
+ #: config/mips/mips.opt:361
+-#, fuzzy
+-#| msgid "Restrict the use of hardware floating-point instructions to 32-bit operations"
+ msgid "Restrict the use of hardware floating-point instructions to 32-bit operations."
+ msgstr "Restringe el uso de instrucciones de coma flotante de hardware para operaciones de 32-bit."
+ 
+ #: config/mips/mips.opt:365
+-#, fuzzy
+-#| msgid "Use SmartMIPS instructions"
+ msgid "Use SmartMIPS instructions."
+ msgstr "Usa instrucciones SmartMIPS."
+ 
+ #: config/mips/mips.opt:369
+-#, fuzzy
+-#| msgid "Prevent the use of all hardware floating-point instructions"
+ msgid "Prevent the use of all hardware floating-point instructions."
+ msgstr "Previene el uso de todas las instrucciones de coma flotante de hardware."
+ 
+ #: config/mips/mips.opt:373
+-#, fuzzy
+-#| msgid "Optimize lui/addiu address loads"
+ msgid "Optimize lui/addiu address loads."
+ msgstr "Optimiza las cargas de las direcciones lui/addiu."
+ 
+ #: config/mips/mips.opt:377
+-#, fuzzy
+-#| msgid "Assume all symbols have 32-bit values"
+ msgid "Assume all symbols have 32-bit values."
+ msgstr "Asume que todos los símbolos tienen valores de 32-bit."
+ 
+ #: config/mips/mips.opt:381
+-#, fuzzy
+-#| msgid "Use synci instruction to invalidate i-cache"
+ msgid "Use synci instruction to invalidate i-cache."
+ msgstr "Usa la instrucción synci para invalidar el i-caché."
+ 
+ #: config/mips/mips.opt:389
+-#, fuzzy
+-#| msgid "-mtune=PROCESSOR\tOptimize the output for PROCESSOR"
+ msgid "-mtune=PROCESSOR\tOptimize the output for PROCESSOR."
+ msgstr "-mtune=PROCESADOR\tOptimiza la salida para el PROCESADOR."
+ 
+ #: config/mips/mips.opt:397
+-#, fuzzy
+-#| msgid "Use decimal floating point instructions"
+ msgid "Use Virtualization Application Specific instructions."
+-msgstr "Usa instrucciones de coma flotante decimal."
++msgstr "Usa instrucciones específicas de aplicación de virtualización."
+ 
+ #: config/mips/mips.opt:401
+-#, fuzzy
+-#| msgid "Use vector/scalar (VSX) instructions"
+ msgid "Use eXtended Physical Address (XPA) instructions."
+-msgstr "Usa instrucciones (VSX) vector/escalar."
++msgstr "Usa instrucciones de direcciones físicas extendidas (XPA)."
+ 
+ #: config/mips/mips.opt:405
+-#, fuzzy
+-#| msgid "Perform VR4130-specific alignment optimizations"
+ msgid "Perform VR4130-specific alignment optimizations."
+ msgstr "Realiza optimizaciones de alineación específicas para VR4130."
+ 
+ #: config/mips/mips.opt:409
+-#, fuzzy
+-#| msgid "Lift restrictions on GOT size"
+ msgid "Lift restrictions on GOT size."
+ msgstr "Levanta restricciones en el tamaño de GOT."
+ 
+ #: config/mips/mips.opt:413
+-#, fuzzy
+-#| msgid "Don't allocate floats and doubles in extended-precision registers"
+ msgid "Enable use of odd-numbered single-precision registers."
+-msgstr "No aloja floats y doubles en registros de precisión extendida."
++msgstr "Activa el uso de registros de precisión sencilla impares."
+ 
+ #: config/mips/mips.opt:417
+-#, fuzzy
+-#| msgid "Optimize for space rather than speed"
+ msgid "Optimize frame header."
+-msgstr "Optimiza para espacio en lugar de velocidad."
++msgstr "Optimiza la cabecera de marco."
+ 
+ #: config/mips/mips.opt:424
+ #, fuzzy
+@@ -13328,11 +12805,11 @@
+ 
+ #: config/mips/mips.opt:428
+ msgid "Specify the compact branch usage policy."
+-msgstr ""
++msgstr "Especifica la política de uso de ramificación compacta."
+ 
+ #: config/mips/mips.opt:432
+ msgid "Policies available for use with -mcompact-branches=:"
+-msgstr ""
++msgstr "Políticas disponibles para usar con -mcompact-branches=:"
+ 
+ #: config/mips/mips-tables.opt:24
+ msgid "Known MIPS CPUs (for use with the -march= and -mtune= options):"
+@@ -13355,136 +12832,104 @@
+ msgstr "Compila con longs y punteros de 64 bit."
+ 
+ #: config/tilegx/tilegx.opt:53
+-#, fuzzy
+-#| msgid "Use given x86-64 code model"
+ msgid "Use given TILE-Gx code model."
+-msgstr "Usa el modelo de código del x86-64 dado."
++msgstr "Usa el modelo de código del TILE-Gx dado."
+ 
+ #: config/arc/arc.opt:26
+-#, fuzzy
+-#| msgid "Generate code in big endian mode"
+ msgid "Compile code for big endian mode."
+-msgstr "Genera código en modo big endian."
++msgstr "Compila código para modo big endian."
+ 
+ #: config/arc/arc.opt:30
+-#, fuzzy
+-#| msgid "Stores doubles in 32 bits.  This is the default."
+ msgid "Compile code for little endian mode.  This is the default."
+-msgstr "Almacena dobles en 32 bits.  Este es el valor por defecto."
++msgstr "Compila código para modo little endian.  Este es el valor predefinido."
+ 
+ #: config/arc/arc.opt:34
+ msgid "Disable ARCompact specific pass to generate conditional execution instructions."
+-msgstr ""
++msgstr "Desactiva el paso específico ARCompact para generar instrucciones de ejecución condicional."
+ 
+ #: config/arc/arc.opt:38
+ msgid "Generate ARCompact 32-bit code for ARC600 processor."
+-msgstr ""
++msgstr "Genera código de 32 bits ARCompact para el procesador ARC600."
+ 
+ #: config/arc/arc.opt:42
+-#, fuzzy
+-#| msgid "Same as -mcpu=i386"
+ msgid "Same as -mA6."
+-msgstr "Igual que -mcpu=i386."
++msgstr "Igual que -mA6."
+ 
+ #: config/arc/arc.opt:46
+ msgid "Generate ARCompact 32-bit code for ARC601 processor."
+-msgstr ""
++msgstr "Genera código de 32 bits ARCompact para el procesador ARC601."
+ 
+ #: config/arc/arc.opt:50
+ msgid "Generate ARCompact 32-bit code for ARC700 processor."
+-msgstr ""
++msgstr "Genera código de 32 bits ARCompact para el procesador ARC700."
+ 
+ #: config/arc/arc.opt:54
+-#, fuzzy
+-#| msgid "Same as -mcpu=i386"
+ msgid "Same as -mA7."
+-msgstr "Igual que -mcpu=i386."
++msgstr "Igual que -mA7."
+ 
+ #: config/arc/arc.opt:58
+ msgid "-mmpy-option={0,1,2,3,4,5,6,7,8,9} Compile ARCv2 code with a multiplier design option.  Option 2 is default on."
+-msgstr ""
++msgstr "-mmpy-option={0,1,2,3,4,5,6,7,8,9} Compila código ARCv2 con una opción de diseño de multiplicador.  La opción 2 es la activa predefinida."
+ 
+ #: config/arc/arc.opt:62
+-#, fuzzy
+-#| msgid "Enable clip instructions"
+ msgid "Enable DIV-REM instructions for ARCv2."
+-msgstr "Activa las instrucciones clip."
++msgstr "Activa las instrucciones DIV-REM para ARCv2."
+ 
+ #: config/arc/arc.opt:66
+-#, fuzzy
+-#| msgid "Enable barrel shift instructions"
+ msgid "Enable code density instructions for ARCv2."
+-msgstr "Activa las instrucciones barrel shift."
++msgstr "Activa las instrucciones de densidad de código para ARCv2."
+ 
+ #: config/arc/arc.opt:70
+-#, fuzzy
+-#| msgid "preferentially allocate registers that allow short instruction generation."
+ msgid "Tweak register allocation to help 16-bit instruction generation."
+-msgstr "aloja de preferencia registros que permitan la generación de instrucciones short."
++msgstr "Retoca la asignación de registros para ayudar a la generación de instrucciones de 16 bits."
+ 
+ #: config/arc/arc.opt:80
+ msgid "Use ordinarily cached memory accesses for volatile references."
+-msgstr ""
++msgstr "Usa accesos normales a memoria cacheada para referencias volátiles."
+ 
+ #: config/arc/arc.opt:84
+-#, fuzzy
+-#| msgid "Don't use data cache for volatile mem refs"
+ msgid "Enable cache bypass for volatile references."
+-msgstr "No usar el caché de datos para referencias a memoria volatile."
++msgstr "Activa el bypass de caché para referencias volátiles."
+ 
+ #: config/arc/arc.opt:88
+-#, fuzzy
+-#| msgid "Generate string instructions for block moves"
+ msgid "Generate instructions supported by barrel shifter."
+-msgstr "Genera instrucciones de cadena para movimiento de bloques."
++msgstr "Genera instrucciones admitidas por el barrel shift."
+ 
+ #: config/arc/arc.opt:92
+-#, fuzzy
+-#| msgid "Generate bit instructions"
+ msgid "Generate norm instruction."
+-msgstr "Genera instrucciones bit."
++msgstr "Genera instrucciones norm."
+ 
+ #: config/arc/arc.opt:96
+-#, fuzzy
+-#| msgid "Generate isel instructions"
+ msgid "Generate swap instruction."
+-msgstr "Genera instrucciones isel."
++msgstr "Genera instrucciones swap."
+ 
+ #: config/arc/arc.opt:100
+-#, fuzzy
+-#| msgid "Generate load/store multiple instructions"
+ msgid "Generate mul64 and mulu64 instructions."
+-msgstr "Genera múltiples instrucciones load/store."
++msgstr "Genera instrucciones mul64 y mulu64."
+ 
+ #: config/arc/arc.opt:104
+-#, fuzzy
+-#| msgid "Do not generate multm instructions"
+ msgid "Do not generate mpy instructions for ARC700."
+-msgstr "No generar instrucciones multm."
++msgstr "No generar instrucciones mpy para ARC700."
+ 
+ #: config/arc/arc.opt:108
+ msgid "Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported."
+-msgstr ""
++msgstr "Genera instrucciones de aritmética extendida.  Actualmente solo se dispone de divaw, adds, subs y sat16."
+ 
+ #: config/arc/arc.opt:112
+ msgid "Dummy flag. This is the default unless FPX switches are provided explicitly."
+-msgstr ""
++msgstr "Indicador tonto. Es el predefinido a menos que que se proporcionen switches FPX explícitamente."
+ 
+ #: config/arc/arc.opt:116
+-#, fuzzy
+-#| msgid "Generate call insns as indirect calls"
+ msgid "Generate call insns as register indirect calls."
+-msgstr "Genera las llamadas insns como llamadas indirectas."
++msgstr "Genera las llamadas insns como llamadas indirectas de registros."
+ 
+ #: config/arc/arc.opt:120
+-#, fuzzy
+-#| msgid "Do not generate char instructions"
+ msgid "Do no generate BRcc instructions in arc_reorg."
+-msgstr "No generar instrucciones char."
++msgstr "No generar instrucciones BRcc en arc_reorg."
+ 
+ #: config/arc/arc.opt:124
+ msgid "Generate sdata references.  This is the default, unless you compile for PIC."
+-msgstr ""
++msgstr "Generar referencias de sdata.  Es lo predefinido, salvo que se compile para PIC."
+ 
+ #: config/arc/arc.opt:128
+ #, fuzzy
+@@ -13494,419 +12939,316 @@
+ 
+ #: config/arc/arc.opt:132 config/arc/arc.opt:136
+ msgid "FPX: Generate Single Precision FPX (compact) instructions."
+-msgstr ""
++msgstr "FPX: Generar instrucciones FPX de precisión sencilla (compactas)."
+ 
+ #: config/arc/arc.opt:140
+-#, fuzzy
+-#| msgid "Generate bit instructions"
+ msgid "FPX: Generate Single Precision FPX (fast) instructions."
+-msgstr "Genera instrucciones bit."
++msgstr "FPX: Generar instrucciones FPX de precisión sencilla (rápidas)."
+ 
+ #: config/arc/arc.opt:144
+ msgid "FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions."
+-msgstr ""
++msgstr "FPX: Activar las extensiones de coma flotante de doble precisión de la CPU Argonaut ARC."
+ 
+ #: config/arc/arc.opt:148 config/arc/arc.opt:152
+-#, fuzzy
+-#| msgid "Generate bit instructions"
+ msgid "FPX: Generate Double Precision FPX (compact) instructions."
+-msgstr "Genera instrucciones bit."
++msgstr "FPX: Generar instrucciones FPX de precisión doble (compactas)."
+ 
+ #: config/arc/arc.opt:156
+-#, fuzzy
+-#| msgid "Generate bit instructions"
+ msgid "FPX: Generate Double Precision FPX (fast) instructions."
+-msgstr "Genera instrucciones bit."
++msgstr "FPX: Generar instrucciones FPX de precisión doble (rápidas)."
+ 
+ #: config/arc/arc.opt:160
+ msgid "Disable LR and SR instructions from using FPX extension aux registers."
+-msgstr ""
++msgstr "Desactivar en las instrucciones LR y SR el uso de registros auxiliares de la extensión FPX."
+ 
+ #: config/arc/arc.opt:164
+ msgid "Enable generation of ARC SIMD instructions via target-specific builtins."
+-msgstr ""
++msgstr "Activar la generación de instrucciones ARC SIMD mediante funciones internas específicas de objetivo."
+ 
+ #: config/arc/arc.opt:168
+-#, fuzzy
+-#| msgid "-mcpu=CPU\tCompile code for ARC variant CPU"
+ msgid "-mcpu=CPU\tCompile code for ARC variant CPU."
+-msgstr "-mcpu=CPU\tCompila código para el CPU de variante ARC."
++msgstr "-mcpu=CPU\tCompila código para la CPU de variante ARC."
+ 
+ #: config/arc/arc.opt:205
+ msgid "size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os."
+-msgstr ""
++msgstr "nivel de optimización del tamaño: 0:nada 1:oportunista 2:regalloc 3:alineación libre, -Os."
+ 
+ #: config/arc/arc.opt:213
+-#, fuzzy
+-#| msgid "Cost to assume for a multiply insn"
+ msgid "Cost to assume for a multiply instruction, with 4 being equal to a normal insn."
+-msgstr "Costo de asumir una instrucción multiply."
++msgstr "Costo de asumir una instrucción multiply, siendo 4 el de una instrucción normal."
+ 
+ #: config/arc/arc.opt:217
+ msgid "Tune for ARC600 cpu."
+-msgstr ""
++msgstr "Afinado para cpu ARC600."
+ 
+ #: config/arc/arc.opt:221
+ msgid "Tune for ARC601 cpu."
+-msgstr ""
++msgstr "Afinado para cpu ARC601."
+ 
+ #: config/arc/arc.opt:225
+ msgid "Tune for ARC700 R4.2 Cpu with standard multiplier block."
+-msgstr ""
++msgstr "Afinado para Cpu ARC700 R4.2 con bloque multiplicador estándar."
+ 
+ #: config/arc/arc.opt:229 config/arc/arc.opt:233 config/arc/arc.opt:237
+ msgid "Tune for ARC700 R4.2 Cpu with XMAC block."
+-msgstr ""
++msgstr "Afinado para Cpu ARC700 R4.2 con bloque XMAC."
+ 
+ #: config/arc/arc.opt:241
+-#, fuzzy
+-#| msgid "Enable the use of the short load instructions"
+ msgid "Enable the use of indexed loads."
+-msgstr "Activa el uso de las instrucciones short load."
++msgstr "Activa el uso de loads indexadas."
+ 
+ #: config/arc/arc.opt:245
+ msgid "Enable the use of pre/post modify with register displacement."
+-msgstr ""
++msgstr "Activa el uso de pre/post modify con desplazamiento de registro."
+ 
+ #: config/arc/arc.opt:249
+-#, fuzzy
+-#| msgid "Generate fused multiply/add instructions"
+ msgid "Generate 32x16 multiply and mac instructions."
+-msgstr "Genera instrucciones multiply/add de corto circuito."
++msgstr "Genera instrucciones multiply y mac de 32x16."
+ 
+ #: config/arc/arc.opt:255
+ msgid "Set probability threshold for unaligning branches."
+-msgstr ""
++msgstr "Establece el umbral de probabilidad para ramificaciones desalineadas."
+ 
+ #: config/arc/arc.opt:259
+ msgid "Don't use less than 25 bit addressing range for calls."
+-msgstr ""
++msgstr "No utilizar rango de direccionamiento de menos de 25 bits para llamadas."
+ 
+ #: config/arc/arc.opt:263
+ msgid "Explain what alignment considerations lead to the decision to make an insn short or long."
+-msgstr ""
++msgstr "Explicar qué consideraciones de alineamiento llevan a la decisión de hacer una insn corta o larga."
+ 
+ #: config/arc/arc.opt:267
+-#, fuzzy
+-#| msgid "Avoid all range limits on call instructions"
+ msgid "Do alignment optimizations for call instructions."
+-msgstr "Evita todos los límites de rango en las instrucciones de llamadas."
++msgstr "Efectúa optimizaciones de alineamiento en las instrucciones de llamadas."
+ 
+ #: config/arc/arc.opt:271
+ msgid "Enable Rcq constraint handling - most short code generation depends on this."
+-msgstr ""
++msgstr "Activa el manejo de restricciones Rcq - la mayor parte de la generación de código corto depende de esto."
+ 
+ #: config/arc/arc.opt:275
+ msgid "Enable Rcw constraint handling - ccfsm condexec mostly depends on this."
+-msgstr ""
++msgstr "Activa el manejo de restricciones Rcw - la ejecución condicional ccfsd depende principalmente de esto."
+ 
+ #: config/arc/arc.opt:279
+-#, fuzzy
+-#| msgid "Enable cbranchdi4 pattern"
+ msgid "Enable pre-reload use of cbranchsi pattern."
+-msgstr "Activa el patrón cbranchdi4."
++msgstr "Activa el uso pre-recarga del patrón cbranchsi."
+ 
+ #: config/arc/arc.opt:283
+ msgid "Enable bbit peephole2."
+-msgstr ""
++msgstr "Activa bbit peephole2."
+ 
+ #: config/arc/arc.opt:287
+ msgid "Use pc-relative switch case tables - this enables case table shortening."
+-msgstr ""
++msgstr "Usa tables switch case relativas a contador de programa - esto activa el acortamiento de tablas case."
+ 
+ #: config/arc/arc.opt:291
+-#, fuzzy
+-#| msgid "Enable cbranchdi4 pattern"
+ msgid "Enable compact casesi pattern."
+-msgstr "Activa el patrón cbranchdi4."
++msgstr "Activa el patrón casesi compacto."
+ 
+ #: config/arc/arc.opt:295
+-#, fuzzy
+-#| msgid "Enable clip instructions"
+ msgid "Enable 'q' instruction alternatives."
+-msgstr "Activa las instrucciones clip."
++msgstr "Activa las instrucciones alternativas 'q'."
+ 
+ #: config/arc/arc.opt:299
+ msgid "Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc."
+-msgstr ""
++msgstr "Expande adddi3 y subdi3 en tiempo de generación de rtl en add.f / adc, etc."
+ 
+ #: config/arc/arc.opt:306
+ msgid "Enable variable polynomial CRC extension."
+-msgstr ""
++msgstr "Activa la extensión de CRC polinómico variable."
+ 
+ #: config/arc/arc.opt:310
+-#, fuzzy
+-#| msgid "Enable Plan 9 language extensions"
+ msgid "Enable DSP 3.1 Pack A extensions."
+-msgstr "Activa las extensiones de lenguaje de Plan9."
++msgstr "Activa las extensiones DSP 3.1 Pack A."
+ 
+ #: config/arc/arc.opt:314
+-#, fuzzy
+-#| msgid "Enable linker relaxation."
+ msgid "Enable dual viterbi butterfly extension."
+-msgstr "Activa la relajación del enlazador."
++msgstr "Activa la la extensión dual viterbi butterfly."
+ 
+ #: config/arc/arc.opt:324
+-#, fuzzy
+-#| msgid "Enable leading zero instructions"
+ msgid "Enable Dual and Single Operand Instructions for Telephony."
+-msgstr "Activa las instrucciones con ceros al inicio."
++msgstr "Activa las instrucciones de operando dual y único para telefonía."
+ 
+ #: config/arc/arc.opt:328
+ msgid "Enable XY Memory extension (DSP version 3)."
+-msgstr ""
++msgstr "Activa la extensión XY Memory (DSP versión 3)."
+ 
+ #: config/arc/arc.opt:333
+-#, fuzzy
+-#| msgid "Enable hoisting loads from conditional pointers."
+ msgid "Enable Locked Load/Store Conditional extension."
+-msgstr "Activa las cargas de elevación de punteros condicionales."
++msgstr "Activa la extensión condicional load/store bloqueada."
+ 
+ #: config/arc/arc.opt:337
+-#, fuzzy
+-#| msgid "Enable sign extend instructions"
+ msgid "Enable swap byte ordering extension instruction."
+-msgstr "Activa las instrucciones de signo extendido."
++msgstr "Activa la instrucción de extensión del orden de byte de intercambio."
+ 
+ #: config/arc/arc.opt:341
+-#, fuzzy
+-#| msgid "Enable bit manipulation instructions"
+ msgid "Enable 64-bit Time-Stamp Counter extension instruction."
+-msgstr "Activa las instrucciones de manipulación de bits."
++msgstr "Activa la instrucción de extensión del contador de sello de tiempo de 64 bits."
+ 
+ #: config/arc/arc.opt:345
+-#, fuzzy
+-#| msgid "Pass -z text to linker"
+ msgid "Pass -EB option through to linker."
+-msgstr "Pasa -z texto al enlazador."
++msgstr "Pasa la opción -EB al enlazador."
+ 
+ #: config/arc/arc.opt:349
+-#, fuzzy
+-#| msgid "Pass -z text to linker"
+ msgid "Pass -EL option through to linker."
+-msgstr "Pasa -z texto al enlazador."
++msgstr "Pasa la opción -EL al enlazador."
+ 
+ #: config/arc/arc.opt:353
+-#, fuzzy
+-#| msgid "Pass -z text to linker"
+ msgid "Pass -marclinux option through to linker."
+-msgstr "Pasa -z texto al enlazador."
++msgstr "Pasa la opción -marclinux al enlazador."
+ 
+ #: config/arc/arc.opt:357
+ msgid "Pass -marclinux_prof option through to linker."
+-msgstr ""
++msgstr "Pasa la opción -marclinux_prof al enlazador."
+ 
+ #: config/arc/arc.opt:365
+-#, fuzzy
+-#| msgid "Enable linker relaxation."
+ msgid "Enable lra."
+-msgstr "Activa la relajación del enlazador."
++msgstr "Activa lra."
+ 
+ #: config/arc/arc.opt:369
+ msgid "Don't indicate any priority with TARGET_REGISTER_PRIORITY."
+-msgstr ""
++msgstr "No indica ninguna prioridad con TARGET_REGISTER_PRIORITY."
+ 
+ #: config/arc/arc.opt:373
+ msgid "Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY."
+-msgstr ""
++msgstr "Indica prioridad para r0..r3 / r12..r15 con TARGET_REGISTER_PRIORITY."
+ 
+ #: config/arc/arc.opt:377
+ msgid "Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY."
+-msgstr ""
++msgstr "Reduce prioridad para r0..r3 / r12..r15 con TARGET_REGISTER_PRIORITY."
+ 
+ #: config/arc/arc.opt:381
+ msgid "instrument with mcount calls as in the ucb code."
+-msgstr ""
++msgstr "instrumenta con llamadas mcount como en el código ucb."
+ 
+ #: config/arc/arc.opt:411
+-#, fuzzy
+-#| msgid "Enable clip instructions"
+ msgid "Enable atomic instructions."
+-msgstr "Activa las instrucciones clip."
++msgstr "Activa instrucciones atómicas."
+ 
+ #: config/arc/arc.opt:415
+-#, fuzzy
+-#| msgid "Enable unaligned load/store instruction"
+ msgid "Enable double load/store instructions for ARC HS."
+-msgstr "Activa la instrucción load/store sin alineación."
++msgstr "Activa las instrucciones dobles load/store para ARC HS."
+ 
+ #: config/arc/arc.opt:419
+-#, fuzzy
+-#| msgid "Specify the name of the target floating point hardware/format"
+ msgid "Specify the name of the target floating point configuration."
+-msgstr "Especifica el nombre del hardware/formato de coma flotante destino."
++msgstr "Especifica el nombre de la configuración de coma flotante destino."
+ 
+ #: java/lang.opt:122
+-#, fuzzy
+-#| msgid "Warn if deprecated empty statements are found"
+ msgid "Warn if deprecated empty statements are found."
+ msgstr "Avisa si se encuentran declaraciones vacías obsoletas."
+ 
+ #: java/lang.opt:126
+-#, fuzzy
+-#| msgid "Warn if .class files are out of date"
+ msgid "Warn if .class files are out of date."
+ msgstr "Avisa si los ficheros .class están desactualizados."
+ 
+ #: java/lang.opt:130
+-#, fuzzy
+-#| msgid "Warn if modifiers are specified when not necessary"
+ msgid "Warn if modifiers are specified when not necessary."
+ msgstr "Avisa si se especifican modificadores cuando no son necesarios."
+ 
+ #: java/lang.opt:150
+-#, fuzzy
+-#| msgid "--CLASSPATH\tDeprecated; use --classpath instead"
+ msgid "--CLASSPATH\tDeprecated; use --classpath instead."
+ msgstr "--CLASSPATH\tObsoleto; use en su lugar --classpath."
+ 
+ #: java/lang.opt:157
+-#, fuzzy
+-#| msgid "Permit the use of the assert keyword"
+ msgid "Permit the use of the assert keyword."
+ msgstr "Permite el uso de la palabra clave assert."
+ 
+ #: java/lang.opt:179
+-#, fuzzy
+-#| msgid "--bootclasspath=<path>\tReplace system path"
+ msgid "--bootclasspath=<path>\tReplace system path."
+ msgstr "--bootclasspath=<ruta>\tReemplaza la ruta del sistema."
+ 
+ #: java/lang.opt:183
+-#, fuzzy
+-#| msgid "Generate checks for references to NULL"
+ msgid "Generate checks for references to NULL."
+ msgstr "Genera revisiones para referencias a NULL."
+ 
+ #: java/lang.opt:187
+-#, fuzzy
+-#| msgid "--classpath=<path>\tSet class path"
+ msgid "--classpath=<path>\tSet class path."
+ msgstr "--classpath=<ruta>\tEstablece la ruta de clases."
+ 
+ #: java/lang.opt:194
+-#, fuzzy
+-#| msgid "Output a class file"
+ msgid "Output a class file."
+ msgstr "Genera un fichero clase como salida."
+ 
+ #: java/lang.opt:198
+-#, fuzzy
+-#| msgid "Alias for -femit-class-file"
+ msgid "Alias for -femit-class-file."
+ msgstr "Alias para -femit-class-file."
+ 
+ #: java/lang.opt:202
+-#, fuzzy
+-#| msgid "--encoding=<encoding>\tChoose input encoding (defaults from your locale)"
+ msgid "--encoding=<encoding>\tChoose input encoding (defaults from your locale)."
+ msgstr "--encoding=<codificación>\tEscoge la codificación de entrada (por defecto viene del local)."
+ 
+ #: java/lang.opt:206
+-#, fuzzy
+-#| msgid "--extdirs=<path>\tSet the extension directory path"
+ msgid "--extdirs=<path>\tSet the extension directory path."
+ msgstr "--extdirs=<ruta>\tEstablece la ruta del directorio de extensiones."
+ 
+ #: java/lang.opt:216
+-#, fuzzy
+-#| msgid "Input file is a file with a list of filenames to compile"
+ msgid "Input file is a file with a list of filenames to compile."
+ msgstr "El fichero de entrada es un fichero con la lista de nombres de fichero a compilar."
+ 
+ #: java/lang.opt:223
+-#, fuzzy
+-#| msgid "Always check for non gcj generated classes archives"
+ msgid "Always check for non gcj generated classes archives."
+ msgstr "Revisa siempre por archivos de clases no generados por gcj."
+ 
+ #: java/lang.opt:227
+-#, fuzzy
+-#| msgid "Assume the runtime uses a hash table to map an object to its synchronization structure"
+ msgid "Assume the runtime uses a hash table to map an object to its synchronization structure."
+ msgstr "Asume que el tiempo de ejecución usa una tabla hash para mapear un objeto a su estructura de sincronización."
+ 
+ #: java/lang.opt:231
+-#, fuzzy
+-#| msgid "Generate instances of Class at runtime"
+ msgid "Generate instances of Class at runtime."
+ msgstr "Genera instancias de Class en tiempo de ejecución."
+ 
+ #: java/lang.opt:235
+-#, fuzzy
+-#| msgid "Use offset tables for virtual method calls"
+ msgid "Use offset tables for virtual method calls."
+ msgstr "Utiliza tablas de desplazamiento para llamadas a métodos virtuales."
+ 
+ #: java/lang.opt:242
+-#, fuzzy
+-#| msgid "Assume native functions are implemented using JNI"
+ msgid "Assume native functions are implemented using JNI."
+ msgstr "Asume que las funciones nativas se implementan usando JNI."
+ 
+ #: java/lang.opt:246
+-#, fuzzy
+-#| msgid "Enable optimization of static class initialization code"
+ msgid "Enable optimization of static class initialization code."
+ msgstr "Activa la optimización del código de inicialización de las clases static."
+ 
+ #: java/lang.opt:253
+-#, fuzzy
+-#| msgid "Reduce the amount of reflection meta-data generated"
+ msgid "Reduce the amount of reflection meta-data generated."
+ msgstr "Reduce la cantidad de metadatos de reflexión generados."
+ 
+ #: java/lang.opt:257
+-#, fuzzy
+-#| msgid "Enable assignability checks for stores into object arrays"
+ msgid "Enable assignability checks for stores into object arrays."
+ msgstr "Activa revisiones de asignabilidad para almacenamientos en matrices de objetos."
+ 
+ #: java/lang.opt:261
+-#, fuzzy
+-#| msgid "Generate code for the Boehm GC"
+ msgid "Generate code for the Boehm GC."
+ msgstr "Genera código para el GC de Boehm."
+ 
+ #: java/lang.opt:265
+-#, fuzzy
+-#| msgid "Call a library routine to do integer divisions"
+ msgid "Call a library routine to do integer divisions."
+ msgstr "Llama a una rutina de biblioteca para hacer divisiones enteras."
+ 
+ #: java/lang.opt:269
+-#, fuzzy
+-#| msgid "Generate code for built-in atomic operations"
+ msgid "Generate code for built-in atomic operations."
+ msgstr "Genera código para operaciones atómicas internas."
+ 
+ #: java/lang.opt:273
+-#, fuzzy
+-#| msgid "Generated should be loaded by bootstrap loader"
+ msgid "Generated should be loaded by bootstrap loader."
+ msgstr "El generado se debe cargar con el cargador de arranque."
+ 
+ #: java/lang.opt:277
+-#, fuzzy
+-#| msgid "Set the source language version"
+ msgid "Set the source language version."
+ msgstr "Establece la versión del lenguaje fuente."
+ 
+ #: java/lang.opt:281
+-#, fuzzy
+-#| msgid "Set the target VM version"
+ msgid "Set the target VM version."
+ msgstr "Establece la versión de la MV destino."
+ 
+ #: lto/lang.opt:28
+-#, fuzzy, c-format
+-#| msgid "unknown architecture %qs"
++#, c-format
+ msgid "unknown linker output %qs"
+-msgstr "arquitectura %qs desconocida"
++msgstr "salida %qs del enlazador desconocida"
+ 
+ #: lto/lang.opt:47
+ msgid "Set linker output type (used internally during LTO optimization)"
+-msgstr ""
++msgstr "Establece el tipo de salida del enlazador (usado internamente durante la optimización LTO)"
+ 
+ #: lto/lang.opt:52
+ msgid "Run the link-time optimizer in local transformation (LTRANS) mode."
+@@ -13922,165 +13264,113 @@
+ 
+ #: lto/lang.opt:64
+ msgid "Whole program analysis (WPA) mode with number of parallel jobs specified."
+-msgstr ""
++msgstr "Modo de análisis del programa completo (WPA) con número de trabajos paralelos especificado."
+ 
+ #: lto/lang.opt:68
+-#, fuzzy
+-#| msgid "The resolution file"
+ msgid "The resolution file."
+ msgstr "El fichero de resolución."
+ 
+ #: common.opt:235
+-#, fuzzy
+-#| msgid "Enable user-defined instructions"
+ msgid "Enable coverage-guided fuzzing code instrumentation."
+-msgstr "Activa las instrucciones definidas por el usuario."
++msgstr "Activa la instrumentación de código borrosa guiada por cobertura."
+ 
+ #: common.opt:302
+-#, fuzzy
+-#| msgid "Display this information"
+ msgid "Display this information."
+ msgstr "Muestra esta información."
+ 
+ #: common.opt:306
+-#, fuzzy
+-#| msgid "--help=<class>\tDisplay descriptions of a specific class of options.  <class> is one or more of optimizers, target, warnings, undocumented, params"
+ msgid "--help=<class>\tDisplay descriptions of a specific class of options.  <class> is one or more of optimizers, target, warnings, undocumented, params."
+ msgstr "--help=<clase>\tMuestra las descripciones para una clase específica de opciones.  <clase> es uno o más de optimizers, target, warnings, undocumented, params."
+ 
+ #: common.opt:424
+-#, fuzzy
+-#| msgid "Alias for --help=target"
+ msgid "Alias for --help=target."
+-msgstr "Alias para -mhelp=target."
++msgstr "Alias para --help=target."
+ 
+ #: common.opt:449
+-#, fuzzy
+-#| msgid "--param <param>=<value>\tSet parameter <param> to value.  See below for a complete list of parameters"
+ msgid "--param <param>=<value>\tSet parameter <param> to value.  See below for a complete list of parameters."
+ msgstr "--param <param>=<valor>\tEstablece el parámetro <param> al valor.  Vea a continuación una lista completa de parámetros."
+ 
+ #: common.opt:477
+-#, fuzzy
+-#| msgid "-O<number>\tSet optimization level to <number>"
+ msgid "-O<number>\tSet optimization level to <number>."
+ msgstr "-O<número>\tEstablece el nivel de optimización a <número>."
+ 
+ #: common.opt:481
+-#, fuzzy
+-#| msgid "Optimize for space rather than speed"
+ msgid "Optimize for space rather than speed."
+ msgstr "Optimiza para espacio en lugar de velocidad."
+ 
+ #: common.opt:485
+-#, fuzzy
+-#| msgid "Optimize for speed disregarding exact standards compliance"
+ msgid "Optimize for speed disregarding exact standards compliance."
+ msgstr "Optimiza para velocidad descartando el cumplimento exacto de estándares."
+ 
+ #: common.opt:489
+-#, fuzzy
+-#| msgid "Optimize for space rather than speed"
+ msgid "Optimize for debugging experience rather than speed or size."
+-msgstr "Optimiza para espacio en lugar de velocidad."
++msgstr "Optimiza para experiencia de depuración en lugar de velocidad o tamaño."
+ 
+ #: common.opt:529
+-#, fuzzy
+-#| msgid "This switch is deprecated; use -Wextra instead"
+ msgid "This switch is deprecated; use -Wextra instead."
+ msgstr "Esta opción es obsoleta; utilice en su lugar -Wextra."
+ 
+ #: common.opt:542
+-#, fuzzy
+-#| msgid "Warn about returning structures, unions or arrays"
+ msgid "Warn about returning structures, unions or arrays."
+ msgstr "Avisa sobre la devolución de estructuras, unions o matrices."
+ 
+ #: common.opt:546
+ msgid "Warn if a loop with constant number of iterations triggers undefined behavior."
+-msgstr ""
++msgstr "Avisa si un bucle con un número constante de iteraciones provoca un comportamiento indefinido."
+ 
+ #: common.opt:550 common.opt:554
+-#, fuzzy
+-#| msgid "Warn if an array is accessed out of bounds"
+ msgid "Warn if an array is accessed out of bounds."
+ msgstr "Avisa si se accede a una matriz fuera de los límites."
+ 
+ #: common.opt:558
+-#, fuzzy
+-#| msgid "Warn about inappropriate attribute usage"
+ msgid "Warn about inappropriate attribute usage."
+ msgstr "Avisa sobre la aritmética de punteros de funciones."
+ 
+ #: common.opt:562
+-#, fuzzy
+-#| msgid "Warn about pointer casts which increase alignment"
+ msgid "Warn about pointer casts which increase alignment."
+ msgstr "Avisa sobre conversión de punteros que incremente la alineación."
+ 
+ #: common.opt:566
+-#, fuzzy
+-#| msgid "Warn when a #warning directive is encountered"
+ msgid "Warn when a #warning directive is encountered."
+ msgstr "Avisa cuando se encuentra una directiva #warning."
+ 
+ #: common.opt:570
+-#, fuzzy
+-#| msgid "Warn about uses of __attribute__((deprecated)) declarations"
+ msgid "Warn about uses of __attribute__((deprecated)) declarations."
+ msgstr "Avisa sobre usos de declaraciones __attribute__((obsoleto))."
+ 
+ #: common.opt:574
+-#, fuzzy
+-#| msgid "Warn when an optimization pass is disabled"
+ msgid "Warn when an optimization pass is disabled."
+ msgstr "Avisa cuando se desactiva un paso de optimización."
+ 
+ #: common.opt:578
+-#, fuzzy
+-#| msgid "Treat all warnings as errors"
+ msgid "Treat all warnings as errors."
+ msgstr "Trata todos los avisos como errores."
+ 
+ #: common.opt:582
+-#, fuzzy
+-#| msgid "Treat specified warning as error"
+ msgid "Treat specified warning as error."
+ msgstr "Trata el aviso especificado como error."
+ 
+ #: common.opt:586
+-#, fuzzy
+-#| msgid "Print extra (possibly unwanted) warnings"
+ msgid "Print extra (possibly unwanted) warnings."
+ msgstr "Muestra avisos extra (posiblemente no deseados)."
+ 
+ #: common.opt:590
+-#, fuzzy
+-#| msgid "Exit on the first error occurred"
+ msgid "Exit on the first error occurred."
+ msgstr "Termina cuando sucede el primer error."
+ 
+ #: common.opt:594
+-#, fuzzy
+-#| msgid "-Wframe-larger-than=<number>\tWarn if a function's stack frame requires more than <number> bytes"
+ msgid "-Wframe-larger-than=<number>\tWarn if a function's stack frame requires more than <number> bytes."
+ msgstr "-Wframe-larger-than=<número>\tAvisa si el marco de la pila de una función requiere más de <número> bytes."
+ 
+ #: common.opt:598
+-#, fuzzy
+-#| msgid "Warn when attempting to free a non-heap object"
+ msgid "Warn when attempting to free a non-heap object."
+ msgstr "Avisa cuando se intenta liberar un objeto que no es de pila."
+ 
+ #: common.opt:602
+-#, fuzzy
+-#| msgid "Warn when an inlined function cannot be inlined"
+ msgid "Warn when a function cannot be expanded to HSAIL."
+-msgstr "Avisa cuando una función incluida en línea no se puede incluir en línea."
++msgstr "Avisa cuando una función no se puede expandir a HSAIL."
+ 
+ #: common.opt:606
+-#, fuzzy
+-#| msgid "Warn when an inlined function cannot be inlined"
+ msgid "Warn when an inlined function cannot be inlined."
+ msgstr "Avisa cuando una función incluida en línea no se puede incluir en línea."
+ 
+@@ -14089,18 +13379,16 @@
+ msgstr "Avisa cuando un parámetro de modelo de memoria atomic se reconoce que está fuera del rango válido."
+ 
+ #: common.opt:617
+-#, fuzzy
+-#| msgid "-Wlarger-than=<number>\tWarn if an object is larger than <number> bytes"
+ msgid "-Wlarger-than=<number>\tWarn if an object is larger than <number> bytes."
+ msgstr "-Wlarger-than=<número>\tAvisa si un objeto es más grande que <número> bytes."
+ 
+ #: common.opt:621
+ msgid "Warn if comparing pointer parameter with nonnull attribute with NULL."
+-msgstr ""
++msgstr "Avisa si se compara parámetro puntero con atributo no nulo con NULL."
+ 
+ #: common.opt:625
+ msgid "Warn if dereferencing a NULL pointer may lead to erroneous or undefined behavior."
+-msgstr ""
++msgstr "Avisa si la desreferencia de un puntero NULL puede llevar a un comportamiento erróneo o indefinido."
+ 
+ #: common.opt:629
+ msgid "Warn if the loop cannot be optimized due to nontrivial assumptions."
+@@ -14108,249 +13396,175 @@
+ 
+ #: common.opt:636
+ msgid "Warn about some C++ One Definition Rule violations during link time optimization."
+-msgstr ""
++msgstr "Advierto de algunas violaciones de la regla de una definición de C++ durante la optimización de tiempo de enlazado."
+ 
+ #: common.opt:640
+-#, fuzzy
+-#| msgid "Warn about overflow in arithmetic expressions"
+ msgid "Warn about overflow in arithmetic expressions."
+ msgstr "Avisa sobre desbordamiento por debajo en expresiones numéricas."
+ 
+ #: common.opt:644
+ msgid "During link time optimization warn about mismatched types of global declarations."
+-msgstr ""
++msgstr "Durante la optimización en tiempo de enlazado advierte de tipos de declaraciones globales que no casan."
+ 
+ #: common.opt:648
+-#, fuzzy
+-#| msgid "Warn when the packed attribute has no effect on struct layout"
+ msgid "Warn when the packed attribute has no effect on struct layout."
+ msgstr "Avisa cuando el atributo packed no tiene efecto en la disposición de un struct."
+ 
+ #: common.opt:652
+-#, fuzzy
+-#| msgid "Warn when padding is required to align structure members"
+ msgid "Warn when padding is required to align structure members."
+ msgstr "Avisa cuando se requiere relleno para alinear a los miembros de una estructura."
+ 
+ #: common.opt:656
+-#, fuzzy
+-#| msgid "Issue warnings needed for strict compliance to the standard"
+ msgid "Issue warnings needed for strict compliance to the standard."
+ msgstr "Activa los avisos necesarios para cumplir estrictamente con el estándar."
+ 
+ #: common.opt:660
+-#, fuzzy
+-#| msgid "returning reference to temporary"
+ msgid "Warn about returning a pointer/reference to a local or temporary variable."
+-msgstr "se devuelve la referencia al temporal."
++msgstr "Advierte del retorno de puntero/referencia a variable local o temporal."
+ 
+ #: common.opt:664
+-#, fuzzy
+-#| msgid "Warn when one local variable shadows another"
+ msgid "Warn when one local variable shadows another."
+-msgstr "Avisa cuando una variable local oscurece otra."
++msgstr "Avisa cuando una variable local oculta otra."
+ 
+ #: common.opt:668
+-#, fuzzy
+-#| msgid "Warn when not issuing stack smashing protection for some reason"
+ msgid "Warn when not issuing stack smashing protection for some reason."
+ msgstr "Avisa cuando no se está usando la protección contra destrucción de la pila por alguna razón."
+ 
+ #: common.opt:672
+-#, fuzzy
+-#| msgid "Warn if stack usage might be larger than specified amount"
+ msgid "Warn if stack usage might be larger than specified amount."
+ msgstr "Avisa si el uso de pila puede ser mayor que el monto especificado."
+ 
+ #: common.opt:676 common.opt:680
+-#, fuzzy
+-#| msgid "Warn about code which might break strict aliasing rules"
+ msgid "Warn about code which might break strict aliasing rules."
+ msgstr "Avisa sobre código que pueda romper las reglas estrictas de aliases."
+ 
+ #: common.opt:684 common.opt:688
+-#, fuzzy
+-#| msgid "Warn about optimizations that assume that signed overflow is undefined"
+ msgid "Warn about optimizations that assume that signed overflow is undefined."
+ msgstr "Desactiva las optimizaciones que asumen que un desbordamiento con signo está indefinido."
+ 
+ #: common.opt:692
+-#, fuzzy
+-#| msgid "Warn about functions which might be candidates for __attribute__((const))"
+ msgid "Warn about functions which might be candidates for __attribute__((const))."
+ msgstr "Avisa sobre funciones que pueden ser candidatas para __attribute__((const))."
+ 
+ #: common.opt:696
+-#, fuzzy
+-#| msgid "Warn about functions which might be candidates for __attribute__((pure))"
+ msgid "Warn about functions which might be candidates for __attribute__((pure))."
+ msgstr "Avisa sobre funciones que pueden ser candidatas para __attribute__((pure))."
+ 
+ #: common.opt:700
+-#, fuzzy
+-#| msgid "Warn about functions which might be candidates for __attribute__((noreturn))"
+ msgid "Warn about functions which might be candidates for __attribute__((noreturn))."
+ msgstr "Avisa sobre funciones que pueden ser candidatas para __attribute((noreturn))."
+ 
+ #: common.opt:704
+ msgid "Warn about C++ polymorphic types where adding final keyword would improve code quality."
+-msgstr ""
++msgstr "Advierte de tipos polimórficos en C++ cuando añadir la palabra clave final mejoraría la calidad del código."
+ 
+ #: common.opt:708
+ msgid "Warn about C++ virtual methods where adding final keyword would improve code quality."
+-msgstr ""
++msgstr "Advierte de métodos virtuales en C++ cuando añadir la palabra clave final mejoraría la calidad del código."
+ 
+ #: common.opt:712
+-#, fuzzy
+-#| msgid "Do not suppress warnings from system headers"
+ msgid "Do not suppress warnings from system headers."
+ msgstr "No suprime los avisos de los encabezados del sistema."
+ 
+ #: common.opt:716
+-#, fuzzy
+-#| msgid "Warn whenever a trampoline is generated"
+ msgid "Warn whenever a trampoline is generated."
+-msgstr "Avisa cuando se genera un trampolín."
++msgstr "Avisa siempre que se genera un trampolín."
+ 
+ #: common.opt:720
+-#, fuzzy
+-#| msgid "Warn if a comparison is always true or always false due to the limited range of the data type"
+ msgid "Warn if a comparison is always true or always false due to the limited range of the data type."
+ msgstr "Avisa si la comparación es siempre verdadera o siempre falsa debido al rango limitado del tipo de datos."
+ 
+ #: common.opt:724
+-#, fuzzy
+-#| msgid "Warn about uninitialized automatic variables"
+ msgid "Warn about uninitialized automatic variables."
+ msgstr "Avisa sobre variables automáticas sin inicializar."
+ 
+ #: common.opt:728
+-#, fuzzy
+-#| msgid "Warn about maybe uninitialized automatic variables"
+ msgid "Warn about maybe uninitialized automatic variables."
+ msgstr "Avisa sobre variables automáticas probablemente sin inicializar."
+ 
+ #: common.opt:736
+-#, fuzzy
+-#| msgid "Enable all -Wunused- warnings"
+ msgid "Enable all -Wunused- warnings."
+ msgstr "Activa todos los avisos -Wunused-."
+ 
+ #: common.opt:740
+-#, fuzzy
+-#| msgid "Warn when a function parameter is only set, otherwise unused"
+ msgid "Warn when a function parameter is only set, otherwise unused."
+ msgstr "Avisa cuando sólo se define un parámetro de función, y no se usa posteriormente."
+ 
+ #: common.opt:744
+-#, fuzzy
+-#| msgid "Warn when a variable is only set, otherwise unused"
+ msgid "Warn when a variable is only set, otherwise unused."
+ msgstr "Avisa cuando sólo se define una variable, y no se usa posteriormente."
+ 
+ #: common.opt:748
+-#, fuzzy
+-#| msgid "Warn when a function is unused"
+ msgid "Warn when a function is unused."
+ msgstr "Avisa cuando no se usa una función."
+ 
+ #: common.opt:752
+-#, fuzzy
+-#| msgid "Warn when a label is unused"
+ msgid "Warn when a label is unused."
+ msgstr "Avisa cuando no se usa una etiqueta."
+ 
+ #: common.opt:756
+-#, fuzzy
+-#| msgid "Warn when a function parameter is unused"
+ msgid "Warn when a function parameter is unused."
+ msgstr "Avisa cuando no se usa un parámetro de una función."
+ 
+ #: common.opt:760
+-#, fuzzy
+-#| msgid "Warn when an expression value is unused"
+ msgid "Warn when an expression value is unused."
+ msgstr "Avisa cuando no se usa un valor de una expresión."
+ 
+ #: common.opt:764
+-#, fuzzy
+-#| msgid "Warn when a variable is unused"
+ msgid "Warn when a variable is unused."
+ msgstr "Avisa cuando no se usa una variable."
+ 
+ #: common.opt:768
+-#, fuzzy
+-#| msgid "Warn in case profiles in -fprofile-use do not match"
+ msgid "Warn in case profiles in -fprofile-use do not match."
+ msgstr "Avisa en perfiles case en -fprofile-use que no coincidan."
+ 
+ #: common.opt:772
+-#, fuzzy
+-#| msgid "Warn when a vector operation is compiled outside the SIMD"
+ msgid "Warn when a vector operation is compiled outside the SIMD."
+ msgstr "Avisar cuando una operación vectorial se compila fuera del SIMD."
+ 
+ #: common.opt:788
+-#, fuzzy
+-#| msgid "-aux-info <file>\tEmit declaration information into <file>"
+ msgid "-aux-info <file>\tEmit declaration information into <file>."
+ msgstr "-aux-info <fichero>\tEmite la información de declaraciones en el <fichero>."
+ 
+ #: common.opt:807
+-#, fuzzy
+-#| msgid "-d<letters>\tEnable dumps from specific passes of the compiler"
+ msgid "-d<letters>\tEnable dumps from specific passes of the compiler."
+ msgstr "-d<letras>\tActiva los volcados de pasos específicos del compilador."
+ 
+ #: common.opt:811
+-#, fuzzy
+-#| msgid "-dumpbase <file>\tSet the file basename to be used for dumps"
+ msgid "-dumpbase <file>\tSet the file basename to be used for dumps."
+ msgstr "-dumpbase <fichero>\tEstablece el nombre base de fichero a usar para los volcados."
+ 
+ #: common.opt:815
+-#, fuzzy
+-#| msgid "-dumpdir <dir>\tSet the directory name to be used for dumps"
+ msgid "-dumpdir <dir>\tSet the directory name to be used for dumps."
+ msgstr "-dumpdir <dir>\tEstablece el nombre del directorio a usar para los volcados."
+ 
+ #: common.opt:884
+ msgid "The version of the C++ ABI in use."
+-msgstr ""
++msgstr "La versión de la ABI de C++ que se está usando."
+ 
+ #: common.opt:888
+ msgid "Aggressively optimize loops using language constraints."
+-msgstr ""
++msgstr "Optimiza los bucles de forma agresiva empleando restricciones del lenguaje."
+ 
+ #: common.opt:892
+-#, fuzzy
+-#| msgid "Align the start of functions"
+ msgid "Align the start of functions."
+ msgstr "Alinea el inicio de las funciones."
+ 
+ #: common.opt:899
+-#, fuzzy
+-#| msgid "Align labels which are only reached by jumping"
+ msgid "Align labels which are only reached by jumping."
+ msgstr "Alinea las etiquetas que solamente se alcanzan saltando."
+ 
+ #: common.opt:906
+-#, fuzzy
+-#| msgid "Align all labels"
+ msgid "Align all labels."
+ msgstr "Alinea todas las etiquetas."
+ 
+ #: common.opt:913
+-#, fuzzy
+-#| msgid "Align the start of loops"
+ msgid "Align the start of loops."
+ msgstr "Alinea el inicio de los bucles."
+ 
+ #: common.opt:936
+-#, fuzzy
+-#| msgid "Select the runtime"
+ msgid "Select what to sanitize."
+-msgstr "Selecciona el tiempo de ejecución."
++msgstr "Selecciona qué sanear."
+ 
+ #: common.opt:940
+ msgid "-fasan-shadow-offset=<number>\tUse custom shadow memory offset."
+@@ -14358,115 +13572,83 @@
+ 
+ #: common.opt:944
+ msgid "-fsanitize-sections=<sec1,sec2,...>\tSanitize global variables"
+-msgstr ""
++msgstr "-fsanitize-sections=<sec1,sec2,...>\tSanea las variables globales"
+ 
+ #: common.opt:949
+ msgid "After diagnosing undefined behavior attempt to continue execution."
+-msgstr ""
++msgstr "Tras el diagnóstico de comportamiento indefinido intenta continuar la ejecución."
+ 
+ #: common.opt:953
+-#, fuzzy
+-#| msgid "This switch is deprecated; use -Wextra instead"
+ msgid "This switch is deprecated; use -fsanitize-recover= instead."
+-msgstr "Esta opción es obsoleta; utilice en su lugar -Wextra."
++msgstr "Esta opción es obsoleta; utilice en su lugar -fsanitize-recover=."
+ 
+ #: common.opt:957
+ msgid "Use trap instead of a library function for undefined behavior sanitization."
+-msgstr ""
++msgstr "Usa trap en lugar de una función de biblioteca para sanear el comportamiento indefinido."
+ 
+ #: common.opt:961
+-#, fuzzy
+-#| msgid "Generate unwind tables that are exact at each instruction boundary"
+ msgid "Generate unwind tables that are exact at each instruction boundary."
+ msgstr "Genera tablas de desenredo que sean exactas en cada límite de instrucción."
+ 
+ #: common.opt:965
+-#, fuzzy
+-#| msgid "Generate auto-inc/dec instructions"
+ msgid "Generate auto-inc/dec instructions."
+ msgstr "Genera instrucciones auto-inc/dec."
+ 
+ #: common.opt:969
+ msgid "Use sample profile information for call graph node weights. The default"
+-msgstr ""
++msgstr "Usa información de perfil de muestra para los pesos de los nodos de los grafos de llamadas. Lo predeterminado"
+ 
+ #: common.opt:974
+-#, fuzzy
+-#| msgid "Use profiling information for branch probabilities"
+ msgid "Use sample profile information for call graph node weights. The profile"
+-msgstr "Usa la información de análisis de perfil para las probabilidades de ramificación"
++msgstr "Usa la información de perfil de muestra para los pesos de los nodos de los grafos de llamadas. El perfil"
+ 
+ #: common.opt:983
+-#, fuzzy
+-#| msgid "Generate code to check bounds before indexing arrays"
+ msgid "Generate code to check bounds before indexing arrays."
+-msgstr "Genera código para revisar los límites antes de indizar matrices."
++msgstr "Genera código para revisar los límites antes de indexar matrices."
+ 
+ #: common.opt:987
+-#, fuzzy
+-#| msgid "Replace add, compare, branch with branch on count register"
+ msgid "Replace add, compare, branch with branch on count register."
+ msgstr "Reemplaza add, compare, branch con branch en la cuenta de registros."
+ 
+ #: common.opt:991
+-#, fuzzy
+-#| msgid "Use profiling information for branch probabilities"
+ msgid "Use profiling information for branch probabilities."
+ msgstr "Usa la información de análisis de perfil para las probabilidades de ramificación."
+ 
+ #: common.opt:995
+-#, fuzzy
+-#| msgid "Perform branch target load optimization before prologue / epilogue threading"
+ msgid "Perform branch target load optimization before prologue / epilogue threading."
+ msgstr "Realiza optimización de carga de ramificación objetivo antes del hilo prólogo / epílogo."
+ 
+ #: common.opt:999
+-#, fuzzy
+-#| msgid "Perform branch target load optimization after prologue / epilogue threading"
+ msgid "Perform branch target load optimization after prologue / epilogue threading."
+ msgstr "Realiza optimización de carga de ramificación objetivo después del hilo prólogo / epílogo."
+ 
+ #: common.opt:1003
+-#, fuzzy
+-#| msgid "Restrict target load migration not to re-use registers in any basic block"
+ msgid "Restrict target load migration not to re-use registers in any basic block."
+ msgstr "Restringe que la migración de carga de objetivos no reuse registros en ningún bloque básico."
+ 
+ #: common.opt:1007
+-#, fuzzy
+-#| msgid "-fcall-saved-<register>\tMark <register> as being preserved across functions"
+ msgid "-fcall-saved-<register>\tMark <register> as being preserved across functions."
+ msgstr "-fcall-saved-<registro>\tMarca el <registro> como preservado entre funciones."
+ 
+ #: common.opt:1011
+-#, fuzzy
+-#| msgid "-fcall-used-<register>\tMark <register> as being corrupted by function calls"
+ msgid "-fcall-used-<register>\tMark <register> as being corrupted by function calls."
+ msgstr "-fcall-used-<registro>\tMarca el <registro> como corrupto por llamadas de función."
+ 
+ #: common.opt:1018
+-#, fuzzy
+-#| msgid "Save registers around function calls"
+ msgid "Save registers around function calls."
+ msgstr "Guarda registros alrededor de llamadas de función."
+ 
+ #: common.opt:1022
+-#, fuzzy
+-#| msgid "This switch is deprecated; use -Wextra instead"
+ msgid "This switch is deprecated; do not use."
+-msgstr "Esta opción es obsoleta; utilice en su lugar -Wextra."
++msgstr "Esta opción es obsoleta; no lo utilice."
+ 
+ #: common.opt:1026
+-#, fuzzy
+-#| msgid "Check the return value of new"
+ msgid "Check the return value of new in C++."
+-msgstr "Revisa el valor de devolución de new."
++msgstr "Revisa el valor de devolución de new en C++."
+ 
+ #: common.opt:1030
+-#, fuzzy
+-#| msgid "internal consistency failure"
+ msgid "Perform internal consistency checkings."
+-msgstr "falla interna de consistencia."
++msgstr "Realiza comprobaciones de consistencia internas."
+ 
+ #: common.opt:1034
+ msgid "Looks for opportunities to reduce stack adjustments and stack references."
+@@ -14473,68 +13655,46 @@
+ msgstr "Busca oportunidades para reducir los ajustes de pila y las referencias de pila."
+ 
+ #: common.opt:1038
+-#, fuzzy
+-#| msgid "Do not put uninitialized globals in the common section"
+ msgid "Do not put uninitialized globals in the common section."
+ msgstr "No pone globales sin inicializar en la sección común."
+ 
+ #: common.opt:1046
+-#, fuzzy
+-#| msgid "-fcompare-debug[=<opts>]\tCompile with and without e.g. -gtoggle, and compare the final-insns dump"
+ msgid "-fcompare-debug[=<opts>]\tCompile with and without e.g. -gtoggle, and compare the final-insns dump."
+ msgstr "-fcompare-debug[=<opts>]\tCompila con y sin p.e. -gtoggle, y compara el volcado de insns finales."
+ 
+ #: common.opt:1050
+-#, fuzzy
+-#| msgid "Run only the second compilation of -fcompare-debug"
+ msgid "Run only the second compilation of -fcompare-debug."
+ msgstr "Ejecuta sólo la segunda compilación de -fcompare-debug."
+ 
+ #: common.opt:1054
+-#, fuzzy
+-#| msgid "Perform comparison elimination after register allocation has finished"
+ msgid "Perform comparison elimination after register allocation has finished."
+ msgstr "Realiza la eliminación de comparaciones después de terminar el alojamiento de registros."
+ 
+ #: common.opt:1058
+-#, fuzzy
+-#| msgid "Do not perform optimizations increasing noticeably stack usage"
+ msgid "Do not perform optimizations increasing noticeably stack usage."
+ msgstr "No realizar optimizaciones que incrementan notablemente el uso de la pila."
+ 
+ #: common.opt:1062
+-#, fuzzy
+-#| msgid "Perform a register copy-propagation optimization pass"
+ msgid "Perform a register copy-propagation optimization pass."
+ msgstr "Realiza el paso de optimización de copia-propagación de registros."
+ 
+ #: common.opt:1066
+-#, fuzzy
+-#| msgid "Perform cross-jumping optimization"
+ msgid "Perform cross-jumping optimization."
+ msgstr "Realiza optimizaciones de saltos cruzados."
+ 
+ #: common.opt:1070
+-#, fuzzy
+-#| msgid "When running CSE, follow jumps to their targets"
+ msgid "When running CSE, follow jumps to their targets."
+ msgstr "Cuando se esté ejecutando CSE, sigue los saltos a sus objetivos."
+ 
+ #: common.opt:1078
+-#, fuzzy
+-#| msgid "Omit range reduction step when performing complex division"
+ msgid "Omit range reduction step when performing complex division."
+ msgstr "Omite el paso de reducción de rango al realizar divisiones complejas."
+ 
+ #: common.opt:1082
+-#, fuzzy
+-#| msgid "Complex multiplication and division follow Fortran rules"
+ msgid "Complex multiplication and division follow Fortran rules."
+ msgstr "La multiplicación y la división complejas siguen las reglas Fortran."
+ 
+ #: common.opt:1086
+-#, fuzzy
+-#| msgid "Place data items into their own section"
+ msgid "Place data items into their own section."
+ msgstr "Coloca los elementos de datos en su propia sección."
+ 
+@@ -14543,14 +13703,10 @@
+ msgstr "Enumera todos los contadores de depuración disponibles con sus límites y cuentas."
+ 
+ #: common.opt:1094
+-#, fuzzy
+-#| msgid "-fdbg-cnt=<counter>:<limit>[,<counter>:<limit>,...]\tSet the debug counter limit.   "
+ msgid "-fdbg-cnt=<counter>:<limit>[,<counter>:<limit>,...]\tSet the debug counter limit."
+ msgstr "-fdbg-cnt=<contador>:<límite>[,<contador>:<límite>,...]\tEstablece el límite del contador de depuración."
+ 
+ #: common.opt:1098
+-#, fuzzy
+-#| msgid "Map one directory name to another in debug information"
+ msgid "Map one directory name to another in debug information."
+ msgstr "Mapea un nombre de directorio a otro en la información de depuración."
+ 
+@@ -14559,58 +13715,52 @@
+ msgstr "Muestra la sección .debug_types al usar la información de depuración DWARF v4."
+ 
+ #: common.opt:1108
+-#, fuzzy
+-#| msgid "Defer popping functions args from stack until later"
+ msgid "Defer popping functions args from stack until later."
+ msgstr "Posterga la extracción de argumentos de funciones de la pila hasta más tarde."
+ 
+ #: common.opt:1112
+-#, fuzzy
+-#| msgid "Attempt to fill delay slots of branch instructions"
+ msgid "Attempt to fill delay slots of branch instructions."
+ msgstr "Intenta rellenar las ranuras de retraso de las instrucciones de ramificación."
+ 
+ #: common.opt:1116
+ msgid "Delete dead instructions that may throw exceptions."
+-msgstr ""
++msgstr "Borra instrucciones muertas que pueden lanzar excepciones."
+ 
+ #: common.opt:1120
+-#, fuzzy
+-#| msgid "Delete useless null pointer checks"
+ msgid "Delete useless null pointer checks."
+ msgstr "Borra las revisiones de punteros nulos sin uso."
+ 
+ #: common.opt:1124
+ msgid "Stream extra data to support more aggressive devirtualization in LTO local transformation mode."
+-msgstr ""
++msgstr "Hace fluir datos extra para permitir desvirtualización más agresiva en el modo de transformación local LTO."
+ 
+ #: common.opt:1128
+ #, fuzzy
+-#| msgid "Perform superblock formation via tail duplication"
+ msgid "Perform speculative devirtualization."
+-msgstr "Realiza la formación de superbloques a través de la duplicación de colas."
++msgstr "Realiza desvirtualización especulativa."
+ 
+ #: common.opt:1132
++#, fuzzy
+ msgid "Try to convert virtual calls to direct ones."
+ msgstr "Trata de convertir las llamadas virtuales a llamadas directas."
+ 
+ #: common.opt:1136
+ #, fuzzy
+-#| msgid "-fdiagnostics-show-location=[once|every-line]\tHow often to emit source location at the beginning of line-wrapped diagnostics"
+ msgid "-fdiagnostics-show-location=[once|every-line]\tHow often to emit source location at the beginning of line-wrapped diagnostics."
+ msgstr "-fdiagnostics-show-location=[once|every-line]\tIndica que tan seguido se debe emitir la ubicación del código al inicio de los diagnósticos con corte de línea."
+ 
+ #: common.opt:1153
++#, fuzzy
+ msgid "Show the source line with a caret indicating the column."
+-msgstr ""
++msgstr "Muestra la línea de código con un signo de intercalación para indicar la columna."
+ 
+ #: common.opt:1161
++#, fuzzy
+ msgid "-fdiagnostics-color=[never|always|auto]\tColorize diagnostics."
+-msgstr ""
++msgstr "-fdiagnostics-color=[never|always|auto]\tColorea los diagnósticos."
+ 
+ #: common.opt:1181
+ #, fuzzy
+-#| msgid "Amend appropriate diagnostic messages with the command line option that controls them"
+ msgid "Amend appropriate diagnostic messages with the command line option that controls them."
+ msgstr "Asocia adecuadamente los mensajes de diagnóstico con la opción de línea de orden que los controla."
+ 
+Index: gcc/po/fr.po
+===================================================================
+--- a/src/gcc/po/fr.po	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/po/fr.po	(.../branches/gcc-6-branch)
+@@ -133,7 +133,7 @@
+ "Project-Id-Version: gcc 6.2.0\n"
+ "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
+ "POT-Creation-Date: 2016-08-19 21:03+0000\n"
+-"PO-Revision-Date: 2016-12-16 19:16+0100\n"
++"PO-Revision-Date: 2016-12-23 15:39+0100\n"
+ "Last-Translator: Frédéric Marchal <fmarchal@perso.be>\n"
+ "Language-Team: French <traduc@traduc.org>\n"
+ "Language: fr\n"
+@@ -1636,9 +1636,8 @@
+ msgstr "attribut de fonction incohérent"
+ 
+ #: cif-code.def:129
+-#, fuzzy
+ msgid "caller function contains cilk spawn"
+-msgstr "la fonction appelante contient du généré cilk"
++msgstr "la fonction appelante contient au moins une fonction démarrée en parallèle par cilk"
+ 
+ #: cif-code.def:133
+ msgid "unreachable"
+@@ -7701,2188 +7700,1613 @@
+ msgstr "Préférer des accès par mots plutôt que des accès par octets."
+ 
+ #: config/mcore/mcore.opt:71
+-#, fuzzy
+-#| msgid "Maximum amount for a single stack increment operation"
+ msgid "Set the maximum amount for a single stack increment operation."
+-msgstr "Montant maximal pour une opération d'incrémentation simple de la pile"
++msgstr "Fixer le montant maximum pour une seule opération d'incrémentation de la pile."
+ 
+ #: config/mcore/mcore.opt:75
+-#, fuzzy
+-#| msgid "Always treat bit-field as int-sized"
+ msgid "Always treat bitfields as int-sized."
+-msgstr "Toujours traiter les champs de bits comme si la taille entière"
++msgstr "Toujours traiter les champs de bits comme ayant la taille d'un « int »."
+ 
+ #: config/linux-android.opt:23
+-#, fuzzy
+-#| msgid "Generate code for little endian"
+ msgid "Generate code for the Android platform."
+-msgstr "Générer du code pour un système à octets de poids faible"
++msgstr "Générer du code pour la plateforme Android."
+ 
+ #: config/mmix/mmix.opt:24
+-#, fuzzy
+-#| msgid "For intrinsics library: pass all parameters in registers"
+ msgid "For intrinsics library: pass all parameters in registers."
+-msgstr "Pour les bibliothèques intrinsèques : passer tous les paramètres par registre"
++msgstr "Pour les bibliothèques intrinsèques : passer tous les paramètres dans des registres."
+ 
+ #: config/mmix/mmix.opt:28
+-#, fuzzy
+-#| msgid "Use register stack for parameters and return value"
+ msgid "Use register stack for parameters and return value."
+-msgstr "Utiliser le registre de la pile pour les paramètres et la valeur retournée"
++msgstr "Utiliser la pile de registres pour les paramètres et la valeur retournée."
+ 
+ #: config/mmix/mmix.opt:32
+-#, fuzzy
+-#| msgid "Use call-clobbered registers for parameters and return value"
+ msgid "Use call-clobbered registers for parameters and return value."
+-msgstr "utiliser les registres d'appels maltraités pour les paramètres et les valeurs retournées"
++msgstr "Utiliser des registres écrasés durant l'appel pour les paramètres et les valeurs retournées."
+ 
+ #: config/mmix/mmix.opt:37
+-#, fuzzy
+-#| msgid "Use epsilon-respecting floating point compare instructions"
+ msgid "Use epsilon-respecting floating point compare instructions."
+-msgstr "Utiliser un epsilon respectant les instructions de comparaison en virgule flottante"
++msgstr "Utiliser des instructions de comparaisons en virgule flottante qui respectent l'epsilon."
+ 
+ #: config/mmix/mmix.opt:41
+-#, fuzzy
+-#| msgid "Use zero-extending memory loads, not sign-extending ones"
+ msgid "Use zero-extending memory loads, not sign-extending ones."
+-msgstr "utiliser des chargements mémoire avec zéro extension, pas celles avec signe d'extension"
++msgstr "Utiliser des chargements mémoire qui étendent les zéros au lieu de celles qui étendent le signe."
+ 
+ #: config/mmix/mmix.opt:45
+-#, fuzzy
+-#| msgid "Generate divide results with reminder having the same sign as the divisor (not the dividend)"
+ msgid "Generate divide results with reminder having the same sign as the divisor (not the dividend)."
+-msgstr "générer des résultats de division avec reste ayant le même signe que le diviseur (pas le dividende)"
++msgstr "Générer des résultats de divisions où le reste a le même signe que le diviseur (pas le dividende)."
+ 
+ #: config/mmix/mmix.opt:49
+-#, fuzzy
+-#| msgid "Prepend global symbols with \":\" (for use with PREFIX)"
+ msgid "Prepend global symbols with \":\" (for use with PREFIX)."
+-msgstr "pré ajouter les symboles globaux avec «:» (pour l'utilisation avec PREFIX)"
++msgstr "Préfixer les symboles globaux avec « : » (pour l'utilisation avec PREFIX)."
+ 
+ #: config/mmix/mmix.opt:53
+-#, fuzzy
+-#| msgid "Do not provide a default start-address 0x100 of the program"
+ msgid "Do not provide a default start-address 0x100 of the program."
+-msgstr "Ne pas fournir d'adresse de départ par défaut 0x100 du programme"
++msgstr "Ne pas fournir d'adresse de départ par défaut 0x100 du programme."
+ 
+ #: config/mmix/mmix.opt:57
+-#, fuzzy
+-#| msgid "Link to emit program in ELF format (rather than mmo)"
+ msgid "Link to emit program in ELF format (rather than mmo)."
+-msgstr "Faire l'édition de liens pour produire le programme en format ELF (au lieu de mmo)"
++msgstr "Faire l'édition de liens pour produire le programme au format ELF (au lieu de mmo)."
+ 
+ #: config/mmix/mmix.opt:61
+-#, fuzzy
+-#| msgid "Use P-mnemonics for branches statically predicted as taken"
+ msgid "Use P-mnemonics for branches statically predicted as taken."
+-msgstr "Utiliser les mnémoniques P pour les branchements statiquement prévus à être pris"
++msgstr "Utiliser les mnémoniques P pour les branchements statiquement prévus comme étant pris."
+ 
+ #: config/mmix/mmix.opt:65
+-#, fuzzy
+-#| msgid "Don't use P-mnemonics for branches"
+ msgid "Don't use P-mnemonics for branches."
+-msgstr "Ne pas utiliser les mnémoniques P pour les branchements"
++msgstr "Ne pas utiliser les mnémoniques P pour les branchements."
+ 
+ #: config/mmix/mmix.opt:79
+-#, fuzzy
+-#| msgid "Use addresses that allocate global registers"
+ msgid "Use addresses that allocate global registers."
+-msgstr "Utiliser les adresses qui allouent des registres globaux"
++msgstr "Utiliser les adresses qui allouent des registres globaux."
+ 
+ #: config/mmix/mmix.opt:83
+-#, fuzzy
+-#| msgid "Do not use addresses that allocate global registers"
+ msgid "Do not use addresses that allocate global registers."
+-msgstr "Ne pas utiliser des adresses qui allouent des registres globaux"
++msgstr "Ne pas utiliser des adresses qui allouent des registres globaux."
+ 
+ #: config/mmix/mmix.opt:87
+-#, fuzzy
+-#| msgid "Generate a single exit point for each function"
+ msgid "Generate a single exit point for each function."
+-msgstr "Générer un point de sortie simple pour chaque fonction"
++msgstr "Générer un point de sortie unique pour chaque fonction."
+ 
+ #: config/mmix/mmix.opt:91
+-#, fuzzy
+-#| msgid "Do not generate a single exit point for each function"
+ msgid "Do not generate a single exit point for each function."
+-msgstr "Ne pas générer un point de sortie simple pour chaque fonction"
++msgstr "Ne pas générer un point de sortie unique pour chaque fonction."
+ 
+ #: config/mmix/mmix.opt:95
+-#, fuzzy
+-#| msgid "Set start-address of the program"
+ msgid "Set start-address of the program."
+-msgstr "Adresse de départ du programme fixée"
++msgstr "Fixer l'adresse de départ du programme."
+ 
+ #: config/mmix/mmix.opt:99
+-#, fuzzy
+-#| msgid "Set start-address of data"
+ msgid "Set start-address of data."
+-msgstr "Adresse de départ des données fixée"
++msgstr "Fixer l'adresse de départ des données."
+ 
+ #: config/darwin.opt:114
+-#, fuzzy
+-#| msgid "Generate code using byte writes"
+ msgid "Generate compile-time CFString objects."
+-msgstr "Générer le code en utilisant des écritures par octets"
++msgstr "Générer les objets CFString à la compilation."
+ 
+ #: config/darwin.opt:211
+ msgid "Warn if constant CFString objects contain non-portable characters."
+-msgstr ""
++msgstr "Avertir si des objets CFString constants contiennent des caractères non portables."
+ 
+ #: config/darwin.opt:216
+ msgid "Generate AT&T-style stubs for Mach-O."
+-msgstr ""
++msgstr "Générer des stubs dans le style AT&T pour Mach-O."
+ 
+ #: config/darwin.opt:220
+-#, fuzzy
+-#| msgid "Generate code suitable for executables (NOT shared libs)"
+ msgid "Generate code suitable for executables (NOT shared libs)."
+-msgstr "Générer du code adapté pour les exécutables (PAS les librairies partagées)"
++msgstr "Générer du code adapté pour les exécutables (PAS pour les librairies partagées)."
+ 
+ #: config/darwin.opt:224
+-#, fuzzy
+-#| msgid "Generate code suitable for executables (NOT shared libs)"
+ msgid "Generate code suitable for fast turn around debugging."
+-msgstr "Générer du code adapté pour les exécutables (PAS les librairies partagées)"
++msgstr "Générer du code adapté pour un débogage avec cycle court."
+ 
+ #: config/darwin.opt:232
+ msgid "The earliest MacOS X version on which this program will run."
+-msgstr ""
++msgstr "La version la plus ancienne de MacOS X sur laquelle ce programme tournera."
+ 
+ #: config/darwin.opt:236
+-#, fuzzy
+-#| msgid "Set sizeof(bool) to 1"
+ msgid "Set sizeof(bool) to 1."
+-msgstr "Affecter sizeof(bool) à 1"
++msgstr "Faire en sorte que sizeof(bool) vaille 1."
+ 
+ #: config/darwin.opt:240
+-#, fuzzy
+-#| msgid "Generate code for little endian"
+ msgid "Generate code for darwin loadable kernel extensions."
+-msgstr "Générer du code pour un système à octets de poids faible"
++msgstr "Générer du code pour des extensions à charger dans le noyau de darwin."
+ 
+ #: config/darwin.opt:244
+-#, fuzzy
+-#| msgid "Generate code for the specified chip or CPU version"
+ msgid "Generate code for the kernel or loadable kernel extensions."
+-msgstr "Générer le code pour la version de processeur ou de circuit spécifiée"
++msgstr "Générer du code pour le noyau ou pour des extensions à charger dans le noyau."
+ 
+ #: config/darwin.opt:248
+-#, fuzzy
+-#| msgid "-idirafter <dir>\tAdd <dir> to the end of the system include path"
+ msgid "-iframework <dir>\tAdd <dir> to the end of the system framework include path."
+-msgstr "-idirafter <répertoire>\tajouter <répertoire> à la fin du chemin système d'inclusion"
++msgstr "-iframework <répertoire>\tAjouter <répertoire> à la fin du chemin d'inclusion du framework système."
+ 
+ #: config/bfin/bfin.opt:40 config/msp430/msp430.opt:3 config/c6x/c6x.opt:38
+ #: config/mep/mep.opt:143
+-#, fuzzy
+-#| msgid "Use the WindISS simulator"
+ msgid "Use simulator runtime."
+-msgstr "Utiliser le simulateur WindISS"
++msgstr "Produire l'exécutable pour un simulateur."
+ 
+ #: config/bfin/bfin.opt:44 config/arm/arm.opt:106
+-#, fuzzy
+-#| msgid "Specify the name of the target CPU"
+ msgid "Specify the name of the target CPU."
+-msgstr "Spécifier le nom du processeur cible"
++msgstr "Spécifier le nom du processeur cible."
+ 
+ #: config/bfin/bfin.opt:48
+-#, fuzzy
+-#| msgid "Omit the frame pointer in leaf functions"
+ msgid "Omit frame pointer for leaf functions."
+-msgstr "Omettre le pointeur de trame dans les fonctions feuilles"
++msgstr "Omettre le pointeur de trame dans les fonctions feuilles."
+ 
+ #: config/bfin/bfin.opt:52
+ msgid "Program is entirely located in low 64k of memory."
+-msgstr ""
++msgstr "Le programme est entièrement situé dans les 64k inférieurs de la mémoire."
+ 
+ #: config/bfin/bfin.opt:56
+ msgid "Work around a hardware anomaly by adding a number of NOPs before a"
+-msgstr ""
++msgstr "Contourner une anomalie du matériel en ajoutant plusieurs NOP devant une instruction CSYNC ou SSYNC."
+ 
+ #: config/bfin/bfin.opt:61
+ msgid "Avoid speculative loads to work around a hardware anomaly."
+-msgstr ""
++msgstr "Éviter les chargements spéculatifs pour contourner une anomalie matérielle."
+ 
+ #: config/bfin/bfin.opt:65
+-#, fuzzy
+-#| msgid "Enable ID based shared library"
+ msgid "Enabled ID based shared library."
+-msgstr "Autoriser les identificateurs de librairies partagées de base"
++msgstr "Autoriser les bibliothèques partagées basées sur un ID."
+ 
+ #: config/bfin/bfin.opt:69
+ msgid "Generate code that won't be linked against any other ID shared libraries,"
+-msgstr ""
++msgstr "Générer du code qui ne sera pas lié avec une autre bibliothèque partagée par son ID mais qui pourra être utilisé comme bibliothèque partagée."
+ 
+ #: config/bfin/bfin.opt:74 config/m68k/m68k.opt:171
+-#, fuzzy
+-#| msgid "ID of shared library to build"
+ msgid "ID of shared library to build."
+-msgstr "Identification de librairie partagé à construire"
++msgstr "Identification de la bibliothèque partagée à construire."
+ 
+ #: config/bfin/bfin.opt:78 config/m68k/m68k.opt:167
+-#, fuzzy
+-#| msgid "Enable separate data segment"
+ msgid "Enable separate data segment."
+-msgstr "Autoriser des segments de données séparés"
++msgstr "Activer des segments de données séparés."
+ 
+ #: config/bfin/bfin.opt:82 config/c6x/c6x.opt:63
+ msgid "Avoid generating pc-relative calls; use indirection."
+-msgstr ""
++msgstr "Éviter des générer des appels relatifs au PC; utiliser des indirections."
+ 
+ #: config/bfin/bfin.opt:86
+-#, fuzzy
+-#| msgid "Use the Xtensa floating-point unit"
+ msgid "Link with the fast floating-point library."
+-msgstr "Utiliser l'unité matérielle pour virgule flottante Xtensa"
++msgstr "Lier avec la bibliothèque en virgule flottante rapide."
+ 
+ #: config/bfin/bfin.opt:90 config/frv/frv.opt:130
+-#, fuzzy
+-#| msgid "Enable function profiling"
+ msgid "Enable Function Descriptor PIC mode."
+-msgstr "Autoriser le profilage de fonction"
++msgstr "Activer le mode PIC avec descripteurs de fonctions."
+ 
+ #: config/bfin/bfin.opt:94 config/frv/frv.opt:162
+-#, fuzzy
+-#| msgid "Enable use of RTPS instruction"
+ msgid "Enable inlining of PLT in function calls."
+-msgstr "Autoriser l'utilisation de l'instruction RTPS"
++msgstr "Activer la mise en ligne de PLT dans les appels de fonctions."
+ 
+ #: config/bfin/bfin.opt:98
+ msgid "Do stack checking using bounds in L1 scratch memory."
+-msgstr ""
++msgstr "Vérifier la pile en utilisant des limites dans la mémoire temporaire L1."
+ 
+ #: config/bfin/bfin.opt:102
+-#, fuzzy
+-#| msgid "Enable multicore support"
+ msgid "Enable multicore support."
+-msgstr "Activer le support multicœur"
++msgstr "Activer le support multicœur."
+ 
+ #: config/bfin/bfin.opt:106
+-#, fuzzy
+-#| msgid "Build for Core A"
+ msgid "Build for Core A."
+-msgstr "Compiler pour Core A"
++msgstr "Compiler pour le cœur A."
+ 
+ #: config/bfin/bfin.opt:110
+-#, fuzzy
+-#| msgid "Build for Core B"
+ msgid "Build for Core B."
+-msgstr "Compiler pour Core B"
++msgstr "Compiler pour le cœur B."
+ 
+ #: config/bfin/bfin.opt:114
+-#, fuzzy
+-#| msgid "Build for SDRAM"
+ msgid "Build for SDRAM."
+-msgstr "compiler pour SDRAM"
++msgstr "Compiler pour SDRAM."
+ 
+ #: config/bfin/bfin.opt:118
+ msgid "Assume ICPLBs are enabled at runtime."
+-msgstr ""
++msgstr "Supposer que les ICPLB sont activés à l'exécution."
+ 
+ #: config/m68k/m68k-tables.opt:25
+ msgid "Known M68K CPUs (for use with the -mcpu= option):"
+-msgstr ""
++msgstr "Processeurs M68K connus (à utiliser avec l'option -mcpu=):"
+ 
+ #: config/m68k/m68k-tables.opt:365
+ msgid "Known M68K microarchitectures (for use with the -mtune= option):"
+-msgstr ""
++msgstr "Microarchitectures M68K connues (à utiliser avec l'option -mtune=):"
+ 
+ #: config/m68k/m68k-tables.opt:411
+ msgid "Known M68K ISAs (for use with the -march= option):"
+-msgstr ""
++msgstr "ISA connues pour M68K (à utiliser avec l'option -march=):"
+ 
+ #: config/m68k/ieee.opt:24 config/i386/i386.opt:358
+-#, fuzzy
+-#| msgid "Use IEEE math for fp comparisons"
+ msgid "Use IEEE math for fp comparisons."
+-msgstr "Utiliser les mathématiques IEEE pour les comparaisons FP"
++msgstr "Utiliser les mathématiques IEEE pour les comparaisons en virgule flottantes."
+ 
+ #: config/m68k/m68k.opt:30
+-#, fuzzy
+-#| msgid "Generate code for a 520X"
+ msgid "Generate code for a 520X."
+-msgstr "Générer du code pour un 520X"
++msgstr "Générer du code pour un 520X."
+ 
+ #: config/m68k/m68k.opt:34
+-#, fuzzy
+-#| msgid "Generate code for a 5206e"
+ msgid "Generate code for a 5206e."
+-msgstr "Générer du code pour un 5206e"
++msgstr "Générer du code pour un 5206e."
+ 
+ #: config/m68k/m68k.opt:38
+-#, fuzzy
+-#| msgid "Generate code for a 528x"
+ msgid "Generate code for a 528x."
+-msgstr "Générer du code pour un 528x"
++msgstr "Générer du code pour un 528x."
+ 
+ #: config/m68k/m68k.opt:42
+-#, fuzzy
+-#| msgid "Generate code for a 5307"
+ msgid "Generate code for a 5307."
+-msgstr "Générer du code pour un 5307"
++msgstr "Générer du code pour un 5307."
+ 
+ #: config/m68k/m68k.opt:46
+-#, fuzzy
+-#| msgid "Generate code for a 5407"
+ msgid "Generate code for a 5407."
+-msgstr "Générer du code pour un 5407"
++msgstr "Générer du code pour un 5407."
+ 
+ #: config/m68k/m68k.opt:50 config/m68k/m68k.opt:111
+-#, fuzzy
+-#| msgid "Generate code for a 68000"
+ msgid "Generate code for a 68000."
+-msgstr "Générer le code pour un 68000"
++msgstr "Générer le code pour un 68000."
+ 
+ #: config/m68k/m68k.opt:54
+-#, fuzzy
+-#| msgid "Generate code for a 68010"
+ msgid "Generate code for a 68010."
+-msgstr "Générer le code pour un 68010"
++msgstr "Générer le code pour un 68010."
+ 
+ #: config/m68k/m68k.opt:58 config/m68k/m68k.opt:115
+-#, fuzzy
+-#| msgid "Generate code for a 68020"
+ msgid "Generate code for a 68020."
+-msgstr "Générer le code pour un 68020"
++msgstr "Générer le code pour un 68020."
+ 
+ #: config/m68k/m68k.opt:62
+-#, fuzzy
+-#| msgid "Generate code for a 68040, without any new instructions"
+ msgid "Generate code for a 68040, without any new instructions."
+-msgstr "Générer du code pour un 68040 sans les nouvelles instructions"
++msgstr "Générer du code pour un 68040 sans les nouvelles instructions."
+ 
+ #: config/m68k/m68k.opt:66
+-#, fuzzy
+-#| msgid "Generate code for a 68060, without any new instructions"
+ msgid "Generate code for a 68060, without any new instructions."
+-msgstr "Générer du code pour un 68060 sans les nouvelles instructions"
++msgstr "Générer du code pour un 68060 sans les nouvelles instructions."
+ 
+ #: config/m68k/m68k.opt:70
+-#, fuzzy
+-#| msgid "Generate code for a 68030"
+ msgid "Generate code for a 68030."
+-msgstr "Générer du code pour un 68030"
++msgstr "Générer du code pour un 68030."
+ 
+ #: config/m68k/m68k.opt:74
+-#, fuzzy
+-#| msgid "Generate code for a 68040"
+ msgid "Generate code for a 68040."
+-msgstr "Générer du code pour un 68040"
++msgstr "Générer du code pour un 68040."
+ 
+ #: config/m68k/m68k.opt:78
+-#, fuzzy
+-#| msgid "Generate code for a 68060"
+ msgid "Generate code for a 68060."
+-msgstr "Générer du code pour un 68060"
++msgstr "Générer du code pour un 68060."
+ 
+ #: config/m68k/m68k.opt:82
+-#, fuzzy
+-#| msgid "Generate code for a 68302"
+ msgid "Generate code for a 68302."
+-msgstr "Générer du code pour un 68302"
++msgstr "Générer du code pour un 68302."
+ 
+ #: config/m68k/m68k.opt:86
+-#, fuzzy
+-#| msgid "Generate code for a 68332"
+ msgid "Generate code for a 68332."
+-msgstr "Générer du code pour un 68332"
++msgstr "Générer du code pour un 68332."
+ 
+ #: config/m68k/m68k.opt:91
+-#, fuzzy
+-#| msgid "Generate code for a 68851"
+ msgid "Generate code for a 68851."
+-msgstr "Générer le code pour un 68851"
++msgstr "Générer le code pour un 68851."
+ 
+ #: config/m68k/m68k.opt:95
+-#, fuzzy
+-#| msgid "Use hardware floating point instructions"
+ msgid "Generate code that uses 68881 floating-point instructions."
+-msgstr "Utiliser les instructions matérielles en virgule flottante"
++msgstr "Générer du code qui utilise les instructions en virgule flottantes du 68881."
+ 
+ #: config/m68k/m68k.opt:99
+-#, fuzzy
+-#| msgid "Align variables on a 32-bit boundary"
+ msgid "Align variables on a 32-bit boundary."
+-msgstr "Aligner les variables sur des frontières de 32 bits"
++msgstr "Aligner les variables sur des frontières de 32 bits."
+ 
+ #: config/m68k/m68k.opt:103 config/arm/arm.opt:81 config/nios2/nios2.opt:570
+ #: config/nds32/nds32.opt:66 config/c6x/c6x.opt:67
+-#, fuzzy
+-#| msgid "Specify the name of the target architecture"
+ msgid "Specify the name of the target architecture."
+-msgstr "Spécifier le nom de l'architecture cible"
++msgstr "Spécifier le nom de l'architecture cible."
+ 
+ #: config/m68k/m68k.opt:107
+-#, fuzzy
+-#| msgid "Use the bit-field instructions"
+ msgid "Use the bit-field instructions."
+-msgstr "Utiliser les instructions de champs de bits"
++msgstr "Utiliser les instructions de champs de bits."
+ 
+ #: config/m68k/m68k.opt:119
+-#, fuzzy
+-#| msgid "Generate code for the M*Core M340"
+ msgid "Generate code for a ColdFire v4e."
+-msgstr "Générer du code pour M*Core M340"
++msgstr "Générer du code pour un ColdFire v4e."
+ 
+ #: config/m68k/m68k.opt:123
+-#, fuzzy
+-#| msgid "Specify the target CPU"
+ msgid "Specify the target CPU."
+-msgstr "Spécifier le processeur cible"
++msgstr "Spécifier le processeur cible."
+ 
+ #: config/m68k/m68k.opt:127
+-#, fuzzy
+-#| msgid "Generate code for a cpu32"
+ msgid "Generate code for a cpu32."
+-msgstr "Générer du code pour un cpu32"
++msgstr "Générer du code pour un cpu32."
+ 
+ #: config/m68k/m68k.opt:131
+-#, fuzzy
+-#| msgid "Use hardware quad fp instructions"
+ msgid "Use hardware division instructions on ColdFire."
+-msgstr "Utiliser les instructions matérielles quad FP"
++msgstr "Utiliser les instructions de divisions matérielles sur un ColdFire."
+ 
+ #: config/m68k/m68k.opt:135
+-#, fuzzy
+-#| msgid "Generate code for a Fido A"
+ msgid "Generate code for a Fido A."
+-msgstr "Générer le code pour un Fido A"
++msgstr "Générer le code pour un Fido A."
+ 
+ #: config/m68k/m68k.opt:139
+-#, fuzzy
+-#| msgid "Use hardware floating point instructions"
+ msgid "Generate code which uses hardware floating point instructions."
+-msgstr "Utiliser les instructions matérielles en virgule flottante"
++msgstr "Générer du code qui utilise les instructions en virgule flottantes matérielles."
+ 
+ #: config/m68k/m68k.opt:143
+-#, fuzzy
+-#| msgid "Enable ID based shared library"
+ msgid "Enable ID based shared library."
+-msgstr "Autoriser les identificateurs de librairies partagées de base"
++msgstr "Activer la bibliothèque partagée basée sur un ID."
+ 
+ #: config/m68k/m68k.opt:147
+-#, fuzzy
+-#| msgid "Do not use the bit-field instructions"
+ msgid "Do not use the bit-field instructions."
+-msgstr "Ne pas utiliser les instructions de champs de bits"
++msgstr "Ne pas utiliser les instructions de champs de bits."
+ 
+ #: config/m68k/m68k.opt:151
+-#, fuzzy
+-#| msgid "Use normal calling convention"
+ msgid "Use normal calling convention."
+-msgstr "Utiliser la convention normale d'appels"
++msgstr "Utiliser la convention d'appels normale."
+ 
+ #: config/m68k/m68k.opt:155
+-#, fuzzy
+-#| msgid "Consider type 'int' to be 32 bits wide"
+ msgid "Consider type 'int' to be 32 bits wide."
+-msgstr "Considérer le type « int » comme ayant une largeur de 32 bits"
++msgstr "Considérer le type « int » comme ayant une largeur de 32 bits."
+ 
+ #: config/m68k/m68k.opt:159
+-#, fuzzy
+-#| msgid "Generate pc-relative code"
+ msgid "Generate pc-relative code."
+-msgstr "Générer du code relatif au compteur de programme (PC)"
++msgstr "Générer du code relatif au compteur de programme (PC)."
+ 
+ #: config/m68k/m68k.opt:163
+-#, fuzzy
+-#| msgid "Use different calling convention using 'rtd'"
+ msgid "Use different calling convention using 'rtd'."
+-msgstr "Utiliser une convention différente d'appel en utilisant « rtd »"
++msgstr "Utiliser une convention d'appel différente en utilisant « rtd »."
+ 
+ #: config/m68k/m68k.opt:175
+-#, fuzzy
+-#| msgid "Consider type 'int' to be 16 bits wide"
+ msgid "Consider type 'int' to be 16 bits wide."
+-msgstr "Considérer le type « int » comme ayant une largeur de 16 bits"
++msgstr "Considérer le type « int » comme ayant une largeur de 16 bits."
+ 
+ #: config/m68k/m68k.opt:179
+-#, fuzzy
+-#| msgid "Generate code with library calls for floating point"
+ msgid "Generate code with library calls for floating point."
+-msgstr "Générer du code avec les appels de bibliothèques pour la virgule flottante"
++msgstr "Générer du code avec des appels de bibliothèque pour la virgule flottante."
+ 
+ #: config/m68k/m68k.opt:183
+-#, fuzzy
+-#| msgid "Do not use unaligned memory references"
+ msgid "Do not use unaligned memory references."
+-msgstr "Ne pas utiliser des références mémoire non alignées"
++msgstr "Ne pas utiliser des références mémoire non alignées."
+ 
+ #: config/m68k/m68k.opt:187
+-#, fuzzy
+-#| msgid "Specify the name of the target architecture"
+ msgid "Tune for the specified target CPU or architecture."
+-msgstr "Spécifier le nom de l'architecture cible"
++msgstr "Ajuster pour le processeur ou l'architecture cible spécifiée."
+ 
+ #: config/m68k/m68k.opt:191
+ msgid "Support more than 8192 GOT entries on ColdFire."
+-msgstr ""
++msgstr "Supporter plus de 8192 entrées dans la GOT d'un ColdFire."
+ 
+ #: config/m68k/m68k.opt:195
+ msgid "Support TLS segment larger than 64K."
+-msgstr ""
++msgstr "Supporter des segments TLS plus grands que 64K."
+ 
+ #: config/m32c/m32c.opt:23
+-#, fuzzy
+-#| msgid "Use the WindISS simulator"
+ msgid "-msim\tUse simulator runtime."
+-msgstr "Utiliser le simulateur WindISS"
++msgstr "-msim\tProduire l'exécutable pour un simulateur."
+ 
+ #: config/m32c/m32c.opt:27
+ msgid "-mcpu=r8c\tCompile code for R8C variants."
+-msgstr ""
++msgstr "-mcpu=r8c\tCompiler le code pour les variantes R8C."
+ 
+ #: config/m32c/m32c.opt:31
+ msgid "-mcpu=m16c\tCompile code for M16C variants."
+-msgstr ""
++msgstr "-mcpu=m16c\tCompiler le code pour les variantes M16C."
+ 
+ #: config/m32c/m32c.opt:35
+ msgid "-mcpu=m32cm\tCompile code for M32CM variants."
+-msgstr ""
++msgstr "-mcpu=m32cm\tCompiler le code pour les variantes M32CM."
+ 
+ #: config/m32c/m32c.opt:39
+ msgid "-mcpu=m32c\tCompile code for M32C variants."
+-msgstr ""
++msgstr "-mcpu=m32c\tCompiler le code pour les variantes M32C."
+ 
+ #: config/m32c/m32c.opt:43
+ msgid "-memregs=\tNumber of memreg bytes (default: 16, range: 0..16)."
+-msgstr ""
++msgstr "-memregs=\tLe nombre d'octets memreg (par défaut: 16, plage: 0..16)."
+ 
+ #: config/msp430/msp430.opt:7
+ msgid "Force assembly output to always use hex constants."
+-msgstr ""
++msgstr "Forcer la sortie en assembleur à toujours utiliser des constantes en hexadécimal."
+ 
+ #: config/msp430/msp430.opt:11
+-#, fuzzy
+-#| msgid "Specify the MCU name"
+ msgid "Specify the MCU to build for."
+-msgstr "Spécifier le nom du MCU"
++msgstr "Spécifier le MCU pour lequel compiler."
+ 
+ #: config/msp430/msp430.opt:15
+ msgid "Warn if an MCU name is unrecognised or conflicts with other options (default: on)."
+-msgstr ""
++msgstr "Avertir si le nom d'un MCU n'est pas reconnu ou entre en conflit avec d'autres options (défaut: on)."
+ 
+ #: config/msp430/msp430.opt:19
+-#, fuzzy
+-#| msgid "Specify the MCU name"
+ msgid "Specify the ISA to build for: msp430, msp430x, msp430xv2."
+-msgstr "Spécifier le nom du MCU"
++msgstr "Spécifier l'ISA pour laquelle compiler: msp430, msp430x, msp430xv2."
+ 
+ #: config/msp430/msp430.opt:23
+ msgid "Select large model - 20-bit addresses/pointers."
+-msgstr ""
++msgstr "Sélectionner le modèle large – adresses/pointeurs sur 20 bits."
+ 
+ #: config/msp430/msp430.opt:27
+ msgid "Select small model - 16-bit addresses/pointers (default)."
+-msgstr ""
++msgstr "Sélectionner le modèle court – adresses/pointeurs sur 16 bits (défaut)."
+ 
+ #: config/msp430/msp430.opt:31
+ msgid "Optimize opcode sizes at link time."
+-msgstr ""
++msgstr "Optimiser la taille des opcodes lors de la liaison."
+ 
+ #: config/msp430/msp430.opt:38
+ msgid "Use a minimum runtime (no static initializers or ctors) for memory-constrained devices."
+-msgstr ""
++msgstr "Utiliser un moteur d'exécution (pas d'initialisations ni de créateurs statiques) pour les périphériques ayant une mémoire limitée."
+ 
+ #: config/msp430/msp430.opt:45
+ msgid "Specify the type of hardware multiply to support."
+-msgstr ""
++msgstr "Spécifier le type de multiplication matérielle à supporter."
+ 
+ #: config/msp430/msp430.opt:67
+ msgid "Specify whether functions should be placed into low or high memory."
+-msgstr ""
++msgstr "Spécifier si les fonctions doivent être placées en mémoire basse ou haute."
+ 
+ #: config/msp430/msp430.opt:71
+ msgid "Specify whether variables should be placed into low or high memory."
+-msgstr ""
++msgstr "Spécifier si les variables doivent être placées en mémoire basse ou haute."
+ 
+ #: config/msp430/msp430.opt:90
+ msgid "Passes on a request to the assembler to enable fixes for various silicon errata."
+-msgstr ""
++msgstr "Passer une requête à l'assembleur pour corriger divers erratas du silicium."
+ 
+ #: config/msp430/msp430.opt:94
+ msgid "Passes on a request to the assembler to warn about various silicon errata."
+-msgstr ""
++msgstr "Passer une requête à l'assembleur pour avertir à propos de divers erratas du silicium."
+ 
+ #: config/aarch64/aarch64.opt:40
+ msgid "The possible TLS dialects:"
+-msgstr ""
++msgstr "Les dialectes TLS possibles:"
+ 
+ #: config/aarch64/aarch64.opt:52
+ msgid "The code model option names for -mcmodel:"
+-msgstr ""
++msgstr "Les noms d'options du modèle de code pour -mcmodel:"
+ 
+ #: config/aarch64/aarch64.opt:65 config/arm/arm.opt:94
+ #: config/microblaze/microblaze.opt:60
+-#, fuzzy
+-#| msgid "Assume target CPU is configured as big endian"
+ msgid "Assume target CPU is configured as big endian."
+-msgstr "Présumer que le processeur cible est un système à octets de poids fort"
++msgstr "Supposer que le processeur cible est configuré comme gros boutiste."
+ 
+ #: config/aarch64/aarch64.opt:69
+-#, fuzzy
+-#| msgid "Generate code which uses the FPU"
+ msgid "Generate code which uses only the general registers."
+-msgstr "Générer du code qui utilise le FPU"
++msgstr "Générer du code qui n'utilise que des registres généraux."
+ 
+ #: config/aarch64/aarch64.opt:73
+ msgid "Workaround for ARM Cortex-A53 Erratum number 835769."
+-msgstr ""
++msgstr "Correctif pour l'erratum numéro 835769 de l'ARM Cortex-A53."
+ 
+ #: config/aarch64/aarch64.opt:77
+ msgid "Workaround for ARM Cortex-A53 Erratum number 843419."
+-msgstr ""
++msgstr "Correctif pour l'erratum numéro 843419 de l'ARM Cortex-A53."
+ 
+ #: config/aarch64/aarch64.opt:81 config/arm/arm.opt:155
+ #: config/microblaze/microblaze.opt:64
+-#, fuzzy
+-#| msgid "Assume target CPU is configured as little endian"
+ msgid "Assume target CPU is configured as little endian."
+-msgstr "Présumer que le processeur cible est un système à octets de poids faible"
++msgstr "Supposer que le processeur cible est configuré comme petit boutiste."
+ 
+ #: config/aarch64/aarch64.opt:85
+-#, fuzzy
+-#| msgid "Specify the MCU name"
+ msgid "Specify the code model."
+-msgstr "Spécifier le nom du MCU"
++msgstr "Spécifier le modèle de code."
+ 
+ #: config/aarch64/aarch64.opt:89
+-#, fuzzy
+-#| msgid "Don't assume that unaligned accesses are handled by the system"
+ msgid "Don't assume that unaligned accesses are handled by the system."
+-msgstr "Ne pas présumer que les accès non alignées sont traités par le système"
++msgstr "Ne pas supposer que les accès non alignés sont traités par le système."
+ 
+ #: config/aarch64/aarch64.opt:93 config/i386/i386.opt:390
+-#, fuzzy
+-#| msgid "Omit the frame pointer in leaf functions"
+ msgid "Omit the frame pointer in leaf functions."
+-msgstr "Omettre le pointeur de trame dans les fonctions feuilles"
++msgstr "Omettre le pointeur de trame dans les fonctions feuilles."
+ 
+ #: config/aarch64/aarch64.opt:97
+ msgid "Specify TLS dialect."
+-msgstr ""
++msgstr "Spécifier le dialecte TLS."
+ 
+ #: config/aarch64/aarch64.opt:101
+-#, fuzzy
+-#| msgid "Specify bit size of immediate TLS offsets"
+ msgid "Specifies bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48."
+-msgstr "Spécifier la taille de bit des décalages immédiats TLS"
++msgstr "Spécifier la taille en bits des décalages TLS immédiats. Les valeurs valides sont 12, 24, 32, 48."
+ 
+ #: config/aarch64/aarch64.opt:120
+-#, fuzzy
+-#| msgid "Use features of and schedule code for given CPU"
+ msgid "-march=ARCH\tUse features of architecture ARCH."
+-msgstr "Utiliser les options et ordonnancer le code pour le processeur donné"
++msgstr "-march=ARCH\tUtiliser les fonctionnalités de l'architecture ARCH."
+ 
+ #: config/aarch64/aarch64.opt:124
+-#, fuzzy
+-#| msgid "Use features of and schedule code for given CPU"
+ msgid "-mcpu=CPU\tUse features of and optimize for CPU."
+-msgstr "Utiliser les options et ordonnancer le code pour le processeur donné"
++msgstr "-mcpu=CPU\tUtiliser les fonctionnalités et optimiser pour ce processeur."
+ 
+ #: config/aarch64/aarch64.opt:128
+-#, fuzzy
+-#| msgid "Use features of and schedule code for given CPU"
+ msgid "-mtune=CPU\tOptimize for CPU."
+-msgstr "Utiliser les options et ordonnancer le code pour le processeur donné"
++msgstr "-mtune=CPU\tOptimiser pour ce processeur."
+ 
+ #: config/aarch64/aarch64.opt:132
+-#, fuzzy
+-#| msgid "Generate code for given CPU"
+ msgid "-mabi=ABI\tGenerate code that conforms to the specified ABI."
+-msgstr "Générer le code pour le processeur donné"
++msgstr "-mabi=ABI\tGénérer du code conforme à l'ABI spécifiée."
+ 
+ #: config/aarch64/aarch64.opt:136
+ msgid "-moverride=STRING\tPower users only! Override CPU optimization parameters."
+-msgstr ""
++msgstr "-moverride=CHAÎNE\tUniquement pour les utilisateurs avertis ! Outrepasser les paramètres d'optimisation du processeur."
+ 
+ #: config/aarch64/aarch64.opt:140
+ msgid "Known AArch64 ABIs (for use with the -mabi= option):"
+-msgstr ""
++msgstr "ABI AArch64 connues (à utiliser avec l'option -mabi=):"
+ 
+ #: config/aarch64/aarch64.opt:150
+ msgid "PC relative literal loads."
+-msgstr ""
++msgstr "Chargements littéraux relatifs au PC."
+ 
+ #: config/aarch64/aarch64.opt:154
+ msgid "When calculating the reciprocal square root approximation,"
+-msgstr ""
++msgstr "Lors du calcul de l'approximation de la racine carrée réciproque, utiliser une étape en moins que d'habitude, ce qui réduit la latence et la précision."
+ 
+ #: config/linux.opt:24
+-#, fuzzy
+-#| msgid "Use uClibc C library"
+ msgid "Use Bionic C library."
+-msgstr "Utiliser la bibliothèque C uClibc"
++msgstr "Utiliser la bibliothèque C Bionic."
+ 
+ #: config/linux.opt:28
+-#, fuzzy
+-#| msgid "Use GNU C library"
+ msgid "Use GNU C library."
+-msgstr "Utiliser la bibliothèque C GNU"
++msgstr "Utiliser la bibliothèque C GNU."
+ 
+ #: config/linux.opt:32
+-#, fuzzy
+-#| msgid "Use uClibc C library"
+ msgid "Use uClibc C library."
+-msgstr "Utiliser la bibliothèque C uClibc"
++msgstr "Utiliser la bibliothèque C uClibc."
+ 
+ #: config/linux.opt:36
+-#, fuzzy
+-#| msgid "Use uClibc C library"
+ msgid "Use musl C library."
+-msgstr "Utiliser la bibliothèque C uClibc"
++msgstr "Utiliser la bibliothèque C musl."
+ 
+ #: config/ia64/ilp32.opt:3
+-#, fuzzy
+-#| msgid "Generate ILP32 code"
+ msgid "Generate ILP32 code."
+-msgstr "Générer du code ILP32"
++msgstr "Générer du code ILP32."
+ 
+ #: config/ia64/ilp32.opt:7
+-#, fuzzy
+-#| msgid "Generate LP64 code"
+ msgid "Generate LP64 code."
+-msgstr "Générer du code LP64"
++msgstr "Générer du code LP64."
+ 
+ #: config/ia64/ia64.opt:28
+-#, fuzzy
+-#| msgid "Generate big endian code"
+ msgid "Generate big endian code."
+-msgstr "Générer du code de système à octets de poids fort"
++msgstr "Générer du code gros boutiste."
+ 
+ #: config/ia64/ia64.opt:32
+-#, fuzzy
+-#| msgid "Generate little endian code"
+ msgid "Generate little endian code."
+-msgstr "Générer du code de système à octets de poids faible"
++msgstr "Générer du code petit boutiste."
+ 
+ #: config/ia64/ia64.opt:36
+-#, fuzzy
+-#| msgid "Generate code for GNU as"
+ msgid "Generate code for GNU as."
+-msgstr "Générer du code pour GNU tel que"
++msgstr "Générer du code pour GNU as."
+ 
+ #: config/ia64/ia64.opt:40
+-#, fuzzy
+-#| msgid "Generate code for GNU ld"
+ msgid "Generate code for GNU ld."
+-msgstr "Générer du code pour GNU ld"
++msgstr "Générer du code pour GNU ld."
+ 
+ #: config/ia64/ia64.opt:44
+-#, fuzzy
+-#| msgid "Emit stop bits before and after volatile extended asms"
+ msgid "Emit stop bits before and after volatile extended asms."
+-msgstr "Produire de stop bits avant et après les asms étendus"
++msgstr "Produire des bits de stop avant et après les asms étendues volatiles."
+ 
+ #: config/ia64/ia64.opt:48
+-#, fuzzy
+-#| msgid "Use in/loc/out register names"
+ msgid "Use in/loc/out register names."
+-msgstr "Utilise les noms des registres in/loc/out "
++msgstr "Utiliser les noms des registres in/loc/out."
+ 
+ #: config/ia64/ia64.opt:55
+-#, fuzzy
+-#| msgid "Enable use of sdata/scommon/sbss"
+ msgid "Enable use of sdata/scommon/sbss."
+-msgstr "Autoriser l'utilisation de sdata/scommon/sbss"
++msgstr "Activer l'utilisation de sdata/scommon/sbss."
+ 
+ #: config/ia64/ia64.opt:59
+-#, fuzzy
+-#| msgid "Generate code without GP reg"
+ msgid "Generate code without GP reg."
+-msgstr "Générer du code sans registre GP"
++msgstr "Générer du code sans registre GP."
+ 
+ #: config/ia64/ia64.opt:63
+-#, fuzzy
+-#| msgid "gp is constant (but save/restore gp on indirect calls)"
+ msgid "gp is constant (but save/restore gp on indirect calls)."
+-msgstr "gp est une constante (mais save/restore gp fait par appels indirects)"
++msgstr "gp est constant (mais save/restore gp lors d'appels indirects)."
+ 
+ #: config/ia64/ia64.opt:67
+-#, fuzzy
+-#| msgid "Generate self-relocatable code"
+ msgid "Generate self-relocatable code."
+-msgstr "Générer du code auto-relocalisable"
++msgstr "Générer du code auto-relocalisable."
+ 
+ #: config/ia64/ia64.opt:71
+-#, fuzzy
+-#| msgid "Generate inline floating point division, optimize for latency"
+ msgid "Generate inline floating point division, optimize for latency."
+-msgstr "Générer la division enligne en point flottant, optimiser pour la latence"
++msgstr "Générer une version en ligne de la division en virgule flottante, optimiser pour la latence."
+ 
+ #: config/ia64/ia64.opt:75
+-#, fuzzy
+-#| msgid "Generate inline floating point division, optimize for throughput"
+ msgid "Generate inline floating point division, optimize for throughput."
+-msgstr "Générer la division en point flottant enligne, optimiser pour le débit"
++msgstr "Générer une version en ligne de la division en virgule flottante, optimiser pour le débit."
+ 
+ #: config/ia64/ia64.opt:82
+-#, fuzzy
+-#| msgid "Generate inline integer division, optimize for latency"
+ msgid "Generate inline integer division, optimize for latency."
+-msgstr "Générer la division entière enligne, optimiser pour la latence"
++msgstr "Générer une version en ligne de la division entière, optimiser pour la latence."
+ 
+ #: config/ia64/ia64.opt:86
+-#, fuzzy
+-#| msgid "Generate inline integer division, optimize for throughput"
+ msgid "Generate inline integer division, optimize for throughput."
+-msgstr "Générer la divisions entière enligne, optimiser pour le débit"
++msgstr "Générer une version en ligne de la division entière, optimiser pour le débit."
+ 
+ #: config/ia64/ia64.opt:90
+-#, fuzzy
+-#| msgid "Warn about compile-time integer division by zero"
+ msgid "Do not inline integer division."
+-msgstr "Avertir au sujet de la division entière par zéro au moment de la compilation"
++msgstr "Ne pas mettre en ligne la division entière."
+ 
+ #: config/ia64/ia64.opt:94
+-#, fuzzy
+-#| msgid "Generate inline square root, optimize for latency"
+ msgid "Generate inline square root, optimize for latency."
+-msgstr "Générer la racine carrée enligne, optimiser pour la latence"
++msgstr "Générer une version en ligne de la racine carrée, optimiser pour la latence."
+ 
+ #: config/ia64/ia64.opt:98
+-#, fuzzy
+-#| msgid "Generate inline square root, optimize for throughput"
+ msgid "Generate inline square root, optimize for throughput."
+-msgstr "Générer la racine carrée enligne, optimiser pour le débit"
++msgstr "Générer une version en ligne de la racine carrée, optimiser pour le débit."
+ 
+ #: config/ia64/ia64.opt:102
+-#, fuzzy
+-#| msgid "Do not disable space regs"
+ msgid "Do not inline square root."
+-msgstr "Ne pas désactiver l'espace registre"
++msgstr "Ne pas mettre en ligne la racine carrée."
+ 
+ #: config/ia64/ia64.opt:106
+-#, fuzzy
+-#| msgid "Enable Dwarf 2 line debug info via GNU as"
+ msgid "Enable DWARF line debug info via GNU as."
+-msgstr "Autoriser les infos de lignes de mise au point Dwarf 2 via GNU tel que"
++msgstr "Activer les infos DWARF de débogage des lignes via GNU as."
+ 
+ #: config/ia64/ia64.opt:110
+-#, fuzzy
+-#| msgid "Enable earlier placing stop bits for better scheduling"
+ msgid "Enable earlier placing stop bits for better scheduling."
+-msgstr "Autoriser l'insertion antérieure de stop bits pour un meilleur ordonnancement"
++msgstr "Activer l'insertion plus tôt de bits de stop pour un meilleur ordonnancement."
+ 
+ #: config/ia64/ia64.opt:114 config/spu/spu.opt:72 config/pa/pa.opt:58
+ #: config/sh/sh.opt:273
+-#, fuzzy
+-#| msgid "Specify range of registers to make fixed"
+ msgid "Specify range of registers to make fixed."
+-msgstr "spécifier l'étendue des registres pour la rendre fixe"
++msgstr "Spécifier la plage des registres à rendre fixes."
+ 
+ #: config/ia64/ia64.opt:118 config/rs6000/sysv4.opt:32
+ #: config/alpha/alpha.opt:130
+-#, fuzzy
+-#| msgid "Specify bit size of immediate TLS offsets"
+ msgid "Specify bit size of immediate TLS offsets."
+-msgstr "Spécifier la taille de bit des décalages immédiats TLS"
++msgstr "Spécifier la taille en bits des décalages TLS immédiats."
+ 
+ #: config/ia64/ia64.opt:122 config/spu/spu.opt:84 config/i386/i386.opt:504
+ #: config/s390/s390.opt:170 config/sparc/sparc.opt:130
+ #: config/visium/visium.opt:49
+-#, fuzzy
+-#| msgid "Schedule code for given CPU"
+ msgid "Schedule code for given CPU."
+-msgstr "Ordonnancer le code pour le processeur donné"
++msgstr "Ordonnancer le code pour le processeur donné."
+ 
+ #: config/ia64/ia64.opt:126
+ msgid "Known Itanium CPUs (for use with the -mtune= option):"
+-msgstr ""
++msgstr "Processeurs Itanium connus (à utiliser avec l'option -mtune=):"
+ 
+ #: config/ia64/ia64.opt:136
+-#, fuzzy
+-#| msgid "Allow speculative motion of more loads"
+ msgid "Use data speculation before reload."
+-msgstr "Autoriser le mouvement spéculatif de plusieurs chargements"
++msgstr "Utiliser la spéculation de données avant le rechargement."
+ 
+ #: config/ia64/ia64.opt:140
+-#, fuzzy
+-#| msgid "Allow speculative motion of more loads"
+ msgid "Use data speculation after reload."
+-msgstr "Autoriser le mouvement spéculatif de plusieurs chargements"
++msgstr "Utiliser la spéculation de données après le rechargement."
+ 
+ #: config/ia64/ia64.opt:144
+-#, fuzzy
+-#| msgid "Create console application"
+ msgid "Use control speculation."
+-msgstr "Créer une application de type console"
++msgstr "Utiliser la spéculation de contrôle."
+ 
+ #: config/ia64/ia64.opt:148
+-#, fuzzy
+-#| msgid "Allow speculative motion of more loads"
+ msgid "Use in block data speculation before reload."
+-msgstr "Autoriser le mouvement spéculatif de plusieurs chargements"
++msgstr "Utiliser la spéculation sur les données dans le bloc avant le rechargement."
+ 
+ #: config/ia64/ia64.opt:152
+-#, fuzzy
+-#| msgid "Allow speculative motion of more loads"
+ msgid "Use in block data speculation after reload."
+-msgstr "Autoriser le mouvement spéculatif de plusieurs chargements"
++msgstr "Utiliser la spéculation sur les données dans le bloc après le rechargement."
+ 
+ #: config/ia64/ia64.opt:156
+-#, fuzzy
+-#| msgid "Create console application"
+ msgid "Use in block control speculation."
+-msgstr "Créer une application de type console"
++msgstr "Utiliser la spéculation sur le contrôle dans le bloc."
+ 
+ #: config/ia64/ia64.opt:160
+-#, fuzzy
+-#| msgid "Allow speculative motion of more loads"
+ msgid "Use simple data speculation check."
+-msgstr "Autoriser le mouvement spéculatif de plusieurs chargements"
++msgstr "Utiliser une vérification simple de la spéculation sur les données."
+ 
+ #: config/ia64/ia64.opt:164
+-#, fuzzy
+-#| msgid "Allow speculative motion of more loads"
+ msgid "Use simple data speculation check for control speculation."
+-msgstr "Autoriser le mouvement spéculatif de plusieurs chargements"
++msgstr "Utiliser une vérification simple de la spéculation sur les données pour la spéculation du contrôle."
+ 
+ #: config/ia64/ia64.opt:174
+ msgid "Count speculative dependencies while calculating priority of instructions."
+-msgstr ""
++msgstr "Compter les dépendances spéculatives tout en calculant la priorité des instructions."
+ 
+ #: config/ia64/ia64.opt:178
+-#, fuzzy
+-#| msgid "Enable earlier placing stop bits for better scheduling"
+ msgid "Place a stop bit after every cycle when scheduling."
+-msgstr "Autoriser l'insertion antérieure de stop bits pour un meilleur ordonnancement"
++msgstr "Placer un bit de stop après chaque cycle lors de l'ordonnancement."
+ 
+ #: config/ia64/ia64.opt:182
+ msgid "Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group."
+-msgstr ""
++msgstr "Supposer que les stockages et chargements de nombres en virgule flottante ne produiront probablement pas de conflits si ils sont placés dans un groupe d'instructions."
+ 
+ #: config/ia64/ia64.opt:186
+ msgid "Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts.  Default value is 1."
+-msgstr ""
++msgstr "Limite souple sur le nombre d'insns mémoire par groupe d'instructions. Donne une priorité plus basse aux insns mémoire suivantes qui tentent d'être ordonnancées dans le même groupe d'insn. Fréquemment utilisé pour éviter des conflits dans les zones de cache. La valeur par défaut est 1. "
+ 
+ #: config/ia64/ia64.opt:190
+ msgid "Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached)."
+-msgstr ""
++msgstr "Interdit plus que « msched-max-memory-insns » dans le groupe d'instructions. Autrement, la limite est « souple » (préfère les opérations non-mémoire quand la limite est atteinte)."
+ 
+ #: config/ia64/ia64.opt:194
+ msgid "Don't generate checks for control speculation in selective scheduling."
+-msgstr ""
++msgstr "Ne pas générer de vérifications pour la spéculation de contrôle dans l'ordonnancement sélectif."
+ 
+ #: config/spu/spu.opt:20
+-#, fuzzy
+-#| msgid "location enumeration for BOOLS"
+ msgid "Emit warnings when run-time relocations are generated."
+-msgstr "localisation d'énumération pour BOOLÉENS"
++msgstr "Émettre des avertissements quand des relocalisations à l'exécution sont générées."
+ 
+ #: config/spu/spu.opt:24
+ msgid "Emit errors when run-time relocations are generated."
+-msgstr ""
++msgstr "Émettre des erreurs quand des relocalisations à l'exécution sont générées."
+ 
+ #: config/spu/spu.opt:28
+ msgid "Specify cost of branches (Default 20)."
+-msgstr ""
++msgstr "Spécifier le coût des branches (20 par défaut)."
+ 
+ #: config/spu/spu.opt:32
+-#, fuzzy
+-#| msgid "Generate load/store with update instructions"
+ msgid "Make sure loads and stores are not moved past DMA instructions."
+-msgstr "Générer les instructions de mise à jour de chargement/stockage"
++msgstr "S'assurer que les chargements et les stockages ne sont pas déplacés au delà d'instructions DMA."
+ 
+ #: config/spu/spu.opt:36
+ msgid "volatile must be specified on any memory that is effected by DMA."
+-msgstr ""
++msgstr "« volatile » doit être spécifié sur toute mémoire qui est affectée par le DMA."
+ 
+ #: config/spu/spu.opt:40 config/spu/spu.opt:44
+ msgid "Insert nops when it might improve performance by allowing dual issue (default)."
+-msgstr ""
++msgstr "Insérer des nops quand cela pourrait améliorer la performance en permettant des doubles émissions dans les pipelines (par défaut)."
+ 
+ #: config/spu/spu.opt:48
+-#, fuzzy
+-#| msgid "Use jsr and rts for function calls and returns"
+ msgid "Use standard main function as entry for startup."
+-msgstr "Utiliser jsr et rtc pour les appels de fonction et les retours"
++msgstr "Utiliser la fonction « main » standard comme point d'entrée au démarrage."
+ 
+ #: config/spu/spu.opt:52
+-#, fuzzy
+-#| msgid "Generate string instructions for block moves"
+ msgid "Generate branch hints for branches."
+-msgstr "Générer les instructions chaînes pour les déplacements de blocs"
++msgstr "Générer des indices de branchement pour les branches."
+ 
+ #: config/spu/spu.opt:56
+-#, fuzzy
+-#| msgid "The maximum number of instructions to consider to fill a delay slot"
+ msgid "Maximum number of nops to insert for a hint (Default 2)."
+-msgstr "Le nombre maximum d'instructions à considérer pour remplir une slot délai"
++msgstr "Le nombre maximum de nops à insérer pour un indice (2 par défaut)."
+ 
+ #: config/spu/spu.opt:60
+-#, fuzzy
+-#| msgid "The maximum number of instructions to consider to unroll in a loop"
+ msgid "Approximate maximum number of instructions to allow between a hint and its branch [125]."
+-msgstr "Le nombre maximum d'instructions à considérer à inclure dans une boucle"
++msgstr "Nombre maximum approximatif d'instructions à permettre entre un indice et sa branche [125]."
+ 
+ #: config/spu/spu.opt:64
+-#, fuzzy
+-#| msgid "Generate code for big endian"
+ msgid "Generate code for 18 bit addressing."
+-msgstr "Générer du code pour un système à octets de poids fort"
++msgstr "Générer du code pour un adressage sur 18 bits."
+ 
+ #: config/spu/spu.opt:68
+-#, fuzzy
+-#| msgid "Generate code for big endian"
+ msgid "Generate code for 32 bit addressing."
+-msgstr "Générer du code pour un système à octets de poids fort"
++msgstr "Générer du code pour un adressage sur 32 bits."
+ 
+ #: config/spu/spu.opt:76
+ msgid "Insert hbrp instructions after hinted branch targets to avoid the SPU hang issue."
+-msgstr ""
++msgstr "Insérer des instructions hbrp après des cibles de branchements avec indices pour éviter de planter le SPU."
+ 
+ #: config/spu/spu.opt:80 config/i386/i386.opt:247 config/s390/s390.opt:56
+-#, fuzzy
+-#| msgid "Generate code for given CPU"
+ msgid "Generate code for given CPU."
+-msgstr "Générer le code pour le processeur donné"
++msgstr "Générer du code pour le processeur donné."
+ 
+ #: config/spu/spu.opt:88
+-#, fuzzy
+-#| msgid "Pass parameters in registers (default)"
+ msgid "Access variables in 32-bit PPU objects (default)."
+-msgstr "Passer les paramètres par les registres (par défaut)"
++msgstr "Accéder aux variables dans des objets PPU sur 32 bits (par défaut)."
+ 
+ #: config/spu/spu.opt:92
+-#, fuzzy
+-#| msgid "Pass parameters in registers (default)"
+ msgid "Access variables in 64-bit PPU objects."
+-msgstr "Passer les paramètres par les registres (par défaut)"
++msgstr "Accéder aux variables dans des objets PPU sur 64 bits."
+ 
+ #: config/spu/spu.opt:96
+ msgid "Allow conversions between __ea and generic pointers (default)."
+-msgstr ""
++msgstr "Permettre les conversions entre __ea et les pointeurs génériques (par défaut)."
+ 
+ #: config/spu/spu.opt:100
+ msgid "Size (in KB) of software data cache."
+-msgstr ""
++msgstr "La taille (en Ko) de la cache des données logicielles."
+ 
+ #: config/spu/spu.opt:104
+ msgid "Atomically write back software data cache lines (default)."
+-msgstr ""
++msgstr "Écrire atomiquement dans les lignes de cache des données logicielles (par défaut)."
+ 
+ #: config/epiphany/epiphany.opt:24
+ msgid "Don't use any of r32..r63."
+-msgstr ""
++msgstr "N'utiliser aucun des r32..r63."
+ 
+ #: config/epiphany/epiphany.opt:28
+ msgid "preferentially allocate registers that allow short instruction generation."
+-msgstr ""
++msgstr "allouer de préférence des registres qui autorisent la génération d'instructions courtes."
+ 
+ #: config/epiphany/epiphany.opt:32
+-#, fuzzy
+-#| msgid "Relax branches"
+ msgid "Set branch cost."
+-msgstr "Branchements relaxés"
++msgstr "Définir le coût d'un branchement."
+ 
+ #: config/epiphany/epiphany.opt:36
+-#, fuzzy
+-#| msgid "Enable use of conditional move instructions"
+ msgid "enable conditional move instruction usage."
+-msgstr "Autoriser l'utilisation des instructions conditionnelles move"
++msgstr "activer l'utilisation de l'instruction de déplacement conditionnel."
+ 
+ #: config/epiphany/epiphany.opt:40
+-#, fuzzy
+-#| msgid "The maximum number of instructions to consider to fill a delay slot"
+ msgid "set number of nops to emit before each insn pattern."
+-msgstr "Le nombre maximum d'instructions à considérer pour remplir une slot délai"
++msgstr "fixer le nombre de nops a émettre avant chaque motif d'insn."
+ 
+ #: config/epiphany/epiphany.opt:52
+-#, fuzzy
+-#| msgid "Use software floating point"
+ msgid "Use software floating point comparisons."
+-msgstr "Utiliser le traitement par logiciel des nombres flottants"
++msgstr "Utiliser les comparaisons logicielles des virgules flottantes."
+ 
+ #: config/epiphany/epiphany.opt:56
+ msgid "Enable split of 32 bit immediate loads into low / high part."
+-msgstr ""
++msgstr "Autoriser la scission des chargements d'immédiats sur 32 bits en partie basse / haute."
+ 
+ #: config/epiphany/epiphany.opt:60
+ msgid "Enable use of POST_INC / POST_DEC."
+-msgstr ""
++msgstr "Activer l'utilisation de POST_INC / POST_DEC."
+ 
+ #: config/epiphany/epiphany.opt:64
+ msgid "Enable use of POST_MODIFY."
+-msgstr ""
++msgstr "Activer l'utilisation de POST_MODIFY."
+ 
+ #: config/epiphany/epiphany.opt:68
+ msgid "Set number of bytes on the stack preallocated for use by the callee."
+-msgstr ""
++msgstr "Définir le nombre d'octets pré-alloués sur la pile destinés à être utilisés par l'appelé."
+ 
+ #: config/epiphany/epiphany.opt:72
+ msgid "Assume round to nearest is selected for purposes of scheduling."
+-msgstr ""
++msgstr "Supposer que l'arrondi au plus proche est sélectionné quand il s'agit d'ordonnancer."
+ 
+ #: config/epiphany/epiphany.opt:76
+-#, fuzzy
+-#| msgid "Generate call insns as indirect calls, if necessary"
+ msgid "Generate call insns as indirect calls."
+-msgstr "Générer l'appel insn comme un appel indirect, si nécessaire"
++msgstr "Générer les insns d'appels comme appels indirects."
+ 
+ #: config/epiphany/epiphany.opt:80
+-#, fuzzy
+-#| msgid "Generate call insns as indirect calls, if necessary"
+ msgid "Generate call insns as direct calls."
+-msgstr "Générer l'appel insn comme un appel indirect, si nécessaire"
++msgstr "Générer les insns d'appels comme appels directs."
+ 
+ #: config/epiphany/epiphany.opt:84
+ msgid "Assume labels and symbols can be addressed using 16 bit absolute addresses."
+-msgstr ""
++msgstr "Supposer que les étiquettes et les symboles peuvent être adressés en utilisant des adresses absolues sur 16 bits."
+ 
+ #: config/epiphany/epiphany.opt:108
+ msgid "A floatig point to integer truncation may be replaced with rounding to save mode switching."
+-msgstr ""
++msgstr "La troncature d'un nombre décimal en nombre entier peut être remplacée par un arrondi pour économiser un changement de mode."
+ 
+ #: config/epiphany/epiphany.opt:112
+-#, fuzzy
+-#| msgid "Use structs on stronger alignment for double-word copies"
+ msgid "Vectorize for double-word operations."
+-msgstr "Utiliser des structs avec alignement plus fort pour les copies de mots-doubles"
++msgstr "Vectoriser pour des opérations sur des doubles mots."
+ 
+ #: config/epiphany/epiphany.opt:128
+ msgid "Split unaligned 8 byte vector moves before post-modify address generation."
+-msgstr ""
++msgstr "Scinder les déplacements de vecteurs de 8 octets non-alignés avant la génération d'adresse post-modifiée."
+ 
+ #: config/epiphany/epiphany.opt:132
+-#, fuzzy
+-#| msgid "Use hardware floating point instructions"
+ msgid "Use the floating point unit for integer add/subtract."
+-msgstr "Utiliser les instructions matérielles en virgule flottante"
++msgstr "Utiliser l'unité en virgule flottante pour ajouter/soustraire des entiers."
+ 
+ #: config/epiphany/epiphany.opt:136
+ msgid "Set register to hold -1."
+-msgstr ""
++msgstr "Définir le registre pour contenir -1."
+ 
+ #: config/ft32/ft32.opt:23
+ msgid "target the software simulator."
+-msgstr ""
++msgstr "cible le simulateur logiciel."
+ 
+ #: config/ft32/ft32.opt:27 config/s390/s390.opt:201 config/mips/mips.opt:385
+-#, fuzzy
+-#| msgid "Use ROM instead of RAM"
+ msgid "Use LRA instead of reload."
+-msgstr "Utiliser le ROM au lieu de la RAM"
++msgstr "Utiliser LRA au lieu d'un rechargement."
+ 
+ #: config/ft32/ft32.opt:31
+-#, fuzzy
+-#| msgid "Enable use of DB instruction"
+ msgid "Avoid use of the DIV and MOD instructions"
+-msgstr "Activer l'utilisation d'instruction DB"
++msgstr "Éviter l'utilisation des instructions DIV et MOD"
+ 
+ #: config/h8300/h8300.opt:23
+-#, fuzzy
+-#| msgid "Generate H8S code"
+ msgid "Generate H8S code."
+-msgstr "Générer du code H8S"
++msgstr "Générer du code H8S."
+ 
+ #: config/h8300/h8300.opt:27
+-#, fuzzy
+-#| msgid "Generate H8SX code"
+ msgid "Generate H8SX code."
+-msgstr "Générer du code H8SX"
++msgstr "Générer du code H8SX."
+ 
+ #: config/h8300/h8300.opt:31
+-#, fuzzy
+-#| msgid "Generate H8S/2600 code"
+ msgid "Generate H8S/2600 code."
+-msgstr "Générer du code H8S/S2600"
++msgstr "Générer du code H8S/S2600."
+ 
+ #: config/h8300/h8300.opt:35
+-#, fuzzy
+-#| msgid "Make integers 32 bits wide"
+ msgid "Make integers 32 bits wide."
+-msgstr "Rendre les entiers larges de 32 bits"
++msgstr "Rendre les entiers larges de 32 bits."
+ 
+ #: config/h8300/h8300.opt:42
+-#, fuzzy
+-#| msgid "Use registers for argument passing"
+ msgid "Use registers for argument passing."
+-msgstr "Utiliser les registres pour le passage d'arguments"
++msgstr "Utiliser les registres pour le passage d'arguments."
+ 
+ #: config/h8300/h8300.opt:46
+-#, fuzzy
+-#| msgid "Consider access to byte sized memory slow"
+ msgid "Consider access to byte sized memory slow."
+-msgstr "Considérer l'accès mémoire lent pour la taille d'octets"
++msgstr "Considérer que l'accès à une mémoire de un octet est lente."
+ 
+ #: config/h8300/h8300.opt:50
+-#, fuzzy
+-#| msgid "Enable linker relaxing"
+ msgid "Enable linker relaxing."
+-msgstr "Activer la relâche par l'éditeur de liens"
++msgstr "Activer la relâche par l'éditeur de liens."
+ 
+ #: config/h8300/h8300.opt:54
+-#, fuzzy
+-#| msgid "Generate H8/300H code"
+ msgid "Generate H8/300H code."
+-msgstr "Générer du code H8/300H"
++msgstr "Générer du code H8/300H."
+ 
+ #: config/h8300/h8300.opt:58
+-#, fuzzy
+-#| msgid "Enable the normal mode"
+ msgid "Enable the normal mode."
+-msgstr "Activer le mode normal"
++msgstr "Activer le mode normal."
+ 
+ #: config/h8300/h8300.opt:62
+-#, fuzzy
+-#| msgid "Use H8/300 alignment rules"
+ msgid "Use H8/300 alignment rules."
+-msgstr "Utiliser les règles d'alignement H8/300"
++msgstr "Utiliser les règles d'alignement du H8/300."
+ 
+ #: config/h8300/h8300.opt:66
+ msgid "Push extended registers on stack in monitor functions."
+-msgstr ""
++msgstr "Pousser les registres étendus sur la pile dans les fonctions de monitoring."
+ 
+ #: config/h8300/h8300.opt:70
+-#, fuzzy
+-#| msgid "Do not use the callt instruction"
+ msgid "Do not push extended registers on stack in monitor functions."
+-msgstr "Ne pas utiliser l'instruction callt"
++msgstr "Ne pas pousser les registres étendus sur la pile dans les fonctions de monitoring."
+ 
+ #: config/pdp11/pdp11.opt:23
+-#, fuzzy
+-#| msgid "Generate code for an 11/10"
+ msgid "Generate code for an 11/10."
+-msgstr "Générer du code pour un 11/10"
++msgstr "Générer du code pour un 11/10."
+ 
+ #: config/pdp11/pdp11.opt:27
+-#, fuzzy
+-#| msgid "Generate code for an 11/40"
+ msgid "Generate code for an 11/40."
+-msgstr "Générer du code pour un 11/40"
++msgstr "Générer du code pour un 11/40."
+ 
+ #: config/pdp11/pdp11.opt:31
+-#, fuzzy
+-#| msgid "Generate code for an 11/45"
+ msgid "Generate code for an 11/45."
+-msgstr "Générer du code pour un 11/45"
++msgstr "Générer du code pour un 11/45."
+ 
+ #: config/pdp11/pdp11.opt:35
+-#, fuzzy
+-#| msgid "Return floating point results in ac0"
+ msgid "Return floating-point results in ac0 (fr0 in Unix assembler syntax)."
+-msgstr "Le résultat retourné en virgule flottante se retrouve dans AC0."
++msgstr "Retourne les résultats en virgule flottante dans ac0 (fr0 dans la syntaxe de l'assembleur Unix)."
+ 
+ #: config/pdp11/pdp11.opt:39
+ msgid "Do not use inline patterns for copying memory."
+-msgstr ""
++msgstr "Ne pas utiliser des motifs en lignes pour copier de la mémoire."
+ 
+ #: config/pdp11/pdp11.opt:43
+ msgid "Use inline patterns for copying memory."
+-msgstr ""
++msgstr "Utiliser des motifs en lignes pour copier de la mémoire."
+ 
+ #: config/pdp11/pdp11.opt:47
+ msgid "Do not pretend that branches are expensive."
+-msgstr ""
++msgstr "Ne pas prétendre que les branches sont onéreuses."
+ 
+ #: config/pdp11/pdp11.opt:51
+ msgid "Pretend that branches are expensive."
+-msgstr ""
++msgstr "Prétendre que les branches sont onéreuses."
+ 
+ #: config/pdp11/pdp11.opt:55
+-#, fuzzy
+-#| msgid "Use the DEC assembler syntax"
+ msgid "Use the DEC assembler syntax."
+-msgstr "Utiliser la syntaxe de l'assembleur DEC"
++msgstr "Utiliser la syntaxe de l'assembleur DEC."
+ 
+ #: config/pdp11/pdp11.opt:59
+-#, fuzzy
+-#| msgid "Use 32 bit float"
+ msgid "Use 32 bit float."
+-msgstr "Utiliser des flottants de 32 bits"
++msgstr "Utiliser des flottants de 32 bits."
+ 
+ #: config/pdp11/pdp11.opt:63
+-#, fuzzy
+-#| msgid "Use 64 bit float"
+ msgid "Use 64 bit float."
+-msgstr "Utiliser des flottants de 64 bits"
++msgstr "Utiliser des flottants de 64 bits."
+ 
+ #: config/pdp11/pdp11.opt:67 config/rs6000/rs6000.opt:177
+ #: config/frv/frv.opt:158
+-#, fuzzy
+-#| msgid "Use hardware floating point"
+ msgid "Use hardware floating point."
+-msgstr "Utiliser l'unité matérielle en virgule flottante"
++msgstr "Utiliser l'unité matérielle pour les opérations en virgule flottante."
+ 
+ #: config/pdp11/pdp11.opt:71
+-#, fuzzy
+-#| msgid "Use 16 bit int"
+ msgid "Use 16 bit int."
+-msgstr "Utiliser des int de 16 bits"
++msgstr "Utiliser des int de 16 bits."
+ 
+ #: config/pdp11/pdp11.opt:75
+-#, fuzzy
+-#| msgid "Use 32 bit int"
+ msgid "Use 32 bit int."
+-msgstr "Utiliser des int de 32 bits"
++msgstr "Utiliser des int de 32 bits."
+ 
+ #: config/pdp11/pdp11.opt:79 config/rs6000/rs6000.opt:173
+-#, fuzzy
+-#| msgid "Do not use hardware floating point"
+ msgid "Do not use hardware floating point."
+-msgstr "Ne pas utiliser le matériel pour virgule flottante"
++msgstr "Ne pas utiliser l'unité matérielle pour les opérations en virgule flottante."
+ 
+ #: config/pdp11/pdp11.opt:83
+-#, fuzzy
+-#| msgid "Target has split I&D"
+ msgid "Target has split I&D."
+-msgstr "Cible a un I&D séparé"
++msgstr "La cible a un bus I&D (Instruction and Data space) séparé."
+ 
+ #: config/pdp11/pdp11.opt:87
+-#, fuzzy
+-#| msgid "Use UNIX assembler syntax"
+ msgid "Use UNIX assembler syntax."
+-msgstr "Utiliser la syntaxe de l'assembleur UNIX"
++msgstr "Utiliser la syntaxe de l'assembleur UNIX."
+ 
+ #: config/xtensa/xtensa.opt:23
+-#, fuzzy
+-#| msgid "Use CONST16 instruction to load constants"
+ msgid "Use CONST16 instruction to load constants."
+-msgstr "Utiliser les instructions CONST16 pour charger les constantes"
++msgstr "Utiliser l'instruction CONST16 pour charger les constantes."
+ 
+ #: config/xtensa/xtensa.opt:27
+-#, fuzzy
+-#| msgid "Generate position-independent code if possible"
+ msgid "Disable position-independent code (PIC) for use in OS kernel code."
+-msgstr "Générer du code indépendant de la position si possible"
++msgstr "Désactiver le code indépendant de la position (PIC) pour l'utilisation dans du code du noyau de l'OS."
+ 
+ #: config/xtensa/xtensa.opt:31
+-#, fuzzy
+-#| msgid "Use indirect CALLXn instructions for large programs"
+ msgid "Use indirect CALLXn instructions for large programs."
+-msgstr "Utiliser les instructions indirectes CALLXn pour les grands programmes"
++msgstr "Utiliser les instructions indirectes CALLXn pour les grands programmes."
+ 
+ #: config/xtensa/xtensa.opt:35
+-#, fuzzy
+-#| msgid "Automatically align branch targets to reduce branch penalties"
+ msgid "Automatically align branch targets to reduce branch penalties."
+-msgstr "Aligner automatiquement les branchements cibles pour réduire les pénalités de branchement"
++msgstr "Aligner automatiquement les cibles des branchements pour réduire les pénalités des branchements."
+ 
+ #: config/xtensa/xtensa.opt:39
+-#, fuzzy
+-#| msgid "Intersperse literal pools with code in the text section"
+ msgid "Intersperse literal pools with code in the text section."
+-msgstr "Entrecouper les lots de littéraux avec le code dans la section texte"
++msgstr "Entrecouper les lots de littéraux avec le code dans la section texte."
+ 
+ #: config/xtensa/xtensa.opt:43
+ msgid "Relax literals in assembler and place them automatically in the text section."
+-msgstr ""
++msgstr "Relaxer les littéraux en assembleur et les placer automatiquement dans la section texte."
+ 
+ #: config/xtensa/xtensa.opt:47
+-#, fuzzy
+-#| msgid "Do not serialize volatile memory references with MEMW instructions"
+ msgid "-mno-serialize-volatile\tDo not serialize volatile memory references with MEMW instructions."
+-msgstr "Ne pas sérialiser les références à la mémoire volatile avec des instructions MEMW"
++msgstr "-mno-serialize-volatile\tNe pas sérialiser les références à la mémoire volatile avec des instructions MEMW."
+ 
+ #: config/i386/cygming.opt:23
+-#, fuzzy
+-#| msgid "Create console application"
+ msgid "Create console application."
+-msgstr "Créer une application de type console"
++msgstr "Créer une application de type console."
+ 
+ #: config/i386/cygming.opt:27
+-#, fuzzy
+-#| msgid "Generate code for a DLL"
+ msgid "Generate code for a DLL."
+-msgstr "Générer le code pour un DLL"
++msgstr "Générer le code pour une DLL."
+ 
+ #: config/i386/cygming.opt:31
+-#, fuzzy
+-#| msgid "Ignore dllimport for functions"
+ msgid "Ignore dllimport for functions."
+-msgstr "Ignorer dllimport pour fonctions"
++msgstr "Ignorer dllimport pour les fonctions."
+ 
+ #: config/i386/cygming.opt:35
+-#, fuzzy
+-#| msgid "Use Mingw-specific thread support"
+ msgid "Use Mingw-specific thread support."
+-msgstr "Utilise le support de thread spécifique à Mingw"
++msgstr "Utiliser le support de threads spécifique à Mingw."
+ 
+ #: config/i386/cygming.opt:39
+-#, fuzzy
+-#| msgid "Set Windows defines"
+ msgid "Set Windows defines."
+-msgstr "Initialiser les définitions Windows"
++msgstr "Initialiser les définitions Windows."
+ 
+ #: config/i386/cygming.opt:43
+-#, fuzzy
+-#| msgid "Create GUI application"
+ msgid "Create GUI application."
+-msgstr "Créer une application de type GUI"
++msgstr "Créer une application de type GUI."
+ 
+ #: config/i386/cygming.opt:47 config/i386/interix.opt:32
+ msgid "Use the GNU extension to the PE format for aligned common data."
+-msgstr ""
++msgstr "Utiliser l'extension GNU du format PE pour les données communes alignées."
+ 
+ #: config/i386/cygming.opt:51
+ msgid "Compile code that relies on Cygwin DLL wrappers to support C++ operator new/delete replacement."
+-msgstr ""
++msgstr "Compiler du code qui repose sur la surcouche de la DLL Cygwin pour supporter le remplacement des opérateurs new et delete du C++."
+ 
+ #: config/i386/cygming.opt:58
+ msgid "Put relocated read-only data into .data section."
+-msgstr ""
++msgstr "Placer les données relocalisées en lecture seule dans la section .data."
+ 
+ #: config/i386/mingw.opt:29
+ msgid "Warn about none ISO msvcrt scanf/printf width extensions."
+-msgstr ""
++msgstr "Avertir à propos des extensions de largeur de scanf/printf de msvcrt qui ne sont pas ISO."
+ 
+ #: config/i386/mingw.opt:33
+ msgid "For nested functions on stack executable permission is set."
+-msgstr ""
++msgstr "Activer la permission d'exécution sur la pile pour les fonctions imbriquées."
+ 
+ #: config/i386/mingw-w64.opt:23
+ msgid "Use unicode startup and define UNICODE macro."
+-msgstr ""
++msgstr "Utiliser une amorce unicode et défini la macro UNICODE."
+ 
+ #: config/i386/i386.opt:182
+-#, fuzzy
+-#| msgid "sizeof(long double) is 16"
+ msgid "sizeof(long double) is 16."
+-msgstr "sizeof(long double) est 16"
++msgstr "sizeof(long double) vaut 16."
+ 
+ #: config/i386/i386.opt:186 config/i386/i386.opt:354
+-#, fuzzy
+-#| msgid "Use hardware fp"
+ msgid "Use hardware fp."
+-msgstr "Utiliser le FP matériel"
++msgstr "Utiliser le coprocesseur mathématique."
+ 
+ #: config/i386/i386.opt:190
+-#, fuzzy
+-#| msgid "sizeof(long double) is 12"
+ msgid "sizeof(long double) is 12."
+-msgstr "sizeof(long double) est 12"
++msgstr "sizeof(long double) vaut 12."
+ 
+ #: config/i386/i386.opt:194
+-#, fuzzy
+-#| msgid "Use 80-bit long double"
+ msgid "Use 80-bit long double."
+-msgstr "Utiliser un long double de 80 bits"
++msgstr "Utiliser un long double de 80 bits."
+ 
+ #: config/i386/i386.opt:198 config/s390/s390.opt:130
+ #: config/sparc/long-double-switch.opt:27 config/alpha/alpha.opt:102
+-#, fuzzy
+-#| msgid "Use 64-bit long double"
+ msgid "Use 64-bit long double."
+-msgstr "Utiliser un long double de 64 bits"
++msgstr "Utiliser un long double de 64 bits."
+ 
+ #: config/i386/i386.opt:202 config/s390/s390.opt:126
+ #: config/sparc/long-double-switch.opt:23 config/alpha/alpha.opt:98
+-#, fuzzy
+-#| msgid "Use 128-bit long double"
+ msgid "Use 128-bit long double."
+-msgstr "Utiliser un long double de 128 bits"
++msgstr "Utiliser un long double de 128 bits."
+ 
+ #: config/i386/i386.opt:206 config/sh/sh.opt:209
+-#, fuzzy
+-#| msgid "Do not move instructions into a function's prologue"
+ msgid "Reserve space for outgoing arguments in the function prologue."
+-msgstr "Ne pas déplacer les instruction dans le prologue de fonction"
++msgstr "Réserver de l'espace dans le prologue d'une fonction pour les arguments de sortie."
+ 
+ #: config/i386/i386.opt:210
+-#, fuzzy
+-#| msgid "Align some doubles on dword boundary"
+ msgid "Align some doubles on dword boundary."
+-msgstr "Aligner quelques doubles sur des frontières de mots doubles"
++msgstr "Aligner quelques doubles sur des frontières de mots doubles."
+ 
+ #: config/i386/i386.opt:214
+-#, fuzzy
+-#| msgid "Function starts are aligned to this power of 2"
+ msgid "Function starts are aligned to this power of 2."
+-msgstr "Débuts des fonction alignés selon une puissance de 2"
++msgstr "Aligner les débuts des fonctions sur une puissance de 2 de cette valeur."
+ 
+ #: config/i386/i386.opt:218
+-#, fuzzy
+-#| msgid "Jump targets are aligned to this power of 2"
+ msgid "Jump targets are aligned to this power of 2."
+-msgstr "Sauts de cibles alignés selon une puissance de 2"
++msgstr "Aligner les cibles des sauts sur une puissance de 2 de cette valeur."
+ 
+ #: config/i386/i386.opt:222
+-#, fuzzy
+-#| msgid "Loop code aligned to this power of 2"
+ msgid "Loop code aligned to this power of 2."
+-msgstr "Codes de boucles alignés selon une puissance de 2"
++msgstr "Aligner le code des boucles sur une puissance de 2 de cette valeur."
+ 
+ #: config/i386/i386.opt:226
+-#, fuzzy
+-#| msgid "Align destination of the string operations"
+ msgid "Align destination of the string operations."
+-msgstr "Aligner la destination des opérations sur les chaînes"
++msgstr "Aligner la destination des opérations sur les chaînes."
+ 
+ #: config/i386/i386.opt:230
+-#, fuzzy
+-#| msgid "Do not tune writable data alignment"
+ msgid "Use the given data alignment."
+-msgstr "Ne pas ajuster l'alignement les sections de données dynamiques"
++msgstr "Utiliser l'alignement de données spécifié."
+ 
+ #: config/i386/i386.opt:234
+ msgid "Known data alignment choices (for use with the -malign-data= option):"
+-msgstr ""
++msgstr "Choix connus pour l'alignement de données (à utiliser avec l'option -malign-data=):"
+ 
+ #: config/i386/i386.opt:251
+-#, fuzzy
+-#| msgid "Use given assembler dialect"
+ msgid "Use given assembler dialect."
+-msgstr "Utiliser la syntaxe de l'assembleur donné"
++msgstr "Utiliser le dialecte de l'assembleur donné."
+ 
+ #: config/i386/i386.opt:255
+ msgid "Known assembler dialects (for use with the -masm-dialect= option):"
+-msgstr ""
++msgstr "Dialectes d'assembleurs connus (à utiliser avec l'option -masm-dialect=):"
+ 
+ #: config/i386/i386.opt:265
+-#, fuzzy
+-#| msgid "Branches are this expensive (1-5, arbitrary units)"
+ msgid "Branches are this expensive (1-5, arbitrary units)."
+-msgstr "Branchements coûteux à ce point (1-4, unités arbitraires)"
++msgstr "Les branchements sont coûteux à ce point (1-5, unités arbitraires)."
+ 
+ #: config/i386/i386.opt:269
+ msgid "Data greater than given threshold will go into .ldata section in x86-64 medium model."
+-msgstr ""
++msgstr "Les données plus grandes que la limite spécifiée iront dans la section .ldata dans le modèle moyen du x86-64."
+ 
+ #: config/i386/i386.opt:273
+-#, fuzzy
+-#| msgid "Use given x86-64 code model"
+ msgid "Use given x86-64 code model."
+-msgstr "Utiliser le modèle de x86-64 donné"
++msgstr "Utiliser le modèle de code x86-64 donné."
+ 
+ #: config/i386/i386.opt:277 config/rs6000/aix64.opt:36
+ #: config/rs6000/linux64.opt:32 config/tilegx/tilegx.opt:57
+ msgid "Known code models (for use with the -mcmodel= option):"
+-msgstr ""
++msgstr "Modèles de code connus (à utiliser avec l'option -mcmodel=):"
+ 
+ #: config/i386/i386.opt:296
+-#, fuzzy
+-#| msgid "Use complex addressing modes"
+ msgid "Use given address mode."
+-msgstr "Utiliser les modes d'adressage complexes"
++msgstr "Utiliser le mode d'adressage spécifié."
+ 
+ #: config/i386/i386.opt:300
+ msgid "Known address mode (for use with the -maddress-mode= option):"
+-msgstr ""
++msgstr "Modes d'adressage connus (à utiliser avec l'option -maddress-mode=):"
+ 
+ #: config/i386/i386.opt:309
+-#, fuzzy
+-#| msgid "This switch is deprecated; use -Wextra instead"
+ msgid "%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead"
+-msgstr "Cette option est obsolète; utiliser -Wextra à la place"
++msgstr "%<-mcpu=%> est déprécié; utilisez plutôt %<-mtune=%> ou %<-march=%>"
+ 
+ #: config/i386/i386.opt:313
+-#, fuzzy
+-#| msgid "Generate sin, cos, sqrt for FPU"
+ msgid "Generate sin, cos, sqrt for FPU."
+-msgstr "Générer sin, cos, sqrt pour le FPU"
++msgstr "Générer sin, cos, sqrt pour le coprocesseur mathématique."
+ 
+ #: config/i386/i386.opt:317
+ msgid "Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack."
+-msgstr ""
++msgstr "Toujours utiliser DRAP (Dynamic Realigned Argument Pointer) pour ré-aligner la pile."
+ 
+ #: config/i386/i386.opt:321
+-#, fuzzy
+-#| msgid "Return values of functions in FPU registers"
+ msgid "Return values of functions in FPU registers."
+-msgstr "Retourner les valeurs de fonctions dans les registres FPU"
++msgstr "Retourner les valeurs de fonctions dans les registres du coprocesseur mathématique."
+ 
+ #: config/i386/i386.opt:325
+-#, fuzzy
+-#| msgid "Generate floating point mathematics using given instruction set"
+ msgid "Generate floating point mathematics using given instruction set."
+-msgstr "Générer les mathématiques en virgule flottante avec le jeu d'instructions données"
++msgstr "Générer les mathématiques en virgule flottante avec le jeu d'instructions donné."
+ 
+ #: config/i386/i386.opt:329
+-#, fuzzy
+-#| msgid "too many arguments for format"
+ msgid "Valid arguments to -mfpmath=:"
+-msgstr "trop d'arguments pour le format"
++msgstr "Arguments valides pour -mfpmath=:"
+ 
+ #: config/i386/i386.opt:362
+-#, fuzzy
+-#| msgid "Inline all known string operations"
+ msgid "Inline all known string operations."
+-msgstr "Permettre l'enlignage dans toutes les opérations portant sur les chaînes"
++msgstr "Mettre en ligne toutes les opérations connues sur des chaînes."
+ 
+ #: config/i386/i386.opt:366
+ msgid "Inline memset/memcpy string operations, but perform inline version only for small blocks."
+-msgstr ""
++msgstr "Mettre en ligne les opérations memset/memcpy sur des chaînes mais n'exécuter la version en ligne que pour des petits blocs."
+ 
+ #: config/i386/i386.opt:369
+ msgid "%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead"
+-msgstr ""
++msgstr "%<-mintel-syntax%> et %<-mno-intel-syntax%> sont dépréciés; utilisez plutôt %<-masm=intel%> et %<-masm=att%>"
+ 
+ #: config/i386/i386.opt:374
+-#, fuzzy
+-#| msgid "Use native (MS) bitfield layout"
+ msgid "Use native (MS) bitfield layout."
+-msgstr "Utiliser une configuration de champ de bits native (MS)"
++msgstr "Utiliser une disposition des champs de bits native (MS)."
+ 
+ #: config/i386/i386.opt:394
+-#, fuzzy
+-#| msgid "Return floating point results in ac0"
+ msgid "Set 80387 floating-point precision to 32-bit."
+-msgstr "Le résultat retourné en virgule flottante se retrouve dans AC0."
++msgstr "Fixer la précision en virgule flottante du 80387 à 32 bits."
+ 
+ #: config/i386/i386.opt:398
+-#, fuzzy
+-#| msgid "Return floating point results in ac0"
+ msgid "Set 80387 floating-point precision to 64-bit."
+-msgstr "Le résultat retourné en virgule flottante se retrouve dans AC0."
++msgstr "Fixer la précision en virgule flottante du 80387 à 64 bits."
+ 
+ #: config/i386/i386.opt:402
+-#, fuzzy
+-#| msgid "Return floating point results in ac0"
+ msgid "Set 80387 floating-point precision to 80-bit."
+-msgstr "Le résultat retourné en virgule flottante se retrouve dans AC0."
++msgstr "Fixer la précision en virgule flottante du 80387 à 80 bits."
+ 
+ #: config/i386/i386.opt:406
+-#, fuzzy
+-#| msgid "Attempt to keep stack aligned to this power of 2"
+ msgid "Attempt to keep stack aligned to this power of 2."
+-msgstr "Tentative de conservation de la pile alignée selon une puissance de 2"
++msgstr "Essayer de conserver l'alignement de la pile sur cette puissance de 2."
+ 
+ #: config/i386/i386.opt:410
+-#, fuzzy
+-#| msgid "Attempt to keep stack aligned to this power of 2"
+ msgid "Assume incoming stack aligned to this power of 2."
+-msgstr "Tentative de conservation de la pile alignée selon une puissance de 2"
++msgstr "Supposer que l'alignement de la pile entrante est sur cette puissance de 2."
+ 
+ #: config/i386/i386.opt:414
+-#, fuzzy
+-#| msgid "Use push instructions to save outgoing arguments"
+ msgid "Use push instructions to save outgoing arguments."
+-msgstr "Utiliser les instructions push pour sauvegardes les arguments sortants"
++msgstr "Utiliser les instructions push pour sauvegardes les arguments sortants."
+ 
+ #: config/i386/i386.opt:418
+-#, fuzzy
+-#| msgid "Use red-zone in the x86-64 code"
+ msgid "Use red-zone in the x86-64 code."
+-msgstr "Utiliser la zone-rouge pour le code x86-64"
++msgstr "Utiliser une zone rouge (espace réservé sur la pile pour usage par l'appelé) dans le code x86-64."
+ 
+ #: config/i386/i386.opt:422
+-#, fuzzy
+-#| msgid "Number of registers used to pass integer arguments"
+ msgid "Number of registers used to pass integer arguments."
+-msgstr "Nombre de registres utilisés pour passer les arguments entiers"
++msgstr "Nombre de registres utilisés pour passer les arguments entiers."
+ 
+ #: config/i386/i386.opt:426
+-#, fuzzy
+-#| msgid "Alternate calling convention"
+ msgid "Alternate calling convention."
+-msgstr "Convention alternative d'appels"
++msgstr "Convention d'appel alternative."
+ 
+ #: config/i386/i386.opt:430 config/alpha/alpha.opt:23
+-#, fuzzy
+-#| msgid "Do not use hardware fp"
+ msgid "Do not use hardware fp."
+-msgstr "Ne pas utiliser l'unité FP matérielle"
++msgstr "Ne pas utiliser le coprocesseur mathématique."
+ 
+ #: config/i386/i386.opt:434
+ msgid "Use SSE register passing conventions for SF and DF mode."
+-msgstr ""
++msgstr "Utiliser les conventions de passage des registres SSE pour les modes SF et DF."
+ 
+ #: config/i386/i386.opt:438
+ msgid "Realign stack in prologue."
+-msgstr ""
++msgstr "Ré-aligner la pile dans le prologue."
+ 
+ #: config/i386/i386.opt:442
+-#, fuzzy
+-#| msgid "Enable stack probing"
+ msgid "Enable stack probing."
+-msgstr "Autoriser le sondage de la pile"
++msgstr "Autoriser le sondage de la pile."
+ 
+ #: config/i386/i386.opt:446
+ msgid "Specify memcpy expansion strategy when expected size is known."
+-msgstr ""
++msgstr "Spécifier la stratégie d'expansion de memcpy quand la taille attendue est connue."
+ 
+ #: config/i386/i386.opt:450
+ msgid "Specify memset expansion strategy when expected size is known."
+-msgstr ""
++msgstr "Spécifier la stratégie d'expansion de memset quand la taille attendue est connue."
+ 
+ #: config/i386/i386.opt:454
+-#, fuzzy
+-#| msgid "possible start of unterminated string literal"
+ msgid "Chose strategy to generate stringop using."
+-msgstr "début possible d'une chaîne de mot non terminée"
++msgstr "Choisir la stratégie pour générer du code en ligne pour les opérations sur des chaînes."
+ 
+ #: config/i386/i386.opt:458
+ msgid "Valid arguments to -mstringop-strategy=:"
+-msgstr ""
++msgstr "Les arguments valables pour -mstringop-strategy=:"
+ 
+ #: config/i386/i386.opt:486
+-#, fuzzy
+-#| msgid "Use given thread-local storage dialect"
+ msgid "Use given thread-local storage dialect."
+-msgstr "Utiliser le dialecte de stockage du thread local fourni"
++msgstr "Utiliser le dialecte de stockage local au thread fourni."
+ 
+ #: config/i386/i386.opt:490
+ msgid "Known TLS dialects (for use with the -mtls-dialect= option):"
+-msgstr ""
++msgstr "Dialectes TLS connus (à utiliser avec l'option -mtls-dialect=):"
+ 
+ #: config/i386/i386.opt:500
+-#, fuzzy, c-format
+-#| msgid "Use direct references against %gs when accessing tls data"
++#, c-format
+ msgid "Use direct references against %gs when accessing tls data."
+-msgstr "Utiliser la référence directe envers %gs lors de l'accès des données tls"
++msgstr "Utiliser les références directes envers %gs lors de l'accès des données TLS."
+ 
+ #: config/i386/i386.opt:508
+-#, fuzzy
+-#| msgid "Allow all ugly features"
+ msgid "Fine grain control of tune features."
+-msgstr "Permettre toutes les options laides"
++msgstr "Contrôle fin des fonctionnalités d'ajustement."
+ 
+ #: config/i386/i386.opt:512
+-#, fuzzy
+-#| msgid "Allow all ugly features"
+ msgid "Clear all tune features."
+-msgstr "Permettre toutes les options laides"
++msgstr "Effacer toutes les fonctionnalités d'ajustement."
+ 
+ #: config/i386/i386.opt:519
+-#, fuzzy
+-#| msgid "Generate code for given CPU"
+ msgid "Generate code that conforms to Intel MCU psABI."
+-msgstr "Générer le code pour le processeur donné"
++msgstr "Générer du code conforme à l'ABI spécifique au processeur (psABI) du MCU Intel."
+ 
+ #: config/i386/i386.opt:523
+-#, fuzzy
+-#| msgid "Generate code for given CPU"
+ msgid "Generate code that conforms to the given ABI."
+-msgstr "Générer le code pour le processeur donné"
++msgstr "Générer du code conforme à l'ABI spécifiée."
+ 
+ #: config/i386/i386.opt:527
+ msgid "Known ABIs (for use with the -mabi= option):"
+-msgstr ""
++msgstr "ABI connues (à utiliser avec l'option -mabi=):"
+ 
+ #: config/i386/i386.opt:537 config/rs6000/rs6000.opt:189
+-#, fuzzy
+-#| msgid "Specify ABI to use"
+ msgid "Vector library ABI to use."
+-msgstr "Spécifier l'ABI à utiliser"
++msgstr "ABI de la bibliothèque vectorielle à utiliser."
+ 
+ #: config/i386/i386.opt:541
+ msgid "Known vectorization library ABIs (for use with the -mveclibabi= option):"
+-msgstr ""
++msgstr "ABI des bibliothèques vectorielles connues (à utiliser avec l'option -mveclibabi=):"
+ 
+ #: config/i386/i386.opt:551
+-#, fuzzy
+-#| msgid "Return floating point results in memory"
+ msgid "Return 8-byte vectors in memory."
+-msgstr "Le résultat retourné en virgule flottante se retrouve en mémoire."
++msgstr "Retourner des vecteurs de 8 octets en mémoire."
+ 
+ #: config/i386/i386.opt:555
+ msgid "Generate reciprocals instead of divss and sqrtss."
+-msgstr ""
++msgstr "Générer des réciproques au lieu de divss et sqrtss."
+ 
+ #: config/i386/i386.opt:559
+ msgid "Control generation of reciprocal estimates."
+-msgstr ""
++msgstr "Contrôle la génération des estimations réciproques."
+ 
+ #: config/i386/i386.opt:563
+-#, fuzzy
+-#| msgid "Do not move instructions into a function's prologue"
+ msgid "Generate cld instruction in the function prologue."
+-msgstr "Ne pas déplacer les instruction dans le prologue de fonction"
++msgstr "Générer l'instruction cld dans le prologue de fonctions."
+ 
+ #: config/i386/i386.opt:567
+ msgid "Generate vzeroupper instruction before a transfer of control flow out of"
+-msgstr ""
++msgstr "Générer l'instruction vzeroupper avant un transfert du flux de contrôle hors d'une fonction."
+ 
+ #: config/i386/i386.opt:572
+ msgid "Disable Scalar to Vector optimization pass transforming 64-bit integer"
+-msgstr ""
++msgstr "Désactiver la passe d'optimisation de scalaires en vecteurs qui transforme les calculs sur des entiers de 64 bits en calculs sur des vecteurs."
+ 
+ #: config/i386/i386.opt:577
+ msgid "Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4"
+-msgstr ""
++msgstr "Effectuer le changement de contexte de l'ordonnanceur si le processeur est un bdver1, bdver2, bdver3, bdver4 ou znver1 et l'ordonnancement Haifa est sélectionné."
+ 
+ #: config/i386/i386.opt:582
+ msgid "Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer."
+-msgstr ""
++msgstr "Utiliser les instructions AVX 128 bits au lieu des instructions AVX 256 bits dans le vectoriseur automatique."
+ 
+ #: config/i386/i386.opt:588
+-#, fuzzy
+-#| msgid "Generate 32bit i386 code"
+ msgid "Generate 32bit i386 code."
+-msgstr "Générer du code 32 bits pour i386"
++msgstr "Générer du code 32 bits pour i386."
+ 
+ #: config/i386/i386.opt:592
+-#, fuzzy
+-#| msgid "Generate 64bit x86-64 code"
+ msgid "Generate 64bit x86-64 code."
+-msgstr "Générer du code 64 bits pour x86-64"
++msgstr "Générer du code 64 bits pour x86-64."
+ 
+ #: config/i386/i386.opt:596
+-#, fuzzy
+-#| msgid "Generate 32bit x86-64 code"
+ msgid "Generate 32bit x86-64 code."
+-msgstr "Générer du code 32 bits pour x86-64"
++msgstr "Générer du code 32 bits pour x86-64."
+ 
+ #: config/i386/i386.opt:600
+-#, fuzzy
+-#| msgid "Generate 16bit i386 code"
+ msgid "Generate 16bit i386 code."
+-msgstr "Générer du code 16 bits pour i386"
++msgstr "Générer du code 16 bits pour i386."
+ 
+ #: config/i386/i386.opt:604
+-#, fuzzy
+-#| msgid "Support MMX built-in functions"
+ msgid "Support MMX built-in functions."
+-msgstr "Supporte les fonctions internes MMX"
++msgstr "Supporter les fonctions internes MMX."
+ 
+ #: config/i386/i386.opt:608
+-#, fuzzy
+-#| msgid "Support 3DNow! built-in functions"
+ msgid "Support 3DNow! built-in functions."
+-msgstr "Supporte les fonctions internes 3DNOW!"
++msgstr "Supporter les fonctions internes 3DNow!."
+ 
+ #: config/i386/i386.opt:612
+-#, fuzzy
+-#| msgid "Support Athlon 3Dnow! built-in functions"
+ msgid "Support Athlon 3Dnow! built-in functions."
+-msgstr "Supporte les fonctions internes 3DNOW!"
++msgstr "Supporter les fonctions internes 3DNow! de l'Athlon."
+ 
+ #: config/i386/i386.opt:616
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support MMX and SSE built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes MMX et SSE et la génération de code."
+ 
+ #: config/i386/i386.opt:620
+-#, fuzzy
+-#| msgid "Support MMX, SSE and SSE2 built-in functions and code generation"
+ msgid "Support MMX, SSE and SSE2 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE et SSE2 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE et SSE2 et la génération de code."
+ 
+ #: config/i386/i386.opt:624
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code."
+ 
+ #: config/i386/i386.opt:628
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3 et SSSE3 et la génération de code."
+ 
+ #: config/i386/i386.opt:632
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3 et SSE4.1 et la génération de code."
+ 
+ #: config/i386/i386.opt:636 config/i386/i386.opt:640
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 et SSE4.2 et la génération de code."
+ 
+ #: config/i386/i386.opt:644
+-#, fuzzy
+-#| msgid "Do not support MMX, SSE and SSE2 built-in functions and code generation"
+ msgid "Do not support SSE4.1 and SSE4.2 built-in functions and code generation."
+-msgstr "Ne supporte pas les fonctions internes MMX, SSE et SSE2 et la génération de code"
++msgstr "Ne pas supporter les fonctions internes SSE4.1 et SSE4.2 et la génération de code."
+ 
+ #: config/i386/i386.opt:647
+ msgid "%<-msse5%> was removed"
+-msgstr ""
++msgstr "%<-msse5%> a été supprimé"
+ 
+ #: config/i386/i386.opt:652
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 et AVX et la génération de code."
+ 
+ #: config/i386/i386.opt:656
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX et AVX2 et la génération de code."
+ 
+ #: config/i386/i386.opt:660
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 et AVX512F et la génération de code."
+ 
+ #: config/i386/i386.opt:664
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512PF et la génération de code."
+ 
+ #: config/i386/i386.opt:668
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512ER et la génération de code."
+ 
+ #: config/i386/i386.opt:672
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512CD et la génération de code."
+ 
+ #: config/i386/i386.opt:676
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512DQ et la génération de code."
+ 
+ #: config/i386/i386.opt:680
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512BW et la génération de code."
+ 
+ #: config/i386/i386.opt:684
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512VL et la génération de code."
+ 
+ #: config/i386/i386.opt:688
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512IFMA et la génération de code."
+ 
+ #: config/i386/i386.opt:692
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F et AVX512VBMI et la génération de code."
+ 
+ #: config/i386/i386.opt:696
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX et FMA et la génération de code."
+ 
+ #: config/i386/i386.opt:700
+-#, fuzzy
+-#| msgid "Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation"
+ msgid "Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX, SSE, SSE2 et SSE3 et la génération de code"
++msgstr "Supporter les fonctions internes MMX, SSE, SSE2, SSE3 et SSE4A et la génération de code."
+ 
+ #: config/i386/i386.opt:704
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support FMA4 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes FMA4 et la génération de code."
+ 
+ #: config/i386/i386.opt:708
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support XOP built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes XOP et la génération de code."
+ 
+ #: config/i386/i386.opt:712
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support LWP built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes LWP et la génération de code."
+ 
+ #: config/i386/i386.opt:716
+ msgid "Support code generation of Advanced Bit Manipulation (ABM) instructions."
+-msgstr ""
++msgstr "Supporter la génération de code des instructions ABM (Advanced Bit Manipulation)."
+ 
+ #: config/i386/i386.opt:720
+-#, fuzzy
+-#| msgid "Do not generate single field mfcr instruction"
+ msgid "Support code generation of popcnt instruction."
+-msgstr "Ne pas générer des instructions à champ simple mfcr"
++msgstr "Supporter la génération de code de l'instruction popcnt."
+ 
+ #: config/i386/i386.opt:724
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support BMI built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes BMI et la génération de code."
+ 
+ #: config/i386/i386.opt:728
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support BMI2 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes BMI2 et la génération de code."
+ 
+ #: config/i386/i386.opt:732
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support LZCNT built-in function and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes LZCNT et la génération de code."
+ 
+ #: config/i386/i386.opt:736
+ msgid "Support Hardware Lock Elision prefixes."
+-msgstr ""
++msgstr "Supporter les préfixes pour l'élision matérielle des verrous (Hardware Lock Elision)."
+ 
+ #: config/i386/i386.opt:740
+-#, fuzzy
+-#| msgid "Support RDSEED instruction"
+ msgid "Support RDSEED instruction."
+-msgstr "Supporte l'instruction RDSEED"
++msgstr "Supporter l'instruction RDSEED."
+ 
+ #: config/i386/i386.opt:744
+-#, fuzzy
+-#| msgid "Support PREFETCHW instruction"
+ msgid "Support PREFETCHW instruction."
+-msgstr "Supporte l'instruction PREFETCHW"
++msgstr "Supporter l'instruction PREFETCHW."
+ 
+ #: config/i386/i386.opt:748
+-#, fuzzy
+-#| msgid "Do not generate char instructions"
+ msgid "Support flag-preserving add-carry instructions."
+-msgstr "Ne pas générer des instructions « char »"
++msgstr "Supporter les instructions de préservation du fanion de report de l'addition."
+ 
+ #: config/i386/i386.opt:752
+-#, fuzzy
+-#| msgid "Support CLFLUSHOPT instructions"
+ msgid "Support CLFLUSHOPT instructions."
+-msgstr "Supporte les instructions CLFLUSHOPT"
++msgstr "Supporter les instructions CLFLUSHOPT."
+ 
+ #: config/i386/i386.opt:756
+-#, fuzzy
+-#| msgid "Support CLWB instruction"
+ msgid "Support CLWB instruction."
+-msgstr "Supporte l'instruction CLWB"
++msgstr "Supporter l'instruction CLWB."
+ 
+ #: config/i386/i386.opt:760
+-#, fuzzy
+-#| msgid "Support PCOMMIT instruction"
+ msgid "Support PCOMMIT instruction."
+-msgstr "Supporte l'instruction PCOMMIT"
++msgstr "Supporter l'instruction PCOMMIT."
+ 
+ #: config/i386/i386.opt:764
+-#, fuzzy
+-#| msgid "Support FXSAVE and FXRSTOR instructions"
+ msgid "Support FXSAVE and FXRSTOR instructions."
+-msgstr "Supporte les instructions FXSAVE et FXRSTOR"
++msgstr "Supporter les instructions FXSAVE et FXRSTOR."
+ 
+ #: config/i386/i386.opt:768
+-#, fuzzy
+-#| msgid "Support XSAVE and XRSTOR instructions"
+ msgid "Support XSAVE and XRSTOR instructions."
+-msgstr "Supporter les instructions XSAVE et XRSTOR"
++msgstr "Supporter les instructions XSAVE et XRSTOR."
+ 
+ #: config/i386/i386.opt:772
+-#, fuzzy
+-#| msgid "Support XSAVEOPT instruction"
+ msgid "Support XSAVEOPT instruction."
+-msgstr "Supporte les instructions XSAVEOPT"
++msgstr "Supporter l'instruction XSAVEOPT."
+ 
+ #: config/i386/i386.opt:776
+-#, fuzzy
+-#| msgid "Support XSAVEC instructions"
+ msgid "Support XSAVEC instructions."
+-msgstr "Supporte les instructions XSAVEC"
++msgstr "Supporter les instructions XSAVEC."
+ 
+ #: config/i386/i386.opt:780
+-#, fuzzy
+-#| msgid "Support XSAVES and XRSTORS instructions"
+ msgid "Support XSAVES and XRSTORS instructions."
+-msgstr "Supporte les instructions XSAVES et XRSTORS"
++msgstr "Supporter les instructions XSAVES et XRSTORS."
+ 
+ #: config/i386/i386.opt:784
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support TBM built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes TBM et la génération de code."
+ 
+ #: config/i386/i386.opt:788
+-#, fuzzy
+-#| msgid "Do not generate single field mfcr instruction"
+ msgid "Support code generation of cmpxchg16b instruction."
+-msgstr "Ne pas générer des instructions à champ simple mfcr"
++msgstr "Supporter la génération de code pour l'instruction cmpxchg16b."
+ 
+ #: config/i386/i386.opt:792
+ msgid "Support code generation of sahf instruction in 64bit x86-64 code."
+-msgstr ""
++msgstr "Supporter la génération de code pour l'instruction sahf dans le code x86-64 en 64 bit."
+ 
+ #: config/i386/i386.opt:796
+-#, fuzzy
+-#| msgid "Do not generate single field mfcr instruction"
+ msgid "Support code generation of movbe instruction."
+-msgstr "Ne pas générer des instructions à champ simple mfcr"
++msgstr "Supporter la génération de code pour l'instruction movbe."
+ 
+ #: config/i386/i386.opt:800
+-#, fuzzy
+-#| msgid "Do not generate char instructions"
+ msgid "Support code generation of crc32 instruction."
+-msgstr "Ne pas générer des instructions « char »"
++msgstr "Supporter la génération de code pour l'instruction crc32."
+ 
+ #: config/i386/i386.opt:804
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support AES built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes AES et la génération de code."
+ 
+ #: config/i386/i386.opt:808
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support SHA1 and SHA256 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes SHA1 et SHA256 et la génération de code."
+ 
+ #: config/i386/i386.opt:812
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support PCLMUL built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes PCLMUL et la génération de code."
+ 
+ #: config/i386/i386.opt:816
+ msgid "Encode SSE instructions with VEX prefix."
+-msgstr ""
++msgstr "Encoder les instructions SSE avec le préfixe VEX."
+ 
+ #: config/i386/i386.opt:820
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support FSGSBASE built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes FSGSBASE et la génération de code."
+ 
+ #: config/i386/i386.opt:824
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support RDRND built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes RDRND et la génération de code."
+ 
+ #: config/i386/i386.opt:828
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support F16C built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes F16C et la génération de code."
+ 
+ #: config/i386/i386.opt:832
+-#, fuzzy
+-#| msgid "Support MMX and SSE built-in functions and code generation"
+ msgid "Support PREFETCHWT1 built-in functions and code generation."
+-msgstr "Supporte les fonctions internes MMX et SSE et la génération de code"
++msgstr "Supporter les fonctions internes PREFETCHWT1 et la génération de code."
+ 
+ #: config/i386/i386.opt:836
+-#, fuzzy
+-#| msgid "Call mcount for profiling after a function prologue"
+ msgid "Emit profiling counter call at function entry before prologue."
+-msgstr "Ne pas appeler mcount pour le profilage avant le prologue de la fonction"
++msgstr "Émettre un appel au compteur de profilage avant le prologue lors de l'entrée dans une fonction."
+ 
+ #: config/i386/i386.opt:840
+ msgid "Generate __mcount_loc section with all mcount or __fentry__ calls."
+-msgstr ""
++msgstr "Générer une section __mcount_loc avec tous des appels à mcount ou __fentry__."
+ 
+ #: config/i386/i386.opt:844
+ msgid "Generate mcount/__fentry__ calls as nops. To activate they need to be"
+-msgstr ""
++msgstr "Générer les appels mcount/__fentry__ sous forme de nops. Pour les activer, il faut insérer les instructions réelles."
+ 
+ #: config/i386/i386.opt:849
+ msgid "Skip setting up RAX register when passing variable arguments."
+-msgstr ""
++msgstr "Passe outre la préparation du registre RAX lors du passage d'arguments variables."
+ 
+ #: config/i386/i386.opt:853
+ msgid "Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check."
+-msgstr ""
++msgstr "Remplacer les divisions entières sur 32 ou 64 bits par des divisions sur 8 bits non signées avec vérification à l'exécution."
+ 
+ #: config/i386/i386.opt:857
+ msgid "Split 32-byte AVX unaligned load."
+-msgstr ""
++msgstr "Scinder les chargements AVX non alignés de 32 octets"
+ 
+ #: config/i386/i386.opt:861
+ msgid "Split 32-byte AVX unaligned store."
+-msgstr ""
++msgstr "Scinder les stockages AVX non alignés de 32 octets."
+ 
+ #: config/i386/i386.opt:865
+ #, fuzzy
+Index: gcc/po/ChangeLog
+===================================================================
+--- a/src/gcc/po/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/po/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,25 @@
++2017-01-02  Joseph Myers  <joseph@codesourcery.com>
++
++	* es.po: Update.
++
++2016-12-30  Jakub Jelinek  <jakub@redhat.com>
++
++	PR translation/78745
++	* exgettext: Handle multi-line help texts in *.opt files.
++	* gcc.pot: Regenerate.
++
++2016-12-30  Joseph Myers  <joseph@codesourcery.com>
++
++	* es.po, fr.po: Update.
++
++2016-12-27  Jakub Jelinek  <jakub@redhat.com>
++
++	* gcc.pot: Regenerate.
++
++2016-12-22  Joseph Myers  <joseph@codesourcery.com>
++
++	* es.po: Update.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: gcc/po/gcc.pot
+===================================================================
+--- a/src/gcc/po/gcc.pot	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/po/gcc.pot	(.../branches/gcc-6-branch)
+@@ -8,7 +8,7 @@
+ msgstr ""
+ "Project-Id-Version: PACKAGE VERSION\n"
+ "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
+-"POT-Creation-Date: 2016-08-19 21:03+0000\n"
++"POT-Creation-Date: 2016-12-30 20:16+0100\n"
+ "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+ "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+ "Language-Team: LANGUAGE <LL@li.org>\n"
+@@ -98,7 +98,7 @@
+ msgid "%s: some warnings being treated as errors"
+ msgstr ""
+ 
+-#: diagnostic.c:290 input.c:169 c-family/c-opts.c:1310 cp/error.c:1196
++#: diagnostic.c:290 input.c:169 c-family/c-opts.c:1310 cp/error.c:1195
+ #: fortran/cpp.c:576 fortran/error.c:996 fortran/error.c:1016
+ msgid "<built-in>"
+ msgstr ""
+@@ -188,13 +188,13 @@
+ #. TARGET_PRINT_OPERAND must handle them.
+ #. We can't handle floating point constants;
+ #. PRINT_OPERAND must handle them.
+-#: final.c:3940 config/arc/arc.c:4817 config/i386/i386.c:15968
++#: final.c:3940 config/arc/arc.c:4817 config/i386/i386.c:16020
+ #: config/pdp11/pdp11.c:1691
+ #, c-format
+ msgid "floating constant misused"
+ msgstr ""
+ 
+-#: final.c:3998 config/arc/arc.c:4889 config/i386/i386.c:16066
++#: final.c:3998 config/arc/arc.c:4889 config/i386/i386.c:16118
+ #: config/pdp11/pdp11.c:1732
+ #, c-format
+ msgid "invalid expression as operand"
+@@ -1077,7 +1077,7 @@
+ msgid "GCSE disabled"
+ msgstr ""
+ 
+-#: gimple-ssa-isolate-paths.c:440 c/c-typeck.c:9773
++#: gimple-ssa-isolate-paths.c:440 c/c-typeck.c:9783
+ #, gcc-internal-format
+ msgid "function returns address of local variable"
+ msgstr ""
+@@ -1102,17 +1102,17 @@
+ msgid "ignoring nonexistent directory \"%s\"\n"
+ msgstr ""
+ 
+-#: incpath.c:373
++#: incpath.c:374
+ #, c-format
+ msgid "#include \"...\" search starts here:\n"
+ msgstr ""
+ 
+-#: incpath.c:377
++#: incpath.c:378
+ #, c-format
+ msgid "#include <...> search starts here:\n"
+ msgstr ""
+ 
+-#: incpath.c:382
++#: incpath.c:383
+ #, c-format
+ msgid "End of search list.\n"
+ msgstr ""
+@@ -1141,25 +1141,25 @@
+ msgid "At top level:"
+ msgstr ""
+ 
+-#: langhooks.c:393 cp/error.c:3315
++#: langhooks.c:393 cp/error.c:3314
+ #, c-format
+ msgid "In member function %qs"
+ msgstr ""
+ 
+-#: langhooks.c:397 cp/error.c:3318
++#: langhooks.c:397 cp/error.c:3317
+ #, c-format
+ msgid "In function %qs"
+ msgstr ""
+ 
+-#: langhooks.c:448 cp/error.c:3268
++#: langhooks.c:448 cp/error.c:3267
+ msgid "    inlined from %qs at %r%s:%d:%d%R"
+ msgstr ""
+ 
+-#: langhooks.c:453 cp/error.c:3273
++#: langhooks.c:453 cp/error.c:3272
+ msgid "    inlined from %qs at %r%s:%d%R"
+ msgstr ""
+ 
+-#: langhooks.c:459 cp/error.c:3279
++#: langhooks.c:459 cp/error.c:3278
+ #, c-format
+ msgid "    inlined from %qs"
+ msgstr ""
+@@ -1184,7 +1184,7 @@
+ msgid "this is the insn:"
+ msgstr ""
+ 
+-#: lra-constraints.c:3564 reload.c:3830
++#: lra-constraints.c:3589 reload.c:3830
+ msgid "unable to generate reloads for:"
+ msgstr ""
+ 
+@@ -1397,8 +1397,8 @@
+ msgid "options enabled: "
+ msgstr ""
+ 
+-#: tree-diagnostic.c:295 c/c-decl.c:5203 c/c-typeck.c:6818 cp/error.c:682
+-#: cp/error.c:995 c-family/c-pretty-print.c:408
++#: tree-diagnostic.c:295 c/c-decl.c:5203 c/c-typeck.c:6828 cp/error.c:682
++#: cp/error.c:994 c-family/c-pretty-print.c:411
+ #, gcc-internal-format
+ msgid "<anonymous>"
+ msgstr ""
+@@ -2929,8 +2929,8 @@
+ msgid "<command-line>"
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.c:4451 config/arm/arm.c:21959 config/arm/arm.c:21972
+-#: config/arm/arm.c:21997 config/nios2/nios2.c:2642
++#: config/aarch64/aarch64.c:4451 config/arm/arm.c:21958 config/arm/arm.c:21971
++#: config/arm/arm.c:21996 config/nios2/nios2.c:2642
+ #, c-format
+ msgid "Unsupported operand for code '%c'"
+ msgstr ""
+@@ -2949,7 +2949,7 @@
+ msgid "incompatible floating point / vector register operand for '%%%c'"
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.c:4627 config/arm/arm.c:22504
++#: config/aarch64/aarch64.c:4627 config/arm/arm.c:22503
+ #, c-format
+ msgid "missing operand"
+ msgstr ""
+@@ -2969,8 +2969,8 @@
+ msgid "invalid operand prefix '%%%c'"
+ msgstr ""
+ 
+-#: config/alpha/alpha.c:5102 config/i386/i386.c:17140
+-#: config/rs6000/rs6000.c:21150 config/sparc/sparc.c:8749
++#: config/alpha/alpha.c:5102 config/i386/i386.c:17192
++#: config/rs6000/rs6000.c:21180 config/sparc/sparc.c:8748
+ #, c-format
+ msgid "'%%&' used without any local dynamic TLS references"
+ msgstr ""
+@@ -2986,18 +2986,18 @@
+ msgstr ""
+ 
+ #: config/alpha/alpha.c:5200 config/ia64/ia64.c:5436
+-#: config/rs6000/rs6000.c:20830 config/xtensa/xtensa.c:2357
++#: config/rs6000/rs6000.c:20860 config/xtensa/xtensa.c:2357
+ #, c-format
+ msgid "invalid %%R value"
+ msgstr ""
+ 
+-#: config/alpha/alpha.c:5206 config/rs6000/rs6000.c:20750
++#: config/alpha/alpha.c:5206 config/rs6000/rs6000.c:20780
+ #: config/xtensa/xtensa.c:2324
+ #, c-format
+ msgid "invalid %%N value"
+ msgstr ""
+ 
+-#: config/alpha/alpha.c:5214 config/rs6000/rs6000.c:20778
++#: config/alpha/alpha.c:5214 config/rs6000/rs6000.c:20808
+ #, c-format
+ msgid "invalid %%P value"
+ msgstr ""
+@@ -3028,7 +3028,7 @@
+ msgstr ""
+ 
+ #: config/alpha/alpha.c:5300 config/alpha/alpha.c:5311
+-#: config/rs6000/rs6000.c:20838
++#: config/rs6000/rs6000.c:20868
+ #, c-format
+ msgid "invalid %%s value"
+ msgstr ""
+@@ -3038,7 +3038,7 @@
+ msgid "invalid %%C value"
+ msgstr ""
+ 
+-#: config/alpha/alpha.c:5359 config/rs6000/rs6000.c:20614
++#: config/alpha/alpha.c:5359 config/rs6000/rs6000.c:20644
+ #, c-format
+ msgid "invalid %%E value"
+ msgstr ""
+@@ -3049,7 +3049,7 @@
+ msgstr ""
+ 
+ #: config/alpha/alpha.c:5393 config/cr16/cr16.c:1531
+-#: config/rs6000/rs6000.c:21155 config/spu/spu.c:1446
++#: config/rs6000/rs6000.c:21185 config/spu/spu.c:1446
+ #, c-format
+ msgid "invalid %%xn code"
+ msgstr ""
+@@ -3102,7 +3102,7 @@
+ #. Unknown flag.
+ #. Undocumented flag.
+ #: config/arc/arc.c:3312 config/epiphany/epiphany.c:1286
+-#: config/m32r/m32r.c:2226 config/nds32/nds32.c:2291 config/sparc/sparc.c:8932
++#: config/m32r/m32r.c:2226 config/nds32/nds32.c:2291 config/sparc/sparc.c:8931
+ #, c-format
+ msgid "invalid operand output code"
+ msgstr ""
+@@ -3112,29 +3112,29 @@
+ msgid "invalid UNSPEC as operand: %d"
+ msgstr ""
+ 
+-#: config/arm/arm.c:19018 config/arm/arm.c:19043 config/arm/arm.c:19053
+-#: config/arm/arm.c:19062 config/arm/arm.c:19070
++#: config/arm/arm.c:19013 config/arm/arm.c:19038 config/arm/arm.c:19048
++#: config/arm/arm.c:19057 config/arm/arm.c:19065
+ #, c-format
+ msgid "invalid shift operand"
+ msgstr ""
+ 
+-#: config/arm/arm.c:21835 config/arm/arm.c:21853
++#: config/arm/arm.c:21834 config/arm/arm.c:21852
+ #, c-format
+ msgid "predicated Thumb instruction"
+ msgstr ""
+ 
+-#: config/arm/arm.c:21841
++#: config/arm/arm.c:21840
+ #, c-format
+ msgid "predicated instruction in conditional sequence"
+ msgstr ""
+ 
+-#: config/arm/arm.c:22074 config/arm/arm.c:22096 config/arm/arm.c:22106
+-#: config/arm/arm.c:22116 config/arm/arm.c:22126 config/arm/arm.c:22165
+-#: config/arm/arm.c:22183 config/arm/arm.c:22208 config/arm/arm.c:22223
+-#: config/arm/arm.c:22250 config/arm/arm.c:22257 config/arm/arm.c:22275
+-#: config/arm/arm.c:22282 config/arm/arm.c:22290 config/arm/arm.c:22311
+-#: config/arm/arm.c:22318 config/arm/arm.c:22451 config/arm/arm.c:22458
+-#: config/arm/arm.c:22485 config/arm/arm.c:22492 config/bfin/bfin.c:1436
++#: config/arm/arm.c:22073 config/arm/arm.c:22095 config/arm/arm.c:22105
++#: config/arm/arm.c:22115 config/arm/arm.c:22125 config/arm/arm.c:22164
++#: config/arm/arm.c:22182 config/arm/arm.c:22207 config/arm/arm.c:22222
++#: config/arm/arm.c:22249 config/arm/arm.c:22256 config/arm/arm.c:22274
++#: config/arm/arm.c:22281 config/arm/arm.c:22289 config/arm/arm.c:22310
++#: config/arm/arm.c:22317 config/arm/arm.c:22450 config/arm/arm.c:22457
++#: config/arm/arm.c:22484 config/arm/arm.c:22491 config/bfin/bfin.c:1436
+ #: config/bfin/bfin.c:1443 config/bfin/bfin.c:1450 config/bfin/bfin.c:1457
+ #: config/bfin/bfin.c:1466 config/bfin/bfin.c:1473 config/bfin/bfin.c:1480
+ #: config/bfin/bfin.c:1487
+@@ -3142,22 +3142,22 @@
+ msgid "invalid operand for code '%c'"
+ msgstr ""
+ 
+-#: config/arm/arm.c:22178
++#: config/arm/arm.c:22177
+ #, c-format
+ msgid "instruction never executed"
+ msgstr ""
+ 
+ #. Former Maverick support, removed after GCC-4.7.
+-#: config/arm/arm.c:22199
++#: config/arm/arm.c:22198
+ #, c-format
+ msgid "obsolete Maverick format code '%c'"
+ msgstr ""
+ 
+-#: config/arm/arm.c:23618
++#: config/arm/arm.c:23617
+ msgid "function parameters cannot have __fp16 type"
+ msgstr ""
+ 
+-#: config/arm/arm.c:23628
++#: config/arm/arm.c:23627
+ msgid "functions cannot return __fp16 type"
+ msgstr ""
+ 
+@@ -3199,32 +3199,32 @@
+ msgid "internal compiler error.  Unknown mode:"
+ msgstr ""
+ 
+-#: config/avr/avr.c:3419 config/avr/avr.c:4349 config/avr/avr.c:4798
++#: config/avr/avr.c:3455 config/avr/avr.c:4385 config/avr/avr.c:4834
+ msgid "invalid insn:"
+ msgstr ""
+ 
+-#: config/avr/avr.c:3473 config/avr/avr.c:3578 config/avr/avr.c:3636
+-#: config/avr/avr.c:3682 config/avr/avr.c:3701 config/avr/avr.c:3893
+-#: config/avr/avr.c:4201 config/avr/avr.c:4485 config/avr/avr.c:4691
+-#: config/avr/avr.c:4855 config/avr/avr.c:4949 config/avr/avr.c:5145
++#: config/avr/avr.c:3509 config/avr/avr.c:3614 config/avr/avr.c:3672
++#: config/avr/avr.c:3718 config/avr/avr.c:3737 config/avr/avr.c:3929
++#: config/avr/avr.c:4237 config/avr/avr.c:4521 config/avr/avr.c:4727
++#: config/avr/avr.c:4891 config/avr/avr.c:4985 config/avr/avr.c:5181
+ msgid "incorrect insn:"
+ msgstr ""
+ 
+-#: config/avr/avr.c:3717 config/avr/avr.c:3992 config/avr/avr.c:4272
+-#: config/avr/avr.c:4557 config/avr/avr.c:4737 config/avr/avr.c:5005
+-#: config/avr/avr.c:5203
++#: config/avr/avr.c:3753 config/avr/avr.c:4028 config/avr/avr.c:4308
++#: config/avr/avr.c:4593 config/avr/avr.c:4773 config/avr/avr.c:5041
++#: config/avr/avr.c:5239
+ msgid "unknown move insn:"
+ msgstr ""
+ 
+-#: config/avr/avr.c:5634
++#: config/avr/avr.c:5670
+ msgid "bad shift insn:"
+ msgstr ""
+ 
+-#: config/avr/avr.c:5742 config/avr/avr.c:6223 config/avr/avr.c:6638
++#: config/avr/avr.c:5778 config/avr/avr.c:6259 config/avr/avr.c:6674
+ msgid "internal compiler error.  Incorrect shift:"
+ msgstr ""
+ 
+-#: config/avr/avr.c:7975
++#: config/avr/avr.c:8011
+ msgid "unsupported fixed-point conversion"
+ msgstr ""
+ 
+@@ -3256,7 +3256,7 @@
+ #: config/cris/cris.c:612 config/ft32/ft32.c:104 config/moxie/moxie.c:103
+ #: final.c:3407 final.c:3409 fold-const.c:271 gcc.c:5211 gcc.c:5225
+ #: loop-iv.c:3043 loop-iv.c:3052 rtl-error.c:101 toplev.c:333
+-#: tree-ssa-loop-niter.c:2328 tree-vrp.c:7480 cp/typeck.c:6065 java/expr.c:382
++#: tree-ssa-loop-niter.c:2328 tree-vrp.c:7508 cp/typeck.c:6065 java/expr.c:382
+ #: lto/lto-object.c:184 lto/lto-object.c:281 lto/lto-object.c:338
+ #: lto/lto-object.c:362
+ #, gcc-internal-format, gfc-internal-format
+@@ -3477,63 +3477,63 @@
+ msgid "bad output_condmove_single operand"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16060
++#: config/i386/i386.c:16112
+ #, c-format
+ msgid "invalid UNSPEC as operand"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16764
++#: config/i386/i386.c:16816
+ #, c-format
+ msgid "invalid operand size for operand code 'O'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16799
++#: config/i386/i386.c:16851
+ #, c-format
+ msgid "invalid operand size for operand code 'z'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16869
++#: config/i386/i386.c:16921
+ #, c-format
+ msgid "invalid operand type used with operand code 'Z'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16874
++#: config/i386/i386.c:16926
+ #, c-format
+ msgid "invalid operand size for operand code 'Z'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16950
++#: config/i386/i386.c:17002
+ #, c-format
+ msgid "operand is not a condition code, invalid operand code 'Y'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:17023
++#: config/i386/i386.c:17075
+ #, c-format
+ msgid "operand is not a condition code, invalid operand code 'D'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:17040
++#: config/i386/i386.c:17092
+ #, c-format
+ msgid "operand is not a condition code, invalid operand code '%c'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:17053
++#: config/i386/i386.c:17105
+ #, c-format
+ msgid ""
+ "operand is not an offsettable memory reference, invalid operand code 'H'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:17218
++#: config/i386/i386.c:17270
+ #, c-format
+ msgid "invalid operand code '%c'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:17276
++#: config/i386/i386.c:17328
+ #, c-format
+ msgid "invalid constraints for operand"
+ msgstr ""
+ 
+-#: config/i386/i386.c:27754
++#: config/i386/i386.c:27807
+ msgid "unknown insn mode"
+ msgstr ""
+ 
+@@ -3572,13 +3572,13 @@
+ msgid "invalid operation on %<__fpreg%>"
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.c:3135 config/tilegx/tilegx.c:5308
++#: config/iq2000/iq2000.c:3135 config/tilegx/tilegx.c:5311
+ #: config/tilepro/tilepro.c:4703
+ #, c-format
+ msgid "invalid %%P operand"
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.c:3143 config/rs6000/rs6000.c:20768
++#: config/iq2000/iq2000.c:3143 config/rs6000/rs6000.c:20798
+ #, c-format
+ msgid "invalid %%p value"
+ msgstr ""
+@@ -3641,7 +3641,7 @@
+ msgid "post-increment address is not a register"
+ msgstr ""
+ 
+-#: config/m32r/m32r.c:2328 config/m32r/m32r.c:2343 config/rs6000/rs6000.c:32640
++#: config/m32r/m32r.c:2328 config/m32r/m32r.c:2343 config/rs6000/rs6000.c:32707
+ msgid "bad address"
+ msgstr ""
+ 
+@@ -3766,277 +3766,277 @@
+ msgid "Try running '%s' in the shell to raise its limit.\n"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3959
++#: config/rs6000/rs6000.c:3967
+ msgid "-maltivec=le not allowed for big-endian targets"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3971
++#: config/rs6000/rs6000.c:3979
+ msgid "-mvsx requires hardware floating point"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3979
++#: config/rs6000/rs6000.c:3987
+ msgid "-mvsx and -mpaired are incompatible"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3981
++#: config/rs6000/rs6000.c:3989
+ msgid "-mvsx needs indexed addressing"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3986
++#: config/rs6000/rs6000.c:3994
+ msgid "-mvsx and -mno-altivec are incompatible"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3988
++#: config/rs6000/rs6000.c:3996
+ msgid "-mno-altivec disables vsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4129
++#: config/rs6000/rs6000.c:4137
+ msgid "-mquad-memory requires 64-bit mode"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4132
++#: config/rs6000/rs6000.c:4140
+ msgid "-mquad-memory-atomic requires 64-bit mode"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4144
++#: config/rs6000/rs6000.c:4152
+ msgid "-mquad-memory is not available in little endian mode"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4212
++#: config/rs6000/rs6000.c:4220
+ msgid "-mtoc-fusion requires 64-bit"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4219
++#: config/rs6000/rs6000.c:4227
+ msgid "-mtoc-fusion requires medium/large code model"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:9919
++#: config/rs6000/rs6000.c:9949
+ msgid "bad move"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20411
++#: config/rs6000/rs6000.c:20441
+ msgid "Bad 128-bit move"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20602
++#: config/rs6000/rs6000.c:20632
+ #, c-format
+ msgid "invalid %%e value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20623
++#: config/rs6000/rs6000.c:20653
+ #, c-format
+ msgid "invalid %%f value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20632
++#: config/rs6000/rs6000.c:20662
+ #, c-format
+ msgid "invalid %%F value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20641
++#: config/rs6000/rs6000.c:20671
+ #, c-format
+ msgid "invalid %%G value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20676
++#: config/rs6000/rs6000.c:20706
+ #, c-format
+ msgid "invalid %%j code"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20686
++#: config/rs6000/rs6000.c:20716
+ #, c-format
+ msgid "invalid %%J code"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20696
++#: config/rs6000/rs6000.c:20726
+ #, c-format
+ msgid "invalid %%k value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20711 config/xtensa/xtensa.c:2343
++#: config/rs6000/rs6000.c:20741 config/xtensa/xtensa.c:2343
+ #, c-format
+ msgid "invalid %%K value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20758
++#: config/rs6000/rs6000.c:20788
+ #, c-format
+ msgid "invalid %%O value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20805
++#: config/rs6000/rs6000.c:20835
+ #, c-format
+ msgid "invalid %%q value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20858
++#: config/rs6000/rs6000.c:20888
+ #, c-format
+ msgid "invalid %%T value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20870
++#: config/rs6000/rs6000.c:20900
+ #, c-format
+ msgid "invalid %%u value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20884 config/xtensa/xtensa.c:2313
++#: config/rs6000/rs6000.c:20914 config/xtensa/xtensa.c:2313
+ #, c-format
+ msgid "invalid %%v value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:20951 config/xtensa/xtensa.c:2364
++#: config/rs6000/rs6000.c:20981 config/xtensa/xtensa.c:2364
+ #, c-format
+ msgid "invalid %%x value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:21099
++#: config/rs6000/rs6000.c:21129
+ #, c-format
+ msgid "invalid %%y value, try using the 'Z' constraint"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:21814
++#: config/rs6000/rs6000.c:21844
+ msgid "__float128 and __ibm128 cannot be used in the same expression"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:21820
++#: config/rs6000/rs6000.c:21850
+ msgid "__ibm128 and long double cannot be used in the same expression"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:21826
++#: config/rs6000/rs6000.c:21856
+ msgid "__float128 and long double cannot be used in the same expression"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:35706
++#: config/rs6000/rs6000.c:35773
+ msgid "AltiVec argument passed to unprototyped function"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37429
++#: config/rs6000/rs6000.c:37496
+ msgid "Could not generate addis value for fusion"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37501
++#: config/rs6000/rs6000.c:37568
+ msgid "Unable to generate load/store offset for fusion"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37605
++#: config/rs6000/rs6000.c:37672
+ msgid "Bad GPR fusion"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37823
++#: config/rs6000/rs6000.c:37890
+ msgid "emit_fusion_p9_load, bad reg #1"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37860
++#: config/rs6000/rs6000.c:37936
+ msgid "emit_fusion_p9_load, bad reg #2"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37863
++#: config/rs6000/rs6000.c:37939
+ msgid "emit_fusion_p9_load not MEM"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37901
++#: config/rs6000/rs6000.c:37977
+ msgid "emit_fusion_p9_store, bad reg #1"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37938
++#: config/rs6000/rs6000.c:38023
+ msgid "emit_fusion_p9_store, bad reg #2"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:37941
++#: config/rs6000/rs6000.c:38026
+ msgid "emit_fusion_p9_store not MEM"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7168
++#: config/s390/s390.c:7170
+ #, c-format
+ msgid "symbolic memory references are only supported on z10 or later"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7179
++#: config/s390/s390.c:7181
+ #, c-format
+ msgid "cannot decompose address"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7248
++#: config/s390/s390.c:7250
+ #, c-format
+ msgid "invalid comparison operator for 'E' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7271
++#: config/s390/s390.c:7273
+ #, c-format
+ msgid "invalid reference for 'J' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7289
++#: config/s390/s390.c:7291
+ #, c-format
+ msgid "invalid address for 'O' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7311
++#: config/s390/s390.c:7313
+ #, c-format
+ msgid "invalid address for 'R' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7329
++#: config/s390/s390.c:7331
+ #, c-format
+ msgid "memory reference expected for 'S' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7339
++#: config/s390/s390.c:7341
+ #, c-format
+ msgid "invalid address for 'S' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7360
++#: config/s390/s390.c:7362
+ #, c-format
+ msgid "register or memory expression expected for 'N' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7371
++#: config/s390/s390.c:7373
+ #, c-format
+ msgid "register or memory expression expected for 'M' output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7456 config/s390/s390.c:7477
++#: config/s390/s390.c:7458 config/s390/s390.c:7479
+ #, c-format
+ msgid "invalid constant for output modifier '%c'"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7474
++#: config/s390/s390.c:7476
+ #, c-format
+ msgid "invalid constant - try using an output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7515
++#: config/s390/s390.c:7517
+ #, c-format
+ msgid "invalid constant vector for output modifier '%c'"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7522
++#: config/s390/s390.c:7524
+ #, c-format
+ msgid "invalid expression - try using an output modifier"
+ msgstr ""
+ 
+-#: config/s390/s390.c:7525
++#: config/s390/s390.c:7527
+ #, c-format
+ msgid "invalid expression for output modifier '%c'"
+ msgstr ""
+ 
+-#: config/s390/s390.c:11377
++#: config/s390/s390.c:11379
+ msgid "Vector argument passed to unprototyped function"
+ msgstr ""
+ 
+-#: config/s390/s390.c:15036
++#: config/s390/s390.c:15038
+ msgid "types differ in signess"
+ msgstr ""
+ 
+-#: config/s390/s390.c:15046
++#: config/s390/s390.c:15048
+ msgid "binary operator does not support two vector bool operands"
+ msgstr ""
+ 
+-#: config/s390/s390.c:15049
++#: config/s390/s390.c:15051
+ msgid "binary operator does not support vector bool operand"
+ msgstr ""
+ 
+-#: config/s390/s390.c:15057
++#: config/s390/s390.c:15059
+ msgid ""
+ "binary operator does not support mixing vector bool with floating point "
+ "vector operands"
+@@ -4064,43 +4064,43 @@
+ msgid "created and used with different endianness"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8758 config/sparc/sparc.c:8764
++#: config/sparc/sparc.c:8757 config/sparc/sparc.c:8763
+ #, c-format
+ msgid "invalid %%Y operand"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8834
++#: config/sparc/sparc.c:8833
+ #, c-format
+ msgid "invalid %%A operand"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8844
++#: config/sparc/sparc.c:8843
+ #, c-format
+ msgid "invalid %%B operand"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8873 config/tilegx/tilegx.c:5095
++#: config/sparc/sparc.c:8872 config/tilegx/tilegx.c:5098
+ #: config/tilepro/tilepro.c:4510
+ #, c-format
+ msgid "invalid %%C operand"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8890 config/tilegx/tilegx.c:5128
++#: config/sparc/sparc.c:8889 config/tilegx/tilegx.c:5131
+ #, c-format
+ msgid "invalid %%D operand"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8906
++#: config/sparc/sparc.c:8905
+ #, c-format
+ msgid "invalid %%f operand"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8918
++#: config/sparc/sparc.c:8917
+ #, c-format
+ msgid "invalid %%s operand"
+ msgstr ""
+ 
+-#: config/sparc/sparc.c:8963
++#: config/sparc/sparc.c:8962
+ #, c-format
+ msgid "floating-point constant not a valid immediate operand"
+ msgstr ""
+@@ -4125,57 +4125,57 @@
+ msgid "xstormy16_print_operand: unknown code"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5080 config/tilepro/tilepro.c:4495
++#: config/tilegx/tilegx.c:5083 config/tilepro/tilepro.c:4495
+ #, c-format
+ msgid "invalid %%c operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5111
++#: config/tilegx/tilegx.c:5114
+ #, c-format
+ msgid "invalid %%d operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5208
++#: config/tilegx/tilegx.c:5211
+ #, c-format
+ msgid "invalid %%H specifier"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5250 config/tilepro/tilepro.c:4524
++#: config/tilegx/tilegx.c:5253 config/tilepro/tilepro.c:4524
+ #, c-format
+ msgid "invalid %%h operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5262 config/tilepro/tilepro.c:4588
++#: config/tilegx/tilegx.c:5265 config/tilepro/tilepro.c:4588
+ #, c-format
+ msgid "invalid %%I operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5274 config/tilepro/tilepro.c:4600
++#: config/tilegx/tilegx.c:5277 config/tilepro/tilepro.c:4600
+ #, c-format
+ msgid "invalid %%i operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5295 config/tilepro/tilepro.c:4621
++#: config/tilegx/tilegx.c:5298 config/tilepro/tilepro.c:4621
+ #, c-format
+ msgid "invalid %%j operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5326
++#: config/tilegx/tilegx.c:5329
+ #, c-format
+ msgid "invalid %%%c operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5341 config/tilepro/tilepro.c:4735
++#: config/tilegx/tilegx.c:5344 config/tilepro/tilepro.c:4735
+ #, c-format
+ msgid "invalid %%N operand"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5385
++#: config/tilegx/tilegx.c:5388
+ #, c-format
+ msgid "invalid operand for 'r' specifier"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.c:5409 config/tilepro/tilepro.c:4816
++#: config/tilegx/tilegx.c:5412 config/tilepro/tilepro.c:4816
+ #, c-format
+ msgid "unable to print out operand yet; code == %d (%c)"
+ msgstr ""
+@@ -4303,7 +4303,7 @@
+ #: c/c-parser.c:8938 c/c-parser.c:9119 c/c-parser.c:9899 c/c-parser.c:9969
+ #: c/c-parser.c:10012 c/c-parser.c:14492 c/c-parser.c:14516 c/c-parser.c:14534
+ #: c/c-parser.c:14747 c/c-parser.c:14790 c/c-parser.c:2950 c/c-parser.c:9112
+-#: cp/parser.c:26388 cp/parser.c:26961
++#: cp/parser.c:26403 cp/parser.c:26976
+ #, gcc-internal-format
+ msgid "expected %<;%>"
+ msgstr ""
+@@ -4323,13 +4323,13 @@
+ #: c/c-parser.c:12632 c/c-parser.c:12714 c/c-parser.c:12822 c/c-parser.c:12857
+ #: c/c-parser.c:12905 c/c-parser.c:12963 c/c-parser.c:14694 c/c-parser.c:16640
+ #: c/c-parser.c:16850 c/c-parser.c:17291 c/c-parser.c:17349 c/c-parser.c:17775
+-#: c/c-parser.c:10969 cp/parser.c:24120 cp/parser.c:26964
++#: c/c-parser.c:10969 cp/parser.c:24134 cp/parser.c:26979
+ #, gcc-internal-format
+ msgid "expected %<(%>"
+ msgstr ""
+ 
+ #: c/c-parser.c:2192 c/c-parser.c:7230 c/c-parser.c:7636 c/c-parser.c:7677
+-#: c/c-parser.c:7813 cp/parser.c:26386 cp/parser.c:26979
++#: c/c-parser.c:7813 cp/parser.c:26401 cp/parser.c:26994
+ #, gcc-internal-format
+ msgid "expected %<,%>"
+ msgstr ""
+@@ -4356,7 +4356,7 @@
+ #: c/c-parser.c:12876 c/c-parser.c:12924 c/c-parser.c:12932 c/c-parser.c:12967
+ #: c/c-parser.c:14576 c/c-parser.c:14755 c/c-parser.c:14801 c/c-parser.c:16829
+ #: c/c-parser.c:16906 c/c-parser.c:17327 c/c-parser.c:17411 c/c-parser.c:17784
+-#: cp/parser.c:24152 cp/parser.c:27009
++#: cp/parser.c:24166 cp/parser.c:27024
+ #, gcc-internal-format
+ msgid "expected %<)%>"
+ msgstr ""
+@@ -4363,8 +4363,8 @@
+ 
+ #: c/c-parser.c:3583 c/c-parser.c:4514 c/c-parser.c:4550 c/c-parser.c:6136
+ #: c/c-parser.c:7744 c/c-parser.c:8102 c/c-parser.c:8251 c/c-parser.c:10656
+-#: c/c-parser.c:17687 c/c-parser.c:17689 c/c-parser.c:18028 cp/parser.c:7024
+-#: cp/parser.c:26973
++#: c/c-parser.c:17687 c/c-parser.c:17689 c/c-parser.c:18028 cp/parser.c:7034
++#: cp/parser.c:26988
+ #, gcc-internal-format
+ msgid "expected %<]%>"
+ msgstr ""
+@@ -4373,13 +4373,13 @@
+ msgid "expected %<;%>, %<,%> or %<)%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:4372 c/c-parser.c:14517 cp/parser.c:26967 cp/parser.c:28889
++#: c/c-parser.c:4372 c/c-parser.c:14517 cp/parser.c:26982 cp/parser.c:28904
+ #, gcc-internal-format
+ msgid "expected %<}%>"
+ msgstr ""
+ 
+ #: c/c-parser.c:4684 c/c-parser.c:9453 c/c-parser.c:15237 c/c-parser.c:2768
+-#: c/c-parser.c:2971 c/c-parser.c:9007 cp/parser.c:17162 cp/parser.c:26970
++#: c/c-parser.c:2971 c/c-parser.c:9007 cp/parser.c:17172 cp/parser.c:26985
+ #, gcc-internal-format
+ msgid "expected %<{%>"
+ msgstr ""
+@@ -4388,7 +4388,7 @@
+ #: c/c-parser.c:7278 c/c-parser.c:9218 c/c-parser.c:9601 c/c-parser.c:9662
+ #: c/c-parser.c:10643 c/c-parser.c:11440 c/c-parser.c:11574 c/c-parser.c:11946
+ #: c/c-parser.c:12038 c/c-parser.c:12666 c/c-parser.c:16697 c/c-parser.c:16753
+-#: c/c-parser.c:11063 cp/parser.c:27003 cp/parser.c:28100 cp/parser.c:30758
++#: c/c-parser.c:11063 cp/parser.c:27018 cp/parser.c:28115 cp/parser.c:30773
+ #, gcc-internal-format
+ msgid "expected %<:%>"
+ msgstr ""
+@@ -4409,7 +4409,7 @@
+ msgid "Cilk array notation cannot be used as a condition for while statement"
+ msgstr ""
+ 
+-#: c/c-parser.c:5656 cp/parser.c:26897
++#: c/c-parser.c:5656 cp/parser.c:26912
+ #, gcc-internal-format
+ msgid "expected %<while%>"
+ msgstr ""
+@@ -4427,39 +4427,39 @@
+ msgid "expected %<.%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:8678 c/c-parser.c:8710 c/c-parser.c:8950 cp/parser.c:28674
+-#: cp/parser.c:28748
++#: c/c-parser.c:8678 c/c-parser.c:8710 c/c-parser.c:8950 cp/parser.c:28689
++#: cp/parser.c:28763
+ #, gcc-internal-format
+ msgid "expected %<@end%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:9367 cp/parser.c:26988
++#: c/c-parser.c:9367 cp/parser.c:27003
+ #, gcc-internal-format
+ msgid "expected %<>%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:12116 c/c-parser.c:12880 cp/parser.c:27012
++#: c/c-parser.c:12116 c/c-parser.c:12880 cp/parser.c:27027
+ #, gcc-internal-format
+ msgid "expected %<,%> or %<)%>"
+ msgstr ""
+ 
+ #: c/c-parser.c:14229 c/c-parser.c:14273 c/c-parser.c:14501 c/c-parser.c:14736
+-#: c/c-parser.c:16891 c/c-parser.c:17513 c/c-parser.c:4573 cp/parser.c:26991
++#: c/c-parser.c:16891 c/c-parser.c:17513 c/c-parser.c:4573 cp/parser.c:27006
+ #, gcc-internal-format
+ msgid "expected %<=%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:15280 c/c-parser.c:15270 cp/parser.c:34132
++#: c/c-parser.c:15280 c/c-parser.c:15270 cp/parser.c:34147
+ #, gcc-internal-format
+ msgid "expected %<#pragma omp section%> or %<}%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:17675 c/c-parser.c:10602 cp/parser.c:26976 cp/parser.c:30031
++#: c/c-parser.c:17675 c/c-parser.c:10602 cp/parser.c:26991 cp/parser.c:30046
+ #, gcc-internal-format
+ msgid "expected %<[%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7405
++#: c/c-typeck.c:7415
+ msgid "(anonymous)"
+ msgstr ""
+ 
+@@ -4471,11 +4471,11 @@
+ msgid "candidate 2:"
+ msgstr ""
+ 
+-#: cp/decl2.c:778
++#: cp/decl2.c:779
+ msgid "candidates are: %+#D"
+ msgstr ""
+ 
+-#: cp/decl2.c:780
++#: cp/decl2.c:781
+ msgid "candidate is: %+#D"
+ msgstr ""
+ 
+@@ -4519,43 +4519,43 @@
+ msgid "(static destructors for %s)"
+ msgstr ""
+ 
+-#: cp/error.c:1063
++#: cp/error.c:1062
+ msgid "vtable for "
+ msgstr ""
+ 
+-#: cp/error.c:1087
++#: cp/error.c:1086
+ msgid "<return value> "
+ msgstr ""
+ 
+-#: cp/error.c:1102
++#: cp/error.c:1101
+ msgid "{anonymous}"
+ msgstr ""
+ 
+-#: cp/error.c:1104
++#: cp/error.c:1103
+ msgid "(anonymous namespace)"
+ msgstr ""
+ 
+-#: cp/error.c:1220
++#: cp/error.c:1219
+ msgid "<template arguments error>"
+ msgstr ""
+ 
+-#: cp/error.c:1242
++#: cp/error.c:1241
+ msgid "<enumerator>"
+ msgstr ""
+ 
+-#: cp/error.c:1282
++#: cp/error.c:1281
+ msgid "<declaration error>"
+ msgstr ""
+ 
+-#: cp/error.c:1819 cp/error.c:1839
++#: cp/error.c:1818 cp/error.c:1838
+ msgid "<template parameter error>"
+ msgstr ""
+ 
+-#: cp/error.c:1969
++#: cp/error.c:1968
+ msgid "<statement>"
+ msgstr ""
+ 
+-#: cp/error.c:1996 cp/error.c:3043 c-family/c-pretty-print.c:2182
++#: cp/error.c:1995 cp/error.c:3042 c-family/c-pretty-print.c:2185
+ #, gcc-internal-format
+ msgid "<unknown>"
+ msgstr ""
+@@ -4562,134 +4562,134 @@
+ 
+ #. While waiting for caret diagnostics, avoid printing
+ #. __cxa_allocate_exception, __cxa_throw, and the like.
+-#: cp/error.c:2014
++#: cp/error.c:2013
+ msgid "<throw-expression>"
+ msgstr ""
+ 
+-#: cp/error.c:2115
++#: cp/error.c:2114
+ msgid "<ubsan routine call>"
+ msgstr ""
+ 
+-#: cp/error.c:2572
++#: cp/error.c:2571
+ msgid "<unparsed>"
+ msgstr ""
+ 
+-#: cp/error.c:2723
++#: cp/error.c:2722
+ msgid "<lambda>"
+ msgstr ""
+ 
+-#: cp/error.c:2766
++#: cp/error.c:2765
+ msgid "*this"
+ msgstr ""
+ 
+-#: cp/error.c:2776
++#: cp/error.c:2775
+ msgid "<expression error>"
+ msgstr ""
+ 
+-#: cp/error.c:2791
++#: cp/error.c:2790
+ msgid "<unknown operator>"
+ msgstr ""
+ 
+-#: cp/error.c:3087
++#: cp/error.c:3086
+ msgid "{unknown}"
+ msgstr ""
+ 
+-#: cp/error.c:3199
++#: cp/error.c:3198
+ msgid "At global scope:"
+ msgstr ""
+ 
+-#: cp/error.c:3305
++#: cp/error.c:3304
+ #, c-format
+ msgid "In static member function %qs"
+ msgstr ""
+ 
+-#: cp/error.c:3307
++#: cp/error.c:3306
+ #, c-format
+ msgid "In copy constructor %qs"
+ msgstr ""
+ 
+-#: cp/error.c:3309
++#: cp/error.c:3308
+ #, c-format
+ msgid "In constructor %qs"
+ msgstr ""
+ 
+-#: cp/error.c:3311
++#: cp/error.c:3310
+ #, c-format
+ msgid "In destructor %qs"
+ msgstr ""
+ 
+-#: cp/error.c:3313
++#: cp/error.c:3312
+ msgid "In lambda function"
+ msgstr ""
+ 
+-#: cp/error.c:3333
++#: cp/error.c:3332
+ #, c-format
+ msgid "%s: In substitution of %qS:\n"
+ msgstr ""
+ 
+-#: cp/error.c:3334
++#: cp/error.c:3333
+ msgid "%s: In instantiation of %q#D:\n"
+ msgstr ""
+ 
+-#: cp/error.c:3359
++#: cp/error.c:3358
+ msgid "%r%s:%d:%d:%R   "
+ msgstr ""
+ 
+-#: cp/error.c:3362
++#: cp/error.c:3361
+ msgid "%r%s:%d:%R   "
+ msgstr ""
+ 
+-#: cp/error.c:3370
++#: cp/error.c:3369
+ #, c-format
+ msgid "recursively required by substitution of %qS\n"
+ msgstr ""
+ 
+-#: cp/error.c:3371
++#: cp/error.c:3370
+ #, c-format
+ msgid "required by substitution of %qS\n"
+ msgstr ""
+ 
+-#: cp/error.c:3376
++#: cp/error.c:3375
+ msgid "recursively required from %q#D\n"
+ msgstr ""
+ 
+-#: cp/error.c:3377
++#: cp/error.c:3376
+ msgid "required from %q#D\n"
+ msgstr ""
+ 
+-#: cp/error.c:3384
++#: cp/error.c:3383
+ msgid "recursively required from here\n"
+ msgstr ""
+ 
+-#: cp/error.c:3385
++#: cp/error.c:3384
+ msgid "required from here\n"
+ msgstr ""
+ 
+-#: cp/error.c:3437
++#: cp/error.c:3436
+ msgid ""
+ "%r%s:%d:%d:%R   [ skipping %d instantiation contexts, use -ftemplate-"
+ "backtrace-limit=0 to disable ]\n"
+ msgstr ""
+ 
+-#: cp/error.c:3443
++#: cp/error.c:3442
+ msgid ""
+ "%r%s:%d:%R   [ skipping %d instantiation contexts, use -ftemplate-backtrace-"
+ "limit=0 to disable ]\n"
+ msgstr ""
+ 
+-#: cp/error.c:3497
++#: cp/error.c:3496
+ msgid "%r%s:%d:%d:%R   in constexpr expansion of %qs"
+ msgstr ""
+ 
+-#: cp/error.c:3501
++#: cp/error.c:3500
+ msgid "%r%s:%d:%R   in constexpr expansion of %qs"
+ msgstr ""
+ 
+-#: cp/pt.c:1945 cp/semantics.c:5217
++#: cp/pt.c:1945 cp/semantics.c:5218
+ msgid "candidates are:"
+ msgstr ""
+ 
+-#: cp/pt.c:21086
++#: cp/pt.c:21090
+ msgid "candidate is:"
+ msgid_plural "candidates are:"
+ msgstr[0] ""
+@@ -4812,17 +4812,17 @@
+ msgid "elemental binary operation"
+ msgstr ""
+ 
+-#: fortran/check.c:2124 fortran/check.c:3115 fortran/check.c:3169
++#: fortran/check.c:2131 fortran/check.c:3122 fortran/check.c:3176
+ #, c-format
+ msgid "arguments '%s' and '%s' for intrinsic %s"
+ msgstr ""
+ 
+-#: fortran/check.c:2921
++#: fortran/check.c:2928
+ #, c-format
+ msgid "arguments 'a%d' and 'a%d' for intrinsic '%s'"
+ msgstr ""
+ 
+-#: fortran/check.c:3444 fortran/intrinsic.c:4290
++#: fortran/check.c:3451 fortran/intrinsic.c:4291
+ #, c-format
+ msgid "arguments '%s' and '%s' for intrinsic '%s'"
+ msgstr ""
+@@ -4871,79 +4871,79 @@
+ msgid "Driving:"
+ msgstr ""
+ 
+-#: fortran/interface.c:3048 fortran/intrinsic.c:3994
++#: fortran/interface.c:3060 fortran/intrinsic.c:3995
+ msgid "actual argument to INTENT = OUT/INOUT"
+ msgstr ""
+ 
+-#: fortran/io.c:550
++#: fortran/io.c:537
+ msgid "Positive width required"
+ msgstr ""
+ 
+-#: fortran/io.c:551
++#: fortran/io.c:538
+ msgid "Nonnegative width required"
+ msgstr ""
+ 
+-#: fortran/io.c:552
++#: fortran/io.c:539
+ msgid "Unexpected element %qc in format string at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:554
++#: fortran/io.c:541
+ msgid "Unexpected end of format string"
+ msgstr ""
+ 
+-#: fortran/io.c:555
++#: fortran/io.c:542
+ msgid "Zero width in format descriptor"
+ msgstr ""
+ 
+-#: fortran/io.c:575
++#: fortran/io.c:562
+ msgid "Missing leading left parenthesis"
+ msgstr ""
+ 
+-#: fortran/io.c:604
++#: fortran/io.c:591
+ msgid "Left parenthesis required after %<*%>"
+ msgstr ""
+ 
+-#: fortran/io.c:635
++#: fortran/io.c:622
+ msgid "Expected P edit descriptor"
+ msgstr ""
+ 
+ #. P requires a prior number.
+-#: fortran/io.c:643
++#: fortran/io.c:630
+ msgid "P descriptor requires leading scale factor"
+ msgstr ""
+ 
+-#: fortran/io.c:736 fortran/io.c:750
++#: fortran/io.c:723 fortran/io.c:737
+ msgid "Comma required after P descriptor"
+ msgstr ""
+ 
+-#: fortran/io.c:764
++#: fortran/io.c:751
+ msgid "Positive width required with T descriptor"
+ msgstr ""
+ 
+-#: fortran/io.c:843
++#: fortran/io.c:830
+ msgid "E specifier not allowed with g0 descriptor"
+ msgstr ""
+ 
+-#: fortran/io.c:913
++#: fortran/io.c:900
+ msgid "Positive exponent width required"
+ msgstr ""
+ 
+-#: fortran/io.c:943
++#: fortran/io.c:930
+ msgid "Period required in format specifier"
+ msgstr ""
+ 
+-#: fortran/io.c:1570
++#: fortran/io.c:1557
+ #, c-format
+ msgid "%s tag"
+ msgstr ""
+ 
+-#: fortran/io.c:2966
++#: fortran/io.c:2953
+ msgid "internal unit in WRITE"
+ msgstr ""
+ 
+ #. For INQUIRE, all tags except FILE, ID and UNIT are variable definition
+ #. contexts.  Thus, use an extended RESOLVE_TAG macro for that.
+-#: fortran/io.c:4185
++#: fortran/io.c:4172
+ #, c-format
+ msgid "%s tag with INQUIRE"
+ msgstr ""
+@@ -5025,39 +5025,39 @@
+ msgid "Unexpected end of module"
+ msgstr ""
+ 
+-#: fortran/parse.c:1671
++#: fortran/parse.c:1665
+ msgid "arithmetic IF"
+ msgstr ""
+ 
+-#: fortran/parse.c:1680
++#: fortran/parse.c:1674
+ msgid "attribute declaration"
+ msgstr ""
+ 
+-#: fortran/parse.c:1716
++#: fortran/parse.c:1710
+ msgid "data declaration"
+ msgstr ""
+ 
+-#: fortran/parse.c:1734
++#: fortran/parse.c:1728
+ msgid "derived type declaration"
+ msgstr ""
+ 
+-#: fortran/parse.c:1846
++#: fortran/parse.c:1840
+ msgid "block IF"
+ msgstr ""
+ 
+-#: fortran/parse.c:1855
++#: fortran/parse.c:1849
+ msgid "implied END DO"
+ msgstr ""
+ 
+-#: fortran/parse.c:1949 fortran/resolve.c:10537
++#: fortran/parse.c:1943 fortran/resolve.c:10575
+ msgid "assignment"
+ msgstr ""
+ 
+-#: fortran/parse.c:1952 fortran/resolve.c:10588 fortran/resolve.c:10591
++#: fortran/parse.c:1946 fortran/resolve.c:10626 fortran/resolve.c:10629
+ msgid "pointer assignment"
+ msgstr ""
+ 
+-#: fortran/parse.c:1970
++#: fortran/parse.c:1964
+ msgid "simple IF"
+ msgstr ""
+ 
+@@ -5211,47 +5211,47 @@
+ msgid "Inconsistent ranks for operator at %%L and %%L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6476
++#: fortran/resolve.c:6481
+ msgid "Loop variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6480
++#: fortran/resolve.c:6485
+ msgid "iterator variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6484
++#: fortran/resolve.c:6489
+ msgid "Start expression in DO loop"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6488
++#: fortran/resolve.c:6493
+ msgid "End expression in DO loop"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6492
++#: fortran/resolve.c:6497
+ msgid "Step expression in DO loop"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6749 fortran/resolve.c:6752
++#: fortran/resolve.c:6754 fortran/resolve.c:6757
+ msgid "DEALLOCATE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7119 fortran/resolve.c:7122
++#: fortran/resolve.c:7124 fortran/resolve.c:7127
+ msgid "ALLOCATE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7351 fortran/resolve.c:8798
++#: fortran/resolve.c:7356 fortran/resolve.c:8815
+ msgid "STAT variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7395 fortran/resolve.c:8810
++#: fortran/resolve.c:7400 fortran/resolve.c:8827
+ msgid "ERRMSG variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8640
++#: fortran/resolve.c:8657
+ msgid "item in READ"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8822
++#: fortran/resolve.c:8839
+ msgid "ACQUIRED_LOCK variable"
+ msgstr ""
+ 
+@@ -5264,7 +5264,7 @@
+ msgid "Integer overflow when calculating the amount of memory to allocate"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5503
++#: fortran/trans-decl.c:5513
+ #, c-format
+ msgid ""
+ "Actual string length does not match the declared one for dummy argument "
+@@ -5271,7 +5271,7 @@
+ "'%s' (%ld/%ld)"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5511
++#: fortran/trans-decl.c:5521
+ #, c-format
+ msgid ""
+ "Actual string length is shorter than the declared one for dummy argument "
+@@ -5278,12 +5278,12 @@
+ "'%s' (%ld/%ld)"
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:8170
++#: fortran/trans-expr.c:8196
+ #, c-format
+ msgid "Target of rank remapping is too small (%ld < %ld)"
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:9375
++#: fortran/trans-expr.c:9401
+ msgid "Assignment of scalar to unallocated array"
+ msgstr ""
+ 
+@@ -5292,12 +5292,12 @@
+ msgid "Unequal character lengths (%ld/%ld) in %s"
+ msgstr ""
+ 
+-#: fortran/trans-intrinsic.c:7002
++#: fortran/trans-intrinsic.c:7015
+ #, c-format
+ msgid "Argument NCOPIES of REPEAT intrinsic is negative (its value is %ld)"
+ msgstr ""
+ 
+-#: fortran/trans-intrinsic.c:7034
++#: fortran/trans-intrinsic.c:7047
+ msgid "Argument NCOPIES of REPEAT intrinsic is too large"
+ msgstr ""
+ 
+@@ -5601,35 +5601,39 @@
+ msgid "-E or -x required when input is from standard input"
+ msgstr ""
+ 
+-#: config/darwin.h:252
++#: config/darwin.h:171
++msgid "rdynamic is not supported"
++msgstr ""
++
++#: config/darwin.h:260
+ msgid "-current_version only allowed with -dynamiclib"
+ msgstr ""
+ 
+-#: config/darwin.h:254
++#: config/darwin.h:262
+ msgid "-install_name only allowed with -dynamiclib"
+ msgstr ""
+ 
+-#: config/darwin.h:259
++#: config/darwin.h:267
+ msgid "-bundle not allowed with -dynamiclib"
+ msgstr ""
+ 
+-#: config/darwin.h:260
++#: config/darwin.h:268
+ msgid "-bundle_loader not allowed with -dynamiclib"
+ msgstr ""
+ 
+-#: config/darwin.h:261
++#: config/darwin.h:269
+ msgid "-client_name not allowed with -dynamiclib"
+ msgstr ""
+ 
+-#: config/darwin.h:266
++#: config/darwin.h:274
+ msgid "-force_flat_namespace not allowed with -dynamiclib"
+ msgstr ""
+ 
+-#: config/darwin.h:268
++#: config/darwin.h:276
+ msgid "-keep_private_externs not allowed with -dynamiclib"
+ msgstr ""
+ 
+-#: config/darwin.h:269
++#: config/darwin.h:277
+ msgid "-private_bundle not allowed with -dynamiclib"
+ msgstr ""
+ 
+@@ -5814,2038 +5818,1824 @@
+ "objc++-cpp-output is deprecated; please use objective-c++-cpp-output instead"
+ msgstr ""
+ 
+-#: fortran/lang.opt:146
+-msgid "-J<directory>\tPut MODULE files in 'directory'."
++#: config/alpha/alpha.opt:23 config/i386/i386.opt:430
++msgid "Do not use hardware fp."
+ msgstr ""
+ 
+-#: fortran/lang.opt:198
+-msgid "Warn about possible aliasing of dummy arguments."
++#: config/alpha/alpha.opt:27
++msgid "Use fp registers."
+ msgstr ""
+ 
+-#: fortran/lang.opt:202
+-msgid "Warn about alignment of COMMON blocks."
++#: config/alpha/alpha.opt:31 common.opt:732 common.opt:920 common.opt:924
++#: common.opt:928 common.opt:932 common.opt:1421 common.opt:1570
++#: common.opt:1574 common.opt:1800 common.opt:1946 common.opt:2598
++#: fortran/lang.opt:445
++msgid "Does nothing. Preserved for backward compatibility."
+ msgstr ""
+ 
+-#: fortran/lang.opt:206
+-msgid "Warn about missing ampersand in continued character constants."
++#: config/alpha/alpha.opt:35
++msgid "Request IEEE-conformant math library routines (OSF/1)."
+ msgstr ""
+ 
+-#: fortran/lang.opt:210
+-msgid "Warn about creation of array temporaries."
++#: config/alpha/alpha.opt:39
++msgid "Emit IEEE-conformant code, without inexact exceptions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:214
+-msgid "Warn if the type of a variable might be not interoperable with C."
++#: config/alpha/alpha.opt:46
++msgid "Do not emit complex integer constants to read-only memory."
+ msgstr ""
+ 
+-#: fortran/lang.opt:222
+-msgid "Warn about truncated character expressions."
++#: config/alpha/alpha.opt:50
++msgid "Use VAX fp."
+ msgstr ""
+ 
+-#: fortran/lang.opt:226
+-msgid "Warn about equality comparisons involving REAL or COMPLEX expressions."
++#: config/alpha/alpha.opt:54
++msgid "Do not use VAX fp."
+ msgstr ""
+ 
+-#: fortran/lang.opt:234
+-msgid "Warn about most implicit conversions."
++#: config/alpha/alpha.opt:58
++msgid "Emit code for the byte/word ISA extension."
+ msgstr ""
+ 
+-#: fortran/lang.opt:242
+-msgid "Warn about function call elimination."
++#: config/alpha/alpha.opt:62
++msgid "Emit code for the motion video ISA extension."
+ msgstr ""
+ 
+-#: fortran/lang.opt:246
+-msgid "Warn about calls with implicit interface."
++#: config/alpha/alpha.opt:66
++msgid "Emit code for the fp move and sqrt ISA extension."
+ msgstr ""
+ 
+-#: fortran/lang.opt:250
+-msgid "Warn about called procedures not explicitly declared."
++#: config/alpha/alpha.opt:70
++msgid "Emit code for the counting ISA extension."
+ msgstr ""
+ 
+-#: fortran/lang.opt:254
+-msgid "Warn about constant integer divisions with truncated results."
++#: config/alpha/alpha.opt:74
++msgid "Emit code using explicit relocation directives."
+ msgstr ""
+ 
+-#: fortran/lang.opt:258
+-msgid "Warn about truncated source lines."
++#: config/alpha/alpha.opt:78
++msgid "Emit 16-bit relocations to the small data areas."
+ msgstr ""
+ 
+-#: fortran/lang.opt:262
+-msgid "Warn on intrinsics not part of the selected standard."
++#: config/alpha/alpha.opt:82
++msgid "Emit 32-bit relocations to the small data areas."
+ msgstr ""
+ 
+-#: fortran/lang.opt:274
+-msgid "Warn about USE statements that have no ONLY qualifier."
++#: config/alpha/alpha.opt:86
++msgid "Emit direct branches to local functions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:286
+-msgid "Warn about real-literal-constants with 'q' exponent-letter."
++#: config/alpha/alpha.opt:90
++msgid "Emit indirect branches to local functions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:290
+-msgid "Warn when a left-hand-side array variable is reallocated."
++#: config/alpha/alpha.opt:94
++msgid "Emit rdval instead of rduniq for thread pointer."
+ msgstr ""
+ 
+-#: fortran/lang.opt:294
+-msgid "Warn when a left-hand-side variable is reallocated."
++#: config/alpha/alpha.opt:98 config/s390/s390.opt:126 config/i386/i386.opt:202
++#: config/sparc/long-double-switch.opt:23
++msgid "Use 128-bit long double."
+ msgstr ""
+ 
+-#: fortran/lang.opt:298
+-msgid "Warn if the pointer in a pointer assignment might outlive its target."
++#: config/alpha/alpha.opt:102 config/s390/s390.opt:130 config/i386/i386.opt:198
++#: config/sparc/long-double-switch.opt:27
++msgid "Use 64-bit long double."
+ msgstr ""
+ 
+-#: fortran/lang.opt:306
+-msgid "Warn about \"suspicious\" constructs."
++#: config/alpha/alpha.opt:106
++msgid "Use features of and schedule given CPU."
+ msgstr ""
+ 
+-#: fortran/lang.opt:310
+-msgid "Permit nonconforming uses of the tab character."
++#: config/alpha/alpha.opt:110
++msgid "Schedule given CPU."
+ msgstr ""
+ 
+-#: fortran/lang.opt:314
+-msgid "Warn about underflow of numerical constant expressions."
++#: config/alpha/alpha.opt:114
++msgid "Control the generated fp rounding mode."
+ msgstr ""
+ 
+-#: fortran/lang.opt:322
+-msgid "Warn if a user-procedure has the same name as an intrinsic."
++#: config/alpha/alpha.opt:118
++msgid "Control the IEEE trap mode."
+ msgstr ""
+ 
+-#: fortran/lang.opt:330
+-msgid "Warn about unused dummy arguments."
++#: config/alpha/alpha.opt:122
++msgid "Control the precision given to fp exceptions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:334
+-msgid "Warn about zero-trip DO loops."
++#: config/alpha/alpha.opt:126
++msgid "Tune expected memory latency."
+ msgstr ""
+ 
+-#: fortran/lang.opt:338
+-msgid "Enable preprocessing."
++#: config/alpha/alpha.opt:130 config/ia64/ia64.opt:118
++#: config/rs6000/sysv4.opt:32
++msgid "Specify bit size of immediate TLS offsets."
+ msgstr ""
+ 
+-#: fortran/lang.opt:346
+-msgid "Disable preprocessing."
++#: config/fused-madd.opt:22
++msgid "%<-mfused-madd%> is deprecated; use %<-ffp-contract=%> instead"
+ msgstr ""
+ 
+-#: fortran/lang.opt:354
+-msgid "Eliminate multiple function invokations also for impure functions."
++#: config/mips/mips-tables.opt:24
++msgid "Known MIPS CPUs (for use with the -march= and -mtune= options):"
+ msgstr ""
+ 
+-#: fortran/lang.opt:358
+-msgid "Enable alignment of COMMON blocks."
++#: config/mips/mips-tables.opt:28
++msgid "Known MIPS ISA levels (for use with the -mips option):"
+ msgstr ""
+ 
+-#: fortran/lang.opt:362
+-msgid ""
+-"All intrinsics procedures are available regardless of selected standard."
++#: config/mips/mips.opt:32
++msgid "-mabi=ABI\tGenerate code that conforms to the given ABI."
+ msgstr ""
+ 
+-#: fortran/lang.opt:370
+-msgid ""
+-"Do not treat local variables and COMMON blocks as if they were named in SAVE "
+-"statements."
++#: config/mips/mips.opt:36
++msgid "Known MIPS ABIs (for use with the -mabi= option):"
+ msgstr ""
+ 
+-#: fortran/lang.opt:374
+-msgid "Specify that backslash in string introduces an escape character."
++#: config/mips/mips.opt:55
++msgid "Generate code that can be used in SVR4-style dynamic objects."
+ msgstr ""
+ 
+-#: fortran/lang.opt:378
+-msgid "Produce a backtrace when a runtime error is encountered."
++#: config/mips/mips.opt:59
++msgid "Use PMC-style 'mad' instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:382
+-msgid ""
+-"-fblas-matmul-limit=<n>\tSize of the smallest matrix for which matmul will "
+-"use BLAS."
++#: config/mips/mips.opt:63
++msgid "Use integer madd/msub instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:386
+-msgid ""
+-"Produce a warning at runtime if a array temporary has been created for a "
+-"procedure argument."
++#: config/mips/mips.opt:67
++msgid "-march=ISA\tGenerate code for the given ISA."
+ msgstr ""
+ 
+-#: fortran/lang.opt:390
++#: config/mips/mips.opt:71
+ msgid ""
+-"-fconvert=<big-endian|little-endian|native|swap> The endianness used for "
+-"unformatted files."
++"-mbranch-cost=COST\tSet the cost of branches to roughly COST instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:393
+-#, c-format
+-msgid "Unrecognized option to endianess value: %qs"
++#: config/mips/mips.opt:75
++msgid "Use Branch Likely instructions, overriding the architecture default."
+ msgstr ""
+ 
+-#: fortran/lang.opt:409
+-msgid "Use the Cray Pointer extension."
++#: config/mips/mips.opt:79
++msgid "Switch on/off MIPS16 ASE on alternating functions for compiler testing."
+ msgstr ""
+ 
+-#: fortran/lang.opt:413
+-msgid "Ignore 'D' in column one in fixed form."
++#: config/mips/mips.opt:83
++msgid "Trap on integer divide by zero."
+ msgstr ""
+ 
+-#: fortran/lang.opt:417
+-msgid "Treat lines with 'D' in column one as comments."
++#: config/mips/mips.opt:87
++msgid ""
++"-mcode-readable=SETTING\tSpecify when instructions are allowed to access "
++"code."
+ msgstr ""
+ 
+-#: fortran/lang.opt:421
+-msgid "Enable all DEC language extensions."
++#: config/mips/mips.opt:91
++msgid "Valid arguments to -mcode-readable=:"
+ msgstr ""
+ 
+-#: fortran/lang.opt:425
+-msgid "Enable support for DEC STRUCTURE/RECORD."
++#: config/mips/mips.opt:104
++msgid "Use branch-and-break sequences to check for integer divide by zero."
+ msgstr ""
+ 
+-#: fortran/lang.opt:429
+-msgid "Set the default double precision kind to an 8 byte wide type."
++#: config/mips/mips.opt:108
++msgid "Use trap instructions to check for integer divide by zero."
+ msgstr ""
+ 
+-#: fortran/lang.opt:433
+-msgid "Set the default integer kind to an 8 byte wide type."
++#: config/mips/mips.opt:112
++msgid "Allow the use of MDMX instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:437
+-msgid "Set the default real kind to an 8 byte wide type."
++#: config/mips/mips.opt:116
++msgid ""
++"Allow hardware floating-point instructions to cover both 32-bit and 64-bit "
++"operations."
+ msgstr ""
+ 
+-#: fortran/lang.opt:441
+-msgid "Allow dollar signs in entity names."
++#: config/mips/mips.opt:120
++msgid "Use MIPS-DSP instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:445 config/alpha/alpha.opt:31 common.opt:732 common.opt:920
+-#: common.opt:924 common.opt:928 common.opt:932 common.opt:1421 common.opt:1570
+-#: common.opt:1574 common.opt:1800 common.opt:1946 common.opt:2598
+-msgid "Does nothing. Preserved for backward compatibility."
++#: config/mips/mips.opt:124
++msgid "Use MIPS-DSP REV 2 instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:449
+-msgid "Display the code tree after parsing."
++#: config/mips/mips.opt:134 config/c6x/c6x.opt:30 config/nios2/nios2.opt:94
++#: config/tilegx/tilegx.opt:45 config/mep/mep.opt:82
++msgid "Use big-endian byte order."
+ msgstr ""
+ 
+-#: fortran/lang.opt:453
+-msgid "Display the code tree after front end optimization."
++#: config/mips/mips.opt:138 config/c6x/c6x.opt:34 config/nios2/nios2.opt:98
++#: config/tilegx/tilegx.opt:49 config/mep/mep.opt:86
++msgid "Use little-endian byte order."
+ msgstr ""
+ 
+-#: fortran/lang.opt:457
+-msgid "Display the code tree after parsing; deprecated option."
++#: config/mips/mips.opt:142 config/iq2000/iq2000.opt:61
++msgid "Use ROM instead of RAM."
+ msgstr ""
+ 
+-#: fortran/lang.opt:461
+-msgid ""
+-"Specify that an external BLAS library should be used for matmul calls on "
+-"large-size arrays."
++#: config/mips/mips.opt:146
++msgid "Use Enhanced Virtual Addressing instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:465
+-msgid "Use f2c calling convention."
++#: config/mips/mips.opt:150
++msgid "Use NewABI-style %reloc() assembly operators."
+ msgstr ""
+ 
+-#: fortran/lang.opt:469
+-msgid "Assume that the source file is fixed form."
++#: config/mips/mips.opt:154
++msgid "Use -G for data that is not defined by the current object."
+ msgstr ""
+ 
+-#: fortran/lang.opt:473
+-msgid "Interpret any INTEGER(4) as an INTEGER(8)."
++#: config/mips/mips.opt:158
++msgid "Work around certain 24K errata."
+ msgstr ""
+ 
+-#: fortran/lang.opt:477 fortran/lang.opt:481
+-msgid "Specify where to find the compiled intrinsic modules."
++#: config/mips/mips.opt:162
++msgid "Work around certain R4000 errata."
+ msgstr ""
+ 
+-#: fortran/lang.opt:485
+-msgid "Allow arbitrary character line width in fixed mode."
++#: config/mips/mips.opt:166
++msgid "Work around certain R4400 errata."
+ msgstr ""
+ 
+-#: fortran/lang.opt:489
+-msgid "-ffixed-line-length-<n>\tUse n as character line width in fixed mode."
++#: config/mips/mips.opt:170
++msgid "Work around certain RM7000 errata."
+ msgstr ""
+ 
+-#: fortran/lang.opt:493
+-msgid "-ffpe-trap=[...]\tStop on following floating point exceptions."
++#: config/mips/mips.opt:174
++msgid "Work around certain R10000 errata."
+ msgstr ""
+ 
+-#: fortran/lang.opt:497
+-msgid "-ffpe-summary=[...]\tPrint summary of floating point exceptions."
++#: config/mips/mips.opt:178
++msgid "Work around errata for early SB-1 revision 2 cores."
+ msgstr ""
+ 
+-#: fortran/lang.opt:501
+-msgid "Assume that the source file is free form."
++#: config/mips/mips.opt:182
++msgid "Work around certain VR4120 errata."
+ msgstr ""
+ 
+-#: fortran/lang.opt:505
+-msgid "Allow arbitrary character line width in free mode."
++#: config/mips/mips.opt:186
++msgid "Work around VR4130 mflo/mfhi errata."
+ msgstr ""
+ 
+-#: fortran/lang.opt:509
+-msgid "-ffree-line-length-<n>\tUse n as character line width in free mode."
++#: config/mips/mips.opt:190
++msgid "Work around an early 4300 hardware bug."
+ msgstr ""
+ 
+-#: fortran/lang.opt:513
+-msgid "Enable front end optimization."
++#: config/mips/mips.opt:194
++msgid "FP exceptions are enabled."
+ msgstr ""
+ 
+-#: fortran/lang.opt:517
+-msgid ""
+-"Specify that no implicit typing is allowed, unless overridden by explicit "
+-"IMPLICIT statements."
++#: config/mips/mips.opt:198
++msgid "Use 32-bit floating-point registers."
+ msgstr ""
+ 
+-#: fortran/lang.opt:521
+-msgid ""
+-"-finit-character=<n>\tInitialize local character variables to ASCII value n."
++#: config/mips/mips.opt:202
++msgid "Conform to the o32 FPXX ABI."
+ msgstr ""
+ 
+-#: fortran/lang.opt:525
+-msgid "-finit-integer=<n>\tInitialize local integer variables to n."
++#: config/mips/mips.opt:206
++msgid "Use 64-bit floating-point registers."
+ msgstr ""
+ 
+-#: fortran/lang.opt:529
+-msgid "Initialize local variables to zero (from g77)."
++#: config/mips/mips.opt:210
++msgid ""
++"-mflush-func=FUNC\tUse FUNC to flush the cache before calling stack "
++"trampolines."
+ msgstr ""
+ 
+-#: fortran/lang.opt:533
+-msgid "-finit-logical=<true|false>\tInitialize local logical variables."
++#: config/mips/mips.opt:214
++msgid "-mabs=MODE\tSelect the IEEE 754 ABS/NEG instruction execution mode."
+ msgstr ""
+ 
+-#: fortran/lang.opt:537
+-msgid "-finit-real=<zero|snan|nan|inf|-inf>\tInitialize local real variables."
++#: config/mips/mips.opt:218
++msgid "-mnan=ENCODING\tSelect the IEEE 754 NaN data encoding."
+ msgstr ""
+ 
+-#: fortran/lang.opt:540
+-#, c-format
+-msgid "Unrecognized option to floating-point init value: %qs"
+-msgstr ""
+-
+-#: fortran/lang.opt:559
++#: config/mips/mips.opt:222
+ msgid ""
+-"-finline-matmul-limit=<n>\tSpecify the size of the largest matrix for which "
+-"matmul will be inlined."
++"Known MIPS IEEE 754 settings (for use with the -mabs= and -mnan= options):"
+ msgstr ""
+ 
+-#: fortran/lang.opt:563
+-msgid ""
+-"-fmax-array-constructor=<n>\tMaximum number of objects in an array "
+-"constructor."
++#: config/mips/mips.opt:232
++msgid "Use 32-bit general registers."
+ msgstr ""
+ 
+-#: fortran/lang.opt:567
+-msgid "-fmax-identifier-length=<n>\tMaximum identifier length."
++#: config/mips/mips.opt:236
++msgid "Use 64-bit general registers."
+ msgstr ""
+ 
+-#: fortran/lang.opt:571
+-msgid "-fmax-subrecord-length=<n>\tMaximum length for subrecords."
++#: config/mips/mips.opt:240
++msgid "Use GP-relative addressing to access small data."
+ msgstr ""
+ 
+-#: fortran/lang.opt:575
++#: config/mips/mips.opt:244
+ msgid ""
+-"-fmax-stack-var-size=<n>\tSize in bytes of the largest array that will be "
+-"put on the stack."
++"When generating -mabicalls code, allow executables to use PLTs and copy "
++"relocations."
+ msgstr ""
+ 
+-#: fortran/lang.opt:579
+-msgid "Put all local arrays on stack."
++#: config/mips/mips.opt:248
++msgid "Allow the use of hardware floating-point ABI and instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:583
+-msgid "Set default accessibility of module entities to PRIVATE."
++#: config/mips/mips.opt:252
++msgid "Generate code that is link-compatible with MIPS16 and microMIPS code."
+ msgstr ""
+ 
+-#: fortran/lang.opt:603
+-msgid "Try to lay out derived types as compactly as possible."
++#: config/mips/mips.opt:256
++msgid "An alias for minterlink-compressed provided for backward-compatibility."
+ msgstr ""
+ 
+-#: fortran/lang.opt:611
+-msgid "Protect parentheses in expressions."
++#: config/mips/mips.opt:260
++msgid "-mipsN\tGenerate code for ISA level N."
+ msgstr ""
+ 
+-#: fortran/lang.opt:615
+-msgid "Enable range checking during compilation."
++#: config/mips/mips.opt:264
++msgid "Generate MIPS16 code."
+ msgstr ""
+ 
+-#: fortran/lang.opt:619
+-msgid "Interpret any REAL(4) as a REAL(8)."
++#: config/mips/mips.opt:268
++msgid "Use MIPS-3D instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:623
+-msgid "Interpret any REAL(4) as a REAL(10)."
++#: config/mips/mips.opt:272
++msgid "Use ll, sc and sync instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:627
+-msgid "Interpret any REAL(4) as a REAL(16)."
++#: config/mips/mips.opt:276
++msgid "Use -G for object-local data."
+ msgstr ""
+ 
+-#: fortran/lang.opt:631
+-msgid "Interpret any REAL(8) as a REAL(4)."
++#: config/mips/mips.opt:280
++msgid "Use indirect calls."
+ msgstr ""
+ 
+-#: fortran/lang.opt:635
+-msgid "Interpret any REAL(8) as a REAL(10)."
++#: config/mips/mips.opt:284
++msgid "Use a 32-bit long type."
+ msgstr ""
+ 
+-#: fortran/lang.opt:639
+-msgid "Interpret any REAL(8) as a REAL(16)."
++#: config/mips/mips.opt:288
++msgid "Use a 64-bit long type."
+ msgstr ""
+ 
+-#: fortran/lang.opt:643
+-msgid "Reallocate the LHS in assignments."
++#: config/mips/mips.opt:292
++msgid "Pass the address of the ra save location to _mcount in $12."
+ msgstr ""
+ 
+-#: fortran/lang.opt:647
+-msgid "Use a 4-byte record marker for unformatted files."
++#: config/mips/mips.opt:296
++msgid "Don't optimize block moves."
+ msgstr ""
+ 
+-#: fortran/lang.opt:651
+-msgid "Use an 8-byte record marker for unformatted files."
++#: config/mips/mips.opt:300
++msgid "Use microMIPS instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:655
+-msgid "Allocate local variables on the stack to allow indirect recursion."
++#: config/mips/mips.opt:304
++msgid "Allow the use of MT instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:659
+-msgid "Copy array sections into a contiguous block on procedure entry."
++#: config/mips/mips.opt:308
++msgid "Prevent the use of all floating-point operations."
+ msgstr ""
+ 
+-#: fortran/lang.opt:663
+-msgid ""
+-"-fcoarray=<none|single|lib>\tSpecify which coarray parallelization should be "
+-"used."
++#: config/mips/mips.opt:312
++msgid "Use MCU instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:666
+-#, c-format
+-msgid "Unrecognized option: %qs"
++#: config/mips/mips.opt:316
++msgid "Do not use a cache-flushing function before calling stack trampolines."
+ msgstr ""
+ 
+-#: fortran/lang.opt:679
+-msgid "-fcheck=[...]\tSpecify which runtime checks are to be performed."
++#: config/mips/mips.opt:320
++msgid "Do not use MDMX instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:683
+-msgid "Append a second underscore if the name already contains an underscore."
++#: config/mips/mips.opt:324
++msgid "Generate normal-mode code."
+ msgstr ""
+ 
+-#: fortran/lang.opt:691
+-msgid "Apply negative sign to zero values."
++#: config/mips/mips.opt:328
++msgid "Do not use MIPS-3D instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:695
+-msgid "Append underscores to externally visible names."
++#: config/mips/mips.opt:332
++msgid "Use paired-single floating-point instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:699 c-family/c.opt:1155 c-family/c.opt:1179
+-#: c-family/c.opt:1409 config/pa/pa.opt:42 config/pa/pa.opt:66
+-#: config/sh/sh.opt:213 common.opt:1074 common.opt:1301 common.opt:1653
+-#: common.opt:1999 common.opt:2035 common.opt:2124 common.opt:2128
+-#: common.opt:2224 common.opt:2306 common.opt:2314 common.opt:2322
+-#: common.opt:2330 common.opt:2431 common.opt:2558
+-msgid "Does nothing.  Preserved for backward compatibility."
++#: config/mips/mips.opt:336
++msgid ""
++"-mr10k-cache-barrier=SETTING\tSpecify when r10k cache barriers should be "
++"inserted."
+ msgstr ""
+ 
+-#: fortran/lang.opt:739
+-msgid "Statically link the GNU Fortran helper library (libgfortran)."
++#: config/mips/mips.opt:340
++msgid "Valid arguments to -mr10k-cache-barrier=:"
+ msgstr ""
+ 
+-#: fortran/lang.opt:743
+-msgid "Conform to the ISO Fortran 2003 standard."
++#: config/mips/mips.opt:353
++msgid "Try to allow the linker to turn PIC calls into direct calls."
+ msgstr ""
+ 
+-#: fortran/lang.opt:747
+-msgid "Conform to the ISO Fortran 2008 standard."
++#: config/mips/mips.opt:357
++msgid ""
++"When generating -mabicalls code, make the code suitable for use in shared "
++"libraries."
+ msgstr ""
+ 
+-#: fortran/lang.opt:751
+-msgid "Conform to the ISO Fortran 2008 standard including TS 29113."
++#: config/mips/mips.opt:361
++msgid ""
++"Restrict the use of hardware floating-point instructions to 32-bit "
++"operations."
+ msgstr ""
+ 
+-#: fortran/lang.opt:755
+-msgid "Conform to the ISO Fortran 95 standard."
++#: config/mips/mips.opt:365
++msgid "Use SmartMIPS instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:759
+-msgid "Conform to nothing in particular."
++#: config/mips/mips.opt:369
++msgid "Prevent the use of all hardware floating-point instructions."
+ msgstr ""
+ 
+-#: fortran/lang.opt:763
+-msgid "Accept extensions to support legacy code."
++#: config/mips/mips.opt:373
++msgid "Optimize lui/addiu address loads."
+ msgstr ""
+ 
+-#: c-family/c.opt:43 c-family/c.opt:46 c-family/c.opt:181
+-#, c-format
+-msgid "assertion missing after %qs"
++#: config/mips/mips.opt:377
++msgid "Assume all symbols have 32-bit values."
+ msgstr ""
+ 
+-#: c-family/c.opt:55 c-family/c.opt:58 c-family/c.opt:163 c-family/c.opt:166
+-#: c-family/c.opt:193 c-family/c.opt:252
+-#, c-format
+-msgid "macro name missing after %qs"
++#: config/mips/mips.opt:381
++msgid "Use synci instruction to invalidate i-cache."
+ msgstr ""
+ 
+-#: c-family/c.opt:70 c-family/c.opt:73 c-family/c.opt:76 c-family/c.opt:79
+-#: c-family/c.opt:175 c-family/c.opt:178 c-family/c.opt:216 c-family/c.opt:220
+-#: c-family/c.opt:232 c-family/c.opt:1601 c-family/c.opt:1609
+-#: config/darwin.opt:53 common.opt:336 common.opt:339 common.opt:2813
+-#, c-format
+-msgid "missing filename after %qs"
++#: config/mips/mips.opt:385 config/s390/s390.opt:201 config/ft32/ft32.opt:27
++msgid "Use LRA instead of reload."
+ msgstr ""
+ 
+-#: c-family/c.opt:85 c-family/c.opt:88 c-family/c.opt:91 c-family/c.opt:94
+-#: c-family/c.opt:200 c-family/c.opt:208 c-family/c.opt:1597
+-#: c-family/c.opt:1617 c-family/c.opt:1621 c-family/c.opt:1625
+-#, c-format
+-msgid "missing path after %qs"
++#: config/mips/mips.opt:389
++msgid "-mtune=PROCESSOR\tOptimize the output for PROCESSOR."
+ msgstr ""
+ 
+-#: c-family/c.opt:182
+-msgid ""
+-"-A<question>=<answer>\tAssert the <answer> to <question>.  Putting '-' "
+-"before <question> disables the <answer> to <question>."
++#: config/mips/mips.opt:393 config/iq2000/iq2000.opt:74
++msgid "Put uninitialized constants in ROM (needs -membedded-data)."
+ msgstr ""
+ 
+-#: c-family/c.opt:186
+-msgid "Do not discard comments."
++#: config/mips/mips.opt:397
++msgid "Use Virtualization Application Specific instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:190
+-msgid "Do not discard comments in macro expansions."
++#: config/mips/mips.opt:401
++msgid "Use eXtended Physical Address (XPA) instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:194
+-msgid ""
+-"-D<macro>[=<val>]\tDefine a <macro> with <val> as its value.  If just "
+-"<macro> is given, <val> is taken to be 1."
++#: config/mips/mips.opt:405
++msgid "Perform VR4130-specific alignment optimizations."
+ msgstr ""
+ 
+-#: c-family/c.opt:201
+-msgid "-F <dir>\tAdd <dir> to the end of the main framework include path."
++#: config/mips/mips.opt:409
++msgid "Lift restrictions on GOT size."
+ msgstr ""
+ 
+-#: c-family/c.opt:205
+-msgid "Print the name of header files as they are used."
++#: config/mips/mips.opt:413
++msgid "Enable use of odd-numbered single-precision registers."
+ msgstr ""
+ 
+-#: c-family/c.opt:209
+-msgid "-I <dir>\tAdd <dir> to the end of the main include path."
++#: config/mips/mips.opt:417
++msgid "Optimize frame header."
+ msgstr ""
+ 
+-#: c-family/c.opt:213
+-msgid "Generate make dependencies."
++#: config/mips/mips.opt:424
++msgid "Enable load/store bonding."
+ msgstr ""
+ 
+-#: c-family/c.opt:217
+-msgid "Generate make dependencies and compile."
++#: config/mips/mips.opt:428
++msgid "Specify the compact branch usage policy."
+ msgstr ""
+ 
+-#: c-family/c.opt:221
+-msgid "-MF <file>\tWrite dependency output to the given file."
++#: config/mips/mips.opt:432
++msgid "Policies available for use with -mcompact-branches=:"
+ msgstr ""
+ 
+-#: c-family/c.opt:225
+-msgid "Treat missing header files as generated files."
++#: config/visium/visium.opt:25
++msgid "Link with libc.a and libdebug.a."
+ msgstr ""
+ 
+-#: c-family/c.opt:229
+-msgid "Like -M but ignore system header files."
++#: config/visium/visium.opt:29
++msgid "Link with libc.a and libsim.a."
+ msgstr ""
+ 
+-#: c-family/c.opt:233
+-msgid "Like -MD but ignore system header files."
++#: config/visium/visium.opt:33
++msgid "Use hardware FP (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:237
+-msgid "Generate phony targets for all headers."
++#: config/visium/visium.opt:37 config/sparc/sparc.opt:30
++#: config/sparc/sparc.opt:34
++msgid "Use hardware FP."
+ msgstr ""
+ 
+-#: c-family/c.opt:240 c-family/c.opt:244
+-#, c-format
+-msgid "missing makefile target after %qs"
++#: config/visium/visium.opt:41 config/sparc/sparc.opt:38
++msgid "Do not use hardware FP."
+ msgstr ""
+ 
+-#: c-family/c.opt:241
+-msgid "-MQ <target>\tAdd a MAKE-quoted target."
++#: config/visium/visium.opt:45 config/sparc/sparc.opt:126
++msgid "Use features of and schedule code for given CPU."
+ msgstr ""
+ 
+-#: c-family/c.opt:245
+-msgid "-MT <target>\tAdd an unquoted target."
++#: config/visium/visium.opt:49 config/spu/spu.opt:84 config/s390/s390.opt:170
++#: config/i386/i386.opt:504 config/sparc/sparc.opt:130 config/ia64/ia64.opt:122
++msgid "Schedule code for given CPU."
+ msgstr ""
+ 
+-#: c-family/c.opt:249
+-msgid "Do not generate #line directives."
++#: config/visium/visium.opt:65
++msgid "Generate code for the supervisor mode (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:253
+-msgid "-U<macro>\tUndefine <macro>."
++#: config/visium/visium.opt:69
++msgid "Generate code for the user mode."
+ msgstr ""
+ 
+-#: c-family/c.opt:257
+-msgid ""
+-"Warn about things that will change when compiling with an ABI-compliant "
+-"compiler."
++#: config/visium/visium.opt:73
++msgid "Only retained for backward compatibility."
+ msgstr ""
+ 
+-#: c-family/c.opt:261
+-msgid ""
+-"Warn about things that change between the current -fabi-version and the "
+-"specified version."
++#: config/epiphany/epiphany.opt:24
++msgid "Don't use any of r32..r63."
+ msgstr ""
+ 
+-#: c-family/c.opt:265
++#: config/epiphany/epiphany.opt:28
+ msgid ""
+-"Warn if a subobject has an abi_tag attribute that the complete object type "
+-"does not have."
++"preferentially allocate registers that allow short instruction generation."
+ msgstr ""
+ 
+-#: c-family/c.opt:272
+-msgid "Warn about suspicious uses of memory addresses."
++#: config/epiphany/epiphany.opt:32
++msgid "Set branch cost."
+ msgstr ""
+ 
+-#: c-family/c.opt:276 ada/gcc-interface/lang.opt:57
+-msgid "Enable most warning messages."
++#: config/epiphany/epiphany.opt:36
++msgid "enable conditional move instruction usage."
+ msgstr ""
+ 
+-#: c-family/c.opt:288
+-msgid ""
+-"Warn whenever an Objective-C assignment is being intercepted by the garbage "
+-"collector."
++#: config/epiphany/epiphany.opt:40
++msgid "set number of nops to emit before each insn pattern."
+ msgstr ""
+ 
+-#: c-family/c.opt:292
+-msgid "Warn about casting functions to incompatible types."
++#: config/epiphany/epiphany.opt:52
++msgid "Use software floating point comparisons."
+ msgstr ""
+ 
+-#: c-family/c.opt:296
+-msgid ""
+-"Warn about boolean expression compared with an integer value different from "
+-"true/false."
++#: config/epiphany/epiphany.opt:56
++msgid "Enable split of 32 bit immediate loads into low / high part."
+ msgstr ""
+ 
+-#: c-family/c.opt:300
+-msgid ""
+-"Warn when __builtin_frame_address or __builtin_return_address is used "
+-"unsafely."
++#: config/epiphany/epiphany.opt:60
++msgid "Enable use of POST_INC / POST_DEC."
+ msgstr ""
+ 
+-#: c-family/c.opt:304
+-msgid "Warn when a built-in preprocessor macro is undefined or redefined."
++#: config/epiphany/epiphany.opt:64
++msgid "Enable use of POST_MODIFY."
+ msgstr ""
+ 
+-#: c-family/c.opt:308
+-msgid "Warn about features not present in ISO C90, but present in ISO C99."
++#: config/epiphany/epiphany.opt:68
++msgid "Set number of bytes on the stack preallocated for use by the callee."
+ msgstr ""
+ 
+-#: c-family/c.opt:312
+-msgid "Warn about features not present in ISO C99, but present in ISO C11."
++#: config/epiphany/epiphany.opt:72
++msgid "Assume round to nearest is selected for purposes of scheduling."
+ msgstr ""
+ 
+-#: c-family/c.opt:316
+-msgid "Warn about C constructs that are not in the common subset of C and C++."
++#: config/epiphany/epiphany.opt:76
++msgid "Generate call insns as indirect calls."
+ msgstr ""
+ 
+-#: c-family/c.opt:323
+-msgid ""
+-"Warn about C++ constructs whose meaning differs between ISO C++ 1998 and ISO "
+-"C++ 2011."
++#: config/epiphany/epiphany.opt:80
++msgid "Generate call insns as direct calls."
+ msgstr ""
+ 
+-#: c-family/c.opt:327
++#: config/epiphany/epiphany.opt:84
+ msgid ""
+-"Warn about C++ constructs whose meaning differs between ISO C++ 2011 and ISO "
+-"C++ 2014."
++"Assume labels and symbols can be addressed using 16 bit absolute addresses."
+ msgstr ""
+ 
+-#: c-family/c.opt:331
+-msgid "Warn about casts which discard qualifiers."
++#: config/epiphany/epiphany.opt:108
++msgid ""
++"A floatig point to integer truncation may be replaced with rounding to save "
++"mode switching."
+ msgstr ""
+ 
+-#: c-family/c.opt:335
+-msgid "Warn about subscripts whose type is \"char\"."
++#: config/epiphany/epiphany.opt:112
++msgid "Vectorize for double-word operations."
+ msgstr ""
+ 
+-#: c-family/c.opt:339
+-msgid "Warn about memory access errors found by Pointer Bounds Checker."
++#: config/epiphany/epiphany.opt:128
++msgid ""
++"Split unaligned 8 byte vector moves before post-modify address generation."
+ msgstr ""
+ 
+-#: c-family/c.opt:343
+-msgid "Warn about variables that might be changed by \"longjmp\" or \"vfork\"."
++#: config/epiphany/epiphany.opt:132
++msgid "Use the floating point unit for integer add/subtract."
+ msgstr ""
+ 
+-#: c-family/c.opt:347
+-msgid ""
+-"Warn about possibly nested block comments, and C++ comments spanning more "
+-"than one physical line."
++#: config/epiphany/epiphany.opt:136
++msgid "Set register to hold -1."
+ msgstr ""
+ 
+-#: c-family/c.opt:351
+-msgid "Synonym for -Wcomment."
++#: config/mn10300/mn10300.opt:30
++msgid "Target the AM33 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:355
+-msgid "Warn for conditionally-supported constructs."
++#: config/mn10300/mn10300.opt:34
++msgid "Target the AM33/2.0 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:359
+-msgid "Warn for implicit type conversions that may change a value."
++#: config/mn10300/mn10300.opt:38
++msgid "Target the AM34 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:363
+-msgid "Warn for converting NULL from/to a non-pointer type."
++#: config/mn10300/mn10300.opt:42 config/arm/arm.opt:227
++msgid "Tune code for the given processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:371
+-msgid "Warn when all constructors and destructors are private."
++#: config/mn10300/mn10300.opt:46
++msgid "Work around hardware multiply bug."
+ msgstr ""
+ 
+-#: c-family/c.opt:375
+-msgid "Warn about __TIME__, __DATE__ and __TIMESTAMP__ usage."
++#: config/mn10300/mn10300.opt:55
++msgid "Enable linker relaxations."
+ msgstr ""
+ 
+-#: c-family/c.opt:379
+-msgid "Warn when a declaration is found after a statement."
++#: config/mn10300/mn10300.opt:59
++msgid "Return pointers in both a0 and d0."
+ msgstr ""
+ 
+-#: c-family/c.opt:383
+-msgid "Warn when deleting a pointer to incomplete type."
++#: config/mn10300/mn10300.opt:63
++msgid "Allow gcc to generate LIW instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:387
+-msgid "Warn about deleting polymorphic objects with non-virtual destructors."
++#: config/mn10300/mn10300.opt:67
++msgid "Allow gcc to generate the SETLB and Lcc instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:391
+-msgid "Warn if a deprecated compiler feature, class, method, or field is used."
++#: config/microblaze/microblaze.opt:40
++msgid "Use software emulation for floating point (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:395
+-msgid ""
+-"Warn about positional initialization of structs requiring designated "
+-"initializers."
++#: config/microblaze/microblaze.opt:44
++msgid "Use hardware floating point instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:399
+-msgid "Warn if qualifiers on arrays which are pointer targets are discarded."
++#: config/microblaze/microblaze.opt:48
++msgid "Use table lookup optimization for small signed integer divisions."
+ msgstr ""
+ 
+-#: c-family/c.opt:403
+-msgid "Warn if type qualifiers on pointers are discarded."
++#: config/microblaze/microblaze.opt:52
++msgid "-mcpu=PROCESSOR\t\tUse features of and schedule code for given CPU."
+ msgstr ""
+ 
+-#: c-family/c.opt:407
+-msgid "Warn about compile-time integer division by zero."
++#: config/microblaze/microblaze.opt:56
++msgid "Don't optimize block moves, use memcpy."
+ msgstr ""
+ 
+-#: c-family/c.opt:411
+-msgid "Warn about duplicated conditions in an if-else-if chain."
++#: config/microblaze/microblaze.opt:60 config/arm/arm.opt:94
++#: config/aarch64/aarch64.opt:65
++msgid "Assume target CPU is configured as big endian."
+ msgstr ""
+ 
+-#: c-family/c.opt:415
+-msgid "Warn about violations of Effective C++ style rules."
++#: config/microblaze/microblaze.opt:64 config/arm/arm.opt:155
++#: config/aarch64/aarch64.opt:81
++msgid "Assume target CPU is configured as little endian."
+ msgstr ""
+ 
+-#: c-family/c.opt:419
+-msgid "Warn about an empty body in an if or else statement."
++#: config/microblaze/microblaze.opt:68
++msgid "Use the soft multiply emulation (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:423
+-msgid "Warn about stray tokens after #elif and #endif."
++#: config/microblaze/microblaze.opt:72
++msgid "Use reorder instructions (swap and byte reversed load/store) (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:427
+-msgid "Warn about comparison of different enum types."
++#: config/microblaze/microblaze.opt:76
++msgid "Use the software emulation for divides (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:435
+-msgid ""
+-"This switch is deprecated; use -Werror=implicit-function-declaration instead."
++#: config/microblaze/microblaze.opt:80
++msgid "Use the hardware barrel shifter instead of emulation."
+ msgstr ""
+ 
+-#: c-family/c.opt:439
+-msgid ""
+-"Warn for implicit type conversions that cause loss of floating point "
+-"precision."
++#: config/microblaze/microblaze.opt:84
++msgid "Use pattern compare instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:443
+-msgid "Warn if testing floating point numbers for equality."
++#: config/microblaze/microblaze.opt:87
++#, c-format
++msgid "%qs is deprecated; use -fstack-check"
+ msgstr ""
+ 
+-#: c-family/c.opt:447 c-family/c.opt:479
+-msgid "Warn about printf/scanf/strftime/strfmon format string anomalies."
++#: config/microblaze/microblaze.opt:88
++msgid "Check for stack overflow at runtime."
+ msgstr ""
+ 
+-#: c-family/c.opt:451
+-msgid "Warn about format strings that contain NUL bytes."
++#: config/microblaze/microblaze.opt:92 config/iq2000/iq2000.opt:65
++msgid "Use GP relative sdata/sbss sections."
+ msgstr ""
+ 
+-#: c-family/c.opt:455
+-msgid "Warn if passing too many arguments to a function for its format string."
++#: config/microblaze/microblaze.opt:95
++#, c-format
++msgid "%qs is deprecated; use -fno-zero-initialized-in-bss"
+ msgstr ""
+ 
+-#: c-family/c.opt:459
+-msgid "Warn about format strings that are not literals."
++#: config/microblaze/microblaze.opt:96
++msgid "Clear the BSS to zero and place zero initialized in BSS."
+ msgstr ""
+ 
+-#: c-family/c.opt:463
+-msgid "Warn about possible security problems with format functions."
++#: config/microblaze/microblaze.opt:100
++msgid "Use multiply high instructions for high part of 32x32 multiply."
+ msgstr ""
+ 
+-#: c-family/c.opt:467
+-msgid "Warn about sign differences with format functions."
++#: config/microblaze/microblaze.opt:104
++msgid "Use hardware floating point conversion instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:471
+-msgid "Warn about strftime formats yielding 2-digit years."
++#: config/microblaze/microblaze.opt:108
++msgid "Use hardware floating point square root instruction."
+ msgstr ""
+ 
+-#: c-family/c.opt:475
+-msgid "Warn about zero-length formats."
++#: config/microblaze/microblaze.opt:112
++msgid "Description for mxl-mode-executable."
+ msgstr ""
+ 
+-#: c-family/c.opt:483
+-msgid "Warn whenever type qualifiers are ignored."
++#: config/microblaze/microblaze.opt:116
++msgid "Description for mxl-mode-xmdstub."
+ msgstr ""
+ 
+-#: c-family/c.opt:487
+-msgid "Warn whenever attributes are ignored."
++#: config/microblaze/microblaze.opt:120
++msgid "Description for mxl-mode-bootstrap."
+ msgstr ""
+ 
+-#: c-family/c.opt:491
+-msgid ""
+-"Warn when there is a conversion between pointers that have incompatible "
+-"types."
++#: config/microblaze/microblaze.opt:124
++msgid "Description for mxl-mode-novectors."
+ msgstr ""
+ 
+-#: c-family/c.opt:495
+-msgid "Warn about variables which are initialized to themselves."
++#: config/microblaze/microblaze.opt:128
++msgid "Use hardware prefetch instruction"
+ msgstr ""
+ 
+-#: c-family/c.opt:499
+-msgid "Warn about implicit declarations."
++#: config/spu/spu.opt:20
++msgid "Emit warnings when run-time relocations are generated."
+ msgstr ""
+ 
+-#: c-family/c.opt:503
+-msgid "Warn about implicit conversions from \"float\" to \"double\"."
++#: config/spu/spu.opt:24
++msgid "Emit errors when run-time relocations are generated."
+ msgstr ""
+ 
+-#: c-family/c.opt:507
+-msgid "Warn about implicit function declarations."
++#: config/spu/spu.opt:28
++msgid "Specify cost of branches (Default 20)."
+ msgstr ""
+ 
+-#: c-family/c.opt:511
+-msgid "Warn when a declaration does not specify a type."
++#: config/spu/spu.opt:32
++msgid "Make sure loads and stores are not moved past DMA instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:518
+-msgid ""
+-"Warn about C++11 inheriting constructors when the base has a variadic "
+-"constructor."
++#: config/spu/spu.opt:36
++msgid "volatile must be specified on any memory that is effected by DMA."
+ msgstr ""
+ 
+-#: c-family/c.opt:522
++#: config/spu/spu.opt:40 config/spu/spu.opt:44
+ msgid ""
+-"Warn about incompatible integer to pointer and pointer to integer "
+-"conversions."
++"Insert nops when it might improve performance by allowing dual issue "
++"(default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:526
+-msgid ""
+-"Warn when there is a cast to a pointer from an integer of a different size."
++#: config/spu/spu.opt:48
++msgid "Use standard main function as entry for startup."
+ msgstr ""
+ 
+-#: c-family/c.opt:530
+-msgid "Warn about invalid uses of the \"offsetof\" macro."
++#: config/spu/spu.opt:52
++msgid "Generate branch hints for branches."
+ msgstr ""
+ 
+-#: c-family/c.opt:534
+-msgid "Warn about PCH files that are found but not used."
++#: config/spu/spu.opt:56
++msgid "Maximum number of nops to insert for a hint (Default 2)."
+ msgstr ""
+ 
+-#: c-family/c.opt:538
+-msgid "Warn when a jump misses a variable initialization."
+-msgstr ""
+-
+-#: c-family/c.opt:542
++#: config/spu/spu.opt:60
+ msgid ""
+-"Warn when a string or character literal is followed by a ud-suffix which "
+-"does not begin with an underscore."
++"Approximate maximum number of instructions to allow between a hint and its "
++"branch [125]."
+ msgstr ""
+ 
+-#: c-family/c.opt:546
+-msgid ""
+-"Warn when a logical operator is suspiciously always evaluating to true or "
+-"false."
++#: config/spu/spu.opt:64
++msgid "Generate code for 18 bit addressing."
+ msgstr ""
+ 
+-#: c-family/c.opt:550
+-msgid ""
+-"Warn when logical not is used on the left hand side operand of a comparison."
++#: config/spu/spu.opt:68
++msgid "Generate code for 32 bit addressing."
+ msgstr ""
+ 
+-#: c-family/c.opt:554
+-msgid "Do not warn about using \"long long\" when -pedantic."
++#: config/spu/spu.opt:72 config/sh/sh.opt:273 config/ia64/ia64.opt:114
++#: config/pa/pa.opt:58
++msgid "Specify range of registers to make fixed."
+ msgstr ""
+ 
+-#: c-family/c.opt:558
+-msgid "Warn about suspicious declarations of \"main\"."
+-msgstr ""
+-
+-#: c-family/c.opt:566
++#: config/spu/spu.opt:76
+ msgid ""
+-"Warn about suspicious calls to memset where the third argument is constant "
+-"literal zero and the second is not."
++"Insert hbrp instructions after hinted branch targets to avoid the SPU hang "
++"issue."
+ msgstr ""
+ 
+-#: c-family/c.opt:570
+-msgid ""
+-"Warn when the indentation of the code does not reflect the block structure."
++#: config/spu/spu.opt:80 config/s390/s390.opt:56 config/i386/i386.opt:247
++msgid "Generate code for given CPU."
+ msgstr ""
+ 
+-#: c-family/c.opt:574
+-msgid "Warn about possibly missing braces around initializers."
++#: config/spu/spu.opt:88
++msgid "Access variables in 32-bit PPU objects (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:578
+-msgid "Warn about global functions without previous declarations."
++#: config/spu/spu.opt:92
++msgid "Access variables in 64-bit PPU objects."
+ msgstr ""
+ 
+-#: c-family/c.opt:582
+-msgid "Warn about missing fields in struct initializers."
++#: config/spu/spu.opt:96
++msgid "Allow conversions between __ea and generic pointers (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:586
+-msgid "Warn on direct multiple inheritance."
++#: config/spu/spu.opt:100
++msgid "Size (in KB) of software data cache."
+ msgstr ""
+ 
+-#: c-family/c.opt:590
+-msgid "Warn on namespace definition."
++#: config/spu/spu.opt:104
++msgid "Atomically write back software data cache lines (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:594
+-msgid "Warn about missing sized deallocation functions."
++#: config/c6x/c6x-tables.opt:24
++msgid "Known C6X ISAs (for use with the -march= option):"
+ msgstr ""
+ 
+-#: c-family/c.opt:598
+-msgid ""
+-"Warn about suspicious length parameters to certain string functions if the "
+-"argument uses sizeof."
++#: config/c6x/c6x.opt:38 config/msp430/msp430.opt:3 config/mep/mep.opt:143
++#: config/bfin/bfin.opt:40
++msgid "Use simulator runtime."
+ msgstr ""
+ 
+-#: c-family/c.opt:602
+-msgid "Warn when sizeof is applied on a parameter declared as an array."
++#: config/c6x/c6x.opt:42 config/rs6000/sysv4.opt:28
++msgid "Select method for sdata handling."
+ msgstr ""
+ 
+-#: c-family/c.opt:606
+-msgid "Warn about functions which might be candidates for format attributes."
++#: config/c6x/c6x.opt:46
++msgid "Valid arguments for the -msdata= option."
+ msgstr ""
+ 
+-#: c-family/c.opt:610
+-msgid ""
+-"Suggest that the override keyword be used when the declaration of a virtual"
++#: config/c6x/c6x.opt:59
++msgid "Compile for the DSBT shared library ABI."
+ msgstr ""
+ 
+-#: c-family/c.opt:615
+-msgid "Warn about enumerated switches, with no default, missing a case."
++#: config/c6x/c6x.opt:63 config/bfin/bfin.opt:82
++msgid "Avoid generating pc-relative calls; use indirection."
+ msgstr ""
+ 
+-#: c-family/c.opt:619
+-msgid "Warn about enumerated switches missing a \"default:\" statement."
++#: config/c6x/c6x.opt:67 config/m68k/m68k.opt:103 config/arm/arm.opt:81
++#: config/nios2/nios2.opt:570 config/nds32/nds32.opt:66
++msgid "Specify the name of the target architecture."
+ msgstr ""
+ 
+-#: c-family/c.opt:623
+-msgid "Warn about all enumerated switches missing a specific case."
++#: config/mcore/mcore.opt:23
++msgid "Generate code for the M*Core M210"
+ msgstr ""
+ 
+-#: c-family/c.opt:627
+-msgid "Warn about switches with boolean controlling expression."
++#: config/mcore/mcore.opt:27
++msgid "Generate code for the M*Core M340"
+ msgstr ""
+ 
+-#: c-family/c.opt:631
+-msgid "Warn on primary template declaration."
++#: config/mcore/mcore.opt:31
++msgid "Force functions to be aligned to a 4 byte boundary."
+ msgstr ""
+ 
+-#: c-family/c.opt:639
+-msgid "Warn about user-specified include directories that do not exist."
++#: config/mcore/mcore.opt:35 config/moxie/moxie.opt:23
++msgid "Generate big-endian code."
+ msgstr ""
+ 
+-#: c-family/c.opt:643
+-msgid ""
+-"Warn about function parameters declared without a type specifier in K&R-"
+-"style functions."
++#: config/mcore/mcore.opt:39
++msgid "Emit call graph information."
+ msgstr ""
+ 
+-#: c-family/c.opt:647
+-msgid "Warn about global functions without prototypes."
++#: config/mcore/mcore.opt:43
++msgid "Use the divide instruction."
+ msgstr ""
+ 
+-#: c-family/c.opt:650 c-family/c.opt:1024 c-family/c.opt:1031
+-#: c-family/c.opt:1205 c-family/c.opt:1224 c-family/c.opt:1247
+-#: c-family/c.opt:1253 c-family/c.opt:1260 c-family/c.opt:1284
+-#: c-family/c.opt:1295 c-family/c.opt:1298 c-family/c.opt:1301
+-#: c-family/c.opt:1304 c-family/c.opt:1307 c-family/c.opt:1344
+-#: c-family/c.opt:1475 c-family/c.opt:1499 c-family/c.opt:1517
+-#: c-family/c.opt:1548 c-family/c.opt:1552 c-family/c.opt:1568
+-#: config/ia64/ia64.opt:167 config/ia64/ia64.opt:170 c-family/c-opts.c:419
+-#, gcc-internal-format
+-msgid "switch %qs is no longer supported"
++#: config/mcore/mcore.opt:47
++msgid "Inline constants if it can be done in 2 insns or less."
+ msgstr ""
+ 
+-#: c-family/c.opt:654
+-msgid "Warn about use of multi-character character constants."
++#: config/mcore/mcore.opt:51 config/moxie/moxie.opt:27
++msgid "Generate little-endian code."
+ msgstr ""
+ 
+-#: c-family/c.opt:658
++#: config/mcore/mcore.opt:56 config/fr30/fr30.opt:27
+ msgid ""
+-"Warn about narrowing conversions within { } that are ill-formed in C++11."
++"Assume that run-time support has been provided, so omit -lsim from the "
++"linker command line."
+ msgstr ""
+ 
+-#: c-family/c.opt:662
+-msgid "Warn about \"extern\" declarations not at file scope."
++#: config/mcore/mcore.opt:60
++msgid "Use arbitrary sized immediates in bit operations."
+ msgstr ""
+ 
+-#: c-family/c.opt:666
+-msgid ""
+-"Warn when a noexcept expression evaluates to false even though the "
+-"expression can't actually throw."
++#: config/mcore/mcore.opt:64
++msgid "Prefer word accesses over byte accesses."
+ msgstr ""
+ 
+-#: c-family/c.opt:670
+-msgid ""
+-"Warn when non-templatized friend functions are declared within a template."
++#: config/mcore/mcore.opt:71
++msgid "Set the maximum amount for a single stack increment operation."
+ msgstr ""
+ 
+-#: c-family/c.opt:674
+-msgid "Warn about non-virtual destructors."
++#: config/mcore/mcore.opt:75
++msgid "Always treat bitfields as int-sized."
+ msgstr ""
+ 
+-#: c-family/c.opt:678
+-msgid ""
+-"Warn about NULL being passed to argument slots marked as requiring non-NULL."
++#: config/arc/arc.opt:26
++msgid "Compile code for big endian mode."
+ msgstr ""
+ 
+-#: c-family/c.opt:694
++#: config/arc/arc.opt:30
++msgid "Compile code for little endian mode.  This is the default."
++msgstr ""
++
++#: config/arc/arc.opt:34
+ msgid ""
+-"-Wnormalized=<none|id|nfc|nfkc>\tWarn about non-normalised Unicode strings."
++"Disable ARCompact specific pass to generate conditional execution "
++"instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:701
+-msgid "argument %qs to %<-Wnormalized%> not recognized"
++#: config/arc/arc.opt:38
++msgid "Generate ARCompact 32-bit code for ARC600 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:717
+-msgid "Warn if a C-style cast is used in a program."
++#: config/arc/arc.opt:42
++msgid "Same as -mA6."
+ msgstr ""
+ 
+-#: c-family/c.opt:721
+-msgid "Warn for obsolescent usage in a declaration."
++#: config/arc/arc.opt:46
++msgid "Generate ARCompact 32-bit code for ARC601 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:725
+-msgid "Warn if an old-style parameter definition is used."
++#: config/arc/arc.opt:50
++msgid "Generate ARCompact 32-bit code for ARC700 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:729
+-msgid "Warn if a simd directive is overridden by the vectorizer cost model."
++#: config/arc/arc.opt:54
++msgid "Same as -mA7."
+ msgstr ""
+ 
+-#: c-family/c.opt:733
++#: config/arc/arc.opt:58
+ msgid ""
+-"Warn if a string is longer than the maximum portable length specified by the "
+-"standard."
++"-mmpy-option={0,1,2,3,4,5,6,7,8,9} Compile ARCv2 code with a multiplier "
++"design option.  Option 2 is default on."
+ msgstr ""
+ 
+-#: c-family/c.opt:737
+-msgid "Warn about overloaded virtual function names."
++#: config/arc/arc.opt:62
++msgid "Enable DIV-REM instructions for ARCv2."
+ msgstr ""
+ 
+-#: c-family/c.opt:741
+-msgid "Warn about overriding initializers without side effects."
++#: config/arc/arc.opt:66
++msgid "Enable code density instructions for ARCv2."
+ msgstr ""
+ 
+-#: c-family/c.opt:745
+-msgid "Warn about overriding initializers with side effects."
++#: config/arc/arc.opt:70
++msgid "Tweak register allocation to help 16-bit instruction generation."
+ msgstr ""
+ 
+-#: c-family/c.opt:749
+-msgid "Warn about packed bit-fields whose offset changed in GCC 4.4."
++#: config/arc/arc.opt:80
++msgid "Use ordinarily cached memory accesses for volatile references."
+ msgstr ""
+ 
+-#: c-family/c.opt:753
+-msgid "Warn about possibly missing parentheses."
++#: config/arc/arc.opt:84
++msgid "Enable cache bypass for volatile references."
+ msgstr ""
+ 
+-#: c-family/c.opt:761
+-msgid "Warn when converting the type of pointers to member functions."
++#: config/arc/arc.opt:88
++msgid "Generate instructions supported by barrel shifter."
+ msgstr ""
+ 
+-#: c-family/c.opt:765
+-msgid "Warn about function pointer arithmetic."
++#: config/arc/arc.opt:92
++msgid "Generate norm instruction."
+ msgstr ""
+ 
+-#: c-family/c.opt:769
+-msgid "Warn when a pointer differs in signedness in an assignment."
++#: config/arc/arc.opt:96
++msgid "Generate swap instruction."
+ msgstr ""
+ 
+-#: c-family/c.opt:773
+-msgid "Warn when a pointer is cast to an integer of a different size."
++#: config/arc/arc.opt:100
++msgid "Generate mul64 and mulu64 instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:777
+-msgid "Warn about misuses of pragmas."
++#: config/arc/arc.opt:104
++msgid "Do not generate mpy instructions for ARC700."
+ msgstr ""
+ 
+-#: c-family/c.opt:781
++#: config/arc/arc.opt:108
+ msgid ""
+-"Warn if a property for an Objective-C object has no assign semantics "
+-"specified."
++"Generate Extended arithmetic instructions.  Currently only divaw, adds, subs "
++"and sat16 are supported."
+ msgstr ""
+ 
+-#: c-family/c.opt:785
+-msgid "Warn if inherited methods are unimplemented."
++#: config/arc/arc.opt:112
++msgid ""
++"Dummy flag. This is the default unless FPX switches are provided explicitly."
+ msgstr ""
+ 
+-#: c-family/c.opt:789 c-family/c.opt:793
+-msgid "Warn for placement new expressions with undefined behavior."
++#: config/arc/arc.opt:116
++msgid "Generate call insns as register indirect calls."
+ msgstr ""
+ 
+-#: c-family/c.opt:797
+-msgid "Warn about multiple declarations of the same object."
++#: config/arc/arc.opt:120
++msgid "Do no generate BRcc instructions in arc_reorg."
+ msgstr ""
+ 
+-#: c-family/c.opt:801
+-msgid "Warn when the compiler reorders code."
+-msgstr ""
+-
+-#: c-family/c.opt:805
++#: config/arc/arc.opt:124
+ msgid ""
+-"Warn whenever a function's return type defaults to \"int\" (C), or about "
+-"inconsistent return types (C++)."
++"Generate sdata references.  This is the default, unless you compile for PIC."
+ msgstr ""
+ 
+-#: c-family/c.opt:809
+-msgid "Warn on suspicious constructs involving reverse scalar storage order."
++#: config/arc/arc.opt:128
++msgid "Do not generate millicode thunks (needed only with -Os)."
+ msgstr ""
+ 
+-#: c-family/c.opt:813
+-msgid "Warn if a selector has multiple methods."
++#: config/arc/arc.opt:132 config/arc/arc.opt:136
++msgid "FPX: Generate Single Precision FPX (compact) instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:817
+-msgid "Warn about possible violations of sequence point rules."
++#: config/arc/arc.opt:140
++msgid "FPX: Generate Single Precision FPX (fast) instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:821
+-msgid "Warn if a local declaration hides an instance variable."
++#: config/arc/arc.opt:144
++msgid ""
++"FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions."
+ msgstr ""
+ 
+-#: c-family/c.opt:825 c-family/c.opt:829
+-msgid "Warn if left shift of a signed value overflows."
++#: config/arc/arc.opt:148 config/arc/arc.opt:152
++msgid "FPX: Generate Double Precision FPX (compact) instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:833
+-msgid "Warn if shift count is negative."
++#: config/arc/arc.opt:156
++msgid "FPX: Generate Double Precision FPX (fast) instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:837
+-msgid "Warn if shift count >= width of type."
++#: config/arc/arc.opt:160
++msgid "Disable LR and SR instructions from using FPX extension aux registers."
+ msgstr ""
+ 
+-#: c-family/c.opt:841
+-msgid "Warn if left shifting a negative value."
+-msgstr ""
+-
+-#: c-family/c.opt:845
+-msgid "Warn about signed-unsigned comparisons."
+-msgstr ""
+-
+-#: c-family/c.opt:853
++#: config/arc/arc.opt:164
+ msgid ""
+-"Warn for implicit type conversions between signed and unsigned integers."
++"Enable generation of ARC SIMD instructions via target-specific builtins."
+ msgstr ""
+ 
+-#: c-family/c.opt:857
+-msgid "Warn when overload promotes from unsigned to signed."
++#: config/arc/arc.opt:168
++msgid "-mcpu=CPU\tCompile code for ARC variant CPU."
+ msgstr ""
+ 
+-#: c-family/c.opt:861
+-msgid "Warn about uncasted NULL used as sentinel."
+-msgstr ""
+-
+-#: c-family/c.opt:865
+-msgid "Warn about unprototyped function declarations."
+-msgstr ""
+-
+-#: c-family/c.opt:877
+-msgid "Warn if type signatures of candidate methods do not match exactly."
+-msgstr ""
+-
+-#: c-family/c.opt:881
++#: config/arc/arc.opt:205
+ msgid ""
+-"Warn when __sync_fetch_and_nand and __sync_nand_and_fetch built-in functions "
+-"are used."
++"size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -"
++"Os."
+ msgstr ""
+ 
+-#: c-family/c.opt:885
+-msgid "Deprecated.  This switch has no effect."
++#: config/arc/arc.opt:209 config/sh/sh.opt:301
++msgid "Annotate assembler instructions with estimated addresses."
+ msgstr ""
+ 
+-#: c-family/c.opt:893
+-msgid "Warn if a comparison always evaluates to true or false."
+-msgstr ""
+-
+-#: c-family/c.opt:897
+-msgid "Warn if a throw expression will always result in a call to terminate()."
+-msgstr ""
+-
+-#: c-family/c.opt:901
+-msgid "Warn about features not present in traditional C."
+-msgstr ""
+-
+-#: c-family/c.opt:905
++#: config/arc/arc.opt:213
+ msgid ""
+-"Warn of prototypes causing type conversions different from what would happen "
+-"in the absence of prototype."
++"Cost to assume for a multiply instruction, with 4 being equal to a normal "
++"insn."
+ msgstr ""
+ 
+-#: c-family/c.opt:909
+-msgid ""
+-"Warn if trigraphs are encountered that might affect the meaning of the "
+-"program."
++#: config/arc/arc.opt:217
++msgid "Tune for ARC600 cpu."
+ msgstr ""
+ 
+-#: c-family/c.opt:913
+-msgid "Warn about @selector()s without previously declared methods."
++#: config/arc/arc.opt:221
++msgid "Tune for ARC601 cpu."
+ msgstr ""
+ 
+-#: c-family/c.opt:917
+-msgid "Warn if an undefined macro is used in an #if directive."
++#: config/arc/arc.opt:225
++msgid "Tune for ARC700 R4.2 Cpu with standard multiplier block."
+ msgstr ""
+ 
+-#: c-family/c.opt:929
+-msgid "Warn about unrecognized pragmas."
++#: config/arc/arc.opt:229 config/arc/arc.opt:233 config/arc/arc.opt:237
++msgid "Tune for ARC700 R4.2 Cpu with XMAC block."
+ msgstr ""
+ 
+-#: c-family/c.opt:933
+-msgid "Warn about unsuffixed float constants."
++#: config/arc/arc.opt:241
++msgid "Enable the use of indexed loads."
+ msgstr ""
+ 
+-#: c-family/c.opt:941
+-msgid "Warn when typedefs locally defined in a function are not used."
++#: config/arc/arc.opt:245
++msgid "Enable the use of pre/post modify with register displacement."
+ msgstr ""
+ 
+-#: c-family/c.opt:945
+-msgid "Warn about macros defined in the main file that are not used."
++#: config/arc/arc.opt:249
++msgid "Generate 32x16 multiply and mac instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:949
+-msgid ""
+-"Warn if a caller of a function, marked with attribute warn_unused_result, "
+-"does not use its return value."
++#: config/arc/arc.opt:255
++msgid "Set probability threshold for unaligning branches."
+ msgstr ""
+ 
+-#: c-family/c.opt:957 c-family/c.opt:961
+-msgid "Warn when a const variable is unused."
++#: config/arc/arc.opt:259
++msgid "Don't use less than 25 bit addressing range for calls."
+ msgstr ""
+ 
+-#: c-family/c.opt:965
+-msgid "Warn about using variadic macros."
+-msgstr ""
+-
+-#: c-family/c.opt:969
++#: config/arc/arc.opt:263
+ msgid ""
+-"Warn about questionable usage of the macros used to retrieve variable "
+-"arguments."
++"Explain what alignment considerations lead to the decision to make an insn "
++"short or long."
+ msgstr ""
+ 
+-#: c-family/c.opt:973
+-msgid "Warn if a variable length array is used."
++#: config/arc/arc.opt:267
++msgid "Do alignment optimizations for call instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:977
+-msgid "Warn when a register variable is declared volatile."
+-msgstr ""
+-
+-#: c-family/c.opt:981
+-msgid "Warn on direct virtual inheritance."
+-msgstr ""
+-
+-#: c-family/c.opt:985
+-msgid "Warn if a virtual base has a non-trivial move assignment operator."
+-msgstr ""
+-
+-#: c-family/c.opt:989
++#: config/arc/arc.opt:271
+ msgid ""
+-"In C++, nonzero means warn about deprecated conversion from string literals "
+-"to 'char *'.  In C, similar warning, except that the conversion is of course "
+-"not deprecated by the ISO C standard."
++"Enable Rcq constraint handling - most short code generation depends on this."
+ msgstr ""
+ 
+-#: c-family/c.opt:993
+-msgid "Warn when a literal '0' is used as null pointer."
++#: config/arc/arc.opt:275
++msgid "Enable Rcw constraint handling - ccfsm condexec mostly depends on this."
+ msgstr ""
+ 
+-#: c-family/c.opt:997
+-msgid "Warn about useless casts."
++#: config/arc/arc.opt:279
++msgid "Enable pre-reload use of cbranchsi pattern."
+ msgstr ""
+ 
+-#: c-family/c.opt:1001
+-msgid ""
+-"Warn if a class type has a base or a field whose type uses the anonymous "
+-"namespace or depends on a type with no linkage."
++#: config/arc/arc.opt:283
++msgid "Enable bbit peephole2."
+ msgstr ""
+ 
+-#: c-family/c.opt:1005
+-msgid "A synonym for -std=c89 (for C) or -std=c++98 (for C++)."
+-msgstr ""
+-
+-#: c-family/c.opt:1013
++#: config/arc/arc.opt:287
+ msgid ""
+-"The version of the C++ ABI used for -Wabi warnings and link compatibility "
+-"aliases."
++"Use pc-relative switch case tables - this enables case table shortening."
+ msgstr ""
+ 
+-#: c-family/c.opt:1017
+-msgid "Enforce class member access control semantics."
++#: config/arc/arc.opt:291
++msgid "Enable compact casesi pattern."
+ msgstr ""
+ 
+-#: c-family/c.opt:1021
+-msgid "-fada-spec-parent=unit  Dump Ada specs as child units of given parent."
++#: config/arc/arc.opt:295
++msgid "Enable 'q' instruction alternatives."
+ msgstr ""
+ 
+-#: c-family/c.opt:1028
+-msgid "Allow variadic functions without named parameter."
++#: config/arc/arc.opt:299
++msgid "Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc."
+ msgstr ""
+ 
+-#: c-family/c.opt:1032 c-family/c.opt:1261 c-family/c.opt:1549
+-#: c-family/c.opt:1553 c-family/c.opt:1569
+-msgid "No longer supported."
++#: config/arc/arc.opt:306
++msgid "Enable variable polynomial CRC extension."
+ msgstr ""
+ 
+-#: c-family/c.opt:1036
+-msgid "Recognize the \"asm\" keyword."
++#: config/arc/arc.opt:310
++msgid "Enable DSP 3.1 Pack A extensions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1044
+-msgid "Recognize built-in functions."
++#: config/arc/arc.opt:314
++msgid "Enable dual viterbi butterfly extension."
+ msgstr ""
+ 
+-#: c-family/c.opt:1051
+-msgid "Where shorter, use canonicalized paths to systems headers."
++#: config/arc/arc.opt:324
++msgid "Enable Dual and Single Operand Instructions for Telephony."
+ msgstr ""
+ 
+-#: c-family/c.opt:1055
+-msgid "Add Pointer Bounds Checker instrumentation.  fchkp-* flags are used to"
++#: config/arc/arc.opt:328
++msgid "Enable XY Memory extension (DSP version 3)."
+ msgstr ""
+ 
+-#: c-family/c.opt:1060
+-msgid "Generate pointer bounds checks for variables with incomplete type."
++#: config/arc/arc.opt:333
++msgid "Enable Locked Load/Store Conditional extension."
+ msgstr ""
+ 
+-#: c-family/c.opt:1064
+-msgid ""
+-"Use zero bounds for all incoming arguments in 'main' function.  It helps when"
++#: config/arc/arc.opt:337
++msgid "Enable swap byte ordering extension instruction."
+ msgstr ""
+ 
+-#: c-family/c.opt:1069
+-msgid ""
+-"Forces Pointer Bounds Checker to use narrowed bounds for address of the first"
++#: config/arc/arc.opt:341
++msgid "Enable 64-bit Time-Stamp Counter extension instruction."
+ msgstr ""
+ 
+-#: c-family/c.opt:1075
+-msgid ""
+-"Control how Pointer Bounds Checker handle pointers to object fields.  When"
++#: config/arc/arc.opt:345
++msgid "Pass -EB option through to linker."
+ msgstr ""
+ 
+-#: c-family/c.opt:1080
+-msgid ""
+-"Forces Pointer Bounds Checker to use bounds of the innermost arrays in case "
+-"of"
++#: config/arc/arc.opt:349
++msgid "Pass -EL option through to linker."
+ msgstr ""
+ 
+-#: c-family/c.opt:1085
+-msgid "Allow Pointer Bounds Checker optimizations.  By default allowed"
++#: config/arc/arc.opt:353
++msgid "Pass -marclinux option through to linker."
+ msgstr ""
+ 
+-#: c-family/c.opt:1090
+-msgid ""
+-"Allow to use *_nobnd versions of string functions by Pointer Bounds Checker."
++#: config/arc/arc.opt:357
++msgid "Pass -marclinux_prof option through to linker."
+ msgstr ""
+ 
+-#: c-family/c.opt:1094
+-msgid ""
+-"Allow to use *_nochk versions of string functions by Pointer Bounds Checker."
++#: config/arc/arc.opt:365
++msgid "Enable lra."
+ msgstr ""
+ 
+-#: c-family/c.opt:1098
+-msgid "Use statically initialized variable for vars bounds instead of"
++#: config/arc/arc.opt:369
++msgid "Don't indicate any priority with TARGET_REGISTER_PRIORITY."
+ msgstr ""
+ 
+-#: c-family/c.opt:1103
+-msgid "Use statically initialized variable for constant bounds instead of"
++#: config/arc/arc.opt:373
++msgid "Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY."
+ msgstr ""
+ 
+-#: c-family/c.opt:1108
+-msgid "With this option zero size obtained dynamically for objects with"
++#: config/arc/arc.opt:377
++msgid "Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY."
+ msgstr ""
+ 
+-#: c-family/c.opt:1113
+-msgid "Generate checks for all read accesses to memory."
++#: config/arc/arc.opt:381
++msgid "instrument with mcount calls as in the ucb code."
+ msgstr ""
+ 
+-#: c-family/c.opt:1117
+-msgid "Generate checks for all write accesses to memory."
++#: config/arc/arc.opt:411
++msgid "Enable atomic instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1121
+-msgid "Generate bounds stores for pointer writes."
++#: config/arc/arc.opt:415
++msgid "Enable double load/store instructions for ARC HS."
+ msgstr ""
+ 
+-#: c-family/c.opt:1125
+-msgid "Generate bounds passing for calls."
++#: config/arc/arc.opt:419
++msgid "Specify the name of the target floating point configuration."
+ msgstr ""
+ 
+-#: c-family/c.opt:1129
+-msgid "Instrument only functions marked with bnd_instrument attribute."
++#: config/m68k/m68k.opt:30
++msgid "Generate code for a 520X."
+ msgstr ""
+ 
+-#: c-family/c.opt:1133
+-msgid "Transform instrumented builtin calls into calls to wrappers."
++#: config/m68k/m68k.opt:34
++msgid "Generate code for a 5206e."
+ msgstr ""
+ 
+-#: c-family/c.opt:1143
+-msgid "Enable Cilk Plus."
++#: config/m68k/m68k.opt:38
++msgid "Generate code for a 528x."
+ msgstr ""
+ 
+-#: c-family/c.opt:1147
+-msgid "Enable support for C++ concepts."
++#: config/m68k/m68k.opt:42
++msgid "Generate code for a 5307."
+ msgstr ""
+ 
+-#: c-family/c.opt:1151
+-msgid "Allow the arguments of the '?' operator to have different types."
++#: config/m68k/m68k.opt:46
++msgid "Generate code for a 5407."
+ msgstr ""
+ 
+-#: c-family/c.opt:1158
+-#, c-format
+-msgid "no class name specified with %qs"
++#: config/m68k/m68k.opt:50 config/m68k/m68k.opt:111
++msgid "Generate code for a 68000."
+ msgstr ""
+ 
+-#: c-family/c.opt:1159
+-msgid "-fconst-string-class=<name>\tUse class <name> for constant strings."
++#: config/m68k/m68k.opt:54
++msgid "Generate code for a 68010."
+ msgstr ""
+ 
+-#: c-family/c.opt:1163
+-msgid "-fconstexpr-depth=<number>\tSpecify maximum constexpr recursion depth."
++#: config/m68k/m68k.opt:58 config/m68k/m68k.opt:115
++msgid "Generate code for a 68020."
+ msgstr ""
+ 
+-#: c-family/c.opt:1167
+-msgid "Emit debug annotations during preprocessing."
++#: config/m68k/m68k.opt:62
++msgid "Generate code for a 68040, without any new instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1171
+-msgid ""
+-"-fdeduce-init-list\tenable deduction of std::initializer_list for a template "
+-"type parameter from a brace-enclosed initializer-list."
++#: config/m68k/m68k.opt:66
++msgid "Generate code for a 68060, without any new instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1175
+-msgid "Factor complex constructors and destructors to favor space over speed."
++#: config/m68k/m68k.opt:70
++msgid "Generate code for a 68030."
+ msgstr ""
+ 
+-#: c-family/c.opt:1183
+-msgid "Preprocess directives only."
++#: config/m68k/m68k.opt:74
++msgid "Generate code for a 68040."
+ msgstr ""
+ 
+-#: c-family/c.opt:1187
+-msgid "Permit '$' as an identifier character."
++#: config/m68k/m68k.opt:78
++msgid "Generate code for a 68060."
+ msgstr ""
+ 
+-#: c-family/c.opt:1191
+-msgid "Write all declarations as Ada code transitively."
++#: config/m68k/m68k.opt:82
++msgid "Generate code for a 68302."
+ msgstr ""
+ 
+-#: c-family/c.opt:1195
+-msgid "Write all declarations as Ada code for the given file only."
++#: config/m68k/m68k.opt:86
++msgid "Generate code for a 68332."
+ msgstr ""
+ 
+-#: c-family/c.opt:1202
+-msgid "Generate code to check exception specifications."
++#: config/m68k/m68k.opt:91
++msgid "Generate code for a 68851."
+ msgstr ""
+ 
+-#: c-family/c.opt:1209
+-msgid ""
+-"-fexec-charset=<cset>\tConvert all strings and character constants to "
+-"character set <cset>."
++#: config/m68k/m68k.opt:95
++msgid "Generate code that uses 68881 floating-point instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1213
+-msgid "Permit universal character names (\\u and \\U) in identifiers."
++#: config/m68k/m68k.opt:99
++msgid "Align variables on a 32-bit boundary."
+ msgstr ""
+ 
+-#: c-family/c.opt:1217
+-msgid ""
+-"-finput-charset=<cset>\tSpecify the default character set for source files."
++#: config/m68k/m68k.opt:107
++msgid "Use the bit-field instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1221
+-msgid ""
+-"Support dynamic initialization of thread-local variables in a different "
+-"translation unit."
++#: config/m68k/m68k.opt:119
++msgid "Generate code for a ColdFire v4e."
+ msgstr ""
+ 
+-#: c-family/c.opt:1228
+-msgid "Scope of for-init-statement variables is local to the loop."
++#: config/m68k/m68k.opt:123
++msgid "Specify the target CPU."
+ msgstr ""
+ 
+-#: c-family/c.opt:1232
+-msgid "Do not assume that standard C libraries and \"main\" exist."
++#: config/m68k/m68k.opt:127
++msgid "Generate code for a cpu32."
+ msgstr ""
+ 
+-#: c-family/c.opt:1236
+-msgid "Recognize GNU-defined keywords."
++#: config/m68k/m68k.opt:131
++msgid "Use hardware division instructions on ColdFire."
+ msgstr ""
+ 
+-#: c-family/c.opt:1240
+-msgid "Generate code for GNU runtime environment."
++#: config/m68k/m68k.opt:135
++msgid "Generate code for a Fido A."
+ msgstr ""
+ 
+-#: c-family/c.opt:1244
+-msgid "Use traditional GNU semantics for inline functions."
++#: config/m68k/m68k.opt:139
++msgid "Generate code which uses hardware floating point instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1250
+-msgid ""
+-"-fhandle-exceptions has been renamed -fexceptions (and is now on by default)"
++#: config/m68k/m68k.opt:143
++msgid "Enable ID based shared library."
+ msgstr ""
+ 
+-#: c-family/c.opt:1257
+-msgid "Assume normal C execution environment."
++#: config/m68k/m68k.opt:147
++msgid "Do not use the bit-field instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1265
+-msgid "Export functions even if they can be inlined."
++#: config/m68k/m68k.opt:151
++msgid "Use normal calling convention."
+ msgstr ""
+ 
+-#: c-family/c.opt:1269
+-msgid "Emit implicit instantiations of inline templates."
++#: config/m68k/m68k.opt:155
++msgid "Consider type 'int' to be 32 bits wide."
+ msgstr ""
+ 
+-#: c-family/c.opt:1273
+-msgid "Emit implicit instantiations of templates."
++#: config/m68k/m68k.opt:159
++msgid "Generate pc-relative code."
+ msgstr ""
+ 
+-#: c-family/c.opt:1277
+-msgid "Inject friend functions into enclosing namespace."
++#: config/m68k/m68k.opt:163
++msgid "Use different calling convention using 'rtd'."
+ msgstr ""
+ 
+-#: c-family/c.opt:1281
+-msgid "Don't emit dllexported inline functions unless needed."
++#: config/m68k/m68k.opt:167 config/bfin/bfin.opt:78
++msgid "Enable separate data segment."
+ msgstr ""
+ 
+-#: c-family/c.opt:1288
+-msgid ""
+-"Allow implicit conversions between vectors with differing numbers of "
+-"subparts and/or differing element types."
++#: config/m68k/m68k.opt:171 config/bfin/bfin.opt:74
++msgid "ID of shared library to build."
+ msgstr ""
+ 
+-#: c-family/c.opt:1292
+-msgid "Don't warn about uses of Microsoft extensions."
++#: config/m68k/m68k.opt:175
++msgid "Consider type 'int' to be 16 bits wide."
+ msgstr ""
+ 
+-#: c-family/c.opt:1311
+-msgid "Generate code for NeXT (Apple Mac OS X) runtime environment."
++#: config/m68k/m68k.opt:179
++msgid "Generate code with library calls for floating point."
+ msgstr ""
+ 
+-#: c-family/c.opt:1315
+-msgid "Assume that receivers of Objective-C messages may be nil."
++#: config/m68k/m68k.opt:183
++msgid "Do not use unaligned memory references."
+ msgstr ""
+ 
+-#: c-family/c.opt:1319
+-msgid ""
+-"Allow access to instance variables as if they were local declarations within "
+-"instance method implementations."
++#: config/m68k/m68k.opt:187
++msgid "Tune for the specified target CPU or architecture."
+ msgstr ""
+ 
+-#: c-family/c.opt:1323
+-msgid ""
+-"-fvisibility=[private|protected|public|package]\tSet the default symbol "
+-"visibility."
++#: config/m68k/m68k.opt:191
++msgid "Support more than 8192 GOT entries on ColdFire."
+ msgstr ""
+ 
+-#: c-family/c.opt:1326
+-#, c-format
+-msgid "unrecognized ivar visibility value %qs"
++#: config/m68k/m68k.opt:195
++msgid "Support TLS segment larger than 64K."
+ msgstr ""
+ 
+-#: c-family/c.opt:1348
+-msgid ""
+-"Treat a throw() exception specification as noexcept to improve code size."
++#: config/m68k/ieee.opt:24 config/i386/i386.opt:358
++msgid "Use IEEE math for fp comparisons."
+ msgstr ""
+ 
+-#: c-family/c.opt:1352
+-msgid ""
+-"Specify which ABI to use for Objective-C family code and meta-data "
+-"generation."
++#: config/m68k/m68k-tables.opt:25
++msgid "Known M68K CPUs (for use with the -mcpu= option):"
+ msgstr ""
+ 
+-#: c-family/c.opt:1358
+-msgid ""
+-"Generate special Objective-C methods to initialize/destroy non-POD C++ "
+-"ivars, if needed."
++#: config/m68k/m68k-tables.opt:365
++msgid "Known M68K microarchitectures (for use with the -mtune= option):"
+ msgstr ""
+ 
+-#: c-family/c.opt:1362
+-msgid "Allow fast jumps to the message dispatcher."
++#: config/m68k/m68k-tables.opt:411
++msgid "Known M68K ISAs (for use with the -march= option):"
+ msgstr ""
+ 
+-#: c-family/c.opt:1368
+-msgid "Enable Objective-C exception and synchronization syntax."
++#: config/v850/v850.opt:29
++msgid "Use registers r2 and r5."
+ msgstr ""
+ 
+-#: c-family/c.opt:1372
+-msgid "Enable garbage collection (GC) in Objective-C/Objective-C++ programs."
++#: config/v850/v850.opt:33
++msgid "Use 4 byte entries in switch tables."
+ msgstr ""
+ 
+-#: c-family/c.opt:1376
+-msgid ""
+-"Enable inline checks for nil receivers with the NeXT runtime and ABI version "
+-"2."
++#: config/v850/v850.opt:37
++msgid "Enable backend debugging."
+ msgstr ""
+ 
+-#: c-family/c.opt:1381
+-msgid "Enable Objective-C setjmp exception handling runtime."
++#: config/v850/v850.opt:41
++msgid "Do not use the callt instruction (default)."
+ msgstr ""
+ 
+-#: c-family/c.opt:1385
+-msgid "Conform to the Objective-C 1.0 language as implemented in GCC 4.0."
++#: config/v850/v850.opt:45
++msgid "Reuse r30 on a per function basis."
+ msgstr ""
+ 
+-#: c-family/c.opt:1389
+-msgid "Enable OpenACC."
++#: config/v850/v850.opt:52
++msgid "Prohibit PC relative function calls."
+ msgstr ""
+ 
+-#: c-family/c.opt:1393
+-msgid "Specify default OpenACC compute dimensions."
++#: config/v850/v850.opt:56
++msgid "Use stubs for function prologues."
+ msgstr ""
+ 
+-#: c-family/c.opt:1397
+-msgid "Enable OpenMP (implies -frecursive in Fortran)."
++#: config/v850/v850.opt:60
++msgid "Set the max size of data eligible for the SDA area."
+ msgstr ""
+ 
+-#: c-family/c.opt:1401
+-msgid "Enable OpenMP's SIMD directives."
++#: config/v850/v850.opt:67
++msgid "Enable the use of the short load instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1405
+-msgid "Recognize C++ keywords like \"compl\" and \"xor\"."
++#: config/v850/v850.opt:71
++msgid "Same as: -mep -mprolog-function."
+ msgstr ""
+ 
+-#: c-family/c.opt:1416
+-msgid "Look for and use PCH files even when preprocessing."
++#: config/v850/v850.opt:75
++msgid "Set the max size of data eligible for the TDA area."
+ msgstr ""
+ 
+-#: c-family/c.opt:1420
+-msgid "Downgrade conformance errors to warnings."
++#: config/v850/v850.opt:82
++msgid "Do not enforce strict alignment."
+ msgstr ""
+ 
+-#: c-family/c.opt:1424
+-msgid "Enable Plan 9 language extensions."
+-msgstr ""
+-
+-#: c-family/c.opt:1428
+-msgid "Treat the input file as already preprocessed."
+-msgstr ""
+-
+-#: c-family/c.opt:1436
++#: config/v850/v850.opt:86
+ msgid ""
+-"-ftrack-macro-expansion=<0|1|2>  Track locations of tokens coming from macro "
+-"expansion and display them in error messages."
++"Put jump tables for switch statements into the .data section rather than "
++"the .code section."
+ msgstr ""
+ 
+-#: c-family/c.opt:1440
+-msgid ""
+-"-fno-pretty-templates Do not pretty-print template specializations as the "
+-"template signature followed by the arguments."
++#: config/v850/v850.opt:93
++msgid "Compile for the v850 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:1444
+-msgid ""
+-"Used in Fix-and-Continue mode to indicate that object files may be swapped "
+-"in at runtime."
++#: config/v850/v850.opt:97
++msgid "Compile for the v850e processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:1448
+-msgid "Enable automatic template instantiation."
++#: config/v850/v850.opt:101
++msgid "Compile for the v850e1 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:1452
+-msgid "Generate run time type descriptor information."
++#: config/v850/v850.opt:105
++msgid "Compile for the v850es variant of the v850e1."
+ msgstr ""
+ 
+-#: c-family/c.opt:1456 ada/gcc-interface/lang.opt:77
+-msgid "Use the narrowest integer type possible for enumeration types."
++#: config/v850/v850.opt:109
++msgid "Compile for the v850e2 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:1460
+-msgid "Force the underlying type for \"wchar_t\" to be \"unsigned short\"."
++#: config/v850/v850.opt:113
++msgid "Compile for the v850e2v3 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:1464
+-msgid "When \"signed\" or \"unsigned\" is not given make the bitfield signed."
++#: config/v850/v850.opt:117
++msgid "Compile for the v850e3v5 processor."
+ msgstr ""
+ 
+-#: c-family/c.opt:1468 ada/gcc-interface/lang.opt:81
+-msgid "Make \"char\" signed by default."
++#: config/v850/v850.opt:124
++msgid "Enable v850e3v5 loop instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1472
+-msgid "Enable C++14 sized deallocation support."
++#: config/v850/v850.opt:128
++msgid "Set the max size of data eligible for the ZDA area."
+ msgstr ""
+ 
+-#: c-family/c.opt:1479
+-msgid ""
+-"-fsso-struct=[big-endian|little-endian]\tSet the default scalar storage "
+-"order."
++#: config/v850/v850.opt:135
++msgid "Enable relaxing in the assembler."
+ msgstr ""
+ 
+-#: c-family/c.opt:1482
+-#, c-format
+-msgid "unrecognized scalar storage order value %qs"
++#: config/v850/v850.opt:139
++msgid "Prohibit PC relative jumps."
+ msgstr ""
+ 
+-#: c-family/c.opt:1492
+-msgid "Display statistics accumulated during compilation."
++#: config/v850/v850.opt:143
++msgid "Inhibit the use of hardware floating point instructions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1496
++#: config/v850/v850.opt:147
+ msgid ""
+-"Assume that values of enumeration type are always within the minimum range "
+-"of that type."
++"Allow the use of hardware floating point instructions for V850E2V3 and up."
+ msgstr ""
+ 
+-#: c-family/c.opt:1503
+-msgid "-ftabstop=<number>\tDistance between tab stops for column reporting."
++#: config/v850/v850.opt:151
++msgid "Enable support for the RH850 ABI.  This is the default."
+ msgstr ""
+ 
+-#: c-family/c.opt:1507
+-msgid ""
+-"Set the maximum number of template instantiation notes for a single warning "
+-"or error."
++#: config/v850/v850.opt:155
++msgid "Enable support for the old GCC ABI."
+ msgstr ""
+ 
+-#: c-family/c.opt:1514
+-msgid ""
+-"-ftemplate-depth=<number>\tSpecify maximum template instantiation depth."
++#: config/v850/v850.opt:159
++msgid "Support alignments of up to 64-bits."
+ msgstr ""
+ 
+-#: c-family/c.opt:1521
+-msgid ""
+-"-fno-threadsafe-statics\tDo not generate thread-safe code for initializing "
+-"local statics."
++#: config/m32r/m32r.opt:34
++msgid "Compile for the m32rx."
+ msgstr ""
+ 
+-#: c-family/c.opt:1525
+-msgid ""
+-"When \"signed\" or \"unsigned\" is not given make the bitfield unsigned."
++#: config/m32r/m32r.opt:38
++msgid "Compile for the m32r2."
+ msgstr ""
+ 
+-#: c-family/c.opt:1529
+-msgid "Make \"char\" unsigned by default."
++#: config/m32r/m32r.opt:42
++msgid "Compile for the m32r."
+ msgstr ""
+ 
+-#: c-family/c.opt:1533
+-msgid "Use __cxa_atexit to register destructors."
++#: config/m32r/m32r.opt:46
++msgid "Align all loops to 32 byte boundary."
+ msgstr ""
+ 
+-#: c-family/c.opt:1537
+-msgid "Use __cxa_get_exception_ptr in exception handling."
++#: config/m32r/m32r.opt:50
++msgid "Prefer branches over conditional execution."
+ msgstr ""
+ 
+-#: c-family/c.opt:1541
+-msgid "Marks all inlined functions and methods as having hidden visibility."
++#: config/m32r/m32r.opt:54
++msgid "Give branches their default cost."
+ msgstr ""
+ 
+-#: c-family/c.opt:1545
+-msgid "Changes visibility to match Microsoft Visual Studio by default."
++#: config/m32r/m32r.opt:58
++msgid "Display compile time statistics."
+ msgstr ""
+ 
+-#: c-family/c.opt:1557
+-msgid "Emit common-like symbols as weak symbols."
++#: config/m32r/m32r.opt:62
++msgid "Specify cache flush function."
+ msgstr ""
+ 
+-#: c-family/c.opt:1561
+-msgid ""
+-"-fwide-exec-charset=<cset>\tConvert all wide strings and character constants "
+-"to character set <cset>."
++#: config/m32r/m32r.opt:66
++msgid "Specify cache flush trap number."
+ msgstr ""
+ 
+-#: c-family/c.opt:1565
+-msgid "Generate a #line directive pointing at the current working directory."
++#: config/m32r/m32r.opt:70
++msgid "Only issue one instruction per cycle."
+ msgstr ""
+ 
+-#: c-family/c.opt:1573
+-msgid ""
+-"Generate lazy class lookup (via objc_getClass()) for use in Zero-Link mode."
++#: config/m32r/m32r.opt:74
++msgid "Allow two instructions to be issued per cycle."
+ msgstr ""
+ 
+-#: c-family/c.opt:1577
+-msgid "Dump declarations to a .decl file."
++#: config/m32r/m32r.opt:78
++msgid "Code size: small, medium or large."
+ msgstr ""
+ 
+-#: c-family/c.opt:1581
+-msgid ""
+-"-femit-struct-debug-baseonly\tAggressive reduced debug info for structs."
++#: config/m32r/m32r.opt:94
++msgid "Don't call any cache flush functions."
+ msgstr ""
+ 
+-#: c-family/c.opt:1585
+-msgid ""
+-"-femit-struct-debug-reduced\tConservative reduced debug info for structs."
++#: config/m32r/m32r.opt:98
++msgid "Don't call any cache flush trap."
+ msgstr ""
+ 
+-#: c-family/c.opt:1589
+-msgid ""
+-"-femit-struct-debug-detailed=<spec-list>\tDetailed reduced debug info for "
+-"structs."
++#: config/m32r/m32r.opt:105
++msgid "Small data area: none, sdata, use."
+ msgstr ""
+ 
+-#: c-family/c.opt:1593
+-msgid ""
+-"Interpret imaginary, fixed-point, or other gnu number suffix as the "
+-"corresponding"
++#: config/arm/arm.opt:26
++msgid "TLS dialect to use:"
+ msgstr ""
+ 
+-#: c-family/c.opt:1598
+-msgid "-idirafter <dir>\tAdd <dir> to the end of the system include path."
++#: config/arm/arm.opt:36
++msgid "Specify an ABI."
+ msgstr ""
+ 
+-#: c-family/c.opt:1602
+-msgid "-imacros <file>\tAccept definition of macros in <file>."
++#: config/arm/arm.opt:40
++msgid "Known ARM ABIs (for use with the -mabi= option):"
+ msgstr ""
+ 
+-#: c-family/c.opt:1606
+-msgid "-imultilib <dir>\tSet <dir> to be the multilib include subdirectory."
++#: config/arm/arm.opt:59
++msgid "Generate a call to abort if a noreturn function returns."
+ msgstr ""
+ 
+-#: c-family/c.opt:1610
+-msgid "-include <file>\tInclude the contents of <file> before other files."
++#: config/arm/arm.opt:66
++msgid "Pass FP arguments in FP registers."
+ msgstr ""
+ 
+-#: c-family/c.opt:1614
+-msgid "-iprefix <path>\tSpecify <path> as a prefix for next two options."
++#: config/arm/arm.opt:70
++msgid "Generate APCS conformant stack frames."
+ msgstr ""
+ 
+-#: c-family/c.opt:1618
+-msgid "-isysroot <dir>\tSet <dir> to be the system root directory."
++#: config/arm/arm.opt:74
++msgid "Generate re-entrant, PIC code."
+ msgstr ""
+ 
+-#: c-family/c.opt:1622
+-msgid "-isystem <dir>\tAdd <dir> to the start of the system include path."
++#: config/arm/arm.opt:90
++msgid "Generate code in 32 bit ARM state."
+ msgstr ""
+ 
+-#: c-family/c.opt:1626
+-msgid "-iquote <dir>\tAdd <dir> to the end of the quote include path."
++#: config/arm/arm.opt:98
++msgid "Thumb: Assume non-static functions may be called from ARM code."
+ msgstr ""
+ 
+-#: c-family/c.opt:1630
+-msgid "-iwithprefix <dir>\tAdd <dir> to the end of the system include path."
++#: config/arm/arm.opt:102
++msgid "Thumb: Assume function pointers may go to non-Thumb aware code."
+ msgstr ""
+ 
+-#: c-family/c.opt:1634
+-msgid ""
+-"-iwithprefixbefore <dir>\tAdd <dir> to the end of the main include path."
++#: config/arm/arm.opt:106 config/bfin/bfin.opt:44
++msgid "Specify the name of the target CPU."
+ msgstr ""
+ 
+-#: c-family/c.opt:1644
+-msgid ""
+-"Do not search standard system include directories (those specified with -"
+-"isystem will still be used)."
++#: config/arm/arm.opt:110
++msgid "Specify if floating point hardware should be used."
+ msgstr ""
+ 
+-#: c-family/c.opt:1648
+-msgid "Do not search standard system include directories for C++."
++#: config/arm/arm.opt:114
++msgid "Known floating-point ABIs (for use with the -mfloat-abi= option):"
+ msgstr ""
+ 
+-#: c-family/c.opt:1660
+-msgid "Generate C header of platform-specific features."
++#: config/arm/arm.opt:127
++msgid "Switch ARM/Thumb modes on alternating functions for compiler testing."
+ msgstr ""
+ 
+-#: c-family/c.opt:1664
+-msgid "Remap file names when including files."
++#: config/arm/arm.opt:131
++msgid "Specify the __fp16 floating-point format."
+ msgstr ""
+ 
+-#: c-family/c.opt:1668 c-family/c.opt:1672
+-msgid ""
+-"Conform to the ISO 1998 C++ standard revised by the 2003 technical "
+-"corrigendum."
++#: config/arm/arm.opt:135
++msgid "Known __fp16 formats (for use with the -mfp16-format= option):"
+ msgstr ""
+ 
+-#: c-family/c.opt:1676
+-msgid "Conform to the ISO 2011 C++ standard."
++#: config/arm/arm.opt:148
++msgid "Specify the name of the target floating point hardware/format."
+ msgstr ""
+ 
+-#: c-family/c.opt:1680
+-msgid "Deprecated in favor of -std=c++11."
++#: config/arm/arm.opt:159
++msgid "Generate call insns as indirect calls, if necessary."
+ msgstr ""
+ 
+-#: c-family/c.opt:1684
+-msgid "Deprecated in favor of -std=c++14."
++#: config/arm/arm.opt:163
++msgid "Assume data segments are relative to text segment."
+ msgstr ""
+ 
+-#: c-family/c.opt:1688
+-msgid "Conform to the ISO 2014 C++ standard."
++#: config/arm/arm.opt:167
++msgid "Specify the register to be used for PIC addressing."
+ msgstr ""
+ 
+-#: c-family/c.opt:1692
+-msgid ""
+-"Conform to the ISO 2017(?) C++ draft standard (experimental and incomplete "
+-"support)."
++#: config/arm/arm.opt:171
++msgid "Store function names in object code."
+ msgstr ""
+ 
+-#: c-family/c.opt:1699 c-family/c.opt:1796
+-msgid "Conform to the ISO 2011 C standard."
++#: config/arm/arm.opt:175
++msgid "Permit scheduling of a function's prologue sequence."
+ msgstr ""
+ 
+-#: c-family/c.opt:1703
+-msgid "Deprecated in favor of -std=c11."
++#: config/arm/arm.opt:179 config/rs6000/rs6000.opt:248
++msgid "Do not load the PIC register in function prologues."
+ msgstr ""
+ 
+-#: c-family/c.opt:1707 c-family/c.opt:1711 c-family/c.opt:1780
+-msgid "Conform to the ISO 1990 C standard."
++#: config/arm/arm.opt:186
++msgid "Specify the minimum bit alignment of structures."
+ msgstr ""
+ 
+-#: c-family/c.opt:1715 c-family/c.opt:1788
+-msgid "Conform to the ISO 1999 C standard."
++#: config/arm/arm.opt:190
++msgid "Generate code for Thumb state."
+ msgstr ""
+ 
+-#: c-family/c.opt:1719
+-msgid "Deprecated in favor of -std=c99."
++#: config/arm/arm.opt:194
++msgid "Support calls between Thumb and ARM instruction sets."
+ msgstr ""
+ 
+-#: c-family/c.opt:1723 c-family/c.opt:1728
+-msgid "Conform to the ISO 1998 C++ standard revised by the 2003 technical"
++#: config/arm/arm.opt:198
++msgid "Specify thread local storage scheme."
+ msgstr ""
+ 
+-#: c-family/c.opt:1733
+-msgid "Conform to the ISO 2011 C++ standard with GNU extensions."
++#: config/arm/arm.opt:202
++msgid "Specify how to access the thread pointer."
+ msgstr ""
+ 
+-#: c-family/c.opt:1737
+-msgid "Deprecated in favor of -std=gnu++11."
++#: config/arm/arm.opt:206
++msgid "Valid arguments to -mtp=:"
+ msgstr ""
+ 
+-#: c-family/c.opt:1741
+-msgid "Deprecated in favor of -std=gnu++14."
++#: config/arm/arm.opt:219
++msgid "Thumb: Generate (non-leaf) stack frames even if not needed."
+ msgstr ""
+ 
+-#: c-family/c.opt:1745
+-msgid "Conform to the ISO 2014 C++ standard with GNU extensions."
++#: config/arm/arm.opt:223
++msgid "Thumb: Generate (leaf) stack frames even if not needed."
+ msgstr ""
+ 
+-#: c-family/c.opt:1749
++#: config/arm/arm.opt:231
+ msgid ""
+-"Conform to the ISO 201z(7?) C++ draft standard with GNU extensions "
+-"(experimental and incomplete support)."
++"Print CPU tuning information as comment in assembler file.  This is an "
++"option used only for regression testing of the compiler and not intended for "
++"ordinary use in compiling code."
+ msgstr ""
+ 
+-#: c-family/c.opt:1756
+-msgid "Conform to the ISO 2011 C standard with GNU extensions."
++#: config/arm/arm.opt:242
++msgid ""
++"Use Neon quad-word (rather than double-word) registers for vectorization."
+ msgstr ""
+ 
+-#: c-family/c.opt:1760
+-msgid "Deprecated in favor of -std=gnu11."
++#: config/arm/arm.opt:246
++msgid ""
++"Use Neon double-word (rather than quad-word) registers for vectorization."
+ msgstr ""
+ 
+-#: c-family/c.opt:1764 c-family/c.opt:1768
+-msgid "Conform to the ISO 1990 C standard with GNU extensions."
++#: config/arm/arm.opt:250
++msgid "Only generate absolute relocations on word sized values."
+ msgstr ""
+ 
+-#: c-family/c.opt:1772
+-msgid "Conform to the ISO 1999 C standard with GNU extensions."
++#: config/arm/arm.opt:254
++msgid "Generate IT blocks appropriate for ARMv8."
+ msgstr ""
+ 
+-#: c-family/c.opt:1776
+-msgid "Deprecated in favor of -std=gnu99."
++#: config/arm/arm.opt:258
++msgid "Use the old RTX costing tables (transitional)."
+ msgstr ""
+ 
+-#: c-family/c.opt:1784
+-msgid "Conform to the ISO 1990 C standard as amended in 1994."
++#: config/arm/arm.opt:262
++msgid ""
++"Use the new generic RTX cost tables if new core-specific cost table not "
++"available (transitional)."
+ msgstr ""
+ 
+-#: c-family/c.opt:1792
+-msgid "Deprecated in favor of -std=iso9899:1999."
++#: config/arm/arm.opt:266
++msgid ""
++"Avoid overlapping destination and address registers on LDRD instructions "
++"that may trigger Cortex-M3 errata."
+ msgstr ""
+ 
+-#: c-family/c.opt:1803
+-msgid "Enable traditional preprocessing."
++#: config/arm/arm.opt:271
++msgid "Enable unaligned word and halfword accesses to packed data."
+ msgstr ""
+ 
+-#: c-family/c.opt:1807
+-msgid "-trigraphs\tSupport ISO C trigraphs."
++#: config/arm/arm.opt:275
++msgid "Use Neon to perform 64-bits operations rather than core registers."
+ msgstr ""
+ 
+-#: c-family/c.opt:1811
+-msgid "Do not predefine system-specific and GCC-specific macros."
++#: config/arm/arm.opt:279
++msgid "Assume loading data from flash is slower than fetching instructions."
+ msgstr ""
+ 
+-#: ada/gcc-interface/lang.opt:61
+-msgid "Synonym of -gnatk8."
++#: config/arm/arm.opt:283
++msgid "Assume unified syntax for inline assembly code."
+ msgstr ""
+ 
+-#: ada/gcc-interface/lang.opt:69
+-msgid "Do not look for object files in standard path."
++#: config/arm/arm-tables.opt:25
++msgid "Known ARM CPUs (for use with the -mcpu= and -mtune= options):"
+ msgstr ""
+ 
+-#: ada/gcc-interface/lang.opt:73
+-msgid "Select the runtime."
++#: config/arm/arm-tables.opt:341
++msgid "Known ARM architectures (for use with the -march= option):"
+ msgstr ""
+ 
+-#: ada/gcc-interface/lang.opt:85
+-msgid "Catch typos."
++#: config/arm/arm-tables.opt:438
++msgid "Known ARM FPUs (for use with the -mfpu= option):"
+ msgstr ""
+ 
+-#: ada/gcc-interface/lang.opt:89
+-msgid "Set name of output ALI file (internal switch)."
++#: config/tilepro/tilepro.opt:23
++msgid ""
++"Compile with 32 bit longs and pointers, which is the only supported behavior "
++"and thus the flag is ignored."
+ msgstr ""
+ 
+-#: ada/gcc-interface/lang.opt:93
+-msgid "-gnat<options>\tSpecify options to GNAT."
++#: config/tilepro/tilepro.opt:28 config/tilegx/tilegx.opt:26
++msgid "-mcpu=CPU\tUse features of and schedule code for given CPU."
+ msgstr ""
+ 
+-#: ada/gcc-interface/lang.opt:97
+-msgid "Ignored."
++#: config/tilepro/tilepro.opt:32
++msgid "Known TILEPro CPUs (for use with the -mcpu= option):"
+ msgstr ""
+ 
+-#: go/lang.opt:42
+-msgid "Add explicit checks for division by zero."
++#: config/sol2.opt:32
++msgid "Clear hardware capabilities when linking."
+ msgstr ""
+ 
+-#: go/lang.opt:46
+-msgid "Add explicit checks for division overflow in INT_MIN / -1."
++#: config/sol2.opt:36
++msgid "Pass -z text to linker."
+ msgstr ""
+ 
+-#: go/lang.opt:50
+-msgid "-fgo-dump-<type>\tDump Go frontend internal information."
+-msgstr ""
+-
+-#: go/lang.opt:54
+-msgid "-fgo-optimize-<type>\tTurn on optimization passes in the frontend."
+-msgstr ""
+-
+-#: go/lang.opt:58
+-msgid "-fgo-pkgpath=<string>\tSet Go package path."
+-msgstr ""
+-
+-#: go/lang.opt:62
+-msgid ""
+-"-fgo-prefix=<string>\tSet package-specific prefix for exported Go names."
+-msgstr ""
+-
+-#: go/lang.opt:66
+-msgid ""
+-"-fgo-relative-import-path=<path> Treat a relative import as relative to path."
+-msgstr ""
+-
+-#: go/lang.opt:70
+-msgid "Functions which return values must end with return statements."
+-msgstr ""
+-
+ #: config/vms/vms.opt:27
+ msgid "Malloc data into P2 space."
+ msgstr ""
+@@ -7867,1157 +7657,600 @@
+ msgid "unknown pointer size model %qs"
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:23
+-msgid "Generate code for the M*Core M210"
++#: config/avr/avr.opt:23
++msgid "Use subroutines for function prologues and epilogues."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:27
+-msgid "Generate code for the M*Core M340"
++#: config/avr/avr.opt:26
++#, c-format
++msgid "missing device or architecture after %qs"
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:31
+-msgid "Force functions to be aligned to a 4 byte boundary."
++#: config/avr/avr.opt:27
++msgid "-mmcu=MCU\tSelect the target MCU."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:35 config/moxie/moxie.opt:23
+-msgid "Generate big-endian code."
++#: config/avr/avr.opt:31
++msgid "Set the number of 64 KiB flash segments."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:39
+-msgid "Emit call graph information."
++#: config/avr/avr.opt:35
++msgid "Indicate presence of a processor erratum."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:43
+-msgid "Use the divide instruction."
++#: config/avr/avr.opt:39
++msgid "Enable Read-Modify-Write (RMW) instructions support/use."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:47
+-msgid "Inline constants if it can be done in 2 insns or less."
++#: config/avr/avr.opt:49
++msgid "Use an 8-bit 'int' type."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:51 config/moxie/moxie.opt:27
+-msgid "Generate little-endian code."
++#: config/avr/avr.opt:53
++msgid "Change the stack pointer without disabling interrupts."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:56 config/fr30/fr30.opt:27
++#: config/avr/avr.opt:57
+ msgid ""
+-"Assume that run-time support has been provided, so omit -lsim from the "
+-"linker command line."
++"Set the branch costs for conditional branch instructions.  Reasonable values "
++"are small, non-negative integers.  The default branch cost is 0."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:60
+-msgid "Use arbitrary sized immediates in bit operations."
++#: config/avr/avr.opt:67
++msgid "Change only the low 8 bits of the stack pointer."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:64
+-msgid "Prefer word accesses over byte accesses."
++#: config/avr/avr.opt:71
++msgid "Relax branches."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:71
+-msgid "Set the maximum amount for a single stack increment operation."
++#: config/avr/avr.opt:75
++msgid ""
++"Make the linker relaxation machine assume that a program counter wrap-around "
++"occurs."
+ msgstr ""
+ 
+-#: config/mcore/mcore.opt:75
+-msgid "Always treat bitfields as int-sized."
++#: config/avr/avr.opt:79
++msgid ""
++"Accumulate outgoing function arguments and acquire/release the needed stack "
++"space for outpoing function arguments in function prologue/epilogue.  "
++"Without this option, outgoing arguments are pushed before calling a function "
++"and popped afterwards.  This option can lead to reduced code size for "
++"functions that call many functions that get their arguments on the stack "
++"like, for example printf."
+ msgstr ""
+ 
+-#: config/linux-android.opt:23
+-msgid "Generate code for the Android platform."
++#: config/avr/avr.opt:83
++msgid ""
++"When accessing RAM, use X as imposed by the hardware, i.e. just use pre-"
++"decrement, post-increment and indirect addressing with the X register.  "
++"Without this option, the compiler may assume that there is an addressing "
++"mode X+const similar to Y+const and Z+const and emit instructions to emulate "
++"such an addressing mode for X."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:24
+-msgid "For intrinsics library: pass all parameters in registers."
++#: config/avr/avr.opt:88
++msgid ""
++"The device has no SPH special function register. This option will be "
++"overridden by the compiler driver with the correct setting if presence/"
++"absence of SPH can be deduced from -mmcu=MCU."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:28
+-msgid "Use register stack for parameters and return value."
++#: config/avr/avr.opt:92
++msgid "Warn if the address space of an address is changed."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:32
+-msgid "Use call-clobbered registers for parameters and return value."
+-msgstr ""
+-
+-#: config/mmix/mmix.opt:37
+-msgid "Use epsilon-respecting floating point compare instructions."
+-msgstr ""
+-
+-#: config/mmix/mmix.opt:41
+-msgid "Use zero-extending memory loads, not sign-extending ones."
+-msgstr ""
+-
+-#: config/mmix/mmix.opt:45
++#: config/avr/avr.opt:96
+ msgid ""
+-"Generate divide results with reminder having the same sign as the divisor "
+-"(not the dividend)."
++"Allow to use truncation instead of rounding towards 0 for fractional int "
++"types."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:49
+-msgid "Prepend global symbols with \":\" (for use with PREFIX)."
++#: config/avr/avr.opt:100
++msgid "Do not link against the device-specific library lib<MCU>.a."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:53
+-msgid "Do not provide a default start-address 0x100 of the program."
++#: config/s390/tpf.opt:23
++msgid "Enable TPF-OS tracing code."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:57
+-msgid "Link to emit program in ELF format (rather than mmo)."
++#: config/s390/tpf.opt:27
++msgid "Specify main object for TPF-OS."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:61
+-msgid "Use P-mnemonics for branches statically predicted as taken."
++#: config/s390/s390.opt:48
++msgid "31 bit ABI."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:65
+-msgid "Don't use P-mnemonics for branches."
++#: config/s390/s390.opt:52
++msgid "64 bit ABI."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:79
+-msgid "Use addresses that allocate global registers."
++#: config/s390/s390.opt:96
++msgid "Maintain backchain pointer."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:83
+-msgid "Do not use addresses that allocate global registers."
++#: config/s390/s390.opt:100
++msgid "Additional debug prints."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:87
+-msgid "Generate a single exit point for each function."
++#: config/s390/s390.opt:104
++msgid "ESA/390 architecture."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:91
+-msgid "Do not generate a single exit point for each function."
++#: config/s390/s390.opt:108
++msgid "Enable decimal floating point hardware support."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:95
+-msgid "Set start-address of the program."
++#: config/s390/s390.opt:112
++msgid "Enable hardware floating point."
+ msgstr ""
+ 
+-#: config/mmix/mmix.opt:99
+-msgid "Set start-address of data."
+-msgstr ""
+-
+-#: config/darwin.opt:114
+-msgid "Generate compile-time CFString objects."
+-msgstr ""
+-
+-#: config/darwin.opt:211
+-msgid "Warn if constant CFString objects contain non-portable characters."
+-msgstr ""
+-
+-#: config/darwin.opt:216
+-msgid "Generate AT&T-style stubs for Mach-O."
+-msgstr ""
+-
+-#: config/darwin.opt:220
+-msgid "Generate code suitable for executables (NOT shared libs)."
+-msgstr ""
+-
+-#: config/darwin.opt:224
+-msgid "Generate code suitable for fast turn around debugging."
+-msgstr ""
+-
+-#: config/darwin.opt:232
+-msgid "The earliest MacOS X version on which this program will run."
+-msgstr ""
+-
+-#: config/darwin.opt:236
+-msgid "Set sizeof(bool) to 1."
+-msgstr ""
+-
+-#: config/darwin.opt:240
+-msgid "Generate code for darwin loadable kernel extensions."
+-msgstr ""
+-
+-#: config/darwin.opt:244
+-msgid "Generate code for the kernel or loadable kernel extensions."
+-msgstr ""
+-
+-#: config/darwin.opt:248
++#: config/s390/s390.opt:116
+ msgid ""
+-"-iframework <dir>\tAdd <dir> to the end of the system framework include path."
++"Takes two non-negative integer numbers separated by a comma. Prepend the "
++"function label with the number of two-byte Nop instructions indicated by the "
++"first.  Append Nop instructions covering the number of halfwords indicated "
++"by the second after the label.  Nop instructions of the largest possible "
++"size are used (six, four or two bytes), beginning with the largest possible "
++"size.  Using 0 for both values disables hotpatching."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:40 config/msp430/msp430.opt:3 config/c6x/c6x.opt:38
+-#: config/mep/mep.opt:143
+-msgid "Use simulator runtime."
++#: config/s390/s390.opt:134
++msgid "Use hardware transactional execution instructions."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:44 config/arm/arm.opt:106
+-msgid "Specify the name of the target CPU."
++#: config/s390/s390.opt:138
++msgid "Use hardware vector facility instructions and enable the vector ABI."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:48
+-msgid "Omit frame pointer for leaf functions."
++#: config/s390/s390.opt:142
++msgid "Use packed stack layout."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:52
+-msgid "Program is entirely located in low 64k of memory."
++#: config/s390/s390.opt:146
++msgid "Use bras for executable < 64k."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:56
+-msgid "Work around a hardware anomaly by adding a number of NOPs before a"
++#: config/s390/s390.opt:150
++msgid "Disable hardware floating point."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:61
+-msgid "Avoid speculative loads to work around a hardware anomaly."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:65
+-msgid "Enabled ID based shared library."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:69
++#: config/s390/s390.opt:154
+ msgid ""
+-"Generate code that won't be linked against any other ID shared libraries,"
++"Set the max. number of bytes which has to be left to stack size before a "
++"trap instruction is triggered."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:74 config/m68k/m68k.opt:171
+-msgid "ID of shared library to build."
++#: config/s390/s390.opt:158
++msgid "Switches off the -mstack-guard= option."
+ msgstr ""
+ 
+-#: config/bfin/bfin.opt:78 config/m68k/m68k.opt:167
+-msgid "Enable separate data segment."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:82 config/c6x/c6x.opt:63
+-msgid "Avoid generating pc-relative calls; use indirection."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:86
+-msgid "Link with the fast floating-point library."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:90 config/frv/frv.opt:130
+-msgid "Enable Function Descriptor PIC mode."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:94 config/frv/frv.opt:162
+-msgid "Enable inlining of PLT in function calls."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:98
+-msgid "Do stack checking using bounds in L1 scratch memory."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:102
+-msgid "Enable multicore support."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:106
+-msgid "Build for Core A."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:110
+-msgid "Build for Core B."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:114
+-msgid "Build for SDRAM."
+-msgstr ""
+-
+-#: config/bfin/bfin.opt:118
+-msgid "Assume ICPLBs are enabled at runtime."
+-msgstr ""
+-
+-#: config/m68k/m68k-tables.opt:25
+-msgid "Known M68K CPUs (for use with the -mcpu= option):"
+-msgstr ""
+-
+-#: config/m68k/m68k-tables.opt:365
+-msgid "Known M68K microarchitectures (for use with the -mtune= option):"
+-msgstr ""
+-
+-#: config/m68k/m68k-tables.opt:411
+-msgid "Known M68K ISAs (for use with the -march= option):"
+-msgstr ""
+-
+-#: config/m68k/ieee.opt:24 config/i386/i386.opt:358
+-msgid "Use IEEE math for fp comparisons."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:30
+-msgid "Generate code for a 520X."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:34
+-msgid "Generate code for a 5206e."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:38
+-msgid "Generate code for a 528x."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:42
+-msgid "Generate code for a 5307."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:46
+-msgid "Generate code for a 5407."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:50 config/m68k/m68k.opt:111
+-msgid "Generate code for a 68000."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:54
+-msgid "Generate code for a 68010."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:58 config/m68k/m68k.opt:115
+-msgid "Generate code for a 68020."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:62
+-msgid "Generate code for a 68040, without any new instructions."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:66
+-msgid "Generate code for a 68060, without any new instructions."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:70
+-msgid "Generate code for a 68030."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:74
+-msgid "Generate code for a 68040."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:78
+-msgid "Generate code for a 68060."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:82
+-msgid "Generate code for a 68302."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:86
+-msgid "Generate code for a 68332."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:91
+-msgid "Generate code for a 68851."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:95
+-msgid "Generate code that uses 68881 floating-point instructions."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:99
+-msgid "Align variables on a 32-bit boundary."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:103 config/arm/arm.opt:81 config/nios2/nios2.opt:570
+-#: config/nds32/nds32.opt:66 config/c6x/c6x.opt:67
+-msgid "Specify the name of the target architecture."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:107
+-msgid "Use the bit-field instructions."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:119
+-msgid "Generate code for a ColdFire v4e."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:123
+-msgid "Specify the target CPU."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:127
+-msgid "Generate code for a cpu32."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:131
+-msgid "Use hardware division instructions on ColdFire."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:135
+-msgid "Generate code for a Fido A."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:139
+-msgid "Generate code which uses hardware floating point instructions."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:143
+-msgid "Enable ID based shared library."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:147
+-msgid "Do not use the bit-field instructions."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:151
+-msgid "Use normal calling convention."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:155
+-msgid "Consider type 'int' to be 32 bits wide."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:159
+-msgid "Generate pc-relative code."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:163
+-msgid "Use different calling convention using 'rtd'."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:175
+-msgid "Consider type 'int' to be 16 bits wide."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:179
+-msgid "Generate code with library calls for floating point."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:183
+-msgid "Do not use unaligned memory references."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:187
+-msgid "Tune for the specified target CPU or architecture."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:191
+-msgid "Support more than 8192 GOT entries on ColdFire."
+-msgstr ""
+-
+-#: config/m68k/m68k.opt:195
+-msgid "Support TLS segment larger than 64K."
+-msgstr ""
+-
+-#: config/m32c/m32c.opt:23
+-msgid "-msim\tUse simulator runtime."
+-msgstr ""
+-
+-#: config/m32c/m32c.opt:27
+-msgid "-mcpu=r8c\tCompile code for R8C variants."
+-msgstr ""
+-
+-#: config/m32c/m32c.opt:31
+-msgid "-mcpu=m16c\tCompile code for M16C variants."
+-msgstr ""
+-
+-#: config/m32c/m32c.opt:35
+-msgid "-mcpu=m32cm\tCompile code for M32CM variants."
+-msgstr ""
+-
+-#: config/m32c/m32c.opt:39
+-msgid "-mcpu=m32c\tCompile code for M32C variants."
+-msgstr ""
+-
+-#: config/m32c/m32c.opt:43
+-msgid "-memregs=\tNumber of memreg bytes (default: 16, range: 0..16)."
+-msgstr ""
+-
+-#: config/msp430/msp430.opt:7
+-msgid "Force assembly output to always use hex constants."
+-msgstr ""
+-
+-#: config/msp430/msp430.opt:11
+-msgid "Specify the MCU to build for."
+-msgstr ""
+-
+-#: config/msp430/msp430.opt:15
++#: config/s390/s390.opt:162
+ msgid ""
+-"Warn if an MCU name is unrecognised or conflicts with other options "
+-"(default: on)."
++"Emit extra code in the function prologue in order to trap if the stack size "
++"exceeds the given limit."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:19
+-msgid "Specify the ISA to build for: msp430, msp430x, msp430xv2."
++#: config/s390/s390.opt:166
++msgid "Switches off the -mstack-size= option."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:23
+-msgid "Select large model - 20-bit addresses/pointers."
++#: config/s390/s390.opt:174
++msgid "Use the mvcle instruction for block moves."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:27
+-msgid "Select small model - 16-bit addresses/pointers (default)."
+-msgstr ""
+-
+-#: config/msp430/msp430.opt:31
+-msgid "Optimize opcode sizes at link time."
+-msgstr ""
+-
+-#: config/msp430/msp430.opt:38
++#: config/s390/s390.opt:178
+ msgid ""
+-"Use a minimum runtime (no static initializers or ctors) for memory-"
+-"constrained devices."
++"Enable the z vector language extension providing the context-sensitive "
++"vector macro and enable the Altivec-style builtins in vecintrin.h."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:45
+-msgid "Specify the type of hardware multiply to support."
++#: config/s390/s390.opt:183
++msgid "Warn if a function uses alloca or creates an array with dynamic size."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:67
+-msgid "Specify whether functions should be placed into low or high memory."
++#: config/s390/s390.opt:187
++msgid "Warn if a single function's framesize exceeds the given framesize."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:71
+-msgid "Specify whether variables should be placed into low or high memory."
++#: config/s390/s390.opt:191
++msgid "z/Architecture."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:90
++#: config/s390/s390.opt:195
+ msgid ""
+-"Passes on a request to the assembler to enable fixes for various silicon "
+-"errata."
++"Set the branch costs for conditional branch instructions.  Reasonable values "
++"are small, non-negative integers.  The default branch cost is 1."
+ msgstr ""
+ 
+-#: config/msp430/msp430.opt:94
+-msgid ""
+-"Passes on a request to the assembler to warn about various silicon errata."
++#: config/darwin.opt:56 common.opt:336 common.opt:339 common.opt:2813
++#: c-family/c.opt:70 c-family/c.opt:73 c-family/c.opt:76 c-family/c.opt:79
++#: c-family/c.opt:175 c-family/c.opt:178 c-family/c.opt:216 c-family/c.opt:220
++#: c-family/c.opt:232 c-family/c.opt:1601 c-family/c.opt:1609
++#, c-format
++msgid "missing filename after %qs"
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:40
+-msgid "The possible TLS dialects:"
++#: config/darwin.opt:117
++msgid "Generate compile-time CFString objects."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:52
+-msgid "The code model option names for -mcmodel:"
++#: config/darwin.opt:214
++msgid "Warn if constant CFString objects contain non-portable characters."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:65 config/arm/arm.opt:94
+-#: config/microblaze/microblaze.opt:60
+-msgid "Assume target CPU is configured as big endian."
++#: config/darwin.opt:219
++msgid "Generate AT&T-style stubs for Mach-O."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:69
+-msgid "Generate code which uses only the general registers."
++#: config/darwin.opt:223
++msgid "Generate code suitable for executables (NOT shared libs)."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:73
+-msgid "Workaround for ARM Cortex-A53 Erratum number 835769."
++#: config/darwin.opt:227
++msgid "Generate code suitable for fast turn around debugging."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:77
+-msgid "Workaround for ARM Cortex-A53 Erratum number 843419."
++#: config/darwin.opt:235
++msgid "The earliest MacOS X version on which this program will run."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:81 config/arm/arm.opt:155
+-#: config/microblaze/microblaze.opt:64
+-msgid "Assume target CPU is configured as little endian."
++#: config/darwin.opt:239
++msgid "Set sizeof(bool) to 1."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:85
+-msgid "Specify the code model."
++#: config/darwin.opt:243
++msgid "Generate code for darwin loadable kernel extensions."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:89
+-msgid "Don't assume that unaligned accesses are handled by the system."
++#: config/darwin.opt:247
++msgid "Generate code for the kernel or loadable kernel extensions."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:93 config/i386/i386.opt:390
+-msgid "Omit the frame pointer in leaf functions."
+-msgstr ""
+-
+-#: config/aarch64/aarch64.opt:97
+-msgid "Specify TLS dialect."
+-msgstr ""
+-
+-#: config/aarch64/aarch64.opt:101
++#: config/darwin.opt:251
+ msgid ""
+-"Specifies bit size of immediate TLS offsets.  Valid values are 12, 24, 32, "
+-"48."
++"-iframework <dir>\tAdd <dir> to the end of the system framework include path."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:120
+-msgid "-march=ARCH\tUse features of architecture ARCH."
++#: config/darwin.opt:401
++msgid "The version of ld64 in use for this toolchain."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:124
+-msgid "-mcpu=CPU\tUse features of and optimize for CPU."
++#: config/sh/superh.opt:6
++msgid "Board name [and memory region]."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:128
+-msgid "-mtune=CPU\tOptimize for CPU."
++#: config/sh/superh.opt:10
++msgid "Runtime name."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:132
+-msgid "-mabi=ABI\tGenerate code that conforms to the specified ABI."
++#: config/sh/sh.opt:48
++msgid "Generate SH1 code."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:136
+-msgid ""
+-"-moverride=STRING\tPower users only! Override CPU optimization parameters."
++#: config/sh/sh.opt:52
++msgid "Generate SH2 code."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:140
+-msgid "Known AArch64 ABIs (for use with the -mabi= option):"
++#: config/sh/sh.opt:56
++msgid "Generate default double-precision SH2a-FPU code."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:150
+-msgid "PC relative literal loads."
++#: config/sh/sh.opt:60
++msgid "Generate SH2a FPU-less code."
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.opt:154
+-msgid "When calculating the reciprocal square root approximation,"
++#: config/sh/sh.opt:64
++msgid "Generate default single-precision SH2a-FPU code."
+ msgstr ""
+ 
+-#: config/linux.opt:24
+-msgid "Use Bionic C library."
++#: config/sh/sh.opt:68
++msgid "Generate only single-precision SH2a-FPU code."
+ msgstr ""
+ 
+-#: config/linux.opt:28
+-msgid "Use GNU C library."
++#: config/sh/sh.opt:72
++msgid "Generate SH2e code."
+ msgstr ""
+ 
+-#: config/linux.opt:32
+-msgid "Use uClibc C library."
++#: config/sh/sh.opt:76
++msgid "Generate SH3 code."
+ msgstr ""
+ 
+-#: config/linux.opt:36
+-msgid "Use musl C library."
++#: config/sh/sh.opt:80
++msgid "Generate SH3e code."
+ msgstr ""
+ 
+-#: config/ia64/ilp32.opt:3
+-msgid "Generate ILP32 code."
++#: config/sh/sh.opt:84
++msgid "Generate SH4 code."
+ msgstr ""
+ 
+-#: config/ia64/ilp32.opt:7
+-msgid "Generate LP64 code."
++#: config/sh/sh.opt:88
++msgid "Generate SH4-100 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:28
+-msgid "Generate big endian code."
++#: config/sh/sh.opt:92
++msgid "Generate SH4-200 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:32
+-msgid "Generate little endian code."
++#: config/sh/sh.opt:98
++msgid "Generate SH4-300 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:36
+-msgid "Generate code for GNU as."
++#: config/sh/sh.opt:102
++msgid "Generate SH4 FPU-less code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:40
+-msgid "Generate code for GNU ld."
++#: config/sh/sh.opt:106
++msgid "Generate SH4-100 FPU-less code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:44
+-msgid "Emit stop bits before and after volatile extended asms."
++#: config/sh/sh.opt:110
++msgid "Generate SH4-200 FPU-less code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:48
+-msgid "Use in/loc/out register names."
++#: config/sh/sh.opt:114
++msgid "Generate SH4-300 FPU-less code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:55
+-msgid "Enable use of sdata/scommon/sbss."
++#: config/sh/sh.opt:118
++msgid "Generate code for SH4 340 series (MMU/FPU-less)."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:59
+-msgid "Generate code without GP reg."
++#: config/sh/sh.opt:123
++msgid "Generate code for SH4 400 series (MMU/FPU-less)."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:63
+-msgid "gp is constant (but save/restore gp on indirect calls)."
++#: config/sh/sh.opt:128
++msgid "Generate code for SH4 500 series (FPU-less)."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:67
+-msgid "Generate self-relocatable code."
++#: config/sh/sh.opt:133
++msgid "Generate default single-precision SH4 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:71
+-msgid "Generate inline floating point division, optimize for latency."
++#: config/sh/sh.opt:137
++msgid "Generate default single-precision SH4-100 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:75
+-msgid "Generate inline floating point division, optimize for throughput."
++#: config/sh/sh.opt:141
++msgid "Generate default single-precision SH4-200 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:82
+-msgid "Generate inline integer division, optimize for latency."
++#: config/sh/sh.opt:145
++msgid "Generate default single-precision SH4-300 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:86
+-msgid "Generate inline integer division, optimize for throughput."
++#: config/sh/sh.opt:149
++msgid "Generate only single-precision SH4 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:90
+-msgid "Do not inline integer division."
++#: config/sh/sh.opt:153
++msgid "Generate only single-precision SH4-100 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:94
+-msgid "Generate inline square root, optimize for latency."
++#: config/sh/sh.opt:157
++msgid "Generate only single-precision SH4-200 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:98
+-msgid "Generate inline square root, optimize for throughput."
++#: config/sh/sh.opt:161
++msgid "Generate only single-precision SH4-300 code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:102
+-msgid "Do not inline square root."
++#: config/sh/sh.opt:165
++msgid "Generate SH4a code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:106
+-msgid "Enable DWARF line debug info via GNU as."
++#: config/sh/sh.opt:169
++msgid "Generate SH4a FPU-less code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:110
+-msgid "Enable earlier placing stop bits for better scheduling."
++#: config/sh/sh.opt:173
++msgid "Generate default single-precision SH4a code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:114 config/spu/spu.opt:72 config/pa/pa.opt:58
+-#: config/sh/sh.opt:273
+-msgid "Specify range of registers to make fixed."
++#: config/sh/sh.opt:177
++msgid "Generate only single-precision SH4a code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:118 config/rs6000/sysv4.opt:32
+-#: config/alpha/alpha.opt:130
+-msgid "Specify bit size of immediate TLS offsets."
++#: config/sh/sh.opt:181
++msgid "Generate SH4al-dsp code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:122 config/spu/spu.opt:84 config/i386/i386.opt:504
+-#: config/s390/s390.opt:170 config/sparc/sparc.opt:130
+-#: config/visium/visium.opt:49
+-msgid "Schedule code for given CPU."
++#: config/sh/sh.opt:185
++msgid "Generate 32-bit SHmedia code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:126
+-msgid "Known Itanium CPUs (for use with the -mtune= option):"
++#: config/sh/sh.opt:189
++msgid "Generate 32-bit FPU-less SHmedia code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:136
+-msgid "Use data speculation before reload."
++#: config/sh/sh.opt:193
++msgid "Generate 64-bit SHmedia code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:140
+-msgid "Use data speculation after reload."
++#: config/sh/sh.opt:197
++msgid "Generate 64-bit FPU-less SHmedia code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:144
+-msgid "Use control speculation."
++#: config/sh/sh.opt:201
++msgid "Generate SHcompact code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:148
+-msgid "Use in block data speculation before reload."
++#: config/sh/sh.opt:205
++msgid "Generate FPU-less SHcompact code."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:152
+-msgid "Use in block data speculation after reload."
++#: config/sh/sh.opt:209 config/i386/i386.opt:206
++msgid "Reserve space for outgoing arguments in the function prologue."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:156
+-msgid "Use in block control speculation."
++#: config/sh/sh.opt:213 config/pa/pa.opt:42 config/pa/pa.opt:66 common.opt:1074
++#: common.opt:1301 common.opt:1653 common.opt:1999 common.opt:2035
++#: common.opt:2124 common.opt:2128 common.opt:2224 common.opt:2306
++#: common.opt:2314 common.opt:2322 common.opt:2330 common.opt:2431
++#: common.opt:2558 c-family/c.opt:1155 c-family/c.opt:1179 c-family/c.opt:1409
++#: fortran/lang.opt:699
++msgid "Does nothing.  Preserved for backward compatibility."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:160
+-msgid "Use simple data speculation check."
++#: config/sh/sh.opt:217
++msgid "Generate code in big endian mode."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:164
+-msgid "Use simple data speculation check for control speculation."
++#: config/sh/sh.opt:221
++msgid "Generate 32-bit offsets in switch tables."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:174
+-msgid ""
+-"Count speculative dependencies while calculating priority of instructions."
++#: config/sh/sh.opt:225
++msgid "Generate bit instructions."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:178
+-msgid "Place a stop bit after every cycle when scheduling."
++#: config/sh/sh.opt:229
++msgid "Cost to assume for a branch insn."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:182
+-msgid ""
+-"Assume that floating-point stores and loads are not likely to cause conflict "
+-"when placed into one instruction group."
++#: config/sh/sh.opt:233
++msgid "Assume that zero displacement conditional branches are fast."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:186
+-msgid ""
+-"Soft limit on number of memory insns per instruction group, giving lower "
+-"priority to subsequent memory insns attempting to schedule in the same insn "
+-"group. Frequently useful to prevent cache bank conflicts.  Default value is "
+-"1."
++#: config/sh/sh.opt:236 config/sh/sh.opt:240
++#, c-format
++msgid "%qs is deprecated and has no effect"
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:190
+-msgid ""
+-"Disallow more than 'msched-max-memory-insns' in instruction group. "
+-"Otherwise, limit is 'soft' (prefer non-memory operations when limit is "
+-"reached)."
++#: config/sh/sh.opt:237
++msgid "Enable cbranchdi4 pattern."
+ msgstr ""
+ 
+-#: config/ia64/ia64.opt:194
+-msgid "Don't generate checks for control speculation in selective scheduling."
++#: config/sh/sh.opt:241
++msgid "Emit cmpeqdi_t pattern even when -mcbranchdi is in effect."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:20
+-msgid "Emit warnings when run-time relocations are generated."
++#: config/sh/sh.opt:245
++msgid "Force the usage of delay slots for conditional branches."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:24
+-msgid "Emit errors when run-time relocations are generated."
++#: config/sh/sh.opt:249
++msgid "Enable SH5 cut2 workaround."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:28
+-msgid "Specify cost of branches (Default 20)."
++#: config/sh/sh.opt:253
++msgid "Align doubles at 64-bit boundaries."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:32
+-msgid "Make sure loads and stores are not moved past DMA instructions."
+-msgstr ""
+-
+-#: config/spu/spu.opt:36
+-msgid "volatile must be specified on any memory that is effected by DMA."
+-msgstr ""
+-
+-#: config/spu/spu.opt:40 config/spu/spu.opt:44
++#: config/sh/sh.opt:257
+ msgid ""
+-"Insert nops when it might improve performance by allowing dual issue "
+-"(default)."
++"Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, "
++"inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:48
+-msgid "Use standard main function as entry for startup."
++#: config/sh/sh.opt:261
++msgid "Specify name for 32 bit signed division function."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:52
+-msgid "Generate branch hints for branches."
++#: config/sh/sh.opt:265
++msgid "Generate ELF FDPIC code."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:56
+-msgid "Maximum number of nops to insert for a hint (Default 2)."
+-msgstr ""
+-
+-#: config/spu/spu.opt:60
++#: config/sh/sh.opt:269
+ msgid ""
+-"Approximate maximum number of instructions to allow between a hint and its "
+-"branch [125]."
++"Enable the use of 64-bit floating point registers in fmov instructions.  See "
++"-mdalign if 64-bit alignment is required."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:64
+-msgid "Generate code for 18 bit addressing."
++#: config/sh/sh.opt:277
++msgid "Cost to assume for gettr insn."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:68
+-msgid "Generate code for 32 bit addressing."
++#: config/sh/sh.opt:281 config/sh/sh.opt:331
++msgid "Follow Renesas (formerly Hitachi) / SuperH calling conventions."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:76
+-msgid ""
+-"Insert hbrp instructions after hinted branch targets to avoid the SPU hang "
+-"issue."
++#: config/sh/sh.opt:285
++msgid "Increase the IEEE compliance for floating-point comparisons."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:80 config/i386/i386.opt:247 config/s390/s390.opt:56
+-msgid "Generate code for given CPU."
++#: config/sh/sh.opt:289
++msgid "Enable the use of the indexed addressing mode for SHmedia32/SHcompact."
+ msgstr ""
+ 
+-#: config/spu/spu.opt:88
+-msgid "Access variables in 32-bit PPU objects (default)."
+-msgstr ""
+-
+-#: config/spu/spu.opt:92
+-msgid "Access variables in 64-bit PPU objects."
+-msgstr ""
+-
+-#: config/spu/spu.opt:96
+-msgid "Allow conversions between __ea and generic pointers (default)."
+-msgstr ""
+-
+-#: config/spu/spu.opt:100
+-msgid "Size (in KB) of software data cache."
+-msgstr ""
+-
+-#: config/spu/spu.opt:104
+-msgid "Atomically write back software data cache lines (default)."
+-msgstr ""
+-
+-#: config/epiphany/epiphany.opt:24
+-msgid "Don't use any of r32..r63."
+-msgstr ""
+-
+-#: config/epiphany/epiphany.opt:28
++#: config/sh/sh.opt:293
+ msgid ""
+-"preferentially allocate registers that allow short instruction generation."
++"inline code to invalidate instruction cache entries after setting up nested "
++"function trampolines."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:32
+-msgid "Set branch cost."
++#: config/sh/sh.opt:297
++msgid "Assume symbols might be invalid."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:36
+-msgid "enable conditional move instruction usage."
++#: config/sh/sh.opt:305
++msgid "Generate code in little endian mode."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:40
+-msgid "set number of nops to emit before each insn pattern."
++#: config/sh/sh.opt:309
++msgid "Mark MAC register as call-clobbered."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:52
+-msgid "Use software floating point comparisons."
++#: config/sh/sh.opt:315
++msgid "Make structs a multiple of 4 bytes (warning: ABI altered)."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:56
+-msgid "Enable split of 32 bit immediate loads into low / high part."
++#: config/sh/sh.opt:319
++msgid "Emit function-calls using global offset table when generating PIC."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:60
+-msgid "Enable use of POST_INC / POST_DEC."
++#: config/sh/sh.opt:323
++msgid "Assume pt* instructions won't trap"
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:64
+-msgid "Enable use of POST_MODIFY."
++#: config/sh/sh.opt:327
++msgid "Shorten address references during linking."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:68
+-msgid "Set number of bytes on the stack preallocated for use by the callee."
++#: config/sh/sh.opt:335
++msgid "Deprecated.  Use -matomic= instead to select the atomic model."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:72
+-msgid "Assume round to nearest is selected for purposes of scheduling."
++#: config/sh/sh.opt:339
++msgid "Specify the model for atomic operations."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:76
+-msgid "Generate call insns as indirect calls."
++#: config/sh/sh.opt:343
++msgid "Use tas.b instruction for __atomic_test_and_set."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:80
+-msgid "Generate call insns as direct calls."
++#: config/sh/sh.opt:347
++msgid "Deprecated.  Use -Os instead."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:84
+-msgid ""
+-"Assume labels and symbols can be addressed using 16 bit absolute addresses."
++#: config/sh/sh.opt:351
++msgid "Cost to assume for a multiply insn."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:108
++#: config/sh/sh.opt:355
+ msgid ""
+-"A floatig point to integer truncation may be replaced with rounding to save "
+-"mode switching."
++"Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate "
++"if the inline code would not work in user mode."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:112
+-msgid "Vectorize for double-word operations."
++#: config/sh/sh.opt:361
++msgid "Pretend a branch-around-a-move is a conditional move."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:128
+-msgid ""
+-"Split unaligned 8 byte vector moves before post-modify address generation."
++#: config/sh/sh.opt:365
++msgid "Enable the use of the fsca instruction."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:132
+-msgid "Use the floating point unit for integer add/subtract."
++#: config/sh/sh.opt:369
++msgid "Enable the use of the fsrra instruction."
+ msgstr ""
+ 
+-#: config/epiphany/epiphany.opt:136
+-msgid "Set register to hold -1."
++#: config/sh/sh.opt:373
++msgid "Use LRA instead of reload (transitional)."
+ msgstr ""
+ 
+-#: config/ft32/ft32.opt:23
+-msgid "target the software simulator."
+-msgstr ""
+-
+-#: config/ft32/ft32.opt:27 config/s390/s390.opt:201 config/mips/mips.opt:385
+-msgid "Use LRA instead of reload."
+-msgstr ""
+-
+-#: config/ft32/ft32.opt:31
+-msgid "Avoid use of the DIV and MOD instructions"
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:23
+-msgid "Generate H8S code."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:27
+-msgid "Generate H8SX code."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:31
+-msgid "Generate H8S/2600 code."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:35
+-msgid "Make integers 32 bits wide."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:42
+-msgid "Use registers for argument passing."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:46
+-msgid "Consider access to byte sized memory slow."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:50
+-msgid "Enable linker relaxing."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:54
+-msgid "Generate H8/300H code."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:58
+-msgid "Enable the normal mode."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:62
+-msgid "Use H8/300 alignment rules."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:66
+-msgid "Push extended registers on stack in monitor functions."
+-msgstr ""
+-
+-#: config/h8300/h8300.opt:70
+-msgid "Do not push extended registers on stack in monitor functions."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:23
+-msgid "Generate code for an 11/10."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:27
+-msgid "Generate code for an 11/40."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:31
+-msgid "Generate code for an 11/45."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:35
+-msgid "Return floating-point results in ac0 (fr0 in Unix assembler syntax)."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:39
+-msgid "Do not use inline patterns for copying memory."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:43
+-msgid "Use inline patterns for copying memory."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:47
+-msgid "Do not pretend that branches are expensive."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:51
+-msgid "Pretend that branches are expensive."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:55
+-msgid "Use the DEC assembler syntax."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:59
+-msgid "Use 32 bit float."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:63
+-msgid "Use 64 bit float."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:67 config/rs6000/rs6000.opt:177
+-#: config/frv/frv.opt:158
+-msgid "Use hardware floating point."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:71
+-msgid "Use 16 bit int."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:75
+-msgid "Use 32 bit int."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:79 config/rs6000/rs6000.opt:173
+-msgid "Do not use hardware floating point."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:83
+-msgid "Target has split I&D."
+-msgstr ""
+-
+-#: config/pdp11/pdp11.opt:87
+-msgid "Use UNIX assembler syntax."
+-msgstr ""
+-
+-#: config/xtensa/xtensa.opt:23
+-msgid "Use CONST16 instruction to load constants."
+-msgstr ""
+-
+-#: config/xtensa/xtensa.opt:27
+-msgid "Disable position-independent code (PIC) for use in OS kernel code."
+-msgstr ""
+-
+-#: config/xtensa/xtensa.opt:31
+-msgid "Use indirect CALLXn instructions for large programs."
+-msgstr ""
+-
+-#: config/xtensa/xtensa.opt:35
+-msgid "Automatically align branch targets to reduce branch penalties."
+-msgstr ""
+-
+-#: config/xtensa/xtensa.opt:39
+-msgid "Intersperse literal pools with code in the text section."
+-msgstr ""
+-
+-#: config/xtensa/xtensa.opt:43
+-msgid ""
+-"Relax literals in assembler and place them automatically in the text section."
+-msgstr ""
+-
+-#: config/xtensa/xtensa.opt:47
+-msgid ""
+-"-mno-serialize-volatile\tDo not serialize volatile memory references with "
+-"MEMW instructions."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:23
+-msgid "Create console application."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:27
+-msgid "Generate code for a DLL."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:31
+-msgid "Ignore dllimport for functions."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:35
+-msgid "Use Mingw-specific thread support."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:39
+-msgid "Set Windows defines."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:43
+-msgid "Create GUI application."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:47 config/i386/interix.opt:32
+-msgid "Use the GNU extension to the PE format for aligned common data."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:51
+-msgid ""
+-"Compile code that relies on Cygwin DLL wrappers to support C++ operator new/"
+-"delete replacement."
+-msgstr ""
+-
+-#: config/i386/cygming.opt:58
+-msgid "Put relocated read-only data into .data section."
+-msgstr ""
+-
+-#: config/i386/mingw.opt:29
+-msgid "Warn about none ISO msvcrt scanf/printf width extensions."
+-msgstr ""
+-
+-#: config/i386/mingw.opt:33
+-msgid "For nested functions on stack executable permission is set."
+-msgstr ""
+-
+-#: config/i386/mingw-w64.opt:23
+-msgid "Use unicode startup and define UNICODE macro."
+-msgstr ""
+-
+ #: config/i386/i386.opt:182
+ msgid "sizeof(long double) is 16."
+ msgstr ""
+@@ -9034,20 +8267,6 @@
+ msgid "Use 80-bit long double."
+ msgstr ""
+ 
+-#: config/i386/i386.opt:198 config/s390/s390.opt:130
+-#: config/sparc/long-double-switch.opt:27 config/alpha/alpha.opt:102
+-msgid "Use 64-bit long double."
+-msgstr ""
+-
+-#: config/i386/i386.opt:202 config/s390/s390.opt:126
+-#: config/sparc/long-double-switch.opt:23 config/alpha/alpha.opt:98
+-msgid "Use 128-bit long double."
+-msgstr ""
+-
+-#: config/i386/i386.opt:206 config/sh/sh.opt:209
+-msgid "Reserve space for outgoing arguments in the function prologue."
+-msgstr ""
+-
+ #: config/i386/i386.opt:210
+ msgid "Align some doubles on dword boundary."
+ msgstr ""
+@@ -9098,8 +8317,8 @@
+ msgid "Use given x86-64 code model."
+ msgstr ""
+ 
+-#: config/i386/i386.opt:277 config/rs6000/aix64.opt:36
+-#: config/rs6000/linux64.opt:32 config/tilegx/tilegx.opt:57
++#: config/i386/i386.opt:277 config/tilegx/tilegx.opt:57
++#: config/rs6000/aix64.opt:36 config/rs6000/linux64.opt:32
+ msgid "Known code models (for use with the -mcmodel= option):"
+ msgstr ""
+ 
+@@ -9155,6 +8374,10 @@
+ msgid "Use native (MS) bitfield layout."
+ msgstr ""
+ 
++#: config/i386/i386.opt:390 config/aarch64/aarch64.opt:93
++msgid "Omit the frame pointer in leaf functions."
++msgstr ""
++
+ #: config/i386/i386.opt:394
+ msgid "Set 80387 floating-point precision to 32-bit."
+ msgstr ""
+@@ -9191,10 +8414,6 @@
+ msgid "Alternate calling convention."
+ msgstr ""
+ 
+-#: config/i386/i386.opt:430 config/alpha/alpha.opt:23
+-msgid "Do not use hardware fp."
+-msgstr ""
+-
+ #: config/i386/i386.opt:434
+ msgid "Use SSE register passing conventions for SF and DF mode."
+ msgstr ""
+@@ -9283,15 +8502,20 @@
+ 
+ #: config/i386/i386.opt:567
+ msgid ""
+-"Generate vzeroupper instruction before a transfer of control flow out of"
++"Generate vzeroupper instruction before a transfer of control flow out of the "
++"function."
+ msgstr ""
+ 
+ #: config/i386/i386.opt:572
+-msgid "Disable Scalar to Vector optimization pass transforming 64-bit integer"
++msgid ""
++"Disable Scalar to Vector optimization pass transforming 64-bit integer "
++"computations into a vector ones."
+ msgstr ""
+ 
+ #: config/i386/i386.opt:577
+-msgid "Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4"
++msgid ""
++"Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4 or "
++"znver1 and Haifa scheduling is selected."
+ msgstr ""
+ 
+ #: config/i386/i386.opt:582
+@@ -9502,8 +8726,8 @@
+ msgid "Support CLWB instruction."
+ msgstr ""
+ 
+-#: config/i386/i386.opt:760
+-msgid "Support PCOMMIT instruction."
++#: config/i386/i386.opt:759
++msgid "%<-mpcommit%> was deprecated"
+ msgstr ""
+ 
+ #: config/i386/i386.opt:764
+@@ -9587,7 +8811,9 @@
+ msgstr ""
+ 
+ #: config/i386/i386.opt:844
+-msgid "Generate mcount/__fentry__ calls as nops. To activate they need to be"
++msgid ""
++"Generate mcount/__fentry__ calls as nops. To activate they need to be "
++"patched in."
+ msgstr ""
+ 
+ #: config/i386/i386.opt:849
+@@ -9642,790 +8868,91 @@
+ msgid "Attempt to avoid generating instruction sequences containing ret bytes."
+ msgstr ""
+ 
+-#: config/i386/stringop.opt:8
+-msgid "the Free Software Foundation; either version 3, or (at your option)"
++#: config/i386/interix.opt:32 config/i386/cygming.opt:47
++msgid "Use the GNU extension to the PE format for aligned common data."
+ msgstr ""
+ 
+-#: config/i386/stringop.opt:13
+-msgid "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the"
++#: config/i386/cygming.opt:23
++msgid "Create console application."
+ msgstr ""
+ 
+-#: config/i386/stringop.opt:18
+-msgid "see <http://www.gnu.org/licenses/>.  */"
++#: config/i386/cygming.opt:27
++msgid "Generate code for a DLL."
+ msgstr ""
+ 
+-#: config/pa/pa64-hpux.opt:23
+-msgid "Assume code will be linked by GNU ld."
++#: config/i386/cygming.opt:31
++msgid "Ignore dllimport for functions."
+ msgstr ""
+ 
+-#: config/pa/pa64-hpux.opt:27
+-msgid "Assume code will be linked by HP ld."
++#: config/i386/cygming.opt:35
++msgid "Use Mingw-specific thread support."
+ msgstr ""
+ 
+-#: config/pa/pa-hpux1010.opt:23 config/pa/pa-hpux.opt:31
+-#: config/pa/pa-hpux1131.opt:23 config/pa/pa-hpux1111.opt:23
+-msgid "Specify UNIX standard for predefines and linking."
++#: config/i386/cygming.opt:39
++msgid "Set Windows defines."
+ msgstr ""
+ 
+-#: config/pa/pa-hpux.opt:27
+-msgid "Generate cpp defines for server IO."
++#: config/i386/cygming.opt:43
++msgid "Create GUI application."
+ msgstr ""
+ 
+-#: config/pa/pa-hpux.opt:35
+-msgid "Generate cpp defines for workstation IO."
+-msgstr ""
+-
+-#: config/pa/pa.opt:30 config/pa/pa.opt:83 config/pa/pa.opt:91
+-msgid "Generate PA1.0 code."
+-msgstr ""
+-
+-#: config/pa/pa.opt:34 config/pa/pa.opt:95 config/pa/pa.opt:136
+-msgid "Generate PA1.1 code."
+-msgstr ""
+-
+-#: config/pa/pa.opt:38 config/pa/pa.opt:99
+-msgid "Generate PA2.0 code (requires binutils 2.10 or later)."
+-msgstr ""
+-
+-#: config/pa/pa.opt:46
+-msgid "Disable FP regs."
+-msgstr ""
+-
+-#: config/pa/pa.opt:50
+-msgid "Disable indexed addressing."
+-msgstr ""
+-
+-#: config/pa/pa.opt:54
+-msgid "Generate fast indirect calls."
+-msgstr ""
+-
+-#: config/pa/pa.opt:62
+-msgid "Assume code will be assembled by GAS."
+-msgstr ""
+-
+-#: config/pa/pa.opt:71
+-msgid "Enable linker optimizations."
+-msgstr ""
+-
+-#: config/pa/pa.opt:75
+-msgid "Always generate long calls."
+-msgstr ""
+-
+-#: config/pa/pa.opt:79
+-msgid "Emit long load/store sequences."
+-msgstr ""
+-
+-#: config/pa/pa.opt:87
+-msgid "Disable space regs."
+-msgstr ""
+-
+-#: config/pa/pa.opt:103
+-msgid "Use portable calling conventions."
+-msgstr ""
+-
+-#: config/pa/pa.opt:107
++#: config/i386/cygming.opt:51
+ msgid ""
+-"Specify CPU for scheduling purposes.  Valid arguments are 700, 7100, 7100LC, "
+-"7200, 7300, and 8000."
++"Compile code that relies on Cygwin DLL wrappers to support C++ operator new/"
++"delete replacement."
+ msgstr ""
+ 
+-#: config/pa/pa.opt:132 config/frv/frv.opt:215
+-msgid "Use software floating point."
++#: config/i386/cygming.opt:58
++msgid "Put relocated read-only data into .data section."
+ msgstr ""
+ 
+-#: config/pa/pa.opt:140
+-msgid "Do not disable space regs."
++#: config/i386/mingw-w64.opt:23
++msgid "Use unicode startup and define UNICODE macro."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:29
+-msgid "Use registers r2 and r5."
++#: config/i386/mingw.opt:29
++msgid "Warn about none ISO msvcrt scanf/printf width extensions."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:33
+-msgid "Use 4 byte entries in switch tables."
++#: config/i386/mingw.opt:33
++msgid "For nested functions on stack executable permission is set."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:37
+-msgid "Enable backend debugging."
++#: config/moxie/moxie.opt:31
++msgid "Enable MUL.X and UMUL.X instructions."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:41
+-msgid "Do not use the callt instruction (default)."
++#: config/xtensa/xtensa.opt:23
++msgid "Use CONST16 instruction to load constants."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:45
+-msgid "Reuse r30 on a per function basis."
++#: config/xtensa/xtensa.opt:27
++msgid "Disable position-independent code (PIC) for use in OS kernel code."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:52
+-msgid "Prohibit PC relative function calls."
++#: config/xtensa/xtensa.opt:31
++msgid "Use indirect CALLXn instructions for large programs."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:56
+-msgid "Use stubs for function prologues."
++#: config/xtensa/xtensa.opt:35
++msgid "Automatically align branch targets to reduce branch penalties."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:60
+-msgid "Set the max size of data eligible for the SDA area."
++#: config/xtensa/xtensa.opt:39
++msgid "Intersperse literal pools with code in the text section."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:67
+-msgid "Enable the use of the short load instructions."
+-msgstr ""
+-
+-#: config/v850/v850.opt:71
+-msgid "Same as: -mep -mprolog-function."
+-msgstr ""
+-
+-#: config/v850/v850.opt:75
+-msgid "Set the max size of data eligible for the TDA area."
+-msgstr ""
+-
+-#: config/v850/v850.opt:82
+-msgid "Do not enforce strict alignment."
+-msgstr ""
+-
+-#: config/v850/v850.opt:86
++#: config/xtensa/xtensa.opt:43
+ msgid ""
+-"Put jump tables for switch statements into the .data section rather than "
+-"the .code section."
++"Relax literals in assembler and place them automatically in the text section."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:93
+-msgid "Compile for the v850 processor."
+-msgstr ""
+-
+-#: config/v850/v850.opt:97
+-msgid "Compile for the v850e processor."
+-msgstr ""
+-
+-#: config/v850/v850.opt:101
+-msgid "Compile for the v850e1 processor."
+-msgstr ""
+-
+-#: config/v850/v850.opt:105
+-msgid "Compile for the v850es variant of the v850e1."
+-msgstr ""
+-
+-#: config/v850/v850.opt:109
+-msgid "Compile for the v850e2 processor."
+-msgstr ""
+-
+-#: config/v850/v850.opt:113
+-msgid "Compile for the v850e2v3 processor."
+-msgstr ""
+-
+-#: config/v850/v850.opt:117
+-msgid "Compile for the v850e3v5 processor."
+-msgstr ""
+-
+-#: config/v850/v850.opt:124
+-msgid "Enable v850e3v5 loop instructions."
+-msgstr ""
+-
+-#: config/v850/v850.opt:128
+-msgid "Set the max size of data eligible for the ZDA area."
+-msgstr ""
+-
+-#: config/v850/v850.opt:135
+-msgid "Enable relaxing in the assembler."
+-msgstr ""
+-
+-#: config/v850/v850.opt:139
+-msgid "Prohibit PC relative jumps."
+-msgstr ""
+-
+-#: config/v850/v850.opt:143
+-msgid "Inhibit the use of hardware floating point instructions."
+-msgstr ""
+-
+-#: config/v850/v850.opt:147
++#: config/xtensa/xtensa.opt:47
+ msgid ""
+-"Allow the use of hardware floating point instructions for V850E2V3 and up."
++"-mno-serialize-volatile\tDo not serialize volatile memory references with "
++"MEMW instructions."
+ msgstr ""
+ 
+-#: config/v850/v850.opt:151
+-msgid "Enable support for the RH850 ABI.  This is the default."
+-msgstr ""
+-
+-#: config/v850/v850.opt:155
+-msgid "Enable support for the old GCC ABI."
+-msgstr ""
+-
+-#: config/v850/v850.opt:159
+-msgid "Support alignments of up to 64-bits."
+-msgstr ""
+-
+-#: config/g.opt:27
+-msgid ""
+-"-G<number>\tPut global and static data smaller than <number> bytes into a "
+-"special section (on some targets)."
+-msgstr ""
+-
+-#: config/lynx.opt:23
+-msgid "Support legacy multi-threading."
+-msgstr ""
+-
+-#: config/lynx.opt:27
+-msgid "Use shared libraries."
+-msgstr ""
+-
+-#: config/lynx.opt:31
+-msgid "Support multi-threading."
+-msgstr ""
+-
+-#: config/nvptx/nvptx.opt:22
+-msgid "Generate code for a 32-bit ABI."
+-msgstr ""
+-
+-#: config/nvptx/nvptx.opt:26
+-msgid "Generate code for a 64-bit ABI."
+-msgstr ""
+-
+-#: config/nvptx/nvptx.opt:30
+-msgid "Link in code for a __main kernel."
+-msgstr ""
+-
+-#: config/nvptx/nvptx.opt:34
+-msgid "Optimize partition neutering."
+-msgstr ""
+-
+-#: config/vxworks.opt:36
+-msgid "Assume the VxWorks RTP environment."
+-msgstr ""
+-
+-#: config/vxworks.opt:43
+-msgid "Assume the VxWorks vThreads environment."
+-msgstr ""
+-
+-#: config/cr16/cr16.opt:23
+-msgid "-msim   Use simulator runtime."
+-msgstr ""
+-
+-#: config/cr16/cr16.opt:27
+-msgid "Generate SBIT, CBIT instructions."
+-msgstr ""
+-
+-#: config/cr16/cr16.opt:31
+-msgid "Support multiply accumulate instructions."
+-msgstr ""
+-
+-#: config/cr16/cr16.opt:38
+-msgid "Treat data references as near, far or medium. medium is default."
+-msgstr ""
+-
+-#: config/cr16/cr16.opt:42
+-msgid "Generate code for CR16C architecture."
+-msgstr ""
+-
+-#: config/cr16/cr16.opt:46
+-msgid "Generate code for CR16C+ architecture (Default)."
+-msgstr ""
+-
+-#: config/cr16/cr16.opt:50
+-msgid "Treat integers as 32-bit."
+-msgstr ""
+-
+-#: config/avr/avr.opt:23
+-msgid "Use subroutines for function prologues and epilogues."
+-msgstr ""
+-
+-#: config/avr/avr.opt:26
+-#, c-format
+-msgid "missing device or architecture after %qs"
+-msgstr ""
+-
+-#: config/avr/avr.opt:27
+-msgid "-mmcu=MCU\tSelect the target MCU."
+-msgstr ""
+-
+-#: config/avr/avr.opt:31
+-msgid "Set the number of 64 KiB flash segments."
+-msgstr ""
+-
+-#: config/avr/avr.opt:35
+-msgid "Indicate presence of a processor erratum."
+-msgstr ""
+-
+-#: config/avr/avr.opt:39
+-msgid "Enable Read-Modify-Write (RMW) instructions support/use."
+-msgstr ""
+-
+-#: config/avr/avr.opt:49
+-msgid "Use an 8-bit 'int' type."
+-msgstr ""
+-
+-#: config/avr/avr.opt:53
+-msgid "Change the stack pointer without disabling interrupts."
+-msgstr ""
+-
+-#: config/avr/avr.opt:57
+-msgid ""
+-"Set the branch costs for conditional branch instructions.  Reasonable values "
+-"are small, non-negative integers.  The default branch cost is 0."
+-msgstr ""
+-
+-#: config/avr/avr.opt:67
+-msgid "Change only the low 8 bits of the stack pointer."
+-msgstr ""
+-
+-#: config/avr/avr.opt:71
+-msgid "Relax branches."
+-msgstr ""
+-
+-#: config/avr/avr.opt:75
+-msgid ""
+-"Make the linker relaxation machine assume that a program counter wrap-around "
+-"occurs."
+-msgstr ""
+-
+-#: config/avr/avr.opt:79
+-msgid ""
+-"Accumulate outgoing function arguments and acquire/release the needed stack "
+-"space for outpoing function arguments in function prologue/epilogue.  "
+-"Without this option, outgoing arguments are pushed before calling a function "
+-"and popped afterwards.  This option can lead to reduced code size for "
+-"functions that call many functions that get their arguments on the stack "
+-"like, for example printf."
+-msgstr ""
+-
+-#: config/avr/avr.opt:83
+-msgid ""
+-"When accessing RAM, use X as imposed by the hardware, i.e. just use pre-"
+-"decrement, post-increment and indirect addressing with the X register.  "
+-"Without this option, the compiler may assume that there is an addressing "
+-"mode X+const similar to Y+const and Z+const and emit instructions to emulate "
+-"such an addressing mode for X."
+-msgstr ""
+-
+-#: config/avr/avr.opt:88
+-msgid ""
+-"The device has no SPH special function register. This option will be "
+-"overridden by the compiler driver with the correct setting if presence/"
+-"absence of SPH can be deduced from -mmcu=MCU."
+-msgstr ""
+-
+-#: config/avr/avr.opt:92
+-msgid "Warn if the address space of an address is changed."
+-msgstr ""
+-
+-#: config/avr/avr.opt:96
+-msgid ""
+-"Allow to use truncation instead of rounding towards 0 for fractional int "
+-"types."
+-msgstr ""
+-
+-#: config/avr/avr.opt:100
+-msgid "Do not link against the device-specific library lib<MCU>.a."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:34
+-msgid "Compile for the m32rx."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:38
+-msgid "Compile for the m32r2."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:42
+-msgid "Compile for the m32r."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:46
+-msgid "Align all loops to 32 byte boundary."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:50
+-msgid "Prefer branches over conditional execution."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:54
+-msgid "Give branches their default cost."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:58
+-msgid "Display compile time statistics."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:62
+-msgid "Specify cache flush function."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:66
+-msgid "Specify cache flush trap number."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:70
+-msgid "Only issue one instruction per cycle."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:74
+-msgid "Allow two instructions to be issued per cycle."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:78
+-msgid "Code size: small, medium or large."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:94
+-msgid "Don't call any cache flush functions."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:98
+-msgid "Don't call any cache flush trap."
+-msgstr ""
+-
+-#: config/m32r/m32r.opt:105
+-msgid "Small data area: none, sdata, use."
+-msgstr ""
+-
+-#: config/s390/tpf.opt:23
+-msgid "Enable TPF-OS tracing code."
+-msgstr ""
+-
+-#: config/s390/tpf.opt:27
+-msgid "Specify main object for TPF-OS."
+-msgstr ""
+-
+-#: config/s390/s390.opt:48
+-msgid "31 bit ABI."
+-msgstr ""
+-
+-#: config/s390/s390.opt:52
+-msgid "64 bit ABI."
+-msgstr ""
+-
+-#: config/s390/s390.opt:96
+-msgid "Maintain backchain pointer."
+-msgstr ""
+-
+-#: config/s390/s390.opt:100
+-msgid "Additional debug prints."
+-msgstr ""
+-
+-#: config/s390/s390.opt:104
+-msgid "ESA/390 architecture."
+-msgstr ""
+-
+-#: config/s390/s390.opt:108
+-msgid "Enable decimal floating point hardware support."
+-msgstr ""
+-
+-#: config/s390/s390.opt:112
+-msgid "Enable hardware floating point."
+-msgstr ""
+-
+-#: config/s390/s390.opt:116
+-msgid "Takes two non-negative integer numbers separated by a comma."
+-msgstr ""
+-
+-#: config/s390/s390.opt:134
+-msgid "Use hardware transactional execution instructions."
+-msgstr ""
+-
+-#: config/s390/s390.opt:138
+-msgid "Use hardware vector facility instructions and enable the vector ABI."
+-msgstr ""
+-
+-#: config/s390/s390.opt:142
+-msgid "Use packed stack layout."
+-msgstr ""
+-
+-#: config/s390/s390.opt:146
+-msgid "Use bras for executable < 64k."
+-msgstr ""
+-
+-#: config/s390/s390.opt:150
+-msgid "Disable hardware floating point."
+-msgstr ""
+-
+-#: config/s390/s390.opt:154
+-msgid ""
+-"Set the max. number of bytes which has to be left to stack size before a "
+-"trap instruction is triggered."
+-msgstr ""
+-
+-#: config/s390/s390.opt:158
+-msgid "Switches off the -mstack-guard= option."
+-msgstr ""
+-
+-#: config/s390/s390.opt:162
+-msgid ""
+-"Emit extra code in the function prologue in order to trap if the stack size "
+-"exceeds the given limit."
+-msgstr ""
+-
+-#: config/s390/s390.opt:166
+-msgid "Switches off the -mstack-size= option."
+-msgstr ""
+-
+-#: config/s390/s390.opt:174
+-msgid "Use the mvcle instruction for block moves."
+-msgstr ""
+-
+-#: config/s390/s390.opt:178
+-msgid "Enable the z vector language extension providing the context-sensitive"
+-msgstr ""
+-
+-#: config/s390/s390.opt:183
+-msgid "Warn if a function uses alloca or creates an array with dynamic size."
+-msgstr ""
+-
+-#: config/s390/s390.opt:187
+-msgid "Warn if a single function's framesize exceeds the given framesize."
+-msgstr ""
+-
+-#: config/s390/s390.opt:191
+-msgid "z/Architecture."
+-msgstr ""
+-
+-#: config/s390/s390.opt:195
+-msgid "Set the branch costs for conditional branch instructions.  Reasonable"
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:27 config/rx/rx.opt:87
+-msgid "Use the simulator runtime."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:31
+-msgid ""
+-"Selects the type of hardware multiplication and division to use (none/g13/"
+-"g14)."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:50
+-msgid "Use all registers, reserving none for interrupt handlers."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:54
+-msgid "Enable assembler and linker relaxation.  Enabled by default at -Os."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:58
+-msgid ""
+-"Selects the type of RL78 core being targeted (g10/g13/g14).  The default is "
+-"the G14.  If set, also selects the hardware multiply support to be used."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:77
+-msgid "Alias for -mcpu=g10."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:81
+-msgid "Alias for -mcpu=g13."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:85 config/rl78/rl78.opt:89
+-msgid "Alias for -mcpu=g14."
+-msgstr ""
+-
+-#: config/rl78/rl78.opt:93
+-msgid ""
+-"Assume ES is zero throughout program execution, use ES: for read-only data."
+-msgstr ""
+-
+-#: config/stormy16/stormy16.opt:24
+-msgid "Provide libraries for the simulator."
+-msgstr ""
+-
+-#: config/arm/arm-tables.opt:25
+-msgid "Known ARM CPUs (for use with the -mcpu= and -mtune= options):"
+-msgstr ""
+-
+-#: config/arm/arm-tables.opt:341
+-msgid "Known ARM architectures (for use with the -march= option):"
+-msgstr ""
+-
+-#: config/arm/arm-tables.opt:438
+-msgid "Known ARM FPUs (for use with the -mfpu= option):"
+-msgstr ""
+-
+-#: config/arm/arm.opt:26
+-msgid "TLS dialect to use:"
+-msgstr ""
+-
+-#: config/arm/arm.opt:36
+-msgid "Specify an ABI."
+-msgstr ""
+-
+-#: config/arm/arm.opt:40
+-msgid "Known ARM ABIs (for use with the -mabi= option):"
+-msgstr ""
+-
+-#: config/arm/arm.opt:59
+-msgid "Generate a call to abort if a noreturn function returns."
+-msgstr ""
+-
+-#: config/arm/arm.opt:66
+-msgid "Pass FP arguments in FP registers."
+-msgstr ""
+-
+-#: config/arm/arm.opt:70
+-msgid "Generate APCS conformant stack frames."
+-msgstr ""
+-
+-#: config/arm/arm.opt:74
+-msgid "Generate re-entrant, PIC code."
+-msgstr ""
+-
+-#: config/arm/arm.opt:90
+-msgid "Generate code in 32 bit ARM state."
+-msgstr ""
+-
+-#: config/arm/arm.opt:98
+-msgid "Thumb: Assume non-static functions may be called from ARM code."
+-msgstr ""
+-
+-#: config/arm/arm.opt:102
+-msgid "Thumb: Assume function pointers may go to non-Thumb aware code."
+-msgstr ""
+-
+-#: config/arm/arm.opt:110
+-msgid "Specify if floating point hardware should be used."
+-msgstr ""
+-
+-#: config/arm/arm.opt:114
+-msgid "Known floating-point ABIs (for use with the -mfloat-abi= option):"
+-msgstr ""
+-
+-#: config/arm/arm.opt:127
+-msgid "Switch ARM/Thumb modes on alternating functions for compiler testing."
+-msgstr ""
+-
+-#: config/arm/arm.opt:131
+-msgid "Specify the __fp16 floating-point format."
+-msgstr ""
+-
+-#: config/arm/arm.opt:135
+-msgid "Known __fp16 formats (for use with the -mfp16-format= option):"
+-msgstr ""
+-
+-#: config/arm/arm.opt:148
+-msgid "Specify the name of the target floating point hardware/format."
+-msgstr ""
+-
+-#: config/arm/arm.opt:159
+-msgid "Generate call insns as indirect calls, if necessary."
+-msgstr ""
+-
+-#: config/arm/arm.opt:163
+-msgid "Assume data segments are relative to text segment."
+-msgstr ""
+-
+-#: config/arm/arm.opt:167
+-msgid "Specify the register to be used for PIC addressing."
+-msgstr ""
+-
+-#: config/arm/arm.opt:171
+-msgid "Store function names in object code."
+-msgstr ""
+-
+-#: config/arm/arm.opt:175
+-msgid "Permit scheduling of a function's prologue sequence."
+-msgstr ""
+-
+-#: config/arm/arm.opt:179 config/rs6000/rs6000.opt:248
+-msgid "Do not load the PIC register in function prologues."
+-msgstr ""
+-
+-#: config/arm/arm.opt:186
+-msgid "Specify the minimum bit alignment of structures."
+-msgstr ""
+-
+-#: config/arm/arm.opt:190
+-msgid "Generate code for Thumb state."
+-msgstr ""
+-
+-#: config/arm/arm.opt:194
+-msgid "Support calls between Thumb and ARM instruction sets."
+-msgstr ""
+-
+-#: config/arm/arm.opt:198
+-msgid "Specify thread local storage scheme."
+-msgstr ""
+-
+-#: config/arm/arm.opt:202
+-msgid "Specify how to access the thread pointer."
+-msgstr ""
+-
+-#: config/arm/arm.opt:206
+-msgid "Valid arguments to -mtp=:"
+-msgstr ""
+-
+-#: config/arm/arm.opt:219
+-msgid "Thumb: Generate (non-leaf) stack frames even if not needed."
+-msgstr ""
+-
+-#: config/arm/arm.opt:223
+-msgid "Thumb: Generate (leaf) stack frames even if not needed."
+-msgstr ""
+-
+-#: config/arm/arm.opt:227 config/mn10300/mn10300.opt:42
+-msgid "Tune code for the given processor."
+-msgstr ""
+-
+-#: config/arm/arm.opt:231
+-msgid "Print CPU tuning information as comment in assembler file.  This is"
+-msgstr ""
+-
+-#: config/arm/arm.opt:242
+-msgid ""
+-"Use Neon quad-word (rather than double-word) registers for vectorization."
+-msgstr ""
+-
+-#: config/arm/arm.opt:246
+-msgid ""
+-"Use Neon double-word (rather than quad-word) registers for vectorization."
+-msgstr ""
+-
+-#: config/arm/arm.opt:250
+-msgid "Only generate absolute relocations on word sized values."
+-msgstr ""
+-
+-#: config/arm/arm.opt:254
+-msgid "Generate IT blocks appropriate for ARMv8."
+-msgstr ""
+-
+-#: config/arm/arm.opt:258
+-msgid "Use the old RTX costing tables (transitional)."
+-msgstr ""
+-
+-#: config/arm/arm.opt:262
+-msgid ""
+-"Use the new generic RTX cost tables if new core-specific cost table not "
+-"available (transitional)."
+-msgstr ""
+-
+-#: config/arm/arm.opt:266
+-msgid ""
+-"Avoid overlapping destination and address registers on LDRD instructions"
+-msgstr ""
+-
+-#: config/arm/arm.opt:271
+-msgid "Enable unaligned word and halfword accesses to packed data."
+-msgstr ""
+-
+-#: config/arm/arm.opt:275
+-msgid "Use Neon to perform 64-bits operations rather than core registers."
+-msgstr ""
+-
+-#: config/arm/arm.opt:279
+-msgid "Assume loading data from flash is slower than fetching instructions."
+-msgstr ""
+-
+-#: config/arm/arm.opt:283
+-msgid "Assume unified syntax for inline assembly code."
+-msgstr ""
+-
+-#: config/sparc/sparc.opt:30 config/sparc/sparc.opt:34
+-#: config/visium/visium.opt:37
+-msgid "Use hardware FP."
+-msgstr ""
+-
+-#: config/sparc/sparc.opt:38 config/visium/visium.opt:41
+-msgid "Do not use hardware FP."
+-msgstr ""
+-
+ #: config/sparc/sparc.opt:42
+ msgid "Use flat register window model."
+ msgstr ""
+@@ -10510,10 +9037,6 @@
+ msgid "Do not generate code that can only run in supervisor mode (default)."
+ msgstr ""
+ 
+-#: config/sparc/sparc.opt:126 config/visium/visium.opt:45
+-msgid "Use features of and schedule code for given CPU."
+-msgstr ""
+-
+ #: config/sparc/sparc.opt:206
+ msgid "Use given SPARC-V9 code model."
+ msgstr ""
+@@ -10527,7 +9050,9 @@
+ msgstr ""
+ 
+ #: config/sparc/sparc.opt:218
+-msgid "Enable workaround for single erratum of AT697F processor"
++msgid ""
++"Enable workaround for single erratum of AT697F processor (corresponding to "
++"erratum #13 of AT697E processor)."
+ msgstr ""
+ 
+ #: config/sparc/sparc.opt:223
+@@ -10538,683 +9063,226 @@
+ msgid "Specify the memory model in effect for the program."
+ msgstr ""
+ 
+-#: config/rs6000/darwin.opt:38 config/rs6000/sysv4.opt:141
+-msgid "Generate 64-bit code."
++#: config/m32c/m32c.opt:23
++msgid "-msim\tUse simulator runtime."
+ msgstr ""
+ 
+-#: config/rs6000/darwin.opt:42 config/rs6000/sysv4.opt:145
+-msgid "Generate 32-bit code."
++#: config/m32c/m32c.opt:27
++msgid "-mcpu=r8c\tCompile code for R8C variants."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000-tables.opt:24
+-msgid "Known CPUs (for use with the -mcpu= and -mtune= options):"
++#: config/m32c/m32c.opt:31
++msgid "-mcpu=m16c\tCompile code for M16C variants."
+ msgstr ""
+ 
+-#: config/rs6000/476.opt:24
+-msgid ""
+-"Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl "
+-"insns used for GOT accesses."
++#: config/m32c/m32c.opt:35
++msgid "-mcpu=m32cm\tCompile code for M32CM variants."
+ msgstr ""
+ 
+-#: config/rs6000/aix64.opt:24
+-msgid "Compile for 64-bit pointers."
++#: config/m32c/m32c.opt:39
++msgid "-mcpu=m32c\tCompile code for M32C variants."
+ msgstr ""
+ 
+-#: config/rs6000/aix64.opt:28
+-msgid "Compile for 32-bit pointers."
++#: config/m32c/m32c.opt:43
++msgid "-memregs=\tNumber of memreg bytes (default: 16, range: 0..16)."
+ msgstr ""
+ 
+-#: config/rs6000/aix64.opt:32 config/rs6000/linux64.opt:28
+-msgid "Select code model."
++#: config/iq2000/iq2000.opt:31
++msgid "Specify CPU for code generation purposes."
+ msgstr ""
+ 
+-#: config/rs6000/aix64.opt:49
+-msgid "Support message passing with the Parallel Environment."
++#: config/iq2000/iq2000.opt:47
++msgid "Specify CPU for scheduling purposes."
+ msgstr ""
+ 
+-#: config/rs6000/linux64.opt:24
+-msgid "Call mcount for profiling before a function prologue."
++#: config/iq2000/iq2000.opt:51
++msgid "Known IQ2000 CPUs (for use with the -mcpu= option):"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:109
+-msgid "Use PowerPC-64 instruction set."
++#: config/iq2000/iq2000.opt:70
++msgid "No default crt0.o."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:113
+-msgid "Use PowerPC General Purpose group optional instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:117
+-msgid "Use PowerPC Graphics group optional instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:121
+-msgid "Use PowerPC V2.01 single field mfcr instruction."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:125
+-msgid "Use PowerPC V2.02 popcntb instruction."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:129
+-msgid "Use PowerPC V2.02 floating point rounding instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:133
+-msgid "Use PowerPC V2.05 compare bytes instruction."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:137
++#: config/g.opt:27
+ msgid ""
+-"Use extended PowerPC V2.05 move floating point to/from GPR instructions."
++"-G<number>\tPut global and static data smaller than <number> bytes into a "
++"special section (on some targets)."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:141
+-msgid "Use AltiVec instructions."
++#: config/linux-android.opt:23
++msgid "Generate code for the Android platform."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:145
+-msgid "Generate Altivec instructions using little-endian element order."
++#: config/ia64/ilp32.opt:3
++msgid "Generate ILP32 code."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:149
+-msgid "Generate Altivec instructions using big-endian element order."
++#: config/ia64/ilp32.opt:7
++msgid "Generate LP64 code."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:153
+-msgid "Use decimal floating point instructions."
++#: config/ia64/ia64.opt:28
++msgid "Generate big endian code."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:157
+-msgid "Use 4xx half-word multiply instructions."
++#: config/ia64/ia64.opt:32
++msgid "Generate little endian code."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:161
+-msgid "Use 4xx string-search dlmzb instruction."
++#: config/ia64/ia64.opt:36
++msgid "Generate code for GNU as."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:165
+-msgid "Generate load/store multiple instructions."
++#: config/ia64/ia64.opt:40
++msgid "Generate code for GNU ld."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:169
+-msgid "Generate string instructions for block moves."
++#: config/ia64/ia64.opt:44
++msgid "Emit stop bits before and after volatile extended asms."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:181
+-msgid "Use PowerPC V2.06 popcntd instruction."
++#: config/ia64/ia64.opt:48
++msgid "Use in/loc/out register names."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:185
+-msgid ""
+-"Under -ffast-math, generate a FRIZ instruction for (double)(long long) "
+-"conversions."
++#: config/ia64/ia64.opt:55
++msgid "Enable use of sdata/scommon/sbss."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:193
+-msgid "Use vector/scalar (VSX) instructions."
++#: config/ia64/ia64.opt:59
++msgid "Generate code without GP reg."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:240
+-msgid "Do not generate load/store with update instructions."
++#: config/ia64/ia64.opt:63
++msgid "gp is constant (but save/restore gp on indirect calls)."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:244
+-msgid "Generate load/store with update instructions."
++#: config/ia64/ia64.opt:67
++msgid "Generate self-relocatable code."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:252
+-msgid "Avoid generation of indexed load/store instructions when possible."
++#: config/ia64/ia64.opt:71
++msgid "Generate inline floating point division, optimize for latency."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:256
+-msgid "Mark __tls_get_addr calls with argument info."
++#: config/ia64/ia64.opt:75
++msgid "Generate inline floating point division, optimize for throughput."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:263
+-msgid "Schedule the start and end of the procedure."
++#: config/ia64/ia64.opt:82
++msgid "Generate inline integer division, optimize for latency."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:267
+-msgid "Return all structures in memory (AIX default)."
++#: config/ia64/ia64.opt:86
++msgid "Generate inline integer division, optimize for throughput."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:271
+-msgid "Return small structures in registers (SVR4 default)."
++#: config/ia64/ia64.opt:90
++msgid "Do not inline integer division."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:275
+-msgid "Conform more closely to IBM XLC semantics."
++#: config/ia64/ia64.opt:94
++msgid "Generate inline square root, optimize for latency."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:279 config/rs6000/rs6000.opt:283
+-msgid ""
+-"Generate software reciprocal divide and square root for better throughput."
++#: config/ia64/ia64.opt:98
++msgid "Generate inline square root, optimize for throughput."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:287
+-msgid "Assume that the reciprocal estimate instructions provide more accuracy."
++#: config/ia64/ia64.opt:102
++msgid "Do not inline square root."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:291
+-msgid "Do not place floating point constants in TOC."
++#: config/ia64/ia64.opt:106
++msgid "Enable DWARF line debug info via GNU as."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:295
+-msgid "Place floating point constants in TOC."
++#: config/ia64/ia64.opt:110
++msgid "Enable earlier placing stop bits for better scheduling."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:299
+-msgid "Do not place symbol+offset constants in TOC."
++#: config/ia64/ia64.opt:126
++msgid "Known Itanium CPUs (for use with the -mtune= option):"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:303
+-msgid "Place symbol+offset constants in TOC."
++#: config/ia64/ia64.opt:136
++msgid "Use data speculation before reload."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:314
+-msgid "Use only one TOC entry per procedure."
++#: config/ia64/ia64.opt:140
++msgid "Use data speculation after reload."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:318
+-msgid "Put everything in the regular TOC."
++#: config/ia64/ia64.opt:144
++msgid "Use control speculation."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:322
+-msgid "Generate VRSAVE instructions when generating AltiVec code."
++#: config/ia64/ia64.opt:148
++msgid "Use in block data speculation before reload."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:326
+-msgid "Deprecated option.  Use -mno-vrsave instead."
++#: config/ia64/ia64.opt:152
++msgid "Use in block data speculation after reload."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:330
+-msgid "Deprecated option.  Use -mvrsave instead."
++#: config/ia64/ia64.opt:156
++msgid "Use in block control speculation."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:334
+-msgid ""
+-"Specify how many bytes should be moved inline before calling out to memcpy/"
+-"memmove."
++#: config/ia64/ia64.opt:160
++msgid "Use simple data speculation check."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:338
+-msgid "Generate isel instructions."
++#: config/ia64/ia64.opt:164
++msgid "Use simple data speculation check for control speculation."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:342
+-msgid "Deprecated option.  Use -mno-isel instead."
++#: config/ia64/ia64.opt:167 config/ia64/ia64.opt:170 c-family/c.opt:650
++#: c-family/c.opt:1024 c-family/c.opt:1031 c-family/c.opt:1205
++#: c-family/c.opt:1224 c-family/c.opt:1247 c-family/c.opt:1253
++#: c-family/c.opt:1260 c-family/c.opt:1284 c-family/c.opt:1295
++#: c-family/c.opt:1298 c-family/c.opt:1301 c-family/c.opt:1304
++#: c-family/c.opt:1307 c-family/c.opt:1344 c-family/c.opt:1475
++#: c-family/c.opt:1499 c-family/c.opt:1517 c-family/c.opt:1548
++#: c-family/c.opt:1552 c-family/c.opt:1568 c-family/c-opts.c:419
++#, gcc-internal-format
++msgid "switch %qs is no longer supported"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:346
+-msgid "Deprecated option.  Use -misel instead."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:350
+-msgid "Generate SPE SIMD instructions on E500."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:354
+-msgid "Generate PPC750CL paired-single instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:358
+-msgid "Deprecated option.  Use -mno-spe instead."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:362
+-msgid "Deprecated option.  Use -mspe instead."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:366
+-msgid "-mdebug=\tEnable debug output."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:370
+-msgid "Use the AltiVec ABI extensions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:374
+-msgid "Do not use the AltiVec ABI extensions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:378
+-msgid "Use the SPE ABI extensions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:382
+-msgid "Do not use the SPE ABI extensions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:386
+-msgid "Use the ELFv1 ABI."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:390
+-msgid "Use the ELFv2 ABI."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:397
+-msgid "using darwin64 ABI"
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:400
+-msgid "using old darwin ABI"
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:403
+-msgid "using IEEE extended precision long double"
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:406
+-msgid "using IBM extended precision long double"
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:410
+-msgid "-mcpu=\tUse features of and schedule code for given CPU."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:414
+-msgid "-mtune=\tSchedule code for given CPU."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:418
+-msgid "-mtraceback=\tSelect full, part, or no traceback table."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:434
+-msgid "Avoid all range limits on call instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:438
+-msgid "Generate Cell microcode."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:442
+-msgid "Warn when a Cell microcoded instruction is emitted."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:446
+-msgid "Warn about deprecated 'vector long ...' AltiVec type usage."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:450
+-msgid "-mfloat-gprs=\tSelect GPR floating point method."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:454
+-msgid "Valid arguments to -mfloat-gprs=:"
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:470
+-msgid "-mlong-double-<n>\tSpecify size of long double (64 or 128 bits)."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:474
+-msgid "Enable Local Register Allocation."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:478
+-msgid "Determine which dependences between insns are considered costly."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:482
+-msgid "Specify which post scheduling nop insertion scheme to apply."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:486
+-msgid "Specify alignment of structure fields default/natural."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:490
+-msgid "Valid arguments to -malign-:"
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:500
+-msgid "Specify scheduling priority for dispatch slot restricted insns."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:504
+-msgid "Single-precision floating point unit."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:508
+-msgid "Double-precision floating point unit."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:512
+-msgid "Floating point unit does not support divide & sqrt."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:516
+-msgid "-mfpu=\tSpecify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:538
+-msgid "Specify Xilinx FPU."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:542
++#: config/ia64/ia64.opt:174
+ msgid ""
+-"Use/do not use r11 to hold the static link in calls to functions via "
+-"pointers."
++"Count speculative dependencies while calculating priority of instructions."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:546
+-msgid ""
+-"Control whether we save the TOC in the prologue for indirect calls or "
+-"generate the save inline."
++#: config/ia64/ia64.opt:178
++msgid "Place a stop bit after every cycle when scheduling."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:550
+-msgid "Allow 128-bit integers in VSX registers."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:554
++#: config/ia64/ia64.opt:182
+ msgid ""
+-"Fuse certain integer operations together for better performance on power8."
++"Assume that floating-point stores and loads are not likely to cause conflict "
++"when placed into one instruction group."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:558
+-msgid "Allow sign extension in fusion operations."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:562
+-msgid "Use/do not use vector and scalar instructions added in ISA 2.07."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:566
+-msgid "Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:570
+-msgid "Use ISA 2.07 direct move between GPR & VSX register instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:574
+-msgid "Use ISA 2.07 transactional memory (HTM) instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:578
+-msgid "Generate the quad word memory instructions (lq/stq)."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:582
+-msgid "Generate the quad word memory atomic instructions (lqarx/stqcx)."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:586
++#: config/ia64/ia64.opt:186
+ msgid ""
+-"Generate aggregate parameter passing code with at most 64-bit alignment."
++"Soft limit on number of memory insns per instruction group, giving lower "
++"priority to subsequent memory insns attempting to schedule in the same insn "
++"group. Frequently useful to prevent cache bank conflicts.  Default value is "
++"1."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:590
+-msgid "Allow double variables in upper registers with -mcpu=power7 or -mvsx."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:594
++#: config/ia64/ia64.opt:190
+ msgid ""
+-"Allow float variables in upper registers with -mcpu=power8 or -mpower8-"
+-"vector."
++"Disallow more than 'msched-max-memory-insns' in instruction group. "
++"Otherwise, limit is 'soft' (prefer non-memory operations when limit is "
++"reached)."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:598
+-msgid "Allow float/double variables in upper registers if cpu allows it."
++#: config/ia64/ia64.opt:194
++msgid "Don't generate checks for control speculation in selective scheduling."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.opt:602
+-msgid "Analyze and remove doubleword swaps from VSX computations."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:606
+-msgid "Fuse certain operations together for better performance on power9."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:610
+-msgid "Use/do not use certain scalar instructions added in ISA 3.0."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:614
+-msgid "Use/do not use vector instructions added in ISA 3.0."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:618
+-msgid ""
+-"Use/do not use scalar register+offset memory instructions added in ISA 3.0."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:622
+-msgid ""
+-"Use/do not use vector register+offset memory instructions added in ISA 3.0."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:626
+-msgid "Use/do not use register+offset memory instructions added in ISA 3.0."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:630
+-msgid "Use/do not use the new min/max instructions defined in ISA 3.0."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:634
+-msgid ""
+-"Fuse medium/large code model toc references with the memory instruction."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:638
+-msgid "Generate the integer modulo instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:642
+-msgid "Enable/disable IEEE 128-bit floating point via the __float128 keyword."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:646
+-msgid "Enable/disable using IEEE 128-bit floating point instructions."
+-msgstr ""
+-
+-#: config/rs6000/rs6000.opt:650
+-msgid "Enable/disable default conversions between __float128 & long double."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:24
+-msgid "Select ABI calling convention."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:28 config/c6x/c6x.opt:42
+-msgid "Select method for sdata handling."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:48 config/rs6000/sysv4.opt:52
+-msgid "Align to the base type of the bit-field."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:57 config/rs6000/sysv4.opt:61
+-msgid "Produce code relocatable at runtime."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:65 config/rs6000/sysv4.opt:69
+-msgid "Produce little endian code."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:73 config/rs6000/sysv4.opt:77
+-msgid "Produce big endian code."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:82 config/rs6000/sysv4.opt:86
+-#: config/rs6000/sysv4.opt:95 config/rs6000/sysv4.opt:137
+-#: config/rs6000/sysv4.opt:149
+-msgid "no description yet."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:90
+-msgid "Assume all variable arg functions are prototyped."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:99
+-msgid "Use EABI."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:103
+-msgid "Allow bit-fields to cross word boundaries."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:107
+-msgid "Use alternate register names."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:113
+-msgid "Use default method for sdata handling."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:117
+-msgid "Link with libsim.a, libc.a and sim-crt0.o."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:121
+-msgid "Link with libads.a, libc.a and crt0.o."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:125
+-msgid "Link with libyk.a, libc.a and crt0.o."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:129
+-msgid "Link with libmvme.a, libc.a and crt0.o."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:133
+-msgid "Set the PPC_EMB bit in the ELF flags header."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:153
+-msgid "Generate code to use a non-exec PLT and GOT."
+-msgstr ""
+-
+-#: config/rs6000/sysv4.opt:157
+-msgid "Generate code for old exec BSS PLT."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:27
+-msgid "Use fp registers."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:35
+-msgid "Request IEEE-conformant math library routines (OSF/1)."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:39
+-msgid "Emit IEEE-conformant code, without inexact exceptions."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:46
+-msgid "Do not emit complex integer constants to read-only memory."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:50
+-msgid "Use VAX fp."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:54
+-msgid "Do not use VAX fp."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:58
+-msgid "Emit code for the byte/word ISA extension."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:62
+-msgid "Emit code for the motion video ISA extension."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:66
+-msgid "Emit code for the fp move and sqrt ISA extension."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:70
+-msgid "Emit code for the counting ISA extension."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:74
+-msgid "Emit code using explicit relocation directives."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:78
+-msgid "Emit 16-bit relocations to the small data areas."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:82
+-msgid "Emit 32-bit relocations to the small data areas."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:86
+-msgid "Emit direct branches to local functions."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:90
+-msgid "Emit indirect branches to local functions."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:94
+-msgid "Emit rdval instead of rduniq for thread pointer."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:106
+-msgid "Use features of and schedule given CPU."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:110
+-msgid "Schedule given CPU."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:114
+-msgid "Control the generated fp rounding mode."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:118
+-msgid "Control the IEEE trap mode."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:122
+-msgid "Control the precision given to fp exceptions."
+-msgstr ""
+-
+-#: config/alpha/alpha.opt:126
+-msgid "Tune expected memory latency."
+-msgstr ""
+-
+-#: config/tilepro/tilepro.opt:23
+-msgid "Compile with 32 bit longs and pointers, which is the only supported"
+-msgstr ""
+-
+-#: config/tilepro/tilepro.opt:28 config/tilegx/tilegx.opt:26
+-msgid "-mcpu=CPU\tUse features of and schedule code for given CPU."
+-msgstr ""
+-
+-#: config/tilepro/tilepro.opt:32
+-msgid "Known TILEPro CPUs (for use with the -mcpu= option):"
+-msgstr ""
+-
+-#: config/lm32/lm32.opt:24
+-msgid "Enable multiply instructions."
+-msgstr ""
+-
+-#: config/lm32/lm32.opt:28
+-msgid "Enable divide and modulus instructions."
+-msgstr ""
+-
+-#: config/lm32/lm32.opt:32
+-msgid "Enable barrel shift instructions."
+-msgstr ""
+-
+-#: config/lm32/lm32.opt:36
+-msgid "Enable sign extend instructions."
+-msgstr ""
+-
+-#: config/lm32/lm32.opt:40
+-msgid "Enable user-defined instructions."
+-msgstr ""
+-
+ #: config/nios2/elf.opt:26
+ msgid "Link with a limited version of the C library."
+ msgstr ""
+@@ -11275,16 +9343,6 @@
+ msgid "Equivalent to -mgpopt=none."
+ msgstr ""
+ 
+-#: config/nios2/nios2.opt:94 config/c6x/c6x.opt:30 config/mep/mep.opt:82
+-#: config/mips/mips.opt:134 config/tilegx/tilegx.opt:45
+-msgid "Use big-endian byte order."
+-msgstr ""
+-
+-#: config/nios2/nios2.opt:98 config/c6x/c6x.opt:34 config/mep/mep.opt:86
+-#: config/mips/mips.opt:138 config/tilegx/tilegx.opt:49
+-msgid "Use little-endian byte order."
+-msgstr ""
+-
+ #: config/nios2/nios2.opt:102
+ msgid "Floating point custom instruction configuration name."
+ msgstr ""
+@@ -11765,6 +9823,85 @@
+ msgid "Enable generation of R2 CDX instructions."
+ msgstr ""
+ 
++#: config/lm32/lm32.opt:24
++msgid "Enable multiply instructions."
++msgstr ""
++
++#: config/lm32/lm32.opt:28
++msgid "Enable divide and modulus instructions."
++msgstr ""
++
++#: config/lm32/lm32.opt:32
++msgid "Enable barrel shift instructions."
++msgstr ""
++
++#: config/lm32/lm32.opt:36
++msgid "Enable sign extend instructions."
++msgstr ""
++
++#: config/lm32/lm32.opt:40
++msgid "Enable user-defined instructions."
++msgstr ""
++
++#: config/msp430/msp430.opt:7
++msgid "Force assembly output to always use hex constants."
++msgstr ""
++
++#: config/msp430/msp430.opt:11
++msgid "Specify the MCU to build for."
++msgstr ""
++
++#: config/msp430/msp430.opt:15
++msgid ""
++"Warn if an MCU name is unrecognised or conflicts with other options "
++"(default: on)."
++msgstr ""
++
++#: config/msp430/msp430.opt:19
++msgid "Specify the ISA to build for: msp430, msp430x, msp430xv2."
++msgstr ""
++
++#: config/msp430/msp430.opt:23
++msgid "Select large model - 20-bit addresses/pointers."
++msgstr ""
++
++#: config/msp430/msp430.opt:27
++msgid "Select small model - 16-bit addresses/pointers (default)."
++msgstr ""
++
++#: config/msp430/msp430.opt:31
++msgid "Optimize opcode sizes at link time."
++msgstr ""
++
++#: config/msp430/msp430.opt:38
++msgid ""
++"Use a minimum runtime (no static initializers or ctors) for memory-"
++"constrained devices."
++msgstr ""
++
++#: config/msp430/msp430.opt:45
++msgid "Specify the type of hardware multiply to support."
++msgstr ""
++
++#: config/msp430/msp430.opt:67
++msgid "Specify whether functions should be placed into low or high memory."
++msgstr ""
++
++#: config/msp430/msp430.opt:71
++msgid "Specify whether variables should be placed into low or high memory."
++msgstr ""
++
++#: config/msp430/msp430.opt:90
++msgid ""
++"Passes on a request to the assembler to enable fixes for various silicon "
++"errata."
++msgstr ""
++
++#: config/msp430/msp430.opt:94
++msgid ""
++"Passes on a request to the assembler to warn about various silicon errata."
++msgstr ""
++
+ #: config/rx/rx.opt:29
+ msgid "Store doubles in 64 bits."
+ msgstr ""
+@@ -11799,6 +9936,10 @@
+ "small data area."
+ msgstr ""
+ 
++#: config/rx/rx.opt:87 config/rl78/rl78.opt:27
++msgid "Use the simulator runtime."
++msgstr ""
++
+ #: config/rx/rx.opt:93
+ msgid ""
+ "Generate assembler output that is compatible with the Renesas AS100 "
+@@ -11860,861 +10001,615 @@
+ msgid "Always use JSR, never BSR, for calls."
+ msgstr ""
+ 
+-#: config/visium/visium.opt:25
+-msgid "Link with libc.a and libdebug.a."
++#: config/cr16/cr16.opt:23
++msgid "-msim   Use simulator runtime."
+ msgstr ""
+ 
+-#: config/visium/visium.opt:29
+-msgid "Link with libc.a and libsim.a."
++#: config/cr16/cr16.opt:27
++msgid "Generate SBIT, CBIT instructions."
+ msgstr ""
+ 
+-#: config/visium/visium.opt:33
+-msgid "Use hardware FP (default)."
++#: config/cr16/cr16.opt:31
++msgid "Support multiply accumulate instructions."
+ msgstr ""
+ 
+-#: config/visium/visium.opt:65
+-msgid "Generate code for the supervisor mode (default)."
++#: config/cr16/cr16.opt:38
++msgid "Treat data references as near, far or medium. medium is default."
+ msgstr ""
+ 
+-#: config/visium/visium.opt:69
+-msgid "Generate code for the user mode."
++#: config/cr16/cr16.opt:42
++msgid "Generate code for CR16C architecture."
+ msgstr ""
+ 
+-#: config/visium/visium.opt:73
+-msgid "Only retained for backward compatibility."
++#: config/cr16/cr16.opt:46
++msgid "Generate code for CR16C+ architecture (Default)."
+ msgstr ""
+ 
+-#: config/fused-madd.opt:22
+-msgid "%<-mfused-madd%> is deprecated; use %<-ffp-contract=%> instead"
++#: config/cr16/cr16.opt:50
++msgid "Treat integers as 32-bit."
+ msgstr ""
+ 
+-#: config/sol2.opt:32
+-msgid "Clear hardware capabilities when linking."
++#: config/pa/pa-hpux.opt:27
++msgid "Generate cpp defines for server IO."
+ msgstr ""
+ 
+-#: config/sol2.opt:36
+-msgid "Pass -z text to linker."
++#: config/pa/pa-hpux.opt:31 config/pa/pa-hpux1131.opt:23
++#: config/pa/pa-hpux1111.opt:23 config/pa/pa-hpux1010.opt:23
++msgid "Specify UNIX standard for predefines and linking."
+ msgstr ""
+ 
+-#: config/moxie/moxie.opt:31
+-msgid "Enable MUL.X and UMUL.X instructions."
++#: config/pa/pa-hpux.opt:35
++msgid "Generate cpp defines for workstation IO."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:40
+-msgid "Use software emulation for floating point (default)."
++#: config/pa/pa.opt:30 config/pa/pa.opt:83 config/pa/pa.opt:91
++msgid "Generate PA1.0 code."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:44
+-msgid "Use hardware floating point instructions."
++#: config/pa/pa.opt:34 config/pa/pa.opt:95 config/pa/pa.opt:136
++msgid "Generate PA1.1 code."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:48
+-msgid "Use table lookup optimization for small signed integer divisions."
++#: config/pa/pa.opt:38 config/pa/pa.opt:99
++msgid "Generate PA2.0 code (requires binutils 2.10 or later)."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:52
+-msgid "-mcpu=PROCESSOR\t\tUse features of and schedule code for given CPU."
++#: config/pa/pa.opt:46
++msgid "Disable FP regs."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:56
+-msgid "Don't optimize block moves, use memcpy."
++#: config/pa/pa.opt:50
++msgid "Disable indexed addressing."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:68
+-msgid "Use the soft multiply emulation (default)."
++#: config/pa/pa.opt:54
++msgid "Generate fast indirect calls."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:72
+-msgid "Use reorder instructions (swap and byte reversed load/store) (default)."
++#: config/pa/pa.opt:62
++msgid "Assume code will be assembled by GAS."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:76
+-msgid "Use the software emulation for divides (default)."
++#: config/pa/pa.opt:71
++msgid "Enable linker optimizations."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:80
+-msgid "Use the hardware barrel shifter instead of emulation."
++#: config/pa/pa.opt:75
++msgid "Always generate long calls."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:84
+-msgid "Use pattern compare instructions."
++#: config/pa/pa.opt:79
++msgid "Emit long load/store sequences."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:87
+-#, c-format
+-msgid "%qs is deprecated; use -fstack-check"
++#: config/pa/pa.opt:87
++msgid "Disable space regs."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:88
+-msgid "Check for stack overflow at runtime."
++#: config/pa/pa.opt:103
++msgid "Use portable calling conventions."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:92 config/iq2000/iq2000.opt:65
+-msgid "Use GP relative sdata/sbss sections."
++#: config/pa/pa.opt:107
++msgid ""
++"Specify CPU for scheduling purposes.  Valid arguments are 700, 7100, 7100LC, "
++"7200, 7300, and 8000."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:95
+-#, c-format
+-msgid "%qs is deprecated; use -fno-zero-initialized-in-bss"
++#: config/pa/pa.opt:132 config/frv/frv.opt:215
++msgid "Use software floating point."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:96
+-msgid "Clear the BSS to zero and place zero initialized in BSS."
++#: config/pa/pa.opt:140
++msgid "Do not disable space regs."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:100
+-msgid "Use multiply high instructions for high part of 32x32 multiply."
++#: config/pa/pa64-hpux.opt:23
++msgid "Assume code will be linked by GNU ld."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:104
+-msgid "Use hardware floating point conversion instructions."
++#: config/pa/pa64-hpux.opt:27
++msgid "Assume code will be linked by HP ld."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:108
+-msgid "Use hardware floating point square root instruction."
++#: config/vxworks.opt:36
++msgid "Assume the VxWorks RTP environment."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:112
+-msgid "Description for mxl-mode-executable."
++#: config/vxworks.opt:43
++msgid "Assume the VxWorks vThreads environment."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:116
+-msgid "Description for mxl-mode-xmdstub."
++#: config/aarch64/aarch64.opt:40
++msgid "The possible TLS dialects:"
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:120
+-msgid "Description for mxl-mode-bootstrap."
++#: config/aarch64/aarch64.opt:52
++msgid "The code model option names for -mcmodel:"
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:124
+-msgid "Description for mxl-mode-novectors."
++#: config/aarch64/aarch64.opt:69
++msgid "Generate code which uses only the general registers."
+ msgstr ""
+ 
+-#: config/microblaze/microblaze.opt:128
+-msgid "Use hardware prefetch instruction"
++#: config/aarch64/aarch64.opt:73
++msgid "Workaround for ARM Cortex-A53 Erratum number 835769."
+ msgstr ""
+ 
+-#: config/vax/vax.opt:23 config/vax/vax.opt:27
+-msgid "Target DFLOAT double precision code."
++#: config/aarch64/aarch64.opt:77
++msgid "Workaround for ARM Cortex-A53 Erratum number 843419."
+ msgstr ""
+ 
+-#: config/vax/vax.opt:31 config/vax/vax.opt:35
+-msgid "Generate GFLOAT double precision code."
++#: config/aarch64/aarch64.opt:85
++msgid "Specify the code model."
+ msgstr ""
+ 
+-#: config/vax/vax.opt:39
+-msgid "Generate code for GNU assembler (gas)."
++#: config/aarch64/aarch64.opt:89
++msgid "Don't assume that unaligned accesses are handled by the system."
+ msgstr ""
+ 
+-#: config/vax/vax.opt:43
+-msgid "Generate code for UNIX assembler."
++#: config/aarch64/aarch64.opt:97
++msgid "Specify TLS dialect."
+ msgstr ""
+ 
+-#: config/vax/vax.opt:47
+-msgid "Use VAXC structure conventions."
++#: config/aarch64/aarch64.opt:101
++msgid ""
++"Specifies bit size of immediate TLS offsets.  Valid values are 12, 24, 32, "
++"48."
+ msgstr ""
+ 
+-#: config/vax/vax.opt:51
+-msgid "Use new adddi3/subdi3 patterns."
++#: config/aarch64/aarch64.opt:120
++msgid "-march=ARCH\tUse features of architecture ARCH."
+ msgstr ""
+ 
+-#: config/frv/frv.opt:30
+-msgid "Use 4 media accumulators."
++#: config/aarch64/aarch64.opt:124
++msgid "-mcpu=CPU\tUse features of and optimize for CPU."
+ msgstr ""
+ 
+-#: config/frv/frv.opt:34
+-msgid "Use 8 media accumulators."
++#: config/aarch64/aarch64.opt:128
++msgid "-mtune=CPU\tOptimize for CPU."
+ msgstr ""
+ 
+-#: config/frv/frv.opt:38
+-msgid "Enable label alignment optimizations."
++#: config/aarch64/aarch64.opt:132
++msgid "-mabi=ABI\tGenerate code that conforms to the specified ABI."
+ msgstr ""
+ 
+-#: config/frv/frv.opt:42
+-msgid "Dynamically allocate cc registers."
+-msgstr ""
+-
+-#: config/frv/frv.opt:49
+-msgid "Set the cost of branches."
+-msgstr ""
+-
+-#: config/frv/frv.opt:53
+-msgid "Enable conditional execution other than moves/scc."
+-msgstr ""
+-
+-#: config/frv/frv.opt:57
+-msgid "Change the maximum length of conditionally-executed sequences."
+-msgstr ""
+-
+-#: config/frv/frv.opt:61
++#: config/aarch64/aarch64.opt:136
+ msgid ""
+-"Change the number of temporary registers that are available to conditionally-"
+-"executed sequences."
++"-moverride=STRING\tPower users only! Override CPU optimization parameters."
+ msgstr ""
+ 
+-#: config/frv/frv.opt:65
+-msgid "Enable conditional moves."
++#: config/aarch64/aarch64.opt:140
++msgid "Known AArch64 ABIs (for use with the -mabi= option):"
+ msgstr ""
+ 
+-#: config/frv/frv.opt:69
+-msgid "Set the target CPU type."
++#: config/aarch64/aarch64.opt:150
++msgid "PC relative literal loads."
+ msgstr ""
+ 
+-#: config/frv/frv.opt:73
+-msgid "Known FR-V CPUs (for use with the -mcpu= option):"
+-msgstr ""
+-
+-#: config/frv/frv.opt:122
+-msgid "Use fp double instructions."
+-msgstr ""
+-
+-#: config/frv/frv.opt:126
+-msgid "Change the ABI to allow double word insns."
+-msgstr ""
+-
+-#: config/frv/frv.opt:134
+-msgid "Just use icc0/fcc0."
+-msgstr ""
+-
+-#: config/frv/frv.opt:138
+-msgid "Only use 32 FPRs."
+-msgstr ""
+-
+-#: config/frv/frv.opt:142
+-msgid "Use 64 FPRs."
+-msgstr ""
+-
+-#: config/frv/frv.opt:146
+-msgid "Only use 32 GPRs."
+-msgstr ""
+-
+-#: config/frv/frv.opt:150
+-msgid "Use 64 GPRs."
+-msgstr ""
+-
+-#: config/frv/frv.opt:154
+-msgid "Enable use of GPREL for read-only data in FDPIC."
+-msgstr ""
+-
+-#: config/frv/frv.opt:166
+-msgid "Enable PIC support for building libraries."
+-msgstr ""
+-
+-#: config/frv/frv.opt:170
+-msgid "Follow the EABI linkage requirements."
+-msgstr ""
+-
+-#: config/frv/frv.opt:174
+-msgid "Disallow direct calls to global functions."
+-msgstr ""
+-
+-#: config/frv/frv.opt:178
+-msgid "Use media instructions."
+-msgstr ""
+-
+-#: config/frv/frv.opt:182
+-msgid "Use multiply add/subtract instructions."
+-msgstr ""
+-
+-#: config/frv/frv.opt:186
+-msgid "Enable optimizing &&/|| in conditional execution."
+-msgstr ""
+-
+-#: config/frv/frv.opt:190
+-msgid "Enable nested conditional execution optimizations."
+-msgstr ""
+-
+-#: config/frv/frv.opt:195
+-msgid "Do not mark ABI switches in e_flags."
+-msgstr ""
+-
+-#: config/frv/frv.opt:199
+-msgid "Remove redundant membars."
+-msgstr ""
+-
+-#: config/frv/frv.opt:203
+-msgid "Pack VLIW instructions."
+-msgstr ""
+-
+-#: config/frv/frv.opt:207
+-msgid "Enable setting GPRs to the result of comparisons."
+-msgstr ""
+-
+-#: config/frv/frv.opt:211
+-msgid "Change the amount of scheduler lookahead."
+-msgstr ""
+-
+-#: config/frv/frv.opt:219
+-msgid "Assume a large TLS segment."
+-msgstr ""
+-
+-#: config/frv/frv.opt:223
+-msgid "Do not assume a large TLS segment."
+-msgstr ""
+-
+-#: config/frv/frv.opt:228
+-msgid "Cause gas to print tomcat statistics."
+-msgstr ""
+-
+-#: config/frv/frv.opt:233
+-msgid "Link with the library-pic libraries."
+-msgstr ""
+-
+-#: config/frv/frv.opt:237
+-msgid "Allow branches to be packed with other instructions."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:30
+-msgid "Target the AM33 processor."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:34
+-msgid "Target the AM33/2.0 processor."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:38
+-msgid "Target the AM34 processor."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:46
+-msgid "Work around hardware multiply bug."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:55
+-msgid "Enable linker relaxations."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:59
+-msgid "Return pointers in both a0 and d0."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:63
+-msgid "Allow gcc to generate LIW instructions."
+-msgstr ""
+-
+-#: config/mn10300/mn10300.opt:67
+-msgid "Allow gcc to generate the SETLB and Lcc instructions."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:26
+-msgid "Generate code in big-endian mode."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:30
+-msgid "Generate code in little-endian mode."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:34
+-msgid "Use reduced-set registers for register allocation."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:38
+-msgid "Use full-set registers for register allocation."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:42
+-msgid "Generate conditional move instructions."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:46
+-msgid "Generate performance extension instructions."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:50
+-msgid "Generate v3 push25/pop25 instructions."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:54
+-msgid "Generate 16-bit instructions."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:58
+-msgid "Specify the size of each interrupt vector, which must be 4 or 16."
+-msgstr ""
+-
+-#: config/nds32/nds32.opt:62
++#: config/aarch64/aarch64.opt:154
+ msgid ""
+-"Specify the size of each cache block, which must be a power of 2 between 4 "
+-"and 512."
++"When calculating the reciprocal square root approximation, uses one less "
++"step than otherwise, thus reducing latency and precision."
+ msgstr ""
+ 
+-#: config/nds32/nds32.opt:70
+-msgid "Known arch types (for use with the -march= option):"
++#: config/h8300/h8300.opt:23
++msgid "Generate H8S code."
+ msgstr ""
+ 
+-#: config/nds32/nds32.opt:83
+-msgid "Specify the address generation strategy for code model."
++#: config/h8300/h8300.opt:27
++msgid "Generate H8SX code."
+ msgstr ""
+ 
+-#: config/nds32/nds32.opt:87
+-msgid "Known cmodel types (for use with the -mcmodel= option):"
++#: config/h8300/h8300.opt:31
++msgid "Generate H8S/2600 code."
+ msgstr ""
+ 
+-#: config/nds32/nds32.opt:100
+-msgid "Enable constructor/destructor feature."
++#: config/h8300/h8300.opt:35
++msgid "Make integers 32 bits wide."
+ msgstr ""
+ 
+-#: config/nds32/nds32.opt:104
+-msgid "Guide linker to relax instructions."
++#: config/h8300/h8300.opt:42
++msgid "Use registers for argument passing."
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.opt:31
+-msgid "Specify CPU for code generation purposes."
++#: config/h8300/h8300.opt:46
++msgid "Consider access to byte sized memory slow."
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.opt:47
+-msgid "Specify CPU for scheduling purposes."
++#: config/h8300/h8300.opt:50
++msgid "Enable linker relaxing."
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.opt:51
+-msgid "Known IQ2000 CPUs (for use with the -mcpu= option):"
++#: config/h8300/h8300.opt:54
++msgid "Generate H8/300H code."
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.opt:61 config/mips/mips.opt:142
+-msgid "Use ROM instead of RAM."
++#: config/h8300/h8300.opt:58
++msgid "Enable the normal mode."
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.opt:70
+-msgid "No default crt0.o."
++#: config/h8300/h8300.opt:62
++msgid "Use H8/300 alignment rules."
+ msgstr ""
+ 
+-#: config/iq2000/iq2000.opt:74 config/mips/mips.opt:393
+-msgid "Put uninitialized constants in ROM (needs -membedded-data)."
++#: config/h8300/h8300.opt:66
++msgid "Push extended registers on stack in monitor functions."
+ msgstr ""
+ 
+-#: config/c6x/c6x-tables.opt:24
+-msgid "Known C6X ISAs (for use with the -march= option):"
++#: config/h8300/h8300.opt:70
++msgid "Do not push extended registers on stack in monitor functions."
+ msgstr ""
+ 
+-#: config/c6x/c6x.opt:46
+-msgid "Valid arguments for the -msdata= option."
++#: config/nvptx/nvptx.opt:22
++msgid "Generate code for a 32-bit ABI."
+ msgstr ""
+ 
+-#: config/c6x/c6x.opt:59
+-msgid "Compile for the DSBT shared library ABI."
++#: config/nvptx/nvptx.opt:26
++msgid "Generate code for a 64-bit ABI."
+ msgstr ""
+ 
+-#: config/cris/linux.opt:27
+-msgid "Together with -fpic and -fPIC, do not use GOTPLT references."
++#: config/nvptx/nvptx.opt:30
++msgid "Link in code for a __main kernel."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:45
+-msgid "Work around bug in multiplication instruction."
++#: config/nvptx/nvptx.opt:34
++msgid "Optimize partition neutering."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:51
+-msgid "Compile for ETRAX 4 (CRIS v3)."
++#: config/vax/vax.opt:23 config/vax/vax.opt:27
++msgid "Target DFLOAT double precision code."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:56
+-msgid "Compile for ETRAX 100 (CRIS v8)."
++#: config/vax/vax.opt:31 config/vax/vax.opt:35
++msgid "Generate GFLOAT double precision code."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:64
+-msgid "Emit verbose debug information in assembly code."
++#: config/vax/vax.opt:39
++msgid "Generate code for GNU assembler (gas)."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:71
+-msgid "Do not use condition codes from normal instructions."
++#: config/vax/vax.opt:43
++msgid "Generate code for UNIX assembler."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:80
+-msgid "Do not emit addressing modes with side-effect assignment."
++#: config/vax/vax.opt:47
++msgid "Use VAXC structure conventions."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:89
+-msgid "Do not tune stack alignment."
++#: config/vax/vax.opt:51
++msgid "Use new adddi3/subdi3 patterns."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:98
+-msgid "Do not tune writable data alignment."
++#: config/linux.opt:24
++msgid "Use Bionic C library."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:107
+-msgid "Do not tune code and read-only data alignment."
++#: config/linux.opt:28
++msgid "Use GNU C library."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:116
+-msgid "Align code and data to 32 bits."
++#: config/linux.opt:32
++msgid "Use uClibc C library."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:133
+-msgid "Don't align items in code or data."
++#: config/linux.opt:36
++msgid "Use musl C library."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:142
+-msgid "Do not emit function prologue or epilogue."
++#: config/mmix/mmix.opt:24
++msgid "For intrinsics library: pass all parameters in registers."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:149
+-msgid "Use the most feature-enabling options allowed by other options."
++#: config/mmix/mmix.opt:28
++msgid "Use register stack for parameters and return value."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:158
+-msgid "Override -mbest-lib-options."
++#: config/mmix/mmix.opt:32
++msgid "Use call-clobbered registers for parameters and return value."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:165
+-msgid "-march=ARCH\tGenerate code for the specified chip or CPU version."
++#: config/mmix/mmix.opt:37
++msgid "Use epsilon-respecting floating point compare instructions."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:169
+-msgid "-mtune=ARCH\tTune alignment for the specified chip or CPU version."
++#: config/mmix/mmix.opt:41
++msgid "Use zero-extending memory loads, not sign-extending ones."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:173
++#: config/mmix/mmix.opt:45
+ msgid ""
+-"-mmax-stackframe=SIZE\tWarn when a stackframe is larger than the specified "
+-"size."
++"Generate divide results with reminder having the same sign as the divisor "
++"(not the dividend)."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:180
+-msgid ""
+-"Emit traps as \"break 8\", default for CRIS v3 and up.  If disabled, calls "
+-"to abort() are used."
++#: config/mmix/mmix.opt:49
++msgid "Prepend global symbols with \":\" (for use with PREFIX)."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:184
+-msgid ""
+-"Emit checks causing \"break 8\" instructions to execute when applying atomic "
+-"builtins on misaligned memory."
++#: config/mmix/mmix.opt:53
++msgid "Do not provide a default start-address 0x100 of the program."
+ msgstr ""
+ 
+-#: config/cris/cris.opt:188
+-msgid ""
+-"Handle atomic builtins that may be applied to unaligned data by calling "
+-"library functions. Overrides -mtrap-unaligned-atomic."
++#: config/mmix/mmix.opt:57
++msgid "Link to emit program in ELF format (rather than mmo)."
+ msgstr ""
+ 
+-#: config/sh/superh.opt:6
+-msgid "Board name [and memory region]."
++#: config/mmix/mmix.opt:61
++msgid "Use P-mnemonics for branches statically predicted as taken."
+ msgstr ""
+ 
+-#: config/sh/superh.opt:10
+-msgid "Runtime name."
++#: config/mmix/mmix.opt:65
++msgid "Don't use P-mnemonics for branches."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:48
+-msgid "Generate SH1 code."
++#: config/mmix/mmix.opt:79
++msgid "Use addresses that allocate global registers."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:52
+-msgid "Generate SH2 code."
++#: config/mmix/mmix.opt:83
++msgid "Do not use addresses that allocate global registers."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:56
+-msgid "Generate default double-precision SH2a-FPU code."
++#: config/mmix/mmix.opt:87
++msgid "Generate a single exit point for each function."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:60
+-msgid "Generate SH2a FPU-less code."
++#: config/mmix/mmix.opt:91
++msgid "Do not generate a single exit point for each function."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:64
+-msgid "Generate default single-precision SH2a-FPU code."
++#: config/mmix/mmix.opt:95
++msgid "Set start-address of the program."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:68
+-msgid "Generate only single-precision SH2a-FPU code."
++#: config/mmix/mmix.opt:99
++msgid "Set start-address of data."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:72
+-msgid "Generate SH2e code."
++#: config/fr30/fr30.opt:23
++msgid "Assume small address space."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:76
+-msgid "Generate SH3 code."
++#: config/pdp11/pdp11.opt:23
++msgid "Generate code for an 11/10."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:80
+-msgid "Generate SH3e code."
++#: config/pdp11/pdp11.opt:27
++msgid "Generate code for an 11/40."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:84
+-msgid "Generate SH4 code."
++#: config/pdp11/pdp11.opt:31
++msgid "Generate code for an 11/45."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:88
+-msgid "Generate SH4-100 code."
++#: config/pdp11/pdp11.opt:35
++msgid "Return floating-point results in ac0 (fr0 in Unix assembler syntax)."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:92
+-msgid "Generate SH4-200 code."
++#: config/pdp11/pdp11.opt:39
++msgid "Do not use inline patterns for copying memory."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:98
+-msgid "Generate SH4-300 code."
++#: config/pdp11/pdp11.opt:43
++msgid "Use inline patterns for copying memory."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:102
+-msgid "Generate SH4 FPU-less code."
++#: config/pdp11/pdp11.opt:47
++msgid "Do not pretend that branches are expensive."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:106
+-msgid "Generate SH4-100 FPU-less code."
++#: config/pdp11/pdp11.opt:51
++msgid "Pretend that branches are expensive."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:110
+-msgid "Generate SH4-200 FPU-less code."
++#: config/pdp11/pdp11.opt:55
++msgid "Use the DEC assembler syntax."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:114
+-msgid "Generate SH4-300 FPU-less code."
++#: config/pdp11/pdp11.opt:59
++msgid "Use 32 bit float."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:118
+-msgid "Generate code for SH4 340 series (MMU/FPU-less)."
++#: config/pdp11/pdp11.opt:63
++msgid "Use 64 bit float."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:123
+-msgid "Generate code for SH4 400 series (MMU/FPU-less)."
++#: config/pdp11/pdp11.opt:67 config/frv/frv.opt:158
++#: config/rs6000/rs6000.opt:177
++msgid "Use hardware floating point."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:128
+-msgid "Generate code for SH4 500 series (FPU-less)."
++#: config/pdp11/pdp11.opt:71
++msgid "Use 16 bit int."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:133
+-msgid "Generate default single-precision SH4 code."
++#: config/pdp11/pdp11.opt:75
++msgid "Use 32 bit int."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:137
+-msgid "Generate default single-precision SH4-100 code."
++#: config/pdp11/pdp11.opt:79 config/rs6000/rs6000.opt:173
++msgid "Do not use hardware floating point."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:141
+-msgid "Generate default single-precision SH4-200 code."
++#: config/pdp11/pdp11.opt:83
++msgid "Target has split I&D."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:145
+-msgid "Generate default single-precision SH4-300 code."
++#: config/pdp11/pdp11.opt:87
++msgid "Use UNIX assembler syntax."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:149
+-msgid "Generate only single-precision SH4 code."
++#: config/frv/frv.opt:30
++msgid "Use 4 media accumulators."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:153
+-msgid "Generate only single-precision SH4-100 code."
++#: config/frv/frv.opt:34
++msgid "Use 8 media accumulators."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:157
+-msgid "Generate only single-precision SH4-200 code."
++#: config/frv/frv.opt:38
++msgid "Enable label alignment optimizations."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:161
+-msgid "Generate only single-precision SH4-300 code."
++#: config/frv/frv.opt:42
++msgid "Dynamically allocate cc registers."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:165
+-msgid "Generate SH4a code."
++#: config/frv/frv.opt:49
++msgid "Set the cost of branches."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:169
+-msgid "Generate SH4a FPU-less code."
++#: config/frv/frv.opt:53
++msgid "Enable conditional execution other than moves/scc."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:173
+-msgid "Generate default single-precision SH4a code."
++#: config/frv/frv.opt:57
++msgid "Change the maximum length of conditionally-executed sequences."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:177
+-msgid "Generate only single-precision SH4a code."
++#: config/frv/frv.opt:61
++msgid ""
++"Change the number of temporary registers that are available to conditionally-"
++"executed sequences."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:181
+-msgid "Generate SH4al-dsp code."
++#: config/frv/frv.opt:65
++msgid "Enable conditional moves."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:185
+-msgid "Generate 32-bit SHmedia code."
++#: config/frv/frv.opt:69
++msgid "Set the target CPU type."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:189
+-msgid "Generate 32-bit FPU-less SHmedia code."
++#: config/frv/frv.opt:73
++msgid "Known FR-V CPUs (for use with the -mcpu= option):"
+ msgstr ""
+ 
+-#: config/sh/sh.opt:193
+-msgid "Generate 64-bit SHmedia code."
++#: config/frv/frv.opt:122
++msgid "Use fp double instructions."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:197
+-msgid "Generate 64-bit FPU-less SHmedia code."
++#: config/frv/frv.opt:126
++msgid "Change the ABI to allow double word insns."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:201
+-msgid "Generate SHcompact code."
++#: config/frv/frv.opt:130 config/bfin/bfin.opt:90
++msgid "Enable Function Descriptor PIC mode."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:205
+-msgid "Generate FPU-less SHcompact code."
++#: config/frv/frv.opt:134
++msgid "Just use icc0/fcc0."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:217
+-msgid "Generate code in big endian mode."
++#: config/frv/frv.opt:138
++msgid "Only use 32 FPRs."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:221
+-msgid "Generate 32-bit offsets in switch tables."
++#: config/frv/frv.opt:142
++msgid "Use 64 FPRs."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:225
+-msgid "Generate bit instructions."
++#: config/frv/frv.opt:146
++msgid "Only use 32 GPRs."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:229
+-msgid "Cost to assume for a branch insn."
++#: config/frv/frv.opt:150
++msgid "Use 64 GPRs."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:233
+-msgid "Assume that zero displacement conditional branches are fast."
++#: config/frv/frv.opt:154
++msgid "Enable use of GPREL for read-only data in FDPIC."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:236 config/sh/sh.opt:240
+-#, c-format
+-msgid "%qs is deprecated and has no effect"
++#: config/frv/frv.opt:162 config/bfin/bfin.opt:94
++msgid "Enable inlining of PLT in function calls."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:237
+-msgid "Enable cbranchdi4 pattern."
++#: config/frv/frv.opt:166
++msgid "Enable PIC support for building libraries."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:241
+-msgid "Emit cmpeqdi_t pattern even when -mcbranchdi is in effect."
++#: config/frv/frv.opt:170
++msgid "Follow the EABI linkage requirements."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:245
+-msgid "Force the usage of delay slots for conditional branches."
++#: config/frv/frv.opt:174
++msgid "Disallow direct calls to global functions."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:249
+-msgid "Enable SH5 cut2 workaround."
++#: config/frv/frv.opt:178
++msgid "Use media instructions."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:253
+-msgid "Align doubles at 64-bit boundaries."
++#: config/frv/frv.opt:182
++msgid "Use multiply add/subtract instructions."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:257
+-msgid ""
+-"Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, "
+-"inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table."
++#: config/frv/frv.opt:186
++msgid "Enable optimizing &&/|| in conditional execution."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:261
+-msgid "Specify name for 32 bit signed division function."
++#: config/frv/frv.opt:190
++msgid "Enable nested conditional execution optimizations."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:265
+-msgid "Generate ELF FDPIC code."
++#: config/frv/frv.opt:195
++msgid "Do not mark ABI switches in e_flags."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:269
+-msgid ""
+-"Enable the use of 64-bit floating point registers in fmov instructions.  See "
+-"-mdalign if 64-bit alignment is required."
++#: config/frv/frv.opt:199
++msgid "Remove redundant membars."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:277
+-msgid "Cost to assume for gettr insn."
++#: config/frv/frv.opt:203
++msgid "Pack VLIW instructions."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:281 config/sh/sh.opt:331
+-msgid "Follow Renesas (formerly Hitachi) / SuperH calling conventions."
++#: config/frv/frv.opt:207
++msgid "Enable setting GPRs to the result of comparisons."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:285
+-msgid "Increase the IEEE compliance for floating-point comparisons."
++#: config/frv/frv.opt:211
++msgid "Change the amount of scheduler lookahead."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:289
+-msgid "Enable the use of the indexed addressing mode for SHmedia32/SHcompact."
++#: config/frv/frv.opt:219
++msgid "Assume a large TLS segment."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:293
+-msgid ""
+-"inline code to invalidate instruction cache entries after setting up nested "
+-"function trampolines."
++#: config/frv/frv.opt:223
++msgid "Do not assume a large TLS segment."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:297
+-msgid "Assume symbols might be invalid."
++#: config/frv/frv.opt:228
++msgid "Cause gas to print tomcat statistics."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:301 config/arc/arc.opt:209
+-msgid "Annotate assembler instructions with estimated addresses."
++#: config/frv/frv.opt:233
++msgid "Link with the library-pic libraries."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:305
+-msgid "Generate code in little endian mode."
++#: config/frv/frv.opt:237
++msgid "Allow branches to be packed with other instructions."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:309
+-msgid "Mark MAC register as call-clobbered."
++#: config/tilegx/tilegx.opt:30
++msgid "Known TILE-Gx CPUs (for use with the -mcpu= option):"
+ msgstr ""
+ 
+-#: config/sh/sh.opt:315
+-msgid "Make structs a multiple of 4 bytes (warning: ABI altered)."
++#: config/tilegx/tilegx.opt:37
++msgid "Compile with 32 bit longs and pointers."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:319
+-msgid "Emit function-calls using global offset table when generating PIC."
++#: config/tilegx/tilegx.opt:41
++msgid "Compile with 64 bit longs and pointers."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:323
+-msgid "Assume pt* instructions won't trap"
++#: config/tilegx/tilegx.opt:53
++msgid "Use given TILE-Gx code model."
+ msgstr ""
+ 
+-#: config/sh/sh.opt:327
+-msgid "Shorten address references during linking."
+-msgstr ""
+-
+-#: config/sh/sh.opt:335
+-msgid "Deprecated.  Use -matomic= instead to select the atomic model."
+-msgstr ""
+-
+-#: config/sh/sh.opt:339
+-msgid "Specify the model for atomic operations."
+-msgstr ""
+-
+-#: config/sh/sh.opt:343
+-msgid "Use tas.b instruction for __atomic_test_and_set."
+-msgstr ""
+-
+-#: config/sh/sh.opt:347
+-msgid "Deprecated.  Use -Os instead."
+-msgstr ""
+-
+-#: config/sh/sh.opt:351
+-msgid "Cost to assume for a multiply insn."
+-msgstr ""
+-
+-#: config/sh/sh.opt:355
+-msgid ""
+-"Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate "
+-"if the inline code would not work in user mode."
+-msgstr ""
+-
+-#: config/sh/sh.opt:361
+-msgid "Pretend a branch-around-a-move is a conditional move."
+-msgstr ""
+-
+-#: config/sh/sh.opt:365
+-msgid "Enable the use of the fsca instruction."
+-msgstr ""
+-
+-#: config/sh/sh.opt:369
+-msgid "Enable the use of the fsrra instruction."
+-msgstr ""
+-
+-#: config/sh/sh.opt:373
+-msgid "Use LRA instead of reload (transitional)."
+-msgstr ""
+-
+-#: config/fr30/fr30.opt:23
+-msgid "Assume small address space."
+-msgstr ""
+-
+ #: config/mep/mep.opt:23
+ msgid "Enable absolute difference instructions."
+ msgstr ""
+@@ -12827,839 +10722,914 @@
+ msgid "Variables this size and smaller go in the tiny section. (default 4)."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:32
+-msgid "-mabi=ABI\tGenerate code that conforms to the given ABI."
++#: config/lynx.opt:23
++msgid "Support legacy multi-threading."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:36
+-msgid "Known MIPS ABIs (for use with the -mabi= option):"
++#: config/lynx.opt:27
++msgid "Use shared libraries."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:55
+-msgid "Generate code that can be used in SVR4-style dynamic objects."
++#: config/lynx.opt:31
++msgid "Support multi-threading."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:59
+-msgid "Use PMC-style 'mad' instructions."
++#: config/stormy16/stormy16.opt:24
++msgid "Provide libraries for the simulator."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:63
+-msgid "Use integer madd/msub instructions."
++#: config/bfin/bfin.opt:48
++msgid "Omit frame pointer for leaf functions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:67
+-msgid "-march=ISA\tGenerate code for the given ISA."
++#: config/bfin/bfin.opt:52
++msgid "Program is entirely located in low 64k of memory."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:71
++#: config/bfin/bfin.opt:56
+ msgid ""
+-"-mbranch-cost=COST\tSet the cost of branches to roughly COST instructions."
++"Work around a hardware anomaly by adding a number of NOPs before a CSYNC or "
++"SSYNC instruction."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:75
+-msgid "Use Branch Likely instructions, overriding the architecture default."
++#: config/bfin/bfin.opt:61
++msgid "Avoid speculative loads to work around a hardware anomaly."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:79
+-msgid "Switch on/off MIPS16 ASE on alternating functions for compiler testing."
++#: config/bfin/bfin.opt:65
++msgid "Enabled ID based shared library."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:83
+-msgid "Trap on integer divide by zero."
+-msgstr ""
+-
+-#: config/mips/mips.opt:87
++#: config/bfin/bfin.opt:69
+ msgid ""
+-"-mcode-readable=SETTING\tSpecify when instructions are allowed to access "
+-"code."
++"Generate code that won't be linked against any other ID shared libraries, "
++"but may be used as a shared library."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:91
+-msgid "Valid arguments to -mcode-readable=:"
++#: config/bfin/bfin.opt:86
++msgid "Link with the fast floating-point library."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:104
+-msgid "Use branch-and-break sequences to check for integer divide by zero."
++#: config/bfin/bfin.opt:98
++msgid "Do stack checking using bounds in L1 scratch memory."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:108
+-msgid "Use trap instructions to check for integer divide by zero."
++#: config/bfin/bfin.opt:102
++msgid "Enable multicore support."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:112
+-msgid "Allow the use of MDMX instructions."
++#: config/bfin/bfin.opt:106
++msgid "Build for Core A."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:116
+-msgid ""
+-"Allow hardware floating-point instructions to cover both 32-bit and 64-bit "
+-"operations."
++#: config/bfin/bfin.opt:110
++msgid "Build for Core B."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:120
+-msgid "Use MIPS-DSP instructions."
++#: config/bfin/bfin.opt:114
++msgid "Build for SDRAM."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:124
+-msgid "Use MIPS-DSP REV 2 instructions."
++#: config/bfin/bfin.opt:118
++msgid "Assume ICPLBs are enabled at runtime."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:146
+-msgid "Use Enhanced Virtual Addressing instructions."
++#: config/cris/cris.opt:45
++msgid "Work around bug in multiplication instruction."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:150
+-msgid "Use NewABI-style %reloc() assembly operators."
++#: config/cris/cris.opt:51
++msgid "Compile for ETRAX 4 (CRIS v3)."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:154
+-msgid "Use -G for data that is not defined by the current object."
++#: config/cris/cris.opt:56
++msgid "Compile for ETRAX 100 (CRIS v8)."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:158
+-msgid "Work around certain 24K errata."
++#: config/cris/cris.opt:64
++msgid "Emit verbose debug information in assembly code."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:162
+-msgid "Work around certain R4000 errata."
++#: config/cris/cris.opt:71
++msgid "Do not use condition codes from normal instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:166
+-msgid "Work around certain R4400 errata."
++#: config/cris/cris.opt:80
++msgid "Do not emit addressing modes with side-effect assignment."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:170
+-msgid "Work around certain RM7000 errata."
++#: config/cris/cris.opt:89
++msgid "Do not tune stack alignment."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:174
+-msgid "Work around certain R10000 errata."
++#: config/cris/cris.opt:98
++msgid "Do not tune writable data alignment."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:178
+-msgid "Work around errata for early SB-1 revision 2 cores."
++#: config/cris/cris.opt:107
++msgid "Do not tune code and read-only data alignment."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:182
+-msgid "Work around certain VR4120 errata."
++#: config/cris/cris.opt:116
++msgid "Align code and data to 32 bits."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:186
+-msgid "Work around VR4130 mflo/mfhi errata."
++#: config/cris/cris.opt:133
++msgid "Don't align items in code or data."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:190
+-msgid "Work around an early 4300 hardware bug."
++#: config/cris/cris.opt:142
++msgid "Do not emit function prologue or epilogue."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:194
+-msgid "FP exceptions are enabled."
++#: config/cris/cris.opt:149
++msgid "Use the most feature-enabling options allowed by other options."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:198
+-msgid "Use 32-bit floating-point registers."
++#: config/cris/cris.opt:158
++msgid "Override -mbest-lib-options."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:202
+-msgid "Conform to the o32 FPXX ABI."
++#: config/cris/cris.opt:165
++msgid "-march=ARCH\tGenerate code for the specified chip or CPU version."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:206
+-msgid "Use 64-bit floating-point registers."
++#: config/cris/cris.opt:169
++msgid "-mtune=ARCH\tTune alignment for the specified chip or CPU version."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:210
++#: config/cris/cris.opt:173
+ msgid ""
+-"-mflush-func=FUNC\tUse FUNC to flush the cache before calling stack "
+-"trampolines."
++"-mmax-stackframe=SIZE\tWarn when a stackframe is larger than the specified "
++"size."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:214
+-msgid "-mabs=MODE\tSelect the IEEE 754 ABS/NEG instruction execution mode."
++#: config/cris/cris.opt:180
++msgid ""
++"Emit traps as \"break 8\", default for CRIS v3 and up.  If disabled, calls "
++"to abort() are used."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:218
+-msgid "-mnan=ENCODING\tSelect the IEEE 754 NaN data encoding."
++#: config/cris/cris.opt:184
++msgid ""
++"Emit checks causing \"break 8\" instructions to execute when applying atomic "
++"builtins on misaligned memory."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:222
++#: config/cris/cris.opt:188
+ msgid ""
+-"Known MIPS IEEE 754 settings (for use with the -mabs= and -mnan= options):"
++"Handle atomic builtins that may be applied to unaligned data by calling "
++"library functions. Overrides -mtrap-unaligned-atomic."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:232
+-msgid "Use 32-bit general registers."
++#: config/cris/linux.opt:27
++msgid "Together with -fpic and -fPIC, do not use GOTPLT references."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:236
+-msgid "Use 64-bit general registers."
++#: config/rs6000/rs6000-tables.opt:24
++msgid "Known CPUs (for use with the -mcpu= and -mtune= options):"
+ msgstr ""
+ 
+-#: config/mips/mips.opt:240
+-msgid "Use GP-relative addressing to access small data."
++#: config/rs6000/rs6000.opt:109
++msgid "Use PowerPC-64 instruction set."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:244
+-msgid ""
+-"When generating -mabicalls code, allow executables to use PLTs and copy "
+-"relocations."
++#: config/rs6000/rs6000.opt:113
++msgid "Use PowerPC General Purpose group optional instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:248
+-msgid "Allow the use of hardware floating-point ABI and instructions."
++#: config/rs6000/rs6000.opt:117
++msgid "Use PowerPC Graphics group optional instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:252
+-msgid "Generate code that is link-compatible with MIPS16 and microMIPS code."
++#: config/rs6000/rs6000.opt:121
++msgid "Use PowerPC V2.01 single field mfcr instruction."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:256
+-msgid "An alias for minterlink-compressed provided for backward-compatibility."
++#: config/rs6000/rs6000.opt:125
++msgid "Use PowerPC V2.02 popcntb instruction."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:260
+-msgid "-mipsN\tGenerate code for ISA level N."
++#: config/rs6000/rs6000.opt:129
++msgid "Use PowerPC V2.02 floating point rounding instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:264
+-msgid "Generate MIPS16 code."
++#: config/rs6000/rs6000.opt:133
++msgid "Use PowerPC V2.05 compare bytes instruction."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:268
+-msgid "Use MIPS-3D instructions."
++#: config/rs6000/rs6000.opt:137
++msgid ""
++"Use extended PowerPC V2.05 move floating point to/from GPR instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:272
+-msgid "Use ll, sc and sync instructions."
++#: config/rs6000/rs6000.opt:141
++msgid "Use AltiVec instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:276
+-msgid "Use -G for object-local data."
++#: config/rs6000/rs6000.opt:145
++msgid "Generate Altivec instructions using little-endian element order."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:280
+-msgid "Use indirect calls."
++#: config/rs6000/rs6000.opt:149
++msgid "Generate Altivec instructions using big-endian element order."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:284
+-msgid "Use a 32-bit long type."
++#: config/rs6000/rs6000.opt:153
++msgid "Use decimal floating point instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:288
+-msgid "Use a 64-bit long type."
++#: config/rs6000/rs6000.opt:157
++msgid "Use 4xx half-word multiply instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:292
+-msgid "Pass the address of the ra save location to _mcount in $12."
++#: config/rs6000/rs6000.opt:161
++msgid "Use 4xx string-search dlmzb instruction."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:296
+-msgid "Don't optimize block moves."
++#: config/rs6000/rs6000.opt:165
++msgid "Generate load/store multiple instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:300
+-msgid "Use microMIPS instructions."
++#: config/rs6000/rs6000.opt:169
++msgid "Generate string instructions for block moves."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:304
+-msgid "Allow the use of MT instructions."
++#: config/rs6000/rs6000.opt:181
++msgid "Use PowerPC V2.06 popcntd instruction."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:308
+-msgid "Prevent the use of all floating-point operations."
++#: config/rs6000/rs6000.opt:185
++msgid ""
++"Under -ffast-math, generate a FRIZ instruction for (double)(long long) "
++"conversions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:312
+-msgid "Use MCU instructions."
++#: config/rs6000/rs6000.opt:193
++msgid "Use vector/scalar (VSX) instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:316
+-msgid "Do not use a cache-flushing function before calling stack trampolines."
++#: config/rs6000/rs6000.opt:240
++msgid "Do not generate load/store with update instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:320
+-msgid "Do not use MDMX instructions."
++#: config/rs6000/rs6000.opt:244
++msgid "Generate load/store with update instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:324
+-msgid "Generate normal-mode code."
++#: config/rs6000/rs6000.opt:252
++msgid "Avoid generation of indexed load/store instructions when possible."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:328
+-msgid "Do not use MIPS-3D instructions."
++#: config/rs6000/rs6000.opt:256
++msgid "Mark __tls_get_addr calls with argument info."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:332
+-msgid "Use paired-single floating-point instructions."
++#: config/rs6000/rs6000.opt:263
++msgid "Schedule the start and end of the procedure."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:336
+-msgid ""
+-"-mr10k-cache-barrier=SETTING\tSpecify when r10k cache barriers should be "
+-"inserted."
++#: config/rs6000/rs6000.opt:267
++msgid "Return all structures in memory (AIX default)."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:340
+-msgid "Valid arguments to -mr10k-cache-barrier=:"
++#: config/rs6000/rs6000.opt:271
++msgid "Return small structures in registers (SVR4 default)."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:353
+-msgid "Try to allow the linker to turn PIC calls into direct calls."
++#: config/rs6000/rs6000.opt:275
++msgid "Conform more closely to IBM XLC semantics."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:357
++#: config/rs6000/rs6000.opt:279 config/rs6000/rs6000.opt:283
+ msgid ""
+-"When generating -mabicalls code, make the code suitable for use in shared "
+-"libraries."
++"Generate software reciprocal divide and square root for better throughput."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:361
++#: config/rs6000/rs6000.opt:287
++msgid "Assume that the reciprocal estimate instructions provide more accuracy."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:291
++msgid "Do not place floating point constants in TOC."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:295
++msgid "Place floating point constants in TOC."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:299
++msgid "Do not place symbol+offset constants in TOC."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:303
++msgid "Place symbol+offset constants in TOC."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:314
++msgid "Use only one TOC entry per procedure."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:318
++msgid "Put everything in the regular TOC."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:322
++msgid "Generate VRSAVE instructions when generating AltiVec code."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:326
++msgid "Deprecated option.  Use -mno-vrsave instead."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:330
++msgid "Deprecated option.  Use -mvrsave instead."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:334
+ msgid ""
+-"Restrict the use of hardware floating-point instructions to 32-bit "
+-"operations."
++"Specify how many bytes should be moved inline before calling out to memcpy/"
++"memmove."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:365
+-msgid "Use SmartMIPS instructions."
++#: config/rs6000/rs6000.opt:338
++msgid "Generate isel instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:369
+-msgid "Prevent the use of all hardware floating-point instructions."
++#: config/rs6000/rs6000.opt:342
++msgid "Deprecated option.  Use -mno-isel instead."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:373
+-msgid "Optimize lui/addiu address loads."
++#: config/rs6000/rs6000.opt:346
++msgid "Deprecated option.  Use -misel instead."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:377
+-msgid "Assume all symbols have 32-bit values."
++#: config/rs6000/rs6000.opt:350
++msgid "Generate SPE SIMD instructions on E500."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:381
+-msgid "Use synci instruction to invalidate i-cache."
++#: config/rs6000/rs6000.opt:354
++msgid "Generate PPC750CL paired-single instructions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:389
+-msgid "-mtune=PROCESSOR\tOptimize the output for PROCESSOR."
++#: config/rs6000/rs6000.opt:358
++msgid "Deprecated option.  Use -mno-spe instead."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:397
+-msgid "Use Virtualization Application Specific instructions."
++#: config/rs6000/rs6000.opt:362
++msgid "Deprecated option.  Use -mspe instead."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:401
+-msgid "Use eXtended Physical Address (XPA) instructions."
++#: config/rs6000/rs6000.opt:366
++msgid "-mdebug=\tEnable debug output."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:405
+-msgid "Perform VR4130-specific alignment optimizations."
++#: config/rs6000/rs6000.opt:370
++msgid "Use the AltiVec ABI extensions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:409
+-msgid "Lift restrictions on GOT size."
++#: config/rs6000/rs6000.opt:374
++msgid "Do not use the AltiVec ABI extensions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:413
+-msgid "Enable use of odd-numbered single-precision registers."
++#: config/rs6000/rs6000.opt:378
++msgid "Use the SPE ABI extensions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:417
+-msgid "Optimize frame header."
++#: config/rs6000/rs6000.opt:382
++msgid "Do not use the SPE ABI extensions."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:424
+-msgid "Enable load/store bonding."
++#: config/rs6000/rs6000.opt:386
++msgid "Use the ELFv1 ABI."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:428
+-msgid "Specify the compact branch usage policy."
++#: config/rs6000/rs6000.opt:390
++msgid "Use the ELFv2 ABI."
+ msgstr ""
+ 
+-#: config/mips/mips.opt:432
+-msgid "Policies available for use with -mcompact-branches=:"
++#: config/rs6000/rs6000.opt:397
++msgid "using darwin64 ABI"
+ msgstr ""
+ 
+-#: config/mips/mips-tables.opt:24
+-msgid "Known MIPS CPUs (for use with the -march= and -mtune= options):"
++#: config/rs6000/rs6000.opt:400
++msgid "using old darwin ABI"
+ msgstr ""
+ 
+-#: config/mips/mips-tables.opt:28
+-msgid "Known MIPS ISA levels (for use with the -mips option):"
++#: config/rs6000/rs6000.opt:403
++msgid "using IEEE extended precision long double"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.opt:30
+-msgid "Known TILE-Gx CPUs (for use with the -mcpu= option):"
++#: config/rs6000/rs6000.opt:406
++msgid "using IBM extended precision long double"
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.opt:37
+-msgid "Compile with 32 bit longs and pointers."
++#: config/rs6000/rs6000.opt:410
++msgid "-mcpu=\tUse features of and schedule code for given CPU."
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.opt:41
+-msgid "Compile with 64 bit longs and pointers."
++#: config/rs6000/rs6000.opt:414
++msgid "-mtune=\tSchedule code for given CPU."
+ msgstr ""
+ 
+-#: config/tilegx/tilegx.opt:53
+-msgid "Use given TILE-Gx code model."
++#: config/rs6000/rs6000.opt:418
++msgid "-mtraceback=\tSelect full, part, or no traceback table."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:26
+-msgid "Compile code for big endian mode."
++#: config/rs6000/rs6000.opt:434
++msgid "Avoid all range limits on call instructions."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:30
+-msgid "Compile code for little endian mode.  This is the default."
++#: config/rs6000/rs6000.opt:438
++msgid "Generate Cell microcode."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:34
+-msgid ""
+-"Disable ARCompact specific pass to generate conditional execution "
+-"instructions."
++#: config/rs6000/rs6000.opt:442
++msgid "Warn when a Cell microcoded instruction is emitted."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:38
+-msgid "Generate ARCompact 32-bit code for ARC600 processor."
++#: config/rs6000/rs6000.opt:446
++msgid "Warn about deprecated 'vector long ...' AltiVec type usage."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:42
+-msgid "Same as -mA6."
++#: config/rs6000/rs6000.opt:450
++msgid "-mfloat-gprs=\tSelect GPR floating point method."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:46
+-msgid "Generate ARCompact 32-bit code for ARC601 processor."
++#: config/rs6000/rs6000.opt:454
++msgid "Valid arguments to -mfloat-gprs=:"
+ msgstr ""
+ 
+-#: config/arc/arc.opt:50
+-msgid "Generate ARCompact 32-bit code for ARC700 processor."
++#: config/rs6000/rs6000.opt:470
++msgid "-mlong-double-<n>\tSpecify size of long double (64 or 128 bits)."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:54
+-msgid "Same as -mA7."
++#: config/rs6000/rs6000.opt:474
++msgid "Enable Local Register Allocation."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:58
+-msgid ""
+-"-mmpy-option={0,1,2,3,4,5,6,7,8,9} Compile ARCv2 code with a multiplier "
+-"design option.  Option 2 is default on."
++#: config/rs6000/rs6000.opt:478
++msgid "Determine which dependences between insns are considered costly."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:62
+-msgid "Enable DIV-REM instructions for ARCv2."
++#: config/rs6000/rs6000.opt:482
++msgid "Specify which post scheduling nop insertion scheme to apply."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:66
+-msgid "Enable code density instructions for ARCv2."
++#: config/rs6000/rs6000.opt:486
++msgid "Specify alignment of structure fields default/natural."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:70
+-msgid "Tweak register allocation to help 16-bit instruction generation."
++#: config/rs6000/rs6000.opt:490
++msgid "Valid arguments to -malign-:"
+ msgstr ""
+ 
+-#: config/arc/arc.opt:80
+-msgid "Use ordinarily cached memory accesses for volatile references."
++#: config/rs6000/rs6000.opt:500
++msgid "Specify scheduling priority for dispatch slot restricted insns."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:84
+-msgid "Enable cache bypass for volatile references."
++#: config/rs6000/rs6000.opt:504
++msgid "Single-precision floating point unit."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:88
+-msgid "Generate instructions supported by barrel shifter."
++#: config/rs6000/rs6000.opt:508
++msgid "Double-precision floating point unit."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:92
+-msgid "Generate norm instruction."
++#: config/rs6000/rs6000.opt:512
++msgid "Floating point unit does not support divide & sqrt."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:96
+-msgid "Generate swap instruction."
++#: config/rs6000/rs6000.opt:516
++msgid "-mfpu=\tSpecify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:100
+-msgid "Generate mul64 and mulu64 instructions."
++#: config/rs6000/rs6000.opt:538
++msgid "Specify Xilinx FPU."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:104
+-msgid "Do not generate mpy instructions for ARC700."
++#: config/rs6000/rs6000.opt:542
++msgid ""
++"Use/do not use r11 to hold the static link in calls to functions via "
++"pointers."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:108
++#: config/rs6000/rs6000.opt:546
+ msgid ""
+-"Generate Extended arithmetic instructions.  Currently only divaw, adds, subs "
+-"and sat16 are supported."
++"Control whether we save the TOC in the prologue for indirect calls or "
++"generate the save inline."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:112
++#: config/rs6000/rs6000.opt:550
++msgid "Allow 128-bit integers in VSX registers."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:554
+ msgid ""
+-"Dummy flag. This is the default unless FPX switches are provided explicitly."
++"Fuse certain integer operations together for better performance on power8."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:116
+-msgid "Generate call insns as register indirect calls."
++#: config/rs6000/rs6000.opt:558
++msgid "Allow sign extension in fusion operations."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:120
+-msgid "Do no generate BRcc instructions in arc_reorg."
++#: config/rs6000/rs6000.opt:562
++msgid "Use/do not use vector and scalar instructions added in ISA 2.07."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:124
+-msgid ""
+-"Generate sdata references.  This is the default, unless you compile for PIC."
++#: config/rs6000/rs6000.opt:566
++msgid "Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:128
+-msgid "Do not generate millicode thunks (needed only with -Os)."
++#: config/rs6000/rs6000.opt:570
++msgid "Use ISA 2.07 direct move between GPR & VSX register instructions."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:132 config/arc/arc.opt:136
+-msgid "FPX: Generate Single Precision FPX (compact) instructions."
++#: config/rs6000/rs6000.opt:574
++msgid "Use ISA 2.07 transactional memory (HTM) instructions."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:140
+-msgid "FPX: Generate Single Precision FPX (fast) instructions."
++#: config/rs6000/rs6000.opt:578
++msgid "Generate the quad word memory instructions (lq/stq)."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:144
++#: config/rs6000/rs6000.opt:582
++msgid "Generate the quad word memory atomic instructions (lqarx/stqcx)."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:586
+ msgid ""
+-"FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions."
++"Generate aggregate parameter passing code with at most 64-bit alignment."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:148 config/arc/arc.opt:152
+-msgid "FPX: Generate Double Precision FPX (compact) instructions."
++#: config/rs6000/rs6000.opt:590
++msgid "Allow double variables in upper registers with -mcpu=power7 or -mvsx."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:156
+-msgid "FPX: Generate Double Precision FPX (fast) instructions."
++#: config/rs6000/rs6000.opt:594
++msgid ""
++"Allow float variables in upper registers with -mcpu=power8 or -mpower8-"
++"vector."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:160
+-msgid "Disable LR and SR instructions from using FPX extension aux registers."
++#: config/rs6000/rs6000.opt:598
++msgid "Allow float/double variables in upper registers if cpu allows it."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:164
+-msgid ""
+-"Enable generation of ARC SIMD instructions via target-specific builtins."
++#: config/rs6000/rs6000.opt:602
++msgid "Analyze and remove doubleword swaps from VSX computations."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:168
+-msgid "-mcpu=CPU\tCompile code for ARC variant CPU."
++#: config/rs6000/rs6000.opt:606
++msgid "Fuse certain operations together for better performance on power9."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:205
++#: config/rs6000/rs6000.opt:610
++msgid "Use/do not use certain scalar instructions added in ISA 3.0."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:614
++msgid "Use/do not use vector instructions added in ISA 3.0."
++msgstr ""
++
++#: config/rs6000/rs6000.opt:618
+ msgid ""
+-"size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -"
+-"Os."
++"Use/do not use scalar register+offset memory instructions added in ISA 3.0."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:213
++#: config/rs6000/rs6000.opt:622
+ msgid ""
+-"Cost to assume for a multiply instruction, with 4 being equal to a normal "
+-"insn."
++"Use/do not use vector register+offset memory instructions added in ISA 3.0."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:217
+-msgid "Tune for ARC600 cpu."
++#: config/rs6000/rs6000.opt:626
++msgid "Use/do not use register+offset memory instructions added in ISA 3.0."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:221
+-msgid "Tune for ARC601 cpu."
++#: config/rs6000/rs6000.opt:630
++msgid "Use/do not use the new min/max instructions defined in ISA 3.0."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:225
+-msgid "Tune for ARC700 R4.2 Cpu with standard multiplier block."
++#: config/rs6000/rs6000.opt:634
++msgid ""
++"Fuse medium/large code model toc references with the memory instruction."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:229 config/arc/arc.opt:233 config/arc/arc.opt:237
+-msgid "Tune for ARC700 R4.2 Cpu with XMAC block."
++#: config/rs6000/rs6000.opt:638
++msgid "Generate the integer modulo instructions."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:241
+-msgid "Enable the use of indexed loads."
++#: config/rs6000/rs6000.opt:642
++msgid "Enable/disable IEEE 128-bit floating point via the __float128 keyword."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:245
+-msgid "Enable the use of pre/post modify with register displacement."
++#: config/rs6000/rs6000.opt:646
++msgid "Enable/disable using IEEE 128-bit floating point instructions."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:249
+-msgid "Generate 32x16 multiply and mac instructions."
++#: config/rs6000/rs6000.opt:650
++msgid "Enable/disable default conversions between __float128 & long double."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:255
+-msgid "Set probability threshold for unaligning branches."
++#: config/rs6000/darwin.opt:38 config/rs6000/sysv4.opt:141
++msgid "Generate 64-bit code."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:259
+-msgid "Don't use less than 25 bit addressing range for calls."
++#: config/rs6000/darwin.opt:42 config/rs6000/sysv4.opt:145
++msgid "Generate 32-bit code."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:263
+-msgid ""
+-"Explain what alignment considerations lead to the decision to make an insn "
+-"short or long."
++#: config/rs6000/sysv4.opt:24
++msgid "Select ABI calling convention."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:267
+-msgid "Do alignment optimizations for call instructions."
++#: config/rs6000/sysv4.opt:48
++msgid "Align to the base type of the bit-field."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:271
++#: config/rs6000/sysv4.opt:52
+ msgid ""
+-"Enable Rcq constraint handling - most short code generation depends on this."
++"Align to the base type of the bit-field. Don't assume that unaligned "
++"accesses are handled by the system."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:275
+-msgid "Enable Rcw constraint handling - ccfsm condexec mostly depends on this."
++#: config/rs6000/sysv4.opt:57 config/rs6000/sysv4.opt:61
++msgid "Produce code relocatable at runtime."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:279
+-msgid "Enable pre-reload use of cbranchsi pattern."
++#: config/rs6000/sysv4.opt:65 config/rs6000/sysv4.opt:69
++msgid "Produce little endian code."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:283
+-msgid "Enable bbit peephole2."
++#: config/rs6000/sysv4.opt:73 config/rs6000/sysv4.opt:77
++msgid "Produce big endian code."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:287
+-msgid ""
+-"Use pc-relative switch case tables - this enables case table shortening."
++#: config/rs6000/sysv4.opt:82 config/rs6000/sysv4.opt:86
++#: config/rs6000/sysv4.opt:95 config/rs6000/sysv4.opt:137
++#: config/rs6000/sysv4.opt:149
++msgid "no description yet."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:291
+-msgid "Enable compact casesi pattern."
++#: config/rs6000/sysv4.opt:90
++msgid "Assume all variable arg functions are prototyped."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:295
+-msgid "Enable 'q' instruction alternatives."
++#: config/rs6000/sysv4.opt:99
++msgid "Use EABI."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:299
+-msgid "Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc."
++#: config/rs6000/sysv4.opt:103
++msgid "Allow bit-fields to cross word boundaries."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:306
+-msgid "Enable variable polynomial CRC extension."
++#: config/rs6000/sysv4.opt:107
++msgid "Use alternate register names."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:310
+-msgid "Enable DSP 3.1 Pack A extensions."
++#: config/rs6000/sysv4.opt:113
++msgid "Use default method for sdata handling."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:314
+-msgid "Enable dual viterbi butterfly extension."
++#: config/rs6000/sysv4.opt:117
++msgid "Link with libsim.a, libc.a and sim-crt0.o."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:324
+-msgid "Enable Dual and Single Operand Instructions for Telephony."
++#: config/rs6000/sysv4.opt:121
++msgid "Link with libads.a, libc.a and crt0.o."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:328
+-msgid "Enable XY Memory extension (DSP version 3)."
++#: config/rs6000/sysv4.opt:125
++msgid "Link with libyk.a, libc.a and crt0.o."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:333
+-msgid "Enable Locked Load/Store Conditional extension."
++#: config/rs6000/sysv4.opt:129
++msgid "Link with libmvme.a, libc.a and crt0.o."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:337
+-msgid "Enable swap byte ordering extension instruction."
++#: config/rs6000/sysv4.opt:133
++msgid "Set the PPC_EMB bit in the ELF flags header."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:341
+-msgid "Enable 64-bit Time-Stamp Counter extension instruction."
++#: config/rs6000/sysv4.opt:153
++msgid "Generate code to use a non-exec PLT and GOT."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:345
+-msgid "Pass -EB option through to linker."
++#: config/rs6000/sysv4.opt:157
++msgid "Generate code for old exec BSS PLT."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:349
+-msgid "Pass -EL option through to linker."
++#: config/rs6000/aix64.opt:24
++msgid "Compile for 64-bit pointers."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:353
+-msgid "Pass -marclinux option through to linker."
++#: config/rs6000/aix64.opt:28
++msgid "Compile for 32-bit pointers."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:357
+-msgid "Pass -marclinux_prof option through to linker."
++#: config/rs6000/aix64.opt:32 config/rs6000/linux64.opt:28
++msgid "Select code model."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:365
+-msgid "Enable lra."
++#: config/rs6000/aix64.opt:49
++msgid "Support message passing with the Parallel Environment."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:369
+-msgid "Don't indicate any priority with TARGET_REGISTER_PRIORITY."
++#: config/rs6000/linux64.opt:24
++msgid "Call mcount for profiling before a function prologue."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:373
+-msgid "Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY."
++#: config/rs6000/476.opt:24
++msgid ""
++"Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl "
++"insns used for GOT accesses."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:377
+-msgid "Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY."
++#: config/rl78/rl78.opt:31
++msgid ""
++"Selects the type of hardware multiplication and division to use (none/g13/"
++"g14)."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:381
+-msgid "instrument with mcount calls as in the ucb code."
++#: config/rl78/rl78.opt:50
++msgid "Use all registers, reserving none for interrupt handlers."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:411
+-msgid "Enable atomic instructions."
++#: config/rl78/rl78.opt:54
++msgid "Enable assembler and linker relaxation.  Enabled by default at -Os."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:415
+-msgid "Enable double load/store instructions for ARC HS."
++#: config/rl78/rl78.opt:58
++msgid ""
++"Selects the type of RL78 core being targeted (g10/g13/g14).  The default is "
++"the G14.  If set, also selects the hardware multiply support to be used."
+ msgstr ""
+ 
+-#: config/arc/arc.opt:419
+-msgid "Specify the name of the target floating point configuration."
++#: config/rl78/rl78.opt:77
++msgid "Alias for -mcpu=g10."
+ msgstr ""
+ 
+-#: java/lang.opt:122
+-msgid "Warn if deprecated empty statements are found."
++#: config/rl78/rl78.opt:81
++msgid "Alias for -mcpu=g13."
+ msgstr ""
+ 
+-#: java/lang.opt:126
+-msgid "Warn if .class files are out of date."
++#: config/rl78/rl78.opt:85 config/rl78/rl78.opt:89
++msgid "Alias for -mcpu=g14."
+ msgstr ""
+ 
+-#: java/lang.opt:130
+-msgid "Warn if modifiers are specified when not necessary."
++#: config/rl78/rl78.opt:93
++msgid ""
++"Assume ES is zero throughout program execution, use ES: for read-only data."
+ msgstr ""
+ 
+-#: java/lang.opt:150
+-msgid "--CLASSPATH\tDeprecated; use --classpath instead."
++#: config/nds32/nds32.opt:26
++msgid "Generate code in big-endian mode."
+ msgstr ""
+ 
+-#: java/lang.opt:157
+-msgid "Permit the use of the assert keyword."
++#: config/nds32/nds32.opt:30
++msgid "Generate code in little-endian mode."
+ msgstr ""
+ 
+-#: java/lang.opt:179
+-msgid "--bootclasspath=<path>\tReplace system path."
++#: config/nds32/nds32.opt:34
++msgid "Use reduced-set registers for register allocation."
+ msgstr ""
+ 
+-#: java/lang.opt:183
+-msgid "Generate checks for references to NULL."
++#: config/nds32/nds32.opt:38
++msgid "Use full-set registers for register allocation."
+ msgstr ""
+ 
+-#: java/lang.opt:187
+-msgid "--classpath=<path>\tSet class path."
++#: config/nds32/nds32.opt:42
++msgid "Generate conditional move instructions."
+ msgstr ""
+ 
+-#: java/lang.opt:194
+-msgid "Output a class file."
++#: config/nds32/nds32.opt:46
++msgid "Generate performance extension instructions."
+ msgstr ""
+ 
+-#: java/lang.opt:198
+-msgid "Alias for -femit-class-file."
++#: config/nds32/nds32.opt:50
++msgid "Generate v3 push25/pop25 instructions."
+ msgstr ""
+ 
+-#: java/lang.opt:202
++#: config/nds32/nds32.opt:54
++msgid "Generate 16-bit instructions."
++msgstr ""
++
++#: config/nds32/nds32.opt:58
++msgid "Specify the size of each interrupt vector, which must be 4 or 16."
++msgstr ""
++
++#: config/nds32/nds32.opt:62
+ msgid ""
+-"--encoding=<encoding>\tChoose input encoding (defaults from your locale)."
++"Specify the size of each cache block, which must be a power of 2 between 4 "
++"and 512."
+ msgstr ""
+ 
+-#: java/lang.opt:206
+-msgid "--extdirs=<path>\tSet the extension directory path."
++#: config/nds32/nds32.opt:70
++msgid "Known arch types (for use with the -march= option):"
+ msgstr ""
+ 
+-#: java/lang.opt:216
+-msgid "Input file is a file with a list of filenames to compile."
++#: config/nds32/nds32.opt:83
++msgid "Specify the address generation strategy for code model."
+ msgstr ""
+ 
+-#: java/lang.opt:223
+-msgid "Always check for non gcj generated classes archives."
++#: config/nds32/nds32.opt:87
++msgid "Known cmodel types (for use with the -mcmodel= option):"
+ msgstr ""
+ 
+-#: java/lang.opt:227
+-msgid ""
+-"Assume the runtime uses a hash table to map an object to its synchronization "
+-"structure."
++#: config/nds32/nds32.opt:100
++msgid "Enable constructor/destructor feature."
+ msgstr ""
+ 
+-#: java/lang.opt:231
+-msgid "Generate instances of Class at runtime."
++#: config/nds32/nds32.opt:104
++msgid "Guide linker to relax instructions."
+ msgstr ""
+ 
+-#: java/lang.opt:235
+-msgid "Use offset tables for virtual method calls."
++#: config/ft32/ft32.opt:23
++msgid "target the software simulator."
+ msgstr ""
+ 
+-#: java/lang.opt:242
+-msgid "Assume native functions are implemented using JNI."
++#: config/ft32/ft32.opt:31
++msgid "Avoid use of the DIV and MOD instructions"
+ msgstr ""
+ 
+-#: java/lang.opt:246
+-msgid "Enable optimization of static class initialization code."
++#: ada/gcc-interface/lang.opt:57 c-family/c.opt:276
++msgid "Enable most warning messages."
+ msgstr ""
+ 
+-#: java/lang.opt:253
+-msgid "Reduce the amount of reflection meta-data generated."
++#: ada/gcc-interface/lang.opt:61
++msgid "Synonym of -gnatk8."
+ msgstr ""
+ 
+-#: java/lang.opt:257
+-msgid "Enable assignability checks for stores into object arrays."
++#: ada/gcc-interface/lang.opt:69
++msgid "Do not look for object files in standard path."
+ msgstr ""
+ 
+-#: java/lang.opt:261
+-msgid "Generate code for the Boehm GC."
++#: ada/gcc-interface/lang.opt:73
++msgid "Select the runtime."
+ msgstr ""
+ 
+-#: java/lang.opt:265
+-msgid "Call a library routine to do integer divisions."
++#: ada/gcc-interface/lang.opt:77 c-family/c.opt:1456
++msgid "Use the narrowest integer type possible for enumeration types."
+ msgstr ""
+ 
+-#: java/lang.opt:269
+-msgid "Generate code for built-in atomic operations."
++#: ada/gcc-interface/lang.opt:81 c-family/c.opt:1468
++msgid "Make \"char\" signed by default."
+ msgstr ""
+ 
+-#: java/lang.opt:273
+-msgid "Generated should be loaded by bootstrap loader."
++#: ada/gcc-interface/lang.opt:85
++msgid "Catch typos."
+ msgstr ""
+ 
+-#: java/lang.opt:277
+-msgid "Set the source language version."
++#: ada/gcc-interface/lang.opt:89
++msgid "Set name of output ALI file (internal switch)."
+ msgstr ""
+ 
+-#: java/lang.opt:281
+-msgid "Set the target VM version."
++#: ada/gcc-interface/lang.opt:93
++msgid "-gnat<options>\tSpecify options to GNAT."
+ msgstr ""
+ 
+-#: lto/lang.opt:28
+-#, c-format
+-msgid "unknown linker output %qs"
++#: ada/gcc-interface/lang.opt:97
++msgid "Ignored."
+ msgstr ""
+ 
+-#: lto/lang.opt:47
+-msgid "Set linker output type (used internally during LTO optimization)"
++#: go/lang.opt:42
++msgid "Add explicit checks for division by zero."
+ msgstr ""
+ 
+-#: lto/lang.opt:52
+-msgid "Run the link-time optimizer in local transformation (LTRANS) mode."
++#: go/lang.opt:46
++msgid "Add explicit checks for division overflow in INT_MIN / -1."
+ msgstr ""
+ 
+-#: lto/lang.opt:56
+-msgid "Specify a file to which a list of files output by LTRANS is written."
++#: go/lang.opt:50
++msgid "-fgo-dump-<type>\tDump Go frontend internal information."
+ msgstr ""
+ 
+-#: lto/lang.opt:60
+-msgid "Run the link-time optimizer in whole program analysis (WPA) mode."
++#: go/lang.opt:54
++msgid "-fgo-optimize-<type>\tTurn on optimization passes in the frontend."
+ msgstr ""
+ 
+-#: lto/lang.opt:64
++#: go/lang.opt:58
++msgid "-fgo-pkgpath=<string>\tSet Go package path."
++msgstr ""
++
++#: go/lang.opt:62
+ msgid ""
+-"Whole program analysis (WPA) mode with number of parallel jobs specified."
++"-fgo-prefix=<string>\tSet package-specific prefix for exported Go names."
+ msgstr ""
+ 
+-#: lto/lang.opt:68
+-msgid "The resolution file."
++#: go/lang.opt:66
++msgid ""
++"-fgo-relative-import-path=<path> Treat a relative import as relative to path."
+ msgstr ""
+ 
++#: go/lang.opt:70
++msgid "Functions which return values must end with return statements."
++msgstr ""
++
+ #: common.opt:235
+-msgid "Enable coverage-guided fuzzing code instrumentation."
++msgid ""
++"Enable coverage-guided fuzzing code instrumentation. Inserts call to "
++"__sanitizer_cov_trace_pc into every basic block."
+ msgstr ""
+ 
+ #: common.opt:302
+@@ -13986,7 +11956,9 @@
+ msgstr ""
+ 
+ #: common.opt:944
+-msgid "-fsanitize-sections=<sec1,sec2,...>\tSanitize global variables"
++msgid ""
++"-fsanitize-sections=<sec1,sec2,...>\tSanitize global variables in user-"
++"defined sections."
+ msgstr ""
+ 
+ #: common.opt:949
+@@ -14011,11 +11983,15 @@
+ msgstr ""
+ 
+ #: common.opt:969
+-msgid "Use sample profile information for call graph node weights. The default"
++msgid ""
++"Use sample profile information for call graph node weights. The default "
++"profile file is fbdata.afdo in 'pwd'."
+ msgstr ""
+ 
+ #: common.opt:974
+-msgid "Use sample profile information for call graph node weights. The profile"
++msgid ""
++"Use sample profile information for call graph node weights. The profile file "
++"is specified in the argument."
+ msgstr ""
+ 
+ #: common.opt:983
+@@ -14219,7 +12195,9 @@
+ msgstr ""
+ 
+ #: common.opt:1212
+-msgid "Collect and dump debug information into temporary file if ICE in C/C++"
++msgid ""
++"Collect and dump debug information into temporary file if ICE in C/C++ "
++"compiler occured."
+ msgstr ""
+ 
+ #: common.opt:1217
+@@ -14345,12 +12323,14 @@
+ 
+ #: common.opt:1349
+ msgid ""
+-"Perform redundant load after store elimination in global common subexpression"
++"Perform redundant load after store elimination in global common "
++"subexpression elimination."
+ msgstr ""
+ 
+ #: common.opt:1354
+ msgid ""
+-"Perform global common subexpression elimination after register allocation has"
++"Perform global common subexpression elimination after register allocation "
++"has finished."
+ msgstr ""
+ 
+ #: common.opt:1371
+@@ -14368,7 +12348,9 @@
+ msgstr ""
+ 
+ #: common.opt:1384
+-msgid "Enable hoisting adjacent loads to encourage generating conditional move"
++msgid ""
++"Enable hoisting adjacent loads to encourage generating conditional move "
++"instructions."
+ msgstr ""
+ 
+ #: common.opt:1393
+@@ -14547,10 +12529,14 @@
+ msgid "unknown IRA region %qs"
+ msgstr ""
+ 
+-#: common.opt:1607 common.opt:1612
+-msgid "Use IRA based register pressure calculation"
++#: common.opt:1607
++msgid "Use IRA based register pressure calculation in RTL hoist optimizations."
+ msgstr ""
+ 
++#: common.opt:1612
++msgid "Use IRA based register pressure calculation in RTL loop optimizations."
++msgstr ""
++
+ #: common.opt:1617
+ msgid "Share slots for saving different hard registers."
+ msgstr ""
+@@ -14808,7 +12794,9 @@
+ msgstr ""
+ 
+ #: common.opt:1888
+-msgid "Set the top-level directory for storing the profile data."
++msgid ""
++"Set the top-level directory for storing the profile data. The default is "
++"'pwd'."
+ msgstr ""
+ 
+ #: common.opt:1893
+@@ -14863,7 +12851,9 @@
+ msgstr ""
+ 
+ #: common.opt:1950
+-msgid "Tell DSE that the storage for a C++ object is dead when the constructor"
++msgid ""
++"Tell DSE that the storage for a C++ object is dead when the constructor "
++"starts and when the destructor finishes."
+ msgstr ""
+ 
+ #: common.opt:1958
+@@ -15029,7 +13019,9 @@
+ msgstr ""
+ 
+ #: common.opt:2140
+-msgid "Emit function prologues only before parts of the function that need it,"
++msgid ""
++"Emit function prologues only before parts of the function that need it, "
++"rather than at the top of the function."
+ msgstr ""
+ 
+ #: common.opt:2145
+@@ -15228,12 +13220,18 @@
+ msgstr ""
+ 
+ #: common.opt:2370
+-msgid "Detect paths that trigger erroneous or undefined behavior due to"
++msgid ""
++"Detect paths that trigger erroneous or undefined behavior due to "
++"dereferencing a null pointer.  Isolate those paths from the main control "
++"flow and turn the statement with erroneous or undefined behavior into a trap."
+ msgstr ""
+ 
+ #: common.opt:2376
+ msgid ""
+-"Detect paths that trigger erroneous or undefined behavior due a null value"
++"Detect paths that trigger erroneous or undefined behavior due a null value "
++"being used in a way forbidden by a returns_nonnull or nonnull attribute.  "
++"Isolate those paths from the main control flow and turn the statement with "
++"erroneous or undefined behavior into a trap."
+ msgstr ""
+ 
+ #: common.opt:2383
+@@ -15311,7 +13309,9 @@
+ msgstr ""
+ 
+ #: common.opt:2463
+-msgid "Assume common declarations may be overridden with ones with a larger"
++msgid ""
++"Assume common declarations may be overridden with ones with a larger "
++"trailing array."
+ msgstr ""
+ 
+ #: common.opt:2468
+@@ -15331,7 +13331,9 @@
+ msgstr ""
+ 
+ #: common.opt:2487
+-msgid "Allow optimization for floating-point arithmetic which may change the"
++msgid ""
++"Allow optimization for floating-point arithmetic which may change the result "
++"of the operation due to rounding."
+ msgstr ""
+ 
+ #: common.opt:2492
+@@ -15613,6 +13615,2088 @@
+ msgid "Use caller save register across calls if possible."
+ msgstr ""
+ 
++#: java/lang.opt:122
++msgid "Warn if deprecated empty statements are found."
++msgstr ""
++
++#: java/lang.opt:126
++msgid "Warn if .class files are out of date."
++msgstr ""
++
++#: java/lang.opt:130
++msgid "Warn if modifiers are specified when not necessary."
++msgstr ""
++
++#: java/lang.opt:150
++msgid "--CLASSPATH\tDeprecated; use --classpath instead."
++msgstr ""
++
++#: java/lang.opt:157
++msgid "Permit the use of the assert keyword."
++msgstr ""
++
++#: java/lang.opt:179
++msgid "--bootclasspath=<path>\tReplace system path."
++msgstr ""
++
++#: java/lang.opt:183
++msgid "Generate checks for references to NULL."
++msgstr ""
++
++#: java/lang.opt:187
++msgid "--classpath=<path>\tSet class path."
++msgstr ""
++
++#: java/lang.opt:194
++msgid "Output a class file."
++msgstr ""
++
++#: java/lang.opt:198
++msgid "Alias for -femit-class-file."
++msgstr ""
++
++#: java/lang.opt:202
++msgid ""
++"--encoding=<encoding>\tChoose input encoding (defaults from your locale)."
++msgstr ""
++
++#: java/lang.opt:206
++msgid "--extdirs=<path>\tSet the extension directory path."
++msgstr ""
++
++#: java/lang.opt:216
++msgid "Input file is a file with a list of filenames to compile."
++msgstr ""
++
++#: java/lang.opt:223
++msgid "Always check for non gcj generated classes archives."
++msgstr ""
++
++#: java/lang.opt:227
++msgid ""
++"Assume the runtime uses a hash table to map an object to its synchronization "
++"structure."
++msgstr ""
++
++#: java/lang.opt:231
++msgid "Generate instances of Class at runtime."
++msgstr ""
++
++#: java/lang.opt:235
++msgid "Use offset tables for virtual method calls."
++msgstr ""
++
++#: java/lang.opt:242
++msgid "Assume native functions are implemented using JNI."
++msgstr ""
++
++#: java/lang.opt:246
++msgid "Enable optimization of static class initialization code."
++msgstr ""
++
++#: java/lang.opt:253
++msgid "Reduce the amount of reflection meta-data generated."
++msgstr ""
++
++#: java/lang.opt:257
++msgid "Enable assignability checks for stores into object arrays."
++msgstr ""
++
++#: java/lang.opt:261
++msgid "Generate code for the Boehm GC."
++msgstr ""
++
++#: java/lang.opt:265
++msgid "Call a library routine to do integer divisions."
++msgstr ""
++
++#: java/lang.opt:269
++msgid "Generate code for built-in atomic operations."
++msgstr ""
++
++#: java/lang.opt:273
++msgid "Generated should be loaded by bootstrap loader."
++msgstr ""
++
++#: java/lang.opt:277
++msgid "Set the source language version."
++msgstr ""
++
++#: java/lang.opt:281
++msgid "Set the target VM version."
++msgstr ""
++
++#: c-family/c.opt:43 c-family/c.opt:46 c-family/c.opt:181
++#, c-format
++msgid "assertion missing after %qs"
++msgstr ""
++
++#: c-family/c.opt:55 c-family/c.opt:58 c-family/c.opt:163 c-family/c.opt:166
++#: c-family/c.opt:193 c-family/c.opt:252
++#, c-format
++msgid "macro name missing after %qs"
++msgstr ""
++
++#: c-family/c.opt:85 c-family/c.opt:88 c-family/c.opt:91 c-family/c.opt:94
++#: c-family/c.opt:200 c-family/c.opt:208 c-family/c.opt:1597
++#: c-family/c.opt:1617 c-family/c.opt:1621 c-family/c.opt:1625
++#, c-format
++msgid "missing path after %qs"
++msgstr ""
++
++#: c-family/c.opt:182
++msgid ""
++"-A<question>=<answer>\tAssert the <answer> to <question>.  Putting '-' "
++"before <question> disables the <answer> to <question>."
++msgstr ""
++
++#: c-family/c.opt:186
++msgid "Do not discard comments."
++msgstr ""
++
++#: c-family/c.opt:190
++msgid "Do not discard comments in macro expansions."
++msgstr ""
++
++#: c-family/c.opt:194
++msgid ""
++"-D<macro>[=<val>]\tDefine a <macro> with <val> as its value.  If just "
++"<macro> is given, <val> is taken to be 1."
++msgstr ""
++
++#: c-family/c.opt:201
++msgid "-F <dir>\tAdd <dir> to the end of the main framework include path."
++msgstr ""
++
++#: c-family/c.opt:205
++msgid "Print the name of header files as they are used."
++msgstr ""
++
++#: c-family/c.opt:209
++msgid "-I <dir>\tAdd <dir> to the end of the main include path."
++msgstr ""
++
++#: c-family/c.opt:213
++msgid "Generate make dependencies."
++msgstr ""
++
++#: c-family/c.opt:217
++msgid "Generate make dependencies and compile."
++msgstr ""
++
++#: c-family/c.opt:221
++msgid "-MF <file>\tWrite dependency output to the given file."
++msgstr ""
++
++#: c-family/c.opt:225
++msgid "Treat missing header files as generated files."
++msgstr ""
++
++#: c-family/c.opt:229
++msgid "Like -M but ignore system header files."
++msgstr ""
++
++#: c-family/c.opt:233
++msgid "Like -MD but ignore system header files."
++msgstr ""
++
++#: c-family/c.opt:237
++msgid "Generate phony targets for all headers."
++msgstr ""
++
++#: c-family/c.opt:240 c-family/c.opt:244
++#, c-format
++msgid "missing makefile target after %qs"
++msgstr ""
++
++#: c-family/c.opt:241
++msgid "-MQ <target>\tAdd a MAKE-quoted target."
++msgstr ""
++
++#: c-family/c.opt:245
++msgid "-MT <target>\tAdd an unquoted target."
++msgstr ""
++
++#: c-family/c.opt:249
++msgid "Do not generate #line directives."
++msgstr ""
++
++#: c-family/c.opt:253
++msgid "-U<macro>\tUndefine <macro>."
++msgstr ""
++
++#: c-family/c.opt:257
++msgid ""
++"Warn about things that will change when compiling with an ABI-compliant "
++"compiler."
++msgstr ""
++
++#: c-family/c.opt:261
++msgid ""
++"Warn about things that change between the current -fabi-version and the "
++"specified version."
++msgstr ""
++
++#: c-family/c.opt:265
++msgid ""
++"Warn if a subobject has an abi_tag attribute that the complete object type "
++"does not have."
++msgstr ""
++
++#: c-family/c.opt:272
++msgid "Warn about suspicious uses of memory addresses."
++msgstr ""
++
++#: c-family/c.opt:288
++msgid ""
++"Warn whenever an Objective-C assignment is being intercepted by the garbage "
++"collector."
++msgstr ""
++
++#: c-family/c.opt:292
++msgid "Warn about casting functions to incompatible types."
++msgstr ""
++
++#: c-family/c.opt:296
++msgid ""
++"Warn about boolean expression compared with an integer value different from "
++"true/false."
++msgstr ""
++
++#: c-family/c.opt:300
++msgid ""
++"Warn when __builtin_frame_address or __builtin_return_address is used "
++"unsafely."
++msgstr ""
++
++#: c-family/c.opt:304
++msgid "Warn when a built-in preprocessor macro is undefined or redefined."
++msgstr ""
++
++#: c-family/c.opt:308
++msgid "Warn about features not present in ISO C90, but present in ISO C99."
++msgstr ""
++
++#: c-family/c.opt:312
++msgid "Warn about features not present in ISO C99, but present in ISO C11."
++msgstr ""
++
++#: c-family/c.opt:316
++msgid "Warn about C constructs that are not in the common subset of C and C++."
++msgstr ""
++
++#: c-family/c.opt:323
++msgid ""
++"Warn about C++ constructs whose meaning differs between ISO C++ 1998 and ISO "
++"C++ 2011."
++msgstr ""
++
++#: c-family/c.opt:327
++msgid ""
++"Warn about C++ constructs whose meaning differs between ISO C++ 2011 and ISO "
++"C++ 2014."
++msgstr ""
++
++#: c-family/c.opt:331
++msgid "Warn about casts which discard qualifiers."
++msgstr ""
++
++#: c-family/c.opt:335
++msgid "Warn about subscripts whose type is \"char\"."
++msgstr ""
++
++#: c-family/c.opt:339
++msgid "Warn about memory access errors found by Pointer Bounds Checker."
++msgstr ""
++
++#: c-family/c.opt:343
++msgid "Warn about variables that might be changed by \"longjmp\" or \"vfork\"."
++msgstr ""
++
++#: c-family/c.opt:347
++msgid ""
++"Warn about possibly nested block comments, and C++ comments spanning more "
++"than one physical line."
++msgstr ""
++
++#: c-family/c.opt:351
++msgid "Synonym for -Wcomment."
++msgstr ""
++
++#: c-family/c.opt:355
++msgid "Warn for conditionally-supported constructs."
++msgstr ""
++
++#: c-family/c.opt:359
++msgid "Warn for implicit type conversions that may change a value."
++msgstr ""
++
++#: c-family/c.opt:363
++msgid "Warn for converting NULL from/to a non-pointer type."
++msgstr ""
++
++#: c-family/c.opt:371
++msgid "Warn when all constructors and destructors are private."
++msgstr ""
++
++#: c-family/c.opt:375
++msgid "Warn about __TIME__, __DATE__ and __TIMESTAMP__ usage."
++msgstr ""
++
++#: c-family/c.opt:379
++msgid "Warn when a declaration is found after a statement."
++msgstr ""
++
++#: c-family/c.opt:383
++msgid "Warn when deleting a pointer to incomplete type."
++msgstr ""
++
++#: c-family/c.opt:387
++msgid "Warn about deleting polymorphic objects with non-virtual destructors."
++msgstr ""
++
++#: c-family/c.opt:391
++msgid "Warn if a deprecated compiler feature, class, method, or field is used."
++msgstr ""
++
++#: c-family/c.opt:395
++msgid ""
++"Warn about positional initialization of structs requiring designated "
++"initializers."
++msgstr ""
++
++#: c-family/c.opt:399
++msgid "Warn if qualifiers on arrays which are pointer targets are discarded."
++msgstr ""
++
++#: c-family/c.opt:403
++msgid "Warn if type qualifiers on pointers are discarded."
++msgstr ""
++
++#: c-family/c.opt:407
++msgid "Warn about compile-time integer division by zero."
++msgstr ""
++
++#: c-family/c.opt:411
++msgid "Warn about duplicated conditions in an if-else-if chain."
++msgstr ""
++
++#: c-family/c.opt:415
++msgid "Warn about violations of Effective C++ style rules."
++msgstr ""
++
++#: c-family/c.opt:419
++msgid "Warn about an empty body in an if or else statement."
++msgstr ""
++
++#: c-family/c.opt:423
++msgid "Warn about stray tokens after #elif and #endif."
++msgstr ""
++
++#: c-family/c.opt:427
++msgid "Warn about comparison of different enum types."
++msgstr ""
++
++#: c-family/c.opt:435
++msgid ""
++"This switch is deprecated; use -Werror=implicit-function-declaration instead."
++msgstr ""
++
++#: c-family/c.opt:439
++msgid ""
++"Warn for implicit type conversions that cause loss of floating point "
++"precision."
++msgstr ""
++
++#: c-family/c.opt:443
++msgid "Warn if testing floating point numbers for equality."
++msgstr ""
++
++#: c-family/c.opt:447 c-family/c.opt:479
++msgid "Warn about printf/scanf/strftime/strfmon format string anomalies."
++msgstr ""
++
++#: c-family/c.opt:451
++msgid "Warn about format strings that contain NUL bytes."
++msgstr ""
++
++#: c-family/c.opt:455
++msgid "Warn if passing too many arguments to a function for its format string."
++msgstr ""
++
++#: c-family/c.opt:459
++msgid "Warn about format strings that are not literals."
++msgstr ""
++
++#: c-family/c.opt:463
++msgid "Warn about possible security problems with format functions."
++msgstr ""
++
++#: c-family/c.opt:467
++msgid "Warn about sign differences with format functions."
++msgstr ""
++
++#: c-family/c.opt:471
++msgid "Warn about strftime formats yielding 2-digit years."
++msgstr ""
++
++#: c-family/c.opt:475
++msgid "Warn about zero-length formats."
++msgstr ""
++
++#: c-family/c.opt:483
++msgid "Warn whenever type qualifiers are ignored."
++msgstr ""
++
++#: c-family/c.opt:487
++msgid "Warn whenever attributes are ignored."
++msgstr ""
++
++#: c-family/c.opt:491
++msgid ""
++"Warn when there is a conversion between pointers that have incompatible "
++"types."
++msgstr ""
++
++#: c-family/c.opt:495
++msgid "Warn about variables which are initialized to themselves."
++msgstr ""
++
++#: c-family/c.opt:499
++msgid "Warn about implicit declarations."
++msgstr ""
++
++#: c-family/c.opt:503
++msgid "Warn about implicit conversions from \"float\" to \"double\"."
++msgstr ""
++
++#: c-family/c.opt:507
++msgid "Warn about implicit function declarations."
++msgstr ""
++
++#: c-family/c.opt:511
++msgid "Warn when a declaration does not specify a type."
++msgstr ""
++
++#: c-family/c.opt:518
++msgid ""
++"Warn about C++11 inheriting constructors when the base has a variadic "
++"constructor."
++msgstr ""
++
++#: c-family/c.opt:522
++msgid ""
++"Warn about incompatible integer to pointer and pointer to integer "
++"conversions."
++msgstr ""
++
++#: c-family/c.opt:526
++msgid ""
++"Warn when there is a cast to a pointer from an integer of a different size."
++msgstr ""
++
++#: c-family/c.opt:530
++msgid "Warn about invalid uses of the \"offsetof\" macro."
++msgstr ""
++
++#: c-family/c.opt:534
++msgid "Warn about PCH files that are found but not used."
++msgstr ""
++
++#: c-family/c.opt:538
++msgid "Warn when a jump misses a variable initialization."
++msgstr ""
++
++#: c-family/c.opt:542
++msgid ""
++"Warn when a string or character literal is followed by a ud-suffix which "
++"does not begin with an underscore."
++msgstr ""
++
++#: c-family/c.opt:546
++msgid ""
++"Warn when a logical operator is suspiciously always evaluating to true or "
++"false."
++msgstr ""
++
++#: c-family/c.opt:550
++msgid ""
++"Warn when logical not is used on the left hand side operand of a comparison."
++msgstr ""
++
++#: c-family/c.opt:554
++msgid "Do not warn about using \"long long\" when -pedantic."
++msgstr ""
++
++#: c-family/c.opt:558
++msgid "Warn about suspicious declarations of \"main\"."
++msgstr ""
++
++#: c-family/c.opt:566
++msgid ""
++"Warn about suspicious calls to memset where the third argument is constant "
++"literal zero and the second is not."
++msgstr ""
++
++#: c-family/c.opt:570
++msgid ""
++"Warn when the indentation of the code does not reflect the block structure."
++msgstr ""
++
++#: c-family/c.opt:574
++msgid "Warn about possibly missing braces around initializers."
++msgstr ""
++
++#: c-family/c.opt:578
++msgid "Warn about global functions without previous declarations."
++msgstr ""
++
++#: c-family/c.opt:582
++msgid "Warn about missing fields in struct initializers."
++msgstr ""
++
++#: c-family/c.opt:586
++msgid "Warn on direct multiple inheritance."
++msgstr ""
++
++#: c-family/c.opt:590
++msgid "Warn on namespace definition."
++msgstr ""
++
++#: c-family/c.opt:594
++msgid "Warn about missing sized deallocation functions."
++msgstr ""
++
++#: c-family/c.opt:598
++msgid ""
++"Warn about suspicious length parameters to certain string functions if the "
++"argument uses sizeof."
++msgstr ""
++
++#: c-family/c.opt:602
++msgid "Warn when sizeof is applied on a parameter declared as an array."
++msgstr ""
++
++#: c-family/c.opt:606
++msgid "Warn about functions which might be candidates for format attributes."
++msgstr ""
++
++#: c-family/c.opt:610
++msgid ""
++"Suggest that the override keyword be used when the declaration of a virtual "
++"function overrides another."
++msgstr ""
++
++#: c-family/c.opt:615
++msgid "Warn about enumerated switches, with no default, missing a case."
++msgstr ""
++
++#: c-family/c.opt:619
++msgid "Warn about enumerated switches missing a \"default:\" statement."
++msgstr ""
++
++#: c-family/c.opt:623
++msgid "Warn about all enumerated switches missing a specific case."
++msgstr ""
++
++#: c-family/c.opt:627
++msgid "Warn about switches with boolean controlling expression."
++msgstr ""
++
++#: c-family/c.opt:631
++msgid "Warn on primary template declaration."
++msgstr ""
++
++#: c-family/c.opt:639
++msgid "Warn about user-specified include directories that do not exist."
++msgstr ""
++
++#: c-family/c.opt:643
++msgid ""
++"Warn about function parameters declared without a type specifier in K&R-"
++"style functions."
++msgstr ""
++
++#: c-family/c.opt:647
++msgid "Warn about global functions without prototypes."
++msgstr ""
++
++#: c-family/c.opt:654
++msgid "Warn about use of multi-character character constants."
++msgstr ""
++
++#: c-family/c.opt:658
++msgid ""
++"Warn about narrowing conversions within { } that are ill-formed in C++11."
++msgstr ""
++
++#: c-family/c.opt:662
++msgid "Warn about \"extern\" declarations not at file scope."
++msgstr ""
++
++#: c-family/c.opt:666
++msgid ""
++"Warn when a noexcept expression evaluates to false even though the "
++"expression can't actually throw."
++msgstr ""
++
++#: c-family/c.opt:670
++msgid ""
++"Warn when non-templatized friend functions are declared within a template."
++msgstr ""
++
++#: c-family/c.opt:674
++msgid "Warn about non-virtual destructors."
++msgstr ""
++
++#: c-family/c.opt:678
++msgid ""
++"Warn about NULL being passed to argument slots marked as requiring non-NULL."
++msgstr ""
++
++#: c-family/c.opt:694
++msgid ""
++"-Wnormalized=<none|id|nfc|nfkc>\tWarn about non-normalised Unicode strings."
++msgstr ""
++
++#: c-family/c.opt:701
++msgid "argument %qs to %<-Wnormalized%> not recognized"
++msgstr ""
++
++#: c-family/c.opt:717
++msgid "Warn if a C-style cast is used in a program."
++msgstr ""
++
++#: c-family/c.opt:721
++msgid "Warn for obsolescent usage in a declaration."
++msgstr ""
++
++#: c-family/c.opt:725
++msgid "Warn if an old-style parameter definition is used."
++msgstr ""
++
++#: c-family/c.opt:729
++msgid "Warn if a simd directive is overridden by the vectorizer cost model."
++msgstr ""
++
++#: c-family/c.opt:733
++msgid ""
++"Warn if a string is longer than the maximum portable length specified by the "
++"standard."
++msgstr ""
++
++#: c-family/c.opt:737
++msgid "Warn about overloaded virtual function names."
++msgstr ""
++
++#: c-family/c.opt:741
++msgid "Warn about overriding initializers without side effects."
++msgstr ""
++
++#: c-family/c.opt:745
++msgid "Warn about overriding initializers with side effects."
++msgstr ""
++
++#: c-family/c.opt:749
++msgid "Warn about packed bit-fields whose offset changed in GCC 4.4."
++msgstr ""
++
++#: c-family/c.opt:753
++msgid "Warn about possibly missing parentheses."
++msgstr ""
++
++#: c-family/c.opt:761
++msgid "Warn when converting the type of pointers to member functions."
++msgstr ""
++
++#: c-family/c.opt:765
++msgid "Warn about function pointer arithmetic."
++msgstr ""
++
++#: c-family/c.opt:769
++msgid "Warn when a pointer differs in signedness in an assignment."
++msgstr ""
++
++#: c-family/c.opt:773
++msgid "Warn when a pointer is cast to an integer of a different size."
++msgstr ""
++
++#: c-family/c.opt:777
++msgid "Warn about misuses of pragmas."
++msgstr ""
++
++#: c-family/c.opt:781
++msgid ""
++"Warn if a property for an Objective-C object has no assign semantics "
++"specified."
++msgstr ""
++
++#: c-family/c.opt:785
++msgid "Warn if inherited methods are unimplemented."
++msgstr ""
++
++#: c-family/c.opt:789 c-family/c.opt:793
++msgid "Warn for placement new expressions with undefined behavior."
++msgstr ""
++
++#: c-family/c.opt:797
++msgid "Warn about multiple declarations of the same object."
++msgstr ""
++
++#: c-family/c.opt:801
++msgid "Warn when the compiler reorders code."
++msgstr ""
++
++#: c-family/c.opt:805
++msgid ""
++"Warn whenever a function's return type defaults to \"int\" (C), or about "
++"inconsistent return types (C++)."
++msgstr ""
++
++#: c-family/c.opt:809
++msgid "Warn on suspicious constructs involving reverse scalar storage order."
++msgstr ""
++
++#: c-family/c.opt:813
++msgid "Warn if a selector has multiple methods."
++msgstr ""
++
++#: c-family/c.opt:817
++msgid "Warn about possible violations of sequence point rules."
++msgstr ""
++
++#: c-family/c.opt:821
++msgid "Warn if a local declaration hides an instance variable."
++msgstr ""
++
++#: c-family/c.opt:825 c-family/c.opt:829
++msgid "Warn if left shift of a signed value overflows."
++msgstr ""
++
++#: c-family/c.opt:833
++msgid "Warn if shift count is negative."
++msgstr ""
++
++#: c-family/c.opt:837
++msgid "Warn if shift count >= width of type."
++msgstr ""
++
++#: c-family/c.opt:841
++msgid "Warn if left shifting a negative value."
++msgstr ""
++
++#: c-family/c.opt:845
++msgid "Warn about signed-unsigned comparisons."
++msgstr ""
++
++#: c-family/c.opt:853
++msgid ""
++"Warn for implicit type conversions between signed and unsigned integers."
++msgstr ""
++
++#: c-family/c.opt:857
++msgid "Warn when overload promotes from unsigned to signed."
++msgstr ""
++
++#: c-family/c.opt:861
++msgid "Warn about uncasted NULL used as sentinel."
++msgstr ""
++
++#: c-family/c.opt:865
++msgid "Warn about unprototyped function declarations."
++msgstr ""
++
++#: c-family/c.opt:877
++msgid "Warn if type signatures of candidate methods do not match exactly."
++msgstr ""
++
++#: c-family/c.opt:881
++msgid ""
++"Warn when __sync_fetch_and_nand and __sync_nand_and_fetch built-in functions "
++"are used."
++msgstr ""
++
++#: c-family/c.opt:885
++msgid "Deprecated.  This switch has no effect."
++msgstr ""
++
++#: c-family/c.opt:893
++msgid "Warn if a comparison always evaluates to true or false."
++msgstr ""
++
++#: c-family/c.opt:897
++msgid "Warn if a throw expression will always result in a call to terminate()."
++msgstr ""
++
++#: c-family/c.opt:901
++msgid "Warn about features not present in traditional C."
++msgstr ""
++
++#: c-family/c.opt:905
++msgid ""
++"Warn of prototypes causing type conversions different from what would happen "
++"in the absence of prototype."
++msgstr ""
++
++#: c-family/c.opt:909
++msgid ""
++"Warn if trigraphs are encountered that might affect the meaning of the "
++"program."
++msgstr ""
++
++#: c-family/c.opt:913
++msgid "Warn about @selector()s without previously declared methods."
++msgstr ""
++
++#: c-family/c.opt:917
++msgid "Warn if an undefined macro is used in an #if directive."
++msgstr ""
++
++#: c-family/c.opt:929
++msgid "Warn about unrecognized pragmas."
++msgstr ""
++
++#: c-family/c.opt:933
++msgid "Warn about unsuffixed float constants."
++msgstr ""
++
++#: c-family/c.opt:941
++msgid "Warn when typedefs locally defined in a function are not used."
++msgstr ""
++
++#: c-family/c.opt:945
++msgid "Warn about macros defined in the main file that are not used."
++msgstr ""
++
++#: c-family/c.opt:949
++msgid ""
++"Warn if a caller of a function, marked with attribute warn_unused_result, "
++"does not use its return value."
++msgstr ""
++
++#: c-family/c.opt:957 c-family/c.opt:961
++msgid "Warn when a const variable is unused."
++msgstr ""
++
++#: c-family/c.opt:965
++msgid "Warn about using variadic macros."
++msgstr ""
++
++#: c-family/c.opt:969
++msgid ""
++"Warn about questionable usage of the macros used to retrieve variable "
++"arguments."
++msgstr ""
++
++#: c-family/c.opt:973
++msgid "Warn if a variable length array is used."
++msgstr ""
++
++#: c-family/c.opt:977
++msgid "Warn when a register variable is declared volatile."
++msgstr ""
++
++#: c-family/c.opt:981
++msgid "Warn on direct virtual inheritance."
++msgstr ""
++
++#: c-family/c.opt:985
++msgid "Warn if a virtual base has a non-trivial move assignment operator."
++msgstr ""
++
++#: c-family/c.opt:989
++msgid ""
++"In C++, nonzero means warn about deprecated conversion from string literals "
++"to 'char *'.  In C, similar warning, except that the conversion is of course "
++"not deprecated by the ISO C standard."
++msgstr ""
++
++#: c-family/c.opt:993
++msgid "Warn when a literal '0' is used as null pointer."
++msgstr ""
++
++#: c-family/c.opt:997
++msgid "Warn about useless casts."
++msgstr ""
++
++#: c-family/c.opt:1001
++msgid ""
++"Warn if a class type has a base or a field whose type uses the anonymous "
++"namespace or depends on a type with no linkage."
++msgstr ""
++
++#: c-family/c.opt:1005
++msgid "A synonym for -std=c89 (for C) or -std=c++98 (for C++)."
++msgstr ""
++
++#: c-family/c.opt:1013
++msgid ""
++"The version of the C++ ABI used for -Wabi warnings and link compatibility "
++"aliases."
++msgstr ""
++
++#: c-family/c.opt:1017
++msgid "Enforce class member access control semantics."
++msgstr ""
++
++#: c-family/c.opt:1021
++msgid "-fada-spec-parent=unit  Dump Ada specs as child units of given parent."
++msgstr ""
++
++#: c-family/c.opt:1028
++msgid "Allow variadic functions without named parameter."
++msgstr ""
++
++#: c-family/c.opt:1032 c-family/c.opt:1261 c-family/c.opt:1549
++#: c-family/c.opt:1553 c-family/c.opt:1569
++msgid "No longer supported."
++msgstr ""
++
++#: c-family/c.opt:1036
++msgid "Recognize the \"asm\" keyword."
++msgstr ""
++
++#: c-family/c.opt:1044
++msgid "Recognize built-in functions."
++msgstr ""
++
++#: c-family/c.opt:1051
++msgid "Where shorter, use canonicalized paths to systems headers."
++msgstr ""
++
++#: c-family/c.opt:1055
++msgid ""
++"Add Pointer Bounds Checker instrumentation.  fchkp-* flags are used to "
++"control instrumentation.  Currently available for C, C++ and ObjC."
++msgstr ""
++
++#: c-family/c.opt:1060
++msgid "Generate pointer bounds checks for variables with incomplete type."
++msgstr ""
++
++#: c-family/c.opt:1064
++msgid ""
++"Use zero bounds for all incoming arguments in 'main' function.  It helps "
++"when instrumented binaries are used with legacy libs."
++msgstr ""
++
++#: c-family/c.opt:1069
++msgid ""
++"Forces Pointer Bounds Checker to use narrowed bounds for address of the "
++"first field in the structure.  By default pointer to the first field has the "
++"same bounds as pointer to the whole structure."
++msgstr ""
++
++#: c-family/c.opt:1075
++msgid ""
++"Control how Pointer Bounds Checker handle pointers to object fields.  When "
++"narrowing is on, field bounds are used.  Otherwise full object bounds are "
++"used."
++msgstr ""
++
++#: c-family/c.opt:1080
++msgid ""
++"Forces Pointer Bounds Checker to use bounds of the innermost arrays in case "
++"of nested static arryas access.  By default outermost array is used."
++msgstr ""
++
++#: c-family/c.opt:1085
++msgid ""
++"Allow Pointer Bounds Checker optimizations.  By default allowed on "
++"optimization levels >0."
++msgstr ""
++
++#: c-family/c.opt:1090
++msgid ""
++"Allow to use *_nobnd versions of string functions by Pointer Bounds Checker."
++msgstr ""
++
++#: c-family/c.opt:1094
++msgid ""
++"Allow to use *_nochk versions of string functions by Pointer Bounds Checker."
++msgstr ""
++
++#: c-family/c.opt:1098
++msgid ""
++"Use statically initialized variable for vars bounds instead of generating "
++"them each time it is required."
++msgstr ""
++
++#: c-family/c.opt:1103
++msgid ""
++"Use statically initialized variable for constant bounds instead of "
++"generating them each time it is required."
++msgstr ""
++
++#: c-family/c.opt:1108
++msgid ""
++"With this option zero size obtained dynamically for objects with incomplete "
++"type will be treated as infinite."
++msgstr ""
++
++#: c-family/c.opt:1113
++msgid "Generate checks for all read accesses to memory."
++msgstr ""
++
++#: c-family/c.opt:1117
++msgid "Generate checks for all write accesses to memory."
++msgstr ""
++
++#: c-family/c.opt:1121
++msgid "Generate bounds stores for pointer writes."
++msgstr ""
++
++#: c-family/c.opt:1125
++msgid "Generate bounds passing for calls."
++msgstr ""
++
++#: c-family/c.opt:1129
++msgid "Instrument only functions marked with bnd_instrument attribute."
++msgstr ""
++
++#: c-family/c.opt:1133
++msgid "Transform instrumented builtin calls into calls to wrappers."
++msgstr ""
++
++#: c-family/c.opt:1143
++msgid "Enable Cilk Plus."
++msgstr ""
++
++#: c-family/c.opt:1147
++msgid "Enable support for C++ concepts."
++msgstr ""
++
++#: c-family/c.opt:1151
++msgid "Allow the arguments of the '?' operator to have different types."
++msgstr ""
++
++#: c-family/c.opt:1158
++#, c-format
++msgid "no class name specified with %qs"
++msgstr ""
++
++#: c-family/c.opt:1159
++msgid "-fconst-string-class=<name>\tUse class <name> for constant strings."
++msgstr ""
++
++#: c-family/c.opt:1163
++msgid "-fconstexpr-depth=<number>\tSpecify maximum constexpr recursion depth."
++msgstr ""
++
++#: c-family/c.opt:1167
++msgid "Emit debug annotations during preprocessing."
++msgstr ""
++
++#: c-family/c.opt:1171
++msgid ""
++"-fdeduce-init-list\tenable deduction of std::initializer_list for a template "
++"type parameter from a brace-enclosed initializer-list."
++msgstr ""
++
++#: c-family/c.opt:1175
++msgid "Factor complex constructors and destructors to favor space over speed."
++msgstr ""
++
++#: c-family/c.opt:1183
++msgid "Preprocess directives only."
++msgstr ""
++
++#: c-family/c.opt:1187
++msgid "Permit '$' as an identifier character."
++msgstr ""
++
++#: c-family/c.opt:1191
++msgid "Write all declarations as Ada code transitively."
++msgstr ""
++
++#: c-family/c.opt:1195
++msgid "Write all declarations as Ada code for the given file only."
++msgstr ""
++
++#: c-family/c.opt:1202
++msgid "Generate code to check exception specifications."
++msgstr ""
++
++#: c-family/c.opt:1209
++msgid ""
++"-fexec-charset=<cset>\tConvert all strings and character constants to "
++"character set <cset>."
++msgstr ""
++
++#: c-family/c.opt:1213
++msgid "Permit universal character names (\\u and \\U) in identifiers."
++msgstr ""
++
++#: c-family/c.opt:1217
++msgid ""
++"-finput-charset=<cset>\tSpecify the default character set for source files."
++msgstr ""
++
++#: c-family/c.opt:1221
++msgid ""
++"Support dynamic initialization of thread-local variables in a different "
++"translation unit."
++msgstr ""
++
++#: c-family/c.opt:1228
++msgid "Scope of for-init-statement variables is local to the loop."
++msgstr ""
++
++#: c-family/c.opt:1232
++msgid "Do not assume that standard C libraries and \"main\" exist."
++msgstr ""
++
++#: c-family/c.opt:1236
++msgid "Recognize GNU-defined keywords."
++msgstr ""
++
++#: c-family/c.opt:1240
++msgid "Generate code for GNU runtime environment."
++msgstr ""
++
++#: c-family/c.opt:1244
++msgid "Use traditional GNU semantics for inline functions."
++msgstr ""
++
++#: c-family/c.opt:1250
++msgid ""
++"-fhandle-exceptions has been renamed -fexceptions (and is now on by default)"
++msgstr ""
++
++#: c-family/c.opt:1257
++msgid "Assume normal C execution environment."
++msgstr ""
++
++#: c-family/c.opt:1265
++msgid "Export functions even if they can be inlined."
++msgstr ""
++
++#: c-family/c.opt:1269
++msgid "Emit implicit instantiations of inline templates."
++msgstr ""
++
++#: c-family/c.opt:1273
++msgid "Emit implicit instantiations of templates."
++msgstr ""
++
++#: c-family/c.opt:1277
++msgid "Inject friend functions into enclosing namespace."
++msgstr ""
++
++#: c-family/c.opt:1281
++msgid "Don't emit dllexported inline functions unless needed."
++msgstr ""
++
++#: c-family/c.opt:1288
++msgid ""
++"Allow implicit conversions between vectors with differing numbers of "
++"subparts and/or differing element types."
++msgstr ""
++
++#: c-family/c.opt:1292
++msgid "Don't warn about uses of Microsoft extensions."
++msgstr ""
++
++#: c-family/c.opt:1311
++msgid "Generate code for NeXT (Apple Mac OS X) runtime environment."
++msgstr ""
++
++#: c-family/c.opt:1315
++msgid "Assume that receivers of Objective-C messages may be nil."
++msgstr ""
++
++#: c-family/c.opt:1319
++msgid ""
++"Allow access to instance variables as if they were local declarations within "
++"instance method implementations."
++msgstr ""
++
++#: c-family/c.opt:1323
++msgid ""
++"-fvisibility=[private|protected|public|package]\tSet the default symbol "
++"visibility."
++msgstr ""
++
++#: c-family/c.opt:1326
++#, c-format
++msgid "unrecognized ivar visibility value %qs"
++msgstr ""
++
++#: c-family/c.opt:1348
++msgid ""
++"Treat a throw() exception specification as noexcept to improve code size."
++msgstr ""
++
++#: c-family/c.opt:1352
++msgid ""
++"Specify which ABI to use for Objective-C family code and meta-data "
++"generation."
++msgstr ""
++
++#: c-family/c.opt:1358
++msgid ""
++"Generate special Objective-C methods to initialize/destroy non-POD C++ "
++"ivars, if needed."
++msgstr ""
++
++#: c-family/c.opt:1362
++msgid "Allow fast jumps to the message dispatcher."
++msgstr ""
++
++#: c-family/c.opt:1368
++msgid "Enable Objective-C exception and synchronization syntax."
++msgstr ""
++
++#: c-family/c.opt:1372
++msgid "Enable garbage collection (GC) in Objective-C/Objective-C++ programs."
++msgstr ""
++
++#: c-family/c.opt:1376
++msgid ""
++"Enable inline checks for nil receivers with the NeXT runtime and ABI version "
++"2."
++msgstr ""
++
++#: c-family/c.opt:1381
++msgid "Enable Objective-C setjmp exception handling runtime."
++msgstr ""
++
++#: c-family/c.opt:1385
++msgid "Conform to the Objective-C 1.0 language as implemented in GCC 4.0."
++msgstr ""
++
++#: c-family/c.opt:1389
++msgid "Enable OpenACC."
++msgstr ""
++
++#: c-family/c.opt:1393
++msgid "Specify default OpenACC compute dimensions."
++msgstr ""
++
++#: c-family/c.opt:1397
++msgid "Enable OpenMP (implies -frecursive in Fortran)."
++msgstr ""
++
++#: c-family/c.opt:1401
++msgid "Enable OpenMP's SIMD directives."
++msgstr ""
++
++#: c-family/c.opt:1405
++msgid "Recognize C++ keywords like \"compl\" and \"xor\"."
++msgstr ""
++
++#: c-family/c.opt:1416
++msgid "Look for and use PCH files even when preprocessing."
++msgstr ""
++
++#: c-family/c.opt:1420
++msgid "Downgrade conformance errors to warnings."
++msgstr ""
++
++#: c-family/c.opt:1424
++msgid "Enable Plan 9 language extensions."
++msgstr ""
++
++#: c-family/c.opt:1428
++msgid "Treat the input file as already preprocessed."
++msgstr ""
++
++#: c-family/c.opt:1436
++msgid ""
++"-ftrack-macro-expansion=<0|1|2>  Track locations of tokens coming from macro "
++"expansion and display them in error messages."
++msgstr ""
++
++#: c-family/c.opt:1440
++msgid ""
++"-fno-pretty-templates Do not pretty-print template specializations as the "
++"template signature followed by the arguments."
++msgstr ""
++
++#: c-family/c.opt:1444
++msgid ""
++"Used in Fix-and-Continue mode to indicate that object files may be swapped "
++"in at runtime."
++msgstr ""
++
++#: c-family/c.opt:1448
++msgid "Enable automatic template instantiation."
++msgstr ""
++
++#: c-family/c.opt:1452
++msgid "Generate run time type descriptor information."
++msgstr ""
++
++#: c-family/c.opt:1460
++msgid "Force the underlying type for \"wchar_t\" to be \"unsigned short\"."
++msgstr ""
++
++#: c-family/c.opt:1464
++msgid "When \"signed\" or \"unsigned\" is not given make the bitfield signed."
++msgstr ""
++
++#: c-family/c.opt:1472
++msgid "Enable C++14 sized deallocation support."
++msgstr ""
++
++#: c-family/c.opt:1479
++msgid ""
++"-fsso-struct=[big-endian|little-endian]\tSet the default scalar storage "
++"order."
++msgstr ""
++
++#: c-family/c.opt:1482
++#, c-format
++msgid "unrecognized scalar storage order value %qs"
++msgstr ""
++
++#: c-family/c.opt:1492
++msgid "Display statistics accumulated during compilation."
++msgstr ""
++
++#: c-family/c.opt:1496
++msgid ""
++"Assume that values of enumeration type are always within the minimum range "
++"of that type."
++msgstr ""
++
++#: c-family/c.opt:1503
++msgid "-ftabstop=<number>\tDistance between tab stops for column reporting."
++msgstr ""
++
++#: c-family/c.opt:1507
++msgid ""
++"Set the maximum number of template instantiation notes for a single warning "
++"or error."
++msgstr ""
++
++#: c-family/c.opt:1514
++msgid ""
++"-ftemplate-depth=<number>\tSpecify maximum template instantiation depth."
++msgstr ""
++
++#: c-family/c.opt:1521
++msgid ""
++"-fno-threadsafe-statics\tDo not generate thread-safe code for initializing "
++"local statics."
++msgstr ""
++
++#: c-family/c.opt:1525
++msgid ""
++"When \"signed\" or \"unsigned\" is not given make the bitfield unsigned."
++msgstr ""
++
++#: c-family/c.opt:1529
++msgid "Make \"char\" unsigned by default."
++msgstr ""
++
++#: c-family/c.opt:1533
++msgid "Use __cxa_atexit to register destructors."
++msgstr ""
++
++#: c-family/c.opt:1537
++msgid "Use __cxa_get_exception_ptr in exception handling."
++msgstr ""
++
++#: c-family/c.opt:1541
++msgid "Marks all inlined functions and methods as having hidden visibility."
++msgstr ""
++
++#: c-family/c.opt:1545
++msgid "Changes visibility to match Microsoft Visual Studio by default."
++msgstr ""
++
++#: c-family/c.opt:1557
++msgid "Emit common-like symbols as weak symbols."
++msgstr ""
++
++#: c-family/c.opt:1561
++msgid ""
++"-fwide-exec-charset=<cset>\tConvert all wide strings and character constants "
++"to character set <cset>."
++msgstr ""
++
++#: c-family/c.opt:1565
++msgid "Generate a #line directive pointing at the current working directory."
++msgstr ""
++
++#: c-family/c.opt:1573
++msgid ""
++"Generate lazy class lookup (via objc_getClass()) for use in Zero-Link mode."
++msgstr ""
++
++#: c-family/c.opt:1577
++msgid "Dump declarations to a .decl file."
++msgstr ""
++
++#: c-family/c.opt:1581
++msgid ""
++"-femit-struct-debug-baseonly\tAggressive reduced debug info for structs."
++msgstr ""
++
++#: c-family/c.opt:1585
++msgid ""
++"-femit-struct-debug-reduced\tConservative reduced debug info for structs."
++msgstr ""
++
++#: c-family/c.opt:1589
++msgid ""
++"-femit-struct-debug-detailed=<spec-list>\tDetailed reduced debug info for "
++"structs."
++msgstr ""
++
++#: c-family/c.opt:1593
++msgid ""
++"Interpret imaginary, fixed-point, or other gnu number suffix as the "
++"corresponding number literal rather than a user-defined number literal."
++msgstr ""
++
++#: c-family/c.opt:1598
++msgid "-idirafter <dir>\tAdd <dir> to the end of the system include path."
++msgstr ""
++
++#: c-family/c.opt:1602
++msgid "-imacros <file>\tAccept definition of macros in <file>."
++msgstr ""
++
++#: c-family/c.opt:1606
++msgid "-imultilib <dir>\tSet <dir> to be the multilib include subdirectory."
++msgstr ""
++
++#: c-family/c.opt:1610
++msgid "-include <file>\tInclude the contents of <file> before other files."
++msgstr ""
++
++#: c-family/c.opt:1614
++msgid "-iprefix <path>\tSpecify <path> as a prefix for next two options."
++msgstr ""
++
++#: c-family/c.opt:1618
++msgid "-isysroot <dir>\tSet <dir> to be the system root directory."
++msgstr ""
++
++#: c-family/c.opt:1622
++msgid "-isystem <dir>\tAdd <dir> to the start of the system include path."
++msgstr ""
++
++#: c-family/c.opt:1626
++msgid "-iquote <dir>\tAdd <dir> to the end of the quote include path."
++msgstr ""
++
++#: c-family/c.opt:1630
++msgid "-iwithprefix <dir>\tAdd <dir> to the end of the system include path."
++msgstr ""
++
++#: c-family/c.opt:1634
++msgid ""
++"-iwithprefixbefore <dir>\tAdd <dir> to the end of the main include path."
++msgstr ""
++
++#: c-family/c.opt:1644
++msgid ""
++"Do not search standard system include directories (those specified with -"
++"isystem will still be used)."
++msgstr ""
++
++#: c-family/c.opt:1648
++msgid "Do not search standard system include directories for C++."
++msgstr ""
++
++#: c-family/c.opt:1660
++msgid "Generate C header of platform-specific features."
++msgstr ""
++
++#: c-family/c.opt:1664
++msgid "Remap file names when including files."
++msgstr ""
++
++#: c-family/c.opt:1668 c-family/c.opt:1672
++msgid ""
++"Conform to the ISO 1998 C++ standard revised by the 2003 technical "
++"corrigendum."
++msgstr ""
++
++#: c-family/c.opt:1676
++msgid "Conform to the ISO 2011 C++ standard."
++msgstr ""
++
++#: c-family/c.opt:1680
++msgid "Deprecated in favor of -std=c++11."
++msgstr ""
++
++#: c-family/c.opt:1684
++msgid "Deprecated in favor of -std=c++14."
++msgstr ""
++
++#: c-family/c.opt:1688
++msgid "Conform to the ISO 2014 C++ standard."
++msgstr ""
++
++#: c-family/c.opt:1692
++msgid ""
++"Conform to the ISO 2017(?) C++ draft standard (experimental and incomplete "
++"support)."
++msgstr ""
++
++#: c-family/c.opt:1699 c-family/c.opt:1796
++msgid "Conform to the ISO 2011 C standard."
++msgstr ""
++
++#: c-family/c.opt:1703
++msgid "Deprecated in favor of -std=c11."
++msgstr ""
++
++#: c-family/c.opt:1707 c-family/c.opt:1711 c-family/c.opt:1780
++msgid "Conform to the ISO 1990 C standard."
++msgstr ""
++
++#: c-family/c.opt:1715 c-family/c.opt:1788
++msgid "Conform to the ISO 1999 C standard."
++msgstr ""
++
++#: c-family/c.opt:1719
++msgid "Deprecated in favor of -std=c99."
++msgstr ""
++
++#: c-family/c.opt:1723 c-family/c.opt:1728
++msgid ""
++"Conform to the ISO 1998 C++ standard revised by the 2003 technical "
++"corrigendum with GNU extensions."
++msgstr ""
++
++#: c-family/c.opt:1733
++msgid "Conform to the ISO 2011 C++ standard with GNU extensions."
++msgstr ""
++
++#: c-family/c.opt:1737
++msgid "Deprecated in favor of -std=gnu++11."
++msgstr ""
++
++#: c-family/c.opt:1741
++msgid "Deprecated in favor of -std=gnu++14."
++msgstr ""
++
++#: c-family/c.opt:1745
++msgid "Conform to the ISO 2014 C++ standard with GNU extensions."
++msgstr ""
++
++#: c-family/c.opt:1749
++msgid ""
++"Conform to the ISO 201z(7?) C++ draft standard with GNU extensions "
++"(experimental and incomplete support)."
++msgstr ""
++
++#: c-family/c.opt:1756
++msgid "Conform to the ISO 2011 C standard with GNU extensions."
++msgstr ""
++
++#: c-family/c.opt:1760
++msgid "Deprecated in favor of -std=gnu11."
++msgstr ""
++
++#: c-family/c.opt:1764 c-family/c.opt:1768
++msgid "Conform to the ISO 1990 C standard with GNU extensions."
++msgstr ""
++
++#: c-family/c.opt:1772
++msgid "Conform to the ISO 1999 C standard with GNU extensions."
++msgstr ""
++
++#: c-family/c.opt:1776
++msgid "Deprecated in favor of -std=gnu99."
++msgstr ""
++
++#: c-family/c.opt:1784
++msgid "Conform to the ISO 1990 C standard as amended in 1994."
++msgstr ""
++
++#: c-family/c.opt:1792
++msgid "Deprecated in favor of -std=iso9899:1999."
++msgstr ""
++
++#: c-family/c.opt:1803
++msgid "Enable traditional preprocessing."
++msgstr ""
++
++#: c-family/c.opt:1807
++msgid "-trigraphs\tSupport ISO C trigraphs."
++msgstr ""
++
++#: c-family/c.opt:1811
++msgid "Do not predefine system-specific and GCC-specific macros."
++msgstr ""
++
++#: fortran/lang.opt:146
++msgid "-J<directory>\tPut MODULE files in 'directory'."
++msgstr ""
++
++#: fortran/lang.opt:198
++msgid "Warn about possible aliasing of dummy arguments."
++msgstr ""
++
++#: fortran/lang.opt:202
++msgid "Warn about alignment of COMMON blocks."
++msgstr ""
++
++#: fortran/lang.opt:206
++msgid "Warn about missing ampersand in continued character constants."
++msgstr ""
++
++#: fortran/lang.opt:210
++msgid "Warn about creation of array temporaries."
++msgstr ""
++
++#: fortran/lang.opt:214
++msgid "Warn if the type of a variable might be not interoperable with C."
++msgstr ""
++
++#: fortran/lang.opt:222
++msgid "Warn about truncated character expressions."
++msgstr ""
++
++#: fortran/lang.opt:226
++msgid "Warn about equality comparisons involving REAL or COMPLEX expressions."
++msgstr ""
++
++#: fortran/lang.opt:234
++msgid "Warn about most implicit conversions."
++msgstr ""
++
++#: fortran/lang.opt:242
++msgid "Warn about function call elimination."
++msgstr ""
++
++#: fortran/lang.opt:246
++msgid "Warn about calls with implicit interface."
++msgstr ""
++
++#: fortran/lang.opt:250
++msgid "Warn about called procedures not explicitly declared."
++msgstr ""
++
++#: fortran/lang.opt:254
++msgid "Warn about constant integer divisions with truncated results."
++msgstr ""
++
++#: fortran/lang.opt:258
++msgid "Warn about truncated source lines."
++msgstr ""
++
++#: fortran/lang.opt:262
++msgid "Warn on intrinsics not part of the selected standard."
++msgstr ""
++
++#: fortran/lang.opt:274
++msgid "Warn about USE statements that have no ONLY qualifier."
++msgstr ""
++
++#: fortran/lang.opt:286
++msgid "Warn about real-literal-constants with 'q' exponent-letter."
++msgstr ""
++
++#: fortran/lang.opt:290
++msgid "Warn when a left-hand-side array variable is reallocated."
++msgstr ""
++
++#: fortran/lang.opt:294
++msgid "Warn when a left-hand-side variable is reallocated."
++msgstr ""
++
++#: fortran/lang.opt:298
++msgid "Warn if the pointer in a pointer assignment might outlive its target."
++msgstr ""
++
++#: fortran/lang.opt:306
++msgid "Warn about \"suspicious\" constructs."
++msgstr ""
++
++#: fortran/lang.opt:310
++msgid "Permit nonconforming uses of the tab character."
++msgstr ""
++
++#: fortran/lang.opt:314
++msgid "Warn about underflow of numerical constant expressions."
++msgstr ""
++
++#: fortran/lang.opt:322
++msgid "Warn if a user-procedure has the same name as an intrinsic."
++msgstr ""
++
++#: fortran/lang.opt:330
++msgid "Warn about unused dummy arguments."
++msgstr ""
++
++#: fortran/lang.opt:334
++msgid "Warn about zero-trip DO loops."
++msgstr ""
++
++#: fortran/lang.opt:338
++msgid "Enable preprocessing."
++msgstr ""
++
++#: fortran/lang.opt:346
++msgid "Disable preprocessing."
++msgstr ""
++
++#: fortran/lang.opt:354
++msgid "Eliminate multiple function invokations also for impure functions."
++msgstr ""
++
++#: fortran/lang.opt:358
++msgid "Enable alignment of COMMON blocks."
++msgstr ""
++
++#: fortran/lang.opt:362
++msgid ""
++"All intrinsics procedures are available regardless of selected standard."
++msgstr ""
++
++#: fortran/lang.opt:370
++msgid ""
++"Do not treat local variables and COMMON blocks as if they were named in SAVE "
++"statements."
++msgstr ""
++
++#: fortran/lang.opt:374
++msgid "Specify that backslash in string introduces an escape character."
++msgstr ""
++
++#: fortran/lang.opt:378
++msgid "Produce a backtrace when a runtime error is encountered."
++msgstr ""
++
++#: fortran/lang.opt:382
++msgid ""
++"-fblas-matmul-limit=<n>\tSize of the smallest matrix for which matmul will "
++"use BLAS."
++msgstr ""
++
++#: fortran/lang.opt:386
++msgid ""
++"Produce a warning at runtime if a array temporary has been created for a "
++"procedure argument."
++msgstr ""
++
++#: fortran/lang.opt:390
++msgid ""
++"-fconvert=<big-endian|little-endian|native|swap> The endianness used for "
++"unformatted files."
++msgstr ""
++
++#: fortran/lang.opt:393
++#, c-format
++msgid "Unrecognized option to endianess value: %qs"
++msgstr ""
++
++#: fortran/lang.opt:409
++msgid "Use the Cray Pointer extension."
++msgstr ""
++
++#: fortran/lang.opt:413
++msgid "Ignore 'D' in column one in fixed form."
++msgstr ""
++
++#: fortran/lang.opt:417
++msgid "Treat lines with 'D' in column one as comments."
++msgstr ""
++
++#: fortran/lang.opt:421
++msgid "Enable all DEC language extensions."
++msgstr ""
++
++#: fortran/lang.opt:425
++msgid "Enable support for DEC STRUCTURE/RECORD."
++msgstr ""
++
++#: fortran/lang.opt:429
++msgid "Set the default double precision kind to an 8 byte wide type."
++msgstr ""
++
++#: fortran/lang.opt:433
++msgid "Set the default integer kind to an 8 byte wide type."
++msgstr ""
++
++#: fortran/lang.opt:437
++msgid "Set the default real kind to an 8 byte wide type."
++msgstr ""
++
++#: fortran/lang.opt:441
++msgid "Allow dollar signs in entity names."
++msgstr ""
++
++#: fortran/lang.opt:449
++msgid "Display the code tree after parsing."
++msgstr ""
++
++#: fortran/lang.opt:453
++msgid "Display the code tree after front end optimization."
++msgstr ""
++
++#: fortran/lang.opt:457
++msgid "Display the code tree after parsing; deprecated option."
++msgstr ""
++
++#: fortran/lang.opt:461
++msgid ""
++"Specify that an external BLAS library should be used for matmul calls on "
++"large-size arrays."
++msgstr ""
++
++#: fortran/lang.opt:465
++msgid "Use f2c calling convention."
++msgstr ""
++
++#: fortran/lang.opt:469
++msgid "Assume that the source file is fixed form."
++msgstr ""
++
++#: fortran/lang.opt:473
++msgid "Interpret any INTEGER(4) as an INTEGER(8)."
++msgstr ""
++
++#: fortran/lang.opt:477 fortran/lang.opt:481
++msgid "Specify where to find the compiled intrinsic modules."
++msgstr ""
++
++#: fortran/lang.opt:485
++msgid "Allow arbitrary character line width in fixed mode."
++msgstr ""
++
++#: fortran/lang.opt:489
++msgid "-ffixed-line-length-<n>\tUse n as character line width in fixed mode."
++msgstr ""
++
++#: fortran/lang.opt:493
++msgid "-ffpe-trap=[...]\tStop on following floating point exceptions."
++msgstr ""
++
++#: fortran/lang.opt:497
++msgid "-ffpe-summary=[...]\tPrint summary of floating point exceptions."
++msgstr ""
++
++#: fortran/lang.opt:501
++msgid "Assume that the source file is free form."
++msgstr ""
++
++#: fortran/lang.opt:505
++msgid "Allow arbitrary character line width in free mode."
++msgstr ""
++
++#: fortran/lang.opt:509
++msgid "-ffree-line-length-<n>\tUse n as character line width in free mode."
++msgstr ""
++
++#: fortran/lang.opt:513
++msgid "Enable front end optimization."
++msgstr ""
++
++#: fortran/lang.opt:517
++msgid ""
++"Specify that no implicit typing is allowed, unless overridden by explicit "
++"IMPLICIT statements."
++msgstr ""
++
++#: fortran/lang.opt:521
++msgid ""
++"-finit-character=<n>\tInitialize local character variables to ASCII value n."
++msgstr ""
++
++#: fortran/lang.opt:525
++msgid "-finit-integer=<n>\tInitialize local integer variables to n."
++msgstr ""
++
++#: fortran/lang.opt:529
++msgid "Initialize local variables to zero (from g77)."
++msgstr ""
++
++#: fortran/lang.opt:533
++msgid "-finit-logical=<true|false>\tInitialize local logical variables."
++msgstr ""
++
++#: fortran/lang.opt:537
++msgid "-finit-real=<zero|snan|nan|inf|-inf>\tInitialize local real variables."
++msgstr ""
++
++#: fortran/lang.opt:540
++#, c-format
++msgid "Unrecognized option to floating-point init value: %qs"
++msgstr ""
++
++#: fortran/lang.opt:559
++msgid ""
++"-finline-matmul-limit=<n>\tSpecify the size of the largest matrix for which "
++"matmul will be inlined."
++msgstr ""
++
++#: fortran/lang.opt:563
++msgid ""
++"-fmax-array-constructor=<n>\tMaximum number of objects in an array "
++"constructor."
++msgstr ""
++
++#: fortran/lang.opt:567
++msgid "-fmax-identifier-length=<n>\tMaximum identifier length."
++msgstr ""
++
++#: fortran/lang.opt:571
++msgid "-fmax-subrecord-length=<n>\tMaximum length for subrecords."
++msgstr ""
++
++#: fortran/lang.opt:575
++msgid ""
++"-fmax-stack-var-size=<n>\tSize in bytes of the largest array that will be "
++"put on the stack."
++msgstr ""
++
++#: fortran/lang.opt:579
++msgid "Put all local arrays on stack."
++msgstr ""
++
++#: fortran/lang.opt:583
++msgid "Set default accessibility of module entities to PRIVATE."
++msgstr ""
++
++#: fortran/lang.opt:603
++msgid "Try to lay out derived types as compactly as possible."
++msgstr ""
++
++#: fortran/lang.opt:611
++msgid "Protect parentheses in expressions."
++msgstr ""
++
++#: fortran/lang.opt:615
++msgid "Enable range checking during compilation."
++msgstr ""
++
++#: fortran/lang.opt:619
++msgid "Interpret any REAL(4) as a REAL(8)."
++msgstr ""
++
++#: fortran/lang.opt:623
++msgid "Interpret any REAL(4) as a REAL(10)."
++msgstr ""
++
++#: fortran/lang.opt:627
++msgid "Interpret any REAL(4) as a REAL(16)."
++msgstr ""
++
++#: fortran/lang.opt:631
++msgid "Interpret any REAL(8) as a REAL(4)."
++msgstr ""
++
++#: fortran/lang.opt:635
++msgid "Interpret any REAL(8) as a REAL(10)."
++msgstr ""
++
++#: fortran/lang.opt:639
++msgid "Interpret any REAL(8) as a REAL(16)."
++msgstr ""
++
++#: fortran/lang.opt:643
++msgid "Reallocate the LHS in assignments."
++msgstr ""
++
++#: fortran/lang.opt:647
++msgid "Use a 4-byte record marker for unformatted files."
++msgstr ""
++
++#: fortran/lang.opt:651
++msgid "Use an 8-byte record marker for unformatted files."
++msgstr ""
++
++#: fortran/lang.opt:655
++msgid "Allocate local variables on the stack to allow indirect recursion."
++msgstr ""
++
++#: fortran/lang.opt:659
++msgid "Copy array sections into a contiguous block on procedure entry."
++msgstr ""
++
++#: fortran/lang.opt:663
++msgid ""
++"-fcoarray=<none|single|lib>\tSpecify which coarray parallelization should be "
++"used."
++msgstr ""
++
++#: fortran/lang.opt:666
++#, c-format
++msgid "Unrecognized option: %qs"
++msgstr ""
++
++#: fortran/lang.opt:679
++msgid "-fcheck=[...]\tSpecify which runtime checks are to be performed."
++msgstr ""
++
++#: fortran/lang.opt:683
++msgid "Append a second underscore if the name already contains an underscore."
++msgstr ""
++
++#: fortran/lang.opt:691
++msgid "Apply negative sign to zero values."
++msgstr ""
++
++#: fortran/lang.opt:695
++msgid "Append underscores to externally visible names."
++msgstr ""
++
++#: fortran/lang.opt:739
++msgid "Statically link the GNU Fortran helper library (libgfortran)."
++msgstr ""
++
++#: fortran/lang.opt:743
++msgid "Conform to the ISO Fortran 2003 standard."
++msgstr ""
++
++#: fortran/lang.opt:747
++msgid "Conform to the ISO Fortran 2008 standard."
++msgstr ""
++
++#: fortran/lang.opt:751
++msgid "Conform to the ISO Fortran 2008 standard including TS 29113."
++msgstr ""
++
++#: fortran/lang.opt:755
++msgid "Conform to the ISO Fortran 95 standard."
++msgstr ""
++
++#: fortran/lang.opt:759
++msgid "Conform to nothing in particular."
++msgstr ""
++
++#: fortran/lang.opt:763
++msgid "Accept extensions to support legacy code."
++msgstr ""
++
++#: lto/lang.opt:28
++#, c-format
++msgid "unknown linker output %qs"
++msgstr ""
++
++#: lto/lang.opt:47
++msgid "Set linker output type (used internally during LTO optimization)"
++msgstr ""
++
++#: lto/lang.opt:52
++msgid "Run the link-time optimizer in local transformation (LTRANS) mode."
++msgstr ""
++
++#: lto/lang.opt:56
++msgid "Specify a file to which a list of files output by LTRANS is written."
++msgstr ""
++
++#: lto/lang.opt:60
++msgid "Run the link-time optimizer in whole program analysis (WPA) mode."
++msgstr ""
++
++#: lto/lang.opt:64
++msgid ""
++"Whole program analysis (WPA) mode with number of parallel jobs specified."
++msgstr ""
++
++#: lto/lang.opt:68
++msgid "The resolution file."
++msgstr ""
++
+ #: go/gofrontend/expressions.cc:93 c-family/c-common.c:1524 cp/cvt.c:1175
+ #: cp/cvt.c:1424
+ #, gcc-internal-format
+@@ -15641,7 +15725,7 @@
+ msgstr ""
+ 
+ #: go/gofrontend/expressions.cc:4015 c/c-parser.c:12578 c/c-parser.c:12585
+-#: cp/parser.c:31735 cp/parser.c:31742
++#: cp/parser.c:31750 cp/parser.c:31757
+ #, gcc-internal-format
+ msgid "expected integer"
+ msgstr ""
+@@ -16227,22 +16311,22 @@
+ msgid "invalid memory model for %<__atomic_store%>"
+ msgstr ""
+ 
+-#: builtins.c:5448
++#: builtins.c:5450
+ #, gcc-internal-format
+ msgid "non-constant argument 1 to __atomic_always_lock_free"
+ msgstr ""
+ 
+-#: builtins.c:5490
++#: builtins.c:5492
+ #, gcc-internal-format
+ msgid "non-integer argument 1 to __atomic_is_lock_free"
+ msgstr ""
+ 
+-#: builtins.c:5554
++#: builtins.c:5556
+ #, gcc-internal-format
+ msgid "__builtin_thread_pointer is not supported on this target"
+ msgstr ""
+ 
+-#: builtins.c:5574
++#: builtins.c:5576
+ #, gcc-internal-format
+ msgid "__builtin_set_thread_pointer is not supported on this target"
+ msgstr ""
+@@ -16249,7 +16333,7 @@
+ 
+ #. All valid uses of __builtin_va_arg_pack () are removed during
+ #. inlining.
+-#: builtins.c:5831 expr.c:10565
++#: builtins.c:5833 expr.c:10598
+ #, gcc-internal-format
+ msgid "%Kinvalid use of %<__builtin_va_arg_pack ()%>"
+ msgstr ""
+@@ -16256,12 +16340,12 @@
+ 
+ #. All valid uses of __builtin_va_arg_pack_len () are removed during
+ #. inlining.
+-#: builtins.c:5837
++#: builtins.c:5839
+ #, gcc-internal-format
+ msgid "%Kinvalid use of %<__builtin_va_arg_pack_len ()%>"
+ msgstr ""
+ 
+-#: builtins.c:6056
++#: builtins.c:6058
+ #, gcc-internal-format
+ msgid "%<__builtin_longjmp%> second argument must be 1"
+ msgstr ""
+@@ -16268,42 +16352,42 @@
+ 
+ #. Software implementation of Pointer Bounds Checker is NYI.
+ #. Target support is required.
+-#: builtins.c:6693
++#: builtins.c:6695
+ #, gcc-internal-format
+ msgid "Your target platform does not support -fcheck-pointer-bounds"
+ msgstr ""
+ 
+-#: builtins.c:7014
++#: builtins.c:7016
+ #, gcc-internal-format
+ msgid "target format does not support infinity"
+ msgstr ""
+ 
+-#: builtins.c:8916
++#: builtins.c:8918
+ #, gcc-internal-format
+ msgid "%<va_start%> used in function with fixed args"
+ msgstr ""
+ 
+-#: builtins.c:8924
++#: builtins.c:8926
+ #, gcc-internal-format
+ msgid "wrong number of arguments to function %<va_start%>"
+ msgstr ""
+ 
+-#: builtins.c:8939
++#: builtins.c:8941
+ #, gcc-internal-format
+ msgid "%<__builtin_next_arg%> called without an argument"
+ msgstr ""
+ 
+-#: builtins.c:8944
++#: builtins.c:8946
+ #, gcc-internal-format
+ msgid "wrong number of arguments to function %<__builtin_next_arg%>"
+ msgstr ""
+ 
+-#: builtins.c:8976
++#: builtins.c:8978
+ #, gcc-internal-format
+ msgid "second parameter of %<va_start%> not last named argument"
+ msgstr ""
+ 
+-#: builtins.c:8989
++#: builtins.c:8991
+ #, gcc-internal-format
+ msgid ""
+ "undefined behavior when second parameter of %<va_start%> is declared with "
+@@ -16310,32 +16394,32 @@
+ "%<register%> storage"
+ msgstr ""
+ 
+-#: builtins.c:9018
++#: builtins.c:9020
+ #, gcc-internal-format
+ msgid "%Kfirst argument of %D must be a pointer, second integer constant"
+ msgstr ""
+ 
+-#: builtins.c:9031
++#: builtins.c:9033
+ #, gcc-internal-format
+ msgid "%Klast argument of %D is not integer constant between 0 and 3"
+ msgstr ""
+ 
+-#: builtins.c:9076 builtins.c:9227 builtins.c:9284
++#: builtins.c:9078 builtins.c:9229 builtins.c:9286
+ #, gcc-internal-format
+ msgid "%Kcall to %D will always overflow destination buffer"
+ msgstr ""
+ 
+-#: builtins.c:9217
++#: builtins.c:9219
+ #, gcc-internal-format
+ msgid "%Kcall to %D might overflow destination buffer"
+ msgstr ""
+ 
+-#: builtins.c:9305
++#: builtins.c:9307
+ #, gcc-internal-format
+ msgid "%Kattempt to free a non-heap object %qD"
+ msgstr ""
+ 
+-#: builtins.c:9308
++#: builtins.c:9310
+ #, gcc-internal-format
+ msgid "%Kattempt to free a non-heap object"
+ msgstr ""
+@@ -16919,62 +17003,62 @@
+ msgid "number of bb notes in insn chain (%d) != n_basic_blocks (%d)"
+ msgstr ""
+ 
+-#: cgraph.c:2739
++#: cgraph.c:2742
+ #, gcc-internal-format
+ msgid "caller edge count is negative"
+ msgstr ""
+ 
+-#: cgraph.c:2744
++#: cgraph.c:2747
+ #, gcc-internal-format
+ msgid "caller edge frequency is negative"
+ msgstr ""
+ 
+-#: cgraph.c:2749
++#: cgraph.c:2752
+ #, gcc-internal-format
+ msgid "caller edge frequency is too large"
+ msgstr ""
+ 
+-#: cgraph.c:2833
++#: cgraph.c:2836
+ #, gcc-internal-format, gfc-internal-format
+ msgid "aux field set for edge %s->%s"
+ msgstr ""
+ 
+-#: cgraph.c:2840
++#: cgraph.c:2843
+ #, gcc-internal-format
+ msgid "execution count is negative"
+ msgstr ""
+ 
+-#: cgraph.c:2845
++#: cgraph.c:2848
+ #, gcc-internal-format
+ msgid "inline clone in same comdat group list"
+ msgstr ""
+ 
+-#: cgraph.c:2850
++#: cgraph.c:2853
+ #, gcc-internal-format
+ msgid "local symbols must be defined"
+ msgstr ""
+ 
+-#: cgraph.c:2855
++#: cgraph.c:2858
+ #, gcc-internal-format
+ msgid "externally visible inline clone"
+ msgstr ""
+ 
+-#: cgraph.c:2860
++#: cgraph.c:2863
+ #, gcc-internal-format
+ msgid "inline clone with address taken"
+ msgstr ""
+ 
+-#: cgraph.c:2865
++#: cgraph.c:2868
+ #, gcc-internal-format
+ msgid "inline clone is forced to output"
+ msgstr ""
+ 
+-#: cgraph.c:2872
++#: cgraph.c:2875
+ #, gcc-internal-format, gfc-internal-format
+ msgid "aux field set for indirect edge from %s"
+ msgstr ""
+ 
+-#: cgraph.c:2879
++#: cgraph.c:2882
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "An indirect edge from %s is not marked as indirect or has associated "
+@@ -16981,157 +17065,157 @@
+ "indirect_info, the corresponding statement is: "
+ msgstr ""
+ 
+-#: cgraph.c:2894
++#: cgraph.c:2897
+ #, gcc-internal-format, gfc-internal-format
+ msgid "comdat-local function called by %s outside its comdat"
+ msgstr ""
+ 
+-#: cgraph.c:2904
++#: cgraph.c:2907
+ #, gcc-internal-format
+ msgid "inlined_to pointer is wrong"
+ msgstr ""
+ 
+-#: cgraph.c:2909
++#: cgraph.c:2912
+ #, gcc-internal-format
+ msgid "multiple inline callers"
+ msgstr ""
+ 
+-#: cgraph.c:2916
++#: cgraph.c:2919
+ #, gcc-internal-format
+ msgid "inlined_to pointer set for noninline callers"
+ msgstr ""
+ 
+-#: cgraph.c:2935
++#: cgraph.c:2938
+ #, gcc-internal-format, gfc-internal-format
+ msgid "caller edge frequency %i does not match BB frequency %i"
+ msgstr ""
+ 
+-#: cgraph.c:2953
++#: cgraph.c:2956
+ #, gcc-internal-format, gfc-internal-format
+ msgid "indirect call frequency %i does not match BB frequency %i"
+ msgstr ""
+ 
+-#: cgraph.c:2962
++#: cgraph.c:2965
+ #, gcc-internal-format
+ msgid "inlined_to pointer is set but no predecessors found"
+ msgstr ""
+ 
+-#: cgraph.c:2967
++#: cgraph.c:2970
+ #, gcc-internal-format
+ msgid "inlined_to pointer refers to itself"
+ msgstr ""
+ 
+-#: cgraph.c:2979
++#: cgraph.c:2982
+ #, gcc-internal-format
+ msgid "cgraph_node has wrong clone_of"
+ msgstr ""
+ 
+-#: cgraph.c:2991
++#: cgraph.c:2994
+ #, gcc-internal-format
+ msgid "cgraph_node has wrong clone list"
+ msgstr ""
+ 
+-#: cgraph.c:2997
++#: cgraph.c:3000
+ #, gcc-internal-format
+ msgid "cgraph_node is in clone list but it is not clone"
+ msgstr ""
+ 
+-#: cgraph.c:3002
++#: cgraph.c:3005
+ #, gcc-internal-format
+ msgid "cgraph_node has wrong prev_clone pointer"
+ msgstr ""
+ 
+-#: cgraph.c:3007
++#: cgraph.c:3010
+ #, gcc-internal-format
+ msgid "double linked list of clones corrupted"
+ msgstr ""
+ 
+-#: cgraph.c:3019
++#: cgraph.c:3022
+ #, gcc-internal-format
+ msgid "Alias has call edges"
+ msgstr ""
+ 
+-#: cgraph.c:3027
++#: cgraph.c:3030
+ #, gcc-internal-format
+ msgid "Alias has non-alias reference"
+ msgstr ""
+ 
+-#: cgraph.c:3032
++#: cgraph.c:3035
+ #, gcc-internal-format
+ msgid "Alias has more than one alias reference"
+ msgstr ""
+ 
+-#: cgraph.c:3039
++#: cgraph.c:3042
+ #, gcc-internal-format
+ msgid "Analyzed alias has no reference"
+ msgstr ""
+ 
+-#: cgraph.c:3048
++#: cgraph.c:3051
+ #, gcc-internal-format
+ msgid "Instrumentation clone does not reference original node"
+ msgstr ""
+ 
+-#: cgraph.c:3055
++#: cgraph.c:3058
+ #, gcc-internal-format
+ msgid "Not instrumented node has non-NULL original declaration"
+ msgstr ""
+ 
+-#: cgraph.c:3065
++#: cgraph.c:3068
+ #, gcc-internal-format
+ msgid "Instrumented node has wrong original declaration"
+ msgstr ""
+ 
+-#: cgraph.c:3083
++#: cgraph.c:3086
+ #, gcc-internal-format
+ msgid "Node has more than one chkp reference"
+ msgstr ""
+ 
+-#: cgraph.c:3088
++#: cgraph.c:3091
+ #, gcc-internal-format
+ msgid "Wrong node is referenced with chkp reference"
+ msgstr ""
+ 
+-#: cgraph.c:3096
++#: cgraph.c:3099
+ #, gcc-internal-format
+ msgid "Analyzed node has no reference to instrumented version"
+ msgstr ""
+ 
+-#: cgraph.c:3110
++#: cgraph.c:3113
+ #, gcc-internal-format
+ msgid "Alias chain for instrumented node is broken"
+ msgstr ""
+ 
+-#: cgraph.c:3119
++#: cgraph.c:3122
+ #, gcc-internal-format
+ msgid "No edge out of thunk node"
+ msgstr ""
+ 
+-#: cgraph.c:3124
++#: cgraph.c:3127
+ #, gcc-internal-format
+ msgid "More than one edge out of thunk node"
+ msgstr ""
+ 
+-#: cgraph.c:3129
++#: cgraph.c:3132
+ #, gcc-internal-format
+ msgid "Thunk is not supposed to have body"
+ msgstr ""
+ 
+-#: cgraph.c:3135
++#: cgraph.c:3138
+ #, gcc-internal-format
+ msgid "Instrumentation thunk has wrong edge callee"
+ msgstr ""
+ 
+-#: cgraph.c:3171
++#: cgraph.c:3174
+ #, gcc-internal-format
+ msgid "shared call_stmt:"
+ msgstr ""
+ 
+-#: cgraph.c:3179
++#: cgraph.c:3182
+ #, gcc-internal-format
+ msgid "edge points to wrong declaration:"
+ msgstr ""
+ 
+-#: cgraph.c:3188
++#: cgraph.c:3191
+ #, gcc-internal-format
+ msgid ""
+ "an indirect edge with unknown callee corresponding to a call_stmt with a "
+@@ -17138,32 +17222,32 @@
+ "known declaration:"
+ msgstr ""
+ 
+-#: cgraph.c:3198
++#: cgraph.c:3201
+ #, gcc-internal-format
+ msgid "missing callgraph edge for call stmt:"
+ msgstr ""
+ 
+-#: cgraph.c:3208
++#: cgraph.c:3211
+ #, gcc-internal-format
+ msgid "reference to dead statement"
+ msgstr ""
+ 
+-#: cgraph.c:3221
++#: cgraph.c:3224
+ #, gcc-internal-format, gfc-internal-format
+ msgid "edge %s->%s has no corresponding call_stmt"
+ msgstr ""
+ 
+-#: cgraph.c:3233
++#: cgraph.c:3236
+ #, gcc-internal-format, gfc-internal-format
+ msgid "an indirect edge from %s has no corresponding call_stmt"
+ msgstr ""
+ 
+-#: cgraph.c:3244
++#: cgraph.c:3247
+ #, gcc-internal-format
+ msgid "verify_cgraph_node failed"
+ msgstr ""
+ 
+-#: cgraph.c:3343 varpool.c:304
++#: cgraph.c:3346 varpool.c:304
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s: section %s is missing"
+ msgstr ""
+@@ -17194,12 +17278,12 @@
+ msgstr ""
+ 
+ #. include_self=
+-#: cgraphunit.c:936 c/c-decl.c:10762
++#: cgraphunit.c:936 c/c-decl.c:10772
+ #, gcc-internal-format
+ msgid "%q+F used but never defined"
+ msgstr ""
+ 
+-#: cgraphunit.c:938 c/c-decl.c:10771 cp/decl.c:918
++#: cgraphunit.c:938 c/c-decl.c:10781 cp/decl.c:918
+ #, gcc-internal-format
+ msgid "%q+F declared %<static%> but never defined"
+ msgstr ""
+@@ -17420,28 +17504,28 @@
+ msgid "conversion to incomplete type"
+ msgstr ""
+ 
+-#: convert.c:942
++#: convert.c:943
+ #, gcc-internal-format
+ msgid ""
+ "can%'t convert a vector of type %qT to type %qT which has different size"
+ msgstr ""
+ 
+-#: convert.c:950
++#: convert.c:951
+ #, gcc-internal-format
+ msgid "aggregate value used where an integer was expected"
+ msgstr ""
+ 
+-#: convert.c:1035
++#: convert.c:1036
+ #, gcc-internal-format
+ msgid "pointer value used where a complex was expected"
+ msgstr ""
+ 
+-#: convert.c:1039
++#: convert.c:1040
+ #, gcc-internal-format
+ msgid "aggregate value used where a complex was expected"
+ msgstr ""
+ 
+-#: convert.c:1073
++#: convert.c:1074
+ #, gcc-internal-format
+ msgid ""
+ "can%'t convert a value of type %qT to vector type %qT which has different "
+@@ -17448,12 +17532,12 @@
+ "size"
+ msgstr ""
+ 
+-#: convert.c:1081
++#: convert.c:1082
+ #, gcc-internal-format
+ msgid "can%'t convert value to a vector"
+ msgstr ""
+ 
+-#: convert.c:1120
++#: convert.c:1121
+ #, gcc-internal-format
+ msgid "aggregate value used where a fixed-point was expected"
+ msgstr ""
+@@ -17609,12 +17693,12 @@
+ "cfi_personality directive"
+ msgstr ""
+ 
+-#: dwarf2out.c:12435
++#: dwarf2out.c:12436
+ #, gcc-internal-format, gfc-internal-format
+ msgid "non-delegitimized UNSPEC %s (%d) found in variable location"
+ msgstr ""
+ 
+-#: dwarf2out.c:25399
++#: dwarf2out.c:25400
+ #, gcc-internal-format
+ msgid "-feliminate-dwarf2-dups is broken for C++, ignoring"
+ msgstr ""
+@@ -17699,7 +17783,7 @@
+ msgid "verify_eh_tree failed"
+ msgstr ""
+ 
+-#: explow.c:1449
++#: explow.c:1457
+ #, gcc-internal-format
+ msgid "stack limits not supported on this target"
+ msgstr ""
+@@ -17726,12 +17810,12 @@
+ "truncated into %wu-bit"
+ msgstr ""
+ 
+-#: expr.c:10572
++#: expr.c:10605
+ #, gcc-internal-format
+ msgid "%Kcall to %qs declared with attribute error: %s"
+ msgstr ""
+ 
+-#: expr.c:10579
++#: expr.c:10612
+ #, gcc-internal-format
+ msgid "%Kcall to %qs declared with attribute warning: %s"
+ msgstr ""
+@@ -17746,12 +17830,12 @@
+ msgid "the frame size of %wd bytes is larger than %wd bytes"
+ msgstr ""
+ 
+-#: final.c:4589 toplev.c:1372 tree-cfgcleanup.c:1122
++#: final.c:4589 toplev.c:1372 tree-cfgcleanup.c:1140
+ #, gcc-internal-format
+ msgid "could not open final insn dump file %qs: %m"
+ msgstr ""
+ 
+-#: final.c:4642 tree-cfgcleanup.c:1138
++#: final.c:4642 tree-cfgcleanup.c:1156
+ #, gcc-internal-format
+ msgid "could not close final insn dump file %qs: %m"
+ msgstr ""
+@@ -17761,38 +17845,38 @@
+ msgid "large fixed-point constant implicitly truncated to fixed-point type"
+ msgstr ""
+ 
+-#: fold-const.c:3945 fold-const.c:3955
++#: fold-const.c:3946 fold-const.c:3956
+ #, gcc-internal-format, gfc-internal-format
+ msgid "comparison is always %d due to width of bit-field"
+ msgstr ""
+ 
+-#: fold-const.c:5321 tree-ssa-reassoc.c:2144
++#: fold-const.c:5322 tree-ssa-reassoc.c:2144
+ #, gcc-internal-format
+ msgid "assuming signed overflow does not occur when simplifying range test"
+ msgstr ""
+ 
+-#: fold-const.c:5770 fold-const.c:5784
++#: fold-const.c:5771 fold-const.c:5785
+ #, gcc-internal-format, gfc-internal-format
+ msgid "comparison is always %d"
+ msgstr ""
+ 
+-#: fold-const.c:5921
++#: fold-const.c:5922
+ #, gcc-internal-format
+ msgid "%<or%> of unmatched not-equal tests is always 1"
+ msgstr ""
+ 
+-#: fold-const.c:5926
++#: fold-const.c:5927
+ #, gcc-internal-format
+ msgid "%<and%> of mutually exclusive equal-tests is always 0"
+ msgstr ""
+ 
+-#: fold-const.c:8277
++#: fold-const.c:8278
+ #, gcc-internal-format
+ msgid ""
+ "assuming signed overflow does not occur when reducing constant in comparison"
+ msgstr ""
+ 
+-#: fold-const.c:8447
++#: fold-const.c:8448
+ #, gcc-internal-format
+ msgid ""
+ "assuming signed overflow does not occur when changing X +- C1 cmp C2 to X "
+@@ -17799,7 +17883,7 @@
+ "cmp C2 -+ C1"
+ msgstr ""
+ 
+-#: fold-const.c:8719
++#: fold-const.c:8720
+ #, gcc-internal-format
+ msgid ""
+ "assuming signed overflow does not occur when combining constants around a "
+@@ -17806,7 +17890,7 @@
+ "comparison"
+ msgstr ""
+ 
+-#: fold-const.c:12289
++#: fold-const.c:12290
+ #, gcc-internal-format
+ msgid "fold check: original tree changed by fold"
+ msgstr ""
+@@ -17816,7 +17900,7 @@
+ msgid "total size of local objects too large"
+ msgstr ""
+ 
+-#: function.c:1758 gimplify.c:5335
++#: function.c:1758 gimplify.c:5334
+ #, gcc-internal-format
+ msgid "impossible constraint in %<asm%>"
+ msgstr ""
+@@ -18319,10 +18403,10 @@
+ msgid "can%'t write PCH file"
+ msgstr ""
+ 
+-#: gimple-ssa-isolate-paths.c:290 gimple-ssa-isolate-paths.c:447 tree.c:12589
+-#: tree.c:12626 c/c-typeck.c:2847 c/c-typeck.c:2931 c/c-typeck.c:9680
+-#: c/c-typeck.c:9697 cp/call.c:6161 cp/constexpr.c:762 cp/constexpr.c:1969
+-#: cp/decl2.c:5112 cp/pt.c:7593 cp/semantics.c:1756 cp/typeck.c:1640
++#: gimple-ssa-isolate-paths.c:290 gimple-ssa-isolate-paths.c:447 tree.c:12600
++#: tree.c:12637 c/c-typeck.c:2847 c/c-typeck.c:2931 c/c-typeck.c:9690
++#: c/c-typeck.c:9707 cp/call.c:6161 cp/constexpr.c:762 cp/constexpr.c:2057
++#: cp/decl2.c:5145 cp/pt.c:7593 cp/semantics.c:1756 cp/typeck.c:1640
+ #: cp/typeck.c:1833 cp/typeck.c:3660
+ #, gcc-internal-format
+ msgid "declared here"
+@@ -18358,117 +18442,117 @@
+ msgid "using result of function returning %<void%>"
+ msgstr ""
+ 
+-#: gimplify.c:5194
++#: gimplify.c:5193
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid lvalue in asm output %d"
+ msgstr ""
+ 
+-#: gimplify.c:5336
++#: gimplify.c:5335
+ #, gcc-internal-format, gfc-internal-format
+ msgid "non-memory input %d must stay in memory"
+ msgstr ""
+ 
+-#: gimplify.c:5376 gimplify.c:5385
++#: gimplify.c:5375 gimplify.c:5384
+ #, gcc-internal-format, gfc-internal-format
+ msgid "memory input %d is not directly addressable"
+ msgstr ""
+ 
+-#: gimplify.c:5956
++#: gimplify.c:5955
+ #, gcc-internal-format
+ msgid "threadprivate variable %qE used in target region"
+ msgstr ""
+ 
+-#: gimplify.c:5958
++#: gimplify.c:5957
+ #, gcc-internal-format
+ msgid "enclosing target region"
+ msgstr ""
+ 
+-#: gimplify.c:5970
++#: gimplify.c:5969
+ #, gcc-internal-format
+ msgid "threadprivate variable %qE used in untied task"
+ msgstr ""
+ 
+-#: gimplify.c:5972
++#: gimplify.c:5971
+ #, gcc-internal-format
+ msgid "enclosing task"
+ msgstr ""
+ 
+-#: gimplify.c:6034
++#: gimplify.c:6033
+ #, gcc-internal-format
+ msgid "%qE not specified in enclosing %s"
+ msgstr ""
+ 
+-#: gimplify.c:6036
++#: gimplify.c:6035
+ #, gcc-internal-format, gfc-internal-format
+ msgid "enclosing %s"
+ msgstr ""
+ 
+-#: gimplify.c:6146
++#: gimplify.c:6145
+ #, gcc-internal-format
+ msgid "%qE not specified in enclosing OpenACC %qs construct"
+ msgstr ""
+ 
+-#: gimplify.c:6148
++#: gimplify.c:6147
+ #, gcc-internal-format
+ msgid "enclosing OpenACC %qs construct"
+ msgstr ""
+ 
+-#: gimplify.c:6199
++#: gimplify.c:6198
+ #, gcc-internal-format
+ msgid "%qE with %<link%> clause used in %<routine%> function"
+ msgstr ""
+ 
+-#: gimplify.c:6207
++#: gimplify.c:6206
+ #, gcc-internal-format
+ msgid "%qE requires a %<declare%> directive for use in a %<routine%> function"
+ msgstr ""
+ 
+-#: gimplify.c:6283 gimplify.c:6887
++#: gimplify.c:6282 gimplify.c:6886
+ #, gcc-internal-format
+ msgid "variable %qE declared in enclosing %<host_data%> region"
+ msgstr ""
+ 
+-#: gimplify.c:6301
++#: gimplify.c:6300
+ #, gcc-internal-format
+ msgid "%qD referenced in target region does not have a mappable type"
+ msgstr ""
+ 
+-#: gimplify.c:6419 gimplify.c:6451
++#: gimplify.c:6418 gimplify.c:6450
+ #, gcc-internal-format
+ msgid "iteration variable %qE is predetermined linear"
+ msgstr ""
+ 
+-#: gimplify.c:6422
++#: gimplify.c:6421
+ #, gcc-internal-format
+ msgid "iteration variable %qE should be private"
+ msgstr ""
+ 
+-#: gimplify.c:6436
++#: gimplify.c:6435
+ #, gcc-internal-format
+ msgid "iteration variable %qE should not be firstprivate"
+ msgstr ""
+ 
+-#: gimplify.c:6439
++#: gimplify.c:6438
+ #, gcc-internal-format
+ msgid "iteration variable %qE should not be reduction"
+ msgstr ""
+ 
+-#: gimplify.c:6442
++#: gimplify.c:6441
+ #, gcc-internal-format
+ msgid "iteration variable %qE should not be linear"
+ msgstr ""
+ 
+-#: gimplify.c:6445
++#: gimplify.c:6444
+ #, gcc-internal-format
+ msgid "iteration variable %qE should not be lastprivate"
+ msgstr ""
+ 
+-#: gimplify.c:6448
++#: gimplify.c:6447
+ #, gcc-internal-format
+ msgid "iteration variable %qE should not be private"
+ msgstr ""
+ 
+-#: gimplify.c:6761
++#: gimplify.c:6760
+ #, gcc-internal-format
+ msgid ""
+ "%<linear%> clause for variable other than loop iterator specified on "
+@@ -18475,33 +18559,33 @@
+ "construct combined with %<distribute%>"
+ msgstr ""
+ 
+-#: gimplify.c:6963
++#: gimplify.c:6962
+ #, gcc-internal-format
+ msgid "mapping field %qE of variable length structure"
+ msgstr ""
+ 
+-#: gimplify.c:7175
++#: gimplify.c:7174
+ #, gcc-internal-format
+ msgid "%qE appears more than once in map clauses"
+ msgstr ""
+ 
+-#: gimplify.c:7467
++#: gimplify.c:7466
+ #, gcc-internal-format
+ msgid ""
+ "copyprivate variable %qE is not threadprivate or private in outer context"
+ msgstr ""
+ 
+-#: gimplify.c:7487
++#: gimplify.c:7486
+ #, gcc-internal-format
+ msgid "%s variable %qE is private in outer context"
+ msgstr ""
+ 
+-#: gimplify.c:7513
++#: gimplify.c:7512
+ #, gcc-internal-format
+ msgid "expected %qs %<if%> clause modifier rather than %qs"
+ msgstr ""
+ 
+-#: gimplify.c:8015
++#: gimplify.c:8021
+ #, gcc-internal-format
+ msgid ""
+ "same variable used in %<firstprivate%> and %<lastprivate%> clauses on "
+@@ -18508,18 +18592,18 @@
+ "%<distribute%> construct"
+ msgstr ""
+ 
+-#: gimplify.c:8097
++#: gimplify.c:8103
+ #, gcc-internal-format
+ msgid ""
+ "incompatible data clause with reduction on %qE; promoting to present_or_copy"
+ msgstr ""
+ 
+-#: gimplify.c:8241
++#: gimplify.c:8247
+ #, gcc-internal-format
+ msgid "invalid private reduction on %qE"
+ msgstr ""
+ 
+-#: gimplify.c:10047 omp-low.c:3616
++#: gimplify.c:10053 omp-low.c:3623
+ #, gcc-internal-format
+ msgid ""
+ "%<ordered%> construct with %<depend%> clause must be closely nested inside a "
+@@ -18526,12 +18610,12 @@
+ "loop with %<ordered%> clause with a parameter"
+ msgstr ""
+ 
+-#: gimplify.c:10065
++#: gimplify.c:10071
+ #, gcc-internal-format
+ msgid "variable %qE is not an iteration of outermost loop %d, expected %qE"
+ msgstr ""
+ 
+-#: gimplify.c:10078
++#: gimplify.c:10084
+ #, gcc-internal-format
+ msgid ""
+ "number of variables in %<depend(sink)%> clause does not match number of "
+@@ -18538,12 +18622,12 @@
+ "iteration variables"
+ msgstr ""
+ 
+-#: gimplify.c:10091
++#: gimplify.c:10097
+ #, gcc-internal-format
+ msgid "more than one %<depend(source)%> clause on an %<ordered%> construct"
+ msgstr ""
+ 
+-#: gimplify.c:10102
++#: gimplify.c:10108
+ #, gcc-internal-format
+ msgid ""
+ "%<depend(source)%> clause specified together with %<depend(sink:)%> clauses "
+@@ -18550,32 +18634,32 @@
+ "on the same construct"
+ msgstr ""
+ 
+-#: gimplify.c:11030
++#: gimplify.c:11036
+ #, gcc-internal-format
+ msgid "expected %<_Cilk_spawn%> before %<_Cilk_sync%>"
+ msgstr ""
+ 
+-#: gimplify.c:11326
++#: gimplify.c:11332
+ #, gcc-internal-format
+ msgid "gimplification failed"
+ msgstr ""
+ 
+-#: gimplify.c:11796 c-family/c-common.c:5731 c-family/c-common.c:5804
++#: gimplify.c:11806 c-family/c-common.c:5731 c-family/c-common.c:5804
+ #, gcc-internal-format
+ msgid "first argument to %<va_arg%> not of type %<va_list%>"
+ msgstr ""
+ 
+-#: gimplify.c:11816
++#: gimplify.c:11826
+ #, gcc-internal-format
+ msgid "%qT is promoted to %qT when passed through %<...%>"
+ msgstr ""
+ 
+-#: gimplify.c:11821
++#: gimplify.c:11831
+ #, gcc-internal-format
+ msgid "(so you should pass %qT not %qT to %<va_arg%>)"
+ msgstr ""
+ 
+-#: gimplify.c:11828
++#: gimplify.c:11838
+ #, gcc-internal-format
+ msgid "if this code is reached, the program will abort"
+ msgstr ""
+@@ -19091,12 +19175,12 @@
+ msgid "Maximum number of LRA assignment passes is achieved (%d)\n"
+ msgstr ""
+ 
+-#: lra-constraints.c:3566 reload.c:3831 reload.c:4086
++#: lra-constraints.c:3591 reload.c:3831 reload.c:4086
+ #, gcc-internal-format
+ msgid "inconsistent operand constraints in an %<asm%>"
+ msgstr ""
+ 
+-#: lra-constraints.c:4429
++#: lra-constraints.c:4466
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Max. number of generated reload insns per insn is achieved (%d)\n"
+ msgstr ""
+@@ -19295,63 +19379,53 @@
+ msgid "default target_clones attribute was not set"
+ msgstr ""
+ 
+-#: multiple_target.c:256
++#: multiple_target.c:250
+ #, gcc-internal-format
+ msgid "single target_clones attribute is ignored"
+ msgstr ""
+ 
+-#: multiple_target.c:268
++#: multiple_target.c:262
+ #, gcc-internal-format
+ msgid "default target was not set"
+ msgstr ""
+ 
+-#: multiple_target.c:300
+-#, gcc-internal-format, gfc-internal-format
+-msgid "attribute(target_clones(\"%s\")) is not valid for current target"
+-msgstr ""
+-
+-#: multiple_target.c:331
++#: omp-low.c:2972 omp-low.c:19397
+ #, gcc-internal-format
+-msgid "attribute(target_clones(\"default\")) is not valid for current target"
+-msgstr ""
+-
+-#: omp-low.c:2965 omp-low.c:19388
+-#, gcc-internal-format
+ msgid "%<seq%> overrides other OpenACC loop specifiers"
+ msgstr ""
+ 
+-#: omp-low.c:2968
++#: omp-low.c:2975
+ #, gcc-internal-format
+ msgid "%<auto%> conflicts with other OpenACC loop specifiers"
+ msgstr ""
+ 
+-#: omp-low.c:2972
++#: omp-low.c:2979
+ #, gcc-internal-format
+ msgid "inner loop uses same OpenACC parallelism as containing loop"
+ msgstr ""
+ 
+-#: omp-low.c:3019
++#: omp-low.c:3026
+ #, gcc-internal-format
+ msgid "argument not permitted on %qs clause in OpenACC %<parallel%>"
+ msgstr ""
+ 
+-#: omp-low.c:3245
++#: omp-low.c:3252
+ #, gcc-internal-format
+ msgid "non-OpenACC construct inside of OpenACC routine"
+ msgstr ""
+ 
+-#: omp-low.c:3254
++#: omp-low.c:3261
+ #, gcc-internal-format
+ msgid "non-OpenACC construct inside of OpenACC region"
+ msgstr ""
+ 
+-#: omp-low.c:3279
++#: omp-low.c:3286
+ #, gcc-internal-format
+ msgid ""
+ "%<ordered simd threads%> must be closely nested inside of %<for simd%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3287
++#: omp-low.c:3294
+ #, gcc-internal-format
+ msgid ""
+ "OpenMP constructs other than %<#pragma omp ordered simd%> may not be nested "
+@@ -19358,7 +19432,7 @@
+ "inside %<simd%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3299
++#: omp-low.c:3306
+ #, gcc-internal-format
+ msgid ""
+ "only %<distribute%> or %<parallel%> regions are allowed to be strictly "
+@@ -19365,55 +19439,55 @@
+ "nested inside %<teams%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3316
++#: omp-low.c:3323
+ #, gcc-internal-format
+ msgid ""
+ "%<distribute%> region must be strictly nested inside %<teams%> construct"
+ msgstr ""
+ 
+-#: omp-low.c:3357
++#: omp-low.c:3364
+ #, gcc-internal-format
+ msgid ""
+ "OpenACC loop directive must be associated with an OpenACC compute region"
+ msgstr ""
+ 
+-#: omp-low.c:3379
++#: omp-low.c:3386
+ #, gcc-internal-format
+ msgid "orphaned %qs construct"
+ msgstr ""
+ 
+-#: omp-low.c:3408
++#: omp-low.c:3415
+ #, gcc-internal-format
+ msgid "%<#pragma omp cancel for%> inside %<nowait%> for construct"
+ msgstr ""
+ 
+-#: omp-low.c:3413
++#: omp-low.c:3420
+ #, gcc-internal-format
+ msgid "%<#pragma omp cancel for%> inside %<ordered%> for construct"
+ msgstr ""
+ 
+-#: omp-low.c:3433 omp-low.c:3446
++#: omp-low.c:3440 omp-low.c:3453
+ #, gcc-internal-format
+ msgid "%<#pragma omp cancel sections%> inside %<nowait%> sections construct"
+ msgstr ""
+ 
+-#: omp-low.c:3472
++#: omp-low.c:3479
+ #, gcc-internal-format
+ msgid ""
+ "%<%s taskgroup%> construct not closely nested inside of %<taskgroup%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3486
++#: omp-low.c:3493
+ #, gcc-internal-format
+ msgid "invalid arguments"
+ msgstr ""
+ 
+-#: omp-low.c:3492
++#: omp-low.c:3499
+ #, gcc-internal-format
+ msgid "%<%s %s%> construct not closely nested inside of %qs"
+ msgstr ""
+ 
+-#: omp-low.c:3520
++#: omp-low.c:3527
+ #, gcc-internal-format
+ msgid ""
+ "barrier region may not be closely nested inside of work-sharing, %<critical"
+@@ -19420,7 +19494,7 @@
+ "%>, %<ordered%>, %<master%>, explicit %<task%> or %<taskloop%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3527
++#: omp-low.c:3534
+ #, gcc-internal-format
+ msgid ""
+ "work-sharing region may not be closely nested inside of work-sharing, "
+@@ -19428,7 +19502,7 @@
+ "region"
+ msgstr ""
+ 
+-#: omp-low.c:3556
++#: omp-low.c:3563
+ #, gcc-internal-format
+ msgid ""
+ "%<master%> region may not be closely nested inside of work-sharing, explicit "
+@@ -19435,12 +19509,12 @@
+ "%<task%> or %<taskloop%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3580 omp-low.c:3719
++#: omp-low.c:3587 omp-low.c:3726
+ #, gcc-internal-format
+ msgid "%<depend(%s)%> is only allowed in %<omp ordered%>"
+ msgstr ""
+ 
+-#: omp-low.c:3608
++#: omp-low.c:3615
+ #, gcc-internal-format
+ msgid ""
+ "%<ordered%> construct with %<depend%> clause must be closely nested inside "
+@@ -19447,17 +19521,17 @@
+ "an %<ordered%> loop"
+ msgstr ""
+ 
+-#: omp-low.c:3625
++#: omp-low.c:3632
+ #, gcc-internal-format
+ msgid "invalid depend kind in omp %<ordered%> %<depend%>"
+ msgstr ""
+ 
+-#: omp-low.c:3640
++#: omp-low.c:3647
+ #, gcc-internal-format
+ msgid "%<ordered%> %<simd%> must be closely nested inside %<simd%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3653
++#: omp-low.c:3660
+ #, gcc-internal-format
+ msgid ""
+ "%<ordered%> region may not be closely nested inside of %<critical%>, "
+@@ -19464,7 +19538,7 @@
+ "%<ordered%>, explicit %<task%> or %<taskloop%> region"
+ msgstr ""
+ 
+-#: omp-low.c:3664 omp-low.c:3677
++#: omp-low.c:3671 omp-low.c:3684
+ #, gcc-internal-format
+ msgid ""
+ "%<ordered%> region must be closely nested inside a loop region with an "
+@@ -19471,7 +19545,7 @@
+ "%<ordered%> clause"
+ msgstr ""
+ 
+-#: omp-low.c:3694
++#: omp-low.c:3701
+ #, gcc-internal-format
+ msgid ""
+ "%<critical%> region may not be nested inside a %<critical%> region with the "
+@@ -19478,12 +19552,12 @@
+ "same name"
+ msgstr ""
+ 
+-#: omp-low.c:3706
++#: omp-low.c:3713
+ #, gcc-internal-format
+ msgid "%<teams%> construct not closely nested inside of %<target%> construct"
+ msgstr ""
+ 
+-#: omp-low.c:3727
++#: omp-low.c:3734
+ #, gcc-internal-format
+ msgid ""
+ "OpenACC region inside of OpenACC routine, nested parallelism not supported "
+@@ -19490,99 +19564,99 @@
+ "yet"
+ msgstr ""
+ 
+-#: omp-low.c:3740
++#: omp-low.c:3747
+ #, gcc-internal-format
+ msgid "OpenACC construct inside of non-OpenACC region"
+ msgstr ""
+ 
+-#: omp-low.c:3785
++#: omp-low.c:3792
+ #, gcc-internal-format
+ msgid "%s %qs construct inside of %s %qs region"
+ msgstr ""
+ 
+-#: omp-low.c:3798 omp-low.c:3805
++#: omp-low.c:3805 omp-low.c:3812
+ #, gcc-internal-format
+ msgid "%qs construct inside of %qs region"
+ msgstr ""
+ 
+-#: omp-low.c:3917
++#: omp-low.c:3924
+ #, gcc-internal-format
+ msgid "setjmp/longjmp inside simd construct"
+ msgstr ""
+ 
+-#: omp-low.c:8002
++#: omp-low.c:8011
+ #, gcc-internal-format
+ msgid "%<depend(sink)%> clause waiting for lexically later iteration"
+ msgstr ""
+ 
+-#: omp-low.c:8089
++#: omp-low.c:8098
+ #, gcc-internal-format
+ msgid "%<depend(sink)%> refers to iteration never in the iteration space"
+ msgstr ""
+ 
+-#: omp-low.c:12629
++#: omp-low.c:12638
+ #, gcc-internal-format
+ msgid "multiple loop axes specified for routine"
+ msgstr ""
+ 
+-#: omp-low.c:14650
++#: omp-low.c:14659
+ #, gcc-internal-format
+ msgid ""
+ "ignoring sink clause with offset that is not a multiple of the loop step"
+ msgstr ""
+ 
+-#: omp-low.c:14673
++#: omp-low.c:14682
+ #, gcc-internal-format
+ msgid "first offset must be in opposite direction of loop iterations"
+ msgstr ""
+ 
+-#: omp-low.c:18016
++#: omp-low.c:18025
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid exit from %s structured block"
+ msgstr ""
+ 
+-#: omp-low.c:18018 omp-low.c:18023
++#: omp-low.c:18027 omp-low.c:18032
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid entry to %s structured block"
+ msgstr ""
+ 
+ #. Otherwise, be vague and lazy, but efficient.
+-#: omp-low.c:18027
++#: omp-low.c:18036
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid branch to/from %s structured block"
+ msgstr ""
+ 
+-#: omp-low.c:18828
++#: omp-low.c:18837
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-fopenacc-dim operand is malformed at '%s'"
+ msgstr ""
+ 
+-#: omp-low.c:19415
++#: omp-low.c:19424
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s uses same OpenACC parallelism as containing loop"
+ msgstr ""
+ 
+-#: omp-low.c:19417 omp-low.c:19446
++#: omp-low.c:19426 omp-low.c:19455
+ #, gcc-internal-format
+ msgid "containing loop here"
+ msgstr ""
+ 
+-#: omp-low.c:19421
++#: omp-low.c:19430
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s uses OpenACC parallelism disallowed by containing routine"
+ msgstr ""
+ 
+-#: omp-low.c:19426
++#: omp-low.c:19435
+ #, gcc-internal-format
+ msgid "routine %qD declared here"
+ msgstr ""
+ 
+-#: omp-low.c:19439
++#: omp-low.c:19448
+ #, gcc-internal-format
+ msgid "incorrectly nested OpenACC loop parallelism"
+ msgstr ""
+ 
+-#: omp-low.c:19503
++#: omp-low.c:19512
+ #, gcc-internal-format
+ msgid "insufficient partitioning available to parallelize loop"
+ msgstr ""
+@@ -19711,7 +19785,7 @@
+ msgid "section anchors must be disabled when toplevel reorder is disabled"
+ msgstr ""
+ 
+-#: opts.c:813 config/darwin.c:3113
++#: opts.c:813 config/darwin.c:3164
+ #, gcc-internal-format
+ msgid ""
+ "-freorder-blocks-and-partition does not work with exceptions on this "
+@@ -20157,7 +20231,7 @@
+ msgid "register of %qD used for multiple global register variables"
+ msgstr ""
+ 
+-#: reginfo.c:777 config/rs6000/rs6000.c:28752
++#: reginfo.c:777 config/rs6000/rs6000.c:28816
+ #, gcc-internal-format
+ msgid "conflicts with %qD"
+ msgstr ""
+@@ -21675,12 +21749,12 @@
+ msgid "BB %i has incorrect fallthru edge"
+ msgstr ""
+ 
+-#: tree-inline.c:3528
++#: tree-inline.c:3536
+ #, gcc-internal-format
+ msgid "function %q+F can never be copied because it receives a non-local goto"
+ msgstr ""
+ 
+-#: tree-inline.c:3535
++#: tree-inline.c:3543
+ #, gcc-internal-format
+ msgid ""
+ "function %q+F can never be copied because it saves address of local label in "
+@@ -21687,7 +21761,7 @@
+ "a static variable"
+ msgstr ""
+ 
+-#: tree-inline.c:3575
++#: tree-inline.c:3583
+ #, gcc-internal-format
+ msgid ""
+ "function %q+F can never be inlined because it uses alloca (override using "
+@@ -21694,18 +21768,18 @@
+ "the always_inline attribute)"
+ msgstr ""
+ 
+-#: tree-inline.c:3589
++#: tree-inline.c:3597
+ #, gcc-internal-format
+ msgid "function %q+F can never be inlined because it uses setjmp"
+ msgstr ""
+ 
+-#: tree-inline.c:3603
++#: tree-inline.c:3611
+ #, gcc-internal-format
+ msgid ""
+ "function %q+F can never be inlined because it uses variable argument lists"
+ msgstr ""
+ 
+-#: tree-inline.c:3615
++#: tree-inline.c:3623
+ #, gcc-internal-format
+ msgid ""
+ "function %q+F can never be inlined because it uses setjmp-longjmp exception "
+@@ -21712,12 +21786,12 @@
+ "handling"
+ msgstr ""
+ 
+-#: tree-inline.c:3623
++#: tree-inline.c:3631
+ #, gcc-internal-format
+ msgid "function %q+F can never be inlined because it uses non-local goto"
+ msgstr ""
+ 
+-#: tree-inline.c:3635
++#: tree-inline.c:3643
+ #, gcc-internal-format
+ msgid ""
+ "function %q+F can never be inlined because it uses __builtin_return or "
+@@ -21724,18 +21798,18 @@
+ "__builtin_apply_args"
+ msgstr ""
+ 
+-#: tree-inline.c:3655
++#: tree-inline.c:3663
+ #, gcc-internal-format
+ msgid "function %q+F can never be inlined because it contains a computed goto"
+ msgstr ""
+ 
+-#: tree-inline.c:3756
++#: tree-inline.c:3764
+ #, gcc-internal-format
+ msgid ""
+ "function %q+F can never be inlined because it is suppressed using -fno-inline"
+ msgstr ""
+ 
+-#: tree-inline.c:3764
++#: tree-inline.c:3772
+ #, gcc-internal-format
+ msgid ""
+ "function %q+F can never be inlined because it uses attributes conflicting "
+@@ -21742,22 +21816,22 @@
+ "with inlining"
+ msgstr ""
+ 
+-#: tree-inline.c:4425
++#: tree-inline.c:4433
+ #, gcc-internal-format
+ msgid "inlining failed in call to always_inline %q+F: %s"
+ msgstr ""
+ 
+-#: tree-inline.c:4428 tree-inline.c:4448
++#: tree-inline.c:4436 tree-inline.c:4456
+ #, gcc-internal-format
+ msgid "called from here"
+ msgstr ""
+ 
+-#: tree-inline.c:4431 tree-inline.c:4451
++#: tree-inline.c:4439 tree-inline.c:4459
+ #, gcc-internal-format
+ msgid "called from this function"
+ msgstr ""
+ 
+-#: tree-inline.c:4444
++#: tree-inline.c:4452
+ #, gcc-internal-format
+ msgid "inlining failed in call to %q+F: %s"
+ msgstr ""
+@@ -22015,22 +22089,22 @@
+ msgid "vectorization did not happen for a simd loop"
+ msgstr ""
+ 
+-#: tree-vrp.c:6500 tree-vrp.c:6540 tree-vrp.c:6621
++#: tree-vrp.c:6532 tree-vrp.c:6572 tree-vrp.c:6653
+ #, gcc-internal-format
+ msgid "array subscript is above array bounds"
+ msgstr ""
+ 
+-#: tree-vrp.c:6524
++#: tree-vrp.c:6556
+ #, gcc-internal-format
+ msgid "array subscript is outside array bounds"
+ msgstr ""
+ 
+-#: tree-vrp.c:6553 tree-vrp.c:6608
++#: tree-vrp.c:6585 tree-vrp.c:6640
+ #, gcc-internal-format
+ msgid "array subscript is below array bounds"
+ msgstr ""
+ 
+-#: tree-vrp.c:7462
++#: tree-vrp.c:7490
+ #, gcc-internal-format
+ msgid ""
+ "assuming signed overflow does not occur when simplifying conditional to "
+@@ -22037,22 +22111,22 @@
+ "constant"
+ msgstr ""
+ 
+-#: tree-vrp.c:7468 tree-vrp.c:9432 tree-vrp.c:9476 tree-vrp.c:9539
++#: tree-vrp.c:7496 tree-vrp.c:9459 tree-vrp.c:9503 tree-vrp.c:9566
+ #, gcc-internal-format
+ msgid "assuming signed overflow does not occur when simplifying conditional"
+ msgstr ""
+ 
+-#: tree-vrp.c:7512
++#: tree-vrp.c:7540
+ #, gcc-internal-format
+ msgid "comparison always false due to limited range of data type"
+ msgstr ""
+ 
+-#: tree-vrp.c:7514
++#: tree-vrp.c:7542
+ #, gcc-internal-format
+ msgid "comparison always true due to limited range of data type"
+ msgstr ""
+ 
+-#: tree-vrp.c:9031
++#: tree-vrp.c:9058
+ #, gcc-internal-format
+ msgid ""
+ "assuming signed overflow does not occur when simplifying %</%> or %<%%%> to "
+@@ -22059,7 +22133,7 @@
+ "%<>>%> or %<&%>"
+ msgstr ""
+ 
+-#: tree-vrp.c:9096
++#: tree-vrp.c:9123
+ #, gcc-internal-format
+ msgid ""
+ "assuming signed overflow does not occur when simplifying %<min/max (X,Y)%> "
+@@ -22066,7 +22140,7 @@
+ "to %<X%> or %<Y%>"
+ msgstr ""
+ 
+-#: tree-vrp.c:9149
++#: tree-vrp.c:9176
+ #, gcc-internal-format
+ msgid ""
+ "assuming signed overflow does not occur when simplifying %<abs (X)%> to %<X"
+@@ -22123,12 +22197,12 @@
+ #: c-family/c-common.c:8827 c-family/c-common.c:8940 c-family/c-common.c:8967
+ #: c-family/c-common.c:9280 c-family/c-common.c:9303 c-family/c-common.c:9342
+ #: c-family/c-common.c:9424 c-family/c-common.c:9467 c-family/c-common.c:9604
+-#: config/darwin.c:2021 config/arm/arm.c:6488 config/arm/arm.c:6516
+-#: config/arm/arm.c:6533 config/avr/avr.c:8968 config/h8300/h8300.c:5477
+-#: config/h8300/h8300.c:5501 config/i386/i386.c:6862 config/i386/i386.c:44609
+-#: config/ia64/ia64.c:756 config/rs6000/rs6000.c:32417 config/spu/spu.c:3738
+-#: ada/gcc-interface/utils.c:6004 ada/gcc-interface/utils.c:6021
+-#: ada/gcc-interface/utils.c:6037 ada/gcc-interface/utils.c:6063
++#: config/darwin.c:2062 config/arm/arm.c:6488 config/arm/arm.c:6516
++#: config/arm/arm.c:6533 config/avr/avr.c:9004 config/h8300/h8300.c:5477
++#: config/h8300/h8300.c:5501 config/i386/i386.c:6855 config/i386/i386.c:44781
++#: config/ia64/ia64.c:756 config/rs6000/rs6000.c:32484 config/spu/spu.c:3738
++#: ada/gcc-interface/utils.c:6030 ada/gcc-interface/utils.c:6047
++#: ada/gcc-interface/utils.c:6063 ada/gcc-interface/utils.c:6089
+ #: lto/lto-lang.c:243
+ #, gcc-internal-format
+ msgid "%qE attribute ignored"
+@@ -22171,32 +22245,32 @@
+ msgid "function return type cannot be function"
+ msgstr ""
+ 
+-#: tree.c:9641 tree.c:9726 tree.c:9787
++#: tree.c:9651 tree.c:9736 tree.c:9797
+ #, gcc-internal-format, gfc-internal-format
+ msgid "tree check: %s, have %s in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9678
++#: tree.c:9688
+ #, gcc-internal-format, gfc-internal-format
+ msgid "tree check: expected none of %s, have %s in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9691
++#: tree.c:9701
+ #, gcc-internal-format
+ msgid "tree check: expected class %qs, have %qs (%s) in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9740
++#: tree.c:9750
+ #, gcc-internal-format
+ msgid "tree check: did not expect class %qs, have %qs (%s) in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9753
++#: tree.c:9763
+ #, gcc-internal-format, gfc-internal-format
+ msgid "tree check: expected omp_clause %s, have %s in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9813
++#: tree.c:9823
+ #, gcc-internal-format
+ msgid ""
+ "tree check: expected tree that contains %qs structure, have %qs in %s, at %s:"
+@@ -22203,23 +22277,23 @@
+ "%d"
+ msgstr ""
+ 
+-#: tree.c:9827
++#: tree.c:9837
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "tree check: accessed elt %d of tree_int_cst with %d elts in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9839
++#: tree.c:9849
+ #, gcc-internal-format, gfc-internal-format
+ msgid "tree check: accessed elt %d of tree_vec with %d elts in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9852
++#: tree.c:9862
+ #, gcc-internal-format, gfc-internal-format
+ msgid "tree check: accessed operand %d of %s with %d operands in %s, at %s:%d"
+ msgstr ""
+ 
+-#: tree.c:9865
++#: tree.c:9875
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "tree check: accessed operand %d of omp_clause %s with %d operands in %s, at "
+@@ -22226,32 +22300,32 @@
+ "%s:%d"
+ msgstr ""
+ 
+-#: tree.c:12584
++#: tree.c:12595
+ #, gcc-internal-format
+ msgid "%qD is deprecated: %s"
+ msgstr ""
+ 
+-#: tree.c:12587
++#: tree.c:12598
+ #, gcc-internal-format
+ msgid "%qD is deprecated"
+ msgstr ""
+ 
+-#: tree.c:12611 tree.c:12633
++#: tree.c:12622 tree.c:12644
+ #, gcc-internal-format
+ msgid "%qE is deprecated: %s"
+ msgstr ""
+ 
+-#: tree.c:12614 tree.c:12636
++#: tree.c:12625 tree.c:12647
+ #, gcc-internal-format
+ msgid "%qE is deprecated"
+ msgstr ""
+ 
+-#: tree.c:12620 tree.c:12641
++#: tree.c:12631 tree.c:12652
+ #, gcc-internal-format, gfc-internal-format
+ msgid "type is deprecated: %s"
+ msgstr ""
+ 
+-#: tree.c:12623 tree.c:12644
++#: tree.c:12634 tree.c:12655
+ #, gcc-internal-format
+ msgid "type is deprecated"
+ msgstr ""
+@@ -22278,252 +22352,252 @@
+ #. main variant only.
+ #.
+ #. Convenience macro for matching individual fields.
+-#: tree.c:13048
++#: tree.c:13059
+ #, gcc-internal-format
+ msgid "type variant differs by "
+ msgstr ""
+ 
+-#: tree.c:13088
++#: tree.c:13099
+ #, gcc-internal-format
+ msgid "type variant has different TYPE_SIZE_UNIT"
+ msgstr ""
+ 
+-#: tree.c:13090
++#: tree.c:13101
+ #, gcc-internal-format
+ msgid "type variant's TYPE_SIZE_UNIT"
+ msgstr ""
+ 
+-#: tree.c:13092
++#: tree.c:13103
+ #, gcc-internal-format
+ msgid "type's TYPE_SIZE_UNIT"
+ msgstr ""
+ 
+-#: tree.c:13112
++#: tree.c:13123
+ #, gcc-internal-format
+ msgid "type variant with TYPE_ALIAS_SET_KNOWN_P"
+ msgstr ""
+ 
+-#: tree.c:13125
++#: tree.c:13136
+ #, gcc-internal-format
+ msgid "type variant has different TYPE_VFIELD"
+ msgstr ""
+ 
+-#: tree.c:13142
++#: tree.c:13153
+ #, gcc-internal-format
+ msgid "type variant has TYPE_METHODS"
+ msgstr ""
+ 
+-#: tree.c:13167
++#: tree.c:13178
+ #, gcc-internal-format
+ msgid "type variant has different TYPE_BINFO"
+ msgstr ""
+ 
+-#: tree.c:13169
++#: tree.c:13180
+ #, gcc-internal-format
+ msgid "type variant's TYPE_BINFO"
+ msgstr ""
+ 
+-#: tree.c:13171
++#: tree.c:13182
+ #, gcc-internal-format
+ msgid "type's TYPE_BINFO"
+ msgstr ""
+ 
+-#: tree.c:13209
++#: tree.c:13220
+ #, gcc-internal-format
+ msgid "type variant has different TYPE_FIELDS"
+ msgstr ""
+ 
+-#: tree.c:13211
++#: tree.c:13222
+ #, gcc-internal-format
+ msgid "first mismatch is field"
+ msgstr ""
+ 
+-#: tree.c:13213
++#: tree.c:13224
+ #, gcc-internal-format
+ msgid "and field"
+ msgstr ""
+ 
+-#: tree.c:13230
++#: tree.c:13241
+ #, gcc-internal-format
+ msgid "type variant has different TREE_TYPE"
+ msgstr ""
+ 
+-#: tree.c:13232 tree.c:13243
++#: tree.c:13243 tree.c:13254
+ #, gcc-internal-format
+ msgid "type variant's TREE_TYPE"
+ msgstr ""
+ 
+-#: tree.c:13234 tree.c:13245
++#: tree.c:13245 tree.c:13256
+ #, gcc-internal-format
+ msgid "type's TREE_TYPE"
+ msgstr ""
+ 
+-#: tree.c:13241
++#: tree.c:13252
+ #, gcc-internal-format
+ msgid "type is not compatible with its vairant"
+ msgstr ""
+ 
+-#: tree.c:13540
++#: tree.c:13555
+ #, gcc-internal-format
+ msgid "Main variant is not defined"
+ msgstr ""
+ 
+-#: tree.c:13545
++#: tree.c:13560
+ #, gcc-internal-format
+ msgid "TYPE_MAIN_VARIANT has different TYPE_MAIN_VARIANT"
+ msgstr ""
+ 
+-#: tree.c:13557
++#: tree.c:13572
+ #, gcc-internal-format
+ msgid "TYPE_CANONICAL has different TYPE_CANONICAL"
+ msgstr ""
+ 
+-#: tree.c:13575
++#: tree.c:13590
+ #, gcc-internal-format
+ msgid "TYPE_CANONICAL is not compatible"
+ msgstr ""
+ 
+-#: tree.c:13583
++#: tree.c:13598
+ #, gcc-internal-format
+ msgid "TYPE_MODE of TYPE_CANONICAL is not compatible"
+ msgstr ""
+ 
+-#: tree.c:13591
++#: tree.c:13606
+ #, gcc-internal-format
+ msgid "TYPE_CANONICAL of main variant is not main variant"
+ msgstr ""
+ 
+-#: tree.c:13607
++#: tree.c:13622
+ #, gcc-internal-format
+ msgid "TYPE_VFIELD is not FIELD_DECL nor TREE_LIST"
+ msgstr ""
+ 
+-#: tree.c:13617
++#: tree.c:13632
+ #, gcc-internal-format
+ msgid "TYPE_NEXT_PTR_TO is not POINTER_TYPE"
+ msgstr ""
+ 
+-#: tree.c:13627
++#: tree.c:13642
+ #, gcc-internal-format
+ msgid "TYPE_NEXT_REF_TO is not REFERENCE_TYPE"
+ msgstr ""
+ 
+-#: tree.c:13645
++#: tree.c:13660
+ #, gcc-internal-format
+ msgid "TYPE_MINVAL non-NULL"
+ msgstr ""
+ 
+-#: tree.c:13657
++#: tree.c:13672
+ #, gcc-internal-format
+ msgid "TYPE_METHODS is not FUNCTION_DECL, TEMPLATE_DECL nor error_mark_node"
+ msgstr ""
+ 
+-#: tree.c:13668
++#: tree.c:13683
+ #, gcc-internal-format
+ msgid "TYPE_METHOD_BASETYPE is not record nor union"
+ msgstr ""
+ 
+-#: tree.c:13679
++#: tree.c:13694
+ #, gcc-internal-format
+ msgid "TYPE_OFFSET_BASETYPE is not record nor union"
+ msgstr ""
+ 
+-#: tree.c:13697
++#: tree.c:13712
+ #, gcc-internal-format
+ msgid "TYPE_ARRAY_MAX_SIZE not INTEGER_CST"
+ msgstr ""
+ 
+-#: tree.c:13704
++#: tree.c:13719
+ #, gcc-internal-format
+ msgid "TYPE_MAXVAL non-NULL"
+ msgstr ""
+ 
+-#: tree.c:13716
++#: tree.c:13731
+ #, gcc-internal-format
+ msgid "TYPE_BINFO is not TREE_BINFO"
+ msgstr ""
+ 
+-#: tree.c:13724
++#: tree.c:13739
+ #, gcc-internal-format
+ msgid "TYPE_BINFO type is not TYPE_MAIN_VARIANT"
+ msgstr ""
+ 
+-#: tree.c:13731
++#: tree.c:13746
+ #, gcc-internal-format
+ msgid "TYPE_LANG_SLOT_1 (binfo) field is non-NULL"
+ msgstr ""
+ 
+-#: tree.c:13747
++#: tree.c:13762
+ #, gcc-internal-format
+ msgid "Enum value is not CONST_DECL or INTEGER_CST"
+ msgstr ""
+ 
+-#: tree.c:13755
++#: tree.c:13770
+ #, gcc-internal-format
+ msgid "Enum value type is not INTEGER_TYPE nor convertible to the enum"
+ msgstr ""
+ 
+-#: tree.c:13762
++#: tree.c:13777
+ #, gcc-internal-format
+ msgid "Enum value name is not IDENTIFIER_NODE"
+ msgstr ""
+ 
+-#: tree.c:13772
++#: tree.c:13787
+ #, gcc-internal-format
+ msgid "Array TYPE_DOMAIN is not integer type"
+ msgstr ""
+ 
+-#: tree.c:13781
++#: tree.c:13796
+ #, gcc-internal-format
+ msgid "TYPE_FIELDS defined in incomplete type"
+ msgstr ""
+ 
+-#: tree.c:13801
++#: tree.c:13816
+ #, gcc-internal-format
+ msgid "Wrong tree in TYPE_FIELDS list"
+ msgstr ""
+ 
+-#: tree.c:13816
++#: tree.c:13831
+ #, gcc-internal-format
+ msgid "TYPE_CACHED_VALUES_P is %i while TYPE_CACHED_VALUES is %p"
+ msgstr ""
+ 
+-#: tree.c:13822
++#: tree.c:13837
+ #, gcc-internal-format
+ msgid "TYPE_CACHED_VALUES is not TREE_VEC"
+ msgstr ""
+ 
+-#: tree.c:13835
++#: tree.c:13850
+ #, gcc-internal-format
+ msgid "wrong TYPE_CACHED_VALUES entry"
+ msgstr ""
+ 
+-#: tree.c:13848
++#: tree.c:13863
+ #, gcc-internal-format
+ msgid "TREE_PURPOSE is non-NULL in TYPE_ARG_TYPES list"
+ msgstr ""
+ 
+-#: tree.c:13854
++#: tree.c:13869
+ #, gcc-internal-format
+ msgid "Wrong entry in TYPE_ARG_TYPES list"
+ msgstr ""
+ 
+-#: tree.c:13861
++#: tree.c:13876
+ #, gcc-internal-format
+ msgid "TYPE_VALUES_RAW field is non-NULL"
+ msgstr ""
+ 
+-#: tree.c:13873
++#: tree.c:13888
+ #, gcc-internal-format
+ msgid "TYPE_CACHED_VALUES_P is set while it should not"
+ msgstr ""
+ 
+-#: tree.c:13879
++#: tree.c:13894
+ #, gcc-internal-format
+ msgid "TYPE_STRING_FLAG is set on wrong type code"
+ msgstr ""
+ 
+-#: tree.c:13891
++#: tree.c:13906
+ #, gcc-internal-format
+ msgid ""
+ "TYPE_STRING_FLAG is set on type that does not look like char nor array of "
+@@ -22530,12 +22604,12 @@
+ "chars"
+ msgstr ""
+ 
+-#: tree.c:13903
++#: tree.c:13918
+ #, gcc-internal-format
+ msgid "TYPE_METHOD_BASETYPE is not main variant"
+ msgstr ""
+ 
+-#: tree.c:13910
++#: tree.c:13925
+ #, gcc-internal-format
+ msgid "verify_type failed"
+ msgstr ""
+@@ -22810,8 +22884,8 @@
+ "required to support"
+ msgstr ""
+ 
+-#: c-family/c-common.c:1126 c-family/c-common.c:1138 cp/constexpr.c:1619
+-#: cp/constexpr.c:3520
++#: c-family/c-common.c:1126 c-family/c-common.c:1138 cp/constexpr.c:1647
++#: cp/constexpr.c:3618
+ #, gcc-internal-format
+ msgid "overflow in constant expression"
+ msgstr ""
+@@ -23218,7 +23292,7 @@
+ msgid "suggest parentheses around assignment used as truth value"
+ msgstr ""
+ 
+-#: c-family/c-common.c:4668 c/c-decl.c:4126 c/c-typeck.c:13534
++#: c-family/c-common.c:4668 c/c-decl.c:4126 c/c-typeck.c:13544
+ #, gcc-internal-format
+ msgid "invalid use of %<restrict%>"
+ msgstr ""
+@@ -23293,7 +23367,7 @@
+ msgid "duplicate case value"
+ msgstr ""
+ 
+-#: c-family/c-common.c:6133 c-family/c-common.c:12710
++#: c-family/c-common.c:6133 c-family/c-common.c:12712
+ #, gcc-internal-format
+ msgid "previously used here"
+ msgstr ""
+@@ -23344,7 +23418,7 @@
+ msgstr ""
+ 
+ #: c-family/c-common.c:6684 c-family/c-common.c:6712 c-family/c-common.c:6808
+-#: ada/gcc-interface/utils.c:5995
++#: ada/gcc-interface/utils.c:6021
+ #, gcc-internal-format
+ msgid "%qE attribute ignored due to conflict with attribute %qs"
+ msgstr ""
+@@ -23683,7 +23757,7 @@
+ msgid "type was previously declared %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:8777 cp/class.c:4626
++#: c-family/c-common.c:8777 cp/class.c:4630
+ #, gcc-internal-format
+ msgid ""
+ "%<transaction_safe_dynamic%> may only be specified for a virtual function"
+@@ -23719,12 +23793,12 @@
+ msgid "invalid vector type for attribute %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9007 ada/gcc-interface/utils.c:3772
++#: c-family/c-common.c:9007 ada/gcc-interface/utils.c:3790
+ #, gcc-internal-format
+ msgid "vector size not an integral multiple of component size"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9013 ada/gcc-interface/utils.c:3779
++#: c-family/c-common.c:9013 ada/gcc-interface/utils.c:3797
+ #, gcc-internal-format
+ msgid "zero vector size"
+ msgstr ""
+@@ -23734,23 +23808,23 @@
+ msgid "number of components of the vector not a power of two"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9049 ada/gcc-interface/utils.c:5852
++#: c-family/c-common.c:9049 ada/gcc-interface/utils.c:5878
+ #, gcc-internal-format
+ msgid "nonnull attribute without arguments on a non-prototype"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9068 ada/gcc-interface/utils.c:5866
++#: c-family/c-common.c:9068 ada/gcc-interface/utils.c:5892
+ #, gcc-internal-format, gfc-internal-format
+ msgid "nonnull argument has invalid operand number (argument %lu)"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9090 ada/gcc-interface/utils.c:5888
++#: c-family/c-common.c:9090 ada/gcc-interface/utils.c:5914
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "nonnull argument with out-of-range operand number (argument %lu, operand %lu)"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9098 ada/gcc-interface/utils.c:5897
++#: c-family/c-common.c:9098 ada/gcc-interface/utils.c:5923
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "nonnull argument references non-pointer operand (argument %lu, operand %lu)"
+@@ -23791,12 +23865,12 @@
+ msgid "%qE attribute only applies to variadic functions"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9382 ada/gcc-interface/utils.c:5939
++#: c-family/c-common.c:9382 ada/gcc-interface/utils.c:5965
+ #, gcc-internal-format
+ msgid "requested position is not an integer constant"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9390 ada/gcc-interface/utils.c:5946
++#: c-family/c-common.c:9390 ada/gcc-interface/utils.c:5972
+ #, gcc-internal-format
+ msgid "requested position is less than zero"
+ msgstr ""
+@@ -23826,7 +23900,7 @@
+ msgid "not enough arguments to function %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:9815 c-family/c-common.c:10816 c/c-typeck.c:3213
++#: c-family/c-common.c:9815 c-family/c-common.c:10818 c/c-typeck.c:3213
+ #, gcc-internal-format
+ msgid "too many arguments to function %qE"
+ msgstr ""
+@@ -24096,102 +24170,102 @@
+ msgid "invalid type argument of implicit conversion (have %qT)"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10666 cp/init.c:2801 cp/init.c:2820
++#: c-family/c-common.c:10666 cp/init.c:2806 cp/init.c:2825
+ #, gcc-internal-format
+ msgid "size of array is too large"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10719 c-family/c-common.c:10790 c/c-typeck.c:3459
++#: c-family/c-common.c:10721 c-family/c-common.c:10792 c/c-typeck.c:3459
+ #, gcc-internal-format
+ msgid "too few arguments to function %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10749
++#: c-family/c-common.c:10751
+ #, gcc-internal-format
+ msgid "operand type %qT is incompatible with argument %d of %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10883
++#: c-family/c-common.c:10885
+ #, gcc-internal-format
+ msgid "incorrect number of arguments to function %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10898
++#: c-family/c-common.c:10900
+ #, gcc-internal-format
+ msgid "argument 1 of %qE must be a non-void pointer type"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10907
++#: c-family/c-common.c:10909
+ #, gcc-internal-format
+ msgid "argument 1 of %qE must be a pointer to a constant size type"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10918
++#: c-family/c-common.c:10920
+ #, gcc-internal-format
+ msgid "argument 1 of %qE must be a pointer to a nonzero size object"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10933
++#: c-family/c-common.c:10935
+ #, gcc-internal-format
+ msgid "argument %d of %qE must be a pointer type"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10941
++#: c-family/c-common.c:10943
+ #, gcc-internal-format
+ msgid "size mismatch in argument %d of %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10957
++#: c-family/c-common.c:10959
+ #, gcc-internal-format
+ msgid "invalid memory model argument %d of %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:10964
++#: c-family/c-common.c:10966
+ #, gcc-internal-format
+ msgid "non-integer memory model argument %d of %qE"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11562
++#: c-family/c-common.c:11564
+ #, gcc-internal-format
+ msgid "array subscript has type %<char%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11597 c-family/c-common.c:11600
++#: c-family/c-common.c:11599 c-family/c-common.c:11602
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<+%> inside %<<<%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11603 c-family/c-common.c:11606
++#: c-family/c-common.c:11605 c-family/c-common.c:11608
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<-%> inside %<<<%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11612 c-family/c-common.c:11615
++#: c-family/c-common.c:11614 c-family/c-common.c:11617
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<+%> inside %<>>%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11618 c-family/c-common.c:11621
++#: c-family/c-common.c:11620 c-family/c-common.c:11623
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<-%> inside %<>>%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11627 c-family/c-common.c:11630
++#: c-family/c-common.c:11629 c-family/c-common.c:11632
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<&&%> within %<||%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11637 c-family/c-common.c:11641
++#: c-family/c-common.c:11639 c-family/c-common.c:11643
+ #, gcc-internal-format
+ msgid "suggest parentheses around arithmetic in operand of %<|%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11645 c-family/c-common.c:11648
++#: c-family/c-common.c:11647 c-family/c-common.c:11650
+ #, gcc-internal-format
+ msgid "suggest parentheses around comparison in operand of %<|%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11653
++#: c-family/c-common.c:11655
+ #, gcc-internal-format
+ msgid ""
+ "suggest parentheses around operand of %<!%> or change %<|%> to %<||%> or %<!"
+@@ -24198,32 +24272,32 @@
+ "%> to %<~%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11661 c-family/c-common.c:11665
++#: c-family/c-common.c:11663 c-family/c-common.c:11667
+ #, gcc-internal-format
+ msgid "suggest parentheses around arithmetic in operand of %<^%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11669 c-family/c-common.c:11672
++#: c-family/c-common.c:11671 c-family/c-common.c:11674
+ #, gcc-internal-format
+ msgid "suggest parentheses around comparison in operand of %<^%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11678 c-family/c-common.c:11681
++#: c-family/c-common.c:11680 c-family/c-common.c:11683
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<+%> in operand of %<&%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11684 c-family/c-common.c:11687
++#: c-family/c-common.c:11686 c-family/c-common.c:11689
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<-%> in operand of %<&%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11691 c-family/c-common.c:11694
++#: c-family/c-common.c:11693 c-family/c-common.c:11696
+ #, gcc-internal-format
+ msgid "suggest parentheses around comparison in operand of %<&%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11699
++#: c-family/c-common.c:11701
+ #, gcc-internal-format
+ msgid ""
+ "suggest parentheses around operand of %<!%> or change %<&%> to %<&&%> or %<!"
+@@ -24230,94 +24304,94 @@
+ "%> to %<~%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11706 c-family/c-common.c:11709
++#: c-family/c-common.c:11708 c-family/c-common.c:11711
+ #, gcc-internal-format
+ msgid "suggest parentheses around comparison in operand of %<==%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11714 c-family/c-common.c:11717
++#: c-family/c-common.c:11716 c-family/c-common.c:11719
+ #, gcc-internal-format
+ msgid "suggest parentheses around comparison in operand of %<!=%>"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11727 c-family/c-common.c:11733
++#: c-family/c-common.c:11729 c-family/c-common.c:11735
+ #, gcc-internal-format
+ msgid "comparisons like %<X<=Y<=Z%> do not have their mathematical meaning"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11749
++#: c-family/c-common.c:11751
+ #, gcc-internal-format
+ msgid "label %q+D defined but not used"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11751
++#: c-family/c-common.c:11753
+ #, gcc-internal-format
+ msgid "label %q+D declared but not defined"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11767
++#: c-family/c-common.c:11769
+ #, gcc-internal-format
+ msgid "division by zero"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11799 c/c-typeck.c:11048 c/c-typeck.c:11205
++#: c-family/c-common.c:11801 c/c-typeck.c:11058 c/c-typeck.c:11215
+ #: cp/typeck.c:4820
+ #, gcc-internal-format
+ msgid "comparison between types %qT and %qT"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11850
++#: c-family/c-common.c:11852
+ #, gcc-internal-format
+ msgid "comparison between signed and unsigned integer expressions"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11901
++#: c-family/c-common.c:11903
+ #, gcc-internal-format
+ msgid "promoted ~unsigned is always non-zero"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11904
++#: c-family/c-common.c:11906
+ #, gcc-internal-format
+ msgid "comparison of promoted ~unsigned with constant"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11914
++#: c-family/c-common.c:11916
+ #, gcc-internal-format
+ msgid "comparison of promoted ~unsigned with unsigned"
+ msgstr ""
+ 
+-#: c-family/c-common.c:11965
++#: c-family/c-common.c:11967
+ #, gcc-internal-format
+ msgid "unused parameter %qD"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12109
++#: c-family/c-common.c:12111
+ #, gcc-internal-format
+ msgid "typedef %qD locally defined but not used"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12146 c-family/c-common.c:12172
++#: c-family/c-common.c:12148 c-family/c-common.c:12174
+ #, gcc-internal-format
+ msgid "comparison of constant %qE with boolean expression is always false"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12149 c-family/c-common.c:12169
++#: c-family/c-common.c:12151 c-family/c-common.c:12171
+ #, gcc-internal-format
+ msgid "comparison of constant %qE with boolean expression is always true"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12218
++#: c-family/c-common.c:12220
+ #, gcc-internal-format
+ msgid "result of %qE requires %u bits to represent, but %qT only has %u bits"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12467
++#: c-family/c-common.c:12469
+ #, gcc-internal-format
+ msgid "index value is out of bound"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12539 c-family/c-common.c:12587
+-#: c-family/c-common.c:12602 cp/call.c:4701 cp/call.c:4708
++#: c-family/c-common.c:12541 c-family/c-common.c:12589
++#: c-family/c-common.c:12604 cp/call.c:4701 cp/call.c:4708
+ #, gcc-internal-format
+ msgid "conversion of scalar %qT to vector %qT involves truncation"
+ msgstr ""
+@@ -24324,22 +24398,22 @@
+ 
+ #. Reject arguments that are built-in functions with
+ #. no library fallback.
+-#: c-family/c-common.c:12673
++#: c-family/c-common.c:12675
+ #, gcc-internal-format
+ msgid "built-in function %qE must be directly called"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12709
++#: c-family/c-common.c:12711
+ #, gcc-internal-format
+ msgid "duplicated %<if%> condition"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12736 c/c-decl.c:5913
++#: c-family/c-common.c:12738 c/c-decl.c:5923
+ #, gcc-internal-format
+ msgid "size of array %qE is too large"
+ msgstr ""
+ 
+-#: c-family/c-common.c:12738 c/c-decl.c:5916
++#: c-family/c-common.c:12740 c/c-decl.c:5926
+ #, gcc-internal-format
+ msgid "size of unnamed array is too large"
+ msgstr ""
+@@ -24811,7 +24885,7 @@
+ msgid "%<#pragma omp atomic capture%> uses two different variables for memory"
+ msgstr ""
+ 
+-#: c-family/c-omp.c:480 cp/semantics.c:8081
++#: c-family/c-omp.c:480 cp/semantics.c:8082
+ #, gcc-internal-format
+ msgid "invalid type for iteration variable %qE"
+ msgstr ""
+@@ -24821,22 +24895,22 @@
+ msgid "%qE is not initialized"
+ msgstr ""
+ 
+-#: c-family/c-omp.c:514 cp/semantics.c:7969
++#: c-family/c-omp.c:514 cp/semantics.c:7970
+ #, gcc-internal-format
+ msgid "missing controlling predicate"
+ msgstr ""
+ 
+-#: c-family/c-omp.c:599 cp/semantics.c:7633
++#: c-family/c-omp.c:599 cp/semantics.c:7634
+ #, gcc-internal-format
+ msgid "invalid controlling predicate"
+ msgstr ""
+ 
+-#: c-family/c-omp.c:606 cp/semantics.c:7975
++#: c-family/c-omp.c:606 cp/semantics.c:7976
+ #, gcc-internal-format
+ msgid "missing increment expression"
+ msgstr ""
+ 
+-#: c-family/c-omp.c:670 cp/semantics.c:7748
++#: c-family/c-omp.c:670 cp/semantics.c:7749
+ #, gcc-internal-format
+ msgid "invalid increment expression"
+ msgstr ""
+@@ -25348,37 +25422,37 @@
+ msgid "<type-error>"
+ msgstr ""
+ 
+-#: c-family/c-pretty-print.c:366
++#: c-family/c-pretty-print.c:369
+ #, gcc-internal-format
+ msgid "<unnamed-unsigned:"
+ msgstr ""
+ 
+-#: c-family/c-pretty-print.c:370
++#: c-family/c-pretty-print.c:373
+ #, gcc-internal-format
+ msgid "<unnamed-float:"
+ msgstr ""
+ 
+-#: c-family/c-pretty-print.c:373
++#: c-family/c-pretty-print.c:376
+ #, gcc-internal-format
+ msgid "<unnamed-fixed:"
+ msgstr ""
+ 
+-#: c-family/c-pretty-print.c:388
++#: c-family/c-pretty-print.c:391
+ #, gcc-internal-format
+ msgid "<typedef-error>"
+ msgstr ""
+ 
+-#: c-family/c-pretty-print.c:403
++#: c-family/c-pretty-print.c:406
+ #, gcc-internal-format
+ msgid "<tag-error>"
+ msgstr ""
+ 
+-#: c-family/c-pretty-print.c:1241
++#: c-family/c-pretty-print.c:1244
+ #, gcc-internal-format
+ msgid "<erroneous-expression>"
+ msgstr ""
+ 
+-#: c-family/c-pretty-print.c:1245 cp/cxx-pretty-print.c:140
++#: c-family/c-pretty-print.c:1248 cp/cxx-pretty-print.c:140
+ #, gcc-internal-format
+ msgid "<return-value>"
+ msgstr ""
+@@ -25388,7 +25462,7 @@
+ msgid "wrong type argument to %s"
+ msgstr ""
+ 
+-#: c-family/cilk.c:93 cp/parser.c:6518
++#: c-family/cilk.c:93 cp/parser.c:6523
+ #, gcc-internal-format
+ msgid "%<_Cilk_spawn%> may only be used inside a function"
+ msgstr ""
+@@ -25468,47 +25542,47 @@
+ msgid "-mcpu=%s has invalid silicon revision"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:985
++#: common/config/i386/i386-common.c:970
+ #, gcc-internal-format
+ msgid "-malign-loops is obsolete, use -falign-loops"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:987
++#: common/config/i386/i386-common.c:972
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-malign-loops=%d is not between 0 and %d"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:994
++#: common/config/i386/i386-common.c:979
+ #, gcc-internal-format
+ msgid "-malign-jumps is obsolete, use -falign-jumps"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:996
++#: common/config/i386/i386-common.c:981
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-malign-jumps=%d is not between 0 and %d"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:1004
++#: common/config/i386/i386-common.c:989
+ #, gcc-internal-format
+ msgid "-malign-functions is obsolete, use -falign-functions"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:1006
++#: common/config/i386/i386-common.c:991
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-malign-functions=%d is not between 0 and %d"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:1015
++#: common/config/i386/i386-common.c:1000
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-mbranch-cost=%d is not between 0 and 5"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:1069
++#: common/config/i386/i386-common.c:1054
+ #, gcc-internal-format
+ msgid "%<-fsplit-stack%> currently only supported on GNU/Linux"
+ msgstr ""
+ 
+-#: common/config/i386/i386-common.c:1075
++#: common/config/i386/i386-common.c:1060
+ #, gcc-internal-format
+ msgid "%<-fsplit-stack%> requires assembler support for CFI directives"
+ msgstr ""
+@@ -25653,53 +25727,53 @@
+ msgid "sysctl for kern.osversion failed: %m"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:84
++#: config/darwin-driver.c:85
+ #, gcc-internal-format
+ msgid "couldn%'t understand kern.osversion %q.*s"
+ msgstr ""
+ 
+ #. Arbitrary limit, number should be like xx.yy.zz
+-#: config/darwin-driver.c:124
++#: config/darwin-driver.c:125
+ #, gcc-internal-format
+ msgid "couldn%'t understand version %s\n"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:177
++#: config/darwin-driver.c:178
+ #, gcc-internal-format, gfc-internal-format
+ msgid "this compiler does not support %s"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:232
++#: config/darwin-driver.c:233
+ #, gcc-internal-format
+ msgid "this compiler does not support PowerPC (arch flags ignored)"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:236
++#: config/darwin-driver.c:237
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s conflicts with i386 (arch flags ignored)"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:244
++#: config/darwin-driver.c:245
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s conflicts with x86_64 (arch flags ignored)"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:251
++#: config/darwin-driver.c:252
+ #, gcc-internal-format
+ msgid "this compiler does not support X86 (arch flags ignored)"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:255
++#: config/darwin-driver.c:256
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s conflicts with ppc (arch flags ignored)"
+ msgstr ""
+ 
+-#: config/darwin-driver.c:263
++#: config/darwin-driver.c:264
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s conflicts with ppc64 (arch flags ignored)"
+ msgstr ""
+ 
+-#: config/darwin.c:1650
++#: config/darwin.c:1691
+ #, gcc-internal-format
+ msgid ""
+ "the use of _OBJC_-prefixed variable names to select meta-data sections is "
+@@ -25706,34 +25780,34 @@
+ "deprecated at 4.6 and will be removed in 4.7"
+ msgstr ""
+ 
+-#: config/darwin.c:1905
++#: config/darwin.c:1946
+ #, gcc-internal-format, gfc-internal-format
+ msgid "failed to open temporary file %s for LTO output"
+ msgstr ""
+ 
+-#: config/darwin.c:1994
++#: config/darwin.c:2035
+ #, gcc-internal-format
+ msgid ""
+ "%qE 2.95 vtable-compatibility attribute applies only when compiling a kext"
+ msgstr ""
+ 
+-#: config/darwin.c:2001
++#: config/darwin.c:2042
+ #, gcc-internal-format
+ msgid "%qE 2.95 vtable-compatibility attribute applies only to C++ classes"
+ msgstr ""
+ 
+-#: config/darwin.c:2713
++#: config/darwin.c:2758
+ #, gcc-internal-format
+ msgid ""
+ "protected visibility attribute not supported in this configuration; ignored"
+ msgstr ""
+ 
+-#: config/darwin.c:2899
++#: config/darwin.c:2944
+ #, gcc-internal-format, gfc-internal-format
+ msgid "failed to open temporary file %s with LTO output"
+ msgstr ""
+ 
+-#: config/darwin.c:3072
++#: config/darwin.c:3123
+ #, gcc-internal-format
+ msgid ""
+ "%<-fobjc-abi-version%> >= 2 must be used for %<-m64%> targets with %<-fnext-"
+@@ -25740,7 +25814,7 @@
+ "runtime%>"
+ msgstr ""
+ 
+-#: config/darwin.c:3076
++#: config/darwin.c:3127
+ #, gcc-internal-format
+ msgid ""
+ "%<-fobjc-abi-version%> >= 2 is not supported on %<-m32%> targets with %<-"
+@@ -25747,33 +25821,33 @@
+ "fnext-runtime%>"
+ msgstr ""
+ 
+-#: config/darwin.c:3161
++#: config/darwin.c:3212
+ #, gcc-internal-format
+ msgid ""
+ "%<-mdynamic-no-pic%> overrides %<-fpic%>, %<-fPIC%>, %<-fpie%> or %<-fPIE%>"
+ msgstr ""
+ 
+-#: config/darwin.c:3349
++#: config/darwin.c:3400
+ #, gcc-internal-format
+ msgid "built-in function %qD requires the %<-mconstant-cfstrings%> flag"
+ msgstr ""
+ 
+-#: config/darwin.c:3356
++#: config/darwin.c:3407
+ #, gcc-internal-format
+ msgid "built-in function %qD takes one argument only"
+ msgstr ""
+ 
+-#: config/darwin.c:3442
++#: config/darwin.c:3493
+ #, gcc-internal-format
+ msgid "CFString literal is missing"
+ msgstr ""
+ 
+-#: config/darwin.c:3453
++#: config/darwin.c:3504
+ #, gcc-internal-format
+ msgid "CFString literal expression is not a string constant"
+ msgstr ""
+ 
+-#: config/darwin.c:3476
++#: config/darwin.c:3527
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s in CFString literal"
+ msgstr ""
+@@ -25853,7 +25927,7 @@
+ #. coalesced sections.  Weak aliases (or any other kind of aliases) are
+ #. not supported.  Weak symbols that aren't visible outside the .s file
+ #. are not supported.
+-#: config/darwin.h:453
++#: config/darwin.h:478
+ #, gcc-internal-format
+ msgid "alias definitions not supported in Mach-O; ignored"
+ msgstr ""
+@@ -26039,12 +26113,12 @@
+ msgid "malformed target %s list %qs"
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.c:10813
++#: config/aarch64/aarch64.c:10811
+ #, gcc-internal-format
+ msgid "%Klane %wd out of range %wd - %wd"
+ msgstr ""
+ 
+-#: config/aarch64/aarch64.c:10815
++#: config/aarch64/aarch64.c:10813
+ #, gcc-internal-format
+ msgid "lane %wd out of range %wd - %wd"
+ msgstr ""
+@@ -26692,14 +26766,14 @@
+ msgid "Thumb-1 hard-float VFP ABI"
+ msgstr ""
+ 
+-#: config/arm/arm.c:6456 config/arm/arm.c:6474 config/avr/avr.c:8988
+-#: config/avr/avr.c:9004 config/bfin/bfin.c:4672 config/bfin/bfin.c:4733
++#: config/arm/arm.c:6456 config/arm/arm.c:6474 config/avr/avr.c:9024
++#: config/avr/avr.c:9040 config/bfin/bfin.c:4672 config/bfin/bfin.c:4733
+ #: config/bfin/bfin.c:4762 config/epiphany/epiphany.c:472
+-#: config/h8300/h8300.c:5453 config/i386/i386.c:6817 config/i386/i386.c:12002
+-#: config/i386/i386.c:44513 config/i386/i386.c:44563 config/i386/i386.c:44633
++#: config/h8300/h8300.c:5453 config/i386/i386.c:6810 config/i386/i386.c:12020
++#: config/i386/i386.c:44685 config/i386/i386.c:44735 config/i386/i386.c:44805
+ #: config/m68k/m68k.c:748 config/mcore/mcore.c:3052 config/mep/mep.c:3884
+ #: config/mep/mep.c:3898 config/mep/mep.c:3972 config/nvptx/nvptx.c:3794
+-#: config/rl78/rl78.c:756 config/rs6000/rs6000.c:32343 config/rx/rx.c:2695
++#: config/rl78/rl78.c:756 config/rs6000/rs6000.c:32410 config/rx/rx.c:2695
+ #: config/rx/rx.c:2721 config/s390/s390.c:1061 config/sh/sh.c:9780
+ #: config/sh/sh.c:9798 config/sh/sh.c:9827 config/sh/sh.c:9909
+ #: config/sh/sh.c:9932 config/spu/spu.c:3680 config/stormy16/stormy16.c:2211
+@@ -26708,27 +26782,27 @@
+ msgid "%qE attribute only applies to functions"
+ msgstr ""
+ 
+-#: config/arm/arm.c:12912
++#: config/arm/arm.c:12907
+ #, gcc-internal-format
+ msgid "%K%s %wd out of range %wd - %wd"
+ msgstr ""
+ 
+-#: config/arm/arm.c:12915
++#: config/arm/arm.c:12910
+ #, gcc-internal-format
+ msgid "%s %wd out of range %wd - %wd"
+ msgstr ""
+ 
+-#: config/arm/arm.c:23605
++#: config/arm/arm.c:23604
+ #, gcc-internal-format
+ msgid "unable to compute real location of stacked parameter"
+ msgstr ""
+ 
+-#: config/arm/arm.c:24216
++#: config/arm/arm.c:24215
+ #, gcc-internal-format
+ msgid "Unexpected thumb1 far jump"
+ msgstr ""
+ 
+-#: config/arm/arm.c:24483
++#: config/arm/arm.c:24482
+ #, gcc-internal-format
+ msgid "no low registers available for popping high registers"
+ msgstr ""
+@@ -26738,23 +26812,23 @@
+ msgid "interrupt Service Routines cannot be coded in Thumb mode"
+ msgstr ""
+ 
+-#: config/arm/arm.c:24956
++#: config/arm/arm.c:24960
+ #, gcc-internal-format
+ msgid "-fstack-check=specific for Thumb-1"
+ msgstr ""
+ 
+-#: config/arm/arm.c:30017 config/i386/i386.c:6041 config/s390/s390.c:14532
++#: config/arm/arm.c:30021 config/i386/i386.c:6034 config/s390/s390.c:14534
+ #, gcc-internal-format
+ msgid "attribute %<target%> argument not a string"
+ msgstr ""
+ 
+-#: config/arm/arm.c:30040
++#: config/arm/arm.c:30044
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid fpu for attribute(target(\"%s\"))"
+ msgstr ""
+ 
+-#: config/arm/arm.c:30046 config/i386/i386.c:6107 config/i386/i386.c:6154
+-#: config/s390/s390.c:14598 config/s390/s390.c:14648 config/s390/s390.c:14665
++#: config/arm/arm.c:30050 config/i386/i386.c:6100 config/i386/i386.c:6147
++#: config/s390/s390.c:14600 config/s390/s390.c:14650 config/s390/s390.c:14667
+ #, gcc-internal-format, gfc-internal-format
+ msgid "attribute(target(\"%s\")) is unknown"
+ msgstr ""
+@@ -26883,68 +26957,68 @@
+ msgid "accessing program memory with data memory address"
+ msgstr ""
+ 
+-#: config/avr/avr.c:2850
++#: config/avr/avr.c:2886
+ #, gcc-internal-format, gfc-internal-format
+ msgid "fixed register %s used to pass parameter to function"
+ msgstr ""
+ 
+-#: config/avr/avr.c:3121
++#: config/avr/avr.c:3157
+ #, gcc-internal-format
+ msgid "writing to address space %qs not supported"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9021 config/bfin/bfin.c:4794 config/i386/winnt.c:58
++#: config/avr/avr.c:9057 config/bfin/bfin.c:4794 config/i386/winnt.c:58
+ #: config/mep/mep.c:3788 config/mep/mep.c:3926
+ #, gcc-internal-format
+ msgid "%qE attribute only applies to variables"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9032 config/mep/mep.c:3936
++#: config/avr/avr.c:9068 config/mep/mep.c:3936
+ #, gcc-internal-format
+ msgid "%qE attribute allows only an integer constant argument"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9042
++#: config/avr/avr.c:9078
+ #, gcc-internal-format
+ msgid "%qE attribute address out of range"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9055
++#: config/avr/avr.c:9091
+ #, gcc-internal-format
+ msgid "both %s and %qE attribute provide address"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9065
++#: config/avr/avr.c:9101
+ #, gcc-internal-format
+ msgid "%qE attribute on non-volatile variable"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9269
++#: config/avr/avr.c:9305
+ #, gcc-internal-format
+ msgid "%qT uses address space %qs beyond flash of %d KiB"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9272
++#: config/avr/avr.c:9308
+ #, gcc-internal-format
+ msgid "%s %q+D uses address space %qs beyond flash of %d KiB"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9278
++#: config/avr/avr.c:9314
+ #, gcc-internal-format
+ msgid "pointer targeting address space %qs must be const in %qT"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9281
++#: config/avr/avr.c:9317
+ #, gcc-internal-format
+ msgid "pointer targeting address space %qs must be const in %s %q+D"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9319
++#: config/avr/avr.c:9355
+ #, gcc-internal-format
+ msgid "variable %q+D located in address space %qs beyond flash of %d KiB"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9324
++#: config/avr/avr.c:9360
+ #, gcc-internal-format
+ msgid ""
+ "variable %q+D located in address space %qs which is not supported for "
+@@ -26951,7 +27025,7 @@
+ "architecture %qs"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9340
++#: config/avr/avr.c:9376
+ #, gcc-internal-format
+ msgid ""
+ "variable %q+D must be const in order to be put into read-only section by "
+@@ -26958,47 +27032,47 @@
+ "means of %qs"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9380
++#: config/avr/avr.c:9416
+ #, gcc-internal-format
+ msgid "static IO declaration for %q+D needs an address"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9412
++#: config/avr/avr.c:9448
+ #, gcc-internal-format
+ msgid "IO definition for %q+D needs an address"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9519
++#: config/avr/avr.c:9555
+ #, gcc-internal-format
+ msgid "only uninitialized variables can be placed in the .noinit section"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9560
++#: config/avr/avr.c:9596
+ #, gcc-internal-format
+ msgid "uninitialized variable %q+D put into program memory area"
+ msgstr ""
+ 
+-#: config/avr/avr.c:9672
++#: config/avr/avr.c:9708
+ #, gcc-internal-format
+ msgid "architecture %qs supported for assembler only"
+ msgstr ""
+ 
+-#: config/avr/avr.c:12191
++#: config/avr/avr.c:12231
+ #, gcc-internal-format
+ msgid "conversion from address space %qs to address space %qs"
+ msgstr ""
+ 
+-#: config/avr/avr.c:13247
++#: config/avr/avr.c:13287
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s expects a compile time integer constant"
+ msgstr ""
+ 
+-#: config/avr/avr.c:13261
++#: config/avr/avr.c:13301
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s expects a compile time long integer constant as first argument"
+ msgstr ""
+ 
+-#: config/avr/avr.c:13289
++#: config/avr/avr.c:13329
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "rounding to %d bits has no effect for fixed-point value with %d fractional "
+@@ -27005,7 +27079,7 @@
+ "bits"
+ msgstr ""
+ 
+-#: config/avr/avr.c:13298
++#: config/avr/avr.c:13338
+ #, gcc-internal-format
+ msgid "rounding result will always be 0"
+ msgstr ""
+@@ -27408,23 +27482,23 @@
+ msgid "can%'t set position in PCH file: %m"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4088
++#: config/i386/i386.c:4089
+ #, gcc-internal-format, gfc-internal-format
+ msgid "wrong arg %s to option %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4095
++#: config/i386/i386.c:4096
+ #, gcc-internal-format, gfc-internal-format
+ msgid "size ranges of option %s should be increasing"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4106
++#: config/i386/i386.c:4107
+ #, gcc-internal-format, gfc-internal-format
+ msgid "wrong stringop strategy name %s specified for option %s"
+ msgstr ""
+ 
+ #. rep; movq isn't available in 32-bit code.
+-#: config/i386/i386.c:4116
++#: config/i386/i386.c:4117
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "stringop strategy name %s specified for option %s not supported for 32-bit "
+@@ -27431,22 +27505,22 @@
+ "code"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4131
++#: config/i386/i386.c:4132
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unknown alignment %s specified for option %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4142
++#: config/i386/i386.c:4143
+ #, gcc-internal-format, gfc-internal-format
+ msgid "the max value for the last size range should be -1 for option %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4150
++#: config/i386/i386.c:4151
+ #, gcc-internal-format, gfc-internal-format
+ msgid "too many size ranges specified in option %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4204
++#: config/i386/i386.c:4205
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unknown parameter to option -mtune-ctrl: %s"
+ msgstr ""
+@@ -27485,7 +27559,7 @@
+ msgid "code model %qs not supported in x32 mode"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4739 config/i386/i386.c:4748 config/i386/i386.c:5837
++#: config/i386/i386.c:4739 config/i386/i386.c:4748 config/i386/i386.c:5831
+ #, gcc-internal-format, gfc-internal-format
+ msgid "code model %s does not support PIC mode"
+ msgstr ""
+@@ -27500,284 +27574,284 @@
+ msgid "%i-bit mode not compiled in"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4794 config/i386/i386.c:5025
++#: config/i386/i386.c:4794 config/i386/i386.c:5022
+ #, gcc-internal-format
+ msgid "CPU you selected does not support x86-64 instruction set"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4986 config/i386/i386.c:4989
++#: config/i386/i386.c:4983 config/i386/i386.c:4986
+ #, gcc-internal-format
+ msgid "Intel MPX does not support x32"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4992
++#: config/i386/i386.c:4989
+ #, gcc-internal-format, gfc-internal-format
+ msgid "generic CPU can be used only for %stune=%s %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4995
++#: config/i386/i386.c:4992
+ #, gcc-internal-format, gfc-internal-format
+ msgid "intel CPU can be used only for %stune=%s %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:4998
++#: config/i386/i386.c:4995
+ #, gcc-internal-format, gfc-internal-format
+ msgid "bad value (%s) for %sarch=%s %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5041
++#: config/i386/i386.c:5038
+ #, gcc-internal-format, gfc-internal-format
+ msgid "bad value (%s) for %stune=%s %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5105
++#: config/i386/i386.c:5102
+ #, gcc-internal-format
+ msgid "-mregparm is ignored in 64-bit mode"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5107
++#: config/i386/i386.c:5104
+ #, gcc-internal-format
+ msgid "-mregparm is ignored for Intel MCU psABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5110
++#: config/i386/i386.c:5107
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-mregparm=%d is not between 0 and %d"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5141
++#: config/i386/i386.c:5138
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%srtd%s is ignored in 64bit mode"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5219
++#: config/i386/i386.c:5212
+ #, gcc-internal-format
+ msgid "-mpreferred-stack-boundary is not supported for this target"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5222
++#: config/i386/i386.c:5215
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-mpreferred-stack-boundary=%d is not between %d and %d"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5245
++#: config/i386/i386.c:5238
+ #, gcc-internal-format, gfc-internal-format
+ msgid "-mincoming-stack-boundary=%d is not between %d and 12"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5258
++#: config/i386/i386.c:5251
+ #, gcc-internal-format
+ msgid "-mnop-mcount is not compatible with this target"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5261
++#: config/i386/i386.c:5254
+ #, gcc-internal-format
+ msgid "-mnop-mcount is not implemented for -fPIC"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5266
++#: config/i386/i386.c:5259
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%ssseregparm%s used without SSE enabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5276
++#: config/i386/i386.c:5269
+ #, gcc-internal-format
+ msgid "SSE instruction set disabled, using 387 arithmetics"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5283
++#: config/i386/i386.c:5276
+ #, gcc-internal-format
+ msgid "387 instruction set disabled, using SSE arithmetics"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5331
++#: config/i386/i386.c:5324
+ #, gcc-internal-format, gfc-internal-format
+ msgid "stack probing requires %saccumulate-outgoing-args%s for correctness"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5342
++#: config/i386/i386.c:5335
+ #, gcc-internal-format, gfc-internal-format
+ msgid "fixed ebp register requires %saccumulate-outgoing-args%s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5455
++#: config/i386/i386.c:5448
+ #, gcc-internal-format
+ msgid "-mfentry isn%'t supported for 32-bit in combination with -fpic"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5462
++#: config/i386/i386.c:5455
+ #, gcc-internal-format
+ msgid "-mno-fentry isn%'t compatible with SEH"
+ msgstr ""
+ 
+-#: config/i386/i386.c:5528 config/rs6000/rs6000.c:4932
++#: config/i386/i386.c:5522 config/rs6000/rs6000.c:4940
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unknown option for -mrecip=%s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6135
++#: config/i386/i386.c:6128
+ #, gcc-internal-format, gfc-internal-format
+ msgid "option(\"%s\") was already specified"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6830 config/i386/i386.c:6881
++#: config/i386/i386.c:6823 config/i386/i386.c:6874
+ #, gcc-internal-format
+ msgid "fastcall and regparm attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6835
++#: config/i386/i386.c:6828
+ #, gcc-internal-format
+ msgid "regparam and thiscall attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6842 config/i386/i386.c:44533
++#: config/i386/i386.c:6835 config/i386/i386.c:44705
+ #, gcc-internal-format
+ msgid "%qE attribute requires an integer constant argument"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6848
++#: config/i386/i386.c:6841
+ #, gcc-internal-format
+ msgid "argument to %qE attribute larger than %d"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6873 config/i386/i386.c:6916
++#: config/i386/i386.c:6866 config/i386/i386.c:6909
+ #, gcc-internal-format
+ msgid "fastcall and cdecl attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6877
++#: config/i386/i386.c:6870
+ #, gcc-internal-format
+ msgid "fastcall and stdcall attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6885 config/i386/i386.c:6934
++#: config/i386/i386.c:6878 config/i386/i386.c:6927
+ #, gcc-internal-format
+ msgid "fastcall and thiscall attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6895 config/i386/i386.c:6912
++#: config/i386/i386.c:6888 config/i386/i386.c:6905
+ #, gcc-internal-format
+ msgid "stdcall and cdecl attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6899
++#: config/i386/i386.c:6892
+ #, gcc-internal-format
+ msgid "stdcall and fastcall attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6903 config/i386/i386.c:6930
++#: config/i386/i386.c:6896 config/i386/i386.c:6923
+ #, gcc-internal-format
+ msgid "stdcall and thiscall attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6920 config/i386/i386.c:6938
++#: config/i386/i386.c:6913 config/i386/i386.c:6931
+ #, gcc-internal-format
+ msgid "cdecl and thiscall attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:6926
++#: config/i386/i386.c:6919
+ #, gcc-internal-format
+ msgid "%qE attribute is used for non-class method"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7164
++#: config/i386/i386.c:7157
+ #, gcc-internal-format
+ msgid "calling %qD with attribute sseregparm without SSE/SSE2 enabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7167
++#: config/i386/i386.c:7160
+ #, gcc-internal-format
+ msgid "calling %qT with attribute sseregparm without SSE/SSE2 enabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7495
++#: config/i386/i386.c:7488
+ #, gcc-internal-format
+ msgid "X32 does not support ms_abi attribute"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7527
++#: config/i386/i386.c:7520
+ #, gcc-internal-format
+ msgid "ms_hook_prologue is not compatible with nested function"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7840
++#: config/i386/i386.c:7833
+ #, gcc-internal-format
+ msgid "AVX512F vector argument without AVX512F enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7846
++#: config/i386/i386.c:7839
+ #, gcc-internal-format
+ msgid "AVX512F vector return without AVX512F enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7860
++#: config/i386/i386.c:7853
+ #, gcc-internal-format
+ msgid "AVX vector argument without AVX enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7866
++#: config/i386/i386.c:7859
+ #, gcc-internal-format
+ msgid "AVX vector return without AVX enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7882
++#: config/i386/i386.c:7875
+ #, gcc-internal-format
+ msgid "SSE vector argument without SSE enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7888
++#: config/i386/i386.c:7881
+ #, gcc-internal-format
+ msgid "SSE vector return without SSE enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7902
++#: config/i386/i386.c:7895
+ #, gcc-internal-format
+ msgid "MMX vector argument without MMX enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:7908
++#: config/i386/i386.c:7901
+ #, gcc-internal-format
+ msgid "MMX vector return without MMX enabled changes the ABI"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8090
++#: config/i386/i386.c:8083
+ #, gcc-internal-format
+ msgid ""
+ "the ABI of passing struct with a flexible array member has changed in GCC 4.4"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8207
++#: config/i386/i386.c:8200
+ #, gcc-internal-format
+ msgid "the ABI of passing union with long double has changed in GCC 4.4"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8325
++#: config/i386/i386.c:8318
+ #, gcc-internal-format
+ msgid ""
+ "the ABI of passing structure with complex float member has changed in GCC 4.4"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8488
++#: config/i386/i386.c:8481
+ #, gcc-internal-format
+ msgid "SSE register return with SSE disabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8494
++#: config/i386/i386.c:8487
+ #, gcc-internal-format
+ msgid "SSE register argument with SSE disabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8510
++#: config/i386/i386.c:8503
+ #, gcc-internal-format
+ msgid "x87 register return with x87 disabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8805 config/i386/i386.c:9070
++#: config/i386/i386.c:8798 config/i386/i386.c:9063
+ #, gcc-internal-format
+ msgid "calling %qD with SSE calling convention without SSE/SSE2 enabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:8807 config/i386/i386.c:9072 config/i386/i386.c:9565
++#: config/i386/i386.c:8800 config/i386/i386.c:9065 config/i386/i386.c:9558
+ #, gcc-internal-format
+ msgid ""
+ "this is a GCC bug that can be worked around by adding attribute used to "
+@@ -27784,28 +27858,28 @@
+ "function called"
+ msgstr ""
+ 
+-#: config/i386/i386.c:9465
++#: config/i386/i386.c:9458
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The ABI for passing parameters with %d-byte alignment has changed in GCC 4.6"
+ msgstr ""
+ 
+-#: config/i386/i386.c:9563
++#: config/i386/i386.c:9556
+ #, gcc-internal-format
+ msgid "calling %qD with SSE caling convention without SSE/SSE2 enabled"
+ msgstr ""
+ 
+-#: config/i386/i386.c:12691
++#: config/i386/i386.c:12709
+ #, gcc-internal-format
+ msgid "ms_hook_prologue attribute isn%'t compatible with -mfentry for 32-bit"
+ msgstr ""
+ 
+-#: config/i386/i386.c:13757
++#: config/i386/i386.c:13807
+ #, gcc-internal-format
+ msgid "-fsplit-stack does not support fastcall with nested function"
+ msgstr ""
+ 
+-#: config/i386/i386.c:13777
++#: config/i386/i386.c:13827
+ #, gcc-internal-format
+ msgid ""
+ "-fsplit-stack does not support 2 register parameters for a nested function"
+@@ -27813,268 +27887,268 @@
+ 
+ #. FIXME: We could make this work by pushing a register
+ #. around the addition and comparison.
+-#: config/i386/i386.c:13788
++#: config/i386/i386.c:13838
+ #, gcc-internal-format
+ msgid "-fsplit-stack does not support 3 register parameters"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16599
++#: config/i386/i386.c:16651
+ #, gcc-internal-format
+ msgid "extended registers have no high halves"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16614
++#: config/i386/i386.c:16666
+ #, gcc-internal-format
+ msgid "unsupported operand size for extended register"
+ msgstr ""
+ 
+-#: config/i386/i386.c:16806
++#: config/i386/i386.c:16858
+ #, gcc-internal-format
+ msgid "non-integer operand used with operand code 'z'"
+ msgstr ""
+ 
+-#: config/i386/i386.c:36446
++#: config/i386/i386.c:36510
+ #, gcc-internal-format
+ msgid "No dispatcher found for the versioning attributes"
+ msgstr ""
+ 
+-#: config/i386/i386.c:36496
++#: config/i386/i386.c:36560
+ #, gcc-internal-format, gfc-internal-format
+ msgid "No dispatcher found for %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:36506
++#: config/i386/i386.c:36570
+ #, gcc-internal-format, gfc-internal-format
+ msgid "No dispatcher found for the versioning attributes : %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:36754
++#: config/i386/i386.c:36818
+ #, gcc-internal-format
+ msgid ""
+ "Function versions cannot be marked as gnu_inline, bodies have to be generated"
+ msgstr ""
+ 
+-#: config/i386/i386.c:36759 config/i386/i386.c:37187
++#: config/i386/i386.c:36823 config/i386/i386.c:37251
+ #, gcc-internal-format
+ msgid "Virtual function multiversioning not supported"
+ msgstr ""
+ 
+-#: config/i386/i386.c:36822
++#: config/i386/i386.c:36886
+ #, gcc-internal-format
+ msgid "missing %<target%> attribute for multi-versioned %D"
+ msgstr ""
+ 
+-#: config/i386/i386.c:36825
++#: config/i386/i386.c:36889
+ #, gcc-internal-format
+ msgid "previous declaration of %D"
+ msgstr ""
+ 
+-#: config/i386/i386.c:37044
++#: config/i386/i386.c:37108
+ #, gcc-internal-format
+ msgid "multiversioning needs ifunc which is not supported on this target"
+ msgstr ""
+ 
+-#: config/i386/i386.c:37430
++#: config/i386/i386.c:37494
+ #, gcc-internal-format
+ msgid "Parameter to builtin must be a string constant or literal"
+ msgstr ""
+ 
+-#: config/i386/i386.c:37455 config/i386/i386.c:37505
++#: config/i386/i386.c:37519 config/i386/i386.c:37569
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Parameter to builtin not valid: %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:37916 config/i386/i386.c:39271
++#: config/i386/i386.c:38086 config/i386/i386.c:39443
+ #, gcc-internal-format
+ msgid "the last argument must be a 2-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:38311
++#: config/i386/i386.c:38481
+ #, gcc-internal-format
+ msgid "the fifth argument must be an 8-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:38406
++#: config/i386/i386.c:38576
+ #, gcc-internal-format
+ msgid "the third argument must be an 8-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39202
++#: config/i386/i386.c:39374
+ #, gcc-internal-format
+ msgid "the last argument must be an 1-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39217
++#: config/i386/i386.c:39389
+ #, gcc-internal-format
+ msgid "the last argument must be a 3-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39250
++#: config/i386/i386.c:39422
+ #, gcc-internal-format
+ msgid "the last argument must be a 4-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39290
++#: config/i386/i386.c:39462
+ #, gcc-internal-format
+ msgid "the last argument must be a 1-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39303
++#: config/i386/i386.c:39475
+ #, gcc-internal-format
+ msgid "the last argument must be a 5-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39313
++#: config/i386/i386.c:39485
+ #, gcc-internal-format
+ msgid "the next to last argument must be an 8-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39317 config/i386/i386.c:40083
++#: config/i386/i386.c:39489 config/i386/i386.c:40255
+ #, gcc-internal-format
+ msgid "the last argument must be an 8-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39485
++#: config/i386/i386.c:39657
+ #, gcc-internal-format
+ msgid "the third argument must be comparison constant"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39490
++#: config/i386/i386.c:39662
+ #, gcc-internal-format
+ msgid "incorrect comparison mode"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39496 config/i386/i386.c:39697
++#: config/i386/i386.c:39668 config/i386/i386.c:39869
+ #, gcc-internal-format
+ msgid "incorrect rounding operand"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39679
++#: config/i386/i386.c:39851
+ #, gcc-internal-format
+ msgid "the immediate argument must be a 4-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39685
++#: config/i386/i386.c:39857
+ #, gcc-internal-format
+ msgid "the immediate argument must be a 5-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:39688
++#: config/i386/i386.c:39860
+ #, gcc-internal-format
+ msgid "the immediate argument must be an 8-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:40081
++#: config/i386/i386.c:40253
+ #, gcc-internal-format
+ msgid "the last argument must be a 32-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:40163 config/rs6000/rs6000.c:14475
++#: config/i386/i386.c:40335 config/rs6000/rs6000.c:14505
+ #, gcc-internal-format
+ msgid "selector must be an integer constant in the range 0..%wi"
+ msgstr ""
+ 
+-#: config/i386/i386.c:40357
++#: config/i386/i386.c:40529
+ #, gcc-internal-format
+ msgid "%qE needs unknown isa option"
+ msgstr ""
+ 
+-#: config/i386/i386.c:40361
++#: config/i386/i386.c:40533
+ #, gcc-internal-format
+ msgid "%qE needs isa option %s"
+ msgstr ""
+ 
+-#: config/i386/i386.c:41123
++#: config/i386/i386.c:41295
+ #, gcc-internal-format
+ msgid "last argument must be an immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:41732 config/i386/i386.c:41914
++#: config/i386/i386.c:41904 config/i386/i386.c:42086
+ #, gcc-internal-format
+ msgid "the last argument must be scale 1, 2, 4, 8"
+ msgstr ""
+ 
+-#: config/i386/i386.c:41967
++#: config/i386/i386.c:42139
+ #, gcc-internal-format
+ msgid "the forth argument must be scale 1, 2, 4, 8"
+ msgstr ""
+ 
+-#: config/i386/i386.c:41973
++#: config/i386/i386.c:42145
+ #, gcc-internal-format
+ msgid "incorrect hint operand"
+ msgstr ""
+ 
+-#: config/i386/i386.c:41992
++#: config/i386/i386.c:42164
+ #, gcc-internal-format
+ msgid "the xabort's argument must be an 8-bit immediate"
+ msgstr ""
+ 
+-#: config/i386/i386.c:44520
++#: config/i386/i386.c:44692
+ #, gcc-internal-format
+ msgid "%qE attribute only available for 32-bit"
+ msgstr ""
+ 
+-#: config/i386/i386.c:44541
++#: config/i386/i386.c:44713
+ #, gcc-internal-format
+ msgid "argument to %qE attribute is neither zero, nor one"
+ msgstr ""
+ 
+-#: config/i386/i386.c:44574 config/i386/i386.c:44583
++#: config/i386/i386.c:44746 config/i386/i386.c:44755
+ #, gcc-internal-format
+ msgid "ms_abi and sysv_abi attributes are not compatible"
+ msgstr ""
+ 
+-#: config/i386/i386.c:44619 config/rs6000/rs6000.c:32426
++#: config/i386/i386.c:44791 config/rs6000/rs6000.c:32493
+ #, gcc-internal-format
+ msgid "%qE incompatible attribute ignored"
+ msgstr ""
+ 
+-#: config/i386/i386.c:47556
++#: config/i386/i386.c:47728
+ #, gcc-internal-format
+ msgid "alternatives not allowed in asm flag output"
+ msgstr ""
+ 
+-#: config/i386/i386.c:47620
++#: config/i386/i386.c:47792
+ #, gcc-internal-format
+ msgid "unknown asm flag output %qs"
+ msgstr ""
+ 
+-#: config/i386/i386.c:47649
++#: config/i386/i386.c:47821
+ #, gcc-internal-format
+ msgid "invalid type for asm flag output"
+ msgstr ""
+ 
+-#: config/i386/i386.c:53809
++#: config/i386/i386.c:53945
+ #, gcc-internal-format
+ msgid "Unknown architecture specific memory model"
+ msgstr ""
+ 
+-#: config/i386/i386.c:53816
++#: config/i386/i386.c:53952
+ #, gcc-internal-format
+ msgid "HLE_ACQUIRE not used with ACQUIRE or stronger memory model"
+ msgstr ""
+ 
+-#: config/i386/i386.c:53822
++#: config/i386/i386.c:53958
+ #, gcc-internal-format
+ msgid "HLE_RELEASE not used with RELEASE or stronger memory model"
+ msgstr ""
+ 
+-#: config/i386/i386.c:53846 config/i386/i386.c:53967
++#: config/i386/i386.c:53982 config/i386/i386.c:54103
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unsupported simdlen %d"
+ msgstr ""
+ 
+-#: config/i386/i386.c:53865
++#: config/i386/i386.c:54001
+ #, gcc-internal-format
+ msgid "unsupported return type %qT for simd\n"
+ msgstr ""
+ 
+-#: config/i386/i386.c:53887
++#: config/i386/i386.c:54023
+ #, gcc-internal-format
+ msgid "unsupported argument type %qT for simd\n"
+ msgstr ""
+ 
+-#: config/i386/i386.c:54214
++#: config/i386/i386.c:54350
+ #, gcc-internal-format
+ msgid ""
+ "Pointer Checker requires MPX support on this target. Use -mmpx options to "
+@@ -28308,7 +28382,7 @@
+ msgid "interrupt_thread is available only on fido"
+ msgstr ""
+ 
+-#: config/m68k/m68k.c:1096 config/rs6000/rs6000.c:25350
++#: config/m68k/m68k.c:1096 config/rs6000/rs6000.c:25380
+ #, gcc-internal-format
+ msgid "stack limit expression is not supported"
+ msgstr ""
+@@ -28547,7 +28621,7 @@
+ msgid "argument %d of %qE must be a multiple of %d"
+ msgstr ""
+ 
+-#: config/mep/mep.c:6144 c/c-typeck.c:6630
++#: config/mep/mep.c:6144 c/c-typeck.c:6640
+ #, gcc-internal-format
+ msgid "incompatible type for argument %d of %qE"
+ msgstr ""
+@@ -29490,27 +29564,27 @@
+ msgid "invalid parameter combination for AltiVec intrinsic"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3512
++#: config/rs6000/rs6000.c:3520
+ #, gcc-internal-format
+ msgid "-mrecip requires -ffinite-math or -ffast-math"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3514
++#: config/rs6000/rs6000.c:3522
+ #, gcc-internal-format
+ msgid "-mrecip requires -fno-trapping-math or -ffast-math"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3516
++#: config/rs6000/rs6000.c:3524
+ #, gcc-internal-format
+ msgid "-mrecip requires -freciprocal-math or -ffast-math"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3616
++#: config/rs6000/rs6000.c:3624
+ #, gcc-internal-format
+ msgid "-m64 requires PowerPC64 architecture, enabling"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3734
++#: config/rs6000/rs6000.c:3742
+ #, gcc-internal-format
+ msgid ""
+ "-malign-power is not supported for 64-bit Darwin; it is incompatible with "
+@@ -29517,177 +29591,177 @@
+ "the installed C and C++ libraries"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3881
++#: config/rs6000/rs6000.c:3889
+ #, gcc-internal-format
+ msgid "not configured for SPE ABI"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3886
++#: config/rs6000/rs6000.c:3894
+ #, gcc-internal-format
+ msgid "not configured for SPE instruction set"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3892
++#: config/rs6000/rs6000.c:3900
+ #, gcc-internal-format
+ msgid "target attribute or pragma changes SPE ABI"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3899
++#: config/rs6000/rs6000.c:3907
+ #, gcc-internal-format
+ msgid "AltiVec not supported in this target"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3901 config/rs6000/rs6000.c:3906
++#: config/rs6000/rs6000.c:3909 config/rs6000/rs6000.c:3914
+ #, gcc-internal-format
+ msgid "SPE not supported in this target"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3934
++#: config/rs6000/rs6000.c:3942
+ #, gcc-internal-format
+ msgid "-mmultiple is not supported on little endian systems"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:3941
++#: config/rs6000/rs6000.c:3949
+ #, gcc-internal-format
+ msgid "-mstring is not supported on little endian systems"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4037
++#: config/rs6000/rs6000.c:4045
+ #, gcc-internal-format
+ msgid "-mcrypto requires -maltivec"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4044
++#: config/rs6000/rs6000.c:4052
+ #, gcc-internal-format
+ msgid "-mdirect-move requires -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4051
++#: config/rs6000/rs6000.c:4059
+ #, gcc-internal-format
+ msgid "-mpower8-vector requires -maltivec"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4058
++#: config/rs6000/rs6000.c:4066
+ #, gcc-internal-format
+ msgid "-mpower8-vector requires -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4065
++#: config/rs6000/rs6000.c:4073
+ #, gcc-internal-format
+ msgid "-mvsx-timode requires -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4072
++#: config/rs6000/rs6000.c:4080
+ #, gcc-internal-format
+ msgid "-mhard-dfp requires -mhard-float"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4113
++#: config/rs6000/rs6000.c:4121
+ #, gcc-internal-format
+ msgid "-mupper-regs-df requires -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4120
++#: config/rs6000/rs6000.c:4128
+ #, gcc-internal-format
+ msgid "-mupper-regs-sf requires -mpower8-vector"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4169
++#: config/rs6000/rs6000.c:4177
+ #, gcc-internal-format
+ msgid "-mpower8-fusion-sign requires -mpower8-fusion"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4172
++#: config/rs6000/rs6000.c:4180
+ #, gcc-internal-format
+ msgid "-mtoc-fusion requires -mpower8-fusion"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4185
++#: config/rs6000/rs6000.c:4193
+ #, gcc-internal-format
+ msgid "-mpower9-fusion requires -mpower8-fusion"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4233
++#: config/rs6000/rs6000.c:4241
+ #, gcc-internal-format
+ msgid "-mpower9-vector requires -mpower8-vector"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4260
++#: config/rs6000/rs6000.c:4268
+ #, gcc-internal-format
+ msgid "-mpower9-dform requires -mpower9-vector"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4268
++#: config/rs6000/rs6000.c:4276
+ #, gcc-internal-format
+ msgid "-mpower9-dform requires -mupper-regs-df"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4275
++#: config/rs6000/rs6000.c:4283
+ #, gcc-internal-format
+ msgid "-mpower9-dform requires -mupper-regs-sf"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4291
++#: config/rs6000/rs6000.c:4299
+ #, gcc-internal-format
+ msgid "-mvsx-timode might need -mlra"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4316
++#: config/rs6000/rs6000.c:4324
+ #, gcc-internal-format
+ msgid "-mallow-movmisalign requires -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4331
++#: config/rs6000/rs6000.c:4339
+ #, gcc-internal-format
+ msgid "-mefficient-unaligned-vsx requires -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4339
++#: config/rs6000/rs6000.c:4347
+ #, gcc-internal-format
+ msgid "-mefficient-unaligned-vsx requires -mallow-movmisalign"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4349
++#: config/rs6000/rs6000.c:4357
+ #, gcc-internal-format
+ msgid "-mfloat128 requires VSX support"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4371
++#: config/rs6000/rs6000.c:4379
+ #, gcc-internal-format
+ msgid "-mfloat128-hardware requires full ISA 3.0 support"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4434
++#: config/rs6000/rs6000.c:4442
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unknown vectorization library ABI type (%s) for -mveclibabi= switch"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4446
++#: config/rs6000/rs6000.c:4454
+ #, gcc-internal-format
+ msgid "target attribute or pragma changes long double size"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4469 config/rs6000/rs6000.c:4484
++#: config/rs6000/rs6000.c:4477 config/rs6000/rs6000.c:4492
+ #, gcc-internal-format
+ msgid "target attribute or pragma changes AltiVec ABI"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4497
++#: config/rs6000/rs6000.c:4505
+ #, gcc-internal-format
+ msgid "target attribute or pragma changes darwin64 ABI"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4563
++#: config/rs6000/rs6000.c:4571
+ #, gcc-internal-format
+ msgid "target attribute or pragma changes single precision floating point"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:4566
++#: config/rs6000/rs6000.c:4574
+ #, gcc-internal-format
+ msgid "target attribute or pragma changes double precision floating point"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:7010
++#: config/rs6000/rs6000.c:7036
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "the layout of aggregates containing vectors with %d-byte alignment has "
+@@ -29694,7 +29768,7 @@
+ "changed in GCC 5"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:10258
++#: config/rs6000/rs6000.c:10288
+ #, gcc-internal-format
+ msgid ""
+ "GCC vector returned by reference: non-standard ABI extension with no "
+@@ -29701,7 +29775,7 @@
+ "compatibility guarantee"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:10411
++#: config/rs6000/rs6000.c:10441
+ #, gcc-internal-format
+ msgid ""
+ "cannot return value in vector register because altivec instructions are "
+@@ -29708,13 +29782,13 @@
+ "disabled, use -maltivec to enable them"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:10611
++#: config/rs6000/rs6000.c:10641
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "the ABI of passing aggregates with %d-byte alignment has changed in GCC 5"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:10873
++#: config/rs6000/rs6000.c:10903
+ #, gcc-internal-format
+ msgid ""
+ "cannot pass argument in vector register because altivec instructions are "
+@@ -29721,12 +29795,12 @@
+ "disabled, use -maltivec to enable them"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:11725
++#: config/rs6000/rs6000.c:11755
+ #, gcc-internal-format
+ msgid "the ABI of passing homogeneous float aggregates has changed in GCC 5"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:11900
++#: config/rs6000/rs6000.c:11930
+ #, gcc-internal-format
+ msgid ""
+ "GCC vector passed by reference: non-standard ABI extension with no "
+@@ -29733,235 +29807,235 @@
+ "compatibility guarantee"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:12684
++#: config/rs6000/rs6000.c:12714
+ #, gcc-internal-format, gfc-internal-format
+ msgid "internal error: builtin function %s already processed"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13182
++#: config/rs6000/rs6000.c:13212
+ #, gcc-internal-format
+ msgid "argument 1 must be an 8-bit field value"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13229
++#: config/rs6000/rs6000.c:13259
+ #, gcc-internal-format
+ msgid "argument 1 must be a 5-bit signed literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13332 config/rs6000/rs6000.c:15019
++#: config/rs6000/rs6000.c:13362 config/rs6000/rs6000.c:15049
+ #, gcc-internal-format
+ msgid "argument 2 must be a 5-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13350
++#: config/rs6000/rs6000.c:13380
+ #, gcc-internal-format
+ msgid "argument 1 must be a 6-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13389
++#: config/rs6000/rs6000.c:13419
+ #, gcc-internal-format
+ msgid "argument 1 of __builtin_altivec_predicate must be a constant"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13441
++#: config/rs6000/rs6000.c:13471
+ #, gcc-internal-format
+ msgid "argument 1 of __builtin_altivec_predicate is out of range"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13815
++#: config/rs6000/rs6000.c:13845
+ #, gcc-internal-format, gfc-internal-format
+ msgid "builtin %s is only valid in 64-bit mode"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13864
++#: config/rs6000/rs6000.c:13894
+ #, gcc-internal-format, gfc-internal-format
+ msgid "argument %d must be an unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:13866
++#: config/rs6000/rs6000.c:13896
+ #, gcc-internal-format, gfc-internal-format
+ msgid "argument %d is an unsigned literal that is out of range"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14004
++#: config/rs6000/rs6000.c:14034
+ #, gcc-internal-format, gfc-internal-format
+ msgid "builtin %s only accepts a string argument"
+ msgstr ""
+ 
+ #. Invalid CPU argument.
+-#: config/rs6000/rs6000.c:14023
++#: config/rs6000/rs6000.c:14053
+ #, gcc-internal-format, gfc-internal-format
+ msgid "cpu %s is an invalid argument to builtin %s"
+ msgstr ""
+ 
+ #. Invalid HWCAP argument.
+-#: config/rs6000/rs6000.c:14051
++#: config/rs6000/rs6000.c:14081
+ #, gcc-internal-format, gfc-internal-format
+ msgid "hwcap %s is an invalid argument to builtin %s"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14124
++#: config/rs6000/rs6000.c:14154
+ #, gcc-internal-format
+ msgid "argument 3 must be a 4-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14142
++#: config/rs6000/rs6000.c:14172
+ #, gcc-internal-format
+ msgid "argument 3 must be a 2-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14162
++#: config/rs6000/rs6000.c:14192
+ #, gcc-internal-format
+ msgid "argument 3 must be a 1-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14174
++#: config/rs6000/rs6000.c:14204
+ #, gcc-internal-format
+ msgid "argument 1 must be 0 or 2"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14186
++#: config/rs6000/rs6000.c:14216
+ #, gcc-internal-format
+ msgid "argument 1 must be a 1-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14200
++#: config/rs6000/rs6000.c:14230
+ #, gcc-internal-format
+ msgid "argument 2 must be a 6-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14212
++#: config/rs6000/rs6000.c:14242
+ #, gcc-internal-format
+ msgid "argument 2 must be 0 or 1"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14219
++#: config/rs6000/rs6000.c:14249
+ #, gcc-internal-format
+ msgid "argument 3 must be in the range 0..15"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14408
++#: config/rs6000/rs6000.c:14438
+ #, gcc-internal-format
+ msgid "argument to %qs must be a 2-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14561
++#: config/rs6000/rs6000.c:14591
+ #, gcc-internal-format
+ msgid "unresolved overload for Altivec builtin %qF"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:14732
++#: config/rs6000/rs6000.c:14762
+ #, gcc-internal-format
+ msgid "argument to dss must be a 2-bit unsigned literal"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15139
++#: config/rs6000/rs6000.c:15169
+ #, gcc-internal-format
+ msgid "argument 1 of __builtin_paired_predicate must be a constant"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15186
++#: config/rs6000/rs6000.c:15216
+ #, gcc-internal-format
+ msgid "argument 1 of __builtin_paired_predicate is out of range"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15211
++#: config/rs6000/rs6000.c:15241
+ #, gcc-internal-format
+ msgid "argument 1 of __builtin_spe_predicate must be a constant"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15283
++#: config/rs6000/rs6000.c:15313
+ #, gcc-internal-format
+ msgid "argument 1 of __builtin_spe_predicate is out of range"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15365
++#: config/rs6000/rs6000.c:15395
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s is only valid for the cell processor"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15367
++#: config/rs6000/rs6000.c:15397
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mvsx option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15369
++#: config/rs6000/rs6000.c:15399
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mhtm option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15371
++#: config/rs6000/rs6000.c:15401
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -maltivec option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15373
++#: config/rs6000/rs6000.c:15403
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mpaired option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15375
++#: config/rs6000/rs6000.c:15405
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mspe option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15378
++#: config/rs6000/rs6000.c:15408
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mhard-dfp and -mpower8-vector options"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15381
++#: config/rs6000/rs6000.c:15411
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mhard-dfp option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15383
++#: config/rs6000/rs6000.c:15413
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mpower8-vector option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15385
++#: config/rs6000/rs6000.c:15415
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mpower9-vector option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15388
++#: config/rs6000/rs6000.c:15418
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mpower9-misc and -m64 options"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15391
++#: config/rs6000/rs6000.c:15421
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mpower9-misc option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15394
++#: config/rs6000/rs6000.c:15424
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Builtin function %s requires the -mhard-float and -mlong-double-128 options"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15397
++#: config/rs6000/rs6000.c:15427
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mhard-float option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15399
++#: config/rs6000/rs6000.c:15429
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s requires the -mfloat128 option"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:15401
++#: config/rs6000/rs6000.c:15431
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s is not supported with the current options"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:17064
++#: config/rs6000/rs6000.c:17094
+ #, gcc-internal-format, gfc-internal-format
+ msgid "internal error: builtin function %s had an unexpected return type %s"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:17081
++#: config/rs6000/rs6000.c:17111
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "internal error: builtin function %s, argument %d had unexpected argument "
+@@ -29968,27 +30042,27 @@
+ "type %s"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:25320
++#: config/rs6000/rs6000.c:25350
+ #, gcc-internal-format
+ msgid "stack frame too large"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:28750
++#: config/rs6000/rs6000.c:28814
+ #, gcc-internal-format
+ msgid "-fsplit-stack uses register r29"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:28758
++#: config/rs6000/rs6000.c:28822
+ #, gcc-internal-format
+ msgid "Stack frame larger than 2G is not supported for -fsplit-stack"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:29761
++#: config/rs6000/rs6000.c:29828
+ #, gcc-internal-format
+ msgid "no profiling of 64-bit code for this ABI"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32113
++#: config/rs6000/rs6000.c:32180
+ #, gcc-internal-format
+ msgid ""
+ "You cannot take the address of a nested function if you use the -mno-"
+@@ -29995,68 +30069,68 @@
+ "pointers-to-nested-functions option."
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32195
++#: config/rs6000/rs6000.c:32262
+ #, gcc-internal-format
+ msgid "use of %<long double%> in AltiVec types is invalid"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32197
++#: config/rs6000/rs6000.c:32264
+ #, gcc-internal-format
+ msgid "use of boolean types in AltiVec types is invalid"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32199
++#: config/rs6000/rs6000.c:32266
+ #, gcc-internal-format
+ msgid "use of %<complex%> in AltiVec types is invalid"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32201
++#: config/rs6000/rs6000.c:32268
+ #, gcc-internal-format
+ msgid "use of decimal floating point types in AltiVec types is invalid"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32207
++#: config/rs6000/rs6000.c:32274
+ #, gcc-internal-format
+ msgid ""
+ "use of %<long%> in AltiVec types is invalid for 64-bit code without -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32210
++#: config/rs6000/rs6000.c:32277
+ #, gcc-internal-format
+ msgid "use of %<long%> in AltiVec types is deprecated; use %<int%>"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32215
++#: config/rs6000/rs6000.c:32282
+ #, gcc-internal-format
+ msgid "use of %<long long%> in AltiVec types is invalid without -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:32218
++#: config/rs6000/rs6000.c:32285
+ #, gcc-internal-format
+ msgid "use of %<double%> in AltiVec types is invalid without -mvsx"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:35741
++#: config/rs6000/rs6000.c:35808
+ #, gcc-internal-format, gfc-internal-format
+ msgid "emitting microcode insn %s\t[%s] #%d"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:35745
++#: config/rs6000/rs6000.c:35812
+ #, gcc-internal-format, gfc-internal-format
+ msgid "emitting conditional microcode insn %s\t[%s] #%d"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:36050
++#: config/rs6000/rs6000.c:36117
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid cpu \"%s\" for %s\"%s\"%s"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:36053
++#: config/rs6000/rs6000.c:36120
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s\"%s\"%s is not allowed"
+ msgstr ""
+ 
+-#: config/rs6000/rs6000.c:36055
++#: config/rs6000/rs6000.c:36122
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s\"%s\"%s is invalid"
+ msgstr ""
+@@ -30419,12 +30493,12 @@
+ "integer constants or too large (max. %d)"
+ msgstr ""
+ 
+-#: config/s390/s390.c:9662
++#: config/s390/s390.c:9664
+ #, gcc-internal-format
+ msgid "total size of local variables exceeds architecture limit"
+ msgstr ""
+ 
+-#: config/s390/s390.c:10768
++#: config/s390/s390.c:10770
+ #, gcc-internal-format
+ msgid ""
+ "frame size of function %qs is %wd bytes exceeding user provided stack limit "
+@@ -30431,7 +30505,7 @@
+ "of %d bytes.  An unconditional trap is added."
+ msgstr ""
+ 
+-#: config/s390/s390.c:10784
++#: config/s390/s390.c:10786
+ #, gcc-internal-format
+ msgid ""
+ "frame size of function %qs is %wd bytes which is more than half the stack "
+@@ -30439,22 +30513,22 @@
+ "function."
+ msgstr ""
+ 
+-#: config/s390/s390.c:10812
++#: config/s390/s390.c:10814
+ #, gcc-internal-format
+ msgid "frame size of %qs is %wd bytes"
+ msgstr ""
+ 
+-#: config/s390/s390.c:10816
++#: config/s390/s390.c:10818
+ #, gcc-internal-format
+ msgid "%qs uses dynamic stack allocation"
+ msgstr ""
+ 
+-#: config/s390/s390.c:11194
++#: config/s390/s390.c:11196
+ #, gcc-internal-format
+ msgid "CPUs older than z900 are not supported for -fsplit-stack"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14185
++#: config/s390/s390.c:14187
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "%sarch=%s%s is deprecated and will be removed in future releases; use at "
+@@ -30461,7 +30535,7 @@
+ "least %sarch=z900%s"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14197
++#: config/s390/s390.c:14199
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "%stune=%s%s is deprecated and will be removed in future releases; use at "
+@@ -30468,76 +30542,76 @@
+ "least %stune=z900%s"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14209
++#: config/s390/s390.c:14211
+ #, gcc-internal-format, gfc-internal-format
+ msgid "z/Architecture mode not supported on %s"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14212
++#: config/s390/s390.c:14214
+ #, gcc-internal-format
+ msgid "64-bit ABI not supported in ESA/390 mode"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14229
++#: config/s390/s390.c:14231
+ #, gcc-internal-format, gfc-internal-format
+ msgid "hardware vector support not available on %s"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14232
++#: config/s390/s390.c:14234
+ #, gcc-internal-format
+ msgid "hardware vector support not available with -msoft-float"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14260
++#: config/s390/s390.c:14262
+ #, gcc-internal-format, gfc-internal-format
+ msgid "hardware decimal floating point instructions not available on %s"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14264
++#: config/s390/s390.c:14266
+ #, gcc-internal-format
+ msgid ""
+ "hardware decimal floating point instructions not available in ESA/390 mode"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14276
++#: config/s390/s390.c:14278
+ #, gcc-internal-format
+ msgid "-mhard-dfp can%'t be used in conjunction with -msoft-float"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14284
++#: config/s390/s390.c:14286
+ #, gcc-internal-format
+ msgid ""
+ "-mbackchain -mpacked-stack -mhard-float are not supported in combination"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14290
++#: config/s390/s390.c:14292
+ #, gcc-internal-format
+ msgid "stack size must be greater than the stack guard value"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14292
++#: config/s390/s390.c:14294
+ #, gcc-internal-format
+ msgid "stack size must not be greater than 64k"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14295
++#: config/s390/s390.c:14297
+ #, gcc-internal-format
+ msgid "-mstack-guard implies use of -mstack-size"
+ msgstr ""
+ 
+ #. argument is not a plain number
+-#: config/s390/s390.c:14389
++#: config/s390/s390.c:14391
+ #, gcc-internal-format
+ msgid "arguments to %qs should be non-negative integers"
+ msgstr ""
+ 
+-#: config/s390/s390.c:14396
++#: config/s390/s390.c:14398
+ #, gcc-internal-format
+ msgid "argument to %qs is too large (max. %d)"
+ msgstr ""
+ 
+ #. Value is not allowed for the target attribute.
+-#: config/s390/s390.c:14604
++#: config/s390/s390.c:14606
+ #, gcc-internal-format
+ msgid "Value %qs is not supported by attribute %<target%>"
+ msgstr ""
+@@ -30983,38 +31057,38 @@
+ msgid "containing loop"
+ msgstr ""
+ 
+-#: ada/gcc-interface/utils.c:3763
++#: ada/gcc-interface/utils.c:3781
+ #, gcc-internal-format
+ msgid "invalid element type for attribute %qs"
+ msgstr ""
+ 
+-#: ada/gcc-interface/utils.c:3787
++#: ada/gcc-interface/utils.c:3805
+ #, gcc-internal-format
+ msgid "number of components of vector not a power of two"
+ msgstr ""
+ 
+-#: ada/gcc-interface/utils.c:5801 ada/gcc-interface/utils.c:5975
+-#: ada/gcc-interface/utils.c:6082
++#: ada/gcc-interface/utils.c:5827 ada/gcc-interface/utils.c:6001
++#: ada/gcc-interface/utils.c:6108
+ #, gcc-internal-format
+ msgid "%qs attribute ignored"
+ msgstr ""
+ 
+-#: ada/gcc-interface/utils.c:5918
++#: ada/gcc-interface/utils.c:5944
+ #, gcc-internal-format
+ msgid "%qs attribute requires prototypes with named arguments"
+ msgstr ""
+ 
+-#: ada/gcc-interface/utils.c:5927
++#: ada/gcc-interface/utils.c:5953
+ #, gcc-internal-format
+ msgid "%qs attribute only applies to variadic functions"
+ msgstr ""
+ 
+-#: ada/gcc-interface/utils.c:6042
++#: ada/gcc-interface/utils.c:6068
+ #, gcc-internal-format
+ msgid "%qE attribute has no effect"
+ msgstr ""
+ 
+-#: ada/gcc-interface/utils.c:6166
++#: ada/gcc-interface/utils.c:6192
+ #, gcc-internal-format
+ msgid "attribute %qs applies to array types only"
+ msgstr ""
+@@ -31077,7 +31151,7 @@
+ #. an unprototyped function, it is compile-time undefined;
+ #. making it a constraint in that case was rejected in
+ #. DR#252.
+-#: c/c-convert.c:98 c/c-typeck.c:2116 c/c-typeck.c:6137 c/c-typeck.c:11655
++#: c/c-convert.c:98 c/c-typeck.c:2116 c/c-typeck.c:6147 c/c-typeck.c:11665
+ #: cp/typeck.c:1956 cp/typeck.c:7557 cp/typeck.c:8284
+ #, gcc-internal-format
+ msgid "void value not ignored as it ought to be"
+@@ -31138,7 +31212,7 @@
+ msgid "type of array %q+D completed incompatibly with implicit initialization"
+ msgstr ""
+ 
+-#: c/c-decl.c:1559 c/c-decl.c:6391 c/c-decl.c:7265 c/c-decl.c:8004
++#: c/c-decl.c:1559 c/c-decl.c:6401 c/c-decl.c:7275 c/c-decl.c:8014
+ #, gcc-internal-format
+ msgid "originally defined here"
+ msgstr ""
+@@ -31435,9 +31509,9 @@
+ msgid "label %qD defined here"
+ msgstr ""
+ 
+-#: c/c-decl.c:3544 c/c-decl.c:3815 c/c-typeck.c:7884 cp/class.c:1438
+-#: cp/class.c:3303 cp/decl.c:3795 cp/friend.c:340 cp/friend.c:349
+-#: cp/parser.c:3146 cp/parser.c:3227 cp/parser.c:3255 cp/parser.c:5994
++#: c/c-decl.c:3544 c/c-decl.c:3815 c/c-typeck.c:7894 cp/class.c:1440
++#: cp/class.c:3307 cp/decl.c:3795 cp/friend.c:340 cp/friend.c:349
++#: cp/parser.c:3146 cp/parser.c:3227 cp/parser.c:3255 cp/parser.c:5996
+ #, gcc-internal-format
+ msgid "%qD declared here"
+ msgstr ""
+@@ -31568,12 +31642,12 @@
+ #. C99 6.7.5.2p4
+ #. A function definition isn't function prototype scope C99 6.2.1p4.
+ #. C99 6.7.5.2p4
+-#: c/c-decl.c:4349 c/c-decl.c:6833
++#: c/c-decl.c:4349 c/c-decl.c:6843
+ #, gcc-internal-format
+ msgid "%<[*]%> not allowed in other than function prototype scope"
+ msgstr ""
+ 
+-#: c/c-decl.c:4436 cp/decl2.c:1463
++#: c/c-decl.c:4436 cp/decl2.c:1464
+ #, gcc-internal-format
+ msgid "%q+D in declare target directive does not have mappable type"
+ msgstr ""
+@@ -31603,7 +31677,7 @@
+ #. of VLAs themselves count as VLAs, it does not make
+ #. sense to permit them to be initialized given that
+ #. ordinary VLAs may not be initialized.
+-#: c/c-decl.c:4524 c/c-decl.c:4539 c/c-typeck.c:7191
++#: c/c-decl.c:4524 c/c-decl.c:4539 c/c-typeck.c:7201
+ #, gcc-internal-format
+ msgid "variable-sized object may not be initialized"
+ msgstr ""
+@@ -31733,127 +31807,127 @@
+ msgid "ISO C90 forbids variable length array"
+ msgstr ""
+ 
+-#: c/c-decl.c:5480 c/c-decl.c:5843 c/c-decl.c:5853
++#: c/c-decl.c:5490 c/c-decl.c:5853 c/c-decl.c:5863
+ #, gcc-internal-format
+ msgid "variably modified %qE at file scope"
+ msgstr ""
+ 
+-#: c/c-decl.c:5482
++#: c/c-decl.c:5492
+ #, gcc-internal-format
+ msgid "variably modified field at file scope"
+ msgstr ""
+ 
+-#: c/c-decl.c:5502
++#: c/c-decl.c:5512
+ #, gcc-internal-format
+ msgid "type defaults to %<int%> in declaration of %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:5506
++#: c/c-decl.c:5516
+ #, gcc-internal-format
+ msgid "type defaults to %<int%> in type name"
+ msgstr ""
+ 
+-#: c/c-decl.c:5538
++#: c/c-decl.c:5548
+ #, gcc-internal-format
+ msgid "duplicate %<const%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5540
++#: c/c-decl.c:5550
+ #, gcc-internal-format
+ msgid "duplicate %<restrict%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5542
++#: c/c-decl.c:5552
+ #, gcc-internal-format
+ msgid "duplicate %<volatile%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5544
++#: c/c-decl.c:5554
+ #, gcc-internal-format
+ msgid "duplicate %<_Atomic%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5547
++#: c/c-decl.c:5557
+ #, gcc-internal-format, gfc-internal-format
+ msgid "conflicting named address spaces (%s vs %s)"
+ msgstr ""
+ 
+-#: c/c-decl.c:5570 c/c-parser.c:2584
++#: c/c-decl.c:5580 c/c-parser.c:2584
+ #, gcc-internal-format
+ msgid "%<_Atomic%>-qualified array type"
+ msgstr ""
+ 
+-#: c/c-decl.c:5584
++#: c/c-decl.c:5594
+ #, gcc-internal-format
+ msgid "function definition declared %<auto%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5586
++#: c/c-decl.c:5596
+ #, gcc-internal-format
+ msgid "function definition declared %<register%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5588
++#: c/c-decl.c:5598
+ #, gcc-internal-format
+ msgid "function definition declared %<typedef%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5590
++#: c/c-decl.c:5600
+ #, gcc-internal-format
+ msgid "function definition declared %qs"
+ msgstr ""
+ 
+-#: c/c-decl.c:5608
++#: c/c-decl.c:5618
+ #, gcc-internal-format
+ msgid "storage class specified for structure field %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:5611
++#: c/c-decl.c:5621
+ #, gcc-internal-format
+ msgid "storage class specified for structure field"
+ msgstr ""
+ 
+-#: c/c-decl.c:5615
++#: c/c-decl.c:5625
+ #, gcc-internal-format
+ msgid "storage class specified for parameter %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:5618
++#: c/c-decl.c:5628
+ #, gcc-internal-format
+ msgid "storage class specified for unnamed parameter"
+ msgstr ""
+ 
+-#: c/c-decl.c:5621 cp/decl.c:9953
++#: c/c-decl.c:5631 cp/decl.c:9953
+ #, gcc-internal-format
+ msgid "storage class specified for typename"
+ msgstr ""
+ 
+-#: c/c-decl.c:5638
++#: c/c-decl.c:5648
+ #, gcc-internal-format
+ msgid "%qE initialized and declared %<extern%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5642
++#: c/c-decl.c:5652
+ #, gcc-internal-format
+ msgid "%qE has both %<extern%> and initializer"
+ msgstr ""
+ 
+-#: c/c-decl.c:5647
++#: c/c-decl.c:5657
+ #, gcc-internal-format
+ msgid "file-scope declaration of %qE specifies %<auto%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5651
++#: c/c-decl.c:5661
+ #, gcc-internal-format
+ msgid "file-scope declaration of %qE specifies %<register%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5656
++#: c/c-decl.c:5666
+ #, gcc-internal-format
+ msgid "nested function %qE declared %<extern%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:5659
++#: c/c-decl.c:5669
+ #, gcc-internal-format
+ msgid "function-scope %qE implicitly auto and declared %qs"
+ msgstr ""
+@@ -31861,83 +31935,83 @@
+ #. Only the innermost declarator (making a parameter be of
+ #. array type which is converted to pointer type)
+ #. may have static or type qualifiers.
+-#: c/c-decl.c:5706 c/c-decl.c:6064
++#: c/c-decl.c:5716 c/c-decl.c:6074
+ #, gcc-internal-format
+ msgid "static or type qualifiers in non-parameter array declarator"
+ msgstr ""
+ 
+-#: c/c-decl.c:5754
++#: c/c-decl.c:5764
+ #, gcc-internal-format
+ msgid "declaration of %qE as array of voids"
+ msgstr ""
+ 
+-#: c/c-decl.c:5756
++#: c/c-decl.c:5766
+ #, gcc-internal-format
+ msgid "declaration of type name as array of voids"
+ msgstr ""
+ 
+-#: c/c-decl.c:5763
++#: c/c-decl.c:5773
+ #, gcc-internal-format
+ msgid "declaration of %qE as array of functions"
+ msgstr ""
+ 
+-#: c/c-decl.c:5766
++#: c/c-decl.c:5776
+ #, gcc-internal-format
+ msgid "declaration of type name as array of functions"
+ msgstr ""
+ 
+-#: c/c-decl.c:5774 c/c-decl.c:7759
++#: c/c-decl.c:5784 c/c-decl.c:7769
+ #, gcc-internal-format
+ msgid "invalid use of structure with flexible array member"
+ msgstr ""
+ 
+-#: c/c-decl.c:5800
++#: c/c-decl.c:5810
+ #, gcc-internal-format
+ msgid "size of array %qE has non-integer type"
+ msgstr ""
+ 
+-#: c/c-decl.c:5804
++#: c/c-decl.c:5814
+ #, gcc-internal-format
+ msgid "size of unnamed array has non-integer type"
+ msgstr ""
+ 
+-#: c/c-decl.c:5814
++#: c/c-decl.c:5824
+ #, gcc-internal-format
+ msgid "ISO C forbids zero-size array %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:5817
++#: c/c-decl.c:5827
+ #, gcc-internal-format
+ msgid "ISO C forbids zero-size array"
+ msgstr ""
+ 
+-#: c/c-decl.c:5826
++#: c/c-decl.c:5836
+ #, gcc-internal-format
+ msgid "size of array %qE is negative"
+ msgstr ""
+ 
+-#: c/c-decl.c:5828
++#: c/c-decl.c:5838
+ #, gcc-internal-format
+ msgid "size of unnamed array is negative"
+ msgstr ""
+ 
+-#: c/c-decl.c:5952 c/c-decl.c:6561
++#: c/c-decl.c:5962 c/c-decl.c:6571
+ #, gcc-internal-format
+ msgid "ISO C90 does not support flexible array members"
+ msgstr ""
+ 
+ #. C99 6.7.5.2p4
+-#: c/c-decl.c:5974
++#: c/c-decl.c:5984
+ #, gcc-internal-format
+ msgid "%<[*]%> not in a declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:5987
++#: c/c-decl.c:5997
+ #, gcc-internal-format
+ msgid "array type has incomplete element type %qT"
+ msgstr ""
+ 
+-#: c/c-decl.c:5993
++#: c/c-decl.c:6003
+ #, gcc-internal-format
+ msgid ""
+ "declaration of %qE as multidimensional array must have bounds for all "
+@@ -31944,7 +32018,7 @@
+ "dimensions except the first"
+ msgstr ""
+ 
+-#: c/c-decl.c:5997
++#: c/c-decl.c:6007
+ #, gcc-internal-format
+ msgid ""
+ "declaration of multidimensional array must have bounds for all dimensions "
+@@ -31951,289 +32025,289 @@
+ "except the first"
+ msgstr ""
+ 
+-#: c/c-decl.c:6100
++#: c/c-decl.c:6110
+ #, gcc-internal-format
+ msgid "%qE declared as function returning a function"
+ msgstr ""
+ 
+-#: c/c-decl.c:6103
++#: c/c-decl.c:6113
+ #, gcc-internal-format
+ msgid "type name declared as function returning a function"
+ msgstr ""
+ 
+-#: c/c-decl.c:6110
++#: c/c-decl.c:6120
+ #, gcc-internal-format
+ msgid "%qE declared as function returning an array"
+ msgstr ""
+ 
+-#: c/c-decl.c:6113
++#: c/c-decl.c:6123
+ #, gcc-internal-format
+ msgid "type name declared as function returning an array"
+ msgstr ""
+ 
+-#: c/c-decl.c:6141
++#: c/c-decl.c:6151
+ #, gcc-internal-format
+ msgid "function definition has qualified void return type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6144 cp/decl.c:10083
++#: c/c-decl.c:6154 cp/decl.c:10083
+ #, gcc-internal-format
+ msgid "type qualifiers ignored on function return type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6173 c/c-decl.c:6357 c/c-decl.c:6411 c/c-decl.c:6495
+-#: c/c-decl.c:6613 c/c-parser.c:2586
++#: c/c-decl.c:6183 c/c-decl.c:6367 c/c-decl.c:6421 c/c-decl.c:6505
++#: c/c-decl.c:6623 c/c-parser.c:2586
+ #, gcc-internal-format
+ msgid "%<_Atomic%>-qualified function type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6179 c/c-decl.c:6363 c/c-decl.c:6500 c/c-decl.c:6618
++#: c/c-decl.c:6189 c/c-decl.c:6373 c/c-decl.c:6510 c/c-decl.c:6628
+ #, gcc-internal-format
+ msgid "ISO C forbids qualified function types"
+ msgstr ""
+ 
+-#: c/c-decl.c:6248
++#: c/c-decl.c:6258
+ #, gcc-internal-format
+ msgid "%qs combined with %<auto%> qualifier for %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6252
++#: c/c-decl.c:6262
+ #, gcc-internal-format
+ msgid "%qs combined with %<register%> qualifier for %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6258
++#: c/c-decl.c:6268
+ #, gcc-internal-format
+ msgid "%qs specified for auto variable %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6274
++#: c/c-decl.c:6284
+ #, gcc-internal-format
+ msgid "%qs specified for parameter %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6277
++#: c/c-decl.c:6287
+ #, gcc-internal-format
+ msgid "%qs specified for unnamed parameter"
+ msgstr ""
+ 
+-#: c/c-decl.c:6283
++#: c/c-decl.c:6293
+ #, gcc-internal-format
+ msgid "%qs specified for structure field %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6286
++#: c/c-decl.c:6296
+ #, gcc-internal-format
+ msgid "%qs specified for structure field"
+ msgstr ""
+ 
+-#: c/c-decl.c:6301
++#: c/c-decl.c:6311
+ #, gcc-internal-format
+ msgid "bit-field %qE has atomic type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6303
++#: c/c-decl.c:6313
+ #, gcc-internal-format
+ msgid "bit-field has atomic type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6312
++#: c/c-decl.c:6322
+ #, gcc-internal-format
+ msgid "alignment specified for typedef %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6314
++#: c/c-decl.c:6324
+ #, gcc-internal-format
+ msgid "alignment specified for %<register%> object %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6319
++#: c/c-decl.c:6329
+ #, gcc-internal-format
+ msgid "alignment specified for parameter %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6321
++#: c/c-decl.c:6331
+ #, gcc-internal-format
+ msgid "alignment specified for unnamed parameter"
+ msgstr ""
+ 
+-#: c/c-decl.c:6326
++#: c/c-decl.c:6336
+ #, gcc-internal-format
+ msgid "alignment specified for bit-field %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6328
++#: c/c-decl.c:6338
+ #, gcc-internal-format
+ msgid "alignment specified for unnamed bit-field"
+ msgstr ""
+ 
+-#: c/c-decl.c:6331
++#: c/c-decl.c:6341
+ #, gcc-internal-format
+ msgid "alignment specified for function %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6338
++#: c/c-decl.c:6348
+ #, gcc-internal-format
+ msgid "%<_Alignas%> specifiers cannot reduce alignment of %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6341
++#: c/c-decl.c:6351
+ #, gcc-internal-format
+ msgid "%<_Alignas%> specifiers cannot reduce alignment of unnamed field"
+ msgstr ""
+ 
+-#: c/c-decl.c:6372
++#: c/c-decl.c:6382
+ #, gcc-internal-format
+ msgid "typedef %q+D declared %<inline%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6374
++#: c/c-decl.c:6384
+ #, gcc-internal-format
+ msgid "typedef %q+D declared %<_Noreturn%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6417
++#: c/c-decl.c:6427
+ #, gcc-internal-format
+ msgid "ISO C forbids const or volatile function types"
+ msgstr ""
+ 
+ #. C99 6.7.2.1p8
+-#: c/c-decl.c:6428
++#: c/c-decl.c:6438
+ #, gcc-internal-format
+ msgid "a member of a structure or union cannot have a variably modified type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6445 cp/decl.c:9158
++#: c/c-decl.c:6455 cp/decl.c:9158
+ #, gcc-internal-format
+ msgid "variable or field %qE declared void"
+ msgstr ""
+ 
+-#: c/c-decl.c:6485
++#: c/c-decl.c:6495
+ #, gcc-internal-format
+ msgid "attributes in parameter array declarator ignored"
+ msgstr ""
+ 
+-#: c/c-decl.c:6527
++#: c/c-decl.c:6537
+ #, gcc-internal-format
+ msgid "parameter %q+D declared %<inline%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6529
++#: c/c-decl.c:6539
+ #, gcc-internal-format
+ msgid "parameter %q+D declared %<_Noreturn%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6542
++#: c/c-decl.c:6552
+ #, gcc-internal-format
+ msgid "field %qE declared as a function"
+ msgstr ""
+ 
+-#: c/c-decl.c:6549
++#: c/c-decl.c:6559
+ #, gcc-internal-format
+ msgid "field %qE has incomplete type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6551
++#: c/c-decl.c:6561
+ #, gcc-internal-format
+ msgid "unnamed field has incomplete type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6584 c/c-decl.c:6595 c/c-decl.c:6598
++#: c/c-decl.c:6594 c/c-decl.c:6605 c/c-decl.c:6608
+ #, gcc-internal-format
+ msgid "invalid storage class for function %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:6655
++#: c/c-decl.c:6665
+ #, gcc-internal-format
+ msgid "cannot inline function %<main%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6657
++#: c/c-decl.c:6667
+ #, gcc-internal-format
+ msgid "%<main%> declared %<_Noreturn%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6668
++#: c/c-decl.c:6678
+ #, gcc-internal-format
+ msgid "ISO C99 does not support %<_Noreturn%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6671
++#: c/c-decl.c:6681
+ #, gcc-internal-format
+ msgid "ISO C90 does not support %<_Noreturn%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6700
++#: c/c-decl.c:6710
+ #, gcc-internal-format
+ msgid "variable previously declared %<static%> redeclared %<extern%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6710
++#: c/c-decl.c:6720
+ #, gcc-internal-format
+ msgid "variable %q+D declared %<inline%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6712
++#: c/c-decl.c:6722
+ #, gcc-internal-format
+ msgid "variable %q+D declared %<_Noreturn%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:6747
++#: c/c-decl.c:6757
+ #, gcc-internal-format
+ msgid "non-nested function with variably modified type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6749
++#: c/c-decl.c:6759
+ #, gcc-internal-format
+ msgid "object with variably modified type must have no linkage"
+ msgstr ""
+ 
+-#: c/c-decl.c:6839 c/c-decl.c:8444
++#: c/c-decl.c:6849 c/c-decl.c:8454
+ #, gcc-internal-format
+ msgid "function declaration isn%'t a prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:6848
++#: c/c-decl.c:6858
+ #, gcc-internal-format
+ msgid "parameter names (without types) in function declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:6886
++#: c/c-decl.c:6896
+ #, gcc-internal-format
+ msgid "parameter %u (%q+D) has incomplete type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6890
++#: c/c-decl.c:6900
+ #, gcc-internal-format, gfc-internal-format
+ msgid "parameter %u has incomplete type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6901
++#: c/c-decl.c:6911
+ #, gcc-internal-format
+ msgid "parameter %u (%q+D) has void type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6905
++#: c/c-decl.c:6915
+ #, gcc-internal-format, gfc-internal-format
+ msgid "parameter %u has void type"
+ msgstr ""
+ 
+-#: c/c-decl.c:6988
++#: c/c-decl.c:6998
+ #, gcc-internal-format
+ msgid "%<void%> as only parameter may not be qualified"
+ msgstr ""
+ 
+-#: c/c-decl.c:6992 c/c-decl.c:7028
++#: c/c-decl.c:7002 c/c-decl.c:7038
+ #, gcc-internal-format
+ msgid "%<void%> must be the only parameter"
+ msgstr ""
+ 
+-#: c/c-decl.c:7022
++#: c/c-decl.c:7032
+ #, gcc-internal-format
+ msgid "parameter %q+D has just a forward declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:7068
++#: c/c-decl.c:7078
+ #, gcc-internal-format
+ msgid ""
+ "%<%s %E%> declared inside parameter list will not be visible outside of this "
+@@ -32240,7 +32314,7 @@
+ "definition or declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:7074
++#: c/c-decl.c:7084
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "anonymous %s declared inside parameter list will not be visible outside of "
+@@ -32247,313 +32321,313 @@
+ "this definition or declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:7176
++#: c/c-decl.c:7186
+ #, gcc-internal-format
+ msgid "enum type defined here"
+ msgstr ""
+ 
+-#: c/c-decl.c:7182
++#: c/c-decl.c:7192
+ #, gcc-internal-format
+ msgid "struct defined here"
+ msgstr ""
+ 
+-#: c/c-decl.c:7188
++#: c/c-decl.c:7198
+ #, gcc-internal-format
+ msgid "union defined here"
+ msgstr ""
+ 
+-#: c/c-decl.c:7261
++#: c/c-decl.c:7271
+ #, gcc-internal-format
+ msgid "redefinition of %<union %E%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:7263
++#: c/c-decl.c:7273
+ #, gcc-internal-format
+ msgid "redefinition of %<struct %E%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:7272
++#: c/c-decl.c:7282
+ #, gcc-internal-format
+ msgid "nested redefinition of %<union %E%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:7274
++#: c/c-decl.c:7284
+ #, gcc-internal-format
+ msgid "nested redefinition of %<struct %E%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:7307 c/c-decl.c:8023
++#: c/c-decl.c:7317 c/c-decl.c:8033
+ #, gcc-internal-format
+ msgid "defining type in %qs expression is invalid in C++"
+ msgstr ""
+ 
+-#: c/c-decl.c:7375 cp/decl.c:4616
++#: c/c-decl.c:7385 cp/decl.c:4616
+ #, gcc-internal-format
+ msgid "declaration does not declare anything"
+ msgstr ""
+ 
+-#: c/c-decl.c:7380
++#: c/c-decl.c:7390
+ #, gcc-internal-format
+ msgid "ISO C99 doesn%'t support unnamed structs/unions"
+ msgstr ""
+ 
+-#: c/c-decl.c:7383
++#: c/c-decl.c:7393
+ #, gcc-internal-format
+ msgid "ISO C90 doesn%'t support unnamed structs/unions"
+ msgstr ""
+ 
+-#: c/c-decl.c:7474 c/c-decl.c:7492 c/c-decl.c:7553
++#: c/c-decl.c:7484 c/c-decl.c:7502 c/c-decl.c:7563
+ #, gcc-internal-format
+ msgid "duplicate member %q+D"
+ msgstr ""
+ 
+-#: c/c-decl.c:7579
++#: c/c-decl.c:7589
+ #, gcc-internal-format
+ msgid "empty struct has size 0 in C, size 1 in C++"
+ msgstr ""
+ 
+-#: c/c-decl.c:7582
++#: c/c-decl.c:7592
+ #, gcc-internal-format
+ msgid "empty union has size 0 in C, size 1 in C++"
+ msgstr ""
+ 
+-#: c/c-decl.c:7668
++#: c/c-decl.c:7678
+ #, gcc-internal-format
+ msgid "union has no named members"
+ msgstr ""
+ 
+-#: c/c-decl.c:7670
++#: c/c-decl.c:7680
+ #, gcc-internal-format
+ msgid "union has no members"
+ msgstr ""
+ 
+-#: c/c-decl.c:7675
++#: c/c-decl.c:7685
+ #, gcc-internal-format
+ msgid "struct has no named members"
+ msgstr ""
+ 
+-#: c/c-decl.c:7677
++#: c/c-decl.c:7687
+ #, gcc-internal-format
+ msgid "struct has no members"
+ msgstr ""
+ 
+-#: c/c-decl.c:7739 cp/decl.c:11032
++#: c/c-decl.c:7749 cp/decl.c:11032
+ #, gcc-internal-format
+ msgid "flexible array member in union"
+ msgstr ""
+ 
+-#: c/c-decl.c:7745
++#: c/c-decl.c:7755
+ #, gcc-internal-format
+ msgid "flexible array member not at end of struct"
+ msgstr ""
+ 
+-#: c/c-decl.c:7751
++#: c/c-decl.c:7761
+ #, gcc-internal-format
+ msgid "flexible array member in otherwise empty struct"
+ msgstr ""
+ 
+-#: c/c-decl.c:7781
++#: c/c-decl.c:7791
+ #, gcc-internal-format
+ msgid "type %qT is too large"
+ msgstr ""
+ 
+-#: c/c-decl.c:7904
++#: c/c-decl.c:7914
+ #, gcc-internal-format
+ msgid "union cannot be made transparent"
+ msgstr ""
+ 
+-#: c/c-decl.c:7995
++#: c/c-decl.c:8005
+ #, gcc-internal-format
+ msgid "nested redefinition of %<enum %E%>"
+ msgstr ""
+ 
+ #. This enum is a named one that has been declared already.
+-#: c/c-decl.c:8002
++#: c/c-decl.c:8012
+ #, gcc-internal-format
+ msgid "redeclaration of %<enum %E%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:8081 cp/decl.c:13403
++#: c/c-decl.c:8091 cp/decl.c:13403
+ #, gcc-internal-format
+ msgid "specified mode too small for enumeral values"
+ msgstr ""
+ 
+-#: c/c-decl.c:8096
++#: c/c-decl.c:8106
+ #, gcc-internal-format
+ msgid "enumeration values exceed range of largest integer"
+ msgstr ""
+ 
+-#: c/c-decl.c:8210 c/c-decl.c:8226
++#: c/c-decl.c:8220 c/c-decl.c:8236
+ #, gcc-internal-format
+ msgid "enumerator value for %qE is not an integer constant"
+ msgstr ""
+ 
+-#: c/c-decl.c:8221
++#: c/c-decl.c:8231
+ #, gcc-internal-format
+ msgid "enumerator value for %qE is not an integer constant expression"
+ msgstr ""
+ 
+-#: c/c-decl.c:8245
++#: c/c-decl.c:8255
+ #, gcc-internal-format
+ msgid "overflow in enumeration values"
+ msgstr ""
+ 
+-#: c/c-decl.c:8253
++#: c/c-decl.c:8263
+ #, gcc-internal-format
+ msgid "ISO C restricts enumerator values to range of %<int%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:8339 cp/decl.c:4918 cp/decl.c:13899
++#: c/c-decl.c:8349 cp/decl.c:4918 cp/decl.c:13902
+ #, gcc-internal-format
+ msgid "inline function %qD given attribute noinline"
+ msgstr ""
+ 
+-#: c/c-decl.c:8357
++#: c/c-decl.c:8367
+ #, gcc-internal-format
+ msgid "return type is an incomplete type"
+ msgstr ""
+ 
+-#: c/c-decl.c:8368
++#: c/c-decl.c:8378
+ #, gcc-internal-format
+ msgid "return type defaults to %<int%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:8394
++#: c/c-decl.c:8404
+ #, gcc-internal-format
+ msgid "%q+D defined as variadic function without prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:8453
++#: c/c-decl.c:8463
+ #, gcc-internal-format
+ msgid "no previous prototype for %qD"
+ msgstr ""
+ 
+-#: c/c-decl.c:8462
++#: c/c-decl.c:8472
+ #, gcc-internal-format
+ msgid "%qD was used with no prototype before its definition"
+ msgstr ""
+ 
+-#: c/c-decl.c:8470 cp/decl.c:14042
++#: c/c-decl.c:8480 cp/decl.c:14045
+ #, gcc-internal-format
+ msgid "no previous declaration for %qD"
+ msgstr ""
+ 
+-#: c/c-decl.c:8480
++#: c/c-decl.c:8490
+ #, gcc-internal-format
+ msgid "%qD was used with no declaration before its definition"
+ msgstr ""
+ 
+-#: c/c-decl.c:8499
++#: c/c-decl.c:8509
+ #, gcc-internal-format
+ msgid "return type of %qD is not %<int%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:8501
++#: c/c-decl.c:8511
+ #, gcc-internal-format
+ msgid "%<_Atomic%>-qualified return type of %qD"
+ msgstr ""
+ 
+-#: c/c-decl.c:8508
++#: c/c-decl.c:8518
+ #, gcc-internal-format
+ msgid "%qD is normally a non-static function"
+ msgstr ""
+ 
+-#: c/c-decl.c:8545
++#: c/c-decl.c:8555
+ #, gcc-internal-format
+ msgid "old-style parameter declarations in prototyped function definition"
+ msgstr ""
+ 
+-#: c/c-decl.c:8560
++#: c/c-decl.c:8570
+ #, gcc-internal-format
+ msgid "traditional C rejects ISO C style function definitions"
+ msgstr ""
+ 
+-#: c/c-decl.c:8576
++#: c/c-decl.c:8586
+ #, gcc-internal-format
+ msgid "parameter name omitted"
+ msgstr ""
+ 
+-#: c/c-decl.c:8613
++#: c/c-decl.c:8623
+ #, gcc-internal-format
+ msgid "old-style function definition"
+ msgstr ""
+ 
+-#: c/c-decl.c:8622
++#: c/c-decl.c:8632
+ #, gcc-internal-format
+ msgid "parameter name missing from parameter list"
+ msgstr ""
+ 
+-#: c/c-decl.c:8637
++#: c/c-decl.c:8647
+ #, gcc-internal-format
+ msgid "%qD declared as a non-parameter"
+ msgstr ""
+ 
+-#: c/c-decl.c:8643
++#: c/c-decl.c:8653
+ #, gcc-internal-format
+ msgid "multiple parameters named %qD"
+ msgstr ""
+ 
+-#: c/c-decl.c:8652
++#: c/c-decl.c:8662
+ #, gcc-internal-format
+ msgid "parameter %qD declared with void type"
+ msgstr ""
+ 
+-#: c/c-decl.c:8681 c/c-decl.c:8686
++#: c/c-decl.c:8691 c/c-decl.c:8696
+ #, gcc-internal-format
+ msgid "type of %qD defaults to %<int%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:8706
++#: c/c-decl.c:8716
+ #, gcc-internal-format
+ msgid "parameter %qD has incomplete type"
+ msgstr ""
+ 
+-#: c/c-decl.c:8713
++#: c/c-decl.c:8723
+ #, gcc-internal-format
+ msgid "declaration for parameter %qD but no such parameter"
+ msgstr ""
+ 
+-#: c/c-decl.c:8763
++#: c/c-decl.c:8773
+ #, gcc-internal-format
+ msgid "number of arguments doesn%'t match built-in prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:8774
++#: c/c-decl.c:8784
+ #, gcc-internal-format
+ msgid "number of arguments doesn%'t match prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:8777 c/c-decl.c:8824 c/c-decl.c:8838
++#: c/c-decl.c:8787 c/c-decl.c:8834 c/c-decl.c:8848
+ #, gcc-internal-format
+ msgid "prototype declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:8816
++#: c/c-decl.c:8826
+ #, gcc-internal-format
+ msgid "promoted argument %qD doesn%'t match built-in prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:8821
++#: c/c-decl.c:8831
+ #, gcc-internal-format
+ msgid "promoted argument %qD doesn%'t match prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:8831
++#: c/c-decl.c:8841
+ #, gcc-internal-format
+ msgid "argument %qD doesn%'t match built-in prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:8836
++#: c/c-decl.c:8846
+ #, gcc-internal-format
+ msgid "argument %qD doesn%'t match prototype"
+ msgstr ""
+ 
+-#: c/c-decl.c:9093 cp/decl.c:14796
++#: c/c-decl.c:9103 cp/decl.c:14799
+ #, gcc-internal-format
+ msgid "no return statement in function returning non-void"
+ msgstr ""
+ 
+-#: c/c-decl.c:9113 cp/decl.c:14828
++#: c/c-decl.c:9123 cp/decl.c:14831
+ #, gcc-internal-format
+ msgid "parameter %qD set but not used"
+ msgstr ""
+@@ -32561,194 +32635,194 @@
+ #. If we get here, declarations have been used in a for loop without
+ #. the C99 for loop scope.  This doesn't make much sense, so don't
+ #. allow it.
+-#: c/c-decl.c:9207
++#: c/c-decl.c:9217
+ #, gcc-internal-format
+ msgid "%<for%> loop initial declarations are only allowed in C99 or C11 mode"
+ msgstr ""
+ 
+-#: c/c-decl.c:9212
++#: c/c-decl.c:9222
+ #, gcc-internal-format
+ msgid ""
+ "use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code"
+ msgstr ""
+ 
+-#: c/c-decl.c:9247
++#: c/c-decl.c:9257
+ #, gcc-internal-format
+ msgid "declaration of static variable %qD in %<for%> loop initial declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:9251
++#: c/c-decl.c:9261
+ #, gcc-internal-format
+ msgid ""
+ "declaration of %<extern%> variable %qD in %<for%> loop initial declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:9258
++#: c/c-decl.c:9268
+ #, gcc-internal-format
+ msgid "%<struct %E%> declared in %<for%> loop initial declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:9263
++#: c/c-decl.c:9273
+ #, gcc-internal-format
+ msgid "%<union %E%> declared in %<for%> loop initial declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:9267
++#: c/c-decl.c:9277
+ #, gcc-internal-format
+ msgid "%<enum %E%> declared in %<for%> loop initial declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:9271
++#: c/c-decl.c:9281
+ #, gcc-internal-format
+ msgid "declaration of non-variable %qD in %<for%> loop initial declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:9519
++#: c/c-decl.c:9529
+ #, gcc-internal-format
+ msgid "incompatible address space qualifiers %qs and %qs"
+ msgstr ""
+ 
+-#: c/c-decl.c:9569 c/c-decl.c:9926 c/c-decl.c:10416
++#: c/c-decl.c:9579 c/c-decl.c:9936 c/c-decl.c:10426
+ #, gcc-internal-format
+ msgid "duplicate %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:9595 c/c-decl.c:9938 c/c-decl.c:10259
++#: c/c-decl.c:9605 c/c-decl.c:9948 c/c-decl.c:10269
+ #, gcc-internal-format
+ msgid "two or more data types in declaration specifiers"
+ msgstr ""
+ 
+-#: c/c-decl.c:9607 cp/parser.c:26808
++#: c/c-decl.c:9617 cp/parser.c:26823
+ #, gcc-internal-format
+ msgid "%<long long long%> is too long for GCC"
+ msgstr ""
+ 
+-#: c/c-decl.c:9620
++#: c/c-decl.c:9630
+ #, gcc-internal-format
+ msgid "ISO C90 does not support %<long long%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:9817 c/c-parser.c:7943
++#: c/c-decl.c:9827 c/c-parser.c:7943
+ #, gcc-internal-format
+ msgid "ISO C90 does not support complex types"
+ msgstr ""
+ 
+-#: c/c-decl.c:9863
++#: c/c-decl.c:9873
+ #, gcc-internal-format
+ msgid "ISO C does not support saturating types"
+ msgstr ""
+ 
+-#: c/c-decl.c:9981
++#: c/c-decl.c:9991
+ #, gcc-internal-format
+ msgid "ISO C does not support %<__int%d%> types"
+ msgstr ""
+ 
+-#: c/c-decl.c:10001
++#: c/c-decl.c:10011
+ #, gcc-internal-format
+ msgid "%<__int%d%> is not supported on this target"
+ msgstr ""
+ 
+-#: c/c-decl.c:10043
++#: c/c-decl.c:10053
+ #, gcc-internal-format
+ msgid "ISO C90 does not support boolean types"
+ msgstr ""
+ 
+-#: c/c-decl.c:10217
++#: c/c-decl.c:10227
+ #, gcc-internal-format
+ msgid "ISO C does not support decimal floating point"
+ msgstr ""
+ 
+-#: c/c-decl.c:10240 c/c-decl.c:10506 c/c-parser.c:7446
++#: c/c-decl.c:10250 c/c-decl.c:10516 c/c-parser.c:7446
+ #, gcc-internal-format
+ msgid "fixed-point types not supported for this target"
+ msgstr ""
+ 
+-#: c/c-decl.c:10242
++#: c/c-decl.c:10252
+ #, gcc-internal-format
+ msgid "ISO C does not support fixed-point types"
+ msgstr ""
+ 
+-#: c/c-decl.c:10277
++#: c/c-decl.c:10287
+ #, gcc-internal-format
+ msgid "C++ lookup of %qD would return a field, not a type"
+ msgstr ""
+ 
+-#: c/c-decl.c:10290
++#: c/c-decl.c:10300
+ #, gcc-internal-format
+ msgid "%qE fails to be a typedef or built in type"
+ msgstr ""
+ 
+-#: c/c-decl.c:10338
++#: c/c-decl.c:10348
+ #, gcc-internal-format
+ msgid "%qE is not at beginning of declaration"
+ msgstr ""
+ 
+-#: c/c-decl.c:10359
++#: c/c-decl.c:10369
+ #, gcc-internal-format
+ msgid "%qE used with %<auto%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10361
++#: c/c-decl.c:10371
+ #, gcc-internal-format
+ msgid "%qE used with %<register%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10363
++#: c/c-decl.c:10373
+ #, gcc-internal-format
+ msgid "%qE used with %<typedef%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10377 c/c-parser.c:7023
++#: c/c-decl.c:10387 c/c-parser.c:7023
+ #, gcc-internal-format
+ msgid "ISO C99 does not support %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:10380 c/c-parser.c:7026
++#: c/c-decl.c:10390 c/c-parser.c:7026
+ #, gcc-internal-format
+ msgid "ISO C90 does not support %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:10392
++#: c/c-decl.c:10402
+ #, gcc-internal-format
+ msgid "%<__thread%> before %<extern%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10401
++#: c/c-decl.c:10411
+ #, gcc-internal-format
+ msgid "%<__thread%> before %<static%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10414
++#: c/c-decl.c:10424
+ #, gcc-internal-format
+ msgid "duplicate %<_Thread_local%> or %<__thread%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10422
++#: c/c-decl.c:10432
+ #, gcc-internal-format
+ msgid "multiple storage classes in declaration specifiers"
+ msgstr ""
+ 
+-#: c/c-decl.c:10430
++#: c/c-decl.c:10440
+ #, gcc-internal-format
+ msgid "%qs used with %qE"
+ msgstr ""
+ 
+-#: c/c-decl.c:10503
++#: c/c-decl.c:10513
+ #, gcc-internal-format
+ msgid "%<_Sat%> is used without %<_Fract%> or %<_Accum%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10518
++#: c/c-decl.c:10528
+ #, gcc-internal-format
+ msgid "ISO C does not support plain %<complex%> meaning %<double complex%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:10569 c/c-decl.c:10582 c/c-decl.c:10608
++#: c/c-decl.c:10579 c/c-decl.c:10592 c/c-decl.c:10618
+ #, gcc-internal-format
+ msgid "ISO C does not support complex integer types"
+ msgstr ""
+ 
+-#: c/c-decl.c:11006 cp/semantics.c:5297
++#: c/c-decl.c:11016 cp/semantics.c:5298
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp declare reduction%> combiner refers to variable %qD which is "
+@@ -32755,7 +32829,7 @@
+ "not %<omp_out%> nor %<omp_in%>"
+ msgstr ""
+ 
+-#: c/c-decl.c:11010 cp/semantics.c:5301
++#: c/c-decl.c:11020 cp/semantics.c:5302
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp declare reduction%> initializer refers to variable %qD which "
+@@ -32762,27 +32836,27 @@
+ "is not %<omp_priv%> nor %<omp_orig%>"
+ msgstr ""
+ 
+-#: c/c-fold.c:319 c/c-typeck.c:10988 cp/typeck.c:4465
++#: c/c-fold.c:319 c/c-typeck.c:10998 cp/typeck.c:4465
+ #, gcc-internal-format
+ msgid "left shift of negative value"
+ msgstr ""
+ 
+-#: c/c-fold.c:331 c/c-typeck.c:10997 cp/typeck.c:4473
++#: c/c-fold.c:331 c/c-typeck.c:11007 cp/typeck.c:4473
+ #, gcc-internal-format
+ msgid "left shift count is negative"
+ msgstr ""
+ 
+-#: c/c-fold.c:332 c/c-typeck.c:10936 cp/typeck.c:4419
++#: c/c-fold.c:332 c/c-typeck.c:10946 cp/typeck.c:4419
+ #, gcc-internal-format
+ msgid "right shift count is negative"
+ msgstr ""
+ 
+-#: c/c-fold.c:338 c/c-typeck.c:11004 cp/typeck.c:4481
++#: c/c-fold.c:338 c/c-typeck.c:11014 cp/typeck.c:4481
+ #, gcc-internal-format
+ msgid "left shift count >= width of type"
+ msgstr ""
+ 
+-#: c/c-fold.c:339 c/c-typeck.c:10948 cp/typeck.c:4427
++#: c/c-fold.c:339 c/c-typeck.c:10958 cp/typeck.c:4427
+ #, gcc-internal-format
+ msgid "right shift count >= width of type"
+ msgstr ""
+@@ -32797,7 +32871,7 @@
+ msgid "version control conflict marker in file"
+ msgstr ""
+ 
+-#: c/c-parser.c:1086 cp/parser.c:27015
++#: c/c-parser.c:1086 cp/parser.c:27030
+ #, gcc-internal-format
+ msgid "expected end of line"
+ msgstr ""
+@@ -32833,7 +32907,7 @@
+ msgstr ""
+ 
+ #: c/c-parser.c:1686 c/c-parser.c:10203 c/c-parser.c:15182 c/c-parser.c:16077
+-#: cp/parser.c:34050 cp/parser.c:34949 cp/parser.c:37474
++#: cp/parser.c:34065 cp/parser.c:34964 cp/parser.c:37489
+ #, gcc-internal-format
+ msgid "expected declaration specifiers"
+ msgstr ""
+@@ -32848,7 +32922,7 @@
+ msgid "expected %<;%>, identifier or %<(%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:1735 cp/parser.c:28663 cp/parser.c:28737
++#: c/c-parser.c:1735 cp/parser.c:28678 cp/parser.c:28752
+ #, gcc-internal-format
+ msgid "prefix attributes are ignored for methods"
+ msgstr ""
+@@ -32897,7 +32971,7 @@
+ msgid "%<__auto_type%> may only be used with a single declarator"
+ msgstr ""
+ 
+-#: c/c-parser.c:2036 cp/parser.c:12465
++#: c/c-parser.c:2036 cp/parser.c:12475
+ #, gcc-internal-format
+ msgid "expected %<,%> or %<;%>"
+ msgstr ""
+@@ -32925,7 +32999,7 @@
+ msgid "ISO C90 does not support %<_Static_assert%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:2209 c/c-parser.c:3877 c/c-parser.c:10261 cp/parser.c:37179
++#: c/c-parser.c:2209 c/c-parser.c:3877 c/c-parser.c:10261 cp/parser.c:37194
+ #, gcc-internal-format
+ msgid "expected string literal"
+ msgstr ""
+@@ -32988,14 +33062,14 @@
+ #: c/c-parser.c:9232 c/c-parser.c:9356 c/c-parser.c:9796 c/c-parser.c:9831
+ #: c/c-parser.c:9884 c/c-parser.c:9937 c/c-parser.c:9953 c/c-parser.c:9999
+ #: c/c-parser.c:10575 c/c-parser.c:10616 c/c-parser.c:12546 c/c-parser.c:12780
+-#: c/c-parser.c:14579 c/c-parser.c:17356 c/c-parser.c:17685 cp/parser.c:27018
+-#: cp/parser.c:29506 cp/parser.c:29536 cp/parser.c:29606 cp/parser.c:31701
+-#: cp/parser.c:36893 cp/parser.c:37618
++#: c/c-parser.c:14579 c/c-parser.c:17356 c/c-parser.c:17685 cp/parser.c:27033
++#: cp/parser.c:29521 cp/parser.c:29551 cp/parser.c:29621 cp/parser.c:31716
++#: cp/parser.c:36908 cp/parser.c:37633
+ #, gcc-internal-format
+ msgid "expected identifier"
+ msgstr ""
+ 
+-#: c/c-parser.c:2745 cp/parser.c:17380
++#: c/c-parser.c:2745 cp/parser.c:17390
+ #, gcc-internal-format
+ msgid "comma at end of enumerator list"
+ msgstr ""
+@@ -33130,7 +33204,7 @@
+ msgid "expected %<}%> before %<else%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:4847 cp/parser.c:10803
++#: c/c-parser.c:4847 cp/parser.c:10813
+ #, gcc-internal-format
+ msgid "%<else%> without a previous %<if%>"
+ msgstr ""
+@@ -33151,12 +33225,12 @@
+ "a label can only be part of a statement and a declaration is not a statement"
+ msgstr ""
+ 
+-#: c/c-parser.c:5156 cp/parser.c:10404
++#: c/c-parser.c:5156 cp/parser.c:10414
+ #, gcc-internal-format
+ msgid "-fcilkplus must be enabled to use %<_Cilk_for%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:5166 cp/parser.c:10430
++#: c/c-parser.c:5166 cp/parser.c:10440
+ #, gcc-internal-format
+ msgid "-fcilkplus must be enabled to use %<_Cilk_sync%>"
+ msgstr ""
+@@ -33170,17 +33244,17 @@
+ #. c_parser_skip_until_found stops at a closing nesting
+ #. delimiter without consuming it, but here we need to consume
+ #. it to proceed further.
+-#: c/c-parser.c:5276 cp/parser.c:10508
++#: c/c-parser.c:5276 cp/parser.c:10518
+ #, gcc-internal-format
+ msgid "expected statement"
+ msgstr ""
+ 
+-#: c/c-parser.c:5380 cp/parser.c:11918
++#: c/c-parser.c:5380 cp/parser.c:11928
+ #, gcc-internal-format
+ msgid "suggest braces around empty body in an %<if%> statement"
+ msgstr ""
+ 
+-#: c/c-parser.c:5414 cp/parser.c:11921
++#: c/c-parser.c:5414 cp/parser.c:11931
+ #, gcc-internal-format
+ msgid "suggest braces around empty body in an %<else%> statement"
+ msgstr ""
+@@ -33190,7 +33264,7 @@
+ msgid "if statement cannot contain %<Cilk_spawn%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:5509 cp/parser.c:10957
++#: c/c-parser.c:5509 cp/parser.c:10967
+ #, gcc-internal-format
+ msgid "suggest explicit braces to avoid ambiguous %<else%>"
+ msgstr ""
+@@ -33210,7 +33284,7 @@
+ msgid "invalid iterating variable in fast enumeration"
+ msgstr ""
+ 
+-#: c/c-parser.c:5852 cp/parser.c:11158
++#: c/c-parser.c:5852 cp/parser.c:11168
+ #, gcc-internal-format
+ msgid "missing loop condition in loop with %<GCC ivdep%> pragma"
+ msgstr ""
+@@ -33385,17 +33459,17 @@
+ msgid "%<__builtin_complex%> operands of different types"
+ msgstr ""
+ 
+-#: c/c-parser.c:7986 cp/parser.c:6590
++#: c/c-parser.c:7986 cp/parser.c:6600
+ #, gcc-internal-format
+ msgid "wrong number of arguments to %<__builtin_shuffle%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:8067 cp/parser.c:6535
++#: c/c-parser.c:8067 cp/parser.c:6540
+ #, gcc-internal-format
+ msgid "-fcilkplus must be enabled to use %<_Cilk_spawn%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:8074 cp/parser.c:6541
++#: c/c-parser.c:8074 cp/parser.c:6546
+ #, gcc-internal-format
+ msgid "consecutive %<_Cilk_spawn%> keywords are not permitted"
+ msgstr ""
+@@ -33415,7 +33489,7 @@
+ msgid "ISO C90 forbids compound literals"
+ msgstr ""
+ 
+-#: c/c-parser.c:8295 cp/parser.c:6843
++#: c/c-parser.c:8295 cp/parser.c:6853
+ #, gcc-internal-format
+ msgid ""
+ "%<memset%> used with constant zero length parameter; this could be due to "
+@@ -33457,32 +33531,32 @@
+ msgid "no type or storage class may be specified here,"
+ msgstr ""
+ 
+-#: c/c-parser.c:9800 c/c-parser.c:9857 cp/parser.c:29566
++#: c/c-parser.c:9800 c/c-parser.c:9857 cp/parser.c:29581
+ #, gcc-internal-format
+ msgid "unknown property attribute"
+ msgstr ""
+ 
+-#: c/c-parser.c:9821 cp/parser.c:29526
++#: c/c-parser.c:9821 cp/parser.c:29541
+ #, gcc-internal-format
+ msgid "missing %<=%> (after %<getter%> attribute)"
+ msgstr ""
+ 
+-#: c/c-parser.c:9824 cp/parser.c:29529
++#: c/c-parser.c:9824 cp/parser.c:29544
+ #, gcc-internal-format
+ msgid "missing %<=%> (after %<setter%> attribute)"
+ msgstr ""
+ 
+-#: c/c-parser.c:9838 cp/parser.c:29544
++#: c/c-parser.c:9838 cp/parser.c:29559
+ #, gcc-internal-format
+ msgid "the %<setter%> attribute may only be specified once"
+ msgstr ""
+ 
+-#: c/c-parser.c:9843 cp/parser.c:29550
++#: c/c-parser.c:9843 cp/parser.c:29565
+ #, gcc-internal-format
+ msgid "setter name must terminate with %<:%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:9850 cp/parser.c:29558
++#: c/c-parser.c:9850 cp/parser.c:29573
+ #, gcc-internal-format
+ msgid "the %<getter%> attribute may only be specified once"
+ msgstr ""
+@@ -33492,38 +33566,38 @@
+ msgid "%<#pragma acc update%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:10063 cp/parser.c:37257
++#: c/c-parser.c:10063 cp/parser.c:37272
+ #, gcc-internal-format
+ msgid "%<#pragma omp barrier%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:10074 cp/parser.c:37272
++#: c/c-parser.c:10074 cp/parser.c:37287
+ #, gcc-internal-format
+ msgid "%<#pragma omp flush%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:10085 cp/parser.c:37288
++#: c/c-parser.c:10085 cp/parser.c:37303
+ #, gcc-internal-format
+ msgid "%<#pragma omp taskwait%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:10096 cp/parser.c:37304
++#: c/c-parser.c:10096 cp/parser.c:37319
+ #, gcc-internal-format
+ msgid "%<#pragma omp taskyield%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:10107 cp/parser.c:37320
++#: c/c-parser.c:10107 cp/parser.c:37335
+ #, gcc-internal-format
+ msgid "%<#pragma omp cancel%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:10118 cp/parser.c:37336
++#: c/c-parser.c:10118 cp/parser.c:37351
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp cancellation point%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:10138 cp/parser.c:37409
++#: c/c-parser.c:10138 cp/parser.c:37424
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp section%> may only be used in %<#pragma omp sections%> "
+@@ -33530,12 +33604,12 @@
+ "construct"
+ msgstr ""
+ 
+-#: c/c-parser.c:10157 cp/parser.c:37428
++#: c/c-parser.c:10157 cp/parser.c:37443
+ #, gcc-internal-format
+ msgid "for, while or do statement expected"
+ msgstr ""
+ 
+-#: c/c-parser.c:10169 cp/parser.c:37247
++#: c/c-parser.c:10169 cp/parser.c:37262
+ #, gcc-internal-format
+ msgid "%<#pragma GCC pch_preprocess%> must be first"
+ msgstr ""
+@@ -33550,12 +33624,12 @@
+ msgid "%<#pragma grainsize%> must be inside a function"
+ msgstr ""
+ 
+-#: c/c-parser.c:10501 cp/parser.c:29956
++#: c/c-parser.c:10501 cp/parser.c:29971
+ #, gcc-internal-format
+ msgid "too many %qs clauses"
+ msgstr ""
+ 
+-#: c/c-parser.c:10522 cp/parser.c:30485
++#: c/c-parser.c:10522 cp/parser.c:30500
+ #, gcc-internal-format
+ msgid "expected integer expression before ')'"
+ msgstr ""
+@@ -33570,53 +33644,53 @@
+ msgid "%qD is not a variable"
+ msgstr ""
+ 
+-#: c/c-parser.c:10813 cp/semantics.c:6719
++#: c/c-parser.c:10813 cp/semantics.c:6720
+ #, gcc-internal-format
+ msgid "%qD is not a pointer variable"
+ msgstr ""
+ 
+-#: c/c-parser.c:10853 cp/parser.c:30563
++#: c/c-parser.c:10853 cp/parser.c:30578
+ #, gcc-internal-format
+ msgid "collapse argument needs positive constant integer expression"
+ msgstr ""
+ 
+-#: c/c-parser.c:10923 cp/parser.c:30619
++#: c/c-parser.c:10923 cp/parser.c:30634
+ #, gcc-internal-format
+ msgid "expected %<none%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:10925 cp/parser.c:30621
++#: c/c-parser.c:10925 cp/parser.c:30636
+ #, gcc-internal-format
+ msgid "expected %<none%> or %<shared%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:11025 cp/parser.c:30721
++#: c/c-parser.c:11025 cp/parser.c:30736
+ #, gcc-internal-format
+ msgid "expected %<data%>, %<update%>, %<enter%> or %<exit%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:11045 c/c-parser.c:15906 c/c-parser.c:15991 cp/parser.c:30739
+-#: cp/parser.c:34733 cp/parser.c:34821
++#: c/c-parser.c:11045 c/c-parser.c:15906 c/c-parser.c:15991 cp/parser.c:30754
++#: cp/parser.c:34748 cp/parser.c:34836
+ #, gcc-internal-format
+ msgid "expected %<data%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:11092 cp/parser.c:30792
++#: c/c-parser.c:11092 cp/parser.c:30807
+ #, gcc-internal-format
+ msgid "too many %<if%> clauses with %qs modifier"
+ msgstr ""
+ 
+-#: c/c-parser.c:11099 cp/parser.c:30799
++#: c/c-parser.c:11099 cp/parser.c:30814
+ #, gcc-internal-format
+ msgid "too many %<if%> clauses"
+ msgstr ""
+ 
+-#: c/c-parser.c:11101 cp/parser.c:30801
++#: c/c-parser.c:11101 cp/parser.c:30816
+ #, gcc-internal-format
+ msgid "too many %<if%> clauses without modifier"
+ msgstr ""
+ 
+-#: c/c-parser.c:11107 cp/parser.c:30807
++#: c/c-parser.c:11107 cp/parser.c:30822
+ #, gcc-internal-format
+ msgid ""
+ "if any %<if%> clause has modifier, then all %<if%> clauses have to use "
+@@ -33646,22 +33720,22 @@
+ msgid "%<num_tasks%> value must be positive"
+ msgstr ""
+ 
+-#: c/c-parser.c:11324 cp/semantics.c:6895
++#: c/c-parser.c:11324 cp/semantics.c:6896
+ #, gcc-internal-format
+ msgid "%<grainsize%> value must be positive"
+ msgstr ""
+ 
+-#: c/c-parser.c:11369 cp/semantics.c:6924
++#: c/c-parser.c:11369 cp/semantics.c:6925
+ #, gcc-internal-format
+ msgid "%<priority%> value must be non-negative"
+ msgstr ""
+ 
+-#: c/c-parser.c:11430 c/c-parser.c:11436 cp/parser.c:31018 cp/parser.c:31025
++#: c/c-parser.c:11430 c/c-parser.c:11436 cp/parser.c:31033 cp/parser.c:31040
+ #, gcc-internal-format
+ msgid "expected %<tofrom%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:11444 c/c-parser.c:11450 cp/parser.c:31034 cp/parser.c:31041
++#: c/c-parser.c:11444 c/c-parser.c:11450 cp/parser.c:31049 cp/parser.c:31056
+ #, gcc-internal-format
+ msgid "expected %<scalar%>"
+ msgstr ""
+@@ -33671,12 +33745,12 @@
+ msgid "%<num_workers%> value must be positive"
+ msgstr ""
+ 
+-#: c/c-parser.c:11580 cp/parser.c:30347
++#: c/c-parser.c:11580 cp/parser.c:30362
+ #, gcc-internal-format
+ msgid "too many %<static%> arguments"
+ msgstr ""
+ 
+-#: c/c-parser.c:11614 cp/parser.c:30380
++#: c/c-parser.c:11614 cp/parser.c:30395
+ #, gcc-internal-format
+ msgid "unexpected argument"
+ msgstr ""
+@@ -33686,17 +33760,17 @@
+ msgid "%<%s%> value must be positive"
+ msgstr ""
+ 
+-#: c/c-parser.c:11769 cp/semantics.c:7008
++#: c/c-parser.c:11769 cp/semantics.c:7009
+ #, gcc-internal-format
+ msgid "%<tile%> value must be integral"
+ msgstr ""
+ 
+-#: c/c-parser.c:11782 cp/semantics.c:7022
++#: c/c-parser.c:11782 cp/semantics.c:7023
+ #, gcc-internal-format
+ msgid "%<tile%> value must be positive"
+ msgstr ""
+ 
+-#: c/c-parser.c:11848 cp/parser.c:31098
++#: c/c-parser.c:11848 cp/parser.c:31113
+ #, gcc-internal-format
+ msgid "ordered argument needs positive constant integer expression"
+ msgstr ""
+@@ -33708,22 +33782,22 @@
+ "or %<max%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:12048 cp/parser.c:31311
++#: c/c-parser.c:12048 cp/parser.c:31326
+ #, gcc-internal-format
+ msgid "both %<monotonic%> and %<nonmonotonic%> modifiers specified"
+ msgstr ""
+ 
+-#: c/c-parser.c:12101 cp/parser.c:31327
++#: c/c-parser.c:12101 cp/parser.c:31342
+ #, gcc-internal-format
+ msgid "schedule %<runtime%> does not take a %<chunk_size%> parameter"
+ msgstr ""
+ 
+-#: c/c-parser.c:12105 cp/parser.c:31330
++#: c/c-parser.c:12105 cp/parser.c:31345
+ #, gcc-internal-format
+ msgid "schedule %<auto%> does not take a %<chunk_size%> parameter"
+ msgstr ""
+ 
+-#: c/c-parser.c:12127 cp/parser.c:31350
++#: c/c-parser.c:12127 cp/parser.c:31365
+ #, gcc-internal-format
+ msgid "invalid schedule kind"
+ msgstr ""
+@@ -33738,12 +33812,12 @@
+ msgid "%<num_teams%> value must be positive"
+ msgstr ""
+ 
+-#: c/c-parser.c:12333 cp/semantics.c:6393
++#: c/c-parser.c:12333 cp/semantics.c:6394
+ #, gcc-internal-format
+ msgid "%<thread_limit%> value must be positive"
+ msgstr ""
+ 
+-#: c/c-parser.c:12375 cp/semantics.c:6503
++#: c/c-parser.c:12375 cp/semantics.c:6504
+ #, gcc-internal-format
+ msgid ""
+ "%<aligned%> clause alignment expression must be positive constant integer "
+@@ -33750,7 +33824,7 @@
+ "expression"
+ msgstr ""
+ 
+-#: c/c-parser.c:12436 cp/parser.c:31608
++#: c/c-parser.c:12436 cp/parser.c:31623
+ #, gcc-internal-format
+ msgid "using parameters for %<linear%> step is not supported yet"
+ msgstr ""
+@@ -33772,17 +33846,17 @@
+ "%<simdlen%> clause expression must be positive constant integer expression"
+ msgstr ""
+ 
+-#: c/c-parser.c:12684 cp/parser.c:31844 cp/parser.c:32067
++#: c/c-parser.c:12684 cp/parser.c:31859 cp/parser.c:32082
+ #, gcc-internal-format
+ msgid "invalid depend kind"
+ msgstr ""
+ 
+-#: c/c-parser.c:12768 cp/parser.c:31917
++#: c/c-parser.c:12768 cp/parser.c:31932
+ #, gcc-internal-format
+ msgid "invalid map kind"
+ msgstr ""
+ 
+-#: c/c-parser.c:12862 cp/parser.c:32014
++#: c/c-parser.c:12862 cp/parser.c:32029
+ #, gcc-internal-format
+ msgid "invalid dist_schedule kind"
+ msgstr ""
+@@ -33792,77 +33866,77 @@
+ msgid "invalid proc_bind kind"
+ msgstr ""
+ 
+-#: c/c-parser.c:13144 cp/parser.c:32292
++#: c/c-parser.c:13144 cp/parser.c:32307
+ #, gcc-internal-format
+ msgid "expected %<#pragma acc%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:13155 c/c-parser.c:13438 cp/parser.c:32303 cp/parser.c:32619
++#: c/c-parser.c:13155 c/c-parser.c:13438 cp/parser.c:32318 cp/parser.c:32634
+ #, gcc-internal-format
+ msgid "%qs is not valid for %qs"
+ msgstr ""
+ 
+-#: c/c-parser.c:13301 cp/parser.c:32479
++#: c/c-parser.c:13301 cp/parser.c:32494
+ #, gcc-internal-format
+ msgid "%qs must be the first clause of %qs"
+ msgstr ""
+ 
+-#: c/c-parser.c:13427 cp/parser.c:32608
++#: c/c-parser.c:13427 cp/parser.c:32623
+ #, gcc-internal-format
+ msgid "expected %<#pragma omp%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:13565 cp/parser.c:35247
++#: c/c-parser.c:13565 cp/parser.c:35262
+ #, gcc-internal-format
+ msgid "no valid clauses specified in %<#pragma acc declare%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:13575 cp/parser.c:35257
++#: c/c-parser.c:13575 cp/parser.c:35272
+ #, gcc-internal-format
+ msgid "array section in %<#pragma acc declare%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:13599 cp/parser.c:35281
++#: c/c-parser.c:13599 cp/parser.c:35296
+ #, gcc-internal-format
+ msgid "%qD must be a global variable in%<#pragma acc declare link%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:13610 cp/parser.c:35292
++#: c/c-parser.c:13610 cp/parser.c:35307
+ #, gcc-internal-format
+ msgid "invalid OpenACC clause at file scope"
+ msgstr ""
+ 
+-#: c/c-parser.c:13617 cp/parser.c:35299
++#: c/c-parser.c:13617 cp/parser.c:35314
+ #, gcc-internal-format
+ msgid "invalid use of %<extern%> variable %qD in %<#pragma acc declare%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:13625 cp/parser.c:35307
++#: c/c-parser.c:13625 cp/parser.c:35322
+ #, gcc-internal-format
+ msgid "invalid use of %<global%> variable %qD in %<#pragma acc declare%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:13637 cp/parser.c:35319
++#: c/c-parser.c:13637 cp/parser.c:35334
+ #, gcc-internal-format
+ msgid "variable %qD used more than once with %<#pragma acc declare%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:13723 cp/parser.c:35402
++#: c/c-parser.c:13723 cp/parser.c:35417
+ #, gcc-internal-format
+ msgid "expected %<data%> in %<#pragma acc enter data%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:13732 cp/parser.c:35412
++#: c/c-parser.c:13732 cp/parser.c:35427
+ #, gcc-internal-format
+ msgid "invalid pragma"
+ msgstr ""
+ 
+-#: c/c-parser.c:13749 cp/parser.c:35429
++#: c/c-parser.c:13749 cp/parser.c:35444
+ #, gcc-internal-format
+ msgid "%<#pragma acc enter data%> has no data movement clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:13953 cp/parser.c:36513
++#: c/c-parser.c:13953 cp/parser.c:36528
+ #, gcc-internal-format
+ msgid "%<#pragma acc routine%> not at file scope"
+ msgstr ""
+@@ -33882,17 +33956,17 @@
+ msgid "%<#pragma acc routine%> %s"
+ msgstr ""
+ 
+-#: c/c-parser.c:14022 cp/parser.c:36726
++#: c/c-parser.c:14022 cp/parser.c:36741
+ #, gcc-internal-format
+ msgid "%<#pragma acc routine%> already applied to %D"
+ msgstr ""
+ 
+-#: c/c-parser.c:14025 cp/parser.c:36733
++#: c/c-parser.c:14025 cp/parser.c:36748
+ #, gcc-internal-format
+ msgid "%<#pragma acc routine%> must be applied before %s"
+ msgstr ""
+ 
+-#: c/c-parser.c:14062 cp/parser.c:35603
++#: c/c-parser.c:14062 cp/parser.c:35618
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma acc update%> must contain at least one %<device%> or %<host%> or "
+@@ -33899,17 +33973,17 @@
+ "%<self%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:14470 cp/parser.c:32990 cp/parser.c:33016
++#: c/c-parser.c:14470 cp/parser.c:33005 cp/parser.c:33031
+ #, gcc-internal-format
+ msgid "invalid form of %<#pragma omp atomic%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:14474 cp/parser.c:33047 cp/parser.c:33063
++#: c/c-parser.c:14474 cp/parser.c:33062 cp/parser.c:33078
+ #, gcc-internal-format
+ msgid "invalid operator for %<#pragma omp atomic%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:14523 cp/semantics.c:8409 cp/semantics.c:8419
++#: c/c-parser.c:14523 cp/semantics.c:8410 cp/semantics.c:8420
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp atomic capture%> uses two different expressions for memory"
+@@ -33920,12 +33994,12 @@
+ msgid "expected %<(%> or end of line"
+ msgstr ""
+ 
+-#: c/c-parser.c:14648 cp/parser.c:33561
++#: c/c-parser.c:14648 cp/parser.c:33576
+ #, gcc-internal-format
+ msgid "%<ordered%> clause parameter is less than %<collapse%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:14659 cp/parser.c:33572
++#: c/c-parser.c:14659 cp/parser.c:33587
+ #, gcc-internal-format
+ msgid ""
+ "%<linear%> clause may not be specified together with %<ordered%> clause with "
+@@ -33932,17 +34006,17 @@
+ "a parameter"
+ msgstr ""
+ 
+-#: c/c-parser.c:14678 cp/parser.c:33599 cp/parser.c:37795
++#: c/c-parser.c:14678 cp/parser.c:33614 cp/parser.c:37810
+ #, gcc-internal-format
+ msgid "for statement expected"
+ msgstr ""
+ 
+-#: c/c-parser.c:14684 cp/parser.c:33605
++#: c/c-parser.c:14684 cp/parser.c:33620
+ #, gcc-internal-format
+ msgid "_Cilk_for statement expected"
+ msgstr ""
+ 
+-#: c/c-parser.c:14753 cp/semantics.c:7959 cp/semantics.c:8046
++#: c/c-parser.c:14753 cp/semantics.c:7960 cp/semantics.c:8047
+ #, gcc-internal-format
+ msgid "expected iteration declaration or initialization"
+ msgstr ""
+@@ -33952,17 +34026,17 @@
+ msgid "not enough perfectly nested loops"
+ msgstr ""
+ 
+-#: c/c-parser.c:14897 cp/parser.c:33832
++#: c/c-parser.c:14897 cp/parser.c:33847
+ #, gcc-internal-format
+ msgid "collapsed loops not perfectly nested"
+ msgstr ""
+ 
+-#: c/c-parser.c:14944 cp/parser.c:33648 cp/parser.c:33690 cp/pt.c:15026
++#: c/c-parser.c:14944 cp/parser.c:33663 cp/parser.c:33705 cp/pt.c:15026
+ #, gcc-internal-format
+ msgid "iteration variable %qD should not be firstprivate"
+ msgstr ""
+ 
+-#: c/c-parser.c:15035 cp/parser.c:33899
++#: c/c-parser.c:15035 cp/parser.c:33914
+ #, gcc-internal-format
+ msgid "%<ordered%> clause with parameter may not be specified on %qs construct"
+ msgstr ""
+@@ -33974,17 +34048,17 @@
+ "statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:15399 cp/parser.c:34257
++#: c/c-parser.c:15399 cp/parser.c:34272
+ #, gcc-internal-format
+ msgid "expected %<for%> after %qs"
+ msgstr ""
+ 
+-#: c/c-parser.c:15598 cp/parser.c:34452
++#: c/c-parser.c:15598 cp/parser.c:34467
+ #, gcc-internal-format
+ msgid "expected %<point%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:15806 cp/parser.c:34675
++#: c/c-parser.c:15806 cp/parser.c:34690
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target data%> with map-type other than %<to%>, %<from%>, "
+@@ -33991,17 +34065,17 @@
+ "%<tofrom%> or %<alloc%> on %<map%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:15819 cp/parser.c:34688
++#: c/c-parser.c:15819 cp/parser.c:34703
+ #, gcc-internal-format
+ msgid "%<#pragma omp target data%> must contain at least one %<map%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:15854 cp/parser.c:34900
++#: c/c-parser.c:15854 cp/parser.c:34915
+ #, gcc-internal-format
+ msgid "%<#pragma omp target update%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:15867 cp/parser.c:34913
++#: c/c-parser.c:15867 cp/parser.c:34928
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target update%> must contain at least one %<from%> or %<to%> "
+@@ -34008,13 +34082,13 @@
+ "clauses"
+ msgstr ""
+ 
+-#: c/c-parser.c:15914 cp/parser.c:34741
++#: c/c-parser.c:15914 cp/parser.c:34756
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target enter data%> may only be used in compound statements"
+ msgstr ""
+ 
+-#: c/c-parser.c:15940 cp/parser.c:34768
++#: c/c-parser.c:15940 cp/parser.c:34783
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target enter data%> with map-type other than %<to%> or %<alloc"
+@@ -34021,13 +34095,13 @@
+ "%> on %<map%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:15952 cp/parser.c:34780
++#: c/c-parser.c:15952 cp/parser.c:34795
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target enter data%> must contain at least one %<map%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:15999 cp/parser.c:34829
++#: c/c-parser.c:15999 cp/parser.c:34844
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target exit data%> may only be used in compound statements"
+@@ -34040,13 +34114,13 @@
+ "%<release> or %<delete%> on %<map%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:16040 cp/parser.c:34870
++#: c/c-parser.c:16040 cp/parser.c:34885
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target exit data%> must contain at least one %<map%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:16249 cp/parser.c:35124
++#: c/c-parser.c:16249 cp/parser.c:35139
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target%> with map-type other than %<to%>, %<from%>, %<tofrom%> "
+@@ -34081,7 +34155,7 @@
+ "declaration or definition"
+ msgstr ""
+ 
+-#: c/c-parser.c:16422 cp/parser.c:35779
++#: c/c-parser.c:16422 cp/parser.c:35794
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp declare simd%> not immediately followed by a single function "
+@@ -34088,7 +34162,7 @@
+ "declaration or definition"
+ msgstr ""
+ 
+-#: c/c-parser.c:16538 cp/parser.c:35850
++#: c/c-parser.c:16538 cp/parser.c:35865
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp declare target%> with clauses in between %<#pragma omp declare "
+@@ -34095,22 +34169,22 @@
+ "target%> without clauses and %<#pragma omp end declare target%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:16557 cp/parser.c:35869
++#: c/c-parser.c:16557 cp/parser.c:35884
+ #, gcc-internal-format
+ msgid "%qD specified both in declare target %<link%> and %<to%> clauses"
+ msgstr ""
+ 
+-#: c/c-parser.c:16595 cp/parser.c:35913
++#: c/c-parser.c:16595 cp/parser.c:35928
+ #, gcc-internal-format
+ msgid "expected %<target%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:16602 cp/parser.c:35920
++#: c/c-parser.c:16602 cp/parser.c:35935
+ #, gcc-internal-format
+ msgid "expected %<declare%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:16608 cp/parser.c:35927
++#: c/c-parser.c:16608 cp/parser.c:35942
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp end declare target%> without corresponding %<#pragma omp "
+@@ -34171,22 +34245,22 @@
+ msgid "one of the initializer call arguments should be %<&omp_priv%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:17004 cp/parser.c:36372
++#: c/c-parser.c:17004 cp/parser.c:36387
+ #, gcc-internal-format
+ msgid "expected %<simd%> or %<reduction%> or %<target%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:17219 cp/semantics.c:7432
++#: c/c-parser.c:17219 cp/semantics.c:7433
+ #, gcc-internal-format
+ msgid "%qE declared %<threadprivate%> after first use"
+ msgstr ""
+ 
+-#: c/c-parser.c:17221 cp/semantics.c:7434
++#: c/c-parser.c:17221 cp/semantics.c:7435
+ #, gcc-internal-format
+ msgid "automatic variable %qE cannot be %<threadprivate%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:17225 cp/semantics.c:7436
++#: c/c-parser.c:17225 cp/semantics.c:7437
+ #, gcc-internal-format
+ msgid "%<threadprivate%> %qE has incomplete type"
+ msgstr ""
+@@ -34201,53 +34275,53 @@
+ msgid "pragma simd must be inside a function"
+ msgstr ""
+ 
+-#: c/c-parser.c:17306 cp/parser.c:37566
++#: c/c-parser.c:17306 cp/parser.c:37581
+ #, gcc-internal-format
+ msgid "vectorlength must be an integer constant"
+ msgstr ""
+ 
+-#: c/c-parser.c:17308 cp/parser.c:37569
++#: c/c-parser.c:17308 cp/parser.c:37584
+ #, gcc-internal-format
+ msgid "vectorlength must be a power of 2"
+ msgstr ""
+ 
+-#: c/c-parser.c:17391 cp/parser.c:37676
++#: c/c-parser.c:17391 cp/parser.c:37691
+ #, gcc-internal-format
+ msgid "step size must be an integer constant expression or an integer variable"
+ msgstr ""
+ 
+-#: c/c-parser.c:17490 cp/parser.c:37769
++#: c/c-parser.c:17490 cp/parser.c:37784
+ #, gcc-internal-format
+ msgid "expected %<#pragma simd%> clause"
+ msgstr ""
+ 
+-#: c/c-parser.c:17534 cp/parser.c:37218
++#: c/c-parser.c:17534 cp/parser.c:37233
+ #, gcc-internal-format
+ msgid "%<#pragma cilk grainsize%> is not followed by %<_Cilk_for%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:17834 cp/parser.c:37110
++#: c/c-parser.c:17834 cp/parser.c:37125
+ #, gcc-internal-format
+ msgid "%<__transaction_cancel%> without transactional memory support enabled"
+ msgstr ""
+ 
+-#: c/c-parser.c:17840 cp/parser.c:37116
++#: c/c-parser.c:17840 cp/parser.c:37131
+ #, gcc-internal-format
+ msgid "%<__transaction_cancel%> within a %<__transaction_relaxed%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:17849 cp/parser.c:37125
++#: c/c-parser.c:17849 cp/parser.c:37140
+ #, gcc-internal-format
+ msgid ""
+ "outer %<__transaction_cancel%> not within outer %<__transaction_atomic%>"
+ msgstr ""
+ 
+-#: c/c-parser.c:17851 cp/parser.c:37128
++#: c/c-parser.c:17851 cp/parser.c:37143
+ #, gcc-internal-format
+ msgid "  or a %<transaction_may_cancel_outer%> function"
+ msgstr ""
+ 
+-#: c/c-parser.c:17857 cp/parser.c:37134
++#: c/c-parser.c:17857 cp/parser.c:37149
+ #, gcc-internal-format
+ msgid "%<__transaction_cancel%> not within %<__transaction_atomic%>"
+ msgstr ""
+@@ -34257,7 +34331,7 @@
+ msgid "base of array section must be pointer or array type"
+ msgstr ""
+ 
+-#: c/c-parser.c:17934 cp/parser.c:7013
++#: c/c-parser.c:17934 cp/parser.c:7023
+ #, gcc-internal-format
+ msgid "expected %<:%> or numeral"
+ msgstr ""
+@@ -34297,7 +34371,7 @@
+ msgid "%qD has an incomplete type %qT"
+ msgstr ""
+ 
+-#: c/c-typeck.c:231 c/c-typeck.c:9508 c/c-typeck.c:9550 cp/call.c:3976
++#: c/c-typeck.c:231 c/c-typeck.c:9518 c/c-typeck.c:9560 cp/call.c:3976
+ #, gcc-internal-format
+ msgid "invalid use of void expression"
+ msgstr ""
+@@ -34725,7 +34799,7 @@
+ msgid "left-hand operand of comma expression has no effect"
+ msgstr ""
+ 
+-#: c/c-typeck.c:5116 c/c-typeck.c:10199
++#: c/c-typeck.c:5116 c/c-typeck.c:10209
+ #, gcc-internal-format
+ msgid "right-hand operand of comma expression has no effect"
+ msgstr ""
+@@ -34827,17 +34901,17 @@
+ msgid "assignment to expression with array type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:5678 c/c-typeck.c:6118
++#: c/c-typeck.c:5678 c/c-typeck.c:6128
+ #, gcc-internal-format
+ msgid "enum conversion in assignment is invalid in C++"
+ msgstr ""
+ 
+-#: c/c-typeck.c:5870 c/c-typeck.c:5888 c/c-typeck.c:5907
++#: c/c-typeck.c:5870 c/c-typeck.c:5893 c/c-typeck.c:5917
+ #, gcc-internal-format
+ msgid "(near initialization for %qs)"
+ msgstr ""
+ 
+-#: c/c-typeck.c:5922
++#: c/c-typeck.c:5932
+ #, gcc-internal-format
+ msgid "array initialized from parenthesized string constant"
+ msgstr ""
+@@ -34853,118 +34927,118 @@
+ #. strings are complete sentences, visible to gettext and checked at
+ #. compile time.  It is the same as PEDWARN_FOR_QUALIFIERS but uses
+ #. warning_at instead of pedwarn.
+-#: c/c-typeck.c:5998 c/c-typeck.c:6027 c/c-typeck.c:6056 c/c-typeck.c:6634
++#: c/c-typeck.c:6008 c/c-typeck.c:6037 c/c-typeck.c:6066 c/c-typeck.c:6644
+ #, gcc-internal-format
+ msgid "expected %qT but argument is of type %qT"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6116
++#: c/c-typeck.c:6126
+ #, gcc-internal-format
+ msgid "enum conversion when passing argument %d of %qE is invalid in C++"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6120 c/c-typeck.c:8718
++#: c/c-typeck.c:6130 c/c-typeck.c:8728
+ #, gcc-internal-format
+ msgid "enum conversion in initialization is invalid in C++"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6122
++#: c/c-typeck.c:6132
+ #, gcc-internal-format
+ msgid "enum conversion in return is invalid in C++"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6153
++#: c/c-typeck.c:6163
+ #, gcc-internal-format
+ msgid "cannot pass rvalue to reference parameter"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6286 c/c-typeck.c:6551
++#: c/c-typeck.c:6296 c/c-typeck.c:6561
+ msgid ""
+ "passing argument %d of %qE makes %q#v qualified function pointer from "
+ "unqualified"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6289 c/c-typeck.c:6554
++#: c/c-typeck.c:6299 c/c-typeck.c:6564
+ msgid "assignment makes %q#v qualified function pointer from unqualified"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6292 c/c-typeck.c:6556
++#: c/c-typeck.c:6302 c/c-typeck.c:6566
+ msgid "initialization makes %q#v qualified function pointer from unqualified"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6295 c/c-typeck.c:6558
++#: c/c-typeck.c:6305 c/c-typeck.c:6568
+ msgid "return makes %q#v qualified function pointer from unqualified"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6303 c/c-typeck.c:6470 c/c-typeck.c:6513
++#: c/c-typeck.c:6313 c/c-typeck.c:6480 c/c-typeck.c:6523
+ msgid ""
+ "passing argument %d of %qE discards %qv qualifier from pointer target type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6305 c/c-typeck.c:6472 c/c-typeck.c:6515
++#: c/c-typeck.c:6315 c/c-typeck.c:6482 c/c-typeck.c:6525
+ msgid "assignment discards %qv qualifier from pointer target type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6307 c/c-typeck.c:6474 c/c-typeck.c:6517
++#: c/c-typeck.c:6317 c/c-typeck.c:6484 c/c-typeck.c:6527
+ msgid "initialization discards %qv qualifier from pointer target type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6309 c/c-typeck.c:6476 c/c-typeck.c:6519
++#: c/c-typeck.c:6319 c/c-typeck.c:6486 c/c-typeck.c:6529
+ msgid "return discards %qv qualifier from pointer target type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6318
++#: c/c-typeck.c:6328
+ #, gcc-internal-format
+ msgid "ISO C prohibits argument conversion to union type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6380
++#: c/c-typeck.c:6390
+ #, gcc-internal-format
+ msgid "request for implicit conversion from %qT to %qT not permitted in C++"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6392
++#: c/c-typeck.c:6402
+ #, gcc-internal-format
+ msgid "passing argument %d of %qE from pointer to non-enclosed address space"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6396
++#: c/c-typeck.c:6406
+ #, gcc-internal-format
+ msgid "assignment from pointer to non-enclosed address space"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6400
++#: c/c-typeck.c:6410
+ #, gcc-internal-format
+ msgid "initialization from pointer to non-enclosed address space"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6404
++#: c/c-typeck.c:6414
+ #, gcc-internal-format
+ msgid "return from pointer to non-enclosed address space"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6422
++#: c/c-typeck.c:6432
+ #, gcc-internal-format
+ msgid "argument %d of %qE might be a candidate for a format attribute"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6428
++#: c/c-typeck.c:6438
+ #, gcc-internal-format
+ msgid "assignment left-hand side might be a candidate for a format attribute"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6433
++#: c/c-typeck.c:6443
+ #, gcc-internal-format
+ msgid ""
+ "initialization left-hand side might be a candidate for a format attribute"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6438 cp/typeck.c:8422
++#: c/c-typeck.c:6448 cp/typeck.c:8422
+ #, gcc-internal-format
+ msgid "return type might be a candidate for a format attribute"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6487
++#: c/c-typeck.c:6497
+ #, gcc-internal-format
+ msgid ""
+ "ISO C forbids passing argument %d of %qE between function pointer and %<void "
+@@ -34971,57 +35045,57 @@
+ "*%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6490
++#: c/c-typeck.c:6500
+ #, gcc-internal-format
+ msgid "ISO C forbids assignment between function pointer and %<void *%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6492
++#: c/c-typeck.c:6502
+ #, gcc-internal-format
+ msgid "ISO C forbids initialization between function pointer and %<void *%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6494
++#: c/c-typeck.c:6504
+ #, gcc-internal-format
+ msgid "ISO C forbids return between function pointer and %<void *%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6531
++#: c/c-typeck.c:6541
+ #, gcc-internal-format
+ msgid "pointer targets in passing argument %d of %qE differ in signedness"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6533
++#: c/c-typeck.c:6543
+ #, gcc-internal-format
+ msgid "pointer targets in assignment differ in signedness"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6535
++#: c/c-typeck.c:6545
+ #, gcc-internal-format
+ msgid "pointer targets in initialization differ in signedness"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6537
++#: c/c-typeck.c:6547
+ #, gcc-internal-format
+ msgid "pointer targets in return differ in signedness"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6568
++#: c/c-typeck.c:6578
+ #, gcc-internal-format
+ msgid "passing argument %d of %qE from incompatible pointer type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6570
++#: c/c-typeck.c:6580
+ #, gcc-internal-format
+ msgid "assignment from incompatible pointer type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6571
++#: c/c-typeck.c:6581
+ #, gcc-internal-format
+ msgid "initialization from incompatible pointer type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6573
++#: c/c-typeck.c:6583
+ #, gcc-internal-format
+ msgid "return from incompatible pointer type"
+ msgstr ""
+@@ -35028,228 +35102,228 @@
+ 
+ #. ??? This should not be an error when inlining calls to
+ #. unprototyped functions.
+-#: c/c-typeck.c:6581 c/c-typeck.c:7075 cp/typeck.c:1992
++#: c/c-typeck.c:6591 c/c-typeck.c:7085 cp/typeck.c:1992
+ #, gcc-internal-format
+ msgid "invalid use of non-lvalue array"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6592
++#: c/c-typeck.c:6602
+ #, gcc-internal-format
+ msgid "passing argument %d of %qE makes pointer from integer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6594
++#: c/c-typeck.c:6604
+ #, gcc-internal-format
+ msgid "assignment makes pointer from integer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6596
++#: c/c-typeck.c:6606
+ #, gcc-internal-format
+ msgid "initialization makes pointer from integer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6598
++#: c/c-typeck.c:6608
+ #, gcc-internal-format
+ msgid "return makes pointer from integer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6607
++#: c/c-typeck.c:6617
+ #, gcc-internal-format
+ msgid "passing argument %d of %qE makes integer from pointer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6609
++#: c/c-typeck.c:6619
+ #, gcc-internal-format
+ msgid "assignment makes integer from pointer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6611
++#: c/c-typeck.c:6621
+ #, gcc-internal-format
+ msgid "initialization makes integer from pointer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6613
++#: c/c-typeck.c:6623
+ #, gcc-internal-format
+ msgid "return makes integer from pointer without a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6637
++#: c/c-typeck.c:6647
+ #, gcc-internal-format
+ msgid "incompatible types when assigning to type %qT from type %qT"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6642
++#: c/c-typeck.c:6652
+ #, gcc-internal-format
+ msgid "incompatible types when initializing type %qT using type %qT"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6647
++#: c/c-typeck.c:6657
+ #, gcc-internal-format
+ msgid "incompatible types when returning type %qT but %qT was expected"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6711
++#: c/c-typeck.c:6721
+ #, gcc-internal-format
+ msgid "traditional C rejects automatic aggregate initialization"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6948 c/c-typeck.c:7827 cp/typeck2.c:1023
++#: c/c-typeck.c:6958 c/c-typeck.c:7837 cp/typeck2.c:1023
+ #, gcc-internal-format
+ msgid "initialization of a flexible array member"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6958 cp/typeck2.c:1038
++#: c/c-typeck.c:6968 cp/typeck2.c:1038
+ #, gcc-internal-format
+ msgid "char-array initialized from wide string"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6967
++#: c/c-typeck.c:6977
+ #, gcc-internal-format
+ msgid "wide character array initialized from non-wide string"
+ msgstr ""
+ 
+-#: c/c-typeck.c:6973
++#: c/c-typeck.c:6983
+ #, gcc-internal-format
+ msgid "wide character array initialized from incompatible wide string"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7007
++#: c/c-typeck.c:7017
+ #, gcc-internal-format
+ msgid "array of inappropriate type initialized from string constant"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7094 c/c-typeck.c:7118 c/c-typeck.c:7121 c/c-typeck.c:7129
+-#: c/c-typeck.c:7169 c/c-typeck.c:8657 c/c-typeck.c:8691
++#: c/c-typeck.c:7104 c/c-typeck.c:7128 c/c-typeck.c:7131 c/c-typeck.c:7139
++#: c/c-typeck.c:7179 c/c-typeck.c:8667 c/c-typeck.c:8701
+ #, gcc-internal-format
+ msgid "initializer element is not constant"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7103
++#: c/c-typeck.c:7113
+ #, gcc-internal-format
+ msgid "array initialized from non-constant array expression"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7134 c/c-typeck.c:7182 c/c-typeck.c:8701
++#: c/c-typeck.c:7144 c/c-typeck.c:7192 c/c-typeck.c:8711
+ #, gcc-internal-format
+ msgid "initializer element is not a constant expression"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7176 c/c-typeck.c:8696
++#: c/c-typeck.c:7186 c/c-typeck.c:8706
+ #, gcc-internal-format
+ msgid "initializer element is not computable at load time"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7195
++#: c/c-typeck.c:7205
+ #, gcc-internal-format
+ msgid "invalid initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7470 cp/decl.c:6115
++#: c/c-typeck.c:7480 cp/decl.c:6115
+ #, gcc-internal-format
+ msgid "opaque vector types cannot be initialized"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7686
++#: c/c-typeck.c:7696
+ #, gcc-internal-format
+ msgid "extra brace group at end of initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7764
++#: c/c-typeck.c:7774
+ #, gcc-internal-format
+ msgid "braces around scalar initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7824 c/c-typeck.c:9130
++#: c/c-typeck.c:7834 c/c-typeck.c:9140
+ #, gcc-internal-format
+ msgid "initialization of flexible array member in a nested context"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7858
++#: c/c-typeck.c:7868
+ #, gcc-internal-format
+ msgid "missing braces around initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7880
++#: c/c-typeck.c:7890
+ #, gcc-internal-format
+ msgid "missing initializer for field %qD of %qT"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7904
++#: c/c-typeck.c:7914
+ #, gcc-internal-format
+ msgid "empty scalar initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:7909
++#: c/c-typeck.c:7919
+ #, gcc-internal-format
+ msgid "extra elements in scalar initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8021 c/c-typeck.c:8103
++#: c/c-typeck.c:8031 c/c-typeck.c:8113
+ #, gcc-internal-format
+ msgid "array index in non-array initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8026 c/c-typeck.c:8165
++#: c/c-typeck.c:8036 c/c-typeck.c:8175
+ #, gcc-internal-format
+ msgid "field name not in record or union initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8076
++#: c/c-typeck.c:8086
+ #, gcc-internal-format
+ msgid "array index in initializer not of integer type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8085 c/c-typeck.c:8094
++#: c/c-typeck.c:8095 c/c-typeck.c:8104
+ #, gcc-internal-format
+ msgid "array index in initializer is not an integer constant expression"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8099 c/c-typeck.c:8101
++#: c/c-typeck.c:8109 c/c-typeck.c:8111
+ #, gcc-internal-format
+ msgid "nonconstant array index in initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8105 c/c-typeck.c:8108
++#: c/c-typeck.c:8115 c/c-typeck.c:8118
+ #, gcc-internal-format
+ msgid "array index in initializer exceeds array bounds"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8127
++#: c/c-typeck.c:8137
+ #, gcc-internal-format
+ msgid "empty index range in initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8136
++#: c/c-typeck.c:8146
+ #, gcc-internal-format
+ msgid "array index range in initializer exceeds array bounds"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8172
++#: c/c-typeck.c:8182
+ #, gcc-internal-format
+ msgid "unknown field %qE specified in initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8225 c/c-typeck.c:8255 c/c-typeck.c:8791
++#: c/c-typeck.c:8235 c/c-typeck.c:8265 c/c-typeck.c:8801
+ #, gcc-internal-format
+ msgid "initialized field with side-effects overwritten"
+ msgstr ""
+ 
+-#: c/c-typeck.c:8229 c/c-typeck.c:8259 c/c-typeck.c:8794
++#: c/c-typeck.c:8239 c/c-typeck.c:8269 c/c-typeck.c:8804
+ #, gcc-internal-format
+ msgid "initialized field overwritten"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9013
++#: c/c-typeck.c:9023
+ #, gcc-internal-format
+ msgid "excess elements in char array initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9020 c/c-typeck.c:9089
++#: c/c-typeck.c:9030 c/c-typeck.c:9099
+ #, gcc-internal-format
+ msgid "excess elements in struct initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9035
++#: c/c-typeck.c:9045
+ #, gcc-internal-format
+ msgid ""
+ "positional initialization of field in %<struct%> declared with "
+@@ -35256,162 +35330,162 @@
+ "%<designated_init%> attribute"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9104
++#: c/c-typeck.c:9114
+ #, gcc-internal-format
+ msgid "non-static initialization of a flexible array member"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9203
++#: c/c-typeck.c:9213
+ #, gcc-internal-format
+ msgid "excess elements in union initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9225
++#: c/c-typeck.c:9235
+ #, gcc-internal-format
+ msgid "traditional C rejects initialization of unions"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9293
++#: c/c-typeck.c:9303
+ #, gcc-internal-format
+ msgid "excess elements in array initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9327
++#: c/c-typeck.c:9337
+ #, gcc-internal-format
+ msgid "excess elements in vector initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9359
++#: c/c-typeck.c:9369
+ #, gcc-internal-format
+ msgid "excess elements in scalar initializer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9599
++#: c/c-typeck.c:9609
+ #, gcc-internal-format
+ msgid "ISO C forbids %<goto *expr;%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9627 cp/typeck.c:8651
++#: c/c-typeck.c:9637 cp/typeck.c:8652
+ #, gcc-internal-format
+ msgid "function declared %<noreturn%> has a %<return%> statement"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9637 cp/cp-array-notation.c:1087
++#: c/c-typeck.c:9647 cp/cp-array-notation.c:1087
+ #, gcc-internal-format
+ msgid "array notation expression cannot be used as a return value"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9644 cp/typeck.c:8642
++#: c/c-typeck.c:9654 cp/typeck.c:8643
+ #, gcc-internal-format
+ msgid "use of %<_Cilk_spawn%> in a return statement is not allowed"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9672 c/c-typeck.c:9676
++#: c/c-typeck.c:9682 c/c-typeck.c:9686
+ #, gcc-internal-format
+ msgid "%<return%> with no value, in function returning non-void"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9690
++#: c/c-typeck.c:9700
+ #, gcc-internal-format
+ msgid "%<return%> with a value, in function returning void"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9693
++#: c/c-typeck.c:9703
+ #, gcc-internal-format
+ msgid "ISO C forbids %<return%> with expression, in function returning void"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9769
++#: c/c-typeck.c:9779
+ #, gcc-internal-format
+ msgid "function returns address of label"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9860 cp/semantics.c:1146
++#: c/c-typeck.c:9870 cp/semantics.c:1146
+ #, gcc-internal-format
+ msgid "switch quantity not an integer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9885
++#: c/c-typeck.c:9895
+ #, gcc-internal-format
+ msgid "%<long%> switch expression not converted to %<int%> in ISO C"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9923 c/c-typeck.c:9931
++#: c/c-typeck.c:9933 c/c-typeck.c:9941
+ #, gcc-internal-format
+ msgid "case label is not an integer constant expression"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9937 cp/parser.c:10626
++#: c/c-typeck.c:9947 cp/parser.c:10636
+ #, gcc-internal-format
+ msgid "case label not within a switch statement"
+ msgstr ""
+ 
+-#: c/c-typeck.c:9939
++#: c/c-typeck.c:9949
+ #, gcc-internal-format
+ msgid "%<default%> label not within a switch statement"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10010
++#: c/c-typeck.c:10020
+ #, gcc-internal-format
+ msgid "rank-mismatch between if-statement%'s condition and the then-block"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10016
++#: c/c-typeck.c:10026
+ #, gcc-internal-format
+ msgid "rank-mismatch between if-statement%'s condition and the else-block"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10141 cp/parser.c:11756
++#: c/c-typeck.c:10151 cp/parser.c:11766
+ #, gcc-internal-format
+ msgid "break statement not within loop or switch"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10143 cp/parser.c:11782
++#: c/c-typeck.c:10153 cp/parser.c:11792
+ #, gcc-internal-format
+ msgid "continue statement not within a loop"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10148 cp/parser.c:11769
++#: c/c-typeck.c:10158 cp/parser.c:11779
+ #, gcc-internal-format
+ msgid "break statement used with OpenMP for loop"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10153
++#: c/c-typeck.c:10163
+ #, gcc-internal-format
+ msgid "break statement within %<#pragma simd%> loop body"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10155 cp/parser.c:11786
++#: c/c-typeck.c:10165 cp/parser.c:11796
+ #, gcc-internal-format
+ msgid "continue statement within %<#pragma simd%> loop body"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10181 cp/cp-gimplify.c:444
++#: c/c-typeck.c:10191 cp/cp-gimplify.c:444
+ #, gcc-internal-format
+ msgid "statement with no effect"
+ msgstr ""
+ 
+-#: c/c-typeck.c:10225
++#: c/c-typeck.c:10235
+ #, gcc-internal-format
+ msgid "expression statement has incomplete type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11026 c/c-typeck.c:11183 cp/typeck.c:4790
++#: c/c-typeck.c:11036 c/c-typeck.c:11193 cp/typeck.c:4790
+ #, gcc-internal-format
+ msgid "comparing vectors with different element types"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11033 c/c-typeck.c:11190 cp/typeck.c:4802
++#: c/c-typeck.c:11043 c/c-typeck.c:11200 cp/typeck.c:4802
+ #, gcc-internal-format
+ msgid "comparing vectors with different number of elements"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11064 cp/typeck.c:4528
++#: c/c-typeck.c:11074 cp/typeck.c:4528
+ #, gcc-internal-format
+ msgid "comparing floating point with == or != is unsafe"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11081 c/c-typeck.c:11101
++#: c/c-typeck.c:11091 c/c-typeck.c:11111
+ #, gcc-internal-format
+ msgid ""
+ "the comparison will always evaluate as %<false%> for the address of %qD will "
+@@ -35418,7 +35492,7 @@
+ "never be NULL"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11087 c/c-typeck.c:11107
++#: c/c-typeck.c:11097 c/c-typeck.c:11117
+ #, gcc-internal-format
+ msgid ""
+ "the comparison will always evaluate as %<true%> for the address of %qD will "
+@@ -35425,48 +35499,48 @@
+ "never be NULL"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11128 c/c-typeck.c:11248
++#: c/c-typeck.c:11138 c/c-typeck.c:11258
+ #, gcc-internal-format
+ msgid "comparison of pointers to disjoint address spaces"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11135 c/c-typeck.c:11141
++#: c/c-typeck.c:11145 c/c-typeck.c:11151
+ #, gcc-internal-format
+ msgid "ISO C forbids comparison of %<void *%> with function pointer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11148 c/c-typeck.c:11258
++#: c/c-typeck.c:11158 c/c-typeck.c:11268
+ #, gcc-internal-format
+ msgid "comparison of distinct pointer types lacks a cast"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11160 c/c-typeck.c:11165 c/c-typeck.c:11284 c/c-typeck.c:11289
++#: c/c-typeck.c:11170 c/c-typeck.c:11175 c/c-typeck.c:11294 c/c-typeck.c:11299
+ #, gcc-internal-format
+ msgid "comparison between pointer and integer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11236
++#: c/c-typeck.c:11246
+ #, gcc-internal-format
+ msgid "comparison of complete and incomplete pointers"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11238
++#: c/c-typeck.c:11248
+ #, gcc-internal-format
+ msgid "ISO C forbids ordered comparisons of pointers to functions"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11243
++#: c/c-typeck.c:11253
+ #, gcc-internal-format
+ msgid "ordered comparison of pointer with null pointer"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11266 c/c-typeck.c:11269 c/c-typeck.c:11276 c/c-typeck.c:11279
++#: c/c-typeck.c:11276 c/c-typeck.c:11279 c/c-typeck.c:11286 c/c-typeck.c:11289
+ #: cp/typeck.c:4853 cp/typeck.c:4860
+ #, gcc-internal-format
+ msgid "ordered comparison of pointer with integer zero"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11330 cp/typeck.c:4939
++#: c/c-typeck.c:11340 cp/typeck.c:4939
+ #, gcc-internal-format
+ msgid ""
+ "implicit conversion from %qT to %qT to match other operand of binary "
+@@ -35473,27 +35547,27 @@
+ "expression"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11643
++#: c/c-typeck.c:11653
+ #, gcc-internal-format
+ msgid "used array that cannot be converted to pointer where scalar is required"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11647
++#: c/c-typeck.c:11657
+ #, gcc-internal-format
+ msgid "used struct type value where scalar is required"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11651
++#: c/c-typeck.c:11661
+ #, gcc-internal-format
+ msgid "used union type value where scalar is required"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11667
++#: c/c-typeck.c:11677
+ #, gcc-internal-format
+ msgid "used vector type where scalar is required"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11857 cp/semantics.c:8516
++#: c/c-typeck.c:11867 cp/semantics.c:8517
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp cancel must specify one of %<parallel%>, %<for%>, %<sections%> "
+@@ -35500,7 +35574,7 @@
+ "or %<taskgroup%> clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11896 cp/semantics.c:8553
++#: c/c-typeck.c:11906 cp/semantics.c:8554
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp cancellation point must specify one of %<parallel%>, %<for%>, "
+@@ -35507,129 +35581,129 @@
+ "%<sections%> or %<taskgroup%> clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11946 c/c-typeck.c:13052 cp/semantics.c:4507
+-#: cp/semantics.c:6628
++#: c/c-typeck.c:11956 c/c-typeck.c:13062 cp/semantics.c:4508
++#: cp/semantics.c:6629
+ #, gcc-internal-format
+ msgid "bit-field %qE in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11955 c/c-typeck.c:13069 cp/semantics.c:4517
+-#: cp/semantics.c:6646
++#: c/c-typeck.c:11965 c/c-typeck.c:13079 cp/semantics.c:4518
++#: cp/semantics.c:6647
+ #, gcc-internal-format
+ msgid "%qE is a member of a union"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11965 cp/semantics.c:4531 cp/semantics.c:6671
++#: c/c-typeck.c:11975 cp/semantics.c:4532 cp/semantics.c:6672
+ #, gcc-internal-format
+ msgid "%qD is not a variable in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11969 c/c-typeck.c:13086 cp/semantics.c:4535
+-#: cp/semantics.c:6674
++#: c/c-typeck.c:11979 c/c-typeck.c:13096 cp/semantics.c:4536
++#: cp/semantics.c:6675
+ #, gcc-internal-format
+ msgid "%qE is not a variable in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11977 c/c-typeck.c:13093 c/c-typeck.c:13178 cp/semantics.c:4552
+-#: cp/semantics.c:6680 cp/semantics.c:6834
++#: c/c-typeck.c:11987 c/c-typeck.c:13103 c/c-typeck.c:13188 cp/semantics.c:4553
++#: cp/semantics.c:6681 cp/semantics.c:6835
+ #, gcc-internal-format
+ msgid "%qD is threadprivate variable in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:11999 cp/semantics.c:4583
++#: c/c-typeck.c:12009 cp/semantics.c:4584
+ #, gcc-internal-format
+ msgid "low bound %qE of array section does not have integral type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12006 cp/semantics.c:4590
++#: c/c-typeck.c:12016 cp/semantics.c:4591
+ #, gcc-internal-format
+ msgid "length %qE of array section does not have integral type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12033 c/c-typeck.c:12097 c/c-typeck.c:12355 cp/semantics.c:4626
+-#: cp/semantics.c:4690
++#: c/c-typeck.c:12043 c/c-typeck.c:12107 c/c-typeck.c:12365 cp/semantics.c:4627
++#: cp/semantics.c:4691
+ #, gcc-internal-format
+ msgid "zero length array section in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12052 cp/semantics.c:4645
++#: c/c-typeck.c:12062 cp/semantics.c:4646
+ #, gcc-internal-format
+ msgid "for unknown bound array type length expression must be specified"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12060 cp/semantics.c:4653
++#: c/c-typeck.c:12070 cp/semantics.c:4654
+ #, gcc-internal-format
+ msgid "negative low bound in array section in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12069 c/c-typeck.c:12179 cp/semantics.c:4662
+-#: cp/semantics.c:4772
++#: c/c-typeck.c:12079 c/c-typeck.c:12189 cp/semantics.c:4663
++#: cp/semantics.c:4773
+ #, gcc-internal-format
+ msgid "negative length in array section in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12086 cp/semantics.c:4679
++#: c/c-typeck.c:12096 cp/semantics.c:4680
+ #, gcc-internal-format
+ msgid "low bound %qE above array section size in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12123 cp/semantics.c:4716
++#: c/c-typeck.c:12133 cp/semantics.c:4717
+ #, gcc-internal-format
+ msgid "length %qE above array section size in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12138 cp/semantics.c:4731
++#: c/c-typeck.c:12148 cp/semantics.c:4732
+ #, gcc-internal-format
+ msgid "high bound %qE above array section size in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12171 cp/semantics.c:4764
++#: c/c-typeck.c:12181 cp/semantics.c:4765
+ #, gcc-internal-format
+ msgid "for pointer type length expression must be specified"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12189 c/c-typeck.c:12298 cp/semantics.c:4782
+-#: cp/semantics.c:4894
++#: c/c-typeck.c:12199 c/c-typeck.c:12308 cp/semantics.c:4783
++#: cp/semantics.c:4895
+ #, gcc-internal-format
+ msgid "array section is not contiguous in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12197 cp/semantics.c:4790
++#: c/c-typeck.c:12207 cp/semantics.c:4791
+ #, gcc-internal-format
+ msgid "%qE does not have pointer or array type"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12575 c/c-typeck.c:12585
++#: c/c-typeck.c:12585 c/c-typeck.c:12595
+ #, gcc-internal-format
+ msgid "%qD in %<reduction%> clause is a zero size array"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12643
++#: c/c-typeck.c:12653
+ #, gcc-internal-format
+ msgid "%qE has invalid type for %<reduction(%s)%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12652 cp/semantics.c:5701
++#: c/c-typeck.c:12662 cp/semantics.c:5702
+ #, gcc-internal-format
+ msgid "user defined reduction not found for %qE"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12740
++#: c/c-typeck.c:12750
+ #, gcc-internal-format
+ msgid "variable length element type in array %<reduction%> clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12758 c/c-typeck.c:13236 cp/semantics.c:7150
++#: c/c-typeck.c:12768 c/c-typeck.c:13246 cp/semantics.c:7151
+ #, gcc-internal-format
+ msgid "%<nowait%> clause must not be used together with %<copyprivate%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12770 cp/semantics.c:7190
++#: c/c-typeck.c:12780 cp/semantics.c:7191
+ #, gcc-internal-format
+ msgid "%qE must be %<threadprivate%> for %<copyin%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12784 cp/semantics.c:5863
++#: c/c-typeck.c:12794 cp/semantics.c:5864
+ #, gcc-internal-format
+ msgid ""
+ "modifier should not be specified in %<linear%> clause on %<simd%> or %<for%> "
+@@ -35636,167 +35710,167 @@
+ "constructs"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12792
++#: c/c-typeck.c:12802
+ #, gcc-internal-format
+ msgid ""
+ "linear clause applied to non-integral non-pointer variable with type %qT"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12812 cp/semantics.c:5931
++#: c/c-typeck.c:12822 cp/semantics.c:5932
+ #, gcc-internal-format
+ msgid "%<linear%> clause step %qE is neither constant nor a parameter"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12842 c/c-typeck.c:13171 cp/semantics.c:6015
+-#: cp/semantics.c:6827
++#: c/c-typeck.c:12852 c/c-typeck.c:13181 cp/semantics.c:6016
++#: cp/semantics.c:6828
+ #, gcc-internal-format
+ msgid "%qE is not a variable in clause %qs"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12851 c/c-typeck.c:12878 c/c-typeck.c:12904
++#: c/c-typeck.c:12861 c/c-typeck.c:12888 c/c-typeck.c:12914
+ #, gcc-internal-format
+ msgid "%qE appears more than once in data clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12857 c/c-typeck.c:12883 c/c-typeck.c:13127 c/c-typeck.c:13144
+-#: cp/semantics.c:6029 cp/semantics.c:6081 cp/semantics.c:6733
+-#: cp/semantics.c:6750
++#: c/c-typeck.c:12867 c/c-typeck.c:12893 c/c-typeck.c:13137 c/c-typeck.c:13154
++#: cp/semantics.c:6030 cp/semantics.c:6082 cp/semantics.c:6734
++#: cp/semantics.c:6751
+ #, gcc-internal-format
+ msgid "%qD appears both in data and map clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12871 cp/semantics.c:6070
++#: c/c-typeck.c:12881 cp/semantics.c:6071
+ #, gcc-internal-format
+ msgid "%qE is not a variable in clause %<firstprivate%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12897 cp/semantics.c:6109
++#: c/c-typeck.c:12907 cp/semantics.c:6110
+ #, gcc-internal-format
+ msgid "%qE is not a variable in clause %<lastprivate%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12916 cp/semantics.c:6459
++#: c/c-typeck.c:12926 cp/semantics.c:6460
+ #, gcc-internal-format
+ msgid "%qE is not a variable in %<aligned%> clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12923
++#: c/c-typeck.c:12933
+ #, gcc-internal-format
+ msgid "%qE in %<aligned%> clause is neither a pointer nor an array"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12930
++#: c/c-typeck.c:12940
+ #, gcc-internal-format
+ msgid "%qE appears more than once in %<aligned%> clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:12985 cp/semantics.c:6541
++#: c/c-typeck.c:12995 cp/semantics.c:6542
+ #, gcc-internal-format
+ msgid "%qE is not a variable in %<depend%> clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13007 cp/semantics.c:6572
++#: c/c-typeck.c:13017 cp/semantics.c:6573
+ #, gcc-internal-format
+ msgid "array section does not have mappable type in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13024 c/c-typeck.c:13136 cp/semantics.c:6591
+-#: cp/semantics.c:6742
++#: c/c-typeck.c:13034 c/c-typeck.c:13146 cp/semantics.c:6592
++#: cp/semantics.c:6743
+ #, gcc-internal-format
+ msgid "%qD appears more than once in motion clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13027 c/c-typeck.c:13138 cp/semantics.c:6594
+-#: cp/semantics.c:6744
++#: c/c-typeck.c:13037 c/c-typeck.c:13148 cp/semantics.c:6595
++#: cp/semantics.c:6745
+ #, gcc-internal-format
+ msgid "%qD appears more than once in map clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13059 cp/semantics.c:6635
++#: c/c-typeck.c:13069 cp/semantics.c:6636
+ #, gcc-internal-format
+ msgid "%qE does not have a mappable type in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13112 c/c-typeck.c:13185 cp/semantics.c:6710
+-#: cp/semantics.c:6841
++#: c/c-typeck.c:13122 c/c-typeck.c:13195 cp/semantics.c:6711
++#: cp/semantics.c:6842
+ #, gcc-internal-format
+ msgid "%qD does not have a mappable type in %qs clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13122 cp/semantics.c:6023 cp/semantics.c:6076
+-#: cp/semantics.c:6115 cp/semantics.c:6728
++#: c/c-typeck.c:13132 cp/semantics.c:6024 cp/semantics.c:6077
++#: cp/semantics.c:6116 cp/semantics.c:6729
+ #, gcc-internal-format
+ msgid "%qD appears more than once in data clauses"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13166 cp/semantics.c:6821
++#: c/c-typeck.c:13176 cp/semantics.c:6822
+ #, gcc-internal-format
+ msgid "%qE is neither a variable nor a function name in clause %qs"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13194 cp/semantics.c:6850
++#: c/c-typeck.c:13204 cp/semantics.c:6851
+ #, gcc-internal-format
+ msgid "%qE appears more than once on the same %<declare target%> directive"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13208 cp/semantics.c:6865
++#: c/c-typeck.c:13218 cp/semantics.c:6866
+ #, gcc-internal-format
+ msgid "%qD is not an argument in %<uniform%> clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13211 cp/semantics.c:6867
++#: c/c-typeck.c:13221 cp/semantics.c:6868
+ #, gcc-internal-format
+ msgid "%qE is not an argument in %<uniform%> clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13226
++#: c/c-typeck.c:13236
+ #, gcc-internal-format
+ msgid "%qs variable is neither a pointer nor an array"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13301 cp/semantics.c:6269
++#: c/c-typeck.c:13311 cp/semantics.c:6270
+ #, gcc-internal-format
+ msgid "%<nonmonotonic%> modifier specified for %qs schedule kind"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13332 cp/semantics.c:7042
++#: c/c-typeck.c:13342 cp/semantics.c:7043
+ #, gcc-internal-format
+ msgid "%<inbranch%> clause is incompatible with %<notinbranch%>"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13382 cp/semantics.c:7233
++#: c/c-typeck.c:13392 cp/semantics.c:7234
+ #, gcc-internal-format
+ msgid "%qE is predetermined %qs for %qs"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13402 cp/semantics.c:7124
++#: c/c-typeck.c:13412 cp/semantics.c:7125
+ #, gcc-internal-format
+ msgid "%<simdlen%> clause value is bigger than %<safelen%> clause value"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13414 cp/semantics.c:7137
++#: c/c-typeck.c:13424 cp/semantics.c:7138
+ #, gcc-internal-format
+ msgid ""
+ "%<nonmonotonic%> schedule modifier specified together with %<ordered%> clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13432 cp/semantics.c:7104
++#: c/c-typeck.c:13442 cp/semantics.c:7105
+ #, gcc-internal-format
+ msgid ""
+ "%<linear%> clause step is a parameter %qD not specified in %<uniform%> clause"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13561
++#: c/c-typeck.c:13571
+ #, gcc-internal-format
+ msgid "cannot use %<va_arg%> with reverse storage order"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13566
++#: c/c-typeck.c:13576
+ #, gcc-internal-format
+ msgid "second argument to %<va_arg%> is of incomplete type %qT"
+ msgstr ""
+ 
+-#: c/c-typeck.c:13572
++#: c/c-typeck.c:13582
+ #, gcc-internal-format
+ msgid "C++ requires promoted type, not enum type, in %<va_arg%>"
+ msgstr ""
+@@ -36411,7 +36485,7 @@
+ "invalid initialization of reference of type %qT from expression of type %qT"
+ msgstr ""
+ 
+-#: cp/class.c:324
++#: cp/class.c:326
+ #, gcc-internal-format
+ msgid ""
+ "cannot convert from pointer to base class %qT to pointer to derived class "
+@@ -36418,7 +36492,7 @@
+ "%qT because the base is virtual"
+ msgstr ""
+ 
+-#: cp/class.c:328
++#: cp/class.c:330
+ #, gcc-internal-format
+ msgid ""
+ "cannot convert from base class %qT to derived class %qT because the base is "
+@@ -36425,7 +36499,7 @@
+ "virtual"
+ msgstr ""
+ 
+-#: cp/class.c:335
++#: cp/class.c:337
+ #, gcc-internal-format
+ msgid ""
+ "cannot convert from pointer to base class %qT to pointer to derived class "
+@@ -36432,238 +36506,238 @@
+ "%qT via virtual base %qT"
+ msgstr ""
+ 
+-#: cp/class.c:340
++#: cp/class.c:342
+ #, gcc-internal-format
+ msgid ""
+ "cannot convert from base class %qT to derived class %qT via virtual base %qT"
+ msgstr ""
+ 
+-#: cp/class.c:1055
++#: cp/class.c:1057
+ #, gcc-internal-format
+ msgid "Java class %qT cannot have a destructor"
+ msgstr ""
+ 
+-#: cp/class.c:1057
++#: cp/class.c:1059
+ #, gcc-internal-format
+ msgid "Java class %qT cannot have an implicit non-trivial destructor"
+ msgstr ""
+ 
+-#: cp/class.c:1193
++#: cp/class.c:1195
+ #, gcc-internal-format
+ msgid "%q#D inherited from %qT"
+ msgstr ""
+ 
+-#: cp/class.c:1196
++#: cp/class.c:1198
+ #, gcc-internal-format
+ msgid "conflicts with version inherited from %qT"
+ msgstr ""
+ 
+-#: cp/class.c:1210
++#: cp/class.c:1212
+ #, gcc-internal-format
+ msgid "%q+#D cannot be overloaded"
+ msgstr ""
+ 
+-#: cp/class.c:1211
++#: cp/class.c:1213
+ #, gcc-internal-format
+ msgid "with %q+#D"
+ msgstr ""
+ 
+-#: cp/class.c:1284
++#: cp/class.c:1286
+ #, gcc-internal-format
+ msgid "conflicting access specifications for method %q+D, ignored"
+ msgstr ""
+ 
+-#: cp/class.c:1287
++#: cp/class.c:1289
+ #, gcc-internal-format
+ msgid "conflicting access specifications for field %qE, ignored"
+ msgstr ""
+ 
+-#: cp/class.c:1350 cp/class.c:1358
++#: cp/class.c:1352 cp/class.c:1360
+ #, gcc-internal-format
+ msgid "%q+D invalid in %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:1351
++#: cp/class.c:1353
+ #, gcc-internal-format
+ msgid "  because of local method %q+#D with same name"
+ msgstr ""
+ 
+-#: cp/class.c:1359
++#: cp/class.c:1361
+ #, gcc-internal-format
+ msgid "  because of local member %q+#D with same name"
+ msgstr ""
+ 
+-#: cp/class.c:1414
++#: cp/class.c:1416
+ #, gcc-internal-format
+ msgid "%qD inherits the %E ABI tag that %qT (used in its return type) has"
+ msgstr ""
+ 
+-#: cp/class.c:1417 cp/class.c:1423 cp/class.c:1429 cp/class.c:1440
++#: cp/class.c:1419 cp/class.c:1425 cp/class.c:1431 cp/class.c:1442
+ #, gcc-internal-format
+ msgid "%qT declared here"
+ msgstr ""
+ 
+-#: cp/class.c:1421
++#: cp/class.c:1423
+ #, gcc-internal-format
+ msgid "%qD inherits the %E ABI tag that %qT (used in its type) has"
+ msgstr ""
+ 
+-#: cp/class.c:1427
++#: cp/class.c:1429
+ #, gcc-internal-format
+ msgid "%qT does not have the %E ABI tag that base %qT has"
+ msgstr ""
+ 
+-#: cp/class.c:1434
++#: cp/class.c:1436
+ #, gcc-internal-format
+ msgid "%qT does not have the %E ABI tag that %qT (used in the type of %qD) has"
+ msgstr ""
+ 
+-#: cp/class.c:1718
++#: cp/class.c:1720
+ #, gcc-internal-format
+ msgid "cannot derive from %<final%> base %qT in derived type %qT"
+ msgstr ""
+ 
+-#: cp/class.c:2164
++#: cp/class.c:2168
+ #, gcc-internal-format
+ msgid "all member functions in class %qT are private"
+ msgstr ""
+ 
+-#: cp/class.c:2176
++#: cp/class.c:2180
+ #, gcc-internal-format
+ msgid "%q#T only defines a private destructor and has no friends"
+ msgstr ""
+ 
+-#: cp/class.c:2221
++#: cp/class.c:2225
+ #, gcc-internal-format
+ msgid "%q#T only defines private constructors and has no friends"
+ msgstr ""
+ 
+-#: cp/class.c:2614
++#: cp/class.c:2618
+ #, gcc-internal-format
+ msgid "no unique final overrider for %qD in %qT"
+ msgstr ""
+ 
+-#: cp/class.c:2975
++#: cp/class.c:2979
+ #, gcc-internal-format
+ msgid "%qD can be marked override"
+ msgstr ""
+ 
+-#: cp/class.c:2987
++#: cp/class.c:2991
+ #, gcc-internal-format
+ msgid "%q+#D marked %<final%>, but is not virtual"
+ msgstr ""
+ 
+-#: cp/class.c:2989
++#: cp/class.c:2993
+ #, gcc-internal-format
+ msgid "%q+#D marked %<override%>, but does not override"
+ msgstr ""
+ 
+-#: cp/class.c:3059
++#: cp/class.c:3063
+ #, gcc-internal-format
+ msgid "%qD was hidden"
+ msgstr ""
+ 
+-#: cp/class.c:3061
++#: cp/class.c:3065
+ #, gcc-internal-format
+ msgid "  by %qD"
+ msgstr ""
+ 
+-#: cp/class.c:3095 cp/decl2.c:1538
++#: cp/class.c:3099 cp/decl2.c:1539
+ #, gcc-internal-format
+ msgid "%q#D invalid; an anonymous union can only have non-static data members"
+ msgstr ""
+ 
+-#: cp/class.c:3099
++#: cp/class.c:3103
+ #, gcc-internal-format
+ msgid "%q#D invalid; an anonymous struct can only have non-static data members"
+ msgstr ""
+ 
+-#: cp/class.c:3111 cp/decl2.c:1545
++#: cp/class.c:3115 cp/decl2.c:1546
+ #, gcc-internal-format
+ msgid "private member %q#D in anonymous union"
+ msgstr ""
+ 
+-#: cp/class.c:3114
++#: cp/class.c:3118
+ #, gcc-internal-format
+ msgid "private member %q#D in anonymous struct"
+ msgstr ""
+ 
+-#: cp/class.c:3120 cp/decl2.c:1548
++#: cp/class.c:3124 cp/decl2.c:1549
+ #, gcc-internal-format
+ msgid "protected member %q#D in anonymous union"
+ msgstr ""
+ 
+-#: cp/class.c:3123
++#: cp/class.c:3127
+ #, gcc-internal-format
+ msgid "protected member %q#D in anonymous struct"
+ msgstr ""
+ 
+-#: cp/class.c:3302
++#: cp/class.c:3306
+ #, gcc-internal-format
+ msgid "the ellipsis in %qD is not inherited"
+ msgstr ""
+ 
+-#: cp/class.c:3480
++#: cp/class.c:3484
+ #, gcc-internal-format
+ msgid "bit-field %q+#D with non-integral type"
+ msgstr ""
+ 
+-#: cp/class.c:3496
++#: cp/class.c:3500
+ #, gcc-internal-format
+ msgid "bit-field %q+D width not an integer constant"
+ msgstr ""
+ 
+-#: cp/class.c:3501
++#: cp/class.c:3505
+ #, gcc-internal-format
+ msgid "negative width in bit-field %q+D"
+ msgstr ""
+ 
+-#: cp/class.c:3506
++#: cp/class.c:3510
+ #, gcc-internal-format
+ msgid "zero width for bit-field %q+D"
+ msgstr ""
+ 
+-#: cp/class.c:3516
++#: cp/class.c:3520
+ #, gcc-internal-format
+ msgid "width of %qD exceeds its type"
+ msgstr ""
+ 
+-#: cp/class.c:3521
++#: cp/class.c:3525
+ #, gcc-internal-format
+ msgid "%qD is too small to hold all values of %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:3581
++#: cp/class.c:3585
+ #, gcc-internal-format
+ msgid "member %q+#D with constructor not allowed in union"
+ msgstr ""
+ 
+-#: cp/class.c:3584
++#: cp/class.c:3588
+ #, gcc-internal-format
+ msgid "member %q+#D with destructor not allowed in union"
+ msgstr ""
+ 
+-#: cp/class.c:3586
++#: cp/class.c:3590
+ #, gcc-internal-format
+ msgid "member %q+#D with copy assignment operator not allowed in union"
+ msgstr ""
+ 
+-#: cp/class.c:3590
++#: cp/class.c:3594
+ #, gcc-internal-format
+ msgid "unrestricted unions only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/class.c:3627
++#: cp/class.c:3631
+ #, gcc-internal-format
+ msgid "multiple fields in union %qT initialized"
+ msgstr ""
+ 
+-#: cp/class.c:3715
++#: cp/class.c:3719
+ #, gcc-internal-format
+ msgid "in C++98 %q+D may not be static because it is a member of a union"
+ msgstr ""
+ 
+-#: cp/class.c:3721
++#: cp/class.c:3725
+ #, gcc-internal-format
+ msgid ""
+ "in C++98 %q+D may not have reference type %qT because it is a member of a "
+@@ -36670,82 +36744,82 @@
+ "union"
+ msgstr ""
+ 
+-#: cp/class.c:3731
++#: cp/class.c:3735
+ #, gcc-internal-format
+ msgid "field %q+D invalidly declared function type"
+ msgstr ""
+ 
+-#: cp/class.c:3737
++#: cp/class.c:3741
+ #, gcc-internal-format
+ msgid "field %q+D invalidly declared method type"
+ msgstr ""
+ 
+-#: cp/class.c:3797
++#: cp/class.c:3801
+ #, gcc-internal-format
+ msgid "ignoring packed attribute because of unpacked non-POD field %q#D"
+ msgstr ""
+ 
+-#: cp/class.c:3845
++#: cp/class.c:3849
+ #, gcc-internal-format
+ msgid "member %q+D cannot be declared both %<const%> and %<mutable%>"
+ msgstr ""
+ 
+-#: cp/class.c:3851
++#: cp/class.c:3855
+ #, gcc-internal-format
+ msgid "member %q+D cannot be declared as a %<mutable%> reference"
+ msgstr ""
+ 
+-#: cp/class.c:3913
++#: cp/class.c:3917
+ #, gcc-internal-format
+ msgid "field %q#D with same name as class"
+ msgstr ""
+ 
+-#: cp/class.c:3936
++#: cp/class.c:3940
+ #, gcc-internal-format
+ msgid "%q#T has pointer data members"
+ msgstr ""
+ 
+-#: cp/class.c:3941
++#: cp/class.c:3945
+ #, gcc-internal-format
+ msgid "  but does not override %<%T(const %T&)%>"
+ msgstr ""
+ 
+-#: cp/class.c:3943
++#: cp/class.c:3947
+ #, gcc-internal-format
+ msgid "  or %<operator=(const %T&)%>"
+ msgstr ""
+ 
+-#: cp/class.c:3947
++#: cp/class.c:3951
+ #, gcc-internal-format
+ msgid "  but does not override %<operator=(const %T&)%>"
+ msgstr ""
+ 
+-#: cp/class.c:4352
++#: cp/class.c:4356
+ #, gcc-internal-format
+ msgid "alignment of %qD increased in -fabi-version=9 (GCC 5.2)"
+ msgstr ""
+ 
+-#: cp/class.c:4355
++#: cp/class.c:4359
+ #, gcc-internal-format
+ msgid "alignment of %qD will increase in -fabi-version=9"
+ msgstr ""
+ 
+-#: cp/class.c:4609
++#: cp/class.c:4613
+ #, gcc-internal-format
+ msgid "initializer specified for non-virtual method %q+D"
+ msgstr ""
+ 
+-#: cp/class.c:5046
++#: cp/class.c:5050
+ #, gcc-internal-format
+ msgid "method overrides both %<transaction_pure%> and %qE methods"
+ msgstr ""
+ 
+-#: cp/class.c:5067
++#: cp/class.c:5071
+ #, gcc-internal-format
+ msgid "method declared %qE overriding %qE method"
+ msgstr ""
+ 
+-#: cp/class.c:5661 cp/constexpr.c:217
++#: cp/class.c:5664 cp/constexpr.c:217
+ #, gcc-internal-format
+ msgid ""
+ "enclosing class of constexpr non-static member function %q+#D is not a "
+@@ -36752,17 +36826,17 @@
+ "literal type"
+ msgstr ""
+ 
+-#: cp/class.c:5686
++#: cp/class.c:5689
+ #, gcc-internal-format
+ msgid "%q+T is not literal because:"
+ msgstr ""
+ 
+-#: cp/class.c:5688
++#: cp/class.c:5691
+ #, gcc-internal-format
+ msgid "  %q+T has a non-trivial destructor"
+ msgstr ""
+ 
+-#: cp/class.c:5693
++#: cp/class.c:5696
+ #, gcc-internal-format
+ msgid ""
+ "  %q+T is not an aggregate, does not have a trivial default constructor, and "
+@@ -36769,32 +36843,32 @@
+ "has no constexpr constructor that is not a copy or move constructor"
+ msgstr ""
+ 
+-#: cp/class.c:5728
++#: cp/class.c:5731
+ #, gcc-internal-format
+ msgid "  base class %qT of %q+T is non-literal"
+ msgstr ""
+ 
+-#: cp/class.c:5743
++#: cp/class.c:5746
+ #, gcc-internal-format
+ msgid "  non-static data member %qD has non-literal type"
+ msgstr ""
+ 
+-#: cp/class.c:5750
++#: cp/class.c:5753
+ #, gcc-internal-format
+ msgid "  non-static data member %qD has volatile type"
+ msgstr ""
+ 
+-#: cp/class.c:5868
++#: cp/class.c:5871
+ #, gcc-internal-format
+ msgid "base class %q#T has accessible non-virtual destructor"
+ msgstr ""
+ 
+-#: cp/class.c:5897
++#: cp/class.c:5900
+ #, gcc-internal-format
+ msgid "non-static reference %q#D in class without a constructor"
+ msgstr ""
+ 
+-#: cp/class.c:5903
++#: cp/class.c:5906
+ #, gcc-internal-format
+ msgid "non-static const member %q#D in class without a constructor"
+ msgstr ""
+@@ -36801,7 +36875,7 @@
+ 
+ #. If the function is defaulted outside the class, we just
+ #. give the synthesis error.
+-#: cp/class.c:5929
++#: cp/class.c:5932
+ #, gcc-internal-format
+ msgid ""
+ "%q+D declared to take const reference, but implicit declaration would take "
+@@ -36808,83 +36882,98 @@
+ "non-const"
+ msgstr ""
+ 
+-#: cp/class.c:6206
++#: cp/class.c:6209
+ #, gcc-internal-format
+ msgid "direct base %qT inaccessible in %qT due to ambiguity"
+ msgstr ""
+ 
+-#: cp/class.c:6218
++#: cp/class.c:6221
+ #, gcc-internal-format
+ msgid "virtual base %qT inaccessible in %qT due to ambiguity"
+ msgstr ""
+ 
+-#: cp/class.c:6446
++#: cp/class.c:6449
+ #, gcc-internal-format
+ msgid ""
+ "offset of %qD is not ABI-compliant and may change in a future version of GCC"
+ msgstr ""
+ 
+-#: cp/class.c:6601
++#: cp/class.c:6604
+ #, gcc-internal-format
+ msgid "size of type %qT is too large (%qE bytes)"
+ msgstr ""
+ 
+-#: cp/class.c:6806
++#: cp/class.c:6903
+ #, gcc-internal-format
++msgid "invalid use of %q#T with a zero-size array in %q#D"
++msgstr ""
++
++#: cp/class.c:6905
++#, gcc-internal-format
++msgid "invalid use of %q#T with a flexible array member in %q#T"
++msgstr ""
++
++#: cp/class.c:6910
++#, gcc-internal-format
++msgid "array member %q#D declared here"
++msgstr ""
++
++#: cp/class.c:6937
++#, gcc-internal-format
+ msgid "zero-size array member %qD not at end of %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:6808
++#: cp/class.c:6939
+ #, gcc-internal-format
+ msgid "zero-size array member %qD in an otherwise empty %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:6813 cp/class.c:6836
++#: cp/class.c:6947 cp/class.c:6990
+ #, gcc-internal-format
+ msgid "in the definition of %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:6818
++#: cp/class.c:6955
+ #, gcc-internal-format
+ msgid "flexible array member %qD not at end of %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:6820
++#: cp/class.c:6957
+ #, gcc-internal-format
+ msgid "flexible array member %qD in an otherwise empty %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:6833
++#: cp/class.c:6988
+ #, gcc-internal-format
+ msgid "next member %q#D declared here"
+ msgstr ""
+ 
+-#: cp/class.c:6930 cp/decl.c:12954 cp/parser.c:22003
++#: cp/class.c:7100 cp/decl.c:12954 cp/parser.c:22013
+ #, gcc-internal-format
+ msgid "redefinition of %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:7076
++#: cp/class.c:7246
+ #, gcc-internal-format
+ msgid "%q#T has virtual functions and accessible non-virtual destructor"
+ msgstr ""
+ 
+-#: cp/class.c:7104
++#: cp/class.c:7274
+ #, gcc-internal-format
+ msgid "type transparent %q#T does not have any fields"
+ msgstr ""
+ 
+-#: cp/class.c:7110
++#: cp/class.c:7280
+ #, gcc-internal-format
+ msgid "type transparent class %qT has base classes"
+ msgstr ""
+ 
+-#: cp/class.c:7114
++#: cp/class.c:7284
+ #, gcc-internal-format
+ msgid "type transparent class %qT has virtual functions"
+ msgstr ""
+ 
+-#: cp/class.c:7120
++#: cp/class.c:7290
+ #, gcc-internal-format
+ msgid ""
+ "type transparent %q#T cannot be made transparent because the type of the "
+@@ -36891,7 +36980,7 @@
+ "first field has a different ABI from the class overall"
+ msgstr ""
+ 
+-#: cp/class.c:7284
++#: cp/class.c:7454
+ #, gcc-internal-format
+ msgid ""
+ "definition of std::initializer_list does not match #include "
+@@ -36898,47 +36987,47 @@
+ "<initializer_list>"
+ msgstr ""
+ 
+-#: cp/class.c:7295
++#: cp/class.c:7465
+ #, gcc-internal-format
+ msgid "trying to finish struct, but kicked out due to previous parse errors"
+ msgstr ""
+ 
+-#: cp/class.c:7831
++#: cp/class.c:8001
+ #, gcc-internal-format
+ msgid "language string %<\"%E\"%> not recognized"
+ msgstr ""
+ 
+-#: cp/class.c:7921
++#: cp/class.c:8091
+ #, gcc-internal-format
+ msgid "cannot resolve overloaded function %qD based on conversion to type %qT"
+ msgstr ""
+ 
+-#: cp/class.c:8068
++#: cp/class.c:8238
+ #, gcc-internal-format
+ msgid "no matches converting function %qD to type %q#T"
+ msgstr ""
+ 
+-#: cp/class.c:8096
++#: cp/class.c:8266
+ #, gcc-internal-format
+ msgid "converting overloaded function %qD to type %q#T is ambiguous"
+ msgstr ""
+ 
+-#: cp/class.c:8123
++#: cp/class.c:8293
+ #, gcc-internal-format
+ msgid "assuming pointer to member %qD"
+ msgstr ""
+ 
+-#: cp/class.c:8126
++#: cp/class.c:8296
+ #, gcc-internal-format
+ msgid "(a pointer to member can only be formed with %<&%E%>)"
+ msgstr ""
+ 
+-#: cp/class.c:8201 cp/class.c:8236
++#: cp/class.c:8371 cp/class.c:8406
+ #, gcc-internal-format
+ msgid "not enough type information"
+ msgstr ""
+ 
+-#: cp/class.c:8219 cp/cvt.c:171 cp/cvt.c:198 cp/cvt.c:247
++#: cp/class.c:8389 cp/cvt.c:171 cp/cvt.c:198 cp/cvt.c:247
+ #, gcc-internal-format
+ msgid "cannot convert %qE from type %qT to type %qT"
+ msgstr ""
+@@ -36948,12 +37037,12 @@
+ #. A name N used in a class S shall refer to the same declaration
+ #. in its context and when re-evaluated in the completed scope of
+ #. S.
+-#: cp/class.c:8500
++#: cp/class.c:8670
+ #, gcc-internal-format
+ msgid "declaration of %q#D"
+ msgstr ""
+ 
+-#: cp/class.c:8502
++#: cp/class.c:8672
+ #, gcc-internal-format
+ msgid "changes meaning of %qD from %q#D"
+ msgstr ""
+@@ -37022,43 +37111,43 @@
+ msgid "%qD is not usable as a constexpr function because:"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1286 cp/constexpr.c:4623
++#: cp/constexpr.c:1314 cp/constexpr.c:4733
+ #, gcc-internal-format
+ msgid "call to internal function"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1304
++#: cp/constexpr.c:1332
+ #, gcc-internal-format
+ msgid "expression %qE does not designate a constexpr function"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1322 cp/constexpr.c:4640
++#: cp/constexpr.c:1350 cp/constexpr.c:4750
+ #, gcc-internal-format
+ msgid "call to non-constexpr function %qD"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1390
++#: cp/constexpr.c:1418
+ #, gcc-internal-format
+ msgid "%qD called in a constant expression before its definition is complete"
+ msgstr ""
+ 
+ #. The definition of fun was somehow unsuitable.
+-#: cp/constexpr.c:1395
++#: cp/constexpr.c:1423
+ #, gcc-internal-format
+ msgid "%qD called in a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1399
++#: cp/constexpr.c:1427
+ #, gcc-internal-format
+ msgid "%qD used before its definition"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1439
++#: cp/constexpr.c:1467
+ #, gcc-internal-format
+ msgid "call has circular dependency"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1450
++#: cp/constexpr.c:1478
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "constexpr evaluation depth exceeds maximum of %d (use -fconstexpr-depth= to "
+@@ -37065,22 +37154,22 @@
+ "increase the maximum)"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1532
++#: cp/constexpr.c:1560
+ #, gcc-internal-format
+ msgid "constexpr call flows off the end of the function"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1612
++#: cp/constexpr.c:1640
+ #, gcc-internal-format
+ msgid "%q+E is not a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1652
++#: cp/constexpr.c:1680
+ #, gcc-internal-format
+ msgid "right operand of shift expression %q+E is negative"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1659
++#: cp/constexpr.c:1687
+ #, gcc-internal-format
+ msgid ""
+ "right operand of shift expression %q+E is >= than the precision of the left "
+@@ -37087,129 +37176,129 @@
+ "operand"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1677
++#: cp/constexpr.c:1705
+ #, gcc-internal-format
+ msgid "left operand of shift expression %q+E is negative"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1696
++#: cp/constexpr.c:1724
+ #, gcc-internal-format
+ msgid "shift expression %q+E overflows"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1967
++#: cp/constexpr.c:2055
+ #, gcc-internal-format
+ msgid ""
+ "array subscript value %qE is outside the bounds of array %qD of type %qT"
+ msgstr ""
+ 
+-#: cp/constexpr.c:1972
++#: cp/constexpr.c:2060
+ #, gcc-internal-format
+ msgid "array subscript value %qE is outside the bounds of array type %qT"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2083
++#: cp/constexpr.c:2185
+ #, gcc-internal-format
+ msgid "accessing uninitialized array element"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2123 cp/constexpr.c:2207 cp/constexpr.c:3587
++#: cp/constexpr.c:2225 cp/constexpr.c:2309 cp/constexpr.c:3686
+ #, gcc-internal-format
+ msgid "%qE is not a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2129
++#: cp/constexpr.c:2231
+ #, gcc-internal-format
+ msgid "mutable %qD is not usable in a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2150
++#: cp/constexpr.c:2252
+ #, gcc-internal-format
+ msgid ""
+ "accessing %qD member instead of initialized %qD member in constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2167
++#: cp/constexpr.c:2269
+ #, gcc-internal-format
+ msgid "accessing uninitialized member %qD"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2885
++#: cp/constexpr.c:2987
+ #, gcc-internal-format
+ msgid "accessing value of %qE through a %qT glvalue in a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2926
++#: cp/constexpr.c:3028
+ #, gcc-internal-format
+ msgid "the value of %qD is not usable in a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2933
++#: cp/constexpr.c:3035
+ #, gcc-internal-format
+ msgid "%qD used in its own initializer"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2938
++#: cp/constexpr.c:3040
+ #, gcc-internal-format
+ msgid "%q#D is not const"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2941
++#: cp/constexpr.c:3043
+ #, gcc-internal-format
+ msgid "%q#D is volatile"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2946
++#: cp/constexpr.c:3048
+ #, gcc-internal-format
+ msgid "%qD was not initialized with a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2955
++#: cp/constexpr.c:3057
+ #, gcc-internal-format
+ msgid "%qD was not declared %<constexpr%>"
+ msgstr ""
+ 
+-#: cp/constexpr.c:2958
++#: cp/constexpr.c:3060
+ #, gcc-internal-format
+ msgid "%qD does not have integral or enumeration type"
+ msgstr ""
+ 
+-#: cp/constexpr.c:3066
++#: cp/constexpr.c:3168
+ #, gcc-internal-format
+ msgid "modification of %qE is not a constant-expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:3633 cp/constexpr.c:4994
++#: cp/constexpr.c:3732 cp/constexpr.c:5104
+ #, gcc-internal-format
+ msgid "temporary of non-literal type %qT in a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:3970
++#: cp/constexpr.c:4080
+ #, gcc-internal-format
+ msgid "a reinterpret_cast is not a constant-expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:3981 cp/constexpr.c:4730
++#: cp/constexpr.c:4091 cp/constexpr.c:4840
+ #, gcc-internal-format
+ msgid "reinterpret_cast from integer to pointer"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4041 cp/constexpr.c:4881 cp/constexpr.c:5170
++#: cp/constexpr.c:4151 cp/constexpr.c:4991 cp/constexpr.c:5280
+ #, gcc-internal-format
+ msgid "expression %qE is not a constant-expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4111
++#: cp/constexpr.c:4221
+ #, gcc-internal-format
+ msgid "statement is not a constant-expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4114
++#: cp/constexpr.c:4224
+ #, gcc-internal-format
+ msgid "unexpected expression %qE of kind %s"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4184
++#: cp/constexpr.c:4294
+ #, gcc-internal-format
+ msgid ""
+ "%qE is not a constant expression because it refers to mutable subobjects of "
+@@ -37216,7 +37305,7 @@
+ "%qT"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4197
++#: cp/constexpr.c:4307
+ #, gcc-internal-format
+ msgid ""
+ "conversion from pointer type %qT to arithmetic type %qT in a constant-"
+@@ -37223,12 +37312,12 @@
+ "expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4559
++#: cp/constexpr.c:4669
+ #, gcc-internal-format
+ msgid "expression %qE has side-effects"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4756
++#: cp/constexpr.c:4866
+ #, gcc-internal-format
+ msgid ""
+ "address-of an object %qE with thread local or automatic storage is not a "
+@@ -37235,12 +37324,12 @@
+ "constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4788
++#: cp/constexpr.c:4898
+ #, gcc-internal-format
+ msgid "use of %<this%> in a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4893
++#: cp/constexpr.c:5003
+ #, gcc-internal-format
+ msgid ""
+ "typeid-expression is not a constant expression because %qE is of polymorphic "
+@@ -37247,32 +37336,32 @@
+ "type"
+ msgstr ""
+ 
+-#: cp/constexpr.c:4955
++#: cp/constexpr.c:5065
+ #, gcc-internal-format
+ msgid "cast to non-integral type %qT in a constant expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:5042
++#: cp/constexpr.c:5152
+ #, gcc-internal-format
+ msgid "division by zero is not a constant-expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:5147
++#: cp/constexpr.c:5257
+ #, gcc-internal-format
+ msgid "%<delete[]%> is not a constant-expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:5178
++#: cp/constexpr.c:5288
+ #, gcc-internal-format
+ msgid "non-constant array initialization"
+ msgstr ""
+ 
+-#: cp/constexpr.c:5198
++#: cp/constexpr.c:5308
+ #, gcc-internal-format
+ msgid "%<goto%> is not a constant-expression"
+ msgstr ""
+ 
+-#: cp/constexpr.c:5206
++#: cp/constexpr.c:5316
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unexpected AST of kind %s"
+ msgstr ""
+@@ -37347,17 +37436,17 @@
+ msgid "try statements are not allowed inside loops marked with #pragma simd"
+ msgstr ""
+ 
+-#: cp/cp-gimplify.c:1372
++#: cp/cp-gimplify.c:1373
+ #, gcc-internal-format
+ msgid "throw will always call terminate()"
+ msgstr ""
+ 
+-#: cp/cp-gimplify.c:1375
++#: cp/cp-gimplify.c:1376
+ #, gcc-internal-format
+ msgid "in C++11 destructors default to noexcept"
+ msgstr ""
+ 
+-#: cp/cp-gimplify.c:1386
++#: cp/cp-gimplify.c:1387
+ #, gcc-internal-format
+ msgid ""
+ "in C++11 this throw will terminate because destructors default to noexcept"
+@@ -38102,7 +38191,7 @@
+ msgid "  skips initialization of %q#D"
+ msgstr ""
+ 
+-#: cp/decl.c:3301 cp/parser.c:11766 cp/parser.c:11793
++#: cp/decl.c:3301 cp/parser.c:11776 cp/parser.c:11803
+ #, gcc-internal-format
+ msgid "invalid exit from OpenMP structured block"
+ msgstr ""
+@@ -38117,7 +38206,7 @@
+ msgid "%qD is not a type"
+ msgstr ""
+ 
+-#: cp/decl.c:3659 cp/parser.c:6033
++#: cp/decl.c:3659 cp/parser.c:6035
+ #, gcc-internal-format
+ msgid "%qD used without template parameters"
+ msgstr ""
+@@ -38296,7 +38385,7 @@
+ "declaration"
+ msgstr ""
+ 
+-#: cp/decl.c:4868 cp/decl2.c:889
++#: cp/decl.c:4868 cp/decl2.c:890
+ #, gcc-internal-format
+ msgid "typedef %qD is initialized (use decltype instead)"
+ msgstr ""
+@@ -38861,7 +38950,7 @@
+ msgid "%q+#D explicitly defaulted here"
+ msgstr ""
+ 
+-#: cp/decl.c:8316 cp/decl2.c:787
++#: cp/decl.c:8316 cp/decl2.c:788
+ #, gcc-internal-format
+ msgid "no %q#D member function declared in class %qT"
+ msgstr ""
+@@ -38937,7 +39026,7 @@
+ msgid "size of array %qD is negative"
+ msgstr ""
+ 
+-#: cp/decl.c:8834 cp/init.c:3437
++#: cp/decl.c:8834 cp/init.c:3442
+ #, gcc-internal-format
+ msgid "size of array is negative"
+ msgstr ""
+@@ -40061,7 +40150,7 @@
+ msgid "%qD has the same name as the class in which it is declared"
+ msgstr ""
+ 
+-#: cp/decl.c:12665 cp/friend.c:261 cp/parser.c:2971 cp/parser.c:6092
++#: cp/decl.c:12665 cp/friend.c:261 cp/parser.c:2971 cp/parser.c:6094
+ #: cp/pt.c:8169
+ #, gcc-internal-format
+ msgid "%qT is not a template"
+@@ -40078,7 +40167,7 @@
+ msgstr ""
+ 
+ #: cp/decl.c:12679 cp/name-lookup.c:2685 cp/name-lookup.c:3524
+-#: cp/name-lookup.c:3569 cp/parser.c:6043 cp/parser.c:24878
++#: cp/name-lookup.c:3569 cp/parser.c:6045 cp/parser.c:24892
+ #, gcc-internal-format
+ msgid "reference to %qD is ambiguous"
+ msgstr ""
+@@ -40143,7 +40232,7 @@
+ msgid "scoped/unscoped mismatch in enum %q#T"
+ msgstr ""
+ 
+-#: cp/decl.c:13191 cp/decl.c:13199 cp/decl.c:13211 cp/parser.c:17280
++#: cp/decl.c:13191 cp/decl.c:13199 cp/decl.c:13211 cp/parser.c:17290
+ #, gcc-internal-format
+ msgid "previous definition here"
+ msgstr ""
+@@ -40172,102 +40261,102 @@
+ msgid "no integral type can represent all of the enumerator values for %qT"
+ msgstr ""
+ 
+-#: cp/decl.c:13595
++#: cp/decl.c:13598
+ #, gcc-internal-format
+ msgid "enumerator value for %qD is not an integer constant"
+ msgstr ""
+ 
+-#: cp/decl.c:13642
++#: cp/decl.c:13645
+ #, gcc-internal-format
+ msgid "incremented enumerator value is too large for %<unsigned long%>"
+ msgstr ""
+ 
+-#: cp/decl.c:13654
++#: cp/decl.c:13657
+ #, gcc-internal-format
+ msgid "overflow in enumeration values at %qD"
+ msgstr ""
+ 
+-#: cp/decl.c:13674
++#: cp/decl.c:13677
+ #, gcc-internal-format
+ msgid "enumerator value %E is outside the range of underlying type %<%T%>"
+ msgstr ""
+ 
+-#: cp/decl.c:13767
++#: cp/decl.c:13770
+ #, gcc-internal-format
+ msgid "return type %q#T is incomplete"
+ msgstr ""
+ 
+-#: cp/decl.c:13769
++#: cp/decl.c:13772
+ #, gcc-internal-format
+ msgid "return type has Java class type %q#T"
+ msgstr ""
+ 
+-#: cp/decl.c:13941 cp/typeck.c:8819
++#: cp/decl.c:13944 cp/typeck.c:8820
+ #, gcc-internal-format
+ msgid "%<operator=%> should return a reference to %<*this%>"
+ msgstr ""
+ 
+-#: cp/decl.c:14284
++#: cp/decl.c:14287
+ #, gcc-internal-format
+ msgid "invalid function declaration"
+ msgstr ""
+ 
+-#: cp/decl.c:14366
++#: cp/decl.c:14369
+ #, gcc-internal-format
+ msgid "parameter %qD declared void"
+ msgstr ""
+ 
+-#: cp/decl.c:14715
++#: cp/decl.c:14718
+ #, gcc-internal-format
+ msgid "no return statements in function returning %qT"
+ msgstr ""
+ 
+-#: cp/decl.c:14717 cp/typeck.c:8700
++#: cp/decl.c:14720 cp/typeck.c:8701
+ #, gcc-internal-format
+ msgid "only plain %<auto%> return type can be deduced to %<void%>"
+ msgstr ""
+ 
+-#: cp/decl.c:14919
++#: cp/decl.c:14922
+ #, gcc-internal-format
+ msgid "invalid member function declaration"
+ msgstr ""
+ 
+-#: cp/decl.c:14933
++#: cp/decl.c:14936
+ #, gcc-internal-format
+ msgid "%qD is already defined in class %qT"
+ msgstr ""
+ 
+-#: cp/decl.c:15305 cp/decl2.c:5131 cp/decl2.c:5181
++#: cp/decl.c:15308 cp/decl2.c:5164 cp/decl2.c:5197
+ #, gcc-internal-format
+ msgid "use of %qD before deduction of %<auto%>"
+ msgstr ""
+ 
+-#: cp/decl2.c:332
++#: cp/decl2.c:333
+ #, gcc-internal-format
+ msgid "name missing for member function"
+ msgstr ""
+ 
+-#: cp/decl2.c:409 cp/decl2.c:423
++#: cp/decl2.c:410 cp/decl2.c:424
+ #, gcc-internal-format
+ msgid "ambiguous conversion for array subscript"
+ msgstr ""
+ 
+-#: cp/decl2.c:417
++#: cp/decl2.c:418
+ #, gcc-internal-format
+ msgid "invalid types %<%T[%T]%> for array subscript"
+ msgstr ""
+ 
+-#: cp/decl2.c:466
++#: cp/decl2.c:467
+ #, gcc-internal-format
+ msgid "deleting array %q#E"
+ msgstr ""
+ 
+-#: cp/decl2.c:472
++#: cp/decl2.c:473
+ #, gcc-internal-format
+ msgid "type %q#T argument given to %<delete%>, expected pointer"
+ msgstr ""
+ 
+-#: cp/decl2.c:484
++#: cp/decl2.c:485
+ #, gcc-internal-format
+ msgid ""
+ "cannot delete a function.  Only pointer-to-objects are valid arguments to "
+@@ -40274,27 +40363,27 @@
+ "%<delete%>"
+ msgstr ""
+ 
+-#: cp/decl2.c:492
++#: cp/decl2.c:493
+ #, gcc-internal-format
+ msgid "deleting %qT is undefined"
+ msgstr ""
+ 
+-#: cp/decl2.c:540 cp/pt.c:5188
++#: cp/decl2.c:541 cp/pt.c:5188
+ #, gcc-internal-format
+ msgid "template declaration of %q#D"
+ msgstr ""
+ 
+-#: cp/decl2.c:592
++#: cp/decl2.c:593
+ #, gcc-internal-format
+ msgid "Java method %qD has non-Java return type %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:609
++#: cp/decl2.c:610
+ #, gcc-internal-format
+ msgid "Java method %qD has non-Java parameter type %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:658
++#: cp/decl2.c:659
+ #, gcc-internal-format
+ msgid ""
+ "template parameter lists provided don%'t match the template parameters of %qD"
+@@ -40303,117 +40392,117 @@
+ #. [temp.mem]
+ #.
+ #. A destructor shall not be a member template.
+-#: cp/decl2.c:673 cp/pt.c:5158
++#: cp/decl2.c:674 cp/pt.c:5158
+ #, gcc-internal-format
+ msgid "destructor %qD declared as member template"
+ msgstr ""
+ 
+-#: cp/decl2.c:749
++#: cp/decl2.c:750
+ #, gcc-internal-format
+ msgid "prototype for %q#D does not match any in class %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:835
++#: cp/decl2.c:836
+ #, gcc-internal-format
+ msgid "local class %q#T shall not have static data member %q#D"
+ msgstr ""
+ 
+-#: cp/decl2.c:843
++#: cp/decl2.c:844
+ #, gcc-internal-format
+ msgid "static data member %qD in unnamed class"
+ msgstr ""
+ 
+-#: cp/decl2.c:845
++#: cp/decl2.c:846
+ #, gcc-internal-format
+ msgid "unnamed class defined here"
+ msgstr ""
+ 
+-#: cp/decl2.c:904
++#: cp/decl2.c:905
+ #, gcc-internal-format
+ msgid "explicit template argument list not allowed"
+ msgstr ""
+ 
+-#: cp/decl2.c:910
++#: cp/decl2.c:911
+ #, gcc-internal-format
+ msgid "member %qD conflicts with virtual function table field name"
+ msgstr ""
+ 
+-#: cp/decl2.c:952
++#: cp/decl2.c:953
+ #, gcc-internal-format
+ msgid "%qD is already defined in %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:979 cp/decl2.c:987
++#: cp/decl2.c:980 cp/decl2.c:988
+ #, gcc-internal-format
+ msgid "invalid initializer for member function %qD"
+ msgstr ""
+ 
+-#: cp/decl2.c:994
++#: cp/decl2.c:995
+ #, gcc-internal-format
+ msgid "initializer specified for friend function %qD"
+ msgstr ""
+ 
+-#: cp/decl2.c:997
++#: cp/decl2.c:998
+ #, gcc-internal-format
+ msgid "initializer specified for static member function %qD"
+ msgstr ""
+ 
+-#: cp/decl2.c:1041
++#: cp/decl2.c:1042
+ #, gcc-internal-format
+ msgid "%<asm%> specifiers are not permitted on non-static data members"
+ msgstr ""
+ 
+-#: cp/decl2.c:1094
++#: cp/decl2.c:1095
+ #, gcc-internal-format
+ msgid "bit-field %qD with non-integral type"
+ msgstr ""
+ 
+-#: cp/decl2.c:1100
++#: cp/decl2.c:1101
+ #, gcc-internal-format
+ msgid "cannot declare %qD to be a bit-field type"
+ msgstr ""
+ 
+-#: cp/decl2.c:1110
++#: cp/decl2.c:1111
+ #, gcc-internal-format
+ msgid "cannot declare bit-field %qD with function type"
+ msgstr ""
+ 
+-#: cp/decl2.c:1117
++#: cp/decl2.c:1118
+ #, gcc-internal-format
+ msgid "%qD is already defined in the class %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:1124
++#: cp/decl2.c:1125
+ #, gcc-internal-format
+ msgid "static member %qD cannot be a bit-field"
+ msgstr ""
+ 
+-#: cp/decl2.c:1134
++#: cp/decl2.c:1135
+ #, gcc-internal-format
+ msgid "width of bit-field %qD has non-integral type %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:1458
++#: cp/decl2.c:1459
+ #, gcc-internal-format
+ msgid "%q+D static data member inside of declare target directive"
+ msgstr ""
+ 
+-#: cp/decl2.c:1522
++#: cp/decl2.c:1523
+ #, gcc-internal-format
+ msgid "anonymous struct not inside named type"
+ msgstr ""
+ 
+-#: cp/decl2.c:1613
++#: cp/decl2.c:1614
+ #, gcc-internal-format
+ msgid "namespace-scope anonymous aggregates must be static"
+ msgstr ""
+ 
+-#: cp/decl2.c:1622
++#: cp/decl2.c:1623
+ #, gcc-internal-format
+ msgid "anonymous union with no members"
+ msgstr ""
+ 
+-#: cp/decl2.c:1655
++#: cp/decl2.c:1656
+ #, gcc-internal-format
+ msgid "%<operator new%> must return type %qT"
+ msgstr ""
+@@ -40422,69 +40511,69 @@
+ #.
+ #. The first parameter shall not have an associated default
+ #. argument.
+-#: cp/decl2.c:1666
++#: cp/decl2.c:1667
+ #, gcc-internal-format
+ msgid "the first parameter of %<operator new%> cannot have a default argument"
+ msgstr ""
+ 
+-#: cp/decl2.c:1682
++#: cp/decl2.c:1683
+ #, gcc-internal-format
+ msgid "%<operator new%> takes type %<size_t%> (%qT) as first parameter"
+ msgstr ""
+ 
+-#: cp/decl2.c:1711
++#: cp/decl2.c:1712
+ #, gcc-internal-format
+ msgid "%<operator delete%> must return type %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:1720
++#: cp/decl2.c:1721
+ #, gcc-internal-format
+ msgid "%<operator delete%> takes type %qT as first parameter"
+ msgstr ""
+ 
+-#: cp/decl2.c:2572
++#: cp/decl2.c:2573
+ #, gcc-internal-format
+ msgid "%qT has a field %qD whose type has no linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:2576
++#: cp/decl2.c:2577
+ #, gcc-internal-format
+ msgid ""
+ "%qT has a field %qD whose type depends on the type %qT which has no linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:2581
++#: cp/decl2.c:2582
+ #, gcc-internal-format
+ msgid "%qT has a field %qD whose type uses the anonymous namespace"
+ msgstr ""
+ 
+-#: cp/decl2.c:2589
++#: cp/decl2.c:2590
+ #, gcc-internal-format
+ msgid "%qT declared with greater visibility than the type of its field %qD"
+ msgstr ""
+ 
+-#: cp/decl2.c:2607
++#: cp/decl2.c:2608
+ #, gcc-internal-format
+ msgid "%qT has a base %qT whose type has no linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:2611
++#: cp/decl2.c:2612
+ #, gcc-internal-format
+ msgid ""
+ "%qT has a base %qT whose type depends on the type %qT which has no linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:2616
++#: cp/decl2.c:2617
+ #, gcc-internal-format
+ msgid "%qT has a base %qT whose type uses the anonymous namespace"
+ msgstr ""
+ 
+-#: cp/decl2.c:2623
++#: cp/decl2.c:2624
+ #, gcc-internal-format
+ msgid "%qT declared with greater visibility than its base %qT"
+ msgstr ""
+ 
+-#: cp/decl2.c:4263
++#: cp/decl2.c:4264
+ #, gcc-internal-format
+ msgid "%q#D, declared using anonymous type, is used but never defined"
+ msgstr ""
+@@ -40493,50 +40582,50 @@
+ #. no linkage can only be used to declare extern "C"
+ #. entities.  Since it's not always an error in the
+ #. ISO C++ 90 Standard, we only issue a warning.
+-#: cp/decl2.c:4272
++#: cp/decl2.c:4273
+ #, gcc-internal-format
+ msgid ""
+ "anonymous type with no linkage used to declare variable %q#D with linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:4276
++#: cp/decl2.c:4277
+ #, gcc-internal-format
+ msgid ""
+ "anonymous type with no linkage used to declare function %q#D with linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:4280
++#: cp/decl2.c:4281
+ #, gcc-internal-format
+ msgid ""
+ "%q#D does not refer to the unqualified type, so it is not used for linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:4288
++#: cp/decl2.c:4289
+ #, gcc-internal-format
+ msgid "%q#D, declared using local type %qT, is used but never defined"
+ msgstr ""
+ 
+-#: cp/decl2.c:4292
++#: cp/decl2.c:4293
+ #, gcc-internal-format
+ msgid "type %qT with no linkage used to declare variable %q#D with linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:4295
++#: cp/decl2.c:4296
+ #, gcc-internal-format
+ msgid "type %qT with no linkage used to declare function %q#D with linkage"
+ msgstr ""
+ 
+-#: cp/decl2.c:4482 cp/decl2.c:4485
++#: cp/decl2.c:4483 cp/decl2.c:4486
+ #, gcc-internal-format
+ msgid "the program should also define %qD"
+ msgstr ""
+ 
+-#: cp/decl2.c:4846
++#: cp/decl2.c:4847
+ #, gcc-internal-format
+ msgid "inline function %qD used but never defined"
+ msgstr ""
+ 
+-#: cp/decl2.c:5035
++#: cp/decl2.c:5036
+ #, gcc-internal-format
+ msgid "default argument missing for parameter %P of %q+#D"
+ msgstr ""
+@@ -40543,54 +40632,54 @@
+ 
+ #. We mark a lambda conversion op as deleted if we can't
+ #. generate it properly; see maybe_add_lambda_conv_op.
+-#: cp/decl2.c:5103
++#: cp/decl2.c:5136
+ #, gcc-internal-format
+ msgid "converting lambda which uses %<...%> to function pointer"
+ msgstr ""
+ 
+-#: cp/decl2.c:5110
++#: cp/decl2.c:5143
+ #, gcc-internal-format
+ msgid "use of deleted function %qD"
+ msgstr ""
+ 
+-#: cp/error.c:1456
++#: cp/error.c:1455
+ #, gcc-internal-format
+ msgid "with"
+ msgstr ""
+ 
+-#: cp/error.c:3597
++#: cp/error.c:3596
+ #, gcc-internal-format
+ msgid ""
+ "extended initializer lists only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3602
++#: cp/error.c:3601
+ #, gcc-internal-format
+ msgid ""
+ "explicit conversion operators only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3607
++#: cp/error.c:3606
+ #, gcc-internal-format
+ msgid "variadic templates only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3612
++#: cp/error.c:3611
+ #, gcc-internal-format
+ msgid "lambda expressions only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3617
++#: cp/error.c:3616
+ #, gcc-internal-format
+ msgid "C++11 auto only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3621
++#: cp/error.c:3620
+ #, gcc-internal-format
+ msgid "scoped enums only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3625
++#: cp/error.c:3624
+ #, gcc-internal-format
+ msgid ""
+ "defaulted and deleted functions only available with -std=c++11 or -std=gnu+"
+@@ -40597,12 +40686,12 @@
+ "+11"
+ msgstr ""
+ 
+-#: cp/error.c:3630
++#: cp/error.c:3629
+ #, gcc-internal-format
+ msgid "inline namespaces only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3635
++#: cp/error.c:3634
+ #, gcc-internal-format
+ msgid ""
+ "override controls (override/final) only available with -std=c++11 or -std=gnu"
+@@ -40609,7 +40698,7 @@
+ "++11"
+ msgstr ""
+ 
+-#: cp/error.c:3640
++#: cp/error.c:3639
+ #, gcc-internal-format
+ msgid ""
+ "non-static data member initializers only available with -std=c++11 or -"
+@@ -40616,52 +40705,52 @@
+ "std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3645
++#: cp/error.c:3644
+ #, gcc-internal-format
+ msgid "user-defined literals only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3650
++#: cp/error.c:3649
+ #, gcc-internal-format
+ msgid "delegating constructors only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3655
++#: cp/error.c:3654
+ #, gcc-internal-format
+ msgid "inheriting constructors only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3660
++#: cp/error.c:3659
+ #, gcc-internal-format
+ msgid "c++11 attributes only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3665
++#: cp/error.c:3664
+ #, gcc-internal-format
+ msgid "ref-qualifiers only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/error.c:3715
++#: cp/error.c:3714
+ #, gcc-internal-format
+ msgid "incomplete type %qT used in nested name specifier"
+ msgstr ""
+ 
+-#: cp/error.c:3719
++#: cp/error.c:3718
+ #, gcc-internal-format
+ msgid "reference to %<%T::%D%> is ambiguous"
+ msgstr ""
+ 
+-#: cp/error.c:3724 cp/typeck.c:2339
++#: cp/error.c:3723 cp/typeck.c:2339
+ #, gcc-internal-format
+ msgid "%qD is not a member of %qT"
+ msgstr ""
+ 
+-#: cp/error.c:3728 cp/typeck.c:2767
++#: cp/error.c:3727 cp/typeck.c:2767
+ #, gcc-internal-format
+ msgid "%qD is not a member of %qD"
+ msgstr ""
+ 
+-#: cp/error.c:3733
++#: cp/error.c:3732
+ #, gcc-internal-format
+ msgid "%<::%D%> has not been declared"
+ msgstr ""
+@@ -40698,7 +40787,7 @@
+ msgid "throwing NULL, which has integral, not pointer type"
+ msgstr ""
+ 
+-#: cp/except.c:754 cp/init.c:2883
++#: cp/except.c:754 cp/init.c:2888
+ #, gcc-internal-format
+ msgid "%qD should never be overloaded"
+ msgstr ""
+@@ -41001,7 +41090,7 @@
+ msgid "bad array initializer"
+ msgstr ""
+ 
+-#: cp/init.c:1877 cp/semantics.c:3187
++#: cp/init.c:1877 cp/semantics.c:3188
+ #, gcc-internal-format
+ msgid "%qT is not a class type"
+ msgstr ""
+@@ -41062,7 +41151,7 @@
+ msgid "uninitialized const member in base %q#T of %q#T"
+ msgstr ""
+ 
+-#: cp/init.c:2537
++#: cp/init.c:2542
+ #, gcc-internal-format
+ msgid ""
+ "placement new constructing an object of type %<%T [%wu]%> and size %qwu in a "
+@@ -41069,7 +41158,7 @@
+ "region of type %qT and size %qwi"
+ msgstr ""
+ 
+-#: cp/init.c:2549
++#: cp/init.c:2554
+ #, gcc-internal-format
+ msgid ""
+ "placement new constructing an array of objects of type %qT and size %qwu in "
+@@ -41076,7 +41165,7 @@
+ "a region of type %qT and size %qwi"
+ msgstr ""
+ 
+-#: cp/init.c:2560
++#: cp/init.c:2565
+ #, gcc-internal-format
+ msgid ""
+ "placement new constructing an object of type %qT and size %qwu in a region "
+@@ -41083,97 +41172,97 @@
+ "of type %qT and size %qwi"
+ msgstr ""
+ 
+-#: cp/init.c:2674
++#: cp/init.c:2679
+ #, gcc-internal-format
+ msgid "integer overflow in array size"
+ msgstr ""
+ 
+-#: cp/init.c:2684
++#: cp/init.c:2689
+ #, gcc-internal-format
+ msgid "array size in new-expression must be constant"
+ msgstr ""
+ 
+-#: cp/init.c:2698
++#: cp/init.c:2703
+ #, gcc-internal-format
+ msgid "variably modified type not allowed in new-expression"
+ msgstr ""
+ 
+-#: cp/init.c:2729
++#: cp/init.c:2734
+ #, gcc-internal-format
+ msgid "invalid type %<void%> for new"
+ msgstr ""
+ 
+-#: cp/init.c:2772
++#: cp/init.c:2777
+ #, gcc-internal-format
+ msgid "uninitialized const in %<new%> of %q#T"
+ msgstr ""
+ 
+-#: cp/init.c:2864
++#: cp/init.c:2869
+ #, gcc-internal-format
+ msgid "%qT isn%'t a valid Java class type"
+ msgstr ""
+ 
+-#: cp/init.c:2877
++#: cp/init.c:2882
+ #, gcc-internal-format
+ msgid "call to Java constructor with %qs undefined"
+ msgstr ""
+ 
+-#: cp/init.c:2892
++#: cp/init.c:2897
+ #, gcc-internal-format
+ msgid "%qD is not a function returning a pointer"
+ msgstr ""
+ 
+-#: cp/init.c:2901
++#: cp/init.c:2906
+ #, gcc-internal-format
+ msgid "Java class %q#T object allocated using placement new"
+ msgstr ""
+ 
+-#: cp/init.c:2945
++#: cp/init.c:2950
+ #, gcc-internal-format
+ msgid "no suitable %qD found in class %qT"
+ msgstr ""
+ 
+-#: cp/init.c:2952 cp/search.c:1172
++#: cp/init.c:2957 cp/search.c:1172
+ #, gcc-internal-format
+ msgid "request for member %qD is ambiguous"
+ msgstr ""
+ 
+-#: cp/init.c:3181
++#: cp/init.c:3186
+ #, gcc-internal-format
+ msgid "parenthesized initializer in array new"
+ msgstr ""
+ 
+-#: cp/init.c:3419
++#: cp/init.c:3424
+ #, gcc-internal-format
+ msgid "size in array new must have integral type"
+ msgstr ""
+ 
+-#: cp/init.c:3451
++#: cp/init.c:3456
+ #, gcc-internal-format
+ msgid "new cannot be applied to a reference type"
+ msgstr ""
+ 
+-#: cp/init.c:3460
++#: cp/init.c:3465
+ #, gcc-internal-format
+ msgid "new cannot be applied to a function type"
+ msgstr ""
+ 
+-#: cp/init.c:3504
++#: cp/init.c:3509
+ #, gcc-internal-format
+ msgid "call to Java constructor, while %<jclass%> undefined"
+ msgstr ""
+ 
+-#: cp/init.c:3522
++#: cp/init.c:3527
+ #, gcc-internal-format
+ msgid "can%'t find %<class$%> in %qT"
+ msgstr ""
+ 
+-#: cp/init.c:3582
++#: cp/init.c:3587
+ #, gcc-internal-format
+ msgid "possible problem detected in invocation of delete [] operator:"
+ msgstr ""
+ 
+-#: cp/init.c:3586
++#: cp/init.c:3591
+ #, gcc-internal-format
+ msgid ""
+ "neither the destructor nor the class-specific operator delete [] will be "
+@@ -41180,27 +41269,27 @@
+ "called, even if they are declared when the class is defined"
+ msgstr ""
+ 
+-#: cp/init.c:4078
++#: cp/init.c:4083
+ #, gcc-internal-format
+ msgid "initializer ends prematurely"
+ msgstr ""
+ 
+-#: cp/init.c:4163
++#: cp/init.c:4168
+ #, gcc-internal-format
+ msgid "cannot initialize multi-dimensional array with initializer"
+ msgstr ""
+ 
+-#: cp/init.c:4370
++#: cp/init.c:4375
+ #, gcc-internal-format
+ msgid "unknown array size in delete"
+ msgstr ""
+ 
+-#: cp/init.c:4394
++#: cp/init.c:4399
+ #, gcc-internal-format
+ msgid "possible problem detected in invocation of delete operator:"
+ msgstr ""
+ 
+-#: cp/init.c:4399
++#: cp/init.c:4404
+ #, gcc-internal-format
+ msgid ""
+ "neither the destructor nor the class-specific operator delete will be "
+@@ -41207,7 +41296,7 @@
+ "called, even if they are declared when the class is defined"
+ msgstr ""
+ 
+-#: cp/init.c:4414
++#: cp/init.c:4419
+ #, gcc-internal-format
+ msgid ""
+ "deleting object of abstract class type %qT which has non-virtual destructor "
+@@ -41214,7 +41303,7 @@
+ "will cause undefined behavior"
+ msgstr ""
+ 
+-#: cp/init.c:4419
++#: cp/init.c:4424
+ #, gcc-internal-format
+ msgid ""
+ "deleting object of polymorphic class type %qT which has non-virtual "
+@@ -41221,7 +41310,7 @@
+ "destructor might cause undefined behavior"
+ msgstr ""
+ 
+-#: cp/init.c:4720
++#: cp/init.c:4725
+ #, gcc-internal-format
+ msgid "type to vector delete is neither pointer or array type"
+ msgstr ""
+@@ -41824,7 +41913,7 @@
+ msgid "LEXER_DEBUGGING_ENABLED_P is not set to true"
+ msgstr ""
+ 
+-#: cp/parser.c:1349 cp/parser.c:35699
++#: cp/parser.c:1349 cp/parser.c:35714
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp declare simd%> not immediately followed by function "
+@@ -41831,8 +41920,8 @@
+ "declaration or definition"
+ msgstr ""
+ 
+-#: cp/parser.c:1387 cp/parser.c:36532 cp/parser.c:36637 cp/parser.c:36662
+-#: cp/parser.c:36719
++#: cp/parser.c:1387 cp/parser.c:36547 cp/parser.c:36652 cp/parser.c:36677
++#: cp/parser.c:36734
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma acc routine%> not followed by a function declaration or definition"
+@@ -41858,7 +41947,7 @@
+ msgid "request for member %qE in non-class type %qT"
+ msgstr ""
+ 
+-#: cp/parser.c:2826 cp/parser.c:17228
++#: cp/parser.c:2826 cp/parser.c:17238
+ #, gcc-internal-format
+ msgid "%<%T::%E%> has not been declared"
+ msgstr ""
+@@ -42145,7 +42234,7 @@
+ msgid "unable to find string literal operator %qD with %qT, %qT arguments"
+ msgstr ""
+ 
+-#: cp/parser.c:4347 cp/parser.c:12322
++#: cp/parser.c:4347 cp/parser.c:12332
+ #, gcc-internal-format
+ msgid "expected declaration"
+ msgstr ""
+@@ -42160,32 +42249,32 @@
+ msgid "expected ..."
+ msgstr ""
+ 
+-#: cp/parser.c:4640
++#: cp/parser.c:4642
+ #, gcc-internal-format
+ msgid "binary expression in operand of fold-expression"
+ msgstr ""
+ 
+-#: cp/parser.c:4643
++#: cp/parser.c:4645
+ #, gcc-internal-format
+ msgid "conditional expression in operand of fold-expression"
+ msgstr ""
+ 
+-#: cp/parser.c:4651
++#: cp/parser.c:4653
+ #, gcc-internal-format
+ msgid "mismatched operator in fold-expression"
+ msgstr ""
+ 
+-#: cp/parser.c:4755
++#: cp/parser.c:4757
+ #, gcc-internal-format
+ msgid "fixed-point types not supported in C++"
+ msgstr ""
+ 
+-#: cp/parser.c:4836
++#: cp/parser.c:4838
+ #, gcc-internal-format
+ msgid "ISO C++ forbids braced-groups within expressions"
+ msgstr ""
+ 
+-#: cp/parser.c:4848
++#: cp/parser.c:4850
+ #, gcc-internal-format
+ msgid ""
+ "statement-expressions are not allowed outside functions nor in template-"
+@@ -42192,57 +42281,57 @@
+ "argument lists"
+ msgstr ""
+ 
+-#: cp/parser.c:4887
++#: cp/parser.c:4889
+ #, gcc-internal-format
+ msgid "fold-expressions only available with -std=c++1z or -std=gnu++1z"
+ msgstr ""
+ 
+-#: cp/parser.c:4945 cp/parser.c:5116 cp/parser.c:5294
++#: cp/parser.c:4947 cp/parser.c:5118 cp/parser.c:5296
+ #, gcc-internal-format
+ msgid "expected primary-expression"
+ msgstr ""
+ 
+-#: cp/parser.c:4975
++#: cp/parser.c:4977
+ #, gcc-internal-format
+ msgid "%<this%> may not be used in this context"
+ msgstr ""
+ 
+-#: cp/parser.c:5111
++#: cp/parser.c:5113
+ #, gcc-internal-format
+ msgid "a template declaration cannot appear at block scope"
+ msgstr ""
+ 
+-#: cp/parser.c:5269
++#: cp/parser.c:5271
+ #, gcc-internal-format
+ msgid "local variable %qD may not appear in this context"
+ msgstr ""
+ 
+-#: cp/parser.c:5446
++#: cp/parser.c:5448
+ #, gcc-internal-format
+ msgid "expected id-expression"
+ msgstr ""
+ 
+-#: cp/parser.c:5578
++#: cp/parser.c:5580
+ #, gcc-internal-format
+ msgid "scope %qT before %<~%> is not a class-name"
+ msgstr ""
+ 
+-#: cp/parser.c:5607 cp/parser.c:7560
++#: cp/parser.c:5609 cp/parser.c:7570
+ #, gcc-internal-format
+ msgid "%<~auto%> only available with -std=c++14 or -std=gnu++14"
+ msgstr ""
+ 
+-#: cp/parser.c:5718
++#: cp/parser.c:5720
+ #, gcc-internal-format
+ msgid "declaration of %<~%T%> as member of %qT"
+ msgstr ""
+ 
+-#: cp/parser.c:5733
++#: cp/parser.c:5735
+ #, gcc-internal-format
+ msgid "typedef-name %qD used as destructor declarator"
+ msgstr ""
+ 
+-#: cp/parser.c:5768
++#: cp/parser.c:5770
+ #, gcc-internal-format
+ msgid ""
+ "literal operator suffixes not preceded by %<_%> are reserved for future "
+@@ -42249,117 +42338,117 @@
+ "standardization"
+ msgstr ""
+ 
+-#: cp/parser.c:5779 cp/parser.c:19204
++#: cp/parser.c:5781 cp/parser.c:19214
+ #, gcc-internal-format
+ msgid "expected unqualified-id"
+ msgstr ""
+ 
+-#: cp/parser.c:5886
++#: cp/parser.c:5888
+ #, gcc-internal-format
+ msgid "found %<:%> in nested-name-specifier, expected %<::%>"
+ msgstr ""
+ 
+-#: cp/parser.c:5955
++#: cp/parser.c:5957
+ #, gcc-internal-format
+ msgid "decltype evaluates to %qT, which is not a class or enumeration type"
+ msgstr ""
+ 
+-#: cp/parser.c:5981
++#: cp/parser.c:5983
+ #, gcc-internal-format
+ msgid "function template-id %qD in nested-name-specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:5989
++#: cp/parser.c:5991
+ #, gcc-internal-format
+ msgid "variable template-id %qD in nested-name-specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:6093 cp/typeck.c:2610 cp/typeck.c:2613 cp/typeck.c:2633
++#: cp/parser.c:6095 cp/typeck.c:2610 cp/typeck.c:2613 cp/typeck.c:2633
+ #, gcc-internal-format
+ msgid "%qD is not a template"
+ msgstr ""
+ 
+-#: cp/parser.c:6171
++#: cp/parser.c:6173
+ #, gcc-internal-format
+ msgid "expected nested-name-specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:6372 cp/parser.c:8540
++#: cp/parser.c:6374 cp/parser.c:8550
+ #, gcc-internal-format
+ msgid "types may not be defined in casts"
+ msgstr ""
+ 
+-#: cp/parser.c:6453
++#: cp/parser.c:6458
+ #, gcc-internal-format
+ msgid "types may not be defined in a %<typeid%> expression"
+ msgstr ""
+ 
+-#: cp/parser.c:6511
++#: cp/parser.c:6516
+ #, gcc-internal-format
+ msgid "%<_Cilk_spawn%> must be followed by an expression"
+ msgstr ""
+ 
+-#: cp/parser.c:6660
++#: cp/parser.c:6670
+ #, gcc-internal-format
+ msgid "ISO C++ forbids compound-literals"
+ msgstr ""
+ 
+-#: cp/parser.c:6719
++#: cp/parser.c:6729
+ #, gcc-internal-format
+ msgid "two consecutive %<[%> shall only introduce an attribute"
+ msgstr ""
+ 
+-#: cp/parser.c:7119
++#: cp/parser.c:7129
+ #, gcc-internal-format
+ msgid "braced list index is not allowed with array notation"
+ msgstr ""
+ 
+-#: cp/parser.c:7212
++#: cp/parser.c:7222
+ #, gcc-internal-format
+ msgid "%qE does not have class type"
+ msgstr ""
+ 
+-#: cp/parser.c:7305 cp/typeck.c:2498
++#: cp/parser.c:7315 cp/typeck.c:2498
+ #, gcc-internal-format
+ msgid "invalid use of %qD"
+ msgstr ""
+ 
+-#: cp/parser.c:7314
++#: cp/parser.c:7324
+ #, gcc-internal-format
+ msgid "%<%D::%D%> is not a class member"
+ msgstr ""
+ 
+-#: cp/parser.c:7612
++#: cp/parser.c:7622
+ #, gcc-internal-format
+ msgid "non-scalar type"
+ msgstr ""
+ 
+-#: cp/parser.c:7711
++#: cp/parser.c:7721
+ #, gcc-internal-format
+ msgid "ISO C++ does not allow %<alignof%> with a non-type"
+ msgstr ""
+ 
+-#: cp/parser.c:7796
++#: cp/parser.c:7806
+ #, gcc-internal-format
+ msgid "types may not be defined in %<noexcept%> expressions"
+ msgstr ""
+ 
+-#: cp/parser.c:8074
++#: cp/parser.c:8084
+ #, gcc-internal-format
+ msgid "types may not be defined in a new-expression"
+ msgstr ""
+ 
+-#: cp/parser.c:8090
++#: cp/parser.c:8100
+ #, gcc-internal-format
+ msgid "array bound forbidden after parenthesized type-id"
+ msgstr ""
+ 
+-#: cp/parser.c:8092
++#: cp/parser.c:8102
+ #, gcc-internal-format
+ msgid "try removing the parentheses around the type-id"
+ msgstr ""
+ 
+-#: cp/parser.c:8123
++#: cp/parser.c:8133
+ #, gcc-internal-format
+ msgid ""
+ "initialization of new-expression for type %<auto%> requires exactly one "
+@@ -42366,94 +42455,94 @@
+ "element"
+ msgstr ""
+ 
+-#: cp/parser.c:8171
++#: cp/parser.c:8181
+ #, gcc-internal-format
+ msgid "expected expression-list or type-id"
+ msgstr ""
+ 
+-#: cp/parser.c:8200
++#: cp/parser.c:8210
+ #, gcc-internal-format
+ msgid "types may not be defined in a new-type-id"
+ msgstr ""
+ 
+-#: cp/parser.c:8328
++#: cp/parser.c:8338
+ #, gcc-internal-format
+ msgid "expression in new-declarator must have integral or enumeration type"
+ msgstr ""
+ 
+-#: cp/parser.c:8636
++#: cp/parser.c:8646
+ #, gcc-internal-format
+ msgid "use of old-style cast"
+ msgstr ""
+ 
+-#: cp/parser.c:8783
++#: cp/parser.c:8793
+ #, gcc-internal-format
+ msgid "%<>>%> operator is treated as two right angle brackets in C++11"
+ msgstr ""
+ 
+-#: cp/parser.c:8786
++#: cp/parser.c:8796
+ #, gcc-internal-format
+ msgid "suggest parentheses around %<>>%> expression"
+ msgstr ""
+ 
+-#: cp/parser.c:8982
++#: cp/parser.c:8992
+ #, gcc-internal-format
+ msgid "ISO C++ does not allow ?: with omitted middle operand"
+ msgstr ""
+ 
+-#: cp/parser.c:9690
++#: cp/parser.c:9700
+ #, gcc-internal-format
+ msgid "lambda-expression in unevaluated context"
+ msgstr ""
+ 
+-#: cp/parser.c:9699
++#: cp/parser.c:9709
+ #, gcc-internal-format
+ msgid "lambda-expression in template-argument"
+ msgstr ""
+ 
+-#: cp/parser.c:9852
++#: cp/parser.c:9862
+ #, gcc-internal-format
+ msgid "expected end of capture-list"
+ msgstr ""
+ 
+-#: cp/parser.c:9866
++#: cp/parser.c:9876
+ #, gcc-internal-format
+ msgid ""
+ "explicit by-copy capture of %<this%> redundant with by-copy capture default"
+ msgstr ""
+ 
+-#: cp/parser.c:9910
++#: cp/parser.c:9920
+ #, gcc-internal-format
+ msgid ""
+ "lambda capture initializers only available with -std=c++14 or -std=gnu++14"
+ msgstr ""
+ 
+-#: cp/parser.c:9917
++#: cp/parser.c:9927
+ #, gcc-internal-format
+ msgid "empty initializer for lambda init-capture"
+ msgstr ""
+ 
+-#: cp/parser.c:9940
++#: cp/parser.c:9950
+ #, gcc-internal-format
+ msgid "capture of non-variable %qD "
+ msgstr ""
+ 
+-#: cp/parser.c:9943 cp/parser.c:9953 cp/semantics.c:3364 cp/semantics.c:3374
++#: cp/parser.c:9953 cp/parser.c:9963 cp/semantics.c:3365 cp/semantics.c:3375
+ #, gcc-internal-format
+ msgid "%q#D declared here"
+ msgstr ""
+ 
+-#: cp/parser.c:9949
++#: cp/parser.c:9959
+ #, gcc-internal-format
+ msgid "capture of variable %qD with non-automatic storage duration"
+ msgstr ""
+ 
+-#: cp/parser.c:9987
++#: cp/parser.c:9997
+ #, gcc-internal-format
+ msgid "explicit by-copy capture of %qD redundant with by-copy capture default"
+ msgstr ""
+ 
+-#: cp/parser.c:9992
++#: cp/parser.c:10002
+ #, gcc-internal-format
+ msgid ""
+ "explicit by-reference capture of %qD redundant with by-reference capture "
+@@ -42460,62 +42549,62 @@
+ "default"
+ msgstr ""
+ 
+-#: cp/parser.c:10039
++#: cp/parser.c:10049
+ #, gcc-internal-format
+ msgid "lambda templates are only available with -std=c++14 or -std=gnu++14"
+ msgstr ""
+ 
+-#: cp/parser.c:10069
++#: cp/parser.c:10079
+ #, gcc-internal-format
+ msgid "default argument specified for lambda parameter"
+ msgstr ""
+ 
+-#: cp/parser.c:10548
++#: cp/parser.c:10558
+ #, gcc-internal-format
+ msgid "attributes at the beginning of statement are ignored"
+ msgstr ""
+ 
+-#: cp/parser.c:10576
++#: cp/parser.c:10586
+ #, gcc-internal-format
+ msgid "expected labeled-statement"
+ msgstr ""
+ 
+-#: cp/parser.c:10614
++#: cp/parser.c:10624
+ #, gcc-internal-format
+ msgid "case label %qE not within a switch statement"
+ msgstr ""
+ 
+-#: cp/parser.c:10699
++#: cp/parser.c:10709
+ #, gcc-internal-format
+ msgid "need %<typename%> before %qE because %qT is a dependent scope"
+ msgstr ""
+ 
+-#: cp/parser.c:10708
++#: cp/parser.c:10718
+ #, gcc-internal-format
+ msgid "%<%T::%D%> names the constructor, not the type"
+ msgstr ""
+ 
+-#: cp/parser.c:10755
++#: cp/parser.c:10765
+ #, gcc-internal-format
+ msgid "compound-statement in constexpr function"
+ msgstr ""
+ 
+-#: cp/parser.c:10997 cp/parser.c:27021
++#: cp/parser.c:11007 cp/parser.c:27036
+ #, gcc-internal-format
+ msgid "expected selection-statement"
+ msgstr ""
+ 
+-#: cp/parser.c:11030
++#: cp/parser.c:11040
+ #, gcc-internal-format
+ msgid "types may not be defined in conditions"
+ msgstr ""
+ 
+-#: cp/parser.c:11419
++#: cp/parser.c:11429
+ #, gcc-internal-format
+ msgid "range-based %<for%> expression of type %qT has incomplete type"
+ msgstr ""
+ 
+-#: cp/parser.c:11457
++#: cp/parser.c:11467
+ #, gcc-internal-format
+ msgid ""
+ "range-based %<for%> expression of type %qT has an %<end%> member but not a "
+@@ -42522,7 +42611,7 @@
+ "%<begin%>"
+ msgstr ""
+ 
+-#: cp/parser.c:11463
++#: cp/parser.c:11473
+ #, gcc-internal-format
+ msgid ""
+ "range-based %<for%> expression of type %qT has a %<begin%> member but not an "
+@@ -42529,80 +42618,80 @@
+ "%<end%>"
+ msgstr ""
+ 
+-#: cp/parser.c:11515
++#: cp/parser.c:11525
+ #, gcc-internal-format
+ msgid ""
+ "inconsistent begin/end types in range-based %<for%> statement: %qT and %qT"
+ msgstr ""
+ 
+-#: cp/parser.c:11650 cp/parser.c:27024
++#: cp/parser.c:11660 cp/parser.c:27039
+ #, gcc-internal-format
+ msgid "expected iteration-statement"
+ msgstr ""
+ 
+-#: cp/parser.c:11698
++#: cp/parser.c:11708
+ #, gcc-internal-format
+ msgid ""
+ "range-based %<for%> loops only available with -std=c++11 or -std=gnu++11"
+ msgstr ""
+ 
+-#: cp/parser.c:11772
++#: cp/parser.c:11782
+ #, gcc-internal-format
+ msgid "break statement used with Cilk Plus for loop"
+ msgstr ""
+ 
+-#: cp/parser.c:11829
++#: cp/parser.c:11839
+ #, gcc-internal-format
+ msgid "%<goto%> in %<constexpr%> function"
+ msgstr ""
+ 
+ #. Issue a warning about this use of a GNU extension.
+-#: cp/parser.c:11837
++#: cp/parser.c:11847
+ #, gcc-internal-format
+ msgid "ISO C++ forbids computed gotos"
+ msgstr ""
+ 
+-#: cp/parser.c:11850 cp/parser.c:27027
++#: cp/parser.c:11860 cp/parser.c:27042
+ #, gcc-internal-format
+ msgid "expected jump-statement"
+ msgstr ""
+ 
+-#: cp/parser.c:12007 cp/parser.c:22346
++#: cp/parser.c:12017 cp/parser.c:22356
+ #, gcc-internal-format
+ msgid "extra %<;%>"
+ msgstr ""
+ 
+-#: cp/parser.c:12247
++#: cp/parser.c:12257
+ #, gcc-internal-format
+ msgid "%<__label__%> not at the beginning of a block"
+ msgstr ""
+ 
+-#: cp/parser.c:12409
++#: cp/parser.c:12419
+ #, gcc-internal-format
+ msgid "inconsistent deduction for %qT: %qT and then %qT"
+ msgstr ""
+ 
+-#: cp/parser.c:12430
++#: cp/parser.c:12440
+ #, gcc-internal-format
+ msgid "mixing declarations and function-definitions is forbidden"
+ msgstr ""
+ 
+-#: cp/parser.c:12454
++#: cp/parser.c:12464
+ #, gcc-internal-format
+ msgid "types may not be defined in a for-range-declaration"
+ msgstr ""
+ 
+-#: cp/parser.c:12508
++#: cp/parser.c:12518
+ #, gcc-internal-format
+ msgid "initializer in range-based %<for%> loop"
+ msgstr ""
+ 
+-#: cp/parser.c:12511
++#: cp/parser.c:12521
+ #, gcc-internal-format
+ msgid "multiple declarations in range-based %<for%> loop"
+ msgstr ""
+ 
+-#: cp/parser.c:12652
++#: cp/parser.c:12662
+ #, gcc-internal-format
+ msgid "%<friend%> used outside of class"
+ msgstr ""
+@@ -42609,32 +42698,32 @@
+ 
+ #. Complain about `auto' as a storage specifier, if
+ #. we're complaining about C++0x compatibility.
+-#: cp/parser.c:12716
++#: cp/parser.c:12726
+ #, gcc-internal-format
+ msgid "%<auto%> changes meaning in C++11; please remove it"
+ msgstr ""
+ 
+-#: cp/parser.c:12752
++#: cp/parser.c:12762
+ #, gcc-internal-format
+ msgid "decl-specifier invalid in condition"
+ msgstr ""
+ 
+-#: cp/parser.c:12844
++#: cp/parser.c:12854
+ #, gcc-internal-format
+ msgid "class definition may not be declared a friend"
+ msgstr ""
+ 
+-#: cp/parser.c:12912 cp/parser.c:22753
++#: cp/parser.c:12922 cp/parser.c:22763
+ #, gcc-internal-format
+ msgid "templates may not be %<virtual%>"
+ msgstr ""
+ 
+-#: cp/parser.c:12952
++#: cp/parser.c:12962
+ #, gcc-internal-format
+ msgid "invalid linkage-specification"
+ msgstr ""
+ 
+-#: cp/parser.c:13039
++#: cp/parser.c:13049
+ #, gcc-internal-format
+ msgid ""
+ "static_assert without a message only available with -std=c++1z or -std=gnu+"
+@@ -42641,53 +42730,53 @@
+ "+1z"
+ msgstr ""
+ 
+-#: cp/parser.c:13233
++#: cp/parser.c:13243
+ #, gcc-internal-format
+ msgid "types may not be defined in %<decltype%> expressions"
+ msgstr ""
+ 
+-#: cp/parser.c:13376
++#: cp/parser.c:13386
+ #, gcc-internal-format
+ msgid "types may not be defined in a conversion-type-id"
+ msgstr ""
+ 
+-#: cp/parser.c:13403
++#: cp/parser.c:13413
+ #, gcc-internal-format
+ msgid "invalid use of %<auto%> in conversion operator"
+ msgstr ""
+ 
+-#: cp/parser.c:13407
++#: cp/parser.c:13417
+ #, gcc-internal-format
+ msgid ""
+ "use of %<auto%> in member template conversion operator can never be deduced"
+ msgstr ""
+ 
+-#: cp/parser.c:13496
++#: cp/parser.c:13506
+ #, gcc-internal-format
+ msgid "only constructors take member initializers"
+ msgstr ""
+ 
+-#: cp/parser.c:13518
++#: cp/parser.c:13528
+ #, gcc-internal-format
+ msgid "cannot expand initializer for member %<%D%>"
+ msgstr ""
+ 
+-#: cp/parser.c:13530
++#: cp/parser.c:13540
+ #, gcc-internal-format
+ msgid "mem-initializer for %qD follows constructor delegation"
+ msgstr ""
+ 
+-#: cp/parser.c:13542
++#: cp/parser.c:13552
+ #, gcc-internal-format
+ msgid "constructor delegation follows mem-initializer for %qD"
+ msgstr ""
+ 
+-#: cp/parser.c:13594
++#: cp/parser.c:13604
+ #, gcc-internal-format
+ msgid "anachronistic old-style base class initializer"
+ msgstr ""
+ 
+-#: cp/parser.c:13664
++#: cp/parser.c:13674
+ #, gcc-internal-format
+ msgid ""
+ "keyword %<typename%> not allowed in this context (a qualified member "
+@@ -42694,83 +42783,83 @@
+ "initializer is implicitly a type)"
+ msgstr ""
+ 
+-#: cp/parser.c:14024
++#: cp/parser.c:14034
+ #, gcc-internal-format
+ msgid "unexpected keyword; remove space between quotes and suffix identifier"
+ msgstr ""
+ 
+-#: cp/parser.c:14030
++#: cp/parser.c:14040
+ #, gcc-internal-format
+ msgid "expected suffix identifier"
+ msgstr ""
+ 
+-#: cp/parser.c:14039
++#: cp/parser.c:14049
+ #, gcc-internal-format
+ msgid "expected empty string after %<operator%> keyword"
+ msgstr ""
+ 
+-#: cp/parser.c:14045
++#: cp/parser.c:14055
+ #, gcc-internal-format
+ msgid "invalid encoding prefix in literal operator"
+ msgstr ""
+ 
+-#: cp/parser.c:14068
++#: cp/parser.c:14078
+ #, gcc-internal-format
+ msgid "expected operator"
+ msgstr ""
+ 
+ #. Warn that we do not support `export'.
+-#: cp/parser.c:14113
++#: cp/parser.c:14123
+ #, gcc-internal-format
+ msgid "keyword %<export%> not implemented, and will be ignored"
+ msgstr ""
+ 
+-#: cp/parser.c:14283
++#: cp/parser.c:14293
+ #, gcc-internal-format
+ msgid "invalid constrained type parameter"
+ msgstr ""
+ 
+-#: cp/parser.c:14291
++#: cp/parser.c:14301
+ #, gcc-internal-format
+ msgid "cv-qualified type parameter"
+ msgstr ""
+ 
+-#: cp/parser.c:14376
++#: cp/parser.c:14386
+ #, gcc-internal-format
+ msgid "variadic constraint introduced without %<...%>"
+ msgstr ""
+ 
+-#: cp/parser.c:14440
++#: cp/parser.c:14450
+ #, gcc-internal-format
+ msgid "invalid use of %<auto%> in default template argument"
+ msgstr ""
+ 
+-#: cp/parser.c:14675 cp/parser.c:14761 cp/parser.c:20621
++#: cp/parser.c:14685 cp/parser.c:14771 cp/parser.c:20631
+ #, gcc-internal-format
+ msgid "template parameter pack %qD cannot have a default argument"
+ msgstr ""
+ 
+-#: cp/parser.c:14679 cp/parser.c:14765
++#: cp/parser.c:14689 cp/parser.c:14775
+ #, gcc-internal-format
+ msgid "template parameter packs cannot have default arguments"
+ msgstr ""
+ 
+-#: cp/parser.c:14831
++#: cp/parser.c:14841
+ #, gcc-internal-format
+ msgid "expected template-id"
+ msgstr ""
+ 
+-#: cp/parser.c:14884 cp/parser.c:26985
++#: cp/parser.c:14894 cp/parser.c:27000
+ #, gcc-internal-format
+ msgid "expected %<<%>"
+ msgstr ""
+ 
+-#: cp/parser.c:14891
++#: cp/parser.c:14901
+ #, gcc-internal-format
+ msgid "%<<::%> cannot begin a template-argument list"
+ msgstr ""
+ 
+-#: cp/parser.c:14895
++#: cp/parser.c:14905
+ #, gcc-internal-format
+ msgid ""
+ "%<<:%> is an alternate spelling for %<[%>. Insert whitespace between %<<%> "
+@@ -42777,7 +42866,7 @@
+ "and %<::%>"
+ msgstr ""
+ 
+-#: cp/parser.c:14899
++#: cp/parser.c:14909
+ #, gcc-internal-format
+ msgid ""
+ "(if you use %<-fpermissive%> or %<-std=c++11%>, or %<-std=gnu++11%> G++ will "
+@@ -42784,64 +42873,64 @@
+ "accept your code)"
+ msgstr ""
+ 
+-#: cp/parser.c:15006
++#: cp/parser.c:15016
+ #, gcc-internal-format
+ msgid "parse error in template argument list"
+ msgstr ""
+ 
+ #. The name does not name a template.
+-#: cp/parser.c:15075 cp/parser.c:15196 cp/parser.c:15411
++#: cp/parser.c:15085 cp/parser.c:15206 cp/parser.c:15421
+ #, gcc-internal-format
+ msgid "expected template-name"
+ msgstr ""
+ 
+ #. Explain what went wrong.
+-#: cp/parser.c:15121
++#: cp/parser.c:15131
+ #, gcc-internal-format
+ msgid "non-template %qD used as template"
+ msgstr ""
+ 
+-#: cp/parser.c:15123
++#: cp/parser.c:15133
+ #, gcc-internal-format
+ msgid "use %<%T::template %D%> to indicate that it is a template"
+ msgstr ""
+ 
+-#: cp/parser.c:15263
++#: cp/parser.c:15273
+ #, gcc-internal-format
+ msgid "expected parameter pack before %<...%>"
+ msgstr ""
+ 
+-#: cp/parser.c:15372 cp/parser.c:15390 cp/parser.c:15557
++#: cp/parser.c:15382 cp/parser.c:15400 cp/parser.c:15567
+ #, gcc-internal-format
+ msgid "expected template-argument"
+ msgstr ""
+ 
+-#: cp/parser.c:15532
++#: cp/parser.c:15542
+ #, gcc-internal-format
+ msgid "invalid non-type template argument"
+ msgstr ""
+ 
+-#: cp/parser.c:15659
++#: cp/parser.c:15669
+ #, gcc-internal-format
+ msgid "explicit instantiation shall not use %<inline%> specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:15663
++#: cp/parser.c:15673
+ #, gcc-internal-format
+ msgid "explicit instantiation shall not use %<constexpr%> specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:15722
++#: cp/parser.c:15732
+ #, gcc-internal-format
+ msgid "template specialization with C linkage"
+ msgstr ""
+ 
+-#: cp/parser.c:15942
++#: cp/parser.c:15952
+ #, gcc-internal-format
+ msgid "expected type specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:16122
++#: cp/parser.c:16132
+ #, gcc-internal-format
+ msgid ""
+ "use of %<auto%> in lambda parameter declaration only available with -std=c+"
+@@ -42848,7 +42937,7 @@
+ "+14 or -std=gnu++14"
+ msgstr ""
+ 
+-#: cp/parser.c:16128
++#: cp/parser.c:16138
+ #, gcc-internal-format
+ msgid ""
+ "use of %<auto%> in parameter declaration only available with -std=c++14 or -"
+@@ -42855,43 +42944,43 @@
+ "std=gnu++14"
+ msgstr ""
+ 
+-#: cp/parser.c:16133
++#: cp/parser.c:16143
+ #, gcc-internal-format
+ msgid "ISO C++ forbids use of %<auto%> in parameter declaration"
+ msgstr ""
+ 
+-#: cp/parser.c:16277
++#: cp/parser.c:16287
+ #, gcc-internal-format
+ msgid "expected template-id for type"
+ msgstr ""
+ 
+-#: cp/parser.c:16304
++#: cp/parser.c:16314
+ #, gcc-internal-format
+ msgid "expected type-name"
+ msgstr ""
+ 
+-#: cp/parser.c:16653
++#: cp/parser.c:16663
+ #, gcc-internal-format
+ msgid ""
+ "elaborated-type-specifier for a scoped enum must not use the %<%D%> keyword"
+ msgstr ""
+ 
+-#: cp/parser.c:16862
++#: cp/parser.c:16872
+ #, gcc-internal-format
+ msgid "declaration %qD does not declare anything"
+ msgstr ""
+ 
+-#: cp/parser.c:16949
++#: cp/parser.c:16959
+ #, gcc-internal-format
+ msgid "attributes ignored on uninstantiated type"
+ msgstr ""
+ 
+-#: cp/parser.c:16953
++#: cp/parser.c:16963
+ #, gcc-internal-format
+ msgid "attributes ignored on template instantiation"
+ msgstr ""
+ 
+-#: cp/parser.c:16958
++#: cp/parser.c:16968
+ #, gcc-internal-format
+ msgid ""
+ "attributes ignored on elaborated-type-specifier that is not a forward "
+@@ -42898,32 +42987,32 @@
+ "declaration"
+ msgstr ""
+ 
+-#: cp/parser.c:17092
++#: cp/parser.c:17102
+ #, gcc-internal-format
+ msgid "%qD is an enumeration template"
+ msgstr ""
+ 
+-#: cp/parser.c:17103
++#: cp/parser.c:17113
+ #, gcc-internal-format
+ msgid "%qD does not name an enumeration in %qT"
+ msgstr ""
+ 
+-#: cp/parser.c:17118
++#: cp/parser.c:17128
+ #, gcc-internal-format
+ msgid "anonymous scoped enum is not allowed"
+ msgstr ""
+ 
+-#: cp/parser.c:17173
++#: cp/parser.c:17183
+ #, gcc-internal-format
+ msgid "expected %<;%> or %<{%>"
+ msgstr ""
+ 
+-#: cp/parser.c:17222
++#: cp/parser.c:17232
+ #, gcc-internal-format
+ msgid "cannot add an enumerator list to a template instantiation"
+ msgstr ""
+ 
+-#: cp/parser.c:17236
++#: cp/parser.c:17246
+ #, gcc-internal-format
+ msgid ""
+ "nested name specifier %qT for enum declaration does not name a class or "
+@@ -42930,83 +43019,83 @@
+ "namespace"
+ msgstr ""
+ 
+-#: cp/parser.c:17248 cp/parser.c:21857
++#: cp/parser.c:17258 cp/parser.c:21867
+ #, gcc-internal-format
+ msgid "declaration of %qD in namespace %qD which does not enclose %qD"
+ msgstr ""
+ 
+-#: cp/parser.c:17253 cp/parser.c:21862
++#: cp/parser.c:17263 cp/parser.c:21872
+ #, gcc-internal-format
+ msgid "declaration of %qD in %qD which does not enclose %qD"
+ msgstr ""
+ 
+-#: cp/parser.c:17278
++#: cp/parser.c:17288
+ #, gcc-internal-format
+ msgid "multiple definition of %q#T"
+ msgstr ""
+ 
+-#: cp/parser.c:17291
++#: cp/parser.c:17301
+ #, gcc-internal-format
+ msgid "ISO C++ forbids empty anonymous enum"
+ msgstr ""
+ 
+-#: cp/parser.c:17311
++#: cp/parser.c:17321
+ #, gcc-internal-format
+ msgid "opaque-enum-specifier without name"
+ msgstr ""
+ 
+-#: cp/parser.c:17314
++#: cp/parser.c:17324
+ #, gcc-internal-format
+ msgid "opaque-enum-specifier must use a simple identifier"
+ msgstr ""
+ 
+-#: cp/parser.c:17492
++#: cp/parser.c:17502
+ #, gcc-internal-format
+ msgid "%qD is not a namespace-name"
+ msgstr ""
+ 
+-#: cp/parser.c:17493
++#: cp/parser.c:17503
+ #, gcc-internal-format
+ msgid "expected namespace-name"
+ msgstr ""
+ 
+-#: cp/parser.c:17571
++#: cp/parser.c:17581
+ #, gcc-internal-format
+ msgid "a nested namespace definition cannot have attributes"
+ msgstr ""
+ 
+-#: cp/parser.c:17574
++#: cp/parser.c:17584
+ #, gcc-internal-format
+ msgid ""
+ "nested namespace definitions only available with -std=c++1z or -std=gnu++1z"
+ msgstr ""
+ 
+-#: cp/parser.c:17577
++#: cp/parser.c:17587
+ #, gcc-internal-format
+ msgid "a nested namespace definition cannot be inline"
+ msgstr ""
+ 
+-#: cp/parser.c:17585
++#: cp/parser.c:17595
+ #, gcc-internal-format
+ msgid "nested identifier required"
+ msgstr ""
+ 
+-#: cp/parser.c:17613
++#: cp/parser.c:17623
+ #, gcc-internal-format
+ msgid "namespace %qD entered"
+ msgstr ""
+ 
+-#: cp/parser.c:17665
++#: cp/parser.c:17675
+ #, gcc-internal-format
+ msgid "%<namespace%> definition is not allowed here"
+ msgstr ""
+ 
+-#: cp/parser.c:17820
++#: cp/parser.c:17830
+ #, gcc-internal-format
+ msgid "a template-id may not appear in a using-declaration"
+ msgstr ""
+ 
+-#: cp/parser.c:17866
++#: cp/parser.c:17876
+ #, gcc-internal-format
+ msgid ""
+ "access declarations are deprecated in favour of using-declarations; "
+@@ -43013,78 +43102,78 @@
+ "suggestion: add the %<using%> keyword"
+ msgstr ""
+ 
+-#: cp/parser.c:17931
++#: cp/parser.c:17941
+ #, gcc-internal-format
+ msgid "types may not be defined in alias template declarations"
+ msgstr ""
+ 
+-#: cp/parser.c:18084
++#: cp/parser.c:18094
+ #, gcc-internal-format
+ msgid "%<asm%> in %<constexpr%> function"
+ msgstr ""
+ 
+-#: cp/parser.c:18450
++#: cp/parser.c:18460
+ #, gcc-internal-format
+ msgid "a function-definition is not allowed here"
+ msgstr ""
+ 
+-#: cp/parser.c:18461
++#: cp/parser.c:18471
+ #, gcc-internal-format
+ msgid "an asm-specification is not allowed on a function-definition"
+ msgstr ""
+ 
+-#: cp/parser.c:18465
++#: cp/parser.c:18475
+ #, gcc-internal-format
+ msgid "attributes are not allowed on a function-definition"
+ msgstr ""
+ 
+-#: cp/parser.c:18516
++#: cp/parser.c:18526
+ #, gcc-internal-format
+ msgid "expected constructor, destructor, or type conversion"
+ msgstr ""
+ 
+ #. Anything else is an error.
+-#: cp/parser.c:18555 cp/parser.c:20812
++#: cp/parser.c:18565 cp/parser.c:20822
+ #, gcc-internal-format
+ msgid "expected initializer"
+ msgstr ""
+ 
+-#: cp/parser.c:18636
++#: cp/parser.c:18646
+ #, gcc-internal-format
+ msgid "initializer provided for function"
+ msgstr ""
+ 
+-#: cp/parser.c:18670
++#: cp/parser.c:18680
+ #, gcc-internal-format
+ msgid "attributes after parenthesized initializer ignored"
+ msgstr ""
+ 
+-#: cp/parser.c:18675
++#: cp/parser.c:18685
+ #, gcc-internal-format
+ msgid "non-function %qD declared as implicit template"
+ msgstr ""
+ 
+-#: cp/parser.c:19124
++#: cp/parser.c:19134
+ #, gcc-internal-format
+ msgid "array bound is not an integer constant"
+ msgstr ""
+ 
+-#: cp/parser.c:19250
++#: cp/parser.c:19260
+ #, gcc-internal-format
+ msgid "cannot define member of dependent typedef %qT"
+ msgstr ""
+ 
+-#: cp/parser.c:19254
++#: cp/parser.c:19264
+ #, gcc-internal-format
+ msgid "%<%T::%E%> is not a type"
+ msgstr ""
+ 
+-#: cp/parser.c:19282
++#: cp/parser.c:19292
+ #, gcc-internal-format
+ msgid "invalid use of constructor as a template"
+ msgstr ""
+ 
+-#: cp/parser.c:19284
++#: cp/parser.c:19294
+ #, gcc-internal-format
+ msgid ""
+ "use %<%T::%D%> instead of %<%T::%D%> to name the constructor in a qualified "
+@@ -43095,7 +43184,7 @@
+ #. here because we do not have enough
+ #. information about its original syntactic
+ #. form.
+-#: cp/parser.c:19301
++#: cp/parser.c:19311
+ #, gcc-internal-format
+ msgid "invalid declarator"
+ msgstr ""
+@@ -43102,187 +43191,187 @@
+ 
+ #. But declarations with qualified-ids can't appear in a
+ #. function.
+-#: cp/parser.c:19371
++#: cp/parser.c:19381
+ #, gcc-internal-format
+ msgid "qualified-id in declaration"
+ msgstr ""
+ 
+-#: cp/parser.c:19396
++#: cp/parser.c:19406
+ #, gcc-internal-format
+ msgid "expected declarator"
+ msgstr ""
+ 
+-#: cp/parser.c:19499
++#: cp/parser.c:19509
+ #, gcc-internal-format
+ msgid "%qD is a namespace"
+ msgstr ""
+ 
+-#: cp/parser.c:19501
++#: cp/parser.c:19511
+ #, gcc-internal-format
+ msgid "cannot form pointer to member of non-class %q#T"
+ msgstr ""
+ 
+-#: cp/parser.c:19522
++#: cp/parser.c:19532
+ #, gcc-internal-format
+ msgid "expected ptr-operator"
+ msgstr ""
+ 
+-#: cp/parser.c:19581
++#: cp/parser.c:19591
+ #, gcc-internal-format
+ msgid "duplicate cv-qualifier"
+ msgstr ""
+ 
+-#: cp/parser.c:19635
++#: cp/parser.c:19645
+ #, gcc-internal-format
+ msgid "multiple ref-qualifiers"
+ msgstr ""
+ 
+-#: cp/parser.c:19672
++#: cp/parser.c:19682
+ #, gcc-internal-format
+ msgid "%E requires %<-fgnu-tm%>"
+ msgstr ""
+ 
+-#: cp/parser.c:19728
++#: cp/parser.c:19738
+ #, gcc-internal-format
+ msgid "duplicate virt-specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:19958 cp/typeck2.c:529 cp/typeck2.c:1953
++#: cp/parser.c:19968 cp/typeck2.c:529 cp/typeck2.c:1953
+ #, gcc-internal-format
+ msgid "invalid use of %<auto%>"
+ msgstr ""
+ 
+-#: cp/parser.c:19979
++#: cp/parser.c:19989
+ #, gcc-internal-format
+ msgid "types may not be defined in template arguments"
+ msgstr ""
+ 
+-#: cp/parser.c:19984
++#: cp/parser.c:19994
+ #, gcc-internal-format
+ msgid "invalid use of %<auto%> in template argument"
+ msgstr ""
+ 
+-#: cp/parser.c:20072
++#: cp/parser.c:20082
+ #, gcc-internal-format
+ msgid "expected type-specifier"
+ msgstr ""
+ 
+-#: cp/parser.c:20378
++#: cp/parser.c:20388
+ #, gcc-internal-format
+ msgid "expected %<,%> or %<...%>"
+ msgstr ""
+ 
+-#: cp/parser.c:20453
++#: cp/parser.c:20463
+ #, gcc-internal-format
+ msgid "types may not be defined in parameter types"
+ msgstr ""
+ 
+-#: cp/parser.c:20605
++#: cp/parser.c:20615
+ #, gcc-internal-format
+ msgid "default arguments are only permitted for function parameters"
+ msgstr ""
+ 
+-#: cp/parser.c:20623
++#: cp/parser.c:20633
+ #, gcc-internal-format
+ msgid "parameter pack %qD cannot have a default argument"
+ msgstr ""
+ 
+-#: cp/parser.c:20629
++#: cp/parser.c:20639
+ #, gcc-internal-format
+ msgid "template parameter pack cannot have a default argument"
+ msgstr ""
+ 
+-#: cp/parser.c:20631
++#: cp/parser.c:20641
+ #, gcc-internal-format
+ msgid "parameter pack cannot have a default argument"
+ msgstr ""
+ 
+-#: cp/parser.c:21015
++#: cp/parser.c:21025
+ #, gcc-internal-format
+ msgid "ISO C++ does not allow designated initializers"
+ msgstr ""
+ 
+-#: cp/parser.c:21029
++#: cp/parser.c:21039
+ #, gcc-internal-format
+ msgid "ISO C++ does not allow C99 designated initializers"
+ msgstr ""
+ 
+-#: cp/parser.c:21149 cp/parser.c:21275
++#: cp/parser.c:21159 cp/parser.c:21285
+ #, gcc-internal-format
+ msgid "expected class-name"
+ msgstr ""
+ 
+-#: cp/parser.c:21462
++#: cp/parser.c:21472
+ #, gcc-internal-format
+ msgid "expected %<;%> after class definition"
+ msgstr ""
+ 
+-#: cp/parser.c:21464
++#: cp/parser.c:21474
+ #, gcc-internal-format
+ msgid "expected %<;%> after struct definition"
+ msgstr ""
+ 
+-#: cp/parser.c:21466
++#: cp/parser.c:21476
+ #, gcc-internal-format
+ msgid "expected %<;%> after union definition"
+ msgstr ""
+ 
+-#: cp/parser.c:21805
++#: cp/parser.c:21815
+ #, gcc-internal-format
+ msgid "expected %<{%> or %<:%>"
+ msgstr ""
+ 
+-#: cp/parser.c:21816
++#: cp/parser.c:21826
+ #, gcc-internal-format
+ msgid "cannot specify %<override%> for a class"
+ msgstr ""
+ 
+-#: cp/parser.c:21824
++#: cp/parser.c:21834
+ #, gcc-internal-format
+ msgid "global qualification of class name is invalid"
+ msgstr ""
+ 
+-#: cp/parser.c:21831
++#: cp/parser.c:21841
+ #, gcc-internal-format
+ msgid "qualified name does not name a class"
+ msgstr ""
+ 
+-#: cp/parser.c:21843
++#: cp/parser.c:21853
+ #, gcc-internal-format
+ msgid "invalid class name in declaration of %qD"
+ msgstr ""
+ 
+-#: cp/parser.c:21876
++#: cp/parser.c:21886
+ #, gcc-internal-format
+ msgid "extra qualification not allowed"
+ msgstr ""
+ 
+-#: cp/parser.c:21888
++#: cp/parser.c:21898
+ #, gcc-internal-format
+ msgid "an explicit specialization must be preceded by %<template <>%>"
+ msgstr ""
+ 
+-#: cp/parser.c:21918
++#: cp/parser.c:21928
+ #, gcc-internal-format
+ msgid "function template %qD redeclared as a class template"
+ msgstr ""
+ 
+-#: cp/parser.c:21949
++#: cp/parser.c:21959
+ #, gcc-internal-format
+ msgid "could not resolve typename type"
+ msgstr ""
+ 
+-#: cp/parser.c:22005
++#: cp/parser.c:22015
+ #, gcc-internal-format
+ msgid "previous definition of %q+#T"
+ msgstr ""
+ 
+-#: cp/parser.c:22096 cp/parser.c:27030
++#: cp/parser.c:22106 cp/parser.c:27045
+ #, gcc-internal-format
+ msgid "expected class-key"
+ msgstr ""
+ 
+-#: cp/parser.c:22120
++#: cp/parser.c:22130
+ #, gcc-internal-format
+ msgid ""
+ "ISO C++ forbids typename key in template template parameter; use -std=c++1z "
+@@ -43289,67 +43378,67 @@
+ "or -std=gnu++1z"
+ msgstr ""
+ 
+-#: cp/parser.c:22124
++#: cp/parser.c:22134
+ #, gcc-internal-format
+ msgid "expected %<class%> or %<typename%>"
+ msgstr ""
+ 
+-#: cp/parser.c:22366
++#: cp/parser.c:22376
+ #, gcc-internal-format
+ msgid "in C++03 a class-key must be used when declaring a friend"
+ msgstr ""
+ 
+-#: cp/parser.c:22384
++#: cp/parser.c:22394
+ #, gcc-internal-format
+ msgid "friend declaration does not name a class or function"
+ msgstr ""
+ 
+-#: cp/parser.c:22402
++#: cp/parser.c:22412
+ #, gcc-internal-format
+ msgid "a storage class on an anonymous aggregate in class scope is not allowed"
+ msgstr ""
+ 
+-#: cp/parser.c:22606
++#: cp/parser.c:22616
+ #, gcc-internal-format
+ msgid "pure-specifier on function-definition"
+ msgstr ""
+ 
+-#: cp/parser.c:22661
++#: cp/parser.c:22671
+ #, gcc-internal-format
+ msgid "stray %<,%> at end of member declaration"
+ msgstr ""
+ 
+-#: cp/parser.c:22673
++#: cp/parser.c:22683
+ #, gcc-internal-format
+ msgid "expected %<;%> at end of member declaration"
+ msgstr ""
+ 
+-#: cp/parser.c:22747
++#: cp/parser.c:22757
+ #, gcc-internal-format
+ msgid "invalid pure specifier (only %<= 0%> is allowed)"
+ msgstr ""
+ 
+-#: cp/parser.c:22782
++#: cp/parser.c:22792
+ #, gcc-internal-format
+ msgid "a brace-enclosed initializer is not allowed here"
+ msgstr ""
+ 
+-#: cp/parser.c:22911
++#: cp/parser.c:22921
+ #, gcc-internal-format
+ msgid "%<virtual%> specified more than once in base-specified"
+ msgstr ""
+ 
+-#: cp/parser.c:22931
++#: cp/parser.c:22941
+ #, gcc-internal-format
+ msgid "more than one access specifier in base-specified"
+ msgstr ""
+ 
+-#: cp/parser.c:22955
++#: cp/parser.c:22965
+ #, gcc-internal-format
+ msgid "keyword %<typename%> not allowed outside of templates"
+ msgstr ""
+ 
+-#: cp/parser.c:22958
++#: cp/parser.c:22968
+ #, gcc-internal-format
+ msgid ""
+ "keyword %<typename%> not allowed in this context (the base class is "
+@@ -43356,12 +43445,12 @@
+ "implicitly a type)"
+ msgstr ""
+ 
+-#: cp/parser.c:23051 cp/parser.c:23133
++#: cp/parser.c:23061 cp/parser.c:23143
+ #, gcc-internal-format
+ msgid "types may not be defined in an exception-specification"
+ msgstr ""
+ 
+-#: cp/parser.c:23115
++#: cp/parser.c:23125
+ #, gcc-internal-format
+ msgid ""
+ "dynamic exception specifications are deprecated in C++0x; use %<noexcept%> "
+@@ -43368,62 +43457,67 @@
+ "instead"
+ msgstr ""
+ 
+-#: cp/parser.c:23175
++#: cp/parser.c:23185
+ #, gcc-internal-format
+ msgid "invalid use of %<auto%> in exception-specification"
+ msgstr ""
+ 
+-#: cp/parser.c:23214
++#: cp/parser.c:23224
+ #, gcc-internal-format
+ msgid "%<try%> in %<constexpr%> function"
+ msgstr ""
+ 
+-#: cp/parser.c:23327
++#: cp/parser.c:23337
+ #, gcc-internal-format
+ msgid "types may not be defined in exception-declarations"
+ msgstr ""
+ 
+-#: cp/parser.c:23939
++#: cp/parser.c:23949
+ #, gcc-internal-format
+ msgid "expected an identifier for the attribute name"
+ msgstr ""
+ 
+-#: cp/parser.c:23958
++#: cp/parser.c:23968
+ #, gcc-internal-format
+ msgid "%<deprecated%> is a C++14 feature; use %<gnu::deprecated%>"
+ msgstr ""
+ 
+-#: cp/parser.c:24020
++#: cp/parser.c:24030
+ #, gcc-internal-format
+ msgid "attribute noreturn can appear at most once in an attribute-list"
+ msgstr ""
+ 
+-#: cp/parser.c:24024
++#: cp/parser.c:24034
+ #, gcc-internal-format
+ msgid "attribute deprecated can appear at most once in an attribute-list"
+ msgstr ""
+ 
+-#: cp/parser.c:24295
++#: cp/parser.c:24071
+ #, gcc-internal-format
++msgid "expected attribute before %<...%>"
++msgstr ""
++
++#: cp/parser.c:24309
++#, gcc-internal-format
+ msgid "%<requires%> only available with -fconcepts"
+ msgstr ""
+ 
+-#: cp/parser.c:24327
++#: cp/parser.c:24341
+ #, gcc-internal-format
+ msgid "a requires expression cannot appear outside a template"
+ msgstr ""
+ 
+-#: cp/parser.c:25037
++#: cp/parser.c:25051
+ #, gcc-internal-format
+ msgid "specializing member %<%T::%E%> requires %<template<>%> syntax"
+ msgstr ""
+ 
+-#: cp/parser.c:25042
++#: cp/parser.c:25056
+ #, gcc-internal-format
+ msgid "invalid declaration of %<%T::%E%>"
+ msgstr ""
+ 
+-#: cp/parser.c:25046
++#: cp/parser.c:25060
+ #, gcc-internal-format
+ msgid "too few template-parameter-lists"
+ msgstr ""
+@@ -43432,17 +43526,17 @@
+ #. something like:
+ #.
+ #. template <class T> template <class U> void S::f();
+-#: cp/parser.c:25053
++#: cp/parser.c:25067
+ #, gcc-internal-format
+ msgid "too many template-parameter-lists"
+ msgstr ""
+ 
+-#: cp/parser.c:25379
++#: cp/parser.c:25393
+ #, gcc-internal-format
+ msgid "named return values are no longer supported"
+ msgstr ""
+ 
+-#: cp/parser.c:25544
++#: cp/parser.c:25559
+ #, gcc-internal-format
+ msgid ""
+ "literal operator template %qD has invalid parameter list.  Expected non-type "
+@@ -43449,7 +43543,7 @@
+ "template argument pack <char...> or <typename CharT, CharT...>"
+ msgstr ""
+ 
+-#: cp/parser.c:25549
++#: cp/parser.c:25564
+ #, gcc-internal-format
+ msgid ""
+ "literal operator template %qD has invalid parameter list.  Expected non-type "
+@@ -43456,355 +43550,355 @@
+ "template argument pack <char...>"
+ msgstr ""
+ 
+-#: cp/parser.c:25618
++#: cp/parser.c:25633
+ #, gcc-internal-format
+ msgid "empty introduction-list"
+ msgstr ""
+ 
+-#: cp/parser.c:25642
++#: cp/parser.c:25657
+ #, gcc-internal-format
+ msgid "no matching concept for template-introduction"
+ msgstr ""
+ 
+-#: cp/parser.c:25664
++#: cp/parser.c:25679
+ #, gcc-internal-format
+ msgid "invalid declaration of member template in local class"
+ msgstr ""
+ 
+-#: cp/parser.c:25673
++#: cp/parser.c:25688
+ #, gcc-internal-format
+ msgid "template with C linkage"
+ msgstr ""
+ 
+-#: cp/parser.c:25692
++#: cp/parser.c:25707
+ #, gcc-internal-format
+ msgid "invalid explicit specialization"
+ msgstr ""
+ 
+-#: cp/parser.c:25796
++#: cp/parser.c:25811
+ #, gcc-internal-format
+ msgid "template declaration of %<typedef%>"
+ msgstr ""
+ 
+-#: cp/parser.c:25847
++#: cp/parser.c:25862
+ #, gcc-internal-format
+ msgid "a class template declaration must not declare anything else"
+ msgstr ""
+ 
+-#: cp/parser.c:25893
++#: cp/parser.c:25908
+ #, gcc-internal-format
+ msgid "explicit template specialization cannot have a storage class"
+ msgstr ""
+ 
+-#: cp/parser.c:26199
++#: cp/parser.c:26214
+ #, gcc-internal-format
+ msgid "%<>>%> should be %<> >%> within a nested template argument list"
+ msgstr ""
+ 
+-#: cp/parser.c:26212
++#: cp/parser.c:26227
+ #, gcc-internal-format
+ msgid "spurious %<>>%>, use %<>%> to terminate a template argument list"
+ msgstr ""
+ 
+-#: cp/parser.c:26509
++#: cp/parser.c:26524
+ #, gcc-internal-format
+ msgid "%<sizeof...%> argument must be surrounded by parentheses"
+ msgstr ""
+ 
+-#: cp/parser.c:26665
++#: cp/parser.c:26680
+ #, gcc-internal-format
+ msgid "invalid use of %qD in linkage specification"
+ msgstr ""
+ 
+-#: cp/parser.c:26680
++#: cp/parser.c:26695
+ #, gcc-internal-format
+ msgid "%<__thread%> before %qD"
+ msgstr ""
+ 
+-#: cp/parser.c:26814
++#: cp/parser.c:26829
+ #, gcc-internal-format
+ msgid "ISO C++ 1998 does not support %<long long%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26822
++#: cp/parser.c:26837
+ #, gcc-internal-format
+ msgid "both %<__thread%> and %<thread_local%> specified"
+ msgstr ""
+ 
+-#: cp/parser.c:26824
++#: cp/parser.c:26839
+ #, gcc-internal-format
+ msgid "duplicate %qD"
+ msgstr ""
+ 
+-#: cp/parser.c:26846
++#: cp/parser.c:26861
+ #, gcc-internal-format
+ msgid "duplicate %qs"
+ msgstr ""
+ 
+-#: cp/parser.c:26888
++#: cp/parser.c:26903
+ #, gcc-internal-format
+ msgid "expected %<new%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26891
++#: cp/parser.c:26906
+ #, gcc-internal-format
+ msgid "expected %<delete%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26894
++#: cp/parser.c:26909
+ #, gcc-internal-format
+ msgid "expected %<return%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26900
++#: cp/parser.c:26915
+ #, gcc-internal-format
+ msgid "expected %<extern%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26903
++#: cp/parser.c:26918
+ #, gcc-internal-format
+ msgid "expected %<static_assert%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26906
++#: cp/parser.c:26921
+ #, gcc-internal-format
+ msgid "expected %<decltype%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26909
++#: cp/parser.c:26924
+ #, gcc-internal-format
+ msgid "expected %<operator%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26912
++#: cp/parser.c:26927
+ #, gcc-internal-format
+ msgid "expected %<class%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26915
++#: cp/parser.c:26930
+ #, gcc-internal-format
+ msgid "expected %<template%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26918
++#: cp/parser.c:26933
+ #, gcc-internal-format
+ msgid "expected %<namespace%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26921
++#: cp/parser.c:26936
+ #, gcc-internal-format
+ msgid "expected %<using%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26924
++#: cp/parser.c:26939
+ #, gcc-internal-format
+ msgid "expected %<asm%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26927
++#: cp/parser.c:26942
+ #, gcc-internal-format
+ msgid "expected %<try%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26930
++#: cp/parser.c:26945
+ #, gcc-internal-format
+ msgid "expected %<catch%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26933
++#: cp/parser.c:26948
+ #, gcc-internal-format
+ msgid "expected %<throw%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26936
++#: cp/parser.c:26951
+ #, gcc-internal-format
+ msgid "expected %<__label__%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26939
++#: cp/parser.c:26954
+ #, gcc-internal-format
+ msgid "expected %<@try%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26942
++#: cp/parser.c:26957
+ #, gcc-internal-format
+ msgid "expected %<@synchronized%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26945
++#: cp/parser.c:26960
+ #, gcc-internal-format
+ msgid "expected %<@throw%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26948
++#: cp/parser.c:26963
+ #, gcc-internal-format
+ msgid "expected %<__transaction_atomic%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26951
++#: cp/parser.c:26966
+ #, gcc-internal-format
+ msgid "expected %<__transaction_relaxed%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26982
++#: cp/parser.c:26997
+ #, gcc-internal-format
+ msgid "expected %<::%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26994
++#: cp/parser.c:27009
+ #, gcc-internal-format
+ msgid "expected %<...%>"
+ msgstr ""
+ 
+-#: cp/parser.c:26997
++#: cp/parser.c:27012
+ #, gcc-internal-format
+ msgid "expected %<*%>"
+ msgstr ""
+ 
+-#: cp/parser.c:27000
++#: cp/parser.c:27015
+ #, gcc-internal-format
+ msgid "expected %<~%>"
+ msgstr ""
+ 
+-#: cp/parser.c:27006
++#: cp/parser.c:27021
+ #, gcc-internal-format
+ msgid "expected %<:%> or %<::%>"
+ msgstr ""
+ 
+-#: cp/parser.c:27034
++#: cp/parser.c:27049
+ #, gcc-internal-format
+ msgid "expected %<class%>, %<typename%>, or %<template%>"
+ msgstr ""
+ 
+-#: cp/parser.c:27295
++#: cp/parser.c:27310
+ #, gcc-internal-format
+ msgid "%qs tag used in naming %q#T"
+ msgstr ""
+ 
+-#: cp/parser.c:27300
++#: cp/parser.c:27315
+ #, gcc-internal-format
+ msgid "%q#T was previously declared here"
+ msgstr ""
+ 
+-#: cp/parser.c:27319
++#: cp/parser.c:27334
+ #, gcc-internal-format
+ msgid "%qD redeclared with different access"
+ msgstr ""
+ 
+-#: cp/parser.c:27340
++#: cp/parser.c:27355
+ #, gcc-internal-format
+ msgid ""
+ "in C++98 %<template%> (as a disambiguator) is only allowed within templates"
+ msgstr ""
+ 
+-#: cp/parser.c:27581
++#: cp/parser.c:27596
+ #, gcc-internal-format
+ msgid "file ends in default argument"
+ msgstr ""
+ 
+-#: cp/parser.c:27810 cp/parser.c:29119 cp/parser.c:29305
++#: cp/parser.c:27825 cp/parser.c:29134 cp/parser.c:29320
+ #, gcc-internal-format
+ msgid "misplaced %<@%D%> Objective-C++ construct"
+ msgstr ""
+ 
+-#: cp/parser.c:27879
++#: cp/parser.c:27894
+ #, gcc-internal-format
+ msgid "objective-c++ message receiver expected"
+ msgstr ""
+ 
+-#: cp/parser.c:27949
++#: cp/parser.c:27964
+ #, gcc-internal-format
+ msgid "objective-c++ message argument(s) are expected"
+ msgstr ""
+ 
+-#: cp/parser.c:27979
++#: cp/parser.c:27994
+ #, gcc-internal-format
+ msgid "%<@encode%> must specify a type as an argument"
+ msgstr ""
+ 
+-#: cp/parser.c:28385
++#: cp/parser.c:28400
+ #, gcc-internal-format
+ msgid "invalid Objective-C++ selector name"
+ msgstr ""
+ 
+-#: cp/parser.c:28460 cp/parser.c:28478
++#: cp/parser.c:28475 cp/parser.c:28493
+ #, gcc-internal-format
+ msgid "objective-c++ method declaration is expected"
+ msgstr ""
+ 
+-#: cp/parser.c:28472 cp/parser.c:28537
++#: cp/parser.c:28487 cp/parser.c:28552
+ #, gcc-internal-format
+ msgid "method attributes must be specified at the end"
+ msgstr ""
+ 
+-#: cp/parser.c:28580
++#: cp/parser.c:28595
+ #, gcc-internal-format
+ msgid "stray %qs between Objective-C++ methods"
+ msgstr ""
+ 
+-#: cp/parser.c:28786 cp/parser.c:28793 cp/parser.c:28800
++#: cp/parser.c:28801 cp/parser.c:28808 cp/parser.c:28815
+ #, gcc-internal-format
+ msgid "invalid type for instance variable"
+ msgstr ""
+ 
+-#: cp/parser.c:28913
++#: cp/parser.c:28928
+ #, gcc-internal-format
+ msgid "identifier expected after %<@protocol%>"
+ msgstr ""
+ 
+-#: cp/parser.c:29084
++#: cp/parser.c:29099
+ #, gcc-internal-format
+ msgid ""
+ "attributes may not be specified before the %<@%D%> Objective-C++ keyword"
+ msgstr ""
+ 
+-#: cp/parser.c:29091
++#: cp/parser.c:29106
+ #, gcc-internal-format
+ msgid "prefix attributes are ignored before %<@%D%>"
+ msgstr ""
+ 
+-#: cp/parser.c:29364 cp/parser.c:29371 cp/parser.c:29378
++#: cp/parser.c:29379 cp/parser.c:29386 cp/parser.c:29393
+ #, gcc-internal-format
+ msgid "invalid type for property"
+ msgstr ""
+ 
+-#: cp/parser.c:30502
++#: cp/parser.c:30517
+ #, gcc-internal-format
+ msgid "%<wait%> expression must be integral"
+ msgstr ""
+ 
+-#: cp/parser.c:31196
++#: cp/parser.c:31211
+ #, gcc-internal-format
+ msgid "invalid reduction-identifier"
+ msgstr ""
+ 
+-#: cp/parser.c:33394
++#: cp/parser.c:33409
+ #, gcc-internal-format
+ msgid "parenthesized initialization is not allowed in OpenMP %<for%> loop"
+ msgstr ""
+ 
+-#: cp/parser.c:33397
++#: cp/parser.c:33412
+ #, gcc-internal-format
+ msgid "parenthesized initialization is not allowed in for-loop"
+ msgstr ""
+ 
+-#: cp/parser.c:33467
++#: cp/parser.c:33482
+ #, gcc-internal-format
+ msgid ""
+ "%<_Cilk_for%> allows expression instead of declaration only in C, not in C++"
+ msgstr ""
+ 
+-#: cp/parser.c:33695 cp/pt.c:15033
++#: cp/parser.c:33710 cp/pt.c:15033
+ #, gcc-internal-format
+ msgid "iteration variable %qD should not be reduction"
+ msgstr ""
+ 
+-#: cp/parser.c:33780
++#: cp/parser.c:33795
+ #, gcc-internal-format
+ msgid "not enough collapsed for loops"
+ msgstr ""
+ 
+-#: cp/parser.c:34064
++#: cp/parser.c:34079
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp ordered%> with %<depend%> clause may only be used in compound "
+@@ -43811,7 +43905,7 @@
+ "statements"
+ msgstr ""
+ 
+-#: cp/parser.c:34857
++#: cp/parser.c:34872
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp target exit data%> with map-type other than %<from%>, %<release"
+@@ -43818,7 +43912,7 @@
+ "%> or %<delete%> on %<map%> clause"
+ msgstr ""
+ 
+-#: cp/parser.c:35720
++#: cp/parser.c:35735
+ #, gcc-internal-format
+ msgid ""
+ "%<#pragma omp declare simd%> of %<simd%> attribute cannot be used in the "
+@@ -43825,7 +43919,7 @@
+ "same function marked as a Cilk Plus SIMD-enabled  function"
+ msgstr ""
+ 
+-#: cp/parser.c:35730
++#: cp/parser.c:35745
+ #, gcc-internal-format
+ msgid ""
+ "vector attribute not immediately followed by a single function declaration "
+@@ -43832,23 +43926,23 @@
+ "or definition"
+ msgstr ""
+ 
+-#: cp/parser.c:36024
++#: cp/parser.c:36039
+ #, gcc-internal-format
+ msgid "invalid initializer clause"
+ msgstr ""
+ 
+-#: cp/parser.c:36052
++#: cp/parser.c:36067
+ #, gcc-internal-format
+ msgid "expected id-expression (arguments)"
+ msgstr ""
+ 
+-#: cp/parser.c:36064
++#: cp/parser.c:36079
+ #, gcc-internal-format
+ msgid ""
+ "one of the initializer call arguments should be %<omp_priv%> or %<&omp_priv%>"
+ msgstr ""
+ 
+-#: cp/parser.c:36145
++#: cp/parser.c:36160
+ #, gcc-internal-format
+ msgid ""
+ "expected %<+%>, %<*%>, %<-%>, %<&%>, %<^%>, %<|%>, %<&&%>, %<||%> or "
+@@ -43855,27 +43949,27 @@
+ "identifier"
+ msgstr ""
+ 
+-#: cp/parser.c:36164
++#: cp/parser.c:36179
+ #, gcc-internal-format
+ msgid "types may not be defined in declare reduction type list"
+ msgstr ""
+ 
+-#: cp/parser.c:36186 cp/semantics.c:5354
++#: cp/parser.c:36201 cp/semantics.c:5355
+ #, gcc-internal-format
+ msgid "predeclared arithmetic type %qT in %<#pragma omp declare reduction%>"
+ msgstr ""
+ 
+-#: cp/parser.c:36191 cp/semantics.c:5363
++#: cp/parser.c:36206 cp/semantics.c:5364
+ #, gcc-internal-format
+ msgid "function or array type %qT in %<#pragma omp declare reduction%>"
+ msgstr ""
+ 
+-#: cp/parser.c:36194 cp/pt.c:11889 cp/semantics.c:5369
++#: cp/parser.c:36209 cp/pt.c:11889 cp/semantics.c:5370
+ #, gcc-internal-format
+ msgid "reference type %qT in %<#pragma omp declare reduction%>"
+ msgstr ""
+ 
+-#: cp/parser.c:36197 cp/semantics.c:5375
++#: cp/parser.c:36212 cp/semantics.c:5376
+ #, gcc-internal-format
+ msgid ""
+ "const, volatile or __restrict qualified type %qT in %<#pragma omp declare "
+@@ -43882,83 +43976,83 @@
+ "reduction%>"
+ msgstr ""
+ 
+-#: cp/parser.c:36579
++#: cp/parser.c:36594
+ #, gcc-internal-format
+ msgid "%<#pragma acc routine%> names a set of overloads"
+ msgstr ""
+ 
+-#: cp/parser.c:36588
++#: cp/parser.c:36603
+ #, gcc-internal-format
+ msgid "%<#pragma acc routine%> does not refer to a namespace scope function"
+ msgstr ""
+ 
+-#: cp/parser.c:36597
++#: cp/parser.c:36612
+ #, gcc-internal-format
+ msgid "%<#pragma acc routine%> does not refer to a function"
+ msgstr ""
+ 
+ #. cancel-and-throw is unimplemented.
+-#: cp/parser.c:36935
++#: cp/parser.c:36950
+ #, gcc-internal-format
+ msgid "atomic_cancel"
+ msgstr ""
+ 
+-#: cp/parser.c:36978 cp/semantics.c:8583
++#: cp/parser.c:36993 cp/semantics.c:8584
+ #, gcc-internal-format
+ msgid "%<__transaction_relaxed%> without transactional memory support enabled"
+ msgstr ""
+ 
+-#: cp/parser.c:36980 cp/semantics.c:8585
++#: cp/parser.c:36995 cp/semantics.c:8586
+ #, gcc-internal-format
+ msgid "%<__transaction_atomic%> without transactional memory support enabled"
+ msgstr ""
+ 
+-#: cp/parser.c:37176
++#: cp/parser.c:37191
+ #, gcc-internal-format
+ msgid "junk at end of %<#pragma GCC pch_preprocess%>"
+ msgstr ""
+ 
+-#: cp/parser.c:37209
++#: cp/parser.c:37224
+ #, gcc-internal-format
+ msgid "invalid grainsize for _Cilk_for"
+ msgstr ""
+ 
+-#: cp/parser.c:37418
++#: cp/parser.c:37433
+ #, gcc-internal-format
+ msgid "%<#pragma GCC ivdep%> must be inside a function"
+ msgstr ""
+ 
+-#: cp/parser.c:37439
++#: cp/parser.c:37454
+ #, gcc-internal-format
+ msgid "%<#pragma simd%> must be inside a function"
+ msgstr ""
+ 
+-#: cp/parser.c:37451
++#: cp/parser.c:37466
+ #, gcc-internal-format
+ msgid "%<#pragma cilk grainsize%> must be inside a function"
+ msgstr ""
+ 
+-#: cp/parser.c:37463
++#: cp/parser.c:37478
+ #, gcc-internal-format
+ msgid "-fcilkplus must be enabled to use %<#pragma cilk grainsize%>"
+ msgstr ""
+ 
+-#: cp/parser.c:37520
++#: cp/parser.c:37535
+ #, gcc-internal-format
+ msgid "inter-module optimizations not implemented for C++"
+ msgstr ""
+ 
+-#: cp/parser.c:37630
++#: cp/parser.c:37645
+ #, gcc-internal-format
+ msgid "expected variable-name"
+ msgstr ""
+ 
+-#: cp/parser.c:37694
++#: cp/parser.c:37709
+ #, gcc-internal-format
+ msgid "expected %<,%> or %<)%> after %qE"
+ msgstr ""
+ 
+-#: cp/parser.c:38093
++#: cp/parser.c:38108
+ #, gcc-internal-format
+ msgid "implicit templates may not be %<virtual%>"
+ msgstr ""
+@@ -44052,7 +44146,7 @@
+ msgid "candidate is: %#D"
+ msgstr ""
+ 
+-#: cp/pt.c:1948 cp/semantics.c:5223
++#: cp/pt.c:1948 cp/semantics.c:5224
+ #, gcc-internal-format
+ msgid "%s %#D"
+ msgstr ""
+@@ -45076,82 +45170,82 @@
+ msgid "  trying to instantiate %qD"
+ msgstr ""
+ 
+-#: cp/pt.c:21083
++#: cp/pt.c:21087
+ #, gcc-internal-format
+ msgid "ambiguous template instantiation for %q#T"
+ msgstr ""
+ 
+-#: cp/pt.c:21085
++#: cp/pt.c:21089
+ #, gcc-internal-format
+ msgid "ambiguous template instantiation for %q#D"
+ msgstr ""
+ 
+-#: cp/pt.c:21091
++#: cp/pt.c:21095
+ msgid "%s %#S"
+ msgstr ""
+ 
+-#: cp/pt.c:21115 cp/pt.c:21202
++#: cp/pt.c:21119 cp/pt.c:21206
+ #, gcc-internal-format
+ msgid "explicit instantiation of non-template %q#D"
+ msgstr ""
+ 
+-#: cp/pt.c:21134
++#: cp/pt.c:21138
+ #, gcc-internal-format
+ msgid "%qD is not a static data member of a class template"
+ msgstr ""
+ 
+-#: cp/pt.c:21140 cp/pt.c:21197
++#: cp/pt.c:21144 cp/pt.c:21201
+ #, gcc-internal-format
+ msgid "no matching template for %qD found"
+ msgstr ""
+ 
+-#: cp/pt.c:21145
++#: cp/pt.c:21149
+ #, gcc-internal-format
+ msgid ""
+ "type %qT for explicit instantiation %qD does not match declared type %qT"
+ msgstr ""
+ 
+-#: cp/pt.c:21153
++#: cp/pt.c:21157
+ #, gcc-internal-format
+ msgid "explicit instantiation of %q#D"
+ msgstr ""
+ 
+-#: cp/pt.c:21189
++#: cp/pt.c:21193
+ #, gcc-internal-format
+ msgid "duplicate explicit instantiation of %q#D"
+ msgstr ""
+ 
+-#: cp/pt.c:21212 cp/pt.c:21309
++#: cp/pt.c:21216 cp/pt.c:21313
+ #, gcc-internal-format
+ msgid "ISO C++ 1998 forbids the use of %<extern%> on explicit instantiations"
+ msgstr ""
+ 
+-#: cp/pt.c:21217 cp/pt.c:21326
++#: cp/pt.c:21221 cp/pt.c:21330
+ #, gcc-internal-format
+ msgid "storage class %qD applied to template instantiation"
+ msgstr ""
+ 
+-#: cp/pt.c:21285
++#: cp/pt.c:21289
+ #, gcc-internal-format
+ msgid "explicit instantiation of non-class template %qD"
+ msgstr ""
+ 
+-#: cp/pt.c:21287
++#: cp/pt.c:21291
+ #, gcc-internal-format
+ msgid "explicit instantiation of non-template type %qT"
+ msgstr ""
+ 
+-#: cp/pt.c:21296
++#: cp/pt.c:21300
+ #, gcc-internal-format
+ msgid "explicit instantiation of %q#T before definition of template"
+ msgstr ""
+ 
+-#: cp/pt.c:21314
++#: cp/pt.c:21318
+ #, gcc-internal-format
+ msgid "ISO C++ forbids the use of %qE on explicit instantiations"
+ msgstr ""
+ 
+-#: cp/pt.c:21360
++#: cp/pt.c:21364
+ #, gcc-internal-format
+ msgid "duplicate explicit instantiation of %q#T"
+ msgstr ""
+@@ -45163,12 +45257,12 @@
+ #. member function or static data member of a class template
+ #. shall be present in every translation unit in which it is
+ #. explicitly instantiated.
+-#: cp/pt.c:21912
++#: cp/pt.c:21917
+ #, gcc-internal-format
+ msgid "explicit instantiation of %qD but no definition available"
+ msgstr ""
+ 
+-#: cp/pt.c:22144
++#: cp/pt.c:22149
+ #, gcc-internal-format
+ msgid ""
+ "template instantiation depth exceeds maximum of %d instantiating %q+D, "
+@@ -45176,17 +45270,17 @@
+ "the maximum)"
+ msgstr ""
+ 
+-#: cp/pt.c:22486
++#: cp/pt.c:22491
+ #, gcc-internal-format
+ msgid "invalid template non-type parameter"
+ msgstr ""
+ 
+-#: cp/pt.c:22488
++#: cp/pt.c:22493
+ #, gcc-internal-format
+ msgid "%q#T is not a valid type for a template non-type parameter"
+ msgstr ""
+ 
+-#: cp/pt.c:23854
++#: cp/pt.c:23856
+ #, gcc-internal-format
+ msgid ""
+ "deducing from brace-enclosed initializer list requires #include "
+@@ -45193,12 +45287,12 @@
+ "<initializer_list>"
+ msgstr ""
+ 
+-#: cp/pt.c:24018
++#: cp/pt.c:24020
+ #, gcc-internal-format
+ msgid "direct-list-initialization of %<auto%> requires exactly one element"
+ msgstr ""
+ 
+-#: cp/pt.c:24021
++#: cp/pt.c:24023
+ #, gcc-internal-format
+ msgid ""
+ "for deduction to %<std::initializer_list%>, use copy-list-initialization (i."
+@@ -45205,37 +45299,37 @@
+ "e. add %<=%> before the %<{%>)"
+ msgstr ""
+ 
+-#: cp/pt.c:24045
++#: cp/pt.c:24047
+ #, gcc-internal-format
+ msgid "%qT as type rather than plain %<decltype(auto)%>"
+ msgstr ""
+ 
+-#: cp/pt.c:24080
++#: cp/pt.c:24082
+ #, gcc-internal-format
+ msgid "unable to deduce lambda return type from %qE"
+ msgstr ""
+ 
+-#: cp/pt.c:24082
++#: cp/pt.c:24084
+ #, gcc-internal-format
+ msgid "unable to deduce %qT from %qE"
+ msgstr ""
+ 
+-#: cp/pt.c:24114
++#: cp/pt.c:24116
+ #, gcc-internal-format
+ msgid "placeholder constraints not satisfied"
+ msgstr ""
+ 
+-#: cp/pt.c:24117
++#: cp/pt.c:24119
+ #, gcc-internal-format
+ msgid "deduced initializer does not satisfy placeholder constraints"
+ msgstr ""
+ 
+-#: cp/pt.c:24121
++#: cp/pt.c:24123
+ #, gcc-internal-format
+ msgid "deduced return type does not satisfy placeholder constraints"
+ msgstr ""
+ 
+-#: cp/pt.c:24125
++#: cp/pt.c:24127
+ #, gcc-internal-format
+ msgid "deduced expression type does not saatisy placeholder constraints"
+ msgstr ""
+@@ -45454,53 +45548,53 @@
+ msgid "compound literal of non-object type %qT"
+ msgstr ""
+ 
+-#: cp/semantics.c:2801
++#: cp/semantics.c:2802
+ #, gcc-internal-format
+ msgid "template type parameters must use the keyword %<class%> or %<typename%>"
+ msgstr ""
+ 
+-#: cp/semantics.c:2851
++#: cp/semantics.c:2852
+ #, gcc-internal-format
+ msgid ""
+ "invalid use of type %qT as a default value for a template template-parameter"
+ msgstr ""
+ 
+-#: cp/semantics.c:2854
++#: cp/semantics.c:2855
+ #, gcc-internal-format
+ msgid "invalid default argument for a template template parameter"
+ msgstr ""
+ 
+-#: cp/semantics.c:2871
++#: cp/semantics.c:2872
+ #, gcc-internal-format
+ msgid "definition of %q#T inside template parameter list"
+ msgstr ""
+ 
+-#: cp/semantics.c:2902
++#: cp/semantics.c:2903
+ #, gcc-internal-format
+ msgid "invalid definition of qualified type %qT"
+ msgstr ""
+ 
+-#: cp/semantics.c:3182
++#: cp/semantics.c:3183
+ #, gcc-internal-format
+ msgid "invalid base-class specification"
+ msgstr ""
+ 
+-#: cp/semantics.c:3341
++#: cp/semantics.c:3342
+ #, gcc-internal-format
+ msgid "cannot capture member %qD of anonymous union"
+ msgstr ""
+ 
+-#: cp/semantics.c:3354 cp/semantics.c:9266
++#: cp/semantics.c:3355 cp/semantics.c:9267
+ #, gcc-internal-format
+ msgid "%qD is not captured"
+ msgstr ""
+ 
+-#: cp/semantics.c:3359
++#: cp/semantics.c:3360
+ #, gcc-internal-format
+ msgid "the lambda has no capture-default"
+ msgstr ""
+ 
+-#: cp/semantics.c:3361
++#: cp/semantics.c:3362
+ #, gcc-internal-format
+ msgid ""
+ "lambda in local class %q+T cannot capture variables from the enclosing "
+@@ -45507,17 +45601,17 @@
+ "context"
+ msgstr ""
+ 
+-#: cp/semantics.c:3372
++#: cp/semantics.c:3373
+ #, gcc-internal-format
+ msgid "use of local variable with automatic storage from containing function"
+ msgstr ""
+ 
+-#: cp/semantics.c:3373
++#: cp/semantics.c:3374
+ #, gcc-internal-format
+ msgid "use of parameter from containing function"
+ msgstr ""
+ 
+-#: cp/semantics.c:3541
++#: cp/semantics.c:3542
+ #, gcc-internal-format
+ msgid ""
+ "template parameter %qD of type %qT is not allowed in an integral constant "
+@@ -45524,49 +45618,49 @@
+ "expression because it is not of integral or enumeration type"
+ msgstr ""
+ 
+-#: cp/semantics.c:3628
++#: cp/semantics.c:3629
+ #, gcc-internal-format
+ msgid "use of namespace %qD as expression"
+ msgstr ""
+ 
+-#: cp/semantics.c:3633
++#: cp/semantics.c:3634
+ #, gcc-internal-format
+ msgid "use of class template %qT as expression"
+ msgstr ""
+ 
+ #. Ambiguous reference to base members.
+-#: cp/semantics.c:3639
++#: cp/semantics.c:3640
+ #, gcc-internal-format
+ msgid "request for member %qD is ambiguous in multiple inheritance lattice"
+ msgstr ""
+ 
+-#: cp/semantics.c:3665
++#: cp/semantics.c:3666
+ #, gcc-internal-format
+ msgid "%qD cannot appear in a constant-expression"
+ msgstr ""
+ 
+-#: cp/semantics.c:3790
++#: cp/semantics.c:3791
+ #, gcc-internal-format
+ msgid "type of %qE is unknown"
+ msgstr ""
+ 
+-#: cp/semantics.c:3818
++#: cp/semantics.c:3819
+ #, gcc-internal-format
+ msgid "%qT is not an enumeration type"
+ msgstr ""
+ 
+ #. Parameter packs can only be used in templates
+-#: cp/semantics.c:3973
++#: cp/semantics.c:3974
+ #, gcc-internal-format
+ msgid "Parameter pack __bases only valid in template declaration"
+ msgstr ""
+ 
+-#: cp/semantics.c:4002
++#: cp/semantics.c:4003
+ #, gcc-internal-format
+ msgid "cannot apply %<offsetof%> to destructor %<~%T%>"
+ msgstr ""
+ 
+-#: cp/semantics.c:4011
++#: cp/semantics.c:4012
+ #, gcc-internal-format
+ msgid ""
+ "second operand of %<offsetof%> is neither a single identifier nor a sequence "
+@@ -45573,44 +45667,44 @@
+ "of member accesses and array references"
+ msgstr ""
+ 
+-#: cp/semantics.c:4019
++#: cp/semantics.c:4020
+ #, gcc-internal-format
+ msgid "cannot apply %<offsetof%> to member function %qD"
+ msgstr ""
+ 
+-#: cp/semantics.c:4035
++#: cp/semantics.c:4036
+ #, gcc-internal-format
+ msgid "offsetof within non-standard-layout type %qT is undefined"
+ msgstr ""
+ 
+-#: cp/semantics.c:4544 cp/semantics.c:6001 cp/semantics.c:6057
+-#: cp/semantics.c:6096 cp/semantics.c:6447 cp/semantics.c:6546
+-#: cp/semantics.c:6686
++#: cp/semantics.c:4545 cp/semantics.c:6002 cp/semantics.c:6058
++#: cp/semantics.c:6097 cp/semantics.c:6448 cp/semantics.c:6547
++#: cp/semantics.c:6687
+ #, gcc-internal-format
+ msgid "%<this%> allowed in OpenMP only in %<declare simd%> clauses"
+ msgstr ""
+ 
+-#: cp/semantics.c:5220
++#: cp/semantics.c:5221
+ #, gcc-internal-format
+ msgid "user defined reduction lookup is ambiguous"
+ msgstr ""
+ 
+-#: cp/semantics.c:5493
++#: cp/semantics.c:5494
+ #, gcc-internal-format
+ msgid "%qE in %<reduction%> clause is a zero size array"
+ msgstr ""
+ 
+-#: cp/semantics.c:5541
++#: cp/semantics.c:5542
+ #, gcc-internal-format
+ msgid "%qE has const type for %<reduction%>"
+ msgstr ""
+ 
+-#: cp/semantics.c:5653
++#: cp/semantics.c:5654
+ #, gcc-internal-format
+ msgid "user defined reduction with constructor initializer for base class %qT"
+ msgstr ""
+ 
+-#: cp/semantics.c:5875
++#: cp/semantics.c:5876
+ #, gcc-internal-format
+ msgid ""
+ "linear clause with %qs modifier applied to non-reference variable with %qT "
+@@ -45617,123 +45711,123 @@
+ "type"
+ msgstr ""
+ 
+-#: cp/semantics.c:5888
++#: cp/semantics.c:5889
+ #, gcc-internal-format
+ msgid ""
+ "linear clause applied to non-integral non-pointer variable with %qT type"
+ msgstr ""
+ 
+-#: cp/semantics.c:5909
++#: cp/semantics.c:5910
+ #, gcc-internal-format
+ msgid "linear step expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6012
++#: cp/semantics.c:6013
+ #, gcc-internal-format
+ msgid "%qD is not a variable in clause %qs"
+ msgstr ""
+ 
+-#: cp/semantics.c:6068
++#: cp/semantics.c:6069
+ #, gcc-internal-format
+ msgid "%qD is not a variable in clause %<firstprivate%>"
+ msgstr ""
+ 
+-#: cp/semantics.c:6107
++#: cp/semantics.c:6108
+ #, gcc-internal-format
+ msgid "%qD is not a variable in clause %<lastprivate%>"
+ msgstr ""
+ 
+-#: cp/semantics.c:6152
++#: cp/semantics.c:6153
+ #, gcc-internal-format
+ msgid "%<gang%> static expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6166
++#: cp/semantics.c:6167
+ #, gcc-internal-format
+ msgid "%<gang%> static value must bepositive"
+ msgstr ""
+ 
+-#: cp/semantics.c:6198
++#: cp/semantics.c:6199
+ #, gcc-internal-format
+ msgid "%<gang%> num expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6201
++#: cp/semantics.c:6202
+ #, gcc-internal-format
+ msgid "%<vector%> length expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6205
++#: cp/semantics.c:6206
+ #, gcc-internal-format
+ msgid "%<worker%> num expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6209
++#: cp/semantics.c:6210
+ #, gcc-internal-format
+ msgid "%qs expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6227
++#: cp/semantics.c:6228
+ #, gcc-internal-format
+ msgid "%<gang%> num value must be positive"
+ msgstr ""
+ 
+-#: cp/semantics.c:6231
++#: cp/semantics.c:6232
+ #, gcc-internal-format
+ msgid "%<vector%> length value must bepositive"
+ msgstr ""
+ 
+-#: cp/semantics.c:6236
++#: cp/semantics.c:6237
+ #, gcc-internal-format
+ msgid "%<worker%> num value must bepositive"
+ msgstr ""
+ 
+-#: cp/semantics.c:6241
++#: cp/semantics.c:6242
+ #, gcc-internal-format
+ msgid "%qs value must be positive"
+ msgstr ""
+ 
+-#: cp/semantics.c:6288
++#: cp/semantics.c:6289
+ #, gcc-internal-format
+ msgid "schedule chunk size expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6320
++#: cp/semantics.c:6321
+ #, gcc-internal-format
+ msgid "%qs length expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6333
++#: cp/semantics.c:6334
+ #, gcc-internal-format
+ msgid "%qs length expression must be positive constant integer expression"
+ msgstr ""
+ 
+-#: cp/semantics.c:6352
++#: cp/semantics.c:6353
+ #, gcc-internal-format
+ msgid "%<async%> expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6380
++#: cp/semantics.c:6381
+ #, gcc-internal-format
+ msgid "%<thread_limit%> expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6409
++#: cp/semantics.c:6410
+ #, gcc-internal-format
+ msgid "%<device%> id must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6430
++#: cp/semantics.c:6431
+ #, gcc-internal-format
+ msgid "%<dist_schedule%> chunk size expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6457
++#: cp/semantics.c:6458
+ #, gcc-internal-format
+ msgid "%qD is not a variable in %<aligned%> clause"
+ msgstr ""
+ 
+-#: cp/semantics.c:6471
++#: cp/semantics.c:6472
+ #, gcc-internal-format
+ msgid ""
+ "%qE in %<aligned%> clause is neither a pointer nor an array nor a reference "
+@@ -45740,47 +45834,47 @@
+ "to pointer or array"
+ msgstr ""
+ 
+-#: cp/semantics.c:6477
++#: cp/semantics.c:6478
+ #, gcc-internal-format
+ msgid "%qD appears more than once in %<aligned%> clauses"
+ msgstr ""
+ 
+-#: cp/semantics.c:6490
++#: cp/semantics.c:6491
+ #, gcc-internal-format
+ msgid "%<aligned%> clause alignment expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6539
++#: cp/semantics.c:6540
+ #, gcc-internal-format
+ msgid "%qD is not a variable in %<depend%> clause"
+ msgstr ""
+ 
+-#: cp/semantics.c:6813
++#: cp/semantics.c:6814
+ #, gcc-internal-format
+ msgid "overloaded function name %qE in clause %qs"
+ msgstr ""
+ 
+-#: cp/semantics.c:6817
++#: cp/semantics.c:6818
+ #, gcc-internal-format
+ msgid "template %qE in clause %qs"
+ msgstr ""
+ 
+-#: cp/semantics.c:6882
++#: cp/semantics.c:6883
+ #, gcc-internal-format
+ msgid "%<grainsize%> expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6911
++#: cp/semantics.c:6912
+ #, gcc-internal-format
+ msgid "%<priority%> expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6940
++#: cp/semantics.c:6941
+ #, gcc-internal-format
+ msgid "%<num_tasks%> expression must be integral"
+ msgstr ""
+ 
+-#: cp/semantics.c:6969
++#: cp/semantics.c:6970
+ #, gcc-internal-format
+ msgid ""
+ "%qs variable is neither a pointer, nor an arraynor reference to pointer or "
+@@ -45787,67 +45881,67 @@
+ "array"
+ msgstr ""
+ 
+-#: cp/semantics.c:7425
++#: cp/semantics.c:7426
+ #, gcc-internal-format
+ msgid "%<threadprivate%> %qD is not file, namespace or block scope variable"
+ msgstr ""
+ 
+-#: cp/semantics.c:7439
++#: cp/semantics.c:7440
+ #, gcc-internal-format
+ msgid "%<threadprivate%> %qE directive not in %qT definition"
+ msgstr ""
+ 
+-#: cp/semantics.c:7644
++#: cp/semantics.c:7645
+ #, gcc-internal-format
+ msgid "difference between %qE and %qD does not have integer type"
+ msgstr ""
+ 
+-#: cp/semantics.c:8064
++#: cp/semantics.c:8065
+ #, gcc-internal-format
+ msgid "%<#pragma omp simd%> used with class iteration variable %qE"
+ msgstr ""
+ 
+-#: cp/semantics.c:8406 cp/semantics.c:8416
++#: cp/semantics.c:8407 cp/semantics.c:8417
+ #, gcc-internal-format
+ msgid "%<#pragma omp atomic update%> uses two different expressions for memory"
+ msgstr ""
+ 
+-#: cp/semantics.c:8709
++#: cp/semantics.c:8710
+ #, gcc-internal-format
+ msgid "static assertion failed"
+ msgstr ""
+ 
+-#: cp/semantics.c:8711
++#: cp/semantics.c:8712
+ #, gcc-internal-format, gfc-internal-format
+ msgid "static assertion failed: %s"
+ msgstr ""
+ 
+-#: cp/semantics.c:8716
++#: cp/semantics.c:8717
+ #, gcc-internal-format
+ msgid "non-constant condition for static assertion"
+ msgstr ""
+ 
+-#: cp/semantics.c:8746
++#: cp/semantics.c:8747
+ #, gcc-internal-format
+ msgid "argument to decltype must be an expression"
+ msgstr ""
+ 
+-#: cp/semantics.c:8774
++#: cp/semantics.c:8775
+ #, gcc-internal-format
+ msgid "decltype cannot resolve address of overloaded function"
+ msgstr ""
+ 
+-#: cp/semantics.c:9305
++#: cp/semantics.c:9306
+ #, gcc-internal-format
+ msgid "operand of fold expression has no unexpanded parameter packs"
+ msgstr ""
+ 
+-#: cp/semantics.c:9358
++#: cp/semantics.c:9359
+ #, gcc-internal-format
+ msgid "both arguments in binary fold have unexpanded parameter packs"
+ msgstr ""
+ 
+-#: cp/semantics.c:9360
++#: cp/semantics.c:9361
+ #, gcc-internal-format
+ msgid "no unexpanded parameter packs in binary fold"
+ msgstr ""
+@@ -46727,32 +46821,32 @@
+ msgid "in passing argument %P of %qD"
+ msgstr ""
+ 
+-#: cp/typeck.c:8581
++#: cp/typeck.c:8582
+ #, gcc-internal-format
+ msgid "returning reference to temporary"
+ msgstr ""
+ 
+-#: cp/typeck.c:8588
++#: cp/typeck.c:8589
+ #, gcc-internal-format
+ msgid "reference to non-lvalue returned"
+ msgstr ""
+ 
+-#: cp/typeck.c:8603
++#: cp/typeck.c:8604
+ #, gcc-internal-format
+ msgid "reference to local variable %qD returned"
+ msgstr ""
+ 
+-#: cp/typeck.c:8607
++#: cp/typeck.c:8608
+ #, gcc-internal-format
+ msgid "address of label %qD returned"
+ msgstr ""
+ 
+-#: cp/typeck.c:8611
++#: cp/typeck.c:8612
+ #, gcc-internal-format
+ msgid "address of local variable %qD returned"
+ msgstr ""
+ 
+-#: cp/typeck.c:8657
++#: cp/typeck.c:8658
+ #, gcc-internal-format
+ msgid "returning a value from a destructor"
+ msgstr ""
+@@ -46759,44 +46853,44 @@
+ 
+ #. If a return statement appears in a handler of the
+ #. function-try-block of a constructor, the program is ill-formed.
+-#: cp/typeck.c:8665
++#: cp/typeck.c:8666
+ #, gcc-internal-format
+ msgid "cannot return from a handler of a function-try-block of a constructor"
+ msgstr ""
+ 
+ #. You can't return a value from a constructor.
+-#: cp/typeck.c:8668
++#: cp/typeck.c:8669
+ #, gcc-internal-format
+ msgid "returning a value from a constructor"
+ msgstr ""
+ 
+ #. Give a helpful error message.
+-#: cp/typeck.c:8698 cp/typeck.c:8744
++#: cp/typeck.c:8699 cp/typeck.c:8745
+ #, gcc-internal-format
+ msgid "return-statement with no value, in function returning %qT"
+ msgstr ""
+ 
+-#: cp/typeck.c:8706
++#: cp/typeck.c:8707
+ #, gcc-internal-format
+ msgid "returning initializer list"
+ msgstr ""
+ 
+-#: cp/typeck.c:8725
++#: cp/typeck.c:8726
+ #, gcc-internal-format
+ msgid "inconsistent types %qT and %qT deduced for lambda return type"
+ msgstr ""
+ 
+-#: cp/typeck.c:8728
++#: cp/typeck.c:8729
+ #, gcc-internal-format
+ msgid "inconsistent deduction for auto return type: %qT and then %qT"
+ msgstr ""
+ 
+-#: cp/typeck.c:8763
++#: cp/typeck.c:8764
+ #, gcc-internal-format
+ msgid "return-statement with a value, in function returning 'void'"
+ msgstr ""
+ 
+-#: cp/typeck.c:8793
++#: cp/typeck.c:8794
+ #, gcc-internal-format
+ msgid ""
+ "%<operator new%> must not return NULL unless it is declared %<throw()%> (or -"
+@@ -46804,12 +46898,12 @@
+ msgstr ""
+ 
+ #. Make this a permerror because we used to accept it.
+-#: cp/typeck.c:9402
++#: cp/typeck.c:9403
+ #, gcc-internal-format
+ msgid "using temporary as lvalue"
+ msgstr ""
+ 
+-#: cp/typeck.c:9404
++#: cp/typeck.c:9405
+ #, gcc-internal-format
+ msgid "using xvalue (rvalue reference) as lvalue"
+ msgstr ""
+@@ -47370,10 +47464,10 @@
+ msgid "Array reference at %C cannot have more than %d dimensions"
+ msgstr ""
+ 
+-#: fortran/array.c:213 fortran/array.c:625 fortran/check.c:2642
+-#: fortran/check.c:4950 fortran/check.c:4988 fortran/check.c:5030
+-#: fortran/check.c:5229 fortran/match.c:1802 fortran/match.c:2909
+-#: fortran/match.c:3104 fortran/match.c:3300 fortran/simplify.c:4737
++#: fortran/array.c:213 fortran/array.c:625 fortran/check.c:2649
++#: fortran/check.c:4957 fortran/check.c:4995 fortran/check.c:5037
++#: fortran/check.c:5236 fortran/match.c:1802 fortran/match.c:2997
++#: fortran/match.c:3192 fortran/match.c:3388 fortran/simplify.c:4740
+ #, gcc-internal-format
+ msgid "Coarrays disabled at %C, use %<-fcoarray=%> to enable"
+ msgstr ""
+@@ -47498,47 +47592,52 @@
+ msgid "DO-iterator %qs at %L is inside iterator of the same name"
+ msgstr ""
+ 
+-#: fortran/array.c:1037 fortran/array.c:1217
++#: fortran/array.c:1037 fortran/array.c:1233
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in array constructor at %C"
+ msgstr ""
+ 
+-#: fortran/array.c:1090
++#: fortran/array.c:1091
+ #, gcc-internal-format, gfc-internal-format
+ msgid "[...] style array constructors at %C"
+ msgstr ""
+ 
+-#: fortran/array.c:1113
++#: fortran/array.c:1114
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Array constructor including type specification at %C"
+ msgstr ""
+ 
+-#: fortran/array.c:1122 fortran/match.c:3730
++#: fortran/array.c:1123 fortran/match.c:3818
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Type-spec at %L cannot contain a deferred type parameter"
+ msgstr ""
+ 
+-#: fortran/array.c:1149
++#: fortran/array.c:1132
+ #, gcc-internal-format, gfc-internal-format
++msgid "Type-spec at %L cannot contain an asterisk for a type parameter"
++msgstr ""
++
++#: fortran/array.c:1159
++#, gcc-internal-format, gfc-internal-format
+ msgid "Empty array constructor at %C is not allowed"
+ msgstr ""
+ 
+-#: fortran/array.c:1188 fortran/array.c:1198
++#: fortran/array.c:1196 fortran/array.c:1206
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Incompatible typespec for array element at %L"
+ msgstr ""
+ 
+-#: fortran/array.c:1264
++#: fortran/array.c:1280
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Element in %s array constructor at %L is %s"
+ msgstr ""
+ 
+-#: fortran/array.c:1595
++#: fortran/array.c:1611
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Iterator step at %L cannot be zero"
+ msgstr ""
+ 
+-#: fortran/array.c:1732
++#: fortran/array.c:1748
+ #, gcc-internal-format
+ msgid ""
+ "The number of elements in the array constructor at %L requires an increase "
+@@ -47545,22 +47644,22 @@
+ "of the allowed %d upper limit.   See %<-fmax-array-constructor%> option"
+ msgstr ""
+ 
+-#: fortran/array.c:1902
++#: fortran/array.c:1918
+ #, gcc-internal-format, gfc-internal-format
+ msgid "AC-IMPLIED-DO initial expression references control variable at %L"
+ msgstr ""
+ 
+-#: fortran/array.c:1909
++#: fortran/array.c:1925
+ #, gcc-internal-format, gfc-internal-format
+ msgid "AC-IMPLIED-DO final expression references control variable at %L"
+ msgstr ""
+ 
+-#: fortran/array.c:1916
++#: fortran/array.c:1932
+ #, gcc-internal-format, gfc-internal-format
+ msgid "AC-IMPLIED-DO step expression references control variable at %L"
+ msgstr ""
+ 
+-#: fortran/array.c:1928
++#: fortran/array.c:1944
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Array constructor value at %L shall not be unlimited polymorphic [F2008: "
+@@ -47567,37 +47666,37 @@
+ "C4106]"
+ msgstr ""
+ 
+-#: fortran/array.c:2011
++#: fortran/array.c:2027
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Different CHARACTER lengths (%d/%d) in array constructor at %L"
+ msgstr ""
+ 
+-#: fortran/array.c:2129
++#: fortran/array.c:2145
+ #, gcc-internal-format
+ msgid "spec_dimen_size(): Bad dimension"
+ msgstr ""
+ 
+-#: fortran/array.c:2187
++#: fortran/array.c:2203
+ #, gcc-internal-format
+ msgid "gfc_ref_dimen_size(): Bad dimension"
+ msgstr ""
+ 
+-#: fortran/array.c:2317
++#: fortran/array.c:2333
+ #, gcc-internal-format
+ msgid "gfc_ref_dimen_size(): Bad dimen_type"
+ msgstr ""
+ 
+-#: fortran/array.c:2368
++#: fortran/array.c:2384
+ #, gcc-internal-format
+ msgid "gfc_array_dimen_size(): Bad dimension"
+ msgstr ""
+ 
+-#: fortran/array.c:2413
++#: fortran/array.c:2429
+ #, gcc-internal-format
+ msgid "gfc_array_dimen_size(): Bad EXPR_ARRAY expr"
+ msgstr ""
+ 
+-#: fortran/array.c:2557
++#: fortran/array.c:2573
+ #, gcc-internal-format
+ msgid "gfc_find_array_ref(): No ref found"
+ msgstr ""
+@@ -47618,162 +47717,162 @@
+ msgid "%qs argument of %qs intrinsic at %L must be %s"
+ msgstr ""
+ 
+-#: fortran/check.c:89
++#: fortran/check.c:96
+ #, gcc-internal-format
+-msgid "%qs argument of %qs intrinsic at %L must be a numeric type"
++msgid "%qs argument of %qs intrinsic at %L must have a numeric type"
+ msgstr ""
+ 
+-#: fortran/check.c:104
++#: fortran/check.c:111
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be INTEGER or REAL"
+ msgstr ""
+ 
+-#: fortran/check.c:121
++#: fortran/check.c:128
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be REAL or COMPLEX"
+ msgstr ""
+ 
+-#: fortran/check.c:138
++#: fortran/check.c:145
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be INTEGER or PROCEDURE"
+ msgstr ""
+ 
+-#: fortran/check.c:167 fortran/check.c:6373
++#: fortran/check.c:174 fortran/check.c:6380
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be a constant"
+ msgstr ""
+ 
+-#: fortran/check.c:176
++#: fortran/check.c:183
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid kind for %s at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:195
++#: fortran/check.c:202
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be double precision"
+ msgstr ""
+ 
+-#: fortran/check.c:218
++#: fortran/check.c:225
+ #, gcc-internal-format
+ msgid "Expected coarray variable as %qs argument to the %s intrinsic at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:235
++#: fortran/check.c:242
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be a logical array"
+ msgstr ""
+ 
+-#: fortran/check.c:261
++#: fortran/check.c:268
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be an array"
+ msgstr ""
+ 
+-#: fortran/check.c:282
++#: fortran/check.c:289
+ #, gcc-internal-format
+ msgid "%qs at %L must be nonnegative"
+ msgstr ""
+ 
+-#: fortran/check.c:313
++#: fortran/check.c:320
+ #, gcc-internal-format
+ msgid ""
+ "The absolute value of SHIFT at %L must be less than or equal to BIT_SIZE(%qs)"
+ msgstr ""
+ 
+-#: fortran/check.c:324
++#: fortran/check.c:331
+ #, gcc-internal-format
+ msgid "%qs at %L must be less than or equal to BIT_SIZE(%qs)"
+ msgstr ""
+ 
+-#: fortran/check.c:334
++#: fortran/check.c:341
+ #, gcc-internal-format
+ msgid "%qs at %L must be less than BIT_SIZE(%qs)"
+ msgstr ""
+ 
+-#: fortran/check.c:361
++#: fortran/check.c:368
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %L must be less than or equal to the BIT_SIZE of INTEGER(KIND=%d)"
+ msgstr ""
+ 
+-#: fortran/check.c:387
++#: fortran/check.c:394
+ #, gcc-internal-format
+ msgid "%<%s + %s%> at %L must be less than or equal to BIT_SIZE(%qs)"
+ msgstr ""
+ 
+-#: fortran/check.c:413
++#: fortran/check.c:420
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must be the same type and kind as %qs"
+ msgstr ""
+ 
+-#: fortran/check.c:430
++#: fortran/check.c:437
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be of rank %d"
+ msgstr ""
+ 
+-#: fortran/check.c:445
++#: fortran/check.c:452
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must not be OPTIONAL"
+ msgstr ""
+ 
+-#: fortran/check.c:466
++#: fortran/check.c:473
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be ALLOCATABLE"
+ msgstr ""
+ 
+-#: fortran/check.c:484
++#: fortran/check.c:491
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be of kind %d"
+ msgstr ""
+ 
+-#: fortran/check.c:522
++#: fortran/check.c:529
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L cannot be INTENT(IN)"
+ msgstr ""
+ 
+-#: fortran/check.c:543
++#: fortran/check.c:550
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be a variable"
+ msgstr ""
+ 
+-#: fortran/check.c:592
++#: fortran/check.c:599
+ #, gcc-internal-format
+ msgid ""
+ "%<dim%> argument of %qs intrinsic at %L is not a valid codimension index"
+ msgstr ""
+ 
+-#: fortran/check.c:642
++#: fortran/check.c:649
+ #, gcc-internal-format
+ msgid "%<dim%> argument of %qs intrinsic at %L is not a valid dimension index"
+ msgstr ""
+ 
+-#: fortran/check.c:745
++#: fortran/check.c:752
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unequal character lengths (%ld/%ld) in %s at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:867 fortran/check.c:6317
++#: fortran/check.c:874 fortran/check.c:6324
+ #, gcc-internal-format
+ msgid "%qs and %qs arguments of %qs intrinsic at %L must have the same type"
+ msgstr ""
+ 
+-#: fortran/check.c:876 fortran/check.c:2279 fortran/check.c:2405
+-#: fortran/check.c:2479 fortran/check.c:2906
++#: fortran/check.c:883 fortran/check.c:2286 fortran/check.c:2412
++#: fortran/check.c:2486 fortran/check.c:2913
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Different type kinds at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:912
++#: fortran/check.c:919
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be a POINTER"
+ msgstr ""
+ 
+-#: fortran/check.c:921 fortran/check.c:957 fortran/check.c:3424
++#: fortran/check.c:928 fortran/check.c:964 fortran/check.c:3431
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:939
++#: fortran/check.c:946
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must be a pointer or target VARIABLE or "
+@@ -47780,12 +47879,12 @@
+ "FUNCTION"
+ msgstr ""
+ 
+-#: fortran/check.c:948
++#: fortran/check.c:955
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be a POINTER or a TARGET"
+ msgstr ""
+ 
+-#: fortran/check.c:973
++#: fortran/check.c:980
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Array section with a vector subscript at %L shall not be the target of a "
+@@ -47792,7 +47891,7 @@
+ "pointer"
+ msgstr ""
+ 
+-#: fortran/check.c:984
++#: fortran/check.c:991
+ #, gcc-internal-format
+ msgid ""
+ "NULL pointer at %L is not permitted as actual argument of %qs intrinsic "
+@@ -47799,7 +47898,7 @@
+ "function"
+ msgstr ""
+ 
+-#: fortran/check.c:1027
++#: fortran/check.c:1034
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "ATOM argument at %L to intrinsic function %s shall be an integer of "
+@@ -47806,7 +47905,7 @@
+ "ATOMIC_INT_KIND or a logical of ATOMIC_LOGICAL_KIND"
+ msgstr ""
+ 
+-#: fortran/check.c:1035
++#: fortran/check.c:1042
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "ATOM argument at %L of the %s intrinsic function shall be a coarray or "
+@@ -47813,23 +47912,23 @@
+ "coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:1042
++#: fortran/check.c:1049
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L shall have the same type as %qs at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:1060 fortran/check.c:1205
++#: fortran/check.c:1067 fortran/check.c:1212
+ #, gcc-internal-format, gfc-internal-format
+ msgid "STAT= argument to %s at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:1079 fortran/check.c:1145 fortran/check.c:1242
++#: fortran/check.c:1086 fortran/check.c:1152 fortran/check.c:1249
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ATOM argument of the %s intrinsic function at %L shall be definable"
+ msgstr ""
+ 
+-#: fortran/check.c:1093 fortran/check.c:1225
++#: fortran/check.c:1100 fortran/check.c:1232
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "ATOM argument at %L to intrinsic function %s shall be an integer of "
+@@ -47836,29 +47935,29 @@
+ "ATOMIC_INT_KIND"
+ msgstr ""
+ 
+-#: fortran/check.c:1113
++#: fortran/check.c:1120
+ #, gcc-internal-format, gfc-internal-format
+ msgid "VALUE argument of the %s intrinsic function at %L shall be definable"
+ msgstr ""
+ 
+-#: fortran/check.c:1152 fortran/check.c:1249
++#: fortran/check.c:1159 fortran/check.c:1256
+ #, gcc-internal-format, gfc-internal-format
+ msgid "OLD argument of the %s intrinsic function at %L shall be definable"
+ msgstr ""
+ 
+-#: fortran/check.c:1167
++#: fortran/check.c:1174
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "EVENT argument at %L to the intrinsic EVENT_QUERY shall be of type EVENT_TYPE"
+ msgstr ""
+ 
+-#: fortran/check.c:1177
++#: fortran/check.c:1184
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "COUNT argument of the EVENT_QUERY intrinsic function at %L shall be definable"
+ msgstr ""
+ 
+-#: fortran/check.c:1190
++#: fortran/check.c:1197
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "COUNT argument of the EVENT_QUERY intrinsic function at %L shall have at "
+@@ -47865,18 +47964,18 @@
+ "least the range of the default integer"
+ msgstr ""
+ 
+-#: fortran/check.c:1269
++#: fortran/check.c:1276
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Negative argument N at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:1441 fortran/check.c:1898
++#: fortran/check.c:1448 fortran/check.c:1905
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must not be present if %<x%> is COMPLEX"
+ msgstr ""
+ 
+-#: fortran/check.c:1450 fortran/check.c:1907
++#: fortran/check.c:1457 fortran/check.c:1914
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must have a type of either REAL or "
+@@ -47883,7 +47982,7 @@
+ "INTEGER"
+ msgstr ""
+ 
+-#: fortran/check.c:1464 fortran/check.c:1470
++#: fortran/check.c:1471 fortran/check.c:1477
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Conversion from %s to default-kind COMPLEX(%d) at %L might lose precision, "
+@@ -47890,7 +47989,7 @@
+ "consider using the KIND argument"
+ msgstr ""
+ 
+-#: fortran/check.c:1492
++#: fortran/check.c:1499
+ #, gcc-internal-format
+ msgid ""
+ "Argument %<A%> with INTENT(INOUT) at %L of the intrinsic subroutine %s shall "
+@@ -47897,27 +47996,27 @@
+ "not have a vector subscript"
+ msgstr ""
+ 
+-#: fortran/check.c:1500
++#: fortran/check.c:1507
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The A argument at %L to the intrinsic %s shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:1523
++#: fortran/check.c:1530
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The stat= argument at %L must be a kind=4 integer variable"
+ msgstr ""
+ 
+-#: fortran/check.c:1539
++#: fortran/check.c:1546
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The errmsg= argument at %L must be a default-kind character variable"
+ msgstr ""
+ 
+-#: fortran/check.c:1547
++#: fortran/check.c:1554
+ #, gcc-internal-format
+ msgid "Coarrays disabled at %L, use %<-fcoarray=%> to enable"
+ msgstr ""
+ 
+-#: fortran/check.c:1562
++#: fortran/check.c:1569
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Support for the A argument at %L which is polymorphic A argument or has "
+@@ -47924,12 +48023,12 @@
+ "allocatable components is not yet implemented"
+ msgstr ""
+ 
+-#: fortran/check.c:1581
++#: fortran/check.c:1588
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The A argument at %L of CO_REDUCE shall not be polymorphic"
+ msgstr ""
+ 
+-#: fortran/check.c:1588
++#: fortran/check.c:1595
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Support for the A argument at %L with allocatable components is not yet "
+@@ -47936,7 +48035,7 @@
+ "implemented"
+ msgstr ""
+ 
+-#: fortran/check.c:1602
++#: fortran/check.c:1609
+ #, gcc-internal-format, gfc-internal-format
+ msgid "OPERATOR argument at %L must be a PURE function"
+ msgstr ""
+@@ -47944,17 +48043,17 @@
+ #. None of the intrinsics fulfills the criteria of taking two arguments,
+ #. returning the same type and kind as the arguments and being permitted
+ #. as actual argument.
+-#: fortran/check.c:1612
++#: fortran/check.c:1619
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Intrinsic function %s at %L is not permitted for CO_REDUCE"
+ msgstr ""
+ 
+-#: fortran/check.c:1629
++#: fortran/check.c:1636
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The function passed as OPERATOR at %L shall have two arguments"
+ msgstr ""
+ 
+-#: fortran/check.c:1639
++#: fortran/check.c:1646
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "A argument at %L has type %s but the function passed as OPERATOR at %L "
+@@ -47961,7 +48060,7 @@
+ "returns %s"
+ msgstr ""
+ 
+-#: fortran/check.c:1648
++#: fortran/check.c:1655
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The function passed as OPERATOR at %L has arguments of type %s and %s but "
+@@ -47968,7 +48067,7 @@
+ "shall have type %s"
+ msgstr ""
+ 
+-#: fortran/check.c:1659
++#: fortran/check.c:1666
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The function passed as OPERATOR at %L shall have scalar nonallocatable "
+@@ -47975,7 +48074,7 @@
+ "nonpointer arguments and return a nonallocatable nonpointer scalar"
+ msgstr ""
+ 
+-#: fortran/check.c:1667
++#: fortran/check.c:1674
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The function passed as OPERATOR at %L shall have the VALUE attribute either "
+@@ -47982,7 +48081,7 @@
+ "for none or both arguments"
+ msgstr ""
+ 
+-#: fortran/check.c:1674
++#: fortran/check.c:1681
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The function passed as OPERATOR at %L shall have the TARGET attribute either "
+@@ -47989,7 +48088,7 @@
+ "for none or both arguments"
+ msgstr ""
+ 
+-#: fortran/check.c:1681
++#: fortran/check.c:1688
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The function passed as OPERATOR at %L shall have the ASYNCHRONOUS attribute "
+@@ -47996,7 +48095,7 @@
+ "either for none or both arguments"
+ msgstr ""
+ 
+-#: fortran/check.c:1689
++#: fortran/check.c:1696
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The function passed as OPERATOR at %L shall not have the OPTIONAL attribute "
+@@ -48003,7 +48102,7 @@
+ "for either of the arguments"
+ msgstr ""
+ 
+-#: fortran/check.c:1719
++#: fortran/check.c:1726
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The character length of the A argument at %L and of the arguments of the "
+@@ -48010,7 +48109,7 @@
+ "OPERATOR at %L shall be the same"
+ msgstr ""
+ 
+-#: fortran/check.c:1726
++#: fortran/check.c:1733
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The character length of the A argument at %L and of the function result of "
+@@ -48017,7 +48116,7 @@
+ "the OPERATOR at %L shall be the same"
+ msgstr ""
+ 
+-#: fortran/check.c:1744
++#: fortran/check.c:1751
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L shall be of type integer, real or "
+@@ -48024,15 +48123,15 @@
+ "character"
+ msgstr ""
+ 
+-#: fortran/check.c:1792 fortran/check.c:2324 fortran/check.c:2427
+-#: fortran/check.c:2628 fortran/check.c:2673 fortran/check.c:3984
+-#: fortran/check.c:4118 fortran/check.c:4173 fortran/check.c:5215
+-#: fortran/check.c:5344
++#: fortran/check.c:1799 fortran/check.c:2331 fortran/check.c:2434
++#: fortran/check.c:2635 fortran/check.c:2680 fortran/check.c:3991
++#: fortran/check.c:4125 fortran/check.c:4180 fortran/check.c:5222
++#: fortran/check.c:5351
+ #, gcc-internal-format
+ msgid "%qs intrinsic with KIND argument at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:1839 fortran/check.c:2090
++#: fortran/check.c:1846 fortran/check.c:2097
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L has invalid shape in dimension %d (%ld/"
+@@ -48039,115 +48138,115 @@
+ "%ld)"
+ msgstr ""
+ 
+-#: fortran/check.c:1854 fortran/check.c:2105 fortran/check.c:2133
++#: fortran/check.c:1861 fortran/check.c:2112 fortran/check.c:2140
+ #, gcc-internal-format
+ msgid "%qs argument of intrinsic %qs at %L of must have rank %d or be a scalar"
+ msgstr ""
+ 
+-#: fortran/check.c:1957 fortran/check.c:3000 fortran/check.c:3008
++#: fortran/check.c:1964 fortran/check.c:3007 fortran/check.c:3015
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be numeric or LOGICAL"
+ msgstr ""
+ 
+-#: fortran/check.c:1971
++#: fortran/check.c:1978
+ #, gcc-internal-format
+ msgid ""
+ "Different shape for arguments %qs and %qs at %L for intrinsic %<dot_product%>"
+ msgstr ""
+ 
+-#: fortran/check.c:1991 fortran/check.c:1999
++#: fortran/check.c:1998 fortran/check.c:2006
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be default real"
+ msgstr ""
+ 
+-#: fortran/check.c:2020
++#: fortran/check.c:2027
+ #, gcc-internal-format
+ msgid "%<I%> at %L and %<J%>' at %L cannot both be BOZ literal constants"
+ msgstr ""
+ 
+-#: fortran/check.c:2151
++#: fortran/check.c:2158
+ #, gcc-internal-format, gfc-internal-format
+ msgid "non-default INTEGER kind argument to %s intrinsic at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:2211
++#: fortran/check.c:2218
+ #, gcc-internal-format
+ msgid "COMPLEX argument %qs of %qs intrinsic at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:2375
++#: fortran/check.c:2382
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of %s at %L must be of length one"
+ msgstr ""
+ 
+-#: fortran/check.c:2434
++#: fortran/check.c:2441
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be the same kind as %qs"
+ msgstr ""
+ 
+-#: fortran/check.c:2524
++#: fortran/check.c:2531
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SIZE at %L must be positive"
+ msgstr ""
+ 
+-#: fortran/check.c:2536
++#: fortran/check.c:2543
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The absolute value of SHIFT at %L must be less than or equal to SIZE at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:2597
++#: fortran/check.c:2604
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be of intrinsic type"
+ msgstr ""
+ 
+-#: fortran/check.c:2604
++#: fortran/check.c:2611
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be a data entity"
+ msgstr ""
+ 
+-#: fortran/check.c:2815
++#: fortran/check.c:2822
+ #, gcc-internal-format
+ msgid "Intrinsic %qs at %L must have at least two arguments"
+ msgstr ""
+ 
+-#: fortran/check.c:2863
++#: fortran/check.c:2870
+ #, gcc-internal-format
+ msgid "Missing %qs argument to the %s intrinsic at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:2878
++#: fortran/check.c:2885
+ #, gcc-internal-format
+ msgid "Duplicate argument %qs at %L to intrinsic %s"
+ msgstr ""
+ 
+-#: fortran/check.c:2883
++#: fortran/check.c:2890
+ #, gcc-internal-format
+ msgid "Unknown argument %qs at %L to intrinsic %s"
+ msgstr ""
+ 
+-#: fortran/check.c:2912
++#: fortran/check.c:2919
+ #, gcc-internal-format
+ msgid "%<a%d%> argument of %qs intrinsic at %L must be %s(%d)"
+ msgstr ""
+ 
+-#: fortran/check.c:2943
++#: fortran/check.c:2950
+ #, gcc-internal-format
+ msgid "%qs intrinsic with CHARACTER argument at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:2950
++#: fortran/check.c:2957
+ #, gcc-internal-format
+ msgid ""
+ "%<a1%> argument of %qs intrinsic at %L must be INTEGER, REAL or CHARACTER"
+ msgstr ""
+ 
+-#: fortran/check.c:3017
++#: fortran/check.c:3024
+ #, gcc-internal-format
+ msgid "Argument types of %qs intrinsic at %L must match (%s/%s)"
+ msgstr ""
+ 
+-#: fortran/check.c:3031
++#: fortran/check.c:3038
+ #, gcc-internal-format
+ msgid ""
+ "Different shape on dimension 1 for arguments %qs and %qs at %L for intrinsic "
+@@ -48154,7 +48253,7 @@
+ "matmul"
+ msgstr ""
+ 
+-#: fortran/check.c:3050
++#: fortran/check.c:3057
+ #, gcc-internal-format
+ msgid ""
+ "Different shape on dimension 2 for argument %qs and dimension 1 for argument "
+@@ -48161,27 +48260,27 @@
+ "%qs at %L for intrinsic matmul"
+ msgstr ""
+ 
+-#: fortran/check.c:3059
++#: fortran/check.c:3066
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be of rank 1 or 2"
+ msgstr ""
+ 
+-#: fortran/check.c:3234
++#: fortran/check.c:3241
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be INTEGER"
+ msgstr ""
+ 
+-#: fortran/check.c:3294
++#: fortran/check.c:3301
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The FROM argument to MOVE_ALLOC at %L shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:3305
++#: fortran/check.c:3312
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The TO argument to MOVE_ALLOC at %L shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:3312
++#: fortran/check.c:3319
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The TO arguments in MOVE_ALLOC at %L must be polymorphic if FROM is "
+@@ -48188,7 +48287,7 @@
+ "polymorphic"
+ msgstr ""
+ 
+-#: fortran/check.c:3323
++#: fortran/check.c:3330
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The FROM and TO arguments of the MOVE_ALLOC intrinsic at %L must have the "
+@@ -48195,7 +48294,7 @@
+ "same rank %d/%d"
+ msgstr ""
+ 
+-#: fortran/check.c:3332
++#: fortran/check.c:3339
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The FROM and TO arguments of the MOVE_ALLOC intrinsic at %L must have the "
+@@ -48202,12 +48301,12 @@
+ "same corank %d/%d"
+ msgstr ""
+ 
+-#: fortran/check.c:3359
++#: fortran/check.c:3366
+ #, gcc-internal-format
+ msgid "Argument %<S%> of NEAREST at %L shall not be zero"
+ msgstr ""
+ 
+-#: fortran/check.c:3409
++#: fortran/check.c:3416
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must be a POINTER, ALLOCATABLE or "
+@@ -48214,12 +48313,12 @@
+ "procedure pointer"
+ msgstr ""
+ 
+-#: fortran/check.c:3417
++#: fortran/check.c:3424
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NULL intrinsic with allocatable MOLD at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:3496 fortran/check.c:5291
++#: fortran/check.c:3503 fortran/check.c:5298
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must provide at least as many elements "
+@@ -48226,28 +48325,28 @@
+ "as there are .TRUE. values in %qs (%ld/%d)"
+ msgstr ""
+ 
+-#: fortran/check.c:3554
++#: fortran/check.c:3561
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be of a dummy variable"
+ msgstr ""
+ 
+-#: fortran/check.c:3562
++#: fortran/check.c:3569
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must be of an OPTIONAL dummy variable"
+ msgstr ""
+ 
+-#: fortran/check.c:3581
++#: fortran/check.c:3588
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must not be a subobject of %qs"
+ msgstr ""
+ 
+-#: fortran/check.c:3629
++#: fortran/check.c:3636
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The argument of the RANK intrinsic at %L must be a data object"
+ msgstr ""
+ 
+-#: fortran/check.c:3733
++#: fortran/check.c:3740
+ #, gcc-internal-format
+ msgid ""
+ "%<shape%> argument of %<reshape%> intrinsic at %L must be an array of "
+@@ -48254,39 +48353,39 @@
+ "constant size"
+ msgstr ""
+ 
+-#: fortran/check.c:3743
++#: fortran/check.c:3750
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L is empty"
+ msgstr ""
+ 
+-#: fortran/check.c:3750
++#: fortran/check.c:3757
+ #, gcc-internal-format
+ msgid ""
+ "%<shape%> argument of %<reshape%> intrinsic at %L has more than %d elements"
+ msgstr ""
+ 
+-#: fortran/check.c:3767
++#: fortran/check.c:3774
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L has negative element (%d)"
+ msgstr ""
+ 
+-#: fortran/check.c:3799
++#: fortran/check.c:3806
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Element %d of actual argument of RESHAPE at %L cannot be negative"
+ msgstr ""
+ 
+-#: fortran/check.c:3837
++#: fortran/check.c:3844
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L has wrong number of elements (%d/%d)"
+ msgstr ""
+ 
+-#: fortran/check.c:3855
++#: fortran/check.c:3862
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L has out-of-range dimension (%d)"
+ msgstr ""
+ 
+-#: fortran/check.c:3864
++#: fortran/check.c:3871
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L has invalid permutation of dimensions "
+@@ -48293,7 +48392,7 @@
+ "(dimension %qd duplicated)"
+ msgstr ""
+ 
+-#: fortran/check.c:3900
++#: fortran/check.c:3907
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Without padding, there are not enough elements in the intrinsic RESHAPE "
+@@ -48300,27 +48399,27 @@
+ "source at %L to match the shape"
+ msgstr ""
+ 
+-#: fortran/check.c:3917 fortran/check.c:3936
++#: fortran/check.c:3924 fortran/check.c:3943
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L cannot be of type %s"
+ msgstr ""
+ 
+-#: fortran/check.c:3927 fortran/check.c:3946
++#: fortran/check.c:3934 fortran/check.c:3953
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be of an extensible type"
+ msgstr ""
+ 
+-#: fortran/check.c:4045
++#: fortran/check.c:4052
+ #, gcc-internal-format
+ msgid "SELECTED_REAL_KIND with neither %<P%> nor %<R%> argument at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:4076
++#: fortran/check.c:4083
+ #, gcc-internal-format
+ msgid "%qs intrinsic with RADIX argument at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:4111
++#: fortran/check.c:4118
+ #, gcc-internal-format
+ msgid ""
+ "%<source%> argument of %<shape%> intrinsic at %L must not be an assumed size "
+@@ -48327,33 +48426,33 @@
+ "array"
+ msgstr ""
+ 
+-#: fortran/check.c:4188 fortran/check.c:6356
++#: fortran/check.c:4195 fortran/check.c:6363
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L shall not be a procedure"
+ msgstr ""
+ 
+-#: fortran/check.c:4201 fortran/check.c:4340 fortran/check.c:6348
++#: fortran/check.c:4208 fortran/check.c:4347 fortran/check.c:6355
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L shall not be TYPE(*)"
+ msgstr ""
+ 
+-#: fortran/check.c:4212 fortran/check.c:4352
++#: fortran/check.c:4219 fortran/check.c:4359
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L shall not be an assumed-size array"
+ msgstr ""
+ 
+-#: fortran/check.c:4282
++#: fortran/check.c:4289
+ #, gcc-internal-format
+ msgid "is_c_interoperable(): gfc_simplify_expr failed"
+ msgstr ""
+ 
+-#: fortran/check.c:4331
++#: fortran/check.c:4338
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must be an interoperable data entity: %s"
+ msgstr ""
+ 
+-#: fortran/check.c:4370
++#: fortran/check.c:4377
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Argument C_PTR_1 at %L to C_ASSOCIATED shall have the type TYPE(C_PTR) or "
+@@ -48360,7 +48459,7 @@
+ "TYPE(C_FUNPTR)"
+ msgstr ""
+ 
+-#: fortran/check.c:4384
++#: fortran/check.c:4391
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Argument C_PTR_2 at %L to C_ASSOCIATED shall have the same type as C_PTR_1: "
+@@ -48367,37 +48466,37 @@
+ "%s instead of %s"
+ msgstr ""
+ 
+-#: fortran/check.c:4408
++#: fortran/check.c:4415
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument CPTR at %L to C_F_POINTER shall have the type TYPE(C_PTR)"
+ msgstr ""
+ 
+-#: fortran/check.c:4420
++#: fortran/check.c:4427
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument FPTR at %L to C_F_POINTER must be a pointer"
+ msgstr ""
+ 
+-#: fortran/check.c:4427
++#: fortran/check.c:4434
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FPTR argument at %L to C_F_POINTER shall not be polymorphic"
+ msgstr ""
+ 
+-#: fortran/check.c:4434
++#: fortran/check.c:4441
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument FPTR at %L to C_F_POINTER shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:4441
++#: fortran/check.c:4448
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected SHAPE argument at %L to C_F_POINTER with scalar FPTR"
+ msgstr ""
+ 
+-#: fortran/check.c:4447
++#: fortran/check.c:4454
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected SHAPE argument to C_F_POINTER with array FPTR at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:4466
++#: fortran/check.c:4473
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "SHAPE argument at %L to C_F_POINTER must have the same size as the RANK of "
+@@ -48404,69 +48503,69 @@
+ "FPTR"
+ msgstr ""
+ 
+-#: fortran/check.c:4476
++#: fortran/check.c:4483
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Polymorphic FPTR at %L to C_F_POINTER"
+ msgstr ""
+ 
+-#: fortran/check.c:4481
++#: fortran/check.c:4488
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Noninteroperable array FPTR at %L to C_F_POINTER: %s"
+ msgstr ""
+ 
+-#: fortran/check.c:4497
++#: fortran/check.c:4504
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Argument CPTR at %L to C_F_PROCPOINTER shall have the type TYPE(C_FUNPTR)"
+ msgstr ""
+ 
+-#: fortran/check.c:4509
++#: fortran/check.c:4516
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument FPTR at %L to C_F_PROCPOINTER shall be a procedure pointer"
+ msgstr ""
+ 
+-#: fortran/check.c:4516
++#: fortran/check.c:4523
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument FPTR at %L to C_F_PROCPOINTER shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:4522
++#: fortran/check.c:4529
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Noninteroperable procedure pointer at %L to C_F_PROCPOINTER"
+ msgstr ""
+ 
+-#: fortran/check.c:4536
++#: fortran/check.c:4543
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument X at %L to C_FUNLOC shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:4551
++#: fortran/check.c:4558
+ #, gcc-internal-format
+ msgid "Function result %qs at %L is invalid as X argument to C_FUNLOC"
+ msgstr ""
+ 
+-#: fortran/check.c:4559
++#: fortran/check.c:4566
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Argument X at %L to C_FUNLOC shall be a procedure or a procedure pointer"
+ msgstr ""
+ 
+-#: fortran/check.c:4565
++#: fortran/check.c:4572
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Noninteroperable procedure at %L to C_FUNLOC"
+ msgstr ""
+ 
+-#: fortran/check.c:4579
++#: fortran/check.c:4586
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument X at %L to C_LOC shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/check.c:4585
++#: fortran/check.c:4592
+ #, gcc-internal-format, gfc-internal-format
+ msgid "X argument at %L to C_LOC shall not be polymorphic"
+ msgstr ""
+ 
+-#: fortran/check.c:4596
++#: fortran/check.c:4603
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Argument X at %L to C_LOC shall have either the POINTER or the TARGET "
+@@ -48473,22 +48572,22 @@
+ "attribute"
+ msgstr ""
+ 
+-#: fortran/check.c:4604
++#: fortran/check.c:4611
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument X at %L to C_LOC shall be not be a zero-sized string"
+ msgstr ""
+ 
+-#: fortran/check.c:4613
++#: fortran/check.c:4620
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument at %L to C_LOC shall not be polymorphic"
+ msgstr ""
+ 
+-#: fortran/check.c:4620
++#: fortran/check.c:4627
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Noninteroperable array at %L as argument to C_LOC: %s"
+ msgstr ""
+ 
+-#: fortran/check.c:4631
++#: fortran/check.c:4638
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Array of interoperable type at %L to C_LOC which is nonallocatable and "
+@@ -48495,32 +48594,32 @@
+ "neither assumed size nor explicit size"
+ msgstr ""
+ 
+-#: fortran/check.c:4636
++#: fortran/check.c:4643
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Array section at %L to C_LOC"
+ msgstr ""
+ 
+-#: fortran/check.c:4664
++#: fortran/check.c:4671
+ #, gcc-internal-format, gfc-internal-format
+ msgid "non double precision REAL argument to %s intrinsic at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:4677
++#: fortran/check.c:4684
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be less than rank %d"
+ msgstr ""
+ 
+-#: fortran/check.c:4696
++#: fortran/check.c:4703
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L is not a valid dimension index"
+ msgstr ""
+ 
+-#: fortran/check.c:4959
++#: fortran/check.c:4966
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s argument to IMAGE_INDEX must be a rank one array at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:4970
++#: fortran/check.c:4977
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The number of array elements of the SUB argument to IMAGE_INDEX at %L shall "
+@@ -48527,17 +48626,17 @@
+ "be %d (corank) not %d"
+ msgstr ""
+ 
+-#: fortran/check.c:5003
++#: fortran/check.c:5010
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DISTANCE= argument to NUM_IMAGES at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5016
++#: fortran/check.c:5023
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FAILED= argument to NUM_IMAGES at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5039
++#: fortran/check.c:5046
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "DIM argument without COARRAY argument not allowed for THIS_IMAGE intrinsic "
+@@ -48544,7 +48643,7 @@
+ "at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5046
++#: fortran/check.c:5053
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The DISTANCE argument may not be specified together with the COARRAY or DIM "
+@@ -48551,22 +48650,22 @@
+ "argument in intrinsic at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5057
++#: fortran/check.c:5064
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected DIM argument with noncoarray argument at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5075
++#: fortran/check.c:5082
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DISTANCE= argument to THIS_IMAGE at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5155
++#: fortran/check.c:5162
+ #, gcc-internal-format
+ msgid "%<MOLD%> argument of %<TRANSFER%> intrinsic at %L must not be %s"
+ msgstr ""
+ 
+-#: fortran/check.c:5183
++#: fortran/check.c:5190
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Intrinsic TRANSFER at %L has partly undefined result: source size %ld < "
+@@ -48573,7 +48672,7 @@
+ "result size %ld"
+ msgstr ""
+ 
+-#: fortran/check.c:5305
++#: fortran/check.c:5312
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must have the same rank as %qs or be a "
+@@ -48580,52 +48679,52 @@
+ "scalar"
+ msgstr ""
+ 
+-#: fortran/check.c:5318
++#: fortran/check.c:5325
+ #, gcc-internal-format
+ msgid "%qs and %qs arguments of %qs intrinsic at %L must have identical shape."
+ msgstr ""
+ 
+-#: fortran/check.c:5576 fortran/check.c:5608
++#: fortran/check.c:5583 fortran/check.c:5615
+ #, gcc-internal-format
+ msgid "Size of %qs argument of %qs intrinsic at %L too small (%i/%i)"
+ msgstr ""
+ 
+-#: fortran/check.c:5616
++#: fortran/check.c:5623
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Too many arguments to %s at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5634
++#: fortran/check.c:5641
+ #, gcc-internal-format
+ msgid "fe_runtime_error string must be null terminated"
+ msgstr ""
+ 
+-#: fortran/check.c:5646
++#: fortran/check.c:5653
+ #, gcc-internal-format, gfc-internal-format
+ msgid "fe_runtime_error: Wrong number of arguments (%d instead of %d)"
+ msgstr ""
+ 
+-#: fortran/check.c:5686
++#: fortran/check.c:5693
+ #, gcc-internal-format, gfc-internal-format
+ msgid "COUNT argument to SYSTEM_CLOCK at %L has non-default kind"
+ msgstr ""
+ 
+-#: fortran/check.c:5705
++#: fortran/check.c:5712
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Real COUNT_RATE argument to SYSTEM_CLOCK at %L"
+ msgstr ""
+ 
+-#: fortran/check.c:5715
++#: fortran/check.c:5722
+ #, gcc-internal-format, gfc-internal-format
+ msgid "COUNT_RATE argument to SYSTEM_CLOCK at %L has non-default kind"
+ msgstr ""
+ 
+-#: fortran/check.c:5732
++#: fortran/check.c:5739
+ #, gcc-internal-format, gfc-internal-format
+ msgid "COUNT_MAX argument to SYSTEM_CLOCK at %L has non-default kind"
+ msgstr ""
+ 
+-#: fortran/check.c:5949
++#: fortran/check.c:5956
+ #, gcc-internal-format
+ msgid ""
+ "%qs argument of %qs intrinsic at %L must be of a kind not wider than the "
+@@ -48632,12 +48731,12 @@
+ "default kind (%d)"
+ msgstr ""
+ 
+-#: fortran/check.c:6301 fortran/check.c:6309
++#: fortran/check.c:6308 fortran/check.c:6316
+ #, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be INTEGER or LOGICAL"
+ msgstr ""
+ 
+-#: fortran/check.c:6340
++#: fortran/check.c:6347
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Intrinsic function NULL at %L cannot be an actual argument to STORAGE_SIZE, "
+@@ -48644,7 +48743,7 @@
+ "because it returns a disassociated pointer"
+ msgstr ""
+ 
+-#: fortran/class.c:612
++#: fortran/class.c:614
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Assumed size polymorphic objects or components, such as that at %C, have not "
+@@ -48653,12 +48752,12 @@
+ 
+ #. Since the extension field is 8 bit wide, we can only have
+ #. up to 255 extension levels.
+-#: fortran/class.c:723 fortran/decl.c:8717
++#: fortran/class.c:725 fortran/decl.c:8735
+ #, gcc-internal-format
+ msgid "Maximum extension level reached with type %qs at %L"
+ msgstr ""
+ 
+-#: fortran/class.c:2762 fortran/class.c:2836
++#: fortran/class.c:2764 fortran/class.c:2838
+ #, gcc-internal-format
+ msgid "%qs of %qs is PRIVATE at %L"
+ msgstr ""
+@@ -48733,107 +48832,107 @@
+ msgid "Symbol %qs must be a PARAMETER in DATA statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:421
++#: fortran/decl.c:422
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid initializer %s in Data statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:523
++#: fortran/decl.c:524
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Initialization at %C is not allowed in a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/decl.c:560
++#: fortran/decl.c:561
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DATA statement at %C cannot appear within an INTERFACE"
+ msgstr ""
+ 
+-#: fortran/decl.c:592
++#: fortran/decl.c:593
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DATA statement at %C is not allowed in a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/decl.c:638
++#: fortran/decl.c:639
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Empty old style initializer list at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:658
++#: fortran/decl.c:659
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Repeat spec invalid in scalar initializer at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:663
++#: fortran/decl.c:664
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Repeat spec must be an integer at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:672
++#: fortran/decl.c:673
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected data constant after repeat spec at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:703
++#: fortran/decl.c:704
+ #, gcc-internal-format, gfc-internal-format
+ msgid "End of scalar initializer expected at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:730
++#: fortran/decl.c:731
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Not enough elements in array initializer at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:732
++#: fortran/decl.c:733
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Too many elements in array initializer at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:751
++#: fortran/decl.c:752
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in old style initializer list at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:774
++#: fortran/decl.c:775
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The assumed-rank array at %C shall not have a codimension"
+ msgstr ""
+ 
+-#: fortran/decl.c:842
++#: fortran/decl.c:843
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Bad INTENT specification at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:863
++#: fortran/decl.c:864
+ #, gcc-internal-format, gfc-internal-format
+ msgid "deferred type parameter at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:935
++#: fortran/decl.c:947
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Scalar INTEGER expression expected at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:961
++#: fortran/decl.c:973
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Old-style character length at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:992
++#: fortran/decl.c:1004
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in character length specification at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:1145
++#: fortran/decl.c:1157
+ #, gcc-internal-format
+ msgid "Procedure %qs at %C is already defined at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:1153
++#: fortran/decl.c:1165
+ #, gcc-internal-format
+ msgid "Name %qs at %C is already defined as a generic interface at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:1166
++#: fortran/decl.c:1178
+ #, gcc-internal-format
+ msgid ""
+ "Procedure %qs at %C has an explicit interface and must not have attributes "
+@@ -48840,13 +48939,13 @@
+ "declared at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:1237
++#: fortran/decl.c:1249
+ #, gcc-internal-format
+ msgid ""
+ "Procedure %qs at %L must have the BIND(C) attribute to be C interoperable"
+ msgstr ""
+ 
+-#: fortran/decl.c:1264
++#: fortran/decl.c:1276
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L is a dummy argument to the BIND(C) procedure %qs but is "
+@@ -48853,7 +48952,7 @@
+ "not C interoperable because derived type %qs is not C interoperable"
+ msgstr ""
+ 
+-#: fortran/decl.c:1271
++#: fortran/decl.c:1283
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L is a dummy argument to the BIND(C) procedure %qs but is "
+@@ -48860,7 +48959,7 @@
+ "not C interoperable because it is polymorphic"
+ msgstr ""
+ 
+-#: fortran/decl.c:1278
++#: fortran/decl.c:1290
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L is a dummy argument of the BIND(C) procedure %qs but may "
+@@ -48867,7 +48966,7 @@
+ "not be C interoperable"
+ msgstr ""
+ 
+-#: fortran/decl.c:1293
++#: fortran/decl.c:1305
+ #, gcc-internal-format
+ msgid ""
+ "Character argument %qs at %L must be length 1 because procedure %qs is "
+@@ -48874,18 +48973,18 @@
+ "BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1306
++#: fortran/decl.c:1318
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L with ALLOCATABLE attribute in procedure %qs with BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1314
++#: fortran/decl.c:1326
+ #, gcc-internal-format
+ msgid "Variable %qs at %L with POINTER attribute in procedure %qs with BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1323
++#: fortran/decl.c:1335
+ #, gcc-internal-format
+ msgid ""
+ "Scalar variable %qs at %L with POINTER or ALLOCATABLE in procedure %qs with "
+@@ -48892,7 +48991,7 @@
+ "BIND(C) is not yet supported"
+ msgstr ""
+ 
+-#: fortran/decl.c:1332
++#: fortran/decl.c:1344
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L cannot have both the OPTIONAL and the VALUE attribute "
+@@ -48899,13 +48998,13 @@
+ "because procedure %qs is BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1339
++#: fortran/decl.c:1351
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L with OPTIONAL attribute in procedure %qs which is BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1350
++#: fortran/decl.c:1362
+ #, gcc-internal-format
+ msgid ""
+ "Assumed-shape array %qs at %L as dummy argument to the BIND(C) procedure %qs "
+@@ -48912,12 +49011,12 @@
+ "at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:1400
++#: fortran/decl.c:1412
+ #, gcc-internal-format
+ msgid "Symbol %qs at %C also declared as a type at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:1459
++#: fortran/decl.c:1471
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs in common block %qs at %C must be declared with a C "
+@@ -48924,12 +49023,17 @@
+ "interoperable kind since common block %qs is BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1504
++#: fortran/decl.c:1505
+ #, gcc-internal-format, gfc-internal-format
++msgid "CHARACTER length must be a constant at %L"
++msgstr ""
++
++#: fortran/decl.c:1520
++#, gcc-internal-format, gfc-internal-format
+ msgid "CHARACTER expression at %L is being truncated (%d/%d)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1511
++#: fortran/decl.c:1527
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The CHARACTER elements of the array constructor at %L must have the same "
+@@ -48936,103 +49040,103 @@
+ "length (%d/%d)"
+ msgstr ""
+ 
+-#: fortran/decl.c:1601
++#: fortran/decl.c:1617
+ #, gcc-internal-format
+ msgid "Initializer not allowed for PARAMETER %qs at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:1611
++#: fortran/decl.c:1627
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PARAMETER at %L is missing an initializer"
+ msgstr ""
+ 
+-#: fortran/decl.c:1621
++#: fortran/decl.c:1637
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %C with an initializer already appears in a DATA statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:1714
++#: fortran/decl.c:1730
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Can't initialize implied-shape array at %L with scalar"
+ msgstr ""
+ 
+-#: fortran/decl.c:1749
++#: fortran/decl.c:1765
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-constant lower bound in implied-shape declaration at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:1835
++#: fortran/decl.c:1851
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Component at %C must have the POINTER attribute"
+ msgstr ""
+ 
+-#: fortran/decl.c:1843
++#: fortran/decl.c:1859
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Array component of structure at %C must have explicit or deferred shape"
+ msgstr ""
+ 
+-#: fortran/decl.c:1867
++#: fortran/decl.c:1883
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Component '%s' at %C already declared at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:1953
++#: fortran/decl.c:1971
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Pointer array component of structure at %C must have a deferred shape"
+ msgstr ""
+ 
+-#: fortran/decl.c:1962
++#: fortran/decl.c:1980
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Allocatable component of structure at %C must have a deferred shape"
+ msgstr ""
+ 
+-#: fortran/decl.c:1971
++#: fortran/decl.c:1989
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Array component of structure at %C must have an explicit shape"
+ msgstr ""
+ 
+-#: fortran/decl.c:2025
++#: fortran/decl.c:2043
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NULL() initialization at %C is ambiguous"
+ msgstr ""
+ 
+-#: fortran/decl.c:2042
++#: fortran/decl.c:2060
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NULL() initialization at %C may not have MOLD"
+ msgstr ""
+ 
+-#: fortran/decl.c:2059
++#: fortran/decl.c:2077
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Initialization of pointer at %C is not allowed in a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/decl.c:2080
++#: fortran/decl.c:2098
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Error in pointer initialization at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2087
++#: fortran/decl.c:2105
+ #, gcc-internal-format, gfc-internal-format
+ msgid "non-NULL pointer initialization at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2110
++#: fortran/decl.c:2128
+ #, gcc-internal-format
+ msgid "Function name %qs not allowed at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2177
++#: fortran/decl.c:2195
+ #, gcc-internal-format
+ msgid "Non-PARAMETER symbol %qs at %L can't be implied-shape"
+ msgstr ""
+ 
+-#: fortran/decl.c:2187
++#: fortran/decl.c:2205
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Implied-shape array at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:2240
++#: fortran/decl.c:2258
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %C is a redefinition of the declaration in the corresponding "
+@@ -49039,164 +49143,164 @@
+ "interface for MODULE PROCEDURE %qs"
+ msgstr ""
+ 
+-#: fortran/decl.c:2269 fortran/decl.c:7291
++#: fortran/decl.c:2287 fortran/decl.c:7309
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate array spec for Cray pointee at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2277
++#: fortran/decl.c:2295
+ #, gcc-internal-format
+ msgid "Couldn't set pointee array spec."
+ msgstr ""
+ 
+-#: fortran/decl.c:2340
++#: fortran/decl.c:2358
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Old-style initialization at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2348
++#: fortran/decl.c:2366
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid old style initialization for derived type component at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2361
++#: fortran/decl.c:2379
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in old style initialization of %s at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2381 fortran/decl.c:5584
++#: fortran/decl.c:2399 fortran/decl.c:5602
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Initialization at %C isn't for a pointer variable"
+ msgstr ""
+ 
+-#: fortran/decl.c:2394
++#: fortran/decl.c:2412
+ #, gcc-internal-format
+ msgid "Pointer initialization at %C requires %<=>%>, not %<=%>"
+ msgstr ""
+ 
+-#: fortran/decl.c:2403 fortran/decl.c:8866
++#: fortran/decl.c:2421 fortran/decl.c:8884
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected an initialization expression at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2410
++#: fortran/decl.c:2428
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Initialization of variable at %C is not allowed in a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/decl.c:2427
++#: fortran/decl.c:2445
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Initialization of allocatable component at %C is not allowed"
+ msgstr ""
+ 
+-#: fortran/decl.c:2487 fortran/decl.c:2523
++#: fortran/decl.c:2505 fortran/decl.c:2541
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Old-style type declaration %s*%d not supported at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2529
++#: fortran/decl.c:2547
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Nonstandard type declaration %s*%d at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2580 fortran/decl.c:2656
++#: fortran/decl.c:2598 fortran/decl.c:2674
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing right parenthesis at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2593 fortran/decl.c:2727
++#: fortran/decl.c:2611 fortran/decl.c:2745
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected initialization expression at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2601 fortran/decl.c:2733
++#: fortran/decl.c:2619 fortran/decl.c:2751
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected scalar initialization expression at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2632
++#: fortran/decl.c:2650
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Kind %d not supported for type %s at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2645
++#: fortran/decl.c:2663
+ #, gcc-internal-format, gfc-internal-format
+ msgid "C kind type parameter is for type %s but type at %L is %s"
+ msgstr ""
+ 
+-#: fortran/decl.c:2654
++#: fortran/decl.c:2672
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing right parenthesis or comma at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2753
++#: fortran/decl.c:2771
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Kind %d is not supported for CHARACTER at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2885
++#: fortran/decl.c:2903
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in CHARACTER declaration at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:2951
++#: fortran/decl.c:2969
+ #, gcc-internal-format, gfc-internal-format
+ msgid "RECORD at %C is an extension, enable it with -fdec-structure"
+ msgstr ""
+ 
+-#: fortran/decl.c:2957
++#: fortran/decl.c:2975
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Structure name expected after RECORD at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3000
++#: fortran/decl.c:3018
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BYTE type at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3005
++#: fortran/decl.c:3023
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BYTE type used at %C is not available on the target machine"
+ msgstr ""
+ 
+-#: fortran/decl.c:3027
++#: fortran/decl.c:3045
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed type at %C is not allowed for components"
+ msgstr ""
+ 
+-#: fortran/decl.c:3030
++#: fortran/decl.c:3048
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed type at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3053 fortran/decl.c:3084 fortran/decl.c:3113
+-#: fortran/decl.c:3331
++#: fortran/decl.c:3071 fortran/decl.c:3102 fortran/decl.c:3131
++#: fortran/decl.c:3349
+ #, gcc-internal-format, gfc-internal-format
+ msgid "TYPE with intrinsic-type-spec at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3109
++#: fortran/decl.c:3127
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DOUBLE COMPLEX at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3146
++#: fortran/decl.c:3164
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Type name '%s' at %C is ambiguous"
+ msgstr ""
+ 
+-#: fortran/decl.c:3224
++#: fortran/decl.c:3242
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CLASS statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3257 fortran/decl.c:3270 fortran/decl.c:3726
+-#: fortran/decl.c:3734
++#: fortran/decl.c:3275 fortran/decl.c:3288 fortran/decl.c:3744
++#: fortran/decl.c:3752
+ #, gcc-internal-format
+ msgid "Type name %qs at %C is ambiguous"
+ msgstr ""
+ 
+-#: fortran/decl.c:3285
++#: fortran/decl.c:3303
+ #, gcc-internal-format
+ msgid ""
+ "Type name %qs at %C conflicts with previously declared entity at %L, which "
+@@ -49203,42 +49307,42 @@
+ "has the same name"
+ msgstr ""
+ 
+-#: fortran/decl.c:3402
++#: fortran/decl.c:3420
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate IMPLICIT NONE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3411
++#: fortran/decl.c:3429
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IMPORT NONE with spec list at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3470
++#: fortran/decl.c:3488
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing character range in IMPLICIT at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3516
++#: fortran/decl.c:3534
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Letters must be in alphabetic order in IMPLICIT statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3569
++#: fortran/decl.c:3587
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IMPLICIT statement at %C following an IMPLICIT NONE (type) statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:3579
++#: fortran/decl.c:3597
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Empty IMPLICIT statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3685
++#: fortran/decl.c:3703
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IMPORT statement at %C only permitted in an INTERFACE body"
+ msgstr ""
+ 
+-#: fortran/decl.c:3692
++#: fortran/decl.c:3710
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "F2008: C1210 IMPORT statement at %C is not permitted in a module procedure "
+@@ -49245,62 +49349,62 @@
+ "interface body"
+ msgstr ""
+ 
+-#: fortran/decl.c:3697
++#: fortran/decl.c:3715
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IMPORT statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3711
++#: fortran/decl.c:3729
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expecting list of named entities at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3740
++#: fortran/decl.c:3758
+ #, gcc-internal-format
+ msgid "Cannot IMPORT %qs from host scoping unit at %C - does not exist."
+ msgstr ""
+ 
+-#: fortran/decl.c:3747
++#: fortran/decl.c:3765
+ #, gcc-internal-format
+ msgid "%qs is already IMPORTed from host scoping unit at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:3788
++#: fortran/decl.c:3806
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in IMPORT statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4087
++#: fortran/decl.c:4105
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing codimension specification at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4089
++#: fortran/decl.c:4107
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing dimension specification at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4172
++#: fortran/decl.c:4190
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate %s attribute at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:4191
++#: fortran/decl.c:4209
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ALLOCATABLE attribute at %C in a TYPE definition"
+ msgstr ""
+ 
+-#: fortran/decl.c:4200
++#: fortran/decl.c:4218
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Attribute at %L is not allowed in a TYPE definition"
+ msgstr ""
+ 
+-#: fortran/decl.c:4218
++#: fortran/decl.c:4236
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Attribute %s at %L in a TYPE definition"
+ msgstr ""
+ 
+-#: fortran/decl.c:4228
++#: fortran/decl.c:4246
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "%s attribute at %L is not allowed outside of the specification part of a "
+@@ -49307,53 +49411,53 @@
+ "module"
+ msgstr ""
+ 
+-#: fortran/decl.c:4242
++#: fortran/decl.c:4260
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASYNCHRONOUS attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4253
++#: fortran/decl.c:4271
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CONTIGUOUS attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4300 fortran/decl.c:7587
++#: fortran/decl.c:4318 fortran/decl.c:7605
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROTECTED at %C only allowed in specification part of a module"
+ msgstr ""
+ 
+-#: fortran/decl.c:4306
++#: fortran/decl.c:4324
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROTECTED attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4335
++#: fortran/decl.c:4353
+ #, gcc-internal-format, gfc-internal-format
+ msgid "VALUE attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4342
++#: fortran/decl.c:4360
+ #, gcc-internal-format, gfc-internal-format
+ msgid "VOLATILE attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4349
++#: fortran/decl.c:4367
+ #, gcc-internal-format
+ msgid "match_attr_spec(): Bad attribute"
+ msgstr ""
+ 
+-#: fortran/decl.c:4389
++#: fortran/decl.c:4407
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Multiple identifiers provided with single NAME= specifier at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4487
++#: fortran/decl.c:4505
+ #, gcc-internal-format
+ msgid ""
+ "Implicitly declared BIND(C) function %qs at %L may not be C interoperable"
+ msgstr ""
+ 
+-#: fortran/decl.c:4509
++#: fortran/decl.c:4527
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs in common block %qs at %L may not be a C interoperable kind "
+@@ -49360,17 +49464,17 @@
+ "though common block %qs is BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:4518
++#: fortran/decl.c:4536
+ #, gcc-internal-format
+ msgid "Type declaration %qs at %L is not C interoperable but it is BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:4522
++#: fortran/decl.c:4540
+ #, gcc-internal-format
+ msgid "Variable %qs at %L may not be a C interoperable kind but it is BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:4534
++#: fortran/decl.c:4552
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs in common block %qs at %L cannot be declared with BIND(C) since "
+@@ -49377,23 +49481,23 @@
+ "it is not a global"
+ msgstr ""
+ 
+-#: fortran/decl.c:4548
++#: fortran/decl.c:4566
+ #, gcc-internal-format
+ msgid "Variable %qs at %L cannot have both the POINTER and BIND(C) attributes"
+ msgstr ""
+ 
+-#: fortran/decl.c:4556
++#: fortran/decl.c:4574
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L cannot have both the ALLOCATABLE and BIND(C) attributes"
+ msgstr ""
+ 
+-#: fortran/decl.c:4568
++#: fortran/decl.c:4586
+ #, gcc-internal-format
+ msgid "Return type of BIND(C) function %qs at %L cannot be an array"
+ msgstr ""
+ 
+-#: fortran/decl.c:4576
++#: fortran/decl.c:4594
+ #, gcc-internal-format
+ msgid "Return type of BIND(C) function %qs at %L cannot be a character string"
+ msgstr ""
+@@ -49400,13 +49504,13 @@
+ 
+ #. Use gfc_warning_now because we won't say that the symbol fails
+ #. just because of this.
+-#: fortran/decl.c:4587
++#: fortran/decl.c:4605
+ #, gcc-internal-format
+ msgid ""
+ "Symbol %qs at %L is marked PRIVATE but has been given the binding label %qs"
+ msgstr ""
+ 
+-#: fortran/decl.c:4661
++#: fortran/decl.c:4679
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Need either entity or common block name for attribute specification "
+@@ -49413,7 +49517,7 @@
+ "statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4706
++#: fortran/decl.c:4724
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Missing entity or common block name for attribute specification statement at "
+@@ -49420,17 +49524,17 @@
+ "%C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4713
++#: fortran/decl.c:4731
+ #, gcc-internal-format
+ msgid "Missing symbol"
+ msgstr ""
+ 
+-#: fortran/decl.c:4742
++#: fortran/decl.c:4760
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BIND(C) statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4822
++#: fortran/decl.c:4840
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Derived type at %C has not been previously defined and so cannot appear in a "
+@@ -49437,360 +49541,360 @@
+ "derived type definition"
+ msgstr ""
+ 
+-#: fortran/decl.c:4854
++#: fortran/decl.c:4872
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in data declaration at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4895
++#: fortran/decl.c:4913
+ #, gcc-internal-format, gfc-internal-format
+ msgid "MODULE prefix at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4940
++#: fortran/decl.c:4958
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IMPURE procedure at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4952
++#: fortran/decl.c:4970
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PURE and IMPURE must not appear both at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:4998
++#: fortran/decl.c:5016
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ELEMENTAL prefix in MODULE PROCEDURE interface is missing at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:5005
++#: fortran/decl.c:5023
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PURE prefix in MODULE PROCEDURE interface is missing at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:5012
++#: fortran/decl.c:5030
+ #, gcc-internal-format, gfc-internal-format
+ msgid "RECURSIVE prefix in MODULE PROCEDURE interface is missing at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:5075 fortran/primary.c:1779
++#: fortran/decl.c:5093 fortran/primary.c:1783
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Alternate-return argument at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5121
++#: fortran/decl.c:5139
+ #, gcc-internal-format
+ msgid "Name %qs at %C is the name of the procedure"
+ msgstr ""
+ 
+-#: fortran/decl.c:5133
++#: fortran/decl.c:5151
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected junk in formal argument list at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5150
++#: fortran/decl.c:5168
+ #, gcc-internal-format
+ msgid "Duplicate symbol %qs in formal argument list at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5189
++#: fortran/decl.c:5207
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Mismatch in MODULE PROCEDURE formal argument names (%s/%s) at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5195
++#: fortran/decl.c:5213
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Mismatch in number of MODULE PROCEDURE formal arguments at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5234
++#: fortran/decl.c:5252
+ #, gcc-internal-format, gfc-internal-format
+ msgid "RESULT variable at %C must be different than function name"
+ msgstr ""
+ 
+-#: fortran/decl.c:5311
++#: fortran/decl.c:5329
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected junk after function declaration at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5321 fortran/decl.c:6418
++#: fortran/decl.c:5339 fortran/decl.c:6436
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BIND(C) attribute at %L may not be specified for an internal procedure"
+ msgstr ""
+ 
+-#: fortran/decl.c:5523
++#: fortran/decl.c:5541
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BIND(C) attribute at %C requires an interface with BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:5530
++#: fortran/decl.c:5548
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BIND(C) procedure with NAME may not have POINTER attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5536
++#: fortran/decl.c:5554
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Dummy procedure at %C may not have BIND(C) attribute with NAME"
+ msgstr ""
+ 
+-#: fortran/decl.c:5559
++#: fortran/decl.c:5577
+ #, gcc-internal-format
+ msgid "Procedure %qs at %L already has basic type of %s"
+ msgstr ""
+ 
+-#: fortran/decl.c:5605 fortran/decl.c:5793 fortran/decl.c:9347
++#: fortran/decl.c:5623 fortran/decl.c:5811 fortran/decl.c:9365
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in PROCEDURE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5654 fortran/decl.c:9249
++#: fortran/decl.c:5672 fortran/decl.c:9267
+ #, gcc-internal-format
+ msgid "Expected %<::%> after binding-attributes at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5661
++#: fortran/decl.c:5679
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NOPASS or explicit interface required at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5665
++#: fortran/decl.c:5683
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Procedure pointer component at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5737
++#: fortran/decl.c:5755
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in procedure pointer component at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5755
++#: fortran/decl.c:5773
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROCEDURE at %C must be in a generic interface"
+ msgstr ""
+ 
+-#: fortran/decl.c:5764 fortran/decl.c:8178
++#: fortran/decl.c:5782 fortran/decl.c:8196
+ #, gcc-internal-format, gfc-internal-format
+ msgid "double colon in MODULE PROCEDURE statement at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:5834
++#: fortran/decl.c:5852
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROCEDURE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5906
++#: fortran/decl.c:5924
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected formal argument list in function definition at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:5930 fortran/decl.c:5934 fortran/decl.c:6190
+-#: fortran/decl.c:6194 fortran/decl.c:6386 fortran/decl.c:6390
++#: fortran/decl.c:5948 fortran/decl.c:5952 fortran/decl.c:6208
++#: fortran/decl.c:6212 fortran/decl.c:6404 fortran/decl.c:6408
+ #: fortran/symbol.c:1713
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BIND(C) attribute at %L can only be used for variables or common blocks"
+ msgstr ""
+ 
+-#: fortran/decl.c:6088
++#: fortran/decl.c:6106
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6097
++#: fortran/decl.c:6115
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a PROGRAM"
+ msgstr ""
+ 
+-#: fortran/decl.c:6100
++#: fortran/decl.c:6118
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a MODULE"
+ msgstr ""
+ 
+-#: fortran/decl.c:6103
++#: fortran/decl.c:6121
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a SUBMODULE"
+ msgstr ""
+ 
+-#: fortran/decl.c:6106
++#: fortran/decl.c:6124
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a BLOCK DATA"
+ msgstr ""
+ 
+-#: fortran/decl.c:6110 fortran/decl.c:6155
++#: fortran/decl.c:6128 fortran/decl.c:6173
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within an INTERFACE"
+ msgstr ""
+ 
+-#: fortran/decl.c:6114
++#: fortran/decl.c:6132
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a STRUCTURE block"
+ msgstr ""
+ 
+-#: fortran/decl.c:6118
++#: fortran/decl.c:6136
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a DERIVED TYPE block"
+ msgstr ""
+ 
+-#: fortran/decl.c:6122
++#: fortran/decl.c:6140
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within an IF-THEN block"
+ msgstr ""
+ 
+-#: fortran/decl.c:6127
++#: fortran/decl.c:6145
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a DO block"
+ msgstr ""
+ 
+-#: fortran/decl.c:6131
++#: fortran/decl.c:6149
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a SELECT block"
+ msgstr ""
+ 
+-#: fortran/decl.c:6135
++#: fortran/decl.c:6153
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a FORALL block"
+ msgstr ""
+ 
+-#: fortran/decl.c:6139
++#: fortran/decl.c:6157
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a WHERE block"
+ msgstr ""
+ 
+-#: fortran/decl.c:6143
++#: fortran/decl.c:6161
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear within a contained subprogram"
+ msgstr ""
+ 
+-#: fortran/decl.c:6147
++#: fortran/decl.c:6165
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected ENTRY statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6168
++#: fortran/decl.c:6186
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENTRY statement at %C cannot appear in a contained procedure"
+ msgstr ""
+ 
+-#: fortran/decl.c:6219 fortran/decl.c:6425
++#: fortran/decl.c:6237 fortran/decl.c:6443
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing required parentheses before BIND(C) at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6487 fortran/decl.c:6494
++#: fortran/decl.c:6505 fortran/decl.c:6512
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid C identifier in NAME= specifier at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6534
++#: fortran/decl.c:6552
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in NAME= specifier for binding label at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6550
++#: fortran/decl.c:6568
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NAME= specifier at %C should be a constant expression"
+ msgstr ""
+ 
+-#: fortran/decl.c:6558
++#: fortran/decl.c:6576
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NAME= specifier at %C should be a scalar of default character kind"
+ msgstr ""
+ 
+-#: fortran/decl.c:6577
++#: fortran/decl.c:6595
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing closing paren for binding label at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6583
++#: fortran/decl.c:6601
+ #, gcc-internal-format, gfc-internal-format
+ msgid "No binding name is allowed in BIND(C) at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6589
++#: fortran/decl.c:6607
+ #, gcc-internal-format, gfc-internal-format
+ msgid "For dummy procedure %s, no binding name is allowed in BIND(C) at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6618
++#: fortran/decl.c:6636
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NAME not allowed on BIND(C) for ABSTRACT INTERFACE at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6861
++#: fortran/decl.c:6879
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected END statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6870
++#: fortran/decl.c:6888
+ #, gcc-internal-format, gfc-internal-format
+ msgid "END statement instead of %s statement at %L"
+ msgstr ""
+ 
+ #. We would have required END [something].
+-#: fortran/decl.c:6879
++#: fortran/decl.c:6897
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement expected at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:6890
++#: fortran/decl.c:6908
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expecting %s statement at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:6910
++#: fortran/decl.c:6928
+ #, gcc-internal-format
+ msgid "Expected block name of %qs in %s statement at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:6927
++#: fortran/decl.c:6945
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected terminating name at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:6941 fortran/decl.c:6949
++#: fortran/decl.c:6959 fortran/decl.c:6967
+ #, gcc-internal-format
+ msgid "Expected label %qs for %s statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7048
++#: fortran/decl.c:7066
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing array specification at %L in DIMENSION statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:7056
++#: fortran/decl.c:7074
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Dimensions specified for %s at %L after its initialisation"
+ msgstr ""
+ 
+-#: fortran/decl.c:7064
++#: fortran/decl.c:7082
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing array specification at %L in CODIMENSION statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:7073
++#: fortran/decl.c:7091
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Array specification must be deferred at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:7171
++#: fortran/decl.c:7189
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected character in variable list at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7208
++#: fortran/decl.c:7226
+ #, gcc-internal-format
+ msgid "Expected %<(%> at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7222 fortran/decl.c:7262
++#: fortran/decl.c:7240 fortran/decl.c:7280
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected variable name at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7238
++#: fortran/decl.c:7256
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Cray pointer at %C must be an integer"
+ msgstr ""
+ 
+-#: fortran/decl.c:7242
++#: fortran/decl.c:7260
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Cray pointer at %C has %d bytes of precision; memory addresses require %d "
+@@ -49797,141 +49901,141 @@
+ "bytes"
+ msgstr ""
+ 
+-#: fortran/decl.c:7248
++#: fortran/decl.c:7266
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected \",\" at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7287
++#: fortran/decl.c:7305
+ #, gcc-internal-format
+ msgid "Couldn't set Cray pointee array spec."
+ msgstr ""
+ 
+-#: fortran/decl.c:7311
++#: fortran/decl.c:7329
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected \")\" at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7323
++#: fortran/decl.c:7341
+ #, gcc-internal-format
+ msgid "Expected %<,%> or end of statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7349
++#: fortran/decl.c:7367
+ #, gcc-internal-format, gfc-internal-format
+ msgid "INTENT is not allowed inside of BLOCK at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7381
++#: fortran/decl.c:7399
+ #, gcc-internal-format, gfc-internal-format
+ msgid "OPTIONAL is not allowed inside of BLOCK at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7400
++#: fortran/decl.c:7418
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Cray pointer declaration at %C requires -fcray-pointer flag"
+ msgstr ""
+ 
+-#: fortran/decl.c:7439
++#: fortran/decl.c:7457
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CONTIGUOUS statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7537
++#: fortran/decl.c:7555
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Access specification of the %s operator at %C has already been specified"
+ msgstr ""
+ 
+-#: fortran/decl.c:7554
++#: fortran/decl.c:7572
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Access specification of the .%s. operator at %C has already been specified"
+ msgstr ""
+ 
+-#: fortran/decl.c:7593
++#: fortran/decl.c:7611
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROTECTED statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7631
++#: fortran/decl.c:7649
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in PROTECTED statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7655
++#: fortran/decl.c:7673
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "PRIVATE statement at %C is only allowed in the specification part of a module"
+ msgstr ""
+ 
+-#: fortran/decl.c:7692
++#: fortran/decl.c:7710
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "PUBLIC statement at %C is only allowed in the specification part of a module"
+ msgstr ""
+ 
+-#: fortran/decl.c:7720
++#: fortran/decl.c:7738
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected variable name at %C in PARAMETER statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:7727
++#: fortran/decl.c:7745
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected = sign in PARAMETER statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7733
++#: fortran/decl.c:7751
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected expression at %C in PARAMETER statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:7753
++#: fortran/decl.c:7771
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Initializing already initialized variable at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7788
++#: fortran/decl.c:7806
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected characters in PARAMETER statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7812
++#: fortran/decl.c:7830
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Blanket SAVE statement at %C follows previous SAVE statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:7823
++#: fortran/decl.c:7841
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SAVE statement at %C follows blanket SAVE statement"
+ msgstr ""
+ 
+-#: fortran/decl.c:7869
++#: fortran/decl.c:7887
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in SAVE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7883
++#: fortran/decl.c:7901
+ #, gcc-internal-format, gfc-internal-format
+ msgid "VALUE is not allowed inside of BLOCK at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7887
++#: fortran/decl.c:7905
+ #, gcc-internal-format, gfc-internal-format
+ msgid "VALUE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7925
++#: fortran/decl.c:7943
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in VALUE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7936
++#: fortran/decl.c:7954
+ #, gcc-internal-format, gfc-internal-format
+ msgid "VOLATILE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7959
++#: fortran/decl.c:7977
+ #, gcc-internal-format
+ msgid ""
+ "Specifying VOLATILE for coarray variable %qs at %C, which is use-/host-"
+@@ -49938,269 +50042,269 @@
+ "associated"
+ msgstr ""
+ 
+-#: fortran/decl.c:7984
++#: fortran/decl.c:8002
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in VOLATILE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:7995
++#: fortran/decl.c:8013
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASYNCHRONOUS statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8035
++#: fortran/decl.c:8053
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in ASYNCHRONOUS statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8060
++#: fortran/decl.c:8078
+ #, gcc-internal-format, gfc-internal-format
+ msgid "MODULE PROCEDURE declaration at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8153
++#: fortran/decl.c:8171
+ #, gcc-internal-format, gfc-internal-format
+ msgid "MODULE PROCEDURE at %C must be in a generic module interface"
+ msgstr ""
+ 
+-#: fortran/decl.c:8211
++#: fortran/decl.c:8229
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Intrinsic procedure at %L cannot be a MODULE PROCEDURE"
+ msgstr ""
+ 
+-#: fortran/decl.c:8260
++#: fortran/decl.c:8278
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Ambiguous symbol in TYPE definition at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8269
++#: fortran/decl.c:8287
+ #, gcc-internal-format
+ msgid "Symbol %qs at %C has not been previously defined"
+ msgstr ""
+ 
+-#: fortran/decl.c:8275
++#: fortran/decl.c:8293
+ #, gcc-internal-format
+ msgid "%qs in EXTENDS expression at %C is not a derived type"
+ msgstr ""
+ 
+-#: fortran/decl.c:8282
++#: fortran/decl.c:8300
+ #, gcc-internal-format
+ msgid "%qs cannot be extended at %C because it is BIND(C)"
+ msgstr ""
+ 
+-#: fortran/decl.c:8289
++#: fortran/decl.c:8307
+ #, gcc-internal-format
+ msgid "%qs cannot be extended at %C because it is a SEQUENCE type"
+ msgstr ""
+ 
+-#: fortran/decl.c:8312
++#: fortran/decl.c:8330
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Derived type at %C can only be PRIVATE in the specification part of a module"
+ msgstr ""
+ 
+-#: fortran/decl.c:8324
++#: fortran/decl.c:8342
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Derived type at %C can only be PUBLIC in the specification part of a module"
+ msgstr ""
+ 
+-#: fortran/decl.c:8345
++#: fortran/decl.c:8363
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ABSTRACT type at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8391
++#: fortran/decl.c:8409
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Failed to create structure type '%s' at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8397
++#: fortran/decl.c:8415
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Type definition of '%s' at %C was already defined at %L"
+ msgstr ""
+ 
+-#: fortran/decl.c:8444
++#: fortran/decl.c:8462
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Junk after MAP statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8477
++#: fortran/decl.c:8495
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Junk after UNION statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8512
++#: fortran/decl.c:8530
+ #, gcc-internal-format, gfc-internal-format
+ msgid "STRUCTURE at %C is a DEC extension, enable with -fdec-structure"
+ msgstr ""
+ 
+-#: fortran/decl.c:8525
++#: fortran/decl.c:8543
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Structure name expected in non-nested structure declaration at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8543
++#: fortran/decl.c:8561
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Junk after non-nested STRUCTURE statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8550
++#: fortran/decl.c:8568
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Structure name '%s' at %C cannot be the same as an intrinsic type"
+ msgstr ""
+ 
+-#: fortran/decl.c:8611
++#: fortran/decl.c:8629
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected :: in TYPE definition at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8622
++#: fortran/decl.c:8640
+ #, gcc-internal-format
+ msgid "Type name %qs at %C cannot be the same as an intrinsic type"
+ msgstr ""
+ 
+-#: fortran/decl.c:8632
++#: fortran/decl.c:8650
+ #, gcc-internal-format
+ msgid "Derived type name %qs at %C already has a basic type of %s"
+ msgstr ""
+ 
+-#: fortran/decl.c:8649
++#: fortran/decl.c:8667
+ #, gcc-internal-format
+ msgid "Derived type definition of %qs at %C has already been defined"
+ msgstr ""
+ 
+-#: fortran/decl.c:8752
++#: fortran/decl.c:8770
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Cray Pointee at %C cannot be assumed shape array"
+ msgstr ""
+ 
+-#: fortran/decl.c:8772
++#: fortran/decl.c:8790
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENUM and ENUMERATOR at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8804
++#: fortran/decl.c:8822
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Enumerator exceeds the C integer type at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8883
++#: fortran/decl.c:8901
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENUMERATOR %L not initialized with integer expression"
+ msgstr ""
+ 
+-#: fortran/decl.c:8931
++#: fortran/decl.c:8949
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENUM definition statement expected before %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:8967
++#: fortran/decl.c:8985
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in ENUMERATOR definition at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9014 fortran/decl.c:9029
++#: fortran/decl.c:9032 fortran/decl.c:9047
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate access-specifier at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9049
++#: fortran/decl.c:9067
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Binding attributes already specify passing, illegal NOPASS at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9069
++#: fortran/decl.c:9087
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Binding attributes already specify passing, illegal PASS at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9096
++#: fortran/decl.c:9114
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate POINTER attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9114
++#: fortran/decl.c:9132
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate NON_OVERRIDABLE at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9130
++#: fortran/decl.c:9148
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate DEFERRED at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9143
++#: fortran/decl.c:9161
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected access-specifier at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9145
++#: fortran/decl.c:9163
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected binding attribute at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9153
++#: fortran/decl.c:9171
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NON_OVERRIDABLE and DEFERRED can't both appear at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9165
++#: fortran/decl.c:9183
+ #, gcc-internal-format, gfc-internal-format
+ msgid "POINTER attribute is required for procedure pointer component at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9207
++#: fortran/decl.c:9225
+ #, gcc-internal-format
+ msgid "Interface-name expected after %<(%> at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9213
++#: fortran/decl.c:9231
+ #, gcc-internal-format
+ msgid "%<)%> expected at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9233
++#: fortran/decl.c:9251
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Interface must be specified for DEFERRED binding at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9238
++#: fortran/decl.c:9256
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROCEDURE(interface) at %C should be declared DEFERRED"
+ msgstr ""
+ 
+-#: fortran/decl.c:9261
++#: fortran/decl.c:9279
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected binding name at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9265
++#: fortran/decl.c:9283
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROCEDURE list at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9277
++#: fortran/decl.c:9295
+ #, gcc-internal-format
+ msgid "%<=> target%> is invalid for DEFERRED binding at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9283
++#: fortran/decl.c:9301
+ #, gcc-internal-format
+ msgid "%<::%> needed in PROCEDURE binding with explicit target at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9293
++#: fortran/decl.c:9311
+ #, gcc-internal-format
+ msgid "Expected binding target after %<=>%> at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9310
++#: fortran/decl.c:9328
+ #, gcc-internal-format
+ msgid "Type %qs containing DEFERRED binding at %C is not ABSTRACT"
+ msgstr ""
+ 
+-#: fortran/decl.c:9321
++#: fortran/decl.c:9339
+ #, gcc-internal-format
+ msgid ""
+ "There is already a procedure with binding name %qs for the derived type %qs "
+@@ -50207,32 +50311,32 @@
+ "at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9370
++#: fortran/decl.c:9388
+ #, gcc-internal-format, gfc-internal-format
+ msgid "GENERIC at %C must be inside a derived-type CONTAINS"
+ msgstr ""
+ 
+-#: fortran/decl.c:9390
++#: fortran/decl.c:9408
+ #, gcc-internal-format
+ msgid "Expected %<::%> at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9402
++#: fortran/decl.c:9420
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected generic name or operator descriptor at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9422
++#: fortran/decl.c:9440
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Malformed GENERIC statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9433
++#: fortran/decl.c:9451
+ #, gcc-internal-format
+ msgid "Expected %<=>%> at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9475
++#: fortran/decl.c:9493
+ #, gcc-internal-format
+ msgid ""
+ "There's already a non-generic procedure with binding name %qs for the "
+@@ -50239,32 +50343,32 @@
+ "derived type %qs at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9483
++#: fortran/decl.c:9501
+ #, gcc-internal-format
+ msgid "Binding at %C must have the same access as already defined binding %qs"
+ msgstr ""
+ 
+-#: fortran/decl.c:9532
++#: fortran/decl.c:9550
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected specific binding name at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9542
++#: fortran/decl.c:9560
+ #, gcc-internal-format
+ msgid "%qs already defined as specific binding for the generic %qs at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9560
++#: fortran/decl.c:9578
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Junk after GENERIC binding at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9595
++#: fortran/decl.c:9613
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FINAL declaration at %C must be inside a derived type CONTAINS section"
+ msgstr ""
+ 
+-#: fortran/decl.c:9606
++#: fortran/decl.c:9624
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Derived type declaration with FINAL at %C must be in the specification part "
+@@ -50271,43 +50375,48 @@
+ "of a MODULE"
+ msgstr ""
+ 
+-#: fortran/decl.c:9628
++#: fortran/decl.c:9646
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Empty FINAL at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9635
++#: fortran/decl.c:9653
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected module procedure name at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9645
++#: fortran/decl.c:9663
+ #, gcc-internal-format
+ msgid "Expected %<,%> at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9651
++#: fortran/decl.c:9669
+ #, gcc-internal-format
+ msgid "Unknown procedure name %qs at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9664
++#: fortran/decl.c:9682
+ #, gcc-internal-format
+ msgid "%qs at %C is already defined as FINAL procedure!"
+ msgstr ""
+ 
+-#: fortran/decl.c:9734
++#: fortran/decl.c:9752
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unknown attribute in !GCC$ ATTRIBUTES statement at %C"
+ msgstr ""
+ 
+-#: fortran/decl.c:9780
++#: fortran/decl.c:9798
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in !GCC$ ATTRIBUTES statement at %C"
+ msgstr ""
+ 
+-#: fortran/dependency.c:191
++#: fortran/dependency.c:105
+ #, gcc-internal-format
++msgid "identical_array_ref(): inconsistent dimensions"
++msgstr ""
++
++#: fortran/dependency.c:193
++#, gcc-internal-format
+ msgid "are_identical_variables: Bad type"
+ msgstr ""
+ 
+@@ -50316,12 +50425,17 @@
+ #. If a dependency is found in the case
+ #. elemental == ELEM_CHECK_VARIABLE, we will generate
+ #. a temporary, so we don't need to bother the user.
+-#: fortran/dependency.c:958
++#: fortran/dependency.c:977
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "INTENT(%s) actual argument at %L might interfere with actual argument at %L."
+ msgstr ""
+ 
++#: fortran/dependency.c:1281
++#, gcc-internal-format
++msgid "gfc_check_dependency: expecting an EXPR_VARIABLE"
++msgstr ""
++
+ #: fortran/dump-parse-tree.c:188
+ #, gcc-internal-format
+ msgid "show_array_spec(): Unhandled array shape type."
+@@ -50625,18 +50739,18 @@
+ msgid "BOZ literal at %L used to initialize non-integer variable %qs"
+ msgstr ""
+ 
+-#: fortran/expr.c:3252 fortran/resolve.c:9548
++#: fortran/expr.c:3252 fortran/resolve.c:9586
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "BOZ literal at %L outside a DATA statement and outside INT/REAL/DBLE/CMPLX"
+ msgstr ""
+ 
+-#: fortran/expr.c:3263 fortran/resolve.c:9559
++#: fortran/expr.c:3263 fortran/resolve.c:9597
+ #, gcc-internal-format
+ msgid "BOZ literal at %L is bitwise transferred non-integer symbol %qs"
+ msgstr ""
+ 
+-#: fortran/expr.c:3271 fortran/resolve.c:9568
++#: fortran/expr.c:3271 fortran/resolve.c:9606
+ #, gcc-internal-format
+ msgid ""
+ "Arithmetic underflow of bit-wise transferred BOZ at %L. This check can be "
+@@ -50643,7 +50757,7 @@
+ "disabled with the option %<-fno-range-check%>"
+ msgstr ""
+ 
+-#: fortran/expr.c:3275 fortran/resolve.c:9572
++#: fortran/expr.c:3275 fortran/resolve.c:9610
+ #, gcc-internal-format
+ msgid ""
+ "Arithmetic overflow of bit-wise transferred BOZ at %L. This check can be "
+@@ -50650,7 +50764,7 @@
+ "disabled with the option %<-fno-range-check%>"
+ msgstr ""
+ 
+-#: fortran/expr.c:3279 fortran/resolve.c:9576
++#: fortran/expr.c:3279 fortran/resolve.c:9614
+ #, gcc-internal-format
+ msgid ""
+ "Arithmetic NaN of bit-wise transferred BOZ at %L. This check can be disabled "
+@@ -50906,19 +51020,19 @@
+ msgid "LOCK_EVENT in variable definition context (%s) at %L"
+ msgstr ""
+ 
+-#: fortran/expr.c:4904
++#: fortran/expr.c:4905
+ #, gcc-internal-format
+ msgid ""
+ "Dummy argument %qs with INTENT(IN) in pointer association context (%s) at %L"
+ msgstr ""
+ 
+-#: fortran/expr.c:4912
++#: fortran/expr.c:4913
+ #, gcc-internal-format
+ msgid ""
+ "Dummy argument %qs with INTENT(IN) in variable definition context (%s) at %L"
+ msgstr ""
+ 
+-#: fortran/expr.c:4925
++#: fortran/expr.c:4926
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs is PROTECTED and can not appear in a pointer association "
+@@ -50925,7 +51039,7 @@
+ "context (%s) at %L"
+ msgstr ""
+ 
+-#: fortran/expr.c:4933
++#: fortran/expr.c:4934
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs is PROTECTED and can not appear in a variable definition "
+@@ -50932,7 +51046,7 @@
+ "context (%s) at %L"
+ msgstr ""
+ 
+-#: fortran/expr.c:4945
++#: fortran/expr.c:4946
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs can not appear in a variable definition context (%s) at %L in "
+@@ -50939,7 +51053,7 @@
+ "PURE procedure"
+ msgstr ""
+ 
+-#: fortran/expr.c:5004
++#: fortran/expr.c:5005
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %L associated to vector-indexed target can not be used in a variable "
+@@ -50946,7 +51060,7 @@
+ "definition context (%s)"
+ msgstr ""
+ 
+-#: fortran/expr.c:5008
++#: fortran/expr.c:5009
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %L associated to expression can not be used in a variable definition "
+@@ -50953,7 +51067,7 @@
+ "context (%s)"
+ msgstr ""
+ 
+-#: fortran/expr.c:5019
++#: fortran/expr.c:5020
+ #, gcc-internal-format
+ msgid ""
+ "Associate-name %qs can not appear in a variable definition context (%s) at "
+@@ -50960,7 +51074,7 @@
+ "%L because its target at %L can not, either"
+ msgstr ""
+ 
+-#: fortran/expr.c:5061
++#: fortran/expr.c:5062
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Elements with the same value at %L and %L in vector subscript in a variable "
+@@ -50972,29 +51086,29 @@
+ msgid "can't open input file: %s"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:311
++#: fortran/frontend-passes.c:326
+ #, gcc-internal-format
+ msgid "Illegal id in copy_walk_reduction_arg"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:711 fortran/trans-array.c:1044
++#: fortran/frontend-passes.c:726 fortran/trans-array.c:1044
+ #: fortran/trans-array.c:6179 fortran/trans-array.c:7535
+-#: fortran/trans-intrinsic.c:6278
++#: fortran/trans-intrinsic.c:6291
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Creating array temporary at %L"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:735 fortran/frontend-passes.c:738
++#: fortran/frontend-passes.c:750 fortran/frontend-passes.c:753
+ #, gcc-internal-format
+ msgid "Removing call to function %qs at %L"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:1718
++#: fortran/frontend-passes.c:1741
+ #, gcc-internal-format
+ msgid "illegal OP in optimize_comparison"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:1910
++#: fortran/frontend-passes.c:1933
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L set to undefined value inside loop  beginning at %L as "
+@@ -51001,7 +51115,7 @@
+ "INTENT(OUT) argument to subroutine %qs"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:1917
++#: fortran/frontend-passes.c:1940
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L not definable inside loop beginning at %L as "
+@@ -51008,7 +51122,7 @@
+ "INTENT(INOUT) argument to subroutine %qs"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:1982
++#: fortran/frontend-passes.c:2005
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L set to undefined value inside loop beginning at %L as "
+@@ -51015,7 +51129,7 @@
+ "INTENT(OUT) argument to function %qs"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:1988
++#: fortran/frontend-passes.c:2011
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L not definable inside loop beginning at %L as "
+@@ -51022,12 +51136,12 @@
+ "INTENT(INOUT) argument to function %qs"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:2236 fortran/trans-expr.c:1522
++#: fortran/frontend-passes.c:2259 fortran/trans-expr.c:1548
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Code for reallocating the allocatable array at %L will be added"
+ msgstr ""
+ 
+-#: fortran/frontend-passes.c:2715
++#: fortran/frontend-passes.c:2738
+ #, gcc-internal-format
+ msgid "Scalarization using DIMEN_RANGE unimplemented"
+ msgstr ""
+@@ -51102,27 +51216,32 @@
+ msgid "Expecting %<END INTERFACE %s%> at %C"
+ msgstr ""
+ 
+-#: fortran/interface.c:769
++#: fortran/interface.c:521
++#, gcc-internal-format
++msgid "gfc_compare_derived_types: invalid derived type"
++msgstr ""
++
++#: fortran/interface.c:770
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Alternate return cannot appear in operator interface at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:798
++#: fortran/interface.c:799
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assignment operator interface at %L must have two arguments"
+ msgstr ""
+ 
+-#: fortran/interface.c:801
++#: fortran/interface.c:802
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Operator interface at %L has the wrong number of arguments"
+ msgstr ""
+ 
+-#: fortran/interface.c:814
++#: fortran/interface.c:815
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assignment operator interface at %L must be a SUBROUTINE"
+ msgstr ""
+ 
+-#: fortran/interface.c:832
++#: fortran/interface.c:833
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Assignment operator interface at %L must not redefine an INTRINSIC type "
+@@ -51129,12 +51248,12 @@
+ "assignment"
+ msgstr ""
+ 
+-#: fortran/interface.c:841
++#: fortran/interface.c:842
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Intrinsic operator interface at %L must be a FUNCTION"
+ msgstr ""
+ 
+-#: fortran/interface.c:852
++#: fortran/interface.c:853
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "First argument of defined assignment at %L must be INTENT(OUT) or "
+@@ -51141,33 +51260,33 @@
+ "INTENT(INOUT)"
+ msgstr ""
+ 
+-#: fortran/interface.c:859
++#: fortran/interface.c:860
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Second argument of defined assignment at %L must be INTENT(IN)"
+ msgstr ""
+ 
+-#: fortran/interface.c:868 fortran/resolve.c:15452
++#: fortran/interface.c:869 fortran/resolve.c:15523
+ #, gcc-internal-format, gfc-internal-format
+ msgid "First argument of operator interface at %L must be INTENT(IN)"
+ msgstr ""
+ 
+-#: fortran/interface.c:875 fortran/resolve.c:15470
++#: fortran/interface.c:876 fortran/resolve.c:15541
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Second argument of operator interface at %L must be INTENT(IN)"
+ msgstr ""
+ 
+-#: fortran/interface.c:980
++#: fortran/interface.c:981
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Operator interface at %L conflicts with intrinsic interface"
+ msgstr ""
+ 
+-#: fortran/interface.c:1312 fortran/interface.c:1371
++#: fortran/interface.c:1313 fortran/interface.c:1372
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "check_dummy_characteristics: Unexpected result %i of gfc_dep_compare_expr"
+ msgstr ""
+ 
+-#: fortran/interface.c:1484
++#: fortran/interface.c:1485
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "check_result_characteristics (1): Unexpected result %i of "
+@@ -51174,7 +51293,7 @@
+ "gfc_dep_compare_expr"
+ msgstr ""
+ 
+-#: fortran/interface.c:1531
++#: fortran/interface.c:1532
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "check_result_characteristics (2): Unexpected result %i of "
+@@ -51181,22 +51300,22 @@
+ "gfc_dep_compare_expr"
+ msgstr ""
+ 
+-#: fortran/interface.c:1698
++#: fortran/interface.c:1708
+ #, gcc-internal-format
+ msgid "Procedure %qs in %s at %L has no explicit interface"
+ msgstr ""
+ 
+-#: fortran/interface.c:1701
++#: fortran/interface.c:1711
+ #, gcc-internal-format
+ msgid "Procedure %qs in %s at %L is neither function nor subroutine"
+ msgstr ""
+ 
+-#: fortran/interface.c:1713
++#: fortran/interface.c:1723
+ #, gcc-internal-format, gfc-internal-format
+ msgid "In %s at %L procedures must be either all SUBROUTINEs or all FUNCTIONs"
+ msgstr ""
+ 
+-#: fortran/interface.c:1717
++#: fortran/interface.c:1727
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "In %s at %L procedures must be all FUNCTIONs as the generic name is also the "
+@@ -51203,27 +51322,27 @@
+ "name of a derived type"
+ msgstr ""
+ 
+-#: fortran/interface.c:1725
++#: fortran/interface.c:1735
+ #, gcc-internal-format
+ msgid "Internal procedure %qs in %s at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:1782 fortran/interface.c:1786
++#: fortran/interface.c:1792 fortran/interface.c:1797
+ #, gcc-internal-format
+-msgid "Ambiguous interfaces %qs and %qs in %s at %L"
++msgid "Ambiguous interfaces in %s for %qs at %L and %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:1790
++#: fortran/interface.c:1802
+ #, gcc-internal-format
+ msgid "Although not referenced, %qs has ambiguous interfaces at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:1825
++#: fortran/interface.c:1837
+ #, gcc-internal-format
+ msgid "%qs at %L is not a module procedure"
+ msgstr ""
+ 
+-#: fortran/interface.c:2029
++#: fortran/interface.c:2041
+ #, gcc-internal-format
+ msgid ""
+ "The assumed-rank array at %L requires that the dummy argument %qs has "
+@@ -51230,32 +51349,32 @@
+ "assumed-rank"
+ msgstr ""
+ 
+-#: fortran/interface.c:2034
++#: fortran/interface.c:2046
+ #, gcc-internal-format
+ msgid "Rank mismatch in argument %qs at %L (scalar and rank-%d)"
+ msgstr ""
+ 
+-#: fortran/interface.c:2039
++#: fortran/interface.c:2051
+ #, gcc-internal-format
+ msgid "Rank mismatch in argument %qs at %L (rank-%d and scalar)"
+ msgstr ""
+ 
+-#: fortran/interface.c:2044
++#: fortran/interface.c:2056
+ #, gcc-internal-format
+ msgid "Rank mismatch in argument %qs at %L (rank-%d and rank-%d)"
+ msgstr ""
+ 
+-#: fortran/interface.c:2087
++#: fortran/interface.c:2099
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid procedure argument at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2095 fortran/interface.c:2122
++#: fortran/interface.c:2107 fortran/interface.c:2134
+ #, gcc-internal-format
+ msgid "Interface mismatch in dummy procedure %qs at %L: %s"
+ msgstr ""
+ 
+-#: fortran/interface.c:2133
++#: fortran/interface.c:2145
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument to contiguous pointer dummy %qs at %L must be simply "
+@@ -51262,12 +51381,12 @@
+ "contiguous"
+ msgstr ""
+ 
+-#: fortran/interface.c:2148
++#: fortran/interface.c:2160
+ #, gcc-internal-format
+ msgid "Type mismatch in argument %qs at %L; passed %s to %s"
+ msgstr ""
+ 
+-#: fortran/interface.c:2157
++#: fortran/interface.c:2169
+ #, gcc-internal-format
+ msgid ""
+ "Assumed-type actual argument at %L requires that dummy argument %qs is of "
+@@ -51274,17 +51393,17 @@
+ "assumed type"
+ msgstr ""
+ 
+-#: fortran/interface.c:2173
++#: fortran/interface.c:2185
+ #, gcc-internal-format
+ msgid "Actual argument to %qs at %L must be polymorphic"
+ msgstr ""
+ 
+-#: fortran/interface.c:2186
++#: fortran/interface.c:2198
+ #, gcc-internal-format
+ msgid "Actual argument to %qs at %L must have the same declared type"
+ msgstr ""
+ 
+-#: fortran/interface.c:2201
++#: fortran/interface.c:2213
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument to %qs at %L must be unlimited polymorphic since the formal "
+@@ -51292,17 +51411,17 @@
+ "12.5.2.5]"
+ msgstr ""
+ 
+-#: fortran/interface.c:2212
++#: fortran/interface.c:2224
+ #, gcc-internal-format
+ msgid "Actual argument to %qs at %L must be a coarray"
+ msgstr ""
+ 
+-#: fortran/interface.c:2231
++#: fortran/interface.c:2243
+ #, gcc-internal-format
+ msgid "Corank mismatch in argument %qs at %L (%d and %d)"
+ msgstr ""
+ 
+-#: fortran/interface.c:2249
++#: fortran/interface.c:2261
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument to %qs at %L must be simply contiguous or an element of such "
+@@ -51309,7 +51428,7 @@
+ "an array"
+ msgstr ""
+ 
+-#: fortran/interface.c:2264
++#: fortran/interface.c:2276
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument to non-INTENT(INOUT) dummy %qs at %L, which is LOCK_TYPE or "
+@@ -51316,7 +51435,7 @@
+ "has a LOCK_TYPE component"
+ msgstr ""
+ 
+-#: fortran/interface.c:2279
++#: fortran/interface.c:2291
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument to non-INTENT(INOUT) dummy %qs at %L, which is EVENT_TYPE or "
+@@ -51323,7 +51442,7 @@
+ "has a EVENT_TYPE component"
+ msgstr ""
+ 
+-#: fortran/interface.c:2298
++#: fortran/interface.c:2310
+ #, gcc-internal-format
+ msgid ""
+ "Dummy argument %qs has to be a pointer, assumed-shape or assumed-rank array "
+@@ -51331,7 +51450,7 @@
+ "contiguous and both are ASYNCHRONOUS or VOLATILE"
+ msgstr ""
+ 
+-#: fortran/interface.c:2311
++#: fortran/interface.c:2323
+ #, gcc-internal-format
+ msgid ""
+ "Passing coarray at %L to allocatable, noncoarray, INTENT(OUT) dummy argument "
+@@ -51338,7 +51457,7 @@
+ "%qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:2318
++#: fortran/interface.c:2330
+ #, gcc-internal-format
+ msgid ""
+ "Passing coarray at %L to allocatable, noncoarray dummy argument %qs, which "
+@@ -51345,12 +51464,12 @@
+ "is invalid if the allocation status is modified"
+ msgstr ""
+ 
+-#: fortran/interface.c:2381
++#: fortran/interface.c:2393
+ #, gcc-internal-format
+ msgid "Polymorphic scalar passed to array dummy argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2390
++#: fortran/interface.c:2402
+ #, gcc-internal-format
+ msgid ""
+ "Element of assumed-shaped or pointer array passed to array dummy argument "
+@@ -51357,7 +51476,7 @@
+ "%qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2402
++#: fortran/interface.c:2414
+ #, gcc-internal-format
+ msgid ""
+ "Extension: Scalar non-default-kind, non-C_CHAR-kind CHARACTER actual "
+@@ -51364,7 +51483,7 @@
+ "argument with array dummy argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2410
++#: fortran/interface.c:2422
+ #, gcc-internal-format
+ msgid ""
+ "Fortran 2003: Scalar CHARACTER actual argument with array dummy argument %qs "
+@@ -51371,43 +51490,43 @@
+ "at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2739
++#: fortran/interface.c:2751
+ #, gcc-internal-format
+ msgid "Keyword argument %qs at %L is not in the procedure"
+ msgstr ""
+ 
+-#: fortran/interface.c:2747
++#: fortran/interface.c:2759
+ #, gcc-internal-format
+ msgid ""
+ "Keyword argument %qs at %L is already associated with another actual argument"
+ msgstr ""
+ 
+-#: fortran/interface.c:2757
++#: fortran/interface.c:2769
+ #, gcc-internal-format, gfc-internal-format
+ msgid "More actual than formal arguments in procedure call at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2769 fortran/interface.c:3139
++#: fortran/interface.c:2781 fortran/interface.c:3151
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing alternate return spec in subroutine call at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2777
++#: fortran/interface.c:2789
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected alternate return spec in subroutine call at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2804
++#: fortran/interface.c:2816
+ #, gcc-internal-format
+ msgid "Unexpected NULL() intrinsic at %L to dummy %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:2807
++#: fortran/interface.c:2819
+ #, gcc-internal-format
+ msgid "Fortran 2008: Null pointer at %L to non-pointer dummy %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:2831
++#: fortran/interface.c:2843
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Actual argument at %L to assumed-type dummy is of derived type with type-"
+@@ -51414,7 +51533,7 @@
+ "bound or FINAL procedures"
+ msgstr ""
+ 
+-#: fortran/interface.c:2853
++#: fortran/interface.c:2865
+ #, gcc-internal-format
+ msgid ""
+ "Character length mismatch (%ld/%ld) between actual argument and pointer or "
+@@ -51421,7 +51540,7 @@
+ "allocatable dummy argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2861
++#: fortran/interface.c:2873
+ #, gcc-internal-format
+ msgid ""
+ "Character length mismatch (%ld/%ld) between actual argument and assumed-"
+@@ -51428,7 +51547,7 @@
+ "shape dummy argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2875
++#: fortran/interface.c:2887
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument at %L to allocatable or pointer dummy argument %qs must have "
+@@ -51435,7 +51554,7 @@
+ "a deferred length type parameter if and only if the dummy has one"
+ msgstr ""
+ 
+-#: fortran/interface.c:2892
++#: fortran/interface.c:2904
+ #, gcc-internal-format
+ msgid ""
+ "Character length of actual argument shorter than of dummy argument %qs (%lu/"
+@@ -51442,7 +51561,7 @@
+ "%lu) at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2897
++#: fortran/interface.c:2909
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument contains too few elements for dummy argument %qs (%lu/%lu) "
+@@ -51449,43 +51568,43 @@
+ "at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2916
++#: fortran/interface.c:2928
+ #, gcc-internal-format
+ msgid "Expected a procedure pointer for argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2932
++#: fortran/interface.c:2944
+ #, gcc-internal-format
+ msgid "Expected a procedure for argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2946
++#: fortran/interface.c:2958
+ #, gcc-internal-format
+ msgid "Actual argument for %qs cannot be an assumed-size array at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2955
++#: fortran/interface.c:2967
+ #, gcc-internal-format
+ msgid "Actual argument for %qs must be a pointer at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:2965
++#: fortran/interface.c:2977
+ #, gcc-internal-format
+ msgid "Fortran 2008: Non-pointer actual argument at %L to pointer dummy %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:2975
++#: fortran/interface.c:2987
+ #, gcc-internal-format
+ msgid "Coindexed actual argument at %L to pointer dummy %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:2988
++#: fortran/interface.c:3000
+ #, gcc-internal-format
+ msgid ""
+ "Coindexed actual argument at %L to allocatable dummy %qs requires INTENT(IN)"
+ msgstr ""
+ 
+-#: fortran/interface.c:3002
++#: fortran/interface.c:3014
+ #, gcc-internal-format
+ msgid ""
+ "Coindexed ASYNCHRONOUS or VOLATILE actual argument at %L requires that dummy "
+@@ -51492,7 +51611,7 @@
+ "%qs has neither ASYNCHRONOUS nor VOLATILE"
+ msgstr ""
+ 
+-#: fortran/interface.c:3016
++#: fortran/interface.c:3028
+ #, gcc-internal-format
+ msgid ""
+ "Coindexed actual argument at %L with allocatable ultimate component to dummy "
+@@ -51499,17 +51618,17 @@
+ "%qs requires either VALUE or INTENT(IN)"
+ msgstr ""
+ 
+-#: fortran/interface.c:3028
++#: fortran/interface.c:3040
+ #, gcc-internal-format
+ msgid "Actual CLASS array argument for %qs must be a full array at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3038
++#: fortran/interface.c:3050
+ #, gcc-internal-format
+ msgid "Actual argument for %qs must be ALLOCATABLE at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3067
++#: fortran/interface.c:3079
+ #, gcc-internal-format
+ msgid ""
+ "Array-section actual argument with vector subscripts at %L is incompatible "
+@@ -51517,7 +51636,7 @@
+ "dummy argument %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:3085
++#: fortran/interface.c:3097
+ #, gcc-internal-format
+ msgid ""
+ "Assumed-shape actual argument at %L is incompatible with the non-assumed-"
+@@ -51524,7 +51643,7 @@
+ "shape dummy argument %qs due to VOLATILE attribute"
+ msgstr ""
+ 
+-#: fortran/interface.c:3097
++#: fortran/interface.c:3109
+ #, gcc-internal-format
+ msgid ""
+ "Array-section actual argument at %L is incompatible with the non-assumed-"
+@@ -51531,7 +51650,7 @@
+ "shape dummy argument %qs due to VOLATILE attribute"
+ msgstr ""
+ 
+-#: fortran/interface.c:3116
++#: fortran/interface.c:3128
+ #, gcc-internal-format
+ msgid ""
+ "Pointer-array actual argument at %L requires an assumed-shape or pointer-"
+@@ -51538,27 +51657,27 @@
+ "array dummy argument %qs due to VOLATILE attribute"
+ msgstr ""
+ 
+-#: fortran/interface.c:3146
++#: fortran/interface.c:3158
+ #, gcc-internal-format
+ msgid "Missing actual argument for argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3263
++#: fortran/interface.c:3275
+ #, gcc-internal-format
+ msgid "compare_actual_expr(): Bad component code"
+ msgstr ""
+ 
+-#: fortran/interface.c:3292
++#: fortran/interface.c:3304
+ #, gcc-internal-format
+ msgid "check_some_aliasing(): List mismatch"
+ msgstr ""
+ 
+-#: fortran/interface.c:3318
++#: fortran/interface.c:3330
+ #, gcc-internal-format
+ msgid "check_some_aliasing(): corrupted data"
+ msgstr ""
+ 
+-#: fortran/interface.c:3328
++#: fortran/interface.c:3340
+ #, gcc-internal-format
+ msgid ""
+ "Same actual argument associated with INTENT(%s) argument %qs and INTENT(%s) "
+@@ -51565,12 +51684,12 @@
+ "argument %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3358
++#: fortran/interface.c:3370
+ #, gcc-internal-format
+ msgid "check_intents(): List mismatch"
+ msgstr ""
+ 
+-#: fortran/interface.c:3378
++#: fortran/interface.c:3390
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Procedure argument at %L is local to a PURE procedure and has the POINTER "
+@@ -51577,7 +51696,7 @@
+ "attribute"
+ msgstr ""
+ 
+-#: fortran/interface.c:3390
++#: fortran/interface.c:3402
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Coindexed actual argument at %L in PURE procedure is passed to an INTENT(%s) "
+@@ -51584,7 +51703,7 @@
+ "argument"
+ msgstr ""
+ 
+-#: fortran/interface.c:3400
++#: fortran/interface.c:3412
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Coindexed actual argument at %L in PURE procedure is passed to a POINTER "
+@@ -51591,7 +51710,7 @@
+ "dummy argument"
+ msgstr ""
+ 
+-#: fortran/interface.c:3411
++#: fortran/interface.c:3423
+ #, gcc-internal-format
+ msgid ""
+ "Coindexed polymorphic actual argument at %L is passed polymorphic dummy "
+@@ -51598,17 +51717,17 @@
+ "argument %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:3439 fortran/interface.c:3449
++#: fortran/interface.c:3451 fortran/interface.c:3461
+ #, gcc-internal-format
+ msgid "Procedure %qs called at %L is not explicitly declared"
+ msgstr ""
+ 
+-#: fortran/interface.c:3445
++#: fortran/interface.c:3457
+ #, gcc-internal-format
+ msgid "Procedure %qs called with an implicit interface at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3459
++#: fortran/interface.c:3471
+ #, gcc-internal-format
+ msgid ""
+ "The pointer object %qs at %L must have an explicit function interface or be "
+@@ -51615,7 +51734,7 @@
+ "declared as array"
+ msgstr ""
+ 
+-#: fortran/interface.c:3467
++#: fortran/interface.c:3479
+ #, gcc-internal-format
+ msgid ""
+ "The allocatable object %qs at %L must have an explicit function interface or "
+@@ -51622,22 +51741,22 @@
+ "be declared as array"
+ msgstr ""
+ 
+-#: fortran/interface.c:3475
++#: fortran/interface.c:3487
+ #, gcc-internal-format
+ msgid "Allocatable function %qs at %L must have an explicit function interface"
+ msgstr ""
+ 
+-#: fortran/interface.c:3485
++#: fortran/interface.c:3497
+ #, gcc-internal-format
+ msgid "Keyword argument requires explicit interface for procedure %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3494
++#: fortran/interface.c:3506
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed-type argument %s at %L requires an explicit interface"
+ msgstr ""
+ 
+-#: fortran/interface.c:3507
++#: fortran/interface.c:3519
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument of LOCK_TYPE or with LOCK_TYPE component at %L requires an "
+@@ -51644,7 +51763,7 @@
+ "explicit interface for procedure %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:3520
++#: fortran/interface.c:3532
+ #, gcc-internal-format
+ msgid ""
+ "Actual argument of EVENT_TYPE or with EVENT_TYPE component at %L requires an "
+@@ -51651,22 +51770,22 @@
+ "explicit interface for procedure %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:3529
++#: fortran/interface.c:3541
+ #, gcc-internal-format, gfc-internal-format
+ msgid "MOLD argument to NULL required at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3537
++#: fortran/interface.c:3549
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed-rank argument requires an explicit interface at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3575
++#: fortran/interface.c:3587
+ #, gcc-internal-format
+ msgid "Procedure pointer component %qs called with an implicit interface at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3586
++#: fortran/interface.c:3598
+ #, gcc-internal-format
+ msgid ""
+ "Keyword argument requires explicit interface for procedure pointer component "
+@@ -51673,7 +51792,7 @@
+ "%qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:3671
++#: fortran/interface.c:3683
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "MOLD= required in NULL() argument at %L: Ambiguity between specific "
+@@ -51680,47 +51799,47 @@
+ "functions %s and %s"
+ msgstr ""
+ 
+-#: fortran/interface.c:3741
++#: fortran/interface.c:3753
+ #, gcc-internal-format
+ msgid "Unable to find symbol %qs"
+ msgstr ""
+ 
+-#: fortran/interface.c:4108
++#: fortran/interface.c:4120
+ #, gcc-internal-format
+ msgid "Entity %qs at %L is already present in the interface"
+ msgstr ""
+ 
+-#: fortran/interface.c:4224
++#: fortran/interface.c:4236
+ #, gcc-internal-format
+ msgid "gfc_add_interface(): Bad interface type"
+ msgstr ""
+ 
+-#: fortran/interface.c:4319
++#: fortran/interface.c:4331
+ #, gcc-internal-format
+ msgid "Can't overwrite GENERIC %qs at %L"
+ msgstr ""
+ 
+-#: fortran/interface.c:4331
++#: fortran/interface.c:4343
+ #, gcc-internal-format
+ msgid "%qs at %L overrides a procedure binding declared NON_OVERRIDABLE"
+ msgstr ""
+ 
+-#: fortran/interface.c:4339
++#: fortran/interface.c:4351
+ #, gcc-internal-format
+ msgid "%qs at %L must not be DEFERRED as it overrides a non-DEFERRED binding"
+ msgstr ""
+ 
+-#: fortran/interface.c:4347
++#: fortran/interface.c:4359
+ #, gcc-internal-format
+ msgid "%qs at %L overrides a PURE procedure and must also be PURE"
+ msgstr ""
+ 
+-#: fortran/interface.c:4356
++#: fortran/interface.c:4368
+ #, gcc-internal-format
+ msgid "%qs at %L overrides an ELEMENTAL procedure and must also be ELEMENTAL"
+ msgstr ""
+ 
+-#: fortran/interface.c:4362
++#: fortran/interface.c:4374
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %L overrides a non-ELEMENTAL procedure and must not be ELEMENTAL, "
+@@ -51727,27 +51846,27 @@
+ "either"
+ msgstr ""
+ 
+-#: fortran/interface.c:4371
++#: fortran/interface.c:4383
+ #, gcc-internal-format
+ msgid "%qs at %L overrides a SUBROUTINE and must also be a SUBROUTINE"
+ msgstr ""
+ 
+-#: fortran/interface.c:4382
++#: fortran/interface.c:4394
+ #, gcc-internal-format
+ msgid "%qs at %L overrides a FUNCTION and must also be a FUNCTION"
+ msgstr ""
+ 
+-#: fortran/interface.c:4390
++#: fortran/interface.c:4402
+ #, gcc-internal-format
+ msgid "Result mismatch for the overriding procedure %qs at %L: %s"
+ msgstr ""
+ 
+-#: fortran/interface.c:4401
++#: fortran/interface.c:4413
+ #, gcc-internal-format
+ msgid "%qs at %L overrides a PUBLIC procedure and must not be PRIVATE"
+ msgstr ""
+ 
+-#: fortran/interface.c:4431
++#: fortran/interface.c:4443
+ #, gcc-internal-format
+ msgid ""
+ "Dummy argument %qs of %qs at %L should be named %qs as to match the "
+@@ -51754,12 +51873,12 @@
+ "corresponding argument of the overridden procedure"
+ msgstr ""
+ 
+-#: fortran/interface.c:4442
++#: fortran/interface.c:4454
+ #, gcc-internal-format
+ msgid "Argument mismatch for the overriding procedure %qs at %L: %s"
+ msgstr ""
+ 
+-#: fortran/interface.c:4451
++#: fortran/interface.c:4463
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %L must have the same number of formal arguments as the overridden "
+@@ -51766,17 +51885,17 @@
+ "procedure"
+ msgstr ""
+ 
+-#: fortran/interface.c:4460
++#: fortran/interface.c:4472
+ #, gcc-internal-format
+ msgid "%qs at %L overrides a NOPASS binding and must also be NOPASS"
+ msgstr ""
+ 
+-#: fortran/interface.c:4471
++#: fortran/interface.c:4483
+ #, gcc-internal-format
+ msgid "%qs at %L overrides a binding with PASS and must also be PASS"
+ msgstr ""
+ 
+-#: fortran/interface.c:4478
++#: fortran/interface.c:4490
+ #, gcc-internal-format
+ msgid ""
+ "Passed-object dummy argument of %qs at %L must be at the same position as "
+@@ -51841,12 +51960,12 @@
+ msgid "make_generic(): Can't find generic symbol %qs"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:3871
++#: fortran/intrinsic.c:3872
+ #, gcc-internal-format
+ msgid "Too many arguments in call to %qs at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:3886
++#: fortran/intrinsic.c:3887
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The argument list functions %%VAL, %%LOC or %%REF are not allowed in this "
+@@ -51853,62 +51972,62 @@
+ "context at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:3889
++#: fortran/intrinsic.c:3890
+ #, gcc-internal-format
+ msgid "Can't find keyword named %qs in call to %qs at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:3896
++#: fortran/intrinsic.c:3897
+ #, gcc-internal-format
+ msgid "Argument %qs appears twice in call to %qs at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:3910
++#: fortran/intrinsic.c:3911
+ #, gcc-internal-format
+ msgid "Missing actual argument %qs in call to %qs at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:3925
++#: fortran/intrinsic.c:3926
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ALTERNATE RETURN not permitted at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:3982
++#: fortran/intrinsic.c:3983
+ #, gcc-internal-format
+ msgid "Type of argument %qs in call to %qs at %L should be %s, not %s"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4088
++#: fortran/intrinsic.c:4089
+ #, gcc-internal-format
+ msgid "resolve_intrinsic(): Too many args for intrinsic"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4174
++#: fortran/intrinsic.c:4175
+ #, gcc-internal-format
+ msgid "do_simplify(): Too many args for intrinsic"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4213
++#: fortran/intrinsic.c:4214
+ #, gcc-internal-format
+ msgid "init_arglist(): too many arguments"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4363
++#: fortran/intrinsic.c:4364
+ #, gcc-internal-format
+ msgid "Invalid standard code on intrinsic %qs (%d)"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4372
++#: fortran/intrinsic.c:4373
+ #, gcc-internal-format
+ msgid "Intrinsic %qs (is %s) is used at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4443
++#: fortran/intrinsic.c:4444
+ #, gcc-internal-format
+ msgid "Function %qs as initialization expression at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4519
++#: fortran/intrinsic.c:4520
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Elemental function as initialization expression with non-integer/non-"
+@@ -51915,43 +52034,43 @@
+ "character arguments at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4590
++#: fortran/intrinsic.c:4591
+ #, gcc-internal-format
+ msgid ""
+ "Subroutine call to intrinsic %qs in DO CONCURRENT block at %L is not PURE"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4597
++#: fortran/intrinsic.c:4598
+ #, gcc-internal-format
+ msgid "Subroutine call to intrinsic %qs at %L is not PURE"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4673
++#: fortran/intrinsic.c:4674
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Extension: Conversion from %s to %s at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4709 fortran/intrinsic.c:4726
++#: fortran/intrinsic.c:4710 fortran/intrinsic.c:4727
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Possible change of value in conversion from %s to %s at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4714 fortran/intrinsic.c:4735
++#: fortran/intrinsic.c:4715 fortran/intrinsic.c:4736
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Conversion from %s to %s at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4788
++#: fortran/intrinsic.c:4789
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Can't convert %s to %s at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4793
++#: fortran/intrinsic.c:4794
+ #, gcc-internal-format
+ msgid "Can't convert %qs to %qs at %L"
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4883
++#: fortran/intrinsic.c:4884
+ #, gcc-internal-format
+ msgid ""
+ "%qs declared at %L may shadow the intrinsic of the same name.  In order to "
+@@ -51958,7 +52077,7 @@
+ "call the intrinsic, explicit INTRINSIC declarations may be required."
+ msgstr ""
+ 
+-#: fortran/intrinsic.c:4889
++#: fortran/intrinsic.c:4890
+ #, gcc-internal-format
+ msgid ""
+ "%qs declared at %L is also the name of an intrinsic.  It can only be called "
+@@ -51970,358 +52089,358 @@
+ msgid "Extension: backslash character at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:203 fortran/io.c:206
++#: fortran/io.c:201
+ #, gcc-internal-format, gfc-internal-format
+-msgid "Extension: Tab character in format at %C"
++msgid "Nonconforming tab character in format at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:454
++#: fortran/io.c:444
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DP format specifier not allowed at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:461
++#: fortran/io.c:451
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DC format specifier not allowed at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:650
++#: fortran/io.c:637
+ #, gcc-internal-format, gfc-internal-format
+ msgid "X descriptor requires leading space count at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:679
++#: fortran/io.c:666
+ #, gcc-internal-format, gfc-internal-format
+ msgid "$ descriptor at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:683
++#: fortran/io.c:670
+ #, gcc-internal-format, gfc-internal-format
+ msgid "$ should be the last specifier in format at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:781
++#: fortran/io.c:768
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Extension: Missing positive width after L descriptor at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:825
++#: fortran/io.c:812
+ #, gcc-internal-format
+ msgid "%<G0%> in format at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:853
++#: fortran/io.c:840
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Positive width required in format specifier %s at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:869 fortran/io.c:876
++#: fortran/io.c:856 fortran/io.c:863
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Period required in format specifier %s at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:948
++#: fortran/io.c:935
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Period required in format specifier at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:970
++#: fortran/io.c:957
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The H format specifier at %L is a Fortran 95 deleted feature"
+ msgstr ""
+ 
+-#: fortran/io.c:1058 fortran/io.c:1120
++#: fortran/io.c:1045 fortran/io.c:1107
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing comma at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1138
++#: fortran/io.c:1125
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s in format string at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1176
++#: fortran/io.c:1163
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Extraneous characters in format at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1198
++#: fortran/io.c:1185
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Format statement in module main block at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1207
++#: fortran/io.c:1194
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORMAT statement at %C cannot appear within an INTERFACE"
+ msgstr ""
+ 
+-#: fortran/io.c:1213
++#: fortran/io.c:1200
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing format label at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1261
++#: fortran/io.c:1248
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IOMSG must be a scalar-default-char-variable at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1275
++#: fortran/io.c:1262
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s requires a scalar-default-char-expr at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1298 fortran/io.c:1329 fortran/io.c:1395
++#: fortran/io.c:1285 fortran/io.c:1316 fortran/io.c:1382
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid value for %s specification at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1304 fortran/io.c:1335
++#: fortran/io.c:1291 fortran/io.c:1322
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate %s specification at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1342
++#: fortran/io.c:1329
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Variable %s cannot be INTENT(IN) at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1350
++#: fortran/io.c:1337
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Variable %s cannot be assigned in PURE procedure at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1401
++#: fortran/io.c:1388
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate %s label specification at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1421
++#: fortran/io.c:1408
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Constant expression in FORMAT tag at %L must be of type default CHARACTER"
+ msgstr ""
+ 
+-#: fortran/io.c:1439
++#: fortran/io.c:1426
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORMAT tag at %L must be of type default-kind CHARACTER or of INTEGER"
+ msgstr ""
+ 
+-#: fortran/io.c:1445
++#: fortran/io.c:1432
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASSIGNED variable in FORMAT tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1450
++#: fortran/io.c:1437
+ #, gcc-internal-format
+ msgid "Variable %qs at %L has not been assigned a format label"
+ msgstr ""
+ 
+-#: fortran/io.c:1457
++#: fortran/io.c:1444
+ #, gcc-internal-format
+ msgid "Scalar %qs in FORMAT tag at %L is not an ASSIGNED variable"
+ msgstr ""
+ 
+-#: fortran/io.c:1469
++#: fortran/io.c:1456
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-character in FORMAT tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1475
++#: fortran/io.c:1462
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-character assumed shape array element in FORMAT tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1482
++#: fortran/io.c:1469
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-character assumed size array element in FORMAT tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1489
++#: fortran/io.c:1476
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-character pointer array element in FORMAT tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1515
++#: fortran/io.c:1502
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s tag at %L must be of type %s"
+ msgstr ""
+ 
+-#: fortran/io.c:1522
++#: fortran/io.c:1509
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s tag at %L must be a character string of default kind"
+ msgstr ""
+ 
+-#: fortran/io.c:1529
++#: fortran/io.c:1516
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s tag at %L must be scalar"
+ msgstr ""
+ 
+-#: fortran/io.c:1535
++#: fortran/io.c:1522
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IOMSG tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1543
++#: fortran/io.c:1530
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Fortran 95 requires default INTEGER in %s tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1552
++#: fortran/io.c:1539
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-default LOGICAL kind in %s tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1559
++#: fortran/io.c:1546
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NEWUNIT specifier at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1577
++#: fortran/io.c:1564
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CONVERT tag at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:1766
++#: fortran/io.c:1753
+ #, gcc-internal-format
+ msgid "Fortran 2003: %s specifier in %s statement at %C has value %qs"
+ msgstr ""
+ 
+-#: fortran/io.c:1774 fortran/io.c:1801
++#: fortran/io.c:1761 fortran/io.c:1788
+ #, gcc-internal-format
+ msgid "%s specifier in %s statement at %C has value %qs"
+ msgstr ""
+ 
+-#: fortran/io.c:1793
++#: fortran/io.c:1780
+ #, gcc-internal-format
+ msgid "Extension: %s specifier in %s statement at %C has value %qs"
+ msgstr ""
+ 
+-#: fortran/io.c:1815 fortran/io.c:1823
++#: fortran/io.c:1802 fortran/io.c:1810
+ #, gcc-internal-format
+ msgid "%s specifier in %s statement at %C has invalid value %qs"
+ msgstr ""
+ 
+-#: fortran/io.c:1876
++#: fortran/io.c:1863
+ #, gcc-internal-format, gfc-internal-format
+ msgid "OPEN statement not allowed in PURE procedure at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1889
++#: fortran/io.c:1876
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNIT specifier not allowed with NEWUNIT at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1899
++#: fortran/io.c:1886
+ #, gcc-internal-format, gfc-internal-format
+ msgid "NEWUNIT specifier must have FILE= or STATUS='scratch' at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:1907
++#: fortran/io.c:1894
+ #, gcc-internal-format, gfc-internal-format
+ msgid "OPEN statement at %C must have UNIT or NEWUNIT specified"
+ msgstr ""
+ 
+-#: fortran/io.c:1945
++#: fortran/io.c:1932
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASYNCHRONOUS= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:1966 fortran/io.c:3461
++#: fortran/io.c:1953 fortran/io.c:3448
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BLANK= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:1987 fortran/io.c:3437
++#: fortran/io.c:1974 fortran/io.c:3424
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DECIMAL= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:2025
++#: fortran/io.c:2012
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENCODING= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:2088 fortran/io.c:3510
++#: fortran/io.c:2075 fortran/io.c:3497
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ROUND= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:2111
++#: fortran/io.c:2098
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SIGN= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:2332
++#: fortran/io.c:2319
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CLOSE statement not allowed in PURE procedure at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:2394
++#: fortran/io.c:2381
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CLOSE statement at %L requires a UNIT number"
+ msgstr ""
+ 
+-#: fortran/io.c:2402
++#: fortran/io.c:2389
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNIT number in CLOSE statement at %L must be non-negative"
+ msgstr ""
+ 
+-#: fortran/io.c:2500 fortran/match.c:2761
++#: fortran/io.c:2487 fortran/match.c:2833
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement not allowed in PURE procedure at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:2534
++#: fortran/io.c:2521
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNIT number missing in statement at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:2542 fortran/io.c:2979
++#: fortran/io.c:2529 fortran/io.c:2966
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNIT number in statement at %L must be non-negative"
+ msgstr ""
+ 
+-#: fortran/io.c:2575
++#: fortran/io.c:2562
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FLUSH statement at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:2630
++#: fortran/io.c:2617
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate UNIT specification at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:2704
++#: fortran/io.c:2691
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate format specification at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:2721
++#: fortran/io.c:2708
+ #, gcc-internal-format
+ msgid "Symbol %qs in namelist %qs is INTENT(IN) at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:2757
++#: fortran/io.c:2744
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate NML specification at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:2766
++#: fortran/io.c:2753
+ #, gcc-internal-format
+ msgid "Symbol %qs at %C must be a NAMELIST group name"
+ msgstr ""
+ 
+-#: fortran/io.c:2836
++#: fortran/io.c:2823
+ #, gcc-internal-format, gfc-internal-format
+ msgid "END tag at %C not allowed in output statement"
+ msgstr ""
+ 
+-#: fortran/io.c:2913
++#: fortran/io.c:2900
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNIT not specified at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:2925
++#: fortran/io.c:2912
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "UNIT specification at %L must be an INTEGER expression or a CHARACTER "
+@@ -52328,22 +52447,22 @@
+ "variable"
+ msgstr ""
+ 
+-#: fortran/io.c:2947
++#: fortran/io.c:2934
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid form of WRITE statement at %L, UNIT required"
+ msgstr ""
+ 
+-#: fortran/io.c:2958
++#: fortran/io.c:2945
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Internal unit with vector subscript at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:2972
++#: fortran/io.c:2959
+ #, gcc-internal-format, gfc-internal-format
+ msgid "External IO UNIT cannot be an array at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:3000
++#: fortran/io.c:2987
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST %qs in READ statement at %L contains the symbol %qs which may not "
+@@ -52350,129 +52469,129 @@
+ "appear in a variable definition context"
+ msgstr ""
+ 
+-#: fortran/io.c:3010
++#: fortran/io.c:2997
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Comma before i/o item list at %L"
+ msgstr ""
+ 
+-#: fortran/io.c:3020
++#: fortran/io.c:3007
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ERR tag label %d at %L not defined"
+ msgstr ""
+ 
+-#: fortran/io.c:3032
++#: fortran/io.c:3019
+ #, gcc-internal-format, gfc-internal-format
+ msgid "END tag label %d at %L not defined"
+ msgstr ""
+ 
+-#: fortran/io.c:3044
++#: fortran/io.c:3031
+ #, gcc-internal-format, gfc-internal-format
+ msgid "EOR tag label %d at %L not defined"
+ msgstr ""
+ 
+-#: fortran/io.c:3054
++#: fortran/io.c:3041
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORMAT label %d at %L not defined"
+ msgstr ""
+ 
+-#: fortran/io.c:3085
++#: fortran/io.c:3072
+ #, gcc-internal-format
+ msgid "io_kind_name(): bad I/O-kind"
+ msgstr ""
+ 
+-#: fortran/io.c:3174
++#: fortran/io.c:3161
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in I/O iterator at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:3205
++#: fortran/io.c:3192
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected variable in READ statement at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:3211
++#: fortran/io.c:3198
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected expression in %s statement at %C"
+ msgstr ""
+ 
+ #. A general purpose syntax error.
+-#: fortran/io.c:3268 fortran/io.c:3886 fortran/gfortran.h:2731
++#: fortran/io.c:3255 fortran/io.c:3873 fortran/gfortran.h:2731
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in %s statement at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:3352
++#: fortran/io.c:3339
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Internal file at %L with namelist"
+ msgstr ""
+ 
+-#: fortran/io.c:3408
++#: fortran/io.c:3395
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASYNCHRONOUS= specifier at %L must be an initialization expression"
+ msgstr ""
+ 
+-#: fortran/io.c:3486
++#: fortran/io.c:3473
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PAD= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:3562
++#: fortran/io.c:3549
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DELIM= at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:3714
++#: fortran/io.c:3701
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PRINT namelist at %C is an extension"
+ msgstr ""
+ 
+-#: fortran/io.c:3857
++#: fortran/io.c:3844
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected comma in I/O list at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:3920
++#: fortran/io.c:3907
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PRINT statement at %C not allowed within PURE procedure"
+ msgstr ""
+ 
+-#: fortran/io.c:4083 fortran/io.c:4143
++#: fortran/io.c:4070 fortran/io.c:4130
+ #, gcc-internal-format, gfc-internal-format
+ msgid "INQUIRE statement not allowed in PURE procedure at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:4111
++#: fortran/io.c:4098
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IOLENGTH tag invalid in INQUIRE statement at %C"
+ msgstr ""
+ 
+-#: fortran/io.c:4121 fortran/trans-io.c:1303
++#: fortran/io.c:4108 fortran/trans-io.c:1303
+ #, gcc-internal-format, gfc-internal-format
+ msgid "INQUIRE statement at %L cannot contain both FILE and UNIT specifiers"
+ msgstr ""
+ 
+-#: fortran/io.c:4128
++#: fortran/io.c:4115
+ #, gcc-internal-format, gfc-internal-format
+ msgid "INQUIRE statement at %L requires either FILE or UNIT specifier"
+ msgstr ""
+ 
+-#: fortran/io.c:4137
++#: fortran/io.c:4124
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNIT number in INQUIRE statement at %L can not be -1"
+ msgstr ""
+ 
+-#: fortran/io.c:4151
++#: fortran/io.c:4138
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "INQUIRE statement at %L requires a PENDING= specifier with the ID= specifier"
+ msgstr ""
+ 
+-#: fortran/io.c:4327
++#: fortran/io.c:4314
+ #, gcc-internal-format, gfc-internal-format
+ msgid "WAIT at %C not allowed in Fortran 95"
+ msgstr ""
+ 
+-#: fortran/io.c:4333
++#: fortran/io.c:4320
+ #, gcc-internal-format, gfc-internal-format
+ msgid "WAIT statement not allowed in PURE procedure at %C"
+ msgstr ""
+@@ -52772,200 +52891,222 @@
+ msgid "CYCLE statement at %C to non-innermost collapsed !$OMP DO loop"
+ msgstr ""
+ 
+-#: fortran/match.c:2755
++#: fortran/match.c:2782
+ #, gcc-internal-format, gfc-internal-format
++msgid "Blank required in %s statement near %C"
++msgstr ""
++
++#: fortran/match.c:2800
++#, gcc-internal-format, gfc-internal-format
++msgid "STOP code at %C cannot be negative"
++msgstr ""
++
++#: fortran/match.c:2806
++#, gcc-internal-format, gfc-internal-format
++msgid "STOP code at %C contains too many digits"
++msgstr ""
++
++#: fortran/match.c:2827
++#, gcc-internal-format, gfc-internal-format
+ msgid "%s statement at %C in PURE procedure"
+ msgstr ""
+ 
+-#: fortran/match.c:2771
++#: fortran/match.c:2843
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement STOP at %C in CRITICAL block"
+ msgstr ""
+ 
+-#: fortran/match.c:2776
++#: fortran/match.c:2848
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement STOP at %C in DO CONCURRENT block"
+ msgstr ""
+ 
+-#: fortran/match.c:2784
++#: fortran/match.c:2859
+ #, gcc-internal-format, gfc-internal-format
++msgid ""
++"STOP code at %L must be a scalar CHARACTER constant or "
++"digit[digit[digit[digit[digit]]]]"
++msgstr ""
++
++#: fortran/match.c:2872
++#, gcc-internal-format, gfc-internal-format
+ msgid "STOP code at %L must be either INTEGER or CHARACTER type"
+ msgstr ""
+ 
+-#: fortran/match.c:2791
++#: fortran/match.c:2879
+ #, gcc-internal-format, gfc-internal-format
+ msgid "STOP code at %L must be scalar"
+ msgstr ""
+ 
+-#: fortran/match.c:2799
++#: fortran/match.c:2886
+ #, gcc-internal-format, gfc-internal-format
+ msgid "STOP code at %L must be default character KIND=%d"
+ msgstr ""
+ 
+-#: fortran/match.c:2807
++#: fortran/match.c:2893
+ #, gcc-internal-format, gfc-internal-format
+ msgid "STOP code at %L must be default integer KIND=%d"
+ msgstr ""
+ 
+-#: fortran/match.c:2853
++#: fortran/match.c:2941
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PAUSE statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:2874
++#: fortran/match.c:2962
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ERROR STOP statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:2900
++#: fortran/match.c:2988
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement EVENT %s at %C in PURE procedure"
+ msgstr ""
+ 
+-#: fortran/match.c:2915
++#: fortran/match.c:3003
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement EVENT %s at %C in CRITICAL block"
+ msgstr ""
+ 
+-#: fortran/match.c:2922
++#: fortran/match.c:3010
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement EVENT %s at %C in DO CONCURRENT block"
+ msgstr ""
+ 
+-#: fortran/match.c:2952 fortran/match.c:3147 fortran/match.c:3359
+-#: fortran/match.c:3869 fortran/match.c:4206
++#: fortran/match.c:3040 fortran/match.c:3235 fortran/match.c:3447
++#: fortran/match.c:3957 fortran/match.c:4294
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redundant STAT tag found at %L "
+ msgstr ""
+ 
+-#: fortran/match.c:2973 fortran/match.c:3168 fortran/match.c:3379
+-#: fortran/match.c:3895 fortran/match.c:4231
++#: fortran/match.c:3061 fortran/match.c:3256 fortran/match.c:3467
++#: fortran/match.c:3983 fortran/match.c:4319
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redundant ERRMSG tag found at %L "
+ msgstr ""
+ 
+-#: fortran/match.c:2994
++#: fortran/match.c:3082
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redundant UNTIL_COUNT tag found at %L "
+ msgstr ""
+ 
+-#: fortran/match.c:3060
++#: fortran/match.c:3148
+ #, gcc-internal-format, gfc-internal-format
+ msgid "EVENT POST statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3070
++#: fortran/match.c:3158
+ #, gcc-internal-format, gfc-internal-format
+ msgid "EVENT WAIT statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3095
++#: fortran/match.c:3183
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement %s at %C in PURE procedure"
+ msgstr ""
+ 
+-#: fortran/match.c:3110
++#: fortran/match.c:3198
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement %s at %C in CRITICAL block"
+ msgstr ""
+ 
+-#: fortran/match.c:3117
++#: fortran/match.c:3205
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement %s at %C in DO CONCURRENT block"
+ msgstr ""
+ 
+-#: fortran/match.c:3189
++#: fortran/match.c:3277
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redundant ACQUIRED_LOCK tag found at %L "
+ msgstr ""
+ 
+-#: fortran/match.c:3254
++#: fortran/match.c:3342
+ #, gcc-internal-format, gfc-internal-format
+ msgid "LOCK statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3264
++#: fortran/match.c:3352
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNLOCK statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3289
++#: fortran/match.c:3377
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement SYNC at %C in PURE procedure"
+ msgstr ""
+ 
+-#: fortran/match.c:3295
++#: fortran/match.c:3383
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SYNC statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3307
++#: fortran/match.c:3395
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement SYNC at %C in CRITICAL block"
+ msgstr ""
+ 
+-#: fortran/match.c:3313
++#: fortran/match.c:3401
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement SYNC at %C in DO CONCURRENT block"
+ msgstr ""
+ 
+-#: fortran/match.c:3493
++#: fortran/match.c:3581
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASSIGN statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3537
++#: fortran/match.c:3625
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assigned GOTO statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3581 fortran/match.c:3632
++#: fortran/match.c:3669 fortran/match.c:3720
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Statement label list in GOTO at %C cannot be empty"
+ msgstr ""
+ 
+-#: fortran/match.c:3642
++#: fortran/match.c:3730
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Computed GOTO at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3714
++#: fortran/match.c:3802
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Error in type-spec at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3724
++#: fortran/match.c:3812
+ #, gcc-internal-format, gfc-internal-format
+ msgid "typespec in ALLOCATE at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3767
++#: fortran/match.c:3855
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Bad allocate-object at %C for a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/match.c:3791
++#: fortran/match.c:3879
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ALLOCATE of coarray at %C in DO CONCURRENT block"
+ msgstr ""
+ 
+-#: fortran/match.c:3796
++#: fortran/match.c:3884
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ALLOCATE of coarray at %C in CRITICAL block"
+ msgstr ""
+ 
+-#: fortran/match.c:3818
++#: fortran/match.c:3906
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocate-object at %L is neither a data pointer nor an allocatable variable"
+ msgstr ""
+ 
+-#: fortran/match.c:3830
++#: fortran/match.c:3918
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Type of entity at %L is type incompatible with typespec"
+ msgstr ""
+ 
+-#: fortran/match.c:3838
++#: fortran/match.c:3926
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Kind type parameter for entity at %L differs from the kind type parameter of "
+@@ -52972,57 +53113,57 @@
+ "the typespec"
+ msgstr ""
+ 
+-#: fortran/match.c:3852
++#: fortran/match.c:3940
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Shape specification for allocatable scalar at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:3889
++#: fortran/match.c:3977
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ERRMSG tag at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3912
++#: fortran/match.c:4000
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SOURCE tag at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3918
++#: fortran/match.c:4006
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redundant SOURCE tag found at %L "
+ msgstr ""
+ 
+-#: fortran/match.c:3925
++#: fortran/match.c:4013
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SOURCE tag at %L conflicts with the typespec at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3931
++#: fortran/match.c:4019
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SOURCE tag at %L with more than a single allocate object"
+ msgstr ""
+ 
+-#: fortran/match.c:3949
++#: fortran/match.c:4037
+ #, gcc-internal-format, gfc-internal-format
+ msgid "MOLD tag at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3955
++#: fortran/match.c:4043
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redundant MOLD tag found at %L "
+ msgstr ""
+ 
+-#: fortran/match.c:3962
++#: fortran/match.c:4050
+ #, gcc-internal-format, gfc-internal-format
+ msgid "MOLD tag at %L conflicts with the typespec at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3988
++#: fortran/match.c:4076
+ #, gcc-internal-format, gfc-internal-format
+ msgid "MOLD tag at %L conflicts with SOURCE tag at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:3996
++#: fortran/match.c:4084
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocate-object at %L with a deferred type parameter requires either a type-"
+@@ -53029,7 +53170,7 @@
+ "spec or SOURCE tag or a MOLD tag"
+ msgstr ""
+ 
+-#: fortran/match.c:4008
++#: fortran/match.c:4096
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Unlimited polymorphic allocate-object at %L requires either a type-spec or "
+@@ -53036,27 +53177,27 @@
+ "SOURCE tag or a MOLD tag"
+ msgstr ""
+ 
+-#: fortran/match.c:4070
++#: fortran/match.c:4158
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Pointer object at %C shall not be coindexed"
+ msgstr ""
+ 
+-#: fortran/match.c:4156
++#: fortran/match.c:4244
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Illegal allocate-object at %C for a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/match.c:4166
++#: fortran/match.c:4254
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DEALLOCATE of coarray at %C in DO CONCURRENT block"
+ msgstr ""
+ 
+-#: fortran/match.c:4173
++#: fortran/match.c:4261
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DEALLOCATE of coarray at %C in CRITICAL block"
+ msgstr ""
+ 
+-#: fortran/match.c:4189
++#: fortran/match.c:4277
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocate-object at %C is not a nonprocedure pointer nor an allocatable "
+@@ -53063,47 +53204,47 @@
+ "variable"
+ msgstr ""
+ 
+-#: fortran/match.c:4226
++#: fortran/match.c:4314
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ERRMSG at %L"
+ msgstr ""
+ 
+-#: fortran/match.c:4283
++#: fortran/match.c:4371
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement RETURN at %C in CRITICAL block"
+ msgstr ""
+ 
+-#: fortran/match.c:4289
++#: fortran/match.c:4377
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Image control statement RETURN at %C in DO CONCURRENT block"
+ msgstr ""
+ 
+-#: fortran/match.c:4298
++#: fortran/match.c:4386
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Alternate RETURN statement at %C is only allowed within a SUBROUTINE"
+ msgstr ""
+ 
+-#: fortran/match.c:4329
++#: fortran/match.c:4417
+ #, gcc-internal-format, gfc-internal-format
+ msgid "RETURN statement in main program at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:4357
++#: fortran/match.c:4445
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected component reference at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:4366
++#: fortran/match.c:4454
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Junk after CALL at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:4377
++#: fortran/match.c:4465
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected type-bound procedure or procedure pointer component at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:4598
++#: fortran/match.c:4686
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in common block name at %C"
+ msgstr ""
+@@ -53111,7 +53252,7 @@
+ #. If we find an error, just print it and continue,
+ #. cause it's just semantic, and we can see if there
+ #. are more errors.
+-#: fortran/match.c:4665
++#: fortran/match.c:4753
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L in common block %qs at %C must be declared with a C "
+@@ -53118,7 +53259,7 @@
+ "interoperable kind since common block %qs is bind(c)"
+ msgstr ""
+ 
+-#: fortran/match.c:4674
++#: fortran/match.c:4762
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs in common block %qs at %C can not be bind(c) since it is not "
+@@ -53125,27 +53266,27 @@
+ "global"
+ msgstr ""
+ 
+-#: fortran/match.c:4681
++#: fortran/match.c:4769
+ #, gcc-internal-format
+ msgid "Symbol %qs at %C is already in a COMMON block"
+ msgstr ""
+ 
+-#: fortran/match.c:4689
++#: fortran/match.c:4777
+ #, gcc-internal-format
+ msgid "Initialized symbol %qs at %C can only be COMMON in BLOCK DATA"
+ msgstr ""
+ 
+-#: fortran/match.c:4705
++#: fortran/match.c:4793
+ #, gcc-internal-format
+ msgid "Array specification for symbol %qs in COMMON at %C must be explicit"
+ msgstr ""
+ 
+-#: fortran/match.c:4715
++#: fortran/match.c:4803
+ #, gcc-internal-format
+ msgid "Symbol %qs in COMMON at %C cannot be a POINTER array"
+ msgstr ""
+ 
+-#: fortran/match.c:4761
++#: fortran/match.c:4849
+ #, gcc-internal-format
+ msgid ""
+ "Symbol %qs, in COMMON block %qs at %C is being indirectly equivalenced to "
+@@ -53152,12 +53293,12 @@
+ "another COMMON block %qs"
+ msgstr ""
+ 
+-#: fortran/match.c:4889
++#: fortran/match.c:4977
+ #, gcc-internal-format
+ msgid "Namelist group name %qs at %C already has a basic type of %s"
+ msgstr ""
+ 
+-#: fortran/match.c:4897
++#: fortran/match.c:4985
+ #, gcc-internal-format
+ msgid ""
+ "Namelist group name %qs at %C already is USE associated and cannot be "
+@@ -53164,94 +53305,94 @@
+ "respecified."
+ msgstr ""
+ 
+-#: fortran/match.c:4923
++#: fortran/match.c:5011
+ #, gcc-internal-format
+ msgid "Assumed size array %qs in namelist %qs at %C is not allowed"
+ msgstr ""
+ 
+-#: fortran/match.c:5057
++#: fortran/match.c:5145
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Derived type component %C is not a permitted EQUIVALENCE member"
+ msgstr ""
+ 
+-#: fortran/match.c:5065
++#: fortran/match.c:5153
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Array reference in EQUIVALENCE at %C cannot be an array section"
+ msgstr ""
+ 
+-#: fortran/match.c:5093
++#: fortran/match.c:5181
+ #, gcc-internal-format, gfc-internal-format
+ msgid "EQUIVALENCE at %C requires two or more objects"
+ msgstr ""
+ 
+-#: fortran/match.c:5107
++#: fortran/match.c:5195
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Attempt to indirectly overlap COMMON blocks %s and %s by EQUIVALENCE at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5120
++#: fortran/match.c:5208
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expecting a comma in EQUIVALENCE at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5236
++#: fortran/match.c:5324
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Statement function at %L is recursive"
+ msgstr ""
+ 
+-#: fortran/match.c:5246
++#: fortran/match.c:5334
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Statement function at %L cannot appear within an INTERFACE"
+ msgstr ""
+ 
+-#: fortran/match.c:5251
++#: fortran/match.c:5339
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Statement function at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5376 fortran/match.c:5392
++#: fortran/match.c:5464 fortran/match.c:5480
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expression in CASE selector at %L cannot be %s"
+ msgstr ""
+ 
+-#: fortran/match.c:5414
++#: fortran/match.c:5502
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected initialization expression in CASE at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5446
++#: fortran/match.c:5534
+ #, gcc-internal-format
+ msgid "Expected block name %qs of SELECT construct at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5726
++#: fortran/match.c:5814
+ #, gcc-internal-format, gfc-internal-format
+ msgid "parse error in SELECT TYPE statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5750
++#: fortran/match.c:5838
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Selector in SELECT TYPE at %C is not a named variable; use associate-name=>"
+ msgstr ""
+ 
+-#: fortran/match.c:5784
++#: fortran/match.c:5872
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected CASE statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5836
++#: fortran/match.c:5924
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in CASE specification at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5854
++#: fortran/match.c:5942
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected TYPE IS statement at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5886
++#: fortran/match.c:5974
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The type-spec shall not specify a sequence derived type or a type with the "
+@@ -53258,22 +53399,22 @@
+ "BIND attribute in SELECT TYPE at %C [F2003:C815]"
+ msgstr ""
+ 
+-#: fortran/match.c:5898
++#: fortran/match.c:5986
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in TYPE IS specification at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:5974
++#: fortran/match.c:6062
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in CLASS IS specification at %C"
+ msgstr ""
+ 
+-#: fortran/match.c:6092
++#: fortran/match.c:6185
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ELSEWHERE statement at %C not enclosed in WHERE block"
+ msgstr ""
+ 
+-#: fortran/match.c:6130
++#: fortran/match.c:6223
+ #, gcc-internal-format
+ msgid "Label %qs at %C doesn't match WHERE label %qs"
+ msgstr ""
+@@ -53731,12 +53872,12 @@
+ msgid "Unexpected junk after $OMP FLUSH statement at %C"
+ msgstr ""
+ 
+-#: fortran/openmp.c:2347 fortran/openmp.c:5206
++#: fortran/openmp.c:2347 fortran/openmp.c:5227
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redefinition of predefined %s !$OMP DECLARE REDUCTION at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:2351 fortran/openmp.c:5210
++#: fortran/openmp.c:2351 fortran/openmp.c:5231
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redefinition of predefined !$OMP DECLARE REDUCTION at %L"
+ msgstr ""
+@@ -53944,7 +54085,7 @@
+ "Implicitly declared subroutine %s used in !$OMP DECLARE REDUCTION at %L "
+ msgstr ""
+ 
+-#: fortran/openmp.c:3226 fortran/resolve.c:9401 fortran/resolve.c:10623
++#: fortran/openmp.c:3226 fortran/resolve.c:9423 fortran/resolve.c:10661
+ #, gcc-internal-format, gfc-internal-format
+ msgid "IF clause at %L requires a scalar LOGICAL expression"
+ msgstr ""
+@@ -53976,7 +54117,7 @@
+ 
+ #: fortran/openmp.c:3313 fortran/openmp.c:3324 fortran/openmp.c:3332
+ #: fortran/openmp.c:3343 fortran/openmp.c:3355 fortran/openmp.c:3370
+-#: fortran/openmp.c:5013
++#: fortran/openmp.c:5034
+ #, gcc-internal-format
+ msgid "Symbol %qs present on multiple clauses at %L"
+ msgstr ""
+@@ -54149,13 +54290,18 @@
+ msgid "THREAD_LIMIT clause at %L requires a scalar INTEGER expression"
+ msgstr ""
+ 
+-#: fortran/openmp.c:3932
++#: fortran/openmp.c:3924
+ #, gcc-internal-format, gfc-internal-format
++msgid "unexpected !$OMP ATOMIC expression at %L"
++msgstr ""
++
++#: fortran/openmp.c:3953
++#, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC statement must set a scalar variable of intrinsic type at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:3957
++#: fortran/openmp.c:3978
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC READ statement must read from a scalar variable of intrinsic "
+@@ -54162,7 +54308,7 @@
+ "type at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:3962
++#: fortran/openmp.c:3983
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "expr in !$OMP ATOMIC WRITE assignment var = expr must be scalar and cannot "
+@@ -54169,7 +54315,7 @@
+ "reference var at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:3984 fortran/openmp.c:4275
++#: fortran/openmp.c:4005 fortran/openmp.c:4296
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC CAPTURE capture statement must read from a scalar variable of "
+@@ -54176,7 +54322,7 @@
+ "intrinsic type at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:3999
++#: fortran/openmp.c:4020
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC CAPTURE update statement must set a scalar variable of "
+@@ -54183,7 +54329,7 @@
+ "intrinsic type at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4006 fortran/openmp.c:4282
++#: fortran/openmp.c:4027 fortran/openmp.c:4303
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC CAPTURE capture statement reads from different variable than "
+@@ -54190,12 +54336,12 @@
+ "update statement writes into at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4022
++#: fortran/openmp.c:4043
+ #, gcc-internal-format, gfc-internal-format
+ msgid "!$OMP ATOMIC with ALLOCATABLE variable at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4064
++#: fortran/openmp.c:4085
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC assignment operator must be binary +, *, -, /, .AND., .OR., ."
+@@ -54202,13 +54348,13 @@
+ "EQV. or .NEQV. at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4112
++#: fortran/openmp.c:4133
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC assignment must be var = var op expr or var = expr op var at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4126
++#: fortran/openmp.c:4147
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC var = var op expr not mathematically equivalent to var = var op "
+@@ -54215,7 +54361,7 @@
+ "(expr) at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4158
++#: fortran/openmp.c:4179
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "expr in !$OMP ATOMIC assignment var = var op expr must be scalar and cannot "
+@@ -54222,7 +54368,7 @@
+ "reference var at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4182
++#: fortran/openmp.c:4203
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC assignment intrinsic IAND, IOR or IEOR must have two arguments "
+@@ -54229,29 +54375,29 @@
+ "at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4189
++#: fortran/openmp.c:4210
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC assignment intrinsic must be MIN, MAX, IAND, IOR or IEOR at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4206
++#: fortran/openmp.c:4227
+ #, gcc-internal-format
+ msgid ""
+ "!$OMP ATOMIC intrinsic arguments except one must not reference %qs at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4213
++#: fortran/openmp.c:4234
+ #, gcc-internal-format, gfc-internal-format
+ msgid "!$OMP ATOMIC intrinsic arguments must be scalar at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4221
++#: fortran/openmp.c:4242
+ #, gcc-internal-format
+ msgid "First or last !$OMP ATOMIC intrinsic argument must be %qs at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4239
++#: fortran/openmp.c:4260
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC assignment must have an operator or intrinsic on right hand "
+@@ -54258,7 +54404,7 @@
+ "side at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4253
++#: fortran/openmp.c:4274
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "!$OMP ATOMIC CAPTURE capture statement must set a scalar variable of "
+@@ -54265,27 +54411,27 @@
+ "intrinsic type at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4530
++#: fortran/openmp.c:4551
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s cannot be a DO WHILE or DO without loop control at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4536
++#: fortran/openmp.c:4557
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s cannot be a DO CONCURRENT loop at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4542
++#: fortran/openmp.c:4563
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s iteration variable must be of type integer at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4546
++#: fortran/openmp.c:4567
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s iteration variable must not be THREADPRIVATE at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4559
++#: fortran/openmp.c:4580
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "%s iteration variable present on clause other than PRIVATE or LASTPRIVATE at "
+@@ -54292,67 +54438,67 @@
+ "%L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4563
++#: fortran/openmp.c:4584
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s iteration variable present on clause other than LASTPRIVATE at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4567
++#: fortran/openmp.c:4588
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s iteration variable present on clause other than LINEAR at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4585
++#: fortran/openmp.c:4606
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s collapsed loops don't form rectangular iteration space at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4599
++#: fortran/openmp.c:4620
+ #, gcc-internal-format, gfc-internal-format
+ msgid "collapsed %s loops not perfectly nested at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4608 fortran/openmp.c:4616
++#: fortran/openmp.c:4629 fortran/openmp.c:4637
+ #, gcc-internal-format, gfc-internal-format
+ msgid "not enough DO loops for collapsed %s at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4700 fortran/openmp.c:4713
++#: fortran/openmp.c:4721 fortran/openmp.c:4734
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The %s directive cannot be specified within a %s region at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4732
++#: fortran/openmp.c:4753
+ #, gcc-internal-format, gfc-internal-format
+ msgid "!$ACC LOOP cannot be a DO WHILE or DO without loop control at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4738
++#: fortran/openmp.c:4759
+ #, gcc-internal-format, gfc-internal-format
+ msgid "!$ACC LOOP iteration variable must be of type integer at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4754
++#: fortran/openmp.c:4775
+ #, gcc-internal-format, gfc-internal-format
+ msgid "!$ACC LOOP %s loops don't form rectangular iteration space at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4768
++#: fortran/openmp.c:4789
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s !$ACC LOOP loops not perfectly nested at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4778 fortran/openmp.c:4787
++#: fortran/openmp.c:4799 fortran/openmp.c:4808
+ #, gcc-internal-format, gfc-internal-format
+ msgid "not enough DO loops for %s !$ACC LOOP at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4802 fortran/openmp.c:4809
++#: fortran/openmp.c:4823 fortran/openmp.c:4830
+ #, gcc-internal-format, gfc-internal-format
+ msgid "!$ACC LOOP %s in PARALLEL region doesn't allow %s arguments at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4831
++#: fortran/openmp.c:4852
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Loop parallelized across gangs is not allowed inside another loop "
+@@ -54359,7 +54505,7 @@
+ "parallelized across gangs at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4835 fortran/openmp.c:4839
++#: fortran/openmp.c:4856 fortran/openmp.c:4860
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Loop parallelized across gangs is not allowed inside loop parallelized "
+@@ -54366,7 +54512,7 @@
+ "across workers at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4846
++#: fortran/openmp.c:4867
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Loop parallelized across workers is not allowed inside another loop "
+@@ -54373,7 +54519,7 @@
+ "parallelized across workers at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4850
++#: fortran/openmp.c:4871
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Loop parallelized across workers is not allowed inside another loop "
+@@ -54380,7 +54526,7 @@
+ "parallelized across vectors at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4856
++#: fortran/openmp.c:4877
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Loop parallelized across vectors is not allowed inside another loop "
+@@ -54387,47 +54533,47 @@
+ "parallelized across vectors at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4868
++#: fortran/openmp.c:4889
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause SEQ conflicts with INDEPENDENT at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4870
++#: fortran/openmp.c:4891
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause SEQ conflicts with GANG at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4872
++#: fortran/openmp.c:4893
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause SEQ conflicts with WORKER at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4874
++#: fortran/openmp.c:4895
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause SEQ conflicts with VECTOR at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4876
++#: fortran/openmp.c:4897
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause SEQ conflicts with AUTO at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4881
++#: fortran/openmp.c:4902
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause AUTO conflicts with GANG at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4883
++#: fortran/openmp.c:4904
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause AUTO conflicts with WORKER at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4885
++#: fortran/openmp.c:4906
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Clause AUTO conflicts with VECTOR at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4889
++#: fortran/openmp.c:4910
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Tiled loop cannot be parallelized across gangs, workers and vectors at the "
+@@ -54434,32 +54580,32 @@
+ "same time at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4924
++#: fortran/openmp.c:4945
+ #, gcc-internal-format, gfc-internal-format
+ msgid "TILE requires constant expression at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4989
++#: fortran/openmp.c:5010
+ #, gcc-internal-format
+ msgid "PARAMETER object %qs is not allowed at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:4996
++#: fortran/openmp.c:5017
+ #, gcc-internal-format
+ msgid "Array sections: %qs not allowed in $!ACC DECLARE at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5115
++#: fortran/openmp.c:5136
+ #, gcc-internal-format, gfc-internal-format
+ msgid "OMP TARGET UPDATE at %L requires at least one TO or FROM clause"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5136
++#: fortran/openmp.c:5157
+ #, gcc-internal-format
+ msgid "!$OMP DECLARE SIMD should refer to containing procedure %qs at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5160
++#: fortran/openmp.c:5181
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable other than OMP_PRIV or OMP_ORIG used in INITIALIZER clause of !$OMP "
+@@ -54466,7 +54612,7 @@
+ "DECLARE REDUCTION at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5168
++#: fortran/openmp.c:5189
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable other than OMP_OUT or OMP_IN used in combiner of !$OMP DECLARE "
+@@ -54473,17 +54619,17 @@
+ "REDUCTION at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5197
++#: fortran/openmp.c:5218
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid operator for !$OMP DECLARE REDUCTION %s at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5219
++#: fortran/openmp.c:5240
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CHARACTER length in !$OMP DECLARE REDUCTION %s not constant at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5235
++#: fortran/openmp.c:5256
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Subroutine call with alternate returns in combiner of !$OMP DECLARE "
+@@ -54490,7 +54636,7 @@
+ "REDUCTION at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5250
++#: fortran/openmp.c:5271
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Subroutine call with alternate returns in INITIALIZER clause of !$OMP "
+@@ -54497,7 +54643,7 @@
+ "DECLARE REDUCTION at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5260
++#: fortran/openmp.c:5281
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "One of actual subroutine arguments in INITIALIZER clause of !$OMP DECLARE "
+@@ -54504,7 +54650,7 @@
+ "REDUCTION must be OMP_PRIV at %L"
+ msgstr ""
+ 
+-#: fortran/openmp.c:5268
++#: fortran/openmp.c:5289
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Missing INITIALIZER clause for !$OMP DECLARE REDUCTION of derived type "
+@@ -54644,122 +54790,122 @@
+ msgid "Unclassifiable GCC directive at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:1048 fortran/parse.c:1280
++#: fortran/parse.c:1048 fortran/parse.c:1275
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Zero is not a valid statement label at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:1055 fortran/parse.c:1272
++#: fortran/parse.c:1055 fortran/parse.c:1267
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-numeric character in statement label at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:1067 fortran/parse.c:1321
++#: fortran/parse.c:1067 fortran/parse.c:1316
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Semicolon at %C needs to be preceded by statement"
+ msgstr ""
+ 
+-#: fortran/parse.c:1075 fortran/parse.c:1336
++#: fortran/parse.c:1074 fortran/parse.c:1331
+ #, gcc-internal-format, gfc-internal-format
+-msgid "Ignoring statement label in empty statement at %L"
++msgid "Statement label without statement at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:1142 fortran/parse.c:1323
++#: fortran/parse.c:1137 fortran/parse.c:1318
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Fortran 2008: Semicolon at %C without preceding statement"
+ msgstr ""
+ 
+-#: fortran/parse.c:1165 fortran/parse.c:1299
++#: fortran/parse.c:1160 fortran/parse.c:1294
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Bad continuation line at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:1593
++#: fortran/parse.c:1587
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORMAT statement at %L does not have a statement label"
+ msgstr ""
+ 
+-#: fortran/parse.c:2291
++#: fortran/parse.c:2285
+ #, gcc-internal-format
+ msgid "gfc_ascii_statement(): Bad statement code"
+ msgstr ""
+ 
+-#: fortran/parse.c:2436
++#: fortran/parse.c:2430
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2591
++#: fortran/parse.c:2585
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement at %C cannot follow %s statement at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:2608
++#: fortran/parse.c:2602
+ #, gcc-internal-format
+ msgid "Unexpected end of file in %qs"
+ msgstr ""
+ 
+-#: fortran/parse.c:2640
++#: fortran/parse.c:2634
+ #, gcc-internal-format
+ msgid "Derived-type %qs with SEQUENCE must not have a CONTAINS section at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2643
++#: fortran/parse.c:2637
+ #, gcc-internal-format
+ msgid "Derived-type %qs with BIND(C) must not have a CONTAINS section at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2663
++#: fortran/parse.c:2657
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Components in TYPE at %C must precede CONTAINS"
+ msgstr ""
+ 
+-#: fortran/parse.c:2667
++#: fortran/parse.c:2661
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Type-bound procedure at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2675
++#: fortran/parse.c:2669
+ #, gcc-internal-format, gfc-internal-format
+ msgid "GENERIC binding at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2683
++#: fortran/parse.c:2677
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FINAL procedure declaration at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2695
++#: fortran/parse.c:2689
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Derived type definition at %C with empty CONTAINS section"
+ msgstr ""
+ 
+-#: fortran/parse.c:2705 fortran/parse.c:3160
++#: fortran/parse.c:2699 fortran/parse.c:3154
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PRIVATE statement in TYPE at %C must be inside a MODULE"
+ msgstr ""
+ 
+-#: fortran/parse.c:2712
++#: fortran/parse.c:2706
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PRIVATE statement at %C must precede procedure bindings"
+ msgstr ""
+ 
+-#: fortran/parse.c:2719 fortran/parse.c:3173
++#: fortran/parse.c:2713 fortran/parse.c:3167
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate PRIVATE statement at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2729
++#: fortran/parse.c:2723
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SEQUENCE statement at %C must precede CONTAINS"
+ msgstr ""
+ 
+-#: fortran/parse.c:2733
++#: fortran/parse.c:2727
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Already inside a CONTAINS block at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:2852
++#: fortran/parse.c:2846
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Component %s at %L of type LOCK_TYPE must have a codimension or be a "
+@@ -54767,7 +54913,7 @@
+ "pointer attribute"
+ msgstr ""
+ 
+-#: fortran/parse.c:2858
++#: fortran/parse.c:2852
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Pointer component %s at %L has a noncoarray subcomponent of type LOCK_TYPE, "
+@@ -54774,13 +54920,13 @@
+ "which must have a codimension or be a subcomponent of a coarray"
+ msgstr ""
+ 
+-#: fortran/parse.c:2863
++#: fortran/parse.c:2857
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocatable component %s at %L of type LOCK_TYPE must have a codimension"
+ msgstr ""
+ 
+-#: fortran/parse.c:2867
++#: fortran/parse.c:2861
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocatable component %s at %L must have a codimension as it has a "
+@@ -54787,7 +54933,7 @@
+ "noncoarray subcomponent of type LOCK_TYPE"
+ msgstr ""
+ 
+-#: fortran/parse.c:2872
++#: fortran/parse.c:2866
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Noncoarray component %s at %L of type LOCK_TYPE or with subcomponent of type "
+@@ -54796,7 +54942,7 @@
+ "subcomponent exists)"
+ msgstr ""
+ 
+-#: fortran/parse.c:2879
++#: fortran/parse.c:2873
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Noncoarray component %s at %L of type LOCK_TYPE or with subcomponent of type "
+@@ -54805,7 +54951,7 @@
+ "codimension or a coarray subcomponent)"
+ msgstr ""
+ 
+-#: fortran/parse.c:2889
++#: fortran/parse.c:2883
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Component %s at %L of type EVENT_TYPE must have a codimension or be a "
+@@ -54813,7 +54959,7 @@
+ "pointer attribute"
+ msgstr ""
+ 
+-#: fortran/parse.c:2895
++#: fortran/parse.c:2889
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Pointer component %s at %L has a noncoarray subcomponent of type EVENT_TYPE, "
+@@ -54820,13 +54966,13 @@
+ "which must have a codimension or be a subcomponent of a coarray"
+ msgstr ""
+ 
+-#: fortran/parse.c:2900
++#: fortran/parse.c:2894
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocatable component %s at %L of type EVENT_TYPE must have a codimension"
+ msgstr ""
+ 
+-#: fortran/parse.c:2904
++#: fortran/parse.c:2898
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocatable component %s at %L must have a codimension as it has a "
+@@ -54833,7 +54979,7 @@
+ "noncoarray subcomponent of type EVENT_TYPE"
+ msgstr ""
+ 
+-#: fortran/parse.c:2909
++#: fortran/parse.c:2903
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Noncoarray component %s at %L of type EVENT_TYPE or with subcomponent of "
+@@ -54842,7 +54988,7 @@
+ "subcomponent exists)"
+ msgstr ""
+ 
+-#: fortran/parse.c:2916
++#: fortran/parse.c:2910
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Noncoarray component %s at %L of type EVENT_TYPE or with subcomponent of "
+@@ -54851,144 +54997,144 @@
+ "codimension or a coarray subcomponent)"
+ msgstr ""
+ 
+-#: fortran/parse.c:2968
++#: fortran/parse.c:2962
+ #, gcc-internal-format, gfc-internal-format
+ msgid "failed to create map component '%s'"
+ msgstr ""
+ 
+-#: fortran/parse.c:3001
++#: fortran/parse.c:2995
+ #, gcc-internal-format, gfc-internal-format
+ msgid "failed to create union component '%s'"
+ msgstr ""
+ 
+-#: fortran/parse.c:3056
++#: fortran/parse.c:3050
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in nested structure declaration at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3143
++#: fortran/parse.c:3137
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FINAL declaration at %C must be inside CONTAINS"
+ msgstr ""
+ 
+-#: fortran/parse.c:3151
++#: fortran/parse.c:3145
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Derived type definition at %C without components"
+ msgstr ""
+ 
+-#: fortran/parse.c:3167
++#: fortran/parse.c:3161
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PRIVATE statement at %C must precede structure components"
+ msgstr ""
+ 
+-#: fortran/parse.c:3184
++#: fortran/parse.c:3178
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SEQUENCE statement at %C must precede structure components"
+ msgstr ""
+ 
+-#: fortran/parse.c:3190
++#: fortran/parse.c:3184
+ #, gcc-internal-format, gfc-internal-format
+ msgid "SEQUENCE attribute at %C already specified in TYPE statement"
+ msgstr ""
+ 
+-#: fortran/parse.c:3195
++#: fortran/parse.c:3189
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate SEQUENCE statement at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3205
++#: fortran/parse.c:3199
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CONTAINS block in derived type definition at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3263
++#: fortran/parse.c:3257
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ENUM declaration at %C has no ENUMERATORS"
+ msgstr ""
+ 
+-#: fortran/parse.c:3350
++#: fortran/parse.c:3344
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement in INTERFACE block at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3374
++#: fortran/parse.c:3368
+ #, gcc-internal-format
+ msgid ""
+ "Name %qs of ABSTRACT INTERFACE at %C cannot be the same as an intrinsic type"
+ msgstr ""
+ 
+-#: fortran/parse.c:3408
++#: fortran/parse.c:3402
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement at %C in INTERFACE body"
+ msgstr ""
+ 
+-#: fortran/parse.c:3426
++#: fortran/parse.c:3420
+ #, gcc-internal-format
+ msgid ""
+ "INTERFACE procedure %qs at %L has the same name as the enclosing procedure"
+ msgstr ""
+ 
+-#: fortran/parse.c:3556
++#: fortran/parse.c:3550
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement is not allowed inside of BLOCK at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3586
++#: fortran/parse.c:3581
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement is not allowed inside of BLOCK DATA at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3676
++#: fortran/parse.c:3671
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement must appear in a MODULE"
+ msgstr ""
+ 
+-#: fortran/parse.c:3684
++#: fortran/parse.c:3679
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement at %C follows another accessibility specification"
+ msgstr ""
+ 
+-#: fortran/parse.c:3736
++#: fortran/parse.c:3731
+ #, gcc-internal-format
+ msgid "Bad kind expression for function %qs at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:3740
++#: fortran/parse.c:3735
+ #, gcc-internal-format
+ msgid "The type for function %qs at %L is not accessible"
+ msgstr ""
+ 
+-#: fortran/parse.c:3800
++#: fortran/parse.c:3795
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ELSEWHERE statement at %C follows previous unmasked ELSEWHERE"
+ msgstr ""
+ 
+-#: fortran/parse.c:3822
++#: fortran/parse.c:3817
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement in WHERE block at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3881
++#: fortran/parse.c:3876
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement in FORALL block at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:3932
++#: fortran/parse.c:3927
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ELSE IF statement at %C cannot follow ELSE statement at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:3950
++#: fortran/parse.c:3945
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Duplicate ELSE statements at %L and %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4011
++#: fortran/parse.c:4006
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected a CASE or END SELECT statement following SELECT CASE at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4094
++#: fortran/parse.c:4089
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Expected TYPE IS, CLASS IS or END SELECT statement following SELECT TYPE at "
+@@ -54995,137 +55141,137 @@
+ "%C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4156
++#: fortran/parse.c:4151
+ #, gcc-internal-format
+ msgid "Variable %qs at %C cannot be redefined inside loop beginning at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:4189
++#: fortran/parse.c:4184
+ #, gcc-internal-format, gfc-internal-format
+ msgid "End of nonblock DO statement at %C is within another block"
+ msgstr ""
+ 
+-#: fortran/parse.c:4199
++#: fortran/parse.c:4194
+ #, gcc-internal-format, gfc-internal-format
+ msgid "End of nonblock DO statement at %C is interwoven with another DO loop"
+ msgstr ""
+ 
+-#: fortran/parse.c:4225
++#: fortran/parse.c:4220
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CRITICAL block inside of OpenACC region at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4252
++#: fortran/parse.c:4247
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Statement label in END CRITICAL at %C does not match CRITICAL label"
+ msgstr ""
+ 
+-#: fortran/parse.c:4321
++#: fortran/parse.c:4316
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BLOCK construct at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4355
++#: fortran/parse.c:4350
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASSOCIATE construct at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4536
++#: fortran/parse.c:4531
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Statement label in ENDDO at %C doesn't match DO label"
+ msgstr ""
+ 
+-#: fortran/parse.c:4552
++#: fortran/parse.c:4547
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Named block DO at %L requires matching ENDDO name"
+ msgstr ""
+ 
+-#: fortran/parse.c:4733
++#: fortran/parse.c:4729
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing !$OMP END ATOMIC after !$OMP ATOMIC CAPTURE at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4749 fortran/parse.c:4808
++#: fortran/parse.c:4745 fortran/parse.c:4804
+ #, gcc-internal-format, gfc-internal-format
+ msgid "OpenACC directive inside of CRITICAL block at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4783
++#: fortran/parse.c:4779
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expecting %s at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4827
++#: fortran/parse.c:4823
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected DO loop at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:4847
++#: fortran/parse.c:4843
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Redundant !$ACC END LOOP at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:5060
++#: fortran/parse.c:5056
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Name after !$omp critical and !$omp end critical does not match at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:5117
++#: fortran/parse.c:5113
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s statement at %C cannot terminate a non-block DO loop"
+ msgstr ""
+ 
+-#: fortran/parse.c:5131
++#: fortran/parse.c:5127
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DATA statement at %C after the first executable statement"
+ msgstr ""
+ 
+-#: fortran/parse.c:5362
++#: fortran/parse.c:5358
+ #, gcc-internal-format
+ msgid "Contained procedure %qs at %C is already ambiguous"
+ msgstr ""
+ 
+-#: fortran/parse.c:5419
++#: fortran/parse.c:5415
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement in CONTAINS section at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:5444
++#: fortran/parse.c:5440
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CONTAINS statement without FUNCTION or SUBROUTINE statement at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:5556
++#: fortran/parse.c:5552
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CONTAINS statement at %C is already in a contained program unit"
+ msgstr ""
+ 
+-#: fortran/parse.c:5602
++#: fortran/parse.c:5598
+ #, gcc-internal-format
+ msgid "gfc_global_used(): Bad type"
+ msgstr ""
+ 
+-#: fortran/parse.c:5607
++#: fortran/parse.c:5603
+ #, gcc-internal-format
+ msgid "Global binding name %qs at %L is already being used as a %s at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:5610
++#: fortran/parse.c:5606
+ #, gcc-internal-format
+ msgid "Global name %qs at %L is already being used as a %s at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:5631
++#: fortran/parse.c:5627
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Blank BLOCK DATA at %C conflicts with prior BLOCK DATA at %L"
+ msgstr ""
+ 
+-#: fortran/parse.c:5657
++#: fortran/parse.c:5653
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement in BLOCK DATA at %C"
+ msgstr ""
+ 
+-#: fortran/parse.c:5742
++#: fortran/parse.c:5738
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unexpected %s statement in MODULE at %C"
+ msgstr ""
+@@ -55133,7 +55279,7 @@
+ #. If we see a duplicate main program, shut down.  If the second
+ #. instance is an implied main program, i.e. data decls or executable
+ #. statements, we're in for lots of errors.
+-#: fortran/parse.c:6129
++#: fortran/parse.c:6125
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Two main PROGRAMs at %L and %C"
+ msgstr ""
+@@ -55325,47 +55471,47 @@
+ msgid "Error converting PARAMETER constant in complex constant at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:1430
++#: fortran/primary.c:1434
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in COMPLEX constant at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:1557
++#: fortran/primary.c:1561
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Namelist '%s' can not be an argument at %L"
+ msgstr ""
+ 
+-#: fortran/primary.c:1643
++#: fortran/primary.c:1647
+ #, gcc-internal-format
+ msgid "Keyword %qs at %C has already appeared in the current argument list"
+ msgstr ""
+ 
+-#: fortran/primary.c:1707
++#: fortran/primary.c:1711
+ #, gcc-internal-format, gfc-internal-format
+ msgid "argument list function at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:1775
++#: fortran/primary.c:1779
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected alternate return label at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:1797
++#: fortran/primary.c:1801
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Missing keyword name in actual argument list at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:1843
++#: fortran/primary.c:1847
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in argument list at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:1864
++#: fortran/primary.c:1868
+ #, gcc-internal-format
+ msgid "extend_ref(): Bad tail"
+ msgstr ""
+ 
+-#: fortran/primary.c:1903
++#: fortran/primary.c:1907
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Array section designator, e.g. '(:)', is required besides the coarray "
+@@ -55372,57 +55518,57 @@
+ "designator '[...]' at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:1911
++#: fortran/primary.c:1915
+ #, gcc-internal-format
+ msgid "Coarray designator at %C but %qs is not a coarray"
+ msgstr ""
+ 
+-#: fortran/primary.c:1988
++#: fortran/primary.c:1992
+ #, gcc-internal-format
+ msgid "Symbol %qs at %C has no IMPLICIT type"
+ msgstr ""
+ 
+-#: fortran/primary.c:1994
++#: fortran/primary.c:1998
+ #, gcc-internal-format
+ msgid "Unexpected %<%c%> for nonderived-type variable %qs at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2012
++#: fortran/primary.c:2016
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected structure component name at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2063
++#: fortran/primary.c:2067
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected argument list at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2103
++#: fortran/primary.c:2107
+ #, gcc-internal-format
+ msgid "Procedure pointer component %qs requires an argument list at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2191
++#: fortran/primary.c:2195
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Coindexed procedure-pointer component at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2226
++#: fortran/primary.c:2230
+ #, gcc-internal-format
+ msgid "gfc_variable_attr(): Expression isn't a variable"
+ msgstr ""
+ 
+-#: fortran/primary.c:2281
++#: fortran/primary.c:2285
+ #, gcc-internal-format
+ msgid "gfc_variable_attr(): Bad array reference"
+ msgstr ""
+ 
+-#: fortran/primary.c:2451
++#: fortran/primary.c:2455
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Structure constructor with missing optional arguments at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2460
++#: fortran/primary.c:2464
+ #, gcc-internal-format
+ msgid ""
+ "No initializer for allocatable component '%qs' given in the structure "
+@@ -55429,50 +55575,50 @@
+ "constructor at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2467
++#: fortran/primary.c:2471
+ #, gcc-internal-format
+ msgid ""
+ "No initializer for component %qs given in the structure constructor at %C!"
+ msgstr ""
+ 
+-#: fortran/primary.c:2515
++#: fortran/primary.c:2519
+ #, gcc-internal-format
+ msgid "Can't construct ABSTRACT type %qs at %L"
+ msgstr ""
+ 
+-#: fortran/primary.c:2535
++#: fortran/primary.c:2539
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Structure constructor with named arguments at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:2550
++#: fortran/primary.c:2554
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Component initializer without name after component named %s at %L!"
+ msgstr ""
+ 
+-#: fortran/primary.c:2555
++#: fortran/primary.c:2559
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Too many components in structure constructor at %L!"
+ msgstr ""
+ 
+-#: fortran/primary.c:2592
++#: fortran/primary.c:2596
+ #, gcc-internal-format
+ msgid "Component %qs is initialized twice in the structure constructor at %L!"
+ msgstr ""
+ 
+-#: fortran/primary.c:2604
++#: fortran/primary.c:2608
+ #, gcc-internal-format
+ msgid ""
+ "Coindexed expression to pointer component %qs in structure constructor at %L!"
+ msgstr ""
+ 
+-#: fortran/primary.c:2658
++#: fortran/primary.c:2662
+ #, gcc-internal-format
+ msgid ""
+ "component %qs at %L has already been set by a parent derived type constructor"
+ msgstr ""
+ 
+-#: fortran/primary.c:2861
++#: fortran/primary.c:2865
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %C is the name of a recursive function and so refers to the result "
+@@ -55479,47 +55625,47 @@
+ "variable. Use an explicit RESULT variable for direct recursion (12.5.2.1)"
+ msgstr ""
+ 
+-#: fortran/primary.c:2985
++#: fortran/primary.c:2989
+ #, gcc-internal-format
+ msgid "Unexpected use of subroutine name %qs at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:3017
++#: fortran/primary.c:3021
+ #, gcc-internal-format
+ msgid "Statement function %qs requires argument list at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:3020
++#: fortran/primary.c:3024
+ #, gcc-internal-format
+ msgid "Function %qs requires an argument list at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:3070
++#: fortran/primary.c:3074
+ #, gcc-internal-format
+ msgid "Missing argument to %qs at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:3228
++#: fortran/primary.c:3232
+ #, gcc-internal-format
+ msgid "Missing argument list in function %qs at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:3272
++#: fortran/primary.c:3276
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Symbol at %C is not appropriate for an expression"
+ msgstr ""
+ 
+-#: fortran/primary.c:3342
++#: fortran/primary.c:3346
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Derived type '%s' cannot be used as a variable at %C"
+ msgstr ""
+ 
+-#: fortran/primary.c:3383
++#: fortran/primary.c:3387
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Named constant at %C in an EQUIVALENCE"
+ msgstr ""
+ 
+-#: fortran/primary.c:3417
++#: fortran/primary.c:3421
+ #, gcc-internal-format
+ msgid "%qs at %C is not a variable"
+ msgstr ""
+@@ -55905,7 +56051,7 @@
+ "Declare it RECURSIVE or use %<-frecursive%>"
+ msgstr ""
+ 
+-#: fortran/resolve.c:1782 fortran/resolve.c:8938 fortran/resolve.c:10563
++#: fortran/resolve.c:1782 fortran/resolve.c:8955 fortran/resolve.c:10601
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Label %d referenced at %L is never defined"
+ msgstr ""
+@@ -56022,7 +56168,7 @@
+ msgid "Unable to resolve the specific function %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:2746 fortran/resolve.c:15387
++#: fortran/resolve.c:2746 fortran/resolve.c:15458
+ #, gcc-internal-format
+ msgid "Function %qs at %L has no IMPLICIT type"
+ msgstr ""
+@@ -56400,7 +56546,7 @@
+ msgid "Assumed-rank variable %s at %L shall not have a subobject reference"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5153
++#: fortran/resolve.c:5158
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs, used in a specification expression, is referenced at %L before "
+@@ -56407,7 +56553,7 @@
+ "the ENTRY statement in which it is a parameter"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5158
++#: fortran/resolve.c:5163
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs is used at %L before the ENTRY statement in which it is a "
+@@ -56414,22 +56560,22 @@
+ "parameter"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5228
++#: fortran/resolve.c:5233
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Polymorphic subobject of coindexed object at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5241
++#: fortran/resolve.c:5246
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Coindexed object with polymorphic allocatable subcomponent at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5579
++#: fortran/resolve.c:5584
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Passed-object at %L must be scalar"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5586
++#: fortran/resolve.c:5591
+ #, gcc-internal-format
+ msgid ""
+ "Base object for procedure-pointer component call at %L is of ABSTRACT type "
+@@ -56436,104 +56582,104 @@
+ "%qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5621
++#: fortran/resolve.c:5626
+ #, gcc-internal-format
+ msgid "Base object for type-bound procedure call at %L is of ABSTRACT type %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5630
++#: fortran/resolve.c:5635
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Base object for NOPASS type-bound procedure call at %L must be scalar"
+ msgstr ""
+ 
+ #. Nothing matching found!
+-#: fortran/resolve.c:5818
++#: fortran/resolve.c:5823
+ #, gcc-internal-format
+ msgid ""
+ "Found no matching specific binding for the call to the GENERIC %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5845
++#: fortran/resolve.c:5850
+ #, gcc-internal-format
+ msgid "%qs at %L should be a SUBROUTINE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:5896
++#: fortran/resolve.c:5901
+ #, gcc-internal-format
+ msgid "%qs at %L should be a FUNCTION"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6413
++#: fortran/resolve.c:6418
+ #, gcc-internal-format
+ msgid "gfc_resolve_expr(): Bad expression type"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6439
++#: fortran/resolve.c:6444
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s at %L must be a scalar"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6449
++#: fortran/resolve.c:6454
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s at %L must be integer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6453 fortran/resolve.c:6460
++#: fortran/resolve.c:6458 fortran/resolve.c:6465
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s at %L must be INTEGER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6502
++#: fortran/resolve.c:6507
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Step expression in DO loop at %L cannot be zero"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6538
++#: fortran/resolve.c:6543
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DO loop at %L will be executed zero times"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6599
++#: fortran/resolve.c:6604
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORALL index-name at %L must be a scalar INTEGER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6604
++#: fortran/resolve.c:6609
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORALL start expression at %L must be a scalar INTEGER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6611
++#: fortran/resolve.c:6616
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORALL end expression at %L must be a scalar INTEGER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6619
++#: fortran/resolve.c:6624
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORALL stride expression at %L must be a scalar %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6624
++#: fortran/resolve.c:6629
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORALL stride expression at %L cannot be zero"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6637
++#: fortran/resolve.c:6642
+ #, gcc-internal-format
+ msgid "FORALL index %qs may not appear in triplet specification at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6735 fortran/resolve.c:7027
++#: fortran/resolve.c:6740 fortran/resolve.c:7032
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Allocate-object at %L must be ALLOCATABLE or a POINTER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6743 fortran/resolve.c:6992
++#: fortran/resolve.c:6748 fortran/resolve.c:6997
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Coindexed allocatable object at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6849
++#: fortran/resolve.c:6854
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Source-expr at %L must be scalar or have the same rank as the allocate-"
+@@ -56540,17 +56686,17 @@
+ "object at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:6880
++#: fortran/resolve.c:6885
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Source-expr at %L and allocate-object at %L must have the same shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7038
++#: fortran/resolve.c:7043
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Type of entity at %L is type incompatible with source-expr at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7050
++#: fortran/resolve.c:7055
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The allocate-object at %L and the source-expr at %L shall have the same kind "
+@@ -56557,7 +56703,7 @@
+ "type parameter"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7064
++#: fortran/resolve.c:7069
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The source-expr at %L shall neither be of type LOCK_TYPE nor have a "
+@@ -56564,7 +56710,7 @@
+ "LOCK_TYPE component if allocate-object at %L is a coarray"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7079
++#: fortran/resolve.c:7084
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The source-expr at %L shall neither be of type EVENT_TYPE nor have a "
+@@ -56571,13 +56717,13 @@
+ "EVENT_TYPE component if allocate-object at %L is a coarray"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7092
++#: fortran/resolve.c:7097
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocating %s of ABSTRACT base type at %L requires a type-spec or source-expr"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7105
++#: fortran/resolve.c:7110
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Allocating %s at %L with type-spec requires the same character-length "
+@@ -56584,12 +56730,12 @@
+ "parameter as in the declaration"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7223 fortran/resolve.c:7238
++#: fortran/resolve.c:7228 fortran/resolve.c:7243
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Array specification required in ALLOCATE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7230
++#: fortran/resolve.c:7235
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Array specification or array-valued SOURCE= expression required in ALLOCATE "
+@@ -56596,17 +56742,17 @@
+ "statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7253
++#: fortran/resolve.c:7258
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Coarray specification required in ALLOCATE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7280
++#: fortran/resolve.c:7285
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Bad array specification in ALLOCATE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7299
++#: fortran/resolve.c:7304
+ #, gcc-internal-format
+ msgid ""
+ "%qs must not appear in the array specification at %L in the same ALLOCATE "
+@@ -56613,47 +56759,47 @@
+ "statement where it is itself allocated"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7314
++#: fortran/resolve.c:7319
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expected '*' in coindex specification in ALLOCATE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7325
++#: fortran/resolve.c:7330
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Bad coarray specification in ALLOCATE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7357
++#: fortran/resolve.c:7362
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Stat-variable at %L must be a scalar INTEGER variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7380
++#: fortran/resolve.c:7385
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Stat-variable at %L shall not be %sd within the same %s statement"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7391
++#: fortran/resolve.c:7396
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ERRMSG at %L is useless without a STAT tag"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7402
++#: fortran/resolve.c:7407
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Errmsg-variable at %L must be a scalar CHARACTER variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7425
++#: fortran/resolve.c:7430
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Errmsg-variable at %L shall not be %sd within the same %s statement"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7455
++#: fortran/resolve.c:7460
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Allocate-object at %L also appears at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7461 fortran/resolve.c:7467
++#: fortran/resolve.c:7466 fortran/resolve.c:7472
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Allocate-object at %L is subobject of object at %L"
+ msgstr ""
+@@ -56662,27 +56808,27 @@
+ #. element in the list.  Either way, we must
+ #. issue an error and get the next case from P.
+ #. FIXME: Sort P and Q by line number.
+-#: fortran/resolve.c:7679
++#: fortran/resolve.c:7684
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CASE label at %L overlaps with CASE label at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7730
++#: fortran/resolve.c:7735
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expression in CASE statement at %L must be of type %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7741
++#: fortran/resolve.c:7746
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expression in CASE statement at %L must be of kind %d"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7754
++#: fortran/resolve.c:7759
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expression in CASE statement at %L must be scalar"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7800
++#: fortran/resolve.c:7805
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Selection expression in computed GOTO statement at %L must be a scalar "
+@@ -56689,100 +56835,100 @@
+ "integer expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7819
++#: fortran/resolve.c:7824
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of SELECT statement at %L cannot be %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7829
++#: fortran/resolve.c:7834
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of SELECT statement at %L must be a scalar expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7847 fortran/resolve.c:7855
++#: fortran/resolve.c:7852 fortran/resolve.c:7860
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Expression in CASE statement at %L is not in the range of %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7917 fortran/resolve.c:8356
++#: fortran/resolve.c:7922 fortran/resolve.c:8373
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The DEFAULT CASE at %L cannot be followed by a second DEFAULT CASE at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7943
++#: fortran/resolve.c:7948
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Logical range in CASE statement at %L is not allowed"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7955
++#: fortran/resolve.c:7960
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Constant logical value in CASE statement is repeated at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:7970
++#: fortran/resolve.c:7975
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Range specification at %L can never be matched"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8073
++#: fortran/resolve.c:8078
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Logical SELECT CASE block at %L has more that two cases"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8148
++#: fortran/resolve.c:8153
+ #, gcc-internal-format
+ msgid "Associate-name %qs at %L is used as array"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8159
++#: fortran/resolve.c:8164
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CLASS selector at %L needs a temporary which is not yet implemented"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8275
++#: fortran/resolve.c:8292
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Selector shall be polymorphic in SELECT TYPE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8292 fortran/resolve.c:8304
++#: fortran/resolve.c:8309 fortran/resolve.c:8321
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Selector at %L must not be coindexed"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8320
++#: fortran/resolve.c:8337
+ #, gcc-internal-format
+ msgid "Derived type %qs at %L must be extensible"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8332
++#: fortran/resolve.c:8349
+ #, gcc-internal-format
+ msgid "Derived type %qs at %L must be an extension of %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8335
++#: fortran/resolve.c:8352
+ #, gcc-internal-format
+ msgid "Unexpected intrinsic type %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8344
++#: fortran/resolve.c:8361
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The type-spec at %L shall specify that each length type parameter is assumed"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8536
++#: fortran/resolve.c:8553
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Double CLASS IS block in SELECT TYPE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8625
++#: fortran/resolve.c:8642
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid context for NULL () intrinsic at %L"
+ msgstr ""
+ 
+ #. FIXME: Test for defined input/output.
+-#: fortran/resolve.c:8653
++#: fortran/resolve.c:8670
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Data transfer element at %L cannot be polymorphic unless it is processed by "
+@@ -56789,7 +56935,7 @@
+ "a defined input/output procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8665
++#: fortran/resolve.c:8682
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Data transfer element at %L cannot have POINTER components unless it is "
+@@ -56796,12 +56942,12 @@
+ "processed by a defined input/output procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8674
++#: fortran/resolve.c:8691
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Data transfer element at %L cannot have procedure pointer components"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8681
++#: fortran/resolve.c:8698
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Data transfer element at %L cannot have ALLOCATABLE components unless it is "
+@@ -56808,12 +56954,12 @@
+ "processed by a defined input/output procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8692 fortran/resolve.c:8698
++#: fortran/resolve.c:8709 fortran/resolve.c:8715
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Data transfer element at %L cannot have PRIVATE components"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8712
++#: fortran/resolve.c:8729
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Data transfer element at %L cannot be a full reference to an assumed-size "
+@@ -56820,57 +56966,57 @@
+ "array"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8769
++#: fortran/resolve.c:8786
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Lock variable at %L must be a scalar of type LOCK_TYPE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8779
++#: fortran/resolve.c:8796
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Event variable at %L must be a scalar of type EVENT_TYPE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8783
++#: fortran/resolve.c:8800
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Event variable argument at %L must be a coarray or coindexed"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8786
++#: fortran/resolve.c:8803
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Event variable argument at %L must be a coarray but not coindexed"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8793 fortran/resolve.c:8911
++#: fortran/resolve.c:8810 fortran/resolve.c:8928
+ #, gcc-internal-format, gfc-internal-format
+ msgid "STAT= argument at %L must be a scalar INTEGER variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8805 fortran/resolve.c:8918
++#: fortran/resolve.c:8822 fortran/resolve.c:8935
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ERRMSG= argument at %L must be a scalar CHARACTER variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8817
++#: fortran/resolve.c:8834
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ACQUIRED_LOCK= argument at %L must be a scalar LOGICAL variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8828
++#: fortran/resolve.c:8845
+ #, gcc-internal-format, gfc-internal-format
+ msgid "UNTIL_COUNT= argument at %L must be a scalar INTEGER expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8888
++#: fortran/resolve.c:8905
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Imageset argument at %L must be a scalar or rank-1 INTEGER expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8892 fortran/resolve.c:8902
++#: fortran/resolve.c:8909 fortran/resolve.c:8919
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Imageset argument at %L must between 1 and num_images()"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8945
++#: fortran/resolve.c:8962
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Statement at %L is not a valid branch target statement for the branch "
+@@ -56877,7 +57023,7 @@
+ "statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8955
++#: fortran/resolve.c:8972
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Branch at %L may result in an infinite loop"
+ msgstr ""
+@@ -56884,12 +57030,12 @@
+ 
+ #. Note: A label at END CRITICAL does not leave the CRITICAL
+ #. construct as END CRITICAL is still part of it.
+-#: fortran/resolve.c:8972 fortran/resolve.c:8995
++#: fortran/resolve.c:8989 fortran/resolve.c:9012
+ #, gcc-internal-format, gfc-internal-format
+ msgid "GOTO statement at %L leaves CRITICAL construct for label at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:8976 fortran/resolve.c:9001
++#: fortran/resolve.c:8993 fortran/resolve.c:9018
+ #, gcc-internal-format, gfc-internal-format
+ msgid "GOTO statement at %L leaves DO CONCURRENT construct for label at %L"
+ msgstr ""
+@@ -56897,37 +57043,37 @@
+ #. The label is not in an enclosing block, so illegal.  This was
+ #. allowed in Fortran 66, so we allow it as extension.  No
+ #. further checks are necessary in this case.
+-#: fortran/resolve.c:9016
++#: fortran/resolve.c:9033
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Label at %L is not in the same block as the GOTO statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9088
++#: fortran/resolve.c:9105
+ #, gcc-internal-format, gfc-internal-format
+ msgid "WHERE mask at %L has inconsistent shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9104
++#: fortran/resolve.c:9121
+ #, gcc-internal-format, gfc-internal-format
+ msgid "WHERE assignment target at %L has inconsistent shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9112 fortran/resolve.c:9199
++#: fortran/resolve.c:9129 fortran/resolve.c:9216
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-ELEMENTAL user-defined assignment in WHERE at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9122 fortran/resolve.c:9209
++#: fortran/resolve.c:9139 fortran/resolve.c:9226
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unsupported statement inside WHERE at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9153
++#: fortran/resolve.c:9170
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assignment to a FORALL index variable at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9162
++#: fortran/resolve.c:9179
+ #, gcc-internal-format
+ msgid ""
+ "The FORALL with index %qs is not used on the left side of the assignment at "
+@@ -56934,27 +57080,32 @@
+ "%L and so might cause multiple assignment to this object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9331
++#: fortran/resolve.c:9344
+ #, gcc-internal-format, gfc-internal-format
++msgid "FORALL index-name at %L must be a scalar variable of type integer"
++msgstr ""
++
++#: fortran/resolve.c:9354
++#, gcc-internal-format, gfc-internal-format
+ msgid "An outer FORALL construct already has an index with this name %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9409
++#: fortran/resolve.c:9431
+ #, gcc-internal-format, gfc-internal-format
+ msgid "WHERE/ELSEWHERE clause at %L requires a LOGICAL array"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9487
++#: fortran/resolve.c:9525
+ #, gcc-internal-format
+ msgid "gfc_resolve_blocks(): Bad block type"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9601
++#: fortran/resolve.c:9639
+ #, gcc-internal-format, gfc-internal-format
+ msgid "CHARACTER expression will be truncated in assignment (%d/%d) at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9633
++#: fortran/resolve.c:9671
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Coindexed expression at %L is assigned to a derived type variable with a "
+@@ -56961,7 +57112,7 @@
+ "POINTER component in a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9638
++#: fortran/resolve.c:9676
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The impure variable at %L is assigned to a derived type variable with a "
+@@ -56968,22 +57119,22 @@
+ "POINTER component in a PURE procedure (12.6)"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9648
++#: fortran/resolve.c:9686
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assignment to coindexed variable at %L in a PURE procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9680
++#: fortran/resolve.c:9718
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assignment to polymorphic coarray at %L is not permitted"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9684
++#: fortran/resolve.c:9722
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assignment to an allocatable polymorphic variable at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9689
++#: fortran/resolve.c:9727
+ #, gcc-internal-format
+ msgid ""
+ "Assignment to an allocatable polymorphic variable at %L requires %<-frealloc-"
+@@ -56991,13 +57142,13 @@
+ msgstr ""
+ 
+ #. See PR 43366.
+-#: fortran/resolve.c:9694
++#: fortran/resolve.c:9732
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Assignment to an allocatable polymorphic variable at %L is not yet supported"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9700
++#: fortran/resolve.c:9738
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Nonallocatable variable must not be polymorphic in intrinsic assignment at "
+@@ -57004,7 +57155,7 @@
+ "%L - check that there is a matching specific subroutine for '=' operator"
+ msgstr ""
+ 
+-#: fortran/resolve.c:9711
++#: fortran/resolve.c:9749
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Coindexed variable must not have an allocatable ultimate component in "
+@@ -57011,7 +57162,7 @@
+ "assignment at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10014
++#: fortran/resolve.c:10052
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "TODO: type-bound defined assignment(s) at %L not done because multiple part "
+@@ -57020,12 +57171,12 @@
+ 
+ #. Even if standard does not support this feature, continue to build
+ #. the two statements to avoid upsetting frontend_passes.c.
+-#: fortran/resolve.c:10256
++#: fortran/resolve.c:10294
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Pointer procedure assignment at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10268
++#: fortran/resolve.c:10306
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "The function result on the lhs of the assignment at %L must have the pointer "
+@@ -57032,60 +57183,60 @@
+ "attribute."
+ msgstr ""
+ 
+-#: fortran/resolve.c:10495
++#: fortran/resolve.c:10533
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASSIGNED GOTO statement at %L requires an INTEGER variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10498
++#: fortran/resolve.c:10536
+ #, gcc-internal-format
+ msgid "Variable %qs has not been assigned a target label at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10509
++#: fortran/resolve.c:10547
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Alternate RETURN statement at %L requires a SCALAR-INTEGER return specifier"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10571
++#: fortran/resolve.c:10609
+ #, gcc-internal-format, gfc-internal-format
+ msgid "ASSIGN statement at %L requires a scalar default INTEGER variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10606
++#: fortran/resolve.c:10644
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Invalid NULL at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10610
++#: fortran/resolve.c:10648
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Arithmetic IF statement at %L requires a scalar REAL or INTEGER expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10666
++#: fortran/resolve.c:10704
+ #, gcc-internal-format
+ msgid "gfc_resolve_code(): No expression on DO WHILE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10671
++#: fortran/resolve.c:10709
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Exit condition of DO WHILE loop at %L must be a scalar LOGICAL expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10755
++#: fortran/resolve.c:10793
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FORALL mask clause at %L requires a scalar LOGICAL expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10826
++#: fortran/resolve.c:10864
+ #, gcc-internal-format
+ msgid "gfc_resolve_code(): Bad statement code"
+ msgstr ""
+ 
+-#: fortran/resolve.c:10921
++#: fortran/resolve.c:10959
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s with binding label %s at %L uses the same global identifier as "
+@@ -57094,7 +57245,7 @@
+ 
+ #. This can only happen if the variable is defined in a module - if it
+ #. isn't the same module, reject it.
+-#: fortran/resolve.c:10934
++#: fortran/resolve.c:10972
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s from module %s with binding label %s at %L uses the same global "
+@@ -57104,7 +57255,7 @@
+ #. Print an error if the procedure is defined multiple times; we have to
+ #. exclude references to the same procedure via module association or
+ #. multiple checks for the same procedure.
+-#: fortran/resolve.c:10951
++#: fortran/resolve.c:10989
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Procedure %s with binding label %s at %L uses the same global identifier as "
+@@ -57111,42 +57262,42 @@
+ "entity at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11028
++#: fortran/resolve.c:11066
+ #, gcc-internal-format, gfc-internal-format
+ msgid "String length at %L is too large"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11364
++#: fortran/resolve.c:11402
+ #, gcc-internal-format
+ msgid "Allocatable array %qs at %L must have a deferred shape or assumed rank"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11368
++#: fortran/resolve.c:11406
+ #, gcc-internal-format
+ msgid "Scalar object %qs at %L may not be ALLOCATABLE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11376
++#: fortran/resolve.c:11414
+ #, gcc-internal-format
+ msgid "Array pointer %qs at %L must have a deferred shape or assumed rank"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11386
++#: fortran/resolve.c:11424
+ #, gcc-internal-format
+ msgid "Array %qs at %L cannot have a deferred shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11401
++#: fortran/resolve.c:11439
+ #, gcc-internal-format
+ msgid "Type %qs of CLASS variable %qs at %L is not extensible"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11413
++#: fortran/resolve.c:11451
+ #, gcc-internal-format
+ msgid "CLASS variable %qs at %L must be dummy, allocatable or pointer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11444
++#: fortran/resolve.c:11482
+ #, gcc-internal-format
+ msgid ""
+ "The type %qs cannot be host associated at %L because it is blocked by an "
+@@ -57153,7 +57304,7 @@
+ "incompatible object of the same name declared at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11466
++#: fortran/resolve.c:11504
+ #, gcc-internal-format
+ msgid ""
+ "Implied SAVE for module variable %qs at %L, needed due to the default "
+@@ -57160,21 +57311,21 @@
+ "initialization"
+ msgstr ""
+ 
++#: fortran/resolve.c:11532
++#, gcc-internal-format
++msgid ""
++"Entity %qs at %L has a deferred type parameter and requires either the "
++"POINTER or ALLOCATABLE attribute"
++msgstr ""
++
+ #. The shape of a main program or module array needs to be
+ #. constant.
+-#: fortran/resolve.c:11514
++#: fortran/resolve.c:11573
+ #, gcc-internal-format
+ msgid "The module or main program array %qs at %L must have constant shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11526
+-#, gcc-internal-format
+-msgid ""
+-"Entity %qs at %L has a deferred type parameter and requires either the "
+-"pointer or allocatable attribute"
+-msgstr ""
+-
+-#: fortran/resolve.c:11542
++#: fortran/resolve.c:11592
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Entity with assumed character length at %L must be a dummy argument or a "
+@@ -57181,57 +57332,57 @@
+ "PARAMETER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11563
++#: fortran/resolve.c:11613
+ #, gcc-internal-format
+ msgid "%qs at %L must have constant character length in this context"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11570
++#: fortran/resolve.c:11620
+ #, gcc-internal-format
+ msgid "COMMON variable %qs at %L must have constant character length"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11617
++#: fortran/resolve.c:11667
+ #, gcc-internal-format
+ msgid "Allocatable %qs at %L cannot have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11620
++#: fortran/resolve.c:11670
+ #, gcc-internal-format
+ msgid "External %qs at %L cannot have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11624
++#: fortran/resolve.c:11674
+ #, gcc-internal-format
+ msgid "Dummy %qs at %L cannot have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11627
++#: fortran/resolve.c:11677
+ #, gcc-internal-format
+ msgid "Intrinsic %qs at %L cannot have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11630
++#: fortran/resolve.c:11680
+ #, gcc-internal-format
+ msgid "Function result %qs at %L cannot have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11633
++#: fortran/resolve.c:11683
+ #, gcc-internal-format
+ msgid "Automatic array %qs at %L cannot have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11675
++#: fortran/resolve.c:11725
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11702
++#: fortran/resolve.c:11752
+ #, gcc-internal-format
+ msgid "Character-valued statement function %qs at %L must have constant length"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11724
++#: fortran/resolve.c:11774
+ #, gcc-internal-format
+ msgid ""
+ "%qs is of a PRIVATE type and cannot be a dummy argument of %qs, which is "
+@@ -57238,7 +57389,7 @@
+ "PUBLIC at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11746
++#: fortran/resolve.c:11796
+ #, gcc-internal-format
+ msgid ""
+ "Procedure %qs in PUBLIC interface %qs at %L takes dummy arguments of %qs "
+@@ -57245,88 +57396,88 @@
+ "which is PRIVATE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11764
++#: fortran/resolve.c:11814
+ #, gcc-internal-format
+ msgid "Function %qs at %L cannot have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11773
++#: fortran/resolve.c:11823
+ #, gcc-internal-format
+ msgid "External object %qs at %L may not have an initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11781
++#: fortran/resolve.c:11831
+ #, gcc-internal-format
+ msgid "ELEMENTAL function %qs at %L must have a scalar result"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11791
++#: fortran/resolve.c:11841
+ #, gcc-internal-format
+ msgid ""
+ "Statement function %qs at %L may not have pointer or allocatable attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11810
++#: fortran/resolve.c:11860
+ #, gcc-internal-format
+ msgid "CHARACTER(*) function %qs at %L cannot be array-valued"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11814
++#: fortran/resolve.c:11864
+ #, gcc-internal-format
+ msgid "CHARACTER(*) function %qs at %L cannot be pointer-valued"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11818
++#: fortran/resolve.c:11868
+ #, gcc-internal-format
+ msgid "CHARACTER(*) function %qs at %L cannot be pure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11822
++#: fortran/resolve.c:11872
+ #, gcc-internal-format
+ msgid "CHARACTER(*) function %qs at %L cannot be recursive"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11835
++#: fortran/resolve.c:11885
+ #, gcc-internal-format
+ msgid "CHARACTER(*) function %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11844
++#: fortran/resolve.c:11894
+ #, gcc-internal-format
+ msgid "Procedure pointer %qs at %L shall not be elemental"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11850
++#: fortran/resolve.c:11900
+ #, gcc-internal-format
+ msgid "Dummy procedure %qs at %L shall not be elemental"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11906
++#: fortran/resolve.c:11956
+ #, gcc-internal-format
+ msgid "PROCEDURE attribute conflicts with SAVE attribute in %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11912
++#: fortran/resolve.c:11962
+ #, gcc-internal-format
+ msgid "PROCEDURE attribute conflicts with INTENT attribute in %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11918
++#: fortran/resolve.c:11968
+ #, gcc-internal-format
+ msgid "PROCEDURE attribute conflicts with RESULT attribute in %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11926
++#: fortran/resolve.c:11976
+ #, gcc-internal-format
+ msgid "EXTERNAL attribute conflicts with FUNCTION attribute in %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11932
++#: fortran/resolve.c:11982
+ #, gcc-internal-format
+ msgid "Procedure pointer result %qs at %L is missing the pointer attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11970
++#: fortran/resolve.c:12027
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Mismatch in ELEMENTAL attribute between MODULE PROCEDURE at %L and its "
+@@ -57333,7 +57484,7 @@
+ "interface in %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11978
++#: fortran/resolve.c:12035
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Mismatch in PURE attribute between MODULE PROCEDURE at %L and its interface "
+@@ -57340,7 +57491,7 @@
+ "in %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11986
++#: fortran/resolve.c:12043
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Mismatch in RECURSIVE attribute between MODULE PROCEDURE at %L and its "
+@@ -57347,7 +57498,7 @@
+ "interface in %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:11995
++#: fortran/resolve.c:12052
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "%s between the MODULE PROCEDURE declaration in module %s and the declaration "
+@@ -57354,52 +57505,52 @@
+ "at %L in SUBMODULE %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12080
++#: fortran/resolve.c:12137
+ #, gcc-internal-format
+ msgid "FINAL procedure %qs at %L is not a SUBROUTINE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12089
++#: fortran/resolve.c:12146
+ #, gcc-internal-format, gfc-internal-format
+ msgid "FINAL procedure at %L must have exactly one argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12098
++#: fortran/resolve.c:12155
+ #, gcc-internal-format
+ msgid "Argument of FINAL procedure at %L must be of type %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12106
++#: fortran/resolve.c:12163
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of FINAL procedure at %L must not be a POINTER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12112
++#: fortran/resolve.c:12169
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of FINAL procedure at %L must not be ALLOCATABLE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12118
++#: fortran/resolve.c:12175
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of FINAL procedure at %L must not be OPTIONAL"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12126
++#: fortran/resolve.c:12183
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of FINAL procedure at %L must not be INTENT(OUT)"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12135
++#: fortran/resolve.c:12192
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Non-scalar FINAL procedure at %L should have assumed shape argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12157
++#: fortran/resolve.c:12214
+ #, gcc-internal-format
+ msgid "FINAL procedure %qs declared at %L has the same rank (%d) as %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12194
++#: fortran/resolve.c:12251
+ #, gcc-internal-format
+ msgid ""
+ "Only array FINAL procedures declared for derived type %qs defined at %L, "
+@@ -57406,37 +57557,37 @@
+ "suggest also scalar one"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12234
++#: fortran/resolve.c:12291
+ #, gcc-internal-format
+ msgid "%qs and %qs can't be mixed FUNCTION/SUBROUTINE for GENERIC %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12270
++#: fortran/resolve.c:12327
+ #, gcc-internal-format
+ msgid "%qs and %qs for GENERIC %qs at %L are ambiguous"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12329
++#: fortran/resolve.c:12386
+ #, gcc-internal-format
+ msgid "Undefined specific binding %qs as target of GENERIC %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12341
++#: fortran/resolve.c:12398
+ #, gcc-internal-format
+ msgid "GENERIC %qs at %L must target a specific binding, %qs is GENERIC, too"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12369
++#: fortran/resolve.c:12426
+ #, gcc-internal-format
+ msgid "GENERIC %qs at %L can't overwrite specific binding with the same name"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12425
++#: fortran/resolve.c:12482
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Type-bound operator at %L can't be NOPASS"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12607
++#: fortran/resolve.c:12674
+ #, gcc-internal-format
+ msgid ""
+ "%qs must be a module procedure or an external procedure with an explicit "
+@@ -57443,52 +57594,52 @@
+ "interface at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12649
++#: fortran/resolve.c:12716
+ #, gcc-internal-format
+ msgid "Procedure %qs with PASS(%s) at %L has no argument %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12663
++#: fortran/resolve.c:12730
+ #, gcc-internal-format
+ msgid "Procedure %qs with PASS at %L must have at least one argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12677 fortran/resolve.c:13125
++#: fortran/resolve.c:12744 fortran/resolve.c:13192
+ #, gcc-internal-format
+ msgid "Non-polymorphic passed-object dummy argument of %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12685
++#: fortran/resolve.c:12752
+ #, gcc-internal-format
+ msgid "Argument %qs of %qs with PASS(%s) at %L must be of the derived-type %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12694
++#: fortran/resolve.c:12761
+ #, gcc-internal-format
+ msgid "Passed-object dummy argument of %qs at %L must be scalar"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12700
++#: fortran/resolve.c:12767
+ #, gcc-internal-format
+ msgid "Passed-object dummy argument of %qs at %L must not be ALLOCATABLE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12706
++#: fortran/resolve.c:12773
+ #, gcc-internal-format
+ msgid "Passed-object dummy argument of %qs at %L must not be POINTER"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12735
++#: fortran/resolve.c:12802
+ #, gcc-internal-format
+ msgid "Procedure %qs at %L has the same name as a component of %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12745
++#: fortran/resolve.c:12812
+ #, gcc-internal-format
+ msgid "Procedure %qs at %L has the same name as an inherited component of %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12837
++#: fortran/resolve.c:12904
+ #, gcc-internal-format
+ msgid ""
+ "Derived-type %qs declared at %L must be ABSTRACT because %qs is DEFERRED and "
+@@ -57495,18 +57646,18 @@
+ "not overridden"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12932
++#: fortran/resolve.c:12999
+ #, gcc-internal-format
+ msgid "Coarray component %qs at %L must be allocatable with deferred shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12941
++#: fortran/resolve.c:13008
+ #, gcc-internal-format
+ msgid ""
+ "Component %qs at %L of TYPE(C_PTR) or TYPE(C_FUNPTR) shall not be a coarray"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12951
++#: fortran/resolve.c:13018
+ #, gcc-internal-format
+ msgid ""
+ "Component %qs at %L with coarray component shall be a nonpointer, "
+@@ -57513,18 +57664,18 @@
+ "nonallocatable scalar"
+ msgstr ""
+ 
+-#: fortran/resolve.c:12960
++#: fortran/resolve.c:13027
+ #, gcc-internal-format
+ msgid ""
+ "Component %qs at %L has the CONTIGUOUS attribute but is not an array pointer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13058
++#: fortran/resolve.c:13125
+ #, gcc-internal-format
+ msgid "Procedure pointer component %qs with PASS(%s) at %L has no argument %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13072
++#: fortran/resolve.c:13139
+ #, gcc-internal-format
+ msgid ""
+ "Procedure pointer component %qs with PASS at %L must have at least one "
+@@ -57531,28 +57682,28 @@
+ "argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13088
++#: fortran/resolve.c:13155
+ #, gcc-internal-format
+ msgid "Argument %qs of %qs with PASS(%s) at %L must be of the derived type %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13098
++#: fortran/resolve.c:13165
+ #, gcc-internal-format
+ msgid "Argument %qs of %qs with PASS(%s) at %L must be scalar"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13107
++#: fortran/resolve.c:13174
+ #, gcc-internal-format
+ msgid ""
+ "Argument %qs of %qs with PASS(%s) at %L may not have the POINTER attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13116
++#: fortran/resolve.c:13183
+ #, gcc-internal-format
+ msgid "Argument %qs of %qs with PASS(%s) at %L may not be ALLOCATABLE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13158
++#: fortran/resolve.c:13225
+ #, gcc-internal-format
+ msgid ""
+ "Component %qs of %qs at %L has the same name as an inherited type-bound "
+@@ -57559,7 +57710,7 @@
+ "procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13171
++#: fortran/resolve.c:13238
+ #, gcc-internal-format
+ msgid ""
+ "Character length of component %qs needs to be a constant specification "
+@@ -57566,7 +57717,7 @@
+ "expression at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13182
++#: fortran/resolve.c:13249
+ #, gcc-internal-format
+ msgid ""
+ "Character component %qs of %qs at %L with deferred length must be a POINTER "
+@@ -57573,7 +57724,7 @@
+ "or ALLOCATABLE"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13213
++#: fortran/resolve.c:13280
+ #, gcc-internal-format
+ msgid ""
+ "the component %qs is a PRIVATE type and cannot be a component of %qs, which "
+@@ -57580,12 +57731,12 @@
+ "is PUBLIC at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13221
++#: fortran/resolve.c:13288
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Polymorphic component %s at %L in SEQUENCE or BIND(C) type %s"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13230
++#: fortran/resolve.c:13297
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Component %s of SEQUENCE type declared at %L does not have the SEQUENCE "
+@@ -57592,23 +57743,23 @@
+ "attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13248 fortran/resolve.c:13260
++#: fortran/resolve.c:13315 fortran/resolve.c:13327
+ #, gcc-internal-format
+ msgid ""
+ "The pointer component %qs of %qs at %L is a type that has not been declared"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13272
++#: fortran/resolve.c:13339
+ #, gcc-internal-format
+ msgid "Component %qs with CLASS at %L must be allocatable or pointer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13339
++#: fortran/resolve.c:13406
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Conflicting initializers in union at %L and %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13383
++#: fortran/resolve.c:13450
+ #, gcc-internal-format
+ msgid ""
+ "As extending type %qs at %L has a coarray component, parent type %qs shall "
+@@ -57615,12 +57766,12 @@
+ "also have one"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13396
++#: fortran/resolve.c:13463
+ #, gcc-internal-format
+ msgid "Non-extensible derived-type %qs at %L must not be ABSTRACT"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13450
++#: fortran/resolve.c:13517
+ #, gcc-internal-format
+ msgid ""
+ "Generic name %qs of function %qs at %L being the same name as derived type "
+@@ -57627,28 +57778,28 @@
+ "at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13506
++#: fortran/resolve.c:13573
+ #, gcc-internal-format
+ msgid "Assumed size array %qs in namelist %qs at %L is not allowed"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13512
++#: fortran/resolve.c:13579
+ #, gcc-internal-format
+ msgid "NAMELIST array object %qs with assumed shape in namelist %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13518
++#: fortran/resolve.c:13585
+ #, gcc-internal-format
+ msgid "NAMELIST array object %qs with nonconstant shape in namelist %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13526
++#: fortran/resolve.c:13593
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST object %qs with nonconstant character length in namelist %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13536
++#: fortran/resolve.c:13603
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST object %qs in namelist %qs at %L is polymorphic and requires a "
+@@ -57655,7 +57806,7 @@
+ "defined input/output procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13546
++#: fortran/resolve.c:13613
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST object %qs in namelist %qs at %L with ALLOCATABLE or POINTER "
+@@ -57664,7 +57815,7 @@
+ 
+ #. FIXME: Once UDDTIO is implemented, the following can be
+ #. removed.
+-#: fortran/resolve.c:13554
++#: fortran/resolve.c:13621
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST object %qs in namelist %qs at %L has ALLOCATABLE or POINTER "
+@@ -57671,7 +57822,7 @@
+ "components and thus requires a defined input/output procedure"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13571
++#: fortran/resolve.c:13638
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST object %qs was declared PRIVATE and cannot be member of PUBLIC "
+@@ -57678,7 +57829,7 @@
+ "namelist %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13581
++#: fortran/resolve.c:13648
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST object %qs has use-associated PRIVATE components and cannot be "
+@@ -57685,7 +57836,7 @@
+ "member of namelist %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13592
++#: fortran/resolve.c:13659
+ #, gcc-internal-format
+ msgid ""
+ "NAMELIST object %qs has PRIVATE components and cannot be a member of PUBLIC "
+@@ -57692,38 +57843,38 @@
+ "namelist %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13619
++#: fortran/resolve.c:13686
+ #, gcc-internal-format
+ msgid "PROCEDURE attribute conflicts with NAMELIST attribute in %qs at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13638
++#: fortran/resolve.c:13705
+ #, gcc-internal-format
+ msgid "Parameter array %qs at %L cannot be automatic or of deferred shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13650
++#: fortran/resolve.c:13721
+ #, gcc-internal-format
+ msgid ""
+ "Implicitly typed PARAMETER %qs at %L doesn't match a later IMPLICIT type"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13661
++#: fortran/resolve.c:13732
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Incompatible derived type in PARAMETER at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13753
++#: fortran/resolve.c:13824
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROTECTED attribute conflicts with EXTERNAL attribute at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13756
++#: fortran/resolve.c:13827
+ #, gcc-internal-format, gfc-internal-format
+ msgid "PROCEDURE attribute conflicts with PROTECTED attribute at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13849
++#: fortran/resolve.c:13920
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %L has the CONTIGUOUS attribute but is not an array pointer or an "
+@@ -57730,39 +57881,39 @@
+ "assumed-shape or assumed-rank array"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13867
++#: fortran/resolve.c:13938
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed size array at %L must be a dummy argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13870
++#: fortran/resolve.c:13941
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed shape array at %L must be a dummy argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13878
++#: fortran/resolve.c:13949
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed-rank array at %L must be a dummy argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13885
++#: fortran/resolve.c:13956
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Assumed-rank array at %L may not have the VALUE or CODIMENSION attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13898
++#: fortran/resolve.c:13969
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Symbol at %L is not a DUMMY variable"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13904
++#: fortran/resolve.c:13975
+ #, gcc-internal-format
+ msgid ""
+ "%qs at %L cannot have the VALUE attribute because it is not a dummy argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13914
++#: fortran/resolve.c:13985
+ #, gcc-internal-format
+ msgid ""
+ "Character dummy variable %qs at %L with VALUE attribute must have constant "
+@@ -57769,7 +57920,7 @@
+ "length"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13923
++#: fortran/resolve.c:13994
+ #, gcc-internal-format
+ msgid ""
+ "C interoperable character dummy variable %qs at %L with VALUE attribute must "
+@@ -57776,17 +57927,17 @@
+ "have length one"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13936 fortran/resolve.c:14103
++#: fortran/resolve.c:14007 fortran/resolve.c:14174
+ #, gcc-internal-format
+ msgid "The derived type %qs at %L is of type %qs, which has not been defined"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13950
++#: fortran/resolve.c:14021
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Variable %s at %L with NO_ARG_CHECK attribute shall be a dummy argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13959
++#: fortran/resolve.c:14030
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s at %L with NO_ARG_CHECK attribute shall be of type TYPE(*) or of "
+@@ -57793,7 +57944,7 @@
+ "an numeric intrinsic type"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13968
++#: fortran/resolve.c:14039
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s at %L with NO_ARG_CHECK attribute may not have the ALLOCATABLE, "
+@@ -57800,7 +57951,7 @@
+ "CODIMENSION, POINTER or VALUE attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13976
++#: fortran/resolve.c:14047
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s at %L with NO_ARG_CHECK attribute may not have the INTENT(OUT) "
+@@ -57807,7 +57958,7 @@
+ "attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:13983
++#: fortran/resolve.c:14054
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s at %L with NO_ARG_CHECK attribute shall either be a scalar or an "
+@@ -57814,12 +57965,12 @@
+ "assumed-size array"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14003
++#: fortran/resolve.c:14074
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed type of variable %s at %L is only permitted for dummy variables"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14010
++#: fortran/resolve.c:14081
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Assumed-type variable %s at %L may not have the ALLOCATABLE, CODIMENSION, "
+@@ -57826,17 +57977,17 @@
+ "POINTER or VALUE attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14017
++#: fortran/resolve.c:14088
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed-type variable %s at %L may not have the INTENT(OUT) attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14024
++#: fortran/resolve.c:14095
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Assumed-type variable %s at %L shall not be an explicit-shape array"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14049
++#: fortran/resolve.c:14120
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L cannot be BIND(C) because it is neither a COMMON block "
+@@ -57843,12 +57994,12 @@
+ "nor declared at the module level scope"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14129
++#: fortran/resolve.c:14200
+ #, gcc-internal-format
+ msgid "PUBLIC %s %qs at %L of PRIVATE derived type %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14144
++#: fortran/resolve.c:14215
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s at %L of type LOCK_TYPE or with subcomponent of type LOCK_TYPE "
+@@ -57855,7 +58006,7 @@
+ "must be a coarray"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14157
++#: fortran/resolve.c:14228
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Variable %s at %L of type EVENT_TYPE or with subcomponent of type LOCK_TYPE "
+@@ -57862,7 +58013,7 @@
+ "must be a coarray"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14175
++#: fortran/resolve.c:14246
+ #, gcc-internal-format
+ msgid ""
+ "The INTENT(OUT) dummy argument %qs at %L is ASSUMED SIZE and so cannot have "
+@@ -57869,29 +58020,29 @@
+ "a default initializer"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14187
++#: fortran/resolve.c:14258
+ #, gcc-internal-format
+ msgid "Dummy argument %qs at %L of LOCK_TYPE shall not be INTENT(OUT)"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14196
++#: fortran/resolve.c:14267
+ #, gcc-internal-format
+ msgid "Dummy argument %qs at %L of EVENT_TYPE shall not be INTENT(OUT)"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14208
++#: fortran/resolve.c:14279
+ #, gcc-internal-format
+ msgid ""
+ "Function result %qs at %L shall not be a coarray or have a coarray component"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14217
++#: fortran/resolve.c:14288
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L of TYPE(C_PTR) or TYPE(C_FUNPTR) shall not be a coarray"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14229
++#: fortran/resolve.c:14300
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L with coarray component shall be a nonpointer, "
+@@ -57898,7 +58049,7 @@
+ "nonallocatable scalar, which is not a coarray"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14244
++#: fortran/resolve.c:14315
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L is a coarray and is not ALLOCATABLE, SAVE nor a dummy "
+@@ -57905,18 +58056,18 @@
+ "argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14252
++#: fortran/resolve.c:14323
+ #, gcc-internal-format
+ msgid ""
+ "Coarray variable %qs at %L shall not have codimensions with deferred shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14259
++#: fortran/resolve.c:14330
+ #, gcc-internal-format
+ msgid "Allocatable coarray variable %qs at %L must have deferred shape"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14271
++#: fortran/resolve.c:14342
+ #, gcc-internal-format
+ msgid ""
+ "Variable %qs at %L is INTENT(OUT) and can thus not be an allocatable coarray "
+@@ -57923,12 +58074,12 @@
+ "or have coarray components"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14280
++#: fortran/resolve.c:14351
+ #, gcc-internal-format
+ msgid "Coarray dummy variable %qs at %L not allowed in BIND(C) procedure %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14296
++#: fortran/resolve.c:14367
+ #, gcc-internal-format
+ msgid ""
+ "LOGICAL dummy argument %qs at %L with non-C_Bool kind in BIND(C) procedure "
+@@ -57935,7 +58086,7 @@
+ "%qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14302
++#: fortran/resolve.c:14373
+ #, gcc-internal-format
+ msgid ""
+ "LOGICAL result variable %qs at %L with non-C_Bool kind in BIND(C) procedure "
+@@ -57942,90 +58093,90 @@
+ "%qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14327
++#: fortran/resolve.c:14398
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Namelist '%s' can not be an argument to subroutine or function at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14396
++#: fortran/resolve.c:14467
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Threadprivate at %L isn't SAVEd"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14407
++#: fortran/resolve.c:14478
+ #, gcc-internal-format
+ msgid "!$OMP DECLARE TARGET variable %qs at %L isn't SAVEd"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14499
++#: fortran/resolve.c:14570
+ #, gcc-internal-format
+ msgid "check_data_variable(): Bad expression"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14505
++#: fortran/resolve.c:14576
+ #, gcc-internal-format
+ msgid "BLOCK DATA element %qs at %L must be in COMMON"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14511
++#: fortran/resolve.c:14582
+ #, gcc-internal-format
+ msgid "DATA array %qs at %L must be specified in a previous declaration"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14520
++#: fortran/resolve.c:14591
+ #, gcc-internal-format
+ msgid "DATA element %qs at %L cannot have a coindex"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14534
++#: fortran/resolve.c:14605
+ #, gcc-internal-format
+ msgid "DATA element %qs at %L is a pointer and so must be a full array"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14580
++#: fortran/resolve.c:14651
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Nonconstant array section at %L in DATA statement"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14593
++#: fortran/resolve.c:14664
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DATA statement at %L has more variables than values"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14692
++#: fortran/resolve.c:14763
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "start of implied-do loop at %L could not be simplified to a constant value"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14700
++#: fortran/resolve.c:14771
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "end of implied-do loop at %L could not be simplified to a constant value"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14708
++#: fortran/resolve.c:14779
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "step of implied-do loop at %L could not be simplified to a constant value"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14833
++#: fortran/resolve.c:14904
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DATA statement at %L has more values than variables"
+ msgstr ""
+ 
+-#: fortran/resolve.c:14998
++#: fortran/resolve.c:15069
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Label %d at %L defined but not used"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15003
++#: fortran/resolve.c:15074
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Label %d at %L defined but cannot be used"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15087
++#: fortran/resolve.c:15158
+ #, gcc-internal-format
+ msgid ""
+ "Derived type variable %qs at %L must have SEQUENCE attribute to be an "
+@@ -58032,7 +58183,7 @@
+ "EQUIVALENCE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15096
++#: fortran/resolve.c:15167
+ #, gcc-internal-format
+ msgid ""
+ "Derived type variable %qs at %L cannot have ALLOCATABLE components to be an "
+@@ -58039,7 +58190,7 @@
+ "EQUIVALENCE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15104
++#: fortran/resolve.c:15175
+ #, gcc-internal-format
+ msgid ""
+ "Derived type variable %qs at %L with default initialization cannot be in "
+@@ -58046,7 +58197,7 @@
+ "EQUIVALENCE with a variable in COMMON"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15120
++#: fortran/resolve.c:15191
+ #, gcc-internal-format
+ msgid ""
+ "Derived type variable %qs at %L with pointer component(s) cannot be an "
+@@ -58053,12 +58204,12 @@
+ "EQUIVALENCE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15223
++#: fortran/resolve.c:15294
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in EQUIVALENCE statement at %L"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15238
++#: fortran/resolve.c:15309
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Either all or none of the objects in the EQUIVALENCE set at %L shall have "
+@@ -58065,7 +58216,7 @@
+ "the PROTECTED attribute"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15250
++#: fortran/resolve.c:15321
+ #, gcc-internal-format
+ msgid ""
+ "Common block member %qs at %L cannot be an EQUIVALENCE object in the pure "
+@@ -58072,68 +58223,68 @@
+ "procedure %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15259
++#: fortran/resolve.c:15330
+ #, gcc-internal-format
+ msgid "Named constant %qs at %L cannot be an EQUIVALENCE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15332
++#: fortran/resolve.c:15403
+ #, gcc-internal-format
+ msgid ""
+ "Array %qs at %L with non-constant bounds cannot be an EQUIVALENCE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15343
++#: fortran/resolve.c:15414
+ #, gcc-internal-format
+ msgid "Structure component %qs at %L cannot be an EQUIVALENCE object"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15354
++#: fortran/resolve.c:15425
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Substring at %L has length zero"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15397
++#: fortran/resolve.c:15468
+ #, gcc-internal-format
+ msgid "PUBLIC function %qs at %L of PRIVATE type %qs"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15410
++#: fortran/resolve.c:15481
+ #, gcc-internal-format
+ msgid "ENTRY %qs at %L has no IMPLICIT type"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15427
++#: fortran/resolve.c:15498
+ #, gcc-internal-format
+ msgid "User operator procedure %qs at %L must be a FUNCTION"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15437
++#: fortran/resolve.c:15508
+ #, gcc-internal-format
+ msgid "User operator procedure %qs at %L cannot be assumed character length"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15445
++#: fortran/resolve.c:15516
+ #, gcc-internal-format
+ msgid "User operator procedure %qs at %L must have at least one argument"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15459
++#: fortran/resolve.c:15530
+ #, gcc-internal-format, gfc-internal-format
+ msgid "First argument of operator interface at %L cannot be optional"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15477
++#: fortran/resolve.c:15548
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Second argument of operator interface at %L cannot be optional"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15484
++#: fortran/resolve.c:15555
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Operator interface at %L must have, at most, two arguments"
+ msgstr ""
+ 
+-#: fortran/resolve.c:15562
++#: fortran/resolve.c:15633
+ #, gcc-internal-format
+ msgid "Contained procedure %qs at %L of a PURE procedure must also be PURE"
+ msgstr ""
+@@ -58247,22 +58398,22 @@
+ msgid "Invalid KIND parameter of %s at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:691
++#: fortran/simplify.c:693
+ #, gcc-internal-format
+ msgid "gfc_simplify_abs(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:712
++#: fortran/simplify.c:714
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of %s function at %L is negative"
+ msgstr ""
+ 
+-#: fortran/simplify.c:719
++#: fortran/simplify.c:721
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of %s function at %L outside of range [0,127]"
+ msgstr ""
+ 
+-#: fortran/simplify.c:737
++#: fortran/simplify.c:739
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Argument of %s function at %L is too large for the collating sequence of "
+@@ -58269,57 +58420,57 @@
+ "kind %d"
+ msgstr ""
+ 
+-#: fortran/simplify.c:774
++#: fortran/simplify.c:776
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of ACOS at %L must be between -1 and 1"
+ msgstr ""
+ 
+-#: fortran/simplify.c:788
++#: fortran/simplify.c:790
+ #, gcc-internal-format
+ msgid "in gfc_simplify_acos(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:807
++#: fortran/simplify.c:809
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of ACOSH at %L must not be less than 1"
+ msgstr ""
+ 
+-#: fortran/simplify.c:822
++#: fortran/simplify.c:824
+ #, gcc-internal-format
+ msgid "in gfc_simplify_acosh(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1051
++#: fortran/simplify.c:1053
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of ASIN at %L must be between -1 and 1"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1065
++#: fortran/simplify.c:1067
+ #, gcc-internal-format
+ msgid "in gfc_simplify_asin(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1093
++#: fortran/simplify.c:1095
+ #, gcc-internal-format
+ msgid "in gfc_simplify_asinh(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1121
++#: fortran/simplify.c:1123
+ #, gcc-internal-format
+ msgid "in gfc_simplify_atan(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1142
++#: fortran/simplify.c:1144
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of ATANH at %L must be inside the range -1 to 1"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1156
++#: fortran/simplify.c:1158
+ #, gcc-internal-format
+ msgid "in gfc_simplify_atanh(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1173
++#: fortran/simplify.c:1175
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "If first argument of ATAN2 %L is zero, then the second argument must not be "
+@@ -58326,78 +58477,78 @@
+ "zero"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1265
++#: fortran/simplify.c:1267
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Result of BESSEL_YN is -INF at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1634
++#: fortran/simplify.c:1636
+ #, gcc-internal-format
+ msgid "gfc_simplify_dcmplx(): Bad type (x)"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1653
++#: fortran/simplify.c:1655
+ #, gcc-internal-format
+ msgid "gfc_simplify_dcmplx(): Bad type (y)"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1730
++#: fortran/simplify.c:1732
+ #, gcc-internal-format
+ msgid "in gfc_simplify_cos(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:1963
++#: fortran/simplify.c:1965
+ #, gcc-internal-format
+ msgid "gfc_simplify_dim(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:2271
++#: fortran/simplify.c:2273
+ #, gcc-internal-format
+ msgid "in gfc_simplify_exp(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:2437
++#: fortran/simplify.c:2440
+ #, gcc-internal-format
+ msgid "gfc_simplify_floor(): Bad kind"
+ msgstr ""
+ 
+-#: fortran/simplify.c:2587
++#: fortran/simplify.c:2590
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of IACHAR at %L must be of length one"
+ msgstr ""
+ 
+-#: fortran/simplify.c:2595
++#: fortran/simplify.c:2598
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of IACHAR function at %L outside of range 0..127"
+ msgstr ""
+ 
+-#: fortran/simplify.c:2710
++#: fortran/simplify.c:2713
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Sum of second and third arguments of IBITS exceeds bit size at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:2734
++#: fortran/simplify.c:2737
+ #, gcc-internal-format
+ msgid "IBITS: Bad bit"
+ msgstr ""
+ 
+-#: fortran/simplify.c:2785
++#: fortran/simplify.c:2788
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of ICHAR at %L must be of length one"
+ msgstr ""
+ 
+ #. Left shift, as in SHIFTL.
+-#: fortran/simplify.c:3150 fortran/simplify.c:3158
++#: fortran/simplify.c:3153 fortran/simplify.c:3161
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Second argument of %s is negative at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:3170
++#: fortran/simplify.c:3173
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Magnitude of second argument of %s exceeds bit size at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:3296
++#: fortran/simplify.c:3299
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Magnitude of second argument of ISHFTC exceeds BIT_SIZE of first argument at "
+@@ -58404,49 +58555,49 @@
+ "%L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:3616 fortran/simplify.c:3748
++#: fortran/simplify.c:3619 fortran/simplify.c:3751
+ #, gcc-internal-format, gfc-internal-format
+ msgid "DIM argument at %L is out of bounds"
+ msgstr ""
+ 
+-#: fortran/simplify.c:3931
++#: fortran/simplify.c:3934
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of LOG at %L cannot be less than or equal to zero"
+ msgstr ""
+ 
+-#: fortran/simplify.c:3944
++#: fortran/simplify.c:3947
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Complex argument of LOG at %L cannot be zero"
+ msgstr ""
+ 
+-#: fortran/simplify.c:3955
++#: fortran/simplify.c:3958
+ #, gcc-internal-format
+ msgid "gfc_simplify_log: bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:3972
++#: fortran/simplify.c:3975
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of LOG10 at %L cannot be less than or equal to zero"
+ msgstr ""
+ 
+-#: fortran/simplify.c:4275
++#: fortran/simplify.c:4278
+ #, gcc-internal-format
+ msgid "simplify_min_max(): Bad type in arglist"
+ msgstr ""
+ 
+ #. Result is processor-dependent.
+-#: fortran/simplify.c:4451
++#: fortran/simplify.c:4454
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Second argument MOD at %L is zero"
+ msgstr ""
+ 
+ #. Result is processor-dependent.
+-#: fortran/simplify.c:4462
++#: fortran/simplify.c:4465
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Second argument of MOD at %L is zero"
+ msgstr ""
+ 
+-#: fortran/simplify.c:4473
++#: fortran/simplify.c:4476
+ #, gcc-internal-format
+ msgid "gfc_simplify_mod(): Bad arguments"
+ msgstr ""
+@@ -58454,57 +58605,57 @@
+ #. Result is processor-dependent. This processor just opts
+ #. to not handle it at all.
+ #. Result is processor-dependent.
+-#: fortran/simplify.c:4499 fortran/simplify.c:4511
++#: fortran/simplify.c:4502 fortran/simplify.c:4514
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Second argument of MODULO at %L is zero"
+ msgstr ""
+ 
+-#: fortran/simplify.c:4531
++#: fortran/simplify.c:4534
+ #, gcc-internal-format
+ msgid "gfc_simplify_modulo(): Bad arguments"
+ msgstr ""
+ 
+-#: fortran/simplify.c:4579
++#: fortran/simplify.c:4582
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Result of NEAREST is NaN at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:5055
++#: fortran/simplify.c:5058
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument NCOPIES of REPEAT intrinsic is negative at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:5110
++#: fortran/simplify.c:5113
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument NCOPIES of REPEAT intrinsic is too large at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:5263
++#: fortran/simplify.c:5266
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Reshaped array too large at %C"
+ msgstr ""
+ 
+-#: fortran/simplify.c:5377
++#: fortran/simplify.c:5380
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Result of SCALE overflows its kind at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:5956
++#: fortran/simplify.c:5959
+ #, gcc-internal-format
+ msgid "Bad type in gfc_simplify_sign"
+ msgstr ""
+ 
+-#: fortran/simplify.c:5985
++#: fortran/simplify.c:5988
+ #, gcc-internal-format
+ msgid "in gfc_simplify_sin(): Bad type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:6112 fortran/simplify.c:6357
++#: fortran/simplify.c:6115 fortran/simplify.c:6360
+ #, gcc-internal-format
+ msgid "Failure getting length of a constant array."
+ msgstr ""
+ 
+-#: fortran/simplify.c:6122
++#: fortran/simplify.c:6125
+ #, gcc-internal-format
+ msgid ""
+ "The number of elements (%d) in the array constructor at %L requires an "
+@@ -58512,22 +58663,22 @@
+ "option."
+ msgstr ""
+ 
+-#: fortran/simplify.c:6188
++#: fortran/simplify.c:6191
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Simplification of SPREAD at %L not yet implemented"
+ msgstr ""
+ 
+-#: fortran/simplify.c:6213
++#: fortran/simplify.c:6216
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Argument of SQRT at %L has a negative value"
+ msgstr ""
+ 
+-#: fortran/simplify.c:6229
++#: fortran/simplify.c:6232
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid argument of SQRT at %L"
+ msgstr ""
+ 
+-#: fortran/simplify.c:6524
++#: fortran/simplify.c:6527
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Out of bounds in IMAGE_INDEX at %L for dimension %d, SUB has %ld and COARRAY "
+@@ -58534,7 +58685,7 @@
+ "lower bound is %ld)"
+ msgstr ""
+ 
+-#: fortran/simplify.c:6547
++#: fortran/simplify.c:6550
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Out of bounds in IMAGE_INDEX at %L for dimension %d, SUB has %ld and COARRAY "
+@@ -58541,12 +58692,12 @@
+ "upper bound is %ld)"
+ msgstr ""
+ 
+-#: fortran/simplify.c:6882
++#: fortran/simplify.c:6885
+ #, gcc-internal-format
+ msgid "gfc_convert_constant(): Unexpected type"
+ msgstr ""
+ 
+-#: fortran/simplify.c:6968
++#: fortran/simplify.c:6971
+ #, gcc-internal-format
+ msgid ""
+ "Character %qs in string at %L cannot be converted into character kind %d"
+@@ -58989,13 +59140,18 @@
+ msgid "Invalid expression in gfc_target_interpret_expr."
+ msgstr ""
+ 
+-#: fortran/target-memory.c:681
++#: fortran/target-memory.c:683
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Overlapping unequal initializers in EQUIVALENCE at %L"
+ msgstr ""
+ 
+-#: fortran/target-memory.c:769
++#: fortran/target-memory.c:686
+ #, gcc-internal-format, gfc-internal-format
++msgid "Overlapping unequal initializers in EQUIVALENCE at %C"
++msgstr ""
++
++#: fortran/target-memory.c:774
++#, gcc-internal-format, gfc-internal-format
+ msgid "BOZ constant at %L is too large (%ld vs %ld bits)"
+ msgstr ""
+ 
+@@ -59025,33 +59181,33 @@
+ "%lu bytes)"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:773
++#: fortran/trans-common.c:778
+ #, gcc-internal-format
+ msgid "get_mpz(): Not an integer constant"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:801
++#: fortran/trans-common.c:806
+ #, gcc-internal-format
+ msgid "element_number(): Bad dimension type"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:863
++#: fortran/trans-common.c:876
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Bad array reference at %L"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:871
++#: fortran/trans-common.c:884
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Illegal reference type at %L as EQUIVALENCE object"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:911
++#: fortran/trans-common.c:924
+ #, gcc-internal-format
+ msgid "Inconsistent equivalence rules involving %qs at %L and %qs at %L"
+ msgstr ""
+ 
+ #. Aligning this field would misalign a previous field.
+-#: fortran/trans-common.c:1044
++#: fortran/trans-common.c:1057
+ #, gcc-internal-format
+ msgid ""
+ "The equivalence set for variable %qs declared at %L violates alignment "
+@@ -59058,18 +59214,18 @@
+ "requirements"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:1109
++#: fortran/trans-common.c:1122
+ #, gcc-internal-format
+ msgid "Equivalence for %qs does not match ordering of COMMON %qs at %L"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:1124
++#: fortran/trans-common.c:1137
+ #, gcc-internal-format
+ msgid ""
+ "The equivalence set for %qs cause an invalid extension to COMMON %qs at %L"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:1140
++#: fortran/trans-common.c:1153
+ #, gcc-internal-format
+ msgid ""
+ "Padding of %d bytes required before %qs in COMMON %qs at %L; reorder "
+@@ -59076,7 +59232,7 @@
+ "elements or use -fno-align-commons"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:1146
++#: fortran/trans-common.c:1159
+ #, gcc-internal-format
+ msgid ""
+ "Padding of %d bytes required before %qs in COMMON at %L; reorder elements or "
+@@ -59083,12 +59239,12 @@
+ "use -fno-align-commons"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:1167
++#: fortran/trans-common.c:1180
+ #, gcc-internal-format
+ msgid "COMMON %qs at %L does not exist"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:1176
++#: fortran/trans-common.c:1189
+ #, gcc-internal-format
+ msgid ""
+ "COMMON %qs at %L requires %d bytes of padding; reorder elements or use %<-"
+@@ -59095,7 +59251,7 @@
+ "fno-align-commons%>"
+ msgstr ""
+ 
+-#: fortran/trans-common.c:1181
++#: fortran/trans-common.c:1194
+ #, gcc-internal-format
+ msgid ""
+ "COMMON at %L requires %d bytes of padding; reorder elements or use %<-fno-"
+@@ -59122,7 +59278,7 @@
+ msgid "intrinsic variable which isn't a procedure"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:4044 fortran/trans-decl.c:6244
++#: fortran/trans-decl.c:4044 fortran/trans-decl.c:6254
+ #, gcc-internal-format
+ msgid "Return value of function %qs at %L not set"
+ msgstr ""
+@@ -59154,7 +59310,7 @@
+ "set and does not have a default initializer"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5259 fortran/trans-decl.c:5390
++#: fortran/trans-decl.c:5259 fortran/trans-decl.c:5400
+ #, gcc-internal-format
+ msgid "Unused dummy argument %qs at %L"
+ msgstr ""
+@@ -59164,27 +59320,27 @@
+ msgid "Unused module variable %qs which has been explicitly imported at %L"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5283
++#: fortran/trans-decl.c:5293
+ #, gcc-internal-format
+ msgid "Unused variable %qs declared at %L"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5332
++#: fortran/trans-decl.c:5342
+ #, gcc-internal-format
+ msgid "Unused parameter %qs declared at %L"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5336
++#: fortran/trans-decl.c:5346
+ #, gcc-internal-format
+ msgid "Unused parameter %qs which has been explicitly imported at %L"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5362
++#: fortran/trans-decl.c:5372
+ #, gcc-internal-format
+ msgid "Return value %qs of function %qs declared at %L not set"
+ msgstr ""
+ 
+-#: fortran/trans-decl.c:5971
++#: fortran/trans-decl.c:5981
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Sorry, $!ACC DECLARE at %L is not allowed in BLOCK construct"
+ msgstr ""
+@@ -59194,12 +59350,12 @@
+ msgid "Can't compute the length of the char array at %L."
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:1526
++#: fortran/trans-expr.c:1552
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Code for reallocating the allocatable variable at %L will be added"
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:1833
++#: fortran/trans-expr.c:1859
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Sorry, coindexed access to a pointer or allocatable component of the "
+@@ -59206,7 +59362,7 @@
+ "coindexed coarray at %L is not yet supported"
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:1847
++#: fortran/trans-expr.c:1873
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Sorry, coindexed coarray at %L with allocatable component is not yet "
+@@ -59213,7 +59369,7 @@
+ "supported"
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:1870
++#: fortran/trans-expr.c:1896
+ #, gcc-internal-format, gfc-internal-format
+ msgid ""
+ "Sorry, coindexed access at %L to a scalar component with an array partref is "
+@@ -59220,12 +59376,12 @@
+ "not yet supported"
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:3309
++#: fortran/trans-expr.c:3335
+ #, gcc-internal-format
+ msgid "Unknown intrinsic op"
+ msgstr ""
+ 
+-#: fortran/trans-expr.c:4597
++#: fortran/trans-expr.c:4623
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Unknown argument list function at %L"
+ msgstr ""
+@@ -59241,12 +59397,12 @@
+ msgid "%<dim%> argument of %s intrinsic at %L is not a valid dimension index"
+ msgstr ""
+ 
+-#: fortran/trans-intrinsic.c:9366 fortran/trans-stmt.c:919
++#: fortran/trans-intrinsic.c:9379 fortran/trans-stmt.c:919
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Sorry, the event component of derived type at %L is not yet supported"
+ msgstr ""
+ 
+-#: fortran/trans-intrinsic.c:9373
++#: fortran/trans-intrinsic.c:9386
+ #, gcc-internal-format, gfc-internal-format
+ msgid "The event variable at %L shall not be coindexed "
+ msgstr ""
+@@ -59261,7 +59417,7 @@
+ msgid "Bad IO basetype (%d)"
+ msgstr ""
+ 
+-#: fortran/trans-openmp.c:4348
++#: fortran/trans-openmp.c:4361
+ #, gcc-internal-format
+ msgid "gfc_trans_omp_workshare(): Bad statement code"
+ msgstr ""
+@@ -59381,7 +59537,7 @@
+ msgid "abstract method in non-abstract class"
+ msgstr ""
+ 
+-#: java/class.c:2682
++#: java/class.c:2683
+ #, gcc-internal-format
+ msgid "non-static method %q+D overrides static method"
+ msgstr ""
+@@ -59788,112 +59944,112 @@
+ msgid "previously declared here"
+ msgstr ""
+ 
+-#: lto/lto.c:1817
++#: lto/lto.c:1819
+ #, gcc-internal-format
+ msgid "bytecode stream: garbage at the end of symbols section"
+ msgstr ""
+ 
+-#: lto/lto.c:1844
++#: lto/lto.c:1846
+ #, gcc-internal-format
+ msgid "could not parse hex number"
+ msgstr ""
+ 
+-#: lto/lto.c:1876
++#: lto/lto.c:1878
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unexpected file name %s in linker resolution file. Expected %s"
+ msgstr ""
+ 
+-#: lto/lto.c:1885
++#: lto/lto.c:1887
+ #, gcc-internal-format
+ msgid "could not parse file offset"
+ msgstr ""
+ 
+-#: lto/lto.c:1888
++#: lto/lto.c:1890
+ #, gcc-internal-format
+ msgid "unexpected offset"
+ msgstr ""
+ 
+-#: lto/lto.c:1910
++#: lto/lto.c:1912
+ #, gcc-internal-format
+ msgid "invalid line in the resolution file"
+ msgstr ""
+ 
+-#: lto/lto.c:1921
++#: lto/lto.c:1923
+ #, gcc-internal-format
+ msgid "invalid resolution in the resolution file"
+ msgstr ""
+ 
+-#: lto/lto.c:1927
++#: lto/lto.c:1929
+ #, gcc-internal-format
+ msgid "resolution sub id %wx not in object file"
+ msgstr ""
+ 
+-#: lto/lto.c:2039
++#: lto/lto.c:2041
+ #, gcc-internal-format, gfc-internal-format
+ msgid "cannot read LTO decls from %s"
+ msgstr ""
+ 
+-#: lto/lto.c:2145
++#: lto/lto.c:2147
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Cannot open %s"
+ msgstr ""
+ 
+-#: lto/lto.c:2166
++#: lto/lto.c:2168
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Cannot map %s"
+ msgstr ""
+ 
+-#: lto/lto.c:2177
++#: lto/lto.c:2179
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Cannot read %s"
+ msgstr ""
+ 
+-#: lto/lto.c:2291
++#: lto/lto.c:2293
+ #, gcc-internal-format
+ msgid "lto_obj_file_open() failed"
+ msgstr ""
+ 
+-#: lto/lto.c:2314
++#: lto/lto.c:2316
+ #, gcc-internal-format
+ msgid "waitpid failed"
+ msgstr ""
+ 
+-#: lto/lto.c:2317
++#: lto/lto.c:2319
+ #, gcc-internal-format
+ msgid "streaming subprocess failed"
+ msgstr ""
+ 
+-#: lto/lto.c:2320
++#: lto/lto.c:2322
+ #, gcc-internal-format
+ msgid "streaming subprocess was killed by signal"
+ msgstr ""
+ 
+-#: lto/lto.c:2396
++#: lto/lto.c:2398
+ #, gcc-internal-format
+ msgid "no LTRANS output list filename provided"
+ msgstr ""
+ 
+-#: lto/lto.c:2484
++#: lto/lto.c:2486
+ #, gcc-internal-format
+ msgid "opening LTRANS output list %s: %m"
+ msgstr ""
+ 
+-#: lto/lto.c:2490
++#: lto/lto.c:2492
+ #, gcc-internal-format
+ msgid "writing to LTRANS output list %s: %m"
+ msgstr ""
+ 
+-#: lto/lto.c:2501
++#: lto/lto.c:2503
+ #, gcc-internal-format
+ msgid "closing LTRANS output list %s: %m"
+ msgstr ""
+ 
+-#: lto/lto.c:2753
++#: lto/lto.c:2755
+ #, gcc-internal-format
+ msgid "could not open symbol resolution file: %m"
+ msgstr ""
+ 
+-#: lto/lto.c:2894
++#: lto/lto.c:2896
+ #, gcc-internal-format
+ msgid "errors during merging of translation units"
+ msgstr ""
+Index: gcc/varasm.c
+===================================================================
+--- a/src/gcc/varasm.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/varasm.c	(.../branches/gcc-6-branch)
+@@ -3276,6 +3276,10 @@
+   set_mem_attributes (rtl, exp, 1);
+   set_mem_alias_set (rtl, 0);
+ 
++  /* Putting EXP into the literal pool might have imposed a different
++     alignment which should be visible in the RTX as well.  */
++  set_mem_align (rtl, DECL_ALIGN (decl));
++
+   /* We cannot share RTX'es in pool entries.
+      Mark this piece of RTL as required for unsharing.  */
+   RTX_FLAG (rtl, used) = 1;
+Index: gcc/ira-costs.c
+===================================================================
+--- a/src/gcc/ira-costs.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ira-costs.c	(.../branches/gcc-6-branch)
+@@ -73,7 +73,7 @@
+ static struct costs *total_allocno_costs;
+ 
+ /* It is the current size of struct costs.  */
+-static int struct_costs_size;
++static size_t struct_costs_size;
+ 
+ /* Return pointer to structure containing costs of allocno or pseudo
+    with given NUM in array ARR.  */
+Index: gcc/tree-inline.c
+===================================================================
+--- a/src/gcc/tree-inline.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-inline.c	(.../branches/gcc-6-branch)
+@@ -4719,7 +4719,7 @@
+ 	{
+ 	  tree name = gimple_call_lhs (stmt);
+ 	  tree var = SSA_NAME_VAR (name);
+-	  tree def = ssa_default_def (cfun, var);
++	  tree def = var ? ssa_default_def (cfun, var) : NULL;
+ 
+ 	  if (def)
+ 	    {
+@@ -4730,6 +4730,11 @@
+ 	    }
+ 	  else
+ 	    {
++	      if (!var)
++		{
++		  var = create_tmp_reg_fn (cfun, TREE_TYPE (name), NULL);
++		  SET_SSA_NAME_VAR_OR_IDENTIFIER (name, var);
++		}
+ 	      /* Otherwise make this variable undefined.  */
+ 	      gsi_remove (&stmt_gsi, true);
+ 	      set_ssa_default_def (cfun, var, name);
+Index: gcc/graphite-sese-to-poly.c
+===================================================================
+--- a/src/gcc/graphite-sese-to-poly.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/graphite-sese-to-poly.c	(.../branches/gcc-6-branch)
+@@ -407,7 +407,7 @@
+ 
+     case SSA_NAME:
+       gcc_assert (-1 != parameter_index_in_region_1 (e, s->scop_info)
+-		  || !invariant_in_sese_p_rec (e, s->scop_info->region, NULL));
++		  || defined_in_sese_p (e, s->scop_info->region));
+       res = extract_affine_name (s, e, space);
+       break;
+ 
+@@ -436,11 +436,11 @@
+ /* Returns a linear expression for tree T evaluated in PBB.  */
+ 
+ static isl_pw_aff *
+-create_pw_aff_from_tree (poly_bb_p pbb, tree t)
++create_pw_aff_from_tree (poly_bb_p pbb, loop_p loop, tree t)
+ {
+   scop_p scop = PBB_SCOP (pbb);
+ 
+-  t = scalar_evolution_in_region (scop->scop_info->region, pbb_loop (pbb), t);
++  t = scalar_evolution_in_region (scop->scop_info->region, loop, t);
+ 
+   gcc_assert (!chrec_contains_undetermined (t));
+   gcc_assert (!automatically_generated_chrec_p (t));
+@@ -455,8 +455,9 @@
+ static void
+ add_condition_to_pbb (poly_bb_p pbb, gcond *stmt, enum tree_code code)
+ {
+-  isl_pw_aff *lhs = create_pw_aff_from_tree (pbb, gimple_cond_lhs (stmt));
+-  isl_pw_aff *rhs = create_pw_aff_from_tree (pbb, gimple_cond_rhs (stmt));
++  loop_p loop = gimple_bb (stmt)->loop_father;
++  isl_pw_aff *lhs = create_pw_aff_from_tree (pbb, loop, gimple_cond_lhs (stmt));
++  isl_pw_aff *rhs = create_pw_aff_from_tree (pbb, loop, gimple_cond_rhs (stmt));
+ 
+   isl_set *cond;
+   switch (code)
+Index: gcc/tree-profile.c
+===================================================================
+--- a/src/gcc/tree-profile.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-profile.c	(.../branches/gcc-6-branch)
+@@ -93,8 +93,6 @@
+   if (targetm.have_tls)
+     set_decl_tls_model (ic_void_ptr_var, decl_default_tls_model (ic_void_ptr_var));
+ 
+-  varpool_node::finalize_decl (ic_void_ptr_var);
+-
+   gcov_type_ptr = build_pointer_type (get_gcov_type ());
+ 
+   ic_gcov_type_ptr_var
+@@ -111,8 +109,6 @@
+   DECL_INITIAL (ic_gcov_type_ptr_var) = NULL;
+   if (targetm.have_tls)
+     set_decl_tls_model (ic_gcov_type_ptr_var, decl_default_tls_model (ic_gcov_type_ptr_var));
+-
+-  varpool_node::finalize_decl (ic_gcov_type_ptr_var);
+ }
+ 
+ /* Create the type and function decls for the interface with gcov.  */
+Index: gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config.gcc	(.../branches/gcc-6-branch)
+@@ -946,6 +946,11 @@
+ 	done
+ 	TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
+ 	;;
++aarch64*-*-freebsd*)
++	tm_file="${tm_file} dbxelf.h elfos.h ${fbsd_tm_file}"
++	tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-freebsd.h"
++	tmake_file="${tmake_file} aarch64/t-aarch64 aarch64/t-aarch64-freebsd"
++	;;
+ aarch64*-*-linux*)
+ 	tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h"
+ 	tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-linux.h"
+Index: gcc/config.host
+===================================================================
+--- a/src/gcc/config.host	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config.host	(.../branches/gcc-6-branch)
+@@ -99,7 +99,7 @@
+ esac
+ 
+ case ${host} in
+-  aarch64*-*-linux*)
++  aarch64*-*-freebsd* | aarch64*-*-linux*)
+     case ${target} in
+       aarch64*-*-*)
+ 	host_extra_gcc_objs="driver-aarch64.o"
+Index: gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/Makefile.in	(.../branches/gcc-6-branch)
+@@ -787,6 +787,7 @@
+ CPP_INSTALL_NAME := $(shell echo cpp|sed '$(program_transform_name)')
+ GCOV_INSTALL_NAME := $(shell echo gcov|sed '$(program_transform_name)')
+ GCOV_TOOL_INSTALL_NAME := $(shell echo gcov-tool|sed '$(program_transform_name)')
++GCOV_DUMP_INSTALL_NAME := $(shell echo gcov-dump|sed '$(program_transform_name)')
+ 
+ # Setup the testing framework, if you have one
+ EXPECT = `if [ -f $${rootme}/../expect/expect ] ; then \
+@@ -3408,6 +3409,15 @@
+ 	    gcov-tool$(exeext) $(DESTDIR)$(bindir)/$(GCOV_TOOL_INSTALL_NAME)$(exeext); \
+ 	  fi; \
+ 	fi
++# Install gcov-dump if it was compiled.
++	-if test "$(enable_as_accelerator)" != "yes" ; then \
++	  if [ -f gcov-dump$(exeext) ]; \
++	  then \
++	    rm -f $(DESTDIR)$(bindir)/$(GCOV_DUMP_INSTALL_NAME)$(exeext); \
++	    $(INSTALL_PROGRAM) \
++	    gcov-dump$(exeext) $(DESTDIR)$(bindir)/$(GCOV_DUMP_INSTALL_NAME)$(exeext); \
++	  fi; \
++	fi
+ 
+ # Install the driver program as $(target_noncanonical)-gcc,
+ # $(target_noncanonical)-gcc-$(version), and also as gcc if native.
+Index: gcc/gimple.c
+===================================================================
+--- a/src/gcc/gimple.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/gimple.c	(.../branches/gcc-6-branch)
+@@ -2487,7 +2487,16 @@
+       if (!targs)
+ 	return true;
+       tree arg = gimple_call_arg (stmt, i);
+-      if (!useless_type_conversion_p (TREE_VALUE (targs), TREE_TYPE (arg)))
++      tree type = TREE_VALUE (targs);
++      if (!useless_type_conversion_p (type, TREE_TYPE (arg))
++	  /* char/short integral arguments are promoted to int
++	     by several frontends if targetm.calls.promote_prototypes
++	     is true.  Allow such promotion too.  */
++	  && !(INTEGRAL_TYPE_P (type)
++	       && TYPE_PRECISION (type) < TYPE_PRECISION (integer_type_node)
++	       && targetm.calls.promote_prototypes (TREE_TYPE (fndecl))
++	       && useless_type_conversion_p (integer_type_node,
++					     TREE_TYPE (arg))))
+ 	return false;
+       targs = TREE_CHAIN (targs);
+     }
+Index: gcc/gimple-expr.c
+===================================================================
+--- a/src/gcc/gimple-expr.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/gimple-expr.c	(.../branches/gcc-6-branch)
+@@ -123,7 +123,7 @@
+   /* Fixed point types with the same mode are compatible.  */
+   else if (FIXED_POINT_TYPE_P (inner_type)
+ 	   && FIXED_POINT_TYPE_P (outer_type))
+-    return true;
++    return TYPE_SATURATING (inner_type) == TYPE_SATURATING (outer_type);
+ 
+   /* We need to take special care recursing to pointed-to types.  */
+   else if (POINTER_TYPE_P (inner_type)
+Index: gcc/tree-ssa-reassoc.c
+===================================================================
+--- a/src/gcc/tree-ssa-reassoc.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/tree-ssa-reassoc.c	(.../branches/gcc-6-branch)
+@@ -599,7 +599,18 @@
+   if (is_gimple_assign (stmt)
+       && gimple_assign_rhs_code (stmt) == code
+       && has_single_use (gimple_assign_lhs (stmt)))
+-    return true;
++    {
++      tree rhs1 = gimple_assign_rhs1 (stmt);
++      tree rhs2 = gimple_assign_rhs1 (stmt);
++      if (TREE_CODE (rhs1) == SSA_NAME
++	  && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (rhs1))
++	return false;
++      if (rhs2
++	  && TREE_CODE (rhs2) == SSA_NAME
++	  && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (rhs2))
++	return false;
++      return true;
++    }
+ 
+   return false;
+ }
+@@ -4466,6 +4477,8 @@
+ can_reassociate_p (tree op)
+ {
+   tree type = TREE_TYPE (op);
++  if (TREE_CODE (op) == SSA_NAME && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (op))
++    return false;
+   if ((ANY_INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_WRAPS (type))
+       || NON_SAT_FIXED_POINT_TYPE_P (type)
+       || (flag_associative_math && FLOAT_TYPE_P (type)))
+Index: gcc/config/nvptx/nvptx.c
+===================================================================
+--- a/src/gcc/config/nvptx/nvptx.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/nvptx/nvptx.c	(.../branches/gcc-6-branch)
+@@ -989,11 +989,14 @@
+     init_frame (file, STACK_POINTER_REGNUM,
+ 		UNITS_PER_WORD, crtl->outgoing_args_size);
+ 
+-  /* Declare a local variable for the frame.  */
++  /* Declare a local variable for the frame.  Force its size to be
++     DImode-compatible.  */
+   HOST_WIDE_INT sz = get_frame_size ();
+   if (sz || cfun->machine->has_chain)
+     init_frame (file, FRAME_POINTER_REGNUM,
+-		crtl->stack_alignment_needed / BITS_PER_UNIT, sz);
++		crtl->stack_alignment_needed / BITS_PER_UNIT,
++		(sz + GET_MODE_SIZE (DImode) - 1)
++		& ~(HOST_WIDE_INT)(GET_MODE_SIZE (DImode) - 1));
+ 
+   /* Declare the pseudos we have as ptx registers.  */
+   int maxregs = max_reg_num ();
+@@ -3212,8 +3215,9 @@
+       rtx pred = NULL_RTX;
+       rtx_code_label *label = NULL;
+ 
+-      gcc_assert (!(fs & (GET_MODE_SIZE (DImode) - 1)));
+-      fs /= GET_MODE_SIZE (DImode);
++      /* The frame size might not be DImode compatible, but the frame
++	 array's declaration will be.  So it's ok to round up here.  */
++      fs = (fs + GET_MODE_SIZE (DImode) - 1) / GET_MODE_SIZE (DImode);
+       /* Detect single iteration loop. */
+       if (fs == 1)
+ 	fs = 0;
+Index: gcc/config/sparc/sparc.c
+===================================================================
+--- a/src/gcc/config/sparc/sparc.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/sparc/sparc.c	(.../branches/gcc-6-branch)
+@@ -11970,8 +11970,9 @@
+   if (TARGET_FLAT)
+     return false;
+ 
+-  /* Otherwise, the frame pointer is required if the function isn't leaf.  */
+-  return !(crtl->is_leaf && only_leaf_regs_used ());
++  /* Otherwise, the frame pointer is required if the function isn't leaf, but
++     we cannot use sparc_leaf_function_p since it hasn't been computed yet.  */
++  return !(optimize > 0 && crtl->is_leaf && only_leaf_regs_used ());
+ }
+ 
+ /* The way this is structured, we can't eliminate SFP in favor of SP
+Index: gcc/config/i386/stringop.opt
+===================================================================
+--- a/src/gcc/config/i386/stringop.opt	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/stringop.opt	(.../branches/gcc-6-branch)
+@@ -1,31 +0,0 @@
+-/* Definitions for stringop option handling for IA-32.
+-   Copyright (C) 2013-2016 Free Software Foundation, Inc.
+-
+-This file is part of GCC.
+-
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
+-
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-GNU General Public License for more details.
+-
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the files COPYING3.  If not,
+-see <http://www.gnu.org/licenses/>.  */
+-
+-Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
+-
+-#undef DEF_ENUM
+-#define DEF_ENUM EnumValue
+-
+-#undef DEF_ALG
+-#define DEF_ALG(alg, name) Enum(stringop_alg) String(name) Value(alg)
+-
+-#include "stringop.def"
+-
+-#undef DEF_ENUM
+-#undef DEF_ALG
+Index: gcc/config/i386/i386.md
+===================================================================
+--- a/src/gcc/config/i386/i386.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/i386.md	(.../branches/gcc-6-branch)
+@@ -2938,6 +2938,36 @@
+   operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
+ })
+ 
++(define_insn_and_split "*pushxf_rounded"
++  [(set (mem:XF
++	  (pre_modify:P
++	    (reg:P SP_REG)
++	    (plus:P (reg:P SP_REG) (const_int -16))))
++	(match_operand:XF 0 "nonmemory_no_elim_operand" "f,r,*r,C"))]
++  "TARGET_64BIT"
++  "#"
++  "&& 1"
++  [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16)))
++   (set (match_dup 1) (match_dup 0))]
++{
++  rtx pat = PATTERN (curr_insn);
++  operands[1] = SET_DEST (pat);
++
++  /* Preserve memory attributes. */
++  operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
++}
++  [(set_attr "type" "multi")
++   (set_attr "unit" "i387,*,*,*")
++   (set (attr "mode")
++	(cond [(eq_attr "alternative" "1,2,3")
++		 (const_string "DI")
++	      ]
++	      (const_string "XF")))
++   (set (attr "preferred_for_size")
++     (cond [(eq_attr "alternative" "1")
++              (symbol_ref "false")]
++           (symbol_ref "true")))])
++
+ (define_insn "*pushxf"
+   [(set (match_operand:XF 0 "push_operand" "=<,<,<,<")
+ 	(match_operand:XF 1 "general_no_elim_operand" "f,r,*r,oF"))]
+@@ -3172,9 +3202,9 @@
+ ;; in alternatives 4, 6, 7 and 8.
+ (define_insn "*movxf_internal"
+   [(set (match_operand:XF 0 "nonimmediate_operand"
+-	 "=f,m,f,?r ,!o,?*r ,!o,!o,!o,r  ,o")
++	 "=f,m,f,?r ,!o,?*r ,!o,!o,!o,r  ,o ,o")
+ 	(match_operand:XF 1 "general_operand"
+-	 "fm,f,G,roF,r , *roF,*r,F ,C,roF,rF"))]
++	 "fm,f,G,roF,r ,*roF,*r,F ,C ,roF,rF,rC"))]
+   "!(MEM_P (operands[0]) && MEM_P (operands[1]))
+    && (lra_in_progress || reload_completed
+        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
+@@ -3201,19 +3231,19 @@
+     }
+ }
+   [(set (attr "isa")
+-	(cond [(eq_attr "alternative" "7")
++	(cond [(eq_attr "alternative" "7,10")
+ 		 (const_string "nox64")
+-	       (eq_attr "alternative" "8")
++	       (eq_attr "alternative" "8,11")
+ 		 (const_string "x64")
+ 	      ]
+ 	      (const_string "*")))
+    (set (attr "type")
+-	(cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10")
++	(cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10,11")
+ 		 (const_string "multi")
+ 	      ]
+ 	      (const_string "fmov")))
+    (set (attr "mode")
+-	(cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10")
++	(cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10,11")
+ 		 (if_then_else (match_test "TARGET_64BIT")
+ 		   (const_string "DI")
+ 		   (const_string "SI"))
+@@ -3224,7 +3254,7 @@
+               (symbol_ref "false")]
+            (symbol_ref "true")))
+    (set (attr "enabled")
+-     (cond [(eq_attr "alternative" "9,10")
++     (cond [(eq_attr "alternative" "9,10,11")
+               (if_then_else
+ 		(match_test "TARGET_HARD_XF_REGS")
+ 		(symbol_ref "false")
+Index: gcc/config/i386/avx512pfintrin.h
+===================================================================
+--- a/src/gcc/config/i386/avx512pfintrin.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/avx512pfintrin.h	(.../branches/gcc-6-branch)
+@@ -49,37 +49,33 @@
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_prefetch_i32gather_pd (__m256i index, __mmask8 mask,
+-				   void *addr, int scale, int hint)
++				   void const *addr, int scale, int hint)
+ {
+-  __builtin_ia32_gatherpfdpd (mask, (__v8si) index, (long long const *) addr,
+-			      scale, hint);
++  __builtin_ia32_gatherpfdpd (mask, (__v8si) index, addr, scale, hint);
+ }
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_prefetch_i32gather_ps (__m512i index, __mmask16 mask,
+-				   void *addr, int scale, int hint)
++				   void const *addr, int scale, int hint)
+ {
+-  __builtin_ia32_gatherpfdps (mask, (__v16si) index, (int const *) addr,
+-			      scale, hint);
++  __builtin_ia32_gatherpfdps (mask, (__v16si) index, addr, scale, hint);
+ }
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_prefetch_i64gather_pd (__m512i index, __mmask8 mask,
+-				   void *addr, int scale, int hint)
++				   void const *addr, int scale, int hint)
+ {
+-  __builtin_ia32_gatherpfqpd (mask, (__v8di) index, (long long const *) addr,
+-			      scale, hint);
++  __builtin_ia32_gatherpfqpd (mask, (__v8di) index, addr, scale, hint);
+ }
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_prefetch_i64gather_ps (__m512i index, __mmask8 mask,
+-				   void *addr, int scale, int hint)
++				   void const *addr, int scale, int hint)
+ {
+-  __builtin_ia32_gatherpfqps (mask, (__v8di) index, (int const *) addr,
+-			      scale, hint);
++  __builtin_ia32_gatherpfqps (mask, (__v8di) index, addr, scale, hint);
+ }
+ 
+ extern __inline void
+@@ -87,8 +83,8 @@
+ _mm512_prefetch_i32scatter_pd (void *addr, __m256i index, int scale,
+ 			       int hint)
+ {
+-  __builtin_ia32_scatterpfdpd ((__mmask8) 0xFF, (__v8si) index, 
+-			       (long long const *)addr, scale, hint);
++  __builtin_ia32_scatterpfdpd ((__mmask8) 0xFF, (__v8si) index, addr, scale,
++			       hint);
+ }
+ 
+ extern __inline void
+@@ -96,8 +92,8 @@
+ _mm512_prefetch_i32scatter_ps (void *addr, __m512i index, int scale,
+ 			       int hint)
+ {
+-  __builtin_ia32_scatterpfdps ((__mmask16) 0xFFFF, (__v16si) index, (int const *) addr,
+-			       scale, hint);
++  __builtin_ia32_scatterpfdps ((__mmask16) 0xFFFF, (__v16si) index, addr, scale,
++			       hint);
+ }
+ 
+ extern __inline void
+@@ -105,8 +101,7 @@
+ _mm512_mask_prefetch_i32scatter_pd (void *addr, __mmask8 mask,
+ 				    __m256i index, int scale, int hint)
+ {
+-  __builtin_ia32_scatterpfdpd (mask, (__v8si) index, (long long const *) addr,
+-			       scale, hint);
++  __builtin_ia32_scatterpfdpd (mask, (__v8si) index, addr, scale, hint);
+ }
+ 
+ extern __inline void
+@@ -114,8 +109,7 @@
+ _mm512_mask_prefetch_i32scatter_ps (void *addr, __mmask16 mask,
+ 				    __m512i index, int scale, int hint)
+ {
+-  __builtin_ia32_scatterpfdps (mask, (__v16si) index, (int const *) addr,
+-			       scale, hint);
++  __builtin_ia32_scatterpfdps (mask, (__v16si) index, addr, scale, hint);
+ }
+ 
+ extern __inline void
+@@ -123,8 +117,8 @@
+ _mm512_prefetch_i64scatter_pd (void *addr, __m512i index, int scale,
+ 			       int hint)
+ {
+-  __builtin_ia32_scatterpfqpd ((__mmask8) 0xFF, (__v8di) index, (long long const *) addr,
+-			       scale, hint);
++  __builtin_ia32_scatterpfqpd ((__mmask8) 0xFF, (__v8di) index, addr, scale,
++			       hint);
+ }
+ 
+ extern __inline void
+@@ -132,8 +126,8 @@
+ _mm512_prefetch_i64scatter_ps (void *addr, __m512i index, int scale,
+ 			       int hint)
+ {
+-  __builtin_ia32_scatterpfqps ((__mmask8) 0xFF, (__v8di) index, (int const *) addr,
+-			       scale, hint);
++  __builtin_ia32_scatterpfqps ((__mmask8) 0xFF, (__v8di) index, addr, scale,
++			       hint);
+ }
+ 
+ extern __inline void
+@@ -141,8 +135,7 @@
+ _mm512_mask_prefetch_i64scatter_pd (void *addr, __mmask16 mask,
+ 				    __m512i index, int scale, int hint)
+ {
+-  __builtin_ia32_scatterpfqpd (mask, (__v8di) index, (long long const *) addr,
+-			       scale, hint);
++  __builtin_ia32_scatterpfqpd (mask, (__v8di) index, addr, scale, hint);
+ }
+ 
+ extern __inline void
+@@ -150,58 +143,57 @@
+ _mm512_mask_prefetch_i64scatter_ps (void *addr, __mmask16 mask,
+ 				    __m512i index, int scale, int hint)
+ {
+-  __builtin_ia32_scatterpfqps (mask, (__v8di) index, (int const *) addr,
+-			       scale, hint);
++  __builtin_ia32_scatterpfqps (mask, (__v8di) index, addr, scale, hint);
+ }
+ 
+ #else
+ #define _mm512_mask_prefetch_i32gather_pd(INDEX, MASK, ADDR, SCALE, HINT)    \
+   __builtin_ia32_gatherpfdpd ((__mmask8)MASK, (__v8si)(__m256i)INDEX,	     \
+-			      (long long const *)ADDR, (int)SCALE, (int)HINT)
++			      (void const *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_mask_prefetch_i32gather_ps(INDEX, MASK, ADDR, SCALE, HINT)    \
+   __builtin_ia32_gatherpfdps ((__mmask16)MASK, (__v16si)(__m512i)INDEX,      \
+-			      (int const *)ADDR, (int)SCALE, (int)HINT)
++			      (void const *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_mask_prefetch_i64gather_pd(INDEX, MASK, ADDR, SCALE, HINT)    \
+   __builtin_ia32_gatherpfqpd ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
+-			      (long long const *)ADDR, (int)SCALE, (int)HINT)
++			      (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_mask_prefetch_i64gather_ps(INDEX, MASK, ADDR, SCALE, HINT)    \
+   __builtin_ia32_gatherpfqps ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
+-			      (int const *)ADDR, (int)SCALE, (int)HINT)
++			      (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_prefetch_i32scatter_pd(ADDR, INDEX, SCALE, HINT)              \
+   __builtin_ia32_scatterpfdpd ((__mmask8)0xFF, (__v8si)(__m256i)INDEX,       \
+-			       (long long const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_prefetch_i32scatter_ps(ADDR, INDEX, SCALE, HINT)              \
+   __builtin_ia32_scatterpfdps ((__mmask16)0xFFFF, (__v16si)(__m512i)INDEX,   \
+-			       (int const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_mask_prefetch_i32scatter_pd(ADDR, MASK, INDEX, SCALE, HINT)   \
+   __builtin_ia32_scatterpfdpd ((__mmask8)MASK, (__v8si)(__m256i)INDEX,       \
+-			       (long long const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_mask_prefetch_i32scatter_ps(ADDR, MASK, INDEX, SCALE, HINT)   \
+   __builtin_ia32_scatterpfdps ((__mmask16)MASK, (__v16si)(__m512i)INDEX,     \
+-			       (int const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_prefetch_i64scatter_pd(ADDR, INDEX, SCALE, HINT)              \
+   __builtin_ia32_scatterpfqpd ((__mmask8)0xFF, (__v8di)(__m512i)INDEX,	     \
+-			       (long long const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_prefetch_i64scatter_ps(ADDR, INDEX, SCALE, HINT)              \
+   __builtin_ia32_scatterpfqps ((__mmask8)0xFF, (__v8di)(__m512i)INDEX,	     \
+-			       (int const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_mask_prefetch_i64scatter_pd(ADDR, MASK, INDEX, SCALE, HINT)   \
+   __builtin_ia32_scatterpfqpd ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
+-			       (long long const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ 
+ #define _mm512_mask_prefetch_i64scatter_ps(ADDR, MASK, INDEX, SCALE, HINT)   \
+   __builtin_ia32_scatterpfqps ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
+-			       (int const *)ADDR, (int)SCALE, (int)HINT)
++			       (void *)ADDR, (int)SCALE, (int)HINT)
+ #endif
+ 
+ #ifdef __DISABLE_AVX512PF__
+Index: gcc/config/i386/x86-64.h
+===================================================================
+--- a/src/gcc/config/i386/x86-64.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/x86-64.h	(.../branches/gcc-6-branch)
+@@ -49,7 +49,7 @@
+ #define WCHAR_TYPE_SIZE 32
+ 
+ #undef ASM_SPEC
+-#define ASM_SPEC "%{m32:--32} %{m64:--64} %{mx32:--x32}"
++#define ASM_SPEC "%{m16|m32:--32} %{m64:--64} %{mx32:--x32}"
+ 
+ #undef ASM_OUTPUT_ALIGNED_BSS
+ #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
+Index: gcc/config/i386/rtemself.h
+===================================================================
+--- a/src/gcc/config/i386/rtemself.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/rtemself.h	(.../branches/gcc-6-branch)
+@@ -29,7 +29,4 @@
+     }						\
+   while (0)
+ 
+-#undef LONG_DOUBLE_TYPE_SIZE
+-#define LONG_DOUBLE_TYPE_SIZE (TARGET_80387 ? 80 : 64)
+-
+ #define IX86_NO_LIBGCC_TFMODE
+Index: gcc/config/i386/cpuid.h
+===================================================================
+--- a/src/gcc/config/i386/cpuid.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/cpuid.h	(.../branches/gcc-6-branch)
+@@ -89,7 +89,7 @@
+ #define bit_AVX512CD	(1 << 28)
+ #define bit_SHA		(1 << 29)
+ #define bit_AVX512BW	(1 << 30)
+-#define bit_AVX512VL	(1 << 31)
++#define bit_AVX512VL	(1u << 31)
+ 
+ /* %ecx */
+ #define bit_PREFETCHWT1	  (1 << 0)
+Index: gcc/config/i386/i386-builtin-types.def
+===================================================================
+--- a/src/gcc/config/i386/i386-builtin-types.def	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/i386-builtin-types.def	(.../branches/gcc-6-branch)
+@@ -969,73 +969,73 @@
+ DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4DI, V4SI, INT)
+ DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V4DI, V8SI, INT)
+ 
+-DEF_FUNCTION_TYPE (V16SF, V16SF, PCFLOAT, V16SI, HI, INT)
+ DEF_FUNCTION_TYPE (V16SF, V16SF, PCFLOAT, V8DI, HI, INT)
+-DEF_FUNCTION_TYPE (V8DF, V8DF, PCDOUBLE, V8SI, QI, INT)
+ DEF_FUNCTION_TYPE (V8DF, V8DF, PCDOUBLE, V16SI, QI, INT)
+-DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V8DI, QI, INT)
+-DEF_FUNCTION_TYPE (V8DF, V8DF, PCDOUBLE, V8DI, QI, INT)
+-DEF_FUNCTION_TYPE (V16SI, V16SI, PCINT, V16SI, HI, INT)
+ DEF_FUNCTION_TYPE (V16SI, V16SI, PCINT, V8DI, HI, INT)
+-DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8SI, QI, INT)
+ DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V16SI, QI, INT)
+-DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8DI, QI, INT)
+-DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8DI, QI, INT)
+-DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V4SI, QI, INT)
+-DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4SI, QI, INT)
+ DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V8SI, QI, INT)
+-DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V2DI, QI, INT)
+-DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4DI, QI, INT)
+-DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4SI, QI, INT)
+-DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V8SI, QI, INT)
+-DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V2DI, QI, INT)
+-DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4DI, QI, INT)
+ DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V4DI, QI, INT)
+-DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V4SI, QI, INT)
+-DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4SI, QI, INT)
+ DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V8SI, QI, INT)
+-DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V2DI, QI, INT)
+-DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4DI, QI, INT)
+-DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4SI, QI, INT)
+-DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8SI, QI, INT)
+-DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V2DI, QI, INT)
+-DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4DI, QI, INT)
+ DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V4DI, QI, INT)
+ 
+-DEF_FUNCTION_TYPE (VOID, PFLOAT, HI, V16SI, V16SF, INT)
+-DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8SI, V8SF, INT)
+-DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4SI, V4SF, INT)
+-DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8SI, V8DF, INT)
+-DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V4DF, INT)
+-DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V2DF, INT)
+-DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8DI, V8SF, INT)
+-DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4DI, V4SF, INT)
+-DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V2DI, V4SF, INT)
+-DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8DI, V8DF, INT)
+-DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4DI, V4DF, INT)
+-DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V2DI, V2DF, INT)
+-DEF_FUNCTION_TYPE (VOID, PINT, HI, V16SI, V16SI, INT)
+-DEF_FUNCTION_TYPE (VOID, PINT, QI, V8SI, V8SI, INT)
+-DEF_FUNCTION_TYPE (VOID, PINT, QI, V4SI, V4SI, INT)
+-DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8SI, V8DI, INT)
+-DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V4DI, INT)
+-DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V2DI, INT)
+-DEF_FUNCTION_TYPE (VOID, PINT, QI, V8DI, V8SI, INT)
+-DEF_FUNCTION_TYPE (VOID, PINT, QI, V4DI, V4SI, INT)
+-DEF_FUNCTION_TYPE (VOID, PINT, QI, V2DI, V4SI, INT)
+-DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8DI, V8DI, INT)
+ DEF_FUNCTION_TYPE (VOID, PFLOAT, HI, V8DI, V16SF, INT)
+ DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V16SI, V8DF, INT)
+ DEF_FUNCTION_TYPE (VOID, PINT, HI, V8DI, V16SI, INT)
+ DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V16SI, V8DI, INT)
+ 
+-DEF_FUNCTION_TYPE (VOID, QI, V8SI, PCINT64, INT, INT)
+-DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4DI, V4DI, INT)
+-DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V2DI, V2DI, INT)
+-DEF_FUNCTION_TYPE (VOID, HI, V16SI, PCINT, INT, INT)
+-DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT64, INT, INT)
+-DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT, INT, INT)
+ 
++DEF_FUNCTION_TYPE (V16SF, V16SF, PCVOID, V16SI, HI, INT)
++DEF_FUNCTION_TYPE (V8DF, V8DF, PCVOID, V8SI, QI, INT)
++DEF_FUNCTION_TYPE (V8SF, V8SF, PCVOID, V8DI, QI, INT)
++DEF_FUNCTION_TYPE (V8DF, V8DF, PCVOID, V8DI, QI, INT)
++DEF_FUNCTION_TYPE (V16SI, V16SI, PCVOID, V16SI, HI, INT)
++DEF_FUNCTION_TYPE (V8DI, V8DI, PCVOID, V8SI, QI, INT)
++DEF_FUNCTION_TYPE (V8SI, V8SI, PCVOID, V8DI, QI, INT)
++DEF_FUNCTION_TYPE (V8DI, V8DI, PCVOID, V8DI, QI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, HI, V16SI, V16SF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8SI, V8DF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8DI, V8SF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8DI, V8DF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, HI, V16SI, V16SI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8SI, V8DI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8DI, V8SI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8DI, V8DI, INT)
++DEF_FUNCTION_TYPE (V2DF, V2DF, PCVOID, V4SI, QI, INT)
++DEF_FUNCTION_TYPE (V4DF, V4DF, PCVOID, V4SI, QI, INT)
++DEF_FUNCTION_TYPE (V2DF, V2DF, PCVOID, V2DI, QI, INT)
++DEF_FUNCTION_TYPE (V4DF, V4DF, PCVOID, V4DI, QI, INT)
++DEF_FUNCTION_TYPE (V4SF, V4SF, PCVOID, V4SI, QI, INT)
++DEF_FUNCTION_TYPE (V8SF, V8SF, PCVOID, V8SI, QI, INT)
++DEF_FUNCTION_TYPE (V4SF, V4SF, PCVOID, V2DI, QI, INT)
++DEF_FUNCTION_TYPE (V4SF, V4SF, PCVOID, V4DI, QI, INT)
++DEF_FUNCTION_TYPE (V2DI, V2DI, PCVOID, V4SI, QI, INT)
++DEF_FUNCTION_TYPE (V4DI, V4DI, PCVOID, V4SI, QI, INT)
++DEF_FUNCTION_TYPE (V2DI, V2DI, PCVOID, V2DI, QI, INT)
++DEF_FUNCTION_TYPE (V4DI, V4DI, PCVOID, V4DI, QI, INT)
++DEF_FUNCTION_TYPE (V4SI, V4SI, PCVOID, V4SI, QI, INT)
++DEF_FUNCTION_TYPE (V8SI, V8SI, PCVOID, V8SI, QI, INT)
++DEF_FUNCTION_TYPE (V4SI, V4SI, PCVOID, V2DI, QI, INT)
++DEF_FUNCTION_TYPE (V4SI, V4SI, PCVOID, V4DI, QI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8SI, V8SF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4SI, V4SF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4SI, V4DF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4SI, V2DF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4DI, V4SF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V2DI, V4SF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4DI, V4DF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V2DI, V2DF, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V8SI, V8SI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4SI, V4SI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4SI, V4DI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4SI, V2DI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4DI, V4SI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V2DI, V4SI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V4DI, V4DI, INT)
++DEF_FUNCTION_TYPE (VOID, PVOID, QI, V2DI, V2DI, INT)
++DEF_FUNCTION_TYPE (VOID, QI, V8SI, PCVOID, INT, INT)
++DEF_FUNCTION_TYPE (VOID, HI, V16SI, PCVOID, INT, INT)
++DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCVOID, INT, INT)
++
+ DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF, ROUND)
+ DEF_FUNCTION_TYPE_ALIAS (V4DF_FTYPE_V4DF, ROUND)
+ DEF_FUNCTION_TYPE_ALIAS (V8DF_FTYPE_V8DF, ROUND)
+Index: gcc/config/i386/avx512fintrin.h
+===================================================================
+--- a/src/gcc/config/i386/avx512fintrin.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/avx512fintrin.h	(.../branches/gcc-6-branch)
+@@ -9209,7 +9209,7 @@
+ #ifdef __OPTIMIZE__
+ extern __inline __m512
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32gather_ps (__m512i __index, float const *__addr, int __scale)
++_mm512_i32gather_ps (__m512i __index, void const *__addr, int __scale)
+ {
+   __m512 v1_old = _mm512_undefined_ps ();
+   __mmask16 mask = 0xFFFF;
+@@ -9223,7 +9223,7 @@
+ extern __inline __m512
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i32gather_ps (__m512 v1_old, __mmask16 __mask,
+-			  __m512i __index, float const *__addr, int __scale)
++			  __m512i __index, void const *__addr, int __scale)
+ {
+   return (__m512) __builtin_ia32_gathersiv16sf ((__v16sf) v1_old,
+ 						__addr,
+@@ -9233,7 +9233,7 @@
+ 
+ extern __inline __m512d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32gather_pd (__m256i __index, double const *__addr, int __scale)
++_mm512_i32gather_pd (__m256i __index, void const *__addr, int __scale)
+ {
+   __m512d v1_old = _mm512_undefined_pd ();
+   __mmask8 mask = 0xFF;
+@@ -9247,7 +9247,7 @@
+ extern __inline __m512d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i32gather_pd (__m512d __v1_old, __mmask8 __mask,
+-			  __m256i __index, double const *__addr, int __scale)
++			  __m256i __index, void const *__addr, int __scale)
+ {
+   return (__m512d) __builtin_ia32_gathersiv8df ((__v8df) __v1_old,
+ 						__addr,
+@@ -9257,7 +9257,7 @@
+ 
+ extern __inline __m256
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64gather_ps (__m512i __index, float const *__addr, int __scale)
++_mm512_i64gather_ps (__m512i __index, void const *__addr, int __scale)
+ {
+   __m256 v1_old = _mm256_undefined_ps ();
+   __mmask8 mask = 0xFF;
+@@ -9271,7 +9271,7 @@
+ extern __inline __m256
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i64gather_ps (__m256 __v1_old, __mmask8 __mask,
+-			  __m512i __index, float const *__addr, int __scale)
++			  __m512i __index, void const *__addr, int __scale)
+ {
+   return (__m256) __builtin_ia32_gatherdiv16sf ((__v8sf) __v1_old,
+ 						__addr,
+@@ -9281,7 +9281,7 @@
+ 
+ extern __inline __m512d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64gather_pd (__m512i __index, double const *__addr, int __scale)
++_mm512_i64gather_pd (__m512i __index, void const *__addr, int __scale)
+ {
+   __m512d v1_old = _mm512_undefined_pd ();
+   __mmask8 mask = 0xFF;
+@@ -9295,7 +9295,7 @@
+ extern __inline __m512d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i64gather_pd (__m512d __v1_old, __mmask8 __mask,
+-			  __m512i __index, double const *__addr, int __scale)
++			  __m512i __index, void const *__addr, int __scale)
+ {
+   return (__m512d) __builtin_ia32_gatherdiv8df ((__v8df) __v1_old,
+ 						__addr,
+@@ -9305,7 +9305,7 @@
+ 
+ extern __inline __m512i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32gather_epi32 (__m512i __index, int const *__addr, int __scale)
++_mm512_i32gather_epi32 (__m512i __index, void const *__addr, int __scale)
+ {
+   __m512i v1_old = _mm512_undefined_epi32 ();
+   __mmask16 mask = 0xFFFF;
+@@ -9319,7 +9319,7 @@
+ extern __inline __m512i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i32gather_epi32 (__m512i __v1_old, __mmask16 __mask,
+-			     __m512i __index, int const *__addr, int __scale)
++			     __m512i __index, void const *__addr, int __scale)
+ {
+   return (__m512i) __builtin_ia32_gathersiv16si ((__v16si) __v1_old,
+ 						 __addr,
+@@ -9329,7 +9329,7 @@
+ 
+ extern __inline __m512i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32gather_epi64 (__m256i __index, long long const *__addr, int __scale)
++_mm512_i32gather_epi64 (__m256i __index, void const *__addr, int __scale)
+ {
+   __m512i v1_old = _mm512_undefined_epi32 ();
+   __mmask8 mask = 0xFF;
+@@ -9343,7 +9343,7 @@
+ extern __inline __m512i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i32gather_epi64 (__m512i __v1_old, __mmask8 __mask,
+-			     __m256i __index, long long const *__addr,
++			     __m256i __index, void const *__addr,
+ 			     int __scale)
+ {
+   return (__m512i) __builtin_ia32_gathersiv8di ((__v8di) __v1_old,
+@@ -9354,7 +9354,7 @@
+ 
+ extern __inline __m256i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64gather_epi32 (__m512i __index, int const *__addr, int __scale)
++_mm512_i64gather_epi32 (__m512i __index, void const *__addr, int __scale)
+ {
+   __m256i v1_old = _mm256_undefined_si256 ();
+   __mmask8 mask = 0xFF;
+@@ -9368,7 +9368,7 @@
+ extern __inline __m256i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i64gather_epi32 (__m256i __v1_old, __mmask8 __mask,
+-			     __m512i __index, int const *__addr, int __scale)
++			     __m512i __index, void const *__addr, int __scale)
+ {
+   return (__m256i) __builtin_ia32_gatherdiv16si ((__v8si) __v1_old,
+ 						 __addr,
+@@ -9378,7 +9378,7 @@
+ 
+ extern __inline __m512i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64gather_epi64 (__m512i __index, long long const *__addr, int __scale)
++_mm512_i64gather_epi64 (__m512i __index, void const *__addr, int __scale)
+ {
+   __m512i v1_old = _mm512_undefined_epi32 ();
+   __mmask8 mask = 0xFF;
+@@ -9392,7 +9392,7 @@
+ extern __inline __m512i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm512_mask_i64gather_epi64 (__m512i __v1_old, __mmask8 __mask,
+-			     __m512i __index, long long const *__addr,
++			     __m512i __index, void const *__addr,
+ 			     int __scale)
+ {
+   return (__m512i) __builtin_ia32_gatherdiv8di ((__v8di) __v1_old,
+@@ -9403,7 +9403,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32scatter_ps (float *__addr, __m512i __index, __m512 __v1, int __scale)
++_mm512_i32scatter_ps (void *__addr, __m512i __index, __m512 __v1, int __scale)
+ {
+   __builtin_ia32_scattersiv16sf (__addr, (__mmask16) 0xFFFF,
+ 				 (__v16si) __index, (__v16sf) __v1, __scale);
+@@ -9411,7 +9411,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i32scatter_ps (float *__addr, __mmask16 __mask,
++_mm512_mask_i32scatter_ps (void *__addr, __mmask16 __mask,
+ 			   __m512i __index, __m512 __v1, int __scale)
+ {
+   __builtin_ia32_scattersiv16sf (__addr, __mask, (__v16si) __index,
+@@ -9420,7 +9420,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32scatter_pd (double *__addr, __m256i __index, __m512d __v1,
++_mm512_i32scatter_pd (void *__addr, __m256i __index, __m512d __v1,
+ 		      int __scale)
+ {
+   __builtin_ia32_scattersiv8df (__addr, (__mmask8) 0xFF,
+@@ -9429,7 +9429,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i32scatter_pd (double *__addr, __mmask8 __mask,
++_mm512_mask_i32scatter_pd (void *__addr, __mmask8 __mask,
+ 			   __m256i __index, __m512d __v1, int __scale)
+ {
+   __builtin_ia32_scattersiv8df (__addr, __mask, (__v8si) __index,
+@@ -9438,7 +9438,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64scatter_ps (float *__addr, __m512i __index, __m256 __v1, int __scale)
++_mm512_i64scatter_ps (void *__addr, __m512i __index, __m256 __v1, int __scale)
+ {
+   __builtin_ia32_scatterdiv16sf (__addr, (__mmask8) 0xFF,
+ 				 (__v8di) __index, (__v8sf) __v1, __scale);
+@@ -9446,7 +9446,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i64scatter_ps (float *__addr, __mmask8 __mask,
++_mm512_mask_i64scatter_ps (void *__addr, __mmask8 __mask,
+ 			   __m512i __index, __m256 __v1, int __scale)
+ {
+   __builtin_ia32_scatterdiv16sf (__addr, __mask, (__v8di) __index,
+@@ -9455,7 +9455,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64scatter_pd (double *__addr, __m512i __index, __m512d __v1,
++_mm512_i64scatter_pd (void *__addr, __m512i __index, __m512d __v1,
+ 		      int __scale)
+ {
+   __builtin_ia32_scatterdiv8df (__addr, (__mmask8) 0xFF,
+@@ -9464,7 +9464,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i64scatter_pd (double *__addr, __mmask8 __mask,
++_mm512_mask_i64scatter_pd (void *__addr, __mmask8 __mask,
+ 			   __m512i __index, __m512d __v1, int __scale)
+ {
+   __builtin_ia32_scatterdiv8df (__addr, __mask, (__v8di) __index,
+@@ -9473,7 +9473,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32scatter_epi32 (int *__addr, __m512i __index,
++_mm512_i32scatter_epi32 (void *__addr, __m512i __index,
+ 			 __m512i __v1, int __scale)
+ {
+   __builtin_ia32_scattersiv16si (__addr, (__mmask16) 0xFFFF,
+@@ -9482,7 +9482,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i32scatter_epi32 (int *__addr, __mmask16 __mask,
++_mm512_mask_i32scatter_epi32 (void *__addr, __mmask16 __mask,
+ 			      __m512i __index, __m512i __v1, int __scale)
+ {
+   __builtin_ia32_scattersiv16si (__addr, __mask, (__v16si) __index,
+@@ -9491,7 +9491,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i32scatter_epi64 (long long *__addr, __m256i __index,
++_mm512_i32scatter_epi64 (void *__addr, __m256i __index,
+ 			 __m512i __v1, int __scale)
+ {
+   __builtin_ia32_scattersiv8di (__addr, (__mmask8) 0xFF,
+@@ -9500,7 +9500,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i32scatter_epi64 (long long *__addr, __mmask8 __mask,
++_mm512_mask_i32scatter_epi64 (void *__addr, __mmask8 __mask,
+ 			      __m256i __index, __m512i __v1, int __scale)
+ {
+   __builtin_ia32_scattersiv8di (__addr, __mask, (__v8si) __index,
+@@ -9509,7 +9509,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64scatter_epi32 (int *__addr, __m512i __index,
++_mm512_i64scatter_epi32 (void *__addr, __m512i __index,
+ 			 __m256i __v1, int __scale)
+ {
+   __builtin_ia32_scatterdiv16si (__addr, (__mmask8) 0xFF,
+@@ -9518,7 +9518,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i64scatter_epi32 (int *__addr, __mmask8 __mask,
++_mm512_mask_i64scatter_epi32 (void *__addr, __mmask8 __mask,
+ 			      __m512i __index, __m256i __v1, int __scale)
+ {
+   __builtin_ia32_scatterdiv16si (__addr, __mask, (__v8di) __index,
+@@ -9527,7 +9527,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_i64scatter_epi64 (long long *__addr, __m512i __index,
++_mm512_i64scatter_epi64 (void *__addr, __m512i __index,
+ 			 __m512i __v1, int __scale)
+ {
+   __builtin_ia32_scatterdiv8di (__addr, (__mmask8) 0xFF,
+@@ -9536,7 +9536,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm512_mask_i64scatter_epi64 (long long *__addr, __mmask8 __mask,
++_mm512_mask_i64scatter_epi64 (void *__addr, __mmask8 __mask,
+ 			      __m512i __index, __m512i __v1, int __scale)
+ {
+   __builtin_ia32_scatterdiv8di (__addr, __mask, (__v8di) __index,
+@@ -9545,177 +9545,177 @@
+ #else
+ #define _mm512_i32gather_ps(INDEX, ADDR, SCALE)				\
+   (__m512) __builtin_ia32_gathersiv16sf ((__v16sf)_mm512_undefined_ps(),\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v16si)(__m512i)INDEX,	\
+ 					 (__mmask16)0xFFFF, (int)SCALE)
+ 
+ #define _mm512_mask_i32gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m512) __builtin_ia32_gathersiv16sf ((__v16sf)(__m512)V1OLD,	\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v16si)(__m512i)INDEX,	\
+ 					 (__mmask16)MASK, (int)SCALE)
+ 
+ #define _mm512_i32gather_pd(INDEX, ADDR, SCALE)				\
+   (__m512d) __builtin_ia32_gathersiv8df ((__v8df)_mm512_undefined_pd(),	\
+-					 (double const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v8si)(__m256i)INDEX,	\
+ 					 (__mmask8)0xFF, (int)SCALE)
+ 
+ #define _mm512_mask_i32gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m512d) __builtin_ia32_gathersiv8df ((__v8df)(__m512d)V1OLD,	\
+-					 (double const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v8si)(__m256i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm512_i64gather_ps(INDEX, ADDR, SCALE)				\
+   (__m256) __builtin_ia32_gatherdiv16sf ((__v8sf)_mm256_undefined_ps(),	\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v8di)(__m512i)INDEX,	\
+ 					 (__mmask8)0xFF, (int)SCALE)
+ 
+ #define _mm512_mask_i64gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256) __builtin_ia32_gatherdiv16sf ((__v8sf)(__m256)V1OLD,		\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v8di)(__m512i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm512_i64gather_pd(INDEX, ADDR, SCALE)				\
+   (__m512d) __builtin_ia32_gatherdiv8df ((__v8df)_mm512_undefined_pd(),	\
+-					 (double const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v8di)(__m512i)INDEX,	\
+ 					 (__mmask8)0xFF, (int)SCALE)
+ 
+ #define _mm512_mask_i64gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m512d) __builtin_ia32_gatherdiv8df ((__v8df)(__m512d)V1OLD,	\
+-					 (double const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v8di)(__m512i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm512_i32gather_epi32(INDEX, ADDR, SCALE)			\
+   (__m512i) __builtin_ia32_gathersiv16si ((__v16si)_mm512_undefined_epi32 (),	\
+-					  (int const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v16si)(__m512i)INDEX,	\
+ 					  (__mmask16)0xFFFF, (int)SCALE)
+ 
+ #define _mm512_mask_i32gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m512i) __builtin_ia32_gathersiv16si ((__v16si)(__m512i)V1OLD,	\
+-					  (int const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v16si)(__m512i)INDEX,	\
+ 					  (__mmask16)MASK, (int)SCALE)
+ 
+ #define _mm512_i32gather_epi64(INDEX, ADDR, SCALE)			\
+   (__m512i) __builtin_ia32_gathersiv8di ((__v8di)_mm512_undefined_epi32 (),	\
+-					 (long long const *)ADDR,	\
++					 (void const *)ADDR,		\
+ 					 (__v8si)(__m256i)INDEX,	\
+ 					 (__mmask8)0xFF, (int)SCALE)
+ 
+ #define _mm512_mask_i32gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m512i) __builtin_ia32_gathersiv8di ((__v8di)(__m512i)V1OLD,	\
+-					 (long long const *)ADDR,	\
++					 (void const *)ADDR,		\
+ 					 (__v8si)(__m256i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm512_i64gather_epi32(INDEX, ADDR, SCALE)			  \
+   (__m256i) __builtin_ia32_gatherdiv16si ((__v8si)_mm256_undefined_si256(), \
+-					  (int const *)ADDR,		  \
++					  (void const *)ADDR,		  \
+ 					  (__v8di)(__m512i)INDEX,	  \
+ 					  (__mmask8)0xFF, (int)SCALE)
+ 
+ #define _mm512_mask_i64gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256i) __builtin_ia32_gatherdiv16si ((__v8si)(__m256i)V1OLD,	\
+-					  (int const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v8di)(__m512i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm512_i64gather_epi64(INDEX, ADDR, SCALE)			\
+   (__m512i) __builtin_ia32_gatherdiv8di ((__v8di)_mm512_undefined_epi32 (),	\
+-					 (long long const *)ADDR,	\
++					 (void const *)ADDR,		\
+ 					 (__v8di)(__m512i)INDEX,	\
+ 					 (__mmask8)0xFF, (int)SCALE)
+ 
+ #define _mm512_mask_i64gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m512i) __builtin_ia32_gatherdiv8di ((__v8di)(__m512i)V1OLD,	\
+-					 (long long const *)ADDR,	\
++					 (void const *)ADDR,		\
+ 					 (__v8di)(__m512i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm512_i32scatter_ps(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv16sf ((float *)ADDR, (__mmask16)0xFFFF,	\
++  __builtin_ia32_scattersiv16sf ((void *)ADDR, (__mmask16)0xFFFF,	\
+ 				 (__v16si)(__m512i)INDEX,		\
+ 				 (__v16sf)(__m512)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i32scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv16sf ((float *)ADDR, (__mmask16)MASK,		\
++  __builtin_ia32_scattersiv16sf ((void *)ADDR, (__mmask16)MASK,		\
+ 				 (__v16si)(__m512i)INDEX,		\
+ 				 (__v16sf)(__m512)V1, (int)SCALE)
+ 
+ #define _mm512_i32scatter_pd(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv8df ((double *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scattersiv8df ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8df)(__m512d)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i32scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv8df ((double *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scattersiv8df ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8df)(__m512d)V1, (int)SCALE)
+ 
+ #define _mm512_i64scatter_ps(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv16sf ((float *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv16sf ((void *)ADDR, (__mmask8)0xFF,		\
+ 				 (__v8di)(__m512i)INDEX,		\
+ 				 (__v8sf)(__m256)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i64scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv16sf ((float *)ADDR, (__mmask16)MASK,		\
++  __builtin_ia32_scatterdiv16sf ((void *)ADDR, (__mmask16)MASK,		\
+ 				 (__v8di)(__m512i)INDEX,		\
+ 				 (__v8sf)(__m256)V1, (int)SCALE)
+ 
+ #define _mm512_i64scatter_pd(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv8df ((double *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv8df ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v8di)(__m512i)INDEX,			\
+ 				(__v8df)(__m512d)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i64scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv8df ((double *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv8df ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v8di)(__m512i)INDEX,			\
+ 				(__v8df)(__m512d)V1, (int)SCALE)
+ 
+ #define _mm512_i32scatter_epi32(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv16si ((int *)ADDR, (__mmask16)0xFFFF,	\
++  __builtin_ia32_scattersiv16si ((void *)ADDR, (__mmask16)0xFFFF,	\
+ 				 (__v16si)(__m512i)INDEX,		\
+ 				 (__v16si)(__m512i)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i32scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scattersiv16si ((int *)ADDR, (__mmask16)MASK,		\
++  __builtin_ia32_scattersiv16si ((void *)ADDR, (__mmask16)MASK,		\
+ 				 (__v16si)(__m512i)INDEX,		\
+ 				 (__v16si)(__m512i)V1, (int)SCALE)
+ 
+ #define _mm512_i32scatter_epi64(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv8di ((long long *)ADDR, (__mmask8)0xFF,	\
++  __builtin_ia32_scattersiv8di ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8di)(__m512i)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i32scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scattersiv8di ((long long *)ADDR, (__mmask8)MASK,	\
++  __builtin_ia32_scattersiv8di ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8di)(__m512i)V1, (int)SCALE)
+ 
+ #define _mm512_i64scatter_epi32(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv16si ((int *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv16si ((void *)ADDR, (__mmask8)0xFF,		\
+ 				 (__v8di)(__m512i)INDEX,		\
+ 				 (__v8si)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i64scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scatterdiv16si ((int *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv16si ((void *)ADDR, (__mmask8)MASK,		\
+ 				 (__v8di)(__m512i)INDEX,		\
+ 				 (__v8si)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm512_i64scatter_epi64(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv8di ((long long *)ADDR, (__mmask8)0xFF,	\
++  __builtin_ia32_scatterdiv8di ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v8di)(__m512i)INDEX,			\
+ 				(__v8di)(__m512i)V1, (int)SCALE)
+ 
+ #define _mm512_mask_i64scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scatterdiv8di ((long long *)ADDR, (__mmask8)MASK,	\
++  __builtin_ia32_scatterdiv8di ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v8di)(__m512i)INDEX,			\
+ 				(__v8di)(__m512i)V1, (int)SCALE)
+ #endif
+Index: gcc/config/i386/avx512vlintrin.h
+===================================================================
+--- a/src/gcc/config/i386/avx512vlintrin.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/avx512vlintrin.h	(.../branches/gcc-6-branch)
+@@ -10216,7 +10216,7 @@
+ extern __inline __m256
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i32gather_ps (__m256 __v1_old, __mmask8 __mask,
+-			   __m256i __index, float const *__addr,
++			   __m256i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m256) __builtin_ia32_gather3siv8sf ((__v8sf) __v1_old,
+@@ -10228,7 +10228,7 @@
+ extern __inline __m128
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i32gather_ps (__m128 __v1_old, __mmask8 __mask,
+-			__m128i __index, float const *__addr,
++			__m128i __index, void const *__addr,
+ 			int __scale)
+ {
+   return (__m128) __builtin_ia32_gather3siv4sf ((__v4sf) __v1_old,
+@@ -10240,7 +10240,7 @@
+ extern __inline __m256d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i32gather_pd (__m256d __v1_old, __mmask8 __mask,
+-			   __m128i __index, double const *__addr,
++			   __m128i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m256d) __builtin_ia32_gather3siv4df ((__v4df) __v1_old,
+@@ -10252,7 +10252,7 @@
+ extern __inline __m128d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i32gather_pd (__m128d __v1_old, __mmask8 __mask,
+-			__m128i __index, double const *__addr,
++			__m128i __index, void const *__addr,
+ 			int __scale)
+ {
+   return (__m128d) __builtin_ia32_gather3siv2df ((__v2df) __v1_old,
+@@ -10264,7 +10264,7 @@
+ extern __inline __m128
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i64gather_ps (__m128 __v1_old, __mmask8 __mask,
+-			   __m256i __index, float const *__addr,
++			   __m256i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m128) __builtin_ia32_gather3div8sf ((__v4sf) __v1_old,
+@@ -10276,7 +10276,7 @@
+ extern __inline __m128
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i64gather_ps (__m128 __v1_old, __mmask8 __mask,
+-			__m128i __index, float const *__addr,
++			__m128i __index, void const *__addr,
+ 			int __scale)
+ {
+   return (__m128) __builtin_ia32_gather3div4sf ((__v4sf) __v1_old,
+@@ -10288,7 +10288,7 @@
+ extern __inline __m256d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i64gather_pd (__m256d __v1_old, __mmask8 __mask,
+-			   __m256i __index, double const *__addr,
++			   __m256i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m256d) __builtin_ia32_gather3div4df ((__v4df) __v1_old,
+@@ -10300,7 +10300,7 @@
+ extern __inline __m128d
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i64gather_pd (__m128d __v1_old, __mmask8 __mask,
+-			__m128i __index, double const *__addr,
++			__m128i __index, void const *__addr,
+ 			int __scale)
+ {
+   return (__m128d) __builtin_ia32_gather3div2df ((__v2df) __v1_old,
+@@ -10312,7 +10312,7 @@
+ extern __inline __m256i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i32gather_epi32 (__m256i __v1_old, __mmask8 __mask,
+-			      __m256i __index, int const *__addr,
++			      __m256i __index, void const *__addr,
+ 			      int __scale)
+ {
+   return (__m256i) __builtin_ia32_gather3siv8si ((__v8si) __v1_old,
+@@ -10324,7 +10324,7 @@
+ extern __inline __m128i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i32gather_epi32 (__m128i __v1_old, __mmask8 __mask,
+-			   __m128i __index, int const *__addr,
++			   __m128i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m128i) __builtin_ia32_gather3siv4si ((__v4si) __v1_old,
+@@ -10336,7 +10336,7 @@
+ extern __inline __m256i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i32gather_epi64 (__m256i __v1_old, __mmask8 __mask,
+-			      __m128i __index, long long const *__addr,
++			      __m128i __index, void const *__addr,
+ 			      int __scale)
+ {
+   return (__m256i) __builtin_ia32_gather3siv4di ((__v4di) __v1_old,
+@@ -10348,7 +10348,7 @@
+ extern __inline __m128i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i32gather_epi64 (__m128i __v1_old, __mmask8 __mask,
+-			   __m128i __index, long long const *__addr,
++			   __m128i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m128i) __builtin_ia32_gather3siv2di ((__v2di) __v1_old,
+@@ -10360,7 +10360,7 @@
+ extern __inline __m128i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i64gather_epi32 (__m128i __v1_old, __mmask8 __mask,
+-			      __m256i __index, int const *__addr,
++			      __m256i __index, void const *__addr,
+ 			      int __scale)
+ {
+   return (__m128i) __builtin_ia32_gather3div8si ((__v4si) __v1_old,
+@@ -10372,7 +10372,7 @@
+ extern __inline __m128i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i64gather_epi32 (__m128i __v1_old, __mmask8 __mask,
+-			   __m128i __index, int const *__addr,
++			   __m128i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m128i) __builtin_ia32_gather3div4si ((__v4si) __v1_old,
+@@ -10384,7 +10384,7 @@
+ extern __inline __m256i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm256_mmask_i64gather_epi64 (__m256i __v1_old, __mmask8 __mask,
+-			      __m256i __index, long long const *__addr,
++			      __m256i __index, void const *__addr,
+ 			      int __scale)
+ {
+   return (__m256i) __builtin_ia32_gather3div4di ((__v4di) __v1_old,
+@@ -10396,7 +10396,7 @@
+ extern __inline __m128i
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+ _mm_mmask_i64gather_epi64 (__m128i __v1_old, __mmask8 __mask,
+-			   __m128i __index, long long const *__addr,
++			   __m128i __index, void const *__addr,
+ 			   int __scale)
+ {
+   return (__m128i) __builtin_ia32_gather3div2di ((__v2di) __v1_old,
+@@ -10407,7 +10407,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i32scatter_ps (float *__addr, __m256i __index,
++_mm256_i32scatter_ps (void *__addr, __m256i __index,
+ 		      __m256 __v1, const int __scale)
+ {
+   __builtin_ia32_scattersiv8sf (__addr, (__mmask8) 0xFF,
+@@ -10417,7 +10417,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i32scatter_ps (float *__addr, __mmask8 __mask,
++_mm256_mask_i32scatter_ps (void *__addr, __mmask8 __mask,
+ 			   __m256i __index, __m256 __v1,
+ 			   const int __scale)
+ {
+@@ -10427,7 +10427,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i32scatter_ps (float *__addr, __m128i __index, __m128 __v1,
++_mm_i32scatter_ps (void *__addr, __m128i __index, __m128 __v1,
+ 		   const int __scale)
+ {
+   __builtin_ia32_scattersiv4sf (__addr, (__mmask8) 0xFF,
+@@ -10437,7 +10437,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i32scatter_ps (float *__addr, __mmask8 __mask,
++_mm_mask_i32scatter_ps (void *__addr, __mmask8 __mask,
+ 			__m128i __index, __m128 __v1,
+ 			const int __scale)
+ {
+@@ -10447,7 +10447,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i32scatter_pd (double *__addr, __m128i __index,
++_mm256_i32scatter_pd (void *__addr, __m128i __index,
+ 		      __m256d __v1, const int __scale)
+ {
+   __builtin_ia32_scattersiv4df (__addr, (__mmask8) 0xFF,
+@@ -10457,7 +10457,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i32scatter_pd (double *__addr, __mmask8 __mask,
++_mm256_mask_i32scatter_pd (void *__addr, __mmask8 __mask,
+ 			   __m128i __index, __m256d __v1,
+ 			   const int __scale)
+ {
+@@ -10467,7 +10467,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i32scatter_pd (double *__addr, __m128i __index,
++_mm_i32scatter_pd (void *__addr, __m128i __index,
+ 		   __m128d __v1, const int __scale)
+ {
+   __builtin_ia32_scattersiv2df (__addr, (__mmask8) 0xFF,
+@@ -10477,7 +10477,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i32scatter_pd (double *__addr, __mmask8 __mask,
++_mm_mask_i32scatter_pd (void *__addr, __mmask8 __mask,
+ 			__m128i __index, __m128d __v1,
+ 			const int __scale)
+ {
+@@ -10487,7 +10487,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i64scatter_ps (float *__addr, __m256i __index,
++_mm256_i64scatter_ps (void *__addr, __m256i __index,
+ 		      __m128 __v1, const int __scale)
+ {
+   __builtin_ia32_scatterdiv8sf (__addr, (__mmask8) 0xFF,
+@@ -10497,7 +10497,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i64scatter_ps (float *__addr, __mmask8 __mask,
++_mm256_mask_i64scatter_ps (void *__addr, __mmask8 __mask,
+ 			   __m256i __index, __m128 __v1,
+ 			   const int __scale)
+ {
+@@ -10507,7 +10507,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i64scatter_ps (float *__addr, __m128i __index, __m128 __v1,
++_mm_i64scatter_ps (void *__addr, __m128i __index, __m128 __v1,
+ 		   const int __scale)
+ {
+   __builtin_ia32_scatterdiv4sf (__addr, (__mmask8) 0xFF,
+@@ -10517,7 +10517,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i64scatter_ps (float *__addr, __mmask8 __mask,
++_mm_mask_i64scatter_ps (void *__addr, __mmask8 __mask,
+ 			__m128i __index, __m128 __v1,
+ 			const int __scale)
+ {
+@@ -10527,7 +10527,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i64scatter_pd (double *__addr, __m256i __index,
++_mm256_i64scatter_pd (void *__addr, __m256i __index,
+ 		      __m256d __v1, const int __scale)
+ {
+   __builtin_ia32_scatterdiv4df (__addr, (__mmask8) 0xFF,
+@@ -10537,7 +10537,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i64scatter_pd (double *__addr, __mmask8 __mask,
++_mm256_mask_i64scatter_pd (void *__addr, __mmask8 __mask,
+ 			   __m256i __index, __m256d __v1,
+ 			   const int __scale)
+ {
+@@ -10547,7 +10547,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i64scatter_pd (double *__addr, __m128i __index,
++_mm_i64scatter_pd (void *__addr, __m128i __index,
+ 		   __m128d __v1, const int __scale)
+ {
+   __builtin_ia32_scatterdiv2df (__addr, (__mmask8) 0xFF,
+@@ -10557,7 +10557,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i64scatter_pd (double *__addr, __mmask8 __mask,
++_mm_mask_i64scatter_pd (void *__addr, __mmask8 __mask,
+ 			__m128i __index, __m128d __v1,
+ 			const int __scale)
+ {
+@@ -10567,7 +10567,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i32scatter_epi32 (int *__addr, __m256i __index,
++_mm256_i32scatter_epi32 (void *__addr, __m256i __index,
+ 			 __m256i __v1, const int __scale)
+ {
+   __builtin_ia32_scattersiv8si (__addr, (__mmask8) 0xFF,
+@@ -10577,7 +10577,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i32scatter_epi32 (int *__addr, __mmask8 __mask,
++_mm256_mask_i32scatter_epi32 (void *__addr, __mmask8 __mask,
+ 			      __m256i __index, __m256i __v1,
+ 			      const int __scale)
+ {
+@@ -10587,7 +10587,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i32scatter_epi32 (int *__addr, __m128i __index,
++_mm_i32scatter_epi32 (void *__addr, __m128i __index,
+ 		      __m128i __v1, const int __scale)
+ {
+   __builtin_ia32_scattersiv4si (__addr, (__mmask8) 0xFF,
+@@ -10597,7 +10597,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i32scatter_epi32 (int *__addr, __mmask8 __mask,
++_mm_mask_i32scatter_epi32 (void *__addr, __mmask8 __mask,
+ 			   __m128i __index, __m128i __v1,
+ 			   const int __scale)
+ {
+@@ -10607,7 +10607,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i32scatter_epi64 (long long *__addr, __m128i __index,
++_mm256_i32scatter_epi64 (void *__addr, __m128i __index,
+ 			 __m256i __v1, const int __scale)
+ {
+   __builtin_ia32_scattersiv4di (__addr, (__mmask8) 0xFF,
+@@ -10617,7 +10617,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i32scatter_epi64 (long long *__addr, __mmask8 __mask,
++_mm256_mask_i32scatter_epi64 (void *__addr, __mmask8 __mask,
+ 			      __m128i __index, __m256i __v1,
+ 			      const int __scale)
+ {
+@@ -10627,7 +10627,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i32scatter_epi64 (long long *__addr, __m128i __index,
++_mm_i32scatter_epi64 (void *__addr, __m128i __index,
+ 		      __m128i __v1, const int __scale)
+ {
+   __builtin_ia32_scattersiv2di (__addr, (__mmask8) 0xFF,
+@@ -10637,7 +10637,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i32scatter_epi64 (long long *__addr, __mmask8 __mask,
++_mm_mask_i32scatter_epi64 (void *__addr, __mmask8 __mask,
+ 			   __m128i __index, __m128i __v1,
+ 			   const int __scale)
+ {
+@@ -10647,7 +10647,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i64scatter_epi32 (int *__addr, __m256i __index,
++_mm256_i64scatter_epi32 (void *__addr, __m256i __index,
+ 			 __m128i __v1, const int __scale)
+ {
+   __builtin_ia32_scatterdiv8si (__addr, (__mmask8) 0xFF,
+@@ -10657,7 +10657,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i64scatter_epi32 (int *__addr, __mmask8 __mask,
++_mm256_mask_i64scatter_epi32 (void *__addr, __mmask8 __mask,
+ 			      __m256i __index, __m128i __v1,
+ 			      const int __scale)
+ {
+@@ -10667,7 +10667,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i64scatter_epi32 (int *__addr, __m128i __index,
++_mm_i64scatter_epi32 (void *__addr, __m128i __index,
+ 		      __m128i __v1, const int __scale)
+ {
+   __builtin_ia32_scatterdiv4si (__addr, (__mmask8) 0xFF,
+@@ -10677,7 +10677,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i64scatter_epi32 (int *__addr, __mmask8 __mask,
++_mm_mask_i64scatter_epi32 (void *__addr, __mmask8 __mask,
+ 			   __m128i __index, __m128i __v1,
+ 			   const int __scale)
+ {
+@@ -10687,7 +10687,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_i64scatter_epi64 (long long *__addr, __m256i __index,
++_mm256_i64scatter_epi64 (void *__addr, __m256i __index,
+ 			 __m256i __v1, const int __scale)
+ {
+   __builtin_ia32_scatterdiv4di (__addr, (__mmask8) 0xFF,
+@@ -10697,7 +10697,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm256_mask_i64scatter_epi64 (long long *__addr, __mmask8 __mask,
++_mm256_mask_i64scatter_epi64 (void *__addr, __mmask8 __mask,
+ 			      __m256i __index, __m256i __v1,
+ 			      const int __scale)
+ {
+@@ -10707,7 +10707,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_i64scatter_epi64 (long long *__addr, __m128i __index,
++_mm_i64scatter_epi64 (void *__addr, __m128i __index,
+ 		      __m128i __v1, const int __scale)
+ {
+   __builtin_ia32_scatterdiv2di (__addr, (__mmask8) 0xFF,
+@@ -10717,7 +10717,7 @@
+ 
+ extern __inline void
+ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+-_mm_mask_i64scatter_epi64 (long long *__addr, __mmask8 __mask,
++_mm_mask_i64scatter_epi64 (void *__addr, __mmask8 __mask,
+ 			   __m128i __index, __m128i __v1,
+ 			   const int __scale)
+ {
+@@ -12868,257 +12868,257 @@
+ 
+ #define _mm256_mmask_i32gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256) __builtin_ia32_gather3siv8sf ((__v8sf)(__m256)V1OLD,		\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v8si)(__m256i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i32gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)		\
+   (__m128) __builtin_ia32_gather3siv4sf ((__v4sf)(__m128)V1OLD,		\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v4si)(__m128i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_mmask_i32gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256d) __builtin_ia32_gather3siv4df ((__v4df)(__m256d)V1OLD,	\
+-					  (double const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v4si)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i32gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)		\
+   (__m128d) __builtin_ia32_gather3siv2df ((__v2df)(__m128d)V1OLD,	\
+-					  (double const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v4si)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_mmask_i64gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m128) __builtin_ia32_gather3div8sf ((__v4sf)(__m128)V1OLD,		\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v4di)(__m256i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i64gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)		\
+   (__m128) __builtin_ia32_gather3div4sf ((__v4sf)(__m128)V1OLD,		\
+-					 (float const *)ADDR,		\
++					 (void const *)ADDR,		\
+ 					 (__v2di)(__m128i)INDEX,	\
+ 					 (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_mmask_i64gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256d) __builtin_ia32_gather3div4df ((__v4df)(__m256d)V1OLD,	\
+-					  (double const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v4di)(__m256i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i64gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)		\
+   (__m128d) __builtin_ia32_gather3div2df ((__v2df)(__m128d)V1OLD,	\
+-					  (double const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v2di)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_mmask_i32gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256i) __builtin_ia32_gather3siv8si ((__v8si)(__m256i)V1OLD,	\
+-					  (int const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v8si)(__m256i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i32gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m128i) __builtin_ia32_gather3siv4si ((__v4si)(__m128i)V1OLD,	\
+-					  (int const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v4si)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_mmask_i32gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256i) __builtin_ia32_gather3siv4di ((__v4di)(__m256i)V1OLD,	\
+-					  (long long const *)ADDR,	\
++					  (void const *)ADDR,		\
+ 					  (__v4si)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i32gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m128i) __builtin_ia32_gather3siv2di ((__v2di)(__m128i)V1OLD,	\
+-					  (long long const *)ADDR,	\
++					  (void const *)ADDR,		\
+ 					  (__v4si)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_mmask_i64gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m128i) __builtin_ia32_gather3div8si ((__v4si)(__m128i)V1OLD,	\
+-					  (int const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v4di)(__m256i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i64gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m128i) __builtin_ia32_gather3div4si ((__v4si)(__m128i)V1OLD,	\
+-					  (int const *)ADDR,		\
++					  (void const *)ADDR,		\
+ 					  (__v2di)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_mmask_i64gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m256i) __builtin_ia32_gather3div4di ((__v4di)(__m256i)V1OLD,	\
+-					  (long long const *)ADDR,	\
++					  (void const *)ADDR,		\
+ 					  (__v4di)(__m256i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm_mmask_i64gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
+   (__m128i) __builtin_ia32_gather3div2di ((__v2di)(__m128i)V1OLD,	\
+-					  (long long const *)ADDR,	\
++					  (void const *)ADDR,		\
+ 					  (__v2di)(__m128i)INDEX,	\
+ 					  (__mmask8)MASK, (int)SCALE)
+ 
+ #define _mm256_i32scatter_ps(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv8sf ((float *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scattersiv8sf ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8sf)(__m256)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i32scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv8sf ((float *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scattersiv8sf ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8sf)(__m256)V1, (int)SCALE)
+ 
+ #define _mm_i32scatter_ps(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv4sf ((float *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scattersiv4sf ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4sf)(__m128)V1, (int)SCALE)
+ 
+ #define _mm_mask_i32scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv4sf ((float *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scattersiv4sf ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4sf)(__m128)V1, (int)SCALE)
+ 
+ #define _mm256_i32scatter_pd(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv4df ((double *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scattersiv4df ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4df)(__m256d)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i32scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv4df ((double *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scattersiv4df ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4df)(__m256d)V1, (int)SCALE)
+ 
+ #define _mm_i32scatter_pd(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv2df ((double *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scattersiv2df ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v2df)(__m128d)V1, (int)SCALE)
+ 
+ #define _mm_mask_i32scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv2df ((double *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scattersiv2df ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v2df)(__m128d)V1, (int)SCALE)
+ 
+ #define _mm256_i64scatter_ps(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv8sf ((float *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv8sf ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4sf)(__m128)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i64scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv8sf ((float *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv8sf ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4sf)(__m128)V1, (int)SCALE)
+ 
+ #define _mm_i64scatter_ps(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv4sf ((float *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv4sf ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v4sf)(__m128)V1, (int)SCALE)
+ 
+ #define _mm_mask_i64scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv4sf ((float *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv4sf ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v4sf)(__m128)V1, (int)SCALE)
+ 
+ #define _mm256_i64scatter_pd(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv4df ((double *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv4df ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4df)(__m256d)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i64scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv4df ((double *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv4df ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4df)(__m256d)V1, (int)SCALE)
+ 
+ #define _mm_i64scatter_pd(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv2df ((double *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv2df ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v2df)(__m128d)V1, (int)SCALE)
+ 
+ #define _mm_mask_i64scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv2df ((double *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv2df ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v2df)(__m128d)V1, (int)SCALE)
+ 
+ #define _mm256_i32scatter_epi32(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv8si ((int *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scattersiv8si ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8si)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i32scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scattersiv8si ((int *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scattersiv8si ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v8si)(__m256i)INDEX,			\
+ 				(__v8si)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm_i32scatter_epi32(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv4si ((int *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scattersiv4si ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4si)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm_mask_i32scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv4si ((int *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scattersiv4si ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4si)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm256_i32scatter_epi64(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv4di ((long long *)ADDR, (__mmask8)0xFF,	\
++  __builtin_ia32_scattersiv4di ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4di)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i32scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scattersiv4di ((long long *)ADDR, (__mmask8)MASK,	\
++  __builtin_ia32_scattersiv4di ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v4di)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm_i32scatter_epi64(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scattersiv2di ((long long *)ADDR, (__mmask8)0xFF,	\
++  __builtin_ia32_scattersiv2di ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v2di)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm_mask_i32scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scattersiv2di ((long long *)ADDR, (__mmask8)MASK,	\
++  __builtin_ia32_scattersiv2di ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4si)(__m128i)INDEX,			\
+ 				(__v2di)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm256_i64scatter_epi32(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv8si ((int *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv8si ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4si)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i64scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scatterdiv8si ((int *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv8si ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4si)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm_i64scatter_epi32(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv4si ((int *)ADDR, (__mmask8)0xFF,		\
++  __builtin_ia32_scatterdiv4si ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v4si)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm_mask_i64scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv4si ((int *)ADDR, (__mmask8)MASK,		\
++  __builtin_ia32_scatterdiv4si ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v4si)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm256_i64scatter_epi64(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv4di ((long long *)ADDR, (__mmask8)0xFF,	\
++  __builtin_ia32_scatterdiv4di ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4di)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm256_mask_i64scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
+-  __builtin_ia32_scatterdiv4di ((long long *)ADDR, (__mmask8)MASK,	\
++  __builtin_ia32_scatterdiv4di ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v4di)(__m256i)INDEX,			\
+ 				(__v4di)(__m256i)V1, (int)SCALE)
+ 
+ #define _mm_i64scatter_epi64(ADDR, INDEX, V1, SCALE)			\
+-  __builtin_ia32_scatterdiv2di ((long long *)ADDR, (__mmask8)0xFF,	\
++  __builtin_ia32_scatterdiv2di ((void *)ADDR, (__mmask8)0xFF,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v2di)(__m128i)V1, (int)SCALE)
+ 
+ #define _mm_mask_i64scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)		\
+-  __builtin_ia32_scatterdiv2di ((long long *)ADDR, (__mmask8)MASK,	\
++  __builtin_ia32_scatterdiv2di ((void *)ADDR, (__mmask8)MASK,		\
+ 				(__v2di)(__m128i)INDEX,			\
+ 				(__v2di)(__m128i)V1, (int)SCALE)
+ 
+Index: gcc/config/i386/i386.c
+===================================================================
+--- a/src/gcc/config/i386/i386.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/i386/i386.c	(.../branches/gcc-6-branch)
+@@ -27721,7 +27721,7 @@
+   else if (disp && !base && !index)
+     {
+       len += 4;
+-      if (rip_relative_addr_p (&parts))
++      if (!rip_relative_addr_p (&parts))
+ 	len++;
+     }
+   else
+@@ -29372,7 +29372,7 @@
+ 		  != TYPE_MAIN_VARIANT (va_list_type_node)))
+ 	  && TYPE_SIZE (type)
+ 	  && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
+-	  && wi::geu_p (TYPE_SIZE (type), 16)
++	  && wi::geu_p (TYPE_SIZE (type), 128)
+ 	  && align < 128)
+ 	return 128;
+     }
+@@ -35719,35 +35719,35 @@
+ 
+   /* AVX512F */
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16sf",
+-	       V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
++	       V16SF_FTYPE_V16SF_PCVOID_V16SI_HI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV16SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8df",
+-	       V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
++	       V8DF_FTYPE_V8DF_PCVOID_V8SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV8DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16sf",
+-	       V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
++	       V8SF_FTYPE_V8SF_PCVOID_V8DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV16SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8df",
+-	       V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
++	       V8DF_FTYPE_V8DF_PCVOID_V8DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV8DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16si",
+-	       V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
++	       V16SI_FTYPE_V16SI_PCVOID_V16SI_HI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV16SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8di",
+-	       V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
++	       V8DI_FTYPE_V8DI_PCVOID_V8SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV8DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16si",
+-	       V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
++	       V8SI_FTYPE_V8SI_PCVOID_V8DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV16SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8di",
+-	       V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
++	       V8DI_FTYPE_V8DI_PCVOID_V8DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV8DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8df ",
+@@ -35767,100 +35767,100 @@
+ 	       IX86_BUILTIN_GATHER3ALTDIV16SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scattersiv16sf",
+-	       VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
++	       VOID_FTYPE_PVOID_HI_V16SI_V16SF_INT,
+ 	       IX86_BUILTIN_SCATTERSIV16SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scattersiv8df",
+-	       VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
++	       VOID_FTYPE_PVOID_QI_V8SI_V8DF_INT,
+ 	       IX86_BUILTIN_SCATTERSIV8DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scatterdiv16sf",
+-	       VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
++	       VOID_FTYPE_PVOID_QI_V8DI_V8SF_INT,
+ 	       IX86_BUILTIN_SCATTERDIV16SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scatterdiv8df",
+-	       VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
++	       VOID_FTYPE_PVOID_QI_V8DI_V8DF_INT,
+ 	       IX86_BUILTIN_SCATTERDIV8DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scattersiv16si",
+-	       VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
++	       VOID_FTYPE_PVOID_HI_V16SI_V16SI_INT,
+ 	       IX86_BUILTIN_SCATTERSIV16SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scattersiv8di",
+-	       VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
++	       VOID_FTYPE_PVOID_QI_V8SI_V8DI_INT,
+ 	       IX86_BUILTIN_SCATTERSIV8DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scatterdiv16si",
+-	       VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
++	       VOID_FTYPE_PVOID_QI_V8DI_V8SI_INT,
+ 	       IX86_BUILTIN_SCATTERDIV16SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scatterdiv8di",
+-	       VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
++	       VOID_FTYPE_PVOID_QI_V8DI_V8DI_INT,
+ 	       IX86_BUILTIN_SCATTERDIV8DI);
+ 
+   /* AVX512VL */
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2df",
+-	       V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
++	       V2DF_FTYPE_V2DF_PCVOID_V4SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV2DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4df",
+-	       V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
++	       V4DF_FTYPE_V4DF_PCVOID_V4SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV4DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2df",
+-	       V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
++	       V2DF_FTYPE_V2DF_PCVOID_V2DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV2DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4df",
+-	       V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
++	       V4DF_FTYPE_V4DF_PCVOID_V4DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV4DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4sf",
+-	       V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
++	       V4SF_FTYPE_V4SF_PCVOID_V4SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV4SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8sf",
+-	       V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
++	       V8SF_FTYPE_V8SF_PCVOID_V8SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV8SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4sf",
+-	       V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
++	       V4SF_FTYPE_V4SF_PCVOID_V2DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV4SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8sf",
+-	       V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
++	       V4SF_FTYPE_V4SF_PCVOID_V4DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV8SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2di",
+-	       V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
++	       V2DI_FTYPE_V2DI_PCVOID_V4SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV2DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4di",
+-	       V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
++	       V4DI_FTYPE_V4DI_PCVOID_V4SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV4DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2di",
+-	       V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
++	       V2DI_FTYPE_V2DI_PCVOID_V2DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV2DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4di",
+-	       V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
++	       V4DI_FTYPE_V4DI_PCVOID_V4DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV4DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4si",
+-	       V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
++	       V4SI_FTYPE_V4SI_PCVOID_V4SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV4SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8si",
+-	       V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
++	       V8SI_FTYPE_V8SI_PCVOID_V8SI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3SIV8SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4si",
+-	       V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
++	       V4SI_FTYPE_V4SI_PCVOID_V2DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV4SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8si",
+-	       V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
++	       V4SI_FTYPE_V4SI_PCVOID_V4DI_QI_INT,
+ 	       IX86_BUILTIN_GATHER3DIV8SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4df ",
+@@ -35880,67 +35880,67 @@
+ 	       IX86_BUILTIN_GATHER3ALTDIV8SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv8sf",
+-	       VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
++	       VOID_FTYPE_PVOID_QI_V8SI_V8SF_INT,
+ 	       IX86_BUILTIN_SCATTERSIV8SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4sf",
+-	       VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
++	       VOID_FTYPE_PVOID_QI_V4SI_V4SF_INT,
+ 	       IX86_BUILTIN_SCATTERSIV4SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4df",
+-	       VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
++	       VOID_FTYPE_PVOID_QI_V4SI_V4DF_INT,
+ 	       IX86_BUILTIN_SCATTERSIV4DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv2df",
+-	       VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
++	       VOID_FTYPE_PVOID_QI_V4SI_V2DF_INT,
+ 	       IX86_BUILTIN_SCATTERSIV2DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv8sf",
+-	       VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
++	       VOID_FTYPE_PVOID_QI_V4DI_V4SF_INT,
+ 	       IX86_BUILTIN_SCATTERDIV8SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4sf",
+-	       VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
++	       VOID_FTYPE_PVOID_QI_V2DI_V4SF_INT,
+ 	       IX86_BUILTIN_SCATTERDIV4SF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4df",
+-	       VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
++	       VOID_FTYPE_PVOID_QI_V4DI_V4DF_INT,
+ 	       IX86_BUILTIN_SCATTERDIV4DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv2df",
+-	       VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
++	       VOID_FTYPE_PVOID_QI_V2DI_V2DF_INT,
+ 	       IX86_BUILTIN_SCATTERDIV2DF);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv8si",
+-	       VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
++	       VOID_FTYPE_PVOID_QI_V8SI_V8SI_INT,
+ 	       IX86_BUILTIN_SCATTERSIV8SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4si",
+-	       VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
++	       VOID_FTYPE_PVOID_QI_V4SI_V4SI_INT,
+ 	       IX86_BUILTIN_SCATTERSIV4SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4di",
+-	       VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
++	       VOID_FTYPE_PVOID_QI_V4SI_V4DI_INT,
+ 	       IX86_BUILTIN_SCATTERSIV4DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv2di",
+-	       VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
++	       VOID_FTYPE_PVOID_QI_V4SI_V2DI_INT,
+ 	       IX86_BUILTIN_SCATTERSIV2DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv8si",
+-	       VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
++	       VOID_FTYPE_PVOID_QI_V4DI_V4SI_INT,
+ 	       IX86_BUILTIN_SCATTERDIV8SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4si",
+-	       VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
++	       VOID_FTYPE_PVOID_QI_V2DI_V4SI_INT,
+ 	       IX86_BUILTIN_SCATTERDIV4SI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4di",
+-	       VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
++	       VOID_FTYPE_PVOID_QI_V4DI_V4DI_INT,
+ 	       IX86_BUILTIN_SCATTERDIV4DI);
+ 
+   def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv2di",
+-	       VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
++	       VOID_FTYPE_PVOID_QI_V2DI_V2DI_INT,
+ 	       IX86_BUILTIN_SCATTERDIV2DI);
+   def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scatteraltsiv8df ",
+ 	       VOID_FTYPE_PDOUBLE_QI_V16SI_V8DF_INT,
+@@ -35960,28 +35960,28 @@
+ 
+   /* AVX512PF */
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfdpd",
+-	       VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
++	       VOID_FTYPE_QI_V8SI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_GATHERPFDPD);
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfdps",
+-	       VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
++	       VOID_FTYPE_HI_V16SI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_GATHERPFDPS);
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfqpd",
+-	       VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
++	       VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_GATHERPFQPD);
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfqps",
+-	       VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
++	       VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_GATHERPFQPS);
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_scatterpfdpd",
+-	       VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
++	       VOID_FTYPE_QI_V8SI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_SCATTERPFDPD);
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_scatterpfdps",
+-	       VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
++	       VOID_FTYPE_HI_V16SI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_SCATTERPFDPS);
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_scatterpfqpd",
+-	       VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
++	       VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_SCATTERPFQPD);
+   def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_scatterpfqps",
+-	       VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
++	       VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
+ 	       IX86_BUILTIN_SCATTERPFQPS);
+ 
+   /* SHA */
+@@ -45938,10 +45938,16 @@
+   if (recog_memoized (insn) < 0)
+     {
+       rtx_insn *seq;
++      machine_mode innermode = GET_MODE_INNER (mode);
++      rtx reg;
++
+       /* If that fails, force VAL into a register.  */
+ 
+       start_sequence ();
+-      XEXP (dup, 0) = force_reg (GET_MODE_INNER (mode), val);
++      reg = force_reg (innermode, val);
++      if (GET_MODE (reg) != innermode)
++	reg = gen_lowpart (innermode, reg);
++      XEXP (dup, 0) = reg;
+       seq = get_insns ();
+       end_sequence ();
+       if (seq)
+Index: gcc/config/tilegx/tilegx.c
+===================================================================
+--- a/src/gcc/config/tilegx/tilegx.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/tilegx/tilegx.c	(.../branches/gcc-6-branch)
+@@ -3996,8 +3996,11 @@
+   /* Save lr first in its special location because code after this
+      might use the link register as a scratch register.  */
+   if (df_regs_ever_live_p (TILEGX_LINK_REGNUM) || crtl->calls_eh_return)
+-    FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
+-			   stack_pointer_rtx, stack_pointer_rtx, 0));
++    {
++      FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
++			     stack_pointer_rtx, stack_pointer_rtx, 0));
++      emit_insn (gen_blockage ());
++    }
+ 
+   if (total_size == 0)
+     {
+Index: gcc/config/nds32/nds32.md
+===================================================================
+--- a/src/gcc/config/nds32/nds32.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/nds32/nds32.md	(.../branches/gcc-6-branch)
+@@ -2288,11 +2288,9 @@
+   emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
+ 				  operands[4]));
+ 
+-  operands[5] = gen_reg_rtx (SImode);
+-  /* Step C, D, E, and F, using another temporary register operands[5].  */
+-  emit_jump_insn (gen_casesi_internal (operands[0],
+-				       operands[3],
+-				       operands[5]));
++  /* Step C, D, E, and F, using another temporary register.  */
++  rtx tmp = gen_reg_rtx (SImode);
++  emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp));
+   DONE;
+ })
+ 
+Index: gcc/config/aarch64/t-aarch64-freebsd
+===================================================================
+--- a/src/gcc/config/aarch64/t-aarch64-freebsd	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/t-aarch64-freebsd	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++# Machine description for AArch64 architecture.
++#  Copyright (C) 2016-2017 Free Software Foundation, Inc.
++#
++#  This file is part of GCC.
++#
++#  GCC is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by
++#  the Free Software Foundation; either version 3, or (at your option)
++#  any later version.
++#
++#  GCC is distributed in the hope that it will be useful, but
++#  WITHOUT ANY WARRANTY; without even the implied warranty of
++#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++#  General Public License for more details.
++#
++#  You should have received a copy of the GNU General Public License
++#  along with GCC; see the file COPYING3.  If not see
++#  <http://www.gnu.org/licenses/>.
++
++LIB1ASMSRC   = aarch64/lib1funcs.asm
++LIB1ASMFUNCS = _aarch64_sync_cache_range
+Index: gcc/config/aarch64/aarch64-freebsd.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-freebsd.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64-freebsd.h	(.../branches/gcc-6-branch)
+@@ -0,0 +1,94 @@
++/* Definitions for AArch64 running FreeBSD
++   Copyright (C) 2016-2017 Free Software Foundation, Inc.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3, or (at your option)
++   any later version.
++
++   GCC is distributed in the hope that it will be useful, but
++   WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_AARCH64_FREEBSD_H
++#define GCC_AARCH64_FREEBSD_H
++
++#undef  SUBTARGET_CPP_SPEC
++#define SUBTARGET_CPP_SPEC FBSD_CPP_SPEC
++
++#if TARGET_BIG_ENDIAN_DEFAULT
++#define TARGET_LINKER_EMULATION  "aarch64fbsdb"
++#else
++#define TARGET_LINKER_EMULATION  "aarch64fbsd"
++#endif
++
++#undef  SUBTARGET_EXTRA_LINK_SPEC
++#define SUBTARGET_EXTRA_LINK_SPEC " -m" TARGET_LINKER_EMULATION
++
++#undef  FBSD_TARGET_LINK_SPEC
++#define FBSD_TARGET_LINK_SPEC "                                 \
++    %{p:%nconsider using `-pg' instead of `-p' with gprof (1) } \
++    %{v:-V}                                                     \
++    %{assert*} %{R*} %{rpath*} %{defsym*}                       \
++    %{shared:-Bshareable %{h*} %{soname*}}                      \
++    %{symbolic:-Bsymbolic}                                      \
++    %{static:-Bstatic}                                          \
++    %{!static:                                                  \
++      %{rdynamic:-export-dynamic}                               \
++      %{!shared:-dynamic-linker " FBSD_DYNAMIC_LINKER " }}      \
++    -X" SUBTARGET_EXTRA_LINK_SPEC "                             \
++    %{mbig-endian:-EB} %{mlittle-endian:-EL}"
++
++#if TARGET_FIX_ERR_A53_835769_DEFAULT
++#define CA53_ERR_835769_SPEC \
++  " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}"
++#else
++#define CA53_ERR_835769_SPEC \
++  " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}"
++#endif
++
++#ifdef TARGET_FIX_ERR_A53_843419_DEFAULT
++#define CA53_ERR_843419_SPEC \
++  " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}"
++#else
++#define CA53_ERR_843419_SPEC \
++  " %{mfix-cortex-a53-843419:--fix-cortex-a53-843419}"
++#endif
++
++#undef  LINK_SPEC
++#define LINK_SPEC FBSD_TARGET_LINK_SPEC	\
++                  CA53_ERR_835769_SPEC	\
++                  CA53_ERR_843419_SPEC
++
++#define GNU_USER_TARGET_MATHFILE_SPEC \
++  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
++
++#undef ENDFILE_SPEC
++#define ENDFILE_SPEC \
++    GNU_USER_TARGET_MATHFILE_SPEC " " \
++    FBSD_ENDFILE_SPEC
++
++#undef  TARGET_OS_CPP_BUILTINS
++#define TARGET_OS_CPP_BUILTINS()              \
++  do                                          \
++  {                                           \
++      FBSD_TARGET_OS_CPP_BUILTINS ();         \
++  }                                           \
++  while (false)
++
++#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
++
++/* Uninitialized common symbols in non-PIE executables, even with
++   strong definitions in dependent shared libraries, will resolve
++   to COPY relocated symbol in the executable.  See PR65780.  */
++#undef TARGET_BINDS_LOCAL_P
++#define TARGET_BINDS_LOCAL_P default_binds_local_p_2
++
++#endif  /* GCC_AARCH64_FREEBSD_H */
+Index: gcc/config/aarch64/aarch64.md
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64.md	(.../branches/gcc-6-branch)
+@@ -587,25 +587,6 @@
+   [(set_attr "type" "branch")]
+ )
+ 
+-(define_insn "eh_return"
+-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
+-    UNSPECV_EH_RETURN)]
+-  ""
+-  "#"
+-  [(set_attr "type" "branch")]
+-
+-)
+-
+-(define_split
+-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "")]
+-    UNSPECV_EH_RETURN)]
+-  "reload_completed"
+-  [(set (match_dup 1) (match_dup 0))]
+-  {
+-    operands[1] = aarch64_final_eh_return_addr ();
+-  }
+-)
+-
+ (define_insn "*cb<optab><mode>1"
+   [(set (pc) (if_then_else (EQL (match_operand:GPI 0 "register_operand" "r")
+ 				(const_int 0))
+Index: gcc/config/aarch64/aarch64-protos.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-protos.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64-protos.h	(.../branches/gcc-6-branch)
+@@ -338,7 +338,7 @@
+ int aarch64_simd_attr_length_move (rtx_insn *);
+ int aarch64_uxt_size (int, HOST_WIDE_INT);
+ int aarch64_vec_fpconst_pow_of_2 (rtx);
+-rtx aarch64_final_eh_return_addr (void);
++rtx aarch64_eh_return_handler_rtx (void);
+ rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int);
+ rtx aarch64_mask_from_zextract_ops (rtx, rtx);
+ const char *aarch64_output_move_struct (rtx *operands);
+Index: gcc/config/aarch64/aarch64.c
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64.c	(.../branches/gcc-6-branch)
+@@ -2480,6 +2480,10 @@
+       && (!crtl->is_leaf || df_regs_ever_live_p (LR_REGNUM)))
+     return true;
+ 
++  /* Force a frame pointer for EH returns so the return address is at FP+8.  */
++  if (crtl->calls_eh_return)
++    return true;
++
+   return false;
+ }
+ 
+@@ -3036,7 +3040,8 @@
+   rtx_insn *insn;
+   /* We need to add memory barrier to prevent read from deallocated stack.  */
+   bool need_barrier_p = (get_frame_size () != 0
+-			 || cfun->machine->frame.saved_varargs_size);
++			 || cfun->machine->frame.saved_varargs_size
++			 || crtl->calls_eh_return);
+ 
+   aarch64_layout_frame ();
+ 
+@@ -3189,52 +3194,40 @@
+     emit_jump_insn (ret_rtx);
+ }
+ 
+-/* Return the place to copy the exception unwinding return address to.
+-   This will probably be a stack slot, but could (in theory be the
+-   return register).  */
+-rtx
+-aarch64_final_eh_return_addr (void)
+-{
+-  HOST_WIDE_INT fp_offset;
++/* Implement EH_RETURN_HANDLER_RTX.  EH returns need to either return
++   normally or return to a previous frame after unwinding.
+ 
+-  aarch64_layout_frame ();
++   An EH return uses a single shared return sequence.  The epilogue is
++   exactly like a normal epilogue except that it has an extra input
++   register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
++   that must be applied after the frame has been destroyed.  An extra label
++   is inserted before the epilogue which initializes this register to zero,
++   and this is the entry point for a normal return.
+ 
+-  fp_offset = cfun->machine->frame.frame_size
+-	      - cfun->machine->frame.hard_fp_offset;
++   An actual EH return updates the return address, initializes the stack
++   adjustment and jumps directly into the epilogue (bypassing the zeroing
++   of the adjustment).  Since the return address is typically saved on the
++   stack when a function makes a call, the saved LR must be updated outside
++   the epilogue.
+ 
+-  if (cfun->machine->frame.reg_offset[LR_REGNUM] < 0)
+-    return gen_rtx_REG (DImode, LR_REGNUM);
++   This poses problems as the store is generated well before the epilogue,
++   so the offset of LR is not known yet.  Also optimizations will remove the
++   store as it appears dead, even after the epilogue is generated (as the
++   base or offset for loading LR is different in many cases).
+ 
+-  /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2.  This can
+-     result in a store to save LR introduced by builtin_eh_return () being
+-     incorrectly deleted because the alias is not detected.
+-     So in the calculation of the address to copy the exception unwinding
+-     return address to, we note 2 cases.
+-     If FP is needed and the fp_offset is 0, it means that SP = FP and hence
+-     we return a SP-relative location since all the addresses are SP-relative
+-     in this case.  This prevents the store from being optimized away.
+-     If the fp_offset is not 0, then the addresses will be FP-relative and
+-     therefore we return a FP-relative location.  */
++   To avoid these problems this implementation forces the frame pointer
++   in eh_return functions so that the location of LR is fixed and known early.
++   It also marks the store volatile, so no optimization is permitted to
++   remove the store.  */
++rtx
++aarch64_eh_return_handler_rtx (void)
++{
++  rtx tmp = gen_frame_mem (Pmode,
++    plus_constant (Pmode, hard_frame_pointer_rtx, UNITS_PER_WORD));
+ 
+-  if (frame_pointer_needed)
+-    {
+-      if (fp_offset)
+-        return gen_frame_mem (DImode,
+-			      plus_constant (Pmode, hard_frame_pointer_rtx, UNITS_PER_WORD));
+-      else
+-        return gen_frame_mem (DImode,
+-			      plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD));
+-    }
+-
+-  /* If FP is not needed, we calculate the location of LR, which would be
+-     at the top of the saved registers block.  */
+-
+-  return gen_frame_mem (DImode,
+-			plus_constant (Pmode,
+-				       stack_pointer_rtx,
+-				       fp_offset
+-				       + cfun->machine->frame.saved_regs_size
+-				       - 2 * UNITS_PER_WORD));
++  /* Mark the store volatile, so no optimization is permitted to remove it.  */
++  MEM_VOLATILE_P (tmp) = true;
++  return tmp;
+ }
+ 
+ /* Possibly output code to build up a constant in a register.  For
+Index: gcc/config/aarch64/aarch64.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64.h	(.../branches/gcc-6-branch)
+@@ -389,9 +389,9 @@
+ #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)	\
+   aarch64_declare_function_name (STR, NAME, DECL)
+ 
+-/* The register that holds the return address in exception handlers.  */
+-#define AARCH64_EH_STACKADJ_REGNUM	(R0_REGNUM + 4)
+-#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM)
++/* For EH returns X4 contains the stack adjustment.  */
++#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, R4_REGNUM)
++#define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
+ 
+ /* Don't use __builtin_setjmp until we've defined it.  */
+ #undef DONT_USE_BUILTIN_SETJMP
+Index: gcc/config/rs6000/predicates.md
+===================================================================
+--- a/src/gcc/config/rs6000/predicates.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/predicates.md	(.../branches/gcc-6-branch)
+@@ -1000,7 +1000,8 @@
+   (and (match_code "symbol_ref")
+        (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
+ 		    && (SYMBOL_REF_LOCAL_P (op)
+-			|| op == XEXP (DECL_RTL (current_function_decl), 0))
++			|| (op == XEXP (DECL_RTL (current_function_decl), 0)
++			    && !decl_replaceable_p (current_function_decl)))
+ 		    && !((DEFAULT_ABI == ABI_AIX
+ 			  || DEFAULT_ABI == ABI_ELFv2)
+ 			 && (SYMBOL_REF_EXTERNAL_P (op)
+Index: gcc/config/rs6000/rs6000-c.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000-c.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000-c.c	(.../branches/gcc-6-branch)
+@@ -2133,14 +2133,14 @@
+     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
+     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
++  { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
++    RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
++  { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
++    RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+   { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
+     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+   { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
+     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+-  { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
+-    RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+-  { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
+-    RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
+     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
+   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
+@@ -2411,7 +2411,7 @@
+     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
+     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+-  { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD,
++  { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
+     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
+     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+@@ -4512,7 +4512,7 @@
+ 
+   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
+     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+-  { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD,
++  { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
+     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+ 
+   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
+@@ -4550,11 +4550,6 @@
+   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
+     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
+ 
+-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+-    RS6000_BTI_V16QI, 0, 0, 0 },
+-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+-    RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
+-
+   { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
+     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+     RS6000_BTI_unsigned_V16QI, 0 },
+Index: gcc/config/rs6000/rs6000.opt
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.opt	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000.opt	(.../branches/gcc-6-branch)
+@@ -142,11 +142,11 @@
+ 
+ maltivec=le
+ Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
+-Generate Altivec instructions using little-endian element order.
++Generate AltiVec instructions using little-endian element order.
+ 
+ maltivec=be
+ Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
+-Generate Altivec instructions using big-endian element order.
++Generate AltiVec instructions using big-endian element order.
+ 
+ mhard-dfp
+ Target Report Mask(DFP) Var(rs6000_isa_flags)
+@@ -602,7 +602,7 @@
+ Analyze and remove doubleword swaps from VSX computations.
+ 
+ mpower9-fusion
+-Target Report Mask(P9_FUSION) Var(rs6000_isa_flags)
++Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
+ Fuse certain operations together for better performance on power9.
+ 
+ mpower9-misc
+@@ -610,7 +610,7 @@
+ Use/do not use certain scalar instructions added in ISA 3.0.
+ 
+ mpower9-vector
+-Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
++Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
+ Use/do not use vector instructions added in ISA 3.0.
+ 
+ mpower9-dform-scalar
+@@ -622,7 +622,7 @@
+ Use/do not use vector register+offset memory instructions added in ISA 3.0.
+ 
+ mpower9-dform
+-Target Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
++Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
+ Use/do not use register+offset memory instructions added in ISA 3.0.
+ 
+ mpower9-minmax
+@@ -634,7 +634,7 @@
+ Fuse medium/large code model toc references with the memory instruction.
+ 
+ mmodulo
+-Target Report Mask(MODULO) Var(rs6000_isa_flags)
++Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
+ Generate the integer modulo instructions.
+ 
+ mfloat128
+Index: gcc/config/rs6000/rs6000.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000.c	(.../branches/gcc-6-branch)
+@@ -3750,6 +3750,13 @@
+       && !global_options_set.x_flag_ira_loop_pressure)
+     flag_ira_loop_pressure = 1;
+ 
++  /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
++     for tracebacks to be complete but not if any -fasynchronous-unwind-tables
++     options were already specified.  */
++  if (flag_sanitize & SANITIZE_USER_ADDRESS
++      && !global_options_set.x_flag_asynchronous_unwind_tables)
++    flag_asynchronous_unwind_tables = 1;
++
+   /* Set the pointer size.  */
+   if (TARGET_64BIT)
+     {
+@@ -4190,6 +4197,10 @@
+     {
+       if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
+ 	{
++	  /* We prefer to not mention undocumented options in
++	     error messages.  However, if users have managed to select
++	     power9-fusion without selecting power8-fusion, they
++	     already know about undocumented flags.  */
+ 	  error ("-mpower9-fusion requires -mpower8-fusion");
+ 	  rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
+ 	}
+@@ -4237,6 +4248,10 @@
+   /* ISA 3.0 vector instructions include ISA 2.07.  */
+   if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
+     {
++      /* We prefer to not mention undocumented options in
++	 error messages.  However, if users have managed to select
++	 power9-vector without selecting power8-vector, they
++	 already know about undocumented flags.  */
+       if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
+ 	error ("-mpower9-vector requires -mpower8-vector");
+       rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
+@@ -4264,6 +4279,10 @@
+   /* ISA 3.0 D-form instructions require p9-vector and upper-regs.  */
+   if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR) && !TARGET_P9_VECTOR)
+     {
++      /* We prefer to not mention undocumented options in
++	 error messages.  However, if users have managed to select
++	 power9-dform without selecting power9-vector, they
++	 already know about undocumented flags.  */
+       if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
+ 	error ("-mpower9-dform requires -mpower9-vector");
+       rs6000_isa_flags &= ~(OPTION_MASK_P9_DFORM_SCALAR
+@@ -4272,6 +4291,10 @@
+ 
+   if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
+     {
++      /* We prefer to not mention undocumented options in
++	 error messages.  However, if users have managed to select
++	 power9-dform without selecting upper-regs-df, they
++	 already know about undocumented flags.  */
+       if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
+ 	error ("-mpower9-dform requires -mupper-regs-df");
+       rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
+@@ -14157,6 +14180,8 @@
+     }
+   else if (icode == CODE_FOR_vsx_xxpermdi_v2df
+            || icode == CODE_FOR_vsx_xxpermdi_v2di
++           || icode == CODE_FOR_vsx_xxpermdi_v2df_be
++           || icode == CODE_FOR_vsx_xxpermdi_v2di_be
+            || icode == CODE_FOR_vsx_xxsldwi_v16qi
+            || icode == CODE_FOR_vsx_xxsldwi_v8hi
+            || icode == CODE_FOR_vsx_xxsldwi_v4si
+@@ -15412,13 +15437,13 @@
+   else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
+     error ("Builtin function %s requires the -mpower8-vector option", name);
+   else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
+-    error ("Builtin function %s requires the -mpower9-vector option", name);
++    error ("Builtin function %s requires the -mcpu=power9 option", name);
+   else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
+ 	   == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
+-    error ("Builtin function %s requires the -mpower9-misc and"
++    error ("Builtin function %s requires the -mcpu=power9 and"
+ 	   " -m64 options", name);
+   else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
+-    error ("Builtin function %s requires the -mpower9-misc option", name);
++    error ("Builtin function %s requires the -mcpu=power9 option", name);
+   else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
+ 	   == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
+     error ("Builtin function %s requires the -mhard-float and"
+@@ -17057,6 +17082,7 @@
+       break;
+ 
+       /* unsigned args, signed return.  */
++    case VSX_BUILTIN_XVCVUXDSP:
+     case VSX_BUILTIN_XVCVUXDDP_UNS:
+     case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
+       h.uns_p[1] = 1;
+@@ -23084,9 +23110,7 @@
+   rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest);
+   rtx shift_reg = dest_di;
+ 
+-  gcc_assert (REG_P (dest));
+-  gcc_assert (REG_P (src) || MEM_P (src));
+-  gcc_assert (s_mode == KFmode || s_mode == TFmode);
++  gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64);
+ 
+   if (MEM_P (src))
+     {
+@@ -23098,17 +23122,20 @@
+ 
+   else
+     {
+-      unsigned int r = REGNO (src);
++      unsigned int r = reg_or_subregno (src);
+ 
+-      /* If this is a VSX register, generate the special mfvsrd instruction
+-	 to get it in a GPR.  Until we support SF and DF modes, that will
+-	 always be true.  */
+-      gcc_assert (VSX_REGNO_P (r));
++      if (INT_REGNO_P (r))
++	shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0));
+ 
+-      if (s_mode == KFmode)
+-	emit_insn (gen_signbitkf2_dm2 (dest_di, src));
+       else
+-	emit_insn (gen_signbittf2_dm2 (dest_di, src));
++	{
++	  /* Generate the special mfvsrd instruction to get it in a GPR.  */
++	  gcc_assert (VSX_REGNO_P (r));
++	  if (s_mode == KFmode)
++	    emit_insn (gen_signbitkf2_dm2 (dest_di, src));
++	  else
++	    emit_insn (gen_signbittf2_dm2 (dest_di, src));
++	}
+     }
+ 
+   emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
+@@ -38564,6 +38591,7 @@
+ 	  case UNSPEC_VSX_CVSPDPN:
+ 	    return 0;
+ 	  case UNSPEC_VSPLT_DIRECT:
++	  case UNSPEC_VSX_XXSPLTD:
+ 	    *special = SH_SPLAT;
+ 	    return 1;
+ 	  case UNSPEC_REDUC_PLUS:
+@@ -38634,6 +38662,12 @@
+     {
+       if (GET_CODE (body) == SET)
+ 	{
++	  rtx rhs = SET_SRC (body);
++	  /* Even without a swap, the RHS might be a vec_select for, say,
++	     a byte-reversing load.  */
++	  if (GET_CODE (rhs) != MEM)
++	    return 0;
++
+ 	  *special = SH_NOSWAP_LD;
+ 	  return 1;
+ 	}
+@@ -38645,6 +38679,12 @@
+     {
+       if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) != UNSPEC)
+ 	{
++	  rtx lhs = SET_DEST (body);
++	  /* Even without a swap, the LHS might be a vec_select for, say,
++	     a byte-reversing store.  */
++	  if (GET_CODE (lhs) != MEM)
++	    return 0;
++
+ 	  *special = SH_NOSWAP_ST;
+ 	  return 1;
+ 	}
+Index: gcc/config/rs6000/vsx.md
+===================================================================
+--- a/src/gcc/config/rs6000/vsx.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/vsx.md	(.../branches/gcc-6-branch)
+@@ -1827,8 +1827,8 @@
+   [(set_attr "type" "vecdouble")])
+ 
+ (define_insn "vsx_xvcvsxdsp"
+-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
+-	(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
++  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
++	(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
+ 		     UNSPEC_VSX_CVSXDSP))]
+   "VECTOR_UNIT_VSX_P (V2DFmode)"
+   "xvcvsxdsp %x0,%x1"
+@@ -1835,11 +1835,11 @@
+   [(set_attr "type" "vecfloat")])
+ 
+ (define_insn "vsx_xvcvuxdsp"
+-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
+-	(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
++  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
++	(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
+ 		     UNSPEC_VSX_CVUXDSP))]
+   "VECTOR_UNIT_VSX_P (V2DFmode)"
+-  "xvcvuxwdp %x0,%x1"
++  "xvcvuxdsp %x0,%x1"
+   [(set_attr "type" "vecdouble")])
+ 
+ ;; Convert from 32-bit to 64-bit types
+@@ -2276,6 +2276,38 @@
+ 	  op1 = gen_lowpart (V2DImode, op1);
+ 	}
+     }
++  emit_insn (gen (target, op0, op1, perm0, perm1));
++  DONE;
++})
++
++;; Special version of xxpermdi that retains big-endian semantics.
++(define_expand "vsx_xxpermdi_<mode>_be"
++  [(match_operand:VSX_L 0 "vsx_register_operand" "")
++   (match_operand:VSX_L 1 "vsx_register_operand" "")
++   (match_operand:VSX_L 2 "vsx_register_operand" "")
++   (match_operand:QI 3 "u5bit_cint_operand" "")]
++  "VECTOR_MEM_VSX_P (<MODE>mode)"
++{
++  rtx target = operands[0];
++  rtx op0 = operands[1];
++  rtx op1 = operands[2];
++  int mask = INTVAL (operands[3]);
++  rtx perm0 = GEN_INT ((mask >> 1) & 1);
++  rtx perm1 = GEN_INT ((mask & 1) + 2);
++  rtx (*gen) (rtx, rtx, rtx, rtx, rtx);
++
++  if (<MODE>mode == V2DFmode)
++    gen = gen_vsx_xxpermdi2_v2df_1;
++  else
++    {
++      gen = gen_vsx_xxpermdi2_v2di_1;
++      if (<MODE>mode != V2DImode)
++	{
++	  target = gen_lowpart (V2DImode, target);
++	  op0 = gen_lowpart (V2DImode, op0);
++	  op1 = gen_lowpart (V2DImode, op1);
++	}
++    }
+   /* In little endian mode, vsx_xxpermdi2_<mode>_1 will perform a
+      transformation we don't want; it is necessary for
+      rs6000_expand_vec_perm_const_1 but not for this use.  So we
+Index: gcc/config/rs6000/rs6000.h
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000.h	(.../branches/gcc-6-branch)
+@@ -635,6 +635,7 @@
+ #define MASK_DIRECT_MOVE		OPTION_MASK_DIRECT_MOVE
+ #define MASK_DLMZB			OPTION_MASK_DLMZB
+ #define MASK_EABI			OPTION_MASK_EABI
++#define MASK_FLOAT128			OPTION_MASK_FLOAT128
+ #define MASK_FPRND			OPTION_MASK_FPRND
+ #define MASK_P8_FUSION			OPTION_MASK_P8_FUSION
+ #define MASK_HARD_FLOAT			OPTION_MASK_HARD_FLOAT
+@@ -2718,7 +2719,7 @@
+ #define RS6000_BTM_HARD_FLOAT	MASK_SOFT_FLOAT	/* Hardware floating point.  */
+ #define RS6000_BTM_LDBL128	MASK_MULTIPLE	/* 128-bit long double.  */
+ #define RS6000_BTM_64BIT	MASK_64BIT	/* 64-bit addressing.  */
+-#define RS6000_BTM_FLOAT128	MASK_P9_VECTOR	/* IEEE 128-bit float.  */
++#define RS6000_BTM_FLOAT128	MASK_FLOAT128	/* IEEE 128-bit float.  */
+ 
+ #define RS6000_BTM_COMMON	(RS6000_BTM_ALTIVEC			\
+ 				 | RS6000_BTM_VSX			\
+Index: gcc/config/rs6000/rs6000.md
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000.md	(.../branches/gcc-6-branch)
+@@ -514,9 +514,6 @@
+ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
+ 			       (TF "FLOAT128_VECTOR_P (TFmode)")])
+ 
+-(define_mode_attr Fsignbit	[(KF "wa")
+-				 (TF "wa")])
+-
+ ; SF/DF suffix for traditional floating instructions
+ (define_mode_attr Ftrad		[(SF "s") (DF "")])
+ 
+@@ -3066,8 +3063,8 @@
+    && ! reg_mentioned_p (operands[3], operands[1])
+    && ! reg_mentioned_p (operands[3], operands[2])"
+   [(set (match_dup 0)
+-	(div:GPR (match_dup 1)
+-		 (match_dup 2)))
++	(udiv:GPR (match_dup 1)
++		  (match_dup 2)))
+    (set (match_dup 3)
+ 	(mult:GPR (match_dup 0)
+ 		  (match_dup 2)))
+@@ -4616,7 +4613,7 @@
+ (define_insn_and_split "signbit<mode>2_dm"
+   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
+ 	(unspec:SI
+-	 [(match_operand:SIGNBIT 1 "input_operand" "<Fsignbit>,m,r")]
++	 [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")]
+ 	 UNSPEC_SIGNBIT))]
+   "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
+   "#"
+@@ -4626,15 +4623,32 @@
+   rs6000_split_signbit (operands[0], operands[1]);
+   DONE;
+ }
+- [(set_attr "length" "8,8,12")
++ [(set_attr "length" "8,8,4")
+   (set_attr "type" "mftgpr,load,integer")])
+ 
++(define_insn_and_split "*signbit<mode>2_dm_<su>ext"
++  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
++	(any_extend:DI
++	 (unspec:SI
++	  [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")]
++	  UNSPEC_SIGNBIT)))]
++  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
++  "#"
++  "&& reload_completed"
++  [(const_int 0)]
++{
++  rs6000_split_signbit (operands[0], operands[1]);
++  DONE;
++}
++ [(set_attr "length" "8,8,4")
++  (set_attr "type" "mftgpr,load,integer")])
++
+ ;; MODES_TIEABLE_P doesn't allow DImode to be tied with the various floating
+ ;; point types, which makes normal SUBREG's problematical. Instead use a
+ ;; special pattern to avoid using a normal movdi.
+ (define_insn "signbit<mode>2_dm2"
+   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+-	(unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "<Fsignbit>")
++	(unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa")
+ 		    (const_int 0)]
+ 		   UNSPEC_SIGNBIT))]
+   "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
+@@ -5415,17 +5429,10 @@
+   [(set_attr "length" "12")
+    (set_attr "type" "fp")])
+ 
+-(define_expand "fixuns_trunc<mode>di2"
+-  [(set (match_operand:DI 0 "register_operand" "")
+-	(unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
+-  "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
+-  "")
+-
+-(define_insn "*fixuns_trunc<mode>di2_fctiduz"
++(define_insn "fixuns_trunc<mode>di2"
+   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
+ 	(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
+-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
+-    && TARGET_FCTIDUZ"
++  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCTIDUZ"
+   "@
+    fctiduz %0,%1
+    xscvdpuxds %x0,%x1"
+@@ -7720,7 +7727,7 @@
+   rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
+ 
+   emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
+-  emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
++  emit_insn (gen_vsx_xxpermdi_<mode>_be (tmp, src, src, GEN_INT (3)));
+   emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
+   DONE;
+ }
+Index: gcc/config/rs6000/altivec.h
+===================================================================
+--- a/src/gcc/config/rs6000/altivec.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/altivec.h	(.../branches/gcc-6-branch)
+@@ -327,8 +327,8 @@
+ #define vec_sqrt __builtin_vec_sqrt
+ #define vec_vsx_ld __builtin_vec_vsx_ld
+ #define vec_vsx_st __builtin_vec_vsx_st
+-#define vec_xl __builtin_vec_xl
+-#define vec_xst __builtin_vec_xst
++#define vec_xl __builtin_vec_vsx_ld
++#define vec_xst __builtin_vec_vsx_st
+ 
+ /* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions
+    instead of __builtin_vec_<xxx>  */
+Index: gcc/config/tilepro/tilepro.c
+===================================================================
+--- a/src/gcc/config/tilepro/tilepro.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/tilepro/tilepro.c	(.../branches/gcc-6-branch)
+@@ -3534,8 +3534,11 @@
+   /* Save lr first in its special location because code after this
+      might use the link register as a scratch register.  */
+   if (df_regs_ever_live_p (TILEPRO_LINK_REGNUM) || crtl->calls_eh_return)
+-    FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
+-			   stack_pointer_rtx, stack_pointer_rtx, 0));
++    {
++      FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
++			     stack_pointer_rtx, stack_pointer_rtx, 0));
++      emit_insn (gen_blockage ());
++    }
+ 
+   if (total_size == 0)
+     {
+Index: gcc/config/arm/arm.c
+===================================================================
+--- a/src/gcc/config/arm/arm.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/arm/arm.c	(.../branches/gcc-6-branch)
+@@ -6707,6 +6707,14 @@
+   if (TARGET_VXWORKS_RTP && flag_pic && decl && !targetm.binds_local_p (decl))
+     return false;
+ 
++  /* ??? Cannot tail-call to long calls with APCS frame and VFP, because IP
++     may be used both as target of the call and base register for restoring
++     the VFP registers  */
++  if (TARGET_APCS_FRAME && TARGET_ARM
++      && TARGET_HARD_FLOAT && TARGET_VFP
++      && decl && arm_is_long_call_p (decl))
++    return false;
++
+   /* If we are interworking and the function is not declared static
+      then we can't tail-call it unless we know that it exists in this
+      compilation unit (since it might be a Thumb routine).  */
+@@ -6859,9 +6867,13 @@
+ 	 same segment as the GOT.  Unfortunately, the flexibility of linker
+ 	 scripts means that we can't be sure of that in general, so assume
+ 	 that GOTOFF is never valid on VxWorks.  */
++      /* References to weak symbols cannot be resolved locally: they
++	 may be overridden by a non-weak definition at link time.  */
+       if ((GET_CODE (orig) == LABEL_REF
+-	   || (GET_CODE (orig) == SYMBOL_REF &&
+-	       SYMBOL_REF_LOCAL_P (orig)))
++	   || (GET_CODE (orig) == SYMBOL_REF
++	       && SYMBOL_REF_LOCAL_P (orig)
++	       && (SYMBOL_REF_DECL (orig)
++		   ? !DECL_WEAK (SYMBOL_REF_DECL (orig)) : 1)))
+ 	  && NEED_GOT_RELOC
+ 	  && arm_pic_data_is_text_relative)
+ 	insn = arm_pic_static_addr (orig, reg);
+@@ -22687,8 +22699,14 @@
+ 	{
+ 	  /* See legitimize_pic_address for an explanation of the
+ 	     TARGET_VXWORKS_RTP check.  */
++	  /* References to weak symbols cannot be resolved locally:
++	     they may be overridden by a non-weak definition at link
++	     time.  */
+ 	  if (!arm_pic_data_is_text_relative
+-	      || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
++	      || (GET_CODE (x) == SYMBOL_REF
++		  && (!SYMBOL_REF_LOCAL_P (x)
++		      || (SYMBOL_REF_DECL (x)
++			  ? DECL_WEAK (SYMBOL_REF_DECL (x)) : 0))))
+ 	    fputs ("(GOT)", asm_out_file);
+ 	  else
+ 	    fputs ("(GOTOFF)", asm_out_file);
+Index: gcc/config/arm/neon.md
+===================================================================
+--- a/src/gcc/config/arm/neon.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/arm/neon.md	(.../branches/gcc-6-branch)
+@@ -1045,12 +1045,12 @@
+ )
+ 
+ (define_insn_and_split "ashldi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand"	    "= w, w,?&r,?r, ?w,w")
+-	(ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r, 0w,w")
+-		   (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,rUm,i")))
+-   (clobber (match_scratch:SI 3				    "= X, X,?&r, X,  X,X"))
+-   (clobber (match_scratch:SI 4				    "= X, X,?&r, X,  X,X"))
+-   (clobber (match_scratch:DI 5				    "=&w, X,  X, X, &w,X"))
++  [(set (match_operand:DI 0 "s_register_operand"	    "= w, w,?&r,?r,?&r, ?w,w")
++	(ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r, 0w,w")
++		   (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,  i,rUm,i")))
++   (clobber (match_scratch:SI 3				    "= X, X,?&r, X,  X,  X,X"))
++   (clobber (match_scratch:SI 4				    "= X, X,?&r, X,  X,  X,X"))
++   (clobber (match_scratch:DI 5				    "=&w, X,  X, X,  X, &w,X"))
+    (clobber (reg:CC_C CC_REGNUM))]
+   "TARGET_NEON"
+   "#"
+@@ -1082,9 +1082,11 @@
+       }
+     else
+       {
+-	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
+-	    && (!reg_overlap_mentioned_p (operands[0], operands[1])
+-		|| REGNO (operands[0]) == REGNO (operands[1])))
++	/* The shift expanders support either full overlap or no overlap.  */
++	gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
++		    || REGNO (operands[0]) == REGNO (operands[1]));
++
++	if (operands[2] == CONST1_RTX (SImode))
+ 	  /* This clobbers CC.  */
+ 	  emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
+ 	else
+@@ -1093,8 +1095,8 @@
+       }
+     DONE;
+   }"
+-  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+-   (set_attr "opt" "*,*,speed,speed,*,*")
++  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
++   (set_attr "opt" "*,*,speed,speed,speed,*,*")
+    (set_attr "type" "multiple")]
+ )
+ 
+@@ -1143,12 +1145,12 @@
+ ;; ashrdi3_neon
+ ;; lshrdi3_neon
+ (define_insn_and_split "<shift>di3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand"	     "= w, w,?&r,?r,?w,?w")
+-	(RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
+-		    (match_operand:SI 2 "reg_or_int_operand" "  r, i,  r, i, r, i")))
+-   (clobber (match_scratch:SI 3				     "=2r, X, &r, X,2r, X"))
+-   (clobber (match_scratch:SI 4				     "= X, X, &r, X, X, X"))
+-   (clobber (match_scratch:DI 5				     "=&w, X,  X, X,&w, X"))
++  [(set (match_operand:DI 0 "s_register_operand"	     "= w, w,?&r,?r,?&r,?w,?w")
++	(RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r,0w, w")
++		    (match_operand:SI 2 "reg_or_int_operand" "  r, i,  r, i,  i, r, i")))
++   (clobber (match_scratch:SI 3				     "=2r, X, &r, X,  X,2r, X"))
++   (clobber (match_scratch:SI 4				     "= X, X, &r, X,  X, X, X"))
++   (clobber (match_scratch:DI 5				     "=&w, X,  X, X, X,&w, X"))
+    (clobber (reg:CC CC_REGNUM))]
+   "TARGET_NEON"
+   "#"
+@@ -1184,9 +1186,11 @@
+       }
+     else
+       {
+-	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
+-	    && (!reg_overlap_mentioned_p (operands[0], operands[1])
+-		|| REGNO (operands[0]) == REGNO (operands[1])))
++	/* The shift expanders support either full overlap or no overlap.  */
++	gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
++		    || REGNO (operands[0]) == REGNO (operands[1]));
++
++	if (operands[2] == CONST1_RTX (SImode))
+ 	  /* This clobbers CC.  */
+ 	  emit_insn (gen_arm_<shift>di3_1bit (operands[0], operands[1]));
+ 	else
+@@ -1197,8 +1201,8 @@
+ 
+     DONE;
+   }"
+-  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+-   (set_attr "opt" "*,*,speed,speed,*,*")
++  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
++   (set_attr "opt" "*,*,speed,speed,speed,*,*")
+    (set_attr "type" "multiple")]
+ )
+ 
+Index: gcc/config/pa/pa-64.h
+===================================================================
+--- a/src/gcc/config/pa/pa-64.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/pa/pa-64.h	(.../branches/gcc-6-branch)
+@@ -83,7 +83,10 @@
+    arguments are padded down when BYTES_BIG_ENDIAN is true.  We don't
+    want aggregates padded down.  */
+ 
+-#define PAD_VARARGS_DOWN (!AGGREGATE_TYPE_P (type))
++#define PAD_VARARGS_DOWN \
++  (!AGGREGATE_TYPE_P (type) \
++   && TREE_CODE (type) != COMPLEX_TYPE \
++   && TREE_CODE (type) != VECTOR_TYPE)
+ 
+ /* In the PA architecture, it is not possible to directly move data
+    between GENERAL_REGS and FP_REGS.  On the 32-bit port, we use the
+Index: gcc/params.def
+===================================================================
+--- a/src/gcc/params.def	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/params.def	(.../branches/gcc-6-branch)
+@@ -1191,7 +1191,7 @@
+ 	  "max-ssa-name-query-depth",
+ 	  "Maximum recursion depth allowed when querying a property of an"
+ 	  " SSA name.",
+-	  3, 1, 0)
++	  3, 1, 10)
+ 
+ DEFPARAM (PARAM_MAX_RTL_IF_CONVERSION_INSNS,
+ 	  "max-rtl-if-conversion-insns",
+Index: gcc/lto-streamer.h
+===================================================================
+--- a/src/gcc/lto-streamer.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/lto-streamer.h	(.../branches/gcc-6-branch)
+@@ -129,7 +129,7 @@
+      form followed by the data for the string.  */
+ 
+ #define LTO_major_version 5
+-#define LTO_minor_version 1
++#define LTO_minor_version 2
+ 
+ typedef unsigned char	lto_decl_flags_t;
+ 
+Index: gcc
+===================================================================
+--- a/src/gcc	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc	(.../branches/gcc-6-branch)
+
+Property changes on: gcc
+___________________________________________________________________
+Modified: svn:mergeinfo
+## -0,0 +0,1 ##
+   Merged /trunk/gcc:r243528,243962
+Index: libgo/runtime/go-unsafe-pointer.c
+===================================================================
+--- a/src/libgo/runtime/go-unsafe-pointer.c	(.../tags/gcc_6_3_0_release)
++++ b/src/libgo/runtime/go-unsafe-pointer.c	(.../branches/gcc-6-branch)
+@@ -36,7 +36,8 @@
+   sizeof REFLECTION - 1
+ };
+ 
+-const uintptr unsafe_Pointer_gc[] = {sizeof(void*), GC_APTR, 0, GC_END};
++const uintptr unsafe_Pointer_gc[] __attribute__((aligned(4))) =
++  {sizeof(void*), GC_APTR, 0, GC_END};
+ 
+ const struct __go_type_descriptor unsafe_Pointer =
+ {
+Index: libgo/runtime/runtime.h
+===================================================================
+--- a/src/libgo/runtime/runtime.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libgo/runtime/runtime.h	(.../branches/gcc-6-branch)
+@@ -154,7 +154,7 @@
+ 	// Futex-based impl treats it as uint32 key,
+ 	// while sema-based impl as M* waitm.
+ 	// Used to be a union, but unions break precise GC.
+-	uintptr	key;
++	uintptr	key __attribute__((aligned(4)));
+ };
+ struct	Note
+ {
+@@ -161,7 +161,7 @@
+ 	// Futex-based impl treats it as uint32 key,
+ 	// while sema-based impl as M* waitm.
+ 	// Used to be a union, but unions break precise GC.
+-	uintptr	key;
++	uintptr	key __attribute__((aligned(4)));
+ };
+ struct String
+ {
+@@ -431,7 +431,7 @@
+ 					// otherwise parfor may return while other threads are still working
+ 	ParForThread *thr;		// array of thread descriptors
+ 	// stats
+-	uint64 nsteal;
++	uint64 nsteal __attribute__((aligned(8))); // force alignment for m68k
+ 	uint64 nstealcnt;
+ 	uint64 nprocyield;
+ 	uint64 nosyield;
+Index: libgo/runtime/parfor.c
+===================================================================
+--- a/src/libgo/runtime/parfor.c	(.../tags/gcc_6_3_0_release)
++++ b/src/libgo/runtime/parfor.c	(.../branches/gcc-6-branch)
+@@ -10,7 +10,7 @@
+ struct ParForThread
+ {
+ 	// the thread's iteration space [32lsb, 32msb)
+-	uint64 pos;
++	uint64 pos __attribute__((aligned(8)));
+ 	// stats
+ 	uint64 nsteal;
+ 	uint64 nstealcnt;
+Index: libgfortran/configure
+===================================================================
+--- a/src/libgfortran/configure	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/configure	(.../branches/gcc-6-branch)
+@@ -10308,7 +10308,7 @@
+ 	if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then
+ 	  export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+ 	else
+-	  export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
++	  export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "L")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+ 	fi
+ 	aix_use_runtimelinking=no
+ 
+@@ -14157,7 +14157,7 @@
+ 	if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then
+ 	  export_symbols_cmds_FC='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+ 	else
+-	  export_symbols_cmds_FC='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
++	  export_symbols_cmds_FC='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "L")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+ 	fi
+ 	aix_use_runtimelinking=no
+ 
+@@ -25762,6 +25762,43 @@
+ fi
+ 
+ 
++# Check if _SOFT_FLOAT is defined
++
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for _SOFT_FLOAT defined" >&5
++$as_echo_n "checking for _SOFT_FLOAT defined... " >&6; }
++if test "${ac_cv_defined__SOFT_FLOAT+set}" = set; then :
++  $as_echo_n "(cached) " >&6
++else
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++int
++main ()
++{
++
++  #ifdef _SOFT_FLOAT
++  int ok;
++  #else
++  choke me
++  #endif
++
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_compile "$LINENO"; then :
++  ac_cv_defined__SOFT_FLOAT=yes
++else
++  ac_cv_defined__SOFT_FLOAT=no
++fi
++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_defined__SOFT_FLOAT" >&5
++$as_echo "$ac_cv_defined__SOFT_FLOAT" >&6; }
++if test $ac_cv_defined__SOFT_FLOAT != "no"; then :
++  have_soft_float=yes
++fi
++
+ # Runs configure.host to set up necessary host-dependent shell variables.
+ # We then display a message about it, and propagate them through the
+ # build chain.
+Index: libgfortran/intrinsics/c99_functions.c
+===================================================================
+--- a/src/libgfortran/intrinsics/c99_functions.c	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/intrinsics/c99_functions.c	(.../branches/gcc-6-branch)
+@@ -913,7 +913,7 @@
+ }
+ #endif
+ 
+-#if !defined(HAVE_CEXPL) && defined(HAVE_COSL) && defined(HAVE_SINL) && defined(EXPL)
++#if !defined(HAVE_CEXPL) && defined(HAVE_COSL) && defined(HAVE_SINL) && defined(HAVE_EXPL)
+ #define HAVE_CEXPL 1
+ long double complex cexpl (long double complex z);
+ 
+Index: libgfortran/caf/single.c
+===================================================================
+--- a/src/libgfortran/caf/single.c	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/caf/single.c	(.../branches/gcc-6-branch)
+@@ -101,9 +101,12 @@
+   void *local;
+ 
+   if (type == CAF_REGTYPE_LOCK_STATIC || type == CAF_REGTYPE_LOCK_ALLOC
+-      || type == CAF_REGTYPE_CRITICAL || type == CAF_REGTYPE_EVENT_STATIC
+-      || type == CAF_REGTYPE_EVENT_ALLOC)
+-    local = calloc (size, sizeof (bool));
++      || type == CAF_REGTYPE_CRITICAL)
++     local = calloc (size, sizeof (bool));
++  else if (type == CAF_REGTYPE_EVENT_STATIC || type == CAF_REGTYPE_EVENT_ALLOC)
++    /* In the event_(wait|post) function the counter for events is a uint32,
++       so better allocate enough memory here.  */
++    local = calloc (size, sizeof (uint32_t));
+   else
+     local = malloc (size);
+   *token = malloc (sizeof (single_token_t));
+Index: libgfortran/configure.host
+===================================================================
+--- a/src/libgfortran/configure.host	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/configure.host	(.../branches/gcc-6-branch)
+@@ -40,7 +40,11 @@
+ # the x86 denormal exception.
+ case "${host_cpu}" in
+   i?86 | x86_64)
+-    fpu_host='fpu-387'
++    if test "x${have_soft_float}" = "xyes"; then
++      fpu_host='fpu-generic'
++    else
++      fpu_host='fpu-387'
++    fi
+     ieee_support='yes'
+     ;;
+ esac
+Index: libgfortran/configure.ac
+===================================================================
+--- a/src/libgfortran/configure.ac	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/configure.ac	(.../branches/gcc-6-branch)
+@@ -551,6 +551,9 @@
+ AC_CHECK_FUNC([fp_trap],[have_fp_trap=yes AC_DEFINE([HAVE_FP_TRAP],[1],[fp_trap is present])])
+ AC_CHECK_FUNC([fp_enable],[have_fp_enable=yes AC_DEFINE([HAVE_FP_ENABLE],[1],[fp_enable is present])])
+ 
++# Check if _SOFT_FLOAT is defined
++AC_CHECK_DEFINE([_SOFT_FLOAT],[have_soft_float=yes])
++
+ # Runs configure.host to set up necessary host-dependent shell variables.
+ # We then display a message about it, and propagate them through the
+ # build chain.
+Index: libgfortran/ChangeLog
+===================================================================
+--- a/src/libgfortran/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,18 @@
++2017-01-31  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/79305
++	* c99_protos.h: Spell HAVE_EXPL correctly.
++	* intrinsics/c99_functions.c: Ditto.
++
++2017-01-24  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/78478
++	* acinclude.m4: Include ../config/ax_check_define.m4
++	* configure.ac: Check if _SOFT_FLOAT is defined.
++	* configure.host (i?86 | x86_64): Use fpu-generic when
++	have_soft_float is set.
++	* configure: Regenerate.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+@@ -13,7 +28,7 @@
+ 
+ 	Backport from trunk
+ 	PR libgfortran/77707
+-	io/transfer.c (next_record): Flush before calculating next_record.
++	* io/transfer.c (next_record): Flush before calculating next_record.
+ 	Correctly calculate.
+ 
+ 2016-09-28  Steven G. Kargl  <kargl@gcc.gnu.org>
+@@ -20,7 +35,7 @@
+ 
+ 	Backport from trunk
+ 	PR fortran/77507
+- 	* ieee/ieee_arithmetic.F90 (IEEE_VALUE_4,IEEE_VALUE_8,IEEE_VALULE_10,
++	* ieee/ieee_arithmetic.F90 (IEEE_VALUE_4,IEEE_VALUE_8,IEEE_VALULE_10,
+ 	IEEE_VALUE_16):  Use correct keyword.
+ 
+ 2016-08-22  Release Manager
+@@ -82,9 +97,10 @@
+ 	(read_logical): If '!' bang encountered when not in namelist mode got
+ 	bad_logical to give an error. (read_integer): Likewise reject '!'.
+ 	(read_character): Remove condition testing c = '!' which is now inside
+-	the is_separator macro. (parse_real): Reject '!' unless in namelist mode.
+-	(read_complex): Reject '!' unless in namelist mode. (read_real): Likewise
+-	reject '!'. 
++	the is_separator macro. (parse_real): Reject '!' unless in
++	namelist mode.
++	(read_complex): Reject '!' unless in namelist mode.
++	(read_real): Likewise reject '!'.
+ 
+ 2016-02-12  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
+ 
+Index: libgfortran/c99_protos.h
+===================================================================
+--- a/src/libgfortran/c99_protos.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/c99_protos.h	(.../branches/gcc-6-branch)
+@@ -332,7 +332,7 @@
+ extern double complex cexp (double complex);
+ #endif
+ 
+-#if !defined(HAVE_CEXPL) && defined(HAVE_COSL) && defined(HAVE_SINL) && defined(EXPL)
++#if !defined(HAVE_CEXPL) && defined(HAVE_COSL) && defined(HAVE_SINL) && defined(HAVE_EXPL)
+ #define HAVE_CEXPL 1
+ extern long double complex cexpl (long double complex);
+ #endif
+Index: libgfortran/acinclude.m4
+===================================================================
+--- a/src/libgfortran/acinclude.m4	(.../tags/gcc_6_3_0_release)
++++ b/src/libgfortran/acinclude.m4	(.../branches/gcc-6-branch)
+@@ -1,6 +1,7 @@
+ m4_include(../config/acx.m4)
+ m4_include(../config/no-executables.m4)
+ m4_include(../config/math.m4)
++m4_include(../config/ax_check_define.m4)
+ 
+ dnl Check that we have a working GNU Fortran compiler
+ AC_DEFUN([LIBGFOR_WORKING_GFORTRAN], [
+Index: fixincludes/ChangeLog
+===================================================================
+--- a/src/fixincludes/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/fixincludes/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,16 @@
++2017-01-30  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	Backport from mainline
++	2017-01-13  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	PR libstdc++/78979
++	* inclhack.def (solaris_gets_c11, solaris_gets_cxx14)
++	(solaris_std_gets_cxx14, solaris_stdlib_noreturn): New fixes.
++	* fixincl.x: Regenerate.
++	* tests/base/iso/stdio_iso.h [SOLARIS_GETS_C11_CHECK,
++	SOLARIS_GETS_CXX14_CHECK, SOLARIS_STD_GETS_CXX14_CHECK,
++	SOLARIS_STDLIB_NORETURN_CHECK]: New tests.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: fixincludes/tests/base/stdio.h
+===================================================================
+--- a/src/fixincludes/tests/base/stdio.h	(.../tags/gcc_6_3_0_release)
++++ b/src/fixincludes/tests/base/stdio.h	(.../branches/gcc-6-branch)
+@@ -90,6 +90,13 @@
+ #endif  /* SOLARIS_STD___FILBUF_CHECK */
+ 
+ 
++#if defined( SOLARIS_STD_GETS_CXX14_CHECK )
++#if __cplusplus < 201402L
++using std::gets;
++#endif
++#endif  /* SOLARIS_STD_GETS_CXX14_CHECK */
++
++
+ #if defined( STDIO_STDARG_H_CHECK )
+ 
+ #endif  /* STDIO_STDARG_H_CHECK */
+Index: fixincludes/tests/base/iso/stdio_iso.h
+===================================================================
+--- a/src/fixincludes/tests/base/iso/stdio_iso.h	(.../tags/gcc_6_3_0_release)
++++ b/src/fixincludes/tests/base/iso/stdio_iso.h	(.../branches/gcc-6-branch)
+@@ -12,3 +12,16 @@
+ #if defined( SOLARIS_GETC_STRICT_STDC_CHECK )
+ #if	!defined(_REENTRANT) && !defined(_LP64) && (!defined(_STRICT_STDC) || (__cplusplus >= 199711L))
+ #endif  /* SOLARIS_GETC_STRICT_STDC_CHECK */
++
++
++#if defined( SOLARIS_GETS_C11_CHECK )
++#if __STDC_VERSION__ < 201112L && __cplusplus < 201402L
++extern char	*gets(char *) __attribute__((__deprecated__));
++#endif
++#endif  /* SOLARIS_GETS_C11_CHECK */
++
++
++#if defined( SOLARIS_GETS_CXX14_CHECK )
++#if __STDC_VERSION__ < 201112L && __cplusplus < 201402L
++extern char	*gets(char *) __ATTR_DEPRECATED;
++#endif  /* SOLARIS_GETS_CXX14_CHECK */
+Index: fixincludes/tests/base/iso/stdlib_c99.h
+===================================================================
+--- a/src/fixincludes/tests/base/iso/stdlib_c99.h	(.../tags/gcc_6_3_0_release)
++++ b/src/fixincludes/tests/base/iso/stdlib_c99.h	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++/*  DO NOT EDIT THIS FILE.
++
++    It has been auto-edited by fixincludes from:
++
++	"fixinc/tests/inc/iso/stdlib_c99.h"
++
++    This had to be done to correct non-standard usages in the
++    original, manufacturer supplied header file.  */
++
++
++
++#if defined( SOLARIS_STDLIB_NORETURN_CHECK )
++extern void quick_exit(int) __attribute__((__noreturn__));
++#endif  /* SOLARIS_STDLIB_NORETURN_CHECK */
+Index: fixincludes/fixincl.x
+===================================================================
+--- a/src/fixincludes/fixincl.x	(.../tags/gcc_6_3_0_release)
++++ b/src/fixincludes/fixincl.x	(.../branches/gcc-6-branch)
+@@ -2,11 +2,11 @@
+  * 
+  * DO NOT EDIT THIS FILE   (fixincl.x)
+  * 
+- * It has been AutoGen-ed  November 18, 2016 at 12:35:01 PM by AutoGen 5.16.2
++ * It has been AutoGen-ed  January  5, 2017 at 06:03:22 PM by AutoGen 5.16.2
+  * From the definitions    inclhack.def
+  * and the template file   fixincl
+  */
+-/* DO NOT SVN-MERGE THIS FILE, EITHER Fri Nov 18 12:35:01  2016
++/* DO NOT SVN-MERGE THIS FILE, EITHER Thu Jan  5 18:03:22 CET 2017
+  *
+  * You must regenerate it.  Use the ./genfixes script.
+  *
+@@ -15,7 +15,7 @@
+  * certain ANSI-incompatible system header files which are fixed to work
+  * correctly with ANSI C and placed in a directory that GNU C will search.
+  *
+- * This file contains 236 fixup descriptions.
++ * This file contains 240 fixup descriptions.
+  *
+  * See README for more information.
+  *
+@@ -6824,6 +6824,84 @@
+ 
+ /* * * * * * * * * * * * * * * * * * * * * * * * * *
+  *
++ *  Description of Solaris_Gets_C11 fix
++ */
++tSCC zSolaris_Gets_C11Name[] =
++     "solaris_gets_c11";
++
++/*
++ *  File name selection pattern
++ */
++tSCC zSolaris_Gets_C11List[] =
++  "iso/stdio_iso.h\0";
++/*
++ *  Machine/OS name selection pattern
++ */
++tSCC* apzSolaris_Gets_C11Machs[] = {
++        "*-*-solaris2*",
++        (const char*)NULL };
++
++/*
++ *  content selection pattern - do fix if pattern found
++ */
++tSCC zSolaris_Gets_C11Select0[] =
++       "(extern char[ \t]*\\*gets\\(char \\*\\));";
++
++#define    SOLARIS_GETS_C11_TEST_CT  1
++static tTestDesc aSolaris_Gets_C11Tests[] = {
++  { TT_EGREP,    zSolaris_Gets_C11Select0, (regex_t*)NULL }, };
++
++/*
++ *  Fix Command Arguments for Solaris_Gets_C11
++ */
++static const char* apzSolaris_Gets_C11Patch[] = {
++    "format",
++    "#if __STDC_VERSION__ < 201112L && __cplusplus < 201402L\n\
++%1 __attribute__((__deprecated__));\n\
++#endif",
++    (char*)NULL };
++
++/* * * * * * * * * * * * * * * * * * * * * * * * * *
++ *
++ *  Description of Solaris_Gets_Cxx14 fix
++ */
++tSCC zSolaris_Gets_Cxx14Name[] =
++     "solaris_gets_cxx14";
++
++/*
++ *  File name selection pattern
++ */
++tSCC zSolaris_Gets_Cxx14List[] =
++  "iso/stdio_iso.h\0";
++/*
++ *  Machine/OS name selection pattern
++ */
++tSCC* apzSolaris_Gets_Cxx14Machs[] = {
++        "*-*-solaris2*",
++        (const char*)NULL };
++
++/*
++ *  content selection pattern - do fix if pattern found
++ */
++tSCC zSolaris_Gets_Cxx14Select0[] =
++       "(#if __STDC_VERSION__ < 201112L)\n\
++(extern char\t\\*gets\\(char \\*\\) __ATTR_DEPRECATED;)";
++
++#define    SOLARIS_GETS_CXX14_TEST_CT  1
++static tTestDesc aSolaris_Gets_Cxx14Tests[] = {
++  { TT_EGREP,    zSolaris_Gets_Cxx14Select0, (regex_t*)NULL }, };
++
++/*
++ *  Fix Command Arguments for Solaris_Gets_Cxx14
++ */
++static const char* apzSolaris_Gets_Cxx14Patch[] = {
++    "format",
++    "%1 && __cplusplus < 201402L\n\
++%2",
++    (char*)NULL };
++
++/* * * * * * * * * * * * * * * * * * * * * * * * * *
++ *
+  *  Description of Solaris_Int_Const fix
+  */
+ tSCC zSolaris_Int_ConstName[] =
+@@ -7576,6 +7654,45 @@
+ 
+ /* * * * * * * * * * * * * * * * * * * * * * * * * *
+  *
++ *  Description of Solaris_Std_Gets_Cxx14 fix
++ */
++tSCC zSolaris_Std_Gets_Cxx14Name[] =
++     "solaris_std_gets_cxx14";
++
++/*
++ *  File name selection pattern
++ */
++tSCC zSolaris_Std_Gets_Cxx14List[] =
++  "stdio.h\0";
++/*
++ *  Machine/OS name selection pattern
++ */
++tSCC* apzSolaris_Std_Gets_Cxx14Machs[] = {
++        "*-*-solaris2*",
++        (const char*)NULL };
++
++/*
++ *  content selection pattern - do fix if pattern found
++ */
++tSCC zSolaris_Std_Gets_Cxx14Select0[] =
++       "using std::gets;";
++
++#define    SOLARIS_STD_GETS_CXX14_TEST_CT  1
++static tTestDesc aSolaris_Std_Gets_Cxx14Tests[] = {
++  { TT_EGREP,    zSolaris_Std_Gets_Cxx14Select0, (regex_t*)NULL }, };
++
++/*
++ *  Fix Command Arguments for Solaris_Std_Gets_Cxx14
++ */
++static const char* apzSolaris_Std_Gets_Cxx14Patch[] = {
++    "format",
++    "#if __cplusplus < 201402L\n\
++%0\n\
++#endif",
++    (char*)NULL };
++
++/* * * * * * * * * * * * * * * * * * * * * * * * * *
++ *
+  *  Description of Solaris_Stdio_Tag fix
+  */
+ tSCC zSolaris_Stdio_TagName[] =
+@@ -7617,6 +7734,43 @@
+ 
+ /* * * * * * * * * * * * * * * * * * * * * * * * * *
+  *
++ *  Description of Solaris_Stdlib_Noreturn fix
++ */
++tSCC zSolaris_Stdlib_NoreturnName[] =
++     "solaris_stdlib_noreturn";
++
++/*
++ *  File name selection pattern
++ */
++tSCC zSolaris_Stdlib_NoreturnList[] =
++  "iso/stdlib_c99.h\0";
++/*
++ *  Machine/OS name selection pattern
++ */
++tSCC* apzSolaris_Stdlib_NoreturnMachs[] = {
++        "*-*-solaris2*",
++        (const char*)NULL };
++
++/*
++ *  content selection pattern - do fix if pattern found
++ */
++tSCC zSolaris_Stdlib_NoreturnSelect0[] =
++       "(extern) _Noreturn (void quick_exit\\(int\\));";
++
++#define    SOLARIS_STDLIB_NORETURN_TEST_CT  1
++static tTestDesc aSolaris_Stdlib_NoreturnTests[] = {
++  { TT_EGREP,    zSolaris_Stdlib_NoreturnSelect0, (regex_t*)NULL }, };
++
++/*
++ *  Fix Command Arguments for Solaris_Stdlib_Noreturn
++ */
++static const char* apzSolaris_Stdlib_NoreturnPatch[] = {
++    "format",
++    "%1 %2 __attribute__((__noreturn__));",
++    (char*)NULL };
++
++/* * * * * * * * * * * * * * * * * * * * * * * * * *
++ *
+  *  Description of Statsswtch fix
+  */
+ tSCC zStatsswtchName[] =
+@@ -9664,9 +9818,9 @@
+  *
+  *  List of all fixes
+  */
+-#define REGEX_COUNT          272
++#define REGEX_COUNT          276
+ #define MACH_LIST_SIZE_LIMIT 187
+-#define FIX_COUNT            236
++#define FIX_COUNT            240
+ 
+ /*
+  *  Enumerate the fixes
+@@ -9837,6 +9991,8 @@
+     SOLARIS_COMPLEX_CXX_FIXIDX,
+     SOLARIS_CXX_LINKAGE_FIXIDX,
+     SOLARIS_GETC_STRICT_STDC_FIXIDX,
++    SOLARIS_GETS_C11_FIXIDX,
++    SOLARIS_GETS_CXX14_FIXIDX,
+     SOLARIS_INT_CONST_FIXIDX,
+     SOLARIS_INT_LIMITS_1_FIXIDX,
+     SOLARIS_INT_LIMITS_2_FIXIDX,
+@@ -9855,7 +10011,9 @@
+     SOLARIS_POW_INT_OVERLOAD_FIXIDX,
+     SOLARIS_RWLOCK_INIT_1_FIXIDX,
+     SOLARIS_STD___FILBUF_FIXIDX,
++    SOLARIS_STD_GETS_CXX14_FIXIDX,
+     SOLARIS_STDIO_TAG_FIXIDX,
++    SOLARIS_STDLIB_NORETURN_FIXIDX,
+     STATSSWTCH_FIXIDX,
+     STDIO_STDARG_H_FIXIDX,
+     STDIO_VA_LIST_FIXIDX,
+@@ -10736,6 +10894,16 @@
+      SOLARIS_GETC_STRICT_STDC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+      aSolaris_Getc_Strict_StdcTests,   apzSolaris_Getc_Strict_StdcPatch, 0 },
+ 
++  {  zSolaris_Gets_C11Name,    zSolaris_Gets_C11List,
++     apzSolaris_Gets_C11Machs,
++     SOLARIS_GETS_C11_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
++     aSolaris_Gets_C11Tests,   apzSolaris_Gets_C11Patch, 0 },
++
++  {  zSolaris_Gets_Cxx14Name,    zSolaris_Gets_Cxx14List,
++     apzSolaris_Gets_Cxx14Machs,
++     SOLARIS_GETS_CXX14_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
++     aSolaris_Gets_Cxx14Tests,   apzSolaris_Gets_Cxx14Patch, 0 },
++
+   {  zSolaris_Int_ConstName,    zSolaris_Int_ConstList,
+      apzSolaris_Int_ConstMachs,
+      SOLARIS_INT_CONST_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+@@ -10826,11 +10994,21 @@
+      SOLARIS_STD___FILBUF_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+      aSolaris_Std___FilbufTests,   apzSolaris_Std___FilbufPatch, 0 },
+ 
++  {  zSolaris_Std_Gets_Cxx14Name,    zSolaris_Std_Gets_Cxx14List,
++     apzSolaris_Std_Gets_Cxx14Machs,
++     SOLARIS_STD_GETS_CXX14_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
++     aSolaris_Std_Gets_Cxx14Tests,   apzSolaris_Std_Gets_Cxx14Patch, 0 },
++
+   {  zSolaris_Stdio_TagName,    zSolaris_Stdio_TagList,
+      apzSolaris_Stdio_TagMachs,
+      SOLARIS_STDIO_TAG_TEST_CT, FD_MACH_ONLY,
+      aSolaris_Stdio_TagTests,   apzSolaris_Stdio_TagPatch, 0 },
+ 
++  {  zSolaris_Stdlib_NoreturnName,    zSolaris_Stdlib_NoreturnList,
++     apzSolaris_Stdlib_NoreturnMachs,
++     SOLARIS_STDLIB_NORETURN_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
++     aSolaris_Stdlib_NoreturnTests,   apzSolaris_Stdlib_NoreturnPatch, 0 },
++
+   {  zStatsswtchName,    zStatsswtchList,
+      apzStatsswtchMachs,
+      STATSSWTCH_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+Index: fixincludes/inclhack.def
+===================================================================
+--- a/src/fixincludes/inclhack.def	(.../tags/gcc_6_3_0_release)
++++ b/src/fixincludes/inclhack.def	(.../branches/gcc-6-branch)
+@@ -3482,6 +3482,43 @@
+ };
+ 
+ /*
++ *  Solaris <iso/stdio_iso.h> should deprecate gets before C11.
++ */
++fix = {
++    hackname  = solaris_gets_c11;
++    mach      = "*-*-solaris2*";
++    files     = "iso/stdio_iso.h";
++    select    = "(extern char[ \t]*\\*gets\\(char \\*\\));";
++
++    c_fix     = format;
++    c_fix_arg = "#if __STDC_VERSION__ < 201112L && __cplusplus < 201402L\n"
++    		"%1 __attribute__((__deprecated__));\n"
++		"#endif";
++
++    test_text = "extern char	*gets(char *);";
++};
++
++/*
++ *  Solaris <iso/stdio_iso.h> shouldn't declare gets for C++14.
++ */
++fix = {
++    hackname  = solaris_gets_cxx14;
++    mach      = "*-*-solaris2*";
++    files     = "iso/stdio_iso.h";
++    select    = <<- _EOSelect_
++(#if __STDC_VERSION__ < 201112L)
++(extern char	\*gets\(char \*\) __ATTR_DEPRECATED;)
++_EOSelect_;
++    c_fix     = format;
++    c_fix_arg = "%1 && __cplusplus < 201402L\n%2";
++
++    test_text = <<- _EOText_
++#if __STDC_VERSION__ < 201112L
++extern char	*gets(char *) __ATTR_DEPRECATED;
++_EOText_;
++};
++
++/*
+  * Sun Solaris 2 has a version of sys/int_const.h that defines
+  * UINT8_C and UINT16_C to unsigned constants.
+  */
+@@ -3871,6 +3908,21 @@
+ };
+ 
+ /*
++ *  Solaris <stdio.h> shouldn't use std::gets for C++14.
++ */
++fix = {
++    hackname  = solaris_std_gets_cxx14;
++    mach      = "*-*-solaris2*";
++    files     = "stdio.h";
++    select    = "using std::gets;";
++
++    c_fix     = format;
++    c_fix_arg = "#if __cplusplus < 201402L\n%0\n#endif";
++
++    test_text = "using std::gets;";
++};
++
++/*
+  * Sun Solaris 8 has what appears to be some gross workaround for
+  * some old version of their c++ compiler.  G++ doesn't want it
+  * either, but doesn't want to be tied to SunPRO version numbers.
+@@ -3889,6 +3941,21 @@
+ };
+ 
+ /*
++ *  Solaris <stdlib.h> shouldn't use _Noreturn, breaks with C++.
++ */
++fix = {
++    hackname  = solaris_stdlib_noreturn;
++    mach      = "*-*-solaris2*";
++    files     = "iso/stdlib_c99.h";
++    select    = "(extern) _Noreturn (void quick_exit\\(int\\));";
++
++    c_fix     = format;
++    c_fix_arg = "%1 %2 __attribute__((__noreturn__));";
++
++    test_text = "extern _Noreturn void quick_exit(int);";
++};
++
++/*
+  *  a missing semi-colon at the end of the statsswtch structure definition.
+  */
+ fix = {
+Index: .
+===================================================================
+--- a/src/.	(.../tags/gcc_6_3_0_release)
++++ b/src/.	(.../branches/gcc-6-branch)
+
+Property changes on: .
+___________________________________________________________________
+Modified: svn:mergeinfo
+## -0,0 +0,1 ##
+   Merged /trunk:r243962,244001
--- gcc-6-6.3.0.orig/debian/patches/sys-auxv-header.diff
+++ gcc-6-6.3.0/debian/patches/sys-auxv-header.diff
@@ -0,0 +1,46 @@
+# DP: Check for the sys/auxv.h header file.
+
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -1093,6 +1093,7 @@ AC_HEADER_TIOCGWINSZ
+ AC_CHECK_HEADERS(limits.h stddef.h string.h strings.h stdlib.h time.h iconv.h \
+ 		 fcntl.h ftw.h unistd.h sys/file.h sys/time.h sys/mman.h \
+ 		 sys/resource.h sys/param.h sys/times.h sys/stat.h \
++		 sys/auxv.h \
+ 		 direct.h malloc.h langinfo.h ldfcn.h locale.h wchar.h)
+ 
+ # Check for thread headers.
+Index: b/src/gcc/config.in
+===================================================================
+--- a/src/gcc/config.in
++++ b/src/gcc/config.in
+@@ -1736,6 +1736,12 @@
+ #endif
+ 
+ 
++/* Define to 1 if you have the <sys/auxv.h> header file. */
++#ifndef USED_FOR_TARGET
++#undef HAVE_SYS_AUXV_H
++#endif
++
++
+ /* Define to 1 if you have the <sys/file.h> header file. */
+ #ifndef USED_FOR_TARGET
+ #undef HAVE_SYS_FILE_H
+Index: b/src/gcc/config/rs6000/driver-rs6000.c
+===================================================================
+--- a/src/gcc/config/rs6000/driver-rs6000.c
++++ b/src/gcc/config/rs6000/driver-rs6000.c
+@@ -31,6 +31,10 @@ along with GCC; see the file COPYING3.
+ # include <link.h>
+ #endif
+ 
++#ifdef HAVE_SYS_AUXV_H
++# include <sys/auxv.h>
++#endif
++
+ #if defined (__APPLE__) || (__FreeBSD__)
+ # include <sys/types.h>
+ # include <sys/sysctl.h>
--- gcc-6-6.3.0.orig/debian/patches/testsuite-glibc-warnings.diff
+++ gcc-6-6.3.0/debian/patches/testsuite-glibc-warnings.diff
@@ -0,0 +1,29 @@
+# DP: fix testcases that triggered -Wunused-result with glibc
+# DP: Author: Steve Beattie <steve.beattie@canonical.com>
+---
+ src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c |    2 +-
+ src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c      |    1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+Index: b/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c
++++ b/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c
+@@ -1,5 +1,5 @@
+ /* { dg-shouldfail "tsan" } */
+-/* { dg-additional-options "-ldl" } */
++/* { dg-additional-options "-Wno-unused-result -ldl" } */
+ 
+ #include <pthread.h>
+ #include <unistd.h>
+Index: b/src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
++++ b/src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-fcilkplus" } */
++/* { dg-options "-fcilkplus -Wno-unused-result" } */
+ 
+ #include <stdlib.h>
+ 
--- gcc-6-6.3.0.orig/debian/patches/testsuite-hardening-format.diff
+++ gcc-6-6.3.0/debian/patches/testsuite-hardening-format.diff
@@ -0,0 +1,371 @@
+#! /bin/sh -e
+
+# All lines beginning with `# DPATCH:' are a description of the patch.
+# DP: Description: use -Wno-format on tests that cannot be adjusted other ways.
+# DP: Author: Kees Cook <kees@ubuntu.com>
+# DP: Ubuntu: https://bugs.launchpad.net/bugs/344502
+
+dir=
+if [ $# -eq 3 -a "$2" = '-d' ]; then
+    pdir="-d $3"
+    dir="$3/"
+elif [ $# -ne 1 ]; then
+    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+    exit 1
+fi
+case "$1" in
+    -patch)
+        patch $pdir -f --no-backup-if-mismatch -p1 < $0
+        #cd ${dir}gcc && autoconf
+        ;;
+    -unpatch)
+        patch $pdir -f --no-backup-if-mismatch -R -p1 < $0
+        #rm ${dir}gcc/configure
+        ;;
+    *)
+        echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+        exit 1
+esac
+exit 0
+
+---
+ src/boehm-gc/testsuite/boehm-gc.c/middle.c                 |    3 +++
+ src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c  |    1 +
+ src/gcc/testsuite/g++.dg/abi/pragma-pack1.C                |    2 ++
+ src/gcc/testsuite/g++.dg/abi/regparm1.C                    |    1 +
+ src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C           |    1 +
+ src/gcc/testsuite/g++.dg/torture/pr51436.C                 |    1 +
+ src/gcc/testsuite/g++.old-deja/g++.law/weak.C              |    2 +-
+ src/gcc/testsuite/g++.old-deja/g++.other/std1.C            |    1 +
+ src/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.x   |    5 +++++
+ src/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.x    |    5 +++++
+ src/gcc/testsuite/gcc.dg/charset/builtin2.c                |    2 +-
+ src/gcc/testsuite/gcc.dg/format/format.exp                 |    2 +-
+ src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c                   |    2 +-
+ src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c                |    2 ++
+ src/gcc/testsuite/gcc.dg/pr30473.c                         |    2 +-
+ src/gcc/testsuite/gcc.dg/pr38902.c                         |    2 +-
+ src/gcc/testsuite/gcc.dg/pr59418.c                         |    2 +-
+ src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c            |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c      |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c  |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c       |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c   |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c     |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c      |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c  |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/isolate-4.c              |    2 +-
+ src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m    |    2 +-
+ 28 files changed, 40 insertions(+), 18 deletions(-)
+
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.x
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.x
+@@ -0,0 +1,5 @@
++# Implement "/* { dg-options "-U_FORITFY_SOURCE" } */", due to
++# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20567
++
++set additional_flags "-U_FORTIFY_SOURCE"
++return 0
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.x
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.x
+@@ -0,0 +1,5 @@
++# Implement "/* { dg-options "-U_FORITFY_SOURCE" } */", due to
++# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20567
++
++set additional_flags "-U_FORTIFY_SOURCE"
++return 0
+Index: b/src/gcc/testsuite/gcc.dg/charset/builtin2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/charset/builtin2.c
++++ b/src/gcc/testsuite/gcc.dg/charset/builtin2.c
+@@ -3,7 +3,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-require-iconv "IBM1047" } */
+-/* { dg-options "-O2 -fexec-charset=IBM1047" } */
++/* { dg-options "-O2 -fexec-charset=IBM1047 -Wno-format" } */
+ /* { dg-final { scan-assembler-not "printf" } } */
+ /* { dg-final { scan-assembler-not "fprintf" } } */
+ /* { dg-final { scan-assembler-not "sprintf" } } */
+Index: b/src/gcc/testsuite/gcc.dg/format/format.exp
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/format/format.exp
++++ b/src/gcc/testsuite/gcc.dg/format/format.exp
+@@ -26,7 +26,7 @@ load_lib gcc-dg.exp
+ load_lib torture-options.exp
+ 
+ torture-init
+-set-torture-options [list { } { -DWIDE } ]
++set-torture-options [list { -Wformat=0 } { -DWIDE -Wformat=0 } ]
+ 
+ dg-init
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] "" ""
+Index: b/src/gcc/testsuite/gcc.dg/pr30473.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr30473.c
++++ b/src/gcc/testsuite/gcc.dg/pr30473.c
+@@ -1,7 +1,7 @@
+ /* PR middle-end/30473 */
+ /* Make sure this doesn't ICE.  */
+ /* { dg-do compile } */
+-/* { dg-options "-O2" } */
++/* { dg-options "-O2 -Wno-format" } */
+ 
+ extern int sprintf (char *, const char *, ...);
+ 
+Index: b/src/gcc/testsuite/gcc.dg/pr38902.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr38902.c
++++ b/src/gcc/testsuite/gcc.dg/pr38902.c
+@@ -1,6 +1,6 @@
+ /* PR target/38902 */
+ /* { dg-do run } */
+-/* { dg-options "-O2 -fstack-protector" } */
++/* { dg-options "-O2 -fstack-protector -Wno-format" } */
+ /* { dg-require-effective-target fstack_protector } */
+ 
+ #ifdef DEBUG
+Index: b/src/gcc/testsuite/gcc.dg/pr59418.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr59418.c
++++ b/src/gcc/testsuite/gcc.dg/pr59418.c
+@@ -2,7 +2,7 @@
+ /* Reported by Ryan Mansfield <rmansfield@qnx.com> */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-Os -g" } */
++/* { dg-options "-Os -g -Wno-format-zero-length" } */
+ /* { dg-options "-march=armv7-a -mfloat-abi=hard -Os -g" { target { arm*-*-* && { ! arm_thumb1 } } } } */
+ 
+ extern int printf (const char *__format, ...);
+Index: b/src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c
++++ b/src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -fipa-sra -fdump-tree-eipa_sra-details"  } */
++/* { dg-options "-O2 -fipa-sra -fdump-tree-eipa_sra-details -Wformat=0"  } */
+ 
+ struct bovid
+ {
+Index: b/src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c
+@@ -1,3 +1,5 @@
++/* { dg-lto-options "-Wno-nonnull" } */
++
+ void set_mem_alias_set ();
+ void emit_push_insn () {
+   set_mem_alias_set ();
+Index: b/src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c
++++ b/src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-do run } */
++/* { dg-options "-Wformat=0" } */
+ #define vector(elcount, type)  \
+ __attribute__((vector_size((elcount)*sizeof(type)))) type
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ extern int printf (const char *, ...);
+ volatile int vi0, vi1, vi2, vi3, vi4, vi5, vi6, vi7, vi8, vi9, via;
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ extern int __printf_chk (int, const char *, ...);
+ volatile int vi0, vi1, vi2, vi3, vi4, vi5, vi6, vi7, vi8, vi9, via;
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ typedef struct { int i; } FILE;
+ FILE *fp;
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ typedef struct { int i; } FILE;
+ FILE *fp;
+Index: b/src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c
++++ b/src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c
+@@ -1,7 +1,7 @@
+ /* { dg-do run }  */
+ /* { dg-require-effective-target tls  }  */
+ /* { dg-require-effective-target pthread } */
+-/* { dg-options "-pthread" } */
++/* { dg-options "-pthread -Wformat=0" } */
+ 
+ #include <pthread.h>
+ extern int printf (char *,...);
+Index: b/src/boehm-gc/testsuite/boehm-gc.c/middle.c
+===================================================================
+--- a/src/boehm-gc/testsuite/boehm-gc.c/middle.c
++++ b/src/boehm-gc/testsuite/boehm-gc.c/middle.c
+@@ -2,6 +2,9 @@
+  * Test at the boundary between small and large objects.
+  * Inspired by a test case from Zoltan Varga.
+  */
++
++/* { dg-options "-Wformat=0" } */
++
+ #include <gc.h>
+ #include <stdio.h>
+ 
+Index: b/src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m
+===================================================================
+--- a/src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m
++++ b/src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m
+@@ -2,7 +2,7 @@
+ /* Developed by Markus Hitter <mah@jump-ing.de>.  */
+ /* { dg-do run } */
+ /* { dg-xfail-run-if "Needs OBJC2 ABI" { *-*-darwin* && { lp64 && { ! objc2 } } } { "-fnext-runtime" } { "" } } */
+-/* { dg-options "-fconstant-string-class=Foo" } */
++/* { dg-options "-fconstant-string-class=Foo -Wno-format-security" } */
+ /* { dg-options "-mno-constant-cfstrings -fconstant-string-class=Foo" { target *-*-darwin* } } */
+ 
+ #include "../../../objc-obj-c++-shared/objc-test-suite-types.h"
+Index: b/src/gcc/testsuite/g++.dg/abi/pragma-pack1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/abi/pragma-pack1.C
++++ b/src/gcc/testsuite/g++.dg/abi/pragma-pack1.C
+@@ -1,5 +1,7 @@
+ // PR c++/7046
+ 
++// { dg-options "-Wformat=0" }
++
+ extern "C" int printf (const char *, ...);
+ 
+ #pragma pack(4)
+Index: b/src/gcc/testsuite/g++.dg/abi/regparm1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/abi/regparm1.C
++++ b/src/gcc/testsuite/g++.dg/abi/regparm1.C
+@@ -1,6 +1,7 @@
+ // PR c++/29911 (9381)
+ // { dg-do run { target i?86-*-* x86_64-*-* } }
+ // { dg-require-effective-target c++11 }
++// { dg-options "-Wformat=0" }
+ 
+ extern "C" int printf(const char *, ...);
+ 
+Index: b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C
++++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C
+@@ -1,5 +1,6 @@
+ // PR c++/53202
+ // { dg-do run { target c++11 } }
++// { dg-options "-Wformat=0" }
+ 
+ #include <tuple>
+ 
+Index: b/src/gcc/testsuite/g++.dg/torture/pr51436.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr51436.C
++++ b/src/gcc/testsuite/g++.dg/torture/pr51436.C
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-options "-Wno-nonnull" } */
+ 
+ typedef __SIZE_TYPE__ size_t;
+ extern "C" void *memcpy (void *, __const void *, size_t);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.law/weak.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.law/weak.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.law/weak.C
+@@ -1,6 +1,6 @@
+ // { dg-do link { target i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } }
+ // { dg-require-effective-target static }
+-// { dg-options "-static" }
++// { dg-options "-static -Wno-nonnull" }
+ // Bug: g++ fails to instantiate operator<<.
+ 
+ // libc-5.4.xx has __IO_putc in its static C library, which can conflict
+Index: b/src/gcc/testsuite/g++.old-deja/g++.other/std1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.other/std1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.other/std1.C
+@@ -1,4 +1,5 @@
+ // { dg-do assemble  }
++// { dg-options "-Wno-nonnull" }
+ // Origin: Mark Mitchell <mark@codesourcery.com>
+ 
+ extern "C" int memcmp (const void * __s1,
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
--- gcc-6-6.3.0.orig/debian/patches/testsuite-hardening-printf-types.diff
+++ gcc-6-6.3.0/debian/patches/testsuite-hardening-printf-types.diff
@@ -0,0 +1,667 @@
+# DP: Description: adjust/standardize printf types to avoid -Wformat warnings.
+# DP: Author: Kees Cook <kees@ubuntu.com>
+# DP: Ubuntu: https://bugs.launchpad.net/bugs/344502
+
+Index: b/src/gcc/testsuite/g++.dg/ext/align1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ext/align1.C
++++ b/src/gcc/testsuite/g++.dg/ext/align1.C
+@@ -16,6 +16,7 @@ float f1 __attribute__ ((aligned));
+ int
+ main (void)
+ {
+-  printf ("%d %d\n", __alignof (a1), __alignof (f1));
++  // "%td" is not allowed by ISO C++, so use %p with a void * cast
++  printf ("%p %p\n", (void*)__alignof (a1), (void*)__alignof (f1));
+   return (__alignof (a1) < __alignof (f1));
+ }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C
+@@ -14,7 +14,8 @@ void* new_test::operator new(size_t sz,
+ {
+   void *p;
+ 
+-  printf("%d %d %d\n", sz, count, type);
++  // ISO C++ does not support format size modifier "z", so use a cast
++  printf("%u %d %d\n", (unsigned int)sz, count, type);
+ 
+   p = new char[sz * count];
+   ((new_test *)p)->type = type;
+Index: b/src/gcc/testsuite/gcc.dg/torture/matrix-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/matrix-2.c
++++ b/src/gcc/testsuite/gcc.dg/torture/matrix-2.c
+@@ -42,7 +42,7 @@ main (int argc, char **argv)
+     }
+   for (i = 0; i < ARCHnodes; i++)
+     for (j = 0; j < 3; j++)
+-      printf ("%x\n",vel[i][j]);
++      printf ("%p\n",vel[i][j]);
+       /*if (i!=1 || j!=1)*/
+       /*if (i==1 && j==1)
+         continue;
+@@ -82,14 +82,14 @@ mem_init (void)
+       for (j = 0; j < 3; j++)
+ 	{
+ 	  vel[i][j] = (int *) malloc (ARCHnodes1 * sizeof (int));
+-          printf ("%x %d %d\n",vel[i][j], ARCHnodes1, sizeof (int));
++          printf ("%p %d %d\n",vel[i][j], ARCHnodes1, (int)sizeof (int));
+ 	}
+     }
+    for (i = 0; i < ARCHnodes; i++)
+     {
+       for (j = 0; j < 3; j++)
+         {
+-          printf ("%x\n",vel[i][j]);
++          printf ("%p\n",vel[i][j]);
+         }
+     }
+ 
+@@ -98,7 +98,7 @@ mem_init (void)
+     {
+       for (j = 0; j < 3; j++)
+ 	{
+-	  printf ("%x\n",vel[i][j]);
++	  printf ("%p\n",vel[i][j]);
+           /*for (k = 0; k < ARCHnodes1; k++)
+ 	    {
+ 	      vel[i][j][k] = d;
+Index: b/src/gcc/testsuite/gcc.dg/packed-vla.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/packed-vla.c
++++ b/src/gcc/testsuite/gcc.dg/packed-vla.c
+@@ -18,8 +18,8 @@ int func(int levels)
+     int			b[4];
+   } __attribute__ ((__packed__)) foo;
+ 
+-  printf("foo %d\n", sizeof(foo));
+-  printf("bar %d\n", sizeof(bar));
++  printf("foo %d\n", (int)sizeof(foo));
++  printf("bar %d\n", (int)sizeof(bar));
+ 
+   if (sizeof (foo) != sizeof (bar))
+     abort ();
+Index: b/src/gcc/testsuite/g++.dg/opt/alias2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/alias2.C
++++ b/src/gcc/testsuite/g++.dg/opt/alias2.C
+@@ -30,14 +30,14 @@ public:
+ 
+ 
+ _Deque_base::~_Deque_base() {
+-  printf ("bb %x %x\n", this, *_M_start._M_node);
++  printf ("bb %p %x\n", this, *_M_start._M_node);
+ }
+ 
+ void
+ _Deque_base::_M_initialize_map()
+ {
+   yy = 0x123;
+-  printf ("aa %x %x\n", this, yy);
++  printf ("aa %p %x\n", this, yy);
+ 
+   _M_start._M_node = &yy;
+   _M_start._M_cur = yy;
+Index: b/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C
+@@ -33,7 +33,7 @@ struct VBase
+   void Offset () const
+   {
+     printf ("VBase\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
+   }
+ };
+ 
+@@ -55,8 +55,8 @@ struct VDerived : virtual VBase
+   void Offset () const
+   {
+     printf ("VDerived\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
+-    printf ("  VDerived::member %d\n", &this->VDerived::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
++    printf ("  VDerived::member %d\n", (int)(&this->VDerived::member - (int *)this));
+   }
+ };
+ struct B : virtual VBase
+@@ -65,8 +65,8 @@ struct B : virtual VBase
+   void Offset () const
+   {
+     printf ("B\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
+-    printf ("  B::member %d\n", &this->B::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
++    printf ("  B::member %d\n", (int)(&this->B::member - (int *)this));
+   }
+ };
+ struct MostDerived : B, virtual VDerived
+@@ -75,10 +75,10 @@ struct MostDerived : B, virtual VDerived
+   void Offset () const
+   {
+     printf ("MostDerived\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
+-    printf ("  B::member %d\n", &this->B::member - (int *)this);
+-    printf ("  VDerived::member %d\n", &this->VDerived::member - (int *)this);
+-    printf ("  MostDerived::member %d\n", &this->MostDerived::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
++    printf ("  B::member %d\n", (int)(&this->B::member - (int *)this));
++    printf ("  VDerived::member %d\n", (int)(&this->VDerived::member - (int *)this));
++    printf ("  MostDerived::member %d\n", (int)(&this->MostDerived::member - (int *)this));
+   }
+ };
+ 
+@@ -95,10 +95,10 @@ int main ()
+     if (ctorVDerived != &dum.VDerived::member)
+       return 24;
+     
+-    printf ("  VBase::member %d\n", &dum.VBase::member - this_);
+-    printf ("  B::member %d\n", &dum.B::member - this_);
+-    printf ("  VDerived::member %d\n", &dum.VDerived::member - this_);
+-    printf ("  MostDerived::member %d\n", &dum.MostDerived::member - this_);
++    printf ("  VBase::member %d\n", (int)(&dum.VBase::member - this_));
++    printf ("  B::member %d\n", (int)(&dum.B::member - this_));
++    printf ("  VDerived::member %d\n", (int)(&dum.VDerived::member - this_));
++    printf ("  MostDerived::member %d\n", (int)(&dum.MostDerived::member - this_));
+     dum.MostDerived::Offset ();
+     dum.B::Offset ();
+     dum.VDerived::Offset ();
+Index: b/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C
+@@ -15,6 +15,6 @@ int main(){
+ 	
+ 	Double_alignt<20000> heap;
+ 
+-	printf(" &heap.array[0] = %d, &heap.for_alignt = %d\n", &heap.array[0], &heap.for_alignt);
++	printf(" &heap.array[0] = %p, &heap.for_alignt = %p\n", (void*)&heap.array[0], (void*)&heap.for_alignt);
+ 
+ }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C
+@@ -16,7 +16,7 @@ int main()
+   }
+ 
+   catch (E *&e) {
+-    printf ("address of e is 0x%lx\n", (__SIZE_TYPE__)e);
++    printf ("address of e is %p\n", (void *)e);
+     return !((__SIZE_TYPE__)e != 5 && e->x == 5);
+   }
+   return 2;
+Index: b/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C
+@@ -42,19 +42,19 @@ public:
+   void DoSomething() {
+     PUB_A = 0;
+     Foo::A = 0;
+-    printf("%x\n",pX);  
++    printf("%p\n",pX);  
+     Foo::PUB.A = 0;
+-    printf("%x\n",PUB.pX);  
++    printf("%p\n",PUB.pX);  
+     B = 0;			
+-    printf("%x\n",Foo::pY);  
++    printf("%p\n",Foo::pY);  
+     PRT_A = 0;
+     PRT.B = 0;		
+-    printf("%x\n",Foo::PRT.pY);	
++    printf("%p\n",Foo::PRT.pY);	
+     PRV_A = 0;			// { dg-error "" } 
+     Foo::C = 0;			// { dg-error "" } 
+-    printf("%x\n",pZ);  	// { dg-error "" } 
++    printf("%p\n",pZ);  	// { dg-error "" } 
+     Foo::PRV.C = 0;		// { dg-error "" } 
+-    printf("%x\n",PRV.pZ); 	// { dg-error "" } 
++    printf("%p\n",PRV.pZ); 	// { dg-error "" } 
+   }
+ };
+ 
+@@ -64,17 +64,17 @@ int main()
+ 
+   a.PUB_A = 0;
+   a.A = 0;
+-  printf("%x\n",a.pX);  
++  printf("%p\n",a.pX);  
+   a.PRT_A = 0;			// { dg-error "" } 
+   a.B = 0;			// { dg-error "" } 
+-  printf("%x\n",a.pY);  	// { dg-error "" } 
++  printf("%p\n",a.pY);  	// { dg-error "" } 
+   a.PRV_A = 0;			// { dg-error "" } 
+   a.C = 0;			// { dg-error "" } 
+-  printf("%x\n",a.pZ);  	// { dg-error "" } 
++  printf("%p\n",a.pZ);  	// { dg-error "" } 
+   a.PUB.A = 0;
+-  printf("%x\n",a.PUB.pX);  
++  printf("%p\n",a.PUB.pX);  
+   a.PRT.B = 0;			// { dg-error "" } 
+-  printf("%x\n",a.PRT.pY);  	// { dg-error "" } 
++  printf("%p\n",a.PRT.pY);  	// { dg-error "" } 
+   a.PRV.C = 0;			// { dg-error "" } 
+-  printf("%x\n",a.PRV.pZ);  	// { dg-error "" } 
++  printf("%p\n",a.PRV.pZ);  	// { dg-error "" } 
+ }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C
+@@ -20,12 +20,12 @@ struct B {
+ B::operator const A&() const {
+         static A a;
+         a.i = i;
+-        printf("convert B to A at %x\n", &a);
++        printf("convert B to A at %p\n", (void*)&a);
+         return a;
+ }
+ 
+ void f(A &a) { // { dg-message "" } in passing argument
+-        printf("A at %x is %d\n", &a, a.i);
++  printf("A at %p is %d\n", (void*)&a, a.i);
+ }
+ 
+ int main() {
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C
+@@ -17,10 +17,10 @@ public:
+ 
+ int main() {
+   C c;
+-  printf("&c.x = %x\n", &c.x);
+-  printf("&c.B1::x = %x\n", &c.B1::x);
+-  printf("&c.B2::x = %x\n", &c.B2::x);
+-  printf("&c.A::x = %x\n", &c.A::x);
++  printf("&c.x = %p\n", (void*)&c.x);
++  printf("&c.B1::x = %p\n", (void*)&c.B1::x);
++  printf("&c.B2::x = %p\n", (void*)&c.B2::x);
++  printf("&c.A::x = %p\n", (void*)&c.A::x);
+   if (&c.x != &c.B1::x
+       || &c.x != &c.B2::x
+       || &c.x != &c.A::x)
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C
+@@ -6,7 +6,7 @@ int fail = 0;
+ class Foo {
+ public:
+    virtual void setName() {
+-     printf("Foo at %x\n", this);
++     printf("Foo at %p\n", (void*)this);
+      if (vp != (void*)this)
+        fail = 1;
+    }
+@@ -15,7 +15,7 @@ public:
+ class Bar : public Foo {
+ public:
+   virtual void init(int argc, char **argv) {
+-    printf("Bar's Foo at %x\n", (Foo*)this);
++    printf("Bar's Foo at %p\n", (void*)(Foo*)this);
+     vp = (void*)(Foo*)this;
+     setName();
+   }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C
+@@ -18,7 +18,7 @@ public:
+     if (ptr2 != &(*this).slist)
+       fail = 6;
+ 
+-    if (0) printf("at %x %x\n", (RWSlistIterator*)this, &(*this).slist);
++    if (0) printf("at %p %p\n", (void*)(RWSlistIterator*)this, (void*)&(*this).slist);
+   }
+ };
+ 
+@@ -54,14 +54,14 @@ Sim_Event_Manager::Sim_Event_Manager ()
+ void Sim_Event_Manager::post_event () {
+   ptr1 = (RWSlistIterator*)&last_posted_event_position_;
+   ptr2 = &((RWSlistIterator*)&last_posted_event_position_)->slist;
+-  if (0) printf("at %x %x\n", (RWSlistIterator*)&last_posted_event_position_,
+-		&((RWSlistIterator*)&last_posted_event_position_)->slist);
++  if (0) printf("at %p %p\n", (void*)(RWSlistIterator*)&last_posted_event_position_,
++		(void*)&((RWSlistIterator*)&last_posted_event_position_)->slist);
+   if (ptr1 != (RWSlistIterator*)&last_posted_event_position_)
+     fail = 1;
+   if (ptr2 != &((RWSlistIterator&)last_posted_event_position_).slist)
+     fail = 2;
+-  if (0) printf("at %x ?%x\n", (RWSlistIterator*)&last_posted_event_position_,
+-		&((RWSlistIterator&)last_posted_event_position_).slist);
++  if (0) printf("at %p ?%p\n", (void*)(RWSlistIterator*)&last_posted_event_position_,
++		(void*)&((RWSlistIterator&)last_posted_event_position_).slist);
+   if (ptr1 != (RWSlistIterator*)&last_posted_event_position_)
+     fail = 3;
+   if (ptr2 != &((RWSlistIterator&)last_posted_event_position_).slist)
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C
+@@ -7,26 +7,26 @@ int num_x;
+ 
+ class Y {
+ public:
+-  Y () { printf("Y()            this: %x\n", this); }
+-  ~Y () { printf("~Y()           this: %x\n", this); }
++  Y () { printf("Y()            this: %p\n", (void*)this); }
++  ~Y () { printf("~Y()           this: %p\n", (void*)this); }
+ };
+ 
+ class X {
+ public:
+   X () {
+     ++num_x;
+-    printf("X()            this: %x\n", this);
++    printf("X()            this: %p\n", (void*)this);
+     Y y;
+     *this = (X) y;
+   }
+ 
+-  X (const Y & yy) { printf("X(const Y&)    this: %x\n", this); ++num_x; }
++  X (const Y & yy) { printf("X(const Y&)    this: %p\n", (void*)this); ++num_x; }
+   X & operator = (const X & xx) {
+-    printf("X.op=(X&)      this: %x\n", this);
++    printf("X.op=(X&)      this: %p\n", (void*)this);
+     return *this;
+   }
+ 
+-  ~X () { printf("~X()           this: %x\n", this); --num_x; }
++  ~X () { printf("~X()           this: %p\n", (void*)this); --num_x; }
+ };
+ 
+ int main (int, char **) {
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C
+@@ -38,7 +38,7 @@ public:
+   virtual void xx(int doit) {
+     --num;
+     if (ptr != this)
+-      printf("FAIL\n%x != %x\n", ptr, this);
++      printf("FAIL\n%p != %p\n", ptr, (void*)this);
+     printf ("C is destructed.\n");
+     B::xx (0);
+     if (doit) A::xx (1);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C
+@@ -48,7 +48,7 @@ public:
+   virtual void xx(int doit) {
+     --num;
+     if (ptr != this) {
+-      printf("FAIL\n%x != %x\n", ptr, this);
++      printf("FAIL\n%p != %p\n", ptr, (void*)this);
+       exit(1);
+     }
+     printf ("D is destructed.\n");
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C
+@@ -38,7 +38,7 @@ public:
+   virtual void xx(int doit) {
+     --num;
+     if (ptr != this)
+-      printf("FAIL\n%x != %x\n", ptr, this);
++      printf("FAIL\n%p != %p\n", ptr, (void*)this);
+     printf ("C is destructed.\n");
+     B::xx (0);
+     if (doit) A::xx (1);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C
+@@ -35,20 +35,20 @@ int foo::si = 0;
+ foo::foo ()
+ {
+   si++;
+-  printf ("new foo @ 0x%x; now %d foos\n", this, si);
++  printf ("new foo @ %p; now %d foos\n", (void*)this, si);
+ }
+ 
+ foo::foo (const foo &other)
+ {
+   si++;
+-  printf ("another foo @ 0x%x; now %d foos\n", this, si);
++  printf ("another foo @ %p; now %d foos\n", (void*)this, si);
+   *this = other;
+ }
+ 
+ foo::~foo ()
+ {
+   si--;
+-  printf ("deleted foo @ 0x%x; now %d foos\n", this, si);
++  printf ("deleted foo @ %p; now %d foos\n", (void*)this, si);
+ }
+ 
+ int
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C
+@@ -30,7 +30,7 @@ class B
+    virtual ~B() {}
+    void operator delete(void*,size_t s)
+   {
+-      printf("B::delete() %d\n",s);
++      printf("B::delete() %u\n",(unsigned int)s);
+    }
+    void operator delete(void*){}
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C
+@@ -13,10 +13,10 @@ struct foo
+   int x;
+   foo () {
+     x = count++;
+-    printf("this %d = %x\n", x, (void *)this);
++    printf("this %d = %p\n", x, (void *)this);
+   }
+   virtual ~foo () {
+-    printf("this %d = %x\n", x, (void *)this);
++    printf("this %d = %p\n", x, (void *)this);
+     --count;
+   }
+ };
+@@ -31,7 +31,7 @@ int main ()
+       {
+ 	for (int j = 0; j < 3; j++)
+ 	  {
+-	    printf("&a[%d][%d] = %x\n", i, j, (void *)&array[i][j]);
++	    printf("&a[%d][%d] = %p\n", i, j, (void *)&array[i][j]);
+ 	  }
+       }
+       // The count should be nine, if not, fail the test.
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C
+@@ -42,7 +42,7 @@ B_table b;
+ bar jar;
+ 
+ int main() {
+-  printf("ptr to B_table=%x, ptr to A_table=%x\n",&b,(A_table*)&b);
++  printf("ptr to B_table=%p, ptr to A_table=%p\n",(void*)&b,(void*)(A_table*)&b);
+   B_table::B_ti_fn z = &B_table::func1;
+   int j = 1;
+   jar.call_fn_fn1(j,(void *)&z);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C
+@@ -7,11 +7,11 @@ class T {
+ public:
+   T() {
+     i = 1;
+-    printf("T() at %x\n", this);
++    printf("T() at %p\n", (void*)this);
+   }
+   T(const T& o) {
+     i = o.i;
+-    printf("T(const T&) at %x <-- %x\n", this, &o);
++    printf("T(const T&) at %p <-- %p\n", (void*)this, (void*)&o);
+   }
+   T operator +(const T& o) {
+     T r;
+@@ -21,7 +21,7 @@ public:
+   operator int () {
+     return i;
+   }
+-  ~T() { printf("~T() at %x\n", this); }
++  ~T() { printf("~T() at %p\n", (void*)this); }
+ } s, b;
+ 
+ int foo() { return getenv("TEST") == 0; }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C
+@@ -5,16 +5,16 @@ int c, d;
+ class Foo 
+ {
+ public:
+-   Foo() { printf("Foo() 0x%08lx\n", (__SIZE_TYPE__)this); ++c; }
+-   Foo(Foo const &) { printf("Foo(Foo const &) 0x%08lx\n", (__SIZE_TYPE__)this); }
+-   ~Foo() { printf("~Foo() 0x%08lx\n", (__SIZE_TYPE__)this); ++d; }
++   Foo() { printf("Foo() %p\n", (void*)this); ++c; }
++   Foo(Foo const &) { printf("Foo(Foo const &) %p\n", (void*)this); }
++   ~Foo() { printf("~Foo() %p\n", (void*)this); ++d; }
+ };
+ 
+ // Bar creates constructs a temporary Foo() as a default
+ class Bar 
+ {
+ public:
+-   Bar(Foo const & = Foo()) { printf("Bar(Foo const &) 0x%08lx\n", (__SIZE_TYPE__)this); }
++   Bar(Foo const & = Foo()) { printf("Bar(Foo const &) %p\n", (void*)this); }
+ };
+ 
+ void fakeRef(Bar *)
+Index: b/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C
+@@ -4,7 +4,7 @@ extern "C" int printf (const char*, ...)
+ struct A
+ {
+   virtual void f () {
+-    printf ("%x\n", this);
++    printf ("%p\n", (void*)this);
+   }
+ };
+ 
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C
+@@ -13,7 +13,7 @@ struct S
+ 
+   template <class U>
+   void f(U u)
+-  { printf ("In S::f(U)\nsizeof(U) == %d\n", sizeof(u)); }
++  { printf ("In S::f(U)\nsizeof(U) == %d\n", (int)sizeof(u)); }
+ 
+   int c[16];
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C
+@@ -13,7 +13,7 @@ struct S
+ 
+   template <class U>
+   void f(U u)
+-  { printf ("In S::f(U)\nsizeof(U) == %d\n", sizeof(u)); }
++  { printf ("In S::f(U)\nsizeof(U) == %d\n", (int)sizeof(u)); }
+ 
+   int c[16];
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C
+@@ -6,7 +6,7 @@ template <class X>
+ struct S
+ {
+   template <class U>
+-  void f(U u) { printf ("%d\n", sizeof (U)); }
++  void f(U u) { printf ("%d\n", (int)sizeof (U)); }
+ 
+   int i[4];
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C
+@@ -16,7 +16,7 @@ template <class X>
+ template <class U>
+ void S<X>::f(U u)
+ {
+-  printf ("%d\n", sizeof (U));
++  printf ("%d\n", (int)sizeof (U));
+ }
+ 
+ 
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C
+@@ -10,9 +10,9 @@ struct frob {
+ 
+ template <class T>
+ void frob<T>::print () {
+-  printf ("this = %08x\n", this);
+-  printf (" ptr = %08x\n", ptr);
+-  printf (" values = %x %x %x ...\n", ptr[0], ptr[1], ptr[2]);
++  printf ("this = %p\n", (void*)this);
++  printf (" ptr = %p\n", (void*)ptr);
++  printf (" values = %x %x %x ...\n", (int)ptr[0], (int)ptr[1], (int)ptr[2]);
+ }
+ 
+   static int x[10];
+Index: b/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C
+@@ -44,15 +44,15 @@ int main()
+     A * a = new B;
+     B * b = dynamic_cast<B *>(a);
+ 
+-    printf("%p\n",b);                // (*2*)
++    printf("%p\n",(void*)b);                // (*2*)
+     b->print();
+ 
+     a = b;
+-    printf("%p\n",a);
++    printf("%p\n",(void*)a);
+     a->print();
+ 
+     a = a->clone();
+-    printf("%p\n",a);
++    printf("%p\n",(void*)a);
+     a->print();                      // (*1*)
+ 
+     return 0;
+Index: b/src/gcc/testsuite/gcc.dg/pch/inline-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pch/inline-4.c
++++ b/src/gcc/testsuite/gcc.dg/pch/inline-4.c
+@@ -1,6 +1,6 @@
+ #include "inline-4.h"
+ extern int printf (const char *, ...);
+ int main(void) {
+-  printf (getstring());
++  printf ("%s", getstring());
+   return 0;
+ }
--- gcc-6-6.3.0.orig/debian/patches/testsuite-hardening-updates.diff
+++ gcc-6-6.3.0/debian/patches/testsuite-hardening-updates.diff
@@ -0,0 +1,143 @@
+# DP: Fix some gcc and g++ testcases to pass with hardening defaults
+
+---
+ src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c     |    2 +-
+ src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c |    2 +-
+ src/gcc/testsuite/g++.dg/asan/asan_test.C                    |    2 +-
+ src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C   |    2 +-
+ src/gcc/testsuite/g++.dg/fstack-protector-strong.C           |    2 +-
+ src/gcc/testsuite/gcc.c-torture/execute/memset-1.c           |    1 -
+ src/gcc/testsuite/gcc.c-torture/execute/memset-1.x           |    5 +++++
+ src/gcc/testsuite/gcc.dg/fstack-protector-strong.c           |    2 +-
+ src/gcc/testsuite/gcc.dg/stack-usage-1.c                     |    2 +-
+ src/gcc/testsuite/gcc.dg/superblock.c                        |    2 +-
+ src/gcc/testsuite/gcc.target/i386/sw-1.c                     |    2 +-
+ 11 files changed, 14 insertions(+), 10 deletions(-)
+
+Index: b/src/gcc/testsuite/g++.dg/asan/asan_test.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/asan/asan_test.C
++++ b/src/gcc/testsuite/g++.dg/asan/asan_test.C
+@@ -2,7 +2,7 @@
+ // { dg-skip-if "" { *-*-* } { "*" } { "-O2" } }
+ // { dg-skip-if "" { *-*-* } { "-flto" } { "" } }
+ // { dg-additional-sources "asan_globals_test-wrapper.cc" }
+-// { dg-options "-std=c++11 -fsanitize=address -fno-builtin -Wall -Wno-format -Werror -g -DASAN_UAR=0 -DASAN_HAS_EXCEPTIONS=1 -DASAN_HAS_BLACKLIST=0 -DSANITIZER_USE_DEJAGNU_GTEST=1 -lasan -lpthread -ldl" }
++// { dg-options "-std=c++11 -fsanitize=address -fno-builtin -Wall -Wno-format -Wno-unused-result -Werror -g -DASAN_UAR=0 -DASAN_HAS_EXCEPTIONS=1 -DASAN_HAS_BLACKLIST=0 -DSANITIZER_USE_DEJAGNU_GTEST=1 -lasan -lpthread -ldl" }
+ // { dg-additional-options "-DASAN_NEEDS_SEGV=1" { target { ! arm*-*-* } } }
+ // { dg-additional-options "-DASAN_LOW_MEMORY=1 -DASAN_NEEDS_SEGV=0" { target arm*-*-* } }
+ // { dg-additional-options "-DASAN_AVOID_EXPENSIVE_TESTS=1" { target { ! run_expensive_tests } } }
+Index: b/src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C
++++ b/src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C
+@@ -1,7 +1,7 @@
+ // ASan interceptor can be accessed with __interceptor_ prefix.
+ 
+ // { dg-do run { target *-*-linux* } }
+-// { dg-options "-fno-builtin-free" }
++// { dg-options "-fno-builtin-free -Wno-unused-result" }
+ // { dg-additional-options "-D__NO_INLINE__" { target { *-*-linux-gnu } } }
+ // { dg-shouldfail "asan" }
+ 
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/memset-1.c
++++ b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.c
+@@ -1,3 +1,5 @@
++/* { dg-prune-output ".*warning: memset used with constant zero length parameter.*" } */
++
+ /* Copyright (C) 2002  Free Software Foundation.
+ 
+    Test memset with various combinations of pointer alignments and lengths to
+Index: b/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c
++++ b/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-fno-builtin-malloc -fno-builtin-strncpy" } */
++/* { dg-options "-fno-builtin-malloc -fno-builtin-strncpy -U_FORTIFY_SOURCE" } */
+ /* { dg-shouldfail "asan" } */
+ 
+ #include <string.h>
+Index: b/src/gcc/testsuite/gcc.dg/superblock.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/superblock.c
++++ b/src/gcc/testsuite/gcc.dg/superblock.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-asynchronous-unwind-tables -fsched2-use-superblocks -fdump-rtl-sched2 -fdump-rtl-bbro" } */
++/* { dg-options "-O2 -fno-asynchronous-unwind-tables -fsched2-use-superblocks -fdump-rtl-sched2 -fdump-rtl-bbro -fno-stack-protector" } */
+ /* { dg-require-effective-target scheduling } */
+ 
+ typedef int aligned __attribute__ ((aligned (64)));
+Index: b/src/gcc/testsuite/gcc.dg/stack-usage-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c
++++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-fstack-usage" } */
++/* { dg-options "-fstack-usage -fno-stack-protector" } */
+ /* nvptx doesn't have a reg allocator, and hence no stack usage data.  */
+ /* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */
+ 
+Index: b/src/gcc/testsuite/gcc.target/i386/sw-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/sw-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/sw-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue" } */
++/* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue -fno-stack-protector" } */
+ /* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } { "*" } { "" } } */
+ 
+ #include <string.h>
+Index: b/src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c
++++ b/src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run  { target { i?86-*-* x86_64-*-* } } } */
+-/* { dg-options "-fcilkplus -w" } */
++/* { dg-options "-fcilkplus -w -U_FORTIFY_SOURCE" } */
+ /* { dg-additional-options "-lcilkrts" { target { i?86-*-* x86_64-*-* } } } */
+ 
+ #include <stdio.h>
+Index: b/src/gcc/testsuite/gcc.dg/fstack-protector-strong.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/fstack-protector-strong.c
++++ b/src/gcc/testsuite/gcc.dg/fstack-protector-strong.c
+@@ -1,7 +1,7 @@
+ /* Test that stack protection is done on chosen functions. */
+ 
+ /* { dg-do compile { target i?86-*-* x86_64-*-* rs6000-*-* s390x-*-* } } */
+-/* { dg-options "-O2 -fstack-protector-strong" } */
++/* { dg-options "-O2 -fstack-protector-strong -U_FORTIFY_SOURCE" } */
+ 
+ /* This test checks the presence of __stack_chk_fail function in assembler.
+  * Compiler generates _stack_chk_fail_local (wrapper) calls instead for PIC.
+Index: b/src/gcc/testsuite/g++.dg/fstack-protector-strong.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/fstack-protector-strong.C
++++ b/src/gcc/testsuite/g++.dg/fstack-protector-strong.C
+@@ -1,7 +1,7 @@
+ /* Test that stack protection is done on chosen functions. */
+ 
+ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+-/* { dg-options "-O2 -fstack-protector-strong" } */
++/* { dg-options "-O2 -fstack-protector-strong -U_FORTIFY_SOURCE" } */
+ 
+ /* This test checks the presence of __stack_chk_fail function in assembler.
+  * Compiler generates _stack_chk_fail_local (wrapper) calls instead for PIC.
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.x
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.x
+@@ -0,0 +1,5 @@
++# Implement "/* { dg-options "-U_FORITFY_SOURCE" } */", due to
++# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20567
++
++set additional_flags "-U_FORTIFY_SOURCE"
++return 0
--- gcc-6-6.3.0.orig/debian/patches/vulcan-costs.diff
+++ gcc-6-6.3.0/debian/patches/vulcan-costs.diff
@@ -0,0 +1,259 @@
+# DP: Add cost model for vulcan CPU
+
+From: jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Fri, 15 Jul 2016 11:17:53 +0000
+Subject: [PATCH] [PATCH/AARCH64] Add rtx_costs routine for vulcan.
+
+gcc/ChangeLog:
+
+2016-07-15  Virendra Pathak  <virendra.pathak@broadcom.com>
+	    Julian Brown  <julian@codesourcery.com>
+
+	* config/aarch64/aarch64-cores.def: Update vulcan COSTS.
+	* config/aarch64/aarch64-cost-tables.h
+	(vulcan_extra_costs): New variable.
+	* config/aarch64/aarch64.c
+	(vulcan_addrcost_table): Likewise.
+	(vulcan_regmove_cost): Likewise.
+	(vulcan_vector_cost): Likewise.
+	(vulcan_branch_cost): Likewise.
+	(vulcan_tunings): Likewise.
+
+[dannf: backported by removing approx_modes function pointer]
+
+diff -urpN a/src/gcc/config/aarch64/aarch64.c b/src/gcc/config/aarch64/aarch64.c
+--- a/src/gcc/config/aarch64/aarch64.c	2016-07-15 16:14:24.268328586 +0000
++++ b/src/gcc/config/aarch64/aarch64.c	2016-07-15 16:15:52.603299822 +0000
+@@ -250,6 +250,22 @@ static const struct cpu_addrcost_table x
+   0, /* imm_offset  */
+ };
+ 
++static const struct cpu_addrcost_table vulcan_addrcost_table =
++{
++    {
++      0, /* hi  */
++      0, /* si  */
++      0, /* di  */
++      2, /* ti  */
++    },
++  0, /* pre_modify  */
++  0, /* post_modify  */
++  2, /* register_offset  */
++  3, /* register_sextend  */
++  3, /* register_zextend  */
++  0, /* imm_offset  */
++};
++
+ static const struct cpu_regmove_cost generic_regmove_cost =
+ {
+   1, /* GP2GP  */
+@@ -308,6 +324,15 @@ static const struct cpu_regmove_cost xge
+   2 /* FP2FP  */
+ };
+ 
++static const struct cpu_regmove_cost vulcan_regmove_cost =
++{
++  1, /* GP2GP  */
++  /* Avoid the use of int<->fp moves for spilling.  */
++  8, /* GP2FP  */
++  8, /* FP2GP  */
++  4  /* FP2FP  */
++};
++
+ /* Generic costs for vector insn classes.  */
+ static const struct cpu_vector_cost generic_vector_cost =
+ {
+@@ -379,6 +404,24 @@ static const struct cpu_vector_cost xgen
+   1 /* cond_not_taken_branch_cost  */
+ };
+ 
++/* Costs for vector insn classes for Vulcan.  */
++static const struct cpu_vector_cost vulcan_vector_cost =
++{
++  6, /* scalar_stmt_cost  */
++  4, /* scalar_load_cost  */
++  1, /* scalar_store_cost  */
++  6, /* vec_stmt_cost  */
++  3, /* vec_permute_cost  */
++  6, /* vec_to_scalar_cost  */
++  5, /* scalar_to_vec_cost  */
++  8, /* vec_align_load_cost  */
++  8, /* vec_unalign_load_cost  */
++  4, /* vec_unalign_store_cost  */
++  4, /* vec_store_cost  */
++  2, /* cond_taken_branch_cost  */
++  1  /* cond_not_taken_branch_cost  */
++};
++
+ /* Generic costs for branch instructions.  */
+ static const struct cpu_branch_cost generic_branch_cost =
+ {
+@@ -393,6 +436,13 @@ static const struct cpu_branch_cost cort
+   3   /* Unpredictable.  */
+ };
+ 
++/* Branch costs for Vulcan.  */
++static const struct cpu_branch_cost vulcan_branch_cost =
++{
++  1,  /* Predictable.  */
++  3   /* Unpredictable.  */
++};
++
+ static const struct tune_params generic_tunings =
+ {
+   &cortexa57_extra_costs,
+@@ -589,6 +639,30 @@ static const struct tune_params xgene1_t
+   (AARCH64_EXTRA_TUNE_APPROX_RSQRT)	/* tune_flags.  */
+ };
+ 
++static const struct tune_params vulcan_tunings =
++{
++  &vulcan_extra_costs,
++  &vulcan_addrcost_table,
++  &vulcan_regmove_cost,
++  &vulcan_vector_cost,
++  &vulcan_branch_cost,
++  4, /* memmov_cost.  */
++  4, /* issue_rate.  */
++  AARCH64_FUSE_NOTHING, /* fuseable_ops.  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  16,	/* loop_align.  */
++  3,	/* int_reassoc_width.  */
++  2,	/* fp_reassoc_width.  */
++  2,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  0,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++};
++
+ /* Support for fine-grained override of the tuning structures.  */
+ struct aarch64_tuning_override_function
+ {
+diff -urpN a/src/gcc/config/aarch64/aarch64-cores.def b/src/gcc/config/aarch64/aarch64-cores.def
+--- a/src/gcc/config/aarch64/aarch64-cores.def	2016-07-15 16:14:24.272328721 +0000
++++ b/src/gcc/config/aarch64/aarch64-cores.def	2016-07-15 16:15:26.730430056 +0000
+@@ -51,7 +51,7 @@ AARCH64_CORE("xgene1",      xgene1,    x
+ 
+ /* V8.1 Architecture Processors.  */
+ 
+-AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, cortexa57, "0x42", "0x516")
++AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, vulcan, "0x42", "0x516")
+ 
+ /* V8 big.LITTLE implementations.  */
+ 
+diff -urpN a/src/gcc/config/aarch64/aarch64-cost-tables.h b/src/gcc/config/aarch64/aarch64-cost-tables.h
+--- a/src/gcc/config/aarch64/aarch64-cost-tables.h	2016-07-15 16:14:24.272328721 +0000
++++ b/src/gcc/config/aarch64/aarch64-cost-tables.h	2016-07-15 16:15:26.730430056 +0000
+@@ -127,6 +127,108 @@ const struct cpu_cost_table thunderx_ext
+   }
+ };
+ 
++const struct cpu_cost_table vulcan_extra_costs =
++{
++  /* ALU */
++  {
++    0,			/* Arith.  */
++    0,			/* Logical.  */
++    0,			/* Shift.  */
++    0,			/* Shift_reg.  */
++    COSTS_N_INSNS (1),	/* Arith_shift.  */
++    COSTS_N_INSNS (1),	/* Arith_shift_reg.  */
++    COSTS_N_INSNS (1),	/* Log_shift.  */
++    COSTS_N_INSNS (1),	/* Log_shift_reg.  */
++    0,			/* Extend.  */
++    COSTS_N_INSNS (1),	/* Extend_arith.  */
++    0,			/* Bfi.  */
++    0,			/* Bfx.  */
++    COSTS_N_INSNS (3),	/* Clz.  */
++    0,			/* Rev.  */
++    0,			/* Non_exec.  */
++    true		/* Non_exec_costs_exec.  */
++  },
++  {
++    /* MULT SImode */
++    {
++      COSTS_N_INSNS (4),	/* Simple.  */
++      COSTS_N_INSNS (4),	/* Flag_setting.  */
++      COSTS_N_INSNS (4),	/* Extend.  */
++      COSTS_N_INSNS (5),	/* Add.  */
++      COSTS_N_INSNS (5),	/* Extend_add.  */
++      COSTS_N_INSNS (18)	/* Idiv.  */
++    },
++    /* MULT DImode */
++    {
++      COSTS_N_INSNS (4),       /* Simple.  */
++      0,                       /* Flag_setting.  */
++      COSTS_N_INSNS (4),       /* Extend.  */
++      COSTS_N_INSNS (5),       /* Add.  */
++      COSTS_N_INSNS (5),       /* Extend_add.  */
++      COSTS_N_INSNS (26)       /* Idiv.  */
++    }
++  },
++  /* LD/ST */
++  {
++    COSTS_N_INSNS (4),	/* Load.  */
++    COSTS_N_INSNS (4),	/* Load_sign_extend.  */
++    COSTS_N_INSNS (5),	/* Ldrd.  */
++    COSTS_N_INSNS (4),	/* Ldm_1st.  */
++    1,			/* Ldm_regs_per_insn_1st.  */
++    1,			/* Ldm_regs_per_insn_subsequent.  */
++    COSTS_N_INSNS (4),	/* Loadf.  */
++    COSTS_N_INSNS (4),	/* Loadd.  */
++    COSTS_N_INSNS (4),	/* Load_unaligned.  */
++    0,			/* Store.  */
++    0,			/* Strd.  */
++    0,			/* Stm_1st.  */
++    1,			/* Stm_regs_per_insn_1st.  */
++    1,			/* Stm_regs_per_insn_subsequent.  */
++    0,			/* Storef.  */
++    0,			/* Stored.  */
++    0,			/* Store_unaligned.  */
++    COSTS_N_INSNS (1),	/* Loadv.  */
++    COSTS_N_INSNS (1)	/* Storev.  */
++  },
++  {
++    /* FP SFmode */
++    {
++      COSTS_N_INSNS (4),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub. */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst. */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    },
++    /* FP DFmode */
++    {
++      COSTS_N_INSNS (6),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub.  */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst.  */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    }
++  },
++  /* Vector */
++  {
++    COSTS_N_INSNS (1)	/* Alu.  */
++  }
++};
+ 
+ 
+ #endif
--- gcc-6-6.3.0.orig/debian/patches/vulcan-cpu-doc.diff
+++ gcc-6-6.3.0/debian/patches/vulcan-cpu-doc.diff
@@ -0,0 +1,27 @@
+# DP: Accept vulcan as a cpu name for the AArch64 port of GCC (documentation)
+
+From: jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Tue, 21 Jun 2016 13:43:29 +0000 (+0000)
+Subject: [PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+X-Git-Url: https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff_plain;h=2c6ac78145ac8ff2fd83271d093e23ab80a15e4f
+
+[PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+
+gcc/ChangeLog
+
+	* config/aarch64/aarch64-cores.def (vulcan): New core.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi: Document vulcan as an available option.
+
+diff -urpN a/src/gcc/doc/invoke.texi b/src/gcc/doc/invoke.texi
+--- a/src/gcc/doc/invoke.texi	2016-06-21 10:31:29.994143994 -0600
++++ b/src/gcc/doc/invoke.texi	2016-06-21 10:35:51.136081208 -0600
+@@ -12988,7 +12988,7 @@ Specify the name of the target processor
+ performance of the code.  Permissible values for this option are:
+ @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+ @samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx},
+-@samp{xgene1}.
++@samp{vulcan}, @samp{xgene1}.
+ 
+ Additionally, this option can specify that GCC should tune the performance
+ of the code for a big.LITTLE system.  Permissible values for this
--- gcc-6-6.3.0.orig/debian/patches/vulcan-cpu.diff
+++ gcc-6-6.3.0/debian/patches/vulcan-cpu.diff
@@ -0,0 +1,39 @@
+# DP: Accept vulcan as a cpu name for the AArch64 port of GCC
+
+From: jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Tue, 21 Jun 2016 13:43:29 +0000 (+0000)
+Subject: [PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+X-Git-Url: https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff_plain;h=2c6ac78145ac8ff2fd83271d093e23ab80a15e4f
+
+[PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+
+gcc/ChangeLog
+
+	* config/aarch64/aarch64-cores.def (vulcan): New core.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi: Document vulcan as an available option.
+
+diff -urpN a/src/gcc/config/aarch64/aarch64-cores.def b/src/gcc/config/aarch64/aarch64-cores.def
+--- a/src/gcc/config/aarch64/aarch64-cores.def	2016-01-04 07:30:50.000000000 -0700
++++ b/src/gcc/config/aarch64/aarch64-cores.def	2016-06-21 10:32:59.191974071 -0600
+@@ -49,6 +49,10 @@ AARCH64_CORE("qdf24xx",     qdf24xx,   c
+ AARCH64_CORE("thunderx",    thunderx,  thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  "0x43", "0x0a1")
+ AARCH64_CORE("xgene1",      xgene1,    xgene1,    8A,  AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
+ 
++/* V8.1 Architecture Processors.  */
++
++AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, cortexa57, "0x42", "0x516")
++
+ /* V8 big.LITTLE implementations.  */
+ 
+ AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07.0xd03")
+diff -urpN a/src/gcc/config/aarch64/aarch64-tune.md b/src/gcc/config/aarch64/aarch64-tune.md
+--- a/src/gcc/config/aarch64/aarch64-tune.md	2016-04-27 02:22:11.000000000 -0600
++++ b/src/gcc/config/aarch64/aarch64-tune.md	2016-06-21 10:32:59.191974071 -0600
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from aarch64-cores.def
+ (define_attr "tune"
+-	"cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
++	"cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53"
+ 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
--- gcc-6-6.3.0.orig/debian/porting.html
+++ gcc-6-6.3.0/debian/porting.html
@@ -0,0 +1,30 @@
+<html lang="en">
+<head>
+<title>Porting libstdc++-v3</title>
+<meta http-equiv="Content-Type" content="text/html">
+<meta name="description" content="Porting libstdc++-v3">
+<meta name="generator" content="makeinfo 4.6">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<style type="text/css"><!--
+  pre.display { font-family:inherit }
+  pre.format  { font-family:inherit }
+  pre.smalldisplay { font-family:inherit; font-size:smaller }
+  pre.smallformat  { font-family:inherit; font-size:smaller }
+  pre.smallexample { font-size:smaller }
+  pre.smalllisp    { font-size:smaller }
+--></style>
+</head>
+<body>
+<h1 class="settitle">Porting libstdc++-v3</h1>
+<div class="node">
+<p><hr>
+Node:&nbsp;<a name="Top">Top</a>,
+Next:&nbsp;<a rel="next" accesskey="n" href="#Operating%20system">Operating system</a>,
+Up:&nbsp;<a rel="up" accesskey="u" href="#dir">(dir)</a>
+<br>
+</div>
+
+The documentation in this file was removed, because it is licencensed
+under a non DFSG conforming licencse.
+
+</body></html>
--- gcc-6-6.3.0.orig/debian/reduce-test-diff.awk
+++ gcc-6-6.3.0/debian/reduce-test-diff.awk
@@ -0,0 +1,33 @@
+#! /usr/bin/gawk -f
+
+BEGIN {
+	skip=0
+	warn=0
+}
+
+/^-(FAIL|ERROR|UNRESOLVED|WARNING)/ {
+	next
+}
+
+# only compare gcc, g++, g77 and objc results
+/=== treelang tests ===/ {
+	skip=1
+}
+
+# omit extra files appended to test-summary
+/^\+Compiler version/ {
+	skip=1
+}
+
+skip == 0 {
+	print
+	next
+}
+
+/^\+(FAIL|ERROR|UNRESOLVED|WARNING)/ {
+	warn=1
+}
+
+END {
+	exit warn
+}
--- gcc-6-6.3.0.orig/debian/relink
+++ gcc-6-6.3.0/debian/relink
@@ -0,0 +1,74 @@
+#! /bin/sh
+#
+# Relink GNAT utilities using the shared library
+#
+
+set -e
+
+pwd=`pwd`
+
+# why?
+chmod a-w build/gcc/ada/rts/*.ali
+
+rm -rf tmp
+ln -s $pwd/build/gcc/ada/rts/libgnat.so.1 tmp/libgnat.so
+
+LD_LIBRARY_PATH=$pwd/tmp
+export LD_LIBRARY_PATH
+
+PATH=$pwd/debian:$pwd/tmp:$PATH
+export PATH
+
+echo "#! /bin/sh" > tmp/dgcc
+echo "$pwd/build/gcc/xgcc -B$pwd/build/gcc/ "'"$@"' >> tmp/dgcc
+chmod 755 tmp/dgcc
+
+echo "#! /bin/sh" > tmp/dgnatlink
+echo "$pwd/build/gcc/gnatlink --GCC=dgcc "'"$@"' >> tmp/dgnatlink
+chmod 755 tmp/dgnatlink
+
+GMCMD="$pwd/build/gcc/gnatmake -I- -Irts -I. -a -m --GNATBIND=$pwd/build/gcc/gnatbind --GNATLINK=dgnatlink --GCC=dgcc"
+
+#cd $pwd/build/gcc/ada
+#make CFLAGS="-O2" CC="../xgcc -B../" STAGE_PREFIX=../ a-link.o a-gmem.o
+#cd $pwd
+
+[ -f build/gcc/gnatmake.old ] || cp -p build/gcc/gnatmake build/gcc/gnatmake.old
+[ -f build/gcc/gnatlink.old ] || cp -p build/gcc/gnatlink build/gcc/gnatlink.old
+
+make -C build/gcc/ada \
+	CFLAGS='-gnatp -gnata -O2 ' \
+	ADA_INCLUDES="-I." \
+	CC="../xgcc -B../" \
+	STAGE_PREFIX=../ \
+    ../gnatmake ../gnatlink
+
+mv gnatmake bgnatmake
+mv gnatlink bgnatlink
+exit 0
+
+cd build/gcc/ada
+for i in ../gnatchop ../gnatcmd \
+    ../gnatkr ../gnatlbr \
+    ../gnatls ../gnatmake \
+    ../gnatprep ../gnatpsys \
+    ../gnatxref ../gnatfind
+do
+  rm -f $i
+  $GMCMD -O2 -gnatp -o $i `basename $i`.adb -largs -L..
+done
+
+rm -f ../gnatmem
+$GMCMD -O2 -gnatp -o ../gnatmem gnatmem.adb -largs -L.. a-gmem.o
+$GMCMD -O2 -gnatp -o ../gnatlink gnatlink -largs -L.. a-link.o
+rm -f ../gnatpsta
+
+make CFLAGS="-O2" CC="../xgcc -B../" a-gettty.o a-deftar.o
+$GMCMD -O2 -gnatp -o ../gnatpsta gnatpsta -largs -L.. a-gettty.o a-deftar.o
+rm -f ../gnatbl
+
+make CFLAGS="-O2" CC="../xgcc -B../" gnatbl.o
+../xgcc -B../ -o ../gnatbl gnatbl.o -L.. -lgnat
+rm -f ../bgnatmake ../bgnatlink ../debian/dgcc ../debian/dgnatlink
+
+chmod +w rts/*.ali
--- gcc-6-6.3.0.orig/debian/rules
+++ gcc-6-6.3.0/debian/rules
@@ -0,0 +1,83 @@
+#! /usr/bin/make -f
+# -*- makefile -*-
+# Build rules for gcc (>= 2.95) and gcc-snapshot
+# Targets found in this makefile:
+#	- unpack tarballs
+#	- patch sources
+#	- (re)create the control file
+#	- create a debian/rules.parameters file, which is included
+#	  by debian/rules2
+# All other targets are passed to the debian/rules2 file
+
+# Uncomment this to turn on verbose mode.
+#export DH_VERBOSE=1
+
+unexport LANG LC_ALL LC_CTYPE LC_COLLATE LC_TIME LC_NUMERIC LC_MESSAGES
+
+default: build
+
+include debian/rules.defs
+include debian/rules.unpack
+include debian/rules.patch
+
+control: $(control_dependencies)
+	-mkdir -p $(stampdir)
+	$(MAKE) -f debian/rules.conf $@
+
+configure: control $(unpack_stamp) $(patch_stamp)
+	$(MAKE) -f debian/rules2 $@
+
+pre-build:
+#ifneq (,$(filter $(distrelease),squeeze sid))
+#ifeq (,$(filter $(DEB_TARGET_ARCH),amd64 i386))
+#	@echo explicitely fail the build for $(DEB_TARGET_ARCH)
+#	@echo no bug report required. please ask the port maintainers if they support gcc-4.5.
+#	false
+#endif
+#endif
+
+build: pre-build control
+	$(MAKE) $(NJOBS) -f debian/rules2 $@
+build-arch: pre-build control
+	$(MAKE) $(NJOBS) -f debian/rules2 $@
+build-indep: pre-build control
+	$(MAKE) $(NJOBS) -f debian/rules2 $@
+
+check: $(check_stamp)
+$(check_stamp): $(build_stamp)
+	$(MAKE) -f debian/rules2 $@
+
+clean:
+	rm -rf $(stampdir)
+# remove temporary dirs used for unpacking
+	rm -rf $(gcc_srcdir) $(gdc_srcdir)
+	-$(MAKE) -f debian/rules2 $@
+	rm -rf $(srcdir)* $(builddir)* debian/tmp* html
+	rm -f bootstrap-* first-move-stamp
+	rm -f debian/*.tmp
+	rm -f debian/soname-cache
+	find debian -name '.#*' | xargs -r rm -f
+	rm -f $(series_file)*
+	dh_clean
+
+install:
+	$(MAKE) -f debian/rules2 $@
+
+html-docs doxygen-docs update-doxygen-docs update-ada-files xxx:
+	$(MAKE) -f debian/rules2 $@
+
+binary-indep binary-arch binary:
+	$(MAKE) -f debian/rules2 $@
+
+source diff:
+	@echo >&2 'source and diff are obsolete - use dpkg-source -b'; false
+
+release:
+	foo=$(shell basename $(CURDIR)); \
+		if [ "$$foo" != "gcc-3.4" ]; then \
+			find -name CVS -o -name .cvsignore -o -name '.#*' | \
+				xargs rm -rf; \
+		fi
+
+.NOTPARALLEL:
+.PHONY: build clean binary-indep binary-arch binary release
--- gcc-6-6.3.0.orig/debian/rules.conf
+++ gcc-6-6.3.0/debian/rules.conf
@@ -0,0 +1,1483 @@
+# -*- makefile -*-
+# rules.conf
+#	- used to build debian/control and debian/rules.parameters
+#	- assumes unpacked sources
+
+include debian/rules.defs
+include debian/rules.sonames
+
+# manual ...
+ifeq ($(DEB_TARGET_GNU_CPU), $(findstring $(DEB_TARGET_GNU_CPU),hppa m68k))
+  ifeq ($(DEB_TARGET_ARCH),m68k)
+    GCC_SONAME := 2
+  endif
+  ifeq ($(DEB_TARGET_ARCH),hppa)
+    GCC_SONAME := 4
+  endif
+else
+  GCC_SONAME := 1
+endif
+DEB_LIBGCC_SOVERSION := $(DEB_SOEVERSION)
+DEB_LIBGCC_VERSION := $(DEB_EVERSION)
+
+_soname_map = gcc=$(GCC_SONAME) stdc++=$(CXX_SONAME) gomp=$(GOMP_SONAME) \
+	ssp=$(SSP_SONAME) gfortran=$(FORTRAN_SONAME) \
+	itm=$(ITM_SONAME) objc=$(OBJC_SONAME) quadmath=$(QUADMATH_SONAME) \
+	go=$(GO_SONAME) backtrace=$(BTRACE_SONAME) \
+	atomic=$(ATOMIC_SONAME) asan=$(ASAN_SONAME) lsan=$(LSAN_SONAME) \
+	tsan=$(TSAN_SONAME) ubsan=$(UBSAN_SONAME) \
+	vtv=$(VTV_SONAME) cilkrts=$(CILKRTS_SONAME) mpx=$(MPX_SONAME) \
+	gphobos=$(GPHOBOS_SONAME)
+_soname = $(patsubst $(1)=%,%,$(filter $(1)=%,$(_soname_map)))
+
+rel_on_dev := $(if $(cross_lib_arch),>=,=)
+# $(call _lib_name,<name>,<biarch>,<ext>)
+_lib_name = $(subst $(SPACE),, \
+  lib$(2)$(1) \
+  $(if $(filter dev,$(3)),,$(call _soname,$(1))) \
+  $(if $(or $(filter $(3),dev),$(and $(filter $(3),dbg),$(filter $(1),stdc++))),-$(BASE_VERSION)) \
+  $(if $(3),-$(3))$(LS)$(AQ))
+# $(call _lib_vers,<ext>,<vers>) 
+_lib_vers = ($(if $(filter $(1),dev),$(rel_on_dev),>=) $(2))
+
+# Helper to generate biarch/triarch dependencies.
+# For example, $(eval $(call gen_multilib_deps,gomp)) will create the
+# libgompbiarch variable, and make it contains the libgompbiarch{32,64,n32}
+# variables if biarch{32,64,n32} is set to yes.
+
+define gen_multilib_deps
+  lib$1biarch64$2  := $(call _lib_name,$(1),64,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarch32$2  := $(call _lib_name,$(1),32,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchn32$2 := $(call _lib_name,$(1),n32,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchx32$2 := $(call _lib_name,$(1),x32,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchhf$2  := $(call _lib_name,$(1),hf,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchsf$2  := $(call _lib_name,$(1),sf,$(2)) $(call _lib_vers,$(2),$(3))
+  ifeq ($$(biarch64),yes)
+    lib$1biarch$2 := $$(lib$1biarch64$2)
+  endif
+  ifeq ($$(biarch32),yes)
+    ifeq ($$(biarch64),yes)
+      lib$1biarch$2 := $$(lib$1biarch64$2), $$(lib$1biarch32$2)
+    else
+      lib$1biarch$2 := $$(lib$1biarch32$2)
+    endif
+  endif
+  ifeq ($$(biarchx32),yes)
+    ifeq ($1,mpx)
+      ifeq ($$(biarch64),yes)
+        lib$1biarch$2 := $$(lib$1biarch64$2)
+      else ifeq ($$(biarch32),yes)
+        lib$1biarch$2 := $$(lib$1biarch32$2)
+      else
+        lib$1biarch$2 :=
+      endif
+    else ifeq ($$(biarch64),yes)
+      lib$1biarch$2 := $$(lib$1biarch64$2), $$(lib$1biarchx32$2)
+    else ifeq ($$(biarch32),yes)
+      lib$1biarch$2 := $$(lib$1biarch32$2), $$(lib$1biarchx32$2)
+    else
+      lib$1biarch$2 := $$(lib$1biarchx32$2)
+    endif
+  endif
+  ifeq ($$(biarchn32),yes)
+    ifeq ($$(biarch64),yes)
+      lib$1biarch$2 := $$(lib$1biarch64$2), $$(lib$1biarchn32$2)
+    else ifeq ($$(biarch32),yes)
+      lib$1biarch$2 := $$(lib$1biarch32$2), $$(lib$1biarchn32$2)
+    else
+      lib$1biarch$2 := $$(lib$1biarchn32$2)
+    endif
+  endif
+  ifeq ($$(biarchhf),yes)
+    lib$1biarch$2 := $$(lib$1biarchhf$2) | $(call _lib_name,$(1),hf,$(2))
+  endif
+  ifeq ($$(biarchsf),yes)
+    lib$1biarch$2 := $$(lib$1biarchsf$2) | $(call _lib_name,$(1),sf,$(2))
+  endif
+endef
+ifeq ($(with_shared_libgcc),yes)
+  LIBGCC_DEP := libgcc$(GCC_SONAME)$(LS)$(AQ) (>= $(DEB_LIBGCC_VERSION))
+  $(eval $(call gen_multilib_deps,gcc,,$(DEB_LIBGCC_VERSION)))
+endif
+LIBGCC_DEV_DEP := libgcc-$(BASE_VERSION)-dev$(LS)$(AQ) ($(rel_on_dev) $(DEB_VERSION))
+$(foreach x,stdc++ gomp ssp gfortran itm objc atomic asan lsan mpx ubsan quadmath go vtv cilkrts, \
+	$(eval $(call gen_multilib_deps,$(x),,$$$${gcc:Version})))
+$(foreach x,gcc stdc++ gfortran objc go gphobos, \
+	$(eval $(call gen_multilib_deps,$(x),dev,$$$${gcc:Version})))
+$(foreach x,gcc stdc++ gfortran objc go gphobos, \
+	$(eval $(call gen_multilib_deps,$(x),dbg,$$$${gcc:Version})))
+
+# Helper to generate _no_archs variables.
+# For example, $(eval $(call gen_no_archs,java)) will create the java_no_archs
+# variable, using the java_no_cpu and java_no_systems variables.
+define gen_no_archs
+  $1_no_archs :=
+  ifneq (,$$($1_no_cpus))
+    $1_no_archs += $$(foreach cpu,$$(filter-out i386 amd64 alpha arm,$$($1_no_cpus)),!$$(cpu))
+    ifneq (,$$(filter i386,$$($1_no_cpus)))
+      $1_no_archs += !i386 !hurd-i386 !kfreebsd-i386
+    endif
+    ifneq (,$$(filter amd64,$$($1_no_cpus)))
+      $1_no_archs += !amd64 !kfreebsd-amd64
+    endif
+    ifneq (,$$(filter alpha,$$($1_no_cpus)))
+      $1_no_archs += !alpha !hurd-alpha
+    endif
+    ifneq (,$$(filter arm,$$($1_no_cpus)))
+      $1_no_archs += !arm !armel !armhf
+    endif
+    ifneq (,$$(strip $3))
+      $1_no_systems_tmp := $$(subst $$(SPACE)gnu$$(SPACE),$$(SPACE)hurd-gnu$$(SPACE),$$(SPACE)$3$$(SPACE))
+      $1_no_archs += $$(foreach cpu,$$($1_no_cpus),$$(foreach system,$$($1_no_systems_tmp),!$$(subst gnu,$$(cpu),$$(system))))
+    endif
+  endif
+  ifneq (,$$($1_no_systems))
+    $1_no_systems_tmp := $$(subst $$(SPACE)gnu$$(SPACE),$$(SPACE)hurd-gnu$$(SPACE),$$(SPACE)$$($1_no_systems)$$(SPACE))
+    $1_no_archs += $$(foreach system,$$($1_no_systems_tmp),$$(foreach cpu,$2,!$$(subst gnu,$$(cpu),$$(system))))
+  endif
+  $1_no_archs := $$(strip $$($1_no_archs))
+endef
+base_deb_cpus := amd64 i386 alpha
+base_deb_systems :=
+$(foreach x,ada java java_plugin fortran libgphobos libgc check locale,$(eval $(call gen_no_archs,$(x),$(base_deb_cpus),$(base_deb_systems))))
+linux_no_archs := !hurd-any !kfreebsd-any
+
+GCC_VERSION := $(strip $(shell cat $(firstword $(wildcard $(srcdir)/gcc/FULL-VER $(srcdir)/gcc/BASE-VER))))
+NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \
+	awk -F. '{OFS="."; $$2 += 1; $$3=0; print}')
+GCC_MAJOR_VERSION := $(shell echo $(GCC_VERSION)   | sed -r 's/([0-9])\.[0-9]\.[0-9]/\1/')
+GCC_MINOR_VERSION := $(shell echo $(GCC_VERSION)   | sed -r 's/[0-9]\.([0-9])\.[0-9]/\1/')
+GCC_RELEASE_VERSION := $(shell echo $(GCC_VERSION) | sed -r 's/[0-9]\.[0-9]\.([0-9])/\1/')
+NEXT_GCC_MAJOR_VERSION := $(shell expr $(echo $(GCC_MAJOR_VERSION)) + 1)
+NEXT_GCC_MINOR_VERSION := $(shell expr $(echo $(GCC_MINOR_VERSION)) + 1)
+NEXT_GCC_RELEASE_VERSION := $(shell expr $(echo $(GCC_MAJOR_VERSION)) + 1)
+
+ifeq ($(single_package),yes)
+  BASE_VERSION := $(shell echo $(GCC_VERSION) | sed -e 's/\([1-9]*\).*/\1/')
+endif
+
+GCC_SOURCE_VERSION := $(shell echo $(DEB_VERSION) | sed 's/-.*//')
+NEXT_GCC_SOURCE_VERSION := $(shell echo $(GCC_SOURCE_VERSION) | \
+	awk -F. '{OFS="."; $$2 += 1; $$3=0; print}')
+
+MAINTAINER = Debian GCC Maintainers <debian-gcc@lists.debian.org>
+ifeq ($(distribution),Ubuntu)
+  ifneq (,$(findstring $(PKGSOURCE),gnat gdc))
+    MAINTAINER = Ubuntu MOTU Developers <ubuntu-motu@lists.ubuntu.com>
+  else
+    MAINTAINER = Ubuntu Core developers <ubuntu-devel-discuss@lists.ubuntu.com>
+  endif
+endif
+
+UPLOADERS = Matthias Klose <doko@debian.org>
+ifneq (,$(findstring $(PKGSOURCE),gnat))
+  UPLOADERS = Ludovic Brenta <lbrenta@debian.org>
+endif
+ifneq (,$(findstring $(PKGSOURCE),gdc))
+  UPLOADERS = Iain Buclaw <ibuclaw@ubuntu.com>, Matthias Klose <doko@debian.org>
+endif
+
+DPKGV = 1.14.15
+ifeq ($(with_multiarch_lib),yes)
+  DPKGV = 1.16.0~ubuntu4
+endif
+ifeq ($(multiarch_stage1),yes)
+  DPKGV = 1.16.0~ubuntu4
+endif
+ifeq (,$(filter $(distrelease),lenny etch squeeze wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring saucy trusty utopic))
+  DPKGV = 1.17.14
+endif
+DPKG_BUILD_DEP = dpkg-dev (>= $(DPKGV)),
+
+ifeq ($(DEB_HOST_ARCH),$(DEB_TARGET_ARCH))
+  TARGET_QUAL = :$(DEB_TARGET_ARCH)
+endif
+
+# The binutils version needed.
+# The oldest suitable versions for the various platforms can be found in
+# INSTALL/specific.html ; we take a tighter dependency if possible to be on
+# the safe side (something like newest( version in stable, versions for the
+# various platforms in INSTALL/specific.html) ).
+# We need binutils (>= 2.19.1) for a new dwarf unwind expression opcode.
+# See http://gcc.gnu.org/ml/gcc-patches/2008-09/msg01713.html
+ifeq ($(trunk_build),yes)
+  BINUTILSBDV = 2.23
+else
+  BINUTILSBDV = 2.22
+  ifneq (,$(filter $(distrelease),vivid))
+    BINUTILSBDV = 2.25-3~
+  else ifneq (,$(filter $(distrelease),jessie))
+    BINUTILSBDV = 2.25-7~
+  else ifneq (,$(filter $(distrelease),xenial))
+    BINUTILSBDV = 2.26.1
+  else ifneq (,$(filter $(distrelease),sid stretch zesty))
+    BINUTILSBDV = 2.28
+  endif
+endif
+ifeq ($(DEB_CROSS),yes)
+  BINUTILS_BUILD_DEP = binutils$(TS)$(NT) (>= $(BINUTILSBDV)), binutils-multiarch$(NT) (>= $(BINUTILSBDV))
+  BINUTILSV := $(shell dpkg -l binutils$(TS) \
+			| awk '/^ii/{print $$3;exit}' | sed 's/-.*//')
+else
+  BINUTILS_BUILD_DEP = binutils$(NT) (>= $(BINUTILSBDV)) | binutils-multiarch$(NT) (>= $(BINUTILSBDV))
+  ifneq (,$(findstring cross-build-,$(build_type)))
+    BINUTILSV := $(shell dpkg -l binutils$(TS) \
+			| awk '/^ii/{print $$3;exit}' | sed 's/-.*//')
+  else
+    BINUTILSV := $(shell dpkg -l binutils binutils-multiarch \
+			| awk '/^ii/{print $$3;exit}' | sed 's/-.*//')
+  endif
+endif
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  ifeq (,$(filter gccgo% gcj% gnat%, $(PKGSOURCE)))
+    ifeq ($(hppa64_archs),hppa)
+      BINUTILS_BUILD_DEP += , binutils-hppa64$(NT) (>= $(BINUTILSBDV)) [$(hppa64_archs)]
+    else
+      BINUTILS_BUILD_DEP += , binutils-hppa64-linux-gnu$(NT) (>= $(BINUTILSBDV)) [$(hppa64_archs)]
+    endif
+  endif
+endif
+ifeq (,$(BINUTILSV))
+  BINUTILSV := $(BINUTILSBDV)
+endif
+
+# FIXME; stripping doesn't work with gold
+#BINUTILS_BUILD_DEP += , binutils-gold (>= $(BINUTILSV)) [$(gold_archs)]
+
+# libc-dev dependencies
+libc_ver := 2.11
+libc_dev_ver := $(libc_ver)
+ifeq ($(with_multiarch_lib),yes)
+  ifeq ($(derivative),Debian)
+    libc_dev_ver := 2.13-5
+  else
+    libc_dev_ver := 2.13-0ubuntu6
+  endif
+endif
+# first set LIBC_DEP/LIBC_DEV_DEP for native builds only
+ifeq ($(DEB_TARGET_ARCH_OS),linux)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),alpha ia64))
+    LIBC_DEP = libc6.1
+  else
+    LIBC_DEP = libc6
+  endif
+  ifneq (,$(findstring musl-linux-,$(DEB_TARGET_ARCH)))
+    LIBC_DEP = musl
+    libc_ver = 0.9
+    libc_dev_ver = 0.9
+  endif
+else
+  ifeq ($(DEB_TARGET_ARCH_OS),hurd)
+    LIBC_DEP = libc0.3
+  endif
+  ifeq ($(DEB_TARGET_ARCH_OS),kfreebsd)
+    LIBC_DEP = libc0.1
+  endif
+  ifeq ($(DEB_TARGET_ARCH),uclibc)
+       LIBC_DEP = libuclibc
+  endif
+endif
+LIBC_DEV_DEP := $(LIBC_DEP)-dev
+
+# this is about Debian archs name, *NOT* GNU target triplet
+biarch_deb_map := \
+	i386=amd64 amd64=i386 \
+	mips=mips64 mipsel=mips64 \
+	powerpc=ppc64 ppc64=powerpc \
+	sparc=sparc64 sparc64=sparc\
+	s390=s390x s390x=s390 \
+	kfreebsd-amd64=i386 \
+	armel=armhf \
+	armhf=armel
+biarch_deb_arch := $(patsubst $(DEB_TARGET_ARCH)=%,%, \
+	$(filter $(DEB_TARGET_ARCH)=%,$(biarch_deb_map)))
+
+LIBC_BIARCH_DEP :=
+LIBC_BIARCH_DEV_DEP :=
+ifneq (,$(findstring yes,$(biarch64) $(biarch32) $(biarchn32) $(biarchx32)$(biarchhf)$(biarchsf)))
+  LIBC_BIARCH_DEP := $${shlibs:Depends}
+  LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-$(biarch_deb_arch)$(LS)$(AQ) (>= $(libc_ver))
+  # amd64, x32, i386
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),amd64 x32 i386))
+  ifeq ($(biarch64)$(biarch32),yesyes)
+    LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-amd64$(LS)$(AQ) (>= $(libc_ver)), $(LIBC_DEV_DEP)-i386$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarch64)$(biarchx32),yesyes)
+    LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-amd64$(LS)$(AQ) (>= $(libc_ver)), $(LIBC_DEV_DEP)-x32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarch32)$(biarchx32),yesyes)
+    LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-i386$(LS)$(AQ) (>= $(libc_ver)), $(LIBC_DEV_DEP)-x32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  endif
+  # mips*
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),mips mipsel mipsn32 mipsn32el mips64 mips64el))
+  ifeq ($(biarchn32)$(biarch32),yesyes)
+      LIBC_BIARCH_DEV_DEP := libc6-dev-mips32$(LS)$(AQ) (>= $(libc_ver)), libc6-dev-mipsn32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarch64)$(biarch32),yesyes)
+      triarch := $(COMMA)$(SPACE)
+      LIBC_BIARCH_DEV_DEP := libc6-dev-mips32$(LS)$(AQ) (>= $(libc_ver)), libc6-dev-mips64$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarchn32)$(biarch64),yesyes)
+      triarch := $(COMMA)$(SPACE)
+      LIBC_BIARCH_DEV_DEP := libc6-dev-mips64$(LS)$(AQ) (>= $(libc_ver)), libc6-dev-mipsn32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  endif
+
+  ifeq ($(biarchhf),yes)
+    LIBC_BIARCH_DEP := $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ) (>= $(libc_ver))
+    LIBC_BIARCH_DEP += | $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+    LIBC_BIARCH_DEV_DEP += | $(LIBC_DEV_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+  endif
+  ifeq ($(biarchsf),yes)
+    LIBC_BIARCH_DEP := $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ) (>= $(libc_ver))
+    LIBC_BIARCH_DEP += | $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+    LIBC_BIARCH_DEV_DEP += | $(LIBC_DEV_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+  endif
+endif
+
+# now add the cross suffix and required version
+LIBC_DEP := $(LIBC_DEP)$(LS)$(AQ)
+LIBC_DEV_DEP := $(LIBC_DEV_DEP)$(LS)$(AQ) (>= $(libc_dev_ver))
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  LIBC_DBG_DEP = libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg,
+endif
+
+# TODO: make this automatic, there must be a better way to define LIBC_DEP.
+ifneq ($(DEB_CROSS),yes)
+  LIBC_BUILD_DEP = libc6.1-dev (>= $(libc_dev_ver)) [alpha ia64] | libc0.3-dev (>= $(libc_dev_ver)) [hurd-i386] | libc0.1-dev (>= $(libc_dev_ver)) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= $(libc_dev_ver))
+  ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick natty oneiric))
+    LIBC_BUILD_DEP += , libc6-dev (>= 2.13-31) [armel armhf]
+  endif
+  LIBC_BIARCH_BUILD_DEP = libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 mipsn32 mipsn32el mips64 mips64el s390x sparc64 x32], libn32gcc1 [mips mipsel mips64 mips64el], lib64gcc1 [i386 mips mipsel mipsn32 mipsn32el powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel mipsn32 mipsn32el], libc6-dev-mipsn32 [mips mipsel mips64 mips64el], libc6-dev-mips32 [mipsn32 mipsn32el mips64 mips64el],
+  ifneq (,$(findstring amd64,$(biarchx32archs)))
+  LIBC_BIARCH_BUILD_DEP += libc6-dev-x32 [amd64 i386], libx32gcc1 [amd64 i386],
+endif
+ifneq (,$(findstring armel,$(biarchhfarchs)))
+  LIBC_BIARCH_BUILD_DEP += libc6-dev-armhf [armel], libhfgcc1 [armel],
+endif
+ifneq (,$(findstring armhf,$(biarchsfarchs)))
+  LIBC_BIARCH_BUILD_DEP += libc6-dev-armel [armhf], libsfgcc1 [armhf],
+endif
+else
+  LIBC_BUILD_DEP = $(LIBC_DEV_DEP),
+  ifneq ($(LIBC_BIARCH_DEV_DEP),)
+    LIBC_BIARCH_BUILD_DEP = $(LIBC_BIARCH_DEV_DEP),
+  else
+    LIBC_BIARCH_BUILD_DEP =
+  endif
+endif
+
+# needed for the include/asm symlink to run the testsuite for
+# non default multilibs
+ifneq (,$(multilib_archs))
+  GCC_MULTILIB_BUILD_DEP = g++-multilib [$(multilib_archs)]$(pf_ncross),
+endif
+GCC_MULTILIB_BUILD_DEP += g++-6 [arm64]$(pf_ncross),
+
+LIBUNWIND_DEV_DEP := libunwind7-dev$(LS)$(AQ) (>= 0.98.5-6)
+LIBUNWIND_BUILD_DEP := $(LIBUNWIND_DEV_DEP) [ia64],
+LIBATOMIC_OPS_BUILD_DEP := libatomic-ops-dev$(LS) [ia64],
+ifneq ($(DEB_TARGET_ARCH),ia64)
+  LIBUNWIND_DEV_DEP := # nothing
+endif
+
+ifneq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick natty))
+  GMP_BUILD_DEP = libgmp3-dev | libgmp-dev (>= 2:5.0.1~),
+  MPFR_BUILD_DEP = libmpfr-dev,
+else
+  GMP_BUILD_DEP = libgmp-dev (>= 2:5.0.1~),
+  MPFR_BUILD_DEP = libmpfr-dev (>= 3.0.0-9~),
+endif
+
+ISL_BUILD_DEP = libisl-dev,
+ifneq (,$(filter $(distrelease),jessie stretch sid experimental))
+  ISL_BUILD_DEP = libisl-dev (>= 0.14),
+endif
+
+ifneq (,$(filter $(distrelease),lenny etch squeeze wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring))
+  MPC_BUILD_DEP = libmpc-dev,
+else
+  MPC_BUILD_DEP = libmpc-dev (>= 1.0),
+endif
+
+SOURCE_BUILD_DEP :=
+ifeq (,$(findstring gcc,$(PKGSOURCE)))
+  SOURCE_BUILD_DEP := gcc-$(BASE_VERSION)-source (>= $(GCC_SOURCE_VERSION)), gcc-$(BASE_VERSION)-source (<< $(NEXT_GCC_SOURCE_VERSION)),
+endif
+
+CHECK_BUILD_DEP := dejagnu [$(check_no_archs)],
+
+AUTO_BUILD_DEP := m4, libtool,
+AUTO_BUILD_DEP += autoconf2.64,
+
+ifeq (,$(filter $(distrelease),lenny etch squeeze wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring saucy trusty))
+  SDT_BUILD_DEP = systemtap-sdt-dev [linux-any kfreebsd-any hurd-any],
+endif
+
+# ensure that the common libs, built from the next GCC version are available
+ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+  ifneq ($(with_common_libs),yes)
+    BASE_BUILD_DEP = gcc-6-base,
+  endif
+endif
+
+PHOBOS_BUILD_DEP = lib32z1-dev [amd64 kfreebsd-amd64], lib64z1-dev [i386],
+ifeq ($(derivative),Ubuntu)
+  PHOBOS_BUILD_DEP += libx32z1-dev [amd64 kfreebsd-amd64 i386],
+endif
+
+ifneq ($(DEB_CROSS),yes)
+# all archs for which to create b-d's
+any_archs = alpha amd64 armel armhf arm64 i386 mips mipsel mips64 mips64el powerpc ppc64 ppc64el m68k sh4 sparc64 s390x x32
+arch_gnutype_map = \
+	alpha=alpha-linux-gnu \
+	amd64=x86-64-linux-gnu \
+	armel=arm-linux-gnueabi \
+	armhf=arm-linux-gnueabihf \
+	arm64=aarch64-linux-gnu \
+	i386=i686-linux-gnu \
+	mips=mips-linux-gnu \
+	mipsel=mipsel-linux-gnu \
+	mips64=mips64-linux-gnuabi64 \
+	mips64el=mips64el-linux-gnuabi64 \
+	powerpc=powerpc-linux-gnu \
+	ppc64=powerpc64-linux-gnu \
+	ppc64el=powerpc64le-linux-gnu \
+	m68k=m68k-linux-gnu \
+	sh4=sh4-linux-gnu \
+	sparc64=sparc64-linux-gnu \
+	s390x=s390x-linux-gnu \
+	x32=x86-64-linux-gnux32
+
+_element = $(filter $1=%,$(arch_gnutype_map))
+_gnu_type = $(subst $1=,,$(filter $1=%,$(arch_gnutype_map)))
+
+ifneq (,$(filter $(distrelease),lenny etch squeeze wheezy wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring saucy trusty utopic vivid))
+  DEBHELPER_BUILD_DEP = debhelper (>= 9),
+  TARGET_TOOL_BUILD_DEP = bash, # non-empty line
+  pf_cross =
+  pf_ncross =
+else
+  DEBHELPER_BUILD_DEP = debhelper (>= 9.20141010),
+  TARGET_TOOL_BUILD_DEP = \
+	$(foreach a, $(any_archs), \
+	  g++-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>, \
+	  $(if $(filter $(a), avr),, \
+	    gobjc-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  gfortran-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>, \
+	  $(if $(filter $(a), avr),, \
+	    gcj-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  $(if $(filter $(a), s390 sh4),, \
+	    gdc-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  $(if $(filter $(a), hppa m68k sh4),, \
+	    gccgo-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  $(if $(filter $(a), m68k mips64 powerpcspe sh4 sparc64 x32),, \
+	    gnat-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	)
+  pf_cross = $(SPACE)<cross>
+  pf_ncross = $(SPACE)<!cross>
+  NT = :native
+endif
+
+JAVA_BUILD_DEP := zlib1g-dev, libantlr-java, python$(NT), libffi-dev,
+
+ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+  bd_java_archs =
+else ifeq ($(single_package)-$(with_java),yes-yes)
+  bd_java_archs =
+else
+  bd_java_archs = $(if $(java_no_archs),$(EMPTY) [$(java_no_archs)])
+endif
+
+ifneq (,$(java_awt_peers))
+  JAVA_BUILD_DEP += fastjar$(bd_java_archs), libmagic-dev$(bd_java_archs),
+  JAVA_BUILD_DEP += libecj-java (>= 3.3.0-2)$(bd_java_archs), zip$(bd_java_archs),
+  ifeq ($(with_java_maintainer_mode),yes)
+    # gcj-6 needed for gjavah-6.
+    JAVA_BUILD_DEP += gcj-6$(bd_java_archs), ecj (>= 3.3.0-2)$(bd_java_archs),
+  endif
+  JAVA_BUILD_DEP += libasound2-dev [$(java_no_archs) $(linux_no_archs)],
+  ifneq (,$(findstring gtk,$(java_awt_peers)))
+    JAVA_BUILD_DEP += libxtst-dev$(bd_java_archs), libxt-dev$(bd_java_archs), libgtk2.0-dev (>= 2.4.4-2)$(bd_java_archs), libart-2.0-dev$(bd_java_archs), libcairo2-dev$(bd_java_archs),
+  endif
+  ifneq (,$(findstring qt,$(java_awt_peers)))
+    JAVA_BUILD_DEP += libqt4-dev (>= 4.1.0)$(bd_java_archs),
+  endif
+  # gconf peer, disabled by default
+  #JAVA_BUILD_DEP += libgconf2-dev$(bd_java_archs),
+  # gstreamer peer
+  #JAVA_BUILD_DEP += libgstreamer-plugins-base0.10-dev$(bd_java_archs),
+endif
+ifneq ($(with_standalone_gcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    JAVA_BUILD_DEP += $(SOURCE_BUILD_DEP)
+  endif
+endif
+#JAVA_BUILD_INDEP := gcj-$(BASE_VERSION)-jdk
+ifeq ($(single_package),yes)
+  LIBSTDCXX_BUILD_INDEP = doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base
+  LIBSTDCXX_BUILD_INDEP +=, xsltproc, libxml2-utils, docbook-xsl-ns
+  JAVA_BUILD_INDEP :=
+endif
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+    JAVA_BUILD_DEP :=
+    JAVA_BUILD_INDEP :=
+  endif
+endif
+
+ifeq ($(with_ecj),yes)
+  ifneq (./,$(dir $(ecj_jar)))
+    ECJ_DEP = libecj-java (>= 3.5.1)
+  endif
+else
+  ECJ_DEP = ecj, libecj-java (>= 3.5.1)
+  ECJ_DEP = ecj-gcj, libecj-java-gcj (>= 3.5.1)
+  ifeq ($(with_external_ecj1),yes)
+    ECJ_DEP +=, ecj1
+  endif
+endif
+
+ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+  LIBSTDCXX_BUILD_INDEP = doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base
+  ifeq (,$(filter $(distrelease),lenny etch dapper hardy jaunty karmic lucid maverick natty oneiric))
+    LIBSTDCXX_BUILD_INDEP +=, xsltproc, libxml2-utils, docbook-xsl-ns
+  endif
+  JAVA_BUILD_INDEP :=, $(JAVA_BUILD_INDEP)
+endif
+
+GO_BUILD_DEP := netbase,
+
+# try to build with itself, or with the last version
+ifneq (,$(filter $(distrelease), jessie))
+  gnat_build_dep := gnat-4.9$(NT) [$(ada_no_archs)], g++-4.9$(NT)
+else ifneq (,$(filter $(distrelease), wheezy precise trusty wily xenial))
+  gnat_build_dep := gnat-5$(NT) [$(ada_no_archs)], g++-5$(NT)
+else ifneq (,$(filter $(distrelease), stretch sid yakkety zesty))
+  gnat_build_dep := gnat-6$(NT) [$(ada_no_archs)], g++-6$(NT)
+else ifneq (,$(filter $(distrelease), squeeze lucid))
+  gnat_build_dep :=
+else
+  gnat_build_dep := gnat$(NT) [$(ada_no_archs)]
+endif
+
+ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+  ifneq ($(with_separate_gnat),yes)
+    # Build gnat as part of the combined gcc-x.y source package.  Do not fail
+    # if gnat is not present on unsupported architectures; the build scripts
+    # will not use gnat anyway.
+    GNAT_BUILD_DEP := $(gnat_build_dep),
+  endif
+else ifeq ($(single_package),yes)
+  # Ditto, as part of the gcc-snapshot package.
+  GNAT_BUILD_DEP := $(gnat_build_dep),
+else ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+  # Special source package just for gnat. Fail early if gnat is not present,
+  # rather than waste CPU cycles and fail later.
+  # Bootstrap step needs a gnatgcc symbolic link.
+  GNAT_BUILD_DEP := $(gnat_build_dep),
+  GNAT_BUILD_DEP += $(SOURCE_BUILD_DEP)
+  JAVA_BUILD_DEP :=
+  JAVA_BUILD_INDEP :=
+  GDC_BUILD_DEP :=
+  GO_BUILD_DEP :=
+else ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+  # Special source package just for gcj.
+  GNAT_BUILD_DEP :=
+  GDC_BUILD_DEP :=
+  GO_BUILD_DEP :=
+else ifeq ($(PKGSOURCE),gdc-$(BASE_VERSION))
+  # Special source package just for gdc.
+  GNAT_BUILD_DEP :=
+  JAVA_BUILD_DEP :=
+  JAVA_BUILD_INDEP :=
+  GDC_BUILD_DEP := $(SOURCE_BUILD_DEP)
+  GO_BUILD_DEP :=
+else ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+  # Special source package just for gccgo.
+  GNAT_BUILD_DEP :=
+  JAVA_BUILD_DEP :=
+  JAVA_BUILD_INDEP :=
+  GDC_BUILD_DEP := $(SOURCE_BUILD_DEP)
+endif
+
+
+else
+# build cross compiler
+  CROSS_BUILD_DEP := libc6-dev$(cross_lib_arch),
+ifneq (,$(findstring cross-build-,$(build_type)))
+  CROSS_BUILD_DEP += zlib1g-dev$(cross_lib_arch), libmpfr-dev$(cross_lib_arch),
+endif
+  SOURCE_BUILD_DEP :=
+  ifeq (,$(findstring gcc,$(PKGSOURCE)))
+    SOURCE_BUILD_DEP := gcc-$(BASE_VERSION)-source (>= $(GCC_SOURCE_VERSION)), gcc-$(BASE_VERSION)-source (<< $(NEXT_GCC_SOURCE_VERSION)),
+  endif
+  ifeq ($(with_java),yes)
+    JAVA_BUILD_DEP := zlib1g-dev, lib64z1-dev [i386 powerpc sparc s390], lib32z1-dev [amd64 ppc64 kfreebsd-amd64 s390x],
+  endif
+  JAVA_BUILD_INDEP :=
+  GNAT_BUILD_DEP :=
+endif # cross compiler
+
+BASE_BREAKS := gcc-4.4-base (<< 4.4.7), gcc-4.7-base (<< 4.7.3), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~)
+# these would need proper updates, and are only needed for upgrades
+ifneq (,$(filter $(distrelease),squeeze wheezy lucid precise trusty))
+  BASE_BREAKS :=
+endif
+
+
+# The numeric part of the gcc version number (x.yy.zz)
+NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \
+		awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}')
+# first version with a new path component in gcc_lib_dir (i.e. GCC_VERSION
+# or TARGET_ALIAS changes), or last version available for all architectures
+DEB_GCC_SOFT_VERSION := 6.3.0-1
+DEB_GCJ_SOFT_VERSION := 6.3.0-1
+DEB_GNAT_SOFT_VERSION := 6.3.0-1
+
+ifeq ($(with_d),yes)
+  GDC_VERSION := $(BASE_VERSION)
+  DEB_GDC_VERSION := $(DEB_VERSION)
+endif
+
+# semiautomatic ...
+DEB_SOVERSION		:= $(DEB_VERSION)
+DEB_SOVERSION		:= 5
+DEB_SOEVERSION		:= $(EPOCH):5
+DEB_STDCXX_SOVERSION	:= 5
+DEB_GCJ_SOVERSION	:= 5
+DEB_GOMP_SOVERSION	:= $(DEB_SOVERSION)
+
+DEB_GCC_VERSION := $(DEB_VERSION)
+DEB_GCJ_VERSION := $(DEB_VERSION)
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    DEB_GCC_VERSION := $(DEB_GCC_SOFT_VERSION)
+  endif
+endif
+
+DEB_GNAT_VERSION := $(DEB_VERSION)
+ifeq ($(with_separate_gnat),yes)
+  ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+    DEB_GCC_VERSION := $(DEB_GCC_SOFT_VERSION)
+  endif
+endif
+
+GNAT_VERSION := $(BASE_VERSION)
+
+LIBGNAT_DEP :=
+ifeq ($(with_libgnat),yes)
+  LIBGNAT_DEP := libgnat-$(GNAT_VERSION)$(LS)$(AQ) (>= $${gcc:Version})
+endif
+
+pkg_ver := -$(BASE_VERSION)
+
+PKG_GCJ_EXT = $(GCJ_SONAME1)
+PKG_LIBGCJ_EXT = $(GCJ_SONAME1)$(if $(GCJ_SONAME2),-$(GCJ_SONAME2))
+
+ctrl_flags = \
+	-DBINUTILSV=$(BINUTILSV) \
+	-DBINUTILSBDV=$(BINUTILSBDV) \
+	-DSRCNAME=$(PKGSOURCE) \
+	-D__$(DEB_TARGET_GNU_CPU)__ \
+	-DARCH=$(DEB_TARGET_ARCH) \
+	-DDIST=$(distribution)
+
+ctrl_flags += \
+	-DLIBC_DEV_DEP="$(LIBC_DEV_DEP)" \
+	-DLIBC_BIARCH_BUILD_DEP="$(LIBC_BIARCH_BUILD_DEP)" \
+	-DLIBC_DBG_DEP="$(LIBC_DBG_DEP)" \
+	-DBASE_BUILD_DEP="$(BASE_BUILD_DEP)" \
+	-DFORTRAN_BUILD_DEP="$(FORTRAN_BUILD_DEP)" \
+	-DGNAT_BUILD_DEP="$(GNAT_BUILD_DEP)" \
+	-DJAVA_BUILD_DEP="$(JAVA_BUILD_DEP)" \
+	-DGO_BUILD_DEP="$(GO_BUILD_DEP)" \
+	-DJAVA_BUILD_INDEP="$(JAVA_BUILD_INDEP)" \
+	-DLIBSTDCXX_BUILD_INDEP="$(LIBSTDCXX_BUILD_INDEP)" \
+	-DGDC_BUILD_DEP="$(GDC_BUILD_DEP)" \
+	-DBINUTILS_BUILD_DEP="$(BINUTILS_BUILD_DEP)" \
+	-DLIBC_BUILD_DEP="$(LIBC_BUILD_DEP)" \
+	-DCHECK_BUILD_DEP="$(CHECK_BUILD_DEP)" \
+	-DAUTO_BUILD_DEP="$(AUTO_BUILD_DEP)" \
+	-DSDT_BUILD_DEP="$(SDT_BUILD_DEP)" \
+	-DISL_BUILD_DEP="$(ISL_BUILD_DEP)" \
+	-DGMP_BUILD_DEP="$(GMP_BUILD_DEP)" \
+	-DMPFR_BUILD_DEP="$(MPFR_BUILD_DEP)" \
+	-DMPC_BUILD_DEP="$(MPC_BUILD_DEP)" \
+	-DDEBHELPER_BUILD_DEP="$(DEBHELPER_BUILD_DEP)" \
+	-DDPKG_BUILD_DEP="$(DPKG_BUILD_DEP)" \
+	-DSOURCE_BUILD_DEP="$(SOURCE_BUILD_DEP)" \
+	-DCROSS_BUILD_DEP="$(CROSS_BUILD_DEP)" \
+	-DGCC_MULTILIB_BUILD_DEP='$(GCC_MULTILIB_BUILD_DEP)' \
+	-DTARGET_TOOL_BUILD_DEP='$(TARGET_TOOL_BUILD_DEP)' \
+	-DPHOBOS_BUILD_DEP="$(PHOBOS_BUILD_DEP)" \
+	-DMULTILIB_ARCHS="$(multilib_archs)" \
+	-DNEON_ARCHS="$(neon_archs)" \
+	-DTP=$(TP) \
+	-DTS=$(TS) \
+	-DLS=$(LS) \
+	-DAQ=$(AQ) \
+	-DNT=$(NT)
+
+ifeq ($(DEB_CROSS),yes)
+  ctrl_flags += \
+	-DTARGET=$(DEB_TARGET_ARCH) \
+	-DLIBUNWIND_BUILD_DEP="$(LIBUNWIND_BUILD_DEP)" \
+	-DLIBATOMIC_OPS_BUILD_DEP="$(LIBATOMIC_OPS_BUILD_DEP)"
+  ifeq ($(DEB_STAGE),rtlibs)
+    ctrl_flags += -DCROSS_ARCH=$(DEB_TARGET_ARCH)
+  endif
+else
+  # add '-DPRI=optional' to ctrl_flags if this is not the default compiler
+  # ctrl_flags += \
+  #     -DPRI=optional
+endif
+
+ifeq ($(with_base_only),yes)
+  ctrl_flags += \
+	-DBASE_ONLY=yes
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  ctrl_flags += \
+	-DMULTIARCH=yes
+endif
+
+control: control-file readme-bugs-file parameters-file symbols-files copyright-file substvars-file versioned-files check-versions
+
+# stage1 and stage2 compilers are only C
+ifneq (,$(filter $(DEB_STAGE),stage1 stage2))
+  languages = c
+  addons = gccbase cdev plugindev
+  ifeq ($(with_gcclbase),yes)
+    addons += gcclbase
+  endif
+  ifeq ($(multilib),yes)
+    addons += multilib
+  endif
+  addons += $(if $(findstring armel,$(biarchhfarchs)),armml)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),armml)
+  addons += $(if $(findstring amd64,$(biarchx32archs)),x32dev)
+  ifeq ($(DEB_STAGE),stage2)
+    addons += libgcc
+    ifeq ($(multilib),yes)
+      addons += lib32gcc lib64gcc libn32gcc
+      addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gcc)
+      addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgcc)
+      addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgcc)
+    endif
+  else
+    LIBC_BIARCH_DEV_DEP :=
+  endif
+else
+languages = c c++ fortran objc objpp
+ifeq ($(DEB_STAGE),rtlibs)
+  ifeq (,$(filter libgfortran, $(with_rtlibs)))
+    languages := $(filter-out fortran, $(languages))
+  endif
+  ifeq (,$(filter libobjc, $(with_rtlibs)))
+    languages := $(filter-out objc objpp, $(languages))
+  endif
+endif
+ifeq ($(with_gccbase),yes)
+    addons += gccbase
+endif
+ifeq ($(with_gcclbase),yes)
+  addons += gcclbase
+endif
+ifneq ($(DEB_STAGE),rtlibs)
+  addons += cdev c++dev source multilib
+  ifeq ($(build_type),build-native)
+    addons += testresults
+  endif
+  ifneq (,$(filter fortran, $(languages)))
+      addons += fdev
+  endif
+  ifneq (,$(filter objc, $(languages)))
+      addons += objcdev
+  endif
+  ifneq (,$(filter objpp, $(languages)))
+      addons += objppdev
+  endif
+  addons += plugindev
+endif
+addons += $(if $(findstring armel,$(biarchhfarchs)),armml)
+addons += $(if $(findstring armhf,$(biarchsfarchs)),armml)
+addons += $(if $(findstring amd64,$(biarchx32archs)),x32dev)
+ifeq ($(with_libgcc),yes)
+  addons += libgcc lib4gcc lib32gcc lib64gcc libn32gcc
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gcc)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgcc)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgcc)
+endif
+ifeq ($(with_libcxx),yes)
+  addons += libcxx lib32cxx lib64cxx libn32cxx
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32cxx)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfcxx)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfcxx)
+endif
+addons += $(if $(findstring amd64,$(biarchx32archs)),libx32dbgcxx)
+addons += $(if $(findstring armel,$(biarchhfarchs)),libhfdbgcxx)
+addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfdbgcxx)
+ifeq ($(with_libgfortran),yes)
+  addons += libgfortran lib32gfortran lib64gfortran libn32gfortran
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gfortran)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgfortran)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgfortran)
+endif
+ifeq ($(with_libobjc),yes)
+  addons += libobjc lib32objc lib64objc libn32objc
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32objc)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfobjc)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfobjc)
+endif
+ifeq ($(with_libgomp),yes)
+  addons += libgomp lib32gomp lib64gomp libn32gomp
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gomp)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgomp)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgomp)
+endif
+ifeq ($(with_libitm),yes)
+  addons += libitm lib32itm lib64itm libn32itm
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32itm)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfitm)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfitm)
+endif
+ifeq ($(with_libatomic),yes)
+  addons += libatomic lib32atomic lib64atomic libn32atomic
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32atomic)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfatomic)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfatomic)
+endif
+ifeq ($(with_libbacktrace),yes)
+  addons += libbtrace lib32btrace lib64btrace libn32btrace
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32btrace)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfbtrace)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfbtrace)
+endif
+ifeq ($(with_libasan),yes)
+  addons += libasan lib32asan lib64asan libn32asan
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32asan)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfasan)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfasan)
+endif
+ifeq ($(with_liblsan),yes)
+  addons += liblsan lib32lsan lib64lsan libn32lsan
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32lsan)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhflsan)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsflsan)
+endif
+ifeq ($(with_libtsan),yes)
+  addons += libtsan
+  addons += libtsan #lib32tsan lib64tsan libn32tsan
+  #addons += $(if $(findstring amd64,$(biarchx32archs)),libx32tsan)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhftsan)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsftsan)
+endif
+ifeq ($(with_libubsan),yes)
+  addons += libubsan lib32ubsan lib64ubsan libn32ubsan
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32ubsan)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfubsan)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfubsan)
+endif
+ifeq ($(with_vtv),yes)
+  addons += libvtv lib32vtv lib64vtv #libn32vtv
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32vtv)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhfvtv)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfvtv)
+endif
+ifeq ($(with_libcilkrts),yes)
+  addons += libcilkrts
+  addons += libcilkrts lib32cilkrts lib64cilkrts #libn32cilkrts
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32cilkrts)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhfcilkrts)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfcilkrts)
+endif
+ifeq ($(with_mpx),yes)
+  addons += libmpx lib32mpx lib64mpx
+endif
+ifeq ($(with_libqmath),yes)
+  addons += libqmath lib32qmath lib64qmath libn32qmath
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32qmath)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfqmath)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfqmath)
+endif
+ifeq ($(with_jit),yes)
+  addons += jit
+endif
+ifeq ($(with_libgccjit),yes)
+  addons += libjit
+endif
+ifeq ($(with_libcc1),yes)
+  addons += libcc1
+endif
+ifeq ($(with_d),yes)
+  languages += d
+  ifeq ($(with_libphobos),yes)
+    addons += libphobos
+    addons += $(if $(findstring amd64,$(biarchx32archs)),libx32phobos)
+  endif
+endif
+ifeq ($(with_go),yes)
+  addons += ggo godev
+  ifeq ($(with_libgo),yes)
+    addons += libggo lib32ggo lib64ggo libn32ggo
+    addons += $(if $(findstring amd64,$(biarchx32archs)),libx32ggo)
+  endif
+endif
+ifeq ($(with_ada),yes)
+  languages += ada
+  addons += libgnat libs # libgmath libnof lib64gnat ssp
+  ifeq ($(with_gnatsjlj),yes)
+    addons += adasjlj
+  endif
+endif
+ifeq ($(with_java),yes)
+  languages += java
+  addons += gcj
+  ifneq ($(DEB_CROSS),yes)
+    addons += libgcj libgcjdev gcjdoc gcjsrc
+  endif
+endif
+
+  ifneq ($(DEB_CROSS),yes)
+  ifneq (,$(neon_archs))
+    addons += libneongcc libneongomp libneonitm libneonobjc libneongfortran libneoncxx
+  endif
+  ifeq ($(with_fixincl),yes)
+    addons += $(if $(DEB_STAGE),,fixincl)
+  endif
+  ifeq ($(with_libgcj_doc),yes)
+    addons += gcjdoc
+  endif
+  endif # DEB_CROSS
+#  ifneq (,$(findstring gtk, $(java_awt_peers)))
+#    addons += gtkpeer
+#  endif
+#  ifneq (,$(findstring qt, $(java_awt_peers)))
+#    addons += qtpeer
+#  endif
+  ifeq ($(with_separate_libgcj),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out java,$(languages))
+      addons := $(filter-out gcj libgcj libgcjdev gcjdoc gcjsrc gtkpeer qtpeer,$(addons))
+    endif
+    ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+      languages = java
+      addons = gcj libgcj libgcjdev gcjsrc
+      addons += $(if $(filter yes,$(with_gcjbase)),gcjbase)
+      addons += $(if $(filter yes,$(with_gcjxbase)),gcjxbase)
+    ifeq ($(with_libgcj_doc),yes)
+      addons += gcjdoc
+    endif
+#      ifneq (,$(findstring gtk, $(java_awt_peers)))
+#        addons += gtkpeer
+#      endif
+#      ifneq (,$(findstring qt, $(java_awt_peers)))
+#        addons += qtpeer
+#      endif
+      ifeq ($(with_standalone_gcj),yes)
+	addons += libgcc lib4gcc lib64gcc lib32gcc libn32gcc libx32gcc
+      endif
+    endif
+  endif
+  ifeq ($(DEB_CROSS),yes)
+    addons := $(filter-out gcjdoc gcjsrc,$(addons))
+  endif
+  ifeq ($(with_standalone_gcj),yes)
+    ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+      ctrl_flags += -DSTANDALONEJAVA
+    endif
+  endif
+  ifeq ($(with_separate_libgo),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out go,$(languages))
+      addons := $(filter-out ggo godev libggo lib64ggo lib32ggo libn32ggo libx32ggo,$(addons))
+    endif
+    ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+      languages = go
+      addons = ggo godev libggo lib64ggo lib32ggo libn32ggo gccbase multilib
+      addons += $(if $(findstring amd64,$(biarchx32archs)),libx32ggo)
+      ifeq ($(with_standalone_go),yes)
+        addons += libgcc lib4gcc lib32gcc lib64gcc libn32gcc
+        addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gcc)
+        addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgcc)
+        addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgcc)
+        ifeq ($(with_libcc1),yes)
+          addons += libcc1
+        endif
+      endif
+    endif
+  endif
+  ifeq ($(with_standalone_go),yes)
+    ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+      ctrl_flags += -DSTANDALONEGO
+    endif
+  endif
+  ifeq ($(with_separate_gnat),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out ada,$(languages))
+      addons := $(filter-out libgnat adasjlj,$(addons))
+    endif
+    ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+      languages = ada
+      addons = gnatbase libgnat
+    endif
+  endif
+  ifeq ($(with_separate_gdc),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out d,$(languages))
+    endif
+    ifeq ($(PKGSOURCE),gdc-$(BASE_VERSION))
+      languages = d
+      addons = 
+      ifeq ($(with_libphobos),yes)
+        addons += libphobos
+      endif
+    endif
+  endif
+  ifneq ($(DEB_CROSS),yes) # no docs for cross compilers
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    addons += gfdldoc
+  endif
+  endif
+endif # not stage
+
+control-file:
+	echo "addons: $(addons)"; \
+	m4 $(ctrl_flags) \
+	  -DPV=$(pkg_ver) \
+	  -DCXX_SO=$(CXX_SONAME) \
+	  -DGCC_SO=$(GCC_SONAME) \
+	  -DOBJC_SO=$(OBJC_SONAME) \
+	  -DFORTRAN_SO=$(FORTRAN_SONAME) \
+	  -DGCJ_SO=$(PKG_GCJ_EXT) \
+	  -DLIBGCJ_EXT=$(PKG_LIBGCJ_EXT) \
+	  -DGNAT_SO=$(GNAT_SONAME) \
+	  -DGNAT_V=$(GNAT_VERSION) \
+	  -DPHOBOS_V=$(GPHOBOS_SONAME) \
+	  -DGDRUNTIME_V=$(GDRUNTIME_SONAME) \
+	  -DGOMP_SO=$(GOMP_SONAME) \
+	  -DITM_SO=$(ITM_SONAME) \
+	  -DATOMIC_SO=$(ATOMIC_SONAME) \
+	  -DBTRACE_SO=$(BTRACE_SONAME) \
+	  -DASAN_SO=$(ASAN_SONAME) \
+	  -DLSAN_SO=$(LSAN_SONAME) \
+	  -DTSAN_SO=$(TSAN_SONAME) \
+	  -DUBSAN_SO=$(UBSAN_SONAME) \
+	  -DVTV_SO=$(VTV_SONAME) \
+	  -DCILKRTS_SO=$(CILKRTS_SONAME) \
+	  -DMPX_SO=$(MPX_SONAME) \
+	  -DQMATH_SO=$(QUADMATH_SONAME) \
+	  -DSSP_SO=$(SSP_SONAME) \
+	  -DGO_SO=$(GO_SONAME) \
+	  -DCC1_SO=$(CC1_SONAME) \
+	  -DGCCJIT_SO=$(GCCJIT_SONAME) \
+	  -Denabled_languages="$(languages) $(addons)" \
+	  -Dada_no_archs="$(ada_no_archs)" \
+	  -Djava_no_archs="$(java_no_archs)" \
+	  -Dfortran_no_archs="$(fortran_no_archs)" \
+	  -Dlibgc_no_archs="$(libgc_no_archs)" \
+	  -Dlibphobos_archs="$(libphobos_archs)" \
+	  -Dlibphobos_no_archs="$(libphobos_no_archs)" \
+	  -Dcheck_no_archs="$(check_no_archs)" \
+	  -Dlocale_no_archs="$(locale_no_archs)" \
+	  -Dlinux_gnu_archs="$(linux_gnu_archs)" \
+	  -Dbiarch32_archs="$(strip $(subst /, ,$(biarch32archs)))" \
+	  -Dbiarch64_archs="$(strip $(subst /, ,$(biarch64archs)))" \
+	  -Dbiarchn32_archs="$(strip $(subst /, ,$(biarchn32archs)))" \
+	  -Dbiarchx32_archs="$(strip $(subst /, ,$(biarchx32archs)))" \
+	  -Dbiarchhf_archs="$(strip $(subst /, ,$(biarchhfarchs)))" \
+	  -Dbiarchsf_archs="$(strip $(subst /, ,$(biarchsfarchs)))" \
+	  -Dadd_built_using=$(add_built_using) \
+	  -DGCC_PORTS_BUILD=$(GCC_PORTS_BUILD) \
+	  -DPR66145BREAKS="$(if $(findstring build-native,$(build_type)),$(if $(filter new,$(libstdcxx_abi)),$$(tr '\n' ' ' < debian/libstdc++-breaks.$(derivative))))" \
+		debian/control.m4 > debian/control.tmp2
+	uniq debian/control.tmp2 | sed '/^Build/s/ *, */, /g;/^  /s/ *, */, /g' \
+		$(if $(filter yes, $(with_base_only)), | awk '/^$$/ {if (p) exit; else p=1; } {print}') \
+		> debian/control.tmp
+	rm -f debian/control.tmp2
+	[ -e debian/control ] \
+	  && cmp -s debian/control debian/control.tmp \
+	  && rm -f debian/control.tmp && exit 0; \
+	  mv debian/control.tmp debian/control; touch $(control_stamp)
+
+readme-bugs-file:
+	m4 -DDIST=$(distribution) -DSRCNAME=$(PKGSOURCE) \
+		debian/README.Bugs.m4 > debian/README.Bugs
+
+copyright-file:
+	rm -f debian/copyright
+	if echo $(SOURCE_VERSION) | grep -E ^'[0-9]\.[0-9]-[0-9]{8}' ; \
+		then SVN_BRANCH="trunk" ; \
+	else \
+		SVN_BRANCH="gcc-$(subst .,_,$(BASE_VERSION))-branch" ; \
+	fi ; \
+	sed debian/copyright.in		\
+		-e "s/@BV@/$(BASE_VERSION)/g"		\
+		-e "s/@SVN_BRANCH@/$$SVN_BRANCH/g"	\
+		> debian/copyright
+
+substvars-file: control-file
+	rm -f debian/substvars.local.tmp
+	( \
+		echo 'libgcc:Version=$(DEB_LIBGCC_VERSION)'; \
+		echo 'gcc:Version=$(DEB_GCC_VERSION)'; \
+		echo 'gcc:EpochVersion=$(DEB_EVERSION)'; \
+		echo 'gcc:SoftVersion=$(DEB_GCC_SOFT_VERSION)'; \
+		echo 'gdc:Version=$(DEB_GDC_VERSION)'; \
+		echo 'gcj:Version=$(DEB_GCJ_VERSION)'; \
+		echo 'gcj:SoftVersion=$(DEB_GCJ_SOFT_VERSION)'; \
+		echo 'gcj:BaseVersion=$(BASE_VERSION)'; \
+		echo 'gnat:Version=$(DEB_GNAT_VERSION)'; \
+		echo 'gnat:SoftVersion=$(DEB_GNAT_SOFT_VERSION)'; \
+		echo 'binutils:Version=$(BINUTILSV)'; \
+		echo 'dep:libgcc=$(LIBGCC_DEP)'; \
+		echo 'dep:libgccdev=$(LIBGCC_DEV_DEP)'; \
+		echo 'dep:libgccbiarch=$(libgccbiarch)'; \
+		echo 'dep:libgccbiarchdev=$(libgccbiarchdev)'; \
+		echo 'dep:libc=$(LIBC_DEP) (>= $(libc_ver))'; \
+		echo 'dep:libcdev=$(LIBC_DEV_DEP)'; \
+		echo 'dep:libcbiarch=$(LIBC_BIARCH_DEP)'; \
+		echo 'dep:libcbiarchdev=$(LIBC_BIARCH_DEV_DEP)'; \
+		echo 'dep:libunwinddev=$(LIBUNWIND_DEV_DEP)'; \
+		echo 'dep:libcxxbiarchdev=$(libstdc++biarchdev)'; \
+		echo 'dep:libcxxbiarchdbg=$(libstdc++biarchdbg)'; \
+		echo 'dep:libgnat=$(LIBGNAT_DEP)'; \
+		echo 'dep:ecj=$(ECJ_DEP)'; \
+		echo 'base:Breaks=$(BASE_BREAKS)'; \
+	) > debian/substvars.local.tmp
+ifneq (,$(filter $(DEB_TARGET_ARCH), $(multilib_archs)))
+	( \
+		echo 'gcc:multilib=gcc-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gxx:multilib=g++-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gobjc:multilib=gobjc-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gobjcxx:multilib=gobjc++-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gfortran:multilib=gfortran-$(BASE_VERSION)-multilib$(TS)'; \
+	) >> debian/substvars.local.tmp
+endif
+ifeq ($(with_gold),yes)
+	echo 'dep:gold=binutils-gold (>= $(BINUTILSV))' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_libssp),yes)
+	echo 'dep:libssp=libssp$(SSP_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_gomp),yes)
+	echo 'dep:libgomp=libgomp$(GOMP_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_itm),yes)
+	echo 'dep:libitm=libitm$(ITM_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_atomic),yes)
+	echo 'dep:libatomic=libatomic$(ATOMIC_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_libbacktrace),yes)
+	echo 'dep:libbacktrace=libbtrace$(BTRACE_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_asan),yes)
+	echo 'dep:libasan=libasan$(ASAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_lsan),yes)
+	echo 'dep:liblsan=liblsan$(LSAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_tsan),yes)
+	echo 'dep:libtsan=libtsan$(TSAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_ubsan),yes)
+	echo 'dep:libubsan=libubsan$(UBSAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_vtv),yes)
+	echo 'dep:libvtv=libvtv$(VTV_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_cilkrts),yes)
+	echo 'dep:libcilkrts=libcilkrts$(CILKRTS_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_mpx),yes)
+	echo 'dep:libmpx=libmpx$(MPX_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_qmath),yes)
+	echo 'dep:libqmath=libquadmath$(QUADMATH_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(distribution),Debian)
+	echo 'dep:libx32z=$(if $(filter $(distribution), Debian),,libx32z1-dev)' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(multilib),yes)
+	echo 'dep:libgfortranbiarchdev=$(libgfortranbiarchdev)' \
+		>> debian/substvars.local.tmp
+	echo 'dep:libobjcbiarchdev=$(libobjcbiarchdev)' \
+		>> debian/substvars.local.tmp
+  ifeq ($(with_libphobos),yes)
+	echo 'dep:libphobosbiarchdev=$(libgphobosbiarchdev)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_libssp),yes)
+	echo 'dep:libsspbiarch=$(libsspbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_gomp),yes)
+	echo 'dep:libgompbiarch=$(libgompbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_itm),yes)
+	echo 'dep:libitmbiarch=$(libitmbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_atomic),yes)
+	echo 'dep:libatomicbiarch=$(libatomicbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_libbacktrace),yes)
+	echo 'dep:libbtracebiarch=$(libbtracebiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_asan),yes)
+	echo 'dep:libasanbiarch=$(libasanbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_lsan),yes)
+	#echo 'dep:liblsanbiarch=$(liblsanbiarch)' \
+	#	>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_tsan),yes)
+	#echo 'dep:libtsanbiarch=$(libtsanbiarch)' \
+	#	>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_ubsan),yes)
+	echo 'dep:libubsanbiarch=$(libubsanbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_vtv),yes)
+	echo 'dep:libvtvbiarch=$(libvtvbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_cilkrts),yes)
+	echo 'dep:libcilkrtsbiarch=$(libcilkrtsbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_mpx),yes)
+	echo 'dep:libmpxbiarch=$(libmpxbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_qmath),yes)
+	echo 'dep:libqmathbiarch=$(libquadmathbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_go),yes)
+	echo 'dep:libgobiarchdev=$(libgobiarchdev)' \
+		>> debian/substvars.local.tmp
+	echo 'dep:libgobiarch=$(libgobiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_libphobosdev),yes)
+	echo 'dep:libphobosbiarchdev=$(libgphobosbiarchdev)' \
+		>> debian/substvars.local.tmp
+	echo 'dep:libphobosbiarch=$(libgphobosbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+ifneq ($(with_standalone_gcj),yes)
+  ifneq (,$(filter $(DEB_HOST_ARCH),armel armhf))
+	echo 'dep:gcj=g++$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  else
+	echo 'dep:gcj=gcc$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(DEB_CROSS),yes)
+	echo 'dep:gcjcross=gcj$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+ifeq ($(DEB_CROSS),yes)
+	echo 'dep:gdccross=gdc$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_libphobos),yes)
+	echo 'dep:phobosdev=libgphobos$(pkg_ver)-dev$(LS)$(AQ) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  ifeq ($(DEB_CROSS),yes)
+	: # FIXME: make the cross gdc aware of both include paths
+	echo 'dep:gdccross=gdc$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+ifeq ($(with_cc1),yes)
+  ifneq (,$(findstring build-cross, $(build_type)))
+	echo 'dep:libcc1=libcc1-$(CC1_SONAME) (>= $${gcc:SoftVersion})' \
+		>> debian/substvars.local.tmp
+  else
+	echo 'dep:libcc1=libcc1-$(CC1_SONAME) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	echo 'pkg:gcjgtk=libgcj$(subst 0,,$(GCJ_SONAME))-awt-gtk (>= $(DEB_GCJ_VERSION))' \
+#		>> debian/substvars.local.tmp
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	echo 'pkg:gcjqt=libgcj$(subst 0,,$(GCJ_SONAME))-awt-qt (>= $(DEB_GCJ_VERSION))' \
+#		>> debian/substvars.local.tmp
+#endif
+ifeq ($(DEB_HOST_ARCH),hppa)
+	echo 'dep:prctl=prctl' >> debian/substvars.local.tmp
+endif
+ifeq ($(derivative)-$(DEB_HOST_ARCH),Debian-amd64)
+	echo 'confl:lib32=libc6-i386 (<< 2.9-22)' >> debian/substvars.local.tmp
+endif
+ifeq ($(with_multiarch_lib),yes)
+	echo 'multiarch:breaks=gcc-4.3 (<< 4.3.6-1), gcc-4.4 (<< 4.4.6-4), gcc-4.5 (<< 4.5.3-2)' >> debian/substvars.local.tmp
+endif
+	echo 'golang:Conflicts=golang-go (<< 2:1.3.3-1ubuntu2)' >> debian/substvars.local.tmp
+ifeq ($(add_built_using),yes)
+	echo "Built-Using=$(shell dpkg-query -f '$${source:Package} (= $${source:Version}), ' -W gcc$(pkg_ver)-source)" \
+	>> debian/substvars.local.tmp
+endif
+	v=`sed -n '/^#define MOD_VERSION/s/.* "\([0-9]*\)"/\1/p' \
+		$(srcdir)/gcc/fortran/module.c`; \
+	echo "fortran:mod-version=gfortran-mod-$$v" >> debian/substvars.local.tmp
+
+	[ -e debian/substvars.local ] \
+	  && cmp -s debian/substvars.local debian/substvars.local.tmp \
+	  && rm -f debian/substvars.local.tmp && exit 0; \
+	  mv debian/substvars.local.tmp debian/substvars.local; \
+	  touch $(control_stamp)
+
+parameters-file:
+	rm -f debian/rules.parameters.tmp
+	( \
+		echo '# configuration parameters taken from upstream source files'; \
+		echo 'GCC_VERSION	:= $(GCC_VERSION)'; \
+		echo 'NEXT_GCC_VERSION	:= $(NEXT_GCC_VERSION)'; \
+		echo 'BASE_VERSION	:= $(BASE_VERSION)'; \
+		echo 'SOURCE_VERSION	:= $(SOURCE_VERSION)'; \
+		echo 'DEB_VERSION	:= $(DEB_VERSION)'; \
+		echo 'DEB_EVERSION	:= $(DEB_EVERSION)'; \
+		echo 'DEB_GDC_VERSION	:= $(DEB_GDC_VERSION)'; \
+		echo 'DEB_SOVERSION	:= $(DEB_SOVERSION)'; \
+		echo 'DEB_SOEVERSION	:= $(DEB_SOEVERSION)'; \
+		echo 'DEB_LIBGCC_SOVERSION	:= $(DEB_LIBGCC_SOVERSION)'; \
+		echo 'DEB_LIBGCC_VERSION	:= $(DEB_LIBGCC_VERSION)'; \
+		echo 'DEB_STDCXX_SOVERSION	:= $(DEB_STDCXX_SOVERSION)'; \
+		echo 'DEB_GCJ_SOVERSION	:= $(DEB_GCJ_SOVERSION)'; \
+		echo 'PKG_GCJ_EXT	:= $(PKG_GCJ_EXT)'; \
+		echo 'PKG_LIBGCJ_EXT	:= $(PKG_LIBGCJ_EXT)'; \
+		echo 'DEB_GOMP_SOVERSION	:= $(DEB_GOMP_SOVERSION)'; \
+		echo 'GCC_SONAME	:= $(GCC_SONAME)'; \
+		echo 'CXX_SONAME	:= $(CXX_SONAME)'; \
+		echo 'FORTRAN_SONAME	:= $(FORTRAN_SONAME)'; \
+		echo 'OBJC_SONAME	:= $(OBJC_SONAME)'; \
+		echo 'GCJ_SONAME	:= $(GCJ_SONAME)'; \
+		echo 'GDC_VERSION	:= $(GDC_VERSION)'; \
+		echo 'GNAT_VERSION	:= $(GNAT_VERSION)'; \
+		echo 'GNAT_SONAME	:= $(GNAT_SONAME)'; \
+		echo 'FFI_SONAME	:= $(FFI_SONAME)'; \
+		echo 'SSP_SONAME	:= $(SSP_SONAME)'; \
+		echo 'GOMP_SONAME	:= $(GOMP_SONAME)'; \
+		echo 'ITM_SONAME	:= $(ITM_SONAME)'; \
+		echo 'ATOMIC_SONAME	:= $(ATOMIC_SONAME)'; \
+		echo 'BTRACE_SONAME	:= $(BTRACE_SONAME)'; \
+		echo 'ASAN_SONAME	:= $(ASAN_SONAME)'; \
+		echo 'LSAN_SONAME	:= $(LSAN_SONAME)'; \
+		echo 'TSAN_SONAME	:= $(TSAN_SONAME)'; \
+		echo 'UBSAN_SONAME	:= $(UBSAN_SONAME)'; \
+		echo 'VTV_SONAME	:= $(VTV_SONAME)'; \
+		echo 'CILKRTS_SONAME	:= $(CILKRTS_SONAME)'; \
+		echo 'MPX_SONAME	:= $(MPX_SONAME)'; \
+		echo 'QUADMATH_SONAME	:= $(QUADMATH_SONAME)'; \
+		echo 'GO_SONAME		:= $(GO_SONAME)'; \
+		echo 'CC1_SONAME	:= $(CC1_SONAME)'; \
+		echo 'GCCJIT_SONAME	:= $(GCCJIT_SONAME)'; \
+		echo 'GPHOBOS_SONAME	:= $(GPHOBOS_SONAME)'; \
+		echo 'GDRUNTIME_SONAME	:= $(GDRUNTIME_SONAME)'; \
+		echo 'LIBC_DEP		:= $(LIBC_DEP)'; \
+	) > debian/rules.parameters.tmp
+	[ -e debian/rules.parameters ] \
+	  && cmp -s debian/rules.parameters debian/rules.parameters.tmp \
+	  && rm -f debian/rules.parameters.tmp && exit 0; \
+	  mv debian/rules.parameters.tmp debian/rules.parameters; \
+	  touch $(control_stamp)
+
+symbols-files: control-file
+ifeq ($(DEB_CROSS),yes)
+  ifneq ($(DEB_STAGE),rtlibs)
+	test -n "$(LS)"
+	set -e; \
+	for p in $$(dh_listpackages -i | grep '^lib'); do \
+	  p=$${p%$(LS)}; \
+	  if [ -f debian/$$p.symbols.$(DEB_TARGET_ARCH) ]; then \
+	    f=debian/$$p.symbols.$(DEB_TARGET_ARCH); \
+	  elif [ -f debian/$$p.symbols ]; then \
+	    f=debian/$$p.symbols; \
+	  else \
+	    continue; \
+	  fi; \
+	  link=debian/$$p$(LS).symbols; \
+	  if [ -L $$link ]; then \
+	    echo >&2 "removing left over symbols file link: $$link"; \
+	    rm -f $$link; \
+	  fi; \
+	  ln -s $$f $$link; \
+	done
+  endif
+endif
+
+versioned-files:
+	fs=`echo debian/*BV* debian/*GCJ* debian/*CXX* debian/*LC* | sort -u`; \
+	for f in $$fs debian/source.lintian-overrides.in; do \
+	  [ -f $$f ] || echo "CANNOT FIND $$f"; \
+	  [ -f $$f ] || continue; \
+	  if [ -z "$(DEB_CROSS)" ]; then case "$$f" in *-CR*) continue; esac; fi; \
+	  f2=$$(echo $$f \
+		| sed 's/BV/$(BASE_VERSION)/;s/CXX/$(CXX_SONAME)/;s/LGCJ/$(PKG_LIBGCJ_EXT)/;s/GCJ/$(PKG_GCJ_EXT)/;s/LC/$(GCC_SONAME)/;s/-CRB/$(cross_bin_arch)/;s/\.in$$//'); \
+	  sed -e 's/@BV@/$(BASE_VERSION)/g' \
+	      -e 's/@CXX@/$(CXX_SONAME)/g' \
+	      -e 's/@LGCJ@/$(PKG_LIBGCJ_EXT)/g' \
+	      -e 's/@GCJ@/$(PKG_GCJ_EXT)/g' \
+	      -e 's/@GCJSO@/$(GCJ_SONAME)/g' \
+	      -e 's/@LC@/$(GCC_SONAME)/g' \
+	      -e 's/@SRC@/$(PKGSOURCE)/g' \
+	      -e 's/@GFDL@/$(if $(filter yes,$(GFDL_INVARIANT_FREE)),#)/g' \
+	      -e 's/@java_priority@/$(java_priority)/g' \
+	      -e 's/@gcc_priority@/$(subst .,,$(BASE_VERSION))/g' \
+	      -e 's/@TARGET@/$(DEB_TARGET_GNU_TYPE)/g' \
+	      -e 's/@TARGET_QUAL@/$(TARGET_QUAL)/g' \
+	    $$f > $$f2; \
+	  touch -r $$f $$f2; \
+	done
+	for t in ar nm ranlib; do \
+	  sed "s/@BV@/$(BASE_VERSION)/g;s/@TOOL@/$$t/g" \
+	    debian/gcc-XX-BV.1 > debian/gcc-$$t-$(BASE_VERSION).1; \
+	done
+
+# don't encode versioned build dependencies in the control file, but check
+# these here instead.
+check-versions:
+	v=$$(dpkg-query -l dpkg-dev | awk '/^.i/ {print $$3}'); \
+	if dpkg --compare-versions "$$v" lt "$(DPKGV)"; then \
+	  echo "dpkg-dev (>= $(DPKGV)) required, found $$v"; \
+	  exit 1; \
+	fi
+	v=$$(dpkg-query -l binutils binutils-multiarch 2>/dev/null | awk '/^.i/ {print $$3;exit}'); \
+	if dpkg --compare-versions "$$v" lt "$(BINUTILSBDV)"; then \
+	  echo "binutils (>= $(BINUTILSBDV)) required, found $$v"; \
+	  exit 1; \
+	fi
+
+.PRECIOUS: $(stampdir)/%-stamp
--- gcc-6-6.3.0.orig/debian/rules.d/binary-ada.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-ada.mk
@@ -0,0 +1,395 @@
+ifeq ($(with_separate_gnat),yes)
+  $(lib_binaries) += gnatbase
+endif
+
+ifeq ($(with_libgnat),yes)
+  $(lib_binaries) += libgnat libgnatvsn libgnatprj
+endif
+
+arch_binaries := $(arch_binaries) ada
+ifneq ($(DEB_CROSS),yes)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    indep_binaries := $(indep_binaries) ada-doc
+  endif
+endif
+
+p_gbase		= $(p_xbase)
+p_glbase	= $(p_lbase)
+ifeq ($(with_separate_gnat),yes)
+  p_gbase	= gnat$(pkg_ver)$(cross_bin_arch)-base
+  p_glbase	= gnat$(pkg_ver)$(cross_bin_arch)-base
+endif
+
+p_gnat	= gnat-$(GNAT_VERSION)$(cross_bin_arch)
+p_gnatsjlj= gnat-$(GNAT_VERSION)-sjlj$(cross_bin_arch)
+p_lgnat	= libgnat-$(GNAT_VERSION)$(cross_lib_arch)
+p_lgnat_dbg = libgnat-$(GNAT_VERSION)-dbg$(cross_lib_arch)
+p_lgnatvsn = libgnatvsn$(GNAT_VERSION)$(cross_lib_arch)
+p_lgnatvsn_dev = libgnatvsn$(GNAT_VERSION)-dev$(cross_lib_arch)
+p_lgnatvsn_dbg = libgnatvsn$(GNAT_VERSION)-dbg$(cross_lib_arch)
+p_lgnatprj = libgnatprj$(GNAT_VERSION)$(cross_lib_arch)
+p_lgnatprj_dev = libgnatprj$(GNAT_VERSION)-dev$(cross_lib_arch)
+p_lgnatprj_dbg = libgnatprj$(GNAT_VERSION)-dbg$(cross_lib_arch)
+p_gnatd	= $(p_gnat)-doc
+
+d_gbase	= debian/$(p_gbase)
+d_gnat	= debian/$(p_gnat)
+d_gnatsjlj	= debian/$(p_gnatsjlj)
+d_lgnat	= debian/$(p_lgnat)
+d_lgnatvsn = debian/$(p_lgnatvsn)
+d_lgnatvsn_dev = debian/$(p_lgnatvsn_dev)
+d_lgnatprj = debian/$(p_lgnatprj)
+d_lgnatprj_dev = debian/$(p_lgnatprj_dev)
+d_gnatd	= debian/$(p_gnatd)
+
+GNAT_TOOLS = gnat gnatbind gnatchop gnatclean gnatfind gnatkr gnatlink \
+	     gnatls gnatmake gnatname gnatprep gnatxref gnathtml
+
+ifeq ($(with_gnatsjlj),yes)
+	rts_subdir = 
+endif
+
+dirs_gnat = \
+	$(docdir)/$(p_gbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(gcc_lib_dir)/{adalib,adainclude} \
+	$(gcc_lexec_dir)
+
+files_gnat = \
+	$(gcc_lexec_dir)/gnat1 \
+	$(gcc_lib_dir)/adainclude/*.ad[bs] \
+	$(gcc_lib_dir)/adalib/*.ali \
+	$(gcc_lib_dir)/adalib/lib*.a \
+	$(foreach i,$(GNAT_TOOLS),$(PF)/bin/$(cmd_prefix)$(i)$(pkg_ver))
+
+dirs_lgnat = \
+	$(docdir) \
+	$(PF)/lib
+files_lgnat = \
+	$(usr_lib)/lib{gnat,gnarl}-$(GNAT_SONAME).so.1
+
+$(binary_stamp)-gnatbase: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	dh_installdocs -p$(p_gbase) debian/README.gnat debian/README.maintainers
+	: # $(p_gbase)
+ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+	mkdir -p $(d_gbase)/$(docdir)/$(p_xbase)
+	ln -sf ../$(p_gbase) $(d_gbase)/$(docdir)/$(p_xbase)/Ada
+endif
+	dh_installchangelogs -p$(p_gbase) src/gcc/ada/ChangeLog
+	dh_compress -p$(p_gbase)
+	dh_fixperms -p$(p_gbase)
+	dh_gencontrol -p$(p_gbase) -- -v$(DEB_VERSION) $(common_substvars)
+	dh_installdeb -p$(p_gbase)
+	dh_md5sums -p$(p_gbase)
+	dh_builddeb -p$(p_gbase)
+	touch $@
+
+
+$(binary_stamp)-libgnat: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	: # libgnat
+	rm -rf $(d_lgnat)
+	dh_installdirs -p$(p_lgnat) $(dirs_lgnat)
+
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  mv $(d)/$(gcc_lib_dir)/$(rts_subdir)/adalib/$$vlib.so.1 $(d)/$(usr_lib)/. ; \
+	  rm -f $(d)/$(gcc_lib_dir)/adalib/$$lib.so.1; \
+	done
+	$(dh_compat2) dh_movefiles -p$(p_lgnat) $(files_lgnat)
+
+	debian/dh_doclink -p$(p_lgnat) $(p_glbase)
+
+	debian/dh_rmemptydirs -p$(p_lgnat)
+
+	b=libgnat; \
+	v=$(GNAT_VERSION); \
+	for ext in preinst postinst prerm postrm; do \
+	  for t in '' -dev -dbg; do \
+	    if [ -f debian/$$b$$t.$$ext ]; then \
+	      cp -pf debian/$$b$$t.$$ext debian/$$b$$v$$t.$$ext; \
+	    fi; \
+	  done; \
+	done
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_lgnat) -V '$(p_lgnat) (>= $(DEB_VERSION))'
+	$(call cross_mangle_shlibs,$(p_lgnat))
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mkdir -p $(d_lgnat)/usr/share/lintian/overrides
+	cp -p debian/$(p_lgnat).overrides \
+		$(d_lgnat)/usr/share/lintian/overrides/$(p_lgnat)
+endif
+
+	dh_strip -p$(p_lgnat) --dbg-package=$(p_lgnat_dbg)
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_lgnat) \
+		$(call shlibdirs_to_search, \
+			$(subst gnat-$(GNAT_SONAME),gcc$(GCC_SONAME),$(p_lgnat)) \
+		,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_lgnat))
+
+	: # $(p_lgnat_dbg)
+	debian/dh_doclink -p$(p_lgnat_dbg) $(p_glbase)
+
+	echo $(p_lgnat) $(p_lgnat_dbg) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+
+$(binary_stamp)-libgnatvsn: $(install_stamp)
+	: # $(p_lgnatvsn_dev)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn_dev) usr/lib/ada/adalib/gnatvsn
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn_dev) usr/share/ada/adainclude/gnatvsn
+	dh_install -p$(p_lgnatvsn_dev) \
+	   debian/gnatvsn.gpr usr/share/ada/adainclude
+else
+	mkdir -p $(d_lgnatvsn_dev)/$(gcc_lib_dir)/{adalib,adainclude}/gnatvsn
+	mv $(d)/usr/lib/ada/adalib/gnatvsn $(d_lgnatvsn_dev)/$(gcc_lib_dir)/adalib/.
+	mv $(d)/usr/share/ada/adainclude/gnatvsn $(d_lgnatvsn_dev)/$(gcc_lib_dir)/adainclude/.
+	dh_install -p$(p_lgnatvsn_dev) \
+	   debian/gnatvsn.gpr $(gcc_lib_dir)/adainclude
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn_dev) $(usr_lib)/libgnatvsn.a
+	dh_link -p$(p_lgnatvsn_dev) \
+	   $(usr_lib)/libgnatvsn.so.$(GNAT_VERSION) \
+	   $(usr_lib)/libgnatvsn.so
+	debian/dh_doclink -p$(p_lgnatvsn_dev) $(p_glbase)
+	dh_strip -p$(p_lgnatvsn_dev) -X.a --keep-debug
+
+	: # $(p_lgnatvsn)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mkdir -p $(d_lgnatvsn)/usr/share/lintian/overrides
+	cp -p debian/$(p_lgnatvsn).overrides \
+		$(d_lgnatvsn)/usr/share/lintian/overrides/$(p_lgnatvsn)
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn) $(usr_lib)/libgnatvsn.so.$(GNAT_VERSION)
+	debian/dh_doclink -p$(p_lgnatvsn) $(p_glbase)
+	dh_strip -p$(p_lgnatvsn) --dbg-package=$(p_lgnatvsn_dbg)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_lgnatvsn) \
+		-V '$(p_lgnatvsn) (>= $(DEB_VERSION))'
+	$(call cross_mangle_shlibs,$(p_lgnatvsn))
+	cat debian/$(p_lgnatvsn)/DEBIAN/shlibs >> debian/shlibs.local
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_lgnatvsn) \
+		$(call shlibdirs_to_search, \
+			$(subst gnatvsn$(GNAT_SONAME),gcc$(GCC_SONAME),$(p_lgnatvsn)) \
+			$(subst gnatvsn$(GNAT_SONAME),gnat-$(GNAT_SONAME),$(p_lgnatvsn)) \
+		,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_lgnatvsn))
+
+	: # $(p_lgnatvsn_dbg)
+	debian/dh_doclink -p$(p_lgnatvsn_dbg) $(p_glbase)
+
+	echo $(p_lgnatvsn) $(p_lgnatvsn_dev) $(p_lgnatvsn_dbg) >> debian/$(lib_binaries)
+	touch $@
+
+$(binary_stamp)-libgnatprj: $(install_stamp)
+	: # $(p_lgnatprj_dev)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj_dev) usr/lib/ada/adalib/gnatprj
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj_dev) usr/share/ada/adainclude/gnatprj
+	dh_install -p$(p_lgnatprj_dev) \
+	   debian/gnatprj.gpr usr/share/ada/adainclude
+else
+	mkdir -p $(d_lgnatprj_dev)/$(gcc_lib_dir)/{adalib,adainclude}/gnatvsn
+	mv $(d)/usr/lib/ada/adalib/gnatprj $(d_lgnatprj_dev)/$(gcc_lib_dir)/adalib/.
+	mv $(d)/usr/share/ada/adainclude/gnatprj $(d_lgnatprj_dev)/$(gcc_lib_dir)/adainclude/.
+	dh_install -p$(p_lgnatprj_dev) \
+	   debian/gnatprj.gpr $(gcc_lib_dir)/adainclude
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj_dev) $(usr_lib)/libgnatprj.a
+	dh_link -p$(p_lgnatprj_dev) \
+	   $(usr_lib)/libgnatprj.so.$(GNAT_VERSION) \
+	   $(usr_lib)/libgnatprj.so
+	dh_strip -p$(p_lgnatprj_dev) -X.a --keep-debug
+	debian/dh_doclink -p$(p_lgnatprj_dev) $(p_glbase)
+
+	: # $(p_lgnatprj)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mkdir -p $(d_lgnatprj)/usr/share/lintian/overrides
+	cp -p debian/$(p_lgnatprj).overrides \
+		$(d_lgnatprj)/usr/share/lintian/overrides/$(p_lgnatprj)
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj) $(usr_lib)/libgnatprj.so.$(GNAT_VERSION)
+	debian/dh_doclink -p$(p_lgnatprj) $(p_glbase)
+	dh_strip -p$(p_lgnatprj) --dbg-package=$(p_lgnatprj_dbg)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_lgnatprj) \
+		-V '$(p_lgnatprj) (>= $(DEB_VERSION))'
+	$(call cross_mangle_shlibs,$(p_lgnatprj))
+	cat debian/$(p_lgnatprj)/DEBIAN/shlibs >> debian/shlibs.local
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_lgnatprj) \
+		$(call shlibdirs_to_search, \
+			$(subst gnatprj$(GNAT_SONAME),gcc$(GCC_SONAME),$(p_lgnatprj)) \
+			$(subst gnatprj$(GNAT_SONAME),gnat-$(GNAT_SONAME),$(p_lgnatprj)) \
+			$(subst gnatprj$(GNAT_SONAME),gnatvsn$(GNAT_SONAME),$(p_lgnatprj)) \
+		,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_lgnatprj))
+
+	: # $(p_lgnatprj_dbg)
+	debian/dh_doclink -p$(p_lgnatprj_dbg) $(p_glbase)
+
+	echo $(p_lgnatprj) $(p_lgnatprj_dev) $(p_lgnatprj_dbg) >> debian/$(lib_binaries)
+	touch $@
+
+$(binary_stamp)-ada: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+	: # $(p_gnat)
+	rm -rf $(d_gnat)
+	dh_installdirs -p$(p_gnat) $(dirs_gnat)
+	: # Upstream does not install gnathtml.
+	cp src/gcc/ada/gnathtml.pl debian/tmp/$(PF)/bin/$(cmd_prefix)gnathtml$(pkg_ver)
+	chmod 755 debian/tmp/$(PF)/bin/$(cmd_prefix)gnathtml$(pkg_ver)
+	$(dh_compat2) dh_movefiles -p$(p_gnat) $(files_gnat)
+
+ifeq ($(with_gnatsjlj),yes)
+	dh_installdirs -p$(p_gnatsjlj) $(gcc_lib_dir)
+	$(dh_compat2) dh_movefiles -p$(p_gnatsjlj) $(gcc_lib_dir)/rts-sjlj/adalib $(gcc_lib_dir)/rts-sjlj/adainclude
+endif
+
+ifeq ($(with_libgnat),yes)
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  dh_link -p$(p_gnat) \
+	    /$(usr_lib)/$$vlib.so.1 /$(usr_lib)/$$vlib.so \
+	    /$(usr_lib)/$$vlib.so.1 /$(usr_lib)/$$lib.so; \
+	done
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  dh_link -p$(p_gnat) \
+	    /$(usr_lib)/$$vlib.so.1 $(gcc_lib_dir)/$(rts_subdir)adalib/$$lib.so; \
+	done
+endif
+	debian/dh_doclink -p$(p_gnat)      $(p_gbase)
+ifeq ($(with_gnatsjlj),yes)
+	debian/dh_doclink -p$(p_gnatsjlj) $(p_gbase)
+endif
+ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+  ifeq ($(with_check),yes)
+	cp -p test-summary $(d_gnat)/$(docdir)/$(p_gbase)/.
+  endif
+else
+	mkdir -p $(d_gnat)/$(docdir)/$(p_gbase)/ada
+	cp -p src/gcc/ada/ChangeLog $(d_gnat)/$(docdir)/$(p_gbase)/ada/.
+endif
+
+	for i in $(GNAT_TOOLS); do \
+	  case "$$i" in \
+	    gnat) cp -p debian/gnat.1 $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)gnat$(pkg_ver).1 ;; \
+	    *) ln -sf $(cmd_prefix)gnat$(pkg_ver).1 $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)$$i$(pkg_ver).1; \
+	  esac; \
+	done
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	: # still ship the unversioned prefixed names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$(cmd_prefix)$$i; \
+	  ln -sf $(cmd_prefix)gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)$$i.1.gz; \
+	done
+  ifeq ($(unprefixed_names),yes)
+	: # ship the versioned prefixed names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$$i$(pkg_ver); \
+	  ln -sf $(cmd_prefix)gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+
+	: # still ship the unversioned names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$$i; \
+	  ln -sf gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$$i.1.gz; \
+	done
+
+  endif
+else
+	: # still ship the unversioned prefixed names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$(cmd_prefix)$$i; \
+	  ln -sf $(cmd_prefix)gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)$$i.1.gz; \
+	done
+endif
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	dh_install -p$(p_gnat) debian/ada/debian_packaging.mk usr/share/ada
+	mv $(d_gnat)/usr/share/ada/debian_packaging.mk \
+	    $(d_gnat)/usr/share/ada/debian_packaging-$(GNAT_VERSION).mk
+endif
+	: # keep this one unversioned, see Debian #802838.
+	dh_link -p$(p_gnat) \
+		usr/bin/$(cmd_prefix)gcc$(pkg_ver) usr/bin/$(cmd_prefix)gnatgcc
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_link -p$(p_gnat) \
+		usr/share/man/man1/$(cmd_prefix)gcc$(pkg_ver).1.gz \
+		usr/share/man/man1/$(cmd_prefix)gnatgcc.1.gz
+endif
+ifeq ($(unprefixed_names),yes)
+	dh_link -p$(p_gnat) \
+		usr/bin/$(cmd_prefix)gcc$(pkg_ver) usr/bin/gnatgcc
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_link -p$(p_gnat) \
+		usr/share/man/man1/$(cmd_prefix)gcc$(pkg_ver).1.gz \
+		usr/share/man/man1/gnatgcc.1.gz
+  endif
+endif
+	debian/dh_rmemptydirs -p$(p_gnat)
+
+	dh_strip -p$(p_gnat)
+	find $(d_gnat) -name '*.ali' | xargs chmod 444
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_gnat) \
+		$(call shlibdirs_to_search, \
+			$(p_lgcc) $(p_lgnat) $(p_lgnatvsn) $(p_lgnatprj) \
+		,)
+	echo $(p_gnat) >> debian/arch_binaries
+
+ifeq ($(with_gnatsjlj),yes)
+	dh_strip -p$(p_gnatsjlj)
+	find $(d_gnatsjlj) -name '*.ali' | xargs chmod 444
+	$(cross_makeshlibs) dh_shlibdeps -p$(p_gnatsjlj)
+	echo $(p_gnatsjlj) >> debian/arch_binaries
+endif
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+
+$(build_gnatdoc_stamp): $(build_stamp)
+	mkdir -p html
+	rm -f html/*.info
+	echo -n gnat_ugn gnat_rm gnat-style | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'cd html && \
+	    echo "generating {}-$(GNAT_VERSION).info"; \
+	    makeinfo -I $(srcdir)/gcc/doc/include -I $(srcdir)/gcc/ada \
+		-I $(builddir)/gcc \
+		-o {}-$(GNAT_VERSION).info \
+		$(srcdir)/gcc/ada/{}.texi'
+	touch $@
+
+$(binary_stamp)-ada-doc: $(build_html_stamp) $(build_gnatdoc_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gnatd)
+	dh_installdirs -p$(p_gnatd) \
+		$(PF)/share/info
+	cp -p html/gnat*info* $(d_gnatd)/$(PF)/share/info/.
+	dh_installdocs -p$(p_gnatd) \
+	    html/gnat_ugn.html html/gnat_rm.html html/gnat-style.html
+	echo $(p_gnatd) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-base.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-base.mk
@@ -0,0 +1,75 @@
+arch_binaries += base
+ifeq ($(with_gcclbase),yes)
+  ifneq ($(with_base_only),yes)
+    indep_binaries += lbase
+  endif
+endif
+
+# ---------------------------------------------------------------------------
+# gcc-base
+
+ifneq (,$(filter $(distrelease),oneiric precise wheezy sid))
+  additional_links =
+else ifneq (,$(filter $(distrelease),))
+  additional_links =
+else
+  additional_links =
+endif
+
+$(binary_stamp)-base: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_base)
+	dh_installdirs -p$(p_base) \
+		$(gcc_lexec_dir)
+
+ifneq ($(DEB_STAGE),rtlibs)
+	ln -sf $(BASE_VERSION) \
+	    $(d_base)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_lib_dir))
+	for link in $(additional_links); do \
+	  ln -sf $(BASE_VERSION) \
+	    $(d_base)/$$(dirname $(gcc_lib_dir))/$$link; \
+        done
+  ifneq ($(gcc_lib_dir),$(gcc_lexec_dir))
+	ln -sf $(BASE_VERSION) \
+	    $(d_base)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_lexec_dir))
+	for link in $(additional_links); do \
+	  ln -sf $(BASE_VERSION) \
+	    $(d_base)/$$(dirname $(gcc_lexec_dir))/$$link; \
+        done
+  endif
+endif
+
+ifeq ($(with_base_only),yes)
+	dh_installdocs -p$(p_base) debian/README.Debian
+else
+	dh_installdocs -p$(p_base) debian/README.Debian.$(DEB_TARGET_ARCH)
+endif
+	rm -f $(d_base)/usr/share/doc/$(p_base)/README.Debian
+	dh_installchangelogs -p$(p_base)
+	dh_compress -p$(p_base)
+	dh_fixperms -p$(p_base)
+ifeq ($(DEB_STAGE)-$(DEB_CROSS),rtlibs-yes)
+	$(cross_gencontrol) dh_gencontrol -p$(p_base) -- -v$(DEB_VERSION) $(common_substvars)
+else
+	dh_gencontrol -p$(p_base) -- -v$(DEB_VERSION) $(common_substvars)
+endif
+	dh_installdeb -p$(p_base)
+	dh_md5sums -p$(p_base)
+	dh_builddeb -p$(p_base)
+	touch $@
+
+$(binary_stamp)-lbase: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_lbase)
+	dh_installdocs -p$(p_lbase) debian/README.Debian
+	rm -f debian/$(p_lbase)/usr/share/doc/$(p_lbase)/README.Debian
+	dh_installchangelogs -p$(p_lbase)
+	dh_compress -p$(p_lbase)
+	dh_fixperms -p$(p_lbase)
+	dh_gencontrol -p$(p_lbase) -- -v$(DEB_VERSION) $(common_substvars)
+	dh_installdeb -p$(p_lbase)
+	dh_md5sums -p$(p_lbase)
+	dh_builddeb -p$(p_lbase)
+	touch $@
--- gcc-6-6.3.0.orig/debian/rules.d/binary-cpp.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-cpp.mk
@@ -0,0 +1,80 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  arch_binaries  := $(arch_binaries) cpp
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) cpp-doc
+    endif
+  endif
+endif
+
+dirs_cpp = \
+	$(docdir) \
+	$(PF)/share/man/man1 \
+	$(PF)/bin \
+	$(gcc_lexec_dir)
+
+files_cpp = \
+	$(PF)/bin/$(cmd_prefix)cpp$(pkg_ver) \
+	$(gcc_lexec_dir)/cc1 \
+	$(gcc_lexec_dir)/liblto_plugin.so{,.0,.0.0.0}
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_cpp += \
+	$(PF)/share/man/man1/$(cmd_prefix)cpp$(pkg_ver).1
+endif
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-cpp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cpp)
+	dh_installdirs -p$(p_cpp) $(dirs_cpp)
+	$(dh_compat2) dh_movefiles -p$(p_cpp) $(files_cpp)
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)cpp$(pkg_ver) \
+	    $(d_cpp)/$(PF)/bin/cpp$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)cpp$(pkg_ver).1 \
+	    $(d_cpp)/$(PF)/share/man/man1/cpp$(pkg_ver).1
+  endif
+endif
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_cpp)/usr/share/lintian/overrides
+	echo '$(p_cpp) binary: binary-without-manpage' \
+	  >> $(d_cpp)/usr/share/lintian/overrides/$(p_cpp)
+endif
+
+	debian/dh_doclink -p$(p_cpp) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_cpp)
+
+	dh_strip -p$(p_cpp) \
+	  $(if $(unstripped_exe),-X/cc1)
+	dh_shlibdeps -p$(p_cpp)
+	echo $(p_cpp) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-cpp-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cppd)
+	dh_installdirs -p$(p_cppd) \
+		$(docdir)/$(p_xbase) \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_cppd) \
+		$(PF)/share/info/cpp*
+
+	debian/dh_doclink -p$(p_cppd) $(p_xbase)
+	dh_installdocs -p$(p_cppd) html/cpp.html html/cppinternals.html
+	rm -f $(d_cppd)/$(docdir)/$(p_xbase)/copyright
+	debian/dh_rmemptydirs -p$(p_cppd)
+	echo $(p_cppd) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-cxx.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-cxx.mk
@@ -0,0 +1,79 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) cxx-multi
+  endif
+  arch_binaries  := $(arch_binaries) cxx
+endif
+
+dirs_cxx = \
+	$(docdir)/$(p_xbase)/C++ \
+	$(PF)/bin \
+	$(PF)/share/info \
+	$(gcc_lexec_dir) \
+	$(PF)/share/man/man1
+files_cxx = \
+	$(PF)/bin/$(cmd_prefix)g++$(pkg_ver) \
+	$(gcc_lexec_dir)/cc1plus
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_cxx += \
+	$(PF)/share/man/man1/$(cmd_prefix)g++$(pkg_ver).1
+endif
+
+p_cxx_m	= g++$(pkg_ver)-multilib$(cross_bin_arch)
+d_cxx_m	= debian/$(p_cxx_m)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-cxx: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cxx)
+	dh_installdirs -p$(p_cxx) $(dirs_cxx)
+	$(dh_compat2) dh_movefiles -p$(p_cxx) $(files_cxx)
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)g++$(pkg_ver) \
+	    $(d_cxx)/$(PF)/bin/g++$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)g++$(pkg_ver).1.gz \
+	    $(d_cxx)/$(PF)/share/man/man1/g++$(pkg_ver).1.gz
+  endif
+endif
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_cxx)/usr/share/lintian/overrides
+	echo '$(p_cxx) binary: binary-without-manpage' \
+	  >> $(d_cxx)/usr/share/lintian/overrides/$(p_cxx)
+endif
+
+	debian/dh_doclink -p$(p_cxx) $(p_xbase)
+	cp -p debian/README.C++ $(d_cxx)/$(docdir)/$(p_xbase)/C++/
+	cp -p $(srcdir)/gcc/cp/ChangeLog \
+		$(d_cxx)/$(docdir)/$(p_xbase)/C++/changelog
+	debian/dh_rmemptydirs -p$(p_cxx)
+
+	dh_shlibdeps -p$(p_cxx)
+	dh_strip -p$(p_cxx) $(if $(unstripped_exe),-X/cc1plus)
+	echo $(p_cxx) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-cxx-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cxx_m)
+	dh_installdirs -p$(p_cxx_m) \
+		$(docdir)
+
+	debian/dh_doclink -p$(p_cxx_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_cxx_m)
+
+	dh_strip -p$(p_cxx_m)
+	dh_shlibdeps -p$(p_cxx_m)
+	echo $(p_cxx_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-d.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-d.mk
@@ -0,0 +1,261 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) gdc-multi
+  endif
+  arch_binaries := $(arch_binaries) gdc
+
+  ifeq ($(with_libphobos),yes)
+    $(lib_binaries) += libphobos-dev
+    $(lib_binaries) += libphobos
+  endif
+
+  ifeq ($(with_lib64phobosdev),yes)
+    $(lib_binaries)	+= lib64phobos-dev
+  endif
+  ifeq ($(with_lib32phobosdev),yes)
+    $(lib_binaries)	+= lib32phobos-dev
+  endif
+  ifeq ($(with_libn32phobosdev),yes)
+    $(lib_binaries)	+= libn32phobos-dev
+  endif
+  ifeq ($(with_libx32phobosdev),yes)
+    $(lib_binaries)	+= libx32phobos-dev
+  endif
+  ifeq ($(with_libhfphobosdev),yes)
+    $(lib_binaries)	+= libhfphobos-dev
+  endif
+  ifeq ($(with_libsfphobosdev),yes)
+    $(lib_binaries)	+= libsfphobos-dev
+  endif
+
+  ifeq ($(with_lib64phobos),yes)
+    $(lib_binaries)	+= lib64phobos
+  endif
+  ifeq ($(with_lib32phobos),yes)
+    $(lib_binaries)	+= lib32phobos
+  endif
+  ifeq ($(with_libn32phobos),yes)
+    $(lib_binaries)	+= libn32phobos
+  endif
+  ifeq ($(with_libx32phobos),yes)
+    $(lib_binaries)	+= libx32phobos
+  endif
+  ifeq ($(with_libhfphobos),yes)
+    $(lib_binaries)	+= libhfphobos
+  endif
+  ifeq ($(with_libsfphobos),yes)
+    $(lib_binaries)	+= libsfphobos
+  endif
+endif
+
+p_gdc           = gdc$(pkg_ver)$(cross_bin_arch)
+p_gdc_m		= gdc$(pkg_ver)-multilib$(cross_bin_arch)
+p_libphobos     = libgphobos$(GPHOBOS_SONAME)
+p_libphobosdev  = libgphobos$(pkg_ver)-dev
+
+d_gdc           = debian/$(p_gdc)
+d_gdc_m		= debian/$(p_gdc_m)
+d_libphobos     = debian/$(p_libphobos)
+d_libphobosdev  = debian/$(p_libphobosdev)
+
+ifeq ($(DEB_CROSS),yes)
+  gdc_include_dir := $(gcc_lib_dir)/include/d
+else
+  gdc_include_dir := $(PF)/include/d/$(BASE_VERSION)
+endif
+# FIXME: always here?
+gdc_include_dir := $(gcc_lib_dir)/include/d
+
+dirs_gdc = \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(gcc_lexec_dir)
+ifneq ($(DEB_CROSS),yes)
+  dirs_gdc += \
+	$(gdc_include_dir)
+endif
+
+files_gdc = \
+	$(PF)/bin/$(cmd_prefix)gdc$(pkg_ver) \
+	$(gcc_lexec_dir)/cc1d
+ifneq ($(GFDL_INVARIANT_FREE),yes-now-pure-gfdl)
+    files_gdc += \
+	$(PF)/share/man/man1/$(cmd_prefix)gdc$(pkg_ver).1
+endif
+
+dirs_libphobos = \
+	$(PF)/lib \
+	$(gdc_include_dir) \
+	$(gcc_lib_dir)
+
+$(binary_stamp)-gdc: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gdc)
+	dh_installdirs -p$(p_gdc) $(dirs_gdc)
+
+	dh_installdocs -p$(p_gdc) src/gcc/d/README
+	dh_installchangelogs -p$(p_gdc) src/gcc/d/ChangeLog
+
+	$(dh_compat2) dh_movefiles -p$(p_gdc) -X/zlib/ $(files_gdc)
+
+ifeq ($(with_libphobos),yes)
+	mv $(d)/$(usr_lib)/libgphobos.spec $(d_gdc)/$(gcc_lib_dir)/
+endif
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gdc$(pkg_ver) \
+	    $(d_gdc)/$(PF)/bin/gdc$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes-now-pure-gfdl)
+	ln -sf $(cmd_prefix)gdc$(pkg_ver).1 \
+	    $(d_gdc)/$(PF)/share/man/man1/gdc$(pkg_ver).1
+  endif
+endif
+
+# FIXME: __entrypoint.di needs to go into a libgdc-dev Multi-Arch: same package
+	# Always needed by gdc.
+	mkdir -p $(d_gdc)/$(gdc_include_dir)
+	cp $(srcdir)/libphobos/libdruntime/__entrypoint.di \
+	    $(d_gdc)/$(gdc_include_dir)/.
+#ifneq ($(DEB_CROSS),yes)
+#	dh_link -p$(p_gdc) \
+#		/$(gdc_include_dir) \
+#		/$(dir $(gdc_include_dir))/$(GCC_VERSION)
+#endif
+
+	dh_link -p$(p_gdc) \
+		/$(docdir)/$(p_gcc)/README.Bugs \
+		/$(docdir)/$(p_gdc)/README.Bugs
+
+	dh_strip -p$(p_gdc) \
+	  $(if $(unstripped_exe),-X/cc1d)
+	dh_shlibdeps -p$(p_gdc)
+	echo $(p_gdc) >> debian/arch_binaries
+
+	find $(d_gdc) -type d -empty -delete
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-gdc-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gdc_m)
+	dh_installdirs -p$(p_gdc_m) $(docdir)
+
+	debian/dh_doclink -p$(p_gdc_m) $(p_xbase)
+
+	dh_strip -p$(p_gdc_m)
+	dh_shlibdeps -p$(p_gdc_m)
+	echo $(p_gdc_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+define __do_libphobos
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) \
+		$(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(usr_lib$(2))/libgphobos.so.* \
+		$(usr_lib$(2))/libgdruntime.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libgphobos.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+		-- -a$(call mlib_to_arch,$(2)) || echo XXXXXXXXXXX ERROR $(p_l)
+	rm -f debian/$(p_l).symbols
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst gphobos$(GPHOBOS_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	dh_lintian -p$(p_l)
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+define __do_libphobos_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(p_l) \
+		$(gcc_lib_dir$(2))
+
+	$(call install_gcc_lib,libgdruntime,$(GDRUNTIME_SONAME),$(2),$(p_l))
+	$(call install_gcc_lib,libgphobos,$(GPHOBOS_SONAME),$(2),$(p_l))
+
+	$(if $(2),,
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(gdc_include_dir)
+	)
+
+	: # included in gdc package
+	rm -f $(d_l)/$(gdc_include_dir)/__entrypoint.di
+
+	debian/dh_doclink -p$(p_l) \
+		$(if $(filter yes,$(with_separate_gdc)),$(p_gdc),$(p_lbase))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# don't put this as a comment within define/endef
+#	$(call install_gcc_lib,libphobos,$(PHOBOS_SONAME),$(2),$(p_l))
+
+do_libphobos = $(call __do_libphobos,lib$(1)gphobos$(GPHOBOS_SONAME),$(1))
+do_libphobos_dev = $(call __do_libphobos_dev,lib$(1)gphobos-$(BASE_VERSION)-dev,$(1))
+
+$(binary_stamp)-libphobos: $(install_stamp)
+	$(call do_libphobos,)
+
+$(binary_stamp)-lib64phobos: $(install_stamp)
+	$(call do_libphobos,64)
+
+$(binary_stamp)-lib32phobos: $(install_stamp)
+	$(call do_libphobos,32)
+
+$(binary_stamp)-libn32phobos: $(install_stamp)
+	$(call do_libphobos,n32)
+
+$(binary_stamp)-libx32phobos: $(install_stamp)
+	$(call do_libphobos,x32)
+
+$(binary_stamp)-libhfphobos: $(install_stamp)
+	$(call do_libphobos,hf)
+
+$(binary_stamp)-libsfphobos: $(install_stamp)
+	$(call do_libphobos,sf)
+
+
+$(binary_stamp)-libphobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,)
+
+$(binary_stamp)-lib64phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,64)
+
+$(binary_stamp)-lib32phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,32)
+
+$(binary_stamp)-libx32phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,x32)
+
+$(binary_stamp)-libn32phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,n32)
+
+$(binary_stamp)-libhfphobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,hf)
+
+$(binary_stamp)-libsfphobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-fixincl.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-fixincl.mk
@@ -0,0 +1,42 @@
+arch_binaries  := $(arch_binaries) fixincl
+
+p_fix	= fixincludes
+d_fix	= debian/$(p_fix)
+
+dirs_fix = \
+	$(docdir)/$(p_xbase)/fixincludes \
+	$(PF)/share/man/man1 \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir)
+files_fix = \
+	$(gcc_lexec_dir)/install-tools \
+	$(gcc_lib_dir)/install-tools
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fixincl: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_fix)
+	dh_installdirs -p$(p_fix) $(dirs_fix)
+	$(dh_compat2) dh_movefiles -p$(p_fix) $(files_fix)
+
+#	$(IP) $(builddir)/gcc/fixinc/fixincl $(d_fix)/$(PF)/lib/fixincludes/
+#	sed -e "s,^FIXINCL=\(.*\),FIXINCL=/$(PF)/lib/fixincludes/fixincl," \
+#	    $(builddir)/gcc/fixinc.sh \
+#		> $(d_fix)/$(PF)/lib/fixincludes/fixinc.sh
+#	chmod 755 $(d_fix)/$(PF)/lib/fixincludes/fixinc.sh
+	$(IR) $(srcdir)/fixincludes/README \
+	    $(d_fix)/$(docdir)/$(p_xbase)/fixincludes
+	sed -e 's,@LIBEXECDIR@,$(gcc_lexec_dir),g' debian/fixincludes.in \
+	    > $(d_fix)/$(PF)/bin/fixincludes
+	chmod 755 $(d_fix)/$(PF)/bin/fixincludes
+
+	debian/dh_doclink -p$(p_fix) $(p_xbase)
+	dh_strip -p$(p_fix)
+	dh_shlibdeps -p$(p_fix)
+	echo $(p_fix) >> debian/arch_binaries.epoch
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-fortran.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-fortran.mk
@@ -0,0 +1,266 @@
+ifeq ($(with_libgfortran),yes)
+  $(lib_binaries) += libgfortran
+endif
+ifeq ($(with_fdev),yes)
+  $(lib_binaries) += libgfortran-dev
+endif
+ifeq ($(with_lib64gfortran),yes)
+  $(lib_binaries) += lib64fortran
+endif
+ifeq ($(with_lib64gfortrandev),yes)
+  $(lib_binaries) += lib64gfortran-dev
+endif
+ifeq ($(with_lib32gfortran),yes)
+  $(lib_binaries) += lib32fortran
+endif
+ifeq ($(with_lib32gfortrandev),yes)
+  $(lib_binaries) += lib32gfortran-dev
+endif
+ifeq ($(with_libn32gfortran),yes)
+  $(lib_binaries) += libn32fortran
+endif
+ifeq ($(with_libn32gfortrandev),yes)
+  $(lib_binaries) += libn32gfortran-dev
+endif
+ifeq ($(with_libx32gfortran),yes)
+  $(lib_binaries) += libx32fortran
+endif
+ifeq ($(with_libx32gfortrandev),yes)
+  $(lib_binaries) += libx32gfortran-dev
+endif
+ifeq ($(with_libhfgfortran),yes)
+  $(lib_binaries) += libhffortran
+endif
+ifeq ($(with_libhfgfortrandev),yes)
+  $(lib_binaries) += libhfgfortran-dev
+endif
+ifeq ($(with_libsfgfortran),yes)
+  $(lib_binaries) += libsffortran
+endif
+ifeq ($(with_libsfgfortrandev),yes)
+  $(lib_binaries) += libsfgfortran-dev
+endif
+
+ifeq ($(with_fdev),yes)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) fdev-multi
+  endif
+  arch_binaries  := $(arch_binaries) fdev
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) fortran-doc
+    endif
+  endif
+endif
+
+p_g95	= gfortran$(pkg_ver)$(cross_bin_arch)
+p_g95_m	= gfortran$(pkg_ver)-multilib$(cross_bin_arch)
+p_g95d	= gfortran$(pkg_ver)-doc
+p_flib	= libgfortran$(FORTRAN_SONAME)$(cross_lib_arch)
+
+d_g95	= debian/$(p_g95)
+d_g95_m	= debian/$(p_g95_m)
+d_g95d	= debian/$(p_g95d)
+
+dirs_g95 = \
+	$(docdir)/$(p_xbase)/fortran \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir) \
+	$(PF)/include \
+	$(PF)/share/man/man1
+files_g95 = \
+	$(PF)/bin/$(cmd_prefix)gfortran$(pkg_ver) \
+	$(gcc_lib_dir)/finclude \
+	$(gcc_lexec_dir)/f951 
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_g95 += \
+	$(PF)/share/man/man1/$(cmd_prefix)gfortran$(pkg_ver).1
+endif
+
+# ----------------------------------------------------------------------
+define __do_fortran
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libgfortran.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libgfortran.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst gfortran$(FORTRAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst gfortran$(FORTRAN_SONAME),gcc$(QUADMATH_SONAME),$(p_l)) \
+		,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_fortran = $(call __do_fortran,lib$(1)gfortran$(FORTRAN_SONAME),$(1))
+
+
+define __do_libgfortran_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(1) $(gcc_lib_dir$(2))
+
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(gcc_lib_dir$(2))/libcaf_single.a
+	$(call install_gcc_lib,libgfortran,$(FORTRAN_SONAME),$(2),$(p_l))
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_l)
+
+	dh_strip -p$(p_l)
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_l)
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+# ----------------------------------------------------------------------
+
+do_libgfortran_dev = $(call __do_libgfortran_dev,lib$(1)gfortran-$(BASE_VERSION)-dev,$(1))
+
+$(binary_stamp)-libgfortran: $(install_stamp)
+	$(call do_fortran,)
+
+$(binary_stamp)-lib64fortran: $(install_stamp)
+	$(call do_fortran,64)
+
+$(binary_stamp)-lib32fortran: $(install_stamp)
+	$(call do_fortran,32)
+
+$(binary_stamp)-libn32fortran: $(install_stamp)
+	$(call do_fortran,n32)
+
+$(binary_stamp)-libx32fortran: $(install_stamp)
+	$(call do_fortran,x32)
+
+$(binary_stamp)-libhffortran: $(install_stamp)
+	$(call do_fortran,hf)
+
+$(binary_stamp)-libsffortran: $(install_stamp)
+	$(call do_fortran,sf)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fdev: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_g95)
+	dh_installdirs -p$(p_g95) $(dirs_g95)
+
+	$(dh_compat2) dh_movefiles -p$(p_g95) $(files_g95)
+
+	mv $(d)/$(usr_lib)/libgfortran.spec $(d_g95)/$(gcc_lib_dir)/
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gfortran$(pkg_ver) \
+	    $(d_g95)/$(PF)/bin/gfortran$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)gfortran$(pkg_ver).1 \
+	    $(d_g95)/$(PF)/share/man/man1/gfortran$(pkg_ver).1
+  endif
+endif
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_g95)/usr/share/lintian/overrides
+	echo '$(p_g95) binary: binary-without-manpage' \
+	  >> $(d_g95)/usr/share/lintian/overrides/$(p_g95)
+endif
+
+	debian/dh_doclink -p$(p_g95) $(p_xbase)
+
+	cp -p $(srcdir)/gcc/fortran/ChangeLog \
+		$(d_g95)/$(docdir)/$(p_xbase)/fortran/changelog
+	debian/dh_rmemptydirs -p$(p_g95)
+
+	dh_strip -p$(p_g95) \
+	  $(if $(unstripped_exe),-X/f951)
+	dh_shlibdeps -p$(p_g95)
+	echo $(p_g95) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fdev-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_g95_m)
+	dh_installdirs -p$(p_g95_m) $(docdir)
+
+	debian/dh_doclink -p$(p_g95_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_g95_m)
+	dh_strip -p$(p_g95_m)
+	dh_shlibdeps -p$(p_g95_m)
+	echo $(p_g95_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fortran-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_g95d)
+	dh_installdirs -p$(p_g95d) \
+		$(docdir)/$(p_xbase)/fortran \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_g95d) \
+		$(PF)/share/info/gfortran*
+
+	debian/dh_doclink -p$(p_g95d) $(p_xbase)
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_installdocs -p$(p_g95d)
+	rm -f $(d_g95d)/$(docdir)/$(p_xbase)/copyright
+	cp -p html/gfortran.html $(d_g95d)/$(docdir)/$(p_xbase)/fortran/
+endif
+	echo $(p_g95d) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-libgfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,)
+
+$(binary_stamp)-lib64gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,64)
+
+$(binary_stamp)-lib32gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,32)
+
+$(binary_stamp)-libn32gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,n32)
+
+$(binary_stamp)-libx32gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,x32)
+
+$(binary_stamp)-libhfgfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,hf)
+
+$(binary_stamp)-libsfgfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,sf)
+
--- gcc-6-6.3.0.orig/debian/rules.d/binary-gcc.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-gcc.mk
@@ -0,0 +1,359 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) gcc-multi
+  endif
+  ifeq ($(with_plugins),yes)
+    arch_binaries  := $(arch_binaries) gcc-plugindev
+  endif
+
+  arch_binaries  := $(arch_binaries) gcc
+
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) gcc-doc
+    endif
+    ifeq ($(with_nls),yes)
+      indep_binaries := $(indep_binaries) gcc-locales
+    endif
+  endif
+
+  ifeq ($(build_type),build-native)
+    arch_binaries  := $(arch_binaries) testresults
+  endif
+endif
+
+# gcc must be moved after g77 and g++
+# not all files $(PF)/include/*.h are part of gcc,
+# but it becomes difficult to name all these files ...
+
+dirs_gcc = \
+	$(docdir)/$(p_xbase)/{gcc,libssp,gomp,itm,quadmath,sanitizer,cilkrts,mpx} \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir)/{include,include-fixed} \
+	$(PF)/share/man/man1 $(libgcc_dir)
+
+# XXX: what about triarch mapping?
+files_gcc = \
+	$(PF)/bin/$(cmd_prefix){gcc,gcov,gcov-tool,gcov-dump}$(pkg_ver) \
+	$(PF)/bin/$(cmd_prefix)gcc-{ar,ranlib,nm}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix)gcc-{ar,nm,ranlib}$(pkg_ver).1 \
+	$(gcc_lexec_dir)/{collect2,lto1,lto-wrapper} \
+	$(shell test -e $(d)/$(gcc_lib_dir)/SYSCALLS.c.X \
+		&& echo $(gcc_lib_dir)/SYSCALLS.c.X)
+
+ifeq ($(with_libcc1_plugin),yes)
+    files_gcc += \
+	$(gcc_lib_dir)/plugin/libcc1plugin.so{,.0,.0.0.0}
+endif
+
+ifeq ($(DEB_STAGE),stage1)
+    files_gcc += \
+	$(gcc_lib_dir)/include \
+	$(shell for h in \
+		  README limits.h syslimits.h; \
+		do \
+		  test -e $(d)/$(gcc_lib_dir)/include-fixed/$$h \
+		    && echo $(gcc_lib_dir)/include-fixed/$$h; \
+		done)
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+    files_gcc += \
+	$(PF)/share/man/man1/$(cmd_prefix){gcc,gcov}$(pkg_ver).1
+endif
+
+usr_doc_files = debian/README.Bugs \
+	$(shell test -f $(srcdir)/FAQ && echo $(srcdir)/FAQ)
+
+p_loc	= gcc$(pkg_ver)-locales
+d_loc	= debian/$(p_loc)
+
+p_gcc_m	= gcc$(pkg_ver)-multilib$(cross_bin_arch)
+d_gcc_m	= debian/$(p_gcc_m)
+
+p_pld	= gcc$(pkg_ver)-plugin-dev$(cross_bin_arch)
+d_pld	= debian/$(p_pld)
+
+p_tst	= gcc$(pkg_ver)-test-results
+d_tst	= debian/$(p_tst)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gcc)
+	dh_installdirs -p$(p_gcc) $(dirs_gcc)
+
+ifeq ($(with_linaro_branch),yes)
+	if [ -f $(srcdir)/gcc/ChangeLog.linaro ]; then \
+	  cp -p $(srcdir)/gcc/ChangeLog.linaro \
+		$(d_gcc)/$(docdir)/$(p_xbase)/changelog.linaro; \
+	fi
+endif
+ifeq ($(with_libssp),yes)
+	cp -p $(srcdir)/libssp/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/libssp/changelog
+endif
+ifeq ($(with_gomp),yes)
+	mv $(d)/$(usr_lib)/libgomp*.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libgomp/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/gomp/changelog
+endif
+ifeq ($(with_itm),yes)
+	mv $(d)/$(usr_lib)/libitm*.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libitm/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/itm/changelog
+endif
+ifeq ($(with_qmath),yes)
+	cp -p $(srcdir)/libquadmath/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/quadmath/changelog
+endif
+ifeq ($(with_asan),yes)
+	mv $(d)/$(usr_lib)/libsanitizer*.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libsanitizer/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/sanitizer/changelog
+endif
+ifeq ($(with_cilkrts),yes)
+	mv $(d)/$(usr_lib)/libcilkrts.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libcilkrts/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/cilkrts/changelog
+endif
+ifeq ($(with_mpx),yes)
+	mv $(d)/$(usr_lib)/libmpx.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libmpx/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/mpx/changelog
+endif
+ifeq ($(with_cc1),yes)
+	rm -f $(d)/$(PF)/lib/$(DEB_HOST_MULTIARCH)/libcc1.so
+	dh_link -p$(p_gcc) \
+	    /$(PF)/lib/$(DEB_HOST_MULTIARCH)/libcc1.so.$(CC1_SONAME) \
+	    /$(gcc_lib_dir)/libcc1.so
+endif
+
+	$(dh_compat2) dh_movefiles -p$(p_gcc) $(files_gcc)
+
+ifeq ($(unprefixed_names),yes)
+	for i in gcc gcov gcov-dump gcov-tool gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gcc)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gcc gcov gcov-tool; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_gcc)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  endif
+	for i in gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_gcc)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+endif
+
+#	dh_installdebconf
+	debian/dh_doclink -p$(p_gcc) $(p_xbase)
+	cp -p $(usr_doc_files) $(d_gcc)/$(docdir)/$(p_xbase)/.
+	cp -p debian/README.ssp $(d_gcc)/$(docdir)/$(p_xbase)/
+	cp -p debian/NEWS.gcc $(d_gcc)/$(docdir)/$(p_xbase)/NEWS
+	cp -p debian/NEWS.html $(d_gcc)/$(docdir)/$(p_xbase)/NEWS.html
+	cp -p $(srcdir)/ChangeLog $(d_gcc)/$(docdir)/$(p_xbase)/changelog
+	cp -p $(srcdir)/gcc/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/gcc/changelog
+	if [ -f $(builddir)/gcc/.bad_compare ]; then \
+	  ( \
+	    echo "The comparision of the stage2 and stage3 object files shows differences."; \
+	    echo "The Debian package was modified to ignore these differences."; \
+	    echo ""; \
+	    echo "The following files differ:"; \
+	    echo ""; \
+	    cat $(builddir)/gcc/.bad_compare; \
+	  ) > $(d_gcc)/$(docdir)/$(p_xbase)/BOOTSTRAP_COMPARISION_FAILURE; \
+	else \
+	  true; \
+	fi
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_gcc)/usr/share/lintian/overrides
+	echo '$(p_gcc) binary: binary-without-manpage' \
+	  >> $(d_gcc)/usr/share/lintian/overrides/$(p_gcc)
+endif
+
+	debian/dh_rmemptydirs -p$(p_gcc)
+	dh_strip -p$(p_gcc) \
+	  $(if $(unstripped_exe),-X/lto1)
+	dh_shlibdeps -p$(p_gcc)
+	echo $(p_gcc) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+
+$(binary_stamp)-gcc-multi: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gcc_m)
+	dh_installdirs -p$(p_gcc_m) $(docdir)
+
+	debian/dh_doclink -p$(p_gcc_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_gcc_m)
+
+	dh_strip -p$(p_gcc_m)
+	dh_shlibdeps -p$(p_gcc_m)
+	echo $(p_gcc_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc-plugindev: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_pld)
+	dh_installdirs -p$(p_pld) \
+		$(docdir) \
+		$(gcc_lib_dir)/plugin
+	$(dh_compat2) dh_movefiles -p$(p_pld) \
+		$(gcc_lib_dir)/plugin/include \
+		$(gcc_lib_dir)/plugin/gtype.state \
+		$(gcc_lexec_dir)/plugin/gengtype
+
+	debian/dh_doclink -p$(p_pld) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_pld)
+	dh_strip -p$(p_pld)
+	dh_shlibdeps -p$(p_pld)
+	echo $(p_pld) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc-locales: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_loc)
+	dh_installdirs -p$(p_loc) \
+		$(docdir)
+	$(dh_compat2) dh_movefiles -p$(p_loc) \
+		$(PF)/share/locale/*/*/cpplib*.* \
+		$(PF)/share/locale/*/*/gcc*.*
+
+	debian/dh_doclink -p$(p_loc) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_loc)
+	echo $(p_loc) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+
+# ----------------------------------------------------------------------
+
+$(binary_stamp)-testresults: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_tst)
+	dh_installdirs -p$(p_tst) $(docdir)
+
+	debian/dh_doclink -p$(p_tst) $(p_xbase)
+
+	mkdir -p $(d_tst)/$(docdir)/$(p_xbase)/test
+	echo "TEST COMPARE BEGIN"
+ifeq ($(with_check),yes)
+	for i in test-summary testsuite-comparision; do \
+	  [ -f $$i ] || continue; \
+	  cp -p $$i $(d_tst)/$(docdir)/$(p_xbase)/$$i; \
+	done
+# more than one libgo.sum, avoid it
+	cp -p $$(find $(builddir)/gcc/testsuite -maxdepth 2 \( -name '*.sum' -o -name '*.log' \)) \
+	      $$(find $(buildlibdir)/*/testsuite -maxdepth 1 \( -name '*.sum'  -o -name '*.log' \) ! -name 'libgo.*') \
+		$(d_tst)/$(docdir)/$(p_xbase)/test/
+  ifeq ($(with_go),yes)
+	cp -p $(buildlibdir)/libgo/libgo.sum \
+		$(d_tst)/$(docdir)/$(p_xbase)/test/
+  endif
+  ifeq (0,1)
+	cd $(builddir); \
+	for i in $(CURDIR)/$(d_tst)/$(docdir)/$(p_xbase)/test/*.sum; do \
+	  b=$$(basename $$i); \
+	  if [ -f /usr/share/doc/$(p_xbase)/test/$$b.gz ]; then \
+	    zcat /usr/share/doc/$(p_xbase)/test/$$b.gz > /tmp/$$b; \
+	    if sh $(srcdir)/contrib/test_summary /tmp/$$b $$i; then \
+	      echo "$$b: OK"; \
+	    else \
+	      echo "$$b: FAILURES"; \
+	    fi; \
+	    rm -f /tmp/$$b; \
+	  else \
+	    echo "Test summary for $$b is not available"; \
+	  fi; \
+	done
+  endif
+	if which xz 2>&1 >/dev/null; then \
+	  echo -n $(d_tst)/$(docdir)/$(p_xbase)/test/* \
+	    | xargs -d ' ' -L 1 -P $(USE_CPUS)	xz -7v; \
+	fi
+else
+	echo "Nothing to compare (testsuite not run)"
+	echo 'Test run disabled, reason: $(with_check)' \
+	  > $(d_tst)/$(docdir)/$(p_xbase)/test-run-disabled
+endif
+	echo "TEST COMPARE END"
+
+	debian/dh_rmemptydirs -p$(p_tst)
+
+	echo $(p_tst) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_doc)
+	dh_installdirs -p$(p_doc) \
+		$(docdir)/$(p_xbase) \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_doc) \
+		$(PF)/share/info/cpp{,internals}-* \
+		$(PF)/share/info/gcc{,int}-* \
+		$(PF)/share/info/lib{gomp,itm}-* \
+		$(if $(with_qmath),$(PF)/share/info/libquadmath-*)
+	rm -f $(d_doc)/$(PF)/share/info/gccinst*
+
+ifeq ($(with_gomp),yes)
+	$(MAKE) -C $(buildlibdir)/libgomp stamp-build-info
+	cp -p $(buildlibdir)/libgomp/$(cmd_prefix)libgomp$(pkg_ver).info \
+		$(d_doc)/$(PF)/share/info/libgomp$(pkg_ver).info
+endif
+ifeq ($(with_itm),yes)
+	-$(MAKE) -C $(buildlibdir)/libitm stamp-build-info
+	if [ -f $(buildlibdir)/libitm/libitm$(pkg_ver).info ]; then \
+	  cp -p $(buildlibdir)/libitm/$(cmd_prefix)libitm$(pkg_ver).info \
+		$(d_doc)/$(PF)/share/info/; \
+	fi
+endif
+
+	debian/dh_doclink -p$(p_doc) $(p_xbase)
+	dh_installdocs -p$(p_doc) html/gcc.html html/gccint.html
+ifeq ($(with_gomp),yes)
+	cp -p html/libgomp.html $(d_doc)/usr/share/doc/$(p_doc)/
+endif
+ifeq ($(with_itm),yes)
+	cp -p html/libitm.html $(d_doc)/usr/share/doc/$(p_doc)/
+endif
+ifeq ($(with_qmath),yes)
+	cp -p html/libquadmath.html $(d_doc)/usr/share/doc/$(p_doc)/
+endif
+	rm -f $(d_doc)/$(docdir)/$(p_xbase)/copyright
+	debian/dh_rmemptydirs -p$(p_doc)
+	echo $(p_doc) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-go.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-go.mk
@@ -0,0 +1,329 @@
+ifeq ($(with_libgo),yes)
+  $(lib_binaries) += libgo
+endif
+ifeq ($(with_lib64go),yes)
+  $(lib_binaries) += lib64go
+endif
+ifeq ($(with_lib32go),yes)
+  $(lib_binaries) += lib32go
+endif
+ifeq ($(with_libn32go),yes)
+  $(lib_binaries) += libn32go
+endif
+ifeq ($(with_libx32go),yes)
+  $(lib_binaries) += libx32go
+endif
+
+ifneq ($(DEB_STAGE),rtlibs)
+  arch_binaries  := $(arch_binaries) gccgo
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32)))
+    arch_binaries  := $(arch_binaries) gccgo-multi
+  endif
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) go-doc
+    endif
+  endif
+endif
+
+p_go	= gccgo$(pkg_ver)$(cross_bin_arch)
+p_go_m	= gccgo$(pkg_ver)-multilib$(cross_bin_arch)
+p_god	= gccgo$(pkg_ver)-doc
+p_golib	= libgo$(GO_SONAME)$(cross_lib_arch)
+
+d_go	= debian/$(p_go)
+d_go_m	= debian/$(p_go_m)
+d_god	= debian/$(p_god)
+d_golib	= debian/$(p_golib)
+
+dirs_go = \
+	$(docdir)/$(p_xbase)/go \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir) \
+	$(PF)/include \
+	$(PF)/share/man/man1
+files_go = \
+	$(PF)/bin/$(cmd_prefix)gccgo$(pkg_ver) \
+	$(gcc_lexec_dir)/go1
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  files_go += \
+	$(PF)/bin/$(cmd_prefix){go,gofmt}$(pkg_ver) \
+	$(gcc_lexec_dir)/cgo \
+	$(PF)/share/man/man1/$(cmd_prefix){go,gofmt}$(pkg_ver).1
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_go += \
+	$(PF)/share/man/man1/$(cmd_prefix)gccgo$(pkg_ver).1
+endif
+
+ifeq ($(with_standalone_go),yes)
+
+  dirs_go += \
+	$(gcc_lib_dir)/include \
+	$(PF)/share/man/man1
+
+# XXX: what about triarch mapping?
+  files_go += \
+	$(PF)/bin/$(cmd_prefix){cpp,gcc,gcov,gcov-tool}$(pkg_ver) \
+	$(PF)/bin/$(cmd_prefix)gcc-{ar,ranlib,nm}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix)gcc-{ar,nm,ranlib}$(pkg_ver).1 \
+	$(gcc_lexec_dir)/{cc1,collect2,lto1,lto-wrapper} \
+	$(gcc_lexec_dir)/liblto_plugin.so{,.0,.0.0.0} \
+	$(gcc_lib_dir)/{libgcc*,libgcov.a,*.o} \
+	$(header_files) \
+	$(shell test -e $(d)/$(gcc_lib_dir)/SYSCALLS.c.X \
+		&& echo $(gcc_lib_dir)/SYSCALLS.c.X)
+
+  ifeq ($(with_cc1),yes)
+    files_go += \
+	$(gcc_lib_dir)/plugin/libcc1plugin.so{,.0,.0.0.0}
+  endif
+
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    files_go += \
+	$(PF)/share/man/man1/$(cmd_prefix){cpp,gcc,gcov,gcov-tool}$(pkg_ver).1
+  endif
+
+  ifeq ($(biarch64),yes)
+    files_go += $(gcc_lib_dir)/$(biarch64subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarch32),yes)
+    files_go += $(gcc_lib_dir)/$(biarch32subdir)/{libgcc*,*.o}
+  endif
+  ifeq ($(biarchn32),yes)
+    files_go += $(gcc_lib_dir)/$(biarchn32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarchx32),yes)
+    files_go += $(gcc_lib_dir)/$(biarchx32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+endif
+
+# ----------------------------------------------------------------------
+define __do_gccgo
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(usr_lib$(2))/libgo.so.* $(usr_lib$(2))/go
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	mkdir -p debian/$(p_l)/usr/share/lintian/overrides
+	echo '$(p_l) binary: unstripped-binary-or-object' \
+	  >> debian/$(p_l)/usr/share/lintian/overrides/$(p_l)
+
+	: # don't strip: https://gcc.gnu.org/ml/gcc-patches/2015-02/msg01722.html
+	: # dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst go$(GO_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst go$(GO_SONAME),atomic$(ATOMIC_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_gccgo = $(call __do_gccgo,lib$(1)go$(GO_SONAME),$(1))
+
+define install_gccgo_lib
+	mv $(d)/$(usr_lib$(3))/$(1).a debian/$(4)/$(gcc_lib_dir$(3))/
+	if [ -f $(d)/$(usr_lib$(3))/$(1)libbegin.a ]; then \
+	  mv $(d)/$(usr_lib$(3))/$(1)libbegin.a debian/$(4)/$(gcc_lib_dir$(3))/; \
+	fi
+	rm -f $(d)/$(usr_lib$(3))/$(1)*.{la,so}
+	dh_link -p$(4) \
+	  /$(usr_lib$(3))/$(1).so.$(2) /$(gcc_lib_dir$(3))/$(1).so
+endef
+
+# __do_gccgo_libgcc(flavour,package,todir,fromdir)
+define __do_gccgo_libgcc
+	$(if $(findstring gccgo,$(PKGSOURCE)),
+		: # libgcc_s.so may be a linker script on some architectures
+		set -e; \
+		if [ -h $(4)/libgcc_s.so ]; then \
+		  rm -f $(4)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    $(3)/libgcc_s.so; \
+		else \
+		  mv $(4)/libgcc_s.so $(d)/$(3)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    $(3)/libgcc_s.so.$(GCC_SONAME); \
+		fi; \
+		$(if $(1), dh_link -p$(2) /$(3)/libgcc_s.so \
+		    $(gcc_lib_dir)/libgcc_s_$(1).so;)
+	)
+endef
+
+define do_go_dev
+	dh_installdirs -p$(2) $(gcc_lib_dir$(1))
+	$(dh_compat2) dh_movefiles -p$(2) \
+		$(gcc_lib_dir$(1))/{libgobegin,libnetgo}.a
+	$(if $(filter yes, $(with_standalone_go)), \
+	  $(call install_gccgo_lib,libgomp,$(GOMP_SONAME),$(1),$(2)))
+	$(call install_gccgo_lib,libgo,$(GO_SONAME),$(1),$(2))
+	$(call __do_gccgo_libgcc,$(1),$(2),$(gcc_lib_dir$(1)),$(d)/$(usr_lib$(1)))
+endef
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgo: $(install_stamp)
+	$(call do_gccgo,)
+
+$(binary_stamp)-lib64go: $(install_stamp)
+	$(call do_gccgo,64)
+
+$(binary_stamp)-lib32go: $(install_stamp)
+	$(call do_gccgo,32)
+
+$(binary_stamp)-libn32go: $(install_stamp)
+	$(call do_gccgo,n32)
+
+$(binary_stamp)-libx32go: $(install_stamp)
+	$(call do_gccgo,x32)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gccgo: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_go)
+	dh_installdirs -p$(p_go) $(dirs_go)
+
+	mv $(d)/$(usr_lib)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/
+	if [ -f $(d)/$(usr_lib64)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_lib64)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/64/; \
+	fi
+	if [ -f $(d)/$(usr_lib32)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_lib32)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/32/; \
+	fi
+	if [ -f $(d)/$(usr_libn32)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_libn32)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/n32/; \
+	fi
+	if [ -f $(d)/$(usr_libx32)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_libx32)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/x32/; \
+	fi
+
+	$(call do_go_dev,,$(p_go))
+
+	$(dh_compat2) dh_movefiles -p$(p_go) $(files_go)
+
+ifneq (,$(findstring gccgo,$(PKGSOURCE)))
+	rm -rf $(d_go)/$(gcc_lib_dir)/include/cilk
+	rm -rf $(d_go)/$(gcc_lib_dir)/include/openacc.h
+endif
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gccgo$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/gccgo$(pkg_ver)
+	ln -sf $(cmd_prefix)go$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/go$(pkg_ver)
+	ln -sf $(cmd_prefix)gofmt$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/gofmt$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)gccgo$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/gccgo$(pkg_ver).1
+  endif
+	ln -sf $(cmd_prefix)go$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/go$(pkg_ver).1
+	ln -sf $(cmd_prefix)gofmt$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/gofmt$(pkg_ver).1
+endif
+
+ifeq ($(with_standalone_go),yes)
+  ifeq ($(unprefixed_names),yes)
+	for i in gcc gcov gcov-tool gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gcc gcov gcov-tool gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)gcc$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/$$i$(pkg_ver).1; \
+	done
+    endif
+  endif
+  ifeq ($(with_gomp),yes)
+	mv $(d)/$(usr_lib)/libgomp*.spec $(d_go)/$(gcc_lib_dir)/
+  endif
+  ifeq ($(with_cc1),yes)
+	rm -f $(d)/$(usr_lib)/libcc1.so
+	dh_link -p$(p_go) \
+		/$(usr_lib)/libcc1.so.$(CC1_SONAME) /$(gcc_lib_dir)/libcc1.so
+  endif
+endif
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_go)/usr/share/lintian/overrides
+	echo '$(p_go) binary: binary-without-manpage' \
+	  >> $(d_go)/usr/share/lintian/overrides/$(p_go)
+endif
+
+	debian/dh_doclink -p$(p_go) $(p_xbase)
+
+#	cp -p $(srcdir)/gcc/go/ChangeLog \
+#		$(d_go)/$(docdir)/$(p_base)/go/changelog
+	debian/dh_rmemptydirs -p$(p_go)
+
+	dh_strip -v -p$(p_go) -X/cgo -X/go$(pkg_ver) -X/gofmt$(pkg_ver) \
+	  $(if $(unstripped_exe),-X/go1)
+	dh_shlibdeps -p$(p_go)
+	echo $(p_go) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gccgo-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_go_m)
+	dh_installdirs -p$(p_go_m) $(docdir)
+
+	$(foreach flavour,$(flavours), \
+		$(call do_go_dev,$(flavour),$(p_go_m)))
+
+	debian/dh_doclink -p$(p_go_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_go_m)
+	dh_strip -p$(p_go_m)
+	dh_shlibdeps -p$(p_go_m)
+	echo $(p_go_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-go-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_god)
+	dh_installdirs -p$(p_god) \
+		$(docdir)/$(p_xbase)/go \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_god) \
+		$(PF)/share/info/gccgo*
+
+	debian/dh_doclink -p$(p_god) $(p_xbase)
+	dh_installdocs -p$(p_god)
+	rm -f $(d_god)/$(docdir)/$(p_xbase)/copyright
+	cp -p html/gccgo.html $(d_god)/$(docdir)/$(p_xbase)/go/
+	echo $(p_god) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-hppa64.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-hppa64.mk
@@ -0,0 +1,32 @@
+arch_binaries  := $(arch_binaries) hppa64
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-hppa64: $(install_hppa64_stamp)
+	dh_testdir
+	dh_testroot
+
+#	dh_installdirs -p$(p_hppa64)
+
+	rm -f $(d_hppa64)/usr/lib/libiberty.a
+	-find $(d_hppa64) ! -type d
+
+	: # provide as and ld links
+	dh_link -p $(p_hppa64) \
+		/usr/bin/hppa64-linux-gnu-as \
+		/$(hppa64libexecdir)/gcc/hppa64-linux-gnu/$(versiondir)/as \
+		/usr/bin/hppa64-linux-gnu-ld \
+		/$(hppa64libexecdir)/gcc/hppa64-linux-gnu/$(versiondir)/ld
+
+	debian/dh_doclink -p$(p_hppa64) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_hppa64)
+
+	dh_strip -p$(p_hppa64) -X.o -Xlibgcc.a -Xlibgcov.a
+	dh_shlibdeps -p$(p_hppa64)
+
+	mkdir -p $(d_hppa64)/usr/share/lintian/overrides
+	cp -p debian/$(p_hppa64).overrides \
+		$(d_hppa64)/usr/share/lintian/overrides/$(p_hppa64)
+
+	echo $(p_hppa64) >> debian/arch_binaries
+
+	touch $@
--- gcc-6-6.3.0.orig/debian/rules.d/binary-java.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-java.mk
@@ -0,0 +1,769 @@
+ifeq ($(with_gcj_base_only),yes)
+  arch_binaries  := $(arch_binaries) jbase
+else
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    arch_binaries  := $(arch_binaries) jbase
+  endif
+endif
+
+ifeq ($(with_libgcj),yes)
+  ifeq ($(with_java),yes)
+    arch_binaries  := $(arch_binaries) java gcjjre
+    indep_binaries  := $(indep_binaries) libgcjjar
+  endif
+
+  ifeq ($(with_javadev),yes)
+    arch_binaries  := $(arch_binaries) gcjjdk libgcjdev libgcjdbg
+    ifneq ($(DEB_CROSS),yes)
+      indep_binaries := $(indep_binaries) libgcjsrc
+      ifeq ($(with_libgcj_doc),yes)
+        indep_binaries := $(indep_binaries) libgcjdoc
+      endif
+    endif
+  endif
+endif
+
+ifeq ($(with_gcj),yes)
+    arch_binaries  := $(arch_binaries) gcj
+endif
+endif
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  p_jbase = gcj$(pkg_ver)-base
+  ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),no-no)
+    p_jbase = gcc$(pkg_ver)-base
+  endif
+else
+  p_jbase = gcj$(pkg_ver)$(cross_bin_arch)-base
+  ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),no-no)
+    p_jbase = gcc$(pkg_ver)$(cross_bin_arch)-base
+  endif
+endif
+
+p_gcj	= gcj$(pkg_ver)$(cross_bin_arch)
+p_jdk	= gcj$(pkg_ver)-jdk$(cross_bin_arch)
+p_jrehl	= gcj$(pkg_ver)-jre-headless$(cross_bin_arch)
+p_jre	= gcj$(pkg_ver)-jre$(cross_bin_arch)
+p_jar	= gcj$(pkg_ver)-jre-lib$(cross_bin_arch)
+p_jsrc	= gcj$(pkg_ver)-source
+p_jlib	= libgcj$(PKG_LIBGCJ_EXT)$(cross_lib_arch)
+p_jdbg	= libgcj$(PKG_GCJ_EXT)-dbg$(cross_lib_arch)
+p_jlibx	= libgcj$(PKG_LIBGCJ_EXT)-awt$(cross_lib_arch)
+p_jgtk	= libgcj$(PKG_GCJ_EXT)-awt-gtk$(cross_lib_arch)
+p_jqt	= libgcj$(PKG_GCJ_EXT)-awt-qt$(cross_lib_arch)
+p_jdev	= libgcj$(PKG_GCJ_EXT)-dev$(cross_lib_arch)
+p_jdoc	= libgcj-doc
+
+d_jbase	= debian/$(p_jbase)
+d_gcj	= debian/$(p_gcj)
+d_jdk	= debian/$(p_jdk)
+d_jrehl	= debian/$(p_jrehl)
+d_jar	= debian/$(p_jar)
+d_jsrc	= debian/$(p_jsrc)
+d_jlib	= debian/$(p_jlib)
+d_jdbg	= debian/$(p_jdbg)
+d_jlibx	= debian/$(p_jlibx)
+d_jgtk	= debian/$(p_jgtk)
+d_jqt	= debian/$(p_jqt)
+d_jdev	= debian/$(p_jdev)
+d_jdoc	= debian/$(p_jdoc)
+d_jre	= debian/$(p_jre)
+
+GCJ_BASE_VERSION = $(BASE_VERSION)
+
+gcj_vlibdir	= $(PF)/$(libdir)/gcj-$(BASE_VERSION)-$(GCJ_SONAME)
+
+jre_tools = java keytool orbd rmid rmiregistry tnameserv
+jdk_tools = appletviewer jar jarsigner javac javadoc javah native2ascii rmic serialver
+
+dirs_gcj = \
+	$(docdir)/$(p_jbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(gcc_lexec_dir)
+
+files_gcj = \
+	$(PF)/bin/$(cmd_prefix)gcj$(pkg_ver) \
+	$(gcc_lexec_dir)/{jc1,jvgenmain}
+
+# FIXME: this really should be included, or else the cross compiler
+# can only be used to build libjava itself.
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  files_gcj += \
+	$(PF)/$(libdir)/libgcj.spec
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_gcj += \
+	$(PF)/share/man/man1/$(cmd_prefix)gcj$(pkg_ver).1
+endif
+
+dirs_jdk = \
+	$(docdir)/$(p_jbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(PF)/share/info \
+	$(gcc_lexec_dir) \
+	$(jvm_dir)/bin
+
+files_jdk = \
+	$(PF)/bin/$(cmd_prefix){gappletviewer,gjdoc,gc-analyze,gjar,gjarsigner,gcjh,gjavah,gnative2ascii,grmic,gserialver,jv-convert,jcf-dump}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix){gappletviewer,gjdoc,gjar,gjarsigner,gcjh,gjavah,gnative2ascii,gserialver}$(pkg_ver).1 \
+	$(gcc_lib_dir)/include/{jni.h,jni_md.h,jvmpi.h} \
+	$(gcc_lib_dir)/include/{jawt.h,jawt_md.h} \
+	$(gcc_lib_dir)/include/gcj/libgcj-config.h \
+	$(PF)/$(libdir)/lib{gij,gcj,gcj-tools}.so \
+	$(jvm_dir)/include \
+	$(jvm_dir)/bin/{appletviewer,jar,jarsigner,javadoc,javah,native2ascii,rmic,serialver} \
+	$(PF)/lib/jvm-exports
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_jdk += \
+	$(PF)/share/info/gcj* \
+	$(PF)/share/man/man1/$(cmd_prefix){gc-analyze,grmic,jv-convert,jcf-dump}$(pkg_ver).1
+endif
+
+dirs_jrehl = \
+	$(docdir)/$(p_jbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(jvm_dir)/bin \
+	$(jvm_dir)/jre/lib \
+	$(jvm_dir)/lib \
+	var/lib/gcj$(pkg_ver)
+
+files_jrehl = \
+	$(PF)/bin/$(cmd_prefix){gij,gcj-dbtool,gorbd,grmid,grmiregistry,gkeytool,gtnameserv}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix){gorbd,grmid,grmiregistry,gkeytool,gtnameserv}$(pkg_ver).1 \
+	$(jvm_dir)/jre/bin \
+	$(jvm_dir)/bin/{java,keytool,orbd,rmid,rmiregistry,tnameserv} \
+	$(jvm_dir)/jre/lib/rt.jar \
+	$(jvm_dir)/jre/lib/$(java_cpu)/{client,server} \
+	$(jvm_dir)/lib/tools.jar
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_jrehl += \
+	$(PF)/share/man/man1/$(cmd_prefix){gij,gcj-dbtool}$(pkg_ver).1
+endif
+
+dirs_jre = \
+	$(docdir)/$(p_jbase) \
+	$(jvm_dir)/jre/lib/$(java_cpu)
+
+files_jre = \
+	$(jvm_dir)/jre/lib/$(java_cpu)/libjawt.so
+
+dirs_jlib = \
+	$(docdir)/$(p_jbase) \
+	$(gcj_vlibdir) \
+	$(PF)/$(libdir) \
+	$(jvm_dir)/jre/lib
+
+files_jlib = \
+	$(PF)/$(libdir)/libgij.so.* \
+	$(PF)/$(libdir)/libgcj-tools.so.* \
+	$(PF)/$(libdir)/libgcj.so.* \
+	$(gcj_vlibdir)/libjvm.so \
+	$(gcj_vlibdir)/libjavamath.so \
+	$(jvm_dir)/jre/lib/security
+
+#	$(gcj_vlibdir)/libgconfpeer.so
+
+ifeq ($(with_java_alsa),yes)
+  files_jlib += \
+	$(gcj_vlibdir)/libgjsmalsa.so
+endif
+
+dirs_jar = \
+	$(PF)/share/java
+
+files_jar = \
+	$(PF)/share/java/libgcj-$(BASE_VERSION).jar \
+	$(PF)/share/java/libgcj-tools-$(BASE_VERSION).jar
+
+dirs_jlibx = \
+	$(PF)/$(libdir) \
+	$(gcj_vlibdir) \
+	$(PF)/share/java
+
+files_jlibx = \
+	$(gcj_vlibdir)/libjawt.so \
+	$(gcj_vlibdir)/libgtkpeer.so
+
+#files_jgtk = \
+#	$(gcj_vlibdir)/libgtkpeer.so
+#files_jqt = \
+#	$(gcj_vlibdir)/libqtpeer.so
+
+dirs_jdev = \
+	$(PF)/{include,lib} \
+	$(jvm_dir)/include
+
+files_jdev = \
+	$(PF)/include/c++/$(BASE_VERSION)/{org,gcj,java,javax} \
+	$(PF)/include/c++/$(BASE_VERSION)/gnu/{awt,classpath,gcj,java,javax} \
+	$(PF)/$(libdir)/pkgconfig/libgcj-$(BASE_VERSION).pc \
+	$(gcj_vlibdir)/lib*peer.so
+
+ifeq ($(with_static_java),yes)
+  files_jdev += \
+	$(PF)/$(libdir)/libgij.a \
+	$(PF)/$(libdir)/libgcj.a \
+	$(PF)/$(libdir)/libgcj-tools.a
+endif
+
+ifeq (,$(p_l64gcc))
+  p_l64gcc = lib64gcc$(GCC_SONAME)
+  d_l64gcc = debian/$(p_l64gcc)
+endif
+
+ifeq ($(with_standalone_gcj),yes)
+
+  dirs_gcj += \
+	$(gcc_lib_dir)/include \
+	$(PF)/share/man/man1
+
+# XXX: what about triarch mapping?
+  files_gcj += \
+	$(PF)/bin/$(cmd_prefix){cpp,gcc,gcov}$(pkg_ver) \
+	$(gcc_lexec_dir)/{collect2,lto1,lto-wrapper} \
+	$(gcc_lexec_dir)/liblto_plugin.so{,.0,.0.0.0} \
+	$(gcc_lib_dir)/{libgcc*,libgcov.a,*.o} \
+	$(header_files) \
+	$(shell test -e $(d)/$(gcc_lib_dir)/SYSCALLS.c.X \
+		&& echo $(gcc_lib_dir)/SYSCALLS.c.X)
+
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    files_gcj += \
+	$(PF)/share/man/man1/$(cmd_prefix){cpp,gcc,gcov}$(pkg_ver).1
+  endif
+
+  ifeq ($(biarch64),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarch64subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarch32),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarch32subdir)/{libgcc*,*.o}
+  endif
+  ifeq ($(biarchn32),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarchn32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarchx32),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarchx32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+endif
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-jbase: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_jbase)
+	dh_installdirs -p$(p_jbase)
+	dh_installdocs -p$(p_jbase)
+	dh_installchangelogs -p$(p_jbase)
+	dh_compress -p$(p_jbase)
+	dh_fixperms -p$(p_jbase)
+	dh_gencontrol -p$(p_jbase) -- -v$(DEB_VERSION) $(common_substvars)
+	dh_installdeb -p$(p_jbase)
+	dh_md5sums -p$(p_jbase)
+	dh_builddeb -p$(p_jbase)
+	touch $@
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcj: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gcj)
+	dh_installdirs -p$(p_gcj)  $(dirs_gcj)
+
+	$(dh_compat2) dh_movefiles -p$(p_gcj)  $(files_gcj)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mv $(d_gcj)/$(PF)/$(libdir)/libgcj.spec $(d_gcj)/$(gcc_lib_dir)/
+endif
+
+ifeq ($(with_external_ecj1),yes)
+	dh_link -p$(p_gcj) \
+		/$(PF)/lib/$(DEB_HOST_MULTIARCH)/gcc/ecj1 /$(gcc_lexec_dir)/ecj1
+endif
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gcj$(pkg_ver) \
+	    $(d_gcj)/$(PF)/bin/gcj$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)gcj$(pkg_ver).1.gz \
+	    $(d_gcj)/$(PF)/share/man/man1/gcj$(pkg_ver).1.gz
+  endif
+endif
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_gcj)/usr/share/lintian/overrides
+	echo '$(p_gcj) binary: binary-without-manpage' \
+	  >> $(d_gcj)/usr/share/lintian/overrides/$(p_gcj)
+endif
+
+	debian/dh_doclink -p$(p_gcj) $(p_jbase)
+	debian/dh_rmemptydirs -p$(p_gcj)
+
+	dh_strip -p$(p_gcj) \
+	  $(if $(unstripped_exe),-X/jc1)
+	dh_shlibdeps -p$(p_gcj) -Xecj1
+	echo $(p_gcj) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgcjjar: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jar) $(dirs_jar)
+	$(dh_compat2) dh_movefiles -p$(p_jar) $(files_jar)
+
+	ln -sf libgcj-$(BASE_VERSION).jar \
+		$(d_jar)/$(PF)/share/java/libgcj-$(GCC_VERSION).jar
+	ln -sf libgcj-tools-$(BASE_VERSION).jar \
+		$(d_jar)/$(PF)/share/java/libgcj-tools-$(GCC_VERSION).jar
+	debian/dh_doclink -p$(p_jar) $(p_jbase)
+	debian/dh_rmemptydirs -p$(p_jar)
+	echo $(p_jar) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(build_javasrc_stamp): $(build_stamp)
+	PATH=$(CURDIR)/bin:$$PATH \
+	  $(MAKE) -C $(buildlibdir)/libjava src.zip
+	touch $@
+
+$(binary_stamp)-libgcjsrc: $(install_stamp) $(build_javasrc_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdirs -p$(p_jsrc) $(PF)/share/java $(jvm_dir)
+	cp -p $(buildlibdir)/libjava/src.zip \
+	   $(d_jsrc)/$(PF)/share/java/libgcj-src-$(BASE_VERSION).zip
+	dh_link -p$(p_jsrc) \
+		$(PF)/share/java/libgcj-src-$(BASE_VERSION).zip \
+		$(jvm_dir)/src.zip
+	debian/dh_doclink -p$(p_jsrc) $(p_jbase)
+	debian/dh_rmemptydirs -p$(p_jsrc)
+	echo $(p_jsrc) >> debian/indep_binaries
+
+	touch $@
+
+# ----------------------------------------------------------------------
+libgcj_version = $$($(builddir)/gcc/xgcc -B$(builddir)/gcc/ --version \
+			 | sed -n '/^xgcc/s/[^)]*) *\(.*\)/\1/p' | sed 's/ \[[^[]*$$//')
+libgcj_title = LibGCJ Classpath
+libgcjhbox_href = http://gcc.gnu.org/java
+libgcjhbox = <span class='logo'><a href='$(libgcjhbox_href)' target='_top'>$(title)</a> ($(libgcj_version))
+
+$(build_javadoc_stamp): $(build_stamp) $(build_javasrc_stamp)
+	mkdir -p $(builddir)/java-src
+	cd $(builddir)/java-src && fastjar -xf $(buildlibdir)/libjava/src.zip
+
+	mkdir -p $(builddir)/html
+	$(buildlibdir)/libjava/gjdoc \
+	    -licensetext \
+	    -use \
+	    -sourcepath "$(builddir)/java-src" \
+	    -encoding UTF-8 \
+	    -breakiterator \
+	    -linksource \
+	    -splitindex \
+	    -d $(builddir)/html \
+	    -doctitle "$(libgcj_title) $(libgcj_version)" \
+	    -windowtitle "$(libgcj_title) $(libgcj_version) Documentation" \
+	    -header "$(classpathbox)" \
+	    -footer "$(classpathbox)" \
+	    -subpackages gnu:java:javax:org
+
+	touch $@
+
+$(binary_stamp)-libgcjdoc: $(install_stamp) $(build_javadoc_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdocs -p$(p_jdoc)
+	sed -i 's/gcc$(pkg_ver)-base/$(p_jbase)/' $(d_jdoc)/usr/share/doc-base/libgcj-doc
+	dh_installchangelogs -p$(p_jdoc)
+	mkdir -p $(d_jdoc)/usr/share/doc/$(p_jbase)
+	cp -al $(builddir)/html $(d_jdoc)/usr/share/doc/$(p_jbase)/api
+	ln -sf api $(d_jdoc)/usr/share/doc/$(p_jbase)/html
+	ln -sf ../$(p_jbase)/api $(d_jdoc)/usr/share/doc/$(p_jdoc)/api
+	ln -sf ../$(p_jbase)/html $(d_jdoc)/usr/share/doc/$(p_jdoc)/html
+	echo $(p_jdoc) >> debian/indep_binaries
+
+	touch $@
+
+# ----------------------------------------------------------------------
+
+#peer_pkgs =
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#  peer_pkgs += -p$(p_jgtk)
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#  peer_pkgs += -p$(p_jqt)
+#endif
+
+$(binary_stamp)-java: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jrehl)   $(dirs_jrehl)
+	dh_installdirs -p$(p_jlib)  $(dirs_jlib)
+	dh_installdirs -p$(p_jlibx) $(dirs_jlibx)
+
+	$(dh_compat2) dh_movefiles -p$(p_jrehl)   $(files_jrehl)
+	$(dh_compat2) dh_movefiles -p$(p_jlib)  $(files_jlib)
+	$(dh_compat2) dh_movefiles -p$(p_jlibx) $(files_jlibx)
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	$(dh_compat2) dh_movefiles -p$(p_jgtk) $(files_jgtk)
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	$(dh_compat2) dh_movefiles -p$(p_jqt) $(files_jqt)
+#endif
+
+ifeq ($(unprefixed_names),yes)
+	for i in gij gcj-dbtool gorbd grmid grmiregistry gkeytool gtnameserv; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_jrehl)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+	for i in gorbd grmid grmiregistry gkeytool gtnameserv; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jrehl)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gij gcj-dbtool; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jrehl)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  endif
+endif
+
+	dh_link -p$(p_jrehl) \
+	  $(jvm_dir) $(PF)/lib/jvm/java-gcj$(pkg_ver) \
+	  $(PF)/bin/$(cmd_prefix)gij$(pkg_ver) $(jvm_dir)/bin/gij \
+	  $(PF)/bin/$(cmd_prefix)gij$(pkg_ver) $(jvm_dir)/jre/bin/gij \
+	  $(PF)/bin/$(cmd_prefix)gcj-dbtool$(pkg_ver) $(jvm_dir)/bin/gcj-dbtool \
+	  $(PF)/bin/$(cmd_prefix)gcj-dbtool$(pkg_ver) $(jvm_dir)/jre/bin/gcj-dbtool \
+	  $(PF)/share/man/man1/$(cmd_prefix)gkeytool$(pkg_ver).1 $(jvm_dir)/man/man1/keytool.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gorbd$(pkg_ver).1 $(jvm_dir)/man/man1/orbd.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)grmid$(pkg_ver).1 $(jvm_dir)/man/man1/rmid.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)grmiregistry$(pkg_ver).1 $(jvm_dir)/man/man1/rmiregistry.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gtnameserv$(pkg_ver).1 $(jvm_dir)/man/man1/tnameserv.1 \
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_link -p$(p_jrehl) \
+	  $(PF)/share/man/man1/$(cmd_prefix)gij$(pkg_ver).1 $(jvm_dir)/man/man1/java.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)grmic$(pkg_ver).1 $(jvm_dir)/man/man1/rmiregistry.1
+endif
+
+ifneq ($(DEB_TARGET_ARCH_CPU),$(java_cpu))
+	ln -sf $(java_cpu) $(d_jlib)/$(jvm_dir)/jre/lib/$(DEB_TARGET_ARCH_CPU)
+endif
+
+	dh_link -p$(p_jlib) \
+	  /etc/java/cacerts-gcj /$(jvm_dir)/jre/lib/cacerts \
+	  $(foreach i, jvm javamath, \
+		/$(gcj_vlibdir)/lib$(i).so /$(jvm_dir)/lib/lib$(i).so)
+
+	dh_link -p$(p_jlib) \
+	  /etc/java/security/classpath.security \
+	  /$(jvm_dir)/jre/lib/security/java.security
+
+	dh_link -p$(p_jlibx) \
+	  $(foreach i, jawt, $(gcj_vlibdir)/lib$(i).so $(jvm_dir)/lib/lib$(i).so)
+
+ifeq ($(DEB_HOST_ARCH),hppa)
+	mv $(d_jrehl)/$(PF)/bin/$(cmd_prefix)gij$(pkg_ver) \
+		$(d_jrehl)/$(PF)/bin/$(cmd_prefix)gij$(pkg_ver).bin
+	install -m755 debian/gij-hppa $(d_jrehl)/$(PF)/bin/$(cmd_prefix)gij$(pkg_ver)
+  ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gij$(pkg_ver) \
+	    $(d_jrehl)/$(PF)/bin/gij$(pkg_ver)
+	ln -sf $(cmd_prefix)gij$(pkg_ver).bin \
+	    $(d_jrehl)/$(PF)/bin/gij$(pkg_ver).bin
+  endif
+endif
+
+	ln -s ../libgcj.so.$(GCJ_SONAME) \
+		$(d_jlib)/$(gcj_vlibdir)/libgcj_bc.so.1
+
+	: # provide .jinfo file
+	( \
+	  echo 'name=$(jvm_name_short)'; \
+	  echo 'alias=java-gcj$(pkg_ver)'; \
+	  echo 'priority=$(priority)'; \
+	  echo 'section=main'; \
+	  echo ''; \
+	  for i in $(jre_tools); do \
+	    echo "jre $$i /$(jvm_dir)/jre/bin/$$i"; \
+	  done; \
+	  for i in $(jdk_tools); do \
+	    echo "jdk $$i /$(jvm_dir)/bin/$$i"; \
+	  done; \
+	) > $(d_jrehl)/usr/lib/jvm/.java-gcj$(pkg_ver).jinfo
+
+ifneq (,$(findstring gcj,$(p_jbase)))
+	cp -p $(srcdir)/libjava/{NEWS,README,THANKS} \
+		$(d_jrehl)/usr/share/doc/$(p_jbase)/
+endif
+	debian/dh_doclink -p$(p_jrehl) $(p_jbase)
+	debian/dh_doclink -p$(p_jlib)  $(p_jbase)
+	debian/dh_doclink -p$(p_jlibx) $(p_jbase)
+
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	debian/dh_doclink -p$(p_jgtk) $(p_jbase)
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	debian/dh_doclink -p$(p_jqt) $(p_jbase)
+#endif
+
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    ifeq ($(with_check),yes)
+	cp -p test-summary $(d_jrehl)/usr/share/doc/$(p_jbase)/test-summary
+    endif
+  endif
+endif
+	debian/dh_rmemptydirs -p$(p_jrehl)
+	debian/dh_rmemptydirs -p$(p_jlib)
+	debian/dh_rmemptydirs -p$(p_jlibx)
+
+	mkdir -p $(d_jrehl)/var/lib/gcj$(pkg_ver)
+
+	dh_makeshlibs $(ldconfig_arg) -p$(p_jlib) -V '$(p_jlib) (>= $(DEB_GCJ_SOVERSION))'
+	echo "libgcj_bc 1 libgcj-bc (>= 4.2.2-1)" >> debian/$(p_jlib)/DEBIAN/shlibs
+	cat debian/$(p_jlib)/DEBIAN/shlibs >> debian/shlibs.local
+
+	dh_makeshlibs $(ldconfig_arg) -p$(p_jlibx) -V '$(p_jlibx) (>= $(DEB_GCJ_SOVERSION))'
+
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	dh_makeshlibs $(ldconfig_arg) -p$(p_jgtk) -V '$(p_jgtk) (>= $(DEB_GCJ_SOVERSION))'
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	dh_makeshlibs $(ldconfig_arg) -p$(p_jqt) -V '$(p_jqt) (>= $(DEB_GCJ_SOVERSION))'
+#endif
+
+	dh_strip -X/bin/ --dbg-package=$(p_jdbg) \
+		-p$(p_jrehl) -p$(p_jlib) -p$(p_jlibx) $(peer_pkgs)
+	rm -f $(d_jdbg)/$(gcc_lib_dir)/libgcj_bc.so
+
+	mkdir -p $(d_jlib)/usr/share/lintian/overrides
+	cp -p debian/$(p_jlib).overrides \
+		$(d_jlib)/usr/share/lintian/overrides/$(p_jlib)
+	mkdir -p $(d_jlibx)/usr/share/lintian/overrides
+	cp -p debian/$(p_jlibx).overrides \
+		$(d_jlibx)/usr/share/lintian/overrides/$(p_jlibx)
+	mkdir -p $(d_jrehl)/usr/share/lintian/overrides
+	cp -p debian/$(p_jrehl).overrides \
+		$(d_jrehl)/usr/share/lintian/overrides/$(p_jrehl)
+
+# the libstdc++ binary packages aren't built yet ...
+	echo 'libstdc++ $(CXX_SONAME) libstdc++$(CXX_SONAME) (>= $(DEB_STDCXX_SOVERSION))' \
+	    >> debian/shlibs.local
+	-[ -d $(d_l64gcc) ] && mv $(d_l64gcc) $(d_l64gcc).saved
+ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),yes-no)
+	dh_shlibdeps \
+		-L$(p_jlib) \
+		-l$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir) \
+		-p$(p_jrehl) -p$(p_jlib) -p$(p_jlibx) $(peer_pkgs)
+else
+	dh_shlibdeps \
+		-L$(p_lgcc) \
+		-L$(p_jlib) \
+		-l:$(d)/$(PF)/$(libdir):$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir):$(d_lgcc)/lib \
+		-p$(p_jrehl) -p$(p_jlib) -p$(p_jlibx) $(peer_pkgs)
+endif
+	-[ -d $(d_l64gcc).saved ] && mv $(d_l64gcc).saved $(d_l64gcc)
+	sed -e 's/$(p_jlib)[^,]*//' -e 's/, *,/,/' debian/$(p_jlib).substvars \
+		>> debian/$(p_jlib).substvars.tmp \
+	    && mv -f debian/$(p_jlib).substvars.tmp debian/$(p_jlib).substvars
+	rm -f debian/shlibs.local
+
+	echo $(p_jrehl) $(p_jlib) $(p_jlibx) $(subst -p,,$(peer_pkgs)) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcjjdk: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jdk)
+	dh_installdirs -p$(p_jdk)  $(dirs_jdk)
+
+#	mkdir -p $(d_jdk)/usr/share/lintian/overrides
+#	cp -p debian/$(p_jdk).overrides \
+#		$(d_jdk)/usr/share/lintian/overrides/$(p_jdk)
+	cp -p $(srcdir)/gcc/java/ChangeLog \
+		$(d_jdk)/usr/share/doc/$(p_jbase)/changelog.gcj
+	cp -p $(srcdir)/libjava/ChangeLog \
+		$(d_jdk)/usr/share/doc/$(p_jbase)/changelog.libjava
+
+ifeq ($(with_standalone_gcj),yes)
+	rm -f $(d)/$(PF)/$(libdir)/libgcc_s.so
+	ln -sf /$(libdir)/libgcc_s.so.$(GCC_SONAME) $(d)/$(gcc_lib_dir)/libgcc_s.so
+endif
+	$(dh_compat2) dh_movefiles -p$(p_jdk)  $(files_jdk)
+
+	for i in libgij libgcj libgcj-tools; do \
+	  dh_link -p$(p_jdk) \
+	    /$(PF)/$(libdir)/$$i.so.$(GCJ_SONAME) /$(gcc_lib_dir)/$$i.so \
+	    /$(PF)/$(libdir)/$$i.so.$(GCJ_SONAME) /$(jvm_dir)/lib/$$i.so; \
+	  rm -f $(d_jdk)/$(PF)/$(libdir)/$$i.{la,so}; \
+	done
+
+	install -m755 debian/jdb.sh $(d_jdk)/$(jvm_dir)/bin/jdb
+
+	install -m 755 $(d)/$(PF)/$(libdir)/libgcj_bc.so.1 \
+		$(d_jdk)/$(gcc_lib_dir)/libgcj_bc.so
+	$(CC_FOR_TARGET) $(LDFLAGS_FOR_TARGET) -shared -fpic -xc /dev/null \
+		-o build/libgcj.so -Wl,-soname,libgcj.so.$(GCJ_SONAME) -nostdlib
+	$(CC_FOR_TARGET) $(LDFLAGS_FOR_TARGET) -shared -fpic \
+		$(srcdir)/libjava/libgcj_bc.c \
+		-o $(d_jdk)/$(gcc_lib_dir)/libgcj_bc.so \
+		-Wl,-soname,libgcj_bc.so.1 $(builddir)/libgcj.so -shared-libgcc 
+
+	dh_link -p$(p_jdk) \
+	  $(gcc_lib_dir)/include/gcj $(jvm_dir)/include/gcj \
+	  usr/bin/ecj $(jvm_dir)/bin/javac \
+	  usr/bin/fastjar $(jvm_dir)/bin/jar \
+	  $(PF)/share/man/man1/ecj.1.gz $(jvm_dir)/man/man1/javac.1.gz \
+	  $(PF)/share/man/man1/fastjar.1.gz $(jvm_dir)/man/man1/jar.1.gz
+
+ifeq ($(unprefixed_names),yes)
+	for i in gappletviewer gjdoc gc-analyze gjar gjarsigner gcjh gjavah gnative2ascii grmic gserialver jv-convert jcf-dump; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_jdk)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+	for i in gappletviewer gjdoc gjar gjarsigner gcjh gjavah gnative2ascii gserialver; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jdk)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gc-analyze gnative2ascii grmic jv-convert jcf-dump; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jdk)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  endif
+endif
+
+	dh_link -p$(p_jdk) \
+	  $(PF)/bin/$(cmd_prefix)gcj$(pkg_ver) $(jvm_dir)/bin/gcj \
+	  $(PF)/share/man/man1/$(cmd_prefix)gjarsigner$(pkg_ver).1 $(jvm_dir)/man/man1/jarsigner.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gjdoc$(pkg_ver).1 $(jvm_dir)/man/man1/javadoc.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gjavah$(pkg_ver).1 $(jvm_dir)/man/man1/javah.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gserialver$(pkg_ver).1 $(jvm_dir)/man/man1/serialver.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gappletviewer$(pkg_ver).1 $(jvm_dir)/man/man1/appletviewer.1
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	cp -p html/gcj.html $(d_jdk)/$(docdir)/$(p_jbase)/
+endif
+	debian/dh_doclink -p$(p_jdk) $(p_jbase)
+
+	cp -p debian/FAQ.gcj $(d_jdk)/$(docdir)/$(p_jbase)/
+
+	cp -p debian/gcj-wrapper$(pkg_ver) \
+		$(d_jdk)/$(PF)/bin/$(cmd_prefix)gcj-wrapper$(pkg_ver)
+	chmod 755 $(d_jdk)/$(PF)/bin/$(cmd_prefix)gcj-wrapper$(pkg_ver)
+	cp -p debian/gcj-wrapper$(pkg_ver).1 \
+		$(d_jdk)/$(PF)/share/man/man1/$(cmd_prefix)gcj-wrapper$(pkg_ver).1
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gcj-wrapper$(pkg_ver) \
+	    $(d_jdk)/$(PF)/bin/gcj-wrapper$(pkg_ver)
+	  ln -sf $(cmd_prefix)gcj-wrapper$(pkg_ver).1.gz \
+	    $(d_jdk)/$(PF)/share/man/man1/gcj-wrapper$(pkg_ver).1.gz
+endif
+
+	debian/dh_rmemptydirs -p$(p_jdk)
+
+	dh_strip -p$(p_jdk)
+	dh_shlibdeps -p$(p_jdk) -l$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/lib -Xecj1
+	echo $(p_jdk) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgcjdev: $(build_html_stamp) $(install_stamp) $(binary_stamp)-java
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jdev) $(dirs_jdev)
+
+	$(dh_compat2) dh_movefiles -p$(p_jdev) $(files_jdev)
+
+ifeq ($(with_static_java),yes)
+	for i in libgij libgcj libgcj-tools; do \
+	  mv $(d_jdev)/$(PF)/$(libdir)/$$i.a $(d_jdev)/$(gcc_lib_dir)/; \
+	done
+endif
+
+	ln -sf libgcj-$(BASE_VERSION).pc \
+		$(d_jdev)/$(PF)/$(libdir)/pkgconfig/libgcj$(PKG_GCJ_EXT).pc
+	sed -i -e 's,-[IL][^ ]* *,,' \
+		$(d_jdev)/$(PF)/$(libdir)/pkgconfig/libgcj-$(BASE_VERSION).pc
+
+	debian/dh_doclink -p$(p_jdev) $(p_jbase)
+
+	debian/dh_rmemptydirs -p$(p_jdev)
+
+#	mkdir -p $(d_jdev)/usr/share/lintian/overrides
+#	cp -p debian/libgcj$(PKG_GCJ_EXT)-dev.overrides \
+#		$(d_jdev)/usr/share/lintian/overrides/$(p_jdev)
+
+	DH_COMPAT=5 dh_strip -p$(p_jdev) --dbg-package=$(p_jdbg)
+ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),yes-no)
+	dh_shlibdeps \
+		-l$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir) \
+		-p$(p_jdev)
+else
+	dh_shlibdeps \
+		-L$(p_lgcc) \
+		-l:$(d)/$(PF)/$(libdir):$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir):$(d_lgcc)/lib \
+		-p$(p_jdev)
+endif
+	echo $(p_jdev) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgcjdbg: $(install_stamp) $(binary_stamp)-java $(binary_stamp)-libgcjdev $(binary_stamp)-gcjjre
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	debian/dh_doclink -p$(p_jdbg) $(p_jbase)
+
+	for i in libgij libgcj libgcj-tools; do \
+	  if [ -f $(d_jdbg)/usr/lib/debug/usr/lib/$$i.so.$(GCJ_SONAME).0.0 ]; then \
+	    ln -sf $$i.so.$(GCJ_SONAME).0.0 \
+	      $(d_jdbg)/usr/lib/debug/usr/lib/$$i.so.$(GCJ_SONAME); \
+	  fi; \
+	done
+#	ln -sf libgconfpeer.so.0.0.0 \
+#	  $(d_jdbg)/usr/lib/debug/$(gcj_vlibdir)/libgconfpeer.so.0
+	echo $(p_jdbg) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcjjre: $(install_stamp) $(binary_stamp)-java
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jre) $(dirs_jre)
+	$(dh_compat2) dh_movefiles -p$(p_jre)   $(files_jre)
+
+	debian/dh_doclink -p$(p_jre) $(p_jbase)
+	DH_COMPAT=5 dh_strip -p$(p_jre) --dbg-package=$(p_jdbg)
+	echo $(p_jre) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libasan.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libasan.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libasan
+ifeq ($(with_lib64asan),yes)
+  $(lib_binaries)  += lib64asan
+endif
+ifeq ($(with_lib32asan),yes)
+  $(lib_binaries)	+= lib32asan
+endif
+ifeq ($(with_libn32asan),yes)
+  $(lib_binaries)	+= libn32asan
+endif
+ifeq ($(with_libx32asan),yes)
+  $(lib_binaries)	+= libx32asan
+endif
+ifeq ($(with_libhfasan),yes)
+  $(lib_binaries)	+= libhfasan
+endif
+ifeq ($(with_libsfasan),yes)
+  $(lib_binaries)	+= libsfasan
+endif
+
+define __do_asan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libasan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) || echo XXXXXXXXXXXXXX ERROR $(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst asan$(ASAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst asan$(ASAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_asan = $(call __do_asan,lib$(1)asan$(ASAN_SONAME),$(1))
+
+$(binary_stamp)-libasan: $(install_stamp)
+	$(call do_asan,)
+
+$(binary_stamp)-lib64asan: $(install_stamp)
+	$(call do_asan,64)
+
+$(binary_stamp)-lib32asan: $(install_stamp)
+	$(call do_asan,32)
+
+$(binary_stamp)-libn32asan: $(install_stamp)
+	$(call do_asan,n32)
+
+$(binary_stamp)-libx32asan: $(install_stamp)
+	$(call do_asan,x32)
+
+$(binary_stamp)-libhfasan: $(install_dependencies)
+	$(call do_asan,hf)
+
+$(binary_stamp)-libsfasan: $(install_dependencies)
+	$(call do_asan,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libatomic.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libatomic.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libatomic
+ifeq ($(with_lib64atomic),yes)
+  $(lib_binaries)  += lib64atomic
+endif
+ifeq ($(with_lib32atomic),yes)
+  $(lib_binaries)	+= lib32atomic
+endif
+ifeq ($(with_libn32atomic),yes)
+  $(lib_binaries)	+= libn32atomic
+endif
+ifeq ($(with_libx32atomic),yes)
+  $(lib_binaries)	+= libx32atomic
+endif
+ifeq ($(with_libhfatomic),yes)
+  $(lib_binaries)	+= libhfatomic
+endif
+ifeq ($(with_libsfatomic),yes)
+  $(lib_binaries)	+= libsfatomic
+endif
+
+define __do_atomic
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libatomic.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libatomic.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_atomic = $(call __do_atomic,lib$(1)atomic$(ATOMIC_SONAME),$(1))
+
+$(binary_stamp)-libatomic: $(install_stamp)
+	$(call do_atomic,)
+
+$(binary_stamp)-lib64atomic: $(install_stamp)
+	$(call do_atomic,64)
+
+$(binary_stamp)-lib32atomic: $(install_stamp)
+	$(call do_atomic,32)
+
+$(binary_stamp)-libn32atomic: $(install_stamp)
+	$(call do_atomic,n32)
+
+$(binary_stamp)-libx32atomic: $(install_stamp)
+	$(call do_atomic,x32)
+
+$(binary_stamp)-libhfatomic: $(install_dependencies)
+	$(call do_atomic,hf)
+
+$(binary_stamp)-libsfatomic: $(install_dependencies)
+	$(call do_atomic,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libcc1.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libcc1.mk
@@ -0,0 +1,31 @@
+ifeq ($(with_libcc1),yes)
+  ifneq ($(DEB_CROSS),yes)
+    arch_binaries  := $(arch_binaries) libcc1
+  endif
+endif
+
+p_cc1	= libcc1-$(CC1_SONAME)
+d_cc1	= debian/$(p_cc1)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libcc1: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cc1)
+	dh_installdirs -p$(p_cc1) \
+		$(docdir) \
+		$(usr_lib)
+	$(dh_compat2) dh_movefiles -p$(p_cc1) \
+		$(usr_lib)/libcc1.so.*
+
+	debian/dh_doclink -p$(p_cc1) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_cc1)
+
+	dh_strip -p$(p_cc1)
+	dh_makeshlibs -p$(p_cc1)
+	dh_shlibdeps -p$(p_cc1)
+	echo $(p_cc1) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libcilkrts.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libcilkrts.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libcilkrts
+ifeq ($(with_lib64cilkrts),yes)
+  $(lib_binaries)  += lib64cilkrts
+endif
+ifeq ($(with_lib32cilkrts),yes)
+  $(lib_binaries)	+= lib32cilkrts
+endif
+ifeq ($(with_libn32cilkrts),yes)
+  $(lib_binaries)	+= libn32cilkrts
+endif
+ifeq ($(with_libx32cilkrts),yes)
+  $(lib_binaries)	+= libx32cilkrts
+endif
+ifeq ($(with_libhfcilkrts),yes)
+  $(lib_binaries)	+= libhfcilkrts
+endif
+ifeq ($(with_libsfcilkrts),yes)
+  $(lib_binaries)	+= libsfcilkrts
+endif
+
+define __do_cilkrts
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libcilkrts.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libcilkrts.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst cilkrts$(CILKRTS_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst cilkrts$(CILKRTS_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_cilkrts = $(call __do_cilkrts,lib$(1)cilkrts$(CILKRTS_SONAME),$(1))
+
+$(binary_stamp)-libcilkrts: $(install_stamp)
+	$(call do_cilkrts,)
+
+$(binary_stamp)-lib64cilkrts: $(install_stamp)
+	$(call do_cilkrts,64)
+
+$(binary_stamp)-lib32cilkrts: $(install_stamp)
+	$(call do_cilkrts,32)
+
+$(binary_stamp)-libn32cilkrts: $(install_stamp)
+	$(call do_cilkrts,n32)
+
+$(binary_stamp)-libx32cilkrts: $(install_stamp)
+	$(call do_cilkrts,x32)
+
+$(binary_stamp)-libhfcilkrts: $(install_dependencies)
+	$(call do_cilkrts,hf)
+
+$(binary_stamp)-libsfcilkrts: $(install_dependencies)
+	$(call do_cilkrts,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libgcc.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libgcc.mk
@@ -0,0 +1,382 @@
+ifeq ($(with_libgcc),yes)
+  $(lib_binaries)	+= libgcc
+endif
+ifeq ($(with_lib64gcc),yes)
+  $(lib_binaries)	+= lib64gcc
+endif
+ifeq ($(with_lib32gcc),yes)
+  $(lib_binaries)	+= lib32gcc
+endif
+ifeq ($(with_libn32gcc),yes)
+  $(lib_binaries)	+= libn32gcc
+endif
+ifeq ($(with_libx32gcc),yes)
+  $(lib_binaries)	+= libx32gcc
+endif
+ifeq ($(with_libhfgcc),yes)
+  $(lib_binaries)	+= libhfgcc
+endif
+ifeq ($(with_libsfgcc),yes)
+  $(lib_binaries)	+= libsfgcc
+endif
+
+ifneq ($(DEB_STAGE),rtlibs)
+  ifeq ($(with_cdev),yes)
+    $(lib_binaries)  += libgcc-dev
+  endif
+  ifeq ($(with_lib64gccdev),yes)
+    $(lib_binaries)  += lib64gcc-dev
+  endif
+  ifeq ($(with_lib32gccdev),yes)
+    $(lib_binaries)  += lib32gcc-dev
+  endif
+  ifeq ($(with_libn32gccdev),yes)
+    $(lib_binaries)  += libn32gcc-dev
+  endif
+  ifeq ($(with_libx32gccdev),yes)
+    $(lib_binaries)  += libx32gcc-dev
+  endif
+  ifeq ($(with_libhfgccdev),yes)
+    $(lib_binaries)  += libhfgcc-dev
+  endif
+  ifeq ($(with_libsfgccdev),yes)
+    $(lib_binaries)  += libsfgcc-dev
+  endif
+endif
+
+header_files = \
+	$(gcc_lib_dir)/include/std*.h \
+	$(shell for h in \
+		    README features.h arm_fp16.h arm_neon.h loongson.h \
+		    {cpuid,decfloat,float,iso646,limits,mm3dnow,mm_malloc}.h \
+		    {ppu_intrinsics,paired,spu2vmx,vec_types,si2vmx}.h \
+		    {,a,b,e,i,n,p,s,t,w,x}mmintrin.h mmintrin-common.h \
+		    {abm,adx,avx,avx2,bmi,bmi2,f16c,fma,fma4,fxsr,ia32,}intrin.h \
+		    {lwp,lzcnt,popcnt,prfchw,rdseed,rtm,tbm,x86,xop,xsave{,opt},xtest,}intrin.h \
+		    {htm,htmxl,mwaitx,pku,sha,vec}intrin.h \
+		    avx512{bw,er,cd,dq,f,ifma,ifmavl,pf,vlbw,vbmi,vldq,vbmivl,vl}intrin.h \
+		    {clflushopt,clwb,clzero,pcommit,xsavec,xsaves}intrin.h \
+		    {arm_acle,unwind-arm-common,s390intrin}.h \
+		    {cross-stdarg,syslimits,unwind,varargs}.h; \
+		do \
+		  test -e $(d)/$(gcc_lib_dir)/include/$$h \
+		    && echo $(gcc_lib_dir)/include/$$h; \
+		  test -e $(d)/$(gcc_lib_dir)/include-fixed/$$h \
+		    && echo $(gcc_lib_dir)/include-fixed/$$h; \
+		done) \
+	$(shell for d in \
+		  asm bits cilk gnu linux sanitizer $(TARGET_ALIAS) \
+		  $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS)); \
+		do \
+		  test -e $(d)/$(gcc_lib_dir)/include/$$d \
+		    && echo $(gcc_lib_dir)/include/$$d; \
+		  test -e $(d)/$(gcc_lib_dir)/include-fixed/$$d \
+		    && echo $(gcc_lib_dir)/include-fixed/$$d; \
+		done)
+
+ifeq ($(with_libssp),yes)
+    header_files += $(gcc_lib_dir)/include/ssp
+endif
+ifeq ($(with_gomp),yes)
+    header_files += $(gcc_lib_dir)/include/{omp,openacc}.h
+endif
+ifeq ($(with_qmath),yes)
+    header_files += $(gcc_lib_dir)/include/quadmath{,_weak}.h
+endif
+
+ifeq ($(DEB_TARGET_ARCH),ia64)
+    header_files += $(gcc_lib_dir)/include/ia64intrin.h
+endif
+
+ifeq ($(DEB_TARGET_ARCH),m68k)
+    header_files += $(gcc_lib_dir)/include/math-68881.h
+endif
+
+ifeq ($(DEB_TARGET_ARCH),$(findstring $(DEB_TARGET_ARCH),powerpc ppc64 ppc64el powerpcspe))
+    header_files += $(gcc_lib_dir)/include/{altivec.h,ppc-asm.h,spe.h}
+endif
+
+ifeq ($(DEB_TARGET_ARCH),tilegx)
+    header_files += $(gcc_lib_dir)/include/feedback.h
+endif
+
+p_lgcc		= libgcc$(GCC_SONAME)$(cross_lib_arch)
+p_lgccdbg	= libgcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lgccdev	= libgcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lgcc		= debian/$(p_lgcc)
+d_lgccdbg	= debian/$(p_lgccdbg)
+d_lgccdev	= debian/$(p_lgccdev)
+
+p_l32gcc	= lib32gcc$(GCC_SONAME)$(cross_lib_arch)
+p_l32gccdbg	= lib32gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_l32gccdev	= lib32gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_l32gcc	= debian/$(p_l32gcc)
+d_l32gccdbg	= debian/$(p_l32gccdbg)
+d_l32gccdev	= debian/$(p_l32gccdev)
+
+p_l64gcc	= lib64gcc$(GCC_SONAME)$(cross_lib_arch)
+p_l64gccdbg	= lib64gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_l64gccdev	= lib64gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_l64gcc	= debian/$(p_l64gcc)
+d_l64gccdbg	= debian/$(p_l64gccdbg)
+d_l64gccdev	= debian/$(p_l64gccdev)
+
+p_ln32gcc	= libn32gcc$(GCC_SONAME)$(cross_lib_arch)
+p_ln32gccdbg	= libn32gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_ln32gccdev	= libn32gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_ln32gcc	= debian/$(p_ln32gcc)
+d_ln32gccdbg	= debian/$(p_ln32gccdbg)
+d_ln32gccdev	= debian/$(p_ln32gccdev)
+
+p_lx32gcc	= libx32gcc$(GCC_SONAME)$(cross_lib_arch)
+p_lx32gccdbg	= libx32gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lx32gccdev	= libx32gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lx32gcc	= debian/$(p_lx32gcc)
+d_lx32gccdbg	= debian/$(p_lx32gccdbg)
+d_lx32gccdev	= debian/$(p_lx32gccdev)
+
+p_lhfgcc	= libhfgcc$(GCC_SONAME)$(cross_lib_arch)
+p_lhfgccdbg	= libhfgcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lhfgccdev	= libhfgcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lhfgcc	= debian/$(p_lhfgcc)
+d_lhfgccdbg	= debian/$(p_lhfgccdbg)
+d_lhfgccdev	= debian/$(p_lhfgccdev)
+
+p_lsfgcc	= libsfgcc$(GCC_SONAME)$(cross_lib_arch)
+p_lsfgccdbg	= libsfgcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lsfgccdev	= libsfgcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lsfgcc	= debian/$(p_lsfgcc)
+d_lsfgccdbg	= debian/$(p_lsfgccdbg)
+d_lsfgccdev	= debian/$(p_lsfgccdev)
+
+# __do_gcc_devels(flavour,package,todir,fromdir)
+define __do_gcc_devels
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	test -n "$(2)"
+	rm -rf debian/$(2)
+	dh_installdirs -p$(2) $(docdir) #TODO
+	dh_installdirs -p$(2) $(3)
+
+	$(call __do_gcc_devels2,$(1),$(2),$(3),$(4))
+
+	debian/dh_doclink -p$(2) $(p_lbase)
+	debian/dh_rmemptydirs -p$(2)
+
+	dh_strip -p$(2)
+	$(cross_shlibdeps) dh_shlibdeps -p$(2)
+	$(call cross_mangle_substvars,$(2))
+	echo $(2) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# __do_gcc_devels2(flavour,package,todir,fromdir)
+define __do_gcc_devels2
+# stage1 builds static libgcc only
+	$(if $(filter $(DEB_STAGE),stage1),,
+		: # libgcc_s.so may be a linker script on some architectures
+		set -e; \
+		if [ -h $(4)/libgcc_s.so ]; then \
+		  rm -f $(4)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    /$(3)/libgcc_s.so; \
+		else \
+		  mv $(4)/libgcc_s.so $(d)/$(3)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    /$(3)/libgcc_s.so.$(GCC_SONAME); \
+		fi; \
+		$(if $(1), dh_link -p$(2) /$(3)/libgcc_s.so \
+		    /$(gcc_lib_dir)/libgcc_s_$(1).so;)
+	)
+	$(dh_compat2) dh_movefiles -p$(2) \
+		$(3)/{libgcc*,libgcov.a,*.o} \
+		$(if $(1),,$(header_files)) # Only move headers for the "main" package
+
+	: # libbacktrace not installed by default
+	$(if $(filter yes, $(with_backtrace)),
+	if [ -f $(buildlibdir)/$(1)/libbacktrace/.libs/libbacktrace.a ]; then \
+	  install -m644 $(buildlibdir)/$(1)/libbacktrace/.libs/libbacktrace.a \
+	      debian/$(2)/$(gcc_lib_dir)/$(1); \
+	fi; \
+	$(if $(1),,
+	if [ -f $(buildlibdir)/libbacktrace/backtrace-supported.h ]; then \
+	  install -m644 $(buildlibdir)/libbacktrace/backtrace-supported.h \
+	    debian/$(2)/$(gcc_lib_dir)/include/; \
+	  install -m644 $(srcdir)/libbacktrace/backtrace.h \
+	    debian/$(2)/$(gcc_lib_dir)/include/; \
+	fi
+	))
+
+	: # If building a flavour, add a lintian override
+	$(if $(1),
+		#TODO: use a file instead of a hacky echo
+		# bu do we want to use one override file (in the source package) per
+		# flavour or not since they are essentially the same?
+		mkdir -p debian/$(2)/usr/share/lintian/overrides
+		echo "$(2) binary: binary-from-other-architecture" \
+			>> debian/$(2)/usr/share/lintian/overrides/$(2)
+	)
+	$(if $(filter yes, $(with_lib$(1)gmath)),
+		$(call install_gcc_lib,libgcc-math,$(GCC_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_libssp)),
+		$(call install_gcc_lib,libssp,$(SSP_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_ssp)),
+		mv $(4)/libssp_nonshared.a debian/$(2)/$(3)/;
+	)
+	$(if $(filter yes, $(with_gomp)),
+		$(call install_gcc_lib,libgomp,$(GOMP_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_itm)),
+		$(call install_gcc_lib,libitm,$(ITM_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_atomic)),
+		$(call install_gcc_lib,libatomic,$(ATOMIC_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_asan)),
+		$(call install_gcc_lib,libasan,$(ASAN_SONAME),$(1),$(2))
+		mv $(4)/libasan_preinit.o debian/$(2)/$(3)/;
+	)
+	$(if $(1),,$(if $(filter yes, $(with_lsan)),
+		$(call install_gcc_lib,liblsan,$(LSAN_SONAME),$(1),$(2))
+	))
+	$(if $(1),,$(if $(filter yes, $(with_tsan)),
+		$(call install_gcc_lib,libtsan,$(TSAN_SONAME),$(1),$(2))
+	))
+	$(if $(filter yes, $(with_ubsan)),
+		$(call install_gcc_lib,libubsan,$(UBSAN_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_vtv)),
+		$(call install_gcc_lib,libvtv,$(VTV_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_cilkrts)),
+		$(call install_gcc_lib,libcilkrts,$(CILKRTS_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_mpx)),
+	    $(if $(filter x32, $(1)),,
+		$(call install_gcc_lib,libmpxwrappers,$(MPX_SONAME),$(1),$(2))
+		$(call install_gcc_lib,libmpx,$(MPX_SONAME),$(1),$(2))
+	    )
+	)
+	$(if $(filter yes, $(with_qmath)),
+		$(call install_gcc_lib,libquadmath,$(QUADMATH_SONAME),$(1),$(2))
+	)
+endef
+
+# do_gcc_devels(flavour)
+define do_gcc_devels
+	$(call __do_gcc_devels,$(1),$(p_l$(1)gccdev),$(gcc_lib_dir$(1)),$(d)/$(usr_lib$(1)))
+endef
+
+
+define __do_libgcc
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+
+	dh_installdirs -p$(p_l) \
+		$(docdir)/$(p_l) \
+		$(libgcc_dir$(2))
+
+	$(if $(filter yes,$(with_shared_libgcc)),
+		mv $(d)/$(usr_lib$(2))/libgcc_s.so.$(GCC_SONAME) \
+			$(d_l)/$(libgcc_dir$(2))/.
+	)
+
+	debian/dh_doclink -p$(p_l) $(if $(3),$(3),$(p_lbase))
+	debian/dh_doclink -p$(p_d) $(if $(3),$(3),$(p_lbase))
+	debian/dh_rmemptydirs -p$(p_l)
+	debian/dh_rmemptydirs -p$(p_d)
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+
+	# see Debian #533843 for the __aeabi symbol handling; this construct is
+	# just to include the symbols for dpkg versions older than 1.15.3 which
+	# didn't allow bypassing the symbol blacklist
+	$(if $(filter yes,$(with_shared_libgcc)),
+		$(if $(findstring gcc1,$(p_l)), \
+		ln -sf libgcc.symbols debian/$(p_l).symbols \
+		)
+		$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) -p$(p_d) \
+			-- -v$(DEB_LIBGCC_VERSION) -a$(call mlib_to_arch,$(2)) || echo XXXXXXXXXXXXXX ERROR $(p_l)
+		$(call cross_mangle_shlibs,$(p_l))
+		$(if $(filter arm-linux-gnueabi%,$(DEB_TARGET_GNU_TYPE)),
+			if head -1 $(d_l)/DEBIAN/symbols 2>/dev/null | grep -q '^lib'; then \
+			  grep -q '^ __aeabi' $(d_l)/DEBIAN/symbols \
+			    || cat debian/libgcc.symbols.aeabi \
+				>> $(d_l)/DEBIAN/symbols; \
+			fi
+		)
+	)
+
+	$(if $(DEB_STAGE),,
+	    $(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	)
+	$(call cross_mangle_substvars,$(p_l))
+
+	$(if $(2),,	# only for native
+		mkdir -p $(d_l)/usr/share/lintian/overrides
+		echo '$(p_l): package-name-doesnt-match-sonames' \
+			> $(d_l)/usr/share/lintian/overrides/$(p_l)
+	)
+
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries).epoch
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_libgcc = $(call __do_libgcc,lib$(1)gcc$(GCC_SONAME),$(1),$(2))
+# ----------------------------------------------------------------------
+
+$(binary_stamp)-libgcc: $(install_dependencies)
+ifeq ($(with_standalone_gcj),yes)
+	$(call do_libgcc,,$(p_jbase))
+else
+	$(call do_libgcc,,)
+endif
+
+$(binary_stamp)-lib64gcc: $(install_dependencies)
+	$(call do_libgcc,64,)
+
+$(binary_stamp)-lib32gcc: $(install_dependencies)
+	$(call do_libgcc,32,)
+
+$(binary_stamp)-libn32gcc: $(install_dependencies)
+	$(call do_libgcc,n32,)
+
+$(binary_stamp)-libx32gcc: $(install_dependencies)
+	$(call do_libgcc,x32,)
+
+$(binary_stamp)-libhfgcc: $(install_dependencies)
+	$(call do_libgcc,hf)
+
+$(binary_stamp)-libsfgcc: $(install_dependencies)
+	$(call do_libgcc,sf)
+
+$(binary_stamp)-libgcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,)
+
+$(binary_stamp)-lib64gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,64)
+
+$(binary_stamp)-lib32gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,32)
+
+$(binary_stamp)-libn32gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,n32)
+
+$(binary_stamp)-libx32gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,x32)
+
+$(binary_stamp)-libhfgcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,hf)
+
+$(binary_stamp)-libsfgcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,sf)
+
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libgccjit.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libgccjit.mk
@@ -0,0 +1,89 @@
+ifeq ($(with_libgccjit),yes)
+  $(lib_binaries)  += libgccjit
+endif
+
+$(lib_binaries)  += libgccjitdev
+
+ifneq ($(DEB_CROSS),yes)
+  indep_binaries := $(indep_binaries) libgccjitdoc
+endif
+
+p_jitlib	= libgccjit$(GCCJIT_SONAME)
+p_jitdbg	= libgccjit$(GCCJIT_SONAME)-dbg
+p_jitdev	= libgccjit$(pkg_ver)-dev
+p_jitdoc	= libgccjit$(pkg_ver)-doc
+
+d_jitlib	= debian/$(p_jitlib)
+d_jitdev	= debian/$(p_jitdev)
+d_jitdbg	= debian/$(p_jitdbg)
+d_jitdoc	= debian/$(p_jitdoc)
+
+$(binary_stamp)-libgccjit: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitlib) $(d_jitdbg)
+	dh_installdirs -p$(p_jitlib) \
+		$(usr_lib)
+	dh_installdirs -p$(p_jitdbg)
+
+	$(dh_compat2) dh_movefiles -p$(p_jitlib) \
+		$(usr_lib)/libgccjit.so.*
+	rm -f $(d)/$(usr_lib)/libgccjit.so
+
+	debian/dh_doclink -p$(p_jitlib) $(p_base)
+	debian/dh_doclink -p$(p_jitdbg) $(p_base)
+
+	dh_strip -p$(p_jitlib) --dbg-package=$(p_jitdbg)
+	$(cross_makeshlibs) dh_makeshlibs -p$(p_jitlib)
+	$(call cross_mangle_shlibs,$(p_jitlib))
+	$(ignshld)$(cross_shlibdeps) dh_shlibdeps -p$(p_jitlib) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_jitlib))
+	echo $(p_jitlib) $(p_jitdbg) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
+
+$(binary_stamp)-libgccjitdev: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitdev)
+	dh_installdirs -p$(p_jitdev) \
+		$(usr_lib) \
+		$(gcc_lib_dir)/include
+
+	rm -f $(d)/$(usr_lib)/libgccjit.so
+
+	$(dh_compat2) dh_movefiles -p$(p_jitdev) \
+		$(gcc_lib_dir)/include/libgccjit*.h
+	dh_link -p$(p_jitdev) \
+		$(usr_lib)/libgccjit.so.$(GCCJIT_SONAME) $(gcc_lib_dir)/libgccjit.so
+
+	debian/dh_doclink -p$(p_jitdev) $(p_base)
+
+	echo $(p_jitdev) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
+
+$(binary_stamp)-libgccjitdoc: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitdoc)
+	dh_installdirs -p$(p_jitdoc) \
+		$(PF)/share/info
+
+	$(dh_compat2) dh_movefiles -p$(p_jitdoc) \
+		$(PF)/share/info/libgccjit*
+
+	debian/dh_doclink -p$(p_jitdoc) $(p_base)
+	echo $(p_jitdoc) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libgomp.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libgomp.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libgomp
+ifeq ($(with_lib64gomp),yes)
+  $(lib_binaries)  += lib64gomp
+endif
+ifeq ($(with_lib32gomp),yes)
+  $(lib_binaries)	+= lib32gomp
+endif
+ifeq ($(with_libn32gomp),yes)
+  $(lib_binaries)	+= libn32gomp
+endif
+ifeq ($(with_libx32gomp),yes)
+  $(lib_binaries)	+= libx32gomp
+endif
+ifeq ($(with_libhfgomp),yes)
+  $(lib_binaries)	+= libhfgomp
+endif
+ifeq ($(with_libsfgomp),yes)
+  $(lib_binaries)	+= libsfgomp
+endif
+
+define __do_gomp
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libgomp.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libgomp.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst gomp$(GOMP_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_gomp = $(call __do_gomp,lib$(1)gomp$(GOMP_SONAME),$(1))
+
+$(binary_stamp)-libgomp: $(install_stamp)
+	$(call do_gomp,)
+
+$(binary_stamp)-lib64gomp: $(install_stamp)
+	$(call do_gomp,64)
+
+$(binary_stamp)-lib32gomp: $(install_stamp)
+	$(call do_gomp,32)
+
+$(binary_stamp)-libn32gomp: $(install_stamp)
+	$(call do_gomp,n32)
+
+$(binary_stamp)-libx32gomp: $(install_stamp)
+	$(call do_gomp,x32)
+
+$(binary_stamp)-libhfgomp: $(install_dependencies)
+	$(call do_gomp,hf)
+
+$(binary_stamp)-libsfgomp: $(install_dependencies)
+	$(call do_gomp,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libitm.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libitm.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libitm
+ifeq ($(with_lib64itm),yes)
+  $(lib_binaries)  += lib64itm
+endif
+ifeq ($(with_lib32itm),yes)
+  $(lib_binaries)	+= lib32itm
+endif
+ifeq ($(with_libn32itm),yes)
+  $(lib_binaries)	+= libn32itm
+endif
+ifeq ($(with_libx32itm),yes)
+  $(lib_binaries)	+= libx32itm
+endif
+ifeq ($(with_libhfitm),yes)
+  $(lib_binaries)	+= libhfitm
+endif
+ifeq ($(with_libsfitm),yes)
+  $(lib_binaries)	+= libsfitm
+endif
+
+define __do_itm
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libitm.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libitm.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_itm = $(call __do_itm,lib$(1)itm$(ITM_SONAME),$(1))
+
+$(binary_stamp)-libitm: $(install_stamp)
+	$(call do_itm,)
+
+$(binary_stamp)-lib64itm: $(install_stamp)
+	$(call do_itm,64)
+
+$(binary_stamp)-lib32itm: $(install_stamp)
+	$(call do_itm,32)
+
+$(binary_stamp)-libn32itm: $(install_stamp)
+	$(call do_itm,n32)
+
+$(binary_stamp)-libx32itm: $(install_stamp)
+	$(call do_itm,x32)
+
+$(binary_stamp)-libhfitm: $(install_dependencies)
+	$(call do_itm,hf)
+
+$(binary_stamp)-libsfitm: $(install_dependencies)
+	$(call do_itm,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-liblsan.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-liblsan.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += liblsan
+ifeq ($(with_lib64lsan),yes)
+  $(lib_binaries)  += lib64lsan
+endif
+ifeq ($(with_lib32lsan),yes)
+  $(lib_binaries)	+= lib32lsan
+endif
+ifeq ($(with_libn32lsan),yes)
+  $(lib_binaries)	+= libn32lsan
+endif
+ifeq ($(with_libx32lsan),yes)
+  $(lib_binaries)	+= libx32lsan
+endif
+ifeq ($(with_libhflsan),yes)
+  $(lib_binaries)	+= libhflsan
+endif
+ifeq ($(with_libsflsan),yes)
+  $(lib_binaries)	+= libsflsan
+endif
+
+define __do_lsan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/liblsan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst lsan$(LSAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst lsan$(LSAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_lsan = $(call __do_lsan,lib$(1)lsan$(LSAN_SONAME),$(1))
+
+$(binary_stamp)-liblsan: $(install_stamp)
+	$(call do_lsan,)
+
+$(binary_stamp)-lib64lsan: $(install_stamp)
+	$(call do_lsan,64)
+
+$(binary_stamp)-lib32lsan: $(install_stamp)
+	$(call do_lsan,32)
+
+$(binary_stamp)-libn32lsan: $(install_stamp)
+	$(call do_lsan,n32)
+
+$(binary_stamp)-libx32lsan: $(install_stamp)
+	$(call do_lsan,x32)
+
+$(binary_stamp)-libhflsan: $(install_dependencies)
+	$(call do_lsan,hf)
+
+$(binary_stamp)-libsflsan: $(install_dependencies)
+	$(call do_lsan,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libmpx.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libmpx.mk
@@ -0,0 +1,74 @@
+$(lib_binaries)  += libmpx
+ifeq ($(with_lib64mpx),yes)
+  $(lib_binaries)  += lib64mpx
+endif
+ifeq ($(with_lib32mpx),yes)
+  $(lib_binaries)	+= lib32mpx
+endif
+ifeq ($(with_libn32mpx),yes)
+  $(lib_binaries)	+= libn32mpx
+endif
+ifeq ($(with_libx32mpx),yes)
+  $(lib_binaries)	+= libx32mpx
+endif
+ifeq ($(with_libhfmpx),yes)
+  $(lib_binaries)	+= libhfmpx
+endif
+ifeq ($(with_libsfmpx),yes)
+  $(lib_binaries)	+= libsfmpx
+endif
+
+define __do_mpx
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(usr_lib$(2))/libmpx.so.* \
+		$(usr_lib$(2))/libmpxwrappers.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libmpx.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l)
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_mpx = $(call __do_mpx,lib$(1)mpx$(MPX_SONAME),$(1))
+
+$(binary_stamp)-libmpx: $(install_stamp)
+	$(call do_mpx,)
+
+$(binary_stamp)-lib64mpx: $(install_stamp)
+	$(call do_mpx,64)
+
+$(binary_stamp)-lib32mpx: $(install_stamp)
+	$(call do_mpx,32)
+
+$(binary_stamp)-libn32mpx: $(install_stamp)
+	$(call do_mpx,n32)
+
+$(binary_stamp)-libx32mpx: $(install_stamp)
+	$(call do_mpx,x32)
+
+$(binary_stamp)-libhfmpx: $(install_dependencies)
+	$(call do_mpx,hf)
+
+$(binary_stamp)-libsfmpx: $(install_dependencies)
+	$(call do_mpx,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libobjc.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libobjc.mk
@@ -0,0 +1,159 @@
+ifeq ($(with_libobjc),yes)
+  $(lib_binaries) += libobjc
+endif
+ifeq ($(with_objcdev),yes)
+  $(lib_binaries) += libobjc-dev
+endif
+ifeq ($(with_lib64objc),yes)
+  $(lib_binaries)	+= lib64objc
+endif
+ifeq ($(with_lib64objcdev),yes)
+  $(lib_binaries)	+= lib64objc-dev
+endif
+ifeq ($(with_lib32objc),yes)
+  $(lib_binaries)	+= lib32objc
+endif
+ifeq ($(with_lib32objcdev),yes)
+  $(lib_binaries)	+= lib32objc-dev
+endif
+ifeq ($(with_libn32objc),yes)
+  $(lib_binaries)	+= libn32objc
+endif
+ifeq ($(with_libn32objcdev),yes)
+  $(lib_binaries)	+= libn32objc-dev
+endif
+ifeq ($(with_libx32objc),yes)
+  $(lib_binaries)	+= libx32objc
+endif
+ifeq ($(with_libx32objcdev),yes)
+  $(lib_binaries)	+= libx32objc-dev
+endif
+ifeq ($(with_libhfobjc),yes)
+  $(lib_binaries)	+= libhfobjc
+endif
+ifeq ($(with_libhfobjcdev),yes)
+  $(lib_binaries)	+= libhfobjc-dev
+endif
+ifeq ($(with_libsfobjc),yes)
+  $(lib_binaries)	+= libsfobjc
+endif
+ifeq ($(with_libsfobjcdev),yes)
+  $(lib_binaries)	+= libsfobjc-dev
+endif
+
+files_lobjcdev= \
+	$(gcc_lib_dir)/include/objc
+
+files_lobjc = \
+	$(usr_lib$(2))/libobjc.so.*
+ifeq ($(with_objc_gc),yes)
+  files_lobjc += \
+	$(usr_lib$(2))/libobjc_gc.so.*
+endif
+
+define __do_libobjc
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) \
+		$(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(files_lobjc)
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(if $(2),
+	  ln -sf libobjc.symbols debian/$(p_l).symbols ,
+	  fgrep -v libobjc.symbols.gc debian/libobjc.symbols > debian/$(p_l).symbols
+	)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+		-- -a$(call mlib_to_arch,$(2)) || echo XXXXXXXXXXXXXX ERROR $(p_l)
+	rm -f debian/$(p_l).symbols
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst objc$(OBJC_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+
+define __do_libobjc_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(p_l) \
+		$(gcc_lib_dir$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(files_lobjcdev)
+
+	$(call install_gcc_lib,libobjc,$(OBJC_SONAME),$(2),$(p_l))
+	$(if $(filter yes,$(with_objc_gc)),
+		dh_link -p$(p_l) \
+		  /$(usr_lib$(2))/libobjc_gc.so.$(OBJC_SONAME) \
+		  /$(gcc_lib_dir$(2))/libobjc_gc.so
+	)
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+
+
+# ----------------------------------------------------------------------
+
+do_libobjc = $(call __do_libobjc,lib$(1)objc$(OBJC_SONAME),$(1))
+do_libobjc_dev = $(call __do_libobjc_dev,lib$(1)objc-$(BASE_VERSION)-dev,$(1))
+
+$(binary_stamp)-libobjc: $(install_stamp)
+	$(call do_libobjc,)
+
+$(binary_stamp)-lib64objc: $(install_stamp)
+	$(call do_libobjc,64)
+
+$(binary_stamp)-lib32objc: $(install_stamp)
+	$(call do_libobjc,32)
+
+$(binary_stamp)-libn32objc: $(install_stamp)
+	$(call do_libobjc,n32)
+
+$(binary_stamp)-libx32objc: $(install_stamp)
+	$(call do_libobjc,x32)
+
+$(binary_stamp)-libhfobjc: $(install_stamp)
+	$(call do_libobjc,hf)
+
+$(binary_stamp)-libsfobjc: $(install_stamp)
+	$(call do_libobjc,sf)
+
+
+$(binary_stamp)-libobjc-dev: $(install_stamp)
+	$(call do_libobjc_dev,)
+
+$(binary_stamp)-lib64objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,64)
+
+$(binary_stamp)-lib32objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,32)
+
+$(binary_stamp)-libx32objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,x32)
+
+$(binary_stamp)-libn32objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,n32)
+
+$(binary_stamp)-libhfobjc-dev: $(install_stamp)
+	$(call do_libobjc_dev,hf)
+
+$(binary_stamp)-libsfobjc-dev: $(install_stamp)
+	$(call do_libobjc_dev,sf)
+
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libquadmath.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libquadmath.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libqmath
+ifeq ($(with_lib64qmath),yes)
+  $(lib_binaries)  += lib64qmath
+endif
+ifeq ($(with_lib32qmath),yes)
+  $(lib_binaries)	+= lib32qmath
+endif
+ifeq ($(with_libn32qmath),yes)
+  $(lib_binaries)	+= libn32qmath
+endif
+ifeq ($(with_libx32qmath),yes)
+  $(lib_binaries)	+= libx32qmath
+endif
+ifeq ($(with_libhfqmath),yes)
+  $(lib_binaries)	+= libhfqmath
+endif
+ifeq ($(with_libsfqmath),yes)
+  $(lib_binaries)	+= libsfqmath
+endif
+
+define __do_qmath
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libquadmath.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libquadmath.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_qmath = $(call __do_qmath,lib$(1)quadmath$(QUADMATH_SONAME),$(1))
+
+$(binary_stamp)-libqmath: $(install_stamp)
+	$(call do_qmath,)
+
+$(binary_stamp)-lib64qmath: $(install_stamp)
+	$(call do_qmath,64)
+
+$(binary_stamp)-lib32qmath: $(install_stamp)
+	$(call do_qmath,32)
+
+$(binary_stamp)-libn32qmath: $(install_stamp)
+	$(call do_qmath,n32)
+
+$(binary_stamp)-libx32qmath: $(install_stamp)
+	$(call do_qmath,x32)
+
+$(binary_stamp)-libhfqmath: $(install_stamp)
+	$(call do_qmath,hf)
+
+$(binary_stamp)-libsfqmath: $(install_stamp)
+	$(call do_qmath,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libssp.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libssp.mk
@@ -0,0 +1,155 @@
+arch_binaries  := $(arch_binaries) libssp
+ifeq ($(with_lib64ssp),yes)
+  arch_binaries  := $(arch_binaries) lib64ssp
+endif
+ifeq ($(with_lib32ssp),yes)
+  arch_binaries	:= $(arch_binaries) lib32ssp
+endif
+ifeq ($(with_libn32ssp),yes)
+  arch_binaries	:= $(arch_binaries) libn32ssp
+endif
+ifeq ($(with_libx32ssp),yes)
+  arch_binaries := $(arch_binaries) libx32ssp
+endif
+
+p_ssp	= libssp$(SSP_SONAME)
+p_ssp32	= lib32ssp$(SSP_SONAME)
+p_ssp64	= lib64ssp$(SSP_SONAME)
+p_sspx32 = libx32ssp$(SSP_SONAME)
+p_sspd	= libssp$(SSP_SONAME)-dev
+
+d_ssp	= debian/$(p_ssp)
+d_ssp32	= debian/$(p_ssp32)
+d_ssp64	= debian/$(p_ssp64)
+d_sspx32 = debian/$(p_sspx32)
+d_sspd	= debian/$(p_sspd)
+
+dirs_ssp = \
+	$(docdir)/$(p_base) \
+	$(PF)/$(libdir)
+files_ssp = \
+	$(PF)/$(libdir)/libssp.so.*
+
+dirs_sspd = \
+	$(docdir) \
+	$(PF)/include \
+	$(PF)/$(libdir)
+files_sspd = \
+	$(gcc_lib_dir)/include/ssp \
+	$(PF)/$(libdir)/libssp.{a,so} \
+	$(PF)/$(libdir)/libssp_nonshared.a
+
+ifeq ($(with_lib32ssp),yes)
+	dirs_sspd  += $(lib32)
+	files_sspd += $(lib32)/libssp.{a,so}
+	files_sspd += $(lib32)/libssp_nonshared.a
+endif
+ifeq ($(with_lib64ssp),yes)
+	dirs_sspd  += $(PF)/lib64
+	files_sspd += $(PF)/lib64/libssp.{a,so}
+	files_sspd += $(PF)/lib64/libssp_nonshared.a
+endif
+
+$(binary_stamp)-libssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_ssp)
+	dh_installdirs -p$(p_ssp)
+
+	$(dh_compat2) dh_movefiles -p$(p_ssp) $(files_ssp)
+	debian/dh_doclink -p$(p_ssp) $(p_lbase)
+
+	debian/dh_rmemptydirs -p$(p_ssp)
+
+	dh_strip -p$(p_ssp)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_ssp) -V '$(p_ssp) (>= $(DEB_SOVERSION))'
+	dh_shlibdeps -p$(p_ssp)
+	echo $(p_ssp) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-lib64ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_ssp64)
+	dh_installdirs -p$(p_ssp64) \
+		$(PF)/lib64
+	$(dh_compat2) dh_movefiles -p$(p_ssp64) \
+		$(PF)/lib64/libssp.so.*
+
+	debian/dh_doclink -p$(p_ssp64) $(p_lbase)
+
+	dh_strip -p$(p_ssp64)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_ssp64) -V '$(p_ssp64) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_ssp64)
+	echo $(p_ssp64) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-lib32ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_ssp32)
+	dh_installdirs -p$(p_ssp32) \
+		$(lib32)
+	$(dh_compat2) dh_movefiles -p$(p_ssp32) \
+		$(lib32)/libssp.so.*
+
+	debian/dh_doclink -p$(p_ssp32) $(p_lbase)
+
+	dh_strip -p$(p_ssp32)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_ssp32) -V '$(p_ssp32) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_ssp32)
+	echo $(p_ssp32) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libn32ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_sspn32)
+	dh_installdirs -p$(p_sspn32) \
+		$(PF)/$(libn32)
+	$(dh_compat2) dh_movefiles -p$(p_sspn32) \
+		$(PF)/$(libn32)/libssp.so.*
+
+	debian/dh_doclink -p$(p_sspn32) $(p_lbase)
+
+	dh_strip -p$(p_sspn32)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_sspn32) -V '$(p_sspn32) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_sspn32)
+	echo $(p_sspn32) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libx32ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_sspx32)
+	dh_installdirs -p$(p_sspx32) \
+		$(PF)/$(libx32)
+	$(dh_compat2) dh_movefiles -p$(p_sspx32) \
+		$(PF)/$(libx32)/libssp.so.*
+
+	debian/dh_doclink -p$(p_sspx32) $(p_lbase)
+
+	dh_strip -p$(p_sspx32)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_sspx32) -V '$(p_sspx32) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_sspx32)
+	echo $(p_sspx32) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libstdcxx.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libstdcxx.mk
@@ -0,0 +1,527 @@
+ifeq ($(with_libcxx),yes)
+  $(lib_binaries)  += libstdcxx
+endif
+ifeq ($(with_lib64cxx),yes)
+  $(lib_binaries)  += lib64stdcxx
+endif
+ifeq ($(with_lib32cxx),yes)
+  $(lib_binaries)	+= lib32stdcxx
+endif
+ifeq ($(with_libn32cxx),yes)
+  $(lib_binaries)	+= libn32stdcxx
+endif
+ifeq ($(with_libx32cxx),yes)
+  $(lib_binaries)	+= libx32stdcxx
+endif
+ifeq ($(with_libhfcxx),yes)
+  $(lib_binaries)	+= libhfstdcxx
+endif
+ifeq ($(with_libsfcxx),yes)
+  $(lib_binaries)	+= libsfstdcxx
+endif
+
+ifneq ($(DEB_STAGE),rtlibs)
+  ifeq ($(with_lib64cxxdev),yes)
+    $(lib_binaries)	+= lib64stdcxx-dev
+  endif
+  ifeq ($(with_lib64cxxdbg),yes)
+    $(lib_binaries)	+= lib64stdcxxdbg
+  endif
+  ifeq ($(with_lib32cxxdev),yes)
+    $(lib_binaries)	+= lib32stdcxx-dev
+  endif
+  ifeq ($(with_lib32cxxdbg),yes)
+    $(lib_binaries)	+= lib32stdcxxdbg
+  endif
+  ifeq ($(with_libn32cxxdev),yes)
+    $(lib_binaries)	+= libn32stdcxx-dev
+  endif
+  ifeq ($(with_libn32cxxdbg),yes)
+    $(lib_binaries)	+= libn32stdcxxdbg
+  endif
+  ifeq ($(with_libx32cxxdev),yes)
+    $(lib_binaries)	+= libx32stdcxx-dev
+  endif
+  ifeq ($(with_libx32cxxdbg),yes)
+    $(lib_binaries)	+= libx32stdcxxdbg
+  endif
+  ifeq ($(with_libhfcxxdev),yes)
+    $(lib_binaries)	+= libhfstdcxx-dev
+  endif
+  ifeq ($(with_libhfcxxdbg),yes)
+    $(lib_binaries)	+= libhfstdcxxdbg
+  endif
+  ifeq ($(with_libsfcxxdev),yes)
+    $(lib_binaries)	+= libsfstdcxx-dev
+  endif
+  ifeq ($(with_libsfcxxdbg),yes)
+    $(lib_binaries)	+= libsfstdcxxdbg
+  endif
+
+  ifeq ($(with_cxxdev),yes)
+    $(lib_binaries)  += libstdcxx-dev
+    ifneq ($(DEB_CROSS),yes)
+      indep_binaries := $(indep_binaries) libstdcxx-doc
+    endif
+  endif
+endif
+
+libstdc_ext = -$(BASE_VERSION)
+
+p_lib	= libstdc++$(CXX_SONAME)$(cross_lib_arch)
+p_lib64	= lib64stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_lib32	= lib32stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libn32= libn32stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libx32= libx32stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libhf	= libhfstdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libsf	= libsfstdc++$(CXX_SONAME)$(cross_lib_arch)
+p_dev	= libstdc++$(libstdc_ext)-dev$(cross_lib_arch)
+p_pic	= libstdc++$(libstdc_ext)-pic$(cross_lib_arch)
+p_dbg	= libstdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbg64	= lib64stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbg32	= lib32stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbgn32= libn32stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbgx32= libx32stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbghf	= libhfstdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbgsf	= libsfstdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_libd	= libstdc++$(libstdc_ext)-doc
+
+d_lib	= debian/$(p_lib)
+d_lib64	= debian/$(p_lib64)
+d_lib32	= debian/$(p_lib32)
+d_libn32= debian/$(p_libn32)
+d_libx32= debian/$(p_libx32)
+d_libhf	= debian/$(p_libhf)
+d_libsf	= debian/$(p_libsf)
+d_dev	= debian/$(p_dev)
+d_pic	= debian/$(p_pic)
+d_dbg	= debian/$(p_dbg)
+d_dbg64	= debian/$(p_dbg64)
+d_dbg32	= debian/$(p_dbg32)
+d_dbghf	= debian/$(p_dbghf)
+d_dbgsf	= debian/$(p_dbgsf)
+d_libd	= debian/$(p_libd)
+
+dirs_dev = \
+	$(docdir)/$(p_base)/C++ \
+	$(usr_lib) \
+	$(gcc_lib_dir)/include \
+	$(PFL)/include/c++
+
+files_dev = \
+	$(PFL)/include/c++/$(BASE_VERSION) \
+	$(gcc_lib_dir)/libstdc++.{a,so} \
+	$(gcc_lib_dir)/libsupc++.a \
+	$(gcc_lib_dir)/libstdc++fs.a
+
+ifeq ($(with_multiarch_cxxheaders),yes)
+  dirs_dev += \
+	$(PF)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION)
+  files_dev += \
+	$(PF)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION)/{bits,ext}
+endif
+
+dirs_dbg = \
+	$(docdir) \
+	$(PF)/lib/debug/$(usr_lib) \
+	$(usr_lib)/debug \
+	$(PF)/share/gdb/auto-load/$(usr_lib)/debug \
+	$(gcc_lib_dir)
+files_dbg = \
+	$(usr_lib)/debug/libstdc++.{a,so*} \
+	$(usr_lib)/debug/libstdc++fs.a
+
+dirs_pic = \
+	$(docdir) \
+	$(gcc_lib_dir)
+files_pic = \
+	$(gcc_lib_dir)/libstdc++_pic.a
+
+# ----------------------------------------------------------------------
+
+gxx_baseline_dir = $(shell \
+			sed -n '/^baseline_dir *=/s,.*= *\(.*\)$$,\1,p' \
+			    $(buildlibdir)/libstdc++-v3/testsuite/Makefile)
+gxx_baseline_file = $(gxx_baseline_dir)/baseline_symbols.txt
+
+debian/README.libstdc++-baseline:
+	cat debian/README.libstdc++-baseline.in \
+		> debian/README.libstdc++-baseline
+
+	baseline_name=`basename $(gxx_baseline_dir)`; \
+	baseline_parentdir=`dirname $(gxx_baseline_dir)`; \
+	compat_baseline_name=""; \
+	if [ -f "$(gxx_baseline_file)" ]; then \
+	  ( \
+	    echo "A baseline file for $$baseline_name was found."; \
+	    echo "Running the check-abi script ..."; \
+	    echo ""; \
+	    $(MAKE) -C $(buildlibdir)/libstdc++-v3/testsuite \
+		check-abi; \
+	  ) >> debian/README.libstdc++-baseline; \
+	else \
+	  ( \
+	    echo "No baseline file found for $$baseline_name."; \
+	    echo "Generating a new baseline file ..."; \
+	    echo ""; \
+	  ) >> debian/README.libstdc++-baseline; \
+	  mkdir -p $(gxx_baseline_dir); \
+	  $(MAKE) -C $(buildlibdir)/libstdc++-v3/testsuite new-abi-baseline; \
+	  if [ -f $(gxx_baseline_file) ]; then \
+	    cat $(gxx_baseline_file); \
+	  else \
+	    cat $$(find $(buildlibdir)/libstdc++-v3 $(srcdir)/libstdc++-v3 -name '.new') || true; \
+	  fi >> debian/README.libstdc++-baseline; \
+	fi
+
+# ----------------------------------------------------------------------
+# FIXME: see #792204, libstdc++ symbols on sparc64, for now ignore errors
+# for the 32bit multilib build
+
+define __do_libstdcxx
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+
+	dh_installdirs -p$(p_l) \
+		$(docdir) \
+		$(usr_lib$(2)) \
+		$(PF)/share/gdb/auto-load/$(usr_lib$(2))
+
+	$(if $(DEB_CROSS),,$(if $(2),,
+	dh_installdirs -p$(p_l) \
+		$(PF)/share/gcc-$(BASE_VERSION)/python
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(PF)/share/gcc-$(BASE_VERSION)/python/libstdcxx
+	))
+	cp -p $(d)/$(usr_lib$(2))/libstdc++.so.*.py \
+		$(d_l)/$(PF)/share/gdb/auto-load/$(usr_lib$(2))/.
+	sed -i -e "/^libdir *=/s,=.*,= '/$(usr_lib$(2))'," \
+		$(d_l)/$(PF)/share/gdb/auto-load/$(usr_lib$(2))/libstdc++.so.*.py
+
+	cp -a $(d)/$(usr_lib$(2))/libstdc++.so.*[0-9] \
+		$(d_l)/$(usr_lib$(2))/.
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_l)
+
+	dh_strip -p$(p_l) $(if $(filter rtlibs,$(DEB_STAGE)),,--dbg-package=$(1)-$(BASE_VERSION)-dbg$(cross_lib_arch))
+
+	$(if $(filter $(DEB_TARGET_ARCH), armel hppa sparc64), \
+	  -$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+	  @echo "FIXME: libstdc++ not feature complete (https://gcc.gnu.org/ml/gcc/2014-07/msg00000.html)", \
+	  $(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+	)
+
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst stdc++$(CXX_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+define __do_libstdcxx_dbg
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_d)
+	dh_installdirs -p$(p_d) \
+		$(PF)/lib/debug/$(usr_lib$(2)) \
+		$(usr_lib$(2))
+
+	$(if $(filter yes,$(with_lib$(2)cxx)),
+		cp -a $(d)/$(usr_lib$(2))/libstdc++.so.*[0-9] \
+			$(d_d)/$(usr_lib$(2))/.;
+		dh_strip -p$(p_d) --keep-debug;
+		$(if $(filter yes,$(with_common_libs)),, # if !with_common_libs
+			# remove the debug symbols for libstdc++
+			# built by a newer version of GCC
+			rm -rf $(d_d)/usr/lib/debug/$(PF);
+		)
+		rm -f $(d_d)/$(usr_lib$(2))/libstdc++.so.*[0-9]
+	)
+
+	$(if $(filter yes,$(with_cxx_debug)),
+		mkdir -p $(d_d)/$(usr_lib$(2))/debug;
+		mv $(d)/$(usr_lib$(2))/debug/libstdc++* $(d_d)/$(usr_lib$(2))/debug;
+		rm -f $(d_d)/$(usr_lib$(2))/debug/libstdc++_pic.a
+	)
+
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_d) \
+		$(call shlibdirs_to_search,$(subst $(pkg_ver),,$(subst stdc++$(CXX_SONAME),gcc$(GCC_SONAME),$(p_l))),$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_d))
+
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_d)
+	echo $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+define __do_libstdcxx_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	mv $(d)/$(usr_lib$(2))/libstdc++.a $(d)/$(usr_lib$(2))/libstdc++fs.a $(d)/$(usr_lib$(2))/libsupc++.a \
+		$(d)/$(gcc_lib_dir$(2))/
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(p_l) $(gcc_lib_dir$(2))
+
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(gcc_lib_dir$(2))/libstdc++.a \
+		$(gcc_lib_dir$(2))/libstdc++fs.a \
+		$(gcc_lib_dir$(2))/libsupc++.a \
+		$(if $(with_multiarch_cxxheaders),$(PF)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION)/$(2))
+	$(call install_gcc_lib,libstdc++,$(CXX_SONAME),$(2),$(p_l))
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_l)
+	dh_strip -p$(p_l)
+	dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst stdc++$(CXX_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_libstdcxx = $(call __do_libstdcxx,lib$(1)stdc++$(CXX_SONAME),$(1))
+do_libstdcxx_dbg = $(call __do_libstdcxx_dbg,lib$(1)stdc++$(CXX_SONAME)$(libstdc_ext),$(1))
+do_libstdcxx_dev = $(call __do_libstdcxx_dev,lib$(1)stdc++-$(BASE_VERSION)-dev,$(1))
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libstdcxx: $(install_stamp)
+	$(call do_libstdcxx,)
+
+$(binary_stamp)-lib64stdcxx: $(install_stamp)
+	$(call do_libstdcxx,64)
+
+$(binary_stamp)-lib32stdcxx: $(install_stamp)
+	$(call do_libstdcxx,32)
+
+$(binary_stamp)-libn32stdcxx: $(install_stamp)
+	$(call do_libstdcxx,n32)
+
+$(binary_stamp)-libx32stdcxx: $(install_stamp)
+	$(call do_libstdcxx,x32)
+
+$(binary_stamp)-libhfstdcxx: $(install_stamp)
+	$(call do_libstdcxx,hf)
+
+$(binary_stamp)-libsfstdcxx: $(install_stamp)
+	$(call do_libstdcxx,sf)
+
+$(binary_stamp)-lib64stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,64)
+
+$(binary_stamp)-lib32stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,32)
+
+$(binary_stamp)-libn32stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,n32)
+
+$(binary_stamp)-libx32stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,x32)
+
+$(binary_stamp)-libhfstdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,hf)
+
+$(binary_stamp)-libsfstdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,sf)
+
+$(binary_stamp)-lib64stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,64)
+
+$(binary_stamp)-lib32stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,32)
+
+$(binary_stamp)-libn32stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,n32)
+
+$(binary_stamp)-libx32stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,x32)
+
+$(binary_stamp)-libhfstdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,hf)
+
+$(binary_stamp)-libsfstdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,sf)
+
+# ----------------------------------------------------------------------
+libcxxdev_deps = $(install_stamp)
+ifeq ($(with_libcxx),yes)
+  libcxxdev_deps += $(binary_stamp)-libstdcxx
+endif
+ifeq ($(with_check),yes)
+  libcxxdev_deps += debian/README.libstdc++-baseline
+endif
+$(binary_stamp)-libstdcxx-dev: $(libcxxdev_deps)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_dev) $(d_pic)
+	dh_installdirs -p$(p_dev) $(dirs_dev)
+	dh_installdirs -p$(p_pic) $(dirs_pic)
+	dh_installdirs -p$(p_dbg) $(dirs_dbg)
+
+	: # - correct libstdc++-v3 file locations
+	mv $(d)/$(usr_lib)/libsupc++.a $(d)/$(gcc_lib_dir)/
+	mv $(d)/$(usr_lib)/libstdc++fs.a $(d)/$(gcc_lib_dir)/
+	mv $(d)/$(usr_lib)/libstdc++.{a,so} $(d)/$(gcc_lib_dir)/
+	ln -sf ../../../$(DEB_TARGET_GNU_TYPE)/libstdc++.so.$(CXX_SONAME) \
+		$(d)/$(gcc_lib_dir)/libstdc++.so
+	mv $(d)/$(usr_lib)/libstdc++_pic.a $(d)/$(gcc_lib_dir)/
+
+	rm -f $(d)/$(usr_lib)/debug/libstdc++_pic.a
+	rm -f $(d)/$(usr_lib64)/debug/libstdc++_pic.a
+
+	: # remove precompiled headers
+	-find $(d) -type d -name '*.gch' | xargs rm -rf
+
+	for i in $(d)/$(PF)/include/c++/$(GCC_VERSION)/*-linux; do \
+	  if [ -d $$i ]; then mv $$i $$i-gnu; fi; \
+	done
+
+	$(dh_compat2) dh_movefiles -p$(p_dev) $(files_dev)
+	$(dh_compat2) dh_movefiles -p$(p_pic) $(files_pic)
+ifeq ($(with_cxx_debug),yes)
+	$(dh_compat2) dh_movefiles -p$(p_dbg) $(files_dbg)
+endif
+
+	dh_link -p$(p_dev) \
+		/$(usr_lib)/libstdc++.so.$(CXX_SONAME) \
+		/$(gcc_lib_dir)/libstdc++.so \
+		/$(PFL)/include/c++/$(BASE_VERSION) /$(PFL)/include/c++/$(GCC_VERSION)
+ifeq ($(with_multiarch_cxxheaders),yes)
+	dh_link -p$(p_dev) \
+		/$(PFL)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION) \
+		/$(PFL)/include/$(DEB_TARGET_MULTIARCH)/c++/$(GCC_VERSION)
+endif
+
+	debian/dh_doclink -p$(p_dev) $(p_lbase)
+	debian/dh_doclink -p$(p_pic) $(p_lbase)
+	debian/dh_doclink -p$(p_dbg) $(p_lbase)
+	cp -p $(srcdir)/libstdc++-v3/ChangeLog \
+		$(d_dev)/$(docdir)/$(p_base)/C++/changelog.libstdc++
+ifeq ($(with_check),yes)
+	cp -p debian/README.libstdc++-baseline \
+		$(d_dev)/$(docdir)/$(p_base)/C++/README.libstdc++-baseline.$(DEB_TARGET_ARCH)
+	if [ -f $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt ]; \
+	then \
+	  cp -p $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt \
+	    $(d_dev)/$(docdir)/$(p_base)/C++/libstdc++_symbols.txt.$(DEB_TARGET_ARCH); \
+	fi
+endif
+	cp -p $(buildlibdir)/libstdc++-v3/src/libstdc++-symbols.ver \
+		$(d_pic)/$(gcc_lib_dir)/libstdc++_pic.map
+
+	cp -p $(d)/$(usr_lib)/libstdc++.so.*.py \
+		$(d_dbg)/$(PF)/share/gdb/auto-load/$(usr_lib)/debug/.
+	sed -i -e "/^libdir *=/s,=.*,= '/$(usr_lib)'," \
+		$(d_dbg)/$(PF)/share/gdb/auto-load/$(usr_lib)/debug/libstdc++.so.*.py
+
+ifeq ($(with_libcxx),yes)
+	cp -a $(d)/$(usr_lib)/libstdc++.so.*[0-9] \
+		$(d_dbg)/$(usr_lib)/
+	dh_strip -p$(p_dbg) --keep-debug
+	rm -f $(d_dbg)/$(usr_lib)/libstdc++.so.*[0-9]
+endif
+
+	dh_strip -p$(p_dev) --dbg-package=$(p_dbg)
+ifneq ($(with_common_libs),yes)
+	: # remove the debug symbols for libstdc++ built by a newer version of GCC
+	rm -rf $(d_dbg)/usr/lib/debug/$(PF)
+endif
+	dh_strip -p$(p_pic)
+
+ifeq ($(with_cxxdev),yes)
+	debian/dh_rmemptydirs -p$(p_dev)
+	debian/dh_rmemptydirs -p$(p_pic)
+	debian/dh_rmemptydirs -p$(p_dbg)
+endif
+
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_dev) -p$(p_pic) -p$(p_dbg) \
+		$(call shlibdirs_to_search,,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_dbg))
+	echo $(p_dev) $(p_pic) $(p_dbg) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+
+doxygen_doc_dir = $(buildlibdir)/libstdc++-v3/doc
+
+doxygen-docs: $(build_doxygen_stamp)
+$(build_doxygen_stamp): $(build_stamp)
+	$(MAKE) -C $(buildlibdir)/libstdc++-v3/doc SHELL=/bin/bash doc-html-doxygen
+	$(MAKE) -C $(buildlibdir)/libstdc++-v3/doc SHELL=/bin/bash doc-man-doxygen
+	-find $(doxygen_doc_dir)/doxygen/html -name 'struct*' -empty | xargs rm -f
+
+	touch $@
+
+$(binary_stamp)-libstdcxx-doc: $(install_stamp) doxygen-docs
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_libd)
+	dh_installdirs -p$(p_libd) \
+		$(docdir)/$(p_base)/libstdc++ \
+		$(PF)/share/man
+
+#	debian/dh_doclink -p$(p_libd) $(p_base)
+	dh_link -p$(p_libd) /usr/share/doc/$(p_base) /usr/share/doc/$(p_libd)
+	dh_installdocs -p$(p_libd)
+	rm -f $(d_libd)/$(docdir)/$(p_base)/copyright
+
+	cp -a $(srcdir)/libstdc++-v3/doc/html/* \
+		$(d_libd)/$(docdir)/$(p_base)/libstdc++/.
+	cp -a $(doxygen_doc_dir)/doxygen/html \
+		$(d_libd)/$(docdir)/$(p_base)/libstdc++/user
+	find $(d_libd)/$(docdir)/$(p_base)/libstdc++ -name '*.md5' \
+		| xargs -r rm -f
+
+# Broken docs ... see #766499
+#	rm -f $(d_libd)/$(docdir)/$(p_base)/libstdc++/*/jquery.js
+#	dh_link -p$(p_libd) \
+#		/usr/share/javascript/jquery/jquery.js \
+#		/$(docdir)/$(p_base)/libstdc++/html/jquery.js \
+#		/usr/share/javascript/jquery/jquery.js \
+#		/$(docdir)/$(p_base)/libstdc++/user/jquery.js
+
+	: FIXME: depending on the doxygen version
+	if [ -d $(doxygen_doc_dir)/doxygen/man/man3cxx ]; then \
+	  cp -a $(doxygen_doc_dir)/doxygen/man/man3cxx \
+	    $(d_libd)/$(PF)/share/man/man3; \
+	  if [ -d $(doxygen_doc_dir)/doxygen/man/man3 ]; then \
+	    cp -a $(doxygen_doc_dir)/doxygen/man/man3/* \
+	      $(d_libd)/$(PF)/share/man/man3/; \
+	  fi; \
+	elif [ -d $(doxygen_doc_dir)/doxygen/man/man3 ]; then \
+	  cp -a $(doxygen_doc_dir)/doxygen/man/man3 \
+	    $(d_libd)/$(PF)/share/man/man3; \
+	fi
+
+	for i in $(d_libd)/$(PF)/share/man/man3/*.3; do \
+	  [ -f $${i} ] || continue; \
+	  mv $${i} $${i}cxx; \
+	done
+	rm -f $(d_libd)/$(PF)/share/man/man3/todo.3*
+
+	mkdir -p $(d_libd)/usr/share/lintian/overrides
+	cp -p debian/$(p_libd).overrides \
+		$(d_libd)/usr/share/lintian/overrides/$(p_libd)
+
+	echo $(p_libd) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libtsan.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libtsan.mk
@@ -0,0 +1,78 @@
+$(lib_binaries)  += libtsan
+ifeq (0,1)
+ifeq ($(with_lib64tsan),yes)
+  $(lib_binaries)  += lib64tsan
+endif
+ifeq ($(with_lib32tsan),yes)
+  $(lib_binaries)	+= lib32tsan
+endif
+ifeq ($(with_libn32tsan),yes)
+  $(lib_binaries)	+= libn32tsan
+endif
+ifeq ($(with_libx32tsan),yes)
+  $(lib_binaries)	+= libx32tsan
+endif
+ifeq ($(with_libhftsan),yes)
+  $(lib_binaries)	+= libhftsan
+endif
+ifeq ($(with_libsftsan),yes)
+  $(lib_binaries)	+= libsftsan
+endif
+endif
+
+define __do_tsan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libtsan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst tsan$(TSAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst tsan$(TSAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_tsan = $(call __do_tsan,lib$(1)tsan$(TSAN_SONAME),$(1))
+
+$(binary_stamp)-libtsan: $(install_stamp)
+	$(call do_tsan,)
+
+$(binary_stamp)-lib64tsan: $(install_stamp)
+	$(call do_tsan,64)
+
+$(binary_stamp)-lib32tsan: $(install_stamp)
+	$(call do_tsan,32)
+
+$(binary_stamp)-libn32tsan: $(install_stamp)
+	$(call do_tsan,n32)
+
+$(binary_stamp)-libx32tsan: $(install_stamp)
+	$(call do_tsan,x32)
+
+$(binary_stamp)-libhftsan: $(install_dependencies)
+	$(call do_tsan,hf)
+
+$(binary_stamp)-libsftsan: $(install_dependencies)
+	$(call do_tsan,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libubsan.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libubsan.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libubsan
+ifeq ($(with_lib64ubsan),yes)
+  $(lib_binaries)  += lib64ubsan
+endif
+ifeq ($(with_lib32ubsan),yes)
+  $(lib_binaries)	+= lib32ubsan
+endif
+ifeq ($(with_libn32ubsan),yes)
+  $(lib_binaries)	+= libn32ubsan
+endif
+ifeq ($(with_libx32ubsan),yes)
+  $(lib_binaries)	+= libx32ubsan
+endif
+ifeq ($(with_libhfubsan),yes)
+  $(lib_binaries)	+= libhfubsan
+endif
+ifeq ($(with_libsfubsan),yes)
+  $(lib_binaries)	+= libsfubsan
+endif
+
+define __do_ubsan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libubsan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst ubsan$(UBSAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst ubsan$(UBSAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_ubsan = $(call __do_ubsan,lib$(1)ubsan$(UBSAN_SONAME),$(1))
+
+$(binary_stamp)-libubsan: $(install_stamp)
+	$(call do_ubsan,)
+
+$(binary_stamp)-lib64ubsan: $(install_stamp)
+	$(call do_ubsan,64)
+
+$(binary_stamp)-lib32ubsan: $(install_stamp)
+	$(call do_ubsan,32)
+
+$(binary_stamp)-libn32ubsan: $(install_stamp)
+	$(call do_ubsan,n32)
+
+$(binary_stamp)-libx32ubsan: $(install_stamp)
+	$(call do_ubsan,x32)
+
+$(binary_stamp)-libhfubsan: $(install_dependencies)
+	$(call do_ubsan,hf)
+
+$(binary_stamp)-libsfubsan: $(install_dependencies)
+	$(call do_ubsan,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-libvtv.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-libvtv.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libvtv
+ifeq ($(with_lib64vtv),yes)
+  $(lib_binaries)  += lib64vtv
+endif
+ifeq ($(with_lib32vtv),yes)
+  $(lib_binaries)	+= lib32vtv
+endif
+ifeq ($(with_libn32vtv),yes)
+  $(lib_binaries)	+= libn32vtv
+endif
+ifeq ($(with_libx32vtv),yes)
+  $(lib_binaries)	+= libx32vtv
+endif
+ifeq ($(with_libhfvtv),yes)
+  $(lib_binaries)	+= libhfvtv
+endif
+ifeq ($(with_libsfvtv),yes)
+  $(lib_binaries)	+= libsfvtv
+endif
+
+define __do_vtv
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libvtv.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst vtv$(VTV_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst vtv$(VTV_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_vtv = $(call __do_vtv,lib$(1)vtv$(VTV_SONAME),$(1))
+
+$(binary_stamp)-libvtv: $(install_stamp)
+	$(call do_vtv,)
+
+$(binary_stamp)-lib64vtv: $(install_stamp)
+	$(call do_vtv,64)
+
+$(binary_stamp)-lib32vtv: $(install_stamp)
+	$(call do_vtv,32)
+
+$(binary_stamp)-libn32vtv: $(install_stamp)
+	$(call do_vtv,n32)
+
+$(binary_stamp)-libx32vtv: $(install_stamp)
+	$(call do_vtv,x32)
+
+$(binary_stamp)-libhfvtv: $(install_dependencies)
+	$(call do_vtv,hf)
+
+$(binary_stamp)-libsfvtv: $(install_dependencies)
+	$(call do_vtv,sf)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-neon.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-neon.mk
@@ -0,0 +1,47 @@
+arch_binaries  := $(arch_binaries) neon
+
+p_nlgcc		= libgcc$(GCC_SONAME)-neon
+p_ngomp		= libgomp$(GOMP_SONAME)-neon
+p_nlobjc	= libobjc$(OBJC_SONAME)-neon
+p_nflib		= libgfortran$(FORTRAN_SONAME)-neon
+p_nlcxx		= libstdc++$(CXX_SONAME)-neon
+
+d_nlgcc		= debian/$(p_nlgcc)
+d_ngomp		= debian/$(p_ngomp)
+d_nlobjc	= debian/$(p_nlobjc)
+d_nflib		= debian/$(p_nflib)
+d_nlcxx		= debian/$(p_nlcxx)
+
+neon_pkgs = -p$(p_nlgcc) -p$(p_ngomp) -p$(p_nlobjc) -p$(p_nflib) -p$(p_nlcxx)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-neon: $(install_neon_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdirs -p$(p_nlgcc) \
+		$(PF)/share/doc \
+		lib/neon
+	dh_installdirs -A -p$(p_ngomp) -p$(p_nlobjc) -p$(p_nflib) -p$(p_nlcxx) \
+		$(PF)/share/doc \
+		$(PF)/lib/neon
+
+	cp -a $(d_neon)/$(PF)/lib/libgcc*.so.* \
+		$(d_nlgcc)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libgomp*.so.* \
+		$(d_ngomp)/$(PF)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libobjc*.so.* \
+		$(d_nlobjc)/$(PF)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libgfortran*.so.* \
+		$(d_nflib)/$(PF)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libstdc++*.so.* \
+		$(d_nlcxx)/$(PF)/lib/neon/
+
+	for p in $(p_nlgcc) $(p_ngomp) $(p_nlobjc) $(p_nflib) $(p_nlcxx); do \
+	  ln -s ../$(p_base) debian/$$p/usr/share/doc/$$p; \
+	done
+	dh_strip $(neon_pkgs)
+	dh_shlibdeps $(neon_pkgs)
+	echo $(p_nlgcc) $(p_ngomp) $(p_nlobjc) $(p_nflib) $(p_nlcxx) >> debian/arch_binaries
+
+	touch $@
--- gcc-6-6.3.0.orig/debian/rules.d/binary-nof.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-nof.mk
@@ -0,0 +1,51 @@
+arch_binaries  := $(arch_binaries) nof
+
+p_nof  = gcc$(pkg_ver)-nof
+d_nof  = debian/$(p_nof)
+
+dirs_nof = \
+	$(docdir) \
+	$(usr_lib)/nof
+ifeq ($(with_cdev),yes)
+  dirs_nof += \
+	$(gcc_lib_dir)/nof
+endif
+
+ifeq ($(with_cdev),yes)
+  files_nof = \
+	$(libgcc_dir)/libgcc_s_nof.so.$(GCC_SONAME) \
+	$(gcc_lib_dir)/libgcc_s_nof.so \
+	$(usr_lib)/nof \
+	$(gcc_lib_dir)/nof
+else
+  files_nof = \
+	$(usr_lib)/libgcc_s_nof.so.$(GCC_SONAME)
+endif
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-nof: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	mv $(d)/$(usr_lib)/libgcc_s_nof.so.$(GCC_SONAME) $(d)/$(libgcc_dir)/.
+	rm -f $(d)/$(usr_lib)/libgcc_s_nof.so
+	ln -sf $(libgcc_dir)/libgcc_s_nof.so.$(GCC_SONAME) \
+		$(d)/$(gcc_lib_dir)/libgcc_s_nof.so
+
+	rm -rf $(d_nof)
+	dh_installdirs -p$(p_nof) $(dirs_nof)
+	$(dh_compat2) dh_movefiles -p$(p_nof) $(files_nof)
+	debian/dh_doclink -p$(p_nof) $(p_xbase)
+	dh_strip -p$(p_nof)
+	dh_shlibdeps -p$(p_nof)
+
+	dh_makeshlibs $(ldconfig_arg) -p$(p_nof)
+	: # Only keep the shlibs file for the libgcc_s_nof library
+	fgrep libgcc_s_nof debian/$(p_nof)/DEBIAN/shlibs \
+		> debian/$(p_nof)/DEBIAN/shlibs.tmp
+	mv -f debian/$(p_nof)/DEBIAN/shlibs.tmp debian/$(p_nof)/DEBIAN/shlibs
+
+	echo $(p_nof) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-objc.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-objc.mk
@@ -0,0 +1,67 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) objc-multi
+  endif
+  arch_binaries := $(arch_binaries) objc
+endif
+
+p_objc	= gobjc$(pkg_ver)$(cross_bin_arch)
+d_objc	= debian/$(p_objc)
+
+p_objc_m= gobjc$(pkg_ver)-multilib$(cross_bin_arch)
+d_objc_m= debian/$(p_objc_m)
+
+dirs_objc = \
+	$(docdir)/$(p_xbase)/ObjC \
+	$(gcc_lexec_dir)
+
+files_objc = \
+	$(gcc_lexec_dir)/cc1obj
+
+$(binary_stamp)-objc: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_objc)
+	dh_installdirs -p$(p_objc) $(dirs_objc)
+	$(dh_compat2) dh_movefiles -p$(p_objc) $(files_objc)
+
+	cp -p $(srcdir)/libobjc/{README*,THREADS*} \
+		$(d_objc)/$(docdir)/$(p_xbase)/ObjC/.
+
+	cp -p $(srcdir)/libobjc/ChangeLog \
+		$(d_objc)/$(docdir)/$(p_xbase)/ObjC/changelog.libobjc
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_objc)/usr/share/lintian/overrides
+	echo '$(p_objc) binary: binary-without-manpage' \
+	  >> $(d_objc)/usr/share/lintian/overrides/$(p_objc)
+endif
+
+	debian/dh_doclink -p$(p_objc) $(p_xbase)
+
+	debian/dh_rmemptydirs -p$(p_objc)
+
+	dh_strip -p$(p_objc) \
+	  $(if $(unstripped_exe),-X/cc1obj)
+	dh_shlibdeps -p$(p_objc)
+	echo $(p_objc) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-objc-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_objc_m)
+	dh_installdirs -p$(p_objc_m) $(docdir)
+
+	debian/dh_doclink -p$(p_objc_m) $(p_xbase)
+
+	dh_strip -p$(p_objc_m)
+	dh_shlibdeps -p$(p_objc_m)
+	echo $(p_objc_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-objcxx.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-objcxx.mk
@@ -0,0 +1,60 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) objcxx-multi
+  endif
+  arch_binaries := $(arch_binaries) objcxx
+endif
+
+p_objcx		= gobjc++$(pkg_ver)$(cross_bin_arch)
+d_objcx		= debian/$(p_objcx)
+
+p_objcx_m	= gobjc++$(pkg_ver)-multilib$(cross_bin_arch)
+d_objcx_m	= debian/$(p_objcx_m)
+
+dirs_objcx = \
+	$(docdir)/$(p_xbase)/Obj-C++ \
+	$(gcc_lexec_dir)
+
+files_objcx = \
+	$(gcc_lexec_dir)/cc1objplus
+
+$(binary_stamp)-objcxx: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_objcx)
+	dh_installdirs -p$(p_objcx) $(dirs_objcx)
+	$(dh_compat2) dh_movefiles -p$(p_objcx) $(files_objcx)
+
+	debian/dh_doclink -p$(p_objcx) $(p_xbase)
+	cp -p $(srcdir)/gcc/objcp/ChangeLog \
+		$(d_objcx)/$(docdir)/$(p_xbase)/Obj-C++/changelog
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_objcx)/usr/share/lintian/overrides
+	echo '$(p_objcx) binary: binary-without-manpage' \
+	  >> $(d_objcx)/usr/share/lintian/overrides/$(p_objcx)
+endif
+
+	debian/dh_rmemptydirs -p$(p_objcx)
+
+	dh_strip -p$(p_objcx) \
+	  $(if $(unstripped_exe),-X/cc1objplus)
+	dh_shlibdeps -p$(p_objcx)
+	echo $(p_objcx) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-objcxx-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+	rm -rf $(d_objcx_m)
+	debian/dh_doclink -p$(p_objcx_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_objcx_m)
+	dh_strip -p$(p_objcx_m)
+	dh_shlibdeps -p$(p_objcx_m)
+	echo $(p_objcx_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-snapshot.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-snapshot.mk
@@ -0,0 +1,234 @@
+arch_binaries  := $(arch_binaries) snapshot
+
+ifneq (,$(findstring gcc-snapshot, $(PKGSOURCE)))
+  p_snap = gcc-snapshot
+else ifneq (,$(findstring gcc-linaro, $(PKGSOURCE)))
+  p_snap = gcc-linaro
+else
+  $(error unknown build for single gcc package)
+endif
+
+ifeq ($(DEB_CROSS),yes)
+  p_snap := $(p_snap)$(cross_bin_arch)
+endif
+d_snap	= debian/$(p_snap)
+
+dirs_snap = \
+	$(docdir)/$(p_snap) \
+	usr/lib
+
+ifeq ($(with_hppa64),yes)
+  snapshot_depends = binutils-hppa64
+endif
+
+$(stampdir)/ecj_binaries: $(install_snap_stamp)
+	mkdir -p $(builddir)/aot/jar $(builddir)/aot/bin
+	cp $(ecj_jar) $(builddir)/aot/jar/ecj-standalone.jar
+	zip -d $(builddir)/aot/jar/ecj-standalone.jar \
+		'org/eclipse/jdt/core/JDTCompilerAdapter*'
+
+	cd $(builddir)/aot/jar \
+	  && fastjar xf ecj-standalone.jar \
+	  && find -name '*.rsc' -o -name '*.properties' \
+		| fastjar -c -@ - -f ../resources.jar
+	rm -rf $(builddir)/aot/jar/META-INF $(builddir)/aot/jar/org
+	$(d)/$(PF)/bin/gcj \
+	    -c -O2 -g -fPIC -fjni -findirect-dispatch \
+	    -o $(builddir)/aot/bin/resources.o $(builddir)/aot/resources.jar
+
+	cp $(srcdir)/libjava/contrib/classfile.py $(builddir)/aot/
+	cp $(buildlibdir)/libjava/contrib/*.py $(builddir)/aot/
+	grep -v '^sys.path.insert' $(buildlibdir)/libjava/contrib/aot-compile \
+	    > $(builddir)/aot/aot-compile
+	chmod 755 $(builddir)/aot/aot-compile
+	patch -p1 < debian/patches/aotcompile.diff
+	LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(CURDIR)/$(d)/$(PF)/lib \
+	RPATH=-Wl,-rpath,/$(PF)/lib \
+	PYTHONPATH=$(builddir)/aot \
+	  python $(builddir)/aot/aot-compile \
+	    --gcj=$(CURDIR)/$(d)/$(PF)/bin/gcj \
+	    --dbtool=$(CURDIR)/$(d)/$(PF)/bin/gcj-dbtool \
+	    --makeflags="$(NJOBS)" \
+	    --ldflags="$(LDFLAGS)" \
+	    $(builddir)/aot/jar $(builddir)/aot/bin
+	touch $@
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-snapshot: $(install_snap_stamp) \
+    $(if $(filter $(with_ecj),yes),$(stampdir)/ecj_binaries)
+	dh_testdir
+	dh_testroot
+	mv $(install_snap_stamp) $(install_snap_stamp)-tmp
+
+	rm -rf $(d_snap)
+	dh_installdirs -p$(p_snap) $(dirs_snap)
+
+	mv $(d)/$(PF) $(d_snap)/usr/lib/
+
+	find $(d_snap) -name '*.gch' -type d | xargs -r rm -rf
+	find $(d_snap) -name '*.la' -o -name '*.lai' | xargs -r rm -f
+
+	: # FIXME: libbacktrace is not installed by default
+	for d in . 32 n32 64 sf hf; do \
+	  if [ -f $(buildlibdir)/$$d/libbacktrace/.libs/libbacktrace.a ]; then \
+	    install -m644 $(buildlibdir)/$$d/libbacktrace/.libs/libbacktrace.a \
+	      $(d_snap)/$(gcc_lib_dir)/$$d; \
+	  fi; \
+	done
+	if [ -f $(buildlibdir)/libbacktrace/backtrace-supported.h ]; then \
+	  install -m644 $(buildlibdir)/libbacktrace/backtrace-supported.h \
+	    $(d_snap)/$(gcc_lib_dir)/include/; \
+	  install -m644 $(srcdir)/libbacktrace/backtrace.h \
+	    $(d_snap)/$(gcc_lib_dir)/include/; \
+	fi
+
+	rm -rf $(d_snap)/$(PF)/lib/nof
+ifeq ($(with_java),yes)
+	mv $(d)/usr/lib/jvm $(d_snap)/usr/lib/
+
+	dh_link -p$(p_snap) \
+	  $(gcc_lib_dir)/include/gcj $(jvm_dir)/include/gcj \
+	  usr/bin/ecj $(jvm_dir)/bin/javac
+
+  ifneq ($(DEB_TARGET_ARCH_CPU),$(java_cpu))
+	ln -sf $(java_cpu) $(d_snap)/$(jvm_dir)/jre/lib/$(DEB_TARGET_ARCH_CPU)
+  endif
+  ifeq ($(with_ecj),yes)
+	install -m755 $(builddir)/aot/bin/javac $(d_snap)/$(jvm_dir)/bin/javac
+	install -m755 $(builddir)/aot/bin/ecj1 $(d_snap)/$(gcc_lexec_dir)/ecj1
+
+    ifeq (./,$(dir $(ecj_jar)))
+	install -m 644 $(ecj_jar) $(d_snap)/$(jvm_dir)/lib/ecj.jar
+    else
+	dh_link -p$(p_snap) \
+	  $(ecj_jar) $(jvm_dir)/lib/ecj.jar
+    endif
+  endif
+
+	: # provide .jinfo file
+	( \
+	  echo 'name=$(jvm_name_short)'; \
+	  echo 'alias=java-gcj$(pkg_ver)'; \
+	  echo 'priority=$(priority)'; \
+	  echo 'section=main'; \
+	  echo ''; \
+	  for i in $(jre_tools); do \
+	    echo "jre $$i /$(jvm_dir)/jre/bin/$$i"; \
+	  done; \
+	  for i in $(jdk_tools); do \
+	    echo "jdk $$i /$(jvm_dir)/bin/$$i"; \
+	  done; \
+	) > $(d_snap)/usr/lib/jvm/.java-gcj$(pkg_ver)-snap.jinfo
+endif
+
+ifeq ($(with_ada),yes FIXME: apply our ada patches)
+	dh_link -p$(p_snap) \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnat.a \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnat-$(GNAT_VERSION).a
+	dh_link -p$(p_snap) \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnarl.a \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnarl-$(GNAT_VERSION).a
+
+	set -e; \
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  mv $(d_snap)/$(gcc_lib_dir)/adalib/$$vlib.so.1 $(d_snap)/$(PF)/$(libdir)/. ; \
+	  rm -f $(d_snap)/$(gcc_lib_dir)/adalib/$$lib.so.1; \
+	  dh_link -p$(p_snap) \
+	    /$(PF)/$(libdir)/$$vlib.so.1 /$(PF)/$(libdir)/$$vlib.so \
+	    /$(PF)/$(libdir)/$$vlib.so.1 /$(PF)/$(libdir)/$$lib.so \
+	    /$(PF)/$(libdir)/$$vlib.so.1 /$(gcc_lib_dir)/rts-native/adalib/$$lib.so; \
+	done
+endif
+ifeq ($(with_ada),yes)
+	ln -sf gcc $(d_snap)/$(PF)/bin/gnatgcc
+endif
+
+ifeq ($(with_hppa64),yes)
+	: # provide as and ld links
+	dh_link -p $(p_snap) \
+		/usr/bin/hppa64-linux-gnu-as \
+		/$(PF)/libexec/gcc/hppa64-linux-gnu/$(GCC_VERSION)/as \
+		/usr/bin/hppa64-linux-gnu-ld \
+		/$(PF)/libexec/gcc/hppa64-linux-gnu/$(GCC_VERSION)/ld
+endif
+
+ifeq ($(with_check),yes)
+	dh_installdocs -p$(p_snap) test-summary
+# more than one libgo.sum, avoid it 
+	mkdir -p $(d_snap)/$(docdir)/$(p_snap)/test-summaries
+	cp -p $$(find $(builddir)/gcc/testsuite -maxdepth 2 \( -name '*.sum' -o -name '*.log' \)) \
+	      $$(find $(buildlibdir)/*/testsuite -maxdepth 1 \( -name '*.sum'  -o -name '*.log' \) ! -name 'libgo.*') \
+		$(d_snap)/$(docdir)/$(p_snap)/test-summaries/
+  ifeq ($(with_go),yes)
+	cp -p $(buildlibdir)/libgo/libgo.sum \
+		$(d_snap)/$(docdir)/$(p_snap)/test-summaries/
+  endif
+	if which xz 2>&1 >/dev/null; then \
+	  echo -n $(d_snap)/$(docdir)/$(p_snap)/test-summaries/* \
+	    | xargs -d ' ' -L 1 -P $(USE_CPUS)	xz -7v; \
+	fi
+else
+	dh_installdocs -p$(p_snap)
+endif
+	if [ -f $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt ]; \
+	then \
+	  cp -p $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt \
+	    $(d_snap)/$(docdir)/$(p_snap)/libstdc++6_symbols.txt; \
+	fi
+	cp -p debian/README.snapshot \
+		$(d_snap)/$(docdir)/$(p_snap)/README.Debian
+	cp -p debian/README.Bugs \
+		$(d_snap)/$(docdir)/$(p_snap)/
+	dh_installchangelogs -p$(p_snap)
+ifeq ($(DEB_TARGET_ARCH),hppa)
+	dh_strip -p$(p_snap) -Xdebug -X.o -X.a -X/cgo -Xbin/go -Xbin/gofmt \
+	  $(if $(unstripped_exe),$(foreach i,cc1 cc1obj cc1objplus cc1plus cc1d f951 go1 jc1 lto1, -X/$(i)))
+else
+	dh_strip -p$(p_snap) -Xdebug -X/cgo -Xbin/go -Xbin/gofmt \
+	  $(if $(unstripped_exe),$(foreach i,cc1 cc1obj cc1objplus cc1plus cc1d f951 go1 jc1 lto1, -X/$(i)))
+endif
+	dh_compress -p$(p_snap) -X README.Bugs -X.log.xz -X.sum.xz
+	-find $(d_snap) -type d ! -perm 755 -exec chmod 755 {} \;
+	dh_fixperms -p$(p_snap)
+ifeq ($(with_ada),yes)
+	find $(d_snap)/$(gcc_lib_dir) -name '*.ali' | xargs -r chmod 444
+endif
+
+	mkdir -p $(d_snap)/usr/share/lintian/overrides
+	cp -p debian/gcc-snapshot.overrides \
+		$(d_snap)/usr/share/lintian/overrides/$(p_snap)
+
+	( \
+	  echo 'libgcc_s $(GCC_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libobjc $(OBJC_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgfortran $(FORTRAN_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libffi $(FFI_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgcj $(GCJ_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgcj-tools $(GCJ_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgij $(GCJ_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgcj_bc 1 ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgomp $(GOMP_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgnat-$(GNAT_SONAME) 1 ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgnarl-$(GNAT_SONAME) 1 ${p_snap} (>= $(DEB_VERSION))'; \
+	) > debian/shlibs.local
+
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps)  \
+	  dh_shlibdeps -p$(p_snap) -l$(CURDIR)/$(d_snap)/$(PF)/lib:$(CURDIR)/$(d_snap)/$(PF)/$(if $(filter $(DEB_TARGET_ARCH),amd64 ppc64),lib32,lib64):/usr/$(DEB_TARGET_GNU_TYPE)/lib -Xlibgcj-tools
+	-sed -i -e 's/$(p_snap)[^,]*, //g' debian/$(p_snap).substvars
+
+ifeq ($(with_multiarch_lib),yes)
+	: # paths needed for relative lookups from startfile_prefixes
+	for ma in $(xarch_multiarch_names); do \
+	  mkdir -p $(d_snap)/lib/$$ma; \
+	  mkdir -p $(d_snap)/usr/lib/$$ma; \
+	done
+endif
+
+	dh_gencontrol -p$(p_snap) -- $(common_substvars) \
+		'-Vsnap:depends=$(snapshot_depends)' '-Vsnap:recommends=$(snapshot_recommends)'
+	dh_installdeb -p$(p_snap)
+	dh_md5sums -p$(p_snap)
+	dh_builddeb -p$(p_snap)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_snap_stamp)-tmp $(install_snap_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-softfloat.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-softfloat.mk
@@ -0,0 +1,31 @@
+arch_binaries  := $(arch_binaries) softfloat
+
+p_softfloat  = gcc$(pkg_ver)-soft-float
+d_softfloat  = debian/$(p_softfloat)
+
+dirs_softfloat = \
+	$(PFL)/$(libdir) \
+	$(gcc_lib_dir)
+
+files_softfloat = \
+	$(PFL)/$(libdir)/soft-float \
+	$(gcc_lib_dir)/soft-float
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-softfloat: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_softfloat)
+	dh_installdirs -p$(p_softfloat) $(dirs_softfloat)
+	$(dh_compat2) dh_movefiles -p$(p_softfloat) $(files_softfloat)
+	rm -rf $(d_softfloat)/$(PFL)/$(libdir)/soft-float/libssp.so*
+	mv $(d_softfloat)/$(PFL)/$(libdir)/soft-float/libssp.a \
+		$(d_softfloat)/$(PFL)/$(libdir)/soft-float/libssp_nonshared.a
+	debian/dh_doclink -p$(p_softfloat) $(p_xbase)
+	dh_strip -p$(p_softfloat) -Xlibgcj.a
+	dh_shlibdeps -p$(p_softfloat)
+	echo $(p_softfloat) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.3.0.orig/debian/rules.d/binary-source.mk
+++ gcc-6-6.3.0/debian/rules.d/binary-source.mk
@@ -0,0 +1,52 @@
+indep_binaries := $(indep_binaries) gcc-source
+
+ifeq ($(BACKPORT),true)
+  p_source = gcc$(pkg_ver)-$(GCC_VERSION)-source
+else
+  p_source = gcc$(pkg_ver)-source
+endif
+d_source= debian/$(p_source)
+
+$(binary_stamp)-gcc-source: $(install_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdocs -p$(p_source)
+	dh_installchangelogs -p$(p_source)
+
+	dh_install -p$(p_source) $(gcc_tarball) usr/src/gcc$(pkg_ver)
+ifneq (,$(gdc_tarball))
+	dh_install -p$(p_source) $(gdc_tarball) usr/src/gcc$(pkg_ver)
+endif
+	tar cf - $$(find './debian' -mindepth 1 \( \
+		-name .svn -prune -o \
+		-path './debian/gcc-*' -type d -prune -o \
+		-path './debian/cpp-*' -type d -prune -o \
+		-path './debian/*fortran*' -type d -prune -o \
+		-path './debian/lib*' -type d -prune -o \
+		-path './debian/patches/*' -prune -o \
+		-path './debian/tmp*' -prune -o \
+		-path './debian/files' -prune -o \
+		-path './debian/rules.d/*' -prune -o \
+		-path './debian/rules.parameters' -prune -o \
+		-path './debian/soname-cache' -prune -o \
+		-path './debian/*substvars*' -prune -o \
+		-path './debian/gcc-snapshot*' -prune -o \
+		-path './debian/*[0-9]*.p*' -prune -o \
+		-path './debian/*$(pkg_ver)[.-]*' -prune -o \
+		-print \) ) \
+	  | tar -x -C $(d_source)/usr/src/gcc$(pkg_ver)  -f -
+	# FIXME: Remove generated files
+	find $(d_source)/usr/src/gcc$(pkg_ver) -name '*.debhelper.log' -o -name .svn | xargs rm -rf
+
+	touch $(d_source)/usr/src/gcc$(pkg_ver)/debian/rules.parameters
+
+	dh_link -p$(p_source) \
+		/usr/src/gcc$(pkg_ver)/debian/patches /usr/src/gcc$(pkg_ver)/patches
+
+	mkdir -p $(d_source)/usr/share/lintian/overrides
+	cp -p debian/$(p_source).overrides \
+		$(d_source)/usr/share/lintian/overrides/$(p_source)
+	echo $(p_source) >> debian/indep_binaries
+
+	touch $@
--- gcc-6-6.3.0.orig/debian/rules.defs
+++ gcc-6-6.3.0/debian/rules.defs
@@ -0,0 +1,2110 @@
+# -*- makefile -*-
+# definitions used in more than one Makefile / rules file
+
+NJOBS :=
+USE_CPUS := 1
+ifneq (,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS))))
+  USE_CPUS := $(subst parallel=,,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS))))
+  NJOBS := -j $(USE_CPUS)
+endif
+
+# common vars
+SHELL		= /bin/bash -e	# brace expansion used in rules file
+srcdir		= $(CURDIR)/src
+builddir	= $(CURDIR)/build
+builddir_jit	= $(CURDIR)/build-jit
+builddir_hppa64	= $(CURDIR)/build-hppa64
+stampdir	= stamps
+
+distribution	:= $(shell lsb_release -is)
+distrelease	:= $(shell lsb_release -cs)
+derivative	:= $(shell if dpkg-vendor --derives-from Ubuntu; then echo Ubuntu; \
+			elif dpkg-vendor --derives-from Debian; then echo Debian; \
+			else echo Unknown; fi)
+
+# On non official archives, "lsb_release -cs" default to "n/a". Assume
+# sid in that case 
+ifeq ($(distrelease),n/a)
+distrelease	:= sid
+endif
+
+on_buildd := $(shell [ -f /CurrentlyBuilding -o "$$LOGNAME" = buildd ] && echo yes)
+
+# creates {srcdir,builddir}_{hppa64,neon}
+$(foreach x,srcdir builddir,$(foreach target,hppa64 neon,$(eval \
+  $(x)_$(target) := $($(x))-$(target))))
+
+# for architecture dependent variables and changelog vars
+vafilt = $(subst $(2)=,,$(filter $(2)=%,$(1)))
+# for rules.sonames
+vafilt_defined = 1
+
+dpkg_target_vars := $(shell (dpkg-architecture | grep -q DEB_TARGET) && echo yes)
+ifeq ($(dpkg_target_vars),yes)
+  DEB_TARGET_ARCH=
+  DEB_TARGET_ARCH_BITS=
+  DEB_TARGET_ARCH_CPU=
+  DEB_TARGET_ARCH_ENDIAN=
+  DEB_TARGET_ARCH_OS=
+  DEB_TARGET_GNU_CPU=
+  DEB_TARGET_GNU_SYSTEM=
+  DEB_TARGET_GNU_TYPE=
+  DEB_TARGET_MULTIARCH=
+endif
+
+DPKG_VARS		:= $(shell dpkg-architecture)
+ifeq ($(dpkg_target_vars),yes)
+  DPKG_VARS		:= $(filter-out DEB_TARGET_%, $(DPKG_VARS))
+endif
+DEB_BUILD_ARCH		?= $(call vafilt,$(DPKG_VARS),DEB_BUILD_ARCH)
+DEB_BUILD_GNU_TYPE	?= $(call vafilt,$(DPKG_VARS),DEB_BUILD_GNU_TYPE)
+DEB_BUILD_MULTIARCH	?= $(call vafilt,$(DPKG_VARS),DEB_BUILD_MULTIARCH)
+DEB_HOST_ARCH		?= $(call vafilt,$(DPKG_VARS),DEB_HOST_ARCH)
+DEB_HOST_GNU_CPU	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_CPU)
+DEB_HOST_GNU_SYSTEM	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_SYSTEM)
+DEB_HOST_GNU_TYPE	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_TYPE)
+DEB_HOST_MULTIARCH	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_MULTIARCH)
+
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper hardy lucid precise quantal raring saucy trusty))
+    ifeq ($(DEB_BUILD_GNU_TYPE),i486-linux-gnu)
+      DEB_BUILD_GNU_TYPE = i686-linux-gnu
+    endif
+    ifeq ($(DEB_HOST_GNU_TYPE),i486-linux-gnu)
+      DEB_HOST_GNU_TYPE	= i686-linux-gnu
+    endif
+  endif
+else
+  ifneq (,$(filter $(distrelease),lenny etch squeeze wheezy))
+    # keep dpkg defaults
+  else ifneq (,$(filter $(distrelease),jessie))
+    ifeq ($(DEB_BUILD_GNU_TYPE),i486-linux-gnu)
+      DEB_BUILD_GNU_TYPE = i586-linux-gnu
+    endif
+    ifeq ($(DEB_HOST_GNU_TYPE),i486-linux-gnu)
+      DEB_HOST_GNU_TYPE	= i586-linux-gnu
+    endif
+  else
+    # stretch and newer ...
+    DEB_BUILD_GNU_TYPE := $(subst i586,i686,$(DEB_BUILD_GNU_TYPE))
+    DEB_HOST_GNU_TYPE := $(subst i586,i686,$(DEB_HOST_GNU_TYPE))
+  endif
+endif
+
+CHANGELOG_VARS := $(shell dpkg-parsechangelog | \
+	sed -n 's/ /_/g;/^[^_]/s/^\([^:]*\):_\(.*\)/\1=\2/p')
+
+# the name of the source package
+PKGSOURCE := $(call vafilt,$(CHANGELOG_VARS),Source)
+# those are required here too
+SOURCE_VERSION := $(call vafilt,$(CHANGELOG_VARS),Version)
+DEB_VERSION := $(strip $(shell echo $(SOURCE_VERSION) | \
+        sed -e 's/.*://' -e 's/ds[0-9]*//'))
+# epoch used for gcc versions up to 3.3.x, now used for some remaining
+# libraries: libgcc1, libobjc1
+EPOCH := 1
+DEB_EVERSION := $(EPOCH):$(DEB_VERSION)
+BASE_VERSION := $(shell echo $(DEB_VERSION) | sed -e 's/\([1-9]\).*-.*/\1/')
+
+ifneq (,$(findstring gcc-snapshot, $(PKGSOURCE)))
+  single_package = yes
+  trunk_build = yes
+else ifneq (,$(findstring gcc-linaro, $(PKGSOURCE)))
+  single_package = yes
+  trunk_build = no
+else
+  # --program-suffix=-$(BASE_VERSION)
+  versioned_packages := yes
+endif
+
+# push glibc stack traces into stderr
+export LIBC_FATAL_STDERR_=1
+
+# ---------------------------------------------------------------------------
+# set target
+# - GNU triplet via DEB_TARGET_GNU_TYPE
+# - Debian arch in debian/target
+# - Debian arch via DEB_GCC_TARGET or GCC_TARGET
+#
+# alias
+ifdef GCC_TARGET
+  DEB_GCC_TARGET := $(GCC_TARGET)
+endif
+ifdef DEB_TARGET_GNU_TYPE
+  TARGET_VARS := $(shell dpkg-architecture -f -t$(DEB_TARGET_GNU_TYPE) 2>/dev/null)
+else
+  # allow debian/target to be used instead of DEB_GCC_TARGET - this was requested
+  # by toolchain-source maintainer
+  DEBIAN_TARGET_FILE := $(strip $(if $(wildcard debian/target),$(shell cat debian/target 2>/dev/null)))
+  ifndef DEB_TARGET_ARCH
+    ifneq (,$(DEBIAN_TARGET_FILE))
+      DEB_TARGET_ARCH := $(DEBIAN_TARGET_FILE)
+    else
+      ifdef DEB_GCC_TARGET
+        DEB_TARGET_ARCH := $(DEB_GCC_TARGET)
+      else
+        DEB_TARGET_ARCH := $(DEB_HOST_ARCH)
+      endif
+    endif
+  endif
+  TARGET_VARS := $(shell dpkg-architecture -f -a$(DEB_TARGET_ARCH) 2>/dev/null)
+endif
+ifeq ($(dpkg_target_vars),yes)
+  TARGET_VARS		:= $(filter-out DEB_TARGET_%, $(TARGET_VARS))
+endif
+
+DEB_TARGET_ARCH		:= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH)
+DEB_TARGET_ARCH_OS	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH_OS)
+DEB_TARGET_ARCH_CPU	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH_CPU)
+DEB_TARGET_GNU_CPU	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_CPU)
+DEB_TARGET_GNU_TYPE	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_TYPE)
+DEB_TARGET_GNU_SYSTEM	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_SYSTEM)
+DEB_TARGET_MULTIARCH	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_MULTIARCH)
+
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper lucid))
+    ifeq ($(DEB_TARGET_GNU_TYPE),i486-linux-gnu)
+      DEB_TARGET_GNU_TYPE = i586-linux-gnu
+    endif
+  endif
+else
+  ifneq (,$(filter $(distrelease),stretch sid))
+    DEB_TARGET_GNU_TYPE := $(subst i586,i686,$(DEB_TARGET_GNU_TYPE))
+    i586_symlinks = $(if $(findstring i686,$(DEB_TARGET_GNU_TYPE)),yes)
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH),)
+  $(error Invalid architecure.)
+endif
+
+# Force this, people get confused about the default. See #760770.
+override with_deps_on_target_arch_pkgs :=
+
+# including unversiond symlinks for binaries
+#with_unversioned = yes
+
+# ---------------------------------------------------------------------------
+# cross-compiler config
+ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
+  ifneq ($(DEB_HOST_GNU_TYPE),$(DEB_TARGET_GNU_TYPE))
+    # cross building a cross compiler, untested.
+    DEB_CROSS = yes
+    build_type = cross-build-cross
+  else
+    # cross building the native compiler
+    ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid))
+      with_sysroot = /
+    endif
+    build_type = cross-build-native
+  endif
+else
+  ifneq ($(DEB_HOST_GNU_TYPE),$(DEB_TARGET_GNU_TYPE))
+    # cross compiler, sets WITH_SYSROOT on it's own
+    DEB_CROSS = yes
+    build_type = build-cross
+  else
+    # native build
+    # first ones are wheezy and maverick
+    ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid))
+      with_sysroot = /
+    endif
+    build_type = build-native
+  endif
+endif
+
+# ---------------------------------------------------------------------------
+# cross compiler support
+ifeq ($(DEB_CROSS),yes)
+  # TARGET: Alias to DEB_TARGET_ARCH (Debian arch name)
+  # TP: Target Prefix. Used primarily as a prefix for cross tool
+  #     names (e.g. powerpc-linux-gcc).
+  # TS: Target Suffix. Used primarily at the end of cross compiler
+  #     package names (e.g. gcc-powerpc).
+  # LS: Library Suffix. Used primarily at the end of cross compiler
+  #     library package names (e.g. libgcc-powerpc-cross).
+  # AQ: Arch Qualifier. Used for cross-arch dependencies
+  DEB_TARGET_ALIAS ?= $(DEB_TARGET_GNU_TYPE)
+  TARGET := $(DEB_TARGET_ARCH)
+  TP :=  $(subst _,-,$(DEB_TARGET_GNU_TYPE))-
+  TS := -$(subst _,-,$(DEB_TARGET_ALIAS))
+  LS := -$(subst _,-,$(DEB_TARGET_ARCH))-cross
+  AQ :=
+
+  cross_bin_arch := -$(subst _,-,$(DEB_TARGET_ALIAS))
+  cross_lib_arch := -$(subst _,-,$(DEB_TARGET_ARCH))-cross
+  cmd_prefix := $(DEB_TARGET_GNU_TYPE)-
+
+  TARGET_ALIAS := $(DEB_TARGET_ALIAS)
+
+  lib_binaries := indep_binaries
+  cross_shlibdeps =  DEB_HOST_ARCH=$(TARGET) ARCH=$(DEB_TARGET_ARCH) MAKEFLAGS="CC=something"
+  cross_gencontrol = DEB_HOST_ARCH=$(TARGET)
+  cross_makeshlibs = DEB_HOST_ARCH=$(TARGET)
+  cross_clean = DEB_HOST_ARCH=$(TARGET)
+else
+  TARGET_ALIAS := $(DEB_TARGET_GNU_TYPE)
+
+  ifeq ($(TARGET_ALIAS),i386-gnu)
+    TARGET_ALIAS := i586-gnu
+  endif
+
+  ifeq ($(single_package),yes)
+    cmd_prefix :=
+    unprefixed_names :=
+  else
+    cmd_prefix := $(DEB_TARGET_GNU_TYPE)-
+    unprefixed_names := yes
+  endif
+
+  #ifeq ($(TARGET_ALIAS),i486-linux-gnu)
+  #  TARGET_ALIAS := i686-linux-gnu
+  #endif
+
+  TARGET_ALIAS := $(subst i386,i486,$(TARGET_ALIAS))
+
+  # configure as linux-gnu, not linux
+  #ifeq ($(findstring linux,$(TARGET_ALIAS))/$(findstring linux-gnu,$(TARGET_ALIAS)),linux/)
+  #  TARGET_ALIAS := $(TARGET_ALIAS)-gnu
+  #endif
+
+  # configure as linux, not linux-gnu
+  #TARGET_ALIAS := $(subst linux-gnu,linux,$(TARGET_ALIAS))
+
+  lib_binaries := arch_binaries
+  cross_shlibdeps :=
+  cross_gencontrol :=
+  cross_makeshlibs :=
+  cross_clean :=
+endif
+
+printarch:
+	@echo DEB_TARGET_ARCH: $(DEB_TARGET_ARCH)
+	@echo DEB_TARGET_ARCH_OS: $(DEB_TARGET_ARCH_OS)
+	@echo DEB_TARGET_ARCH_CPU: $(DEB_TARGET_ARCH_CPU)
+	@echo DEB_TARGET_GNU_SYSTEM: $(DEB_TARGET_GNU_SYSTEM)
+	@echo DEB_TARGET_MULTIARCH: $(DEB_TARGET_MULTIARCH)
+	@echo MULTIARCH_CONFARG: $(MULTIARCH_CONFARG)
+	@echo TARGET_ALIAS: $(TARGET_ALIAS)
+	@echo TP: $(TP)
+	@echo TS: $(TS)
+
+# -------------------------------------------------------------------
+# bootstrap options
+ifdef WITH_BOOTSTRAP
+  # "yes" is the default and causes a 3-stage bootstrap.
+  # "off" runs a complete build with --disable-bootstrap
+  # "no" means to just build the first stage, and not create the stage1
+  # directory.
+  # "lean" means a lean 3-stage bootstrap, i.e. delete each stage when no
+  # longer needed.
+  with_bootstrap = $(WITH_BOOTSTRAP)
+endif
+ifneq ($(findstring nostrap, $(DEB_BUILD_OPTIONS)),)
+  with_bootstrap := off
+endif
+
+ifneq ($(findstring gccdebug, $(DEB_BUILD_OPTIONS)),)
+  with_bootstrap := off
+  DEB_BUILD_OPTIONS := $(DEB_BUILD_OPTIONS) nostrip
+  export DEB_BUILD_OPTIONS
+endif
+
+# -------------------------------------------------------------------
+# stage options
+ifdef DEB_STAGE
+  with_cdev := yes
+  separate_lang := yes
+  # "stage1" is minimal compiler with static libgcc
+  # "stage2" is minimal compiler with shared libgcc
+  # "rtlibs" is a subset of target libraries, without compilers
+  ifeq ($(DEB_STAGE),stage1)
+    with_shared_libgcc := no
+  endif
+  ifeq ($(DEB_STAGE),stage2)
+    with_libgcc := yes
+    with_shared_libgcc := yes
+  endif
+  ifeq ($(DEB_STAGE),rtlibs)
+    with_rtlibs := libgcc libgomp libstdc++ libgfortran libquadmath
+    ifeq ($(DEB_CROSS),yes)
+      LS :=
+      TS :=
+      cross_lib_arch :=
+    endif
+  endif
+endif
+
+ifeq ($(BACKPORT),true)
+  with_dev := no
+  with_source := yes
+  with_base_only := yes
+endif
+
+# -------------------------------------------------------------------
+# sysroot options
+ifdef WITH_SYSROOT
+  with_sysroot = $(WITH_SYSROOT)
+endif
+ifdef WITH_BUILD_SYSROOT
+  with_build_sysroot = $(WITH_BUILD_SYSROOT)
+endif
+
+# -------------------------------------------------------------------
+# for components configuration
+
+COMMA = ,
+SPACE = $(EMPTY) $(EMPTY)
+
+# lang= overwrites all of nolang=, overwrites all of WITHOUT_LANG
+
+DEB_LANG_OPT	:= $(filter lang=%,$(DEB_BUILD_OPTIONS))
+DEB_LANG	:= $(strip $(subst $(COMMA), ,$(patsubst lang=%,%,$(DEB_LANG_OPT))))
+DEB_NOLANG_OPT	:= $(filter nolang=%,$(DEB_BUILD_OPTIONS))
+DEB_NOLANG	:= $(strip $(subst $(COMMA), ,$(patsubst nolang=%,%,$(DEB_NOLANG_OPT))))
+lfilt	= $(strip $(if $(DEB_LANG), \
+		$(if $(filter $(1) $(2),$(DEB_LANG)),yes),$(3)))
+nlfilt	= $(strip $(if $(DEB_NOLANG), \
+		$(if $(filter $(1) $(2),$(DEB_NOLANG)),disabled by $(DEB_NOLANG_OPT),$(3))))
+wlfilt	= $(strip $(if $(filter $(1) $(2), $(subst $(COMMA), ,$(WITHOUT_LANG))), \
+		disabled by WITHOUT_LANG=$(WITHOUT_LANG),$(3)))
+envfilt	= $(strip $(or $(call lfilt,$(1),$(2)),$(call nlfilt,$(1),$(3)),$(call wlfilt,$(1),$(3)),$(4)))
+
+# -------------------------------------------------------------------
+# architecture specific config
+
+# FIXME: libjava is not ported for thumb, this hack only works for
+# separate gcj builds
+ifeq (,$(findstring gcj,$(PKGSOURCE)))
+  ifeq ($(DEB_TARGET_ARCH),armhf)
+    ifeq ($(distribution),Raspbian)
+      with_arm_thumb := no
+    else
+      with_arm_thumb := yes
+    endif
+  else
+    ifeq ($(derivative)-$(DEB_TARGET_ARCH),Ubuntu-armel)
+      ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+        with_arm_thumb := yes
+      endif
+    endif
+  endif
+endif
+
+# build using fsf or linaro
+ifeq ($(distribution),Ubuntu)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64 armel armhf))
+    with_linaro_branch = yes
+  endif
+endif
+
+# build using fsf or the ibm branch
+ifeq ($(distribution),Ubuntu)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),ppc64el))
+    #with_ibm_branch = yes
+  endif
+endif
+
+ifneq (,$(findstring gcc-snapshot, $(PKGSOURCE)))
+  with_linaro_branch =
+  with_ibm_branch =
+else ifneq (,$(findstring gcc-linaro, $(PKGSOURCE)))
+  with_ibm_branch =
+endif
+
+# check if we're building for armel or armhf
+ifneq (,$(filter %eabihf,$(DEB_TARGET_GNU_SYSTEM)))
+  float_abi := hard
+else ifneq (,$(filter $(distribution)-$(DEB_TARGET_ARCH), Ubuntu-armel))
+  ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+    float_abi := softfp
+  else
+    float_abi := soft
+  endif
+else ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel))
+  float_abi := soft
+endif
+
+# -------------------------------------------------------------------
+# basic config
+
+# allows to wrote backtraces for ICEs
+#unstripped_exe = yes
+
+# common things ---------------
+# build common packages, where package names don't differ in different
+# gcc versions (fixincludes, libgcj-common) ...
+with_common_pkgs := yes
+# ... and some libraries, which do not change (libgcc1, libssp0).
+with_common_libs := yes
+# XXX: should with_common_libs be "yes" only if this is the default compiler
+# version on the targeted arch?
+
+# is this a multiarch-enabled build?
+ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick))
+  with_multiarch_lib := yes
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  ifneq ($(single_package),yes)
+    ifneq ($(DEB_CROSS),yes)
+      with_multiarch_cxxheaders := yes
+    endif
+  endif
+endif
+
+ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick))
+  multiarch_stage1 := yes
+endif
+
+# mapping for the non-default biarch multilib / multiarch names
+multiarch_xarch_map = \
+	amd64=i386-linux-gnu,x86_64-linux-gnux32 \
+	armel=arm-linux-gnueabi \
+	armhf=arm-linux-gnueabihf \
+	i386=x86_64-linux-gnu,x86_64-linux-gnux32 \
+	powerpc=powerpc64-linux-gnu \
+	ppc64=powerpc-linux-gnu \
+	sparc=sparc64-linux-gnu \
+	sparc64=sparc-linux-gnu \
+	s390=s390x-linux-gnu \
+	s390x=s390-linux-gnu \
+	mips=mips64-linux-gnuabin32,mips64-linux-gnuabi64 \
+	mipsel=mips64el-linux-gnuabin32,mips64el-linux-gnuabi64 \
+	mipsn32=mips-linux-gnu,mips64-linux-gnuabi64 \
+	mipsn32el=mipsel-linux-gnu,mips64el-linux-gnuabi64 \
+	mips64=mips-linux-gnu,mips64-linux-gnuabin32 \
+	mips64el=mipsel-linux-gnu,mips64el-linux-gnuabin32 \
+	x32=x86_64-linux-gnu,i386-linux-gnu \
+	kfreebsd-amd64=i386-kfreebsd-gnu
+xarch_multiarch_names = $(subst $(COMMA),$(SPACE),$(patsubst $(DEB_TARGET_ARCH)=%,%, \
+		$(filter $(DEB_TARGET_ARCH)=%,$(multiarch_xarch_map))))
+
+multilib_multiarch_map = \
+	$(DEB_TARGET_ARCH)/=$(DEB_TARGET_MULTIARCH) \
+	amd64/32=i386-linux-gnu \
+	amd64/x32=x86_64-linux-gnux32 \
+	armel/hf=arm-linux-gnueabihf \
+	armhf/sf=arm-linux-gnueabi \
+	i386/64=x86_64-linux-gnu \
+	i386/x32=x86_64-linux-gnux32 \
+	powerpc/64=powerpc64-linux-gnu \
+	ppc64/32=powerpc-linux-gnu \
+	sparc/64=sparc64-linux-gnu \
+	sparc64/32=sparc-linux-gnu \
+	s390/64=s390x-linux-gnu \
+	s390x/32=s390-linux-gnu \
+	mips/n32=mips64-linux-gnuabin32 \
+	mips/64=mips64-linux-gnuabi64 \
+	mipsel/n32=mips64el-linux-gnuabin32 \
+	mipsel/64=mips64el-linux-gnuabi64 \
+	mipsn32/32=mips-linux-gnu \
+	mipsn32/64=mips64-linux-gnuabi64 \
+	mipsn32el/32=mipsel-linux-gnu \
+	mipsn32el/64=mips64el-linux-gnuabi64 \
+	mips64/32=mips-linux-gnu \
+	mips64/n32=mips64-linux-gnuabin32 \
+	mips64el/32=mipsel-linux-gnu \
+	mips64el/n32=mips64el-linux-gnuabin32 \
+	x32/32=i386-linux-gnu \
+	x32/64=x86_64-linux-gnu \
+	kfreebsd-amd64/32=i386-kfreebsd-gnu
+# $(call mlib_to_march,<empty>|32|64|n32|x32|hf|sf)
+mlib_to_march = $(patsubst $(DEB_TARGET_ARCH)/$(1)=%,%, \
+		   $(filter $(DEB_TARGET_ARCH)/$(1)=%,$(multilib_multiarch_map)))
+
+multilib_arch_map = \
+	$(DEB_TARGET_ARCH)/=$(DEB_TARGET_ARCH) \
+	amd64/32=i386 \
+	amd64/x32=x32 \
+	armel/hf=armhf \
+	armhf/sf=armel \
+	i386/64=amd64 \
+	i386/x32=x32 \
+	powerpc/64=ppc64 \
+	ppc64/32=powerpc \
+	sparc/64=sparc64 \
+	sparc64/32=sparc \
+	s390/64=s390x \
+	s390x/32=s390 \
+	mips/n32=mipsn32 \
+	mips/64=mips64 \
+	mipsel/n32=mipsn32el \
+	mipsel/64=mips64el \
+	mipsn32/32=mips \
+	mipsn32/64=mips64 \
+	mipsn32el/32=mipsel \
+	mipsn32el/64=mips64el \
+	mips64/32=mips \
+	mips64/n32=mipsn32 \
+	mips64el/32=mipsel \
+	mips64el/n32=mipsn32el \
+	x32/32=i386 \
+	x32/64=amd64 \
+	kfreebsd-amd64/32=kfreebsd-i386
+# $(call mlib_to_arch,<empty>|32|64|n32|x32|hf|sf)
+mlib_to_arch = $(patsubst $(DEB_TARGET_ARCH)/$(1)=%,%, \
+		   $(filter $(DEB_TARGET_ARCH)/$(1)=%,$(multilib_arch_map)))
+
+# build -base packages
+with_gccbase := yes
+ifeq ($(build_type),build-cross)
+  ifneq ($(DEB_STAGE),rtlibs)
+    with_gcclbase := yes
+  endif
+endif
+
+# build dev packages.
+ifneq ($(DEB_STAGE),rtlibs)
+  with_dev := yes
+endif
+
+with_cpp := yes
+
+# set lang when built from a different source package.
+separate_lang := no
+
+#no_dummy_cpus := ia64 i386 hppa s390 sparc
+#ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(no_dummy_cpus)))
+#  with_base_only	:= no
+#  with_common_libs	:= yes
+#  with_common_pkgs	:= yes
+#else
+#  with_base_only	:= yes
+#  with_common_libs	:= no
+#  with_common_pkgs	:= no
+#  with_dev		:= no
+#endif
+
+ifeq ($(versioned_packages),yes)
+  pkg_ver := -$(BASE_VERSION)
+  PV := $(pkg_ver)
+endif
+
+# -------------------------------------------------------------------
+# configure languages
+
+# C ---------------------------
+enabled_languages := c
+
+with_jit = yes
+
+# FIXME: compiler bug
+jit_no_cpus	:= ia64
+
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(jit_no_cpus)))
+  with_jit := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(with_rtlibs))
+  with_jit := disabled for rtlibs stage
+endif
+with_jit := $(call envfilt, jit, , , $(with_jit))
+
+ifeq (,$(findstring gcc-,$(PKGSOURCE)))
+  with_jit :=
+endif
+
+ifneq (,$(findstring build-cross, $(build_type)))
+  with_jit := disabled for cross builds
+endif
+
+ifeq ($(with_jit),yes)
+    ifeq ($(with_common_libs),yes)
+      with_libgccjit := yes
+    endif
+endif
+
+with_cc1 := yes
+with_cc1 := $(call envfilt, cc1, , , $(with_cc1))
+
+ifeq ($(with_cc1),yes)
+  ifeq ($(with_common_libs),yes)
+    with_libcc1 := yes
+  endif
+  with_libcc1_plugin := yes
+endif
+
+ifneq (,$(with_rtlibs))
+  with_libcc1 := disabled for rtlibs stage
+  with_libcc1_plugin := disabled for rtlibs stage
+endif
+ifneq (,$(findstring build-cross, $(build_type)))
+  with_libcc1 := disabled for cross builds
+endif
+
+# Build all packages needed for C development
+ifneq ($(with_base_only),yes)
+  ifeq ($(with_dev),yes)
+    with_cdev := yes
+  endif
+endif
+
+ifeq (,$(filter $(DEB_STAGE),stage1 stage2))
+# Ada --------------------
+ada_no_cpus	:= m32r sh3 sh3eb sh4eb
+# no Debian builds ... some of these should exist
+ada_no_cpus += powerpcspe
+ada_no_cpus += m68k # see https://bugs.debian.org/814221
+ada_no_cpus += mips64 # see https://gcc.gnu.org/PR65337
+ada_no_cpus += x32 # see https://gcc.gnu.org/PR61954
+ada_no_systems	:= 
+ada_no_cross	:= no
+ada_no_snap	:= no
+ifeq ($(single_package),yes)
+  ada_no_cpus += powerpcspe
+  ifneq (,$(filter $(DEB_TARGET_ARCH),mips mipsel powerpcspe kfreebsd-i386 kfreebsd-amd64))
+    #ada_no_cpus += mips mipsel
+    ada_no_cpus += kfreebsd-i386 kfreebsd-amd64
+    ada_no_snap := yes
+  endif
+endif
+
+ifeq ($(with_dev),yes)
+  ifneq ($(separate_lang),yes)
+    with_ada := yes
+  endif
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(ada_no_cpus)))
+  with_ada := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH),powerpcspe x32))
+  with_ada := disabled for architecture $(DEB_TARGET_ARCH)
+endif
+ifneq (,$(findstring cross,$(build_type)))
+  ifneq (,$(filter $(DEB_BUILD_ARCH),powerpcspe x32))
+    with_ada := no gnat host compiler on $(DEB_BUILD_ARCH)
+  endif
+endif
+ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(ada_no_systems)))
+  with_ada := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(ada_no_cross)-$(DEB_CROSS),yes-yes)
+  with_ada := disabled for cross compiler package
+endif
+ifeq ($(ada_no_snap)-$(single_package),yes-yes)
+  with_ada := disabled for snapshot build
+endif
+ifneq (,$(findstring gccgo,$(PKGSOURCE)))
+  with_ada :=
+endif
+ifneq (,$(filter $(distrelease),lucid))
+  with_ada :=
+endif
+# disable building gnat cross compilers on 32bit archs targeting 64bit archs
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  ifneq (,$(filter $(DEB_HOST_ARCH), armhf armel i386 mips mipsel powerpc))
+    ifneq (,$(filter $(DEB_TARGET_ARCH), alpha amd64 arm64 mips64 mips64el ppc64 ppc64el s390x sparc64))
+      with_ada := disabled on 32bit archs targeting 64bit archs
+    endif
+  endif
+endif
+with_ada := $(call envfilt, ada, , , $(with_ada))
+
+#with_ada := disabled for GCC 6
+
+ifeq ($(DEB_STAGE)-$(filter libgnat, $(with_rtlibs)),rtlibs-)
+  with_ada := disabled for rtlibs stage
+endif
+
+#ifneq ($(single_package),yes)
+#  with_separate_gnat := yes
+#endif
+
+ifneq ($(with_separate_gnat),yes)
+  ifeq ($(with_ada),yes)
+    ifneq (,$(filter $(distrelease),squeeze lucid))
+      with_ada :=
+    endif
+  endif
+endif
+
+ifeq ($(with_ada)-$(with_separate_gnat),yes-yes)
+  ifneq (,$(findstring gnat,$(PKGSOURCE)))
+    languages := c
+    separate_lang := yes
+    with_mudflap := no
+    with_gccbase := no
+    with_cdev := no
+    with_cc1 := no
+    with_libcc1 := no
+  else
+    debian_extra_langs += ada
+    with_ada := built from separate source
+    with_libgnat := built from separate source
+  endif
+endif
+
+ifeq ($(with_ada),yes)
+  enabled_languages += ada
+  with_libgnat := yes
+  with_gnatsjlj := yes
+endif
+
+# C++ -------------------------
+cxx_no_cpus := avr
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_cxx := yes
+  endif
+endif
+ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(cxx_no_cpus)))
+  with_cxx := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+with_cxx := $(call envfilt, c++, obj-c++ java, , $(with_cxx))
+
+# Set the default libstdc++ ABI. libstdc++ provides both ABI's.
+# Existing code still runs with the new c++11 ABI, however link
+# errors are seen when one object is compiled with the new std::string in scope,
+# another object is compiled with the old std::string in scope. both can link
+# to libstdc++.so but not to each other.
+# two objects (which might be some system library and a user's program) need to
+# agree on the version of std::string they're using
+
+libstdcxx_abi = new
+# backports default to the old ABI
+ifneq (,$(filter $(distrelease),squeeze wheezy jessie lucid precise trusty utopic vivid))
+  libstdcxx_abi = gcc4-compatible
+endif
+
+# Build all packages needed for C++ development
+ifeq ($(with_cxx),yes)
+  ifeq ($(with_dev),yes)
+    with_cxxdev := yes
+    with_libcxxdbg := yes
+  endif
+  ifeq ($(with_common_libs),yes)
+    with_libcxx := yes
+  endif
+
+  # debugging versions of libstdc++
+  ifneq (,$(findstring gcc-, $(PKGSOURCE)))
+  ifeq ($(with_cxxdev),yes)
+    with_cxx_debug := yes
+    debug_no_cpus :=
+    ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(debug_no_cpus)))
+      with_cxx_debug := disabled for cpu $(DEB_TARGET_GNU_CPU)
+    endif
+  endif
+  endif
+  with_cxx_debug := $(call envfilt, debug, , , $(with_cxx_debug))
+
+  enabled_languages += c++
+endif
+
+# Java --------------------
+# - To build a standalone gcj package (with no corresponding gcc
+#   package): with_separate_libgcj=yes, with_standalone_gcj=yes
+# - To build the java packages from the gcc source package:
+#   with_separate_libgcj=no, with_standalone_gcj=no
+# - To build gcc and java from separate sources:
+#   with_separate_libgcj=yes, with_standalone_gcj=no
+
+java_no_cpus := # arm64 mips mipsel
+java_no_systems :=
+
+ifneq ($(single_package),yes)
+  with_separate_libgcj := yes
+endif
+with_separate_libgcj := no
+with_standalone_gcj := no
+
+ifneq ($(separate_lang),yes)
+  with_java := yes
+endif
+
+# java converted for V3 C++ ABI for some archs
+ifeq ($(with_base_only),yes)
+  with_java := no
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(java_no_cpus)))
+  with_java := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(filter $(DEB_TARGET_GNU_SYSTEM),$(java_no_systems)))
+  with_java := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(java_no_cross)-$(DEB_CROSS),yes-yes)
+  with_java := disabled for cross compiler package
+endif
+with_java := $(call envfilt, java, , c++, $(with_java))
+
+ifeq ($(DEB_STAGE)-$(filter libgcj, $(with_rtlibs)),rtlibs-)
+  with_java := disabled for rtlibs stage
+endif
+
+ifneq (,$(findstring gccgo, $(PKGSOURCE)))
+  with_java :=
+endif
+
+ifeq ($(with_java)-$(with_separate_libgcj),yes-yes)
+  ifneq (,$(findstring gcj, $(PKGSOURCE)))
+    languages := c c++
+    separate_lang := yes
+  else
+    debian_extra_langs += java
+    with_java := built from separate source
+    with_gcj := built from separate source
+    with_libgcj := buit from separate source
+  endif
+endif
+
+with_java_plugin := no
+
+ifeq ($(with_java),yes)
+  # use the same names as OpenJDK
+  java_cpu_map = armel=arm armhf=arm arm64=aarch64 hppa=parisc \
+	i686=i386 i586=i386 i486=i386 x32=x32 \
+	mipsel=mips mips64=mips mips64el=mips mipsn32=mips mipsn32el=mips \
+	powerpc=ppc ppc64el=ppc64le sh4=sh x32=x32
+  java_cpu = $(patsubst $(DEB_TARGET_ARCH_CPU)=%,%, \
+                         $(filter $(DEB_TARGET_ARCH_CPU)=%,$(java_cpu_map)))
+  ifeq (,$(java_cpu))
+    java_cpu = $(DEB_TARGET_ARCH_CPU)
+  endif
+  java_priority = 10$(subst .,,$(BASE_VERSION))0
+
+  with_libgcj := yes
+  with_libgcjbc := no
+
+  ifneq (,$(findstring gcj-4,$(PKGSOURCE)))
+    ifneq (,$(filter $(DEB_TARGET_ARCH), arm))
+      with_gcj_base_only := yes
+    endif
+  endif
+
+  ifeq ($(single_package),yes)
+    with_ecj := yes
+  endif
+
+  #ifneq (,$(filter $(DEB_TARGET_ARCH),hppa))
+  #  with_native_ecj := yes
+  #endif
+
+  ifneq (,$(filter $(DEB_TARGET_ARCH),arm armel))
+    with_external_ecj1 := yes
+  endif
+  ifeq (,$(filter $(distrelease),squeeze wheezy jessie lucid precise trusty xenial))
+    # not yet built ...
+    ifeq (,$(filter $(DEB_TARGET_ARCH),powerpcspe sh4))
+      with_external_ecj1 := yes
+    endif
+    with_external_ecj1 := yes
+  endif
+
+  with_java_maintainer_mode := no
+
+  # used as well in debian/rules.conf to determine the build deps
+  java_awt_peers = gtk # qt # xlib
+
+  with_libgcj_doc := yes
+
+  # Build all packages needed for Java development (gcj, libgcj-dev)
+  ifeq ($(with_dev),yes)
+    with_javadev := yes
+    with_gcj := yes
+  endif
+
+  with_java_alsa := yes
+  ifeq (,$(filter $(DEB_TARGET_GNU_SYSTEM),linux-gnu))
+    with_java_alsa := no
+  endif
+
+  # Just build the cross compiler to be able to cross build a native build.
+  ifeq ($(DEB_CROSS),yes)
+    with_libgcj :=
+  endif
+
+  enabled_languages += java
+endif
+
+# Go -------------------
+# - To build a standalone gccgo package (with no corresponding gcc
+#   package): with_separate_libgo=yes, with_standalone_go=yes
+# - To build the go packages from the gcc source package:
+#   with_separate_libgo=no, with_standalone_go=no
+# - To build gcc and go from separate sources:
+#   with_separate_libgo=yes, with_standalone_go=no
+
+go_no_cross := yes
+go_no_cross := no
+
+ifneq (,$(findstring gccgo, $(PKGSOURCE)))
+  with_separate_libgo := yes
+  with_standalone_go := yes
+  with_cc1 :=
+  with_libcc1 :=
+endif
+
+go_no_cpus := avr arm hppa sh4
+ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick natty oneiric))
+  go_no_cpus := $(filter-out arm, $(go_no_cpus))
+endif
+go_no_systems := kfreebsd
+
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_go := yes
+  endif
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(go_no_cpus)))
+  with_go := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(findstring $(DEB_TARGET_ARCH_OS),$(go_no_systems)))
+  with_go := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(go_no_cross)-$(DEB_CROSS),yes-yes)
+  with_go := disabled for cross compiler package
+endif
+ifeq ($(DEB_STAGE)-$(filter libgo, $(with_rtlibs)),rtlibs-)
+  with_go := disabled for rtlibs stage
+endif
+with_go := $(call envfilt, go, , , $(with_go))
+
+# Build all packages needed for Go development
+ifneq (,$(findstring gcc, $(PKGSOURCE)))
+  ifeq ($(with_go),yes)
+    ifeq ($(with_common_libs),yes)
+      with_libgo := yes
+    endif
+    enabled_languages += go
+  endif
+endif
+
+ifeq ($(with_go)-$(with_separate_libgo),yes-yes)
+  ifneq (,$(findstring gccgo, $(PKGSOURCE)))
+    languages := c c++ go
+    separate_lang := yes
+    with_libgcc := yes
+    with_shared_libgcc := yes
+  else
+    debian_extra_langs += go
+    with_go := built from separate source
+    with_libgo := buit from separate source
+  endif
+endif
+
+# D ---------------------------
+d_no_cross := yes
+d_no_snap := yes
+d_no_cpus := s390
+
+ifneq ($(single_package),yes)
+  with_separate_gdc := yes
+endif
+with_separate_gdc := no
+
+ifneq ($(separate_lang),yes)
+  with_d := yes
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(d_no_cpus)))
+  with_d := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifeq ($(d_no_snap)-$(single_package),yes-yes)
+  with_d := disabled for snapshot build
+endif
+ifeq ($(DEB_STAGE)-$(filter libphobos, $(with_rtlibs)),rtlibs-)
+  with_d := disabled for rtlibs stage
+endif
+with_d := $(call envfilt, d, , , $(with_d))
+
+#with_d := not yet built for GCC 6
+
+ifeq ($(with_base_only),yes)
+  with_d := no
+endif
+
+ifeq ($(with_d)-$(with_separate_gdc),yes-yes)
+  ifneq (,$(findstring gdc,$(PKGSOURCE)))
+    languages := c c++
+    separate_lang := yes
+
+    # FIXME: language selection needs improvement.
+    with_go := disabled for d
+  else
+    debian_extra_langs += d
+    with_d := built from separate source
+  endif
+endif
+
+ifeq ($(with_d),yes)
+  libphobos_archs = amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+  ifneq (,$(filter $(DEB_TARGET_ARCH), $(libphobos_archs)))
+    with_libphobos := yes
+  endif
+
+  libphobos_no_cpus := alpha avr arm64 hppa ia64 m68k \
+	mips mipsel mips64 mips64el mipsn32 mipsn32el \
+	powerpc powerpcspe ppc64 s390 s390x sh4 sparc sparc64
+  libphobos_no_systems := gnu kfreebsd-gnu
+  ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(libphobos_no_cpus)))
+    with_libphobos := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+  endif
+  ifneq (,$(filter $(DEB_TARGET_GNU_SYSTEM),$(libphobos_no_systems)))
+    with_libphobos := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+  endif
+  with_libphobosdev := $(with_libphobos)
+
+  enabled_languages += d
+endif
+
+# Fortran 95 -------------------
+fortran_no_cross := yes
+fortran_no_cross := no
+
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_fortran := yes
+  endif
+endif
+ifeq ($(fortran_no_cross)-$(DEB_CROSS),yes-yes)
+  with_fortran := disabled for cross compiler package
+endif
+ifeq ($(DEB_STAGE)-$(filter libgfortran libquadmath, $(with_rtlibs)),rtlibs-)
+  with_fortran := disabled for rtlibs stage
+endif
+
+with_fortran := $(call envfilt, fortran, , , $(with_fortran))
+
+# Build all packages needed for Fortran development
+ifeq ($(with_fortran),yes)
+  ifeq ($(with_dev),yes)
+    ifneq ($(DEB_STAGE)-$(filter libgfortran libquadmath, $(with_rtlibs)),rtlibs-)
+      with_fdev := yes
+    endif
+  endif
+  with_libgfortran := yes
+  enabled_languages += fortran
+endif
+
+# libquadmath -------------------
+
+ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU), ia64 i386 i486 i586 i686 amd64))
+  # FIXME: upstream build tied to gfortran build
+  ifeq ($(with_fortran),yes)
+    with_qmath := yes
+    ifneq (,$(findstring gcc-6,$(PKGSOURCE)))
+      ifeq ($(with_common_libs),yes)
+        with_libqmath := yes
+      endif
+    endif
+  endif
+endif
+
+# ObjC ------------------------
+objc_no_cross := no
+
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_objc := yes
+    objc_no_archs =
+    ifneq (,$(filter $(DEB_TARGET_ARCH),$(objc_no_archs)))
+      with_objc :=
+    endif
+  endif
+endif
+ifeq ($(objc_no_cross)-$(DEB_CROSS),yes-yes)
+  with_objc := disabled for cross compiler package
+endif
+ifeq ($(DEB_STAGE)-$(filter libobjc, $(with_rtlibs)),rtlibs-)
+  with_objc := disabled for rtlibs stage
+endif
+with_objc := $(call envfilt, objc, obj-c++, , $(with_objc))
+
+ifeq ($(with_objc),yes)
+  # the ObjC runtime with garbage collection enabled needs the Boehm GC
+  with_objc_gc := yes
+
+  # disable ObjC garbage collection library (needs libgc)
+  libgc_no_cpus := arm64 avr mips mipsel # alpha amd64 arm armel armhf hppa i386 ia64 m68k mips mipsel powerpc ppc64 s390 s390x sparc
+  libgc_no_systems := knetbsd-gnu
+  ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(libgc_no_cpus)))
+    with_objc_gc := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+  endif
+  ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(libgc_no_systems)))
+    with_objc_gc := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+  endif
+
+  # Build all packages needed for Objective-C development
+  ifeq ($(with_dev),yes)
+    with_objcdev := yes
+  endif
+  ifeq ($(with_common_libs),yes)
+    with_libobjc := yes
+  endif
+
+  enabled_languages += objc
+endif
+
+# ObjC++ ----------------------
+objcxx_no_cross := no
+
+ifeq ($(with_objc),yes)
+  ifneq ($(with_base_only),yes)
+    ifneq ($(separate_lang),yes)
+      with_objcxx := yes
+    endif
+  endif
+endif
+ifeq ($(objcxx_no_cross)-$(DEB_CROSS),yes-yes)
+  with_objcxx := disabled for cross compiler package
+endif
+with_objcxx := $(call envfilt, obj-c++, , c++ objc, $(with_objcxx))
+
+ifeq ($(with_objcxx),yes)
+  enabled_languages += obj-c++
+endif
+
+# -------------------------------------------------------------------
+# other config
+
+# not built from the main source package
+ifeq (,$(findstring gcc-,$(PKGSOURCE)))
+  extra_package := yes
+endif
+
+with_nls := yes
+ifeq ($(trunk_build),yes)
+  with_nls := no
+endif
+with_nls := $(call envfilt, nls, , , $(with_nls))
+
+# powerpc nof libraries -----
+with_libnof := no
+
+ifneq (,$(findstring gcc-6,$(PKGSOURCE)))
+  ifeq (,$(with_rtlibs))
+    with_source := yes
+  endif
+endif
+with_source := $(call envfilt, source, , , $(with_source))
+
+ifeq ($(with_cdev),yes)
+
+# ssp & libssp -------------------------
+with_ssp := yes
+ssp_no_archs = alpha hppa ia64 m68k
+ifneq (, $(filter $(DEB_TARGET_ARCH),$(ssp_no_archs) $(ssp_no_archs:%=uclibc-%)))
+  with_ssp := not available on $(DEB_TARGET_ARCH)
+endif
+with_ssp := $(call envfilt, ssp, , , $(with_ssp))
+
+ifeq ($(with_ssp),yes)
+  ifneq ($(derivative),Debian)
+    ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+      with_ssp_default := yes
+    endif
+  endif
+endif
+
+# gomp --------------------
+with_gomp := yes
+with_gomp := $(call envfilt, gomp, , , $(with_gomp))
+gomp_no_archs =
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(gomp_no_archs)))
+  with_gomp :=
+endif
+
+# itm --------------------
+itm_archs = alpha amd64 arm64 i386 x32 ppc64 ppc64el s390x sh4 sparc64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(itm_archs)))
+  with_itm := yes
+endif
+with_itm := $(call envfilt, itm, , , $(with_itm))
+
+# atomic --------------------
+with_atomic := yes
+atomic_no_archs =
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(atomic_no_archs)))
+  with_atomic :=
+endif
+
+# backtrace --------------------
+with_backtrace := yes
+backtrace_no_archs = m68k
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(backtrace_no_archs)))
+  with_backtrace :=
+endif
+
+# asan / sanitizer --------------------
+with_asan :=
+with_asan := $(call envfilt, asan, , , $(with_asan))
+asan_archs = amd64 armel armhf arm64 i386 powerpc ppc64 ppc64el x32 sparc sparc64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(asan_archs)))
+  with_asan := yes
+endif
+
+# lsan / sanitizer --------------------
+with_lsan :=
+with_lsan := $(call envfilt, lsan, , , $(with_lsan))
+lsan_archs = amd64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(lsan_archs)))
+  with_lsan := yes
+endif
+
+# tsan / sanitizer --------------------
+with_tsan :=
+with_tsan := $(call envfilt, tsan, , , $(with_tsan))
+tsan_archs = amd64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(tsan_archs)))
+  with_tsan := yes
+endif
+
+endif # with_cdev
+
+# ubsan / sanitizer --------------------
+with_ubsan :=
+with_ubsan := $(call envfilt, ubsan, , , $(with_ubsan))
+ubsan_archs = amd64 armel armhf arm64 i386 powerpc ppc64 ppc64el x32 sparc sparc64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(ubsan_archs)))
+  with_ubsan := yes
+endif
+
+# libvtv --------------------
+with_vtv :=
+with_vtv := $(call envfilt, vtv, , , $(with_vtv))
+vtv_archs = amd64 i386 x32
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(vtv_archs)))
+  with_vtv := yes
+  with_libvtv := yes
+endif
+# libvtv builds a modified libstdc++, don't enable it by default
+with_vtv :=
+with_libvtv :=
+
+# libcilkrts --------------------
+with_cilkrts :=
+with_cilkrts := $(call envfilt, cilkrts, , , $(with_cilkrts))
+cilkrts_archs = amd64 i386 x32
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(cilkrts_archs)))
+  with_cilkrts := yes
+endif
+
+# libmpx --------------------
+with_mpx :=
+with_mpx := $(call envfilt, mpx, , , $(with_mpx))
+mpx_archs = amd64 i386
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(mpx_archs)))
+  # requires newer binutils, or else libmpxwrappers isn't built
+  ifeq (,$(filter $(distrelease),squeeze lucid precise))
+    with_mpx := yes
+    ifneq (,$(findstring gcc-, $(PKGSOURCE)))
+      with_libmpx := yes
+    endif
+  endif
+endif
+
+# pie by default --------------------
+with_pie :=
+ifeq ($(distribution),Debian)
+  ifeq (,$(filter $(distrelease),wheezy squeeze jessie))
+    pie_archs = amd64 arm64 armel armhf i386 mips mipsel mips64el \
+		ppc64el s390x sparc sparc64 kfreebsd-amd64 kfreebsd-i386
+  endif
+else ifeq ($(distribution),Ubuntu)
+  ifeq (,$(filter $(distrelease),lucid precise trusty utopic vivid wily))
+    pie_archs = s390x
+  endif
+  ifeq (,$(filter $(distrelease),lucid precise trusty utopic vivid wily xenial))
+    pie_archs += amd64 ppc64el
+  endif
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(pie_archs)))
+  with_pie := yes
+endif
+
+# gold --------------------
+# armel with binutils 2.20.51 only
+gold_archs = amd64 armel armhf i386 powerpc powerpcspe ppc64 ppc64el sparc sparc64 x32 hurd-i386
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(gold_archs)))
+  with_gold := yes
+endif
+
+# plugins --------------------
+with_plugins := yes
+ifneq (,$(with_rtlibs))
+  with_plugins := disabled for rtlibs stage
+endif
+
+endif # ifeq (,$(filter $(DEB_STAGE),stage1 stage2))
+
+# Don't include docs with GFDL invariant sections
+GFDL_INVARIANT_FREE := yes
+ifeq ($(derivative),Ubuntu)
+  GFDL_INVARIANT_FREE := no
+endif
+
+# -------------------------------------------------------------------
+# non-extra config
+ifeq ($(extra_package),yes)
+  ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),yes-no)
+    # package stuff
+    with_gccbase := no
+    with_cdev := no
+    with_cxx := no
+    with_cxxdev := no
+
+    ifneq ($(DEB_CROSS),yes)
+      with_gcjbase := yes
+    else
+      with_gcjxbase := yes
+    endif
+  endif
+  ifeq ($(with_separate_libgo),yes)
+    # package stuff
+    with_gccbase := yes
+    with_cdev := no
+    with_cxx := no
+    with_cxxdev := no
+  endif
+else
+  # libssp ------------------
+  ifeq ($(with_ssp)-$(with_common_libs),yes-yes)
+    #ifneq ($(DEB_CROSS),yes)
+      with_libssp := $(if $(wildcard $(builddir)/gcc/auto-host.h),$(shell if grep -qs '^\#define TARGET_LIBC_PROVIDES_SSP 1' $(builddir)/gcc/auto-host.h; then echo 'libc provides ssp'; else echo 'yes'; fi))
+    #endif
+    with_libssp := libc provides ssp
+  endif
+
+  # libgomp -----------------
+  ifeq ($(with_gomp)-$(with_common_libs),yes-yes)
+      with_libgomp := yes
+  endif
+
+  # libitm -----------------
+  ifeq ($(with_itm)-$(with_common_libs),yes-yes)
+      with_libitm := yes
+  endif
+
+  # libatomic -----------------
+  ifeq ($(with_atomic)-$(with_common_libs),yes-yes)
+      with_libatomic := yes
+  endif
+
+  # libbacktrace -----------------
+  ifeq ($(with_backtrace)-$(with_common_libs),yes-yes)
+      # currently not a shared library
+      #with_libbacktrace := yes
+  endif
+
+  # libasan -----------------
+  # asan changes soname in GCC 6
+  #ifeq ($(with_asan)-$(with_common_libs),yes-yes)
+    ifeq ($(with_asan),yes)
+      with_libasan := yes
+    endif
+  #endif
+
+  # liblsan -----------------
+  ifeq ($(with_lsan)-$(with_common_libs),yes-yes)
+    #ifneq ($(DEB_CROSS),yes)
+      with_liblsan := yes
+    #endif
+  endif
+
+  # libtsan -----------------
+  ifeq ($(with_tsan)-$(with_common_libs),yes-yes)
+      with_libtsan := yes
+  endif
+
+  # libubsan -----------------
+  ifeq ($(with_ubsan)-$(with_common_libs),yes-yes)
+      with_libubsan := yes
+  endif
+
+  # libvtv -----------------
+  ifeq ($(with_vtv)-$(with_common_libs),yes-yes)
+      with_libvtv := yes
+  endif
+
+  # libcilkrts -----------------
+  ifeq ($(with_cilkrts)-$(with_common_libs),yes-yes)
+      with_libcilkrts := yes
+  endif
+
+  # libquadmath -----------------
+  ifeq ($(with_qmath)-$(with_common_libs),yes-yes)
+      with_libqmath := yes
+  endif
+
+  # fixincludes -------
+  ifneq ($(DEB_CROSS),yes)
+    ifeq ($(with_common_pkgs),yes)
+      with_fixincl	:= yes
+    endif
+  endif
+
+  # Shared libgcc --------------------
+  ifneq ($(DEB_STAGE),stage1)
+    with_shared_libgcc := yes
+    ifeq ($(with_common_libs),yes)
+      with_libgcc := yes
+    endif
+  endif
+
+  # libgcc-math --------------------
+  with_libgmath := no
+  ifneq (,$(findstring i486,$(DEB_TARGET_ARCH)))
+    #with_libgccmath := yes
+    #with_lib64gmath := yes
+    #with_libgmathdev := yes
+  endif
+  ifeq ($(DEB_TARGET_ARCH),amd64)
+    #with_libgccmath := yes
+    #with_lib32gmath := yes
+    #with_libgmathdev := yes
+  endif
+
+  # hppa64 build ----------------
+  hppa64_no_snap := no
+  hppa64_archs := hppa
+  ifneq (,$(filter $(build_type), build-native cross-build-native))
+    ifeq (,$(filter $(distrelease),wheezy squeeze jessie lucid precise trusty utopic vivid wily))
+      hppa64_archs += amd64 i386 x32
+    endif
+    ifneq (,$(filter $(DEB_TARGET_ARCH),$(hppa64_archs)))
+      with_hppa64 := yes
+    endif
+  endif
+  ifeq ($(hppa64_no_snap)-$(trunk_build),yes-yes)
+    with_hppa64 := disabled for snapshot build
+  endif
+  with_hppa64 := $(call envfilt, hppa64, , , $(with_hppa64))
+
+  ifeq ($(DEB_STAGE),rtlibs)
+    with_libatomic := disabled for rtlibs stage
+    with_libasan := disabled for rtlibs stage
+    with_liblsan := disabled for rtlibs stage
+    with_libtsan := disabled for rtlibs stage
+    with_libubsan := disabled for rtlibs stage
+    with_libcilkrts := disabled for rtlibs stage
+    with_fixincl := disabled for rtlibs stage
+    with_hppa64 := disabled for rtlibs stage
+  endif
+
+  # neon build -------------------
+  # FIXME: build as a cross compiler to build on armv4 as well
+  ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+    ifeq ($(derivative),Ubuntu)
+#      neon_archs = armel armhf
+#      ifneq (, $(filter $(DEB_TARGET_ARCH),$(neon_archs)))
+#        with_neon = yes
+#      endif
+    endif
+  endif
+endif
+
+# run testsuite ---------------
+with_check := yes
+# if you don't want to run the gcc testsuite, uncomment the next line
+#with_check := disabled by hand
+ifeq ($(with_base_only),yes)
+  with_check := no
+endif
+ifeq ($(DEB_CROSS),yes)
+  with_check := disabled for cross compiler package
+endif
+ifneq (,$(findstring cross-build-,$(build_type)))
+  with_check := disabled for cross building the compiler
+endif
+ifneq (,$(with_rtlibs))
+  with_check := disabled for rtlibs stage
+endif
+check_no_cpus := m68k
+check_no_systems := # gnu kfreebsd-gnu
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(check_no_cpus)))
+  with_check := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(check_no_systems)))
+  with_check := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(derivative)-$(DEB_HOST_ARCH),Ubuntu-hppa)
+  ifneq ($(single_package),yes)
+    with_check := disabled, testsuite timeouts with expect
+  endif
+endif
+ifneq (,$(findstring gdc,$(PKGSOURCE)))
+  with_check := disabled for D
+endif
+with_check := $(call envfilt, check, , , $(with_check))
+ifdef WITHOUT_CHECK
+  with_check := disabled by environment
+endif
+ifneq ($(findstring nocheck, $(DEB_BUILD_OPTIONS)),)
+  with_check := disabled by DEB_BUILD_OPTIONS
+endif
+ifneq (,$(filter $(DEB_HOST_ARCH), hppa mips))
+  ifneq ($(single_package),yes)
+    with_check := disabled for $(DEB_HOST_ARCH), testsuite timeouts with expect
+  endif
+endif
+#with_check := disabled for this upload
+
+# not a dependency on all archs, but if available, use it for the testsuite
+ifneq (,$(wildcard /usr/bin/localedef))
+  locale_data = generate
+endif
+
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  ldconfig_arg = --noscripts
+endif
+
+all_enabled_languages := $(enabled_languages)
+languages_without_lang_opt := c++ objc obj-c++
+
+debian_extra_langs := $(subst obj-c++,objcp,$(debian_extra_langs))
+export debian_extra_langs
+
+# multilib
+biarch_map := i686=x86_64 powerpc=powerpc64 sparc=sparc64 sparc64=sparc s390=s390x s390x=s390 \
+		x86_64=i686 powerpc64=powerpc mips=mips64 mipsel=mips64el \
+		mips64=mips mips64el=mipsel mipsn32=mips mipsn32el=mipsel
+ifneq (,$(filter $(derivative),Ubuntu))
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid))
+    biarch_map := $(subst i686=,i486=,$(biarch_map))
+  endif
+else # Debian
+  biarch_map := $(subst i686=,i486=,$(biarch_map))
+endif
+
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid maverick natty))
+    biarch_map += arm=arm
+  endif
+endif
+biarch_cpu := $(strip $(patsubst $(DEB_TARGET_GNU_CPU)=%,%, \
+			 $(filter $(DEB_TARGET_GNU_CPU)=%,$(biarch_map))))
+
+biarch64 := no
+biarch32 := no
+biarchn32 := no
+biarchx32 := no
+biarchhf := no
+biarchsf := no
+flavours :=
+define gen_biarch
+  ifneq (yes,$$(call envfilt, biarch, , ,yes))
+    biarch$1archs :=
+  endif
+  ifneq (,$$(findstring /$$(DEB_TARGET_ARCH)/,$$(biarch$1archs)))
+    biarch$1 := yes
+    flavours += $1
+    #biarch$1subdir = $$(biarch_cpu)-$$(DEB_TARGET_GNU_SYSTEM)
+    biarch$1subdir = $1
+    ifeq ($$(with_libgcc),yes)
+      with_lib$1gcc := yes
+    endif
+    ifeq ($$(with_cdev),yes)
+      with_lib$1gccdev := yes
+    endif
+    ifeq ($$(with_libcxx),yes)
+      with_lib$1cxx := yes
+    endif
+    ifeq ($$(with_libcxxdbg),yes)
+      with_lib$1cxxdbg := yes
+    endif
+    ifeq ($$(with_cxxdev),yes)
+      with_lib$1cxxdev := yes
+    endif
+    ifeq ($$(with_libobjc),yes)
+      with_lib$1objc := yes
+    endif
+    ifeq ($$(with_objcdev),yes)
+      with_lib$1objcdev := yes
+    endif
+    ifeq ($$(with_libgfortran),yes)
+      with_lib$1gfortran := yes
+    endif
+    ifeq ($$(with_fdev),yes)
+      with_lib$1gfortrandev := yes
+    endif
+    ifeq (,$(filter $1, hf))
+      ifeq ($$(with_libphobos),yes)
+        with_lib$1phobos := yes
+      endif
+      ifeq ($$(with_libphobosdev),yes)
+        with_lib$1phobosdev := yes
+      endif
+    endif
+    ifeq ($$(with_libssp),yes)
+      with_lib$1ssp := yes
+    endif
+    ifeq ($$(with_libgomp),yes)
+      with_lib$1gomp:= yes
+    endif
+    ifeq ($$(with_libitm),yes)
+      with_lib$1itm:= yes
+    endif
+    ifeq ($$(with_libatomic),yes)
+      with_lib$1atomic:= yes
+    endif
+    ifeq ($$(with_libbacktrace),yes)
+      with_lib$1backtrace:= yes
+    endif
+    ifeq ($$(with_libasan),yes)
+      with_lib$1asan:= yes
+    endif
+    ifeq ($$(with_liblsan),yes)
+      with_lib$1lsan := yes
+    endif
+    ifeq ($$(with_libtsan),yes)
+      with_lib$1tsan:= yes
+    endif
+    ifeq ($$(with_libubsan),yes)
+      with_lib$1ubsan := yes
+    endif
+    ifeq ($$(with_libvtv),yes)
+      with_lib$1vtv := yes
+    endif
+    ifeq ($$(with_libcilkrts),yes)
+      with_lib$1cilkrts := yes
+    endif
+    ifeq ($$(with_libmpx),yes)
+      ifneq (,$(filter $1, 32 64))
+        with_lib$1mpx := yes
+      endif
+    endif
+    ifeq ($$(with_libqmath),yes)
+      with_lib$1qmath := yes
+    endif
+    ifeq ($$(with_libgo),yes)
+      with_lib$1go := yes
+    endif
+
+    biarch_multidir_names = libiberty libgcc libbacktrace libatomic libgomp
+    ifneq (,$$(findstring gcc-, $$(PKGSOURCE)))
+      biarch_multidir_names += libstdc++-v3 libobjc libgfortran libssp \
+				zlib libitm libmpx \
+				libsanitizer \
+				libcilkrts libvtv
+      ifeq ($$(with_objc_gc),yes)
+        biarch_multidir_names += boehm-gc
+      endif
+    endif
+    ifneq (,$(findstring yes, $(with_java) $(with_go)))
+      biarch_multidir_names += libffi
+    endif
+    ifeq ($(with_fortran),yes)
+      biarch_multidir_names += libquadmath
+    endif
+    ifeq ($(with_go),yes)
+      biarch_multidir_names += libgo
+    endif
+    ifeq ($(with_libphobos),yes)
+      ifeq (,$(filter $1, hf))
+        biarch_multidir_names += libphobos
+      endif
+    endif
+    ifneq (,$$(findstring 32,$1))
+      TARGET64_MACHINE := $$(strip $$(subst $$(DEB_TARGET_GNU_CPU),$$(biarch_cpu), \
+				$$(TARGET_ALIAS)))
+      TARGET32_MACHINE := $$(TARGET_ALIAS)
+    else
+      TARGET64_MACHINE := $$(TARGET_ALIAS)
+      TARGET64_MACHINE := $$(strip $$(subst $$(DEB_TARGET_GNU_CPU),$$(biarch_cpu), \
+				$$(TARGET_ALIAS)))
+    endif
+    export TARGET32_MACHINE
+    export TARGET64_MACHINE
+  endif
+endef
+biarch32archs := /amd64/ppc64/kfreebsd-amd64/s390x/sparc64/x32/mipsn32/mipsn32el/mips64/mips64el/
+biarch64archs := /i386/powerpc/sparc/s390/mips/mipsel/mipsn32/mipsn32el/x32/
+biarchn32archs := /mips/mipsel/mips64/mips64el/
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid maverick natty))
+    biarchhfarchs := /armel/
+    biarchsfarchs := /armhf/
+  endif
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal))
+    biarchx32archs := /amd64/i386/
+  endif
+endif
+ifeq ($(derivative),Debian)
+  ifeq (,$(filter $(distrelease),etch squeeze wheezy))
+    biarchx32archs := /amd64/i386/
+  endif
+endif
+$(foreach x,32 64 n32 x32 hf sf,$(eval $(call gen_biarch,$(x))))
+
+ifeq ($(DEB_TARGET_ARCH),sh4)
+  biarch_multidir_names=none
+endif
+export biarch_multidir_names
+
+#ifeq ($(trunk_build),yes)
+#  no_biarch_libs := yes
+#endif
+no_biarch_libs :=
+
+ifeq ($(no_biarch_libs),yes)
+  with_lib64gcc		:= no
+  with_lib64cxx		:= no
+  with_lib64cxxdbg	:= no
+  with_lib64objc	:= no
+  with_lib64ffi		:= no
+  with_lib64gcj		:= no
+  with_lib64gfortran	:= no
+  with_lib64ssp		:= no
+  with_lib64go		:= no
+  with_lib64gomp	:= no
+  with_lib64itm		:= no
+  with_lib64qmath	:= no
+  with_lib64atomic	:= no
+  with_lib64backtrace	:= no
+  with_lib64asan	:= no
+  with_lib64lsan	:= no
+  with_lib64tsan	:= no
+  with_lib64ubsan	:= no
+  with_lib64vtv		:= no
+  with_lib64cilkrts	:= no
+  with_lib64mpx		:= no
+  with_lib64gccdev	:= no
+  with_lib64cxxdev	:= no
+  with_lib64objcdev	:= no
+  with_lib64gfortrandev	:= no
+  with_lib64phobosdev	:= no
+
+  with_lib32gcc		:= no
+  with_lib32cxx		:= no
+  with_lib32cxxdbg	:= no
+  with_lib32objc	:= no
+  with_lib32ffi		:= no
+  with_lib32gcj		:= no
+  with_lib32gfortran	:= no
+  with_lib32ssp		:= no
+  with_lib32go		:= no
+  with_lib32gomp	:= no
+  with_lib32itm		:= no
+  with_lib32qmath	:= no
+  with_lib32atomic	:= no
+  with_lib32backtrace	:= no
+  with_lib32asan	:= no
+  with_lib32lsan	:= no
+  with_lib32tsan	:= no
+  with_lib32ubsan	:= no
+  with_lib32vtv		:= no
+  with_lib32cilkrts	:= no
+  with_lib32mpx		:= no
+  with_lib32gccdev	:= no
+  with_lib32cxxdev	:= no
+  with_lib32objcdev	:= no
+  with_lib32gfortrandev	:= no
+  with_lib32phobosdev	:= no
+
+  with_libn32gcc	:= no
+  with_libn32cxx	:= no
+  with_libn32cxxdbg	:= no
+  with_libn32objc	:= no
+  with_libn32ffi	:= no
+  with_libn32gcj	:= no
+  with_libn32gfortran	:= no
+  with_libn32ssp	:= no
+  with_libn32go		:= no
+  with_libn32gomp	:= no
+  with_libn32itm	:= no
+  with_libn32qmath	:= no
+  with_libn32atomic	:= no
+  with_libn32backtrace	:= no
+  with_libn32asan	:= no
+  with_libn32lsan	:= no
+  with_libn32tsan	:= no
+  with_libn32ubsan	:= no
+  with_libn32gccdev	:= no
+  with_libn32cxxdev	:= no
+  with_libn32objcdev	:= no
+  with_libn32gfortrandev:= no
+  with_libn32phobosdev	:= no
+
+  with_libx32gcc	:= no
+  with_libx32cxx	:= no
+  with_libx32cxxdbg	:= no
+  with_libx32objc	:= no
+  with_libx32ffi	:= no
+  with_libx32gcj	:= no
+  with_libx32gfortran	:= no
+  with_libx32ssp	:= no
+  with_libx32go		:= no
+  with_libx32gomp	:= no
+  with_libx32itm	:= no
+  with_libx32qmath	:= no
+  with_libx32atomic	:= no
+  with_libx32backtrace	:= no
+  with_libx32asan	:= no
+  with_libx32lsan	:= no
+  with_libx32tsan	:= no
+  with_libx32ubsan	:= no
+  with_libx32vtv	:= no
+  with_libx32cilkrts	:= no
+  with_libx32gccdev	:= no
+  with_libx32cxxdev	:= no
+  with_libx32objcdev	:= no
+  with_libx32gfortrandev:= no
+  with_libx32phobosdev	:= no
+
+  with_libhfgcc		:= no
+  with_libhfcxx		:= no
+  with_libhfcxxdbg	:= no
+  with_libhfobjc	:= no
+  with_libhfffi		:= no
+  with_libhfgcj		:= no
+  with_libhfgfortran	:= no
+  with_libhfssp		:= no
+  with_libhfgo		:= no
+  with_libhfgomp	:= no
+  with_libhfitm		:= no
+  with_libhfqmath	:= no
+  with_libhfatomic	:= no
+  with_libhfbacktrace	:= no
+  with_libhfasan	:= no
+  with_libhflsan	:= no
+  with_libhftsan	:= no
+  with_libhfubsan	:= no
+  with_libhfgccdev	:= no
+  with_libhfcxxdev	:= no
+  with_libhfobjcdev	:= no
+  with_libhfgfortrandev	:= no
+  with_libhfphobosdev	:= no
+
+  with_libsfgcc		:= no
+  with_libsfcxx		:= no
+  with_libsfcxxdbg	:= no
+  with_libsfobjc	:= no
+  with_libsfffi		:= no
+  with_libsfgcj		:= no
+  with_libsfgfortran	:= no
+  with_libsfssp		:= no
+  with_libsfgo		:= no
+  with_libsfgomp	:= no
+  with_libsfitm		:= no
+  with_libsfqmath	:= no
+  with_libsfatomic	:= no
+  with_libsfbacktrace	:= no
+  with_libsfasan	:= no
+  with_libsflsan	:= no
+  with_libsftsan	:= no
+  with_libsfubsan	:= no
+  with_libsfgccdev	:= no
+  with_libsfcxxdev	:= no
+  with_libsfobjcdev	:= no
+  with_libsfgfortrandev	:= no
+  with_libsfphobosdev	:= no
+
+  with_java_plugin := no
+
+  ifeq ($(with_ada)-$(with_separate_gnat),yes-yes)
+    biarchhf	:= disabled for Ada
+    biarchsf	:= disabled for Ada
+  endif
+
+endif
+
+ifneq (,$(filter yes,$(biarch32) $(biarch64) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+  multilib := yes
+endif
+
+multilib_archs = $(sort $(subst /, , $(biarch64archs) $(biarch32archs) $(biarchn32archs) $(biarchx32archs) $(biarchhfarchs) $(biarchsfarchs)))
+
+biarchsubdirs := \
+  $(if $(filter yes,$(biarch64)),$(biarch64subdir),) \
+  $(if $(filter yes,$(biarch32)),$(biarch32subdir),) \
+  $(if $(filter yes,$(biarchn32)),$(biarchn32subdir),) \
+  $(if $(filter yes,$(biarchx32)),$(biarchx32subdir),) \
+  $(if $(filter yes,$(biarchhf)),$(biarchhfsubdir),) \
+  $(if $(filter yes,$(biarchsf)),$(biarchsfsubdir),)
+biarchsubdirs := {$(strip $(shell echo $(biarchsubdirs) | tr " " ","))}
+
+# GNU locales
+force_gnu_locales := yes
+locale_no_cpus :=
+locale_no_systems :=
+ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(locale_no_systems)))
+  force_gnu_locales := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+
+gcc_tarpath		:= $(firstword $(wildcard gcc-*.tar.* /usr/src/gcc-6/gcc-*.tar.*))
+gcc_tarball		:= $(notdir $(gcc_tarpath))
+gcc_srcdir		:= $(subst -dfsg,,$(patsubst %.tar.xz,%,$(patsubst %.tar.lzma,%,$(patsubst %.tar.gz,%,$(gcc_tarball:.tar.bz2=)))))
+
+ifeq ($(with_d),yes)
+  gdc_tarpath		:= $(firstword $(wildcard gdc-*.tar.* /usr/src/gcc-$(BASE_VERSION)/gdc-*.tar.*))
+  gdc_tarball		:= $(notdir $(gdc_tarpath))
+  gdc_srcdir		:= $(patsubst %.tar.xz,%,$(patsubst %.tar.lzma,%,$(patsubst %.tar.gz,%,$(gdc_tarball:.tar.bz2=))))
+endif
+
+# NOTE: This is not yet used. when building gcj, gdc or gnat using the
+# gcc-source package, we don't require an exact binary dependency.
+ifneq ($(dir $(gcc_tarpath)),./)
+  built_using_external_source := yes
+else
+  built_using_external_source :=
+endif
+ifeq ($(DEB_CROSS),yes)
+  add_built_using = yes
+endif
+ifeq ($(with_ada)-$(with_separate_gnat),yes-yes)
+  add_built_using = yes
+endif
+
+ecj_jar := $(firstword $(wildcard ecj.jar /usr/share/java/eclipse-ecj.jar /usr/share/java/ecj.jar))
+
+unpack_stamp		:= $(stampdir)/01-unpack-stamp
+pre_patch_stamp		:= $(stampdir)/02-pre-patch-stamp
+patch_stamp		:= $(stampdir)/02-patch-stamp
+control_stamp		:= $(stampdir)/03-control-stamp
+configure_stamp		:= $(stampdir)/04-configure-stamp
+build_stamp		:= $(stampdir)/05-build-stamp
+build_arch_stamp	:= $(stampdir)/05-build-arch-stamp
+build_indep_stamp	:= $(stampdir)/05-build-indep-stamp
+build_html_stamp	:= $(stampdir)/05-build-html-stamp
+build_locale_stamp	:= $(stampdir)/05-build-locale-stamp
+build_doxygen_stamp	:= $(stampdir)/05-build-doxygen-stamp
+build_javasrc_stamp	:= $(stampdir)/05-build-javasrc-stamp
+build_javadoc_stamp	:= $(stampdir)/05-build-javadoc-stamp
+build_gnatdoc_stamp	:= $(stampdir)/05-build-gnatdoc-stamp
+check_stamp		:= $(stampdir)/06-check-stamp
+check_inst_stamp	:= $(stampdir)/06-check-inst-stamp
+install_stamp		:= $(stampdir)/07-install-stamp
+install_snap_stamp	:= $(stampdir)/07-install-snap-stamp
+binary_stamp		:= $(stampdir)/08-binary-stamp
+
+configure_dummy_stamp	:= $(stampdir)/04-configure-dummy-stamp
+build_dummy_stamp	:= $(stampdir)/05-build-dummy-stamp
+install_dummy_stamp	:= $(stampdir)/07-install-dummy-stamp
+
+configure_jit_stamp	:= $(stampdir)/04-configure-jit-stamp
+build_jit_stamp		:= $(stampdir)/05-build-jit-stamp
+install_jit_stamp	:= $(stampdir)/07-install-jit-stamp
+
+configure_hppa64_stamp	:= $(stampdir)/04-configure-hppa64-stamp
+build_hppa64_stamp	:= $(stampdir)/05-build-hppa64-stamp
+install_hppa64_stamp	:= $(stampdir)/07-install-hppa64-stamp
+
+configure_neon_stamp	:= $(stampdir)/04-configure-neon-stamp
+build_neon_stamp		:= $(stampdir)/05-build-neon-stamp
+install_neon_stamp	:= $(stampdir)/07-install-neon-stamp
+
+control_dependencies	:= $(patch_stamp)
+
+ifeq ($(single_package),yes)
+    configure_dependencies = $(configure_stamp)
+    build_dependencies = $(build_stamp)
+    install_dependencies = $(install_snap_stamp)
+    ifeq ($(with_check),yes)
+      check_dependencies += $(check_stamp)
+    endif
+else
+  ifeq ($(with_base_only),yes)
+    configure_dependencies = $(configure_dummy_stamp)
+    build_dependencies = $(build_dummy_stamp)
+    install_dependencies = $(install_dummy_stamp)
+  else
+    configure_dependencies = $(configure_stamp)
+    build_dependencies = $(build_stamp)
+    install_dependencies = $(install_stamp)
+    ifeq ($(with_check),yes)
+      check_dependencies += $(check_stamp)
+    endif
+  endif
+endif
+
+ifneq (,$(findstring gcj-, $(PKGSOURCE)))
+  ifeq ($(with_gcj_base_only),yes)
+    configure_dependencies = $(configure_dummy_stamp)
+    build_dependencies = $(build_dummy_stamp)
+    install_dependencies = $(install_dummy_stamp)
+  endif
+endif
+
+ifeq ($(with_jit),yes)
+  build_dependencies += $(build_jit_stamp)
+  install_dependencies += $(install_jit_stamp)
+endif
+
+ifeq ($(with_neon),yes)
+  build_dependencies += $(build_neon_stamp)
+  install_dependencies += $(install_neon_stamp)
+endif
+
+ifeq ($(with_hppa64),yes)
+  build_dependencies += $(build_hppa64_stamp)
+  ifneq ($(trunk_build),yes)
+    install_dependencies += $(install_hppa64_stamp)
+  endif
+endif
+
+build_dependencies += $(check_dependencies)
+
+build_arch_dependencies = $(build_dependencies)
+build_indep_dependencies = $(build_dependencies)
+
+ifneq (,$(findstring build-native, $(build_type)))
+  ifneq ($(single_package),yes)
+    build_indep_dependencies += $(build_html_stamp)
+    ifeq ($(with_cxx),yes)
+      build_indep_dependencies += $(build_doxygen_stamp)
+    endif
+    ifeq ($(with_java),yes)
+      build_arch_dependencies += $(build_html_stamp)
+      build_indep_dependencies += $(build_javasrc_stamp)
+      build_indep_dependencies += $(build_javadoc_stamp)
+    endif
+    ifeq ($(with_ada),yes)
+      build_indep_dependencies += $(build_gnatdoc_stamp)
+    endif
+  endif
+endif
+
+stamp-dir:
+	mkdir -p $(stampdir)
+
+ifeq ($(DEB_CROSS),yes)
+  define cross_mangle_shlibs
+	if [ -f debian/$(1)/DEBIAN/shlibs ]; then \
+	  sed -i s/$(cross_lib_arch)/:$(DEB_TARGET_ARCH)/g debian/$(1)/DEBIAN/shlibs; \
+	fi
+  endef
+  define cross_mangle_substvars
+	if [ -f debian/$(1).substvars ]; then \
+	  sed -i \
+	    -e 's/:$(DEB_TARGET_ARCH)/$(cross_lib_arch)/g' \
+	    -e 's/\(libc[.0-9]*-[^:]*\):\([a-z0-9-]*\)/\1-\2-cross/g' \
+	    $(if $(filter armel,$(DEB_TARGET_ARCH)),-e 's/:armhf/-armhf-cross/g') \
+	    $(if $(filter armhf,$(DEB_TARGET_ARCH)),-e 's/:armel/-armel-cross/g') \
+	    debian/$(1).substvars; \
+	fi
+  endef
+else
+  define cross_mangle_shlibs
+  endef
+  define cross_mangle_substvars
+  endef
+  # precise's dh_shlibdeps doesn't work well for ARM multilibs
+  # and dh_shlibdeps doesn't work well for cross builds, see #698881.
+  ifneq (,$(filter $(distrelease),precise quantal raring))
+    ifneq (,$(filter $(DEB_TARGET_ARCH), armel armhf arm64))
+      ignshld = -
+    endif
+  endif
+endif
+ifeq ($(DEB_STAGE),rtlibs)
+  define cross_mangle_shlibs
+  endef
+  define cross_mangle_substvars
+  endef
+endif
+
+# takes a *list* of package names as $1, the multilib dirname as $2
+_shlibdirs = \
+	$(if $(strip $(1)), \
+	  $(shell find $(foreach p,$(1),$(CURDIR)/debian/$(p)) \
+		-name '*.so.*' -printf '%h ' | uniq)) \
+	$(with_build_sysroot)/lib/$(call mlib_to_march,$(2)) \
+	$(with_build_sysroot)/usr/lib/$(call mlib_to_march,$(2)) \
+	$(with_build_sysroot)$(subst /usr,,/$(usr_lib$(2))) \
+	$(with_build_sysroot)/$(usr_lib$(2)) \
+	$(if $(filter yes,$(biarchsf) $(biarchhf)), \
+	  $(with_build_sysroot)/usr/$(call mlib_to_march,$(2))/lib) \
+	$(if $(filter yes, $(with_common_libs)),, \
+	  $(CURDIR)/$(d)/$(usr_lib$(2)) \
+	  $(CURDIR)/$(d)/usr/$(call mlib_to_march,$(2))/lib)
+shlibdirs_to_search = -l$(subst $(SPACE),:,$(foreach d,$(_shlibdirs),$(d)))
--- gcc-6-6.3.0.orig/debian/rules.parameters
+++ gcc-6-6.3.0/debian/rules.parameters
@@ -0,0 +1,45 @@
+# configuration parameters taken from upstream source files
+GCC_VERSION	:= 6.3.0
+NEXT_GCC_VERSION	:= 6.3.1
+BASE_VERSION	:= 6
+SOURCE_VERSION	:= 6.3.0-9ubuntu1
+DEB_VERSION	:= 6.3.0-9ubuntu1
+DEB_EVERSION	:= 1:6.3.0-9ubuntu1
+DEB_GDC_VERSION	:= 6.3.0-9ubuntu1
+DEB_SOVERSION	:= 5
+DEB_SOEVERSION	:= 1:5
+DEB_LIBGCC_SOVERSION	:= 
+DEB_LIBGCC_VERSION	:= 1:6.3.0-9ubuntu1
+DEB_STDCXX_SOVERSION	:= 5
+DEB_GCJ_SOVERSION	:= 5
+PKG_GCJ_EXT	:= 17
+PKG_LIBGCJ_EXT	:= 17
+DEB_GOMP_SOVERSION	:= 5
+GCC_SONAME	:= 1
+CXX_SONAME	:= 6
+FORTRAN_SONAME	:= 3
+OBJC_SONAME	:= 4
+GCJ_SONAME	:= 17
+GDC_VERSION	:= 6
+GNAT_VERSION	:= 6
+GNAT_SONAME	:= 6
+FFI_SONAME	:= 7
+SSP_SONAME	:= 0
+GOMP_SONAME	:= 1
+ITM_SONAME	:= 1
+ATOMIC_SONAME	:= 1
+BTRACE_SONAME	:= 1
+ASAN_SONAME	:= 3
+LSAN_SONAME	:= 0
+TSAN_SONAME	:= 0
+UBSAN_SONAME	:= 0
+VTV_SONAME	:= 0
+CILKRTS_SONAME	:= 5
+MPX_SONAME	:= 2
+QUADMATH_SONAME	:= 0
+GO_SONAME		:= 9
+CC1_SONAME	:= 0
+GCCJIT_SONAME	:= 0
+GPHOBOS_SONAME	:= 68
+GDRUNTIME_SONAME	:= 68
+LIBC_DEP		:= libc6
--- gcc-6-6.3.0.orig/debian/rules.patch
+++ gcc-6-6.3.0/debian/rules.patch
@@ -0,0 +1,474 @@
+# -*- makefile -*-
+# rules to patch the unpacked files in the source directory
+# ---------------------------------------------------------------------------
+# various rules to unpack addons and (un)apply patches.
+# 	- patch / apply-patches
+#	- unpatch / reverse-patches
+
+.NOTPARALLEL:
+
+patchdir	?= debian/patches
+series_file	?= $(patchdir)/series
+
+# which patches should be applied?
+
+debian_patches = \
+	svn-updates \
+	libiberty-updates \
+	$(if $(with_linaro_branch),gcc-linaro) \
+	$(if $(with_linaro_branch),gcc-linaro-no-macros) \
+
+#	svn-updates \
+
+ifeq ($(with_java),yes)
+#  debian_patches += \
+#	svn-class-updates
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  debian_patches += \
+	$(if $(with_linaro_branch),gcc-linaro-doc) \
+	rename-info-files \
+	gcc-SOURCE_DATE_EPOCH-doc \
+	gcc-SOURCE_DATE_EPOCH-2-doc \
+	$(if $(with_linaro_branch),,vulcan-cpu-doc) \
+	gcc-fuse-ld-lld-doc \
+
+#	svn-doc-updates \
+#	$(if $(with_linaro_branch),,svn-doc-updates) \
+
+else
+endif
+debian_patches += \
+	gcc-gfdl-build
+
+#	boehm-gc-nocheck: seems to work on the buildds \
+
+debian_patches += \
+	gcc-textdomain \
+	gcc-driver-extra-langs$(if $(with_linaro_branch),-linaro)
+
+ifneq (,$(filter $(distrelease),etch lenny squeeze wheezy dapper hardy intrepid jaunty karmic lucid))
+  debian_patches += gcc-hash-style-both
+else
+  debian_patches += gcc-hash-style-gnu
+endif
+
+debian_patches += \
+	libstdc++-pic \
+	libstdc++-doclink \
+	libstdc++-man-3cxx \
+	libstdc++-test-installed \
+	libjava-stacktrace \
+	libjava-jnipath \
+	libjava-sjlj \
+	libjava-disable-plugin \
+	alpha-no-ev4-directive \
+	boehm-gc-getnprocs \
+	note-gnu-stack \
+	libgomp-omp_h-multilib \
+	gccgo-version \
+	pr47818 \
+	gcc-base-version \
+	libgo-testsuite \
+	gcc-target-include-asm \
+	libgo-revert-timeout-exp \
+	libgo-setcontext-config \
+	gcc-auto-build \
+	kfreebsd-unwind \
+	libitm-no-fortify-source \
+	sparc64-biarch-long-double-128 \
+	gcc-ia64-bootstrap-ignore \
+	gotools-configury \
+	pr66368 \
+	pr67590 \
+	ada-gnattools-ldflags \
+	libjit-ldflags \
+	gcc-SOURCE_DATE_EPOCH \
+	gcc-SOURCE_DATE_EPOCH-2 \
+	cmd-go-combine-gccgo-s-ld-and-ldShared-methods \
+	libjava-mips64el \
+	gccgo-issue16780 \
+	$(if $(with_linaro_branch),,vulcan-cpu) \
+	$(if $(with_linaro_branch),,vulcan-costs) \
+	libffi-pax \
+	libffi-race-condition \
+	libgo-add-getrandom-mips-sparc \
+	libgo-fix-getrandom-clone-sparc64 \
+	libgo-rawClone-no_split_stack \
+	libgo-rawClone-no-pt_regs \
+	libgo-elf-relocations-sparc64 \
+	libobjc-system-gc \
+	compress-debug-check \
+	pr77267 \
+	pr78774 \
+	CVE-2016-9840 \
+	CVE-2016-9841 \
+	CVE-2016-9842 \
+	CVE-2016-9843 \
+	libcc1-compiler-name \
+	mips-pr78176-add-mlxc1-sxc1 \
+	mips-loongson3a-use-fused-madd.d \
+	mips-madd4 \
+	gcc-fuse-ld-lld \
+
+ifeq ($(libstdcxx_abi),new)
+  debian_patches += libstdc++-functexcept
+endif
+
+#	$(if $(filter yes, $(DEB_CROSS)),,gcc-print-file-name) \
+#	libstdc++-nothumb-check \
+# TODO: update ...
+#	libjava-rpath \
+
+hardening_patches =
+ifeq ($(with_ssp)-$(with_ssp_default),yes-yes)
+  hardening_patches += gcc-default-ssp
+  hardening_patches += gcc-default-format-security
+  ifeq (,$(filter $(distrelease),dapper hardy lucid maverick natty oneiric precise quantal raring saucy trusty))
+    hardening_patches += gcc-default-ssp-strong
+  endif
+endif
+ifneq (,$(filter $(derivative),Ubuntu))
+  ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+    hardening_patches += \
+	gcc-default-fortify-source \
+	gcc-default-relro \
+	testsuite-hardening-format \
+	testsuite-hardening-printf-types \
+	testsuite-hardening-updates \
+	testsuite-glibc-warnings
+    ifeq ($(with_pie),yes)
+      hardening_patches += \
+	bind_now_when_pie
+    else
+      hardening_patches += \
+	ignore-pie-specs-when-not-enabled
+    endif
+  endif
+else ifneq (,$(filter $(derivative),Debian))
+  ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+#    ifneq ($(with_pie),yes)
+#      hardening_patches += \
+#	ignore-pie-specs-when-not-enabled
+#    endif
+  endif
+endif
+
+# FIXME 4.5: Drop and adjust symbols files
+ifneq (,$(findstring 4.4, $(PKGSOURCE)))
+  debian_patches += pr39491
+endif
+
+debian_patches += ada-arm
+debian_patches += ada-kfreebsd
+debian_patches += ada-revert-pr63225
+
+ifeq (,$(DEB_STAGE))
+# there should be no harm to always apply these, except for new GCC versions
+#ifeq ($(with_ada),yes)
+  debian_patches += \
+	ada-driver-check \
+	ada-default-project-path \
+	ada-library-project-files-soname
+
+	# FIXME: needs update
+	#ada-symbolic-tracebacks \
+
+  ifeq ($(biarch64),yes)
+    debian_patches += \
+	ada-nobiarch-check
+  endif
+
+  #ifeq ($(with_libgnat),yes)
+    debian_patches += \
+	ada-link-lib \
+	ada-libgnatvsn \
+	ada-libgnatprj \
+	ada-gnattools-cross \
+	ada-acats \
+	libgnatprj-cross-hack
+    ifneq (,$(filter $(distrelease),lucid precise))
+      debian_patches += \
+	libgnatprj-link
+    endif
+  #endif
+  #ifeq ($(with_gnatsjlj),yes)
+    debian_patches += \
+	ada-sjlj
+  #endif
+
+  debian_patches += ada-link-shlib
+#endif
+endif # DEB_STAGE
+
+
+ifeq ($(with_d),yes)
+  debian_patches += \
+	gdc-6 \
+	gdc-updates \
+	libphobos-zlib \
+	gdc-versym-cpu \
+	gdc-versym-os \
+	gdc-frontend-posix \
+	gdc-base-version \
+	gdc-profiledbuild \
+#	gdc-multiarch
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    debian_patches += gdc-6-doc
+  else
+    debian_patches += gdc-texinfo
+  endif
+  ifeq ($(with_libphobos),yes)
+    debian_patches += gdc-libphobos-build
+  else
+    debian_patches += gdc-driver-nophobos
+  endif
+  ifeq (,$(filter $(DEB_TARGET_ARCH),amd64 i386))
+    debian_patches += disable-gdc-tests
+  endif
+else
+  debian_patches += gcc-d-lang
+endif
+
+ifeq ($(DEB_TARGET_ARCH),alpha)
+  debian_patches += alpha-ieee
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    debian_patches += alpha-ieee-doc
+  endif
+endif
+
+ifeq (,$(filter $(derivative),Ubuntu))
+  debian_patches += pr64735-headers
+  ifeq ($(DEB_TARGET_ARCH),armel)
+    debian_patches += pr64735
+  endif
+endif
+
+ifneq (,$(findstring $(DEB_TARGET_ARCH),arm armel armhf))
+  debian_patches += libjava-armel-unwind
+endif
+
+ifeq ($(DEB_TARGET_ARCH),armhf)
+ debian_patches += gcj-arm-mode
+else ifeq ($(DEB_TARGET_ARCH),armel)
+  ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+    debian_patches += gcj-arm-mode
+  endif
+endif
+
+ifneq (,$(findstring mips, $(DEB_TARGET_ARCH)))
+  debian_patches += pr65618
+endif
+
+ifeq ($(DEB_TARGET_ARCH),powerpcspe)
+  debian_patches += powerpc_remove_many
+  debian_patches += powerpc_nofprs
+endif
+
+#debian_patches += link-libs
+
+# all patches below this line are applied for gcc-snapshot builds as well
+
+ifeq ($(single_package),yes)
+  debian_patches =
+endif
+
+debian_patches += \
+	sys-auxv-header \
+	libcilkrts-targets \
+
+ifeq ($(with_ibm_branch),yes)
+  debian_patches += ibm-branch
+endif
+
+ifeq ($(with_softfloat),yes)
+  debian_patches += arm-multilib-soft-float
+else ifeq ($(multilib),yes)
+  ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+    debian_patches += arm-multilib-softfp$(if $(filter yes,$(DEB_CROSS)),-cross)
+  else
+    debian_patches += arm-multilib-soft$(if $(filter yes,$(DEB_CROSS)),-cross)
+  endif
+endif
+debian_patches += arm-multilib-defaults
+
+ifeq ($(DEB_CROSS),yes)
+  debian_patches += cross-fixes
+  debian_patches += cross-install-location
+  ifeq ($(with_d),yes)
+    debian_patches += gdc-cross-install-location
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH_OS),hurd)
+  debian_patches += hurd-changes
+  debian_patches += \
+		src_gcc_config_i386_gnu.h \
+		src_libgo_configure.ac \
+		src_libgo_runtime_go-caller.c \
+		src_libgo_go_net_sendfile_gnu.go \
+		src_libgo_go_net_sock_gnu.go \
+		src_libgo_go_net_sockopt_gnu.go \
+		src_libgo_go_net_sockoptip_gnu.go \
+		src_libgo_go_syscall_libcall_gnu_386.go \
+		src_libgo_go_syscall_libcall_gnu.go \
+		src_libgo_go_syscall_libcall_posix-1.go \
+		src_libgo_go_syscall_socket_gnu.go \
+		src_libgo_go_syscall_wait.c \
+		src_libgo_Makefile.am \
+		src_libgo_Makefile.in \
+		src_libgo_mksysinfo.sh \
+		src_libgo_runtime_getncpu-gnu.c \
+		src_libgo_runtime_netpoll.goc \
+		src_libgo_go_os_os_test.go \
+		src_libgo_go_syscall_syscall_gnu_test.go \
+		src_libgo_testsuite_gotest \
+		add-gnu-to-libgo-headers
+endif
+
+debian_patches += gcc-ice-dump
+debian_patches += gcc-ice-apport
+debian_patches += skip-bootstrap-multilib
+debian_patches += libjava-fixed-symlinks
+debian_patches += libffi-ro-eh_frame_sect
+debian_patches += libffi-mips
+
+# sigaction on sparc changed between glibc 2.19 and 2.21
+ifeq (,$(filter 2.1%, $(shell dpkg-query -l libc-bin | awk '/^.i/ {print $$3}')))
+  debian_patches += pr67899
+endif
+
+debian_patches += gcc-multiarch
+ifeq ($(with_multiarch_lib),yes)
+  ifneq ($(single_package),yes)
+    debian_patches += libjava-multiarch
+  endif
+endif
+debian_patches += libjava-nobiarch-check
+debian_patches += config-ml
+ifneq ($(single_package),yes)
+  ifeq ($(with_multiarch_cxxheaders),yes)
+    debian_patches += g++-multiarch-incdir
+    debian_patches += canonical-cpppath
+  endif
+endif
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  debian_patches += cross-no-locale-include
+  debian_patches += cross-biarch
+  ifeq ($(with_libphobos),yes)
+    debian_patches += gdc-cross-biarch
+  endif
+endif
+debian_patches += gcc-multilib-multiarch
+
+ifneq (,$(filter $(derivative),Ubuntu))
+  ifeq (,$(filter $(distrelease),dapper hardy intrepid jaunty karmic lucid maverick))
+    debian_patches += gcc-as-needed
+    ifeq (,$(filter $(distrelease),dapper hardy intrepid jaunty karmic lucid maverick precise trusty utopic vivid wily xenial yakkety))
+      debian_patches += gcc-as-needed-gold
+    endif
+  endif
+else # Debian
+    #debian_patches += gcc-as-needed
+endif
+
+debian_patches += libgomp-kfreebsd-testsuite
+debian_patches += go-testsuite
+
+# Ada patches needed for both the stable package and snapshot builds
+debian_patches += ada-749574
+debian_patches += ada-mips
+ifeq ($(DEB_TARGET_ARCH),m68k)
+  debian_patches += ada-m68k
+  ifeq ($(with_ada),yes)
+    debian_patches += m68k-revert-pr45144
+  endif
+endif
+
+# don't remove, this is regularly overwritten, see PR sanitizer/63958.
+#debian_patches += libasan-sparc
+
+series_stamp = $(stampdir)/02-series-stamp
+series: $(series_stamp)
+$(series_stamp):
+	echo $(strip $(addsuffix .diff,$(debian_patches))) \
+	  | sed -r 's/  +/ /g' | tr " " "\n" > $(series_file)
+ifneq (,$(strip $(hardening_patches)))
+  ifneq ($(trunk_build),yes)
+	echo $(strip $(addsuffix .diff,$(hardening_patches))) \
+	  | sed -r 's/  +/ /g' | tr " " "\n" >> $(series_file)
+  endif
+endif
+	sed -r 's/(.)$$/\1 -p1/' -i $(series_file)
+	touch $@
+
+autoconf_files = $(filter-out src/libjava/classpath/m4/acinclude.m4, \
+	  $(shell lsdiff --no-filename $(foreach patch,$(debian_patches),$(patchdir)/$(patch).diff) \
+	    | sed -rn '/(configure\.ac|acinclude.m4)$$/s:[^/]+/src/:src/:p' | sort -u))
+autoconf_dirs = $(sort $(dir $(autoconf_files)))
+
+automake_files = $(addprefix ./, $(filter-out none, \
+	  $(shell lsdiff --no-filename $(foreach patch,$(debian_patches),$(patchdir)/$(patch).diff) \
+	    | sed -rn '/Makefile\.(am|in)$$/s:[^/]+/src/:src/:p' | sort -u)))
+
+autoconf_version = 2.64
+ifeq ($(trunk_build),yes)
+  # The actual version depends on the build-dependencies set by
+  # variable AUTO_BUILD_DEP in rules.conf.  Here, we assume the
+  # correct version is installed.
+  #autoconf_version =
+endif
+
+# FIXME: the auto* stuff is done every time for every subdir, which
+# leads to build errors. Idea: record the auto* calls in the patch
+# files (AUTO <dir> <auto-command with options>) and run them separately,
+# maybe only once per directory).
+$(patch_stamp): $(unpack_stamp) $(series_stamp)
+	sync
+	QUILT_PATCHES=$(patchdir) \
+	  quilt --quiltrc /dev/null push -a || test $$? = 2
+
+ifneq (,$(filter svn-updates, $(debian_patches)))
+	awk '/^EOF/ {exit} p==1 {print} /EOF$$/ {p=1}' \
+	  $(patchdir)/svn-updates.diff > src/LAST_UPDATED
+endif
+
+ifneq (,$(filter libgo-elf-relocations-sparc64, $(debian_patches)))
+	uudecode $(patchdir)/../go-relocation-test-gcc620-sparc64.obj.uue
+endif
+
+	: # only needed when we have changes, and currently fails with autogen 5.18
+	: #cd $(srcdir)/fixincludes && ./genfixes
+
+	sync
+	echo -n $(autoconf_dirs) | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'echo "Running autoconf$(autoconf_version) in {}..." ; \
+	  cd $(CURDIR)/{} && \
+	  AUTOM4TE=/usr/bin/autom4te$(autoconf_version) autoconf$(autoconf_version)'
+
+	for i in $(debian_patches) $(hardening_patches); do \
+	  echo -e "\n$$i:" >> pxxx; \
+	  sed -n 's/^# *DP: */  /p' $(patchdir)/$$i.diff >> pxxx; \
+	done
+#	-$(srcdir)/move-if-change pxxx $@
+	mv pxxx $@
+
+unpatch:
+ifneq (,$(filter libgo-elf-relocations-sparc64, $(debian_patches)))
+	# uudecoded in $(patch_stamp) rule
+	rm -f $(srcdir)/libgo/go/debug/elf/testdata/go-relocation-test-gcc620-sparc64.obj
+endif
+
+	QUILT_PATCHES=$(patchdir) \
+	  quilt --quiltrc /dev/null pop -a -R || test $$? = 2
+	rm -rf .pc
+
+update-patches: $(series_stamp)
+	export QUILT_PATCHES=$(patchdir); \
+	export QUILT_REFRESH_ARGS="--no-timestamps --no-index -pab"; \
+	export QUILT_DIFF_ARGS="--no-timestamps --no-index -pab"; \
+	while quilt push; do quilt refresh; done
+
+patch: $(patch_stamp)
+.PHONY: patch series quilt autotools
--- gcc-6-6.3.0.orig/debian/rules.sonames
+++ gcc-6-6.3.0/debian/rules.sonames
@@ -0,0 +1,101 @@
+ifneq ($(vafilt_defined),1)
+  $(error rules.defs must be included before rules.sonames)
+endif
+
+ifeq (,$(wildcard debian/soname-cache))
+  SONAME_VARS := $(shell \
+	cache=debian/soname-cache; \
+	rm -f $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libstdc++-v3/acinclude.m4`; \
+	echo CXX_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libobjc/configure.ac`; \
+	echo OBJC_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libgfortran/libtool-version | cut -d: -f1`; \
+	echo FORTRAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libssp/libtool-version | cut -d: -f1`; \
+	echo SSP_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libjava/libtool-version | cut -d: -f1`; \
+	echo GCJ_SONAME=$$v >> $$cache; \
+	if [ "$$v" -ge 70 ]; then \
+	  echo GCJ_SONAME1=`echo $$v | sed 's/.$$//'` >> $$cache; \
+	  echo GCJ_SONAME2=`echo $$v | sed 's/.*\(.\)$$/\1/'` >> $$cache; \
+	else \
+	  echo GCJ_SONAME1=$$v >> $$cache; \
+	  echo GCJ_SONAME2= >> $$cache; \
+	fi; \
+	v=`tail -1 $(srcdir)/libffi/libtool-version | cut -d: -f1`; \
+	echo FFI_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libgomp/configure.ac`; \
+	echo GOMP_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/asan/libtool-version | cut -d: -f1`; \
+	echo ASAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/lsan/libtool-version | cut -d: -f1`; \
+	echo LSAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/tsan/libtool-version | cut -d: -f1`; \
+	echo TSAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/ubsan/libtool-version | cut -d: -f1`; \
+	echo UBSAN_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libatomic/configure.ac`; \
+        v=1; \
+	echo ATOMIC_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libbacktrace/configure.ac`; \
+	echo BTRACE_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libquadmath/libtool-version | cut -d: -f1`; \
+	  echo QUADMATH_SONAME=$$v >> $$cache; \
+	v=`grep '[^_]Library_Version.*:' $(srcdir)/gcc/ada/gnatvsn.ads \
+		| sed -e 's/.*"\([^"]*\)".*/\1/'`; \
+	echo GNAT_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libgo/configure.ac`; \
+	echo GO_SONAME=$$v >> $$cache; \
+	echo ITM_SONAME=1 >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libvtv/configure.ac`; \
+	v=0; \
+	echo VTV_SONAME=$$v >> $$cache; \
+	echo CILKRTS_SONAME=5 >> $$cache; \
+	echo CC1_SONAME=0 >> $$cache; \
+	echo GCCJIT_SONAME=0 >> $$cache; \
+	v=`tail -1 $(srcdir)/libmpx/mpxrt/libtool-version | cut -d: -f1`; \
+	echo MPX_SONAME=$$v >> $$cache; \
+	echo GPHOBOS_SONAME=68 >> $$cache; \
+	echo GDRUNTIME_SONAME=68 >> $$cache; \
+	cat $$cache)
+else
+  SONAME_VARS := $(shell cat debian/soname-cache)
+endif
+CXX_SONAME	= $(call vafilt,$(SONAME_VARS),CXX_SONAME)
+OBJC_SONAME	= $(call vafilt,$(SONAME_VARS),OBJC_SONAME)
+FORTRAN_SONAME	= $(call vafilt,$(SONAME_VARS),FORTRAN_SONAME)
+SSP_SONAME	= $(call vafilt,$(SONAME_VARS),SSP_SONAME)
+GCJ_SONAME	= $(call vafilt,$(SONAME_VARS),GCJ_SONAME)
+GCJ_SONAME1	= $(call vafilt,$(SONAME_VARS),GCJ_SONAME1)
+GCJ_SONAME2	= $(call vafilt,$(SONAME_VARS),GCJ_SONAME2)
+FFI_SONAME	= $(call vafilt,$(SONAME_VARS),FFI_SONAME)
+GOMP_SONAME	= $(call vafilt,$(SONAME_VARS),GOMP_SONAME)
+ATOMIC_SONAME	= $(call vafilt,$(SONAME_VARS),ATOMIC_SONAME)
+BTRACE_SONAME	= $(call vafilt,$(SONAME_VARS),BTRACE_SONAME)
+ASAN_SONAME	= $(call vafilt,$(SONAME_VARS),ASAN_SONAME)
+LSAN_SONAME	= $(call vafilt,$(SONAME_VARS),LSAN_SONAME)
+TSAN_SONAME	= $(call vafilt,$(SONAME_VARS),TSAN_SONAME)
+UBSAN_SONAME	= $(call vafilt,$(SONAME_VARS),UBSAN_SONAME)
+VTV_SONAME	= $(call vafilt,$(SONAME_VARS),VTV_SONAME)
+CILKRTS_SONAME	= $(call vafilt,$(SONAME_VARS),CILKRTS_SONAME)
+QUADMATH_SONAME	= $(call vafilt,$(SONAME_VARS),QUADMATH_SONAME)
+GNAT_SONAME	= $(call vafilt,$(SONAME_VARS),GNAT_SONAME)
+GO_SONAME	= $(call vafilt,$(SONAME_VARS),GO_SONAME)
+ITM_SONAME	= $(call vafilt,$(SONAME_VARS),ITM_SONAME)
+CC1_SONAME	= $(call vafilt,$(SONAME_VARS),CC1_SONAME)
+GCCJIT_SONAME	= $(call vafilt,$(SONAME_VARS),GCCJIT_SONAME)
+MPX_SONAME	= $(call vafilt,$(SONAME_VARS),MPX_SONAME)
+GPHOBOS_SONAME	= $(call vafilt,$(SONAME_VARS),GPHOBOS_SONAME)
+GDRUNTIME_SONAME= $(call vafilt,$(SONAME_VARS),GDRUNTIME_SONAME)
+
+# alias
+GFORTRAN_SONAME = $(FORTRAN_SONAME)
+STDC++_SONAME = $(CXX_SONAME)
--- gcc-6-6.3.0.orig/debian/rules.source
+++ gcc-6-6.3.0/debian/rules.source
@@ -0,0 +1,15 @@
+SOURCE_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
+patchdir = $(SOURCE_DIR)/patches
+
+include $(SOURCE_DIR)/debian/rules.defs
+include $(SOURCE_DIR)/debian/rules.patch
+include $(SOURCE_DIR)/debian/rules.unpack
+
+patch-source: $(patch_stamp)
+
+clean-source:
+	rm -rf $(stampdir)
+	rm -rf $(gcc_srcdir) $(gdc_srcdir)
+	rm -rf bin
+	rm -rf $(srcdir)
+
--- gcc-6-6.3.0.orig/debian/rules.unpack
+++ gcc-6-6.3.0/debian/rules.unpack
@@ -0,0 +1,246 @@
+# -*- makefile -*-
+# rules to unpack the source tarballs in $(srcdir); if the source dir already
+# exists, the rule exits with an error to prevent deletion of modified
+# source files. It has to be deleted manually.
+
+tarballs = $(gcc_tarball) # $(gcj_tarball)
+ifeq ($(with_d),yes)
+  tarballs += $(gdc_tarball)
+endif
+
+unpack_stamps = $(foreach i,$(tarballs),$(unpack_stamp)-$(i))
+
+unpack: stamp-dir $(unpack_stamp) debian-chmod
+$(unpack_stamp): $(unpack_stamps)
+$(unpack_stamp): $(foreach p,$(debian_tarballs),unpacked-$(p))
+	echo -e "\nBuilt from Debian source package $(PKGSOURCE)-$(SOURCE_VERSION)" \
+		> pxxx
+	echo -e "Integrated upstream packages in this version:\n" >> pxxx
+	for i in $(tarballs); do echo "  $$i" >> pxxx; done
+	mv -f pxxx $@
+
+debian-chmod:
+	@chmod 755 debian/dh_*
+
+# ---------------------------------------------------------------------------
+
+gfdl_texinfo_files = \
+	gcc/doc/avr-mmcu.texi \
+	gcc/doc/bugreport.texi \
+	gcc/doc/cfg.texi \
+	gcc/doc/collect2.texi \
+	gcc/doc/compat.texi \
+	gcc/doc/configfiles.texi \
+	gcc/doc/configterms.texi \
+	gcc/doc/contrib.texi \
+	gcc/doc/contribute.texi \
+	gcc/doc/cpp.texi \
+	gcc/doc/cppenv.texi \
+	gcc/doc/cppinternals.texi \
+	gcc/doc/cppopts.texi \
+	gcc/doc/extend.texi \
+	gcc/doc/fragments.texi \
+	gcc/doc/frontends.texi \
+	gcc/doc/gccint.texi \
+	gcc/doc/gcov.texi \
+	gcc/doc/gcov-tool.texi \
+	gcc/doc/generic.texi \
+	gcc/doc/gimple.texi \
+	gcc/doc/gnu.texi \
+	gcc/doc/gty.texi \
+	gcc/doc/headerdirs.texi \
+	gcc/doc/hostconfig.texi \
+	gcc/doc/implement-c.texi \
+	gcc/doc/implement-cxx.texi \
+	gcc/doc/install-old.texi \
+	gcc/doc/install.texi \
+	gcc/doc/interface.texi \
+	gcc/doc/invoke.texi \
+	gcc/doc/languages.texi \
+	gcc/doc/libgcc.texi \
+	gcc/doc/loop.texi \
+	gcc/doc/lto.texi \
+	gcc/doc/makefile.texi \
+	gcc/doc/match-and-simplify.texi \
+	gcc/doc/md.texi \
+	gcc/doc/objc.texi \
+	gcc/doc/optinfo.texi \
+	gcc/doc/options.texi \
+	gcc/doc/passes.texi \
+	gcc/doc/plugins.texi \
+	gcc/doc/portability.texi \
+	gcc/doc/rtl.texi \
+	gcc/doc/service.texi \
+	gcc/doc/sourcebuild.texi \
+	gcc/doc/standards.texi \
+	gcc/doc/tm.texi.in \
+	gcc/doc/tm.texi \
+	gcc/doc/tree-ssa.texi \
+	gcc/doc/trouble.texi \
+	gcc/doc/include/gcc-common.texi \
+	gcc/doc/include/funding.texi \
+	gcc/fortran/gfc-internals.texi \
+	gcc/fortran/invoke.texi \
+	gcc/fortran/intrinsic.texi \
+
+
+gfdl_toplevel_texinfo_files = \
+	gcc/doc/gcc.texi \
+	gcc/java/gcj.texi \
+	gcc/ada/gnat-style.texi \
+	gcc/ada/gnat_rm.texi \
+	gcc/ada/gnat_ugn.texi \
+	gcc/fortran/gfortran.texi \
+	gcc/go/gccgo.texi \
+	libgomp/libgomp.texi \
+	libquadmath/libquadmath.texi \
+
+gfdl_manpages = \
+	gcc/doc/cpp.1 \
+	gcc/doc/g++.1 \
+	gcc/doc/gc-analyze.1 \
+	gcc/doc/gcc.1 \
+	gcc/doc/gccgo.1 \
+	gcc/doc/gcj.1 \
+	gcc/doc/gcj-dbtool.1 \
+	gcc/doc/gcjh.1 \
+	gcc/doc/gcov.1 \
+	gcc/doc/gcov-tool.1 \
+	gcc/doc/gfortran.1 \
+	gcc/doc/gij.1 \
+	gcc/doc/grmic.1 \
+	gcc/doc/grmiregistry.1 \
+	gcc/doc/jcf-dump.1 \
+	gcc/doc/jv-convert.1 \
+	gcc/doc/fsf-funding.7 \
+
+# ---------------------------------------------------------------------------
+$(unpack_stamp)-$(gcc_tarball): $(gcc_tarpath)
+	: # unpack gcc tarball
+	mkdir -p $(stampdir)
+	if [ -d $(srcdir) ]; then \
+	  echo >&2 "Source directory $(srcdir) exists. Delete by hand"; \
+	  false; \
+	fi
+	rm -rf $(gcc_srcdir)
+	tar -x -f $(gcc_tarpath)
+	mv $(gcc_srcdir) $(srcdir)
+	ln -sf libsanitizer $(srcdir)/libasan
+ifneq (,$(wildcard java-class-files.tar.xz.uue))
+# work around #533356
+#	uudecode -o - java-class-files.tar.xz.uue | tar -C src -xvz
+	uudecode java-class-files.tar.xz.uue
+	xzcat java-class-files.tar.xz | tar -C src -xv -f -
+	rm -f java-class-files.tar.xz
+endif
+#ifeq ($(with_java),yes)
+#	tar -x -C $(srcdir)/libjava/testsuite/libmauve.exp \
+#		$(wildcard /usr/src/mauve*.tar.*)
+#endif
+ifeq (0,1)
+	cd $(srcdir) && tar cfj ../gcc-4.1.1-doc.tar.bz2 \
+		$(gfdl_texinfo_files) \
+		$(gfdl_toplevel_texinfo_files) \
+		$(gfdl_manpages)
+endif
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+  ifneq ($(single_package),yes)
+	rm -f $(srcdir)/gcc/doc/*.1
+	rm -f $(srcdir)/gcc/doc/fsf-funding.7
+	rm -f $(srcdir)/gcc/doc/*.info
+	rm -f $(srcdir)/gcc/fortran/*.info
+	rm -f $(srcdir)/libgomp/*.info
+	rm -f $(srcdir)/gcc/java/*.1
+	rm -f $(srcdir)/gcc/java/*.info
+	for i in $(gfdl_texinfo_files); do \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \
+	  else \
+	    cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in $(gfdl_toplevel_texinfo_files); do \
+	  n=$$(basename $$i .texi); \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	  else \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in $(gfdl_manpages); do \
+	  touch $(srcdir)/$$i; \
+	done
+	rm -f $(srcdir)/INSTALL/*.html
+	rm -f $(srcdir)/zlib/contrib/dotzlib/DotZLib.chm
+  endif
+endif
+	echo "$(gcc_tarball) unpacked." > $@
+
+# ---------------------------------------------------------------------------
+ifneq (,$(gcj_tarball))
+$(unpack_stamp)-$(gcj_tarball): $(gcj_tarpath) $(unpack_stamp)-$(gcc_tarball)
+	: # unpack gcj tarball
+	rm -rf $(srcdir)/gcc/java $(srcdir)/libjava
+	tar -x -C $(srcdir) -f $(gcj_tarpath)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+  ifneq ($(single_package),yes)
+	rm -f $(srcdir)/gcc/java/*.1
+	rm -f $(srcdir)/gcc/java/*.info
+	for i in $(gfdl_texinfo_files); do \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \
+	  else \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in $(gfdl_toplevel_texinfo_files); do \
+	  n=$$(basename $$i .texi); \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	  else \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+  endif
+endif
+	echo "$(gcj_tarball) unpacked." > $@
+endif
+
+# ---------------------------------------------------------------------------
+ifneq (,$(gdc_tarball))
+$(unpack_stamp)-$(gdc_tarball): $(gdc_tarpath) $(unpack_stamp)-$(gcc_tarball)
+	: # unpack gdc tarball
+	mkdir -p $(stampdir)
+	if [ -d $(srcdir)/gcc/d ]; then \
+	  echo >&2 "Source directory $(srcdir)/gcc/d exists. Delete by hand";\
+	  false; \
+	fi
+	#rm -rf $(gdc_srcdir)
+	rm -rf $(srcdir)/gcc/d
+	rm -rf $(srcdir)/gcc/testsuite/gdc.test
+	rm -f $(srcdir)/gcc/testsuite/lib/gdc*.exp
+	rm -rf $(srcdir)/libphobos
+	tar -x -C $(srcdir) --strip-components=1 -f $(gdc_tarpath)
+ifeq ($(GFDL_INVARIANT_FREE),yes-now-purge-gfdl)
+  ifneq ($(single_package),yes)
+	for i in gcc/d/gdc.texi; do \
+	  n=$$(basename $$i .texi); \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	  else \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in gcc/d/gdc.1; do \
+	  touch $(srcdir)/$$i; \
+	done
+  endif
+endif
+	echo "$(gdc_tarball) unpacked." > $@
+endif
--- gcc-6-6.3.0.orig/debian/rules2
+++ gcc-6-6.3.0/debian/rules2
@@ -0,0 +1,2591 @@
+#! /usr/bin/make -f
+# -*- makefile -*-
+
+# Uncomment this to turn on verbose mode.
+#export DH_VERBOSE=1
+
+.SUFFIXES:
+
+include debian/rules.defs
+include debian/rules.parameters
+
+dh_compat2 := $(shell dpkg --compare-versions "$$(dpkg-query -f '$${Version}' -W debhelper)" lt 9.20150811ubuntu2 \
+			&& echo DH_COMPAT=2)
+
+# some tools
+SHELL	= /bin/bash -e		# brace expansion in rules file
+IR	= install -m 644	# Install regular file
+IP	= install -m 755	# Install program
+IS	= install -m 755	# Install script
+
+# kernel-specific ulimit hack
+ifeq ($(findstring linux,$(DEB_HOST_GNU_SYSTEM)),linux)
+  ULIMIT_M =  if [ -e /proc/meminfo ]; then \
+	    m=`awk '/^((Mem|Swap)Free|Cached)/{m+=$$2}END{print int(m*.9)}' \
+		/proc/meminfo`; \
+	  else \
+	    m=`vmstat --free --swap-free --kilobytes|awk '{m+=$$2}END{print int(m*.9)}'`; \
+	  fi; \
+	  echo "Limiting memory for test runs to $${m}kB"; \
+	  if ulimit -m $$m; then \
+	    echo "  limited to `ulimit -m`kB"; \
+	  else \
+	    echo "  failed"; \
+	  fi
+else
+  ULIMIT_M = true
+endif
+
+ifeq ($(locale_data),generate)
+  SET_LOCPATH = LOCPATH=$(CURDIR)/locales
+endif
+
+SET_PATH = PATH=$(CURDIR)/bin:/usr/$(libdir)/gcc/bin:$$PATH
+ifeq ($(trunk_build),yes)
+  ifneq (,$(findstring sparc64-linux,$(DEB_TARGET_GNU_TYPE)))
+    SET_PATH = PATH=/usr/lib/gcc-snapshot/bin:$(CURDIR)/bin:/usr/$(libdir)/gcc/bin:$$PATH
+  endif
+  ifneq (,$(findstring ppc64-linux,$(DEB_TARGET_GNU_TYPE)))
+    SET_PATH = PATH=/usr/lib/gcc-snapshot/bin:$(CURDIR)/bin:/usr/$(libdir)/gcc/bin:$$PATH
+  endif
+endif
+
+# the recipient for the test summaries. Send with: debian/rules mail-summary
+S_EMAIL = gcc@packages.debian.org gcc-testresults@gcc.gnu.org
+
+# build not yet prepared to take variables from the environment
+define unsetenv
+  unexport $(1)
+  $(1) =
+endef
+$(foreach v, CPPFLAGS CFLAGS CXXFLAGS DFLAGS FFLAGS FCFLAGS LDFLAGS OBJCFLAGS OBJCXXFLAGS GCJFLAGS, $(if $(filter environment,$(origin $(v))),$(eval $(call unsetenv, $(v)))))
+
+CC = $(notdir $(firstword $(wildcard \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gcc-6 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gcc-5 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gcc)))
+CXX = $(notdir $(firstword $(wildcard \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-g++-6 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-g++-5 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-g++)))
+ifeq ($(with_ada),yes)
+  GNAT = $(notdir $(firstword $(wildcard \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gnat-6 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gnat-5 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gnat /usr/bin/gnatgcc)))
+  ifeq ($(GNAT),gnatgcc)
+    CC := $(shell readlink /usr/bin/gnatgcc)
+  else ifneq (,$(GNAT))
+    CC = $(subst gnat,gcc,$(GNAT))
+  else ifneq (,$(filter $(distrelease), trusty))
+    CC = gcc-4.8
+  else ifneq (,$(wildcard /usr/bin/$(DEB_HOST_GNU_TYPE)-gcc))
+    CC = $(DEB_HOST_GNU_TYPE)-gcc
+  else
+    CC = gcc
+  endif
+  CXX = $(subst gcc,g++,$(CC))
+endif
+
+ifneq (,$(filter $(build_type),cross-build-native cross-build-cross))
+  SET_TARGET_TOOLS = \
+	CC_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gcc-$(BASE_VERSION) \
+	CXX_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-g++-$(BASE_VERSION) \
+	GFORTRAN_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gfortran-$(BASE_VERSION) \
+	GCJ_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gcj-$(BASE_VERSION) \
+	GOC_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gccgo-$(BASE_VERSION) \
+	GNAT_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gnat-$(BASE_VERSION) \
+	GDC_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gdc-$(BASE_VERSION)
+endif
+
+ifeq ($(DEB_BUILD_GNU_TYPE),$(DEB_TARGET_GNU_TYPE))
+  CC_FOR_TARGET = $(builddir)/gcc/xgcc -B$(builddir)/gcc/
+else
+  CC_FOR_TARGET = $(DEB_TARGET_GNU_TYPE)-gcc
+endif
+
+ifneq ($(derivative),Ubuntu)
+  ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel mips mipsel))
+    STAGE1_CFLAGS = -g -O2
+  endif
+endif
+
+# work around PR 57689
+ifeq ($(DEB_TARGET_ARCH),ia64)
+  BOOT_CFLAGS	= -g -O1
+endif
+
+ifeq ($(with_ssp_default),yes)
+  STAGE1_CFLAGS	= -g
+  ifeq (,$(BOOT_CFLAGS))
+    BOOT_CFLAGS	= -g -O2
+  endif
+  LIBCFLAGS		= -g -O2
+  LIBCXXFLAGS	= -g -O2 -fno-implicit-templates
+  # Only use -fno-stack-protector when known to the stage1 compiler.
+  cc-fno-stack-protector := $(shell if $(CC) $(CFLAGS) -fno-stack-protector \
+                             -S -o /dev/null -xc /dev/null > /dev/null 2>&1; \
+							 then echo "-fno-stack-protector"; fi;)
+  $(foreach var,STAGE1_CFLAGS BOOT_CFLAGS LIBCFLAGS LIBCXXFLAGS,$(eval \
+    $(var) += $(cc-fno-stack-protector)))
+endif
+
+# FIXME: passing LDFLAGS for native doesn't do anything
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  CFLAGS	= -g -O2
+  LDFLAGS	= -Wl,-z,relro
+  ifeq ($(DEB_TARGET_ARCH),alpha)
+    LDFLAGS += -Wl,--no-relax
+  endif
+else
+  BOOT_LDFLAGS	= -Wl,-z,relro
+  ifeq ($(DEB_TARGET_ARCH),alpha)
+    BOOT_LDFLAGS += -Wl,--no-relax
+  endif
+endif
+LDFLAGS_FOR_TARGET = -Wl,-z,relro
+ifeq ($(DEB_TARGET_ARCH),alpha)
+  LDFLAGS := $(filter-out -Wl$(COMMA)--no-relax, $(LDFLAGS)) -Wl,--no-relax
+endif
+
+ifneq (,$(findstring static,$(DEB_BUILD_OPTIONS)))
+  LDFLAGS	+= -static
+endif
+
+ifneq ($(findstring gccdebug, $(DEB_BUILD_OPTIONS)),)
+  CFLAGS		= -O0 -g3 -fno-inline
+  CXXFLAGS		= -O0 -g3 -fno-inline
+  CFLAGS_FOR_BUILD	= -O0 -g3 -fno-inline
+  CXXFLAGS_FOR_BUILD	= -O0 -g3 -fno-inline
+  CFLAGS_FOR_TARGET	= -O0 -g3 -fno-inline
+  CXXFLAGS_FOR_TARGET	= -O0 -g3 -fno-inline
+  BOOT_CFLAGS		=
+  BOOT_LDFLAGS		=
+  STAGE1_CFLAGS		=
+  STAGE1_LDFLAGS	=
+endif
+
+# set CFLAGS/LDFLAGS for the configure step only, maybe be modifed for some target
+# all other flags are passed to the make step.
+CFLAGS_TO_PASS = \
+	$(if $(CFLAGS),CFLAGS="$(CFLAGS)") \
+	$(if $(CXXFLAGS),CXXFLAGS="$(CXXFLAGS)") \
+	$(if $(LIBCFLAGS),LIBCFLAGS="$(LIBCFLAGS)") \
+	$(if $(LIBCXXFLAGS),LIBCXXFLAGS="$(LIBCXXFLAGS)")
+LDFLAGS_TO_PASS = \
+	$(if $(LDFLAGS),LDFLAGS="$(LDFLAGS)")
+
+STAGE1_CFLAGS_TO_PASS = \
+	$(if $(STAGE1_CFLAGS),STAGE1_CFLAGS="$(STAGE1_CFLAGS)")
+STAGE1_LDFLAGS_TO_PASS = \
+	$(if $(STAGE1_LDFLAGS),STAGE1_LDFLAGS="$(STAGE1_LDFLAGS)")
+
+BOOT_CFLAGS_TO_PASS = \
+	$(if $(BOOT_CFLAGS),BOOT_CFLAGS="$(BOOT_CFLAGS)")
+BOOT_LDFLAGS_TO_PASS = \
+	$(if $(BOOT_LDFLAGS),BOOT_LDFLAGS="$(BOOT_LDFLAGS)")
+
+CFLAGS_FOR_BUILD_TO_PASS = \
+	$(if $(CFLAGS_FOR_BUILD),CFLAGS_FOR_BUILD="$(CFLAGS_FOR_BUILD)")
+CXXFLAGS_FOR_BUILD_TO_PASS = \
+	$(if $(CXXFLAGS_FOR_BUILD),CXXFLAGS_FOR_BUILD="$(CXXFLAGS_FOR_BUILD)")
+LDFLAGS_FOR_BUILD_TO_PASS = \
+	$(if $(LDFLAGS_FOR_BUILD),LDFLAGS_FOR_BUILD="$(LDFLAGS_FOR_BUILD)")
+
+CFLAGS_FOR_TARGET_TO_PASS = \
+	$(if $(CFLAGS_FOR_TARGET),CFLAGS_FOR_TARGET="$(CFLAGS_FOR_TARGET)")
+CXXFLAGS_FOR_TARGET_TO_PASS = \
+	$(if $(CXXFLAGS_FOR_TARGET),CXXFLAGS_FOR_TARGET="$(CXXFLAGS_FOR_TARGET)")
+LDFLAGS_FOR_TARGET_TO_PASS = \
+	$(if $(LDFLAGS_FOR_TARGET),LDFLAGS_FOR_TARGET="$(LDFLAGS_FOR_TARGET)")
+
+docdir		= usr/share/doc
+
+CONFARGS = -v \
+	--with-pkgversion='$(distribution)$(if $(with_linaro_branch),/Linaro)$(if $(with_ibm_branch),/IBM)___$(DEB_VERSION)' \
+	--with-bugurl='file:///usr/share/doc/$(subst gcj,gcc,$(PKGSOURCE))/README.Bugs'
+
+CONFARGS += \
+	--enable-languages=$(subst $(SPACE),$(COMMA),$(enabled_languages)) \
+	--prefix=/$(PF)
+
+ifeq ($(versioned_packages),yes)
+  CONFARGS += --program-suffix=-$(BASE_VERSION)
+endif
+ifeq ($(build_type),build-native)
+  CONFARGS += --program-prefix=$(cmd_prefix)
+endif
+
+ifneq (,$(filter $(DEB_STAGE),stage1 stage2))
+  CONFARGS += \
+	--disable-decimal-float \
+	--disable-libatomic \
+	--disable-libgomp \
+	--disable-libmpx \
+	--disable-libssp \
+	--disable-libquadmath \
+	--disable-libsanitizer \
+	--disable-threads \
+	--libexecdir=/$(libexecdir) \
+	--libdir=/$(PF)/$(configured_libdir) \
+	$(if $(with_build_sysroot),--with-build-sysroot=$(with_build_sysroot)) \
+	$(if $(with_sysroot),--with-sysroot=$(with_sysroot)) \
+	--enable-linker-build-id
+
+  ifeq ($(with_multiarch_lib),yes)
+    CONFARGS += \
+	--enable-multiarch
+  endif
+
+  ifeq ($(DEB_STAGE),stage1)
+    CONFARGS += \
+	--disable-shared  \
+	--with-newlib  \
+	--without-headers
+  else
+    # stage2
+    CONFARGS += \
+	--enable-shared
+  endif
+else
+  CONFARGS += \
+	--enable-shared \
+	--enable-linker-build-id \
+
+ifneq ($(single_package),yes)
+  CONFARGS += \
+        --libexecdir=/$(libexecdir) \
+        --without-included-gettext \
+        --enable-threads=posix \
+	--libdir=/$(PF)/$(configured_libdir)
+endif
+
+ifneq ($(with_cpp),yes)
+  CONFARGS += --disable-cpp
+endif
+
+ifeq ($(with_nls),yes)
+  CONFARGS += --enable-nls
+else
+  CONFARGS += --disable-nls
+endif
+
+ifeq ($(with_bootstrap),off)
+  CONFARGS += --disable-bootstrap
+else ifneq ($(with_bootstrap),)
+  CONFARGS += --enable-bootstrap=$(with_bootstrap)
+endif
+
+ifneq ($(with_sysroot),)
+  CONFARGS += --with-sysroot=$(with_sysroot)
+endif
+ifneq ($(with_build_sysroot),)
+  CONFARGS += --with-build-sysroot=$(with_build_sysroot)
+endif
+
+ifeq ($(force_gnu_locales),yes)
+  CONFARGS += --enable-clocale=gnu
+endif
+
+ifeq ($(with_cxx)-$(with_cxx_debug),yes-yes)
+  CONFARGS += --enable-libstdcxx-debug
+endif
+CONFARGS += --enable-libstdcxx-time=yes
+CONFARGS += --with-default-libstdcxx-abi=$(libstdcxx_abi)
+ifeq ($(libstdcxx_abi),gcc4-compatible)
+  CONFARGS += --disable-libstdcxx-dual-abi
+endif
+
+ifeq (,$(filter $(DEB_TARGET_ARCH), hurd-i386 kfreebsd-i386 kfreebsd-amd64))
+  CONFARGS += --enable-gnu-unique-object
+endif
+
+ifneq ($(with_ssp),yes)
+  CONFARGS += --disable-libssp
+endif
+
+ifneq ($(with_gomp),yes)
+  CONFARGS += --disable-libgomp
+endif
+
+ifneq ($(with_itm),yes)
+  CONFARGS += --disable-libitm
+endif
+
+ifneq ($(with_atomic),yes)
+  CONFARGS += --disable-libatomic
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(vtv_archs)))
+  ifeq ($(with_vtv),yes)
+    CONFARGS += --enable-vtable-verify
+  else
+    CONFARGS += --disable-vtable-verify
+  endif
+endif
+
+ifneq ($(with_asan),yes)
+  CONFARGS += --disable-libsanitizer
+endif
+
+ifneq ($(with_qmath),yes)
+  CONFARGS += --disable-libquadmath
+endif
+
+ifeq ($(with_mpx),yes)
+  CONFARGS += --enable-libmpx
+endif
+
+ifeq ($(with_plugins),yes)
+  CONFARGS += --enable-plugin
+endif
+
+#ifeq ($(with_gold),yes)
+#  CONFARGS += --enable-gold --enable-ld=default
+#endif
+
+#CONFARGS += --with-plugin-ld=ld.gold
+#CONFARGS += --with-plugin-ld
+
+# enable pie-by-default on pie_archs
+ifeq ($(with_pie),yes)
+  CONFARGS += --enable-default-pie
+endif
+
+endif # !DEB_STAGE
+
+CONFARGS += --with-system-zlib
+
+jvm_name_short = java-1.5.0-gcj-$(BASE_VERSION)$(if $(findstring snap,$(PKGSOURCE)),-snap)
+jvm_name_long = $(jvm_name_short)-1.5.0.0
+
+ifeq ($(with_java),yes)
+  CONFARGS += --disable-browser-plugin
+  ifeq ($(with_java_maintainer_mode),yes)
+    CONFARGS += --enable-java-maintainer-mode
+  endif
+  ifeq ($(with_java_biarch_awt),yes)
+    CONFARGS += --enable-java-awt=$(subst $(SPACE),$(COMMA),$(foreach p,$(java_awt_peers),$(p)-default))
+  else
+    CONFARGS += --enable-java-awt=$(subst $(SPACE),$(COMMA),$(foreach p,$(java_awt_peers),$(p)))
+  endif
+  ifneq (,$(findstring gtk,$(java_awt_peers)))
+    CONFARGS += --enable-gtk-cairo
+  endif
+  jvm_ext = -$(DEB_TARGET_ARCH)$(if $(filter yes,$(DEB_CROSS)),-cross)
+  jvm_dir = /usr/lib/jvm/$(jvm_name_short)$(jvm_ext)
+  CONFARGS += --with-java-home=$(jvm_dir)/jre
+  CONFARGS += --enable-java-home \
+	--with-jvm-root-dir=$(jvm_dir) \
+	--with-jvm-jar-dir=/usr/lib/jvm-exports/$(jvm_name_short)$(jvm_ext)
+  CONFARGS += --with-arch-directory=$(java_cpu)
+  ifeq (./,$(dir $(ecj_jar)))
+    CONFARGS += --with-ecj-jar=$(jvm_dir)/lib/ecj.jar
+  else
+    CONFARGS += --with-ecj-jar=$(ecj_jar)
+  endif
+  ifneq ($(with_libgcj),yes)
+    CONFARGS += --disable-libgcj
+  endif
+endif
+
+ifeq ($(with_gcj),yes)
+  ifeq ($(DEB_HOST_GNU_CPU),m32r)
+    CONFARGS += --enable-libgcj
+  endif
+endif
+
+ifeq ($(with_libphobos),yes)
+  CONFARGS += --with-target-system-zlib
+endif
+
+ifeq ($(with_objc)-$(with_objc_gc),yes-yes)
+  CONFARGS += --enable-objc-gc=auto
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), i486-linux-gnu i586-linux-gnu i686-linux-gnu))
+    ifeq ($(multilib),yes)
+      ifeq ($(biarch64),yes)
+        CONFARGS += --enable-targets=all
+      endif
+    endif
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), x86_64-linux-gnu x86_64-linux-gnux32 x86_64-kfreebsd-gnu s390x-linux-gnu sparc64-linux-gnu))
+    ifneq ($(biarch32),yes)
+      CONFARGS += --disable-multilib
+    endif
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), powerpc-linux-gnu powerpc-linux-gnuspe))
+    CONFARGS += --enable-secureplt
+    ifeq ($(biarch64),yes)
+      CONFARGS += --disable-softfloat --with-cpu=default32
+      ifeq ($(multilib),yes)
+        CONFARGS += --disable-softfloat \
+	  --enable-targets=powerpc-linux,powerpc64-linux
+      endif
+    else
+      CONFARGS += --disable-multilib
+    endif
+endif
+
+ifneq (,$(findstring powerpc64le-linux,$(DEB_TARGET_GNU_TYPE)))
+    CONFARGS += --enable-secureplt
+    ifneq (,$(filter $(distrelease),jessie trusty utopic vivid wily))
+      CONFARGS += --with-cpu=power7 --with-tune=power8
+    else
+      CONFARGS += --with-cpu=power8
+    endif
+    CONFARGS += --enable-targets=powerpcle-linux
+    CONFARGS += --disable-multilib
+endif
+
+ifneq (,$(findstring powerpc64-linux,$(DEB_TARGET_GNU_TYPE)))
+    CONFARGS += --enable-secureplt
+    ifeq ($(biarch32),yes)
+      ifeq ($(multilib),yes)
+        CONFARGS += --disable-softfloat --enable-targets=powerpc64-linux,powerpc-linux
+      endif
+    else
+      CONFARGS += --disable-multilib
+    endif
+    ifeq ($(derivative),Ubuntu)
+      CONFARGS += --with-cpu-32=power7 --with-cpu-64=power7
+    endif
+endif
+
+# FIXME: only needed for isl-0.13 for now
+#CONFARGS += --disable-isl-version-check
+
+ifneq (,$(findstring cross-build-,$(build_type)))
+  # FIXME: requires isl headers for the target
+  #CONFARGS += --without-isl
+  # FIXME: build currently fails build the precompiled headers
+  CONFARGS += --disable-libstdcxx-pch
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  CONFARGS += --enable-multiarch
+endif
+
+ifneq (,$(findstring aarch64,$(DEB_TARGET_GNU_CPU)))
+  # requires binutils 2.25.90 or newer
+  ifeq (,$(filter $(distrelease),squeeze precise trusty utopic vivid wily))
+    CONFARGS += --enable-fix-cortex-a53-843419
+  endif
+endif
+
+ifeq ($(findstring powerpcspe,$(DEB_TARGET_ARCH)),powerpcspe)
+  CONFARGS += --with-cpu=8548 --enable-e500_double
+endif
+
+ifneq (,$(findstring softfloat,$(DEB_TARGET_GNU_CPU)))
+  CONFARGS += --with-float=soft
+endif
+
+ifneq (,$(findstring arm-vfp,$(DEB_TARGET_GNU_CPU)))
+  CONFARGS += --with-fpu=vfp
+endif
+
+ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU)))
+  ifeq ($(multilib),yes)
+    CONFARGS += --enable-multilib
+  endif
+  CONFARGS += --disable-sjlj-exceptions
+  # FIXME: libjava is not ported for thumb, this hack only works for
+  # separate gcj builds
+  ifneq (,$(filter %armhf,$(DEB_TARGET_ARCH)))
+    ifeq ($(distribution),Raspbian)
+      with_arm_arch = armv6
+      with_arm_fpu = vfp
+    else
+      ifneq (,$(findstring gcj,$(PKGSOURCE)))
+        with_arm_arch = armv6
+      else
+        with_arm_arch = armv7-a
+      endif
+      with_arm_fpu = vfpv3-d16
+    endif
+  else
+    # armel
+    ifeq ($(derivative),Debian)
+      with_arm_arch = armv4t
+    else ifneq (,$(filter $(distrelease),karmic))
+      with_arm_arch = armv6
+      with_arm_fpu = vfpv3-d16
+    else ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+      ifneq (,$(findstring gcj,$(PKGSOURCE)))
+        with_arm_arch = armv6
+      else
+        with_arm_arch = armv7-a
+      endif
+      with_arm_fpu = vfpv3-d16
+    else
+      with_arm_arch = armv5t  # starting with quantal
+    endif
+  endif
+  CONFARGS += --with-arch=$(with_arm_arch)
+  ifneq (,$(with_arm_fpu))
+    CONFARGS += --with-fpu=$(with_arm_fpu)
+  endif
+  CONFARGS += --with-float=$(float_abi)
+  ifeq ($(with_arm_thumb),yes)
+    CONFARGS += --with-mode=thumb
+  endif
+endif
+
+ifeq ($(DEB_TARGET_GNU_CPU),$(findstring $(DEB_TARGET_GNU_CPU),m68k))
+  CONFARGS += --disable-werror
+endif
+# FIXME: correct fix-warnings.dpatch
+ifeq ($(derivative),Ubuntu)
+  CONFARGS += --disable-werror
+endif
+
+ifneq (,$(findstring sparc-linux,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(biarch64),yes)
+    CONFARGS += --enable-targets=all
+    CONFARGS += --with-cpu-32=ultrasparc
+  else
+    CONFARGS += --with-cpu=ultrasparc
+  endif
+endif
+
+ifneq (,$(findstring sparc64-linux,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(biarch32),yes)
+    CONFARGS += --enable-targets=all
+    CONFARGS += --with-cpu-32=ultrasparc
+  endif
+endif
+
+ifneq (,$(findstring ia64-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-system-libunwind
+endif
+
+ifneq (,$(findstring sh4-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-cpu=sh4 --with-multilib-list=m4,m4-nofpu
+endif
+
+ifneq (,$(findstring m68k-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --disable-multilib
+endif
+
+ifneq (,$(filter tilegx,$(DEB_TARGET_GNU_CPU)))
+  CONFARGS += --disable-multilib
+endif
+
+ifeq ($(derivative),Ubuntu)
+  ifneq (,$(findstring s390x-linux,$(DEB_TARGET_GNU_TYPE)))
+    CONFARGS += --with-arch=zEC12
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH_OS),linux)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH), alpha powerpc powerpcspe ppc64 ppc64el s390 s390x sparc sparc64))
+    CONFARGS += --with-long-double-128
+  endif
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386 kfreebsd-i386 kfreebsd-amd64))
+  ifneq (,$(filter $(derivative),Ubuntu))
+    ifneq (,$(filter $(distrelease),dapper hardy))
+      CONFARGS += --with-arch-32=i486
+    else ifneq (,$(filter $(distrelease),jaunty karmic lucid))
+      CONFARGS += --with-arch-32=i586
+    else
+      CONFARGS += --with-arch-32=i686
+    endif
+  else # Debian
+    ifneq (,$(filter $(distrelease),etch lenny))
+      CONFARGS += --with-arch-32=i486
+    else ifneq (,$(filter $(distrelease),squeeze wheezy jessie))
+      CONFARGS += --with-arch-32=i586
+    else
+      CONFARGS += --with-arch-32=i686
+    endif
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH),amd64)
+  CONFARGS += --with-abi=m64
+endif
+ifeq ($(DEB_TARGET_ARCH),x32)
+  CONFARGS += --with-abi=mx32
+endif
+ifeq ($(multilib),yes)
+  ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386))
+    CONFARGS += --with-multilib-list=m32,m64$(if $(filter yes,$(biarchx32)),$(COMMA)mx32)
+  else ifeq ($(DEB_TARGET_ARCH),x32)
+    CONFARGS += --with-multilib-list=mx32,m64,m32
+  endif
+  CONFARGS += --enable-multilib
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), hurd-i386))
+  CONFARGS += --with-arch=i586
+endif
+
+ifeq ($(DEB_TARGET_ARCH),lpia)
+  CONFARGS += --with-arch=pentium-m --with-tune=i586
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386 hurd-i386 kfreebsd-i386 kfreebsd-amd64))
+  CONFARGS += --with-tune=generic
+endif
+
+ifneq (,$(findstring mips-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+  CONFARGS += --with-lxc1-sxc1=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch64),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mipsel-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+  CONFARGS += --with-madd4=no
+  CONFARGS += --with-lxc1-sxc1=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch64),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+    endif
+  endif
+endif
+
+#FIXME: howto for mipsn32?
+ifneq (,$(findstring mips64el-linux-gnuabin32,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-madd4=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips64-linux-gnuabin32,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips64el-linux-gnuabi64,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  CONFARGS += --with-arch-64=mips64r2
+  CONFARGS += --with-madd4=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips64-linux-gnuabi64,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  CONFARGS += --with-arch-64=mips64r2
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips,$(DEB_TARGET_GNU_TYPE)))
+  ifeq (,$(filter yes,$(biarch32) $(biarchn32) $(biarch64)))
+      CONFARGS += --disable-multilib
+  endif
+endif
+
+ifneq (,$(findstring s390-linux,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(multilib),yes)
+    ifeq ($(biarch64),yes)
+      CONFARGS += --enable-targets=all
+    endif
+  endif
+endif
+
+ifneq (,$(findstring hppa-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --disable-libstdcxx-pch
+endif
+
+ifneq (,$(findstring gdc, $(PKGSOURCE)))
+    CONFARGS += --disable-libquadmath
+endif
+
+ifeq ($(trunk_build),yes)
+  ifeq ($(findstring --disable-werror, $(CONFARGS)),)
+    CONFARGS += --disable-werror
+  endif
+  CONFARGS += --enable-checking=yes
+else
+  CONFARGS += --enable-checking=release
+endif
+
+CONFARGS += \
+	--build=$(DEB_BUILD_GNU_TYPE) \
+	--host=$(DEB_HOST_GNU_TYPE) \
+	--target=$(TARGET_ALIAS)
+
+ifeq ($(DEB_CROSS),yes)
+  CONFARGS += \
+	--program-prefix=$(TARGET_ALIAS)- \
+	--includedir=/$(PFL)/include
+endif
+
+ifeq ($(with_bootstrap),off)
+  bootstrap_target =
+else ifeq ($(with_bootstrap),)
+  bootstrap_target = bootstrap
+  # no profiledbootstrap on the following architectures
+  # - m68k: we're happy that it builds at all
+  no_profiled_bs_archs := alpha arm hppa m68k mips mipsel mips64 mips64el \
+	powerpcspe s390 sh4 sparc sparc64
+  ifeq (,$(filter $(DEB_TARGET_ARCH),$(no_profiled_bs_archs)))
+    bootstrap_target = profiledbootstrap
+  endif
+  ifneq (, $(filter $(PKGSOURCE),gcc-$(BASE_VERSION) gcj-$(BASE_VERSION) gnat-$(BASE_VERSION) gcc-snapshot))
+    bootstrap_target = bootstrap
+  endif
+  ifneq (,$(DEB_STAGE))
+    bootstrap_target = bootstrap
+  endif
+
+  ifeq ($(derivative),Debian)
+    # disable profiled bootstrap for backports
+    ifneq (,$(filter $(distrelease),squeeze wheezy jessie))
+      bootstrap_target = bootstrap
+    endif
+    # disable profiled bootstrap on slow archs, get to testing first ...
+    ifneq (,$(filter $(DEB_TARGET_ARCH), arm arm64 armel armhf mips mipsel sparc))
+      bootstrap_target = bootstrap
+    endif
+  endif
+  ifeq ($(derivative),Ubuntu)
+    ifneq (,$(filter $(distrelease),lucid precise trusty utopic vivid wily))
+      bootstrap_target = bootstrap
+    endif
+    ifeq ($(with_linaro_branch),yes)
+      bootstrap_target = bootstrap
+    endif
+  endif
+endif
+
+DEJAGNU_TIMEOUT=300
+# Increase the timeout for one testrun on slow architectures
+ifeq ($(derivative),Debian)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64))
+    DEJAGNU_TIMEOUT=240
+  else ifneq (,$(findstring $(DEB_TARGET_ARCH),arm armel armhf hppa m68k sparc))
+    DEJAGNU_TIMEOUT=600
+  else ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),amd64 i386 i486 i686 lpia))
+    DEJAGNU_TIMEOUT=180
+  endif
+  ifeq ($(DEB_TARGET_GNU_SYSTEM),gnu)
+    DEJAGNU_TIMEOUT=900
+  endif
+else ifeq ($(derivative),Ubuntu)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64))
+    DEJAGNU_TIMEOUT=240
+  else ifneq (,$(findstring $(DEB_TARGET_ARCH),armel armhf hppa ia64 sparc))
+    DEJAGNU_TIMEOUT=600
+  else ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),amd64 i386 i486 i686 lpia))
+    DEJAGNU_TIMEOUT=180
+  endif
+endif
+
+DEJAGNU_RUNS =
+ifneq ($(trunk_build),yes)
+ifeq ($(with_ssp),yes)
+  # the buildds are just slow ... don't check the non-default
+  ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),sh4 mips))
+    DEJAGNU_RUNS =
+  else ifneq (,$(filter $(DEB_TARGET_ARCH),armel))
+    DEJAGNU_RUNS =
+  else
+    ifneq ($(single_package),yes)
+      DEJAGNU_RUNS += $(if $(filter yes,$(with_ssp_default)),-fno-stack-protector,-fstack-protector)
+    endif
+  endif
+  ifeq ($(derivative),Ubuntu)
+    # the buildds are just slow ... don't check the non-default
+    ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),ia64 sparc))
+      DEJAGNU_RUNS =
+    endif
+    # FIXME Ubuntu armel buildd hangs
+    ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU)))
+      DEJAGNU_RUNS =
+    endif
+  endif
+endif
+endif
+
+ifeq ($(derivative),Ubuntu)
+  ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU)))
+    ifeq ($(with_arm_thumb),yes)
+      #DEJAGNU_RUNS += -marm
+    else
+      DEJAGNU_RUNS += -mthumb
+    endif
+  endif
+endif
+
+# no b-d on g++-multilib, this is run by the built compiler
+abi_run_check = $(strip $(if $(wildcard build/runcheck$(1).out), \
+				$(shell cat build/runcheck$(1).out), \
+				$(shell CC="$(builddir)/gcc/xg++ -B$(builddir)/gcc/ -static-libgcc $(1)" bash debian/runcheck.sh)))
+ifeq ($(biarch32),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,$(if $(filter $(DEB_TARGET_ARCH_CPU),mips64 mips64el mipsn32 mipsn32el),-mabi=32,-m32))
+endif
+ifeq ($(biarch64),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,$(if $(filter $(DEB_TARGET_ARCH_CPU),mips mipsel),-mabi=64,-m64))
+endif
+ifeq ($(biarchn32),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,-mabi=n32)
+endif
+ifeq ($(biarchx32),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,-mx32)
+endif
+
+# gdc is not multilib'd
+ifneq (,$(findstring gdc, $(PKGSOURCE)))
+  DEJAGNU_RUNS =
+endif
+
+ifneq (,$(findstring gcj, $(PKGSOURCE)))
+  DEJAGNU_RUNS =
+endif
+
+# neither is gnat
+ifneq (,$(findstring gnat, $(PKGSOURCE)))
+  DEJAGNU_RUNS =
+endif
+
+ifneq (,$(strip $(value DEJAGNU_RUNS)))
+  RUNTESTFLAGS = RUNTESTFLAGS="--target_board=unix\{,$(subst $(SPACE),$(COMMA),$(strip $(DEJAGNU_RUNS)))\}"
+endif
+
+# PF is the installation prefix for the package without the leading slash.
+# It's "usr" for gcc releases.
+ifneq (,$(PF))
+  # use value set in the environment
+else ifeq ($(trunk_build),yes)
+  PF		= usr/lib/gcc-snapshot
+else ifeq ($(PKGSOURCE),gcc-linaro)
+  PF		= usr/lib/gcc-linaro
+else
+  PF		= usr
+endif
+
+# PFL is the installation prefix with DEB_TARGET_GNU_TYPE attached for cross builds
+ifeq ($(DEB_CROSS),yes)
+  PFL		= $(PF)/$(DEB_TARGET_GNU_TYPE)
+else
+  PFL		= $(PF)
+endif
+
+# RPF is the base prefix or installation prefix with DEB_TARGET_GNU_TYPE attached for cross builds
+ifeq ($(DEB_CROSS),yes)
+  RPF		= $(PF)/$(DEB_TARGET_GNU_TYPE)
+else
+  RPF		=
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  ifeq ($(DEB_CROSS),yes)
+    libdir	= lib
+  else
+    libdir	= lib/$(DEB_TARGET_MULTIARCH)
+  endif
+else
+  libdir	= lib
+endif
+configured_libdir = lib
+
+hppa64libexecdir= $(PF)/lib
+
+# /usr/libexec doesn't follow the FHS
+ifeq ($(single_package),yes)
+  libdir	= lib
+  libexecdir	= $(PF)/libexec
+  versiondir	= $(GCC_VERSION)
+else
+  libexecdir	= $(PF)/$(configured_libdir)
+  versiondir	= $(BASE_VERSION)
+endif
+buildlibdir	= $(builddir)/$(TARGET_ALIAS)
+
+# install cross compilers in /usr/lib/gcc-cross, native ones in /usr/lib/gcc
+gcc_subdir_name = gcc
+ifneq ($(single_package),yes)
+  ifeq ($(DEB_CROSS),yes)
+    gcc_subdir_name = gcc-cross
+  endif
+endif
+
+gcc_lib_dir	= $(PF)/$(configured_libdir)/$(gcc_subdir_name)/$(TARGET_ALIAS)/$(versiondir)
+gcc_lexec_dir	= $(libexecdir)/$(gcc_subdir_name)/$(TARGET_ALIAS)/$(versiondir)
+
+lib32loc   = lib32
+ifneq (,$(findstring mips,$(DEB_TARGET_GNU_TYPE)))
+lib32loc   = libo32
+endif
+lib32      = $(PF)/$(lib32loc)
+lib64		= lib64
+libn32		= lib32
+libx32		= libx32
+
+p_l= $(1)$(cross_lib_arch)
+p_d= $(1)-dbg$(cross_lib_arch)
+d_l= debian/$(p_l)
+d_d= debian/$(p_d)
+
+ifeq ($(DEB_CROSS),yes)
+  usr_lib = $(PFL)/lib
+else
+  usr_lib = $(PFL)/$(libdir)
+endif
+usr_lib32 = $(PFL)/$(lib32loc)
+usr_libn32 = $(PFL)/lib32
+usr_libx32 = $(PFL)/libx32
+usr_lib64 = $(PFL)/lib64
+# FIXME: Move to the new location for native builds too
+ifeq ($(DEB_CROSS),yes)
+  usr_libhf = $(PFL)/libhf
+  usr_libsf = $(PFL)/libsf
+else
+  usr_libhf = $(PFL)/lib/arm-linux-gnueabihf
+  usr_libsf = $(PFL)/lib/arm-linux-gnueabi
+endif
+
+ifeq ($(DEB_STAGE)-$(DEB_CROSS),rtlibs-yes)
+  PFL		= $(PF)
+  RPF		=
+  libdir	= lib/$(DEB_TARGET_MULTIARCH)
+  usr_lib	= $(PF)/lib/$(DEB_TARGET_MULTIARCH)
+endif
+
+gcc_lib_dir32 = $(gcc_lib_dir)/$(biarch32subdir)
+gcc_lib_dirn32 = $(gcc_lib_dir)/$(biarchn32subdir)
+gcc_lib_dirx32 = $(gcc_lib_dir)/$(biarchx32subdir)
+gcc_lib_dir64 = $(gcc_lib_dir)/$(biarch64subdir)
+gcc_lib_dirhf = $(gcc_lib_dir)/$(biarchhfsubdir)
+gcc_lib_dirsf = $(gcc_lib_dir)/$(biarchsfsubdir)
+
+libgcc_dir = $(RPF)/$(libdir)
+# yes, really; lib32gcc_s ends up in usr
+libgcc_dir32 = $(PFL)/$(lib32loc)
+libgcc_dirn32 = $(RPF)/lib32
+# libx32gcc_s also ends up in usr
+libgcc_dirx32 = $(PFL)/libx32
+libgcc_dir64 = $(RPF)/lib64
+# FIXME: Move to the new location for native builds too
+ifeq ($(DEB_CROSS),yes)
+  libgcc_dirhf = $(RPF)/libhf
+  libgcc_dirsf = $(RPF)/libsf
+else
+  libgcc_dirhf = $(RPF)/lib/arm-linux-gnueabihf
+  libgcc_dirsf = $(RPF)/lib/arm-linux-gnueabi
+endif
+
+# install_gcc_lib(lib,soname,flavour,package)
+define install_gcc_lib
+	mv $(d)/$(usr_lib$(3))/$(1)*.a debian/$(4)/$(gcc_lib_dir$(3))/
+	rm -f $(d)/$(usr_lib$(3))/$(1)*.{la,so}
+	dh_link -p$(4) \
+	  /$(usr_lib$(3))/$(1).so.$(2) /$(gcc_lib_dir$(3))/$(1).so
+
+endef
+
+checkdirs = $(builddir)
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    ifneq ($(with_standalone_gcj),yes)
+      checkdirs = $(buildlibdir)/libffi $(buildlibdir)/libjava
+    endif
+  endif
+endif
+ifeq ($(with_separate_go),yes)
+  ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+    checkdirs = $(buildlibdir)/libgo
+  endif
+endif
+ifeq ($(with_separate_gnat),yes)
+  ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+    checkdirs = $(builddir)/gcc
+  endif
+endif
+
+# FIXME: MULTIARCH_DIRNAME needed for g++-multiarch-incdir.diff
+MULTIARCH_DIRNAME := $(DEB_TARGET_MULTIARCH)
+export MULTIARCH_DIRNAME
+
+default: build
+
+configure: $(configure_dependencies)
+
+$(configure_dummy_stamp):
+	touch $(configure_dummy_stamp)
+
+$(configure_stamp):
+	dh_testdir
+	: # give information about the build process
+	@echo "------------------------ Build process variables ------------------------"
+	@echo "Memory on this machine:"
+	@egrep '^(Mem|Swap)' /proc/meminfo || true
+	@echo "Number of parallel processes used for the build: $(USE_CPUS)"
+	@echo "DEB_BUILD_OPTIONS: $$DEB_BUILD_OPTIONS"
+	@echo "Package source: $(PKGSOURCE)"
+	@echo "GCC version: $(GCC_VERSION)"
+	@echo "Base Debian version: $(BASE_VERSION)"
+	@echo -e "Configured with: $(subst ___, ,$(foreach i,$(CONFARGS),$(i)\n\t))"
+ifeq ($(DEB_CROSS),yes)
+	@echo "Building cross compiler for $(DEB_TARGET_ARCH)"
+endif
+	@echo "Using shell $(SHELL)"
+	@echo "Architecture: $(DEB_TARGET_ARCH) (GNU: $(TARGET_ALIAS))"
+	@echo "CPPFLAGS: $(CPPFLAGS)"
+	@echo "CFLAGS: $(CFLAGS)"
+	@echo "LDFLAGS: $(LDFLAGS)"
+	@echo "BOOT_CFLAGS: $(BOOT_CFLAGS)"
+	@echo "DEBIAN_BUILDARCH: $(DEBIAN_BUILDARCH)"
+	@echo "Install prefix: /$(PF)"
+ifeq ($(biarchn32)-$(biarch64),yes-yes)
+	@echo "Will build the triarch compilers (o32/n32/64, defaulting to o32)"
+else ifeq ($(biarchn32)-$(biarch32),yes-yes)
+	@echo "Will build the triarch compilers (o32/n32/64, defaulting to 64)"
+else ifeq ($(biarch64)-$(biarch32),yes-yes)
+	@echo "Will build the triarch compilers (x32/64/32, defaulting to x32)"
+else ifeq ($(biarch64)-$(biarchx32),yes-yes)
+	@echo "Will build the triarch compilers (32/64/x32, defaulting to 32bit)"
+else ifeq ($(biarch32)-$(biarchx32),yes-yes)
+	@echo "Will build the triarch compilers (64/32/x32, defaulting to 64bit)"
+else
+  ifeq ($(biarch64),yes)
+	@echo "Will build the biarch compilers (32/64, defaulting to 32bit)"
+  else
+    ifeq ($(biarch32),yes)
+	@echo "Will build the biarch compilers (64/32, defaulting to 64bit)"
+    else
+	@echo "Will not build the biarch compilers"
+    endif
+  endif
+endif
+
+ifeq ($(with_cxx),yes)
+	@echo "Will build the C++ compiler"
+else
+	@echo "Will not build the C++ compiler: $(with_cxx)"
+endif
+ifeq ($(with_objc),yes)
+	@echo "Will build the ObjC compiler."
+    ifeq ($(with_objc_gc),yes)
+	@echo "Will build the extra ObjC runtime for garbage collection."
+    else
+	@echo "Will not build the extra ObjC runtime for garbage collection."
+    endif
+else
+	@echo "Will not build the ObjC compiler: $(with_objc)"
+endif
+ifeq ($(with_objcxx),yes)
+	@echo "Will build the Obj-C++ compiler"
+else
+	@echo "Will not build the Obj-C++ compiler: $(with_objcxx)"
+endif
+ifeq ($(with_fortran),yes)
+	@echo "Will build the Fortran 95 compiler."
+else
+	@echo "Will not build the Fortran 95 compiler: $(with_fortran)"
+endif
+ifeq ($(with_java),yes)
+	@echo "Will build the Java compiler."
+else
+	@echo "Will not build the Java compiler: $(with_java)"
+endif
+ifeq ($(with_ada),yes)
+	@echo "Will build the Ada compiler."
+  ifeq ($(with_libgnat),yes)
+	@echo "Will build the shared Ada libraries."
+  else
+	@echo "Will not build the shared Ada libraries."
+  endif
+else
+	@echo "Will not build the Ada compiler: $(with_ada)"
+endif
+ifeq ($(with_go),yes)
+	@echo "Will build the Go compiler."
+else
+	@echo "Will not build the Go compiler: $(with_go)"
+endif
+ifeq ($(with_d),yes)
+	@echo "Will build the D compiler"
+  ifeq ($(with_libphobos),yes)
+	@echo "Will build the phobos D runtime library."
+  else
+	@echo "Will not build the phobos D runtime library: $(with_libphobos)"
+  endif
+else
+	@echo "Will not build the D compiler: $(with_d)"
+endif
+ifeq ($(with_ssp),yes)
+	@echo "Will build with SSP support."
+else
+	@echo "Will build without SSP support: $(with_ssp)"
+endif
+ifeq ($(with_check),yes)
+	@echo "Will run the testsuite."
+else
+	@echo "Will not run the testsuite: $(with_check)"
+endif
+ifeq ($(with_nls),yes)
+	@echo "Will enable national language support."
+else
+	@echo "Will disable national language support: $(with_nls)"
+endif
+	@echo "-----------------------------------------------------------------------------"
+	@echo ""
+ifeq ($(with_check),yes)
+	@if echo "spawn true" | /usr/bin/expect -f - >/dev/null; then \
+	  : ; \
+	else \
+	  echo "expect is failing on your system with the above error, which means the GCC"; \
+	  echo "testsuite will fail.  Please resolve the above issues and retry the build."; \
+	  echo "-----------------------------------------------------------------------------"; \
+	  exit 1; \
+	fi
+endif
+	rm -f $(configure_stamp) $(build_stamp)
+	cat debian/README.Debian $(patch_stamp) > debian/README.Debian.$(DEB_TARGET_ARCH)
+
+	rm -rf $(builddir)
+	mkdir $(builddir)
+
+	: # some tools like gettext are built with a newer libstdc++
+	mkdir -p bin
+	for i in msgfmt; do \
+	  install -m755 debian/bin-wrapper.in bin/$$i; \
+	done
+
+	: # configure
+	cd $(builddir) \
+	  && $(SET_PATH) \
+		CC="$(CC)" \
+		CXX="$(CXX)" \
+		$(CFLAGS_TO_PASS) \
+		$(CXXFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_BUILD_TO_PASS) \
+		$(CXXFLAGS_FOR_BUILD_TO_PASS) \
+		$(LDFLAGS_FOR_BUILD_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(CXXFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS) \
+		$(SET_SHELL) $(SET_TARGET_TOOLS) \
+	LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc/ada/rts \
+		../src/configure $(subst ___, ,$(CONFARGS))
+
+	: # multilib builds without b-d on gcc-multilib (used in FLAGS_FOR_TARGET)
+	if [ -d /usr/include/$(DEB_TARGET_MULTIARCH)/asm ]; then \
+	  mkdir -p $(builddir)/sys-include; \
+	  ln -sf /usr/include/$(DEB_TARGET_MULTIARCH)/asm $(builddir)/sys-include/asm; \
+	fi
+
+	touch $(configure_stamp)
+
+build: $(sort $(build_arch_dependencies) $(build_indep_dependencies))
+build-arch: $(build_arch_dependencies)
+build-indep: $(build_indep_dependencies)
+
+$(build_dummy_stamp):
+	touch $(build_dummy_stamp)
+
+$(build_locale_stamp):
+ifeq ($(locale_data)-$(with_cxx),generate-yes)
+	: # build locales needed by libstdc++ testsuite
+	rm -rf locales
+	mkdir locales
+	-USE_CPUS=$(USE_CPUS) sh debian/locale-gen
+endif
+	touch $(build_locale_stamp)
+
+
+$(build_stamp): $(configure_stamp) $(build_locale_stamp)
+	dh_testdir
+	rm -f bootstrap-protocol
+	@echo TTTTT $$(date -R)
+ifeq ($(build_type),build-native)
+	: # native build
+  ifeq ($(with_java),yes)
+	mkdir -p bin
+	ln -sf /usr/bin/fastjar bin/jar
+    ifeq ($(with_native_ecj),yes)
+	: # prepare the standalone ecj jar
+	cp /usr/share/java/ecj.jar $(srcdir)/ecj-standalone.jar
+	zip -d $(srcdir)/ecj-standalone.jar 'org/eclipse/jdt/core/JDTCompilerAdapter*'
+    endif
+    ifeq ($(with_java_maintainer_mode),yes)
+	( \
+	  echo '#!/bin/sh'; \
+	  echo 'exec gij-6 -cp /usr/share/java/ecj.jar org.eclipse.jdt.internal.compiler.batch.GCCMain "$$@"'; \
+	) > bin/ecj1
+	chmod +x bin/ecj1
+	: # If we don't have gjavah in PATH, try to build it with the old gij
+	mkdir -p bin
+	if [ -x /usr/bin/gjavah-6 ]; then \
+	  ln -sf /usr/bin/gjavah-6 bin/gjavah; \
+	elif [ -x bin/gjavah ]; then \
+	  : ; \
+	else \
+	  mkdir -p $(builddir)/java_hacks; \
+	  cd $(builddir)/java_hacks; \
+	  cp -a $(srcdir)/libjava/classpath/tools/external external; \
+	  mkdir -p gnu/classpath/tools; \
+	  cp -a $(srcdir)/libjava/classpath/tools/gnu/classpath/tools/{common,javah,getopt} \
+	    gnu/classpath/tools/; \
+	  cp -a $(srcdir)/libjava/classpath/tools/resource/gnu/classpath/tools/common/Messages.properties \
+	    gnu/classpath/tools/common; \
+	  cd external/asm; \
+	  for i in `find . -name \*.java`; do gcj-6 --encoding ISO-8859-1 -C $$i -I.; done; \
+	  cd ../..; \
+	  for i in `find gnu -name \*.java`; do gcj-6 -C $$i -I. -Iexternal/asm/; done; \
+	  gcj-6 -findirect-dispatch -O2 -fmain=gnu.classpath.tools.javah.Main \
+	    -I. -Iexternal/asm/ `find . -name \*.class` -o $(CURDIR)/bin/gjavah.real; \
+	  ( \
+	    echo '#!/bin/sh'; \
+	    echo 'export CLASSPATH='`pwd`'$${CLASSPATH:+:$$CLASSPATH}'; \
+	    echo 'exec $(CURDIR)/bin/gjavah.real "$$@"'; \
+	  ) > $(CURDIR)/bin/gjavah; \
+	  chmod +x $(CURDIR)/bin/gjavah; \
+	fi
+    endif
+  endif
+	: # build native compiler
+	( \
+	  set +e; \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	    $(MAKE) -C $(builddir) $(bootstrap_target) \
+		CC="$(CC)" \
+		$(STAGE1_CFLAGS_TO_PASS) \
+		$(STAGE1_LDFLAGS_TO_PASS) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_TO_PASS) \
+		$(CXXFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_BUILD_TO_PASS) \
+		$(CXXFLAGS_FOR_BUILD_TO_PASS) \
+		$(LDFLAGS_FOR_BUILD_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(CXXFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS) \
+		; \
+	  echo $$? > status; \
+	) 2>&1 | tee bootstrap-protocol
+else ifneq (,$(filter $(build_type),build-cross cross-build-native cross-build-cross))
+	: # build cross compiler for $(TARGET_ALIAS)
+	( \
+	  set +e; \
+	  $(SET_PATH) \
+	  $(SET_LOCPATH) \
+	    $(MAKE) -C $(builddir) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS) \
+		; \
+	  echo $$? > status; \
+	) 2>&1 | tee bootstrap-protocol
+endif
+	@echo TTTTT $$(date -R)
+	s=`cat status`; rm -f status; \
+	if [ $$s -ne 0 ] && [ -z "$$NO_CONFIG_LOG_DUMP$$NO_CONFIG_LOG_DUMPS" ]; then \
+	  for log in $$(find $(builddir) -name config.log); do \
+	    case "$$log" in */build/build-*|*/stage1-*|*/prev-*) continue; esac; \
+	    echo LOGFILE START $$log; \
+	    cat $$log; \
+	    echo LOGFILE END $$log; \
+	  done; \
+	fi; \
+	test $$s -eq 0
+
+	if [ -f $(srcdir)/contrib/warn_summary ]; then \
+	  rm -f bootstrap-summary; \
+	  /bin/sh $(srcdir)/contrib/warn_summary bootstrap-protocol \
+	    > bootstrap-summary; \
+	fi
+
+	touch $(build_stamp)
+
+ifneq ($(build_type),build-native)
+  BUILT_CC = $(CC)
+  BUILT_CXX = $(CXX)
+else
+  BUILT_CC = $(builddir)/gcc/xgcc -B$(builddir)/gcc/
+  BUILT_CXX = $(builddir)/gcc/xg++ -B$(builddir)/gcc/ \
+	-B$(builddir)/$(TARGET_ALIAS)/libatomic/.libs \
+	-B$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/src/.libs \
+	-B$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/libsupc++/.libs \
+	-I$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/include \
+	-I$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/include/$(TARGET_ALIAS) \
+	-I$(srcdir)/libstdc++-v3/libsupc++ \
+	-L$(builddir)/$(TARGET_ALIAS)/libatomic/.libs \
+	-L$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/src/.libs \
+	-L$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/libsupc++/.libs
+endif
+
+CONFARGS_JIT := \
+	$(filter-out --enable-languages=% \
+		--enable-libstdcxx-debug %bootstrap,\
+	  $(CONFARGS)) \
+	--enable-languages=c++,jit \
+	--enable-host-shared \
+	--disable-bootstrap
+
+$(configure_jit_stamp): $(build_stamp)
+	dh_testdir
+	rm -f $(configure_jit_stamp) $(build_jit_stamp)
+	rm -rf $(builddir_jit)
+	mkdir $(builddir_jit)
+
+	: # configure jit
+	cd $(builddir_jit) && \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  CC="$(BUILT_CC)" \
+	  CXX="$(BUILT_CXX)" \
+	     ../src/configure $(subst ___, ,$(CONFARGS_JIT))
+	touch $(configure_jit_stamp)
+
+$(build_jit_stamp): $(configure_jit_stamp)
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	  LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc \
+	  biarch_multidir_names=none \
+		$(MAKE) -C $(builddir_jit) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS)
+
+ifeq ($(with_check),yes)
+  # FIXME: #782444
+  ifeq (,$(filter $(DEB_TARGET_ARCH), kfreebsd-i386 kfreebsd-amd64))
+	-$(MAKE) -C $(builddir_jit)/gcc check-jit \
+		RUNTESTFLAGS="-v -v"
+  endif
+endif
+
+	touch $(build_jit_stamp)
+
+ifeq ($(versioned_packages),yes)
+  hppa64_configure_flags += --program-suffix=-$(BASE_VERSION)
+endif
+
+$(configure_hppa64_stamp): $(build_stamp)
+	dh_testdir
+	rm -f $(configure_hppa64_stamp) $(build_hppa64_stamp)
+	rm -rf $(builddir_hppa64)
+	mkdir $(builddir_hppa64)
+	: # configure hppa64
+	cd $(builddir_hppa64) && \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  CC="$(BUILT_CC)" \
+	  CXX="$(BUILT_CXX)" \
+	  $(CFLAGS_TO_PASS) \
+	  $(LDFLAGS_TO_PASS) \
+	     ../src/configure \
+		--enable-languages=c \
+		--prefix=/$(PF) \
+		--libexecdir=/$(hppa64libexecdir) \
+		--disable-shared \
+		--disable-nls \
+		--disable-threads \
+		--disable-libatomic \
+		--disable-libgomp \
+		--disable-libitm \
+		--disable-libssp \
+		--disable-libquadmath \
+		--enable-plugin \
+		--with-system-zlib \
+		--with-as=/usr/bin/hppa64-linux-gnu-as \
+		--with-ld=/usr/bin/hppa64-linux-gnu-ld \
+		--includedir=/usr/hppa64-linux-gnu/include \
+		--build=$(DEB_BUILD_GNU_TYPE) \
+		--host=$(DEB_HOST_GNU_TYPE) \
+		--target=hppa64-linux-gnu
+	touch $(configure_hppa64_stamp)
+
+$(build_hppa64_stamp): $(configure_hppa64_stamp)
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	  LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc \
+	    $(MAKE) -C $(builddir_hppa64) \
+		$(if $(CFLAGS_FOR_TARGET),CFLAGS="$(CFLAGS_FOR_TARGET)") \
+		$(if $(CXXFLAGS_FOR_TARGET),CXXFLAGS="$(CXXFLAGS_FOR_TARGET)") \
+		$(if $(LDFLAGS_FOR_TARGET),LDFLAGS="$(LDFLAGS_FOR_TARGET)") \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS)
+	touch $(build_hppa64_stamp)
+
+$(configure_neon_stamp): $(build_stamp)
+	dh_testdir
+	rm -f $(configure_neon_stamp) $(build_neon_stamp)
+	rm -rf $(builddir_neon)
+	mkdir $(builddir_neon)
+	: # configure neon
+	cd $(builddir_neon) && \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(CFLAGS_TO_PASS) \
+	  $(LDFLAGS_TO_PASS) \
+	  CC="$(builddir)/gcc/xg++ -B$(builddir)/gcc/" \
+	     ../src/configure \
+		--disable-bootstrap \
+		--enable-languages=c,c++,objc,fortran \
+		--prefix=/$(PF) \
+		--libexecdir=/$(libexecdir) \
+		--program-suffix=-$(BASE_VERSION) \
+		--disable-nls \
+		--enable-plugin \
+		--with-arch=armv7-a --with-tune=cortex-a8 \
+		--with-float=$(float_abi) --with-fpu=neon \
+		--host=arm-linux-gnueabi \
+		--build=arm-linux-gnueabi \
+		--target=arm-linux-gnueabi
+	touch $(configure_neon_stamp)
+
+$(build_neon_stamp): $(configure_neon_stamp)
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	    $(MAKE) -C $(builddir_neon) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS)
+	touch $(build_neon_stamp)
+
+
+ifeq ($(with_ada),yes)
+  MANUALS = \
+	$(srcdir)/gcc/ada/gnat_ugn.texi \
+	$(srcdir)/gcc/ada/gnat_rm.texi
+endif
+MANUALS += \
+	$(srcdir)/gcc/doc/gccint.texi \
+	$(srcdir)/gcc/doc/gcc.texi \
+	$(srcdir)/gcc/doc/cpp.texi \
+	$(srcdir)/gcc/doc/cppinternals.texi
+ifeq ($(with_fortran),yes)
+  MANUALS += $(srcdir)/gcc/fortran/gfortran.texi
+endif
+ifeq ($(with_java),yes)
+  MANUALS += $(srcdir)/gcc/java/gcj.texi
+endif
+ifeq ($(with_ada),yes)
+  MANUALS += $(srcdir)/gcc/ada/gnat-style.texi
+endif
+ifeq ($(with_gomp),yes)
+  MANUALS += $(srcdir)/libgomp/libgomp.texi
+endif
+ifeq ($(with_itm),yes)
+  MANUALS += $(srcdir)/libitm/libitm.texi
+endif
+ifeq ($(with_qmath),yes)
+  MANUALS += $(srcdir)/libquadmath/libquadmath.texi
+endif
+ifeq ($(with_go),yes)
+  MANUALS += $(srcdir)/gcc/go/gccgo.texi
+endif
+
+html-docs: $(build_html_stamp)
+#$(build_html_stamp): $(stampdir)/05-build-html-split
+$(build_html_stamp): $(stampdir)/05-build-html-nosplit
+
+html-makeinfo-split: $(stampdir)/05-build-html-split
+$(stampdir)/05-build-html-split: $(build_stamp)
+	mkdir -p html
+	rm -f html/*.html
+	cd $(builddir)/gcc; \
+	echo -n $(MANUALS) | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'outname=`basename {} .texi`.html; \
+	  outname=`basename {} .texi`; \
+	  echo "generating $$outname ..."; \
+	  makeinfo --html --number-sections \
+		-I $(srcdir)/gcc/doc/include -I `dirname {}` \
+		-I $(srcdir)/gcc/p/doc \
+		-I $(srcdir)/gcc/p/doc/generated \
+		-I $(builddir)/gcc \
+		-I $(buildlibdir)/libquadmath \
+		-o $${outname} \
+		{}'
+	touch $@
+
+html-makeinfo-nosplit: $(stampdir)/05-build-html-nosplit
+$(stampdir)/05-build-html-nosplit: $(build_stamp)
+	mkdir -p html
+	rm -f html/*.html
+	cd $(builddir)/gcc; \
+	echo -n $(MANUALS) | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'outname=`basename {} .texi`.html; \
+	  echo "generating $$outname ..."; \
+	  makeinfo --html --number-sections --no-split \
+		-I $(srcdir)/gcc/doc/include -I `dirname {}` \
+		-I $(srcdir)/gcc/p/doc \
+		-I $(srcdir)/gcc/p/doc/generated \
+		-I $(builddir)/gcc \
+		-I $(buildlibdir)/libquadmath \
+		-o $(CURDIR)/html/$${outname} \
+		{}'
+	touch $@
+
+# start the script only on architectures known to have slow autobuilders ...
+logwatch_archs := alpha arm m68k mips mipsel mips64el sparc
+ifeq ($(DEB_HOST_GNU_CPU), $(findstring $(DEB_HOST_GNU_CPU),$(logwatch_archs)))
+  start_logwatch = yes
+endif
+ifeq ($(DEB_HOST_GNU_SYSTEM),gnu)
+  start_logwatch = yes
+endif
+
+stamps/mauve-build: stamps/build
+	rm -rf mauve
+	mkdir -p mauve
+ifeq ($(with_mauve_check),yes)
+	tar xf $(wildcard /usr/src/mauve*.tar.*)
+	cd mauve \
+	    && aclocal \
+	    && automake \
+	    && autoconf2.59 \
+	    && PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH ./configure --host=$(DEB_HOST_GNU_TYPE) --build=$(DEB_BUILD_GNU_TYPE)
+	PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH $(MAKE) -C mauve
+endif
+	touch $@
+
+stamps/mauve-check: stamps/build stamps/mauve-build
+ifeq ($(with_mauve_check),yes)
+	-cd mauve && \
+	    JAVA_HOME=$(CURDIR)/$(sdkimg) \
+	    PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH \
+		xvfb-run -s "-extension GLX" java Harness \
+		    -vm $(CURDIR)/$(sdkimg)/bin/java \
+		    -file $(CURDIR)/debian/mauve_tests \
+		    -timeout 30000 2>&1 \
+		| tee mauve_output
+	@sleep 5
+else
+	echo "mauve testsuite not run for this build" > mauve/mauve_output
+endif
+	touch $@
+
+check: $(check_stamp) # $(if $(filter yes, $(with_java)),stamps/05-build-mauve-stamp) #$(check_inst_stamp)
+$(check_stamp): $(filter $(build_stamp) $(build_jit_stamp) $(build_hppa64_stamp), $(build_dependencies))
+	rm -f test-protocol
+	rm -f $(builddir)/runcheck*
+
+	-chmod 755 $(srcdir)/contrib/test_summary
+
+	: # needed for the plugin tests to succeed
+	ln -sf gcc $(builddir)/prev-gcc
+	ln -sf $(DEB_TARGET_GNU_TYPE) $(builddir)/prev-$(DEB_TARGET_GNU_TYPE)
+
+ifneq ($(with_common_libs),yes)
+  ifeq ($(with_cxx),yes)
+	: # libstdc++6 built from newer gcc-X source, run testsuite against the installed lib
+
+	sed 's/-L[^ ]*//g' $(buildlibdir)/libstdc++-v3/scripts/testsuite_flags \
+	  > $(buildlibdir)/libstdc++-v3/scripts/testsuite_flags.installed
+	-$(ULIMIT_M); \
+	    set +e; \
+	    for d in $(buildlibdir)/libstdc++-v3/testsuite; do \
+	      echo "Running testsuite in $$d ..."; \
+	      TEST_INSTALLED=1 \
+	      $(SET_SHELL) \
+	      $(SET_LOCPATH) \
+	      $(SET_PATH) \
+	      DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \
+	      DEB_GCC_NO_O3=1 \
+		$(MAKE) -k -C $$d $(NJOBS) check $(RUNTESTFLAGS); \
+	    done 2>&1 | tee test-protocol2
+
+	BOOT_CFLAGS="$(BOOT_CFLAGS)" \
+	  $(srcdir)/contrib/test_summary -m "$(S_EMAIL)" > raw-test-summary
+	-( \
+	  sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-summary; \
+	  awk '/^cat/, /^EOF/' raw-test-summary | grep -v EOF; \
+	) > libstdc++-test-summary
+	echo 'BEGIN installed libstdc++-v3 test-summary'
+	cat libstdc++-test-summary
+	echo 'END installed libstdc++-v3 test-summary'
+	find $(buildlibdir)/libstdc++-v3/testsuite -name '*.log' -o -name '*.sum' \
+	  | xargs -r rm -f
+  endif
+endif
+
+ifeq ($(start_logwatch),yes)
+	: # start logwatch script for regular output during test runs
+	chmod +x debian/logwatch.sh
+	-debian/logwatch.sh -t 900 -p $(builddir)/logwatch.pid \
+		-m '\ntestsuite still running ...\n' \
+		test-protocol \
+		$(builddir)/gcc/testsuite/gcc/gcc.log \
+		$(builddir)/gcc/testsuite/g++/g++.log \
+		$(builddir)/gcc/testsuite/gfortran/gfortran.log \
+		$(builddir)/gcc/testsuite/objc/objc.log \
+		$(builddir)/gcc/testsuite/obj-c++/obj-c++.log \
+		$(builddir)/gcc/testsuite/gnat/gnat.log \
+		$(builddir)/gcc/testsuite/ada/acats/acats.log \
+		$(builddir)/gcc/testsuite/gfortran/gfortran.log \
+		$(builddir)/gcc/p/test/test_log \
+		$(buildlibdir)/libstdc++-v3/testsuite/libstdc++.log \
+		$(buildlibdir)/libjava/testsuite/libjava.log \
+		$(buildlibdir)/libgomp/testsuite/libgomp.log \
+		$(buildlibdir)/libffi/testsuite/libffi.log \
+		&
+endif
+
+ifeq ($(with_ada),yes)
+	chmod +x debian/acats-killer.sh
+	-debian/acats-killer.sh -p $(builddir)/acats-killer.pid \
+		$(builddir)/gcc/testsuite/ada/acats/acats.log \
+		$(builddir)/gcc/testsuite/g++.log \
+		&
+endif
+
+	-$(ULIMIT_M); \
+	    set +e; \
+	    for d in $(checkdirs); do \
+	      echo "Running testsuite in $$d ..."; \
+	      $(SET_SHELL) \
+	      $(SET_LOCPATH) \
+	      $(SET_PATH) \
+	      EXTRA_TEST_PFLAGS=-g0 \
+	      DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \
+	      DEB_GCC_NO_O3=1 \
+		$(MAKE) -k -C $$d $(NJOBS) check $(RUNTESTFLAGS); \
+	    done 2>&1 | tee test-protocol
+
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+	-if [ -f $(builddir)/logwatch.pid ]; then \
+	  kill -1 `cat $(builddir)/logwatch.pid`; \
+	  sleep 1; \
+	  kill -9 `cat $(builddir)/logwatch.pid`; \
+	  rm -f $(builddir)/logwatch.pid; \
+	fi
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+
+ifeq ($(with_ada),yes)
+	-if [ -f $(builddir)/acats-killer.pid ]; then \
+	  kill -1 `cat $(builddir)/acats-killer.pid`; \
+	  sleep 1; \
+	  kill -9 `cat $(builddir)/acats-killer.pid`; \
+	  rm -f $(builddir)/acats-killer.pid; \
+	fi
+endif
+
+	: # running the libjava testsuite alone is missing this information
+	$(builddir)/gcc/xgcc -B$(builddir)/gcc/ -v > $(builddir)/compiler_version.sum 2>&1
+
+	if [ -x $(srcdir)/contrib/test_summary ]; then \
+	  rm -f test-summary; \
+	  ( \
+	    cd $(builddir); \
+	    echo '' > ts-include; \
+	    echo '' >> ts-include; \
+	    if [ -f $(builddir)/gcc/.bad_compare ]; then \
+	      echo 'Bootstrap comparison failure:' >> ts-include; \
+	      cat $(builddir)/gcc/.bad_compare >> ts-include; \
+	      echo '' >> ts-include; \
+	      echo '' >> ts-include; \
+	    fi; \
+	    echo "Build Dependencies:" >> ts-include; \
+	    dpkg -l g++-* binutils* `echo '$(LIBC_DEP)' | awk '{print $$1}'` \
+		libgmp*-dev libmpfr-dev libmpc-dev libisl-dev \
+	        | fgrep -v '<none>' >> ts-include; \
+	    echo '' >> ts-include; \
+	    cat ../$(patch_stamp) >> ts-include; \
+	    BOOT_CFLAGS="$(BOOT_CFLAGS)" \
+	      $(srcdir)/contrib/test_summary \
+		-i ts-include -m "$(S_EMAIL)" \
+	  ) > raw-test-summary; \
+	  if [ -n "$(testsuite_tarball)" ]; then \
+	    echo "Test suite used: $(testsuite_srcdir)" > test-summary; \
+	    echo "  Do not interpret the results on its own" >> test-summary; \
+	    echo "  but compare them with the results from" >> test-summary; \
+	    echo "  the gcc-snapshot package." >> test-summary; \
+	  fi; \
+	  sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-summary \
+		>> test-summary; \
+	  awk '/^cat/, /^EOF/' raw-test-summary | grep -v EOF >> test-summary; \
+	  if [ -f bootstrap-summary -a "$(bootstrap_target)" != profiledbootstrap ]; then \
+	    echo '' >> test-summary; \
+	    cat bootstrap-summary >> test-summary; \
+	  fi; \
+	  echo 'BEGIN test-summary'; \
+	  cat test-summary; \
+	  echo 'END test-summary'; \
+	fi
+ifeq ($(with_d),yes)
+	: # the D test failures for the non-default multilibs are known, ignore them
+	egrep -v '^(FAIL|UNRESOLVED): (runnable|fail_c|comp)' test-summary > test-summary.tmp
+	mv -f test-summary.tmp test-summary
+endif
+
+	touch $(check_stamp)
+
+$(check_inst_stamp): $(check_stamp)
+	rm -f test-inst-protocol
+
+ifeq ($(start_logwatch),yes)
+	: # start logwatch script for regular output during test runs
+	chmod +x debian/logwatch.sh
+	-debian/logwatch.sh -t 900 -p $(builddir)/logwatch-inst.pid \
+		-m '\ntestsuite (3.3) still running ...\n' \
+		test-inst-protocol \
+		check-inst/{gcc,g++,g77,objc}.log \
+		&
+endif
+
+	rm -rf check-inst
+	mkdir check-inst
+
+	echo "Running testsuite ..."
+	-$(ULIMIT_M) ; \
+	    $(SET_SHELL) \
+	    $(SET_LOCPATH) \
+	    EXTRA_TEST_PFLAGS=-g0 \
+	    DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \
+	  cd check-inst && $(srcdir)/contrib/test_installed \
+	    --with-gcc=gcc-3.3 --with-g++=g++-3.3 --with-g77=g77-3.3 \
+		2>&1 | tee test-inst-protocol
+
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+	if [ -f $(builddir)/logwatch-inst.pid ]; then \
+	  kill -1 `cat $(builddir)/logwatch-inst.pid`; \
+	else \
+	  true; \
+	fi
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+
+	-chmod 755 $(srcdir)/contrib/test_summary
+	if [ -x $(srcdir)/contrib/test_summary ]; then \
+	  rm -f test-inst-summary; \
+	  ( \
+	    cd check-inst; \
+	    echo '' > ts-include; \
+	    echo '' >> ts-include; \
+	    echo "Build Dependencies:" >> ts-include; \
+	    dpkg -l g++-* binutils* `echo '$(LIBC_DEP)' | awk '{print $$1}'` \
+		libgmp*-dev libmpfr-dev libmpc-dev libisl*-dev \
+	        | fgrep -v '<none>' >> ts-include; \
+	    echo '' >> ts-include; \
+	    echo 'Results for the installed GCC-3.3 compilers' >> ts-include; \
+	    $(srcdir)/contrib/test_summary \
+		-i ts-include -m "$(S_EMAIL)" \
+	  ) > raw-test-inst-summary; \
+	  sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-inst-summary \
+		>> test-inst-summary; \
+	  awk '/^cat/, /^EOF/' raw-test-inst-summary \
+		| grep -v EOF >> test-inst-summary; \
+	  echo 'BEGIN test-installed-summary'; \
+	  cat test-inst-summary; \
+	  echo 'END test-installed-summary'; \
+	fi
+
+	chmod 755 debian/reduce-test-diff.awk
+	if diff -u test-inst-summary test-summary \
+		| debian/reduce-test-diff.awk > diff-summary; \
+	then \
+	  mv -f diff-summary testsuite-comparision; \
+	else \
+	  ( \
+	    echo "WARNING: New failures in gcc-3.4 compared to gcc-3.3"; \
+	    echo ''; \
+	    cat diff-summary; \
+	  ) > testsuite-comparision; \
+	  rm -f diff-summary; \
+	fi
+	touch $(check_inst_stamp)
+
+clean: debian/control
+	dh_testdir
+	rm -f pxxx status
+	rm -f *-summary *-protocol testsuite-comparision summary-diff
+	rm -f $(srcdir)/gcc/po/*.gmo
+	rm -f debian/lib{gcc,gcj,objc,stdc++}{-v3,[0-9]}*.{{pre,post}{inst,rm},shlibs}
+	fs=`echo debian/*BV* debian/*GCJ* debian/*CXX* debian/*LC* debian/*MF* | sort -u`; \
+	for f in $$fs; do \
+	  [ -f $$f ] || continue; \
+	  f2=$$(echo $$f \
+		| sed 's/BV/$(BASE_VERSION)/;s/CXX/$(CXX_SONAME)/;s/LGCJ/$(PKG_LIBGCJ_EXT)/;s/GCJ/$(PKG_GCJ_EXT)/;s/LC/$(GCC_SONAME)/;s/-CRB/$(cross_bin_arch)/;s/\.in$$//'); \
+	  rm -f $$f2; \
+	done
+	rm -f debian/lib*gcc1.symbols
+	rm -f debian/lib*{atomic$(ATOMIC_SONAME),cilkrts$(CILKRTS_SONAME),gfortran$(FORTRAN_SONAME),gomp$(GOMP_SONAME),itm$(ITM_SONAME),mpx$(MPX_SONAME),quadmath$(QUADMATH_SONAME)}.symbols
+	find debian -maxdepth 1 -name '*-cross.symbols' -type l | xargs -r rm -f
+	rm -f debian/gcc-{XX,ar,nm,ranlib}-$(BASE_VERSION).1
+	rm -f debian/shlibs.local debian/shlibs.common* debian/substvars.local
+	rm -f debian/*.debhelper
+	-[ -d debian/bugs ] && $(MAKE) -C debian/bugs clean
+	rm -f debian/README.libstdc++-baseline debian/README.Bugs debian/README.Debian.$(DEB_TARGET_ARCH)
+	rm -f debian/lib*gcj-bc.shlibs
+	rm -f debian/arch_binaries* debian/indep_binaries*
+	rm -rf bin locales share
+	rm -rf check-inst
+	rm -rf .pc
+	dh_clean
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+	$(cross_clean) dh_clean
+endif
+
+# -----------------------------------------------------------------------------
+# some abbrevations for the package names and directories;
+# p_XXX is the package name, d_XXX is the package directory
+# these macros are only used in the binary-* targets.
+
+ifeq ($(versioned_packages),yes)
+  pkg_ver := -$(BASE_VERSION)
+endif
+
+ifneq ($(DEB_CROSS),yes)
+  p_base = gcc$(pkg_ver)-base
+  p_lbase = $(p_base)
+  p_xbase = gcc$(pkg_ver)-base
+  p_gcc  = gcc$(pkg_ver)
+  p_cpp  = cpp$(pkg_ver)
+  p_cppd = cpp$(pkg_ver)-doc
+  p_cxx  = g++$(pkg_ver)
+  p_doc  = gcc$(pkg_ver)-doc
+else
+  # only triggered if DEB_CROSS set
+  p_base = gcc$(pkg_ver)$(cross_bin_arch)-base
+  p_lbase = gcc$(pkg_ver)-cross-base$(GCC_PORTS_BUILD)
+  p_xbase = gcc$(pkg_ver)$(cross_bin_arch)-base
+  p_cpp  = cpp$(pkg_ver)$(cross_bin_arch)
+  p_gcc  = gcc$(pkg_ver)$(cross_bin_arch)
+  p_cxx  = g++$(pkg_ver)$(cross_bin_arch)
+endif
+p_hppa64 = gcc$(pkg_ver)-hppa64-linux-gnu
+
+# needed for shlibs.common* generation
+ifeq (,$(p_lgcc))
+  p_lgcc = libgcc$(GCC_SONAME)$(cross_lib_arch)
+endif
+ifeq (,$(p_lib))
+  p_lib = libstdc++$(CXX_SONAME)$(cross_lib_arch)
+endif
+
+d	= debian/tmp
+d_base	= debian/$(p_base)
+d_xbase = debian/$(p_xbase)
+d_gcc	= debian/$(p_gcc)
+d_cpp	= debian/$(p_cpp)
+d_cppd	= debian/$(p_cppd)
+d_cxx	= debian/$(p_cxx)
+d_doc	= debian/$(p_doc)
+d_lgcc	= debian/$(p_lgcc)
+d_hppa64= debian/$(p_hppa64)
+
+d_neon   = debian/tmp-neon
+
+common_substvars = \
+	$(shell awk "{printf \"'-V%s' \", \$$0}" debian/substvars.local)
+
+ifeq ($(DEB_CROSS),yes)
+  lib_binaries := indep_binaries
+else
+  lib_binaries := arch_binaries
+endif
+
+# ---------------------------------------------------------------------------
+
+ifeq ($(single_package),yes)
+  include debian/rules.d/binary-snapshot.mk
+else
+
+ifneq ($(with_base_only),yes)
+ifneq ($(DEB_CROSS),yes)
+ifeq ($(with_source),yes)
+  include debian/rules.d/binary-source.mk
+endif
+endif
+endif
+
+ifneq ($(BACKPORT),true)
+
+ifeq ($(with_gccbase),yes)
+  include debian/rules.d/binary-base.mk
+endif
+
+ifneq ($(with_base_only),yes)
+
+# always include to get some definitions
+include debian/rules.d/binary-libgcc.mk
+
+ifeq ($(with_libqmath),yes)
+  include debian/rules.d/binary-libquadmath.mk
+endif
+
+ifeq ($(with_libgmath),yes)
+  include debian/rules.d/binary-libgccmath.mk
+endif
+
+ifeq ($(with_libgomp),yes)
+  include debian/rules.d/binary-libgomp.mk
+endif
+
+ifeq ($(with_libitm),yes)
+  include debian/rules.d/binary-libitm.mk
+endif
+
+ifeq ($(with_libatomic),yes)
+  include debian/rules.d/binary-libatomic.mk
+endif
+
+ifeq ($(with_libbacktrace),yes)
+  include debian/rules.d/binary-libbacktrace.mk
+endif
+
+ifeq ($(with_cdev),yes)
+  include debian/rules.d/binary-cpp.mk
+endif
+
+ifeq ($(with_fixincl),yes)
+  include debian/rules.d/binary-fixincl.mk
+endif
+
+ifeq ($(with_libssp),yes)
+  include debian/rules.d/binary-libssp.mk
+endif
+
+ifeq ($(with_objcxx),yes)
+  include debian/rules.d/binary-objcxx.mk
+endif
+
+ifeq ($(with_objc),yes)
+  include debian/rules.d/binary-objc.mk
+  include debian/rules.d/binary-libobjc.mk
+endif
+
+ifeq ($(with_go),yes)
+  include debian/rules.d/binary-go.mk
+endif
+
+# include before cxx
+ifeq ($(with_java),yes)
+  include debian/rules.d/binary-java.mk
+endif
+
+ifeq ($(with_cxxdev),yes)
+  include debian/rules.d/binary-cxx.mk
+endif
+ifeq ($(with_cxx),yes)
+  include debian/rules.d/binary-libstdcxx.mk
+endif
+
+ifeq ($(with_libasan),yes)
+  include debian/rules.d/binary-libasan.mk
+endif
+
+ifeq ($(with_liblsan),yes)
+  include debian/rules.d/binary-liblsan.mk
+endif
+
+ifeq ($(with_libtsan),yes)
+  include debian/rules.d/binary-libtsan.mk
+endif
+
+ifeq ($(with_libubsan),yes)
+  include debian/rules.d/binary-libubsan.mk
+endif
+
+ifeq ($(with_libvtv),yes)
+  include debian/rules.d/binary-libvtv.mk
+endif
+
+ifeq ($(with_libcilkrts),yes)
+  include debian/rules.d/binary-libcilkrts.mk
+endif
+
+ifeq ($(with_libmpx),yes)
+  include debian/rules.d/binary-libmpx.mk
+endif
+
+ifeq ($(with_f77),yes)
+  include debian/rules.d/binary-f77.mk
+endif
+
+ifeq ($(with_fortran),yes)
+  include debian/rules.d/binary-fortran.mk
+endif
+
+ifeq ($(with_ada),yes)
+  include debian/rules.d/binary-ada.mk
+endif
+
+ifeq ($(with_d),yes)
+  include debian/rules.d/binary-d.mk
+endif
+
+ifeq ($(with_libcc1),yes)
+  include debian/rules.d/binary-libcc1.mk
+endif
+
+ifeq ($(with_jit),yes)
+  include debian/rules.d/binary-libgccjit.mk
+endif
+
+ifeq ($(with_libnof),yes)
+  ifeq ($(DEB_TARGET_GNU_CPU),powerpc)
+    include debian/rules.d/binary-nof.mk
+  endif
+endif
+
+ifeq ($(with_softfloat),yes)
+  include debian/rules.d/binary-softfloat.mk
+endif
+
+# gcc must be moved/built after g77 and g++
+ifeq ($(with_cdev),yes)
+  include debian/rules.d/binary-gcc.mk
+endif
+
+ifeq ($(with_hppa64),yes)
+  include debian/rules.d/binary-hppa64.mk
+endif
+
+ifeq ($(with_neon),yes)
+  include debian/rules.d/binary-neon.mk
+endif
+
+endif # with_base_only
+endif # BACKPORT
+endif # ($(single_package),yes)
+
+# ----------------------------------------------------------------------
+install: $(install_dependencies)
+
+$(install_dummy_stamp): $(build_dummy_stamp)
+	touch $(install_dummy_stamp)
+
+$(install_snap_stamp): $(build_dependencies)
+	dh_testdir
+	dh_testroot
+	dh_prep
+
+	: # Install directories
+	rm -rf $(d)
+	mkdir -p $(d)/$(PF)
+
+ifeq ($(with_hppa64),yes)
+	: # Install hppa64
+	$(SET_PATH) \
+	    $(MAKE) -C $(builddir_hppa64) \
+		CC="$(CC)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d) \
+		    install
+
+	ls -l $(d)/$(PF)/bin
+	if [ ! -x $(d)/$(PF)/bin/hppa64-linux-gnu-gcc ]; then \
+	  mv $(d)/$(PF)/bin/hppa64-linux-gnu-gcc-6* $(d)/$(PF)/bin/hppa64-linux-gnu-gcc; \
+	else \
+	  rm -f $(d)/$(PF)/bin/hppa64-linux-gnu-gcc-6*; \
+	fi
+
+	for i in ar nm ranlib; do \
+	  cp debian/gcc-$$i-$(BASE_VERSION).1 \
+	    $(d)/$(PF)/share/man/man1/hppa64-linux-gnu-gcc-$$i.1; \
+	done
+
+	: # remove files not needed from the hppa64 build
+	rm -rf $(d)/$(PF)/share/info
+	rm -rf $(d)/$(PF)/share/man
+	rm -f $(d)/$(PF)/$(libdir)/libiberty.a
+	rm -f $(d)/$(PF)/bin/*{gcov,gcov-dump,gcov-tool,gccbug,gcc}
+
+	rm -rf $(d)/$(PF)/hppa64-linux-gnu/include
+	rm -rf $(d)/$(PF)/hppa64-linux-gnu/lib
+	set -e; \
+	  cd $(d)/$(PF)/$(libdir)/gcc/hppa64-linux-gnu/$(versiondir)/include-fixed; \
+	  for i in *; do \
+	    case "$$i" in \
+	      README|features.h|syslimits.h|limits.h) ;; \
+	      linux|$(TARGET_ALIAS)) ;; \
+	      $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS))) ;; \
+	      *) echo "remove include-fixed/$$i"; rm -rf $$i; \
+	    esac; \
+	  done
+endif
+
+	: # Work around PR lto/41569
+	ln -sf gcc $(builddir)/prev-gcc
+	ln -sf $(DEB_TARGET_GNU_TYPE) $(builddir)/prev-$(DEB_TARGET_GNU_TYPE)
+
+	: # Install everything
+	$(SET_PATH) \
+	$(SET_SHELL) \
+	  $(MAKE) -C $(builddir) \
+	    $(CFLAGS_TO_PASS) \
+	    $(LDFLAGS_TO_PASS) \
+	    DESTDIR=$(CURDIR)/$(d) \
+	    infodir=/$(PF)/share/info \
+	    mandir=/$(PF)/share/man \
+		install
+
+	ls -l $(d)/$(PF)/bin
+
+	for i in ar nm ranlib; do \
+	  cp debian/gcc-$$i-$(BASE_VERSION).1 \
+	    $(d)/$(PF)/share/man/man1/$(cmd_prefix)gcc-$$i.1; \
+	done
+
+	if [ ! -x $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc ]; then \
+	  mv $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc-6* $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc; \
+	else \
+	  rm -f $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc-6*; \
+	fi
+	set -e; \
+	  cd $(d)/$(gcc_lib_dir)/include-fixed; \
+	  for i in *; do \
+	    case "$$i" in \
+	      README|features.h|syslimits.h|limits.h) ;; \
+	      linux|$(TARGET_ALIAS)) ;; \
+	      $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS))) ;; \
+	      *) echo "remove include-fixed/$$i"; rm -rf $$i; \
+	    esac; \
+	  done
+
+ifneq ($(configured_libdir),$(libdir))
+	for i in debug go pkgconfig '*.so' '*.so.*' '*.a' '*.la' '*.py' '*.spec'; do \
+	  mv $(d)/$(PF)/$(configured_libdir)/$$i \
+		$(d)/$(PF)/$(libdir)/. || true; \
+	done
+endif
+
+# FIXME: libjava/classpath not correctly patched
+ifeq ($(with_java),yes)
+	-if [ -d $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME) ]; then \
+	  ls -l $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	  mv $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME)/* \
+	    $(d)/$(PF)/lib/gcj-$(BASE_VERSION)-$(GCJ_SONAME)/; \
+	  rmdir $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	fi
+
+	ln -sf libgcj.so.$(GCJ_SONAME).0.0 $(d)/$(PF)/lib/libgcj_bc.so.1.0.0
+
+	install -m 755 $(d)/$(PF)/lib/libgcj_bc.so.1 \
+		$(d)/$(gcc_lib_dir)/libgcj_bc.so
+	$(builddir)/gcc/xgcc -B$(builddir)/gcc/ -shared -fpic -xc /dev/null \
+		-o build/libgcj.so -Wl,-soname,libgcj.so.$(GCJ_SONAME) -nostdlib
+	$(builddir)/gcc/xgcc -B$(builddir)/gcc/ -shared -fpic \
+		$(srcdir)/libjava/libgcj_bc.c \
+		-o $(d)/$(gcc_lib_dir)/libgcj_bc.so \
+		-Wl,-soname,libgcj_bc.so.1 $(builddir)/libgcj.so -shared-libgcc
+endif
+
+	-ls -l $(d)/usr
+	if [ -d $(d)/usr/man/man1 ]; then \
+	  mv $(d)/usr/man/man1/* $(d)/usr/share/man/man1/; \
+	fi
+
+	chmod 755 debian/dh_*
+	touch $(install_snap_stamp)
+
+$(install_stamp): $(build_stamp)
+	dh_testdir
+	dh_testroot
+	dh_prep -N$(p_hppa64)
+
+	if [ -f $(binary_stamp)-hppa64 ]; then \
+	  mv $(binary_stamp)-hppa64 saved-stamp-hppa64; \
+	fi
+	rm -f $(binary_stamp)*
+	if [ -f saved-stamp-hppa64 ]; then \
+	  mv saved-stamp-hppa64 $(binary_stamp)-hppa64; \
+	fi
+
+	: # Install directories
+	rm -rf $(d)
+	mkdir -p $(d)/$(libdir) $(d)/$(PF) $(d)/$(PF)/$(libdir)/debug
+ifeq ($(biarch32),yes)
+	mkdir -p $(d)/$(PF)/$(lib32loc)/debug
+endif
+ifeq ($(biarch64),yes)
+	mkdir -p $(d)/$(PF)/lib64/debug
+endif
+ifeq ($(biarchn32),yes)
+	mkdir -p $(d)/$(PF)/$(libn32)/debug
+endif
+ifeq ($(biarchx32),yes)
+	mkdir -p $(d)/$(PF)/libx32/debug
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_CPU),x86_64 sparc64 s390x powerpc64))
+ifneq ($(DEB_TARGET_ARCH),x32)
+	: # link lib to lib64 and $(PF)/lib to $(PF)/lib64
+	: # (this works when CONFARGS contains '--disable-multilib')
+	ln -s $(configured_libdir) $(d)/lib64
+	mkdir -p $(d)/$(PF)/$(configured_libdir)
+	ln -s $(configured_libdir) $(d)/$(PF)/lib64
+endif
+endif
+ifeq ($(DEB_TARGET_ARCH),x32)
+	: # link lib to libx32 and $(PF)/lib to $(PF)/libx32
+	ln -s $(configured_libdir) $(d)/libx32
+	mkdir -p $(d)/$(PF)/$(configured_libdir)
+	ln -s $(configured_libdir) $(d)/$(PF)/libx32
+endif
+
+	: # Work around PR lto/41569
+	ln -sf gcc $(builddir)/prev-gcc
+
+	: # Install everything
+	$(SET_PATH) \
+	$(SET_SHELL) \
+	  $(MAKE) -C $(builddir) \
+	    $(CFLAGS_TO_PASS) \
+	    $(LDFLAGS_TO_PASS) \
+	    DESTDIR=$(CURDIR)/$(d) \
+	    infodir=/$(PF)/share/info \
+	    mandir=/$(PF)/share/man \
+		install
+
+ifeq ($(DEB_STAGE)-$(DEB_CROSS),rtlibs-yes)
+	@echo configured_libdir=$(configured_libdir) / libdir=$(libdir) / usr_lib=$(usr_lib)
+	ls $(d)/$(PF)/$(TARGET_ALIAS)/lib
+	set -x; \
+	if [ -d $(d)/$(PF)/$(TARGET_ALIAS)/lib ]; then \
+	  cp -a $(d)/$(PF)/$(TARGET_ALIAS)/lib/* $(d)/$(PF)/lib/$(DEB_TARGET_MULTIARCH)/.; \
+	fi
+	for d in $$(cd $(d)/$(PF)/$(TARGET_ALIAS); echo lib?*); do \
+	  [ -d $(d)/$(PF)/$(TARGET_ALIAS)/$$d ] || continue; \
+	  cp -a $(d)/$(PF)/$(TARGET_ALIAS)/$$d/* $(d)/$(PF)/$$d/.; \
+	done
+else
+  ifneq ($(configured_libdir),$(libdir))
+	for i in debug go pkgconfig '*.so' '*.so.*' '*.a' '*.la' '*.o' '*.py' '*.spec'; do \
+	  mv $(d)/$(PF)/$(configured_libdir)/$$i \
+		$(d)/$(PF)/$(libdir)/. || true; \
+	done
+  endif
+endif
+
+ifneq (,$(cmd_prefix))
+	for i in $(d)/$(PF)/share/info/$(cmd_prefix)*; do \
+	  [ -f "$$i" ] || continue; \
+	  mv $$i $$(echo $$i | sed 's/$(cmd_prefix)//'); \
+	done
+endif
+
+ifeq ($(with_libcxxdbg),yes)
+	: # FIXME: the libstdc++ gdb.py file is installed with a wrong name
+	for i in $$(find $(d)/$(PF) -name libstdc++_pic.a-gdb.py); do \
+	  [ -f $$i ] || continue; \
+	  d=$$(dirname $$i); \
+	  b=$$(basename $$i); \
+	  t=$$(cd $$d; echo libstdc++.so.*.*.*)-gdb.py; \
+	  mv $$i $$d/$$t; \
+	done
+endif
+
+	if [ -d $(d)/$(PF)/include/cilk ]; then \
+	  mv $(d)/$(PF)/include/cilk $(d)/$(gcc_lib_dir)/include/. ;\
+	fi
+
+ifeq ($(with_java),yes)
+# FIXME: libjava/classpath not correctly patched
+	-if [ -d $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME) ]; then \
+	  ls -l $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	  mv $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME)/* \
+	    $(d)/$(PF)/lib/gcj-$(BASE_VERSION)-$(GCJ_SONAME)/; \
+	  rmdir $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	fi
+endif
+
+	: # remove rpath settings from binaries and shared libs
+	for i in $$(chrpath -k $(d)/$(PF)/bin/* $(d)/$(PFL)/lib*/lib*.so.* \
+			$(d)/$(gcc_lib_dir)/plugin/* \
+			$(if $(filter $(with_multiarch_lib),yes), \
+			  $(d)/$(PF)/lib/$(DEB_TARGET_MULTIARCH)/lib*.so.*) \
+			$(d)/$(PF)/lib*/gcj$(pkg_ver)*/lib*.so.* \
+			2>/dev/null | awk -F: '/R(UN)?PATH=/ {print $$1}'); \
+	do \
+	  case "$$i" in ecj1|*gij-*|*libjawt*|*libjvm*) continue; esac; \
+	  [ -h $$i ] && continue; \
+	  chrpath --delete $$i; \
+	  echo "removed RPATH/RUNPATH: $$i"; \
+	done
+
+	: # remove '*.la' and '*.lai' files, not shipped in any package.
+	find $(d) -name '*.la' -o -name '*.lai' | xargs -r rm -f
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gcc gcov; do \
+	  I=`echo $$i | tr a-z A-Z`; \
+	  sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \
+	    debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \
+	done
+
+  ifeq ($(with_fortran),yes)
+	for i in g77; do \
+	  I=`echo $$i | tr a-z A-Z`; \
+	  sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \
+	    debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \
+	done
+  endif
+  ifeq ($(with_java),yes)
+	for i in gcj gcjh gij jv-convert jv-scan jcf-dump grmic grmiregistry; \
+	do \
+	  I=`echo $$i | tr a-z A-Z`; \
+	  sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \
+	    debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \
+	done
+  endif
+endif
+
+ifneq ($(with_libgnat),yes)
+	rm -f $(d)/$(gcc_lib_dir)/adalib/lib*.so*
+endif
+
+# FIXME: libgnatprj and libgnatvsn need proper configury/Makefiles
+ifeq ($(DEB_CROSS),yes)
+  ifeq ($(with_ada),yes)
+	for i in 'libgnatprj*' 'libgnatvsn*'; do \
+	  mv $(d)/$(PF)/lib/$$i $(d)/$(usr_lib)/. || true; \
+	done
+  endif
+endif
+
+#  ifeq ($(with_ada),yes)
+#	: # rename files (versioned ada binaries)
+#	for i in ; do \
+#	  mv $(d)/$(PF)/bin/$$i $(d)/$(PF)/bin/$$i-$(GNAT_VERSION); \
+#	  mv $(d)/$(PF)/share/man/man1/$$i.1 \
+#		$(d)/$(PF)/share/man/man1/$$i-$(GNAT_VERSION).1; \
+#	done
+#	for i in $(GNAT_TOOLS); do \
+#	  mv $(d)/$(PF)/bin/$$i $(d)/$(PF)/bin/$$i-$(GNAT_VERSION); \
+#	done
+#  endif
+
+	for i in ar nm ranlib; do \
+	  cp debian/gcc-$$i-$(BASE_VERSION).1 \
+	    $(d)/$(PF)/share/man/man1/$(cmd_prefix)gcc-$$i$(pkg_ver).1; \
+	done
+
+	chmod 755 debian/dh_*
+
+ifneq ($(with_common_libs),yes)
+# for native builds, the default ml libs are always available; no need for a placeholder
+# apparently this changed with newer dpkg versions (1.18.7?) ...
+	echo 'libgcc_s $(GCC_SONAME) $(p_lgcc)' > debian/shlibs.common
+	echo 'libstdc++ $(CXX_SONAME) $(p_lib)' >> debian/shlibs.common
+	$(foreach ml,32 64 n32 x32 hf sf, \
+	  echo 'libgcc_s $(GCC_SONAME) $(subst lib,lib$(ml),$(p_lgcc))' > debian/shlibs.common$(ml); \
+	  echo 'libstdc++ $(CXX_SONAME) $(subst lib,lib$(ml),$(p_lib))' >> debian/shlibs.common$(ml); \
+	)
+endif
+
+	@echo XXXXX `date -R`
+	find $(d) ! -type d -print
+	@echo XXXXX
+	touch $(install_stamp)
+
+$(install_jit_stamp): $(build_jit_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d)-jit
+	mkdir -p $(d)-jit/$(PF)
+
+	$(SET_PATH) \
+	  biarch_multidir_names=none \
+	    $(MAKE) -C $(builddir_jit) \
+		CC="$(CC_FOR_JIT)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d)-jit \
+		    install
+
+	: # copy files to the standard build
+	cp -a $(d)-jit/$(PF)/include/libgccjit*.h \
+		$(d)/$(gcc_lib_dir)/include/.
+	cp -a $(d)-jit/$(PF)/lib/libgccjit.so* \
+		$(d)/$(usr_lib)/.
+	cp -a $(d)-jit/$(PF)/share/info/libgccjit* \
+		$(d)/$(PF)/share/info/.
+
+	@echo XXXXX `date -R`
+	touch $(install_jit_stamp)
+
+$(install_hppa64_stamp): $(build_hppa64_stamp)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_hppa64)
+	mkdir -p $(d_hppa64)/$(PF)
+
+	$(SET_PATH) \
+	    $(MAKE) -C $(builddir_hppa64) \
+		CC="$(CC)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d_hppa64) \
+		    install
+
+	: # remove files not needed
+	rm -rf $(d_hppa64)/$(PF)/info $(d_hppa64)/$(PF)/share/info
+	rm -rf $(d_hppa64)/$(PF)/man $(d_hppa64)/$(PF)/share/man
+	rm -rf $(d_hppa64)/$(PF)/lib/gcc/hppa64-linux-gnu/$(BASE_VERSION)/plugin
+	rm -f $(d_hppa64)/$(PF)/lib/libiberty.a
+	rm -f $(d_hppa64)/$(PF)/lib/libcc1.*
+	rm -f $(d_hppa64)/$(PF)/bin/*{gcov,gcov-dump,gcov-tool,gccbug,gcc}
+
+	rm -rf $(d_hppa64)/$(PF)/hppa64-linux-gnu
+	rm -rf $(d_hppa64)/$(PF)/lib/gcc/hppa64-linux-gnu/$(BASE_VERSION)/install-tools
+
+ifeq ($(versioned_packages),yes)
+	for i in cpp gcc-ar gcc-nm gcc-ranlib; do \
+	  mv -f $(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-$$i \
+		$(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-$$i$(pkg_ver); \
+	done
+endif
+	mkdir -p $(d_hppa64)/$(PF)/share/man/man1
+	for i in gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $$i$(pkg_ver).1.gz \
+	    $(d_hppa64)/$(PF)/share/man/man1/hppa64-linux-gnu-$$i$(pkg_ver).1.gz; \
+	done
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in cpp gcc; do \
+	  ln -sf $$i$(pkg_ver).1.gz \
+	    $(d_hppa64)/$(PF)/share/man/man1/hppa64-linux-gnu-$$i$(pkg_ver).1.gz; \
+	done
+endif
+
+	touch $(install_hppa64_stamp)
+
+$(install_neon_stamp): $(build_neon_stamp)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_neon)
+	mkdir -p $(d_neon)/$(PF)
+
+	$(SET_PATH) \
+	    $(MAKE) -C $(builddir_neon) \
+		CC="$(CC)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d_neon) \
+		    install
+	touch $(install_neon_stamp)
+
+# ----------------------------------------------------------------------
+# Build architecture-dependent files here.
+debian/arch_binaries.all: $(foreach i,$(arch_binaries),$(binary_stamp)-$(i))
+	cd debian; xargs -r du -s < arch_binaries | sort -nr | awk '{print $$2}' \
+		> arch_binaries.tmp
+	mv debian/arch_binaries.tmp debian/arch_binaries
+	sed -i 's/ /\n/g' debian/arch_binaries.epoch || touch debian/arch_binaries.epoch
+	cat debian/arch_binaries debian/arch_binaries.epoch > debian/arch_binaries.all
+
+binary-arch: debian/arch_binaries.all
+	dh_compress $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p)) \
+	  -X.log.xz -X.sum.xz -X.java -X.c -X.txt -X.tag -X.map -XREADME.Bugs
+ifeq ($(i586_symlinks),yes)
+	cd debian; \
+	for x in $$(find `cat arch_binaries` -type l -name 'i686-*'); do \
+	  link=$$(echo $$x | sed 's/i686-/i586-/'); \
+	  tgt=$$(basename $$x); \
+	  echo "Adding symlink: $$link -> $$tgt"; \
+	  rm -f $$link; cp -a $$x $$link; \
+	done
+endif
+	dh_fixperms $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+	dh_gencontrol $(foreach p,$(shell echo `cat debian/arch_binaries`),-p$(p)) \
+	  -- -v$(DEB_VERSION) $(common_substvars)
+	@set -e; \
+	pkgs='$(strip $(foreach p,$(shell echo `cat debian/arch_binaries.epoch`),-p$(p)))'; \
+	if [ -n "$$pkgs" ]; then \
+	  echo dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	  dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	fi
+	dh_installdeb $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+	dh_md5sums $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+	dh_builddeb $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+ifeq ($(with_check),yes)
+	@echo Done
+#	: # Send Email about sucessfull build.
+#	# cat raw-test-summary | sh; echo "Sent mail to $(S_EMAIL)"
+endif
+
+	: # remove empty directories, when all components are in place
+	-find $(d) -type d -empty -delete
+
+	@echo "Listing installed files not included in any package:"
+	-find $(d) ! -type d
+
+	@echo XXXXX `date -R`
+
+# ----------------------------------------------------------------------
+# Build architecture-independent files here.
+debian/indep_binaries.all: $(foreach i,$(indep_binaries),$(binary_stamp)-$(i))
+	cd debian; xargs -r du -s < indep_binaries | sort -nr | awk '{print $$2}' \
+		> indep_binaries.tmp
+	mv debian/indep_binaries.tmp debian/indep_binaries
+	sed -i 's/ /\n/g' debian/indep_binaries.epoch || touch debian/indep_binaries.epoch
+	cat debian/indep_binaries debian/indep_binaries.epoch > debian/indep_binaries.all
+
+binary-indep: debian/indep_binaries.all
+	dh_compress $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p)) \
+	  -X.log.xz -X.sum.xz -X.java -X.c -X.txt -X.tag -X.map -XREADME.Bugs
+	dh_fixperms $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+	: # the export should be harmless for the binary indep packages of a native build
+	export DEB_HOST_ARCH=$(TARGET); \
+	dh_gencontrol $(foreach p,$(shell echo `cat debian/indep_binaries`),-p$(p)) \
+	  -- -v$(DEB_VERSION) $(common_substvars)
+	@set -e; \
+	export DEB_HOST_ARCH=$(TARGET); \
+	pkgs='$(strip $(foreach p,$(shell echo `cat debian/indep_binaries.epoch`),-p$(p)))'; \
+	if [ -n "$$pkgs" ]; then \
+	  echo dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	  dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	fi
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), mips mipsel mips64 mips64el mipsn32 mipsn32el))
+	for p in `cat debian/indep_binaries debian/indep_binaries.epoch`; do \
+	  p=$${p#-p*}; \
+	  case "$$p" in \
+	    lib64*)  echo mangle $$p; sed -i -r '/^(Dep|Rec|Sug)/s/libn?32[^,]+(, *|$$)//g;/^(Dep|Rec|Sug)/s/$(p_lgcc)/$(p_l64gcc)/;/^(Dep|Rec|Sug)/s/ *, *$$//' debian/$$p/DEBIAN/control;; \
+	    libn32*) echo mangle $$p; sed -i -r '/^(Dep|Rec|Sug)/s/lib64[^,]+(, *|$$)//g;/^(Dep|Rec|Sug)/s/$(p_lgcc)/$(p_ln32gcc)/;/^(Dep|Rec|Sug)/s/ *, *$$//' debian/$$p/DEBIAN/control;; \
+	  esac; \
+	done
+endif
+
+	dh_installdeb $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+	dh_md5sums $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+	dh_builddeb $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+
+	@echo XXXXX `date -R`
+
+source diff:
+	@echo >&2 'source and diff are obsolete - use dpkg-source -b'; false
+
+binary: binary-indep binary-arch
+.PHONY: build clean binary-indep binary-arch binary 
+.PRECIOUS: $(stampdir)/%-stamp debian/indep_binaries.all debian/arch_binaries.all
--- gcc-6-6.3.0.orig/debian/runcheck.sh
+++ gcc-6-6.3.0/debian/runcheck.sh
@@ -0,0 +1,23 @@
+#! /bin/sh
+
+mkdir -p build
+
+abi=${CC##* }
+base=build/runcheck$abi
+
+cat >$base.c <<EOF
+#include <stdio.h>
+int main()
+{
+	printf("$abi");
+	return 0;
+}
+EOF
+
+
+if ${CC:-gcc} -o $base $base.c 2>/dev/null; then
+  if [ "$($base 2>&1)" = "$abi" ]; then
+    printf "%s" $abi > $base.out
+    printf "%s" $abi
+  fi
+fi
--- gcc-6-6.3.0.orig/debian/source.lintian-overrides
+++ gcc-6-6.3.0/debian/source.lintian-overrides
@@ -0,0 +1,4 @@
+gcc-6 source: invalid-arch-string-in-source-relation
+gcc-6 source: quilt-build-dep-but-no-series-file
+# lintian can't handle (>= ${gcc:Version})
+gcc-6 source: weak-library-dev-dependency
--- gcc-6-6.3.0.orig/debian/source.lintian-overrides.in
+++ gcc-6-6.3.0/debian/source.lintian-overrides.in
@@ -0,0 +1,4 @@
+@SRC@ source: invalid-arch-string-in-source-relation
+@SRC@ source: quilt-build-dep-but-no-series-file
+# lintian can't handle (>= ${gcc:Version})
+@SRC@ source: weak-library-dev-dependency
--- gcc-6-6.3.0.orig/debian/source/format
+++ gcc-6-6.3.0/debian/source/format
@@ -0,0 +1 @@
+1.0
--- gcc-6-6.3.0.orig/debian/watch
+++ gcc-6-6.3.0/debian/watch
@@ -0,0 +1,2 @@
+version=2
+ftp://gcc.gnu.org/pub/gcc/releases/gcc-(6\.[\d\.]*)	debian	uupdate